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module NIOS_Sys_PIO0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
irq,
readdata
)
;
inout [ 4: 0] bidir_port;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire [ 4: 0] bidir_port;
wire clk_en;
reg [ 4: 0] d1_data_in;
reg [ 4: 0] d2_data_in;
reg [ 4: 0] data_dir;
wire [ 4: 0] data_in;
reg [ 4: 0] data_out;
reg [ 4: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 4: 0] edge_detect;
wire irq;
reg [ 4: 0] irq_mask;
wire [ 4: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({5 {(address == 0)}} & data_in) |
({5 {(address == 1)}} & data_dir) |
({5 {(address == 2)}} & irq_mask) |
({5 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[4 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign bidir_port[4] = data_dir[4] ? data_out[4] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata[4 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[4 : 0];
end
assign irq = |(data_in & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
module sky130_fd_sc_hd__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
|
module sky130_fd_sc_hvl__o22ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
reg SLEEP;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
SLEEP = 1'bX;
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 SLEEP = 1'b0;
#40 UDP_IN = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 SLEEP = 1'b1;
#120 UDP_IN = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 SLEEP = 1'b0;
#200 UDP_IN = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 UDP_IN = 1'b1;
#320 SLEEP = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 UDP_IN = 1'bx;
#400 SLEEP = 1'bx;
end
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .SLEEP(SLEEP), .UDP_OUT(UDP_OUT));
endmodule
|
module sky130_fd_sc_hd__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
|
module fifo # (parameter abits = 400, dbits = 1)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full,
output reg ledres
);
wire db_wr;
wire db_rd;
reg dffw1, dffr1;
reg [dbits-1:0] out;
initial ledres = 0;
reg [1:0] count;
reg [1:0] count1;
//always @ (posedge clock) dffw1 <= ~wr;
//always @ (posedge clock) dffw2 <= rd;
assign db_wr = dffw1; //monostable multivibrator to detect only one pulse of the button
//always @ (posedge clock) dffr1 <= rd;
//always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = dffr1; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
always @ (posedge clock)//only write
begin
if(wr && ~rd)
begin
if(count)
begin
//dffr1<=0;
dffw1<=0;
count<=count+1;
end
else
begin
//dffr1<=0;
dffw1<=1;
count<=0;
end
end
else dffw1<=0;
end
always @ (posedge clock)//only read
begin
if(rd && ~wr)
begin
if(count1)
begin
//dffw1<=0;
dffr1<=0;
count1<=count1+1;
end
else
begin
//dffw1<=0;
dffr1<=1;
count1<=0;
end
end
else dffr1<=0;
end
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
end
//always block for read operation
always @ (posedge clock)
begin
if(db_rd)
out <= regarray[rd_reg];
end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
ledres=1;
end
end
always @(clock)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__decaphe dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
|
module ledtest_mm_interconnect_1 (
input wire CLOCK_clk_clk, // CLOCK_clk.clk
input wire MM_BRIDGE_reset_reset_bridge_in_reset_reset, // MM_BRIDGE_reset_reset_bridge_in_reset.reset
input wire [4:0] MM_BRIDGE_m0_address, // MM_BRIDGE_m0.address
output wire MM_BRIDGE_m0_waitrequest, // .waitrequest
input wire [0:0] MM_BRIDGE_m0_burstcount, // .burstcount
input wire [3:0] MM_BRIDGE_m0_byteenable, // .byteenable
input wire MM_BRIDGE_m0_read, // .read
output wire [31:0] MM_BRIDGE_m0_readdata, // .readdata
output wire MM_BRIDGE_m0_readdatavalid, // .readdatavalid
input wire MM_BRIDGE_m0_write, // .write
input wire [31:0] MM_BRIDGE_m0_writedata, // .writedata
input wire MM_BRIDGE_m0_debugaccess, // .debugaccess
output wire [1:0] LED_ARRAY_s1_address, // LED_ARRAY_s1.address
output wire LED_ARRAY_s1_write, // .write
input wire [31:0] LED_ARRAY_s1_readdata, // .readdata
output wire [31:0] LED_ARRAY_s1_writedata, // .writedata
output wire LED_ARRAY_s1_chipselect, // .chipselect
output wire [1:0] SWITCH_ARRAY_s1_address, // SWITCH_ARRAY_s1.address
input wire [31:0] SWITCH_ARRAY_s1_readdata // .readdata
);
wire mm_bridge_m0_translator_avalon_universal_master_0_waitrequest; // MM_BRIDGE_m0_agent:av_waitrequest -> MM_BRIDGE_m0_translator:uav_waitrequest
wire [31:0] mm_bridge_m0_translator_avalon_universal_master_0_readdata; // MM_BRIDGE_m0_agent:av_readdata -> MM_BRIDGE_m0_translator:uav_readdata
wire mm_bridge_m0_translator_avalon_universal_master_0_debugaccess; // MM_BRIDGE_m0_translator:uav_debugaccess -> MM_BRIDGE_m0_agent:av_debugaccess
wire [4:0] mm_bridge_m0_translator_avalon_universal_master_0_address; // MM_BRIDGE_m0_translator:uav_address -> MM_BRIDGE_m0_agent:av_address
wire mm_bridge_m0_translator_avalon_universal_master_0_read; // MM_BRIDGE_m0_translator:uav_read -> MM_BRIDGE_m0_agent:av_read
wire [3:0] mm_bridge_m0_translator_avalon_universal_master_0_byteenable; // MM_BRIDGE_m0_translator:uav_byteenable -> MM_BRIDGE_m0_agent:av_byteenable
wire mm_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // MM_BRIDGE_m0_agent:av_readdatavalid -> MM_BRIDGE_m0_translator:uav_readdatavalid
wire mm_bridge_m0_translator_avalon_universal_master_0_lock; // MM_BRIDGE_m0_translator:uav_lock -> MM_BRIDGE_m0_agent:av_lock
wire mm_bridge_m0_translator_avalon_universal_master_0_write; // MM_BRIDGE_m0_translator:uav_write -> MM_BRIDGE_m0_agent:av_write
wire [31:0] mm_bridge_m0_translator_avalon_universal_master_0_writedata; // MM_BRIDGE_m0_translator:uav_writedata -> MM_BRIDGE_m0_agent:av_writedata
wire [2:0] mm_bridge_m0_translator_avalon_universal_master_0_burstcount; // MM_BRIDGE_m0_translator:uav_burstcount -> MM_BRIDGE_m0_agent:av_burstcount
wire [31:0] led_array_s1_agent_m0_readdata; // LED_ARRAY_s1_translator:uav_readdata -> LED_ARRAY_s1_agent:m0_readdata
wire led_array_s1_agent_m0_waitrequest; // LED_ARRAY_s1_translator:uav_waitrequest -> LED_ARRAY_s1_agent:m0_waitrequest
wire led_array_s1_agent_m0_debugaccess; // LED_ARRAY_s1_agent:m0_debugaccess -> LED_ARRAY_s1_translator:uav_debugaccess
wire [4:0] led_array_s1_agent_m0_address; // LED_ARRAY_s1_agent:m0_address -> LED_ARRAY_s1_translator:uav_address
wire [3:0] led_array_s1_agent_m0_byteenable; // LED_ARRAY_s1_agent:m0_byteenable -> LED_ARRAY_s1_translator:uav_byteenable
wire led_array_s1_agent_m0_read; // LED_ARRAY_s1_agent:m0_read -> LED_ARRAY_s1_translator:uav_read
wire led_array_s1_agent_m0_readdatavalid; // LED_ARRAY_s1_translator:uav_readdatavalid -> LED_ARRAY_s1_agent:m0_readdatavalid
wire led_array_s1_agent_m0_lock; // LED_ARRAY_s1_agent:m0_lock -> LED_ARRAY_s1_translator:uav_lock
wire [31:0] led_array_s1_agent_m0_writedata; // LED_ARRAY_s1_agent:m0_writedata -> LED_ARRAY_s1_translator:uav_writedata
wire led_array_s1_agent_m0_write; // LED_ARRAY_s1_agent:m0_write -> LED_ARRAY_s1_translator:uav_write
wire [2:0] led_array_s1_agent_m0_burstcount; // LED_ARRAY_s1_agent:m0_burstcount -> LED_ARRAY_s1_translator:uav_burstcount
wire led_array_s1_agent_rf_source_valid; // LED_ARRAY_s1_agent:rf_source_valid -> LED_ARRAY_s1_agent_rsp_fifo:in_valid
wire [75:0] led_array_s1_agent_rf_source_data; // LED_ARRAY_s1_agent:rf_source_data -> LED_ARRAY_s1_agent_rsp_fifo:in_data
wire led_array_s1_agent_rf_source_ready; // LED_ARRAY_s1_agent_rsp_fifo:in_ready -> LED_ARRAY_s1_agent:rf_source_ready
wire led_array_s1_agent_rf_source_startofpacket; // LED_ARRAY_s1_agent:rf_source_startofpacket -> LED_ARRAY_s1_agent_rsp_fifo:in_startofpacket
wire led_array_s1_agent_rf_source_endofpacket; // LED_ARRAY_s1_agent:rf_source_endofpacket -> LED_ARRAY_s1_agent_rsp_fifo:in_endofpacket
wire led_array_s1_agent_rsp_fifo_out_valid; // LED_ARRAY_s1_agent_rsp_fifo:out_valid -> LED_ARRAY_s1_agent:rf_sink_valid
wire [75:0] led_array_s1_agent_rsp_fifo_out_data; // LED_ARRAY_s1_agent_rsp_fifo:out_data -> LED_ARRAY_s1_agent:rf_sink_data
wire led_array_s1_agent_rsp_fifo_out_ready; // LED_ARRAY_s1_agent:rf_sink_ready -> LED_ARRAY_s1_agent_rsp_fifo:out_ready
wire led_array_s1_agent_rsp_fifo_out_startofpacket; // LED_ARRAY_s1_agent_rsp_fifo:out_startofpacket -> LED_ARRAY_s1_agent:rf_sink_startofpacket
wire led_array_s1_agent_rsp_fifo_out_endofpacket; // LED_ARRAY_s1_agent_rsp_fifo:out_endofpacket -> LED_ARRAY_s1_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> LED_ARRAY_s1_agent:cp_valid
wire [74:0] cmd_mux_src_data; // cmd_mux:src_data -> LED_ARRAY_s1_agent:cp_data
wire cmd_mux_src_ready; // LED_ARRAY_s1_agent:cp_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> LED_ARRAY_s1_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> LED_ARRAY_s1_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> LED_ARRAY_s1_agent:cp_endofpacket
wire [31:0] switch_array_s1_agent_m0_readdata; // SWITCH_ARRAY_s1_translator:uav_readdata -> SWITCH_ARRAY_s1_agent:m0_readdata
wire switch_array_s1_agent_m0_waitrequest; // SWITCH_ARRAY_s1_translator:uav_waitrequest -> SWITCH_ARRAY_s1_agent:m0_waitrequest
wire switch_array_s1_agent_m0_debugaccess; // SWITCH_ARRAY_s1_agent:m0_debugaccess -> SWITCH_ARRAY_s1_translator:uav_debugaccess
wire [4:0] switch_array_s1_agent_m0_address; // SWITCH_ARRAY_s1_agent:m0_address -> SWITCH_ARRAY_s1_translator:uav_address
wire [3:0] switch_array_s1_agent_m0_byteenable; // SWITCH_ARRAY_s1_agent:m0_byteenable -> SWITCH_ARRAY_s1_translator:uav_byteenable
wire switch_array_s1_agent_m0_read; // SWITCH_ARRAY_s1_agent:m0_read -> SWITCH_ARRAY_s1_translator:uav_read
wire switch_array_s1_agent_m0_readdatavalid; // SWITCH_ARRAY_s1_translator:uav_readdatavalid -> SWITCH_ARRAY_s1_agent:m0_readdatavalid
wire switch_array_s1_agent_m0_lock; // SWITCH_ARRAY_s1_agent:m0_lock -> SWITCH_ARRAY_s1_translator:uav_lock
wire [31:0] switch_array_s1_agent_m0_writedata; // SWITCH_ARRAY_s1_agent:m0_writedata -> SWITCH_ARRAY_s1_translator:uav_writedata
wire switch_array_s1_agent_m0_write; // SWITCH_ARRAY_s1_agent:m0_write -> SWITCH_ARRAY_s1_translator:uav_write
wire [2:0] switch_array_s1_agent_m0_burstcount; // SWITCH_ARRAY_s1_agent:m0_burstcount -> SWITCH_ARRAY_s1_translator:uav_burstcount
wire switch_array_s1_agent_rf_source_valid; // SWITCH_ARRAY_s1_agent:rf_source_valid -> SWITCH_ARRAY_s1_agent_rsp_fifo:in_valid
wire [75:0] switch_array_s1_agent_rf_source_data; // SWITCH_ARRAY_s1_agent:rf_source_data -> SWITCH_ARRAY_s1_agent_rsp_fifo:in_data
wire switch_array_s1_agent_rf_source_ready; // SWITCH_ARRAY_s1_agent_rsp_fifo:in_ready -> SWITCH_ARRAY_s1_agent:rf_source_ready
wire switch_array_s1_agent_rf_source_startofpacket; // SWITCH_ARRAY_s1_agent:rf_source_startofpacket -> SWITCH_ARRAY_s1_agent_rsp_fifo:in_startofpacket
wire switch_array_s1_agent_rf_source_endofpacket; // SWITCH_ARRAY_s1_agent:rf_source_endofpacket -> SWITCH_ARRAY_s1_agent_rsp_fifo:in_endofpacket
wire switch_array_s1_agent_rsp_fifo_out_valid; // SWITCH_ARRAY_s1_agent_rsp_fifo:out_valid -> SWITCH_ARRAY_s1_agent:rf_sink_valid
wire [75:0] switch_array_s1_agent_rsp_fifo_out_data; // SWITCH_ARRAY_s1_agent_rsp_fifo:out_data -> SWITCH_ARRAY_s1_agent:rf_sink_data
wire switch_array_s1_agent_rsp_fifo_out_ready; // SWITCH_ARRAY_s1_agent:rf_sink_ready -> SWITCH_ARRAY_s1_agent_rsp_fifo:out_ready
wire switch_array_s1_agent_rsp_fifo_out_startofpacket; // SWITCH_ARRAY_s1_agent_rsp_fifo:out_startofpacket -> SWITCH_ARRAY_s1_agent:rf_sink_startofpacket
wire switch_array_s1_agent_rsp_fifo_out_endofpacket; // SWITCH_ARRAY_s1_agent_rsp_fifo:out_endofpacket -> SWITCH_ARRAY_s1_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> SWITCH_ARRAY_s1_agent:cp_valid
wire [74:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> SWITCH_ARRAY_s1_agent:cp_data
wire cmd_mux_001_src_ready; // SWITCH_ARRAY_s1_agent:cp_ready -> cmd_mux_001:src_ready
wire [1:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> SWITCH_ARRAY_s1_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> SWITCH_ARRAY_s1_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> SWITCH_ARRAY_s1_agent:cp_endofpacket
wire mm_bridge_m0_agent_cp_valid; // MM_BRIDGE_m0_agent:cp_valid -> router:sink_valid
wire [74:0] mm_bridge_m0_agent_cp_data; // MM_BRIDGE_m0_agent:cp_data -> router:sink_data
wire mm_bridge_m0_agent_cp_ready; // router:sink_ready -> MM_BRIDGE_m0_agent:cp_ready
wire mm_bridge_m0_agent_cp_startofpacket; // MM_BRIDGE_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire mm_bridge_m0_agent_cp_endofpacket; // MM_BRIDGE_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire led_array_s1_agent_rp_valid; // LED_ARRAY_s1_agent:rp_valid -> router_001:sink_valid
wire [74:0] led_array_s1_agent_rp_data; // LED_ARRAY_s1_agent:rp_data -> router_001:sink_data
wire led_array_s1_agent_rp_ready; // router_001:sink_ready -> LED_ARRAY_s1_agent:rp_ready
wire led_array_s1_agent_rp_startofpacket; // LED_ARRAY_s1_agent:rp_startofpacket -> router_001:sink_startofpacket
wire led_array_s1_agent_rp_endofpacket; // LED_ARRAY_s1_agent:rp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire [74:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire switch_array_s1_agent_rp_valid; // SWITCH_ARRAY_s1_agent:rp_valid -> router_002:sink_valid
wire [74:0] switch_array_s1_agent_rp_data; // SWITCH_ARRAY_s1_agent:rp_data -> router_002:sink_data
wire switch_array_s1_agent_rp_ready; // router_002:sink_ready -> SWITCH_ARRAY_s1_agent:rp_ready
wire switch_array_s1_agent_rp_startofpacket; // SWITCH_ARRAY_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire switch_array_s1_agent_rp_endofpacket; // SWITCH_ARRAY_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux_001:sink_valid
wire [74:0] router_002_src_data; // router_002:src_data -> rsp_demux_001:sink_data
wire router_002_src_ready; // rsp_demux_001:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux_001:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_src_valid; // router:src_valid -> MM_BRIDGE_m0_limiter:cmd_sink_valid
wire [74:0] router_src_data; // router:src_data -> MM_BRIDGE_m0_limiter:cmd_sink_data
wire router_src_ready; // MM_BRIDGE_m0_limiter:cmd_sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> MM_BRIDGE_m0_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> MM_BRIDGE_m0_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> MM_BRIDGE_m0_limiter:cmd_sink_endofpacket
wire [74:0] mm_bridge_m0_limiter_cmd_src_data; // MM_BRIDGE_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire mm_bridge_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> MM_BRIDGE_m0_limiter:cmd_src_ready
wire [1:0] mm_bridge_m0_limiter_cmd_src_channel; // MM_BRIDGE_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire mm_bridge_m0_limiter_cmd_src_startofpacket; // MM_BRIDGE_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire mm_bridge_m0_limiter_cmd_src_endofpacket; // MM_BRIDGE_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> MM_BRIDGE_m0_limiter:rsp_sink_valid
wire [74:0] rsp_mux_src_data; // rsp_mux:src_data -> MM_BRIDGE_m0_limiter:rsp_sink_data
wire rsp_mux_src_ready; // MM_BRIDGE_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> MM_BRIDGE_m0_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> MM_BRIDGE_m0_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> MM_BRIDGE_m0_limiter:rsp_sink_endofpacket
wire mm_bridge_m0_limiter_rsp_src_valid; // MM_BRIDGE_m0_limiter:rsp_src_valid -> MM_BRIDGE_m0_agent:rp_valid
wire [74:0] mm_bridge_m0_limiter_rsp_src_data; // MM_BRIDGE_m0_limiter:rsp_src_data -> MM_BRIDGE_m0_agent:rp_data
wire mm_bridge_m0_limiter_rsp_src_ready; // MM_BRIDGE_m0_agent:rp_ready -> MM_BRIDGE_m0_limiter:rsp_src_ready
wire [1:0] mm_bridge_m0_limiter_rsp_src_channel; // MM_BRIDGE_m0_limiter:rsp_src_channel -> MM_BRIDGE_m0_agent:rp_channel
wire mm_bridge_m0_limiter_rsp_src_startofpacket; // MM_BRIDGE_m0_limiter:rsp_src_startofpacket -> MM_BRIDGE_m0_agent:rp_startofpacket
wire mm_bridge_m0_limiter_rsp_src_endofpacket; // MM_BRIDGE_m0_limiter:rsp_src_endofpacket -> MM_BRIDGE_m0_agent:rp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [74:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [74:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [1:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [74:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [74:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [1:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire [1:0] mm_bridge_m0_limiter_cmd_valid_data; // MM_BRIDGE_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire led_array_s1_agent_rdata_fifo_src_valid; // LED_ARRAY_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] led_array_s1_agent_rdata_fifo_src_data; // LED_ARRAY_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire led_array_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> LED_ARRAY_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> LED_ARRAY_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> LED_ARRAY_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // LED_ARRAY_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> LED_ARRAY_s1_agent:rdata_fifo_sink_error
wire switch_array_s1_agent_rdata_fifo_src_valid; // SWITCH_ARRAY_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] switch_array_s1_agent_rdata_fifo_src_data; // SWITCH_ARRAY_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire switch_array_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> SWITCH_ARRAY_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> SWITCH_ARRAY_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> SWITCH_ARRAY_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // SWITCH_ARRAY_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> SWITCH_ARRAY_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (5),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (5),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) mm_bridge_m0_translator (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mm_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (mm_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (mm_bridge_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (mm_bridge_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (mm_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (mm_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (mm_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (mm_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (mm_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (mm_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (mm_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (MM_BRIDGE_m0_address), // avalon_anti_master_0.address
.av_waitrequest (MM_BRIDGE_m0_waitrequest), // .waitrequest
.av_burstcount (MM_BRIDGE_m0_burstcount), // .burstcount
.av_byteenable (MM_BRIDGE_m0_byteenable), // .byteenable
.av_read (MM_BRIDGE_m0_read), // .read
.av_readdata (MM_BRIDGE_m0_readdata), // .readdata
.av_readdatavalid (MM_BRIDGE_m0_readdatavalid), // .readdatavalid
.av_write (MM_BRIDGE_m0_write), // .write
.av_writedata (MM_BRIDGE_m0_writedata), // .writedata
.av_debugaccess (MM_BRIDGE_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (5),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) led_array_s1_translator (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (led_array_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (led_array_s1_agent_m0_burstcount), // .burstcount
.uav_read (led_array_s1_agent_m0_read), // .read
.uav_write (led_array_s1_agent_m0_write), // .write
.uav_waitrequest (led_array_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (led_array_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (led_array_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (led_array_s1_agent_m0_readdata), // .readdata
.uav_writedata (led_array_s1_agent_m0_writedata), // .writedata
.uav_lock (led_array_s1_agent_m0_lock), // .lock
.uav_debugaccess (led_array_s1_agent_m0_debugaccess), // .debugaccess
.av_address (LED_ARRAY_s1_address), // avalon_anti_slave_0.address
.av_write (LED_ARRAY_s1_write), // .write
.av_readdata (LED_ARRAY_s1_readdata), // .readdata
.av_writedata (LED_ARRAY_s1_writedata), // .writedata
.av_chipselect (LED_ARRAY_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (5),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) switch_array_s1_translator (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (switch_array_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (switch_array_s1_agent_m0_burstcount), // .burstcount
.uav_read (switch_array_s1_agent_m0_read), // .read
.uav_write (switch_array_s1_agent_m0_write), // .write
.uav_waitrequest (switch_array_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (switch_array_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (switch_array_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (switch_array_s1_agent_m0_readdata), // .readdata
.uav_writedata (switch_array_s1_agent_m0_writedata), // .writedata
.uav_lock (switch_array_s1_agent_m0_lock), // .lock
.uav_debugaccess (switch_array_s1_agent_m0_debugaccess), // .debugaccess
.av_address (SWITCH_ARRAY_s1_address), // avalon_anti_slave_0.address
.av_readdata (SWITCH_ARRAY_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (74),
.PKT_ORI_BURST_SIZE_L (72),
.PKT_RESPONSE_STATUS_H (71),
.PKT_RESPONSE_STATUS_L (70),
.PKT_QOS_H (59),
.PKT_QOS_L (59),
.PKT_DATA_SIDEBAND_H (57),
.PKT_DATA_SIDEBAND_L (57),
.PKT_ADDR_SIDEBAND_H (56),
.PKT_ADDR_SIDEBAND_L (56),
.PKT_BURST_TYPE_H (55),
.PKT_BURST_TYPE_L (54),
.PKT_CACHE_H (69),
.PKT_CACHE_L (66),
.PKT_THREAD_ID_H (62),
.PKT_THREAD_ID_L (62),
.PKT_BURST_SIZE_H (53),
.PKT_BURST_SIZE_L (51),
.PKT_TRANS_EXCLUSIVE (46),
.PKT_TRANS_LOCK (45),
.PKT_BEGIN_BURST (58),
.PKT_PROTECTION_H (65),
.PKT_PROTECTION_L (63),
.PKT_BURSTWRAP_H (50),
.PKT_BURSTWRAP_L (50),
.PKT_BYTE_CNT_H (49),
.PKT_BYTE_CNT_L (47),
.PKT_ADDR_H (40),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (41),
.PKT_TRANS_POSTED (42),
.PKT_TRANS_WRITE (43),
.PKT_TRANS_READ (44),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (60),
.PKT_SRC_ID_L (60),
.PKT_DEST_ID_H (61),
.PKT_DEST_ID_L (61),
.ST_DATA_W (75),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mm_bridge_m0_agent (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (mm_bridge_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (mm_bridge_m0_translator_avalon_universal_master_0_write), // .write
.av_read (mm_bridge_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (mm_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (mm_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (mm_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (mm_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (mm_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (mm_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (mm_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (mm_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (mm_bridge_m0_agent_cp_valid), // cp.valid
.cp_data (mm_bridge_m0_agent_cp_data), // .data
.cp_startofpacket (mm_bridge_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (mm_bridge_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (mm_bridge_m0_agent_cp_ready), // .ready
.rp_valid (mm_bridge_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (mm_bridge_m0_limiter_rsp_src_data), // .data
.rp_channel (mm_bridge_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (mm_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (mm_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (mm_bridge_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (74),
.PKT_ORI_BURST_SIZE_L (72),
.PKT_RESPONSE_STATUS_H (71),
.PKT_RESPONSE_STATUS_L (70),
.PKT_BURST_SIZE_H (53),
.PKT_BURST_SIZE_L (51),
.PKT_TRANS_LOCK (45),
.PKT_BEGIN_BURST (58),
.PKT_PROTECTION_H (65),
.PKT_PROTECTION_L (63),
.PKT_BURSTWRAP_H (50),
.PKT_BURSTWRAP_L (50),
.PKT_BYTE_CNT_H (49),
.PKT_BYTE_CNT_L (47),
.PKT_ADDR_H (40),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (41),
.PKT_TRANS_POSTED (42),
.PKT_TRANS_WRITE (43),
.PKT_TRANS_READ (44),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (60),
.PKT_SRC_ID_L (60),
.PKT_DEST_ID_H (61),
.PKT_DEST_ID_L (61),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) led_array_s1_agent (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (led_array_s1_agent_m0_address), // m0.address
.m0_burstcount (led_array_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (led_array_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (led_array_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (led_array_s1_agent_m0_lock), // .lock
.m0_readdata (led_array_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (led_array_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (led_array_s1_agent_m0_read), // .read
.m0_waitrequest (led_array_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (led_array_s1_agent_m0_writedata), // .writedata
.m0_write (led_array_s1_agent_m0_write), // .write
.rp_endofpacket (led_array_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (led_array_s1_agent_rp_ready), // .ready
.rp_valid (led_array_s1_agent_rp_valid), // .valid
.rp_data (led_array_s1_agent_rp_data), // .data
.rp_startofpacket (led_array_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (led_array_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (led_array_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (led_array_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (led_array_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (led_array_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (led_array_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (led_array_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (led_array_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (led_array_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (led_array_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (led_array_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (led_array_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (led_array_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_array_s1_agent_rsp_fifo (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (led_array_s1_agent_rf_source_data), // in.data
.in_valid (led_array_s1_agent_rf_source_valid), // .valid
.in_ready (led_array_s1_agent_rf_source_ready), // .ready
.in_startofpacket (led_array_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (led_array_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (led_array_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (led_array_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (led_array_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (led_array_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (led_array_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (74),
.PKT_ORI_BURST_SIZE_L (72),
.PKT_RESPONSE_STATUS_H (71),
.PKT_RESPONSE_STATUS_L (70),
.PKT_BURST_SIZE_H (53),
.PKT_BURST_SIZE_L (51),
.PKT_TRANS_LOCK (45),
.PKT_BEGIN_BURST (58),
.PKT_PROTECTION_H (65),
.PKT_PROTECTION_L (63),
.PKT_BURSTWRAP_H (50),
.PKT_BURSTWRAP_L (50),
.PKT_BYTE_CNT_H (49),
.PKT_BYTE_CNT_L (47),
.PKT_ADDR_H (40),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (41),
.PKT_TRANS_POSTED (42),
.PKT_TRANS_WRITE (43),
.PKT_TRANS_READ (44),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (60),
.PKT_SRC_ID_L (60),
.PKT_DEST_ID_H (61),
.PKT_DEST_ID_L (61),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (75),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) switch_array_s1_agent (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (switch_array_s1_agent_m0_address), // m0.address
.m0_burstcount (switch_array_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (switch_array_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (switch_array_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (switch_array_s1_agent_m0_lock), // .lock
.m0_readdata (switch_array_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (switch_array_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (switch_array_s1_agent_m0_read), // .read
.m0_waitrequest (switch_array_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (switch_array_s1_agent_m0_writedata), // .writedata
.m0_write (switch_array_s1_agent_m0_write), // .write
.rp_endofpacket (switch_array_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (switch_array_s1_agent_rp_ready), // .ready
.rp_valid (switch_array_s1_agent_rp_valid), // .valid
.rp_data (switch_array_s1_agent_rp_data), // .data
.rp_startofpacket (switch_array_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (switch_array_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (switch_array_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (switch_array_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (switch_array_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (switch_array_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (switch_array_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (switch_array_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (switch_array_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (switch_array_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (switch_array_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (switch_array_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (switch_array_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (switch_array_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (76),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) switch_array_s1_agent_rsp_fifo (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (switch_array_s1_agent_rf_source_data), // in.data
.in_valid (switch_array_s1_agent_rf_source_valid), // .valid
.in_ready (switch_array_s1_agent_rf_source_ready), // .ready
.in_startofpacket (switch_array_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (switch_array_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (switch_array_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (switch_array_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (switch_array_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (switch_array_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (switch_array_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
ledtest_mm_interconnect_1_router router (
.sink_ready (mm_bridge_m0_agent_cp_ready), // sink.ready
.sink_valid (mm_bridge_m0_agent_cp_valid), // .valid
.sink_data (mm_bridge_m0_agent_cp_data), // .data
.sink_startofpacket (mm_bridge_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (mm_bridge_m0_agent_cp_endofpacket), // .endofpacket
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_router_001 router_001 (
.sink_ready (led_array_s1_agent_rp_ready), // sink.ready
.sink_valid (led_array_s1_agent_rp_valid), // .valid
.sink_data (led_array_s1_agent_rp_data), // .data
.sink_startofpacket (led_array_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (led_array_s1_agent_rp_endofpacket), // .endofpacket
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_router_001 router_002 (
.sink_ready (switch_array_s1_agent_rp_ready), // sink.ready
.sink_valid (switch_array_s1_agent_rp_valid), // .valid
.sink_data (switch_array_s1_agent_rp_data), // .data
.sink_startofpacket (switch_array_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (switch_array_s1_agent_rp_endofpacket), // .endofpacket
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (61),
.PKT_DEST_ID_L (61),
.PKT_SRC_ID_H (60),
.PKT_SRC_ID_L (60),
.PKT_BYTE_CNT_H (49),
.PKT_BYTE_CNT_L (47),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (42),
.PKT_TRANS_WRITE (43),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (75),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) mm_bridge_m0_limiter (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (mm_bridge_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (mm_bridge_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (mm_bridge_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (mm_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (mm_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (mm_bridge_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (mm_bridge_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (mm_bridge_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (mm_bridge_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (mm_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (mm_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (mm_bridge_m0_limiter_cmd_valid_data) // cmd_valid.data
);
ledtest_mm_interconnect_1_cmd_demux cmd_demux (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (mm_bridge_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (mm_bridge_m0_limiter_cmd_src_channel), // .channel
.sink_data (mm_bridge_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (mm_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (mm_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (mm_bridge_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_cmd_mux cmd_mux (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_rsp_demux rsp_demux (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_1_rsp_mux rsp_mux (
.clk (CLOCK_clk_clk), // clk.clk
.reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
ledtest_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (CLOCK_clk_clk), // in_clk_0.clk
.in_rst_0_reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (led_array_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (led_array_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (led_array_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
ledtest_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (CLOCK_clk_clk), // in_clk_0.clk
.in_rst_0_reset (MM_BRIDGE_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (switch_array_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (switch_array_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (switch_array_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
endmodule
|
module sky130_fd_sc_lp__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
|
module DUAL_AD_PREADDER
(
A, ACIN, D, INMODE,
ACOUT, XMUX, AMULT,
CEA1, CEA2, RSTA, CED, CEAD, RSTD, CLK
);
parameter A_INPUT = "DIRECT";
parameter ACASCREG = 1;
parameter ADREG = 1;
parameter ALUMODEREG = 1;
parameter AREG = 1;
parameter DREG = 1;
parameter USE_DPORT = "FALSE";
input wire [29:0] A;
input wire [29:0] ACIN;
input wire [24:0] D;
input wire [4:0] INMODE;
output wire [29:0] ACOUT;
output wire [29:0] XMUX;
output wire [24:0] AMULT;
input wire CEA1;
input wire CEA2;
input wire RSTA;
input wire CED;
input wire CEAD;
input wire RSTD;
input wire CLK;
wire [29:0] A1IN;
wire [29:0] A1REG_OUT;
wire [29:0] A2IN;
wire [29:0] A2REG_OUT;
wire [29:0] XMUX;
wire [24:0] DREG_OUT;
wire [24:0] DOUT;
wire [24:0] ADDER_OUT;
wire [24:0] ADDER_AIN;
wire [24:0] ADDER_DIN;
wire [24:0] ADREG_OUT;
wire [24:0] AD_OUT;
wire [24:0] A_ADDER_CANDIDATE;
`ifndef PB_TYPE
AIN_MUX #(.S(A_INPUT == "DIRECT")) ain_mux (.A(A), .ACIN(ACIN), .O(A1IN));
AREG_MUX #(.S(AREG==2)) a1mux (.BYPASS(A1IN), .REG(A1REG_OUT), .O(A2IN));
AREG_MUX #(.S(AREG>0)) a2mux (.BYPASS(A2IN), .REG(A2REG_OUT), .O(XMUX));
ACOUT_MUX #(.S(ACASCREG == 1)) acout_mux (.I0(A1REG_OUT), .I1(XMUX), .O(ACOUT));
NREG #(.NBITS(30)) a1 (.D(A1IN), .Q(A1REG_OUT), .CLK(CLK), .CE(CEA1), .RESET(RSTA));
NREG #(.NBITS(30)) a2 (.D(A2IN), .Q(A2REG_OUT), .CLK(CLK), .CE(CEA2), .RESET(RSTA));
DREG_MUX #(.S(DREG == 0)) d_mux (.BYPASS(D), .REG(DREG_OUT), .O(DOUT));
DREG_MUX #(.S(ADREG == 0)) ad_mux (.BYPASS(ADDER_OUT), .REG(ADREG_OUT), .O(AD_OUT));
NREG #(.NBITS(25)) d (.D(D), .Q(DREG_OUT), .CLK(CLK), .CE(CED), .RESET(RSTD));
NREG #(.NBITS(25)) ad (.D(ADDER_OUT), .Q(ADREG_OUT), .CLK(CLK), .CE(CEAD), .RESET(RSTD));
A_ADDER_MUX a_adder_muxx (.A2(XMUX[24:0]), .A1(A1REG_OUT[24:0]), .S(INMODE[0]), .O(A_ADDER_CANDIDATE));
A_ADDER_MUX a_or_zero (.A2(A_ADDER_CANDIDATE), .A1(25'b0), .S(INMODE[1]), .O(ADDER_AIN));
A_ADDER_MUX d_or_zero (.A2(25'b0), .A1(DOUT), .S(INMODE[2]), .O(ADDER_DIN));
assign ADDER_OUT = INMODE[3] ? (ADDER_DIN - ADDER_AIN) : (ADDER_DIN + ADDER_AIN);
AMULT_MUX #(.S(USE_DPORT == "FALSE")) amult_mux (.A(ADDER_AIN), .ADDER_OUT(ADDER_OUT), .O(AMULT));
`endif // `ifndef PB_TYPE
endmodule
|
module sky130_fd_sc_hd__o22a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module sky130_fd_sc_ms__einvn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__einvn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
|
module or1200_mult_mac(
// Clock and reset
clk, rst,
// Multiplier/MAC interface
ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
// SPR interface
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Multiplier/MAC interface
//
input ex_freeze;
input id_macrc_op;
input macrc_op;
input [width-1:0] a;
input [width-1:0] b;
input [`OR1200_MACOP_WIDTH-1:0] mac_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [width-1:0] result;
output mac_stall_r;
//
// SPR interface
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
`ifdef OR1200_MULT_IMPLEMENTED
reg [width-1:0] result;
reg [2*width-1:0] mul_prod_r;
`else
wire [width-1:0] result;
wire [2*width-1:0] mul_prod_r;
`endif
wire [2*width-1:0] mul_prod;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
reg mac_stall_r;
reg [2*width-1:0] mac_r;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
wire mac_stall_r;
wire [2*width-1:0] mac_r;
`endif
wire [width-1:0] x;
wire [width-1:0] y;
wire spr_maclo_we;
wire spr_machi_we;
wire alu_op_div_divu;
wire alu_op_div;
reg div_free;
`ifdef OR1200_IMPL_DIV
wire [width-1:0] div_tmp;
reg [5:0] div_cntr;
`endif
//
// Combinatorial logic
//
`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`else
assign spr_maclo_we = 1'b0;
assign spr_machi_we = 1'b0;
assign spr_dat_o = 32'h0000_0000;
`endif
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
`else
assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
`endif
`ifdef OR1200_IMPL_DIV
assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
assign div_tmp = mul_prod_r[63:32] - y;
`else
assign alu_op_div = 1'b0;
assign alu_op_div_divu = 1'b0;
`endif
`ifdef OR1200_MULT_IMPLEMENTED
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @(alu_op or mul_prod_r or mac_r or a or b)
casex(alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_DIV
`OR1200_ALUOP_DIV:
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL: begin
result = mul_prod_r[31:0];
end
default:
`ifdef OR1200_MAC_SHIFTBY
result = mac_r[`OR1200_MAC_SHIFTBY+31:`OR1200_MAC_SHIFTBY];
`else
result = mac_r[31:0];
`endif
endcase
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`else // OR1200_ASIC_MULTP2_32X32
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`endif // OR1200_ASIC_MULTP2_32X32
//
// Registered output from the multiplier and
// an optional divider
//
always @(posedge rst or posedge clk)
if (rst) begin
mul_prod_r <= #1 64'h0000_0000_0000_0000;
div_free <= #1 1'b1;
`ifdef OR1200_IMPL_DIV
div_cntr <= #1 6'b00_0000;
`endif
end
`ifdef OR1200_IMPL_DIV
else if (|div_cntr) begin
if (div_tmp[31])
mul_prod_r <= #1 {mul_prod_r[62:0], 1'b0};
else
mul_prod_r <= #1 {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
div_cntr <= #1 div_cntr - 1'b1;
end
else if (alu_op_div_divu && div_free) begin
mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};
div_cntr <= #1 6'b10_0000;
div_free <= #1 1'b0;
end
`endif // OR1200_IMPL_DIV
else if (div_free | !ex_freeze) begin
mul_prod_r <= #1 mul_prod[63:0];
div_free <= #1 1'b1;
end
`else // OR1200_MULT_IMPLEMENTED
assign result = {width{1'b0}};
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
`endif // OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r1 <= #1 mac_op;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r2 <= #1 mac_op_r1;
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
if (rst)
mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
else
mac_op_r3 <= #1 mac_op_r2;
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
if (rst)
mac_r <= #1 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
else if (spr_maclo_we)
mac_r[31:0] <= #1 spr_dat_i;
else if (spr_machi_we)
mac_r[63:32] <= #1 spr_dat_i;
`endif
else if (mac_op_r3 == `OR1200_MACOP_MAC)
mac_r <= #1 mac_r + mul_prod_r;
else if (mac_op_r3 == `OR1200_MACOP_MSB)
mac_r <= #1 mac_r - mul_prod_r;
else if (macrc_op & !ex_freeze)
mac_r <= #1 64'h0000_0000_0000_0000;
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(posedge rst or posedge clk)
if (rst)
mac_stall_r <= #1 1'b0;
else
mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
`ifdef OR1200_IMPL_DIV
| (|div_cntr)
`endif
;
`else // OR1200_MAC_IMPLEMENTED
assign mac_stall_r = 1'b0;
assign mac_r = {2*width{1'b0}};
assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
`endif // OR1200_MAC_IMPLEMENTED
//
// Abstruct the signal we are interested in
//
//always @(posedge clk or posedge rst)
//$show_signal_value(or1200_mult_mac, mac_stall_r);
endmodule
|
module sky130_fd_sc_ls__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
|
module juniversalShiftRegisterTb;
wire [3:0] DATAOUT;
reg clock, reset;
reg [1:0] MODE;
reg [3:0] DATAIN;
juniversalShiftRegister jusr(DATAOUT, clock, reset, MODE, DATAIN);
initial
begin
clock =0; MODE = 2'b00; DATAIN = 4'b0000;
reset = 1; #10; reset = 0; #10;
$display("RSLT\tD == DOUT");
// Start testing Right Shift mode
MODE = 2'b00; reset = 1; #10; reset = 0; #10;
MODE = 2'b01; DATAIN = 4'b0011; #10;
if ( DATAOUT === 4'b1000 ) // look at previous value of DATAOUT as well
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
MODE = 2'b01; DATAIN = 4'b0011; #10;
if ( DATAOUT === 4'b1100 ) // look at previous value of DATAOUT as well
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
// Start testing Left Shift mode
MODE = 2'b00; reset = 1; #10; reset = 0; #10;
MODE = 2'b10; DATAIN = 4'b0111; #10;
if ( DATAOUT === 4'b0001 ) //
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
MODE = 2'b10; DATAIN = 4'b0111; #10;
if ( DATAOUT === 4'b0011 ) //
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
// Start testing parallel load mode
MODE = 2'b00; reset = 1; #10; reset = 0; #10;
MODE = 2'b11; DATAIN = 4'b1010; #10;
if ( DATAOUT === 4'b1010 )
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
#20;
$finish;
end
always #5 clock = ~clock;
endmodule
|
module ex_mem(
input wire clk,
input wire rst,
//À´×Ô¿ØÖÆÄ£¿éµÄÐÅÏ¢
input wire[5:0] stall,
input wire flush,
//À´×ÔÖ´Ðн׶εÄÐÅÏ¢
input wire[`RegAddrBus] ex_wd,
input wire ex_wreg,
input wire[`RegBus] ex_wdata,
input wire[`RegBus] ex_hi,
input wire[`RegBus] ex_lo,
input wire ex_whilo,
//ΪʵÏÖ¼ÓÔØ¡¢·Ã´æÖ¸Áî¶øÌí¼Ó
input wire[`AluOpBus] ex_aluop,
input wire[`RegBus] ex_mem_addr,
input wire[`RegBus] ex_reg2,
input wire[`DoubleRegBus] hilo_i,
input wire[1:0] cnt_i,
input wire ex_cp0_reg_we,
input wire[4:0] ex_cp0_reg_write_addr,
input wire[`RegBus] ex_cp0_reg_data,
input wire[31:0] ex_excepttype,
input wire ex_is_in_delayslot,
input wire[`RegBus] ex_current_inst_address,
//Ë͵½·Ã´æ½×¶ÎµÄÐÅÏ¢
output reg[`RegAddrBus] mem_wd,
output reg mem_wreg,
output reg[`RegBus] mem_wdata,
output reg[`RegBus] mem_hi,
output reg[`RegBus] mem_lo,
output reg mem_whilo,
//ΪʵÏÖ¼ÓÔØ¡¢·Ã´æÖ¸Áî¶øÌí¼Ó
output reg[`AluOpBus] mem_aluop,
output reg[`RegBus] mem_mem_addr,
output reg[`RegBus] mem_reg2,
output reg mem_cp0_reg_we,
output reg[4:0] mem_cp0_reg_write_addr,
output reg[`RegBus] mem_cp0_reg_data,
output reg[31:0] mem_excepttype,
output reg mem_is_in_delayslot,
output reg[`RegBus] mem_current_inst_address,
output reg[`DoubleRegBus] hilo_o,
output reg[1:0] cnt_o
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
mem_whilo <= `WriteDisable;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_we <= `WriteDisable;
mem_cp0_reg_write_addr <= 5'b00000;
mem_cp0_reg_data <= `ZeroWord;
mem_excepttype <= `ZeroWord;
mem_is_in_delayslot <= `NotInDelaySlot;
mem_current_inst_address <= `ZeroWord;
end else if(flush == 1'b1 ) begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
mem_whilo <= `WriteDisable;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_we <= `WriteDisable;
mem_cp0_reg_write_addr <= 5'b00000;
mem_cp0_reg_data <= `ZeroWord;
mem_excepttype <= `ZeroWord;
mem_is_in_delayslot <= `NotInDelaySlot;
mem_current_inst_address <= `ZeroWord;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
end else if(stall[3] == `Stop && stall[4] == `NoStop) begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
mem_whilo <= `WriteDisable;
hilo_o <= hilo_i;
cnt_o <= cnt_i;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_we <= `WriteDisable;
mem_cp0_reg_write_addr <= 5'b00000;
mem_cp0_reg_data <= `ZeroWord;
mem_excepttype <= `ZeroWord;
mem_is_in_delayslot <= `NotInDelaySlot;
mem_current_inst_address <= `ZeroWord;
end else if(stall[3] == `NoStop) begin
mem_wd <= ex_wd;
mem_wreg <= ex_wreg;
mem_wdata <= ex_wdata;
mem_hi <= ex_hi;
mem_lo <= ex_lo;
mem_whilo <= ex_whilo;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
mem_aluop <= ex_aluop;
mem_mem_addr <= ex_mem_addr;
mem_reg2 <= ex_reg2;
mem_cp0_reg_we <= ex_cp0_reg_we;
mem_cp0_reg_write_addr <= ex_cp0_reg_write_addr;
mem_cp0_reg_data <= ex_cp0_reg_data;
mem_excepttype <= ex_excepttype;
mem_is_in_delayslot <= ex_is_in_delayslot;
mem_current_inst_address <= ex_current_inst_address;
end else begin
hilo_o <= hilo_i;
cnt_o <= cnt_i;
end //if
end //always
endmodule
|
module mig_7series_v2_0_qdr_rld_phy_4lanes #(
parameter MEMORY_TYPE = "SRAM",
parameter SIMULATION = "FALSE",
parameter PO_COARSE_BYPASS = "FALSE",
parameter CPT_CLK_CQ_ONLY = "TRUE",
parameter INTERFACE_TYPE = "UNIDIR",
parameter PRE_FIFO = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG", //May be assigned unique name
// when mult IP cores in design
parameter IODELAY_HP_MODE = "ON", //IODELAY High Performance Mode
parameter BYTE_GROUP_TYPE = 4'b1111,
parameter GENERATE_CQ = 4'b0000,
// next three parameter fields correspond to byte lanes for lane order DCBA
parameter BYTE_LANES = 4'b1111, // lane existence, one per lane
parameter BITLANES_IN = 48'h000_000_000_000,
parameter BITLANES_OUT = 48'h000_000_000_000,
parameter CK_P_OUT = 48'h000_000_000_000,
parameter DATA_CTL_N = 4'b1111, // data or control, per lane
parameter CPT_CLK_SEL = 32'h12_12_11_11,
parameter PO_FINE_DELAY = 0,
parameter PI_FINE_DELAY = 0,
parameter A_PO_COARSE_DELAY = 0,
parameter B_PO_COARSE_DELAY = 0,
parameter C_PO_COARSE_DELAY = 0,
parameter D_PO_COARSE_DELAY = 0,
parameter A_PO_FINE_DELAY = 0,
parameter B_PO_FINE_DELAY = 0,
parameter C_PO_FINE_DELAY = 0,
parameter D_PO_FINE_DELAY = 0,
parameter BUFMR_DELAY = 500,
parameter GENERATE_DDR_CK = 4'b1111,
parameter GENERATE_DDR_DK = 4'b0000,
parameter DIFF_CK = 1'b1,
parameter DIFF_DK = 1'b1,
parameter DIFF_CQ = 1'b0,
parameter CK_VALUE_D1 = 1'b0,
parameter DK_VALUE_D1 = 1'b0,
parameter LANE_REMAP = 16'h3210,// 4-bit index
// used to rewire to one of four
// input/output buss lanes
// example: 0321 remaps lanes as:
// D->A
// C->D
// B->C
// A->B
parameter LAST_BANK = "FALSE",
//phaser_in parameters
parameter A_PI_FREQ_REF_DIV = "NONE",
parameter A_PI_FINE_DELAY = PI_FINE_DELAY,
parameter real A_PI_REFCLK_PERIOD = 2.5,
parameter real MEMREFCLK_PERIOD = 2.5,
parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter real B_PI_REFCLK_PERIOD = 2.5,
parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter C_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter real C_PI_REFCLK_PERIOD = 2.5,
parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter D_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter real D_PI_REFCLK_PERIOD = 2.5,
//phaser_out parameters
//parameter A_PO_FINE_DELAY = PO_FINE_DELAY,
parameter A_PO_OCLK_DELAY = 5,
parameter A_PO_OCLKDELAY_INV = "TRUE",
parameter real A_PO_REFCLK_PERIOD = 2.5,
//parameter B_PO_FINE_DELAY = PO_FINE_DELAY,
parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter real B_PO_REFCLK_PERIOD = A_PO_REFCLK_PERIOD,
//parameter C_PO_FINE_DELAY = PO_FINE_DELAY,
parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter real C_PO_REFCLK_PERIOD = A_PO_REFCLK_PERIOD,
//parameter D_PO_FINE_DELAY = PO_FINE_DELAY,
parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter real D_PO_REFCLK_PERIOD = A_PO_REFCLK_PERIOD,
// phy_control parameters
parameter PC_BURST_MODE = "TRUE",
parameter PC_CLK_RATIO = 2,
//parameter PC_DATA_CTL_N = DATA_CTL_N,
parameter PC_CMD_OFFSET = 0,
parameter PC_RD_CMD_OFFSET_0 = 0,
parameter PC_RD_CMD_OFFSET_1 = 0,
parameter PC_RD_CMD_OFFSET_2 = 0,
parameter PC_RD_CMD_OFFSET_3 = 0,
parameter PC_CO_DURATION = 1,
parameter PC_DI_DURATION = 1,
parameter PC_DO_DURATION = 1,
parameter PC_RD_DURATION_0 = 0,
parameter PC_RD_DURATION_1 = 0,
parameter PC_RD_DURATION_2 = 0,
parameter PC_RD_DURATION_3 = 0,
parameter PC_WR_CMD_OFFSET_0 = 5,
parameter PC_WR_CMD_OFFSET_1 = 5,
parameter PC_WR_CMD_OFFSET_2 = 5,
parameter PC_WR_CMD_OFFSET_3 = 5,
parameter PC_WR_DURATION_0 = 6,
parameter PC_WR_DURATION_1 = 6,
parameter PC_WR_DURATION_2 = 6,
parameter PC_WR_DURATION_3 = 6,
parameter PC_AO_WRLVL_EN = 0,
parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PC_FOUR_WINDOW_CLOCKS = 63,
parameter PC_EVENTS_DELAY = 18,
parameter PC_PHY_COUNT_EN = "TRUE",
parameter PC_SYNC_MODE = "FALSE",
parameter PC_DISABLE_SEQ_MATCH = "TRUE",
parameter PC_MULTI_REGION = "FALSE",
parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),
parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),
parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),
parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,
parameter REFCLK_FREQ = 300.0, //Reference Clk Feq for IODELAYs
parameter BUFG_FOR_OUTPUTS = "OFF",
parameter CLK_PERIOD = 0,
parameter TCQ = 100
)
(
input rst,
input phy_clk,
input phy_clk_fast,
input freq_refclk,
input mem_refclk,
//input mem_refclk_div4,
input sync_pulse,
input phy_ctl_mstr_empty,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input out_fifos_full ,
// phy control word
input phy_ctl_clk,
input pll_lock,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
//input input_sink,
output phy_ctl_a_full,
output phy_ctl_full,
//output reg mcGo,
output phy_ctl_empty,
output phy_ctl_ready,
input phy_read_calib,
input phy_write_calib,
output [7:0] ddr_clk, // to memory
output if_a_empty,
output if_empty,
output if_full,
output of_empty,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output [HIGHEST_LANE*80-1:0]phy_din, // array_mode 4x4
output [HIGHEST_LANE*12-1:0]O,
input [HIGHEST_LANE*12-1:0]I,
output wire [HIGHEST_LANE*12-1:0] mem_dq_ts,
input sys_rst,
input rst_rd_clk,
input [3:0] Q_clk,
input [3:0] Qn_clk,
input [1:0] cpt_clk_above, //read clock from bank above
input [1:0] cpt_clk_n_above, //read clock from bank above
input [1:0] cpt_clk_below, //read clock from bank below
input [1:0] cpt_clk_n_below, //read clock from bank below
output [1:0] cpt_clk,
output [1:0] cpt_clk_n,
input idelay_ld,
input [47:0] idelay_ce,
input [47:0] idelay_inc,
input [HIGHEST_LANE*5*12-1:0] idelay_cnt_in,
output wire [HIGHEST_LANE*5*12-1:0] idelay_cnt_out,
input [2:0] calib_sel,
input calib_in_common,
input [3:0] drive_on_calib_in_common,
input po_edge_adv,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [8:0] po_counter_load_val,
input po_sel_fine_oclk_delay,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
output wire po_delay_done,
input po_dec_done,
input po_inc_done,
input pi_edge_adv,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output wire ref_dll_lock,
input rst_phaser_ref,
output [1023:0] dbg_byte_lane, // RC
output [255:0] dbg_phy_4lanes // RC
);
localparam DATA_CTL_A = (~DATA_CTL_N[0]);
localparam DATA_CTL_B = (~DATA_CTL_N[1]);
localparam DATA_CTL_C = (~DATA_CTL_N[2]);
localparam DATA_CTL_D = (~DATA_CTL_N[3]);
localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];
localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];
localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];
localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];
// OUTPUT_BANK is true when the byte lane has atleast one output byte lane.
localparam OUTPUT_BANK = ((BYTE_LANES[0] && ~BYTE_GROUP_TYPE[0]) ||
(BYTE_LANES[1] && ~BYTE_GROUP_TYPE[1]) ||
(BYTE_LANES[2] && ~BYTE_GROUP_TYPE[2]) ||
(BYTE_LANES[3] && ~BYTE_GROUP_TYPE[3]) ) ? "TRUE" : "FALSE";
localparam INPUT_BANK = ((BYTE_LANES[0] && DATA_CTL_N[0]) ||
(BYTE_LANES[1] && DATA_CTL_N[1]) ||
(BYTE_LANES[2] && DATA_CTL_N[2]) ||
(BYTE_LANES[3] && DATA_CTL_N[3]) ) ? "TRUE" : "FALSE";
localparam PC_DATA_CTL_A = (MEMORY_TYPE == "RLD3" && DATA_CTL_A) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_B = (MEMORY_TYPE == "RLD3" && DATA_CTL_B) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_C = (MEMORY_TYPE == "RLD3" && DATA_CTL_C) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_D = (MEMORY_TYPE == "RLD3" && DATA_CTL_D) ? "FALSE" : "TRUE";
localparam MSB_BURST_PEND_PO = 3;
localparam MSB_BURST_PEND_PI = 7;
localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI+ 8;
localparam MSB_RANK_SEL_O = MSB_RANK_SEL_I + 8;
localparam MSB_DIV_RST = MSB_RANK_SEL_O + 1;
localparam MSB_PHASE_SELECT = MSB_DIV_RST + 1;
localparam MSB_BURST_PI = MSB_PHASE_SELECT + 4;
localparam PHASER_CTL_BUS_WIDTH = MSB_BURST_PI + 1;
localparam A_BYTE_GROUP_TYPE = ((BYTE_LANES[0] != 1) ? "DC" :
(INTERFACE_TYPE == "BIDIR") ?
((DATA_CTL_N[0] == 1) ? "BIDIR" : "OUT") :
(BYTE_GROUP_TYPE[0] == 1'b1)? "IN" : "OUT");
localparam B_BYTE_GROUP_TYPE = ((BYTE_LANES[1] != 1) ? "DC" :
(INTERFACE_TYPE == "BIDIR") ?
((DATA_CTL_N[1] == 1) ? "BIDIR" : "OUT"):
(BYTE_GROUP_TYPE[1] == 1'b1)? "IN" : "OUT");
localparam C_BYTE_GROUP_TYPE = ((BYTE_LANES[2] != 1) ? "DC" :
(INTERFACE_TYPE == "BIDIR") ?
((DATA_CTL_N[2] == 1) ? "BIDIR" : "OUT") :
(BYTE_GROUP_TYPE[2] == 1'b1)? "IN" : "OUT");
localparam D_BYTE_GROUP_TYPE = ((BYTE_LANES[3] != 1) ? "DC" :
(INTERFACE_TYPE == "BIDIR") ?
((DATA_CTL_N[3] == 1) ? "BIDIR" : "OUT") :
(BYTE_GROUP_TYPE[3] == 1'b1)? "IN" : "OUT");
wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;
wire [7:0] in_rank;
wire [7:0] out_rank;
wire [11:0] IO_A;
wire [11:0] IO_B;
wire [11:0] IO_C;
wire [11:0] IO_D;
wire [319:0] phy_din_remap;
reg A_po_counter_read_en;
wire [8:0] A_po_counter_read_val;
reg A_pi_counter_read_en;
wire [5:0] A_pi_counter_read_val;
wire A_pi_fine_overflow;
wire A_po_coarse_overflow;
wire A_po_fine_overflow;
reg A_pi_edge_adv;
reg A_pi_fine_enable;
reg A_pi_fine_inc;
reg A_pi_counter_load_en;
reg [5:0] A_pi_counter_load_val;
reg A_po_fine_enable;
reg A_po_edge_adv;
reg A_po_coarse_enable;
reg A_po_fine_inc;
reg A_po_sel_fine_oclk_delay;
reg A_po_coarse_inc;
reg A_po_counter_load_en;
reg [8:0] A_po_counter_load_val;
wire A_po_delay_done;
reg B_po_counter_read_en;
wire [8:0] B_po_counter_read_val;
reg B_pi_counter_read_en;
wire [5:0] B_pi_counter_read_val;
wire B_pi_fine_overflow;
wire B_po_coarse_overflow;
wire B_po_fine_overflow;
reg B_pi_edge_adv;
reg B_pi_fine_enable;
reg B_pi_fine_inc;
reg B_pi_counter_load_en;
reg [5:0] B_pi_counter_load_val;
wire B_po_delay_done;
reg B_po_fine_enable;
reg B_po_edge_adv;
reg B_po_coarse_enable;
reg B_po_fine_inc;
reg B_po_coarse_inc;
reg B_po_sel_fine_oclk_delay;
reg B_po_counter_load_en;
reg [8:0] B_po_counter_load_val;
reg C_pi_fine_inc;
reg D_pi_fine_inc;
reg C_pi_fine_enable;
reg D_pi_fine_enable;
reg C_pi_edge_adv;
reg D_pi_edge_adv;
reg C_po_counter_load_en;
reg D_po_counter_load_en;
reg C_po_coarse_inc;
reg D_po_coarse_inc;
reg C_po_fine_inc;
reg D_po_fine_inc;
reg C_po_sel_fine_oclk_delay;
reg D_po_sel_fine_oclk_delay;
reg [5:0] C_pi_counter_load_val;
reg [5:0] D_pi_counter_load_val;
reg [8:0] C_po_counter_load_val;
reg [8:0] D_po_counter_load_val;
reg C_po_edge_adv;
reg C_po_coarse_enable;
reg D_po_edge_adv;
reg D_po_coarse_enable;
reg C_po_fine_enable;
reg D_po_fine_enable;
wire C_po_coarse_overflow;
wire D_po_coarse_overflow;
wire C_po_fine_overflow;
wire D_po_fine_overflow;
wire [8:0] C_po_counter_read_val;
wire [8:0] D_po_counter_read_val;
reg C_po_counter_read_en;
reg D_po_counter_read_en;
wire C_pi_fine_overflow;
wire D_pi_fine_overflow;
reg C_pi_counter_read_en;
reg D_pi_counter_read_en;
reg C_pi_counter_load_en;
reg D_pi_counter_load_en;
wire [5:0] C_pi_counter_read_val;
wire [5:0] D_pi_counter_read_val;
wire C_po_delay_done;
wire D_po_delay_done;
wire A_if_empty;
wire B_if_empty;
wire C_if_empty;
wire D_if_empty;
wire A_if_a_empty;
wire B_if_a_empty;
wire C_if_a_empty;
wire D_if_a_empty;
wire A_if_full;
wire B_if_full;
wire C_if_full;
wire D_if_full;
//wire A_if_a_full;
//wire B_if_a_full;
//wire C_if_a_full;
//wire D_if_a_full;
wire A_of_empty;
wire B_of_empty;
wire C_of_empty;
wire D_of_empty;
wire A_of_full;
wire B_of_full;
wire C_of_full;
wire D_of_full;
wire A_of_ctl_full;
wire B_of_ctl_full;
wire C_of_ctl_full;
wire D_of_ctl_full;
wire A_of_data_full;
wire B_of_data_full;
wire C_of_data_full;
wire D_of_data_full;
wire A_of_a_full;
wire B_of_a_full;
wire C_of_a_full;
wire D_of_a_full;
wire A_of_ctl_a_full;
wire B_of_ctl_a_full;
wire C_of_ctl_a_full;
wire D_of_ctl_a_full;
wire A_of_data_a_full;
wire B_of_data_a_full;
wire C_of_data_a_full;
wire D_of_data_a_full;
reg A_cq_clk;
reg B_cq_clk;
reg C_cq_clk;
reg D_cq_clk;
reg A_cqn_clk;
reg B_cqn_clk;
reg C_cqn_clk;
reg D_cqn_clk;
wire [1:0] A_ddr_clk; // for generation
wire [1:0] B_ddr_clk; //
wire [1:0] C_ddr_clk; //
wire [1:0] D_ddr_clk; //
wire [1:0] cq_buf_clk;
wire [1:0] cqn_buf_clk;
wire [3:0] cq_clk;
wire [3:0] cqn_clk;
wire cq_capt_clk;
wire cqn_capt_clk;
wire [3:0] aux_out;
wire [1:0] phy_encalib;
wire dangling_outputs; // this reduces all constant 0 values to 1 signal
// which can be tied to an unused input. The purpose
// is to fake the tools into ignoring dangling outputs.
// Because it is anded with 1'b0, the contributing signals
// are folded as constants or trimmed.
assign dbg_phy_4lanes[3:0] = {D_if_empty, C_if_empty, B_if_empty, A_if_empty};
wire [255:0] A_dbg_byte_lane;
wire [255:0] B_dbg_byte_lane;
wire [255:0] C_dbg_byte_lane;
wire [255:0] D_dbg_byte_lane;
assign dbg_byte_lane = {D_dbg_byte_lane,
C_dbg_byte_lane,
B_dbg_byte_lane,
A_dbg_byte_lane};
assign dangling_outputs = (& idelay_cnt_in) & ( &phy_dout) ;
assign if_empty = A_if_empty | B_if_empty | C_if_empty | D_if_empty;
assign if_a_empty = A_if_a_empty & B_if_a_empty & C_if_a_empty & D_if_a_empty;
assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;
//assign if_a_full = A_if_a_full | B_if_a_full | C_if_a_full | D_if_a_full ;
assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;
assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;
assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;
assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;
assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full ;
assign po_delay_done = A_po_delay_done & B_po_delay_done & C_po_delay_done & D_po_delay_done;
function [47:0] part_select_48;
input [191:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_48[47:0] = vector[1*48-1:0*48];
2'b01 : part_select_48[47:0] = vector[2*48-1:1*48];
2'b10 : part_select_48[47:0] = vector[3*48-1:2*48];
2'b11 : part_select_48[47:0] = vector[4*48-1:3*48];
endcase
end
endfunction
function [79:0] part_select_80;
input [319:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];
2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];
2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];
2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];
endcase
end
endfunction
wire [319:0] phy_dout_remap;
assign ddr_clk = {D_ddr_clk, C_ddr_clk, B_ddr_clk, A_ddr_clk};
generate
if (~BYTE_LANES[0]) begin
assign A_of_ctl_full = 0;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = 0;
assign A_of_data_a_full = 0;
end else if (PRESENT_DATA_A) begin
assign A_of_data_full = A_of_full;
assign A_of_ctl_full = 0;
assign A_of_data_a_full = A_of_a_full;
assign A_of_ctl_a_full = 0;
end else begin
assign A_of_ctl_full = A_of_full;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = A_of_a_full;
assign A_of_data_a_full = 0;
end
if (~BYTE_LANES[1]) begin
assign B_of_ctl_full = 0;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = 0;
assign B_of_data_a_full = 0;
end else if (PRESENT_DATA_B) begin
assign B_of_data_full = B_of_full;
assign B_of_ctl_full = 0;
assign B_of_data_a_full = B_of_a_full;
assign B_of_ctl_a_full = 0;
end else begin
assign B_of_ctl_full = B_of_full;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = B_of_a_full;
assign B_of_data_a_full = 0;
end
if (~BYTE_LANES[2]) begin
assign C_of_ctl_full = 0;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = 0;
assign C_of_data_a_full = 0;
end else if (PRESENT_DATA_C) begin
assign C_of_data_full = C_of_full;
assign C_of_ctl_full = 0;
assign C_of_data_a_full = C_of_a_full;
assign C_of_ctl_a_full = 0;
end else begin
assign C_of_ctl_full = C_of_full;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = C_of_a_full;
assign C_of_data_a_full = 0;
end
if (~BYTE_LANES[3]) begin
assign D_of_ctl_full = 0;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = 0;
assign D_of_data_a_full = 0;
end else if (PRESENT_DATA_D) begin
assign D_of_data_full = D_of_full;
assign D_of_ctl_full = 0;
assign D_of_data_a_full = D_of_a_full;
assign D_of_ctl_a_full = 0;
end else begin
assign D_of_ctl_full = D_of_full;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = D_of_a_full;
assign D_of_data_a_full = 0;
end
// byte lane must exist and be data lane.
if (PRESENT_DATA_A )
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];
endcase
else
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_B )
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];
endcase
else
if (HIGHEST_LANE > 1)
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
// byte lane must exist and be data lane.
if (PRESENT_DATA_C)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];
endcase
else
if (HIGHEST_LANE > 2)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_D )
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];
endcase
else
if (HIGHEST_LANE > 3)
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
endgenerate
assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;
generate
if (OUTPUT_BANK == "TRUE" && BUFG_FOR_OUTPUTS == "OFF") begin : PHY_CONTROL_INST
`ifdef FUJI_BLH
B_PHY_CONTROL #(
`else
PHY_CONTROL #(
`endif
//B_PHY_CONTROL #(
.AO_WRLVL_EN ( PC_AO_WRLVL_EN),
.AO_TOGGLE ( PC_AO_TOGGLE),
.BURST_MODE ( PC_BURST_MODE),
.CO_DURATION ( PC_CO_DURATION ),
.CLK_RATIO ( PC_CLK_RATIO),
.DATA_CTL_A_N ( PC_DATA_CTL_A),
.DATA_CTL_B_N ( PC_DATA_CTL_B),
.DATA_CTL_C_N ( PC_DATA_CTL_C),
.DATA_CTL_D_N ( PC_DATA_CTL_D),
.DI_DURATION ( PC_DI_DURATION ),
.DO_DURATION ( PC_DO_DURATION ),
.EVENTS_DELAY ( PC_EVENTS_DELAY),
.FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),
.MULTI_REGION ( PC_MULTI_REGION ),
.PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),
.DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),
.SYNC_MODE ( PC_SYNC_MODE),
.CMD_OFFSET ( PC_CMD_OFFSET),
.RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),
.RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),
.RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),
.RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),
.RD_DURATION_0 ( PC_RD_DURATION_0),
.RD_DURATION_1 ( PC_RD_DURATION_1),
.RD_DURATION_2 ( PC_RD_DURATION_2),
.RD_DURATION_3 ( PC_RD_DURATION_3),
.WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),
.WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),
.WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),
.WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),
.WR_DURATION_0 ( PC_WR_DURATION_0),
.WR_DURATION_1 ( PC_WR_DURATION_1),
.WR_DURATION_2 ( PC_WR_DURATION_2),
.WR_DURATION_3 ( PC_WR_DURATION_3)
) phy_control_i (
.AUXOUTPUT (aux_out),
//`ifdef DEDICATED_ROUTES
.INBURSTPENDING (),
.INRANKA (),
.INRANKB (),
.INRANKC (),
.INRANKD (),
// .OUTBURSTPENDING (),
// .PCENABLECALIB (),
//`else
// .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),
// .INRANKA (in_rank[1:0]),
// .INRANKB (in_rank[3:2]),
// .INRANKC (in_rank[5:4]),
// .INRANKD (in_rank[7:6]),
.OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),
.PCENABLECALIB (phy_encalib),
//`endif
.PHYCTLALMOSTFULL (phy_ctl_a_full),
.PHYCTLFULL (phy_ctl_full),
.PHYCTLEMPTY (phy_ctl_empty),
.PHYCTLREADY (phy_ctl_ready),
.MEMREFCLK (mem_refclk),
.PHYCLK (phy_ctl_clk),
.PHYCTLMSTREMPTY (phy_ctl_mstr_empty),
.PHYCTLWD (phy_ctl_wd),
.PHYCTLWRENABLE (phy_ctl_wr),
.PLLLOCK (pll_lock),
.REFDLLLOCK (ref_dll_lock),
.RESET (rst),
.SYNCIN (sync_pulse),
.READCALIBENABLE (phy_read_calib),
.WRITECALIBENABLE (phy_write_calib)
);
end else begin : NO_PHY_CONTROL_INST
assign phaser_ctl_bus = 'b0;
assign phy_ctl_full = 1'b0;
assign phy_ctl_a_full = 1'b0;
assign phy_ctl_ready = ~rst;//1'b1;
assign phy_ctl_empty = 1'b0;
end
endgenerate
//obligatory phaser-ref
//GENERATE statement commented out to avoid a change in the UCF for placing the
//PHASER_REF for non-BUFG interfaces (which is most of them).
//To use the BUFG scheme for outputs this will need to be uncommented
//generate
// if (BUFG_FOR_OUTPUTS == "OFF" ||
// (BUFG_FOR_OUTPUTS == "ON" && INPUT_BANK == "TRUE")) begin : PHASER_REF_INST
PHASER_REF phaser_ref_i(
.LOCKED (ref_dll_lock),
.CLKIN (freq_refclk),
.PWRDWN (1'b0),
.RST (rst_phaser_ref)
);
// end else begin : GEN_NO_PHASER_REF
// assign ref_dll_lock = 1'b1;
// end
//endgenerate
generate
if ( BYTE_LANES[0] ) begin : qdr_rld_byte_lane_A
assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));
mig_7series_v2_0_qdr_rld_byte_lane#(
.ABCD ("A"),
.SIMULATION (SIMULATION),
.PO_COARSE_BYPASS (PO_COARSE_BYPASS),
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY),
.PRE_FIFO (PRE_FIFO),
.BITLANES_IN (BITLANES_IN[11:0]),
.BITLANES_OUT (BITLANES_OUT[11:0]),
.CK_P_OUT (CK_P_OUT[11:0]),
.MEMORY_TYPE (MEMORY_TYPE),
.DATA_CTL_N (DATA_CTL_N[0]),
.GENERATE_DDR_CK (GENERATE_DDR_CK[0]),
.GENERATE_DDR_DK (GENERATE_DDR_DK[0]),
.DIFF_CK (DIFF_CK),
.DIFF_DK (DIFF_DK),
.CK_VALUE_D1 (CK_VALUE_D1),
.DK_VALUE_D1 (DK_VALUE_D1),
.IODELAY_GRP (IODELAY_GRP),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.BYTE_GROUP_TYPE (A_BYTE_GROUP_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.BUFG_FOR_OUTPUTS (BUFG_FOR_OUTPUTS),
.CLK_PERIOD (CLK_PERIOD),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (A_PI_FINE_DELAY),
.PI_REFCLK_PERIOD (A_PI_REFCLK_PERIOD),
.MEMREFCLK_PERIOD (MEMREFCLK_PERIOD),
.PO_FINE_DELAY (PO_FINE_DELAY),
.PO_FINE_SKEW_DELAY (A_PO_FINE_DELAY),
.PO_COARSE_SKEW_DELAY (A_PO_COARSE_DELAY),
.PO_OCLK_DELAY (A_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),
.PO_REFCLK_PERIOD (A_PO_REFCLK_PERIOD),
.PHASER_CTL_BUS_WIDTH (PHASER_CTL_BUS_WIDTH),
.TCQ (TCQ)
)
qdr_rld_byte_lane_A(
.O ( O[11:0]),
.I ( I[11:0]),
.mem_dq_ts ( mem_dq_ts[11:0]),
.rst (rst),
.phy_clk (phy_clk),
.phy_clk_fast (phy_clk_fast),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.sync_pulse (sync_pulse),
.sys_rst (sys_rst),
.rst_rd_clk (rst_rd_clk),
.cq_buf_clk (A_cq_clk),
.cqn_buf_clk (A_cqn_clk),
.ddr_ck_out (A_ddr_clk),
.if_a_empty (A_if_a_empty),
.if_empty (A_if_empty),
.if_a_full (),
.if_full (A_if_full),
.of_a_empty (),
.of_empty (A_of_empty),
.of_a_full (A_of_a_full),
.of_full (A_of_full),
.out_fifos_full (out_fifos_full ),
.phy_din (phy_din_remap[79:0]),
.phy_dout (phy_dout_remap[79:0]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce[(1*12)-1:(12)*0]),
.idelay_inc (idelay_inc[(1*12)-1:(12)*0]),
.idelay_cnt_in (idelay_cnt_in[12*5-1:0]),
.idelay_cnt_out (idelay_cnt_out[12*5-1:0]),
.po_edge_adv (A_po_edge_adv),
.po_fine_enable (A_po_fine_enable),
.po_coarse_enable (A_po_coarse_enable),
.po_fine_inc (A_po_fine_inc),
.po_coarse_inc (A_po_coarse_inc),
.po_counter_load_en (A_po_counter_load_en),
.po_counter_read_en (A_po_counter_read_en),
.po_counter_load_val (A_po_counter_load_val),
.po_coarse_overflow (A_po_coarse_overflow),
.po_fine_overflow (A_po_fine_overflow),
.po_counter_read_val (A_po_counter_read_val),
.po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),
.pi_edge_adv (A_pi_edge_adv),
.pi_fine_enable (A_pi_fine_enable),
.pi_fine_inc (A_pi_fine_inc),
.pi_counter_load_en (A_pi_counter_load_en),
.pi_counter_read_en (A_pi_counter_read_en),
.pi_counter_load_val (A_pi_counter_load_val),
.pi_fine_overflow (A_pi_fine_overflow),
.pi_counter_read_val (A_pi_counter_read_val),
.po_delay_done (A_po_delay_done),
.po_dec_done (po_dec_done),
.po_inc_done (po_inc_done),
.dbg_byte_lane (A_dbg_byte_lane)
);
end
else begin : no_byte_lane_A
assign A_of_a_full = 1'b0;
assign A_of_full = 1'b0;
assign A_if_full = 1'b0;
assign A_if_empty = 0;
assign A_po_delay_done = 1;
assign O[11:0] = 0;
end
if ( BYTE_LANES[1] ) begin : qdr_rld_byte_lane_B
assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));
mig_7series_v2_0_qdr_rld_byte_lane#(
.ABCD ("B"),
.SIMULATION (SIMULATION),
.PO_COARSE_BYPASS (PO_COARSE_BYPASS),
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY),
.PRE_FIFO (PRE_FIFO),
.BITLANES_IN (BITLANES_IN[23:12]),
.BITLANES_OUT (BITLANES_OUT[23:12]),
.CK_P_OUT (CK_P_OUT[23:12]),
.MEMORY_TYPE (MEMORY_TYPE),
.BYTE_GROUP_TYPE (B_BYTE_GROUP_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.BUFG_FOR_OUTPUTS (BUFG_FOR_OUTPUTS),
.CLK_PERIOD (CLK_PERIOD),
.PC_CLK_RATIO (PC_CLK_RATIO),
.IODELAY_GRP (IODELAY_GRP),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.DATA_CTL_N (DATA_CTL_N[1]),
.GENERATE_DDR_CK (GENERATE_DDR_CK[1]),
.GENERATE_DDR_DK (GENERATE_DDR_DK[1]),
.DIFF_CK (DIFF_CK),
.DIFF_DK (DIFF_DK),
.CK_VALUE_D1 (CK_VALUE_D1),
.DK_VALUE_D1 (DK_VALUE_D1),
.PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (B_PI_FINE_DELAY),
.PI_REFCLK_PERIOD (B_PI_REFCLK_PERIOD),
.MEMREFCLK_PERIOD (MEMREFCLK_PERIOD),
.PO_FINE_DELAY (PO_FINE_DELAY),
.PO_FINE_SKEW_DELAY (B_PO_FINE_DELAY),
.PO_COARSE_SKEW_DELAY (B_PO_COARSE_DELAY),
.PO_OCLK_DELAY (B_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),
.PO_REFCLK_PERIOD (B_PO_REFCLK_PERIOD),
.PHASER_CTL_BUS_WIDTH (PHASER_CTL_BUS_WIDTH),
.TCQ (TCQ)
)
qdr_rld_byte_lane_B(
.O ( O[23:12]),
.I ( I[23:12]),
.mem_dq_ts ( mem_dq_ts[23:12]),
.rst (rst),
.phy_clk (phy_clk),
.phy_clk_fast (phy_clk_fast),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.sync_pulse (sync_pulse),
.sys_rst (sys_rst),
.rst_rd_clk (rst_rd_clk),
.cq_buf_clk (B_cq_clk),
.cqn_buf_clk (B_cqn_clk),
.ddr_ck_out (B_ddr_clk),
.if_a_empty (B_if_a_empty),
.if_empty (B_if_empty),
.if_a_full (),
.if_full (B_if_full),
.of_a_empty (),
.of_empty (B_of_empty),
.of_a_full (B_of_a_full),
.of_full (B_of_full),
.out_fifos_full (out_fifos_full ),
.phy_din (phy_din_remap[159:80]),
.phy_dout (phy_dout_remap[159:80]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce[(2*12)-1:(12)*1]),
.idelay_inc (idelay_inc[(2*12)-1:(12)*1]),
.idelay_cnt_in (idelay_cnt_in[24*5-1:12*5]),
.idelay_cnt_out (idelay_cnt_out[24*5-1:12*5]),
.po_edge_adv (B_po_edge_adv),
.po_fine_enable (B_po_fine_enable),
.po_coarse_enable (B_po_coarse_enable),
.po_fine_inc (B_po_fine_inc),
.po_coarse_inc (B_po_coarse_inc),
.po_counter_load_en (B_po_counter_load_en),
.po_counter_read_en (B_po_counter_read_en),
.po_counter_load_val (B_po_counter_load_val),
.po_coarse_overflow (B_po_coarse_overflow),
.po_fine_overflow (B_po_fine_overflow),
.po_counter_read_val (B_po_counter_read_val),
.po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),
.pi_edge_adv (B_pi_edge_adv),
.pi_fine_enable (B_pi_fine_enable),
.pi_fine_inc (B_pi_fine_inc),
.pi_counter_load_en (B_pi_counter_load_en),
.pi_counter_read_en (B_pi_counter_read_en),
.pi_counter_load_val (B_pi_counter_load_val),
.pi_fine_overflow (B_pi_fine_overflow),
.pi_counter_read_val (B_pi_counter_read_val),
.po_delay_done (B_po_delay_done),
.po_dec_done (po_dec_done),
.po_inc_done (po_inc_done),
.dbg_byte_lane (B_dbg_byte_lane)
);
end
else begin : no_byte_lane_B
assign B_of_a_full = 1'b0;
assign B_of_full = 1'b0;
assign B_if_full = 1'b0;
assign B_if_empty = 0;
assign B_po_delay_done = 1;
if ( HIGHEST_LANE > 1) begin
assign O[23:12] = 0;
end
end
if ( BYTE_LANES[2] ) begin : qdr_rld_byte_lane_C
assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));
mig_7series_v2_0_qdr_rld_byte_lane#(
.ABCD ("C"),
.SIMULATION (SIMULATION),
.PO_COARSE_BYPASS (PO_COARSE_BYPASS),
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY),
.PRE_FIFO (PRE_FIFO),
.BITLANES_IN (BITLANES_IN[35:24]),
.BITLANES_OUT (BITLANES_OUT[35:24]),
.CK_P_OUT (CK_P_OUT[35:24]),
.MEMORY_TYPE (MEMORY_TYPE),
.BYTE_GROUP_TYPE (C_BYTE_GROUP_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.BUFG_FOR_OUTPUTS (BUFG_FOR_OUTPUTS),
.CLK_PERIOD (CLK_PERIOD),
.PC_CLK_RATIO (PC_CLK_RATIO),
.IODELAY_GRP (IODELAY_GRP),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.DATA_CTL_N (DATA_CTL_N[2]),
.GENERATE_DDR_CK (GENERATE_DDR_CK[2]),
.GENERATE_DDR_DK (GENERATE_DDR_DK[2]),
.DIFF_CK (DIFF_CK),
.DIFF_DK (DIFF_DK),
.CK_VALUE_D1 (CK_VALUE_D1),
.DK_VALUE_D1 (DK_VALUE_D1),
.PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (C_PI_FINE_DELAY),
.PI_REFCLK_PERIOD (C_PI_REFCLK_PERIOD),
.MEMREFCLK_PERIOD (MEMREFCLK_PERIOD),
.PO_FINE_DELAY (PO_FINE_DELAY),
.PO_FINE_SKEW_DELAY (C_PO_FINE_DELAY),
.PO_COARSE_SKEW_DELAY (C_PO_COARSE_DELAY),
.PO_OCLK_DELAY (C_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),
.PO_REFCLK_PERIOD (C_PO_REFCLK_PERIOD),
.PHASER_CTL_BUS_WIDTH (PHASER_CTL_BUS_WIDTH),
.TCQ (TCQ)
)
qdr_rld_byte_lane_C(
.O ( O[35:24]),
.I ( I[35:24]),
.mem_dq_ts ( mem_dq_ts[35:24]),
.rst (rst),
.phy_clk (phy_clk),
.phy_clk_fast (phy_clk_fast),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.sync_pulse (sync_pulse),
.sys_rst (sys_rst),
.rst_rd_clk (rst_rd_clk),
.cq_buf_clk (C_cq_clk),
.cqn_buf_clk (C_cqn_clk),
.ddr_ck_out (C_ddr_clk),
.if_a_empty (C_if_a_empty),
.if_empty (C_if_empty),
.if_a_full (),
.if_full (C_if_full),
.of_a_empty (),
.of_empty (C_of_empty),
.of_a_full (C_of_a_full),
.of_full (C_of_full),
.out_fifos_full (out_fifos_full ),
.phy_din (phy_din_remap[239:160]),
.phy_dout (phy_dout_remap[239:160]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce[(3*12)-1:(12)*2]),
.idelay_inc (idelay_inc[(3*12)-1:(12)*2]),
.idelay_cnt_in (idelay_cnt_in[36*5-1:24*5]),
.idelay_cnt_out (idelay_cnt_out[36*5-1:24*5]),
.po_edge_adv (C_po_edge_adv),
.po_fine_enable (C_po_fine_enable),
.po_coarse_enable (C_po_coarse_enable),
.po_fine_inc (C_po_fine_inc),
.po_coarse_inc (C_po_coarse_inc),
.po_counter_load_en (C_po_counter_load_en),
.po_counter_read_en (C_po_counter_read_en),
.po_counter_load_val (C_po_counter_load_val),
.po_coarse_overflow (C_po_coarse_overflow),
.po_fine_overflow (C_po_fine_overflow),
.po_counter_read_val (C_po_counter_read_val),
.po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),
.pi_edge_adv (C_pi_edge_adv),
.pi_fine_enable (C_pi_fine_enable),
.pi_fine_inc (C_pi_fine_inc),
.pi_counter_load_en (C_pi_counter_load_en),
.pi_counter_read_en (C_pi_counter_read_en),
.pi_counter_load_val (C_pi_counter_load_val),
.pi_fine_overflow (C_pi_fine_overflow),
.pi_counter_read_val (C_pi_counter_read_val),
.po_delay_done (C_po_delay_done),
.po_dec_done (po_dec_done),
.po_inc_done (po_inc_done),
.dbg_byte_lane (C_dbg_byte_lane)
);
end
else begin : no_byte_lane_C
assign C_of_a_full = 1'b0;
assign C_of_full = 1'b0;
assign C_if_full = 1'b0;
assign C_if_empty = 0;
assign C_po_delay_done = 1;
if ( HIGHEST_LANE > 2) begin
assign O[35:24] = 0;
end
end
if ( BYTE_LANES[3] ) begin : qdr_rld_byte_lane_D
assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));
mig_7series_v2_0_qdr_rld_byte_lane#(
.ABCD ("D"),
.SIMULATION (SIMULATION),
.PO_COARSE_BYPASS (PO_COARSE_BYPASS),
.CPT_CLK_CQ_ONLY (CPT_CLK_CQ_ONLY),
.PRE_FIFO (PRE_FIFO),
.BITLANES_IN (BITLANES_IN[47:36]),
.BITLANES_OUT (BITLANES_OUT[47:36]),
.CK_P_OUT (CK_P_OUT[47:36]),
.MEMORY_TYPE (MEMORY_TYPE),
.BYTE_GROUP_TYPE (D_BYTE_GROUP_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.BUFG_FOR_OUTPUTS (BUFG_FOR_OUTPUTS),
.CLK_PERIOD (CLK_PERIOD),
.PC_CLK_RATIO (PC_CLK_RATIO),
.IODELAY_GRP (IODELAY_GRP),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.DATA_CTL_N (DATA_CTL_N[3]),
.GENERATE_DDR_CK (GENERATE_DDR_CK[3]),
.GENERATE_DDR_DK (GENERATE_DDR_DK[3]),
.DIFF_CK (DIFF_CK),
.DIFF_DK (DIFF_DK),
.CK_VALUE_D1 (CK_VALUE_D1),
.DK_VALUE_D1 (DK_VALUE_D1),
.PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (D_PI_FINE_DELAY),
.PI_REFCLK_PERIOD (D_PI_REFCLK_PERIOD),
.MEMREFCLK_PERIOD (MEMREFCLK_PERIOD),
.PO_FINE_DELAY (PO_FINE_DELAY),
.PO_FINE_SKEW_DELAY (D_PO_FINE_DELAY),
.PO_COARSE_SKEW_DELAY (D_PO_COARSE_DELAY),
.PO_OCLK_DELAY (D_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),
.PO_REFCLK_PERIOD (D_PO_REFCLK_PERIOD),
.PHASER_CTL_BUS_WIDTH (PHASER_CTL_BUS_WIDTH),
.TCQ (TCQ)
)
qdr_rld_byte_lane_D(
.O ( O[47:36]),
.I ( I[47:36]),
.mem_dq_ts ( mem_dq_ts[47:36]),
.rst (rst),
.phy_clk (phy_clk),
.phy_clk_fast (phy_clk_fast),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.sync_pulse (sync_pulse),
.sys_rst (sys_rst),
.rst_rd_clk (rst_rd_clk),
.cq_buf_clk (D_cq_clk),
.cqn_buf_clk (D_cqn_clk),
.ddr_ck_out (D_ddr_clk),
.if_a_empty (D_if_a_empty),
.if_empty (D_if_empty),
.if_a_full (),
.if_full (D_if_full),
.of_a_empty (),
.of_empty (D_of_empty),
.of_a_full (D_of_a_full),
.of_full (D_of_full),
.out_fifos_full (out_fifos_full),
.phy_din (phy_din_remap[319:240]),
.phy_dout (phy_dout_remap[319:240]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce[(4*12)-1:(12)*3]),
.idelay_inc (idelay_inc[(4*12)-1:(12)*3]),
.idelay_cnt_in (idelay_cnt_in[48*5-1:36*5]),
.idelay_cnt_out (idelay_cnt_out[48*5-1:36*5]),
.po_edge_adv (D_po_edge_adv),
.po_fine_enable (D_po_fine_enable),
.po_coarse_enable (D_po_coarse_enable),
.po_fine_inc (D_po_fine_inc),
.po_coarse_inc (D_po_coarse_inc),
.po_counter_load_en (D_po_counter_load_en),
.po_counter_read_en (D_po_counter_read_en),
.po_counter_load_val (D_po_counter_load_val),
.po_coarse_overflow (D_po_coarse_overflow),
.po_fine_overflow (D_po_fine_overflow),
.po_counter_read_val (D_po_counter_read_val),
.po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),
.pi_edge_adv (D_pi_edge_adv),
.pi_fine_enable (D_pi_fine_enable),
.pi_fine_inc (D_pi_fine_inc),
.pi_counter_load_en (D_pi_counter_load_en),
.pi_counter_read_en (D_pi_counter_read_en),
.pi_counter_load_val (D_pi_counter_load_val),
.pi_fine_overflow (D_pi_fine_overflow),
.pi_counter_read_val (D_pi_counter_read_val),
.po_delay_done (D_po_delay_done),
.po_dec_done (po_dec_done),
.po_inc_done (po_inc_done),
.dbg_byte_lane (D_dbg_byte_lane)
);
end
else begin : no_byte_lane_D
assign D_of_a_full = 1'b0;
assign D_of_full = 1'b0;
assign D_if_full = 1'b0;
assign D_if_empty = 0;
assign D_po_delay_done = 1;
if ( HIGHEST_LANE > 3) begin
assign O[47:36] = 0;
end
end
endgenerate
// register outputs to give extra slack in timing
always @(posedge phy_clk) begin
case (calib_sel[1:0])
2'h0: begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val <= #1 A_pi_counter_read_val;
end
2'h1: begin
po_coarse_overflow <= #1 B_po_coarse_overflow;
po_fine_overflow <= #1 B_po_fine_overflow;
po_counter_read_val <= #1 B_po_counter_read_val;
pi_fine_overflow <= #1 B_pi_fine_overflow;
pi_counter_read_val <= #1 B_pi_counter_read_val;
end
2'h2: begin
po_coarse_overflow <= #1 C_po_coarse_overflow;
po_fine_overflow <= #1 C_po_fine_overflow;
po_counter_read_val <= #1 C_po_counter_read_val;
pi_fine_overflow <= #1 C_pi_fine_overflow;
pi_counter_read_val <= #1 C_pi_counter_read_val;
end
2'h3: begin
po_coarse_overflow <= #1 D_po_coarse_overflow;
po_fine_overflow <= #1 D_po_fine_overflow;
po_counter_read_val <= #1 D_po_counter_read_val;
pi_fine_overflow <= #1 D_pi_fine_overflow;
pi_counter_read_val <= #1 D_pi_counter_read_val;
end
default: begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val <= #1 A_pi_counter_read_val;
end
endcase
end
always @(posedge phy_clk) begin
if ( calib_sel[2]) begin
A_pi_fine_enable <= #TCQ 0;
A_pi_edge_adv <= #TCQ 0;
A_pi_fine_inc <= #TCQ 0;
A_pi_counter_load_en <= #TCQ 0;
A_pi_counter_read_en <= #TCQ 0;
A_pi_counter_load_val <= #TCQ 0;
A_po_fine_enable <= #TCQ 0;
A_po_edge_adv <= #TCQ 0;
A_po_coarse_enable <= #TCQ 0;
A_po_fine_inc <= #TCQ 0;
A_po_coarse_inc <= #TCQ 0;
A_po_counter_load_en <= #TCQ 0;
A_po_counter_read_en <= #TCQ 0;
A_po_counter_load_val <= #TCQ 0;
A_po_sel_fine_oclk_delay <= #TCQ 0;
B_pi_fine_enable <= #TCQ 0;
B_pi_edge_adv <= #TCQ 0;
B_pi_fine_inc <= #TCQ 0;
B_pi_counter_load_en <= #TCQ 0;
B_pi_counter_read_en <= #TCQ 0;
B_pi_counter_load_val <= #TCQ 0;
B_po_fine_enable <= #TCQ 0;
B_po_edge_adv <= #TCQ 0;
B_po_coarse_enable <= #TCQ 0;
B_po_fine_inc <= #TCQ 0;
B_po_coarse_inc <= #TCQ 0;
B_po_counter_load_en <= #TCQ 0;
B_po_counter_read_en <= #TCQ 0;
B_po_counter_load_val <= #TCQ 0;
B_po_sel_fine_oclk_delay <= #TCQ 0;
C_pi_fine_enable <= #TCQ 0;
C_pi_edge_adv <= #TCQ 0;
C_pi_fine_inc <= #TCQ 0;
C_pi_counter_load_en <= #TCQ 0;
C_pi_counter_read_en <= #TCQ 0;
C_pi_counter_load_val <= #TCQ 0;
C_po_fine_enable <= #TCQ 0;
C_po_edge_adv <= #TCQ 0;
C_po_coarse_enable <= #TCQ 0;
C_po_fine_inc <= #TCQ 0;
C_po_coarse_inc <= #TCQ 0;
C_po_counter_load_en <= #TCQ 0;
C_po_counter_read_en <= #TCQ 0;
C_po_counter_load_val <= #TCQ 0;
C_po_sel_fine_oclk_delay <= #TCQ 0;
D_pi_fine_enable <= #TCQ 0;
D_pi_edge_adv <= #TCQ 0;
D_pi_fine_inc <= #TCQ 0;
D_pi_counter_load_en <= #TCQ 0;
D_pi_counter_read_en <= #TCQ 0;
D_pi_counter_load_val <= #TCQ 0;
D_po_fine_enable <= #TCQ 0;
D_po_edge_adv <= #TCQ 0;
D_po_coarse_enable <= #TCQ 0;
D_po_fine_inc <= #TCQ 0;
D_po_coarse_inc <= #TCQ 0;
D_po_counter_load_en <= #TCQ 0;
D_po_counter_read_en <= #TCQ 0;
D_po_counter_load_val <= #TCQ 0;
D_po_sel_fine_oclk_delay <= #TCQ 0;
end else
if (calib_in_common) begin
if (drive_on_calib_in_common[0] == 1) begin
A_pi_fine_enable <= #TCQ pi_fine_enable;
A_pi_edge_adv <= #TCQ pi_edge_adv;
A_pi_fine_inc <= #TCQ pi_fine_inc;
A_pi_counter_load_en <= #TCQ pi_counter_load_en;
A_pi_counter_read_en <= #TCQ pi_counter_read_en;
A_pi_counter_load_val <= #TCQ pi_counter_load_val;
A_po_fine_enable <= #TCQ po_fine_enable;
A_po_edge_adv <= #TCQ po_edge_adv;
A_po_coarse_enable <= #TCQ po_coarse_enable;
A_po_fine_inc <= #TCQ po_fine_inc;
A_po_coarse_inc <= #TCQ po_coarse_inc;
A_po_counter_load_en <= #TCQ po_counter_load_en;
A_po_counter_read_en <= #TCQ po_counter_read_en;
A_po_counter_load_val <= #TCQ po_counter_load_val;
A_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
if (drive_on_calib_in_common[1] == 1) begin
B_pi_fine_enable <= #TCQ pi_fine_enable;
B_pi_edge_adv <= #TCQ pi_edge_adv;
B_pi_fine_inc <= #TCQ pi_fine_inc;
B_pi_counter_load_en <= #TCQ pi_counter_load_en;
B_pi_counter_read_en <= #TCQ pi_counter_read_en;
B_pi_counter_load_val <= #TCQ pi_counter_load_val;
B_po_fine_enable <= #TCQ po_fine_enable;
B_po_edge_adv <= #TCQ po_edge_adv;
B_po_coarse_enable <= #TCQ po_coarse_enable;
B_po_fine_inc <= #TCQ po_fine_inc;
B_po_coarse_inc <= #TCQ po_coarse_inc;
B_po_counter_load_en <= #TCQ po_counter_load_en;
B_po_counter_read_en <= #TCQ po_counter_read_en;
B_po_counter_load_val <= #TCQ po_counter_load_val;
B_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
if (drive_on_calib_in_common[2] == 1) begin
C_pi_fine_enable <= #TCQ pi_fine_enable;
C_pi_edge_adv <= #TCQ pi_edge_adv;
C_pi_fine_inc <= #TCQ pi_fine_inc;
C_pi_counter_load_en <= #TCQ pi_counter_load_en;
C_pi_counter_read_en <= #TCQ pi_counter_read_en;
C_pi_counter_load_val <= #TCQ pi_counter_load_val;
C_po_fine_enable <= #TCQ po_fine_enable;
C_po_edge_adv <= #TCQ po_edge_adv;
C_po_coarse_enable <= #TCQ po_coarse_enable;
C_po_fine_inc <= #TCQ po_fine_inc;
C_po_coarse_inc <= #TCQ po_coarse_inc;
C_po_counter_load_en <= #TCQ po_counter_load_en;
C_po_counter_read_en <= #TCQ po_counter_read_en;
C_po_counter_load_val <= #TCQ po_counter_load_val;
C_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
if (drive_on_calib_in_common[3] == 1) begin
D_pi_fine_enable <= #TCQ pi_fine_enable;
D_pi_edge_adv <= #TCQ pi_edge_adv;
D_pi_fine_inc <= #TCQ pi_fine_inc;
D_pi_counter_load_en <= #TCQ pi_counter_load_en;
D_pi_counter_read_en <= #TCQ pi_counter_read_en;
D_pi_counter_load_val <= #TCQ pi_counter_load_val;
D_po_fine_enable <= #TCQ po_fine_enable;
D_po_edge_adv <= #TCQ po_edge_adv;
D_po_coarse_enable <= #TCQ po_coarse_enable;
D_po_fine_inc <= #TCQ po_fine_inc;
D_po_coarse_inc <= #TCQ po_coarse_inc;
D_po_counter_load_en <= #TCQ po_counter_load_en;
D_po_counter_read_en <= #TCQ po_counter_read_en;
D_po_counter_load_val <= #TCQ po_counter_load_val;
D_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
end
else begin
// otherwise, only a single phaser is selected
A_pi_fine_enable <= #TCQ 0;
A_pi_edge_adv <= #TCQ 0;
A_pi_fine_inc <= #TCQ 0;
A_pi_counter_load_en <= #TCQ 0;
A_pi_counter_read_en <= #TCQ 0;
A_pi_counter_load_val <= #TCQ 0;
A_po_fine_enable <= #TCQ 0;
A_po_edge_adv <= #TCQ 0;
A_po_coarse_enable <= #TCQ 0;
A_po_fine_inc <= #TCQ 0;
A_po_coarse_inc <= #TCQ 0;
A_po_counter_load_en <= #TCQ 0;
A_po_counter_read_en <= #TCQ 0;
A_po_counter_load_val <= #TCQ 0;
A_po_sel_fine_oclk_delay <= #TCQ 0;
B_pi_fine_enable <= #TCQ 0;
B_pi_edge_adv <= #TCQ 0;
B_pi_fine_inc <= #TCQ 0;
B_pi_counter_load_en <= #TCQ 0;
B_pi_counter_read_en <= #TCQ 0;
B_pi_counter_load_val <= #TCQ 0;
B_po_fine_enable <= #TCQ 0;
B_po_edge_adv <= #TCQ 0;
B_po_coarse_enable <= #TCQ 0;
B_po_fine_inc <= #TCQ 0;
B_po_coarse_inc <= #TCQ 0;
B_po_counter_load_en <= #TCQ 0;
B_po_counter_read_en <= #TCQ 0;
B_po_counter_load_val <= #TCQ 0;
B_po_sel_fine_oclk_delay <= #TCQ 0;
C_pi_fine_enable <= #TCQ 0;
C_pi_edge_adv <= #TCQ 0;
C_pi_fine_inc <= #TCQ 0;
C_pi_counter_load_en <= #TCQ 0;
C_pi_counter_read_en <= #TCQ 0;
C_pi_counter_load_val <= #TCQ 0;
C_po_fine_enable <= #TCQ 0;
C_po_edge_adv <= #TCQ 0;
C_po_coarse_enable <= #TCQ 0;
C_po_fine_inc <= #TCQ 0;
C_po_coarse_inc <= #TCQ 0;
C_po_counter_load_en <= #TCQ 0;
C_po_counter_read_en <= #TCQ 0;
C_po_counter_load_val <= #TCQ 0;
C_po_sel_fine_oclk_delay <= #TCQ 0;
D_pi_fine_enable <= #TCQ 0;
D_pi_edge_adv <= #TCQ 0;
D_pi_fine_inc <= #TCQ 0;
D_pi_counter_load_en <= #TCQ 0;
D_pi_counter_read_en <= #TCQ 0;
D_pi_counter_load_val <= #TCQ 0;
D_po_fine_enable <= #TCQ 0;
D_po_edge_adv <= #TCQ 0;
D_po_coarse_enable <= #TCQ 0;
D_po_fine_inc <= #TCQ 0;
D_po_coarse_inc <= #TCQ 0;
D_po_counter_load_en <= #TCQ 0;
D_po_counter_read_en <= #TCQ 0;
D_po_counter_load_val <= #TCQ 0;
D_po_sel_fine_oclk_delay <= #TCQ 0;
case (calib_sel[1:0])
0: begin
A_pi_fine_enable <= #TCQ pi_fine_enable;
A_pi_edge_adv <= #TCQ pi_edge_adv;
A_pi_fine_inc <= #TCQ pi_fine_inc;
A_pi_counter_load_en <= #TCQ pi_counter_load_en;
A_pi_counter_read_en <= #TCQ pi_counter_read_en;
A_pi_counter_load_val <= #TCQ pi_counter_load_val;
A_po_fine_enable <= #TCQ po_fine_enable;
A_po_edge_adv <= #TCQ po_edge_adv;
A_po_coarse_enable <= #TCQ po_coarse_enable;
A_po_fine_inc <= #TCQ po_fine_inc;
A_po_coarse_inc <= #TCQ po_coarse_inc;
A_po_counter_load_en <= #TCQ po_counter_load_en;
A_po_counter_read_en <= #TCQ po_counter_read_en;
A_po_counter_load_val <= #TCQ po_counter_load_val;
A_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
1: begin
B_pi_fine_enable <= #TCQ pi_fine_enable;
B_pi_edge_adv <= #TCQ pi_edge_adv;
B_pi_fine_inc <= #TCQ pi_fine_inc;
B_pi_counter_load_en <= #TCQ pi_counter_load_en;
B_pi_counter_read_en <= #TCQ pi_counter_read_en;
B_pi_counter_load_val <= #TCQ pi_counter_load_val;
B_po_fine_enable <= #TCQ po_fine_enable;
B_po_edge_adv <= #TCQ po_edge_adv;
B_po_coarse_enable <= #TCQ po_coarse_enable;
B_po_fine_inc <= #TCQ po_fine_inc;
B_po_coarse_inc <= #TCQ po_coarse_inc;
B_po_counter_load_en <= #TCQ po_counter_load_en;
B_po_counter_read_en <= #TCQ po_counter_read_en;
B_po_counter_load_val <= #TCQ po_counter_load_val;
B_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
2: begin
C_pi_fine_enable <= #TCQ pi_fine_enable;
C_pi_edge_adv <= #TCQ pi_edge_adv;
C_pi_fine_inc <= #TCQ pi_fine_inc;
C_pi_counter_load_en <= #TCQ pi_counter_load_en;
C_pi_counter_read_en <= #TCQ pi_counter_read_en;
C_pi_counter_load_val <= #TCQ pi_counter_load_val;
C_po_fine_enable <= #TCQ po_fine_enable;
C_po_edge_adv <= #TCQ po_edge_adv;
C_po_coarse_enable <= #TCQ po_coarse_enable;
C_po_fine_inc <= #TCQ po_fine_inc;
C_po_coarse_inc <= #TCQ po_coarse_inc;
C_po_counter_load_en <= #TCQ po_counter_load_en;
C_po_counter_read_en <= #TCQ po_counter_read_en;
C_po_counter_load_val <= #TCQ po_counter_load_val;
C_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
3: begin
D_pi_fine_enable <= #TCQ pi_fine_enable;
D_pi_edge_adv <= #TCQ pi_edge_adv;
D_pi_fine_inc <= #TCQ pi_fine_inc;
D_pi_counter_load_en <= #TCQ pi_counter_load_en;
D_pi_counter_read_en <= #TCQ pi_counter_read_en;
D_pi_counter_load_val <= #TCQ pi_counter_load_val;
D_po_fine_enable <= #TCQ po_fine_enable;
D_po_edge_adv <= #TCQ po_edge_adv;
D_po_coarse_enable <= #TCQ po_coarse_enable;
D_po_fine_inc <= #TCQ po_fine_inc;
D_po_coarse_inc <= #TCQ po_coarse_inc;
D_po_counter_load_en <= #TCQ po_counter_load_en;
D_po_counter_read_en <= #TCQ po_counter_read_en;
D_po_counter_load_val <= #TCQ po_counter_load_val;
D_po_sel_fine_oclk_delay <= #TCQ po_sel_fine_oclk_delay;
end
endcase
end
end
//For QDR2+ since there is only one clock we use both BUFMR locations
//Hence, even if we only specify one location we generate both in that case
generate
genvar i;
if (DIFF_CQ == 1) begin: gen_ibufds_cq //Differential Read Clock
assign cqn_buf_clk = 'b0; //tie-off unused signal
if (MEMORY_TYPE == "RLD3") begin : gen_ibufds_cq_rld3
for (i = 0; i < 4; i = i + 1) begin
if (GENERATE_CQ[i]==1) begin
IBUFDS u_bufds_cq ( .I (Q_clk[i]),
.IB (Qn_clk[i]),
.O (cq_clk[i]) //cq_buf_clk[i]
);
assign cqn_clk[i] = ~cq_clk[i];
end //end of if
end //end of for
end else begin
//BUFMR instances
if (GENERATE_CQ[1]==1) begin
IBUFDS bufds_cq_1 ( .I (Q_clk[1]),
.IB (Qn_clk[1]),
.O (cq_buf_clk[0])
);
BUFMR bufmr_cq_1 ( .O(cq_clk[0]), .I(cq_buf_clk[0]) );
assign cqn_clk[0] = ~cq_clk[0];
end //end of if
if (GENERATE_CQ[2]==1) begin
IBUFDS bufds_cq_2 ( .I (Q_clk[2]),
.IB (Qn_clk[2]),
.O (cq_buf_clk[1])
);
BUFMR bufmr_cq_2 ( .O(cq_clk[1]), .I(cq_buf_clk[1]) );
assign cqn_clk[1] = ~cq_clk[1];
end //end of if
end
end else begin: gen_ibuf_cq //QDR2+ case, use both locations all the time
//work around for current QDR2+ parameters
//ideally since we have 4 byte lanes we want the parameters to specify
//where the clocks should go, but QDR2+ parameters handle it differently
// When changed, fix this to [1] & {2] as expected
if (GENERATE_CQ[0]==1 || GENERATE_CQ[1]==1 ||
GENERATE_CQ[2]==1 || GENERATE_CQ[3]==1 ) begin
//tie-off unused signals
assign cq_clk[1] = 1'b0;
assign cqn_clk[1] = 1'b0;
// it is legal to have the cq in either bytelane 1 or 2 for QDR.
if (GENERATE_CQ[1] == 1) begin
assign cq_capt_clk = Q_clk[1];
assign cqn_capt_clk = Qn_clk[1];
end else if (GENERATE_CQ[2] == 1) begin
assign cq_capt_clk = Q_clk[2];
assign cqn_capt_clk = Qn_clk[2];
end
IBUF buf_cq (.O (cq_buf_clk[0]), .I (cq_capt_clk) );
IBUF buf_cqn (.O (cqn_buf_clk[0]), .I (cqn_capt_clk) );
BUFMR bufmr_cq (.O (cq_clk[0]), .I (cq_buf_clk[0]) );
BUFMR bufmr_cqn (.O (cqn_clk[0]), .I (cqn_buf_clk[0]));
end else begin
assign cq_buf_clk = 'b0;
assign cqn_buf_clk= 'b0;
assign cq_clk = 'b0;
assign cqn_clk = 'b0;
end
end //end gen_ibuf_cq
endgenerate
assign #(BUFMR_DELAY) cpt_clk[0] = cq_clk[0];
assign #(BUFMR_DELAY) cpt_clk[1] = cq_clk[1];
assign #(BUFMR_DELAY) cpt_clk_n[0] = cqn_clk[0];
assign #(BUFMR_DELAY) cpt_clk_n[1] = cqn_clk[1];
//assign all of the read clocks to the different phy lanes (RLDRAM only)
generate
if (DIFF_CQ == 1) begin: gen_cpt_assignments
if (MEMORY_TYPE == "RLD3") begin
//One clock per byte lane, no BUFMR so no extra delay needs to be inserted
//for simulation
always @(*) begin
A_cq_clk <= cq_clk[0];
B_cq_clk <= cq_clk[1];
C_cq_clk <= cq_clk[2];
D_cq_clk <= cq_clk[3];
//N-side not used
A_cqn_clk <= 1'b0;
B_cqn_clk <= 1'b0;
C_cqn_clk <= 1'b0;
D_cqn_clk <= 1'b0;
end
end else begin
always @(*) begin
//A byte lane
if (CPT_CLK_SEL[7:0]==8'h11)
A_cq_clk <= cpt_clk[0];
else if (CPT_CLK_SEL[7:0]==8'h12)
A_cq_clk <= cpt_clk[1];
else if (CPT_CLK_SEL[7:0]==8'h01) //from Bank below
A_cq_clk <= cpt_clk_below[0];
else if (CPT_CLK_SEL[7:0]==8'h02) //from Bank below
A_cq_clk <= cpt_clk_below[1];
else if (CPT_CLK_SEL[7:0]==8'h21) //from Bank above
A_cq_clk <= cpt_clk_above[0];
else if (CPT_CLK_SEL[7:0]==8'h22) //from Bank above
A_cq_clk <= cpt_clk_above[1];
else
A_cq_clk <= cpt_clk[0]; //default
//B byte lane
if (CPT_CLK_SEL[15:8]==8'h11)
B_cq_clk <= cpt_clk[0];
else if (CPT_CLK_SEL[15:8]==8'h12)
B_cq_clk <= cpt_clk[1];
else if (CPT_CLK_SEL[15:8]==8'h01) //from Bank below
B_cq_clk <= cpt_clk_below[0];
else if (CPT_CLK_SEL[15:8]==8'h02) //from Bank below
B_cq_clk <= cpt_clk_below[1];
else if (CPT_CLK_SEL[15:8]==8'h21) //from Bank above
B_cq_clk <= cpt_clk_above[0];
else if (CPT_CLK_SEL[15:8]==8'h22) //from Bank above
B_cq_clk <= cpt_clk_above[1];
else
B_cq_clk <= cpt_clk[0]; //default
//C byte lane
if (CPT_CLK_SEL[23:16]==8'h11)
C_cq_clk <= cpt_clk[0];
else if (CPT_CLK_SEL[23:16]==8'h12)
C_cq_clk <= cpt_clk[1];
else if (CPT_CLK_SEL[23:16]==8'h01) //from Bank below
C_cq_clk <= cpt_clk_below[0];
else if (CPT_CLK_SEL[23:16]==8'h02) //from Bank below
C_cq_clk <= cpt_clk_below[1];
else if (CPT_CLK_SEL[23:16]==8'h21) //from Bank above
C_cq_clk <= cpt_clk_above[0];
else if (CPT_CLK_SEL[23:16]==8'h22) //from Bank above
C_cq_clk <= cpt_clk_above[1];
else
C_cq_clk <= cpt_clk[0]; //default
//D byte lane
if (CPT_CLK_SEL[31:24]==8'h11)
D_cq_clk <= cpt_clk[0];
else if (CPT_CLK_SEL[31:24]==8'h12)
D_cq_clk <= cpt_clk[1];
else if (CPT_CLK_SEL[31:24]==8'h01) //from Bank below
D_cq_clk <= cpt_clk_below[0];
else if (CPT_CLK_SEL[31:24]==8'h02) //from Bank below
D_cq_clk <= cpt_clk_below[1];
else if (CPT_CLK_SEL[31:24]==8'h21) //from Bank above
D_cq_clk <= cpt_clk_above[0];
else if (CPT_CLK_SEL[31:24]==8'h22) //from Bank above
D_cq_clk <= cpt_clk_above[1];
else
D_cq_clk <= cpt_clk[0]; //default
//n-side of signal not used, tie to 0
A_cqn_clk <= #(BUFMR_DELAY) 1'b0;
B_cqn_clk <= #(BUFMR_DELAY) 1'b0;
C_cqn_clk <= #(BUFMR_DELAY) 1'b0;
D_cqn_clk <= #(BUFMR_DELAY) 1'b0;
end //always @ (*)
end
end else begin : gen_qdr_assignments
always @(*) begin
//A byte lane
if (CPT_CLK_SEL[7:4]== 4'h1) begin
A_cq_clk = cpt_clk[0];
A_cqn_clk = cpt_clk_n[0];
end else if (CPT_CLK_SEL[7:4]==4'h0) begin//from Bank below
A_cq_clk = cpt_clk_below[0];
A_cqn_clk = cpt_clk_n_below[0];
end else if (CPT_CLK_SEL[7:4]==4'h2) begin //from Bank above
A_cq_clk = cpt_clk_above[0];
A_cqn_clk = cpt_clk_n_above[0];
end else begin //default case
A_cq_clk = cpt_clk[0];
A_cqn_clk = cpt_clk_n[0];
end
//B byte lane
if (CPT_CLK_SEL[15:12]== 4'h1) begin
B_cq_clk = cpt_clk[0];
B_cqn_clk = cpt_clk_n[0];
end else if (CPT_CLK_SEL[15:12]==4'h0) begin//from Bank below
B_cq_clk = cpt_clk_below[0];
B_cqn_clk = cpt_clk_n_below[0];
end else if (CPT_CLK_SEL[15:12]==4'h2) begin //from Bank above
B_cq_clk = cpt_clk_above[0];
B_cqn_clk = cpt_clk_n_above[0];
end else begin //default case
B_cq_clk = cpt_clk[0];
B_cqn_clk = cpt_clk_n[0];
end
//C byte lane
if (CPT_CLK_SEL[23:20]== 4'h1) begin
C_cq_clk = cpt_clk[0];
C_cqn_clk = cpt_clk_n[0];
end else if (CPT_CLK_SEL[23:20]==4'h0) begin//from Bank below
C_cq_clk = cpt_clk_below[0];
C_cqn_clk = cpt_clk_n_below[0];
end else if (CPT_CLK_SEL[23:20]==4'h2) begin //from Bank above
C_cq_clk = cpt_clk_above[0];
C_cqn_clk = cpt_clk_n_above[0];
end else begin //default case
C_cq_clk = cpt_clk[0];
C_cqn_clk = cpt_clk_n[0];
end
//D byte lane
if (CPT_CLK_SEL[31:28]== 4'h1) begin
D_cq_clk = cpt_clk[0];
D_cqn_clk = cpt_clk_n[0];
end else if (CPT_CLK_SEL[31:28]==4'h0) begin//from Bank below
D_cq_clk = cpt_clk_below[0];
D_cqn_clk = cpt_clk_n_below[0];
end else if (CPT_CLK_SEL[31:28]==4'h2) begin //from Bank above
D_cq_clk = cpt_clk_above[0];
D_cqn_clk = cpt_clk_n_above[0];
end else begin //default case
D_cq_clk = cpt_clk[0];
D_cqn_clk = cpt_clk_n[0];
end
end
end
endgenerate
endmodule
|
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (DRT) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
assign wbs0_int_i = 0;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Spi Stuff
wire [31:0] ss_pad_o;
//wire ss_pad_o;
wire sclk_pad_o;
wire mosi_pad_o;
reg miso_pad_i;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_spi s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int ),
.ss_pad_o (ss_pad_o ),
.sclk_pad_o (sclk_pad_o ),
.mosi_pad_o (mosi_pad_o ),
.miso_pad_i (miso_pad_i )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
$display ("");
end
else begin
$display ("Error unrecognized line: %h" % ch);
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
$display ("Sleep for %h Clock cycles", r_in_data_count);
`SLEEP_CLK(r_in_data_count);
$display ("Sleep Finished");
end
else begin
$display ("Error: read_count = %h != 4", read_count);
$display ("Character: %h", ch);
end
end
else begin
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
$display ("Execute Command");
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
$display ("TB: reading a new double word: %h", r_in_data);
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
$display ("Command Finished");
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
$display ("TB: finished command");
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
$display ("TB: sdram is ready");
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
$display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data);
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
$display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count);
state <= WRITE_RESPONSE;
end
end
else begin
$display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data);
$display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count);
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
$display ("TB: Ping Response Good");
end
else begin
$display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status);
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
$display ("In Write Response");
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
$display ("TB: Write Response Good");
end
else begin
$display ("TB: Write Response Bad (Malformed response: %h)", w_out_status);
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
$display ("TB: Read Response Good");
if (w_out_data_count > 0) begin
$display("TB: w_out_data_count: %d", w_out_data_count);
if (data_read_count <= w_out_data_count) begin
$display ("TB: Read more data...");
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
$display ("TB: Read Response Bad (Malformed response: %h)", w_out_status);
state <= FINISHED;
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
$display ("TB: Read a 32bit data packet");
$display ("TB: \tRead Data: %h", w_out_data);
data_read_count <= data_read_count + 1;
end
if (data_read_count > r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
$display ("Execute Command is low");
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
$display("TB: Output Handler Recieved interrupt");
$display("TB:\tcommand: %h", w_out_status);
$display("TB:\taddress: %h", w_out_address);
$display("TB:\tdata: %h", w_out_data);
end
end//not reset
end
reg prev_sclk;
reg [127:0]mosi_data;
wire pos_edge_sclk;
reg [7:0] index;
assign pos_edge_sclk = ~prev_sclk && sclk_pad_o;
always @ (posedge clk) begin
if (rst) begin
miso_pad_i <= 0;
prev_sclk <= 0;
mosi_data <= 0;
index <= 0;
end
else begin
if (~ss_pad_o[0]) begin
//if (~ss_pad_o) begin
index <= 0;
end
if (pos_edge_sclk) begin
miso_pad_i <= ~miso_pad_i;
mosi_data[index] <= mosi_pad_o;
index <= index + 1;
end
prev_sclk <= sclk_pad_o;
end
end
endmodule
|
module sky130_fd_sc_hvl__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
|
module rs_ldst_ent
(
//Memory
input wire clk,
input wire reset,
input wire busy,
input wire [`ADDR_LEN-1:0] wpc,
input wire [`DATA_LEN-1:0] wsrc1,
input wire [`DATA_LEN-1:0] wsrc2,
input wire wvalid1,
input wire wvalid2,
input wire [`DATA_LEN-1:0] wimm,
input wire [`RRF_SEL-1:0] wrrftag,
input wire wdstval,
input wire [`SPECTAG_LEN-1:0] wspectag,
input wire we,
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire ready,
output reg [`ADDR_LEN-1:0] pc,
output reg [`DATA_LEN-1:0] imm,
output reg [`RRF_SEL-1:0] rrftag,
output reg dstval,
output reg [`SPECTAG_LEN-1:0] spectag,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
reg [`DATA_LEN-1:0] src1;
reg [`DATA_LEN-1:0] src2;
reg valid1;
reg valid2;
wire [`DATA_LEN-1:0] nextsrc1;
wire [`DATA_LEN-1:0] nextsrc2;
wire nextvalid1;
wire nextvalid2;
assign ready = busy & valid1 & valid2;
assign ex_src1 = ~valid1 & nextvalid1 ?
nextsrc1 : src1;
assign ex_src2 = ~valid2 & nextvalid2 ?
nextsrc2 : src2;
always @ (posedge clk) begin
if (reset) begin
pc <= 0;
imm <= 0;
rrftag <= 0;
dstval <= 0;
spectag <= 0;
src1 <= 0;
src2 <= 0;
valid1 <= 0;
valid2 <= 0;
end else if (we) begin
pc <= wpc;
imm <= wimm;
rrftag <= wrrftag;
dstval <= wdstval;
spectag <= wspectag;
src1 <= wsrc1;
src2 <= wsrc2;
valid1 <= wvalid1;
valid2 <= wvalid2;
end else begin // if (we)
src1 <= nextsrc1;
src2 <= nextsrc2;
valid1 <= nextvalid1;
valid2 <= nextvalid2;
end
end
src_manager srcmng1(
.opr(src1),
.opr_rdy(valid1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc1),
.resolved(nextvalid1)
);
src_manager srcmng2(
.opr(src2),
.opr_rdy(valid2),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc2),
.resolved(nextvalid2)
);
endmodule
|
module rs_ldst
(
//System
input wire clk,
input wire reset,
output reg [`LDST_ENT_NUM-1:0] busyvec,
input wire prmiss,
input wire prsuccess,
input wire [`SPECTAG_LEN-1:0] prtag,
input wire [`SPECTAG_LEN-1:0] specfixtag,
output wire [`LDST_ENT_NUM-1:0] prbusyvec_next,
//WriteSignal
input wire clearbusy, //Issue
input wire [`LDST_ENT_SEL-1:0] issueaddr, //= raddr, clsbsyadr
input wire we1, //alloc1
input wire we2, //alloc2
input wire [`LDST_ENT_SEL-1:0] waddr1, //allocent1
input wire [`LDST_ENT_SEL-1:0] waddr2, //allocent2
//WriteSignal1
input wire [`ADDR_LEN-1:0] wpc_1,
input wire [`DATA_LEN-1:0] wsrc1_1,
input wire [`DATA_LEN-1:0] wsrc2_1,
input wire wvalid1_1,
input wire wvalid2_1,
input wire [`DATA_LEN-1:0] wimm_1,
input wire [`RRF_SEL-1:0] wrrftag_1,
input wire wdstval_1,
input wire [`SPECTAG_LEN-1:0] wspectag_1,
input wire wspecbit_1,
//WriteSignal2
input wire [`ADDR_LEN-1:0] wpc_2,
input wire [`DATA_LEN-1:0] wsrc1_2,
input wire [`DATA_LEN-1:0] wsrc2_2,
input wire wvalid1_2,
input wire wvalid2_2,
input wire [`DATA_LEN-1:0] wimm_2,
input wire [`RRF_SEL-1:0] wrrftag_2,
input wire wdstval_2,
input wire [`SPECTAG_LEN-1:0] wspectag_2,
input wire wspecbit_2,
//ReadSignal
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire [`LDST_ENT_NUM-1:0] ready,
output wire [`ADDR_LEN-1:0] pc,
output wire [`DATA_LEN-1:0] imm,
output wire [`RRF_SEL-1:0] rrftag,
output wire dstval,
output wire [`SPECTAG_LEN-1:0] spectag,
output wire specbit,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
//_0
wire [`DATA_LEN-1:0] ex_src1_0;
wire [`DATA_LEN-1:0] ex_src2_0;
wire ready_0;
wire [`ADDR_LEN-1:0] pc_0;
wire [`DATA_LEN-1:0] imm_0;
wire [`RRF_SEL-1:0] rrftag_0;
wire dstval_0;
wire [`SPECTAG_LEN-1:0] spectag_0;
//_1
wire [`DATA_LEN-1:0] ex_src1_1;
wire [`DATA_LEN-1:0] ex_src2_1;
wire ready_1;
wire [`ADDR_LEN-1:0] pc_1;
wire [`DATA_LEN-1:0] imm_1;
wire [`RRF_SEL-1:0] rrftag_1;
wire dstval_1;
wire [`SPECTAG_LEN-1:0] spectag_1;
//_2
wire [`DATA_LEN-1:0] ex_src1_2;
wire [`DATA_LEN-1:0] ex_src2_2;
wire ready_2;
wire [`ADDR_LEN-1:0] pc_2;
wire [`DATA_LEN-1:0] imm_2;
wire [`RRF_SEL-1:0] rrftag_2;
wire dstval_2;
wire [`SPECTAG_LEN-1:0] spectag_2;
//_3
wire [`DATA_LEN-1:0] ex_src1_3;
wire [`DATA_LEN-1:0] ex_src2_3;
wire ready_3;
wire [`ADDR_LEN-1:0] pc_3;
wire [`DATA_LEN-1:0] imm_3;
wire [`RRF_SEL-1:0] rrftag_3;
wire dstval_3;
wire [`SPECTAG_LEN-1:0] spectag_3;
reg [`LDST_ENT_NUM-1:0] specbitvec;
//busy invalidation
wire [`LDST_ENT_NUM-1:0] inv_vector =
{(spectag_3 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_2 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_1 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_0 & specfixtag) == 0 ? 1'b1 : 1'b0};
wire [`LDST_ENT_NUM-1:0] inv_vector_spec =
{(spectag_3 == prtag) ? 1'b0 : 1'b1,
(spectag_2 == prtag) ? 1'b0 : 1'b1,
(spectag_1 == prtag) ? 1'b0 : 1'b1,
(spectag_0 == prtag) ? 1'b0 : 1'b1};
wire [`LDST_ENT_NUM-1:0] specbitvec_next =
(inv_vector_spec & specbitvec);
/*|
(we1 & wspecbit_1 ? (`LDST_ENT_SEL'b1 << waddr1) : 0) |
(we2 & wspecbit_2 ? (`LDST_ENT_SEL'b1 << waddr2) : 0);
*/
assign specbit = prsuccess ?
specbitvec_next[issueaddr] : specbitvec[issueaddr];
assign ready = {ready_3, ready_2, ready_1, ready_0};
assign prbusyvec_next = inv_vector & busyvec;
always @ (posedge clk) begin
if (reset) begin
busyvec <= 0;
specbitvec <= 0;
end else begin
if (prmiss) begin
busyvec <= prbusyvec_next;
specbitvec <= 0;
end else if (prsuccess) begin
specbitvec <= specbitvec_next;
/*
if (we1) begin
busyvec[waddr1] <= 1'b1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
end
*/
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end else begin
if (we1) begin
busyvec[waddr1] <= 1'b1;
specbitvec[waddr1] <= wspecbit_1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
specbitvec[waddr2] <= wspecbit_2;
end
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end
end
end
rs_ldst_ent ent0(
.clk(clk),
.reset(reset),
.busy(busyvec[0]),
.wpc((we1 && (waddr1 == 0)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 0)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 0)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 0)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 0)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 0)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 0)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 0)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 0)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 0)) || (we2 && (waddr2 == 0))),
.ex_src1(ex_src1_0),
.ex_src2(ex_src2_0),
.ready(ready_0),
.pc(pc_0),
.imm(imm_0),
.rrftag(rrftag_0),
.dstval(dstval_0),
.spectag(spectag_0),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_ldst_ent ent1(
.clk(clk),
.reset(reset),
.busy(busyvec[1]),
.wpc((we1 && (waddr1 == 1)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 1)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 1)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 1)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 1)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 1)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))),
.ex_src1(ex_src1_1),
.ex_src2(ex_src2_1),
.ready(ready_1),
.pc(pc_1),
.imm(imm_1),
.rrftag(rrftag_1),
.dstval(dstval_1),
.spectag(spectag_1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_ldst_ent ent2(
.clk(clk),
.reset(reset),
.busy(busyvec[2]),
.wpc((we1 && (waddr1 == 2)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 2)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 2)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 2)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 2)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 2)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 2)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 2)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 2)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 2)) || (we2 && (waddr2 == 2))),
.ex_src1(ex_src1_2),
.ex_src2(ex_src2_2),
.ready(ready_2),
.pc(pc_2),
.imm(imm_2),
.rrftag(rrftag_2),
.dstval(dstval_2),
.spectag(spectag_2),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_ldst_ent ent3(
.clk(clk),
.reset(reset),
.busy(busyvec[3]),
.wpc((we1 && (waddr1 == 3)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 3)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 3)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 3)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 3)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 3)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 3)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 3)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 3)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 3)) || (we2 && (waddr2 == 3))),
.ex_src1(ex_src1_3),
.ex_src2(ex_src2_3),
.ready(ready_3),
.pc(pc_3),
.imm(imm_3),
.rrftag(rrftag_3),
.dstval(dstval_3),
.spectag(spectag_3),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
assign ex_src1 = (issueaddr == 0) ? ex_src1_0 :
(issueaddr == 1) ? ex_src1_1 :
(issueaddr == 2) ? ex_src1_2 : ex_src1_3;
assign ex_src2 = (issueaddr == 0) ? ex_src2_0 :
(issueaddr == 1) ? ex_src2_1 :
(issueaddr == 2) ? ex_src2_2 : ex_src2_3;
assign pc = (issueaddr == 0) ? pc_0 :
(issueaddr == 1) ? pc_1 :
(issueaddr == 2) ? pc_2 : pc_3;
assign imm = (issueaddr == 0) ? imm_0 :
(issueaddr == 1) ? imm_1 :
(issueaddr == 2) ? imm_2 : imm_3;
assign rrftag = (issueaddr == 0) ? rrftag_0 :
(issueaddr == 1) ? rrftag_1 :
(issueaddr == 2) ? rrftag_2 : rrftag_3;
assign dstval = (issueaddr == 0) ? dstval_0 :
(issueaddr == 1) ? dstval_1 :
(issueaddr == 2) ? dstval_2 : dstval_3;
assign spectag = (issueaddr == 0) ? spectag_0 :
(issueaddr == 1) ? spectag_1 :
(issueaddr == 2) ? spectag_2 : spectag_3;
endmodule
|
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset), // resetrequest.reset
.source_ready (1'b1), // (terminated)
.mgmt_valid (), // (terminated)
.mgmt_channel (), // (terminated)
.mgmt_data (), // (terminated)
.jtag_tck (1'b0), // (terminated)
.jtag_tms (1'b0), // (terminated)
.jtag_tdi (1'b0), // (terminated)
.jtag_tdo (), // (terminated)
.jtag_ena (1'b0), // (terminated)
.jtag_usr1 (1'b0), // (terminated)
.jtag_clr (1'b0), // (terminated)
.jtag_clrn (1'b0), // (terminated)
.jtag_state_tlr (1'b0), // (terminated)
.jtag_state_rti (1'b0), // (terminated)
.jtag_state_sdrs (1'b0), // (terminated)
.jtag_state_cdr (1'b0), // (terminated)
.jtag_state_sdr (1'b0), // (terminated)
.jtag_state_e1dr (1'b0), // (terminated)
.jtag_state_pdr (1'b0), // (terminated)
.jtag_state_e2dr (1'b0), // (terminated)
.jtag_state_udr (1'b0), // (terminated)
.jtag_state_sirs (1'b0), // (terminated)
.jtag_state_cir (1'b0), // (terminated)
.jtag_state_sir (1'b0), // (terminated)
.jtag_state_e1ir (1'b0), // (terminated)
.jtag_state_pir (1'b0), // (terminated)
.jtag_state_e2ir (1'b0), // (terminated)
.jtag_state_uir (1'b0), // (terminated)
.jtag_ir_in (3'b000), // (terminated)
.jtag_irq (), // (terminated)
.jtag_ir_out () // (terminated)
);
soc_system_fpga_only_master_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.out_data (timing_adt_out_data), // out.data
.out_valid (timing_adt_out_valid), // .valid
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
soc_system_fpga_only_master_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (b2p_out_packets_stream_data), // in.data
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_ready (b2p_out_packets_stream_ready), // .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_channel (b2p_out_packets_stream_channel), // .channel
.out_data (b2p_adapter_out_data), // out.data
.out_valid (b2p_adapter_out_valid), // .valid
.out_ready (b2p_adapter_out_ready), // .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
soc_system_fpga_only_master_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (transacto_out_stream_data), // in.data
.in_valid (transacto_out_stream_valid), // .valid
.in_ready (transacto_out_stream_ready), // .ready
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_data (p2b_adapter_out_data), // out.data
.out_valid (p2b_adapter_out_valid), // .valid
.out_ready (p2b_adapter_out_ready), // .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module charComp(char, enter, cEnter, cEne, cVirgul, cDelete, cNum);
input [6:0] char;
input enter;
output reg cEnter, cEne, cVirgul, cDelete,cNum;
always @(char or enter) begin
if(enter==0) begin
case (char)
7'b0000100:begin
cEnter=1;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=0;
end
7'b1101110:begin
cEnter=0;
cEne=1;
cVirgul=0;
cDelete=0;
cNum=0;
end
7'b1001110:begin
cEnter=0;
cEne=1;
cVirgul=0;
cDelete=0;
cNum=0;
end
7'b1111110:begin
cEnter=0;
cEne=0;
cVirgul=1;
cDelete=0;
cNum=0;
end
7'b0001000:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=1;
cNum=0;
end
default: begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=0;
end
endcase
end
if(enter==1) begin
case (char)
7'b0110000:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110001:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110010:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110011:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110100:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110101:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110110:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0110111:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0111000:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
7'b0111001:begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=1;
end
default: begin
cEnter=0;
cEne=0;
cVirgul=0;
cDelete=0;
cNum=0;
end
endcase
end
end
endmodule
|
module sky130_fd_sc_ms__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
|
module jt12_timers(
input clk,
input rst,
input clk_en /* synthesis direct_enable */,
input zero,
input [9:0] value_A,
input [7:0] value_B,
input load_A,
input load_B,
input clr_flag_A,
input clr_flag_B,
input enable_irq_A,
input enable_irq_B,
output flag_A,
output flag_B,
output overflow_A,
output irq_n
);
parameter num_ch = 6;
assign irq_n = ~( (flag_A&enable_irq_A) | (flag_B&enable_irq_B) );
/*
reg zero2;
always @(posedge clk, posedge rst) begin
if( rst )
zero2 <= 0;
else if(clk_en) begin
if( zero ) zero2 <= ~zero;
end
end
wire zero = num_ch == 6 ? zero : (zero2&zero);
*/
jt12_timer #(.CW(10)) timer_A(
.clk ( clk ),
.rst ( rst ),
.cen ( clk_en ),
.zero ( zero ),
.start_value( value_A ),
.load ( load_A ),
.clr_flag ( clr_flag_A ),
.flag ( flag_A ),
.overflow ( overflow_A )
);
jt12_timer #(.CW(8),.FREE_EN(1)) timer_B(
.clk ( clk ),
.rst ( rst ),
.cen ( clk_en ),
.zero ( zero ),
.start_value( value_B ),
.load ( load_B ),
.clr_flag ( clr_flag_B ),
.flag ( flag_B ),
.overflow ( )
);
endmodule
|
module jt12_timer #(parameter
CW = 8, // counter bit width. This is the counter that can be loaded
FW = 4, // number of bits for the free-running counter
FREE_EN = 0 // enables a 4-bit free enable count
) (
input rst,
input clk,
input cen,
input zero,
input [CW-1:0] start_value,
input load,
input clr_flag,
output reg flag,
output reg overflow
);
/* verilator lint_off WIDTH */
reg load_l;
reg [CW-1:0] cnt, next;
reg [FW-1:0] free_cnt, free_next;
reg free_ov;
always@(posedge clk, posedge rst)
if( rst )
flag <= 1'b0;
else /*if(cen)*/ begin
if( clr_flag )
flag <= 1'b0;
else if( cen && zero && load && overflow ) flag<=1'b1;
end
always @(*) begin
{free_ov, free_next} = { 1'b0, free_cnt} + 1'b1;
{overflow, next } = { 1'b0, cnt } + (FREE_EN ? free_ov : 1'b1);
end
always @(posedge clk) begin
load_l <= load;
if( !load_l && load ) begin
cnt <= start_value;
end else if( cen && zero && load )
cnt <= overflow ? start_value : next;
end
// Free running counter
always @(posedge clk) begin
if( rst ) begin
free_cnt <= 0;
end else if( cen && zero ) begin
free_cnt <= free_cnt+1'd1;
end
end
/* verilator lint_on WIDTH */
endmodule
|
module intr_controller(
input I_clk,
input I_rst,
input [2:0] I_intr_rq,
input I_intr_ack,
output reg O_intr = 0,
output reg [1:0] O_intr_vector = 0
);
reg wait_state = 0;
reg [2:0] intr_rq = 0;
always @(posedge I_clk) begin
if (I_intr_rq[1]) begin
intr_rq[1] <= 1;
end
if (I_intr_rq[2]) begin
intr_rq[2] <= 1;
end
if (wait_state) begin
if (I_intr_ack) begin
wait_state <= 0;
intr_rq[O_intr_vector] <= 0;
O_intr <= 0;
end
end
else begin
if(intr_rq[1]) begin
O_intr <= 1;
O_intr_vector <= 1;
wait_state <= 1;
$display("intr_contr 1 is called vector = %d", O_intr_vector);
end
else if (intr_rq[2]) begin
O_intr <= 1;
O_intr_vector <= 2;
wait_state <= 1;
$display("intr_contr 2 is called vector = %d", O_intr_vector);
end
end
end
endmodule
|
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module sky130_fd_sc_lp__a311o_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__a311o_0 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
|
module Register_Bank (
// memory interface
din,
dout,
address,
size,
enable,
read_write,
// register inputs
PC0_next,
PC1_next,
PC2_next,
MSR0_next,
MSR1_next,
MSR2_next,
HMULT_next,
result,
result_reg,
result_valid,
// register outputs
reg0,
reg1,
reg2,
reg3,
PC0,
PC1,
PC2,
MSR0,
MSR1,
MSR2,
HMULT,
// control
sel0,
sel1,
sel2,
sel3,
state,
clk,
reset
);
`include "definition/Definition.v"
parameter REGWSTATE_HMULT = 0; // state to write HMULT
parameter REGWSTATE_GEN = 0; // state to write any general registers
parameter REGWSTATE_SFR = 0; // state to write all SFRs
// memory interface
input [WORD-1:0] din;
input [WORD-1:0] address;
output reg [WORD-1:0] dout;
input enable;
input read_write;
input [LOGWORDBYTE-1:0] size;
// register inputs
input [WORD-1:0] PC0_next;
input [WORD-1:0] PC1_next;
input [WORD-1:0] PC2_next;
input [WORD-1:0] MSR0_next;
input [WORD-1:0] MSR1_next;
input [WORD-1:0] MSR2_next;
input [WORD-1:0] HMULT_next;
input [WORD-1:0] result;
input [WORD-1:0] result_reg;
input result_valid;
// register outputs
output reg [WORD-1:0] reg0;
output reg [WORD-1:0] reg1;
output reg [WORD-1:0] reg2;
output reg [WORD-1:0] reg3;
output reg [WORD-1:0] PC0;
output reg [WORD-1:0] PC1;
output reg [WORD-1:0] PC2;
output reg [WORD-1:0] MSR0;
output reg [WORD-1:0] MSR1;
output reg [WORD-1:0] MSR2;
output reg [WORD-1:0] HMULT;
// control
input [WIDTH_FIELD0-1:0] sel0;
input [WIDTH_FIELD1-1:0] sel1;
input [WIDTH_FIELD2-1:0] sel2;
input [WIDTH_SHAMT_R-1:0] sel3;
input [WORD-1:0] state;
input clk;
input reset;
wire [WORD-1:0] value [TOTAL_SPACE-1:0]; // register value outputs
reg active;
reg unpacked_sel_memory [REG_SPACE-1:0];
always @(*) begin
dout <= value[address];
reg0 <= value[sel0];
reg1 <= value[sel1];
reg2 <= value[sel2];
reg3 <= value[sel3];
PC0 <= value[SFR_PC0];
PC1 <= value[SFR_PC1];
PC2 <= value[SFR_PC2];
MSR0 <= value[SFR_MSR0];
MSR1 <= value[SFR_MSR1];
MSR2 <= value[SFR_MSR2];
HMULT <= value[REG_HMULT];
end
genvar i;
generate
for(i=0; i<REG_SPACE; i=i+1) begin : REGSEL
always @(*) begin
unpacked_sel_memory[i] <= ((address/WORDBYTE) == i) && (read_write == WRITE) && enable;
end
end
endgenerate
// register set ****************************************************************
// Zero register
Register X0(
.value (value[REG_Z] ),
.memory (0 ),
.datapath (0 ),
.sel_memory (0 ),
.sel_datapath (0 ),
.clk (clk ),
.reset (reset )
);
// Higher Multiplication register
Register X1(
.value (value[REG_HMULT] ),
.memory (din ),
.datapath (HMULT_next ),
.sel_memory (unpacked_sel_memory[REG_HMULT] ),
.sel_datapath ((state == REGWSTATE_HMULT) ),
.clk (clk ),
.reset (reset )
);
// "Real" general purpose registers
generate
for(i=GENERAL_OFFSET; i<GENERAL_SPACE; i=i+1) begin : REGGENERAL
Register X(
.value (value[i] ),
.memory (din ),
.datapath (result ),
.sel_memory (unpacked_sel_memory[i] ),
.sel_datapath ((state == REGWSTATE_GEN) && (result_reg == i) && result_valid ), // REGWRITE_BROADSIDE
.clk (clk ),
.reset (reset )
);
end
endgenerate
// PC*
Register X16(
.value (value[SFR_PC0] ),
.memory (din ),
.datapath (PC0_next ),
.sel_memory (unpacked_sel_memory[SFR_PC0] ),
.sel_datapath ((state == REGWSTATE_SFR) ), // REGWRITE_BROADSIDE
.clk (clk ),
.reset (reset )
);
Register X17(
.value (value[SFR_PC1] ),
.memory (din ),
.datapath (PC1_next ),
.sel_memory (unpacked_sel_memory[SFR_PC1] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
Register X18(
.value (value[SFR_PC2] ),
.memory (din ),
.datapath (PC2_next ),
.sel_memory (unpacked_sel_memory[SFR_PC2] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
// MSR*
Register X19(
.value (value[SFR_MSR0] ),
.memory (din ),
.datapath (MSR0_next ),
.sel_memory (unpacked_sel_memory[SFR_MSR0] ),
.sel_datapath ((state == REGWSTATE_SFR) ), // REGWRITE_BROADSIDE
.clk (clk ),
.reset (reset )
);
Register X20(
.value (value[SFR_MSR1] ),
.memory (din ),
.datapath (MSR1_next ),
.sel_memory (unpacked_sel_memory[SFR_MSR1] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
Register X21(
.value (value[SFR_MSR2] ),
.memory (din ),
.datapath (MSR2_next ),
.sel_memory (unpacked_sel_memory[SFR_MSR2] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
endmodule
|
module tai_ecc(
input clk,
input rst_n,
input pps,
input [63 : 0] tai_sec_1,
input [63 : 0] tai_sec_2,
input [63 : 0] tai_sec_3,
output [63 : 0] tai_sec_correct,
output [ 7 : 0] tai_cnt_err_1,
output [ 7 : 0] tai_cnt_err_2,
output [ 7 : 0] tai_cnt_err_3,
output reg fault_interrupt
);
localparam IDLE = 5'b0;
localparam WAIT_PPS_RISE = 5'b1;
localparam GET_DATA = 5'b10;
localparam CMP_DATA = 5'b100;
localparam ERROR_CNT = 5'b1000;
localparam WAIT_PPS_FALL = 5'b10000;
reg [ 4 : 0] corr_state;
reg [ 4 : 0] corr_next_state;
reg [63 : 0] tai_sec_1_hold;
reg [63 : 0] tai_sec_2_hold;
reg [63 : 0] tai_sec_3_hold;
reg [63 : 0] tai_most_probably_fine;
reg [63 : 0] last_sec;
reg [ 7 : 0] t1_err;
reg [ 7 : 0] t2_err;
reg [ 7 : 0] t3_err;
reg t1_equal_t2;
reg t1_equal_t3;
reg t2_equal_t3;
assign tai_sec_correct = tai_most_probably_fine;
assign tai_cnt_err_1 = t1_err;
assign tai_cnt_err_2 = t2_err;
assign tai_cnt_err_3 = t3_err;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
tai_most_probably_fine <= 64'b0;
end
else begin
tai_most_probably_fine <= ((tai_sec_1 & tai_sec_2 & tai_sec_3) |
(( ~tai_sec_1) & tai_sec_2 & tai_sec_3) |
( tai_sec_1 & (~tai_sec_2) & tai_sec_3) |
( tai_sec_1 & tai_sec_2 & (~tai_sec_3)));
end
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
corr_state <= 0;
end
else begin
corr_state <= corr_next_state;
end
end
always @ (*)
begin
case (corr_state)
IDLE : begin
corr_next_state = WAIT_PPS_RISE;
end
WAIT_PPS_RISE : begin
if (pps) begin
corr_next_state = GET_DATA;
end
else begin
corr_next_state = WAIT_PPS_RISE;
end
end
GET_DATA : begin
corr_next_state = CMP_DATA;
end
CMP_DATA : begin
corr_next_state = ERROR_CNT;
end
ERROR_CNT : begin
corr_next_state = WAIT_PPS_FALL;
end
WAIT_PPS_FALL : begin
if (!pps) begin
corr_next_state = WAIT_PPS_RISE;
end
else begin
corr_next_state = WAIT_PPS_FALL;
end
end
default : begin
corr_next_state = IDLE;
end
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
tai_sec_1_hold <= 64'b0;
tai_sec_2_hold <= 64'b0;
tai_sec_3_hold <= 64'b0;
t1_equal_t2 <= 1'b0;
t1_equal_t3 <= 1'b0;
t2_equal_t3 <= 1'b0;
fault_interrupt <= 1'b0;
t1_err <= 8'b0;
t2_err <= 8'b0;
t3_err <= 8'b0;
end
else begin
case (corr_state)
IDLE : begin
end
WAIT_PPS_RISE : begin
end
GET_DATA : begin
tai_sec_1_hold <= tai_sec_1;
tai_sec_2_hold <= tai_sec_2;
tai_sec_3_hold <= tai_sec_3;
end
CMP_DATA : begin
t1_equal_t2 <= (tai_sec_1_hold == tai_sec_2_hold) ? 1'b1 : 1'b0;
t1_equal_t3 <= (tai_sec_1_hold == tai_sec_3_hold) ? 1'b1 : 1'b0;
t2_equal_t3 <= (tai_sec_2_hold == tai_sec_3_hold) ? 1'b1 : 1'b0;
end
ERROR_CNT : begin
casez ({t1_equal_t2, t1_equal_t3, t2_equal_t3})
3'b11? : begin
fault_interrupt <= 1'b0;
end
3'b10? : begin
t3_err <= t3_err + 1'b1;
fault_interrupt <= 1'b1;
end
3'b01? : begin
t2_err <= t2_err + 1'b1;
fault_interrupt <= 1'b1;
end
3'b001 : begin
t1_err <= t1_err + 1'b1;
fault_interrupt <= 1'b1;
end
3'b000 : begin
fault_interrupt <= 1'b1;
end
endcase
end
WAIT_PPS_FALL : begin
end
endcase
end
end
endmodule
|
module jfsmMealyWithOverlapTb;
wire dataout;
reg clock, reset, datain;
jfsmMealyWithOverlap jfsmM(dataout, clock, reset, datain);
initial
begin
reset = 1; datain = 0;
clock = 1; #5; clock = 0; #5;
reset = 0;
clock = 1; #5; clock = 0; #5;
$display("Starting input sequence");
// we now make the 5 transistions and check the dataout to see if it is detected
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 0; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
if ( dataout === 1 )
$display("PASS %b", dataout);
else
$display("FAIL %b", dataout);
// we now make the ONLY 4 transistions and check the dataout to see if it is detected
//datain = 1; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
datain = 0; clock = 1; #5; clock = 0; #5;
datain = 1; clock = 1; #5; clock = 0; #5;
if ( dataout === 1 )
$display("PASS %b", dataout);
else
$display("FAIL %b", dataout);
// we now make a wrongsequence the 5 transistions and check the dataout to see if it is detected
datain = 0; clock = 1; #5; clock = 0; #5;
datain = 0; clock = 1; #5; clock = 0; #5;
if ( dataout === 0 )
$display("PASS %b", dataout);
else
$display("FAIL %b", dataout);
end
endmodule
|
module clocker (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [4:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 25000,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1000,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clocker",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
|
module top();
// Inputs are registered
reg A;
reg SLEEP;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__inputiso1p dut (.A(A), .SLEEP(SLEEP), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module asyn_256_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire [7:0] sub_wire1;
wire [133:0] q = sub_wire0[133:0];
wire [7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.wrusedw (sub_wire1),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 134,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
|
module wr_port_mux_9to1
(/*AUTOARG*/
// Outputs
muxed_port_wr_en, muxed_port_wr_mask, muxed_port_wr_addr,
muxed_port_wr_data,
// Inputs
wr_port_select, port0_wr_en, port0_wr_mask, port0_wr_addr,
port0_wr_data, port1_wr_en, port1_wr_mask, port1_wr_addr,
port1_wr_data, port2_wr_en, port2_wr_mask, port2_wr_addr,
port2_wr_data, port3_wr_en, port3_wr_mask, port3_wr_addr,
port3_wr_data, port4_wr_en, port4_wr_mask, port4_wr_addr,
port4_wr_data, port5_wr_en, port5_wr_mask, port5_wr_addr,
port5_wr_data, port6_wr_en, port6_wr_mask, port6_wr_addr,
port6_wr_data, port7_wr_en, port7_wr_mask, port7_wr_addr,
port7_wr_data, port8_wr_en, port8_wr_mask, port8_wr_addr,
port8_wr_data
);
output[3:0] muxed_port_wr_en;
output [63:0] muxed_port_wr_mask;
output [9:0] muxed_port_wr_addr;
// change output port width
output [2047:0] muxed_port_wr_data;
input [15:0] wr_port_select;
input[3:0] port0_wr_en;
input [63:0] port0_wr_mask;
input [9:0] port0_wr_addr;
input [2047:0] port0_wr_data;
input[3:0] port1_wr_en;
input [63:0] port1_wr_mask;
input [9:0] port1_wr_addr;
input [2047:0] port1_wr_data;
input[3:0] port2_wr_en;
input [63:0] port2_wr_mask;
input [9:0] port2_wr_addr;
input [2047:0] port2_wr_data;
input[3:0] port3_wr_en;
input [63:0] port3_wr_mask;
input [9:0] port3_wr_addr;
input [2047:0] port3_wr_data;
input[3:0] port4_wr_en;
input [63:0] port4_wr_mask;
input [9:0] port4_wr_addr;
input [2047:0] port4_wr_data;
input[3:0] port5_wr_en;
input [63:0] port5_wr_mask;
input [9:0] port5_wr_addr;
input [2047:0] port5_wr_data;
input[3:0] port6_wr_en;
input [63:0] port6_wr_mask;
input [9:0] port6_wr_addr;
input [2047:0] port6_wr_data;
input[3:0] port7_wr_en;
input [63:0] port7_wr_mask;
input [9:0] port7_wr_addr;
input [2047:0] port7_wr_data;
input[3:0] port8_wr_en;
input [63:0] port8_wr_mask;
input [9:0] port8_wr_addr;
// S: change output width
input [2047:0] port8_wr_data;
/*
wire [2047:0] port0_wr_data_i, port1_wr_data_i, port2_wr_data_i,
port3_wr_data_i, port4_wr_data_i, port5_wr_data_i,
port6_wr_data_i, port7_wr_data_i;
assign port0_wr_data_i =
*/
/*
genvar i;
generate
for (i = 0; i<64; i=i+1) begin
assign port0_wr_data_i[i*32+:32] = {port0_wr_data[i*32+:32]};
assign port1_wr_data_i[i*32+:32] = {port1_wr_data[i*32+:32]};
assign port2_wr_data_i[i*32+:32] = {port2_wr_data[i*32+:32]};
assign port3_wr_data_i[i*32+:32] = {port3_wr_data[i*32+:32]};
assign port4_wr_data_i[i*128+:128] = {port4_wr_data[i*32+:32]};
assign port5_wr_data_i[i*128+:128] = {port5_wr_data[i*32+:32]};
assign port6_wr_data_i[i*128+:128] = {port6_wr_data[i*32+:32]};
assign port7_wr_data_i[i*128+:128] = {port7_wr_data[i*32+:32]};
end
endgenerate
*/
reg [3:0] muxed_port_wr_en;
reg [63:0] muxed_port_wr_mask;
reg [9:0] muxed_port_wr_addr;
reg [2047:0] muxed_port_wr_data;
always @ (*) begin
casex(wr_port_select)
16'h0001:
begin
muxed_port_wr_en <= port0_wr_en;
muxed_port_wr_mask <= port0_wr_mask;
muxed_port_wr_addr <= port0_wr_addr;
muxed_port_wr_data <= port0_wr_data;
end
16'h0002:
begin
muxed_port_wr_en <= port1_wr_en;
muxed_port_wr_mask <= port1_wr_mask;
muxed_port_wr_addr <= port1_wr_addr;
muxed_port_wr_data <= port1_wr_data;
end
16'h0004:
begin
muxed_port_wr_en <= port2_wr_en;
muxed_port_wr_mask <= port2_wr_mask;
muxed_port_wr_addr <= port2_wr_addr;
muxed_port_wr_data <= port2_wr_data;
end
16'h0008:
begin
muxed_port_wr_en <= port3_wr_en;
muxed_port_wr_mask <= port3_wr_mask;
muxed_port_wr_addr <= port3_wr_addr;
muxed_port_wr_data <= port3_wr_data;
end
16'h0010:
begin
muxed_port_wr_en <= port4_wr_en;
muxed_port_wr_mask <= port4_wr_mask;
muxed_port_wr_addr <= port4_wr_addr;
muxed_port_wr_data <= port4_wr_data;
end
16'h0020:
begin
muxed_port_wr_en <= port5_wr_en;
muxed_port_wr_mask <= port5_wr_mask;
muxed_port_wr_addr <= port5_wr_addr;
muxed_port_wr_data <= port5_wr_data;
end
16'h0040:
begin
muxed_port_wr_en <= port6_wr_en;
muxed_port_wr_mask <= port6_wr_mask;
muxed_port_wr_addr <= port6_wr_addr;
muxed_port_wr_data <= port6_wr_data;
end
16'h0080:
begin
muxed_port_wr_en <= port7_wr_en;
muxed_port_wr_mask <= port7_wr_mask;
muxed_port_wr_addr <= port7_wr_addr;
muxed_port_wr_data <= port7_wr_data;
end
16'h0100:
begin
muxed_port_wr_en <= port8_wr_en;
muxed_port_wr_mask <= port8_wr_mask;
muxed_port_wr_addr <= port8_wr_addr;
muxed_port_wr_data <= port8_wr_data;
end
16'b0000:
begin
muxed_port_wr_en <= 4'd0;
muxed_port_wr_mask <= 64'b0;
muxed_port_wr_addr <= {10{1'bx}};
// S: change from 8k to 2k
muxed_port_wr_data <= {2048{1'bx}};
end
default:
begin
muxed_port_wr_en <= 4'd0;
muxed_port_wr_mask <= {64{1'b0}};
muxed_port_wr_addr <= {10{1'bx}};
// S: change from 8k to 2k
muxed_port_wr_data <= {2048{1'bx}};
end
endcase
end
endmodule
|
module MemWinner(a, clk, spo)
/* synthesis syn_black_box black_box_pad_pin="a[4:0],clk,spo[107:0]" */;
input [4:0]a;
input clk;
output [107:0]spo;
endmodule
|
module axi_dmac #(
parameter ID = 0,
parameter DMA_DATA_WIDTH_SRC = 64,
parameter DMA_DATA_WIDTH_DEST = 64,
parameter DMA_LENGTH_WIDTH = 24,
parameter DMA_2D_TRANSFER = 0,
parameter ASYNC_CLK_REQ_SRC = 1,
parameter ASYNC_CLK_SRC_DEST = 1,
parameter ASYNC_CLK_DEST_REQ = 1,
parameter AXI_SLICE_DEST = 0,
parameter AXI_SLICE_SRC = 0,
parameter SYNC_TRANSFER_START = 0,
parameter CYCLIC = 1,
parameter DMA_AXI_PROTOCOL_DEST = 0,
parameter DMA_AXI_PROTOCOL_SRC = 0,
parameter DMA_TYPE_DEST = 0,
parameter DMA_TYPE_SRC = 2,
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter MAX_BYTES_PER_BURST = 128,
parameter FIFO_SIZE = 8, // In bursts
parameter AXI_ID_WIDTH_SRC = 1,
parameter AXI_ID_WIDTH_DEST = 1,
parameter DISABLE_DEBUG_REGISTERS = 0,
parameter ENABLE_DIAGNOSTICS_IF = 0)(
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [11:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [11:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
// Interrupt
output irq,
// Master AXI interface
input m_dest_axi_aclk,
input m_dest_axi_aresetn,
// Write address
output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_awaddr,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
output [ 2:0] m_dest_axi_awsize,
output [ 1:0] m_dest_axi_awburst,
output [ 2:0] m_dest_axi_awprot,
output [ 3:0] m_dest_axi_awcache,
output m_dest_axi_awvalid,
input m_dest_axi_awready,
output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_awid,
output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_awlock,
// Write data
output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
input m_dest_axi_wready,
output m_dest_axi_wvalid,
output m_dest_axi_wlast,
output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_wid,
// Write response
input m_dest_axi_bvalid,
input [ 1:0] m_dest_axi_bresp,
output m_dest_axi_bready,
input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_bid,
// Unused read interface
output m_dest_axi_arvalid,
output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_araddr,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
output [ 2:0] m_dest_axi_arsize,
output [ 1:0] m_dest_axi_arburst,
output [ 3:0] m_dest_axi_arcache,
output [ 2:0] m_dest_axi_arprot,
input m_dest_axi_arready,
input m_dest_axi_rvalid,
input [ 1:0] m_dest_axi_rresp,
input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
output m_dest_axi_rready,
output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_arid,
output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_arlock,
input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_rid,
input m_dest_axi_rlast,
// Master AXI interface
input m_src_axi_aclk,
input m_src_axi_aresetn,
// Read address
input m_src_axi_arready,
output m_src_axi_arvalid,
output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_araddr,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
output [ 2:0] m_src_axi_arsize,
output [ 1:0] m_src_axi_arburst,
output [ 2:0] m_src_axi_arprot,
output [ 3:0] m_src_axi_arcache,
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_arid,
output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_arlock,
// Read data and response
input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
output m_src_axi_rready,
input m_src_axi_rvalid,
input [ 1:0] m_src_axi_rresp,
input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_rid,
input m_src_axi_rlast,
// Unused write interface
output m_src_axi_awvalid,
output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_awaddr,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
output [ 2:0] m_src_axi_awsize,
output [ 1:0] m_src_axi_awburst,
output [ 3:0] m_src_axi_awcache,
output [ 2:0] m_src_axi_awprot,
input m_src_axi_awready,
output m_src_axi_wvalid,
output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
output m_src_axi_wlast,
input m_src_axi_wready,
input m_src_axi_bvalid,
input [ 1:0] m_src_axi_bresp,
output m_src_axi_bready,
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_awid,
output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_awlock,
output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_wid,
input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_bid,
// Slave streaming AXI interface
input s_axis_aclk,
output s_axis_ready,
input s_axis_valid,
input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
input s_axis_last,
output s_axis_xfer_req,
// Master streaming AXI interface
input m_axis_aclk,
input m_axis_ready,
output m_axis_valid,
output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output m_axis_last,
output m_axis_xfer_req,
// Input FIFO interface
input fifo_wr_clk,
input fifo_wr_en,
input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
output fifo_wr_xfer_req,
// Input FIFO interface
input fifo_rd_clk,
input fifo_rd_en,
output fifo_rd_valid,
output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output fifo_rd_underflow,
output fifo_rd_xfer_req,
// Diagnostics interface
output [7:0] dest_diag_level_bursts
);
localparam DMA_TYPE_AXI_MM = 0;
localparam DMA_TYPE_AXI_STREAM = 1;
localparam DMA_TYPE_FIFO = 2;
localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :
DMA_DATA_WIDTH_DEST > 512 ? 7 :
DMA_DATA_WIDTH_DEST > 256 ? 6 :
DMA_DATA_WIDTH_DEST > 128 ? 5 :
DMA_DATA_WIDTH_DEST > 64 ? 4 :
DMA_DATA_WIDTH_DEST > 32 ? 3 :
DMA_DATA_WIDTH_DEST > 16 ? 2 :
DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
DMA_DATA_WIDTH_SRC > 512 ? 7 :
DMA_DATA_WIDTH_SRC > 256 ? 6 :
DMA_DATA_WIDTH_SRC > 128 ? 5 :
DMA_DATA_WIDTH_SRC > 64 ? 4 :
DMA_DATA_WIDTH_SRC > 32 ? 3 :
DMA_DATA_WIDTH_SRC > 16 ? 2 :
DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 :
(FIFO_SIZE) > 32 ? 7 :
(FIFO_SIZE) > 16 ? 6 :
(FIFO_SIZE) > 8 ? 5 :
(FIFO_SIZE) > 4 ? 4 :
(FIFO_SIZE) > 2 ? 3 :
(FIFO_SIZE) > 1 ? 2 : 1;
localparam DBG_ID_PADDING = ID_WIDTH > 8 ? 0 : 8 - ID_WIDTH;
/* AXI3 supports a maximum of 16 beats per burst. AXI4 supports a maximum of
256 beats per burst. If either bus is AXI3 set the maximum number of beats
per burst to 16. For non AXI interfaces the maximum beats per burst is in
theory unlimted. Set it to 1024 to provide a reasonable upper threshold */
localparam BEATS_PER_BURST_LIMIT_DEST =
(DMA_TYPE_DEST == DMA_TYPE_AXI_MM) ?
(DMA_AXI_PROTOCOL_DEST == 1 ? 16 : 256) :
1024;
localparam BYTES_PER_BURST_LIMIT_DEST =
BEATS_PER_BURST_LIMIT_DEST * DMA_DATA_WIDTH_DEST / 8;
localparam BEATS_PER_BURST_LIMIT_SRC =
(DMA_TYPE_SRC == DMA_TYPE_AXI_MM) ?
(DMA_AXI_PROTOCOL_SRC == 1 ? 16 : 256) :
1024;
localparam BYTES_PER_BURST_LIMIT_SRC =
BEATS_PER_BURST_LIMIT_SRC * DMA_DATA_WIDTH_SRC / 8;
/* The smaller bus limits the maximum bytes per burst. */
localparam BYTES_PER_BURST_LIMIT =
(BYTES_PER_BURST_LIMIT_DEST < BYTES_PER_BURST_LIMIT_SRC) ?
BYTES_PER_BURST_LIMIT_DEST : BYTES_PER_BURST_LIMIT_SRC;
/* Make sure the requested MAX_BYTES_PER_BURST does not exceed what the
interfaces can support. Limit the value if necessary. */
localparam REAL_MAX_BYTES_PER_BURST =
BYTES_PER_BURST_LIMIT < MAX_BYTES_PER_BURST ?
BYTES_PER_BURST_LIMIT : MAX_BYTES_PER_BURST;
/* Align to the length to the wider interface */
localparam DMA_LENGTH_ALIGN =
BYTES_PER_BEAT_WIDTH_DEST < BYTES_PER_BEAT_WIDTH_SRC ?
BYTES_PER_BEAT_WIDTH_SRC : BYTES_PER_BEAT_WIDTH_DEST;
localparam BYTES_PER_BURST_WIDTH =
REAL_MAX_BYTES_PER_BURST > 2048 ? 12 :
REAL_MAX_BYTES_PER_BURST > 1024 ? 11 :
REAL_MAX_BYTES_PER_BURST > 512 ? 10 :
REAL_MAX_BYTES_PER_BURST > 256 ? 9 :
REAL_MAX_BYTES_PER_BURST > 128 ? 8 :
REAL_MAX_BYTES_PER_BURST > 64 ? 7 :
REAL_MAX_BYTES_PER_BURST > 32 ? 6 :
REAL_MAX_BYTES_PER_BURST > 16 ? 5 :
REAL_MAX_BYTES_PER_BURST > 8 ? 4 :
REAL_MAX_BYTES_PER_BURST > 4 ? 3 :
REAL_MAX_BYTES_PER_BURST > 2 ? 2 : 1;
// ID signals from the DMAC, just for debugging
wire [ID_WIDTH-1:0] dest_request_id;
wire [ID_WIDTH-1:0] dest_data_id;
wire [ID_WIDTH-1:0] dest_address_id;
wire [ID_WIDTH-1:0] dest_response_id;
wire [ID_WIDTH-1:0] src_request_id;
wire [ID_WIDTH-1:0] src_data_id;
wire [ID_WIDTH-1:0] src_address_id;
wire [ID_WIDTH-1:0] src_response_id;
wire [11:0] dbg_status;
wire [31:0] dbg_ids0;
wire [31:0] dbg_ids1;
assign m_dest_axi_araddr = 'd0;
assign m_dest_axi_arlen = 'd0;
assign m_dest_axi_arsize = 'd0;
assign m_dest_axi_arburst = 'd0;
assign m_dest_axi_arcache = 'd0;
assign m_dest_axi_arprot = 'd0;
assign m_dest_axi_awid = 'h0;
assign m_dest_axi_awlock = 'h0;
assign m_dest_axi_wid = 'h0;
assign m_dest_axi_arid = 'h0;
assign m_dest_axi_arlock = 'h0;
assign m_src_axi_awaddr = 'd0;
assign m_src_axi_awlen = 'd0;
assign m_src_axi_awsize = 'd0;
assign m_src_axi_awburst = 'd0;
assign m_src_axi_awcache = 'd0;
assign m_src_axi_awprot = 'd0;
assign m_src_axi_wdata = 'd0;
assign m_src_axi_wstrb = 'd0;
assign m_src_axi_wlast = 'd0;
assign m_src_axi_awid = 'h0;
assign m_src_axi_awlock = 'h0;
assign m_src_axi_wid = 'h0;
assign m_src_axi_arid = 'h0;
assign m_src_axi_arlock = 'h0;
wire up_req_eot;
wire [BYTES_PER_BURST_WIDTH-1:0] up_req_measured_burst_length;
wire up_response_partial;
wire up_response_valid;
wire up_response_ready;
wire ctrl_enable;
wire ctrl_pause;
wire up_dma_req_valid;
wire up_dma_req_ready;
wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_req_dest_address;
wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_req_src_address;
wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_x_length;
wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_y_length;
wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_dest_stride;
wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_src_stride;
wire up_dma_req_sync_transfer_start;
wire up_dma_req_last;
assign dbg_ids0 = {
{DBG_ID_PADDING{1'b0}}, dest_response_id,
{DBG_ID_PADDING{1'b0}}, dest_data_id,
{DBG_ID_PADDING{1'b0}}, dest_address_id,
{DBG_ID_PADDING{1'b0}}, dest_request_id
};
assign dbg_ids1 = {
{DBG_ID_PADDING{1'b0}}, src_response_id,
{DBG_ID_PADDING{1'b0}}, src_data_id,
{DBG_ID_PADDING{1'b0}}, src_address_id,
{DBG_ID_PADDING{1'b0}}, src_request_id
};
axi_dmac_regmap #(
.DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
.DMA_CYCLIC(CYCLIC),
.HAS_DEST_ADDR(HAS_DEST_ADDR),
.HAS_SRC_ADDR(HAS_SRC_ADDR),
.DMA_2D_TRANSFER(DMA_2D_TRANSFER),
.SYNC_TRANSFER_START(SYNC_TRANSFER_START)
) i_regmap (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awprot(s_axi_awprot),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wready(s_axi_wready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bready(s_axi_bready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arready(s_axi_arready),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
// Interrupt
.irq(irq),
// Control interface
.ctrl_enable(ctrl_enable),
.ctrl_pause(ctrl_pause),
// Request interface
.request_valid(up_dma_req_valid),
.request_ready(up_dma_req_ready),
.request_dest_address(up_dma_req_dest_address),
.request_src_address(up_dma_req_src_address),
.request_x_length(up_dma_req_x_length),
.request_y_length(up_dma_req_y_length),
.request_dest_stride(up_dma_req_dest_stride),
.request_src_stride(up_dma_req_src_stride),
.request_sync_transfer_start(up_dma_req_sync_transfer_start),
.request_last(up_dma_req_last),
// DMA response interface
.response_eot(up_req_eot),
.response_measured_burst_length(up_req_measured_burst_length),
.response_partial(up_response_partial),
.response_valid(up_response_valid),
.response_ready(up_response_ready),
// Debug interface
.dbg_dest_addr(m_dest_axi_awaddr),
.dbg_src_addr(m_src_axi_araddr),
.dbg_status(dbg_status),
.dbg_ids0(dbg_ids0),
.dbg_ids1(dbg_ids1)
);
axi_dmac_transfer #(
.DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
.DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
.DMA_TYPE_DEST(DMA_TYPE_DEST),
.DMA_TYPE_SRC(DMA_TYPE_SRC),
.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
.DMA_2D_TRANSFER(DMA_2D_TRANSFER),
.ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
.ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
.ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
.AXI_SLICE_DEST(AXI_SLICE_DEST),
.AXI_SLICE_SRC(AXI_SLICE_SRC),
.MAX_BYTES_PER_BURST(REAL_MAX_BYTES_PER_BURST),
.FIFO_SIZE(FIFO_SIZE),
.ID_WIDTH(ID_WIDTH),
.AXI_LENGTH_WIDTH_SRC(8-(4*DMA_AXI_PROTOCOL_SRC)),
.AXI_LENGTH_WIDTH_DEST(8-(4*DMA_AXI_PROTOCOL_DEST)),
.ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF)
) i_transfer (
.ctrl_clk(s_axi_aclk),
.ctrl_resetn(s_axi_aresetn),
.ctrl_enable(ctrl_enable),
.ctrl_pause(ctrl_pause),
.req_valid(up_dma_req_valid),
.req_ready(up_dma_req_ready),
.req_dest_address(up_dma_req_dest_address),
.req_src_address(up_dma_req_src_address),
.req_x_length(up_dma_req_x_length),
.req_y_length(up_dma_req_y_length),
.req_dest_stride(up_dma_req_dest_stride),
.req_src_stride(up_dma_req_src_stride),
.req_sync_transfer_start(up_dma_req_sync_transfer_start),
.req_last(up_dma_req_last),
.req_eot(up_req_eot),
.req_measured_burst_length(up_req_measured_burst_length),
.req_response_partial(up_response_partial),
.req_response_valid(up_response_valid),
.req_response_ready(up_response_ready),
.m_dest_axi_aclk(m_dest_axi_aclk),
.m_dest_axi_aresetn(m_dest_axi_aresetn),
.m_src_axi_aclk(m_src_axi_aclk),
.m_src_axi_aresetn(m_src_axi_aresetn),
.m_axi_awaddr(m_dest_axi_awaddr),
.m_axi_awlen(m_dest_axi_awlen),
.m_axi_awsize(m_dest_axi_awsize),
.m_axi_awburst(m_dest_axi_awburst),
.m_axi_awprot(m_dest_axi_awprot),
.m_axi_awcache(m_dest_axi_awcache),
.m_axi_awvalid(m_dest_axi_awvalid),
.m_axi_awready(m_dest_axi_awready),
.m_axi_wdata(m_dest_axi_wdata),
.m_axi_wstrb(m_dest_axi_wstrb),
.m_axi_wready(m_dest_axi_wready),
.m_axi_wvalid(m_dest_axi_wvalid),
.m_axi_wlast(m_dest_axi_wlast),
.m_axi_bvalid(m_dest_axi_bvalid),
.m_axi_bresp(m_dest_axi_bresp),
.m_axi_bready(m_dest_axi_bready),
.m_axi_arready(m_src_axi_arready),
.m_axi_arvalid(m_src_axi_arvalid),
.m_axi_araddr(m_src_axi_araddr),
.m_axi_arlen(m_src_axi_arlen),
.m_axi_arsize(m_src_axi_arsize),
.m_axi_arburst(m_src_axi_arburst),
.m_axi_arprot(m_src_axi_arprot),
.m_axi_arcache(m_src_axi_arcache),
.m_axi_rdata(m_src_axi_rdata),
.m_axi_rready(m_src_axi_rready),
.m_axi_rvalid(m_src_axi_rvalid),
.m_axi_rlast(m_src_axi_rlast),
.m_axi_rresp(m_src_axi_rresp),
.s_axis_aclk(s_axis_aclk),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user),
.s_axis_last(s_axis_last),
.s_axis_xfer_req(s_axis_xfer_req),
.m_axis_aclk(m_axis_aclk),
.m_axis_ready(m_axis_ready),
.m_axis_valid(m_axis_valid),
.m_axis_data(m_axis_data),
.m_axis_last(m_axis_last),
.m_axis_xfer_req(m_axis_xfer_req),
.fifo_wr_clk(fifo_wr_clk),
.fifo_wr_en(fifo_wr_en),
.fifo_wr_din(fifo_wr_din),
.fifo_wr_overflow(fifo_wr_overflow),
.fifo_wr_sync(fifo_wr_sync),
.fifo_wr_xfer_req(fifo_wr_xfer_req),
.fifo_rd_clk(fifo_rd_clk),
.fifo_rd_en(fifo_rd_en),
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_dout(fifo_rd_dout),
.fifo_rd_underflow(fifo_rd_underflow),
.fifo_rd_xfer_req(fifo_rd_xfer_req),
// DBG
.dbg_dest_request_id(dest_request_id),
.dbg_dest_address_id(dest_address_id),
.dbg_dest_data_id(dest_data_id),
.dbg_dest_response_id(dest_response_id),
.dbg_src_request_id(src_request_id),
.dbg_src_address_id(src_address_id),
.dbg_src_data_id(src_data_id),
.dbg_src_response_id(src_response_id),
.dbg_status(dbg_status),
.dest_diag_level_bursts(dest_diag_level_bursts)
);
assign m_dest_axi_arvalid = 1'b0;
assign m_dest_axi_rready = 1'b0;
assign m_dest_axi_araddr = 'h0;
assign m_dest_axi_arlen = 'h0;
assign m_dest_axi_arsize = 'h0;
assign m_dest_axi_arburst = 'h0;
assign m_dest_axi_arcache = 'h0;
assign m_dest_axi_arprot = 'h0;
assign m_src_axi_awvalid = 1'b0;
assign m_src_axi_wvalid = 1'b0;
assign m_src_axi_bready = 1'b0;
assign m_src_axi_awvalid = 'h0;
assign m_src_axi_awaddr = 'h0;
assign m_src_axi_awlen = 'h0;
assign m_src_axi_awsize = 'h0;
assign m_src_axi_awburst = 'h0;
assign m_src_axi_awcache = 'h0;
assign m_src_axi_awprot = 'h0;
assign m_src_axi_wvalid = 'h0;
assign m_src_axi_wdata = 'h0;
assign m_src_axi_wstrb = 'h0;
assign m_src_axi_wlast = 'h0;
endmodule
|
module async_transmitter(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 50000000; // 25MHz
parameter Baud = 115200;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
////////////////////////////////
`ifdef SIMULATION
wire BitTick = 1'b1; // output one bit per clock cycle
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits
endmodule
|
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 50000000; // 25MHz
parameter Baud = 115200;
parameter Oversampling = 16; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
////////////////////////////////
reg [3:0] RxD_state = 0;
`ifdef SIMULATION
wire RxD_bit = RxD;
wire sampleNow = 1'b1; // receive one bit per clock cycle
`else
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk)
if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk)
if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
`endif
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3])
RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk)
if (RxD_state!=0)
GapCnt<=0;
else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1])
GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk)
RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
endmodule
|
module ASSERTION_ERROR();
endmodule
|
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 50000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
//acc width == 16
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
//shiftlimiter == 5
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk)
if(enable)
Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0];
else
Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
|
module seven_segment_display
(
input clk,
input [15:0]num_in,
output reg [6:0]dig,
output reg dp,
output reg neg,
output reg clr,
output reg [3:0]dig_sel
);
//dig format
//dig[0] : A, top
//dig[1] : B, top/right
//dig[2] : C, bottom/right
//dig[3] : D, bottom
//dig[4] : E, bottom/left
//dig[5] : F, top/left
//dig[6] : G, middle
reg [6:0]dig1;
reg [6:0]dig2;
reg [6:0]dig3;
reg [6:0]dig4;
reg [19:0] clk_div;
always @(posedge clk) begin
clk_div = clk_div + 1;
end
always @(posedge clk) begin
/* dig_sel <= 4'b0001; */
/* dig <= dig1; */
if (clk_div == 0)
begin
if(dig_sel == 0)
dig_sel <= 1;
else
dig_sel <= {dig_sel[0],dig_sel[3:1]};
case(dig_sel)
4'b0010: dig <= dig4;
4'b0100: dig <= dig3;
4'b1000: dig <= dig2;
4'b0001: dig <= dig1;
endcase
end
end
always @(posedge clk) begin
case(num_in[3:0])
4'b0000: dig1 = 7'b1000000; //0
4'b0001: dig1 = 7'b1111001; //1
4'b0010: dig1 = 7'b0100100; //2
4'b0011: dig1 = 7'b0110000; //3
4'b0100: dig1 = 7'b0011001; //4
4'b0101: dig1 = 7'b0010010; //5
4'b0110: dig1 = 7'b0000010; //6
4'b0111: dig1 = 7'b1111000; //7
4'b1000: dig1 = 7'b0000000; //8
4'b1001: dig1 = 7'b0010000; //9
4'b1010: dig1 = 7'b0001000; //A
4'b1011: dig1 = 7'b0000011; //b
4'b1100: dig1 = 7'b1000110; //C
4'b1101: dig1 = 7'b0100001; //d
4'b1110: dig1 = 7'b0000110; //E
4'b1111: dig1 = 7'b0001110; //F
endcase
case(num_in[7:4])
4'b0000: dig2 = 7'b1000000; //0
4'b0001: dig2 = 7'b1111001; //1
4'b0010: dig2 = 7'b0100100; //2
4'b0011: dig2 = 7'b0110000; //3
4'b0100: dig2 = 7'b0011001; //4
4'b0101: dig2 = 7'b0010010; //5
4'b0110: dig2 = 7'b0000010; //6
4'b0111: dig2 = 7'b1111000; //7
4'b1000: dig2 = 7'b0000000; //8
4'b1001: dig2 = 7'b0010000; //9
4'b1010: dig2 = 7'b0001000; //A
4'b1011: dig2 = 7'b0000011; //b
4'b1100: dig2 = 7'b1000110; //C
4'b1101: dig2 = 7'b0100001; //d
4'b1110: dig2 = 7'b0000110; //E
4'b1111: dig2 = 7'b0001110; //F
endcase
case(num_in[11:8])
4'b0000: dig3 = 7'b1000000; //0
4'b0001: dig3 = 7'b1111001; //1
4'b0010: dig3 = 7'b0100100; //2
4'b0011: dig3 = 7'b0110000; //3
4'b0100: dig3 = 7'b0011001; //4
4'b0101: dig3 = 7'b0010010; //5
4'b0110: dig3 = 7'b0000010; //6
4'b0111: dig3 = 7'b1111000; //7
4'b1000: dig3 = 7'b0000000; //8
4'b1001: dig3 = 7'b0010000; //9
4'b1010: dig3 = 7'b0001000; //A
4'b1011: dig3 = 7'b0000011; //b
4'b1100: dig3 = 7'b1000110; //C
4'b1101: dig3 = 7'b0100001; //d
4'b1110: dig3 = 7'b0000110; //E
4'b1111: dig3 = 7'b0001110; //F
endcase
case(num_in[15:12])
4'b0000: dig4 = 7'b1000000; //0
4'b0001: dig4 = 7'b1111001; //1
4'b0010: dig4 = 7'b0100100; //2
4'b0011: dig4 = 7'b0110000; //3
4'b0100: dig4 = 7'b0011001; //4
4'b0101: dig4 = 7'b0010010; //5
4'b0110: dig4 = 7'b0000010; //6
4'b0111: dig4 = 7'b1111000; //7
4'b1000: dig4 = 7'b0000000; //8
4'b1001: dig4 = 7'b0010000; //9
4'b1010: dig4 = 7'b0001000; //A
4'b1011: dig4 = 7'b0000011; //b
4'b1100: dig4 = 7'b1000110; //C
4'b1101: dig4 = 7'b0100001; //d
4'b1110: dig4 = 7'b0000110; //E
4'b1111: dig4 = 7'b0001110; //F
endcase
end
always @(posedge clk) begin
dp <= 1;
neg <= 1;
clr <= 0;
end
endmodule
|
module sky130_fd_sc_hdll__and3b (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_hvl__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
|
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_selector_D, intAS,
sign_final_result, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n43, n44, n45, n47, n48, n49, n51, n52,
n53, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81,
n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95,
n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107,
n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,
n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151,
n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162,
n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173,
n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184,
n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206,
n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239,
n240, n241, n242, n243, n244, n245, n246, n247, n248, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476,
n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486,
n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496,
n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506,
n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516,
n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526,
n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790;
wire [1:0] FSM_selector_B;
wire [31:0] intDX;
wire [31:0] intDY;
wire [30:0] DMP;
wire [30:0] DmP;
wire [7:0] exp_oper_result;
wire [4:0] LZA_output;
wire [25:0] Add_Subt_result;
wire [25:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [51:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n173), .CK(clk), .RN(
n1790), .Q(DmP[28]) );
DFFRXLTS YRegister_Q_reg_27_ ( .D(n171), .CK(clk), .RN(n1762), .Q(intDY[27]),
.QN(n688) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n170), .CK(clk), .RN(
n1790), .Q(DmP[27]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n167), .CK(clk), .RN(
n1781), .Q(DmP[26]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n164), .CK(clk), .RN(
n1782), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n161), .CK(clk), .RN(
n1781), .Q(DmP[24]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n158), .CK(clk), .RN(
n1773), .Q(DmP[23]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n155), .CK(clk), .RN(
n1763), .Q(DmP[22]), .QN(n1743) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n152), .CK(clk), .RN(
n1763), .Q(DmP[21]), .QN(n1734) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n149), .CK(clk), .RN(
n1763), .QN(n660) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n146), .CK(clk), .RN(
n1763), .Q(DmP[19]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n143), .CK(clk), .RN(
n1763), .Q(DmP[18]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n137), .CK(clk), .RN(
n1779), .Q(DmP[16]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n134), .CK(clk), .RN(
n1783), .Q(DmP[15]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n131), .CK(clk), .RN(
n1787), .Q(DmP[14]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n128), .CK(clk), .RN(
n1779), .Q(DmP[13]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n125), .CK(clk), .RN(
n1787), .Q(DmP[12]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n122), .CK(clk), .RN(
n1789), .Q(DmP[11]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n119), .CK(clk), .RN(
n1783), .Q(DmP[10]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n107), .CK(clk), .RN(
n1764), .Q(DmP[6]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n101), .CK(clk), .RN(
n1764), .Q(DmP[4]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n98), .CK(clk), .RN(
n1764), .Q(DmP[3]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n95), .CK(clk), .RN(
n1765), .Q(DmP[2]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n75), .CK(clk), .RN(n1786), .QN(n654) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n73), .CK(clk), .RN(n1765), .Q(LZA_output[0]), .QN(n1757) );
DFFRX1TS Sel_B_Q_reg_1_ ( .D(n70), .CK(clk), .RN(n244), .Q(FSM_selector_B[1]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRX1TS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n77), .CK(clk), .RN(
n1771), .Q(overflow_flag), .QN(n1760) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n74), .CK(clk), .RN(n1782), .Q(LZA_output[1]), .QN(n1758) );
DFFRX1TS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n69), .CK(clk), .RN(
n1771), .Q(underflow_flag), .QN(n1756) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[35]), .QN(n1755) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[34]), .QN(n1754) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[47]), .QN(n1753) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[49]), .QN(n1752) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[48]), .QN(n1751) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n1778),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[51]), .QN(n1749) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n21), .CK(clk),
.RN(n1778), .Q(Sgf_normalized_result[22]), .QN(n1742) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n17), .CK(clk),
.RN(n1778), .Q(Sgf_normalized_result[23]), .QN(n1741) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n14), .CK(clk),
.RN(n1778), .Q(Sgf_normalized_result[24]), .QN(n1740) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n225), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[9]), .QN(n1738) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n223), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[7]), .QN(n1736) );
DFFRX2TS XRegister_Q_reg_16_ ( .D(n199), .CK(clk), .RN(n1788), .Q(intDX[16]),
.QN(n1733) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n29), .CK(clk),
.RN(n1780), .Q(Sgf_normalized_result[20]), .QN(n1732) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n25), .CK(clk),
.RN(n1785), .Q(Sgf_normalized_result[21]), .QN(n1731) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n227), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[11]), .QN(n1730) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n226), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[10]), .QN(n1729) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n33), .CK(clk),
.RN(n1780), .Q(Sgf_normalized_result[19]), .QN(n1726) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n37), .CK(clk),
.RN(n1785), .Q(Sgf_normalized_result[18]), .QN(n1725) );
DFFRX2TS XRegister_Q_reg_10_ ( .D(n193), .CK(clk), .RN(n1762), .Q(intDX[10]),
.QN(n1724) );
DFFRX2TS XRegister_Q_reg_28_ ( .D(n211), .CK(clk), .RN(n1784), .QN(n1723) );
DFFRX2TS XRegister_Q_reg_5_ ( .D(n188), .CK(clk), .RN(n1780), .Q(intDX[5]),
.QN(n1721) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(n126), .CK(clk), .RN(n1783), .Q(intDY[12]),
.QN(n1719) );
DFFRX2TS XRegister_Q_reg_6_ ( .D(n189), .CK(clk), .RN(n1776), .Q(intDX[6]),
.QN(n1718) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n57), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[13]), .QN(n1716) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n49), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[15]), .QN(n1715) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n45), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[16]), .QN(n1714) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n41), .CK(clk),
.RN(n1780), .Q(Sgf_normalized_result[17]), .QN(n1713) );
DFFRX2TS YRegister_Q_reg_18_ ( .D(n144), .CK(clk), .RN(n1763), .Q(intDY[18]),
.QN(n1711) );
DFFRX2TS YRegister_Q_reg_30_ ( .D(n180), .CK(clk), .RN(n1762), .Q(intDY[30]),
.QN(n1710) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n228), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[12]), .QN(n1709) );
DFFRX2TS YRegister_Q_reg_21_ ( .D(n153), .CK(clk), .RN(n1763), .Q(intDY[21]),
.QN(n1708) );
DFFRX2TS YRegister_Q_reg_26_ ( .D(n168), .CK(clk), .RN(n1762), .Q(intDY[26]),
.QN(n1707) );
DFFRX1TS XRegister_Q_reg_8_ ( .D(n191), .CK(clk), .RN(n1776), .Q(intDX[8]),
.QN(n1704) );
DFFRX2TS XRegister_Q_reg_30_ ( .D(n213), .CK(clk), .RN(n1789), .Q(intDX[30]),
.QN(n1702) );
DFFRX2TS XRegister_Q_reg_29_ ( .D(n212), .CK(clk), .RN(n1788), .Q(intDX[29]),
.QN(n1701) );
DFFRX2TS XRegister_Q_reg_19_ ( .D(n202), .CK(clk), .RN(n1784), .Q(intDX[19]),
.QN(n1700) );
DFFRX2TS XRegister_Q_reg_14_ ( .D(n197), .CK(clk), .RN(n1788), .Q(intDX[14]),
.QN(n1699) );
DFFRX2TS XRegister_Q_reg_13_ ( .D(n196), .CK(clk), .RN(n1789), .Q(intDX[13]),
.QN(n1698) );
DFFRX2TS XRegister_Q_reg_18_ ( .D(n201), .CK(clk), .RN(n1784), .Q(intDX[18]),
.QN(n1697) );
DFFRX2TS XRegister_Q_reg_17_ ( .D(n200), .CK(clk), .RN(n1789), .Q(intDX[17]),
.QN(n1696) );
DFFRX2TS XRegister_Q_reg_15_ ( .D(n198), .CK(clk), .RN(n1788), .Q(intDX[15]),
.QN(n1695) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n53), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[14]), .QN(n1693) );
DFFRX2TS YRegister_Q_reg_8_ ( .D(n114), .CK(clk), .RN(n1784), .Q(intDY[8]),
.QN(n1690) );
DFFRX2TS YRegister_Q_reg_17_ ( .D(n141), .CK(clk), .RN(n1763), .Q(intDY[17]),
.QN(n1689) );
DFFRX2TS YRegister_Q_reg_25_ ( .D(n165), .CK(clk), .RN(n1762), .Q(intDY[25]),
.QN(n1688) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n231), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[15]), .QN(n1687) );
DFFRX2TS YRegister_Q_reg_20_ ( .D(n150), .CK(clk), .RN(n1763), .Q(intDY[20]),
.QN(n1685) );
DFFRX2TS YRegister_Q_reg_22_ ( .D(n156), .CK(clk), .RN(n1762), .Q(intDY[22]),
.QN(n1684) );
DFFRX2TS YRegister_Q_reg_11_ ( .D(n123), .CK(clk), .RN(n1787), .Q(intDY[11]),
.QN(n1683) );
DFFRX2TS YRegister_Q_reg_14_ ( .D(n132), .CK(clk), .RN(n1783), .Q(intDY[14]),
.QN(n1681) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n217), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[1]), .QN(n1678) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n218), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[2]), .QN(n1677) );
DFFRX2TS XRegister_Q_reg_4_ ( .D(n187), .CK(clk), .RN(n1780), .Q(intDX[4]),
.QN(n1676) );
DFFRX2TS Sel_C_Q_reg_0_ ( .D(n243), .CK(clk), .RN(n244), .Q(FSM_selector_C),
.QN(n1727) );
DFFRX2TS XRegister_Q_reg_7_ ( .D(n190), .CK(clk), .RN(n1776), .Q(intDX[7]),
.QN(n1675) );
DFFRX2TS YRegister_Q_reg_29_ ( .D(n177), .CK(clk), .RN(n1762), .Q(intDY[29]),
.QN(n1674) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(n192), .CK(clk), .RN(n1774), .Q(intDX[9]),
.QN(n1673) );
DFFRX2TS YRegister_Q_reg_19_ ( .D(n147), .CK(clk), .RN(n1763), .Q(intDY[19]),
.QN(n1672) );
DFFRX2TS YRegister_Q_reg_7_ ( .D(n111), .CK(clk), .RN(n1787), .Q(intDY[7]),
.QN(n1671) );
DFFRX2TS XRegister_Q_reg_26_ ( .D(n209), .CK(clk), .RN(n1784), .Q(intDX[26]),
.QN(n1670) );
DFFRX2TS XRegister_Q_reg_24_ ( .D(n207), .CK(clk), .RN(n1788), .Q(intDX[24]),
.QN(n1669) );
DFFRX2TS XRegister_Q_reg_22_ ( .D(n205), .CK(clk), .RN(n1789), .Q(intDX[22]),
.QN(n1668) );
DFFRX2TS XRegister_Q_reg_21_ ( .D(n204), .CK(clk), .RN(n1788), .Q(intDX[21]),
.QN(n1667) );
DFFRX2TS XRegister_Q_reg_27_ ( .D(n210), .CK(clk), .RN(n1788), .Q(intDX[27]),
.QN(n1666) );
DFFRX2TS XRegister_Q_reg_25_ ( .D(n208), .CK(clk), .RN(n1789), .Q(intDX[25]),
.QN(n1665) );
DFFRX2TS XRegister_Q_reg_23_ ( .D(n206), .CK(clk), .RN(n1784), .Q(intDX[23]),
.QN(n1664) );
DFFRX2TS XRegister_Q_reg_11_ ( .D(n194), .CK(clk), .RN(n1789), .Q(intDX[11]),
.QN(n1663) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n230), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[14]), .QN(n1662) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(n159), .CK(clk), .RN(n1762), .Q(intDY[23]),
.QN(n1661) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(n135), .CK(clk), .RN(n1785), .Q(intDY[15]),
.QN(n1660) );
DFFRX2TS XRegister_Q_reg_20_ ( .D(n203), .CK(clk), .RN(n1789), .Q(intDX[20]),
.QN(n1659) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n68),
.CK(clk), .RN(n1767), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n58),
.CK(clk), .RN(n1768), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n56),
.CK(clk), .RN(n1769), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n52),
.CK(clk), .RN(n1769), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n48),
.CK(clk), .RN(n1769), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n44),
.CK(clk), .RN(n1769), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n40),
.CK(clk), .RN(n1769), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n36),
.CK(clk), .RN(n1769), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n32),
.CK(clk), .RN(n1769), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n28),
.CK(clk), .RN(n1769), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n24),
.CK(clk), .RN(n1769), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n20),
.CK(clk), .RN(n1769), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n16),
.CK(clk), .RN(n1770), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n13),
.CK(clk), .RN(n1770), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n38), .CK(
clk), .RN(n1770), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n34), .CK(
clk), .RN(n1770), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n30), .CK(
clk), .RN(n1770), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n26), .CK(
clk), .RN(n1770), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n22), .CK(
clk), .RN(n1771), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n18), .CK(
clk), .RN(n1771), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n62),
.CK(clk), .RN(n1768), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n61),
.CK(clk), .RN(n1768), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n60),
.CK(clk), .RN(n1768), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n1747),
.CK(clk), .RN(n1770), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n1746),
.CK(clk), .RN(n1770), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n1745),
.CK(clk), .RN(n1770), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n1744),
.CK(clk), .RN(n1770), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n67),
.CK(clk), .RN(n1767), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n66),
.CK(clk), .RN(n1767), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n65),
.CK(clk), .RN(n1767), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n64),
.CK(clk), .RN(n1767), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n63),
.CK(clk), .RN(n1768), .Q(final_result_ieee[27]) );
DFFRX1TS XRegister_Q_reg_3_ ( .D(n186), .CK(clk), .RN(n1786), .Q(intDX[3]),
.QN(n1703) );
DFFRX2TS YRegister_Q_reg_13_ ( .D(n129), .CK(clk), .RN(n1787), .Q(intDY[13]),
.QN(n1686) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n59), .CK(clk),
.RN(n1777), .Q(Sgf_normalized_result[12]), .QN(n1717) );
DFFRX1TS XRegister_Q_reg_31_ ( .D(n182), .CK(clk), .RN(n1779), .Q(intDX[31]),
.QN(n1761) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n23), .CK(clk), .RN(
n1775), .Q(Sgf_normalized_result[3]) );
DFFRX2TS Sel_D_Q_reg_0_ ( .D(n245), .CK(clk), .RN(n244), .Q(FSM_selector_D)
);
DFFRX2TS YRegister_Q_reg_5_ ( .D(n105), .CK(clk), .RN(n1764), .Q(intDY[5])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n219), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[3]) );
DFFRX2TS YRegister_Q_reg_6_ ( .D(n108), .CK(clk), .RN(n1764), .Q(intDY[6])
);
DFFRX2TS YRegister_Q_reg_16_ ( .D(n138), .CK(clk), .RN(n1787), .Q(intDY[16])
);
DFFRX2TS XRegister_Q_reg_12_ ( .D(n195), .CK(clk), .RN(n1784), .Q(intDX[12])
);
DFFRX2TS YRegister_Q_reg_2_ ( .D(n96), .CK(clk), .RN(n1764), .Q(intDY[2]) );
DFFRX2TS YRegister_Q_reg_10_ ( .D(n120), .CK(clk), .RN(n1783), .Q(intDY[10])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n222), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[6]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n224), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[8]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n236), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[20]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n220), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[4]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n234), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[18]) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n241), .CK(
clk), .RN(n1775), .Q(add_overflow_flag), .QN(n1759) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[46]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n232), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[16]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n1765),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[44]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n1768),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[45]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n216), .CK(clk),
.RN(n1778), .Q(Add_Subt_result[0]) );
DFFRX2TS YRegister_Q_reg_1_ ( .D(n93), .CK(clk), .RN(n1765), .Q(intDY[1]),
.QN(n1682) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(n99), .CK(clk), .RN(n1764), .Q(intDY[3]),
.QN(n1680) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n83), .CK(clk), .RN(
n1781), .Q(exp_oper_result[4]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n1765),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[42]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
DFFRX1TS XRegister_Q_reg_1_ ( .D(n184), .CK(clk), .RN(n1775), .Q(intDX[1]),
.QN(n1705) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n1765),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[43]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n15), .CK(clk), .RN(
n1774), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n82), .CK(clk), .RN(
n1790), .Q(exp_oper_result[3]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n79), .CK(clk), .RN(
n1773), .Q(exp_oper_result[0]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n80), .CK(clk), .RN(
n1790), .Q(exp_oper_result[1]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n81), .CK(clk), .RN(
n1781), .Q(exp_oper_result[2]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n1765),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n19), .CK(clk), .RN(
n1775), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n27), .CK(clk), .RN(
n1775), .Q(Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n31), .CK(clk), .RN(
n1786), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n35), .CK(clk), .RN(
n1786), .Q(Sgf_normalized_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n39), .CK(clk), .RN(
n1781), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n47), .CK(clk), .RN(
n1776), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n78), .CK(clk), .RN(
n1774), .Q(exp_oper_result[7]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n84), .CK(clk), .RN(
n1774), .Q(exp_oper_result[5]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n85), .CK(clk), .RN(
n1774), .Q(exp_oper_result[6]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n76), .CK(clk), .RN(n1790), .Q(LZA_output[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n12), .CK(clk),
.RN(n1779), .Q(Sgf_normalized_result[25]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n157), .CK(clk), .RN(
n1782), .Q(DMP[23]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n163), .CK(clk), .RN(
n1782), .Q(DMP[25]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n169), .CK(clk), .RN(
n1782), .Q(DMP[27]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n72), .CK(clk), .RN(n1782), .Q(LZA_output[4]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n112), .CK(clk), .RN(
n1776), .Q(DMP[8]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n115), .CK(clk), .RN(
n1777), .Q(DMP[9]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n89), .CK(clk), .RN(
n1765), .Q(DmP[0]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n113), .CK(clk), .RN(
n1783), .Q(DmP[8]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n116), .CK(clk), .RN(
n1783), .Q(DmP[9]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n127), .CK(clk), .RN(
n1777), .Q(DMP[13]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n133), .CK(clk), .RN(
n1780), .Q(DMP[15]) );
DFFRX2TS YRegister_Q_reg_4_ ( .D(n102), .CK(clk), .RN(n1764), .Q(intDY[4])
);
DFFRX2TS YRegister_Q_reg_9_ ( .D(n117), .CK(clk), .RN(n1787), .Q(intDY[9])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n221), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[5]) );
DFFRX2TS YRegister_Q_reg_0_ ( .D(n90), .CK(clk), .RN(n1765), .Q(intDY[0]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n238), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[22]) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(n183), .CK(clk), .RN(n1775), .Q(intDX[0]),
.QN(n1722) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n248), .CK(clk),
.RN(n1775), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n55), .CK(clk),
.RN(n1776), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n51), .CK(clk),
.RN(n1776), .Q(Sgf_normalized_result[10]) );
DFFRX1TS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n86), .CK(clk),
.RN(n1779), .Q(sign_final_result), .QN(n1679) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n1779),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[50]), .QN(n1748) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n139), .CK(clk), .RN(
n1780), .Q(DMP[17]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n160), .CK(clk), .RN(
n1786), .Q(DMP[24]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n166), .CK(clk), .RN(
n1786), .Q(DMP[26]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n176), .CK(clk), .RN(
n1786), .Q(DmP[29]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n179), .CK(clk), .RN(
n1781), .Q(DmP[30]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n118), .CK(clk), .RN(
n1777), .Q(DMP[10]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n109), .CK(clk), .RN(
n1776), .Q(DMP[7]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n106), .CK(clk), .RN(
n1776), .Q(DMP[6]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n103), .CK(clk), .RN(
n1782), .Q(DMP[5]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n100), .CK(clk), .RN(
n1782), .Q(DMP[4]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n97), .CK(clk), .RN(
n1782), .Q(DMP[3]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n94), .CK(clk), .RN(
n1775), .Q(DMP[2]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n91), .CK(clk), .RN(
n1775), .Q(DMP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n88), .CK(clk), .RN(
n1775), .Q(DMP[0]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n1767),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n140), .CK(clk), .RN(
n1783), .Q(DmP[17]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n110), .CK(clk), .RN(
n1764), .Q(DmP[7]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n104), .CK(clk), .RN(
n1764), .Q(DmP[5]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n92), .CK(clk), .RN(
n1765), .Q(DmP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n178), .CK(clk), .RN(
n1774), .Q(DMP[30]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n175), .CK(clk), .RN(
n1774), .Q(DMP[29]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n172), .CK(clk), .RN(
n1774), .Q(DMP[28]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n154), .CK(clk), .RN(
n1778), .Q(DMP[22]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n151), .CK(clk), .RN(
n1778), .Q(DMP[21]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n148), .CK(clk), .RN(
n1778), .Q(DMP[20]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n142), .CK(clk), .RN(
n1785), .Q(DMP[18]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n136), .CK(clk), .RN(
n1785), .Q(DMP[16]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n130), .CK(clk), .RN(
n1785), .Q(DMP[14]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n124), .CK(clk), .RN(
n1777), .Q(DMP[12]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n121), .CK(clk), .RN(
n1777), .Q(DMP[11]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n1766),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n247), .CK(clk), .RN(n1779), .Q(
FS_Module_state_reg[1]), .QN(n655) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n246), .CK(clk), .RN(n1779), .Q(
FS_Module_state_reg[2]), .QN(n1694) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n214), .CK(clk), .RN(n1774), .Q(
FS_Module_state_reg[0]), .QN(n1712) );
DFFRX1TS YRegister_Q_reg_31_ ( .D(n87), .CK(clk), .RN(n1779), .Q(intDY[31])
);
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n233), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[17]), .QN(n1750) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n235), .CK(clk),
.RN(n1772), .Q(Add_Subt_result[19]), .QN(n1739) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n240), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[24]), .QN(n1737) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n237), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[21]), .QN(n1735) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(n185), .CK(clk), .RN(n1780), .Q(intDX[2]),
.QN(n1706) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n71), .CK(clk), .RN(n244), .Q(FSM_selector_B[0]), .QN(n1692) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n229), .CK(clk),
.RN(n1771), .Q(Add_Subt_result[13]), .QN(n1691) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n215), .CK(clk),
.RN(n1778), .Q(Add_Subt_result[25]) );
DFFRX1TS ASRegister_Q_reg_0_ ( .D(n181), .CK(clk), .RN(n1779), .Q(intAS) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n43), .CK(clk), .RN(
n1776), .Q(Sgf_normalized_result[8]) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n242), .CK(clk), .RN(n1774), .Q(
FS_Module_state_reg[3]), .QN(n1720) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n145), .CK(clk), .RN(
n1778), .Q(DMP[19]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n239), .CK(clk),
.RN(n1773), .Q(Add_Subt_result[23]), .QN(n1728) );
DFFRX2TS YRegister_Q_reg_24_ ( .D(n162), .CK(clk), .RN(n1762), .Q(intDY[24])
);
DFFRX2TS YRegister_Q_reg_28_ ( .D(n174), .CK(clk), .RN(n1762), .Q(intDY[28])
);
AND2X2TS U892 ( .A(n1109), .B(n653), .Y(n1165) );
CLKXOR2X2TS U893 ( .A(n740), .B(n739), .Y(n1285) );
OAI21X2TS U894 ( .A0(n740), .A1(n736), .B0(n737), .Y(n767) );
INVX4TS U895 ( .A(n744), .Y(n751) );
NAND2X2TS U896 ( .A(n1712), .B(n954), .Y(n1144) );
NOR2X1TS U897 ( .A(n731), .B(n730), .Y(n736) );
NAND2X1TS U898 ( .A(n727), .B(n726), .Y(n741) );
AOI21X1TS U899 ( .A0(n696), .A1(n745), .B0(n722), .Y(n723) );
NOR2X4TS U900 ( .A(FSM_selector_B[1]), .B(n1692), .Y(n702) );
NOR2X1TS U901 ( .A(FS_Module_state_reg[3]), .B(n909), .Y(n954) );
NOR2X1TS U902 ( .A(n1444), .B(n1456), .Y(n838) );
NOR2X1TS U903 ( .A(n1402), .B(n1404), .Y(n816) );
NOR2X1TS U904 ( .A(n1366), .B(n1378), .Y(n1391) );
NAND2BX2TS U905 ( .AN(n1316), .B(n1317), .Y(n776) );
NAND2X1TS U906 ( .A(n844), .B(n843), .Y(n1481) );
INVX6TS U907 ( .A(n1281), .Y(n877) );
INVX4TS U908 ( .A(n1281), .Y(n821) );
XOR2X2TS U909 ( .A(n1201), .B(intDX[31]), .Y(n1174) );
OAI21XLTS U910 ( .A0(intDX[15]), .A1(n1660), .B0(intDX[14]), .Y(n1076) );
OAI21XLTS U911 ( .A0(n1471), .A1(n1481), .B0(n1472), .Y(n847) );
NOR2XLTS U912 ( .A(n1716), .B(n885), .Y(n827) );
NOR2XLTS U913 ( .A(n885), .B(n1742), .Y(n882) );
NOR2XLTS U914 ( .A(n1725), .B(n894), .Y(n866) );
NOR2XLTS U915 ( .A(n885), .B(n1717), .Y(n826) );
OAI21XLTS U916 ( .A0(intDX[23]), .A1(n1661), .B0(intDX[22]), .Y(n1096) );
XOR2X1TS U917 ( .A(n768), .B(n725), .Y(n727) );
XOR2X1TS U918 ( .A(n821), .B(n819), .Y(n830) );
NOR2XLTS U919 ( .A(n1555), .B(n1728), .Y(n969) );
NAND2X1TS U920 ( .A(n695), .B(n696), .Y(n724) );
OR2X1TS U921 ( .A(n907), .B(n1012), .Y(n657) );
OAI211XLTS U922 ( .A0(Add_Subt_result[25]), .A1(n789), .B0(n788), .C0(n787),
.Y(n790) );
CLKINVX3TS U923 ( .A(n690), .Y(n1139) );
NOR2XLTS U924 ( .A(n1352), .B(n1351), .Y(n1357) );
OAI211XLTS U925 ( .A0(n1317), .A1(n1316), .B0(n1315), .C0(n1314), .Y(n1319)
);
OAI211XLTS U926 ( .A0(n917), .A1(n1754), .B0(n916), .C0(n1640), .Y(n918) );
OR2X1TS U927 ( .A(n907), .B(n1017), .Y(n1274) );
OAI211XLTS U928 ( .A0(n917), .A1(n1755), .B0(n911), .C0(n1640), .Y(n912) );
OAI21XLTS U929 ( .A0(n1663), .A1(n1160), .B0(n1121), .Y(n121) );
OAI21XLTS U930 ( .A0(n1702), .A1(n1160), .B0(n1125), .Y(n178) );
OAI21XLTS U931 ( .A0(n1164), .A1(n1722), .B0(n1148), .Y(n88) );
OAI211XLTS U932 ( .A0(n1749), .A1(n658), .B0(n1024), .C0(n1023), .Y(n248) );
OAI21XLTS U933 ( .A0(n1666), .A1(n1160), .B0(n1136), .Y(n169) );
OAI211XLTS U934 ( .A0(n658), .A1(n1753), .B0(n1011), .C0(n1010), .Y(n27) );
OAI211XLTS U935 ( .A0(n1504), .A1(n1043), .B0(n1042), .C0(n1041), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
OAI21XLTS U936 ( .A0(n1724), .A1(n1188), .B0(n1184), .Y(n119) );
CLKINVX3TS U937 ( .A(n1373), .Y(n1495) );
NAND4X1TS U938 ( .A(n1328), .B(n1299), .C(n1298), .D(n1297), .Y(n1300) );
AOI21X2TS U939 ( .A0(n751), .A1(n695), .B0(n745), .Y(n748) );
NAND2X1TS U940 ( .A(n738), .B(n737), .Y(n739) );
INVX2TS U941 ( .A(n746), .Y(n722) );
INVX2TS U942 ( .A(n765), .Y(n766) );
INVX2TS U943 ( .A(n736), .Y(n738) );
INVX4TS U944 ( .A(n1198), .Y(n1161) );
INVX4TS U945 ( .A(n690), .Y(n1147) );
INVX2TS U946 ( .A(n1375), .Y(n1376) );
INVX3TS U947 ( .A(n653), .Y(n1196) );
OAI21X1TS U948 ( .A0(n1334), .A1(n1759), .B0(n986), .Y(n70) );
INVX3TS U949 ( .A(n653), .Y(n1162) );
INVX3TS U950 ( .A(n653), .Y(n1128) );
INVX3TS U951 ( .A(n653), .Y(n1155) );
INVX3TS U952 ( .A(n653), .Y(n1190) );
INVX3TS U953 ( .A(n653), .Y(n1186) );
NAND2X4TS U954 ( .A(n1638), .B(n664), .Y(n907) );
XOR2X1TS U955 ( .A(n821), .B(n805), .Y(n812) );
NOR2X4TS U956 ( .A(n776), .B(Add_Subt_result[18]), .Y(n1306) );
INVX1TS U957 ( .A(n1174), .Y(n955) );
OAI211X1TS U958 ( .A0(intDX[8]), .A1(n1690), .B0(n1070), .C0(n1073), .Y(
n1084) );
NOR2X1TS U959 ( .A(n1103), .B(intDY[24]), .Y(n1044) );
NAND3X1TS U960 ( .A(n1690), .B(n1070), .C(intDX[8]), .Y(n1071) );
NOR2X1TS U961 ( .A(n1693), .B(n885), .Y(n828) );
MX2X2TS U962 ( .A(add_overflow_flag), .B(n1283), .S0(n661), .Y(n241) );
MX2X2TS U963 ( .A(Add_Subt_result[25]), .B(n900), .S0(n1450), .Y(n215) );
OAI2BB1X1TS U964 ( .A0N(n682), .A1N(n1334), .B0(n1321), .Y(n75) );
XOR2X2TS U965 ( .A(n770), .B(n769), .Y(n1209) );
OAI21X1TS U966 ( .A0(n1320), .A1(n1319), .B0(n1318), .Y(n1321) );
NAND3BX1TS U967 ( .AN(n1284), .B(n1206), .C(n1205), .Y(n1208) );
AOI21X2TS U968 ( .A0(n767), .A1(n691), .B0(n766), .Y(n770) );
OAI211X2TS U969 ( .A0(Add_Subt_result[3]), .A1(n780), .B0(n779), .C0(n1299),
.Y(n1320) );
XOR2X2TS U970 ( .A(n748), .B(n747), .Y(n1287) );
OAI21X1TS U971 ( .A0(n1164), .A1(n1703), .B0(n1151), .Y(n97) );
OAI21X1TS U972 ( .A0(n1164), .A1(n1706), .B0(n1153), .Y(n94) );
OAI21X1TS U973 ( .A0(n1164), .A1(n1705), .B0(n1152), .Y(n91) );
OAI21X1TS U974 ( .A0(n1703), .A1(n690), .B0(n1180), .Y(n98) );
OAI21X1TS U975 ( .A0(n1676), .A1(n690), .B0(n1193), .Y(n101) );
OAI21X1TS U976 ( .A0(n1667), .A1(n1192), .B0(n1131), .Y(n152) );
OAI21X1TS U977 ( .A0(n1663), .A1(n1188), .B0(n1167), .Y(n122) );
OAI21X1TS U978 ( .A0(n1670), .A1(n1188), .B0(n1126), .Y(n167) );
OAI21X1TS U979 ( .A0(n1669), .A1(n1188), .B0(n1143), .Y(n161) );
OAI21X1TS U980 ( .A0(n1722), .A1(n1188), .B0(n1182), .Y(n89) );
OAI21X1TS U981 ( .A0(n1719), .A1(n1202), .B0(n1133), .Y(n125) );
OAI211X1TS U982 ( .A0(n658), .A1(n1752), .B0(n1007), .C0(n1006), .Y(n19) );
OAI211X1TS U983 ( .A0(n1000), .A1(n1504), .B0(n1502), .C0(n995), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
OAI21X1TS U984 ( .A0(n1704), .A1(n1188), .B0(n1173), .Y(n113) );
OAI21X1TS U985 ( .A0(n1028), .A1(n1605), .B0(n1027), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI21X1TS U986 ( .A0(n1665), .A1(n1188), .B0(n1127), .Y(n164) );
OAI21X1TS U987 ( .A0(n1705), .A1(n1198), .B0(n1181), .Y(n92) );
OAI21X1TS U988 ( .A0(n1673), .A1(n1188), .B0(n1187), .Y(n116) );
OAI21X1TS U989 ( .A0(n1718), .A1(n690), .B0(n1194), .Y(n107) );
OAI21X1TS U990 ( .A0(n1668), .A1(n1188), .B0(n1166), .Y(n155) );
OAI21X1TS U991 ( .A0(n1706), .A1(n690), .B0(n1185), .Y(n95) );
OAI21X1TS U992 ( .A0(n1695), .A1(n1141), .B0(n1113), .Y(n133) );
OAI21X1TS U993 ( .A0(n1698), .A1(n1192), .B0(n1170), .Y(n128) );
OAI21X1TS U994 ( .A0(n1733), .A1(n1141), .B0(n1140), .Y(n136) );
OAI21X1TS U995 ( .A0(n1666), .A1(n1192), .B0(n1142), .Y(n170) );
OAI21X1TS U996 ( .A0(n1699), .A1(n1141), .B0(n1112), .Y(n130) );
OAI21X1TS U997 ( .A0(n1669), .A1(n1160), .B0(n1137), .Y(n160) );
OAI21X1TS U998 ( .A0(n1700), .A1(n1198), .B0(n1132), .Y(n146) );
OAI21X1TS U999 ( .A0(n1699), .A1(n1192), .B0(n1171), .Y(n131) );
OAI21X1TS U1000 ( .A0(n1700), .A1(n1141), .B0(n1117), .Y(n145) );
OAI211X1TS U1001 ( .A0(n1043), .A1(n1508), .B0(n1031), .C0(n1030), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
OAI21X1TS U1002 ( .A0(n1670), .A1(n1160), .B0(n1123), .Y(n166) );
OAI21X1TS U1003 ( .A0(n1702), .A1(n1192), .B0(n1129), .Y(n179) );
OAI21X1TS U1004 ( .A0(n1696), .A1(n1141), .B0(n1119), .Y(n139) );
OAI21X1TS U1005 ( .A0(n1697), .A1(n1198), .B0(n1168), .Y(n143) );
OAI21X1TS U1006 ( .A0(n1721), .A1(n1198), .B0(n1197), .Y(n104) );
OAI211X1TS U1007 ( .A0(n658), .A1(n1751), .B0(n1004), .C0(n1003), .Y(n23) );
OAI211X1TS U1008 ( .A0(n1043), .A1(n991), .B0(n1036), .C0(n1035), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
OAI21X1TS U1009 ( .A0(n1719), .A1(n1192), .B0(n1183), .Y(n124) );
OAI21X1TS U1010 ( .A0(n1695), .A1(n1192), .B0(n1169), .Y(n134) );
OAI21X1TS U1011 ( .A0(n1723), .A1(n1192), .B0(n1145), .Y(n173) );
OAI21X1TS U1012 ( .A0(n1701), .A1(n1192), .B0(n1130), .Y(n176) );
OAI21X1TS U1013 ( .A0(n1671), .A1(n1202), .B0(n1135), .Y(n110) );
OAI21X1TS U1014 ( .A0(n1696), .A1(n1198), .B0(n1172), .Y(n140) );
OAI21X1TS U1015 ( .A0(n1664), .A1(n1188), .B0(n1156), .Y(n158) );
OAI21X1TS U1016 ( .A0(n1733), .A1(n1192), .B0(n1191), .Y(n137) );
OAI21X1TS U1017 ( .A0(n1464), .A1(n1426), .B0(n1425), .Y(n1431) );
NAND3X1TS U1018 ( .A(n1623), .B(n1622), .C(n1640), .Y(n21) );
OAI21X1TS U1019 ( .A0(n1659), .A1(n1198), .B0(n1110), .Y(n149) );
INVX2TS U1020 ( .A(n1146), .Y(n1164) );
OAI21X1TS U1021 ( .A0(n1403), .A1(n1402), .B0(n1401), .Y(n1408) );
OAI211X1TS U1022 ( .A0(n1636), .A1(n1229), .B0(n1228), .C0(n1227), .Y(n1230)
);
OAI211X1TS U1023 ( .A0(n1016), .A1(n907), .B0(n1015), .C0(n1014), .Y(n43) );
NAND3X1TS U1024 ( .A(n1642), .B(n1641), .C(n1640), .Y(n33) );
NAND3X1TS U1025 ( .A(n1618), .B(n1617), .C(n1640), .Y(n17) );
NAND3X1TS U1026 ( .A(n1628), .B(n1627), .C(n1640), .Y(n25) );
OAI21X1TS U1027 ( .A0(n1510), .A1(n1605), .B0(n1502), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
OAI211X1TS U1028 ( .A0(n1021), .A1(n907), .B0(n1020), .C0(n1019), .Y(n47) );
OAI211X1TS U1029 ( .A0(n1638), .A1(n1717), .B0(n1252), .C0(n1251), .Y(n1253)
);
NAND3X1TS U1030 ( .A(n1633), .B(n1632), .C(n1640), .Y(n29) );
OAI211X1TS U1031 ( .A0(n658), .A1(n1748), .B0(n999), .C0(n998), .Y(n15) );
OAI211X1TS U1032 ( .A0(n1043), .A1(n1025), .B0(n984), .C0(n983), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
NOR2X4TS U1033 ( .A(n710), .B(n709), .Y(n759) );
AOI32X2TS U1034 ( .A0(n1586), .A1(n1585), .A2(n1584), .B0(n1583), .B1(n1591),
.Y(n1601) );
AOI32X2TS U1035 ( .A0(n1578), .A1(n1585), .A2(n1577), .B0(n1576), .B1(n1591),
.Y(n1599) );
OAI211X1TS U1036 ( .A0(n1179), .A1(n1178), .B0(n1177), .C0(n1176), .Y(n242)
);
INVX2TS U1037 ( .A(n768), .Y(n769) );
NOR2X4TS U1038 ( .A(Add_Subt_result[10]), .B(n777), .Y(n1296) );
NOR2X1TS U1039 ( .A(n907), .B(n1619), .Y(n1002) );
NOR2X1TS U1040 ( .A(n907), .B(n1614), .Y(n1005) );
INVX1TS U1041 ( .A(n1344), .Y(n1352) );
NOR2X1TS U1042 ( .A(n907), .B(n1624), .Y(n1008) );
NOR2X4TS U1043 ( .A(n907), .B(n996), .Y(n1241) );
NAND2X1TS U1044 ( .A(n1391), .B(n816), .Y(n818) );
OR2X2TS U1045 ( .A(n1636), .B(n996), .Y(n658) );
OAI21X1TS U1046 ( .A0(n1508), .A1(n1605), .B0(n1038), .Y(n990) );
INVX3TS U1047 ( .A(n674), .Y(n676) );
NOR2X1TS U1048 ( .A(n1311), .B(n1310), .Y(n1304) );
NOR2X1TS U1049 ( .A(n1555), .B(Add_Subt_result[25]), .Y(n989) );
OAI21X1TS U1050 ( .A0(n1404), .A1(n1401), .B0(n1405), .Y(n815) );
NOR2X4TS U1051 ( .A(n1636), .B(n1012), .Y(n906) );
NOR2X1TS U1052 ( .A(n1555), .B(n1737), .Y(n980) );
NOR2X1TS U1053 ( .A(n664), .B(Add_Subt_result[0]), .Y(n988) );
OAI31XLTS U1054 ( .A0(FS_Module_state_reg[0]), .A1(FS_Module_state_reg[1]),
.A2(FS_Module_state_reg[3]), .B0(n956), .Y(n957) );
INVX3TS U1055 ( .A(n1500), .Y(n1594) );
AND2X2TS U1056 ( .A(n1638), .B(n905), .Y(n1237) );
INVX2TS U1057 ( .A(n1289), .Y(n1336) );
INVX3TS U1058 ( .A(n1500), .Y(n1608) );
INVX1TS U1059 ( .A(n954), .Y(n697) );
INVX4TS U1060 ( .A(n1144), .Y(n653) );
AO22X1TS U1061 ( .A0(LZA_output[4]), .A1(n702), .B0(n665), .B1(
exp_oper_result[4]), .Y(n656) );
INVX2TS U1062 ( .A(n960), .Y(n1651) );
AND2X2TS U1063 ( .A(n904), .B(n903), .Y(n905) );
NOR2X1TS U1064 ( .A(n1715), .B(n894), .Y(n853) );
NAND2BX1TS U1065 ( .AN(Sgf_normalized_result[25]), .B(n894), .Y(n1279) );
NAND2BX1TS U1066 ( .AN(n689), .B(intDX[27]), .Y(n1046) );
NOR2X1TS U1067 ( .A(n1740), .B(n894), .Y(n890) );
NAND3X1TS U1068 ( .A(n1707), .B(n1045), .C(intDX[26]), .Y(n1047) );
NOR2X1TS U1069 ( .A(n1068), .B(intDY[10]), .Y(n1069) );
NOR2X1TS U1070 ( .A(n885), .B(n1741), .Y(n886) );
AOI211X1TS U1071 ( .A0(intDY[28]), .A1(n1723), .B0(n1051), .C0(n1049), .Y(
n1102) );
NOR2X1TS U1072 ( .A(n885), .B(n1731), .Y(n876) );
NOR2X1TS U1073 ( .A(n1582), .B(FS_Module_state_reg[3]), .Y(n904) );
OAI211X2TS U1074 ( .A0(intDX[12]), .A1(n1719), .B0(n1080), .C0(n1066), .Y(
n1082) );
NOR2X1TS U1075 ( .A(n885), .B(n1732), .Y(n873) );
OAI211X2TS U1076 ( .A0(intDX[20]), .A1(n1685), .B0(n1100), .C0(n1085), .Y(
n1094) );
NOR2X1TS U1077 ( .A(n1714), .B(n894), .Y(n854) );
NOR2X1TS U1078 ( .A(n885), .B(n1726), .Y(n869) );
NOR2X1TS U1079 ( .A(n1713), .B(n894), .Y(n862) );
NAND2BX1TS U1080 ( .AN(n962), .B(n961), .Y(n963) );
NOR3X2TS U1081 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]), .C(
n962), .Y(n1217) );
OR2X2TS U1082 ( .A(n899), .B(FS_Module_state_reg[3]), .Y(n1373) );
NOR2X1TS U1083 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[8]), .Y(n775) );
NAND2BX1TS U1084 ( .AN(intDX[21]), .B(intDY[21]), .Y(n1085) );
NAND2BX1TS U1085 ( .AN(intDX[19]), .B(intDY[19]), .Y(n1091) );
NAND2BX1TS U1086 ( .AN(intDX[27]), .B(intDY[27]), .Y(n1045) );
OR2X2TS U1087 ( .A(FSM_selector_B[1]), .B(FSM_selector_B[0]), .Y(n703) );
NAND2BX1TS U1088 ( .AN(intDX[24]), .B(intDY[24]), .Y(n1101) );
NOR2X1TS U1089 ( .A(r_mode[1]), .B(sign_final_result), .Y(n965) );
NAND2BX1TS U1090 ( .AN(intDX[9]), .B(intDY[9]), .Y(n1070) );
NAND2BX1TS U1091 ( .AN(intDX[13]), .B(intDY[13]), .Y(n1066) );
NOR3X1TS U1092 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]), .C(
FS_Module_state_reg[3]), .Y(n959) );
OR2X4TS U1093 ( .A(n1174), .B(n885), .Y(n1281) );
AOI21X2TS U1094 ( .A0(n1441), .A1(n838), .B0(n837), .Y(n1462) );
OAI21X1TS U1095 ( .A0(n1456), .A1(n1452), .B0(n1457), .Y(n837) );
XOR2X2TS U1096 ( .A(n1282), .B(n1281), .Y(n1283) );
NAND2X2TS U1097 ( .A(n1296), .B(n775), .Y(n783) );
NAND2X4TS U1098 ( .A(n1709), .B(n1302), .Y(n777) );
AOI31X1TS U1099 ( .A0(n1301), .A1(Add_Subt_result[0]), .A2(n1678), .B0(n1332), .Y(n779) );
NAND2X1TS U1100 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]),
.Y(n962) );
OAI2BB2XLTS U1101 ( .B0(intDY[12]), .B1(n1067), .A0N(intDX[13]), .A1N(n1686),
.Y(n1079) );
OAI2BB2XLTS U1102 ( .B0(n1075), .B1(n1082), .A0N(n1074), .A1N(n1073), .Y(
n1078) );
XOR2X1TS U1103 ( .A(n768), .B(n717), .Y(n721) );
AO22XLTS U1104 ( .A0(LZA_output[4]), .A1(n702), .B0(n666), .B1(DmP[27]), .Y(
n717) );
XOR2X1TS U1105 ( .A(n768), .B(n716), .Y(n719) );
AO22XLTS U1106 ( .A0(LZA_output[3]), .A1(n702), .B0(n666), .B1(DmP[26]), .Y(
n716) );
MX2X1TS U1107 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n825), .Y(n811) );
OAI21X2TS U1108 ( .A0(n1378), .A1(n1375), .B0(n1379), .Y(n1390) );
MX2X1TS U1109 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n878), .Y(
n855) );
INVX2TS U1110 ( .A(n741), .Y(n728) );
NAND2X1TS U1111 ( .A(n761), .B(n760), .Y(n763) );
INVX2TS U1112 ( .A(n759), .Y(n761) );
XNOR2X2TS U1113 ( .A(n756), .B(n755), .Y(n1290) );
NAND2X1TS U1114 ( .A(n754), .B(n753), .Y(n755) );
OAI21X1TS U1115 ( .A0(n762), .A1(n759), .B0(n760), .Y(n756) );
INVX2TS U1116 ( .A(n752), .Y(n754) );
NAND4XLTS U1117 ( .A(n933), .B(n932), .C(n931), .D(n930), .Y(n952) );
NAND4XLTS U1118 ( .A(n925), .B(n924), .C(n923), .D(n922), .Y(n953) );
NAND4XLTS U1119 ( .A(n941), .B(n940), .C(n939), .D(n938), .Y(n951) );
AOI2BB2XLTS U1120 ( .B0(intDX[3]), .B1(n1680), .A0N(intDY[2]), .A1N(n1059),
.Y(n1060) );
OAI21XLTS U1121 ( .A0(intDX[3]), .A1(n1680), .B0(intDX[2]), .Y(n1059) );
CLKXOR2X2TS U1122 ( .A(n768), .B(n704), .Y(n710) );
AO22XLTS U1123 ( .A0(LZA_output[1]), .A1(n702), .B0(n665), .B1(DmP[24]), .Y(
n704) );
MX2X1TS U1124 ( .A(DMP[24]), .B(exp_oper_result[1]), .S0(n891), .Y(n709) );
XOR2X1TS U1125 ( .A(n768), .B(n705), .Y(n712) );
AO22XLTS U1126 ( .A0(n682), .A1(n702), .B0(n666), .B1(DmP[25]), .Y(n705) );
MX2X1TS U1127 ( .A(DMP[25]), .B(exp_oper_result[2]), .S0(n891), .Y(n711) );
MX2X1TS U1128 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n878), .Y(
n857) );
MX2X1TS U1129 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n878), .Y(
n867) );
MX2X1TS U1130 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n825), .Y(n809) );
MX2X1TS U1131 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n825), .Y(n831) );
MX2X1TS U1132 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n825), .Y(n813) );
MX2X1TS U1133 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n825), .Y(n807) );
MX2X1TS U1134 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n825), .Y(n799) );
MX2X1TS U1135 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n878), .Y(
n843) );
MX2X1TS U1136 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(n825), .Y(
n835) );
MX2X1TS U1137 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n825), .Y(
n839) );
MX2X1TS U1138 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n825), .Y(n829) );
MX2X1TS U1139 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n825), .Y(n833) );
MX2X1TS U1140 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n878), .Y(
n870) );
MX2X1TS U1141 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n878), .Y(
n863) );
NAND3X1TS U1142 ( .A(n1327), .B(n1662), .C(n1691), .Y(n1329) );
AOI32X1TS U1143 ( .A0(n1108), .A1(n1107), .A2(n1106), .B0(n1105), .B1(n1108),
.Y(n1109) );
AOI2BB2X1TS U1144 ( .B0(n1053), .B1(n1102), .A0N(n1052), .A1N(n1051), .Y(
n1108) );
INVX2TS U1145 ( .A(n1165), .Y(n1141) );
NAND2BXLTS U1146 ( .AN(Add_Subt_result[6]), .B(n1736), .Y(n1293) );
INVX2TS U1147 ( .A(n1165), .Y(n1160) );
CLKAND2X2TS U1148 ( .A(n891), .B(Sgf_normalized_result[0]), .Y(n797) );
OR2X1TS U1149 ( .A(n858), .B(n857), .Y(n1436) );
AO22XLTS U1150 ( .A0(n1603), .A1(Add_Subt_result[4]), .B0(DmP[19]), .B1(
n1727), .Y(n977) );
CLKAND2X2TS U1151 ( .A(n1179), .B(n1217), .Y(n1211) );
CLKAND2X2TS U1152 ( .A(n967), .B(Sgf_normalized_result[1]), .Y(n793) );
OR2X1TS U1153 ( .A(n888), .B(n887), .Y(n1347) );
OR2X1TS U1154 ( .A(n880), .B(n879), .Y(n1370) );
INVX2TS U1155 ( .A(n1237), .Y(n1636) );
OR2X1TS U1156 ( .A(n864), .B(n863), .Y(n1421) );
NOR2BX2TS U1157 ( .AN(n1306), .B(n1305), .Y(n1327) );
INVX2TS U1158 ( .A(n776), .Y(n1323) );
MX2X1TS U1159 ( .A(DMP[23]), .B(exp_oper_result[0]), .S0(n891), .Y(n758) );
AO21XLTS U1160 ( .A0(DmP[23]), .A1(n1692), .B0(n972), .Y(n708) );
NAND2X1TS U1161 ( .A(n695), .B(n749), .Y(n750) );
NAND2X1TS U1162 ( .A(n696), .B(n746), .Y(n747) );
XNOR2X2TS U1163 ( .A(n743), .B(n742), .Y(n1286) );
NAND2X1TS U1164 ( .A(n692), .B(n741), .Y(n742) );
XNOR2X2TS U1165 ( .A(n767), .B(n735), .Y(n1284) );
INVX2TS U1166 ( .A(n783), .Y(n1294) );
NOR2X2TS U1167 ( .A(Add_Subt_result[11]), .B(n1329), .Y(n1302) );
NAND2X1TS U1168 ( .A(n1324), .B(n1326), .Y(n1316) );
BUFX3TS U1169 ( .A(n1165), .Y(n1189) );
BUFX3TS U1170 ( .A(n1165), .Y(n1146) );
AOI2BB2XLTS U1171 ( .B0(intDX[31]), .B1(n653), .A0N(n1199), .A1N(n1198), .Y(
n1200) );
MX2X1TS U1172 ( .A(Add_Subt_result[5]), .B(n1395), .S0(n661), .Y(n221) );
MX2X1TS U1173 ( .A(Add_Subt_result[15]), .B(n1451), .S0(n1495), .Y(n231) );
MX2X1TS U1174 ( .A(Add_Subt_result[12]), .B(n1496), .S0(n1495), .Y(n228) );
NAND2BXLTS U1175 ( .AN(intDX[2]), .B(intDY[2]), .Y(n1057) );
NAND2BXLTS U1176 ( .AN(intDY[9]), .B(intDX[9]), .Y(n1072) );
NOR2X1TS U1177 ( .A(n1469), .B(n1471), .Y(n848) );
XOR2X1TS U1178 ( .A(n768), .B(n729), .Y(n731) );
CLKAND2X2TS U1179 ( .A(n666), .B(DmP[29]), .Y(n729) );
MX2X1TS U1180 ( .A(DMP[29]), .B(exp_oper_result[6]), .S0(n891), .Y(n730) );
MX2X1TS U1181 ( .A(DMP[27]), .B(exp_oper_result[4]), .S0(n891), .Y(n720) );
MX2X1TS U1182 ( .A(DMP[26]), .B(exp_oper_result[3]), .S0(n891), .Y(n718) );
NOR2X1TS U1183 ( .A(n759), .B(n752), .Y(n715) );
OAI21X1TS U1184 ( .A0(n752), .A1(n760), .B0(n753), .Y(n713) );
CLKAND2X2TS U1185 ( .A(n666), .B(DmP[28]), .Y(n725) );
MX2X1TS U1186 ( .A(DMP[28]), .B(exp_oper_result[5]), .S0(n891), .Y(n726) );
XOR2X1TS U1187 ( .A(n768), .B(n732), .Y(n734) );
CLKAND2X2TS U1188 ( .A(n666), .B(DmP[30]), .Y(n732) );
MX2X1TS U1189 ( .A(DMP[30]), .B(exp_oper_result[7]), .S0(n891), .Y(n733) );
OAI21XLTS U1190 ( .A0(intDX[21]), .A1(n1708), .B0(intDX[20]), .Y(n1088) );
NAND3BX1TS U1191 ( .AN(n1089), .B(n1087), .C(n1086), .Y(n1107) );
MX2X1TS U1192 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n894), .Y(
n883) );
AO22XLTS U1193 ( .A0(n1603), .A1(Add_Subt_result[8]), .B0(DmP[15]), .B1(
n1560), .Y(n976) );
MX2X1TS U1194 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n878), .Y(
n874) );
MX2X1TS U1195 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n878), .Y(
n845) );
NOR2X1TS U1196 ( .A(n1477), .B(n1490), .Y(n1465) );
NAND2X1TS U1197 ( .A(n1440), .B(n838), .Y(n1463) );
MX2X1TS U1198 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n878), .Y(
n841) );
MX2X1TS U1199 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(
FSM_selector_D), .Y(n887) );
MX2X1TS U1200 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n878), .Y(
n879) );
MX2X1TS U1201 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n891), .Y(
n892) );
AO22XLTS U1202 ( .A0(n1603), .A1(Add_Subt_result[13]), .B0(DmP[10]), .B1(
n1560), .Y(n1528) );
AO22XLTS U1203 ( .A0(n1603), .A1(Add_Subt_result[12]), .B0(DmP[11]), .B1(
n1560), .Y(n1523) );
NOR2X2TS U1204 ( .A(n712), .B(n711), .Y(n752) );
NAND2X2TS U1205 ( .A(n710), .B(n709), .Y(n760) );
NAND2X1TS U1206 ( .A(n712), .B(n711), .Y(n753) );
NAND2X1TS U1207 ( .A(n719), .B(n718), .Y(n749) );
NAND2X1TS U1208 ( .A(n731), .B(n730), .Y(n737) );
NAND2X1TS U1209 ( .A(n721), .B(n720), .Y(n746) );
INVX2TS U1210 ( .A(n749), .Y(n745) );
NAND2X1TS U1211 ( .A(n734), .B(n733), .Y(n765) );
AO22XLTS U1212 ( .A0(n670), .A1(Add_Subt_result[17]), .B0(DmP[6]), .B1(n1727), .Y(n1549) );
AO22XLTS U1213 ( .A0(n670), .A1(Add_Subt_result[20]), .B0(DmP[3]), .B1(n1727), .Y(n1566) );
NAND4XLTS U1214 ( .A(n949), .B(n948), .C(n947), .D(n946), .Y(n950) );
AO22XLTS U1215 ( .A0(n1603), .A1(Add_Subt_result[5]), .B0(DmP[18]), .B1(
n1727), .Y(n978) );
AOI222X1TS U1216 ( .A0(n1039), .A1(n1038), .B0(n1590), .B1(n1499), .C0(n1498), .C1(n687), .Y(n1510) );
INVX2TS U1217 ( .A(n1651), .Y(n1269) );
AO22XLTS U1218 ( .A0(n670), .A1(Add_Subt_result[21]), .B0(DmP[2]), .B1(n1727), .Y(n1571) );
AOI2BB1XLTS U1219 ( .A0N(n784), .A1N(Add_Subt_result[23]), .B0(
Add_Subt_result[24]), .Y(n789) );
NAND3XLTS U1220 ( .A(n1323), .B(Add_Subt_result[16]), .C(n1750), .Y(n787) );
CLKAND2X2TS U1221 ( .A(Add_Subt_result[8]), .B(n1738), .Y(n782) );
NAND3XLTS U1222 ( .A(n1652), .B(n1214), .C(n1213), .Y(n247) );
AOI211XLTS U1223 ( .A0(FS_Module_state_reg[1]), .A1(n1215), .B0(n1211), .C0(
n1216), .Y(n1214) );
NAND4XLTS U1224 ( .A(n1261), .B(n1260), .C(n1259), .D(n1258), .Y(n51) );
NAND4XLTS U1225 ( .A(n1261), .B(n1257), .C(n1256), .D(n1255), .Y(n55) );
MX2X1TS U1226 ( .A(Data_X[0]), .B(intDX[0]), .S0(n1652), .Y(n183) );
MX2X1TS U1227 ( .A(Add_Subt_result[22]), .B(n1364), .S0(n661), .Y(n238) );
AO22XLTS U1228 ( .A0(n1653), .A1(Data_Y[0]), .B0(n1650), .B1(intDY[0]), .Y(
n90) );
AO22XLTS U1229 ( .A0(n1647), .A1(Data_Y[9]), .B0(n1269), .B1(intDY[9]), .Y(
n117) );
AO22XLTS U1230 ( .A0(n1647), .A1(Data_Y[4]), .B0(n1646), .B1(intDY[4]), .Y(
n102) );
OAI21XLTS U1231 ( .A0(n1164), .A1(n1673), .B0(n1154), .Y(n115) );
OAI21XLTS U1232 ( .A0(n1164), .A1(n1704), .B0(n1150), .Y(n112) );
MX2X1TS U1233 ( .A(n1300), .B(LZA_output[4]), .S0(n1334), .Y(n72) );
OAI21XLTS U1234 ( .A0(n1665), .A1(n1160), .B0(n1122), .Y(n163) );
OAI21XLTS U1235 ( .A0(n1664), .A1(n1160), .B0(n1120), .Y(n157) );
AO21XLTS U1236 ( .A0(n1022), .A1(n1237), .B0(n918), .Y(n12) );
AO21XLTS U1237 ( .A0(LZA_output[3]), .A1(n1334), .B0(n1309), .Y(n76) );
MX2X1TS U1238 ( .A(exp_oper_result[6]), .B(n1285), .S0(n1289), .Y(n85) );
MX2X1TS U1239 ( .A(exp_oper_result[5]), .B(n1286), .S0(n1289), .Y(n84) );
MX2X1TS U1240 ( .A(exp_oper_result[7]), .B(n1284), .S0(n1289), .Y(n78) );
NAND4XLTS U1241 ( .A(n1265), .B(n1264), .C(n1263), .D(n1274), .Y(n39) );
NAND4XLTS U1242 ( .A(n1268), .B(n1267), .C(n1266), .D(n1274), .Y(n35) );
NAND4XLTS U1243 ( .A(n1277), .B(n1276), .C(n1275), .D(n1274), .Y(n31) );
MX2X1TS U1244 ( .A(exp_oper_result[2]), .B(n1290), .S0(n1289), .Y(n81) );
MX2X1TS U1245 ( .A(n1291), .B(exp_oper_result[1]), .S0(n1336), .Y(n80) );
MX2X1TS U1246 ( .A(n1337), .B(exp_oper_result[0]), .S0(n1336), .Y(n79) );
MX2X1TS U1247 ( .A(exp_oper_result[3]), .B(n1288), .S0(n1289), .Y(n82) );
MX2X1TS U1248 ( .A(Data_X[1]), .B(intDX[1]), .S0(n1648), .Y(n184) );
MX2X1TS U1249 ( .A(exp_oper_result[4]), .B(n1287), .S0(n1289), .Y(n83) );
AO22XLTS U1250 ( .A0(n1647), .A1(Data_Y[3]), .B0(n1269), .B1(intDY[3]), .Y(
n99) );
AO22XLTS U1251 ( .A0(n1647), .A1(Data_Y[1]), .B0(n1648), .B1(intDY[1]), .Y(
n93) );
MX2X1TS U1252 ( .A(Add_Subt_result[0]), .B(n1224), .S0(n1495), .Y(n216) );
MX2X1TS U1253 ( .A(Add_Subt_result[16]), .B(n1439), .S0(n661), .Y(n232) );
MX2X1TS U1254 ( .A(Add_Subt_result[18]), .B(n1415), .S0(n661), .Y(n234) );
MX2X1TS U1255 ( .A(Add_Subt_result[4]), .B(n1383), .S0(n1450), .Y(n220) );
MX2X1TS U1256 ( .A(Add_Subt_result[20]), .B(n1389), .S0(n1450), .Y(n236) );
MX2X1TS U1257 ( .A(Add_Subt_result[8]), .B(n1432), .S0(n1495), .Y(n224) );
MX2X1TS U1258 ( .A(Add_Subt_result[6]), .B(n1409), .S0(n1495), .Y(n222) );
AO22XLTS U1259 ( .A0(n1647), .A1(Data_Y[10]), .B0(n1646), .B1(intDY[10]),
.Y(n120) );
AO22XLTS U1260 ( .A0(n1651), .A1(Data_Y[2]), .B0(n1652), .B1(intDY[2]), .Y(
n96) );
AO22XLTS U1261 ( .A0(n1653), .A1(Data_X[12]), .B0(n1652), .B1(intDX[12]),
.Y(n195) );
AO22XLTS U1262 ( .A0(n1649), .A1(Data_Y[16]), .B0(n1646), .B1(intDY[16]),
.Y(n138) );
AO22XLTS U1263 ( .A0(n1653), .A1(Data_Y[24]), .B0(n1646), .B1(intDY[24]),
.Y(n162) );
AO22XLTS U1264 ( .A0(n1647), .A1(Data_Y[6]), .B0(n1648), .B1(intDY[6]), .Y(
n108) );
AO22XLTS U1265 ( .A0(n1653), .A1(Data_Y[28]), .B0(n1646), .B1(intDY[28]),
.Y(n174) );
MX2X1TS U1266 ( .A(Add_Subt_result[3]), .B(n1368), .S0(n1495), .Y(n219) );
AO22XLTS U1267 ( .A0(n1647), .A1(Data_Y[5]), .B0(n1650), .B1(intDY[5]), .Y(
n105) );
OR2X1TS U1268 ( .A(n1211), .B(n967), .Y(n245) );
MX2X1TS U1269 ( .A(Data_X[31]), .B(intDX[31]), .S0(n1646), .Y(n182) );
MX2X1TS U1270 ( .A(add_subt), .B(intAS), .S0(n1269), .Y(n181) );
AO22XLTS U1271 ( .A0(n1649), .A1(Data_Y[13]), .B0(n1648), .B1(intDY[13]),
.Y(n129) );
MX2X1TS U1272 ( .A(Data_X[3]), .B(intDX[3]), .S0(n1648), .Y(n186) );
AO22XLTS U1273 ( .A0(final_result_ieee[6]), .A1(n1203), .B0(
Sgf_normalized_result[8]), .B1(n1497), .Y(n1744) );
AO22XLTS U1274 ( .A0(final_result_ieee[7]), .A1(n1643), .B0(
Sgf_normalized_result[9]), .B1(n1497), .Y(n1745) );
AO22XLTS U1275 ( .A0(final_result_ieee[8]), .A1(n1203), .B0(
Sgf_normalized_result[10]), .B1(n1497), .Y(n1746) );
AO22XLTS U1276 ( .A0(final_result_ieee[9]), .A1(n1643), .B0(
Sgf_normalized_result[11]), .B1(n1497), .Y(n1747) );
AO22XLTS U1277 ( .A0(Sgf_normalized_result[2]), .A1(n1497), .B0(
final_result_ieee[0]), .B1(n1203), .Y(n18) );
AO22XLTS U1278 ( .A0(n1203), .A1(final_result_ieee[1]), .B0(
Sgf_normalized_result[3]), .B1(n1497), .Y(n22) );
AO22XLTS U1279 ( .A0(n1643), .A1(final_result_ieee[2]), .B0(
Sgf_normalized_result[4]), .B1(n1497), .Y(n26) );
AO22XLTS U1280 ( .A0(n1203), .A1(final_result_ieee[3]), .B0(
Sgf_normalized_result[5]), .B1(n1497), .Y(n30) );
AO22XLTS U1281 ( .A0(n1643), .A1(final_result_ieee[4]), .B0(
Sgf_normalized_result[6]), .B1(n1497), .Y(n34) );
AO22XLTS U1282 ( .A0(n1643), .A1(final_result_ieee[5]), .B0(
Sgf_normalized_result[7]), .B1(n1497), .Y(n38) );
OAI2BB2XLTS U1283 ( .B0(n1725), .B1(n672), .A0N(final_result_ieee[16]),
.A1N(n1203), .Y(n36) );
OAI2BB2XLTS U1284 ( .B0(n1713), .B1(n673), .A0N(final_result_ieee[15]),
.A1N(n1643), .Y(n40) );
OAI2BB2XLTS U1285 ( .B0(n1714), .B1(n672), .A0N(final_result_ieee[14]),
.A1N(n1203), .Y(n44) );
OAI2BB2XLTS U1286 ( .B0(n1715), .B1(n673), .A0N(final_result_ieee[13]),
.A1N(n1643), .Y(n48) );
AO22XLTS U1287 ( .A0(n1644), .A1(n964), .B0(n1629), .B1(
final_result_ieee[31]), .Y(n68) );
AO22XLTS U1288 ( .A0(n1649), .A1(Data_Y[15]), .B0(n1269), .B1(intDY[15]),
.Y(n135) );
AO22XLTS U1289 ( .A0(n1653), .A1(Data_Y[23]), .B0(n1652), .B1(intDY[23]),
.Y(n159) );
AO22XLTS U1290 ( .A0(n1649), .A1(Data_Y[19]), .B0(n1650), .B1(intDY[19]),
.Y(n147) );
MX2X1TS U1291 ( .A(Data_X[9]), .B(intDX[9]), .S0(n1269), .Y(n192) );
AO22XLTS U1292 ( .A0(n1653), .A1(Data_Y[29]), .B0(n1650), .B1(intDY[29]),
.Y(n177) );
MX2X1TS U1293 ( .A(Data_X[7]), .B(intDX[7]), .S0(n1650), .Y(n190) );
OAI21XLTS U1294 ( .A0(n1373), .A1(FS_Module_state_reg[0]), .B0(n1560), .Y(
n243) );
MX2X1TS U1295 ( .A(Data_X[4]), .B(intDX[4]), .S0(n1269), .Y(n187) );
MX2X1TS U1296 ( .A(Add_Subt_result[2]), .B(n1358), .S0(n1495), .Y(n218) );
MX2X1TS U1297 ( .A(Add_Subt_result[1]), .B(n1345), .S0(n662), .Y(n217) );
AO22XLTS U1298 ( .A0(n1649), .A1(Data_Y[14]), .B0(n1652), .B1(intDY[14]),
.Y(n132) );
AO22XLTS U1299 ( .A0(n1647), .A1(Data_Y[11]), .B0(n1650), .B1(intDY[11]),
.Y(n123) );
AO22XLTS U1300 ( .A0(n1649), .A1(Data_Y[22]), .B0(n1269), .B1(intDY[22]),
.Y(n156) );
AO22XLTS U1301 ( .A0(n1649), .A1(Data_Y[20]), .B0(n1648), .B1(intDY[20]),
.Y(n150) );
AO22XLTS U1302 ( .A0(n1653), .A1(Data_Y[25]), .B0(n1269), .B1(intDY[25]),
.Y(n165) );
AO22XLTS U1303 ( .A0(n1649), .A1(Data_Y[17]), .B0(n1650), .B1(intDY[17]),
.Y(n141) );
AO22XLTS U1304 ( .A0(n1647), .A1(Data_Y[8]), .B0(n1652), .B1(intDY[8]), .Y(
n114) );
MX2X1TS U1305 ( .A(Add_Subt_result[13]), .B(n1485), .S0(n661), .Y(n229) );
NAND4XLTS U1306 ( .A(n1261), .B(n1247), .C(n1246), .D(n1245), .Y(n53) );
MX2X1TS U1307 ( .A(Data_X[8]), .B(intDX[8]), .S0(n1650), .Y(n191) );
MX2X1TS U1308 ( .A(Data_X[2]), .B(intDX[2]), .S0(n1650), .Y(n185) );
AO22XLTS U1309 ( .A0(n1653), .A1(Data_Y[26]), .B0(n1648), .B1(intDY[26]),
.Y(n168) );
AO22XLTS U1310 ( .A0(n1649), .A1(Data_Y[21]), .B0(n1652), .B1(intDY[21]),
.Y(n153) );
AO22XLTS U1311 ( .A0(n1653), .A1(Data_Y[30]), .B0(n1648), .B1(intDY[30]),
.Y(n180) );
AO22XLTS U1312 ( .A0(n1649), .A1(Data_Y[18]), .B0(n1646), .B1(intDY[18]),
.Y(n144) );
NAND4XLTS U1313 ( .A(n1261), .B(n1235), .C(n1234), .D(n1233), .Y(n41) );
NAND4XLTS U1314 ( .A(n1261), .B(n1240), .C(n1239), .D(n1238), .Y(n45) );
NAND4XLTS U1315 ( .A(n1261), .B(n1244), .C(n1243), .D(n1242), .Y(n49) );
NAND4XLTS U1316 ( .A(n1261), .B(n1250), .C(n1249), .D(n1248), .Y(n57) );
MX2X1TS U1317 ( .A(Data_X[6]), .B(intDX[6]), .S0(n1648), .Y(n189) );
MX2X1TS U1318 ( .A(Data_X[5]), .B(intDX[5]), .S0(n1652), .Y(n188) );
AO21XLTS U1319 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n1230), .Y(n37)
);
MX2X1TS U1320 ( .A(Add_Subt_result[23]), .B(n1350), .S0(n662), .Y(n239) );
MX2X1TS U1321 ( .A(Add_Subt_result[10]), .B(n1461), .S0(n1495), .Y(n226) );
MX2X1TS U1322 ( .A(Add_Subt_result[11]), .B(n1480), .S0(n662), .Y(n227) );
MX2X1TS U1323 ( .A(Add_Subt_result[21]), .B(n1374), .S0(n1450), .Y(n237) );
MX2X1TS U1324 ( .A(Add_Subt_result[7]), .B(n1419), .S0(n662), .Y(n223) );
MX2X1TS U1325 ( .A(Add_Subt_result[24]), .B(n1343), .S0(n662), .Y(n240) );
MX2X1TS U1326 ( .A(Add_Subt_result[9]), .B(n1446), .S0(n662), .Y(n225) );
MX2X1TS U1327 ( .A(Add_Subt_result[19]), .B(n1400), .S0(n1450), .Y(n235) );
AO21XLTS U1328 ( .A0(n997), .A1(n1237), .B0(n912), .Y(n14) );
MX2X1TS U1329 ( .A(Add_Subt_result[17]), .B(n1424), .S0(n1450), .Y(n233) );
AND3X1TS U1330 ( .A(n1323), .B(n1322), .C(Add_Subt_result[15]), .Y(n1333) );
AO22XLTS U1331 ( .A0(n1327), .A1(Add_Subt_result[14]), .B0(n1326), .B1(n1325), .Y(n1331) );
AOI21X1TS U1332 ( .A0(n1284), .A1(n771), .B0(n1209), .Y(n773) );
AOI2BB2X1TS U1333 ( .B0(n1757), .B1(n1334), .A0N(n1320), .A1N(n792), .Y(n73)
);
NAND2BX1TS U1334 ( .AN(n693), .B(n791), .Y(n792) );
AO21XLTS U1335 ( .A0(n1302), .A1(n782), .B0(n781), .Y(n693) );
AOI31XLTS U1336 ( .A0(Add_Subt_result[6]), .A1(n1294), .A2(n1736), .B0(n790),
.Y(n791) );
AO21XLTS U1337 ( .A0(n1311), .A1(n1709), .B0(n1310), .Y(n1315) );
MX2X1TS U1338 ( .A(Data_Y[31]), .B(intDY[31]), .S0(n1646), .Y(n87) );
AO22XLTS U1339 ( .A0(n1653), .A1(Data_Y[27]), .B0(n1646), .B1(n689), .Y(n171) );
AOI2BB1XLTS U1340 ( .A0N(n958), .A1N(n957), .B0(n1215), .Y(n214) );
NAND4BXLTS U1341 ( .AN(n1221), .B(n1220), .C(n1336), .D(n1219), .Y(n246) );
AOI211XLTS U1342 ( .A0(n1218), .A1(n655), .B0(n1217), .C0(n1216), .Y(n1219)
);
XOR2X1TS U1343 ( .A(n768), .B(n708), .Y(n757) );
NAND2X4TS U1344 ( .A(n1210), .B(n908), .Y(n1638) );
INVX2TS U1345 ( .A(n1555), .Y(n1604) );
INVX2TS U1346 ( .A(n663), .Y(n1603) );
BUFX3TS U1347 ( .A(n690), .Y(n1198) );
INVX2TS U1348 ( .A(n1025), .Y(n1602) );
NOR3X2TS U1349 ( .A(overflow_flag), .B(underflow_flag), .C(n1629), .Y(n659)
);
INVX2TS U1350 ( .A(n1373), .Y(n661) );
INVX2TS U1351 ( .A(n1373), .Y(n662) );
INVX2TS U1352 ( .A(n905), .Y(n663) );
INVX2TS U1353 ( .A(n905), .Y(n664) );
INVX2TS U1354 ( .A(n703), .Y(n665) );
INVX2TS U1355 ( .A(n703), .Y(n666) );
INVX2TS U1356 ( .A(n657), .Y(n667) );
INVX2TS U1357 ( .A(n657), .Y(n668) );
INVX2TS U1358 ( .A(n1555), .Y(n669) );
INVX2TS U1359 ( .A(n663), .Y(n670) );
INVX2TS U1360 ( .A(n659), .Y(n671) );
INVX2TS U1361 ( .A(n659), .Y(n672) );
INVX2TS U1362 ( .A(n659), .Y(n673) );
INVX2TS U1363 ( .A(n1272), .Y(n674) );
INVX2TS U1364 ( .A(n674), .Y(n675) );
AOI211X1TS U1365 ( .A0(n1218), .A1(n1212), .B0(n1217), .C0(n1175), .Y(n956)
);
AOI211X1TS U1366 ( .A0(n1306), .A1(n1305), .B0(n1304), .C0(n1303), .Y(n1307)
);
OAI21XLTS U1367 ( .A0(n1697), .A1(n1141), .B0(n1111), .Y(n142) );
OAI21XLTS U1368 ( .A0(n1659), .A1(n1141), .B0(n1118), .Y(n148) );
OAI21XLTS U1369 ( .A0(n1667), .A1(n1141), .B0(n1116), .Y(n151) );
OAI21XLTS U1370 ( .A0(n1668), .A1(n1141), .B0(n1115), .Y(n154) );
OAI21XLTS U1371 ( .A0(n1723), .A1(n1160), .B0(n1138), .Y(n172) );
OAI21XLTS U1372 ( .A0(n1701), .A1(n1160), .B0(n1124), .Y(n175) );
INVX2TS U1373 ( .A(n660), .Y(n677) );
OAI21XLTS U1374 ( .A0(n1164), .A1(n1676), .B0(n1158), .Y(n100) );
OAI21XLTS U1375 ( .A0(n1164), .A1(n1721), .B0(n1163), .Y(n103) );
OAI21XLTS U1376 ( .A0(n1160), .A1(n1718), .B0(n1159), .Y(n106) );
OAI21XLTS U1377 ( .A0(n1164), .A1(n1675), .B0(n1149), .Y(n109) );
OAI21XLTS U1378 ( .A0(n1164), .A1(n1724), .B0(n1157), .Y(n118) );
INVX2TS U1379 ( .A(n1602), .Y(n678) );
INVX2TS U1380 ( .A(n678), .Y(n679) );
INVX2TS U1381 ( .A(n678), .Y(n680) );
BUFX3TS U1382 ( .A(n1782), .Y(n1781) );
AOI221X1TS U1383 ( .A0(n1670), .A1(intDY[26]), .B0(intDY[1]), .B1(n1705),
.C0(n936), .Y(n939) );
AOI221X1TS U1384 ( .A0(n1701), .A1(intDY[29]), .B0(n689), .B1(n1666), .C0(
n927), .Y(n932) );
MXI2X1TS U1385 ( .A(n1760), .B(n773), .S0(n1289), .Y(n77) );
INVX2TS U1386 ( .A(n656), .Y(n681) );
OA21X2TS U1387 ( .A0(n1175), .A1(n1207), .B0(add_overflow_flag), .Y(n1038)
);
OAI21X2TS U1388 ( .A0(n1210), .A1(n1560), .B0(n908), .Y(n1175) );
NOR2X2TS U1389 ( .A(n989), .B(n988), .Y(n1499) );
OAI22X2TS U1390 ( .A0(n910), .A1(n1582), .B0(n962), .B1(n909), .Y(n1207) );
NAND2X1TS U1391 ( .A(n700), .B(n1712), .Y(n910) );
INVX2TS U1392 ( .A(n1504), .Y(n1600) );
BUFX3TS U1393 ( .A(n1781), .Y(n1786) );
BUFX3TS U1394 ( .A(n1790), .Y(n1780) );
INVX2TS U1395 ( .A(n654), .Y(n682) );
INVX2TS U1396 ( .A(n658), .Y(n683) );
INVX2TS U1397 ( .A(n658), .Y(n684) );
INVX2TS U1398 ( .A(n658), .Y(n685) );
AOI22X2TS U1399 ( .A0(n1608), .A1(n1507), .B0(n1026), .B1(n1605), .Y(n1034)
);
AOI22X2TS U1400 ( .A0(n1608), .A1(n1509), .B0(n992), .B1(n1500), .Y(n1032)
);
AOI22X2TS U1401 ( .A0(n1608), .A1(n1524), .B0(n1507), .B1(n1605), .Y(n1520)
);
AOI21X2TS U1402 ( .A0(n669), .A1(Add_Subt_result[21]), .B0(n977), .Y(n1507)
);
AOI221X1TS U1403 ( .A0(n1722), .A1(intDY[0]), .B0(intDY[28]), .B1(n1723),
.C0(n937), .Y(n938) );
OAI31X1TS U1404 ( .A0(Add_Subt_result[5]), .A1(Add_Subt_result[9]), .A2(
Add_Subt_result[8]), .B0(n1296), .Y(n1297) );
NAND2BX2TS U1405 ( .AN(Add_Subt_result[5]), .B(n1313), .Y(n778) );
AOI221X1TS U1406 ( .A0(n1706), .A1(intDY[2]), .B0(intDY[9]), .B1(n1673),
.C0(n944), .Y(n947) );
AOI222X1TS U1407 ( .A0(intDY[4]), .A1(n1676), .B0(n1061), .B1(n1060), .C0(
intDY[5]), .C1(n1721), .Y(n1063) );
AOI221X1TS U1408 ( .A0(n1676), .A1(intDY[4]), .B0(intDY[3]), .B1(n1703),
.C0(n935), .Y(n940) );
OAI21XLTS U1409 ( .A0(n1698), .A1(n1141), .B0(n1114), .Y(n127) );
NOR2X2TS U1410 ( .A(n832), .B(n831), .Y(n1427) );
AOI211X1TS U1411 ( .A0(intDY[16]), .A1(n1733), .B0(n1094), .C0(n1095), .Y(
n1086) );
NOR2X4TS U1412 ( .A(n655), .B(FS_Module_state_reg[2]), .Y(n1212) );
BUFX3TS U1413 ( .A(n1790), .Y(n1782) );
OAI21XLTS U1414 ( .A0(n1215), .A1(n1212), .B0(FS_Module_state_reg[3]), .Y(
n1177) );
OAI22X2TS U1415 ( .A0(beg_FSM), .A1(n244), .B0(ack_FSM), .B1(n987), .Y(n1215) );
BUFX3TS U1416 ( .A(n975), .Y(n686) );
BUFX3TS U1417 ( .A(n975), .Y(n687) );
AOI22X2TS U1418 ( .A0(LZA_output[1]), .A1(n702), .B0(n666), .B1(
exp_oper_result[1]), .Y(n981) );
AOI21X2TS U1419 ( .A0(exp_oper_result[0]), .A1(n1692), .B0(n972), .Y(n982)
);
AOI22X2TS U1420 ( .A0(LZA_output[3]), .A1(n702), .B0(n665), .B1(
exp_oper_result[3]), .Y(n901) );
AOI32X4TS U1421 ( .A0(n1512), .A1(n1585), .A2(n1511), .B0(n1510), .B1(n1591),
.Y(Barrel_Shifter_module_Mux_Array_Data_array[20]) );
NOR2BX1TS U1422 ( .AN(n961), .B(add_overflow_flag), .Y(n903) );
NOR3X2TS U1423 ( .A(Add_Subt_result[21]), .B(Add_Subt_result[20]), .C(
Add_Subt_result[19]), .Y(n1317) );
AOI21X2TS U1424 ( .A0(n669), .A1(Add_Subt_result[20]), .B0(n978), .Y(n1509)
);
OAI31X1TS U1425 ( .A0(n1739), .A1(Add_Subt_result[21]), .A2(
Add_Subt_result[20]), .B0(n1324), .Y(n1325) );
AOI221X1TS U1426 ( .A0(n1698), .A1(intDY[13]), .B0(intDY[10]), .B1(n1724),
.C0(n943), .Y(n948) );
OAI21XLTS U1427 ( .A0(intDX[13]), .A1(n1686), .B0(intDX[12]), .Y(n1067) );
INVX2TS U1428 ( .A(n688), .Y(n689) );
OR2X4TS U1429 ( .A(n1109), .B(n1144), .Y(n690) );
OR2X1TS U1430 ( .A(n734), .B(n733), .Y(n691) );
OR2X1TS U1431 ( .A(n727), .B(n726), .Y(n692) );
OR2X1TS U1432 ( .A(n856), .B(n855), .Y(n694) );
OR2X2TS U1433 ( .A(n719), .B(n718), .Y(n695) );
OR2X2TS U1434 ( .A(n721), .B(n720), .Y(n696) );
OAI21XLTS U1435 ( .A0(intDX[1]), .A1(n1682), .B0(intDX[0]), .Y(n1056) );
NOR2XLTS U1436 ( .A(n1089), .B(intDY[16]), .Y(n1090) );
NAND2X1TS U1437 ( .A(n1465), .B(n848), .Y(n850) );
INVX2TS U1438 ( .A(n762), .Y(n714) );
OAI21X2TS U1439 ( .A0(n1365), .A1(n818), .B0(n817), .Y(n1416) );
OR2X1TS U1440 ( .A(n871), .B(n870), .Y(n1397) );
INVX2TS U1441 ( .A(n1416), .Y(n1464) );
AND4X1TS U1442 ( .A(n1285), .B(n1286), .C(n1287), .D(n764), .Y(n771) );
OAI21XLTS U1443 ( .A0(Add_Subt_result[1]), .A1(Add_Subt_result[0]), .B0(
n1301), .Y(n1298) );
NAND2X1TS U1444 ( .A(n691), .B(n765), .Y(n735) );
XNOR2X2TS U1445 ( .A(intDY[31]), .B(intAS), .Y(n1201) );
CLKXOR2X2TS U1446 ( .A(n763), .B(n762), .Y(n1291) );
NAND2X2TS U1447 ( .A(n959), .B(n1712), .Y(n244) );
NOR2X2TS U1448 ( .A(FS_Module_state_reg[1]), .B(n1694), .Y(n961) );
NOR2BX2TS U1449 ( .AN(n961), .B(FS_Module_state_reg[3]), .Y(n700) );
NOR2X1TS U1450 ( .A(n910), .B(FSM_selector_C), .Y(n699) );
INVX2TS U1451 ( .A(n1212), .Y(n909) );
NAND2X1TS U1452 ( .A(add_overflow_flag), .B(n697), .Y(n698) );
NOR2X1TS U1453 ( .A(n699), .B(n698), .Y(n701) );
NAND2X2TS U1454 ( .A(n700), .B(FS_Module_state_reg[0]), .Y(n1210) );
NOR2X4TS U1455 ( .A(FS_Module_state_reg[0]), .B(n1720), .Y(n1218) );
NAND2X1TS U1456 ( .A(n1218), .B(n961), .Y(n908) );
INVX6TS U1457 ( .A(n1638), .Y(n1272) );
NAND3X6TS U1458 ( .A(n701), .B(n675), .C(n244), .Y(n768) );
BUFX3TS U1459 ( .A(FSM_selector_D), .Y(n891) );
NAND2X1TS U1460 ( .A(n702), .B(LZA_output[0]), .Y(n707) );
NAND2X1TS U1461 ( .A(n1692), .B(FSM_selector_B[1]), .Y(n706) );
NAND2X1TS U1462 ( .A(n707), .B(n706), .Y(n972) );
AOI21X4TS U1463 ( .A0(n715), .A1(n714), .B0(n713), .Y(n744) );
OAI21X4TS U1464 ( .A0(n744), .A1(n724), .B0(n723), .Y(n743) );
AOI21X4TS U1465 ( .A0(n743), .A1(n692), .B0(n728), .Y(n740) );
XNOR2X4TS U1466 ( .A(n751), .B(n750), .Y(n1288) );
AFHCONX2TS U1467 ( .A(n758), .B(n768), .CI(n757), .CON(n762), .S(n1337) );
AND4X1TS U1468 ( .A(n1288), .B(n1290), .C(n1337), .D(n1291), .Y(n764) );
NAND2X1TS U1469 ( .A(FS_Module_state_reg[0]), .B(n1212), .Y(n772) );
NAND2X2TS U1470 ( .A(n910), .B(n772), .Y(n1289) );
INVX2TS U1471 ( .A(n1218), .Y(n774) );
NOR2X2TS U1472 ( .A(FS_Module_state_reg[2]), .B(n774), .Y(n1292) );
NAND2X2TS U1473 ( .A(n1292), .B(n655), .Y(n1334) );
NOR2X1TS U1474 ( .A(Add_Subt_result[23]), .B(Add_Subt_result[22]), .Y(n1324)
);
NOR2X1TS U1475 ( .A(Add_Subt_result[25]), .B(Add_Subt_result[24]), .Y(n1326)
);
NOR2X1TS U1476 ( .A(Add_Subt_result[17]), .B(Add_Subt_result[16]), .Y(n1322)
);
NAND2X1TS U1477 ( .A(n1322), .B(n1687), .Y(n1305) );
NOR3X2TS U1478 ( .A(Add_Subt_result[7]), .B(Add_Subt_result[6]), .C(n783),
.Y(n1313) );
NOR2X4TS U1479 ( .A(Add_Subt_result[4]), .B(n778), .Y(n1312) );
NAND2X1TS U1480 ( .A(Add_Subt_result[2]), .B(n1312), .Y(n780) );
NOR3BX4TS U1481 ( .AN(n1312), .B(Add_Subt_result[3]), .C(Add_Subt_result[2]),
.Y(n1301) );
OAI2BB2X1TS U1482 ( .B0(n1729), .B1(n777), .A0N(Add_Subt_result[18]), .A1N(
n1323), .Y(n1332) );
NAND2BX1TS U1483 ( .AN(n778), .B(Add_Subt_result[4]), .Y(n1299) );
INVX2TS U1484 ( .A(n1334), .Y(n1318) );
INVX2TS U1485 ( .A(n1318), .Y(n781) );
AOI21X1TS U1486 ( .A0(n1735), .A1(Add_Subt_result[20]), .B0(
Add_Subt_result[22]), .Y(n784) );
INVX2TS U1487 ( .A(n1327), .Y(n786) );
AOI21X1TS U1488 ( .A0(n1691), .A1(Add_Subt_result[12]), .B0(
Add_Subt_result[14]), .Y(n785) );
NOR2X1TS U1489 ( .A(n786), .B(n785), .Y(n1303) );
INVX2TS U1490 ( .A(n1303), .Y(n788) );
BUFX3TS U1491 ( .A(FSM_selector_D), .Y(n885) );
XOR2X1TS U1492 ( .A(n821), .B(Sgf_normalized_result[1]), .Y(n794) );
BUFX3TS U1493 ( .A(FSM_selector_D), .Y(n967) );
NOR2X2TS U1494 ( .A(n794), .B(n793), .Y(n1351) );
OR2X1TS U1495 ( .A(n885), .B(Sgf_normalized_result[2]), .Y(n795) );
XOR2X1TS U1496 ( .A(n821), .B(n795), .Y(n800) );
BUFX3TS U1497 ( .A(FSM_selector_D), .Y(n825) );
NOR2X1TS U1498 ( .A(n800), .B(n799), .Y(n1353) );
NOR2X1TS U1499 ( .A(n1351), .B(n1353), .Y(n802) );
INVX4TS U1500 ( .A(n1281), .Y(n896) );
BUFX3TS U1501 ( .A(FSM_selector_D), .Y(n894) );
NOR2BX1TS U1502 ( .AN(Sgf_normalized_result[0]), .B(n894), .Y(n796) );
XOR2X1TS U1503 ( .A(n896), .B(n796), .Y(n1222) );
INVX2TS U1504 ( .A(n1222), .Y(n798) );
NOR2X1TS U1505 ( .A(n896), .B(n797), .Y(n1223) );
NOR2X1TS U1506 ( .A(n798), .B(n1223), .Y(n1344) );
NAND2X1TS U1507 ( .A(n800), .B(n799), .Y(n1354) );
INVX2TS U1508 ( .A(n1354), .Y(n801) );
AOI21X2TS U1509 ( .A0(n802), .A1(n1344), .B0(n801), .Y(n1365) );
NOR2BX1TS U1510 ( .AN(Sgf_normalized_result[3]), .B(n967), .Y(n803) );
XOR2X1TS U1511 ( .A(n821), .B(n803), .Y(n808) );
NOR2X1TS U1512 ( .A(n808), .B(n807), .Y(n1366) );
NOR2BX1TS U1513 ( .AN(Sgf_normalized_result[4]), .B(n894), .Y(n804) );
XOR2X1TS U1514 ( .A(n821), .B(n804), .Y(n810) );
NOR2X2TS U1515 ( .A(n810), .B(n809), .Y(n1378) );
NOR2BX1TS U1516 ( .AN(Sgf_normalized_result[5]), .B(n894), .Y(n805) );
NOR2X2TS U1517 ( .A(n812), .B(n811), .Y(n1402) );
NOR2BX1TS U1518 ( .AN(Sgf_normalized_result[6]), .B(n967), .Y(n806) );
XOR2X1TS U1519 ( .A(n821), .B(n806), .Y(n814) );
NOR2X2TS U1520 ( .A(n814), .B(n813), .Y(n1404) );
NAND2X1TS U1521 ( .A(n808), .B(n807), .Y(n1375) );
NAND2X1TS U1522 ( .A(n810), .B(n809), .Y(n1379) );
NAND2X1TS U1523 ( .A(n812), .B(n811), .Y(n1401) );
NAND2X1TS U1524 ( .A(n814), .B(n813), .Y(n1405) );
AOI21X1TS U1525 ( .A0(n1390), .A1(n816), .B0(n815), .Y(n817) );
NOR2BX1TS U1526 ( .AN(Sgf_normalized_result[7]), .B(n967), .Y(n819) );
NOR2X2TS U1527 ( .A(n830), .B(n829), .Y(n1426) );
NOR2BX1TS U1528 ( .AN(Sgf_normalized_result[8]), .B(n967), .Y(n820) );
XOR2X1TS U1529 ( .A(n821), .B(n820), .Y(n832) );
NOR2X1TS U1530 ( .A(n1426), .B(n1427), .Y(n1440) );
NOR2BX1TS U1531 ( .AN(Sgf_normalized_result[9]), .B(n967), .Y(n822) );
XOR2X1TS U1532 ( .A(n877), .B(n822), .Y(n834) );
NOR2X1TS U1533 ( .A(n834), .B(n833), .Y(n1444) );
NOR2BX1TS U1534 ( .AN(Sgf_normalized_result[10]), .B(n967), .Y(n823) );
XOR2X1TS U1535 ( .A(n877), .B(n823), .Y(n836) );
NOR2X2TS U1536 ( .A(n836), .B(n835), .Y(n1456) );
NOR2BX1TS U1537 ( .AN(Sgf_normalized_result[11]), .B(n967), .Y(n824) );
XOR2X1TS U1538 ( .A(n877), .B(n824), .Y(n840) );
NOR2X1TS U1539 ( .A(n840), .B(n839), .Y(n1477) );
XOR2X1TS U1540 ( .A(n877), .B(n826), .Y(n842) );
BUFX3TS U1541 ( .A(FSM_selector_D), .Y(n878) );
NOR2X2TS U1542 ( .A(n842), .B(n841), .Y(n1490) );
XOR2X1TS U1543 ( .A(n877), .B(n827), .Y(n844) );
NOR2X1TS U1544 ( .A(n844), .B(n843), .Y(n1469) );
XOR2X1TS U1545 ( .A(n877), .B(n828), .Y(n846) );
NOR2X2TS U1546 ( .A(n846), .B(n845), .Y(n1471) );
NOR2X2TS U1547 ( .A(n1463), .B(n850), .Y(n852) );
NAND2X2TS U1548 ( .A(n830), .B(n829), .Y(n1425) );
NAND2X1TS U1549 ( .A(n832), .B(n831), .Y(n1428) );
OAI21X1TS U1550 ( .A0(n1427), .A1(n1425), .B0(n1428), .Y(n1441) );
NAND2X1TS U1551 ( .A(n834), .B(n833), .Y(n1452) );
NAND2X1TS U1552 ( .A(n836), .B(n835), .Y(n1457) );
NAND2X1TS U1553 ( .A(n840), .B(n839), .Y(n1486) );
NAND2X1TS U1554 ( .A(n842), .B(n841), .Y(n1491) );
OAI21X1TS U1555 ( .A0(n1490), .A1(n1486), .B0(n1491), .Y(n1466) );
NAND2X1TS U1556 ( .A(n846), .B(n845), .Y(n1472) );
AOI21X1TS U1557 ( .A0(n1466), .A1(n848), .B0(n847), .Y(n849) );
OAI21X2TS U1558 ( .A0(n1462), .A1(n850), .B0(n849), .Y(n851) );
AOI21X4TS U1559 ( .A0(n1416), .A1(n852), .B0(n851), .Y(n1433) );
XOR2X1TS U1560 ( .A(n877), .B(n853), .Y(n856) );
XOR2X1TS U1561 ( .A(n877), .B(n854), .Y(n858) );
NAND2X1TS U1562 ( .A(n694), .B(n1436), .Y(n861) );
NAND2X1TS U1563 ( .A(n856), .B(n855), .Y(n1447) );
INVX2TS U1564 ( .A(n1447), .Y(n1434) );
NAND2X1TS U1565 ( .A(n858), .B(n857), .Y(n1435) );
INVX2TS U1566 ( .A(n1435), .Y(n859) );
AOI21X1TS U1567 ( .A0(n1436), .A1(n1434), .B0(n859), .Y(n860) );
OAI21X4TS U1568 ( .A0(n1433), .A1(n861), .B0(n860), .Y(n1423) );
XOR2X1TS U1569 ( .A(n877), .B(n862), .Y(n864) );
NAND2X1TS U1570 ( .A(n864), .B(n863), .Y(n1420) );
INVX2TS U1571 ( .A(n1420), .Y(n865) );
AOI21X4TS U1572 ( .A0(n1423), .A1(n1421), .B0(n865), .Y(n1414) );
XOR2X1TS U1573 ( .A(n896), .B(n866), .Y(n868) );
NOR2X1TS U1574 ( .A(n868), .B(n867), .Y(n1410) );
NAND2X1TS U1575 ( .A(n868), .B(n867), .Y(n1411) );
OAI21X4TS U1576 ( .A0(n1414), .A1(n1410), .B0(n1411), .Y(n1399) );
XOR2X1TS U1577 ( .A(n896), .B(n869), .Y(n871) );
NAND2X1TS U1578 ( .A(n871), .B(n870), .Y(n1396) );
INVX2TS U1579 ( .A(n1396), .Y(n872) );
AOI21X4TS U1580 ( .A0(n1399), .A1(n1397), .B0(n872), .Y(n1388) );
XOR2X1TS U1581 ( .A(n896), .B(n873), .Y(n875) );
NOR2X1TS U1582 ( .A(n875), .B(n874), .Y(n1384) );
NAND2X1TS U1583 ( .A(n875), .B(n874), .Y(n1385) );
OAI21X4TS U1584 ( .A0(n1388), .A1(n1384), .B0(n1385), .Y(n1372) );
XOR2X1TS U1585 ( .A(n877), .B(n876), .Y(n880) );
NAND2X1TS U1586 ( .A(n880), .B(n879), .Y(n1369) );
INVX2TS U1587 ( .A(n1369), .Y(n881) );
AOI21X4TS U1588 ( .A0(n1372), .A1(n1370), .B0(n881), .Y(n1363) );
XOR2X1TS U1589 ( .A(n896), .B(n882), .Y(n884) );
NOR2X1TS U1590 ( .A(n884), .B(n883), .Y(n1359) );
NAND2X1TS U1591 ( .A(n884), .B(n883), .Y(n1360) );
OAI21X4TS U1592 ( .A0(n1363), .A1(n1359), .B0(n1360), .Y(n1349) );
XOR2X1TS U1593 ( .A(n896), .B(n886), .Y(n888) );
NAND2X1TS U1594 ( .A(n888), .B(n887), .Y(n1346) );
INVX2TS U1595 ( .A(n1346), .Y(n889) );
AOI21X4TS U1596 ( .A0(n1349), .A1(n1347), .B0(n889), .Y(n1342) );
XOR2X1TS U1597 ( .A(n896), .B(n890), .Y(n893) );
NOR2X1TS U1598 ( .A(n893), .B(n892), .Y(n1338) );
NAND2X1TS U1599 ( .A(n893), .B(n892), .Y(n1339) );
OAI21X4TS U1600 ( .A0(n1342), .A1(n1338), .B0(n1339), .Y(n1280) );
NOR2BX1TS U1601 ( .AN(Sgf_normalized_result[25]), .B(n967), .Y(n895) );
XOR2X1TS U1602 ( .A(n896), .B(n895), .Y(n1278) );
INVX2TS U1603 ( .A(n1278), .Y(n897) );
NAND2X1TS U1604 ( .A(n1279), .B(n897), .Y(n898) );
XNOR2X1TS U1605 ( .A(n1280), .B(n898), .Y(n900) );
NAND2X1TS U1606 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]),
.Y(n899) );
NOR2X1TS U1607 ( .A(n681), .B(n901), .Y(n915) );
NAND2X1TS U1608 ( .A(n901), .B(n681), .Y(n996) );
INVX2TS U1609 ( .A(n996), .Y(n913) );
INVX2TS U1610 ( .A(n901), .Y(n1001) );
NOR2X4TS U1611 ( .A(n681), .B(n1001), .Y(n1225) );
AOI22X1TS U1612 ( .A0(n913), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .B0(n1225), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n902) );
OAI2BB1X1TS U1613 ( .A0N(Barrel_Shifter_module_Mux_Array_Data_array[51]),
.A1N(n915), .B0(n902), .Y(n997) );
BUFX3TS U1614 ( .A(n1727), .Y(n1582) );
NAND2X1TS U1615 ( .A(n1001), .B(n681), .Y(n1012) );
INVX2TS U1616 ( .A(n906), .Y(n917) );
BUFX3TS U1617 ( .A(n1241), .Y(n1639) );
AOI22X1TS U1618 ( .A0(n675), .A1(Sgf_normalized_result[24]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B1(n1639), .Y(n911)
);
BUFX3TS U1619 ( .A(n1727), .Y(n1560) );
INVX2TS U1620 ( .A(n1038), .Y(n1000) );
NOR3X1TS U1621 ( .A(n1000), .B(n675), .C(n913), .Y(n1226) );
INVX2TS U1622 ( .A(n1226), .Y(n1640) );
AOI22X1TS U1623 ( .A0(n913), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .B0(n1225), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n914) );
OAI2BB1X1TS U1624 ( .A0N(Barrel_Shifter_module_Mux_Array_Data_array[50]),
.A1N(n915), .B0(n914), .Y(n1022) );
AOI22X1TS U1625 ( .A0(n676), .A1(Sgf_normalized_result[25]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B1(n1639), .Y(n916)
);
INVX2TS U1626 ( .A(rst), .Y(n1790) );
OAI22X1TS U1627 ( .A0(n1719), .A1(intDX[12]), .B0(n1704), .B1(intDY[8]), .Y(
n919) );
AOI221X1TS U1628 ( .A0(n1719), .A1(intDX[12]), .B0(intDY[8]), .B1(n1704),
.C0(n919), .Y(n925) );
OAI22X1TS U1629 ( .A0(n1667), .A1(intDY[21]), .B0(n1696), .B1(intDY[17]),
.Y(n920) );
AOI221X1TS U1630 ( .A0(n1667), .A1(intDY[21]), .B0(intDY[17]), .B1(n1696),
.C0(n920), .Y(n924) );
OAI22X1TS U1631 ( .A0(n1733), .A1(intDY[16]), .B0(n1664), .B1(intDY[23]),
.Y(n921) );
AOI221X1TS U1632 ( .A0(n1733), .A1(intDY[16]), .B0(intDY[23]), .B1(n1664),
.C0(n921), .Y(n923) );
AOI22X1TS U1633 ( .A0(intDX[7]), .A1(n1671), .B0(intDY[7]), .B1(n1675), .Y(
n922) );
OAI22X1TS U1634 ( .A0(n1668), .A1(intDY[22]), .B0(n1697), .B1(intDY[18]),
.Y(n926) );
AOI221X1TS U1635 ( .A0(n1668), .A1(intDY[22]), .B0(intDY[18]), .B1(n1697),
.C0(n926), .Y(n933) );
OAI22X1TS U1636 ( .A0(n1701), .A1(intDY[29]), .B0(n1666), .B1(intDY[27]),
.Y(n927) );
OAI22X1TS U1637 ( .A0(n1700), .A1(intDY[19]), .B0(n1665), .B1(intDY[25]),
.Y(n928) );
AOI221X1TS U1638 ( .A0(n1700), .A1(intDY[19]), .B0(intDY[25]), .B1(n1665),
.C0(n928), .Y(n931) );
OAI22X1TS U1639 ( .A0(n1669), .A1(intDY[24]), .B0(n1659), .B1(intDY[20]),
.Y(n929) );
AOI221X1TS U1640 ( .A0(n1669), .A1(intDY[24]), .B0(intDY[20]), .B1(n1659),
.C0(n929), .Y(n930) );
OAI22X1TS U1641 ( .A0(n1702), .A1(intDY[30]), .B0(n1721), .B1(intDY[5]), .Y(
n934) );
AOI221X1TS U1642 ( .A0(n1702), .A1(intDY[30]), .B0(intDY[5]), .B1(n1721),
.C0(n934), .Y(n941) );
OAI22X1TS U1643 ( .A0(n1676), .A1(intDY[4]), .B0(n1703), .B1(intDY[3]), .Y(
n935) );
OAI22X1TS U1644 ( .A0(n1670), .A1(intDY[26]), .B0(n1705), .B1(intDY[1]), .Y(
n936) );
OAI22X1TS U1645 ( .A0(n1722), .A1(intDY[0]), .B0(n1723), .B1(intDY[28]), .Y(
n937) );
OAI22X1TS U1646 ( .A0(n1718), .A1(intDY[6]), .B0(n1695), .B1(intDY[15]), .Y(
n942) );
AOI221X1TS U1647 ( .A0(n1718), .A1(intDY[6]), .B0(intDY[15]), .B1(n1695),
.C0(n942), .Y(n949) );
OAI22X1TS U1648 ( .A0(n1698), .A1(intDY[13]), .B0(n1724), .B1(intDY[10]),
.Y(n943) );
OAI22X1TS U1649 ( .A0(n1706), .A1(intDY[2]), .B0(n1673), .B1(intDY[9]), .Y(
n944) );
OAI22X1TS U1650 ( .A0(n1699), .A1(intDY[14]), .B0(n1663), .B1(intDY[11]),
.Y(n945) );
AOI221X1TS U1651 ( .A0(n1699), .A1(intDY[14]), .B0(intDY[11]), .B1(n1663),
.C0(n945), .Y(n946) );
NOR4X2TS U1652 ( .A(n953), .B(n952), .C(n951), .D(n950), .Y(n1199) );
AOI21X1TS U1653 ( .A0(n1199), .A1(n955), .B0(n1190), .Y(n958) );
NAND3X1TS U1654 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[2]),
.C(n1218), .Y(n987) );
BUFX3TS U1655 ( .A(n1786), .Y(n1766) );
BUFX3TS U1656 ( .A(n1780), .Y(n1785) );
BUFX3TS U1657 ( .A(n1785), .Y(n1783) );
BUFX3TS U1658 ( .A(n1783), .Y(n1772) );
BUFX3TS U1659 ( .A(n1785), .Y(n1769) );
BUFX3TS U1660 ( .A(n1785), .Y(n1768) );
BUFX3TS U1661 ( .A(n1786), .Y(n1767) );
BUFX3TS U1662 ( .A(n1781), .Y(n1775) );
BUFX3TS U1663 ( .A(n1790), .Y(n1778) );
BUFX3TS U1664 ( .A(n1781), .Y(n1776) );
BUFX3TS U1665 ( .A(n1781), .Y(n1774) );
BUFX3TS U1666 ( .A(n1785), .Y(n1787) );
BUFX3TS U1667 ( .A(n1780), .Y(n1777) );
BUFX3TS U1668 ( .A(n1786), .Y(n1784) );
CLKBUFX3TS U1669 ( .A(n1784), .Y(n1789) );
CLKBUFX3TS U1670 ( .A(n1789), .Y(n1788) );
BUFX3TS U1671 ( .A(n1788), .Y(n1762) );
BUFX3TS U1672 ( .A(n1783), .Y(n1773) );
BUFX3TS U1673 ( .A(n1788), .Y(n1763) );
NAND2X1TS U1674 ( .A(n959), .B(FS_Module_state_reg[0]), .Y(n960) );
INVX2TS U1675 ( .A(n960), .Y(n1654) );
BUFX3TS U1676 ( .A(n1654), .Y(n1653) );
INVX2TS U1677 ( .A(n1651), .Y(n1650) );
BUFX3TS U1678 ( .A(n1651), .Y(n1647) );
BUFX3TS U1679 ( .A(n1654), .Y(n1655) );
OAI2BB2XLTS U1680 ( .B0(n1647), .B1(n1663), .A0N(n1655), .A1N(Data_X[11]),
.Y(n194) );
BUFX3TS U1681 ( .A(n1654), .Y(n1658) );
OAI2BB2XLTS U1682 ( .B0(n1658), .B1(n1702), .A0N(n1654), .A1N(Data_X[30]),
.Y(n213) );
OAI2BB2XLTS U1683 ( .B0(n1658), .B1(n1701), .A0N(n1654), .A1N(Data_X[29]),
.Y(n212) );
INVX2TS U1684 ( .A(n963), .Y(n1645) );
BUFX3TS U1685 ( .A(n1645), .Y(n1644) );
AOI21X1TS U1686 ( .A0(n1679), .A1(n1756), .B0(overflow_flag), .Y(n964) );
INVX2TS U1687 ( .A(n1644), .Y(n1629) );
OAI22X1TS U1688 ( .A0(r_mode[0]), .A1(n1679), .B0(Sgf_normalized_result[0]),
.B1(Sgf_normalized_result[1]), .Y(n966) );
AOI211X1TS U1689 ( .A0(r_mode[0]), .A1(r_mode[1]), .B0(n966), .C0(n965), .Y(
n1179) );
AO22X2TS U1690 ( .A0(n682), .A1(n702), .B0(n666), .B1(exp_oper_result[2]),
.Y(n1500) );
INVX2TS U1691 ( .A(n1500), .Y(n1585) );
NAND2X4TS U1692 ( .A(n663), .B(FSM_selector_C), .Y(n1555) );
OAI22X1TS U1693 ( .A0(n664), .A1(n1677), .B0(FSM_selector_C), .B1(n1734),
.Y(n968) );
NOR2X1TS U1694 ( .A(n969), .B(n968), .Y(n993) );
INVX2TS U1695 ( .A(n993), .Y(n1505) );
AOI22X1TS U1696 ( .A0(n670), .A1(Add_Subt_result[6]), .B0(DmP[17]), .B1(
n1582), .Y(n970) );
OA21XLTS U1697 ( .A0(n1555), .A1(n1739), .B0(n970), .Y(n1514) );
OAI2BB2X2TS U1698 ( .B0(n1585), .B1(n1505), .A0N(n1585), .A1N(n1514), .Y(
n1043) );
INVX2TS U1699 ( .A(n981), .Y(n1039) );
NAND2X1TS U1700 ( .A(n1039), .B(n982), .Y(n1025) );
OR2X2TS U1701 ( .A(n982), .B(n1039), .Y(n991) );
INVX2TS U1702 ( .A(n991), .Y(n1611) );
OAI2BB2XLTS U1703 ( .B0(n664), .B1(n1736), .A0N(DmP[16]), .A1N(n1560), .Y(
n973) );
AOI21X1TS U1704 ( .A0(n669), .A1(Add_Subt_result[18]), .B0(n973), .Y(n1519)
);
AOI22X1TS U1705 ( .A0(n670), .A1(Add_Subt_result[3]), .B0(n677), .B1(n1582),
.Y(n974) );
OAI2BB1X2TS U1706 ( .A0N(Add_Subt_result[22]), .A1N(n669), .B0(n974), .Y(
n1506) );
AOI2BB2X2TS U1707 ( .B0(n1585), .B1(n1519), .A0N(n1506), .A1N(n1585), .Y(
n1515) );
NAND2X2TS U1708 ( .A(n982), .B(n981), .Y(n1508) );
INVX2TS U1709 ( .A(n1508), .Y(n975) );
AOI21X1TS U1710 ( .A0(n669), .A1(Add_Subt_result[17]), .B0(n976), .Y(n1524)
);
BUFX3TS U1711 ( .A(n1500), .Y(n1544) );
BUFX3TS U1712 ( .A(n1544), .Y(n1605) );
AOI22X1TS U1713 ( .A0(n1590), .A1(n1515), .B0(n687), .B1(n1520), .Y(n984) );
OAI22X1TS U1714 ( .A0(n664), .A1(n1678), .B0(FSM_selector_C), .B1(n1743),
.Y(n979) );
NOR2X1TS U1715 ( .A(n980), .B(n979), .Y(n992) );
OR2X2TS U1716 ( .A(n982), .B(n981), .Y(n1504) );
INVX2TS U1717 ( .A(n1504), .Y(n1033) );
NAND2X1TS U1718 ( .A(n1032), .B(n1600), .Y(n983) );
BUFX3TS U1719 ( .A(n1787), .Y(n1765) );
BUFX3TS U1720 ( .A(n1787), .Y(n1764) );
BUFX3TS U1721 ( .A(n1787), .Y(n1779) );
BUFX3TS U1722 ( .A(n1784), .Y(n1770) );
BUFX3TS U1723 ( .A(n1784), .Y(n1771) );
INVX2TS U1724 ( .A(n1292), .Y(n985) );
AOI22X1TS U1725 ( .A0(n1218), .A1(n1212), .B0(FSM_selector_B[1]), .B1(n985),
.Y(n986) );
INVX2TS U1726 ( .A(n987), .Y(ready) );
INVX2TS U1727 ( .A(n1499), .Y(n1026) );
OAI31X1TS U1728 ( .A0(n1508), .A1(n1605), .A2(n1026), .B0(n990), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
NAND2X2TS U1729 ( .A(n1605), .B(n1038), .Y(n1502) );
INVX2TS U1730 ( .A(n991), .Y(n1037) );
INVX2TS U1731 ( .A(n992), .Y(n1498) );
OAI22X1TS U1732 ( .A0(n993), .A1(n1508), .B0(n1025), .B1(n1026), .Y(n994) );
AOI32X1TS U1733 ( .A0(n1037), .A1(n1585), .A2(n1498), .B0(n994), .B1(n1594),
.Y(n995) );
INVX2TS U1734 ( .A(n907), .Y(n1273) );
NAND2X1TS U1735 ( .A(n997), .B(n1273), .Y(n999) );
AOI22X1TS U1736 ( .A0(n667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n1272), .B1(
Sgf_normalized_result[1]), .Y(n998) );
NOR2X1TS U1737 ( .A(n1000), .B(n681), .Y(n1231) );
NAND2X1TS U1738 ( .A(n1231), .B(n1001), .Y(n1017) );
INVX2TS U1739 ( .A(n1274), .Y(n1009) );
NAND2X1TS U1740 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[45]), .B(
n1225), .Y(n1619) );
AOI211X1TS U1741 ( .A0(n676), .A1(Sgf_normalized_result[3]), .B0(n1009),
.C0(n1002), .Y(n1004) );
BUFX3TS U1742 ( .A(n1241), .Y(n1270) );
AOI22X1TS U1743 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n1003) );
NAND2X1TS U1744 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[44]), .B(
n1225), .Y(n1614) );
AOI211X1TS U1745 ( .A0(n676), .A1(Sgf_normalized_result[2]), .B0(n1009),
.C0(n1005), .Y(n1007) );
AOI22X1TS U1746 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n1006) );
NAND2X1TS U1747 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[46]), .B(
n1225), .Y(n1624) );
AOI211X1TS U1748 ( .A0(n1272), .A1(Sgf_normalized_result[4]), .B0(n1009),
.C0(n1008), .Y(n1011) );
AOI22X1TS U1749 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1010) );
INVX2TS U1750 ( .A(n1012), .Y(n1635) );
AOI22X1TS U1751 ( .A0(n1635), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B1(n1225), .Y(n1013)
);
NAND2X1TS U1752 ( .A(n1013), .B(n1017), .Y(n1232) );
INVX2TS U1753 ( .A(n1232), .Y(n1016) );
AOI22X1TS U1754 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(n1272), .B1(
Sgf_normalized_result[8]), .Y(n1015) );
AOI22X1TS U1755 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(n685), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n1014) );
AOI22X1TS U1756 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(
n1225), .B0(n1635), .B1(Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n1018) );
NAND2X1TS U1757 ( .A(n1018), .B(n1017), .Y(n1236) );
INVX2TS U1758 ( .A(n1236), .Y(n1021) );
AOI22X1TS U1759 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n676), .B1(
Sgf_normalized_result[9]), .Y(n1020) );
AOI22X1TS U1760 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(n683), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n1019) );
NAND2X1TS U1761 ( .A(n1022), .B(n1273), .Y(n1024) );
AOI22X1TS U1762 ( .A0(n667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(n676), .B1(
Sgf_normalized_result[0]), .Y(n1023) );
AOI222X1TS U1763 ( .A0(n1506), .A1(n1590), .B0(n1498), .B1(n1600), .C0(n1505), .C1(n679), .Y(n1028) );
INVX2TS U1764 ( .A(n1502), .Y(n1029) );
AOI22X1TS U1765 ( .A0(n975), .A1(n1034), .B0(n1029), .B1(n1508), .Y(n1027)
);
AOI22X1TS U1766 ( .A0(n1037), .A1(n1032), .B0(n679), .B1(n1034), .Y(n1031)
);
INVX2TS U1767 ( .A(n1504), .Y(n1596) );
AOI32X1TS U1768 ( .A0(n1608), .A1(n1596), .A2(n1506), .B0(n1029), .B1(n1596),
.Y(n1030) );
AOI22X1TS U1769 ( .A0(n1032), .A1(n679), .B0(n686), .B1(n1515), .Y(n1036) );
NAND2X1TS U1770 ( .A(n1034), .B(n1033), .Y(n1035) );
OAI2BB2XLTS U1771 ( .B0(n664), .B1(n1738), .A0N(DmP[14]), .A1N(n1560), .Y(
n1040) );
AOI21X1TS U1772 ( .A0(n669), .A1(Add_Subt_result[16]), .B0(n1040), .Y(n1529)
);
AOI22X2TS U1773 ( .A0(n1608), .A1(n1529), .B0(n1509), .B1(n1544), .Y(n1525)
);
AOI22X1TS U1774 ( .A0(n1611), .A1(n1520), .B0(n686), .B1(n1525), .Y(n1042)
);
NAND2X1TS U1775 ( .A(n679), .B(n1515), .Y(n1041) );
NOR2X1TS U1776 ( .A(n1688), .B(intDX[25]), .Y(n1103) );
AOI22X1TS U1777 ( .A0(intDX[25]), .A1(n1688), .B0(intDX[24]), .B1(n1044),
.Y(n1048) );
OAI21X1TS U1778 ( .A0(intDX[26]), .A1(n1707), .B0(n1045), .Y(n1104) );
OAI211X1TS U1779 ( .A0(n1048), .A1(n1104), .B0(n1047), .C0(n1046), .Y(n1053)
);
NOR2X1TS U1780 ( .A(n1710), .B(intDX[30]), .Y(n1051) );
NOR2X1TS U1781 ( .A(n1674), .B(intDX[29]), .Y(n1049) );
NOR3X1TS U1782 ( .A(n1723), .B(n1049), .C(intDY[28]), .Y(n1050) );
AOI221X1TS U1783 ( .A0(intDX[30]), .A1(n1710), .B0(intDX[29]), .B1(n1674),
.C0(n1050), .Y(n1052) );
NOR2X1TS U1784 ( .A(n1689), .B(intDX[17]), .Y(n1089) );
NOR2X1TS U1785 ( .A(n1683), .B(intDX[11]), .Y(n1068) );
AOI21X1TS U1786 ( .A0(intDY[10]), .A1(n1724), .B0(n1068), .Y(n1073) );
OAI2BB1X1TS U1787 ( .A0N(n1721), .A1N(intDY[5]), .B0(intDX[4]), .Y(n1054) );
OAI22X1TS U1788 ( .A0(intDY[4]), .A1(n1054), .B0(n1721), .B1(intDY[5]), .Y(
n1065) );
OAI2BB1X1TS U1789 ( .A0N(n1675), .A1N(intDY[7]), .B0(intDX[6]), .Y(n1055) );
OAI22X1TS U1790 ( .A0(intDY[6]), .A1(n1055), .B0(n1675), .B1(intDY[7]), .Y(
n1064) );
OAI2BB2XLTS U1791 ( .B0(intDY[0]), .B1(n1056), .A0N(intDX[1]), .A1N(n1682),
.Y(n1058) );
OAI211X1TS U1792 ( .A0(n1680), .A1(intDX[3]), .B0(n1058), .C0(n1057), .Y(
n1061) );
AOI22X1TS U1793 ( .A0(intDY[7]), .A1(n1675), .B0(intDY[6]), .B1(n1718), .Y(
n1062) );
OAI32X1TS U1794 ( .A0(n1065), .A1(n1064), .A2(n1063), .B0(n1062), .B1(n1064),
.Y(n1083) );
OA22X1TS U1795 ( .A0(n1681), .A1(intDX[14]), .B0(n1660), .B1(intDX[15]), .Y(
n1080) );
AOI22X1TS U1796 ( .A0(intDX[11]), .A1(n1683), .B0(intDX[10]), .B1(n1069),
.Y(n1075) );
AOI21X1TS U1797 ( .A0(n1072), .A1(n1071), .B0(n1082), .Y(n1074) );
OAI2BB2XLTS U1798 ( .B0(intDY[14]), .B1(n1076), .A0N(intDX[15]), .A1N(n1660),
.Y(n1077) );
AOI211X1TS U1799 ( .A0(n1080), .A1(n1079), .B0(n1078), .C0(n1077), .Y(n1081)
);
OAI31X1TS U1800 ( .A0(n1084), .A1(n1083), .A2(n1082), .B0(n1081), .Y(n1087)
);
OA22X1TS U1801 ( .A0(n1684), .A1(intDX[22]), .B0(n1661), .B1(intDX[23]), .Y(
n1100) );
OAI21X1TS U1802 ( .A0(intDX[18]), .A1(n1711), .B0(n1091), .Y(n1095) );
OAI2BB2XLTS U1803 ( .B0(intDY[20]), .B1(n1088), .A0N(intDX[21]), .A1N(n1708),
.Y(n1099) );
AOI22X1TS U1804 ( .A0(intDX[17]), .A1(n1689), .B0(intDX[16]), .B1(n1090),
.Y(n1093) );
AOI32X1TS U1805 ( .A0(n1711), .A1(n1091), .A2(intDX[18]), .B0(intDX[19]),
.B1(n1672), .Y(n1092) );
OAI32X1TS U1806 ( .A0(n1095), .A1(n1094), .A2(n1093), .B0(n1092), .B1(n1094),
.Y(n1098) );
OAI2BB2XLTS U1807 ( .B0(intDY[22]), .B1(n1096), .A0N(intDX[23]), .A1N(n1661),
.Y(n1097) );
AOI211X1TS U1808 ( .A0(n1100), .A1(n1099), .B0(n1098), .C0(n1097), .Y(n1106)
);
NAND4BBX1TS U1809 ( .AN(n1104), .BN(n1103), .C(n1102), .D(n1101), .Y(n1105)
);
AOI22X1TS U1810 ( .A0(n677), .A1(n1186), .B0(intDY[20]), .B1(n1165), .Y(
n1110) );
AOI22X1TS U1811 ( .A0(intDY[18]), .A1(n1139), .B0(DMP[18]), .B1(n1128), .Y(
n1111) );
AOI22X1TS U1812 ( .A0(intDY[14]), .A1(n1139), .B0(DMP[14]), .B1(n1128), .Y(
n1112) );
AOI22X1TS U1813 ( .A0(intDY[15]), .A1(n1139), .B0(DMP[15]), .B1(n1190), .Y(
n1113) );
AOI22X1TS U1814 ( .A0(intDY[13]), .A1(n1139), .B0(DMP[13]), .B1(n1190), .Y(
n1114) );
AOI22X1TS U1815 ( .A0(intDY[22]), .A1(n1147), .B0(DMP[22]), .B1(n1128), .Y(
n1115) );
AOI22X1TS U1816 ( .A0(intDY[21]), .A1(n1147), .B0(DMP[21]), .B1(n1128), .Y(
n1116) );
AOI22X1TS U1817 ( .A0(intDY[19]), .A1(n1139), .B0(DMP[19]), .B1(n1128), .Y(
n1117) );
AOI22X1TS U1818 ( .A0(intDY[20]), .A1(n1139), .B0(DMP[20]), .B1(n1128), .Y(
n1118) );
AOI22X1TS U1819 ( .A0(intDY[17]), .A1(n1139), .B0(DMP[17]), .B1(n1128), .Y(
n1119) );
AOI22X1TS U1820 ( .A0(intDY[23]), .A1(n1147), .B0(DMP[23]), .B1(n1128), .Y(
n1120) );
AOI22X1TS U1821 ( .A0(intDY[11]), .A1(n1139), .B0(DMP[11]), .B1(n1128), .Y(
n1121) );
AOI22X1TS U1822 ( .A0(intDY[25]), .A1(n1147), .B0(DMP[25]), .B1(n1155), .Y(
n1122) );
AOI22X1TS U1823 ( .A0(intDY[26]), .A1(n1147), .B0(DMP[26]), .B1(n1155), .Y(
n1123) );
AOI22X1TS U1824 ( .A0(intDY[29]), .A1(n1147), .B0(DMP[29]), .B1(n1144), .Y(
n1124) );
AOI22X1TS U1825 ( .A0(intDY[30]), .A1(n1139), .B0(DMP[30]), .B1(n1144), .Y(
n1125) );
BUFX3TS U1826 ( .A(n1198), .Y(n1188) );
AOI22X1TS U1827 ( .A0(intDY[26]), .A1(n1146), .B0(DmP[26]), .B1(n1155), .Y(
n1126) );
AOI22X1TS U1828 ( .A0(intDY[25]), .A1(n1146), .B0(DmP[25]), .B1(n1155), .Y(
n1127) );
BUFX3TS U1829 ( .A(n690), .Y(n1192) );
AOI22X1TS U1830 ( .A0(intDY[30]), .A1(n1146), .B0(DmP[30]), .B1(n1128), .Y(
n1129) );
AOI22X1TS U1831 ( .A0(intDY[29]), .A1(n1146), .B0(DmP[29]), .B1(n1144), .Y(
n1130) );
AOI22X1TS U1832 ( .A0(DmP[21]), .A1(n1196), .B0(intDY[21]), .B1(n1146), .Y(
n1131) );
AOI22X1TS U1833 ( .A0(DmP[19]), .A1(n1196), .B0(intDY[19]), .B1(n1146), .Y(
n1132) );
INVX2TS U1834 ( .A(n1165), .Y(n1202) );
INVX2TS U1835 ( .A(n690), .Y(n1134) );
AOI22X1TS U1836 ( .A0(DmP[12]), .A1(n1196), .B0(intDX[12]), .B1(n1134), .Y(
n1133) );
AOI22X1TS U1837 ( .A0(DmP[7]), .A1(n1196), .B0(intDX[7]), .B1(n1134), .Y(
n1135) );
AOI22X1TS U1838 ( .A0(n689), .A1(n1147), .B0(DMP[27]), .B1(n1155), .Y(n1136)
);
AOI22X1TS U1839 ( .A0(intDY[24]), .A1(n1147), .B0(DMP[24]), .B1(n1155), .Y(
n1137) );
AOI22X1TS U1840 ( .A0(intDY[28]), .A1(n1147), .B0(DMP[28]), .B1(n1155), .Y(
n1138) );
AOI22X1TS U1841 ( .A0(intDY[16]), .A1(n1139), .B0(DMP[16]), .B1(n1190), .Y(
n1140) );
AOI22X1TS U1842 ( .A0(n689), .A1(n1146), .B0(DmP[27]), .B1(n1155), .Y(n1142)
);
AOI22X1TS U1843 ( .A0(intDY[24]), .A1(n1146), .B0(DmP[24]), .B1(n1155), .Y(
n1143) );
AOI22X1TS U1844 ( .A0(intDY[28]), .A1(n1146), .B0(DmP[28]), .B1(n1144), .Y(
n1145) );
AOI22X1TS U1845 ( .A0(n1190), .A1(DMP[0]), .B0(intDY[0]), .B1(n1147), .Y(
n1148) );
AOI22X1TS U1846 ( .A0(n1196), .A1(DMP[7]), .B0(intDY[7]), .B1(n1161), .Y(
n1149) );
AOI22X1TS U1847 ( .A0(n1162), .A1(DMP[8]), .B0(intDY[8]), .B1(n1161), .Y(
n1150) );
AOI22X1TS U1848 ( .A0(n1196), .A1(DMP[3]), .B0(intDY[3]), .B1(n1161), .Y(
n1151) );
AOI22X1TS U1849 ( .A0(n1162), .A1(DMP[1]), .B0(intDY[1]), .B1(n1161), .Y(
n1152) );
AOI22X1TS U1850 ( .A0(n1186), .A1(DMP[2]), .B0(intDY[2]), .B1(n1161), .Y(
n1153) );
AOI22X1TS U1851 ( .A0(n1186), .A1(DMP[9]), .B0(intDY[9]), .B1(n1161), .Y(
n1154) );
BUFX3TS U1852 ( .A(n1165), .Y(n1195) );
AOI22X1TS U1853 ( .A0(intDY[23]), .A1(n1195), .B0(DmP[23]), .B1(n1155), .Y(
n1156) );
AOI22X1TS U1854 ( .A0(n1186), .A1(DMP[10]), .B0(intDY[10]), .B1(n1161), .Y(
n1157) );
AOI22X1TS U1855 ( .A0(n1196), .A1(DMP[4]), .B0(intDY[4]), .B1(n1161), .Y(
n1158) );
AOI22X1TS U1856 ( .A0(n1162), .A1(DMP[6]), .B0(intDY[6]), .B1(n1161), .Y(
n1159) );
AOI22X1TS U1857 ( .A0(n1186), .A1(DMP[5]), .B0(intDY[5]), .B1(n1161), .Y(
n1163) );
AOI22X1TS U1858 ( .A0(DmP[22]), .A1(n1162), .B0(intDY[22]), .B1(n1189), .Y(
n1166) );
AOI22X1TS U1859 ( .A0(DmP[11]), .A1(n1162), .B0(intDY[11]), .B1(n1189), .Y(
n1167) );
AOI22X1TS U1860 ( .A0(DmP[18]), .A1(n1162), .B0(intDY[18]), .B1(n1189), .Y(
n1168) );
AOI22X1TS U1861 ( .A0(DmP[15]), .A1(n1196), .B0(intDY[15]), .B1(n1189), .Y(
n1169) );
AOI22X1TS U1862 ( .A0(DmP[13]), .A1(n1186), .B0(intDY[13]), .B1(n1189), .Y(
n1170) );
AOI22X1TS U1863 ( .A0(DmP[14]), .A1(n1190), .B0(intDY[14]), .B1(n1189), .Y(
n1171) );
AOI22X1TS U1864 ( .A0(DmP[17]), .A1(n1186), .B0(intDY[17]), .B1(n1189), .Y(
n1172) );
AOI22X1TS U1865 ( .A0(DmP[8]), .A1(n1190), .B0(intDY[8]), .B1(n1195), .Y(
n1173) );
INVX2TS U1866 ( .A(n1217), .Y(n1178) );
NOR3BX1TS U1867 ( .AN(n1199), .B(n1190), .C(n1174), .Y(n1221) );
NOR4X1TS U1868 ( .A(n1221), .B(n1644), .C(n1450), .D(n1175), .Y(n1176) );
AOI22X1TS U1869 ( .A0(DmP[3]), .A1(n1162), .B0(intDY[3]), .B1(n1195), .Y(
n1180) );
AOI22X1TS U1870 ( .A0(DmP[1]), .A1(n1196), .B0(intDY[1]), .B1(n1195), .Y(
n1181) );
AOI22X1TS U1871 ( .A0(DmP[0]), .A1(n1190), .B0(intDY[0]), .B1(n1189), .Y(
n1182) );
AOI22X1TS U1872 ( .A0(intDX[12]), .A1(n1195), .B0(DMP[12]), .B1(n1162), .Y(
n1183) );
AOI22X1TS U1873 ( .A0(DmP[10]), .A1(n1186), .B0(intDY[10]), .B1(n1189), .Y(
n1184) );
AOI22X1TS U1874 ( .A0(DmP[2]), .A1(n1162), .B0(intDY[2]), .B1(n1195), .Y(
n1185) );
AOI22X1TS U1875 ( .A0(DmP[9]), .A1(n1190), .B0(intDY[9]), .B1(n1195), .Y(
n1187) );
AOI22X1TS U1876 ( .A0(DmP[16]), .A1(n1162), .B0(intDY[16]), .B1(n1189), .Y(
n1191) );
AOI22X1TS U1877 ( .A0(DmP[4]), .A1(n1186), .B0(intDY[4]), .B1(n1195), .Y(
n1193) );
AOI22X1TS U1878 ( .A0(DmP[6]), .A1(n1196), .B0(intDY[6]), .B1(n1195), .Y(
n1194) );
AOI22X1TS U1879 ( .A0(DmP[5]), .A1(n1186), .B0(intDY[5]), .B1(n1195), .Y(
n1197) );
INVX2TS U1880 ( .A(n1645), .Y(n1643) );
INVX2TS U1881 ( .A(n671), .Y(n1497) );
INVX2TS U1882 ( .A(n1645), .Y(n1203) );
OAI222X1TS U1883 ( .A0(n1202), .A1(n1761), .B0(n1679), .B1(n653), .C0(n1201),
.C1(n1200), .Y(n86) );
NOR4BX1TS U1884 ( .AN(n1207), .B(n1290), .C(n1337), .D(n1291), .Y(n1204) );
NOR4BX1TS U1885 ( .AN(n1204), .B(n1286), .C(n1287), .D(n1288), .Y(n1206) );
INVX2TS U1886 ( .A(n1285), .Y(n1205) );
OAI22X1TS U1887 ( .A0(n1209), .A1(n1208), .B0(n1756), .B1(n1207), .Y(n69) );
OAI21X1TS U1888 ( .A0(FSM_selector_C), .A1(n1210), .B0(n1643), .Y(n1216) );
AOI22X1TS U1889 ( .A0(FS_Module_state_reg[0]), .A1(n1450), .B0(n1212), .B1(
n1712), .Y(n1213) );
NAND2X1TS U1890 ( .A(FS_Module_state_reg[2]), .B(n1215), .Y(n1220) );
XNOR2X1TS U1891 ( .A(n1223), .B(n1222), .Y(n1224) );
INVX2TS U1892 ( .A(n1225), .Y(n1271) );
NOR2X1TS U1893 ( .A(n1752), .B(n1271), .Y(n1262) );
INVX2TS U1894 ( .A(n1262), .Y(n1229) );
AOI21X1TS U1895 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1639), .B0(n1226), .Y(n1228) );
AOI22X1TS U1896 ( .A0(n676), .A1(Sgf_normalized_result[18]), .B0(n683), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .Y(n1227) );
NAND2X2TS U1897 ( .A(n1231), .B(n1273), .Y(n1261) );
AOI22X1TS U1898 ( .A0(n1237), .A1(n1232), .B0(n684), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n1235) );
AOI22X1TS U1899 ( .A0(n1272), .A1(Sgf_normalized_result[17]), .B0(n1639),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n1234) );
NAND2X1TS U1900 ( .A(n667), .B(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .Y(n1233) );
AOI22X1TS U1901 ( .A0(n1237), .A1(n1236), .B0(n685), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .Y(n1240) );
AOI22X1TS U1902 ( .A0(n676), .A1(Sgf_normalized_result[16]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(n1639), .Y(n1239)
);
NAND2X1TS U1903 ( .A(n668), .B(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .Y(n1238) );
AOI22X1TS U1904 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n906), .B0(Barrel_Shifter_module_Mux_Array_Data_array[49]), .B1(n668),
.Y(n1244) );
AOI22X1TS U1905 ( .A0(n1272), .A1(Sgf_normalized_result[15]), .B0(n685),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n1243) );
NAND2X1TS U1906 ( .A(n1241), .B(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n1242) );
AOI22X1TS U1907 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n906), .B0(Barrel_Shifter_module_Mux_Array_Data_array[48]), .B1(n668),
.Y(n1247) );
AOI22X1TS U1908 ( .A0(n676), .A1(Sgf_normalized_result[14]), .B0(n684), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n1246) );
NAND2X1TS U1909 ( .A(n1241), .B(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n1245) );
AOI22X1TS U1910 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n906), .B0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .B1(n668),
.Y(n1250) );
AOI22X1TS U1911 ( .A0(n1272), .A1(Sgf_normalized_result[13]), .B0(n685),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1249) );
NAND2X1TS U1912 ( .A(n1241), .B(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n1248) );
NAND2X1TS U1913 ( .A(n1241), .B(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1252) );
AOI22X1TS U1914 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n667), .B0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .B1(n906),
.Y(n1251) );
AOI21X1TS U1915 ( .A0(n684), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(n1253), .Y(n1254)
);
NAND2X1TS U1916 ( .A(n1261), .B(n1254), .Y(n59) );
AOI22X1TS U1917 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n1257) );
AOI22X1TS U1918 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .B0(n1272), .B1(
Sgf_normalized_result[11]), .Y(n1256) );
NAND2X1TS U1919 ( .A(n683), .B(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n1255) );
AOI22X1TS U1920 ( .A0(n906), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n667), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .Y(n1260) );
AOI22X1TS U1921 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .B0(n676), .B1(
Sgf_normalized_result[10]), .Y(n1259) );
NAND2X1TS U1922 ( .A(n684), .B(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n1258) );
AOI22X1TS U1923 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .B0(n667), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n1265) );
NAND2X1TS U1924 ( .A(n684), .B(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .Y(n1264) );
AOI22X1TS U1925 ( .A0(n1273), .A1(n1262), .B0(n1272), .B1(
Sgf_normalized_result[7]), .Y(n1263) );
AOI22X1TS U1926 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .B0(n668), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n1268) );
NAND2X1TS U1927 ( .A(n685), .B(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n1267) );
NOR2X1TS U1928 ( .A(n1751), .B(n1271), .Y(n1634) );
AOI22X1TS U1929 ( .A0(n1273), .A1(n1634), .B0(n676), .B1(
Sgf_normalized_result[6]), .Y(n1266) );
AOI22X1TS U1930 ( .A0(n1270), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .B0(n667), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n1277) );
NAND2X1TS U1931 ( .A(n685), .B(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n1276) );
NOR2X1TS U1932 ( .A(n1753), .B(n1271), .Y(n1630) );
AOI22X1TS U1933 ( .A0(n1273), .A1(n1630), .B0(n1272), .B1(
Sgf_normalized_result[5]), .Y(n1275) );
INVX2TS U1934 ( .A(n1651), .Y(n1646) );
AOI21X2TS U1935 ( .A0(n1280), .A1(n1279), .B0(n1278), .Y(n1282) );
MXI2X1TS U1936 ( .A(n1692), .B(add_overflow_flag), .S0(n1292), .Y(n71) );
OR2X1TS U1937 ( .A(Add_Subt_result[3]), .B(Add_Subt_result[2]), .Y(n1295) );
AOI22X1TS U1938 ( .A0(n1312), .A1(n1295), .B0(n1294), .B1(n1293), .Y(n1328)
);
AOI22X1TS U1939 ( .A0(Add_Subt_result[10]), .A1(n1302), .B0(n1301), .B1(
Add_Subt_result[1]), .Y(n1308) );
NOR2X1TS U1940 ( .A(Add_Subt_result[11]), .B(Add_Subt_result[13]), .Y(n1311)
);
NAND2X1TS U1941 ( .A(n1327), .B(n1662), .Y(n1310) );
AOI21X1TS U1942 ( .A0(n1308), .A1(n1307), .B0(n1334), .Y(n1309) );
AOI22X1TS U1943 ( .A0(Add_Subt_result[5]), .A1(n1313), .B0(
Add_Subt_result[3]), .B1(n1312), .Y(n1314) );
OAI31X1TS U1944 ( .A0(Add_Subt_result[12]), .A1(n1730), .A2(n1329), .B0(
n1328), .Y(n1330) );
NOR4X1TS U1945 ( .A(n1333), .B(n1332), .C(n1331), .D(n1330), .Y(n1335) );
MXI2X1TS U1946 ( .A(n1335), .B(n1758), .S0(n1334), .Y(n74) );
INVX2TS U1947 ( .A(n1338), .Y(n1340) );
NAND2X1TS U1948 ( .A(n1340), .B(n1339), .Y(n1341) );
XOR2X1TS U1949 ( .A(n1342), .B(n1341), .Y(n1343) );
XOR2X1TS U1950 ( .A(n1351), .B(n1352), .Y(n1345) );
NAND2X1TS U1951 ( .A(n1347), .B(n1346), .Y(n1348) );
XNOR2X1TS U1952 ( .A(n1349), .B(n1348), .Y(n1350) );
INVX2TS U1953 ( .A(n1353), .Y(n1355) );
NAND2X1TS U1954 ( .A(n1355), .B(n1354), .Y(n1356) );
XNOR2X1TS U1955 ( .A(n1357), .B(n1356), .Y(n1358) );
INVX2TS U1956 ( .A(n1359), .Y(n1361) );
NAND2X1TS U1957 ( .A(n1361), .B(n1360), .Y(n1362) );
XOR2X1TS U1958 ( .A(n1363), .B(n1362), .Y(n1364) );
INVX2TS U1959 ( .A(n1365), .Y(n1392) );
INVX2TS U1960 ( .A(n1366), .Y(n1377) );
NAND2X1TS U1961 ( .A(n1377), .B(n1375), .Y(n1367) );
XNOR2X1TS U1962 ( .A(n1392), .B(n1367), .Y(n1368) );
NAND2X1TS U1963 ( .A(n1370), .B(n1369), .Y(n1371) );
XNOR2X1TS U1964 ( .A(n1372), .B(n1371), .Y(n1374) );
INVX2TS U1965 ( .A(n1373), .Y(n1450) );
AOI21X1TS U1966 ( .A0(n1392), .A1(n1377), .B0(n1376), .Y(n1382) );
INVX2TS U1967 ( .A(n1378), .Y(n1380) );
NAND2X1TS U1968 ( .A(n1380), .B(n1379), .Y(n1381) );
XOR2X1TS U1969 ( .A(n1382), .B(n1381), .Y(n1383) );
INVX2TS U1970 ( .A(n1384), .Y(n1386) );
NAND2X1TS U1971 ( .A(n1386), .B(n1385), .Y(n1387) );
XOR2X1TS U1972 ( .A(n1388), .B(n1387), .Y(n1389) );
AOI21X1TS U1973 ( .A0(n1392), .A1(n1391), .B0(n1390), .Y(n1403) );
INVX2TS U1974 ( .A(n1402), .Y(n1393) );
NAND2X1TS U1975 ( .A(n1393), .B(n1401), .Y(n1394) );
XOR2X1TS U1976 ( .A(n1403), .B(n1394), .Y(n1395) );
NAND2X1TS U1977 ( .A(n1397), .B(n1396), .Y(n1398) );
XNOR2X1TS U1978 ( .A(n1399), .B(n1398), .Y(n1400) );
INVX2TS U1979 ( .A(n1404), .Y(n1406) );
NAND2X1TS U1980 ( .A(n1406), .B(n1405), .Y(n1407) );
XNOR2X1TS U1981 ( .A(n1408), .B(n1407), .Y(n1409) );
INVX2TS U1982 ( .A(n1410), .Y(n1412) );
NAND2X1TS U1983 ( .A(n1412), .B(n1411), .Y(n1413) );
XOR2X1TS U1984 ( .A(n1414), .B(n1413), .Y(n1415) );
INVX2TS U1985 ( .A(n1426), .Y(n1417) );
NAND2X1TS U1986 ( .A(n1417), .B(n1425), .Y(n1418) );
XOR2X1TS U1987 ( .A(n1464), .B(n1418), .Y(n1419) );
NAND2X1TS U1988 ( .A(n1421), .B(n1420), .Y(n1422) );
XNOR2X1TS U1989 ( .A(n1423), .B(n1422), .Y(n1424) );
INVX2TS U1990 ( .A(n1427), .Y(n1429) );
NAND2X1TS U1991 ( .A(n1429), .B(n1428), .Y(n1430) );
XNOR2X1TS U1992 ( .A(n1431), .B(n1430), .Y(n1432) );
INVX2TS U1993 ( .A(n1433), .Y(n1449) );
AOI21X1TS U1994 ( .A0(n1449), .A1(n694), .B0(n1434), .Y(n1438) );
NAND2X1TS U1995 ( .A(n1436), .B(n1435), .Y(n1437) );
XOR2X1TS U1996 ( .A(n1438), .B(n1437), .Y(n1439) );
INVX2TS U1997 ( .A(n1440), .Y(n1443) );
INVX2TS U1998 ( .A(n1441), .Y(n1442) );
OAI21X1TS U1999 ( .A0(n1464), .A1(n1443), .B0(n1442), .Y(n1455) );
INVX2TS U2000 ( .A(n1444), .Y(n1454) );
NAND2X1TS U2001 ( .A(n1454), .B(n1452), .Y(n1445) );
XNOR2X1TS U2002 ( .A(n1455), .B(n1445), .Y(n1446) );
NAND2X1TS U2003 ( .A(n694), .B(n1447), .Y(n1448) );
XNOR2X1TS U2004 ( .A(n1449), .B(n1448), .Y(n1451) );
INVX2TS U2005 ( .A(n1452), .Y(n1453) );
AOI21X1TS U2006 ( .A0(n1455), .A1(n1454), .B0(n1453), .Y(n1460) );
INVX2TS U2007 ( .A(n1456), .Y(n1458) );
NAND2X1TS U2008 ( .A(n1458), .B(n1457), .Y(n1459) );
XOR2X1TS U2009 ( .A(n1460), .B(n1459), .Y(n1461) );
OAI21X1TS U2010 ( .A0(n1464), .A1(n1463), .B0(n1462), .Y(n1489) );
INVX2TS U2011 ( .A(n1489), .Y(n1479) );
INVX2TS U2012 ( .A(n1465), .Y(n1468) );
INVX2TS U2013 ( .A(n1466), .Y(n1467) );
OAI21X1TS U2014 ( .A0(n1479), .A1(n1468), .B0(n1467), .Y(n1484) );
INVX2TS U2015 ( .A(n1469), .Y(n1482) );
INVX2TS U2016 ( .A(n1481), .Y(n1470) );
AOI21X1TS U2017 ( .A0(n1484), .A1(n1482), .B0(n1470), .Y(n1475) );
INVX2TS U2018 ( .A(n1471), .Y(n1473) );
NAND2X1TS U2019 ( .A(n1473), .B(n1472), .Y(n1474) );
XOR2X1TS U2020 ( .A(n1475), .B(n1474), .Y(n1476) );
CLKMX2X2TS U2021 ( .A(Add_Subt_result[14]), .B(n1476), .S0(n1495), .Y(n230)
);
INVX2TS U2022 ( .A(n1477), .Y(n1488) );
NAND2X1TS U2023 ( .A(n1488), .B(n1486), .Y(n1478) );
XOR2X1TS U2024 ( .A(n1479), .B(n1478), .Y(n1480) );
NAND2X1TS U2025 ( .A(n1482), .B(n1481), .Y(n1483) );
XNOR2X1TS U2026 ( .A(n1484), .B(n1483), .Y(n1485) );
INVX2TS U2027 ( .A(n1486), .Y(n1487) );
AOI21X1TS U2028 ( .A0(n1489), .A1(n1488), .B0(n1487), .Y(n1494) );
INVX2TS U2029 ( .A(n1490), .Y(n1492) );
NAND2X1TS U2030 ( .A(n1492), .B(n1491), .Y(n1493) );
XOR2X1TS U2031 ( .A(n1494), .B(n1493), .Y(n1496) );
AOI22X1TS U2032 ( .A0(n1037), .A1(n1505), .B0(n679), .B1(n1498), .Y(n1503)
);
AOI22X1TS U2033 ( .A0(n1499), .A1(n1596), .B0(n686), .B1(n1506), .Y(n1501)
);
BUFX3TS U2034 ( .A(n1500), .Y(n1591) );
AOI32X1TS U2035 ( .A0(n1503), .A1(n1502), .A2(n1501), .B0(n1591), .B1(n1502),
.Y(Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI22X1TS U2036 ( .A0(n679), .A1(n1506), .B0(n1596), .B1(n1505), .Y(n1512)
);
OA22X1TS U2037 ( .A0(n1509), .A1(n1508), .B0(n1507), .B1(n991), .Y(n1511) );
OAI2BB2XLTS U2038 ( .B0(n664), .B1(n1729), .A0N(DmP[13]), .A1N(n1560), .Y(
n1513) );
AOI21X1TS U2039 ( .A0(n669), .A1(Add_Subt_result[15]), .B0(n1513), .Y(n1534)
);
AOI22X2TS U2040 ( .A0(n1608), .A1(n1534), .B0(n1514), .B1(n1544), .Y(n1530)
);
AOI22X1TS U2041 ( .A0(n1590), .A1(n1525), .B0(n975), .B1(n1530), .Y(n1517)
);
AOI22X1TS U2042 ( .A0(n680), .A1(n1520), .B0(n1033), .B1(n1515), .Y(n1516)
);
NAND2X1TS U2043 ( .A(n1517), .B(n1516), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
OAI2BB2XLTS U2044 ( .B0(n664), .B1(n1730), .A0N(DmP[12]), .A1N(n1560), .Y(
n1518) );
AOI21X1TS U2045 ( .A0(n1604), .A1(Add_Subt_result[14]), .B0(n1518), .Y(n1539) );
AOI22X2TS U2046 ( .A0(n1608), .A1(n1539), .B0(n1519), .B1(n1544), .Y(n1535)
);
AOI22X1TS U2047 ( .A0(n1037), .A1(n1530), .B0(n686), .B1(n1535), .Y(n1522)
);
AOI22X1TS U2048 ( .A0(n1602), .A1(n1525), .B0(n1596), .B1(n1520), .Y(n1521)
);
NAND2X1TS U2049 ( .A(n1522), .B(n1521), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI21X1TS U2050 ( .A0(n1604), .A1(Add_Subt_result[13]), .B0(n1523), .Y(n1545) );
AOI22X2TS U2051 ( .A0(n1608), .A1(n1545), .B0(n1524), .B1(n1544), .Y(n1540)
);
AOI22X1TS U2052 ( .A0(n1611), .A1(n1535), .B0(n687), .B1(n1540), .Y(n1527)
);
AOI22X1TS U2053 ( .A0(n1602), .A1(n1530), .B0(n1600), .B1(n1525), .Y(n1526)
);
NAND2X1TS U2054 ( .A(n1527), .B(n1526), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI21X1TS U2055 ( .A0(n1604), .A1(Add_Subt_result[12]), .B0(n1528), .Y(n1550) );
AOI22X2TS U2056 ( .A0(n1608), .A1(n1550), .B0(n1529), .B1(n1605), .Y(n1546)
);
AOI22X1TS U2057 ( .A0(n1590), .A1(n1540), .B0(n686), .B1(n1546), .Y(n1532)
);
AOI22X1TS U2058 ( .A0(n1602), .A1(n1535), .B0(n1600), .B1(n1530), .Y(n1531)
);
NAND2X1TS U2059 ( .A(n1532), .B(n1531), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI22X1TS U2060 ( .A0(n670), .A1(Add_Subt_result[14]), .B0(DmP[9]), .B1(
n1582), .Y(n1533) );
OA21XLTS U2061 ( .A0(n1555), .A1(n1730), .B0(n1533), .Y(n1556) );
AOI22X2TS U2062 ( .A0(n1594), .A1(n1556), .B0(n1534), .B1(n1544), .Y(n1551)
);
AOI22X1TS U2063 ( .A0(n1037), .A1(n1546), .B0(n687), .B1(n1551), .Y(n1537)
);
AOI22X1TS U2064 ( .A0(n680), .A1(n1540), .B0(n1600), .B1(n1535), .Y(n1536)
);
NAND2X1TS U2065 ( .A(n1537), .B(n1536), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
INVX2TS U2066 ( .A(n991), .Y(n1590) );
AOI22X1TS U2067 ( .A0(n905), .A1(Add_Subt_result[15]), .B0(DmP[8]), .B1(
n1582), .Y(n1538) );
OA21XLTS U2068 ( .A0(n1555), .A1(n1729), .B0(n1538), .Y(n1562) );
AOI22X2TS U2069 ( .A0(n1594), .A1(n1562), .B0(n1539), .B1(n1605), .Y(n1557)
);
AOI22X1TS U2070 ( .A0(n1611), .A1(n1551), .B0(n686), .B1(n1557), .Y(n1542)
);
AOI22X1TS U2071 ( .A0(n680), .A1(n1546), .B0(n1033), .B1(n1540), .Y(n1541)
);
NAND2X1TS U2072 ( .A(n1542), .B(n1541), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U2073 ( .A0(n670), .A1(Add_Subt_result[16]), .B0(DmP[7]), .B1(
n1582), .Y(n1543) );
OA21XLTS U2074 ( .A0(n1555), .A1(n1738), .B0(n1543), .Y(n1567) );
AOI22X2TS U2075 ( .A0(n1594), .A1(n1567), .B0(n1545), .B1(n1544), .Y(n1563)
);
AOI22X1TS U2076 ( .A0(n1590), .A1(n1557), .B0(n975), .B1(n1563), .Y(n1548)
);
AOI22X1TS U2077 ( .A0(n680), .A1(n1551), .B0(n1033), .B1(n1546), .Y(n1547)
);
NAND2X1TS U2078 ( .A(n1548), .B(n1547), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI21X1TS U2079 ( .A0(n669), .A1(Add_Subt_result[8]), .B0(n1549), .Y(n1572)
);
AOI22X2TS U2080 ( .A0(n1594), .A1(n1572), .B0(n1550), .B1(n1591), .Y(n1568)
);
AOI22X1TS U2081 ( .A0(n1037), .A1(n1563), .B0(n687), .B1(n1568), .Y(n1553)
);
AOI22X1TS U2082 ( .A0(n1602), .A1(n1557), .B0(n1600), .B1(n1551), .Y(n1552)
);
NAND2X1TS U2083 ( .A(n1553), .B(n1552), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U2084 ( .A0(n1603), .A1(Add_Subt_result[18]), .B0(DmP[5]), .B1(
n1582), .Y(n1554) );
OA21XLTS U2085 ( .A0(n1555), .A1(n1736), .B0(n1554), .Y(n1576) );
AOI22X2TS U2086 ( .A0(n1594), .A1(n1576), .B0(n1556), .B1(n1591), .Y(n1573)
);
AOI22X1TS U2087 ( .A0(n1590), .A1(n1568), .B0(n687), .B1(n1573), .Y(n1559)
);
AOI22X1TS U2088 ( .A0(n680), .A1(n1563), .B0(n1033), .B1(n1557), .Y(n1558)
);
NAND2X1TS U2089 ( .A(n1559), .B(n1558), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
OAI2BB2XLTS U2090 ( .B0(n664), .B1(n1739), .A0N(DmP[4]), .A1N(n1560), .Y(
n1561) );
AOI21X1TS U2091 ( .A0(n1604), .A1(Add_Subt_result[6]), .B0(n1561), .Y(n1583)
);
AOI22X2TS U2092 ( .A0(n1594), .A1(n1583), .B0(n1562), .B1(n1591), .Y(n1579)
);
AOI22X1TS U2093 ( .A0(n1037), .A1(n1573), .B0(n686), .B1(n1579), .Y(n1565)
);
AOI22X1TS U2094 ( .A0(n1602), .A1(n1568), .B0(n1600), .B1(n1563), .Y(n1564)
);
NAND2X1TS U2095 ( .A(n1565), .B(n1564), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI21X1TS U2096 ( .A0(n1604), .A1(Add_Subt_result[5]), .B0(n1566), .Y(n1592)
);
AOI22X2TS U2097 ( .A0(n1594), .A1(n1592), .B0(n1567), .B1(n1591), .Y(n1587)
);
AOI22X1TS U2098 ( .A0(n1611), .A1(n1579), .B0(n687), .B1(n1587), .Y(n1570)
);
AOI22X1TS U2099 ( .A0(n680), .A1(n1573), .B0(n1033), .B1(n1568), .Y(n1569)
);
NAND2X1TS U2100 ( .A(n1570), .B(n1569), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI21X1TS U2101 ( .A0(n1604), .A1(Add_Subt_result[4]), .B0(n1571), .Y(n1606)
);
AOI22X2TS U2102 ( .A0(n1594), .A1(n1606), .B0(n1572), .B1(n1591), .Y(n1595)
);
AOI22X1TS U2103 ( .A0(n1590), .A1(n1587), .B0(n686), .B1(n1595), .Y(n1575)
);
AOI22X1TS U2104 ( .A0(n1602), .A1(n1579), .B0(n1600), .B1(n1573), .Y(n1574)
);
NAND2X1TS U2105 ( .A(n1575), .B(n1574), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U2106 ( .A0(n1603), .A1(Add_Subt_result[22]), .B0(DmP[1]), .B1(
n1582), .Y(n1578) );
NAND2X1TS U2107 ( .A(Add_Subt_result[3]), .B(n1604), .Y(n1577) );
AOI22X1TS U2108 ( .A0(n1037), .A1(n1595), .B0(n687), .B1(n1599), .Y(n1581)
);
AOI22X1TS U2109 ( .A0(n680), .A1(n1587), .B0(n1033), .B1(n1579), .Y(n1580)
);
NAND2X1TS U2110 ( .A(n1581), .B(n1580), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U2111 ( .A0(n670), .A1(Add_Subt_result[23]), .B0(DmP[0]), .B1(
n1582), .Y(n1586) );
NAND2X1TS U2112 ( .A(Add_Subt_result[2]), .B(n1604), .Y(n1584) );
AOI22X1TS U2113 ( .A0(n1611), .A1(n1599), .B0(n687), .B1(n1601), .Y(n1589)
);
AOI22X1TS U2114 ( .A0(n680), .A1(n1595), .B0(n1600), .B1(n1587), .Y(n1588)
);
NAND2X1TS U2115 ( .A(n1589), .B(n1588), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U2116 ( .A0(n1611), .A1(n1601), .B0(n680), .B1(n1599), .Y(n1598)
);
AOI22X1TS U2117 ( .A0(n1604), .A1(Add_Subt_result[1]), .B0(n1603), .B1(
Add_Subt_result[24]), .Y(n1593) );
AOI22X1TS U2118 ( .A0(n1594), .A1(n1593), .B0(n1592), .B1(n1591), .Y(n1610)
);
AOI22X1TS U2119 ( .A0(n686), .A1(n1610), .B0(n1033), .B1(n1595), .Y(n1597)
);
NAND2X1TS U2120 ( .A(n1598), .B(n1597), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
AOI22X1TS U2121 ( .A0(n1602), .A1(n1601), .B0(n1033), .B1(n1599), .Y(n1613)
);
AOI22X1TS U2122 ( .A0(n669), .A1(Add_Subt_result[0]), .B0(
Add_Subt_result[25]), .B1(n670), .Y(n1607) );
AOI22X1TS U2123 ( .A0(n1608), .A1(n1607), .B0(n1606), .B1(n1605), .Y(n1609)
);
AOI22X1TS U2124 ( .A0(n1611), .A1(n1610), .B0(n686), .B1(n1609), .Y(n1612)
);
NAND2X1TS U2125 ( .A(n1613), .B(n1612), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
OAI2BB2XLTS U2126 ( .B0(n1740), .B1(n671), .A0N(final_result_ieee[22]),
.A1N(n1629), .Y(n13) );
OAI2BB2XLTS U2127 ( .B0(n1741), .B1(n672), .A0N(final_result_ieee[21]),
.A1N(n1629), .Y(n16) );
INVX2TS U2128 ( .A(n1614), .Y(n1615) );
AOI21X1TS U2129 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[36]), .A1(
n1635), .B0(n1615), .Y(n1616) );
OA22X1TS U2130 ( .A0(n1638), .A1(n1741), .B0(n1616), .B1(n1636), .Y(n1618)
);
AOI22X1TS U2131 ( .A0(n684), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(n1617) );
OAI2BB2XLTS U2132 ( .B0(n1742), .B1(n673), .A0N(final_result_ieee[20]),
.A1N(n1629), .Y(n20) );
INVX2TS U2133 ( .A(n1619), .Y(n1620) );
AOI21X1TS U2134 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[37]), .A1(
n1635), .B0(n1620), .Y(n1621) );
OA22X1TS U2135 ( .A0(n1638), .A1(n1742), .B0(n1621), .B1(n1636), .Y(n1623)
);
AOI22X1TS U2136 ( .A0(n685), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(n1622) );
OAI2BB2XLTS U2137 ( .B0(n1731), .B1(n672), .A0N(final_result_ieee[19]),
.A1N(n1629), .Y(n24) );
INVX2TS U2138 ( .A(n1624), .Y(n1625) );
AOI21X1TS U2139 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[38]), .A1(
n1635), .B0(n1625), .Y(n1626) );
OA22X1TS U2140 ( .A0(n1638), .A1(n1731), .B0(n1626), .B1(n1636), .Y(n1628)
);
AOI22X1TS U2141 ( .A0(n684), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n1627) );
OAI2BB2XLTS U2142 ( .B0(n1732), .B1(n673), .A0N(final_result_ieee[18]),
.A1N(n1629), .Y(n28) );
AOI21X1TS U2143 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[39]), .A1(
n1635), .B0(n1630), .Y(n1631) );
OA22X1TS U2144 ( .A0(n1638), .A1(n1732), .B0(n1631), .B1(n1636), .Y(n1633)
);
AOI22X1TS U2145 ( .A0(n685), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n1632) );
OAI2BB2XLTS U2146 ( .B0(n1726), .B1(n672), .A0N(final_result_ieee[17]),
.A1N(n1203), .Y(n32) );
AOI21X1TS U2147 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[40]), .A1(
n1635), .B0(n1634), .Y(n1637) );
OA22X1TS U2148 ( .A0(n1638), .A1(n1726), .B0(n1637), .B1(n1636), .Y(n1642)
);
AOI22X1TS U2149 ( .A0(n684), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .B0(n1639), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n1641) );
OAI2BB2XLTS U2150 ( .B0(n1693), .B1(n671), .A0N(final_result_ieee[12]),
.A1N(n1643), .Y(n52) );
OAI2BB2XLTS U2151 ( .B0(n1716), .B1(n673), .A0N(final_result_ieee[11]),
.A1N(n1203), .Y(n56) );
OAI2BB2XLTS U2152 ( .B0(n1717), .B1(n673), .A0N(final_result_ieee[10]),
.A1N(n1643), .Y(n58) );
OA22X1TS U2153 ( .A0(exp_oper_result[7]), .A1(n672), .B0(n1644), .B1(
final_result_ieee[30]), .Y(n60) );
OA22X1TS U2154 ( .A0(exp_oper_result[6]), .A1(n673), .B0(n1644), .B1(
final_result_ieee[29]), .Y(n61) );
OA22X1TS U2155 ( .A0(exp_oper_result[5]), .A1(n672), .B0(n1644), .B1(
final_result_ieee[28]), .Y(n62) );
OA22X1TS U2156 ( .A0(n1644), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n672), .Y(n63) );
OA22X1TS U2157 ( .A0(n1644), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n673), .Y(n64) );
OA22X1TS U2158 ( .A0(n1644), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n672), .Y(n65) );
OA22X1TS U2159 ( .A0(n1644), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n673), .Y(n66) );
OA22X1TS U2160 ( .A0(n1645), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n673), .Y(n67) );
INVX2TS U2161 ( .A(n1651), .Y(n1648) );
BUFX3TS U2162 ( .A(n1654), .Y(n1657) );
OAI2BB2XLTS U2163 ( .B0(n1658), .B1(n1671), .A0N(n1657), .A1N(Data_Y[7]),
.Y(n111) );
OAI2BB2XLTS U2164 ( .B0(n1651), .B1(n1719), .A0N(n1655), .A1N(Data_Y[12]),
.Y(n126) );
BUFX3TS U2165 ( .A(n1651), .Y(n1649) );
INVX2TS U2166 ( .A(n1651), .Y(n1652) );
OAI2BB2XLTS U2167 ( .B0(n1658), .B1(n1724), .A0N(n1655), .A1N(Data_X[10]),
.Y(n193) );
BUFX3TS U2168 ( .A(n1654), .Y(n1656) );
OAI2BB2XLTS U2169 ( .B0(n1656), .B1(n1698), .A0N(n1655), .A1N(Data_X[13]),
.Y(n196) );
OAI2BB2XLTS U2170 ( .B0(n1656), .B1(n1699), .A0N(n1655), .A1N(Data_X[14]),
.Y(n197) );
OAI2BB2XLTS U2171 ( .B0(n1656), .B1(n1695), .A0N(n1655), .A1N(Data_X[15]),
.Y(n198) );
OAI2BB2XLTS U2172 ( .B0(n1656), .B1(n1733), .A0N(n1655), .A1N(Data_X[16]),
.Y(n199) );
OAI2BB2XLTS U2173 ( .B0(n1656), .B1(n1696), .A0N(n1655), .A1N(Data_X[17]),
.Y(n200) );
OAI2BB2XLTS U2174 ( .B0(n1656), .B1(n1697), .A0N(n1655), .A1N(Data_X[18]),
.Y(n201) );
OAI2BB2XLTS U2175 ( .B0(n1656), .B1(n1700), .A0N(n1655), .A1N(Data_X[19]),
.Y(n202) );
OAI2BB2XLTS U2176 ( .B0(n1656), .B1(n1659), .A0N(n1657), .A1N(Data_X[20]),
.Y(n203) );
OAI2BB2XLTS U2177 ( .B0(n1656), .B1(n1667), .A0N(n1657), .A1N(Data_X[21]),
.Y(n204) );
OAI2BB2XLTS U2178 ( .B0(n1656), .B1(n1668), .A0N(n1657), .A1N(Data_X[22]),
.Y(n205) );
OAI2BB2XLTS U2179 ( .B0(n1658), .B1(n1664), .A0N(n1657), .A1N(Data_X[23]),
.Y(n206) );
OAI2BB2XLTS U2180 ( .B0(n1658), .B1(n1669), .A0N(n1657), .A1N(Data_X[24]),
.Y(n207) );
OAI2BB2XLTS U2181 ( .B0(n1658), .B1(n1665), .A0N(n1657), .A1N(Data_X[25]),
.Y(n208) );
OAI2BB2XLTS U2182 ( .B0(n1658), .B1(n1670), .A0N(n1657), .A1N(Data_X[26]),
.Y(n209) );
OAI2BB2XLTS U2183 ( .B0(n1658), .B1(n1666), .A0N(n1657), .A1N(Data_X[27]),
.Y(n210) );
OAI2BB2XLTS U2184 ( .B0(n1658), .B1(n1723), .A0N(n1657), .A1N(Data_X[28]),
.Y(n211) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
|
module sky130_fd_sc_hd__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module cmd_seq #(
parameter BASEADDR = 32'h0000,
parameter HIGHADDR = 32'h0000,
parameter ABUSWIDTH = 16,
parameter OUTPUTS = 1,
parameter CMD_MEM_SIZE = 2048
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire [OUTPUTS-1:0] CMD_CLK_OUT,
input wire CMD_CLK_IN,
input wire CMD_EXT_START_FLAG,
output wire CMD_EXT_START_ENABLE,
output wire [OUTPUTS-1:0] CMD_DATA,
output wire CMD_READY,
output wire CMD_START_FLAG
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
cmd_seq_core #(
.CMD_MEM_SIZE(CMD_MEM_SIZE),
.ABUSWIDTH(ABUSWIDTH),
.OUTPUTS(OUTPUTS)
) i_cmd_seq_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CMD_CLK_OUT(CMD_CLK_OUT),
.CMD_CLK_IN(CMD_CLK_IN),
.CMD_EXT_START_FLAG(CMD_EXT_START_FLAG),
.CMD_EXT_START_ENABLE(CMD_EXT_START_ENABLE),
.CMD_DATA(CMD_DATA),
.CMD_READY(CMD_READY),
.CMD_START_FLAG(CMD_START_FLAG)
);
endmodule
|
module testbench;
localparam CLOCK_FREQ_HZ = 12e6;
localparam BAUD_RATE = 115200;
reg clk = 0;
initial begin
#(1.5e9 / CLOCK_FREQ_HZ);
forever #(0.5e9 / CLOCK_FREQ_HZ) clk = ~clk;
end
reg resetq = 0;
initial begin
repeat (100) @(posedge clk);
resetq <= 1;
end
reg RXD = 1;
wire TXD;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
// wait 10 bit times
repeat (10) #(1e9 / BAUD_RATE);
// send 'a' (b01100001)
#(1e9 / BAUD_RATE); RXD <= 0; // start bit
#(1e9 / BAUD_RATE); RXD <= 1; // data bit #0 (LSB)
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #1
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #2
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #3
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #4
#(1e9 / BAUD_RATE); RXD <= 1; // data bit #5
#(1e9 / BAUD_RATE); RXD <= 1; // data bit #6
#(1e9 / BAUD_RATE); RXD <= 0; // data bit #7 (MSB)
#(1e9 / BAUD_RATE); RXD <= 1; // stop bit
// wait 100 bit times
repeat (100) #(1e9 / BAUD_RATE);
$finish;
end
reg [7:0] tx_buffer;
integer i;
always begin
// tx start bit
@(negedge TXD);
#(0.5e9 / BAUD_RATE);
// tx data bits
tx_buffer = 0;
for (i = 0; i < 8; i = i+1) begin
#(1e9 / BAUD_RATE);
tx_buffer = tx_buffer | (TXD << i);
end
if (tx_buffer < 32)
$display("TX char: hex %02x", tx_buffer);
else
$display("TX char: '%c'", tx_buffer);
end
top uut (
.clk(clk),
.resetq(resetq),
.TXD(TXD),
.RXD(RXD)
);
endmodule
|
module binary_to_BCD_fourteen_bit_tb;
// Inputs
reg [13:0] in;
// Outputs
wire [3:0] ones;
wire [3:0] tens;
wire [3:0] hundreds;
wire [3:0] thousands;
// Instantiate the Unit Under Test (UUT)
binary_to_BCD_fourteen_bit uut (
.in(in),
.ones(ones),
.tens(tens),
.hundreds(hundreds),
.thousands(thousands)
);
initial begin
// Initialize Inputs
in = 0;
for (in =0;in< 10000;in = in +1) begin
#10
$display(" in = %d thousands = %d hundreds = %d tens = %d ones = %d",in, thousands, hundreds, tens, ones);
end
end
endmodule
|
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module sky130_fd_sc_ls__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
`ROI
roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
|
module roi_brami_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
|
module roi_brami_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
|
module roi_bramis_bit0(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b0))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
|
module roi_bramis_bit1(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y42"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y44"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y46"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y48"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y50"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y52"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y54"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y56"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y58"), .INIT0(1'b0), .INIT({256{1'b0}}), .IS_ENARDEN_INVERTED(1'b1))
r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
endmodule
|
module roi_invalid(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .INIT({256{1'b1}}))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
ram_RAMB18E1 #(.LOC("RAMB18_X0Y41"), .INIT({256{1'b1}}))
r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT({256{1'b1}}))
r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
endmodule
|
module roi_bram18_width_a(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .READ_WIDTH_A(1))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
|
module roi_bram18_width_b(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .READ_WIDTH_A(0))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
|
module roi_bram18_write_mode_a(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .WRITE_MODE_A("WRITE_FIRST"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
|
module roi_bram18_write_mode_b(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .WRITE_MODE_A("NO_CHANGE"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
|
module roi_bram18_ram_mode_tdp(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .RAM_MODE("TDP"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
|
module roi_bram18_ram_mode_sdp(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .RAM_MODE("SDP"))
r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule
|
module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RAM_MODE = "TDP";
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter SRVAL_A = 18'b0;
parameter SRVAL_B = 18'b0;
parameter INIT_A = 18'b0;
parameter INIT_B = 18'b0;
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
(* LOC=LOC *)
RAMB18E1 #(
.INITP_00(INIT),
.INITP_01(INIT),
.INITP_02(INIT),
.INITP_03(INIT),
.INITP_04(INIT),
.INITP_05(INIT),
.INITP_06(INIT),
.INITP_07(INIT),
.INIT_00(INIT0),
.INIT_01(INIT),
.INIT_02(INIT),
.INIT_03(INIT),
.INIT_04(INIT),
.INIT_05(INIT),
.INIT_06(INIT),
.INIT_07(INIT),
.INIT_08(INIT),
.INIT_09(INIT),
.INIT_0A(INIT),
.INIT_0B(INIT),
.INIT_0C(INIT),
.INIT_0D(INIT),
.INIT_0E(INIT),
.INIT_0F(INIT),
.INIT_10(INIT),
.INIT_11(INIT),
.INIT_12(INIT),
.INIT_13(INIT),
.INIT_14(INIT),
.INIT_15(INIT),
.INIT_16(INIT),
.INIT_17(INIT),
.INIT_18(INIT),
.INIT_19(INIT),
.INIT_1A(INIT),
.INIT_1B(INIT),
.INIT_1C(INIT),
.INIT_1D(INIT),
.INIT_1E(INIT),
.INIT_1F(INIT),
.INIT_20(INIT),
.INIT_21(INIT),
.INIT_22(INIT),
.INIT_23(INIT),
.INIT_24(INIT),
.INIT_25(INIT),
.INIT_26(INIT),
.INIT_27(INIT),
.INIT_28(INIT),
.INIT_29(INIT),
.INIT_2A(INIT),
.INIT_2B(INIT),
.INIT_2C(INIT),
.INIT_2D(INIT),
.INIT_2E(INIT),
.INIT_2F(INIT),
.INIT_30(INIT),
.INIT_31(INIT),
.INIT_32(INIT),
.INIT_33(INIT),
.INIT_34(INIT),
.INIT_35(INIT),
.INIT_36(INIT),
.INIT_37(INIT),
.INIT_38(INIT),
.INIT_39(INIT),
.INIT_3A(INIT),
.INIT_3B(INIT),
.INIT_3C(INIT),
.INIT_3D(INIT),
.INIT_3E(INIT),
.INIT_3F(INIT),
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RAM_MODE(RAM_MODE),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B)
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
|
module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_ENARDEN_INVERTED = 1'b0;
(* LOC=LOC *)
RAMB36E1 #(
.INITP_00(INIT),
.INITP_01(INIT),
.INITP_02(INIT),
.INITP_03(INIT),
.INITP_04(INIT),
.INITP_05(INIT),
.INITP_06(INIT),
.INITP_07(INIT),
.INITP_08(INIT),
.INITP_09(INIT),
.INITP_0A(INIT),
.INITP_0B(INIT),
.INITP_0C(INIT),
.INITP_0D(INIT),
.INITP_0E(INIT),
.INITP_0F(INIT),
.INIT_00(INIT0),
.INIT_01(INIT),
.INIT_02(INIT),
.INIT_03(INIT),
.INIT_04(INIT),
.INIT_05(INIT),
.INIT_06(INIT),
.INIT_07(INIT),
.INIT_08(INIT),
.INIT_09(INIT),
.INIT_0A(INIT),
.INIT_0B(INIT),
.INIT_0C(INIT),
.INIT_0D(INIT),
.INIT_0E(INIT),
.INIT_0F(INIT),
.INIT_10(INIT),
.INIT_11(INIT),
.INIT_12(INIT),
.INIT_13(INIT),
.INIT_14(INIT),
.INIT_15(INIT),
.INIT_16(INIT),
.INIT_17(INIT),
.INIT_18(INIT),
.INIT_19(INIT),
.INIT_1A(INIT),
.INIT_1B(INIT),
.INIT_1C(INIT),
.INIT_1D(INIT),
.INIT_1E(INIT),
.INIT_1F(INIT),
.INIT_20(INIT),
.INIT_21(INIT),
.INIT_22(INIT),
.INIT_23(INIT),
.INIT_24(INIT),
.INIT_25(INIT),
.INIT_26(INIT),
.INIT_27(INIT),
.INIT_28(INIT),
.INIT_29(INIT),
.INIT_2A(INIT),
.INIT_2B(INIT),
.INIT_2C(INIT),
.INIT_2D(INIT),
.INIT_2E(INIT),
.INIT_2F(INIT),
.INIT_30(INIT),
.INIT_31(INIT),
.INIT_32(INIT),
.INIT_33(INIT),
.INIT_34(INIT),
.INIT_35(INIT),
.INIT_36(INIT),
.INIT_37(INIT),
.INIT_38(INIT),
.INIT_39(INIT),
.INIT_3A(INIT),
.INIT_3B(INIT),
.INIT_3C(INIT),
.INIT_3D(INIT),
.INIT_3E(INIT),
.INIT_3F(INIT),
.INIT_40(INIT),
.INIT_41(INIT),
.INIT_42(INIT),
.INIT_43(INIT),
.INIT_44(INIT),
.INIT_45(INIT),
.INIT_46(INIT),
.INIT_47(INIT),
.INIT_48(INIT),
.INIT_49(INIT),
.INIT_4A(INIT),
.INIT_4B(INIT),
.INIT_4C(INIT),
.INIT_4D(INIT),
.INIT_4E(INIT),
.INIT_4F(INIT),
.INIT_50(INIT),
.INIT_51(INIT),
.INIT_52(INIT),
.INIT_53(INIT),
.INIT_54(INIT),
.INIT_55(INIT),
.INIT_56(INIT),
.INIT_57(INIT),
.INIT_58(INIT),
.INIT_59(INIT),
.INIT_5A(INIT),
.INIT_5B(INIT),
.INIT_5C(INIT),
.INIT_5D(INIT),
.INIT_5E(INIT),
.INIT_5F(INIT),
.INIT_60(INIT),
.INIT_61(INIT),
.INIT_62(INIT),
.INIT_63(INIT),
.INIT_64(INIT),
.INIT_65(INIT),
.INIT_66(INIT),
.INIT_67(INIT),
.INIT_68(INIT),
.INIT_69(INIT),
.INIT_6A(INIT),
.INIT_6B(INIT),
.INIT_6C(INIT),
.INIT_6D(INIT),
.INIT_6E(INIT),
.INIT_6F(INIT),
.INIT_70(INIT),
.INIT_71(INIT),
.INIT_72(INIT),
.INIT_73(INIT),
.INIT_74(INIT),
.INIT_75(INIT),
.INIT_76(INIT),
.INIT_77(INIT),
.INIT_78(INIT),
.INIT_79(INIT),
.INIT_7A(INIT),
.INIT_7B(INIT),
.INIT_7C(INIT),
.INIT_7D(INIT),
.INIT_7E(INIT),
.INIT_7F(INIT),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule
|
module sky130_fd_sc_hd__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module sky130_fd_sc_ms__a32oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__a32oi_2 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
|
module sky130_fd_sc_ms__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module out_switch(
input clk,
input reset,
output [239:0] TRIG0,
input [63:0] pb_out_data0,
input [23:0] pb_out_pkt_route0,
input pb_out_wr0,
input pb_out_req0,
output pb_out_ack0,
input [1:0] pb_out_neighbor0,
input pb_out_bop0,
input pb_out_eop0,
output pb_out_rdy0,
input pb_out_bypass0,
input [63:0] pb_out_data1,
input [23:0] pb_out_pkt_route1,
input pb_out_wr1,
input pb_out_req1,
output pb_out_ack1,
input [1:0] pb_out_neighbor1,
input pb_out_bop1,
input pb_out_eop1,
output pb_out_rdy1,
input pb_out_bypass1,
input [63:0] pb_out_data2,
input [23:0] pb_out_pkt_route2,
input pb_out_wr2,
input pb_out_req2,
output pb_out_ack2,
input [1:0] pb_out_neighbor2,
input pb_out_bop2,
input pb_out_eop2,
output pb_out_rdy2,
input pb_out_bypass2,
input [63:0] pb_out_data3,
input [23:0] pb_out_pkt_route3,
input pb_out_wr3,
input pb_out_req3,
output pb_out_ack3,
input [1:0] pb_out_neighbor3,
input pb_out_bop3,
input pb_out_eop3,
output pb_out_rdy3,
input pb_out_bypass3,
//4 bypass packet buffers
input [63:0] pb_out_data4,
input [23:0] pb_out_pkt_route4,
input pb_out_wr4,
input pb_out_req4,
output pb_out_ack4,
input [1:0] pb_out_neighbor4,
input pb_out_bop4,
input pb_out_eop4,
output pb_out_rdy4,
input pb_out_bypass4,
input [63:0] pb_out_data5,
input [23:0] pb_out_pkt_route5,
input pb_out_wr5,
input pb_out_req5,
output pb_out_ack5,
input [1:0] pb_out_neighbor5,
input pb_out_bop5,
input pb_out_eop5,
output pb_out_rdy5,
input pb_out_bypass5,
// input [63:0] pb_out_data6,
// input [23:0] pb_out_pkt_route6,
// input pb_out_wr6,
// input pb_out_req6,
// output pb_out_ack6,
// input [1:0] pb_out_neighbor6,
// input pb_out_bop6,
// input pb_out_eop6,
// output pb_out_rdy6,
// input pb_out_bypass6,
// input [63:0] pb_out_data7,
// input [23:0] pb_out_pkt_route7,
// input pb_out_wr7,
// input pb_out_req7,
// output pb_out_ack7,
// input [1:0] pb_out_neighbor7,
// input pb_out_bop7,
// input pb_out_eop7,
// output pb_out_rdy7,
// input pb_out_bypass7,
output reg [63:0] out_data0,
output reg [23:0] out_pkt_route0,
output reg out_wr0,
output reg out_req0,
input out_ack0,
output reg out_bop0,
output reg out_eop0,
input out_rdy0,
output reg out_bypass0,
output reg [63:0] out_data1,
output reg [23:0] out_pkt_route1,
output reg out_wr1,
output reg out_req1,
input out_ack1,
output reg out_bop1,
output reg out_eop1,
input out_rdy1,
output reg out_bypass1,
output reg [63:0] out_data2,
output reg [23:0] out_pkt_route2,
output reg out_wr2,
output reg out_req2,
input out_ack2,
output reg out_bop2,
output reg out_eop2,
input out_rdy2,
output reg out_bypass2,
output reg [63:0] out_data3,
output reg [23:0] out_pkt_route3,
output reg out_wr3,
output reg out_req3,
input out_ack3,
output reg out_bop3,
output reg out_eop3,
input out_rdy3,
output reg out_bypass3
);
reg [7:0] pb_out_ack;
assign pb_out_ack0 = pb_out_ack[0];
assign pb_out_ack1 = pb_out_ack[1];
assign pb_out_ack2 = pb_out_ack[2];
assign pb_out_ack3 = pb_out_ack[3];
assign pb_out_ack4 = pb_out_ack[4];
assign pb_out_ack5 = pb_out_ack[5];
//assign pb_out_ack6 = pb_out_ack[6];
//assign pb_out_ack7 = pb_out_ack[7];
wire [7:0] pb_out_req;
assign pb_out_req[0] = pb_out_req0;
assign pb_out_req[1] = pb_out_req1;
assign pb_out_req[2] = pb_out_req2;
assign pb_out_req[3] = pb_out_req3;
assign pb_out_req[4] = pb_out_req4;
assign pb_out_req[5] = pb_out_req5;
//assign pb_out_req[6] = pb_out_req6;
//assign pb_out_req[7] = pb_out_req7;
wire [1:0] pb_out_neighbor[7:0];
assign pb_out_neighbor[0] = pb_out_neighbor0;
assign pb_out_neighbor[1] = pb_out_neighbor1;
assign pb_out_neighbor[2] = pb_out_neighbor2;
assign pb_out_neighbor[3] = pb_out_neighbor3;
assign pb_out_neighbor[4] = pb_out_neighbor4;
assign pb_out_neighbor[5] = pb_out_neighbor5;
//assign pb_out_neighbor[6] = pb_out_neighbor6;
//assign pb_out_neighbor[7] = pb_out_neighbor7;
wire pb_out_bypass[7:0];
assign pb_out_bypass[0] = pb_out_bypass0;
assign pb_out_bypass[1] = pb_out_bypass1;
assign pb_out_bypass[2] = pb_out_bypass2;
assign pb_out_bypass[3] = pb_out_bypass3;
assign pb_out_bypass[4] = pb_out_bypass4;
assign pb_out_bypass[5] = pb_out_bypass5;
//assign pb_out_bypass[6] = pb_out_bypass6;
//assign pb_out_bypass[7] = pb_out_bypass7;
wire [63:0] pb_out_data [7:0];
assign pb_out_data[0] = pb_out_data0;
assign pb_out_data[1] = pb_out_data1;
assign pb_out_data[2] = pb_out_data2;
assign pb_out_data[3] = pb_out_data3;
assign pb_out_data[4] = pb_out_data4;
assign pb_out_data[5] = pb_out_data5;
//assign pb_out_data[6] = pb_out_data6;
//assign pb_out_data[7] = pb_out_data7;
wire [23:0] pb_out_pkt_route [7:0];
assign pb_out_pkt_route[0] = pb_out_pkt_route0;
assign pb_out_pkt_route[1] = pb_out_pkt_route1;
assign pb_out_pkt_route[2] = pb_out_pkt_route2;
assign pb_out_pkt_route[3] = pb_out_pkt_route3;
assign pb_out_pkt_route[4] = pb_out_pkt_route4;
assign pb_out_pkt_route[5] = pb_out_pkt_route5;
//assign pb_out_pkt_route[6] = pb_out_pkt_route6;
//assign pb_out_pkt_route[7] = pb_out_pkt_route7;
wire [7:0] pb_out_wr;
assign pb_out_wr[0] = pb_out_wr0;
assign pb_out_wr[1] = pb_out_wr1;
assign pb_out_wr[2] = pb_out_wr2;
assign pb_out_wr[3] = pb_out_wr3;
assign pb_out_wr[4] = pb_out_wr4;
assign pb_out_wr[5] = pb_out_wr5;
//assign pb_out_wr[6] = pb_out_wr6;
//assign pb_out_wr[7] = pb_out_wr7;
wire [7:0] pb_out_bop;
assign pb_out_bop[0] = pb_out_bop0;
assign pb_out_bop[1] = pb_out_bop1;
assign pb_out_bop[2] = pb_out_bop2;
assign pb_out_bop[3] = pb_out_bop3;
assign pb_out_bop[4] = pb_out_bop4;
assign pb_out_bop[5] = pb_out_bop5;
//assign pb_out_bop[6] = pb_out_bop6;
//assign pb_out_bop[7] = pb_out_bop7;
wire [7:0] pb_out_eop;
assign pb_out_eop[0] = pb_out_eop0;
assign pb_out_eop[1] = pb_out_eop1;
assign pb_out_eop[2] = pb_out_eop2;
assign pb_out_eop[3] = pb_out_eop3;
assign pb_out_eop[4] = pb_out_eop4;
assign pb_out_eop[5] = pb_out_eop5;
//assign pb_out_eop[6] = pb_out_eop6;
//assign pb_out_eop[7] = pb_out_eop7;
reg tx_in_progress0;
reg tx_in_progress1;
reg tx_in_progress2;
reg tx_in_progress3;
reg [2:0] curr_buff0;
reg [2:0] curr_buff1;
reg [2:0] curr_buff2;
reg [2:0] curr_buff3;
reg [2:0] curr_buff0_next;
reg [2:0] curr_buff1_next;
reg [2:0] curr_buff2_next;
reg [2:0] curr_buff3_next;
wire [2:0] curr_buff0_plus_1;
wire [2:0] curr_buff1_plus_1;
wire [2:0] curr_buff2_plus_1;
wire [2:0] curr_buff3_plus_1;
assign curr_buff0_plus_1 = (curr_buff0 == 3'b101) ? 0 : curr_buff0 + 1;
assign curr_buff1_plus_1 = (curr_buff1 == 3'b101) ? 0 : curr_buff1 + 1;
assign curr_buff2_plus_1 = (curr_buff2 == 3'b101) ? 0 : curr_buff2 + 1;
assign curr_buff3_plus_1 = (curr_buff3 == 3'b101) ? 0 : curr_buff3 + 1;
wire [1:0] pb_nei0;
wire [1:0] pb_nei1;
wire [1:0] pb_nei2;
wire [1:0] pb_nei3;
assign pb_nei0 = pb_out_neighbor[curr_buff0];
assign pb_nei1 = pb_out_neighbor[curr_buff1];
assign pb_nei2 = pb_out_neighbor[curr_buff2];
assign pb_nei3 = pb_out_neighbor[curr_buff3];
wire pb_bypass0;
wire pb_bypass1;
wire pb_bypass2;
wire pb_bypass3;
assign pb_bypass0 = pb_out_bypass[curr_buff0];
assign pb_bypass1 = pb_out_bypass[curr_buff1];
assign pb_bypass2 = pb_out_bypass[curr_buff2];
assign pb_bypass3 = pb_out_bypass[curr_buff3];
parameter OS_IDLE = 3'b001,
OS_LOOKUP_BUFF = 3'b010,
OS_PORT_REQ = 3'b011,
OS_TX = 3'b100,
OS_CANCEL = 3'b101;
reg [2:0] os_state0;
reg [2:0] os_state_next0;
reg [2:0] os_state1;
reg [2:0] os_state_next1;
reg [2:0] os_state2;
reg [2:0] os_state_next2;
reg [2:0] os_state3;
reg [2:0] os_state_next3;
always @(*)
begin
pb_out_ack = 0;
curr_buff0_next = curr_buff0;
os_state_next0 = os_state0;
case(os_state0)
OS_IDLE: begin
out_bypass0 = 0;
out_req0 = 0;
tx_in_progress0 = 0;
os_state_next0 = OS_LOOKUP_BUFF;
end
OS_LOOKUP_BUFF: begin
out_req0 = 0;
if(pb_out_req[curr_buff0]) begin
if(pb_nei0 == 2'b00) begin
os_state_next0 = OS_PORT_REQ;
end else begin
curr_buff0_next = curr_buff0_plus_1;
end
end else begin
curr_buff0_next = curr_buff0_plus_1;
end
end
OS_PORT_REQ: begin
out_bypass0 = pb_bypass0;
out_req0 = 1;
if(out_ack0) begin
os_state_next0 = OS_TX;
end
end
OS_TX: begin
out_req0 = 1;
if(pb_out_req[curr_buff0]) begin
tx_in_progress0 = 1;
pb_out_ack[curr_buff0] = 1;
end else begin
tx_in_progress0 = 0;
os_state_next0 = OS_CANCEL;
end
end
OS_CANCEL: begin
out_req0 = 0;
if(!out_ack0) begin
pb_out_ack[curr_buff0] = 0;
os_state_next0 = OS_IDLE;
end
end
default: begin
out_bypass0 = 0;
out_req0 = 0;
tx_in_progress0 = 0;
os_state_next0 = OS_IDLE;
end
endcase
curr_buff1_next = curr_buff1;
os_state_next1 = os_state1;
case(os_state1)
OS_IDLE: begin
out_bypass1 = 0;
out_req1 = 0;
tx_in_progress1 = 0;
os_state_next1 = OS_LOOKUP_BUFF;
end
OS_LOOKUP_BUFF: begin
out_req1 = 0;
if(pb_out_req[curr_buff1]) begin
if(pb_nei1 == 2'b01) begin
os_state_next1 = OS_PORT_REQ;
end else begin
curr_buff1_next = curr_buff1_plus_1;
end
end else begin
curr_buff1_next = curr_buff1_plus_1;
end
end
OS_PORT_REQ: begin
out_bypass1 = pb_bypass1;
out_req1 = 1;
if(out_ack1) begin
os_state_next1 = OS_TX;
end
end
OS_TX: begin
out_req1 = 1;
if(pb_out_req[curr_buff1]) begin
tx_in_progress1 = 1;
pb_out_ack[curr_buff1] = 1;
end else begin
tx_in_progress1 = 0;
os_state_next1 = OS_CANCEL;
end
end
OS_CANCEL: begin
out_req1 = 0;
if(!out_ack1) begin
pb_out_ack[curr_buff1] = 0;
os_state_next1 = OS_IDLE;
end
end
default: begin
out_bypass1 = 0;
out_req1 = 0;
tx_in_progress1 = 0;
os_state_next1 = OS_IDLE;
end
endcase
curr_buff2_next = curr_buff2;
os_state_next2 = os_state2;
case(os_state2)
OS_IDLE: begin
out_bypass2 = 0;
out_req2 = 0;
tx_in_progress2 = 0;
os_state_next2 = OS_LOOKUP_BUFF;
end
OS_LOOKUP_BUFF: begin
out_req2 = 0;
if(pb_out_req[curr_buff2]) begin
if(pb_nei2 == 2'b10) begin
os_state_next2 = OS_PORT_REQ;
end else begin
curr_buff2_next = curr_buff2_plus_1;
end
end else begin
curr_buff2_next = curr_buff2_plus_1;
end
end
OS_PORT_REQ: begin
out_bypass2 = pb_bypass2;
out_req2 = 1;
if(out_ack2) begin
os_state_next2 = OS_TX;
end
end
OS_TX: begin
out_req2 = 1;
if(pb_out_req[curr_buff2]) begin
tx_in_progress2 = 1;
pb_out_ack[curr_buff2] = 1;
end else begin
tx_in_progress2 = 0;
os_state_next2 = OS_CANCEL;
end
end
OS_CANCEL: begin
out_req2 = 0;
if(!out_ack2) begin
pb_out_ack[curr_buff2] = 0;
os_state_next2 = OS_IDLE;
end
end
default: begin
out_bypass2 = 0;
out_req2 = 0;
tx_in_progress2 = 0;
os_state_next2 = OS_IDLE;
end
endcase
curr_buff3_next = curr_buff3;
os_state_next3 = os_state3;
case(os_state3)
OS_IDLE: begin
out_bypass3 = 0;
out_req3 = 0;
tx_in_progress3 = 0;
os_state_next3 = OS_LOOKUP_BUFF;
end
OS_LOOKUP_BUFF: begin
out_req3 = 0;
if(pb_out_req[curr_buff3]) begin
if(pb_nei3 == 2'b11) begin
os_state_next3 = OS_PORT_REQ;
end else begin
curr_buff3_next = curr_buff3_plus_1;
end
end else begin
curr_buff3_next = curr_buff3_plus_1;
end
end
OS_PORT_REQ: begin
out_bypass3 = pb_bypass3;
out_req3 = 1;
if(out_ack3) begin
os_state_next3 = OS_TX;
end
end
OS_TX: begin
out_req3 = 1;
if(pb_out_req[curr_buff3]) begin
tx_in_progress3 = 1;
pb_out_ack[curr_buff3] = 1;
end else begin
tx_in_progress3 = 0;
os_state_next3 = OS_CANCEL;
end
end
OS_CANCEL: begin
out_req3 = 0;
if(!out_ack3) begin
pb_out_ack[curr_buff3] = 0;
os_state_next3 = OS_IDLE;
end
end
default: begin
out_bypass3 = 0;
out_req3 = 0;
tx_in_progress3 = 0;
os_state_next3 = OS_IDLE;
end
endcase
end
always @(posedge clk)
begin
if(reset) begin
os_state0 <= 0;
os_state1 <= 0;
os_state2 <= 0;
os_state3 <= 0;
curr_buff0 <= 0;
curr_buff1 <= 0;
curr_buff2 <= 0;
curr_buff3 <= 0;
end else begin
os_state0 <= os_state_next0;
os_state1 <= os_state_next1;
os_state2 <= os_state_next2;
os_state3 <= os_state_next3;
curr_buff0 <= curr_buff0_next;
curr_buff1 <= curr_buff1_next;
curr_buff2 <= curr_buff2_next;
curr_buff3 <= curr_buff3_next;
if(tx_in_progress0) begin
out_data0 <= pb_out_data[curr_buff0];
out_pkt_route0 <= pb_out_pkt_route[curr_buff0];
out_wr0 <= pb_out_wr[curr_buff0];
out_bop0 <= pb_out_bop[curr_buff0];
out_eop0 <= pb_out_eop[curr_buff0];
end
if(tx_in_progress1) begin
out_data1 <= pb_out_data[curr_buff1];
out_pkt_route1 <= pb_out_pkt_route[curr_buff1];
out_wr1 <= pb_out_wr[curr_buff1];
out_bop1 <= pb_out_bop[curr_buff1];
out_eop1 <= pb_out_eop[curr_buff1];
end
if(tx_in_progress2) begin
out_data2 <= pb_out_data[curr_buff2];
out_pkt_route2 <= pb_out_pkt_route[curr_buff2];
out_wr2 <= pb_out_wr[curr_buff2];
out_bop2 <= pb_out_bop[curr_buff2];
out_eop2 <= pb_out_eop[curr_buff2];
end
if(tx_in_progress3) begin
out_data3 <= pb_out_data[curr_buff3];
out_pkt_route3 <= pb_out_pkt_route[curr_buff3];
out_wr3 <= pb_out_wr[curr_buff3];
out_bop3 <= pb_out_bop[curr_buff3];
out_eop3 <= pb_out_eop[curr_buff3];
end
end
end
assign pb_out_rdy0 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b000) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b000) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b000) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b000) ? out_rdy3 : 0 ;
assign pb_out_rdy1 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b001) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b001) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b001) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b001) ? out_rdy3 : 0 ;
assign pb_out_rdy2 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b010) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b010) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b010) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b010) ? out_rdy3 : 0 ;
assign pb_out_rdy3 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b011) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b011) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b011) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b011) ? out_rdy3 : 0 ;
assign pb_out_rdy4 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b100) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b100) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b100) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b100) ? out_rdy3 : 0 ;
assign pb_out_rdy5 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b101) ? out_rdy0 :
(tx_in_progress1 == 1'b1 && curr_buff1 == 3'b101) ? out_rdy1 :
(tx_in_progress2 == 1'b1 && curr_buff2 == 3'b101) ? out_rdy2 :
(tx_in_progress3 == 1'b1 && curr_buff3 == 3'b101) ? out_rdy3 : 0 ;
//assign pb_out_rdy6 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b110) ? out_rdy0 :
// (tx_in_progress1 == 1'b1 && curr_buff1 == 3'b110) ? out_rdy1 :
// (tx_in_progress2 == 1'b1 && curr_buff2 == 3'b110) ? out_rdy2 :
// (tx_in_progress3 == 1'b1 && curr_buff3 == 3'b110) ? out_rdy3 : 0 ;
//assign pb_out_rdy7 = (tx_in_progress0 == 1'b1 && curr_buff0 == 3'b111) ? out_rdy0 :
// (tx_in_progress1 == 1'b1 && curr_buff1 == 3'b111) ? out_rdy1 :
// (tx_in_progress2 == 1'b1 && curr_buff2 == 3'b111) ? out_rdy2 :
// (tx_in_progress3 == 1'b1 && curr_buff3 == 3'b111) ? out_rdy3 : 0 ;
assign TRIG0[0] = pb_out_wr0;
assign TRIG0[1] = pb_out_req0;
assign TRIG0[2] = pb_out_ack0;
assign TRIG0[4:3] = pb_out_neighbor0;
assign TRIG0[5] = pb_out_bop0;
assign TRIG0[6] = pb_out_eop0;
assign TRIG0[7] = pb_out_rdy0;
assign TRIG0[8] = pb_out_bypass0;
assign TRIG0[10] = pb_out_wr1;
assign TRIG0[11] = pb_out_req1;
assign TRIG0[12] = pb_out_ack1;
assign TRIG0[14:13] = pb_out_neighbor1;
assign TRIG0[15] = pb_out_bop1;
assign TRIG0[16] = pb_out_eop1;
assign TRIG0[17] = pb_out_rdy1;
assign TRIG0[18] = pb_out_bypass1;
assign TRIG0[20] = pb_out_wr2;
assign TRIG0[21] = pb_out_req2;
assign TRIG0[22] = pb_out_ack2;
assign TRIG0[24:23] = pb_out_neighbor2;
assign TRIG0[25] = pb_out_bop2;
assign TRIG0[26] = pb_out_eop2;
assign TRIG0[27] = pb_out_rdy2;
assign TRIG0[28] = pb_out_bypass2;
assign TRIG0[30] = pb_out_wr3;
assign TRIG0[31] = pb_out_req3;
assign TRIG0[32] = pb_out_ack3;
assign TRIG0[34:33] = pb_out_neighbor3;
assign TRIG0[35] = pb_out_bop3;
assign TRIG0[36] = pb_out_eop3;
assign TRIG0[37] = pb_out_rdy3;
assign TRIG0[38] = pb_out_bypass3;
assign TRIG0[40] = pb_out_wr4;
assign TRIG0[41] = pb_out_req4;
assign TRIG0[42] = pb_out_ack4;
assign TRIG0[44:43] = pb_out_neighbor4;
assign TRIG0[45] = pb_out_bop4;
assign TRIG0[46] = pb_out_eop4;
assign TRIG0[47] = pb_out_rdy4;
assign TRIG0[48] = pb_out_bypass4;
assign TRIG0[50] = pb_out_wr5;
assign TRIG0[51] = pb_out_req5;
assign TRIG0[52] = pb_out_ack5;
assign TRIG0[54:53] = pb_out_neighbor5;
assign TRIG0[55] = pb_out_bop5;
assign TRIG0[56] = pb_out_eop5;
assign TRIG0[57] = pb_out_rdy5;
assign TRIG0[58] = pb_out_bypass5;
assign TRIG0[60] = out_wr3;
assign TRIG0[61] = out_req3;
assign TRIG0[62] = out_ack3;
assign TRIG0[63] = out_bop3;
assign TRIG0[64] = out_eop3;
assign TRIG0[65] = out_rdy3;
assign TRIG0[66] = out_bypass3;
assign TRIG0[67] = tx_in_progress0;
assign TRIG0[68] = tx_in_progress1;
assign TRIG0[69] = tx_in_progress2;
assign TRIG0[70] = tx_in_progress3;
assign TRIG0[73:71] = curr_buff3;
assign TRIG0[76:74] = curr_buff0;
assign TRIG0[79:77] = curr_buff2;
assign TRIG0[82:80] = curr_buff1;
assign TRIG0[92:90] = os_state0;
assign TRIG0[95:93] = os_state1;
assign TRIG0[98:96] = os_state2;
assign TRIG0[101:99] = os_state3;
assign TRIG0[173:110] = out_data3;
endmodule
|
module bsg_mem_1r1w_one_hot #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter safe_els_lp=`BSG_MAX(els_p,1)
)
(input w_clk_i
// Currently unused
, input w_reset_i
// one or zero-hot
, input [safe_els_lp-1:0] w_v_i
, input [width_p-1:0] w_data_i
// one or zero-hot
, input [safe_els_lp-1:0] r_v_i
, output logic [width_p-1:0] r_data_o
);
logic [safe_els_lp-1:0][width_p-1:0] data_r;
wire unused0 = w_reset_i;
for (genvar i = 0; i < els_p; i++)
begin : mem_array
bsg_dff_en
#(.width_p(width_p))
mem_reg
(.clk_i(w_clk_i)
,.en_i(w_v_i[i])
,.data_i(w_data_i)
,.data_o(data_r[i])
);
end
bsg_mux_one_hot
#(.width_p(width_p)
,.els_p(safe_els_lp)
)
one_hot_sel
(.data_i(data_r)
,.sel_one_hot_i(r_v_i)
,.data_o(r_data_o)
);
//synopsys translate_off
initial
begin
if (width_p*els_p >= 64)
$display("## %L: instantiating width_p=%d, els_p=%d (%m)"
,width_p,els_p);
end
always_ff @(negedge w_clk_i)
begin
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || $countones(w_v_i) <= 1)
else $error("Invalid write address %b to %m is not onehot (w_reset_i=%b)\n", w_v_i, w_reset_i);
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || $countones(r_v_i) <= 1)
else $error("Invalid read address %b to %m is not onehot (w_reset_i=%b)\n", r_v_i, w_reset_i);
end
//synopsys translate_on
endmodule
|
module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clk = 0;
#5 clk = 1;
// Period = 10 ns
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
ip = 2'd0;
rst = 1'd0;
// @t=9,
#9
ip = 2'd1;
rst = 1'd0;
// @t=19,
#10
ip = 2'd0;
rst = 1'd0;
// @t=29,
#10
ip = 2'd2;
rst = 1'd0;
// @t=39,
#10
ip = 2'd1;
rst = 1'd0;
// @t=49,
#10
ip = 2'd3;
rst = 1'd0;
// @t=59,
#10
ip = 2'd0;
rst = 1'd0;
// @t=69,
#10
ip = 2'd1;
rst = 1'd0;
// @t=79,
#10
ip = 2'd0;
rst = 1'd0;
// @t=89,
#10
ip = 2'd1;
rst = 1'd0;
// @t=99,
#10
ip = 2'd0;
rst = 1'd0;
// @t=109,
#10
ip = 2'd3;
rst = 1'd0;
// @t=119,
#10
ip = 2'd0;
rst = 1'd0;
// @t=129,
#10
ip = 2'd1;
rst = 1'd0;
// @t=139,
#10
ip = 2'd0;
rst = 1'd0;
// @t=149,
#10
ip = 2'd1;
rst = 1'd0;
// @t=159,
#10
ip = 2'd2;
rst = 1'd0;
// @t=169,
#10
ip = 2'd1;
rst = 1'd0;
// @t=179,
#10
ip = 2'd0;
rst = 1'd0;
// @t=189,
#10
ip = 2'd2;
rst = 1'd0;
// @t=199,
#10
ip = 2'd0;
rst = 1'd0;
// @t=209,
#10
ip = 2'd3;
rst = 1'd0;
// @t=219,
#10
ip = 2'd3;
rst = 1'd0;
// @t=229,
#10
ip = 2'd1;
rst = 1'd0;
// @t=239,
#10
ip = 2'd2;
rst = 1'd0;
// @t=249,
#10
ip = 2'd1;
rst = 1'd0;
// @t=259,
#10
ip = 2'd0;
rst = 1'd0;
// @t=269,
#10
ip = 2'd1;
rst = 1'd0;
// @t=279,
#10
ip = 2'd2;
rst = 1'd1;
// @t=289,
#10
ip = 2'd1;
rst = 1'd0;
// @t=299,
#10
ip = 2'd0;
rst = 1'd0;
// @t=309,
#10
ip = 2'd2;
rst = 1'd0;
// @t=319,
#10
ip = 2'd1;
rst = 1'd0;
// @t=329,
#10
ip = 2'd0;
rst = 1'd0;
// @t=339,
#10
ip = 2'd2;
rst = 1'd0;
// @t=349,
#10
ip = 2'd0;
rst = 1'd0;
// @t=359,
#10
ip = 2'd3;
rst = 1'd0;
// @t=369,
#10
ip = 2'd1;
rst = 1'd0;
// @t=379,
#10
ip = 2'd2;
rst = 1'd0;
// @t=389,
#10
ip = 2'd1;
rst = 1'd0;
// @t=399,
#10
ip = 2'd0;
rst = 1'd0;
// @t=409,
#10
ip = 2'd1;
rst = 1'd0;
// @t=419,
#10
ip = 2'd2;
rst = 1'd0;
// @t=429,
#10
ip = 2'd1;
rst = 1'd0;
// @t=439,
#10
ip = 2'd3;
rst = 1'd0;
// @t=449,
#10
ip = 2'd1;
rst = 1'd0;
// @t=459,
#10
ip = 2'd0;
rst = 1'd0;
// @t=469,
#10
ip = 2'd2;
rst = 1'd0;
// @t=479,
#10
ip = 2'd0;
rst = 1'd0;
// @t=489,
#10
ip = 2'd0;
rst = 1'd0;
// @t=499,
#10
ip = 2'd0;
rst = 1'd0;
// @t=509,
#10
ip = 2'd0;
rst = 1'd0;
// @t=519,
#10
ip = 2'd2;
rst = 1'd0;
// @t=529,
#10
ip = 2'd1;
rst = 1'd0;
// @t=539,
#10
ip = 2'd0;
rst = 1'd0;
// @t=549,
#10
ip = 2'd1;
rst = 1'd0;
// @t=559,
#10
ip = 2'd3;
rst = 1'd0;
// @t=569,
#10
ip = 2'd1;
rst = 1'd0;
// @t=579,
#10
ip = 2'd1;
rst = 1'd0;
// @t=589,
#10
ip = 2'd0;
rst = 1'd0;
// @t=599,
#10
ip = 2'd1;
rst = 1'd0;
// @t=609,
#10
ip = 2'd0;
rst = 1'd0;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
module spw_light_autostart (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
module reg_16bit(
clk,
Load,
not_reset,
D,
Q
);
input wire clk;
input wire not_reset;
input wire Load;
input wire [15:0] D;
output wire [15:0] Q;
reg [15:0] Q_ALTERA_SYNTHESIZED;
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[15] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[15] <= D[15];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[14] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[14] <= D[14];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[5] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[5] <= D[5];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[4] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[4] <= D[4];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[3] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[3] <= D[3];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[2] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[2] <= D[2];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[1] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[1] <= D[1];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[0] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[0] <= D[0];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[13] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[13] <= D[13];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[12] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[12] <= D[12];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[11] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[11] <= D[11];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[10] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[10] <= D[10];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[9] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[9] <= D[9];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[8] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[8] <= D[8];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[7] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[7] <= D[7];
end
end
always@(posedge clk or negedge not_reset)
begin
if (!not_reset)
begin
Q_ALTERA_SYNTHESIZED[6] <= 0;
end
else
if (Load)
begin
Q_ALTERA_SYNTHESIZED[6] <= D[6];
end
end
assign Q = Q_ALTERA_SYNTHESIZED;
endmodule
|
module sky130_fd_sc_lp__inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule
|
module
output reg rw_d;
output reg dm_access_size;
always @(ALUOp, rsData, rtData)
begin : EXECUTE
if (enable_execute == 1) begin
branch_taken = 0;
if(insn[31:26] == RTYPE) begin
case (ALUOp)
ADD: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData + rtData;
rw_d = 0;
dm_we = 0;
end
ADDU: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData + rtData;
rw_d = 0;
dm_we = 0;
end
SUB: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData - rtData;
rw_d = 0;
dm_we = 0;
end
SUBU: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData - rtData;
rw_d = 0;
dm_we = 0;
end
MUL_FUNC: begin
temp = rsData * rtData;
dataOut = temp[31:0];
end
DIV: begin
temp = rsData / rtData;
hi = temp[63:32]; // remainder
lo = temp[31:0]; // quotient
end
DIVU: begin
temp = rsData / rtData;
hi = temp[63:32]; // remainder
lo = temp[31:0]; // quotient
end
MFHI: begin
dataOut = hi;
end
MFLO: begin
dataOut = lo;
end
SLT: begin
if (rsData < rtData) begin
dataOut = 32'h00000001;
end else begin
dataOut = 32'h00000000;
end
end
SLTU: begin
if (rsData < rtData) begin
dataOut = 32'h00000001;
end else begin
dataOut = 32'h00000000;
end
end
SLL: begin
dataOut = rtData << saData;
end
SLLV: begin
dataOut = rtData << rsData;
end
SRL: begin
dataOut = rtData >> saData;
end
SRLV: begin
dataOut = rtData >> rsData;
end
SRA: begin
dataOut = rtData >>> saData;
end
SRAV: begin
dataOut = rtData >>> rsData;
end
AND: begin
dataOut = rsData & rtData;
end
OR: begin
dataOut = rsData | rtData;
end
XOR: begin
dataOut = rsData ^ rtData;
end
NOR: begin
dataOut = ~(rsData | rtData);
end
JR: begin
dataOut = rsData;
branch_taken = 1;
end
JALR: begin
dataOut = (pc + 8);
//pc_out_execute = rsData
branch_taken = 1;
end
endcase
end else if (insn[31:26] != 6'b000000 && insn[31:27] != 5'b00001 && insn[31:26] != 6'b000001) begin
case (ALUOp)
ADDI: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData + immSXData[15:0];
rw_d = 0;
dm_we = 0;
end
ADDIU: begin
//writeback dataOut to regfile, bypass DMem
//dataOut is data_in_alu in writeback
dataOut = rsData + immSXData[15:0];
rw_d = 0;
dm_we = 0;
end
SLTI: begin
if (rsData < immSXData[15:0]) begin
dataOut = 32'h00000001;
end else begin
dataOut = 32'h00000000;
end
end
SLTIU: begin
if (rsData < immSXData[15:0]) begin
dataOut = 32'h00000001;
end else begin
dataOut = 32'h00000000;
end
end
ORI: begin
dataOut = rsData | immSXData[15:0];
end
XORI: begin
dataOut = rsData ^ immSXData[15:0];
end
LW: begin
// TODO: MEMTYPE
dm_we = 0; //read from memory
dm_access_size = 2'b0_0; // 1 WORD
rw_d = 1;
// rt <= MEM[rs + SX(imm,32)]
// dataOut MEM ADDR of data to load
// dataOut goes to input a of DMEM
// writeback mem contents at MEM[dataOut] to regfile
dataOut = rsData + immSXData[15:0];
end
SW: begin
// TODO: MEMTYPE
dm_we = 1;
dm_access_size = 2'b0_0; // 1 WORD
rw_d = 0;
// MEM[rs + SX(imm)] <= rt
// dataOut has MEM ADDR to store rt
// get rt straight from output of decode
// rt is input d of data memory
// dataOut is input a of data memory
// no writeback, disable regfile we
// store value of rt in MEM[dataOut]
dataOut = rsData + immSXData[15:0];
end
LB: begin
// TODO: MEMTYPE (modify access size)
// First get LW to work, then do this
dataOut = rsData + immSXData[15:0];
end
LUI: begin
// TODO: MEMTYPE
//dataOut = immSXData[15:0] << 16;
dataOut = {immSXData[15:0], 16'd0};
end
SB: begin
// TODO: MEMTYPE (modify access size)
dataOut = rsData + immSXData[15:0];
end
LBU: begin
// TODO: MEMTYPE
dataOut = rsData + immSXData[15:0];
end
BEQ: begin
if (rsData == rtData) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
BNE: begin
if (rsData != rtData) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
BGTZ: begin
if (rsData > 0) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
BLEZ: begin
if (rsData <= 0) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
endcase
end else if (insn[31:26] == 6'b000001) begin
// REGIMM
case(ALUOp)
BLTZ: begin
if (rsData < 0) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
BGEZ: begin
if (rsData >= 0) begin
dataOut = pc + (immSXData[15:0] << 2);
branch_taken = 1;
end else begin
branch_taken = 0;
end
end
endcase
end else if (insn[31:27] == 5'b00001) begin
// J-Type
case (ALUOp)
J: begin
//
dataOut[31:28] = pc[31:28];
dataOut[27:0] = immSXData[25:0] << 2;
branch_taken = 1;
end
JAL: begin
dataOut = pc + 8;
branch_taken = 1;
end
endcase
end else if (insn == NOP) begin
dataOut = dataOut;
end
end
end
endmodule
|
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 RESET = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER = 1'b1;
#220 RESET = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER = 1'b0;
#360 RESET = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 RESET = 1'b1;
#520 NOTIFIER = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 RESET = 1'bx;
#660 NOTIFIER = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__udp_dff$NR_pp$PKG$sN dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK_N(CLK_N));
endmodule
|
module dram_addr_gen(/*AUTOARG*/
// Outputs
addr_err, rank_adr, stack_adr, bank_adr, ras_adr, cas_adr, addr_parity,
// Inputs
addr_in, config_reg, two_channel_mode, rank1_present, eight_bank_mode
);
input [39:4] addr_in;
input [8:0] config_reg;
input rank1_present;
input eight_bank_mode;
input two_channel_mode;
output addr_parity;
output addr_err;
output rank_adr;
output stack_adr;
output [2:0] bank_adr;
output [14:0] ras_adr;
output [13:0] cas_adr;
//////////////////////////////////////////////////////////////////
// WIRE
//////////////////////////////////////////////////////////////////
wire [14:0] ras_adr_cas12;
wire [14:0] ras_adr_cas11;
//////////////////////////////////////////////////////////////////
// Mux the RAS address
//////////////////////////////////////////////////////////////////
assign ras_adr_cas12[14:0] = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ?
{1'h0,addr_in[33:20]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[32:20]} : addr_in[34:20]) :
(config_reg[8:5] == 4'he) ?
{1'h0,addr_in[32:19]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[31:19]} : addr_in[33:19]) :
eight_bank_mode ? (
(config_reg[8:5] == 4'he) ?
{1'h0,addr_in[34:21]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[33:21]} : addr_in[35:21]) :
((config_reg[8:5] == 4'he) ?
{1'h0,addr_in[33:20]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[32:20]} : addr_in[34:20]);
assign ras_adr_cas11[14:0] = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ?
{1'h0,addr_in[32:19]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[31:19]} : addr_in[33:19]) :
(config_reg[8:5] == 4'he) ?
{1'h0,addr_in[31:18]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[30:18]} : addr_in[32:18]) :
eight_bank_mode ? (
(config_reg[8:5] == 4'he) ?
{1'h0,addr_in[33:20]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[32:20]} : addr_in[34:20]) :
((config_reg[8:5] == 4'he) ?
{1'h0,addr_in[32:19]} : (config_reg[8:5] == 4'hd) ?
{2'h0,addr_in[31:19]} : addr_in[33:19]);
assign ras_adr[14:0] = (config_reg[4:1] == 4'hc) ? ras_adr_cas12 : ras_adr_cas11;
wire stack_adr_present = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34])) :
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[32] : addr_in[31]) :
((config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33])) :
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
((config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35])) :
((config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]));
wire stack_adr = config_reg[0] ? stack_adr_present : 1'b0;
wire rank_adr_present = two_channel_mode ? (
eight_bank_mode ? (
config_reg[0] ? (
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
((config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35]) ) :
( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) )) :
config_reg[0] ? (
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) ) :
( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[32] : addr_in[31]) :
((config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) )) :
eight_bank_mode ? (
config_reg[0] ? (
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
((config_reg[4:1] == 4'hc) ? addr_in[37] : addr_in[36]) ) :
( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
((config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35]) )) :
(config_reg[0] ? (
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
((config_reg[4:1] == 4'hc) ? addr_in[36] : addr_in[35]) ) :
( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? addr_in[34] : addr_in[33]) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? addr_in[33] : addr_in[32]) :
((config_reg[4:1] == 4'hc) ? addr_in[35] : addr_in[34]) ));
wire rank_adr = rank1_present ? rank_adr_present : 1'b0;
wire [8:0] upper_addr_no_sd_no_rank = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]})) :
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {1'h0,addr_in[39:32]} : addr_in[39:31]) :
((config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]})) :
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
((config_reg[4:1] == 4'hc) ? {5'h0,addr_in[39:36]} : {4'h0,addr_in[39:35]})) :
((config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:34]} : {2'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:33]} : {1'h0,addr_in[39:32]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:35]} : {3'h0,addr_in[39:34]}));
wire [7:0] upper_addr_sd_or_rank = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]})) :
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {1'h0,addr_in[39:33]} : addr_in[39:32]) :
((config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]})) :
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
((config_reg[4:1] == 4'hc) ? {5'h0,addr_in[39:37]} : {4'h0,addr_in[39:36]})) :
((config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:35]} : {2'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:34]} : {1'h0,addr_in[39:33]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:36]} : {3'h0,addr_in[39:35]}));
wire [6:0] upper_addr_sd_and_rank = two_channel_mode ? (
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:36]} : {2'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:35]} : {1'h0,addr_in[39:34]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:37]} : {3'h0,addr_in[39:36]})) :
(config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:35]} : {1'h0,addr_in[39:34]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {1'h0,addr_in[39:34]} : addr_in[39:33]) :
((config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:36]} : {2'h0,addr_in[39:35]})) :
eight_bank_mode ? ( (config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:37]} : {3'h0,addr_in[39:36]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:36]} : {2'h0,addr_in[39:35]}) :
((config_reg[4:1] == 4'hc) ? {5'h0,addr_in[39:38]} : {4'h0,addr_in[39:37]})) :
((config_reg[8:5] == 4'he) ? (
(config_reg[4:1] == 4'hc) ? {3'h0,addr_in[39:36]} : {2'h0,addr_in[39:35]}) :
(config_reg[8:5] == 4'hd) ? (
(config_reg[4:1] == 4'hc) ? {2'h0,addr_in[39:35]} : {1'h0,addr_in[39:34]}) :
((config_reg[4:1] == 4'hc) ? {4'h0,addr_in[39:37]} : {3'h0,addr_in[39:36]}));
wire [8:0] upper_addr =
(rank1_present & config_reg[0]) ? {upper_addr_sd_and_rank[6:0],2'b0} :
(rank1_present | config_reg[0]) ? {upper_addr_sd_or_rank[7:0],1'b0} :
upper_addr_no_sd_no_rank[8:0];
wire addr_err = |upper_addr[8:0];
//////////////////////////////////////////////////////////////////
// Mux the CAS address
//////////////////////////////////////////////////////////////////
assign cas_adr[13:0] = two_channel_mode ? (
eight_bank_mode ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[19:18],1'b1,addr_in[17:10],addr_in[5:4]} :
{2'h0,addr_in[18],1'b1,addr_in[17:10],addr_in[5:4]}) :
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[18:17],1'b1,addr_in[16:9],addr_in[5:4]} :
{2'h0,addr_in[17],1'b1,addr_in[16:9],addr_in[5:4]}) :
eight_bank_mode ? (
(config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[20:19],1'b1,addr_in[18:11],addr_in[5:4]} :
{2'h0,addr_in[19],1'b1,addr_in[18:11],addr_in[5:4]}) :
((config_reg[4:1] == 4'hc) ?
{1'h0,addr_in[19:18],1'b1,addr_in[17:10],addr_in[5:4]} :
{2'h0,addr_in[18],1'b1,addr_in[17:10],addr_in[5:4]});
assign bank_adr[2:0] = two_channel_mode ? (
eight_bank_mode ? addr_in[9:7] ^ addr_in[20:18] ^ addr_in[30:28] :
config_reg[0] ? { stack_adr, addr_in[8:7] ^ addr_in[19:18] ^ addr_in[29:28] } :
rank1_present ? {rank_adr, addr_in[8:7] ^ addr_in[19:18] ^ addr_in[29:28] } :
{1'b0, addr_in[8:7] ^ addr_in[19:18] ^ addr_in[29:28] }) :
(eight_bank_mode ? addr_in[10:8] ^ addr_in[20:18] ^ addr_in[30:28] :
config_reg[0] ? { stack_adr, addr_in[9:8] ^ addr_in[19:18] ^ addr_in[29:28]} :
rank1_present ? {rank_adr, addr_in[9:8] ^ addr_in[19:18] ^ addr_in[29:28] } :
{1'b0, addr_in[9:8] ^ addr_in[19:18] ^ addr_in[29:28] });
wire addr_parity = two_channel_mode ? ^(addr_in[39:7]) : ^(addr_in[39:8]);
endmodule
|
module receives an Ethernet frame with header fields in parallel and
payload on an AXI stream interface, decodes and strips the IP header fields,
then produces the header fields in parallel along with the IP payload in a
separate AXI stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_eth_hdr;
reg store_hdr_word_0;
reg store_hdr_word_1;
reg store_hdr_word_2;
reg store_last_word;
reg flush_save;
reg transfer_in_save;
reg [5:0] hdr_ptr_reg = 6'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [16:0] hdr_sum_high_reg = 17'd0;
reg [16:0] hdr_sum_low_reg = 17'd0;
reg [19:0] hdr_sum_temp;
reg [19:0] hdr_sum_reg = 20'd0, hdr_sum_next;
reg check_hdr_reg = 1'b0, check_hdr_next;
reg [63:0] last_word_data_reg = 64'd0;
reg [7:0] last_word_keep_reg = 8'd0;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
reg error_invalid_header_reg = 1'b0, error_invalid_header_next;
reg error_invalid_checksum_reg = 1'b0, error_invalid_checksum_next;
reg [63:0] save_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] save_eth_payload_axis_tkeep_reg = 8'd0;
reg save_eth_payload_axis_tlast_reg = 1'b0;
reg save_eth_payload_axis_tuser_reg = 1'b0;
reg [63:0] shift_eth_payload_axis_tdata;
reg [7:0] shift_eth_payload_axis_tkeep;
reg shift_eth_payload_axis_tvalid;
reg shift_eth_payload_axis_tlast;
reg shift_eth_payload_axis_tuser;
reg shift_eth_payload_s_tready;
reg shift_eth_payload_extra_cycle_reg = 1'b0;
// internal datapath
reg [63:0] m_ip_payload_axis_tdata_int;
reg [7:0] m_ip_payload_axis_tkeep_int;
reg m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
assign error_invalid_header = error_invalid_header_reg;
assign error_invalid_checksum = error_invalid_checksum_reg;
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
shift_eth_payload_axis_tdata[31:0] = save_eth_payload_axis_tdata_reg[63:32];
shift_eth_payload_axis_tkeep[3:0] = save_eth_payload_axis_tkeep_reg[7:4];
if (shift_eth_payload_extra_cycle_reg) begin
shift_eth_payload_axis_tdata[63:32] = 32'd0;
shift_eth_payload_axis_tkeep[7:4] = 4'd0;
shift_eth_payload_axis_tvalid = 1'b1;
shift_eth_payload_axis_tlast = save_eth_payload_axis_tlast_reg;
shift_eth_payload_axis_tuser = save_eth_payload_axis_tuser_reg;
shift_eth_payload_s_tready = flush_save;
end else begin
shift_eth_payload_axis_tdata[63:32] = s_eth_payload_axis_tdata[31:0];
shift_eth_payload_axis_tkeep[7:4] = s_eth_payload_axis_tkeep[3:0];
shift_eth_payload_axis_tvalid = s_eth_payload_axis_tvalid;
shift_eth_payload_axis_tlast = (s_eth_payload_axis_tlast && (s_eth_payload_axis_tkeep[7:4] == 0));
shift_eth_payload_axis_tuser = (s_eth_payload_axis_tuser && (s_eth_payload_axis_tkeep[7:4] == 0));
shift_eth_payload_s_tready = !(s_eth_payload_axis_tlast && s_eth_payload_axis_tvalid && transfer_in_save);
end
end
always @* begin
state_next = STATE_IDLE;
flush_save = 1'b0;
transfer_in_save = 1'b0;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
store_eth_hdr = 1'b0;
store_hdr_word_0 = 1'b0;
store_hdr_word_1 = 1'b0;
store_hdr_word_2 = 1'b0;
store_last_word = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
hdr_sum_temp = 32'd0;
hdr_sum_next = hdr_sum_reg;
check_hdr_next = check_hdr_reg;
m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready;
error_header_early_termination_next = 1'b0;
error_payload_early_termination_next = 1'b0;
error_invalid_header_next = 1'b0;
error_invalid_checksum_next = 1'b0;
m_ip_payload_axis_tdata_int = 64'd0;
m_ip_payload_axis_tkeep_int = 8'd0;
m_ip_payload_axis_tvalid_int = 1'b0;
m_ip_payload_axis_tlast_int = 1'b0;
m_ip_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
hdr_ptr_next = 6'd0;
hdr_sum_next = 32'd0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b1;
store_eth_hdr = 1'b1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
word_count_next = m_ip_length_reg - 5*4;
if (s_eth_payload_axis_tvalid) begin
// word transfer in - store it
hdr_ptr_next = hdr_ptr_reg + 6'd8;
transfer_in_save = 1'b1;
state_next = STATE_READ_HEADER;
case (hdr_ptr_reg)
6'h00: begin
store_hdr_word_0 = 1'b1;
end
6'h08: begin
store_hdr_word_1 = 1'b1;
hdr_sum_next = hdr_sum_high_reg + hdr_sum_low_reg;
end
6'h10: begin
store_hdr_word_2 = 1'b1;
hdr_sum_next = hdr_sum_reg + hdr_sum_high_reg + hdr_sum_low_reg;
// check header checksum on next cycle for improved timing
check_hdr_next = 1'b1;
if (m_ip_version_reg != 4'd4 || m_ip_ihl_reg != 4'd5) begin
error_invalid_header_next = 1'b1;
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
state_next = STATE_WAIT_LAST;
end else begin
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
state_next = STATE_READ_PAYLOAD;
end
end
endcase
if (shift_eth_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
error_invalid_header_next = 1'b0;
error_invalid_checksum_next = 1'b0;
m_ip_hdr_valid_next = 1'b0;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD: begin
// read payload
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
m_ip_payload_axis_tdata_int = shift_eth_payload_axis_tdata;
m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep;
m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast;
m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser;
store_last_word = 1'b1;
if (m_ip_payload_axis_tready_int_reg && shift_eth_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd8;
transfer_in_save = 1'b1;
m_ip_payload_axis_tvalid_int = 1'b1;
if (word_count_reg <= 8) begin
// have entire payload
m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep & count2keep(word_count_reg);
if (shift_eth_payload_axis_tlast) begin
if (keep2count(shift_eth_payload_axis_tkeep) < word_count_reg[4:0]) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
end
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
m_ip_payload_axis_tvalid_int = 1'b0;
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
if (shift_eth_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD;
end
if (check_hdr_reg) begin
check_hdr_next = 1'b0;
hdr_sum_temp = hdr_sum_reg[15:0] + hdr_sum_reg[19:16] + hdr_sum_low_reg;
if (hdr_sum_temp != 19'h0ffff && hdr_sum_temp != 19'h1fffe) begin
// bad checksum
error_invalid_checksum_next = 1'b1;
m_ip_payload_axis_tvalid_int = 1'b0;
if (shift_eth_payload_axis_tlast && shift_eth_payload_axis_tvalid) begin
// only one payload cycle; return to idle now
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
// drop payload
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
state_next = STATE_WAIT_LAST;
end
end else begin
// good checksum; transfer header
m_ip_hdr_valid_next = 1'b1;
end
end
end
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
m_ip_payload_axis_tdata_int = last_word_data_reg;
m_ip_payload_axis_tkeep_int = last_word_keep_reg;
m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast;
m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser;
if (m_ip_payload_axis_tready_int_reg && shift_eth_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
m_ip_payload_axis_tvalid_int = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// read and discard until end of frame
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
if (shift_eth_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_ip_hdr_valid_reg <= 1'b0;
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_extra_cycle_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
error_invalid_header_reg <= 1'b0;
error_invalid_checksum_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_payload_early_termination_reg <= error_payload_early_termination_next;
error_invalid_header_reg <= error_invalid_header_next;
error_invalid_checksum_reg <= error_invalid_checksum_next;
busy_reg <= state_next != STATE_IDLE;
// datapath
if (flush_save) begin
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_eth_payload_axis_tlast_reg <= s_eth_payload_axis_tlast;
shift_eth_payload_extra_cycle_reg <= s_eth_payload_axis_tlast && (s_eth_payload_axis_tkeep[7:4] != 0);
end
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
hdr_sum_reg <= hdr_sum_next;
check_hdr_reg <= check_hdr_next;
if (s_eth_payload_axis_tvalid) begin
hdr_sum_low_reg <= s_eth_payload_axis_tdata[15:0] + s_eth_payload_axis_tdata[31:16];
hdr_sum_high_reg <= s_eth_payload_axis_tdata[47:32] + s_eth_payload_axis_tdata[63:48];
end
// datapath
if (store_eth_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
end
if (store_last_word) begin
last_word_data_reg <= m_ip_payload_axis_tdata_int;
last_word_keep_reg <= m_ip_payload_axis_tkeep_int;
end
if (store_hdr_word_0) begin
{m_ip_version_reg, m_ip_ihl_reg} <= s_eth_payload_axis_tdata[ 7: 0];
{m_ip_dscp_reg, m_ip_ecn_reg} <= s_eth_payload_axis_tdata[15: 8];
m_ip_length_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_length_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
m_ip_identification_reg[15: 8] <= s_eth_payload_axis_tdata[39:32];
m_ip_identification_reg[ 7: 0] <= s_eth_payload_axis_tdata[47:40];
{m_ip_flags_reg, m_ip_fragment_offset_reg[12:8]} <= s_eth_payload_axis_tdata[55:48];
m_ip_fragment_offset_reg[ 7:0] <= s_eth_payload_axis_tdata[63:56];
end
if (store_hdr_word_1) begin
m_ip_ttl_reg <= s_eth_payload_axis_tdata[ 7: 0];
m_ip_protocol_reg <= s_eth_payload_axis_tdata[15: 8];
m_ip_header_checksum_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_header_checksum_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
m_ip_source_ip_reg[31:24] <= s_eth_payload_axis_tdata[39:32];
m_ip_source_ip_reg[23:16] <= s_eth_payload_axis_tdata[47:40];
m_ip_source_ip_reg[15: 8] <= s_eth_payload_axis_tdata[55:48];
m_ip_source_ip_reg[ 7: 0] <= s_eth_payload_axis_tdata[63:56];
end
if (store_hdr_word_2) begin
m_ip_dest_ip_reg[31:24] <= s_eth_payload_axis_tdata[ 7: 0];
m_ip_dest_ip_reg[23:16] <= s_eth_payload_axis_tdata[15: 8];
m_ip_dest_ip_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_dest_ip_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
end
if (transfer_in_save) begin
save_eth_payload_axis_tdata_reg <= s_eth_payload_axis_tdata;
save_eth_payload_axis_tkeep_reg <= s_eth_payload_axis_tkeep;
save_eth_payload_axis_tuser_reg <= s_eth_payload_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_ip_payload_axis_tkeep_reg = 8'd0;
reg m_ip_payload_axis_tvalid_reg = 1'b0, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg m_ip_payload_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_ip_payload_axis_tkeep_reg = 8'd0;
reg temp_m_ip_payload_axis_tvalid_reg = 1'b0, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg temp_m_ip_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_ip_payload_int_to_output;
reg store_ip_payload_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = m_ip_payload_axis_tdata_reg;
assign m_ip_payload_axis_tkeep = m_ip_payload_axis_tkeep_reg;
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_ip_payload_int_to_output = 1'b0;
store_ip_payload_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if (m_ip_payload_axis_tready || !m_ip_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_ip_payload_axis_tvalid_reg <= 1'b0;
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
end
// datapath
if (store_ip_payload_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tkeep_reg <= temp_m_ip_payload_axis_tkeep_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_ip_payload_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
end
endmodule
|
module counter48 #(
parameter DATASIZE = 16 // width of the counter, must be <=48 bits!
) (
input wire clk,
input wire res_n,
input wire increment,
input wire [DATASIZE-1:0] load,
input wire load_enable,
output wire [DATASIZE-1:0] value
);
reg [DATASIZE-1:0] value_reg;
reg load_enable_reg;
assign value = value_reg;
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if (!res_n)
begin
value_reg <= {DATASIZE{1'b0}};
load_enable_reg <= 1'b0;
end
else
begin
load_enable_reg <= load_enable;
case ({load_enable_reg,increment})
2'b00:
value_reg <= value_reg;
2'b01:
value_reg <= (value_reg + 1'b1);
2'b10:
value_reg <= {DATASIZE{1'b0}};
2'b11:
value_reg <= {DATASIZE{1'b0}} + 1'b1;
endcase
end
end
endmodule
|
module HLS_accel_fpext_32ns_64_1
#(parameter
ID = 6,
NUM_STAGE = 1,
din0_WIDTH = 32,
dout_WIDTH = 64
)(
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
//------------------------Instantiation------------------
HLS_accel_ap_fpext_0_no_dsp_32 HLS_accel_ap_fpext_0_no_dsp_32_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign dout = r_tdata;
endmodule
|
module sky130_fd_sc_hs__o31ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__o31ai_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
|
module sky130_fd_sc_lp__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
|
module were
// read from.
// 1 if read from X.
// 0 if read from Y.
wire readbuf_switch_z;
// Delayed content of readbuf_swith_z;
reg readbuf_switch_z_last;
// Delayed content of out1_addr_z_old since we need to use
// it after it may have changed.
reg [NLOG2-1:0] out1_addr_z_old;
// The address to write the currently received BF output.
wire [NLOG2-1:0] out_addr_z;
assign out_addr_z = (z_nd)?out0_addr_z:out1_addr_z_old;
// A delayed z_nd. Tells us when to expect ZB.
reg z_nd_last;
// For delaying variables. It takes 2 steps to write the output data
// to the buffer at which point we decide whether to write the data
// to bufferout. These registers are needed for that decision.
reg finished_z_old[1:0];
reg last_stage_z_old[0:0];
reg readbuf_switch_z_old[1:0];
initial
begin
bufferout_full_A <= 1'b0;
z_nd_last <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
bufferout_full_A <= 1'b0;
z_nd_last <= 1'b0;
end
else
begin
// Put updated reset here so we drive it from same process.
if ((fsm_state == FSM_ST_CALC) & (&(out1_addr)))
begin
if (readbuf_switch)
updatedX <= {N{1'b0}};
else
updatedY <= {N{1'b0}};
end
// Set all the delays.
readbuf_switch_z_last <= readbuf_switch_z;
finished_z_old[0] <= finished_z;
finished_z_old[1] <= finished_z_old[0];
last_stage_z_old[0] <= last_stage_z;
readbuf_switch_z_old[0] <= readbuf_switch_z;
readbuf_switch_z_old[1] <= readbuf_switch_z_old[0];
out1_addr_z_old <= out1_addr_z;
z_nd_last <= z_nd;
if (finished_z_old[1])
// We have filled the output buffer
bufferout_full_A <= ~bufferout_full_A;
// Write received data to the buffers and set updated flag.
if (z_nd | z_nd_last)
begin
if ((last_stage_z & z_nd)|(last_stage_z_old[0] & ~z_nd))
begin
bufferout[out_addr_z] <= z;
end
else
begin
if ((readbuf_switch_z & z_nd)|(readbuf_switch_z_old[0] & ~z_nd))
begin
bufferY[out_addr_z] <= z;
updatedY[out_addr_z] <= 1'b1;
end
else
begin
bufferX[out_addr_z] <= z;
updatedX[out_addr_z] <= 1'b1;
end
end
end
end
end
/* Instantiate twiddle factor unit. */
twiddlefactors
twiddlefactors_0 (
.clk (clk),
.addr (tf_addr),
.addr_nd (tf_addr_nd),
.tf_out (tf)
);
/* Instantiate the generic butterfly unit. */
butterfly #(
.M_WDTH (3 + 2*NLOG2),
.X_WDTH (X_WDTH)
)
butterfly_0 (
.clk (clk),
.rst_n (rst_n),
.m_in ({readbuf_switch_old, out0_addr, out1_addr, finished, last_stage}),
.w (tf),
.xa (in0),
.xb (in1),
.x_nd (x_nd),
.m_out ({readbuf_switch_z, out0_addr_z, out1_addr_z, finished_z, last_stage_z}),
.y (z),
.y_nd (z_nd)
);
endmodule
|
module WcaPortWrite(
input wire reset,
input wire port_enable, //Enables/Disable port writing.
input wire wr_clk, // Clock input to fifo.
input wire wr_en, //Allows input if specified.
input wire [31:0] wr_in, // Clock data input.
output wire empty, // Active high indicates buffer is empty.
output wire full, // Active high indicates buffer is full.
output wire prog_empty, // Active high indicates buffer is almost empty at or below 160 samples.
output wire prog_full, // Active high indicates buffer is almost full at or above 352 samples.
//Port Controller interface.
inout [31:0] pifData, // 32 bit port interface data bus.
input wire [(NBITS_ADDR+2):0] portCtrl, // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
output wire [1:0] portCmd // Port Command ID
);
parameter ADDR_PORT = 0;
parameter NBITS_ADDR = 2;
parameter TEST_PATTERN = 0;
wire [31:0] dout;
wire isAddr = (ADDR_PORT == portCtrl[NBITS_ADDR+2:3]);
wire rd_en = isAddr & portCtrl[1];
//Request a read of data from the FIFO Slave interface.
assign portCmd = (isAddr) ? ((prog_full & port_enable) ? `PIFCMD_WRITE : `PIFCMD_IDLE) : 2'bz;
//Buffer the data.
FiFo512Core32W32R fifo512 (
.rst(reset), // input rst
.wr_clk(wr_clk), // input wr_clk
.rd_clk(portCtrl[0]), // input rd_clk
.din(wr_in), // input [31 : 0] din
.wr_en(wr_en & port_enable), // input wr_en
.rd_en(rd_en), // input rd_en
.dout(dout), // output [31 : 0] dout
.full(full), // output full
.empty(empty), // output empty
.prog_full(prog_full), // output prog_full threhold at 388 DWORDS
.prog_empty(prog_empty) // output prog_empty threshold at 256 DWORDS
);
generate if( TEST_PATTERN == 1)
begin
//Place data on the buss if reading.
assign pifData = ( rd_en ) ? ctr : 32'bz;
//Writes a sequence of interface out the Port, use for USB Troubleshooting.
reg [31:0] ctr;
always @(posedge portCtrl[0])
begin
if( reset)
ctr <= 32'h0;
else if( rd_en )
ctr <= ctr + 32'h1;
end
end
else
begin
//Place data on the buss if reading.
assign pifData = ( rd_en ) ? dout : 32'bz;
end
endgenerate
endmodule
|
module TOP
( input CLK32,
output [3:0] TMDS_out_P,
output [3:0] TMDS_out_N,
output [12:0] SDRAM_ADDR,
inout [15:0] SDRAM_DATA,
output SDRAM_BA0,
output SDRAM_BA1,
output SDRAM_UDQM,
output SDRAM_LDQM,
output SDRAM_CLK,
output SDRAM_CKE,
output SDRAM_CSn,
output SDRAM_RASn,
output SDRAM_CASn,
output SDRAM_WEn,
output SD_CLK,
output SD_CD_DAT3,
input SD_DAT0,
output SD_DAT1,
output SD_DAT2,
output SD_CMD,
output [7:0] LEDS
);
wire PixelClk;
wire PixelClk2;
wire PixelClk10;
wire SerDesStrobe;
wire [7:0] Red;
wire [7:0] Green;
wire [7:0] Blue;
wire HSync;
wire VSync;
wire VideoEnable;
wire [10:0] GetRow;
wire StartBuffer;
wire [8:0] BufferAddr;
wire [15:0] BufferData;
wire BufferWrite;
wire [23:0] ExtAddr;
wire [15:0] ExtDataWrite;
wire [1:0] ExtDataMask;
wire [15:0] ExtDataRead;
wire ExtOP;
wire ExtReq;
wire ExtReady;
wire [7:0] PalAddr;
wire [31:0] PalData;
wire PalWrite;
wire [5:0] XOffsetData;
wire [9:0] YOffsetData;
wire OffsetWrite;
wire [24:0] Address;
wire [31:0] DataWrite;
wire [31:0] DataRead;
wire [1:0] DataSize;
wire ReadWrite;
wire Request;
wire Ready;
CLOCK CLOCK(CLK32, PixelClk, PixelClk2, PixelClk10, SerDesStrobe);
DVI_OUT DVI_OUT(PixelClk, PixelClk2, PixelClk10, SerDesStrobe, Red, Green, Blue, HSync, VSync, VideoEnable, TMDS_out_P, TMDS_out_N);
VIDEOGEN VIDEOGEN(PixelClk, PixelClk2, Red, Green, Blue, HSync, VSync, VideoEnable,
GetRow, StartBuffer, BufferAddr, BufferData, BufferWrite,
PalAddr, PalData, PalWrite, XOffsetData, YOffsetData, OffsetWrite);
SDRAM SDRAM(.PixelClk2(PixelClk2), .SDRAMCK(SDRAM_CLK), .CMD({SDRAM_CKE,SDRAM_CSn,SDRAM_RASn,SDRAM_CASn,SDRAM_WEn}),
.DQM({SDRAM_UDQM,SDRAM_LDQM}), .BANK({SDRAM_BA1,SDRAM_BA0}), .ADDR(SDRAM_ADDR), .DATA(SDRAM_DATA),
.ExtAddr(ExtAddr), .ExtDataWrite(ExtDataWrite), .ExtDataMask(ExtDataMask), .ExtDataRead(ExtDataRead), .ExtOP(ExtOP),
.ExtReq(ExtReq), .ExtReady(ExtReady),
.GetRow(GetRow), .StartBuffer(StartBuffer), .BufferAddr(BufferAddr), .BufferData(BufferData), .BufferWrite(BufferWrite));
MemoryAdapter MA(PixelClk2, ExtAddr, ExtDataWrite, ExtDataMask, ExtDataRead, ExtOP, ExtReq, ExtReady,
Address, DataWrite, DataRead, DataSize, ReadWrite, Request, Ready);
SD SD(PixelClk2, SD_CLK, SD_CD_DAT3, SD_DAT0, SD_DAT1, SD_DAT2, SD_CMD, LEDS,
Address, DataWrite, DataRead, DataSize, ReadWrite, Request, Ready, PalAddr, PalData, PalWrite);
Test Test(PixelClk2, VSync, XOffsetData, YOffsetData, OffsetWrite);
endmodule
|
module microcode_context_store(
input iCLOCK,
input inRESET,
//Select
input [31:0] iSELECT,
//Output
output [31:0] oCODE_SIZE,
input [72:0] oCODE0,
input [72:0] oCODE1
);
wire [73:0] tmp0;
wire [73:0] tmp1;
assign tmp0 = func_microcode(iSELECT<<1);
assign tmp1 = func_microcode((iSELECT<<1) + 32'h1);
assign oCODE_SIZE = `MICROCODE_SIZE;
assign oCODE0 = tmp0[72:0];
assign oCODE1 = tmp1[72:0];
/*
//PC Reserved
movepc srr0, -1
//SPR Reserved
srspr ssr1
//R0, R1 Reserved
move ssr2 r0
move ssr3 r1
//Set SPR
srtisr r0
add r0, 128
srtidr r1
mull r1, 144
add r1, r0
srspw r1
//General Register Store
push ssr2
push ssr3
push r2
push r3
push r4
push r5
push r6
push r7
push r8
push r9
push r10
push r11
push r12
push r13
push r14
push r15
push r16
push r17
push r18
push r19
push r20
push r21
push r22
push r23
push r24
push r25
push r26
push r27
push r28
push r29
push r30
push r31
//Push PC
push srr0
//Push SPR
push srr1
//Push PDTR
srpdtr r0
push r0
*/
function [73:0] func_microcode;
input func_addr;
begin
case(func_addr)
32'd0 : //MOVEPC SSR0, -1
begin
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_PC,
/* Source1 */ 32'hFFFFFFFF,//-1
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SSR0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
32'd1 :
begin //SRSPR SSR1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_SPR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SSR1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_LDST_READ_SPR,
/* Execute Module */ `EXE_SELECT_SYS_LDST
};
end
32'd2 :
begin //MOVE SSR2, R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ `LOGICREG_R0,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SSR2,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_BUFFER1,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
32'd3 :
begin //MOVE SSR3, R1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ `LOGICREG_R1,
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SSR3,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LOGIC_BUFFER1,
/* Execute Module */ `EXE_SELECT_LOGIC
};
end
32'd4 :
begin //SRTISR R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_TISR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
32'd5 :
begin //ADD R0, 128
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R0,
/* Source1 */ 32'd128,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
32'd6 :
begin //SRTIDR R1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_TIDR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
32'd7 :
begin //MULL R1, 144
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R1,
/* Source1 */ 32'd144,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MULDIV_MULL,
/* Execute Module */ `EXE_SELECT_MUL
};
end
32'd8 :
begin //ADD R1, R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R1,
/* Source1 */ {{27{1'b0}}, `LOGICREG_R0},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
32'd9 :
begin //SRSPW R1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R1,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SPR,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_LDST_WRITE_SPR,
/* Execute Module */ `EXE_SELECT_SYS_LDST
};
end
32'd10 :
begin //PUSH SSR2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_SSR2, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd11 :
begin //PUSH SSR3
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_SSR3, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd12 :
begin //PUSH R2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R2, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd13 :
begin //PUSH R3
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R3, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd14 :
begin //PUSH R4
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R4, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd15 :
begin //PUSH R5
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R5, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd16 :
begin //PUSH R6
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R6, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd17 :
begin //PUSH R7
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R7, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd18 :
begin //PUSH R8
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R8, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd19 :
begin //PUSH R9
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R9, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd20 :
begin //PUSH R10
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R10, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd21 :
begin //PUSH R11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R11, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd22 :
begin //PUSH R12
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R12, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd23 :
begin //PUSH R13
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R13, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd24 :
begin //PUSH R14
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R14, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd25 :
begin //PUSH R15
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R15, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd26 :
begin //PUSH R16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R16, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd27 :
begin //PUSH R17
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R17, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd28 :
begin //PUSH R18
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R18, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd29 :
begin //PUSH R19
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R19, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd30 :
begin //PUSH R20
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R20, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd31 :
begin //PUSH R21
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R21, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd32 :
begin //PUSH R22
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R22, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd33 :
begin //PUSH R23
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R23, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd34 :
begin //PUSH R24
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R24, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd35 :
begin //PUSH R25
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R25, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd36 :
begin //PUSH R26
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R26, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd37 :
begin //PUSH R27
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R27, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd38 :
begin //PUSH R28
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R28, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd39 :
begin //PUSH R29
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R29, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd40 :
begin //PUSH R30
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R30, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd41 :
begin //PUSH R31
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R31, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd42 :
begin //PUSH SSR0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_SSR0, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd43 :
begin //PUSH SSR1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_SSR1, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd44 :
begin //SRPDTR R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_PDTR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
32'd45 :
begin //PUSH R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R0, //Rs
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ 5'h00, //Memory
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_LDSW_PUSH,
/* Execute Module */ `EXE_SELECT_LDST
};
end
default:
begin
$display("[ERROR] : microcode_context_store.v case Error");
f_decode = {74{1'b1}};
end
endcase
end
endfunction
endmodule
|
module erx_io (/*AUTOARG*/
// Outputs
rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
// Inputs
reset, rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait
);
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
//1=ephycard
// Can we do this in a better way?
//parameter [3:0] RX_TAP_DELAY [8:0]=;
//parameter RX_TAP_DELAY = 1;
parameter [5*10:0] RX_TAP_DELAY ={5'd0, //clk
5'd12, //frame
5'd12, //d7
5'd12, //d6
5'd12, //d5
5'd12, //d4
5'd12, //d3
5'd12, //d2
5'd12, //d1
5'd12 //d0
};
//#########################
//# reset, clocks
//#########################
input reset; // reset
input rx_lclk; // fast I/O clock
input rx_lclk_div4; // slow clock
output rx_lclk_pll; // clock output for pll
//##########################
//# elink pins
//##########################
input rxi_lclk_p, rxi_lclk_n; // rx clock input
input rxi_frame_p, rxi_frame_n; // rx frame signal
input [7:0] rxi_data_p, rxi_data_n; // rx data
output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
//##########################
//# erx logic interface
//##########################
output rx_access;
output rx_burst;
output [PW-1:0] rx_packet;
input rx_wr_wait;
input rx_rd_wait;
//############
//# WIRES
//############
wire [7:0] rxi_data;
wire rxi_frame;
wire rxi_lclk;
wire access_wide;
reg valid_packet;
reg [15:0] rx_word;
wire [15:0] rx_word_i;
//############
//# REGS
//############
reg [7:0] data_even_reg;
reg [7:0] data_odd_reg;
reg rx_frame;
wire rx_frame_i;
reg [111:0] rx_sample;
reg [6:0] rx_pointer;
reg access;
reg burst;
reg [PW-1:0] rx_packet_lclk;
reg rx_access;
reg [PW-1:0] rx_packet;
reg rx_burst;
wire rx_lclk_iddr;
wire [9:0] rxi_delay_in;
wire [9:0] rxi_delay_out;
//#####################
//#CREATE 112 BIT PACKET
//#####################
//write Pointer
always @ (posedge rx_lclk)
if (~rx_frame)
rx_pointer[6:0] <= 7'b0000001; //new frame
else if (rx_pointer[6])
rx_pointer[6:0] <= 7'b0001000; //anticipate burst
else if(rx_frame)
rx_pointer[6:0] <= {rx_pointer[5:0],1'b0};//middle of frame
//convert to 112 bit packet
always @ (posedge rx_lclk)
if(rx_frame)
begin
if(rx_pointer[0])
rx_sample[15:0] <= rx_word[15:0];
if(rx_pointer[1])
rx_sample[31:16] <= rx_word[15:0];
if(rx_pointer[2])
rx_sample[47:32] <= rx_word[15:0];
if(rx_pointer[3])
rx_sample[63:48] <= rx_word[15:0];
if(rx_pointer[4])
rx_sample[79:64] <= rx_word[15:0];
if(rx_pointer[5])
rx_sample[95:80] <= rx_word[15:0];
if(rx_pointer[6])
rx_sample[111:96] <= rx_word[15:0];
end // if (rx_frame)
//#####################
//#DATA VALID SIGNAL
//####################
always @ (posedge rx_lclk)
begin
access <= rx_pointer[6];
valid_packet <= access;//data pipeline
end
reg burst_detect;
always @ (posedge rx_lclk)
if(access & rx_frame)
burst_detect <= 1'b1;
else if(~rx_frame)
burst_detect <= 1'b0;
//###################################
//#SAMPLE AND HOLD DATA
//###################################
//(..and shuffle data for 104 bit packet)
always @ (posedge rx_lclk)
if(access)
begin
//pipelin burst (delay by one frame)
burst <= burst_detect;
//access
rx_packet_lclk[0] <= rx_sample[40];
//write
rx_packet_lclk[1] <= rx_sample[41];
//datamode
rx_packet_lclk[3:2] <= rx_sample[43:42];
//ctrlmode
rx_packet_lclk[7:4] <= rx_sample[15:12];
//dstaddr
rx_packet_lclk[39:8] <= {rx_sample[11:8],
rx_sample[23:16],
rx_sample[31:24],
rx_sample[39:32],
rx_sample[47:44]};
//data
rx_packet_lclk[71:40] <= {rx_sample[55:48],
rx_sample[63:56],
rx_sample[71:64],
rx_sample[79:72]};
//srcaddr
rx_packet_lclk[103:72]<= {rx_sample[87:80],
rx_sample[95:88],
rx_sample[103:96],
rx_sample[111:104]
};
end
//###################################
//#SYNCHRONIZE TO SLOW CLK
//###################################
//stretch access pulse to 4 cycles
pulse_stretcher #(.DW(3))
ps0 (
.out(access_wide),
.in(valid_packet),
.clk(rx_lclk),
.reset(reset));
always @ (posedge rx_lclk_div4)
rx_access <= access_wide;
always @ (posedge rx_lclk_div4)
if(access_wide)
begin
rx_packet[PW-1:0] <= rx_packet_lclk[PW-1:0];
rx_burst <= burst;
end
//################################
//# I/O Buffers Instantiation
//################################
IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_data[7:0]
(.I (rxi_data_p[7:0]),
.IB (rxi_data_n[7:0]),
.O (rxi_data[7:0]));
IBUFDS #(.DIFF_TERM ("TRUE"), .IOSTANDARD (IOSTD_ELINK))
ibuf_frame
(.I (rxi_frame_p),
.IB (rxi_frame_n),
.O (rxi_frame));
IBUFGDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_lclk (.I (rxi_lclk_p),
.IB (rxi_lclk_n),
.O (rxi_lclk)
);
generate
if(ETYPE==1)
begin
OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
obuft_wrwait (
.O(rxo_wr_wait_p),
.T(rx_wr_wait),
.I(1'b0)
);
OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
obuft_rdwait (
.O(rxo_rd_wait_p),
.T(rx_rd_wait),
.I(1'b0)
);
assign rxo_wr_wait_n = 1'b0;
assign rxo_rd_wait_n = 1'b0;
end
else if(ETYPE==0)
begin
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_wrwait (
.O(rxo_wr_wait_p),
.OB(rxo_wr_wait_n),
.I(rx_wr_wait)
);
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_rdwait (.O(rxo_rd_wait_p),
.OB(rxo_rd_wait_n),
.I(rx_rd_wait)
);
end
endgenerate
//###################################
//#RX CLOCK
//###################################
BUFG rxi_lclk_bufg_i(.I(rxi_lclk), .O(rx_lclk_pll)); //for mmcm
BUFIO rx_lclk_bufio_i(.I(rxi_delay_out[9]), .O(rx_lclk_iddr));//for iddr (NOT USED!)
//###################################
//#IDELAY CIRCUIT
//###################################
assign rxi_delay_in[9:0] ={rxi_lclk,rxi_frame,rxi_data[7:0]};
genvar j;
generate for(j=0; j<10; j=j+1)
begin : gen_idelay
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("FALSE"),
.IDELAY_TYPE("FIXED"),
.IDELAY_VALUE(RX_TAP_DELAY[(j+1)*5-1:j*5]),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA"))
idelay_inst (.CNTVALUEOUT(),
.DATAOUT(rxi_delay_out[j]),
.C(1'b0),
.CE(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'b0),
.DATAIN(1'b0),
.IDATAIN(rxi_delay_in[j]),
.INC(1'b0),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
end // block: gen_idelay
endgenerate
//#############################
//# IDDR SAMPLERS
//#############################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_iddr
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_data (
.Q1 (rx_word_i[i]),
.Q2 (rx_word_i[i+8]),
.C (rx_lclk),//rx_lclk_iddr
.CE (1'b1),
.D (rxi_delay_out[i]),
.R (reset),
.S (1'b0)
);
end
endgenerate
//FRAME
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_frame (
.Q1 (rx_frame_i),
.Q2 (),
.C (rx_lclk),//rx_lclk_iddr
.CE (1'b1),
.D (rxi_delay_out[8]),
.R (reset),
.S (1'b0)
);
always @ ( posedge rx_lclk )
rx_frame <= rx_frame_i;
always @ ( posedge rx_lclk )
rx_word <= rx_word_i;
endmodule
|
module sky130_fd_sc_lp__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module sky130_fd_sc_ms__a211o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_hs__a31o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
|
module sky130_fd_sc_lp__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
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