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module sky130_fd_sc_ms__nor2b_4 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__nor2b_4 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
|
module ram_r(
input clk,
input rst,
output wire[ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire[BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input wire[DATA_WIDTH-1:0] ram_r_readdata,
output wire[BURST_WIDTH_R-1:0] ram_r_burstcount,
output wire [DATA_WIDTH-1:0] data_fifo_in,
input read_fifo_in,
input start_fifo_in,
input [ADD_WIDTH-1:0] address_fifo_in,
input [DATA_WIDTH-1:0] n_burst_fifo_in,
output wire bussy_fifo_in,
output wire empty_fifo_in,
output wire [FIFO_DEPTH_LOG2:0] usedw_fifo_in
);
parameter DATA_WIDTH = 32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // derived parameter
parameter MAX_BURST_COUNT_R = 32; // must be a multiple of 2 between 2 and 1024, when bursting is disabled this value must be set to 1
parameter BURST_WIDTH_R = 6;
parameter FIFO_DEPTH_LOG2 = 8;
parameter FIFO_DEPTH = 256;
wire read_complete;
reg [DATA_WIDTH-1:0] reads_pending;
wire read_burst_end;
reg next_r;
wire too_many_reads_pending;
reg [ADD_WIDTH-1:0] read_address;
reg [DATA_WIDTH-1:0] in_n;
reg [DATA_WIDTH-1:0] in_n_2;
wire fifo_full;
wire fifo_empty;
wire [FIFO_DEPTH_LOG2:0] fifo_used;
scfifo master_to_st_fifo(
.aclr(start_fifo_in),
.clock(clk),
.data(ram_r_readdata),
.wrreq(read_complete),
.q(data_fifo_in),
.rdreq(read_fifo_in),
.full(fifo_full),
.empty(fifo_empty),
.usedw(fifo_used[FIFO_DEPTH_LOG2-1:0])
);
defparam master_to_st_fifo.lpm_width = DATA_WIDTH;
defparam master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam master_to_st_fifo.lpm_showahead = "ON";
defparam master_to_st_fifo.use_eab = "ON";
defparam master_to_st_fifo.add_ram_output_register = "OFF"; // FIFO latency of 2
defparam master_to_st_fifo.underflow_checking = "OFF";
defparam master_to_st_fifo.overflow_checking = "OFF";
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_complete == 1) begin
in_n <= in_n - 1;
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n_2 <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n_2 <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_burst_end == 1) begin
in_n_2 <= in_n_2 - MAX_BURST_COUNT_R;
end
end
end
end
always @(posedge clk) begin
if (start_fifo_in == 1) begin
read_address <= address_fifo_in;
end else begin
if (read_burst_end == 1) begin
read_address <= read_address + MAX_BURST_COUNT_R * BYTE_ENABLE_WIDTH;
end
end
end
// tracking FIFO
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
reads_pending <= 0;
end else begin
if(read_burst_end == 1) begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R;
end else begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R - 1; // a burst read was posted, but a word returned
end
end else begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end else begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
next_r <= 0;
end else begin
if(read_burst_end == 1) begin
next_r <= 0;
end else begin
if (ram_r_read == 1) begin
next_r <= 1;
end
end
end
end
assign read_complete = (ram_r_readdatavalid == 1);
assign read_burst_end = (ram_r_waitrequest == 0) & (next_r == 1);// & (header_c > 4);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFO_DEPTH - MAX_BURST_COUNT_R - 4); // make sure there are fewer reads posted than room in the FIFO
assign ram_r_address = read_address;
assign ram_r_read = (too_many_reads_pending == 0) & (in_n_2 != 0);// & (header_c > 4);
assign ram_r_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_r_burstcount = MAX_BURST_COUNT_R;
assign bussy_fifo_in = in_n != 0;
assign empty_fifo_in = fifo_empty;
assign usedw_fifo_in = fifo_used;
endmodule
|
module pdatapath_top(
input wire clk,
input wire top_pb_clk,
input wire right_pb_rst_general
);
wire [7:0] alu_1st_input, alu_2nd_input;
wire [7:0] alu_output;
wire [2:0] ALUOp;
wire alu_ovf_flag;
wire alu_zero_output;
wire [15:0] instruction;
//insturction fields
wire [3:0] opcode;
wire [1:0] rs_addr;
wire [1:0] rt_addr;
wire [1:0] rd_addr;
wire [7:0] immediate;
//control signals
wire RegDst;
wire RegWrite;
wire ALUSrc1;
wire ALUSrc2;
wire MemWrite;
wire MemToReg;
wire [1:0] regfile_write_address;//destination register address
wire [8:0] regfile_write_data;//result data
wire [8:0] read_data1;//source register1 data
wire [8:0] read_data2;//source register2 data
wire [8:0] alu_result;
wire [8:0] zero_register;
wire [8:0] data_mem_out;
wire pb_clk_debounced;
wire [7:0] pc;
debounce debounce_clk(
.clk_in(clk),
.rst_in(right_pb_rst_general),
.sig_in(top_pb_clk),
.sig_debounced_out(pb_clk_debounced)
);
inst_decoder instruction_decoder (
.instruction(instruction),
.opcode(opcode),
.rs_addr(rs_addr),
.rt_addr(rt_addr),
.rd_addr(rd_addr),
.immediate(immediate),
.RegDst(RegDst),
.RegWrite(RegWrite),
.ALUSrc1(ALUSrc1),
.ALUSrc2(ALUSrc2),
.ALUOp(ALUOp),
.MemWrite(MemWrite),
.MemToReg(MemToReg)
);
//Select the right signal for the ALU's first input
assign alu_1st_input = ALUSrc1 ? zero_register[7:0] : read_data1[7:0];
//Select the right signal for the ALU's second input
assign alu_2nd_input = ALUSrc2 ? immediate[7:0] : read_data2[7:0];
assign zero_register = 8'b0;//ZERO constant
//ALU
eightbit_alu alu (
.a(alu_1st_input),
.b(alu_2nd_input),
.sel(ALUOp),
.f(alu_output),
.ovf(alu_ovf_flag),
.zero(alu_zero_output)
);
//VIO Module
vio_0 vio_core (
.clk(clk), // input wire clk
.probe_in0(alu_output), // input wire [7 : 0] probe_in0
.probe_in1(alu_ovf_flag), // input wire [0 : 0] probe_in1
.probe_in2(alu_zero_output), // input wire [0 : 0] probe_in2
.probe_in3(read_data1), // input wire [7 : 0] probe_in3
.probe_in4(read_data2), // input wire [7 : 0] probe_in4
.probe_in5(alu_1st_input), // input wire [7 : 0] probe_in5
.probe_in6(alu_2nd_input), // input wire [7 : 0] probe_in6
.probe_in7(read_data2), // input wire [8 : 0] probe_in7
.probe_in8(data_mem_out), // input wire [8 : 0] probe_in8
.probe_in9(opcode), // input wire [2 : 0] probe_in9
.probe_in10(rs_addr), // input wire [1 : 0] probe_in10
.probe_in11(rt_addr), // input wire [1 : 0] probe_in11
.probe_in12(rd_addr), // input wire [1 : 0] probe_in12
.probe_in13(immediate), // input wire [7 : 0] probe_in13
.probe_in14(RegDst), // input wire [0 : 0] probe_in14
.probe_in15(RegWrite), // input wire [0 : 0] probe_in15
.probe_in16(ALUSrc1), // input wire [0 : 0] probe_in16
.probe_in17(ALUSrc2), // input wire [0 : 0] probe_in17
.probe_in18(ALUOp), // input wire [0 : 0] probe_in18
.probe_in19(MemWrite), // input wire [0 : 0] probe_in19
.probe_in20(MemToReg), // input wire [0 : 0] probe_in20
.probe_in21(pc), // input wire [7 : 0] probe_in21
.probe_in22(instruction) // input wire [15 : 0] probe_in22
);
assign alu_result = {alu_ovf_flag, alu_output};
//Select the right signal for the register file write data
assign regfile_write_data = MemToReg ? data_mem_out : alu_result;
//Select the right signal for the register file write address
assign regfile_write_address = RegDst ? rd_addr : rt_addr;
reg_file register_file (
.rst(right_pb_rst_general),//reset
.clk(pb_clk_debounced),//clock
.wr_en(RegWrite),//Write enable
.rd0_addr(rs_addr),//source register1 address
.rd1_addr(rt_addr),//source register2 address
.wr_addr(regfile_write_address),//destination register address
.wr_data(regfile_write_data),//result data
.rd0_data(read_data1),//source register1 data
.rd1_data(read_data2)//source register2 data
);
data_memory_take2 data_memory (
.a(alu_output), // input wire [7 : 0] a
.d(read_data2), // input wire [8 : 0] d
.clk(pb_clk_debounced), // input wire clk
.we(MemWrite), // input wire we
.spo(data_mem_out) // output wire [8 : 0] spo
);
program_counter program_counter(
.clk(pb_clk_debounced),
.rst(right_pb_rst_general),
.branch_offs(immediate),
.ALU_zero(alu_zero_output),
.value(pc)
);
instr_memory inst_memory (
.clka(pb_clk_debounced), // input wire clka
.rsta(right_pb_rst_general), // input wire rsta
.addra(pc), // input wire [7 : 0] addra
.douta(instruction) ); //ire [15 : 0] douta
endmodule
|
module CacheBlockRAM (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input clock;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] sub_wire1;
wire [17:0] q_a = sub_wire0[17:0];
wire [17:0] q_b = sub_wire1[17:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 18,
altsyncram_component.width_b = 18,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
|
module sky130_fd_sc_lp__nand2b_4 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__nand2b_4 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
|
module sky130_fd_sc_ms__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_ls__decaphe_18 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__decaphe base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__decaphe_18 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__decaphe base ();
endmodule
|
module top
(
input wire clk,
input wire [15:0] sw,
output wire [15:0] led,
input wire rx,
output wire tx,
inout wire jc1, // sda
inout wire jc2, // scl
output wire jc3, // unused
input wire jc4 // unused
);
// ============================================================================
// IOBUFs
wire sda_i;
wire sda_o;
wire sda_t;
wire scl_i;
wire scl_o;
wire scl_t;
IOBUF # (
.IOSTANDARD("LVCMOS33"),
.DRIVE(12),
.SLEW("SLOW")
)
iobuf_sda
(
.I (sda_i),
.O (sda_o),
.T (sda_t),
.IO (jc1)
);
IOBUF # (
.IOSTANDARD("LVCMOS33"),
.DRIVE(12),
.SLEW("SLOW")
)
iobuf_scl
(
.I (scl_i),
.O (scl_o),
.T (scl_t),
.IO (jc2)
);
// ============================================================================
// Clock buffer, reset generator
reg [3:0] rst_sr;
wire rst;
wire clk_g;
initial rst_sr <= 4'hF;
always @(posedge clk_g)
if (sw[0]) rst_sr <= 4'hF;
else rst_sr = {1'b0, rst_sr[3:1]};
assign rst = rst_sr[0];
wire clk_ibuf;
IBUF ibuf (.I(clk), .O(clk_ibuf));
BUFG bufg (.I(clk_ibuf), .O(clk_g));
// ============================================================================
// I2C scanner
wire i2c_scan_trg;
wire i2c_scan_trg_en;
wire i2c_scan_bsy;
// Button synchronizer
reg [3:0] i2c_scan_trg_en_sr;
initial i2c_scan_trg_en_sr <= 4'h0;
always @(posedge clk_g)
i2c_scan_trg_en_sr <= {sw[1], i2c_scan_trg_en_sr[3:1]};
// The scanner
i2c_scan #
(
.UART_PRESCALER (868), // 115200 @100MHz
.I2C_PRESCALER (250) // 100kHz @100MHz
)
i2c_scan
(
.clk (clk_g),
.rst (rst),
.scl_i (scl_o),
.scl_o (scl_i),
.scl_t (scl_t),
.sda_i (sda_o),
.sda_o (sda_i),
.sda_t (sda_t),
.rx (rx),
.tx (tx),
.i_trg (i2c_scan_trg & i2c_scan_trg_en_sr[0]),
.i_bsy (i2c_scan_bsy)
);
// Trigger generator
reg [32:0] trg_cnt;
always @(posedge clk_g)
if (rst) trg_cnt <= 0;
else if (trg_cnt[32]) trg_cnt <= 1 * 100000000; // 1s @100MHz
else trg_cnt <= trg_cnt - 1;
assign i2c_scan_trg = trg_cnt[32];
// ============================================================================
// I/O
assign led[0] = rst;
assign led[1] = i2c_scan_bsy;
assign led[15:2] = sw[15:2];
endmodule
|
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n7077, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_exp_operation_A_S, FPMULT_FSM_add_overflow_flag,
FPMULT_zero_flag, FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG,
FPADDSUB_SIGN_FLAG_NRM, FPADDSUB_SIGN_FLAG_SHT1SHT2,
FPADDSUB_ADD_OVRFLW_NRM2, FPADDSUB_OP_FLAG_SHT2,
FPADDSUB_SIGN_FLAG_SHT2, FPADDSUB_bit_shift_SHT2,
FPADDSUB_left_right_SHT2, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1236, n1237, n1238, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1288, n1289, n1290, n1291, n1292, n1293,
n1295, n1296, n1297, n1298, n1299, n1300, n1302, n1303, n1304, n1305,
n1306, n1307, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1481, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796,
n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806,
n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816,
n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826,
n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836,
n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846,
n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856,
n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866,
n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876,
n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886,
n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896,
n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906,
n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916,
n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926,
n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936,
n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946,
n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956,
n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966,
n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976,
n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986,
n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996,
n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006,
n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016,
n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026,
n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036,
n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046,
n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056,
n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066,
n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076,
n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086,
n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096,
n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106,
n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116,
n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126,
n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136,
n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146,
n2147, n2148, n2149, n2191, mult_x_311_n37, mult_x_311_n36,
mult_x_311_n30, mult_x_311_n29, mult_x_311_n23, mult_x_311_n22,
mult_x_311_n18, mult_x_311_n17, mult_x_311_n15, mult_x_311_n14,
mult_x_309_n37, mult_x_309_n36, mult_x_309_n30, mult_x_309_n29,
mult_x_309_n23, mult_x_309_n22, mult_x_309_n18, mult_x_309_n17,
mult_x_309_n15, mult_x_309_n14, DP_OP_26J223_129_1325_n18,
DP_OP_26J223_129_1325_n17, DP_OP_26J223_129_1325_n16,
DP_OP_26J223_129_1325_n15, DP_OP_26J223_129_1325_n14,
DP_OP_26J223_129_1325_n8, DP_OP_26J223_129_1325_n7,
DP_OP_26J223_129_1325_n6, DP_OP_26J223_129_1325_n5,
DP_OP_26J223_129_1325_n4, DP_OP_26J223_129_1325_n3,
DP_OP_26J223_129_1325_n2, DP_OP_26J223_129_1325_n1,
DP_OP_234J223_132_4955_n22, DP_OP_234J223_132_4955_n21,
DP_OP_234J223_132_4955_n20, DP_OP_234J223_132_4955_n19,
DP_OP_234J223_132_4955_n18, DP_OP_234J223_132_4955_n17,
DP_OP_234J223_132_4955_n16, DP_OP_234J223_132_4955_n15,
DP_OP_234J223_132_4955_n9, DP_OP_234J223_132_4955_n8,
DP_OP_234J223_132_4955_n7, DP_OP_234J223_132_4955_n6,
DP_OP_234J223_132_4955_n5, DP_OP_234J223_132_4955_n4,
DP_OP_234J223_132_4955_n3, DP_OP_234J223_132_4955_n2,
DP_OP_234J223_132_4955_n1, intadd_512_A_7_, intadd_512_A_6_,
intadd_512_A_5_, intadd_512_A_4_, intadd_512_A_3_, intadd_512_A_2_,
intadd_512_A_1_, intadd_512_A_0_, intadd_512_B_7_, intadd_512_B_6_,
intadd_512_B_5_, intadd_512_B_4_, intadd_512_B_3_, intadd_512_B_2_,
intadd_512_B_1_, intadd_512_B_0_, intadd_512_CI, intadd_512_SUM_7_,
intadd_512_SUM_6_, intadd_512_SUM_5_, intadd_512_SUM_4_,
intadd_512_SUM_3_, intadd_512_SUM_2_, intadd_512_SUM_1_,
intadd_512_SUM_0_, intadd_512_n8, intadd_512_n7, intadd_512_n6,
intadd_512_n5, intadd_512_n4, intadd_512_n3, intadd_512_n2,
intadd_512_n1, intadd_513_A_7_, intadd_513_A_0_, intadd_513_B_7_,
intadd_513_B_6_, intadd_513_B_1_, intadd_513_B_0_, intadd_513_CI,
intadd_513_n8, intadd_513_n7, intadd_513_n6, intadd_513_n5,
intadd_513_n4, intadd_513_n3, intadd_513_n2, intadd_513_n1,
intadd_514_A_7_, intadd_514_A_6_, intadd_514_A_5_, intadd_514_A_4_,
intadd_514_A_3_, intadd_514_A_2_, intadd_514_A_1_, intadd_514_A_0_,
intadd_514_B_7_, intadd_514_B_6_, intadd_514_B_5_, intadd_514_B_4_,
intadd_514_B_3_, intadd_514_B_2_, intadd_514_B_1_, intadd_514_B_0_,
intadd_514_CI, intadd_514_SUM_7_, intadd_514_SUM_6_,
intadd_514_SUM_5_, intadd_514_SUM_4_, intadd_514_SUM_3_,
intadd_514_SUM_2_, intadd_514_SUM_1_, intadd_514_SUM_0_,
intadd_514_n8, intadd_514_n7, intadd_514_n6, intadd_514_n5,
intadd_514_n4, intadd_514_n3, intadd_514_n2, intadd_514_n1,
intadd_515_A_0_, intadd_515_B_6_, intadd_515_B_1_, intadd_515_B_0_,
intadd_515_CI, intadd_515_n7, intadd_515_n6, intadd_515_n5,
intadd_515_n4, intadd_515_n3, intadd_515_n2, intadd_515_n1,
intadd_516_CI, intadd_516_SUM_2_, intadd_516_SUM_1_,
intadd_516_SUM_0_, intadd_516_n3, intadd_516_n2, intadd_516_n1,
intadd_517_B_1_, intadd_517_CI, intadd_517_SUM_2_, intadd_517_SUM_1_,
intadd_517_SUM_0_, intadd_517_n3, intadd_517_n2, intadd_517_n1,
intadd_518_CI, intadd_518_SUM_2_, intadd_518_SUM_1_,
intadd_518_SUM_0_, intadd_518_n3, intadd_518_n2, intadd_518_n1,
DP_OP_500J223_126_4510_n188, DP_OP_500J223_126_4510_n187,
DP_OP_500J223_126_4510_n186, DP_OP_500J223_126_4510_n185,
DP_OP_500J223_126_4510_n181, DP_OP_500J223_126_4510_n180,
DP_OP_500J223_126_4510_n179, DP_OP_500J223_126_4510_n178,
DP_OP_500J223_126_4510_n174, DP_OP_500J223_126_4510_n172,
DP_OP_500J223_126_4510_n171, DP_OP_500J223_126_4510_n170,
DP_OP_500J223_126_4510_n165, DP_OP_500J223_126_4510_n164,
DP_OP_500J223_126_4510_n162, DP_OP_500J223_126_4510_n161,
DP_OP_500J223_126_4510_n158, DP_OP_500J223_126_4510_n157,
DP_OP_500J223_126_4510_n155, DP_OP_500J223_126_4510_n154,
DP_OP_500J223_126_4510_n151, DP_OP_500J223_126_4510_n150,
DP_OP_500J223_126_4510_n147, DP_OP_500J223_126_4510_n141,
DP_OP_500J223_126_4510_n138, DP_OP_500J223_126_4510_n137,
DP_OP_500J223_126_4510_n136, DP_OP_500J223_126_4510_n135,
DP_OP_500J223_126_4510_n134, DP_OP_500J223_126_4510_n132,
DP_OP_500J223_126_4510_n131, DP_OP_500J223_126_4510_n130,
DP_OP_500J223_126_4510_n129, DP_OP_500J223_126_4510_n128,
DP_OP_500J223_126_4510_n127, DP_OP_500J223_126_4510_n126,
DP_OP_500J223_126_4510_n125, DP_OP_500J223_126_4510_n124,
DP_OP_500J223_126_4510_n123, DP_OP_500J223_126_4510_n122,
DP_OP_500J223_126_4510_n121, DP_OP_500J223_126_4510_n120,
DP_OP_500J223_126_4510_n119, DP_OP_500J223_126_4510_n118,
DP_OP_500J223_126_4510_n117, DP_OP_500J223_126_4510_n116,
DP_OP_500J223_126_4510_n115, DP_OP_500J223_126_4510_n112,
DP_OP_500J223_126_4510_n111, DP_OP_500J223_126_4510_n110,
DP_OP_500J223_126_4510_n109, DP_OP_500J223_126_4510_n108,
DP_OP_500J223_126_4510_n107, DP_OP_500J223_126_4510_n106,
DP_OP_500J223_126_4510_n105, DP_OP_500J223_126_4510_n104,
DP_OP_500J223_126_4510_n103, DP_OP_500J223_126_4510_n102,
DP_OP_500J223_126_4510_n101, DP_OP_500J223_126_4510_n100,
DP_OP_502J223_128_4510_n188, DP_OP_502J223_128_4510_n187,
DP_OP_502J223_128_4510_n186, DP_OP_502J223_128_4510_n185,
DP_OP_502J223_128_4510_n181, DP_OP_502J223_128_4510_n180,
DP_OP_502J223_128_4510_n179, DP_OP_502J223_128_4510_n178,
DP_OP_502J223_128_4510_n174, DP_OP_502J223_128_4510_n172,
DP_OP_502J223_128_4510_n171, DP_OP_502J223_128_4510_n170,
DP_OP_502J223_128_4510_n165, DP_OP_502J223_128_4510_n164,
DP_OP_502J223_128_4510_n162, DP_OP_502J223_128_4510_n161,
DP_OP_502J223_128_4510_n158, DP_OP_502J223_128_4510_n157,
DP_OP_502J223_128_4510_n155, DP_OP_502J223_128_4510_n154,
DP_OP_502J223_128_4510_n151, DP_OP_502J223_128_4510_n150,
DP_OP_502J223_128_4510_n147, DP_OP_502J223_128_4510_n141,
DP_OP_502J223_128_4510_n138, DP_OP_502J223_128_4510_n137,
DP_OP_502J223_128_4510_n136, DP_OP_502J223_128_4510_n135,
DP_OP_502J223_128_4510_n134, DP_OP_502J223_128_4510_n132,
DP_OP_502J223_128_4510_n131, DP_OP_502J223_128_4510_n130,
DP_OP_502J223_128_4510_n129, DP_OP_502J223_128_4510_n128,
DP_OP_502J223_128_4510_n127, DP_OP_502J223_128_4510_n126,
DP_OP_502J223_128_4510_n125, DP_OP_502J223_128_4510_n124,
DP_OP_502J223_128_4510_n123, DP_OP_502J223_128_4510_n122,
DP_OP_502J223_128_4510_n121, DP_OP_502J223_128_4510_n120,
DP_OP_502J223_128_4510_n119, DP_OP_502J223_128_4510_n118,
DP_OP_502J223_128_4510_n117, DP_OP_502J223_128_4510_n116,
DP_OP_502J223_128_4510_n115, DP_OP_502J223_128_4510_n112,
DP_OP_502J223_128_4510_n111, DP_OP_502J223_128_4510_n110,
DP_OP_502J223_128_4510_n109, DP_OP_502J223_128_4510_n108,
DP_OP_502J223_128_4510_n107, DP_OP_502J223_128_4510_n106,
DP_OP_502J223_128_4510_n105, DP_OP_502J223_128_4510_n104,
DP_OP_502J223_128_4510_n103, DP_OP_502J223_128_4510_n102,
DP_OP_502J223_128_4510_n101, DP_OP_502J223_128_4510_n100,
DP_OP_499J223_125_1651_n304, DP_OP_499J223_125_1651_n303,
DP_OP_499J223_125_1651_n302, DP_OP_499J223_125_1651_n301,
DP_OP_499J223_125_1651_n300, DP_OP_499J223_125_1651_n299,
DP_OP_499J223_125_1651_n297, DP_OP_499J223_125_1651_n296,
DP_OP_499J223_125_1651_n295, DP_OP_499J223_125_1651_n294,
DP_OP_499J223_125_1651_n293, DP_OP_499J223_125_1651_n292,
DP_OP_499J223_125_1651_n281, DP_OP_499J223_125_1651_n280,
DP_OP_499J223_125_1651_n279, DP_OP_499J223_125_1651_n278,
DP_OP_499J223_125_1651_n277, DP_OP_499J223_125_1651_n276,
DP_OP_499J223_125_1651_n274, DP_OP_499J223_125_1651_n273,
DP_OP_499J223_125_1651_n272, DP_OP_499J223_125_1651_n271,
DP_OP_499J223_125_1651_n270, DP_OP_499J223_125_1651_n269,
DP_OP_499J223_125_1651_n268, DP_OP_499J223_125_1651_n266,
DP_OP_499J223_125_1651_n252, DP_OP_499J223_125_1651_n250,
DP_OP_499J223_125_1651_n249, DP_OP_499J223_125_1651_n248,
DP_OP_499J223_125_1651_n247, DP_OP_499J223_125_1651_n246,
DP_OP_499J223_125_1651_n245, DP_OP_499J223_125_1651_n244,
DP_OP_499J223_125_1651_n243, DP_OP_499J223_125_1651_n242,
DP_OP_499J223_125_1651_n241, DP_OP_499J223_125_1651_n240,
DP_OP_499J223_125_1651_n239, DP_OP_499J223_125_1651_n238,
DP_OP_499J223_125_1651_n237, DP_OP_499J223_125_1651_n236,
DP_OP_499J223_125_1651_n235, DP_OP_499J223_125_1651_n234,
DP_OP_499J223_125_1651_n233, DP_OP_499J223_125_1651_n232,
DP_OP_499J223_125_1651_n231, DP_OP_499J223_125_1651_n230,
DP_OP_499J223_125_1651_n229, DP_OP_499J223_125_1651_n228,
DP_OP_499J223_125_1651_n227, DP_OP_499J223_125_1651_n226,
DP_OP_499J223_125_1651_n225, DP_OP_499J223_125_1651_n224,
DP_OP_499J223_125_1651_n223, DP_OP_499J223_125_1651_n222,
DP_OP_499J223_125_1651_n221, DP_OP_499J223_125_1651_n220,
DP_OP_499J223_125_1651_n219, DP_OP_499J223_125_1651_n218,
DP_OP_499J223_125_1651_n217, DP_OP_499J223_125_1651_n216,
DP_OP_499J223_125_1651_n215, DP_OP_499J223_125_1651_n214,
DP_OP_499J223_125_1651_n213, DP_OP_499J223_125_1651_n212,
DP_OP_499J223_125_1651_n211, DP_OP_499J223_125_1651_n210,
DP_OP_499J223_125_1651_n209, DP_OP_499J223_125_1651_n208,
DP_OP_499J223_125_1651_n207, DP_OP_499J223_125_1651_n206,
DP_OP_499J223_125_1651_n205, DP_OP_499J223_125_1651_n204,
DP_OP_499J223_125_1651_n203, DP_OP_499J223_125_1651_n202,
DP_OP_496J223_122_3236_n147, DP_OP_501J223_127_5235_n944,
DP_OP_501J223_127_5235_n903, DP_OP_501J223_127_5235_n897,
DP_OP_501J223_127_5235_n723, DP_OP_501J223_127_5235_n630,
DP_OP_501J223_127_5235_n523, DP_OP_501J223_127_5235_n521,
DP_OP_501J223_127_5235_n517, DP_OP_501J223_127_5235_n515,
DP_OP_501J223_127_5235_n511, DP_OP_501J223_127_5235_n510,
DP_OP_501J223_127_5235_n509, DP_OP_501J223_127_5235_n508,
DP_OP_501J223_127_5235_n503, DP_OP_501J223_127_5235_n500,
DP_OP_501J223_127_5235_n497, DP_OP_501J223_127_5235_n495,
DP_OP_501J223_127_5235_n494, DP_OP_501J223_127_5235_n491,
DP_OP_501J223_127_5235_n488, DP_OP_501J223_127_5235_n482,
DP_OP_501J223_127_5235_n479, DP_OP_501J223_127_5235_n478,
DP_OP_501J223_127_5235_n477, DP_OP_501J223_127_5235_n476,
DP_OP_501J223_127_5235_n475, DP_OP_501J223_127_5235_n474,
DP_OP_501J223_127_5235_n473, DP_OP_501J223_127_5235_n472,
DP_OP_501J223_127_5235_n471, DP_OP_501J223_127_5235_n470,
DP_OP_501J223_127_5235_n469, DP_OP_501J223_127_5235_n468,
DP_OP_501J223_127_5235_n467, DP_OP_501J223_127_5235_n466,
DP_OP_501J223_127_5235_n465, DP_OP_501J223_127_5235_n464,
DP_OP_501J223_127_5235_n463, DP_OP_501J223_127_5235_n462,
DP_OP_501J223_127_5235_n460, DP_OP_501J223_127_5235_n459,
DP_OP_501J223_127_5235_n458, DP_OP_501J223_127_5235_n457,
DP_OP_501J223_127_5235_n456, DP_OP_501J223_127_5235_n455,
DP_OP_501J223_127_5235_n454, DP_OP_501J223_127_5235_n453,
DP_OP_501J223_127_5235_n452, DP_OP_501J223_127_5235_n451,
DP_OP_501J223_127_5235_n450, DP_OP_501J223_127_5235_n449,
DP_OP_501J223_127_5235_n448, DP_OP_501J223_127_5235_n447,
DP_OP_501J223_127_5235_n263, DP_OP_501J223_127_5235_n262,
DP_OP_501J223_127_5235_n261, DP_OP_501J223_127_5235_n260,
DP_OP_501J223_127_5235_n259, DP_OP_501J223_127_5235_n254,
DP_OP_501J223_127_5235_n253, DP_OP_501J223_127_5235_n252,
DP_OP_501J223_127_5235_n251, DP_OP_501J223_127_5235_n250,
DP_OP_501J223_127_5235_n247, DP_OP_501J223_127_5235_n246,
DP_OP_501J223_127_5235_n245, DP_OP_501J223_127_5235_n244,
DP_OP_501J223_127_5235_n243, DP_OP_501J223_127_5235_n242,
DP_OP_501J223_127_5235_n241, DP_OP_501J223_127_5235_n237,
DP_OP_501J223_127_5235_n236, DP_OP_501J223_127_5235_n235,
DP_OP_501J223_127_5235_n234, DP_OP_501J223_127_5235_n233,
DP_OP_501J223_127_5235_n232, DP_OP_501J223_127_5235_n229,
DP_OP_501J223_127_5235_n228, DP_OP_501J223_127_5235_n227,
DP_OP_501J223_127_5235_n225, DP_OP_501J223_127_5235_n224,
DP_OP_501J223_127_5235_n219, DP_OP_501J223_127_5235_n216,
DP_OP_501J223_127_5235_n214, DP_OP_501J223_127_5235_n211,
DP_OP_501J223_127_5235_n208, DP_OP_501J223_127_5235_n207,
DP_OP_501J223_127_5235_n206, DP_OP_501J223_127_5235_n203,
DP_OP_501J223_127_5235_n200, DP_OP_501J223_127_5235_n198,
DP_OP_501J223_127_5235_n193, DP_OP_501J223_127_5235_n191,
DP_OP_501J223_127_5235_n190, DP_OP_501J223_127_5235_n188,
DP_OP_501J223_127_5235_n187, DP_OP_501J223_127_5235_n186,
DP_OP_501J223_127_5235_n184, DP_OP_501J223_127_5235_n183,
DP_OP_501J223_127_5235_n182, DP_OP_501J223_127_5235_n181,
DP_OP_501J223_127_5235_n180, DP_OP_501J223_127_5235_n179,
DP_OP_501J223_127_5235_n178, DP_OP_501J223_127_5235_n176,
DP_OP_501J223_127_5235_n175, DP_OP_501J223_127_5235_n174,
DP_OP_501J223_127_5235_n173, DP_OP_501J223_127_5235_n172,
DP_OP_501J223_127_5235_n171, DP_OP_501J223_127_5235_n169,
DP_OP_501J223_127_5235_n168, DP_OP_501J223_127_5235_n167,
DP_OP_501J223_127_5235_n166, DP_OP_501J223_127_5235_n165,
DP_OP_501J223_127_5235_n164, DP_OP_501J223_127_5235_n163,
DP_OP_501J223_127_5235_n162, DP_OP_501J223_127_5235_n161,
DP_OP_501J223_127_5235_n160, DP_OP_501J223_127_5235_n159,
DP_OP_501J223_127_5235_n158, DP_OP_501J223_127_5235_n157,
DP_OP_501J223_127_5235_n156, DP_OP_501J223_127_5235_n155,
DP_OP_501J223_127_5235_n154, DP_OP_501J223_127_5235_n153,
DP_OP_501J223_127_5235_n152, DP_OP_501J223_127_5235_n151,
DP_OP_501J223_127_5235_n150, DP_OP_501J223_127_5235_n149,
DP_OP_501J223_127_5235_n148, DP_OP_501J223_127_5235_n147,
DP_OP_501J223_127_5235_n146, DP_OP_501J223_127_5235_n145,
DP_OP_501J223_127_5235_n144, DP_OP_501J223_127_5235_n143,
DP_OP_501J223_127_5235_n142, DP_OP_501J223_127_5235_n141,
DP_OP_501J223_127_5235_n140, DP_OP_501J223_127_5235_n139,
DP_OP_501J223_127_5235_n138, DP_OP_501J223_127_5235_n137,
DP_OP_501J223_127_5235_n136, DP_OP_501J223_127_5235_n135,
DP_OP_501J223_127_5235_n134, DP_OP_501J223_127_5235_n133,
DP_OP_501J223_127_5235_n132, DP_OP_501J223_127_5235_n131,
DP_OP_501J223_127_5235_n130, DP_OP_501J223_127_5235_n129,
DP_OP_501J223_127_5235_n128, DP_OP_501J223_127_5235_n127,
DP_OP_501J223_127_5235_n126, DP_OP_501J223_127_5235_n125,
DP_OP_501J223_127_5235_n124, DP_OP_501J223_127_5235_n123,
DP_OP_501J223_127_5235_n122, DP_OP_501J223_127_5235_n121,
DP_OP_501J223_127_5235_n120, n2194, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401,
n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411,
n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791,
n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801,
n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811,
n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821,
n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831,
n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841,
n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851,
n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861,
n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991,
n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001,
n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011,
n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021,
n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051,
n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061,
n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071,
n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081,
n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091,
n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101,
n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111,
n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121,
n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141,
n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151,
n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161,
n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171,
n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181,
n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191,
n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201,
n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211,
n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221,
n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231,
n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241,
n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251,
n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261,
n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271,
n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281,
n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291,
n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301,
n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311,
n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321,
n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331,
n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341,
n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351,
n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361,
n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371,
n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381,
n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391,
n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401,
n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411,
n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421,
n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431,
n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441,
n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451,
n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461,
n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471,
n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481,
n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491,
n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501,
n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511,
n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521,
n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531,
n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541,
n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551,
n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561,
n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571,
n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581,
n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591,
n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601,
n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611,
n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621,
n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631,
n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641,
n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651,
n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661,
n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671,
n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681,
n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691,
n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701,
n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711,
n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721,
n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731,
n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741,
n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751,
n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761,
n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771,
n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781,
n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791,
n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801,
n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811,
n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821,
n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831,
n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841,
n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851,
n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861,
n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871,
n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881,
n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891,
n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901,
n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911,
n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921,
n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931,
n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941,
n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951,
n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961,
n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971,
n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981,
n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991,
n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001,
n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011,
n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021,
n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031,
n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041,
n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051,
n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061,
n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071,
n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081,
n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091,
n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101,
n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111,
n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121,
n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131,
n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141,
n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151,
n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161,
n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171,
n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181,
n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191,
n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201,
n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211,
n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221,
n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231,
n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241,
n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251,
n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261,
n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271,
n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281,
n4282, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292,
n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302,
n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312,
n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322,
n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332,
n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342,
n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352,
n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362,
n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372,
n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382,
n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392,
n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402,
n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412,
n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422,
n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432,
n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562,
n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572,
n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582,
n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592,
n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602,
n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612,
n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622,
n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632,
n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642,
n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652,
n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662,
n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672,
n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682,
n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692,
n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702,
n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712,
n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722,
n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732,
n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742,
n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752,
n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762,
n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772,
n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782,
n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792,
n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802,
n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812,
n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892,
n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902,
n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912,
n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922,
n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932,
n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942,
n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952,
n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962,
n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972,
n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982,
n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992,
n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002,
n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012,
n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022,
n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032,
n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042,
n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052,
n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062,
n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072,
n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082,
n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092,
n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102,
n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112,
n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122,
n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132,
n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142,
n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152,
n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162,
n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172,
n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182,
n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192,
n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202,
n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212,
n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222,
n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232,
n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242,
n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252,
n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262,
n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272,
n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282,
n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292,
n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302,
n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312,
n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322,
n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332,
n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412,
n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422,
n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432,
n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442,
n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452,
n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462,
n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472,
n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482,
n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522,
n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532,
n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542,
n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552,
n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562,
n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572,
n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582,
n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592,
n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602,
n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612,
n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622,
n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632,
n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642,
n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652,
n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662,
n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672,
n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682,
n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692,
n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702,
n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712,
n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722,
n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732,
n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742,
n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752,
n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762,
n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772,
n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782,
n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792,
n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802,
n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812,
n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822,
n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832,
n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842,
n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852,
n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862,
n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872,
n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882,
n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892,
n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902,
n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912,
n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922,
n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932,
n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942,
n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952,
n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962,
n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972,
n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982,
n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992,
n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002,
n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012,
n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022,
n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032,
n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042,
n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052,
n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062,
n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, n6072,
n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081, n6082,
n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091, n6092,
n6093, n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, n6102,
n6103, n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, n6112,
n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, n6122,
n6123, n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, n6132,
n6133, n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, n6142,
n6143, n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, n6152,
n6153, n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, n6162,
n6163, n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, n6172,
n6173, n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, n6182,
n6183, n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, n6192,
n6193, n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, n6202,
n6203, n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, n6212,
n6213, n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, n6222,
n6223, n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, n6232,
n6233, n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, n6242,
n6243, n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, n6252,
n6253, n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, n6262,
n6263, n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, n6272,
n6273, n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, n6282,
n6283, n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, n6292,
n6293, n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, n6302,
n6303, n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, n6312,
n6313, n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, n6322,
n6323, n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, n6332,
n6333, n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, n6342,
n6343, n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, n6352,
n6353, n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, n6362,
n6363, n6364, n6365, n6366, n6367, n6368, n6369, n6370, n6371, n6372,
n6373, n6374, n6375, n6376, n6377, n6378, n6379, n6380, n6381, n6382,
n6383, n6384, n6385, n6386, n6387, n6388, n6389, n6390, n6391, n6392,
n6393, n6394, n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402,
n6403, n6404, n6405, n6406, n6407, n6408, n6409, n6410, n6411, n6412,
n6413, n6414, n6415, n6416, n6417, n6418, n6419, n6420, n6421, n6422,
n6423, n6424, n6425, n6426, n6427, n6428, n6429, n6430, n6431, n6432,
n6433, n6434, n6435, n6436, n6437, n6438, n6439, n6440, n6441, n6442,
n6443, n6444, n6445, n6446, n6447, n6448, n6449, n6450, n6451, n6452,
n6453, n6454, n6455, n6456, n6457, n6458, n6459, n6460, n6461, n6462,
n6463, n6464, n6465, n6466, n6467, n6468, n6469, n6470, n6471, n6472,
n6473, n6474, n6475, n6476, n6477, n6478, n6479, n6480, n6481, n6482,
n6483, n6484, n6485, n6486, n6487, n6488, n6489, n6490, n6491, n6492,
n6493, n6494, n6495, n6496, n6497, n6498, n6499, n6500, n6501, n6502,
n6503, n6504, n6505, n6506, n6507, n6508, n6509, n6510, n6511, n6512,
n6513, n6514, n6515, n6516, n6517, n6518, n6519, n6520, n6521, n6522,
n6523, n6524, n6525, n6526, n6527, n6528, n6529, n6530, n6531, n6532,
n6533, n6534, n6535, n6536, n6537, n6538, n6539, n6540, n6541, n6542,
n6543, n6544, n6545, n6546, n6547, n6548, n6549, n6550, n6551, n6552,
n6553, n6554, n6555, n6556, n6557, n6558, n6559, n6560, n6561, n6562,
n6563, n6564, n6565, n6566, n6567, n6568, n6569, n6570, n6572, n6573,
n6574, n6575, n6576, n6579, n6580, n6581, n6582, n6583, n6584, n6585,
n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595,
n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605,
n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615,
n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625,
n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635,
n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645,
n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655,
n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665,
n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675,
n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685,
n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695,
n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705,
n6706, n6707, n6708, n6709, n6710, n6711, n6713, n6714, n6715, n6716,
n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725, n6726,
n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735, n6736,
n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6746, n6747,
n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755, n6756, n6757,
n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765, n6766, n6767,
n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775, n6776, n6777,
n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785, n6786, n6787,
n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795, n6796, n6797,
n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805, n6806, n6807,
n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815, n6816, n6817,
n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825, n6826, n6827,
n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835, n6836, n6837,
n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845, n6846, n6847,
n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855, n6856, n6857,
n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865, n6866, n6867,
n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875, n6876, n6877,
n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885, n6886, n6887,
n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895, n6896, n6897,
n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905, n6906, n6907,
n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915, n6916, n6917,
n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925, n6926, n6927,
n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935, n6936, n6937,
n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945, n6946, n6947,
n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955, n6956, n6957,
n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965, n6966, n6967,
n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975, n6976, n6977,
n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985, n6986, n6987,
n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995, n6996, n6997,
n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005, n7006, n7007,
n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015, n7016, n7017,
n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025, n7026, n7027,
n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035, n7036, n7037,
n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045, n7046, n7047,
n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055, n7056, n7057,
n7058, n7059, n7060, n7062, n7063, n7064, n7065, n7066, n7067, n7068,
n7069, n7070, n7071, n7072, n7073, n7074, n7075, n7076;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:4] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:3] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:2] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [35:0] FPMULT_P_Sgf;
wire [25:0] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:0] FPMULT_Sgf_operation_Result;
wire [5:0] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
wire [13:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle;
wire [11:6] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [15:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle;
wire [13:1] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [10:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [13:0] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle;
wire [11:5] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n7027), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n7027), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n7041), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n7026), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n7026), .Q(
dataB[31]) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2141), .CK(clk), .RN(n7025),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n2468) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2139), .CK(clk), .RN(n7025),
.Q(FPSENCOS_cont_iter_out[2]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2147), .CK(clk), .RN(
n6959), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n6852) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2145), .CK(clk), .RN(
n6997), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2142), .CK(clk), .RN(
n4492), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n6849) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n7024),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2132), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[1]), .QN(n6900) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2130), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n6901) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2126), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[7]), .QN(n6902) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2125), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2123), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2121), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2120), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n6903) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2119), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2117), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2115), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2114), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[26]), .QN(n6899) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2113), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1853), .CK(clk), .RN(n7022),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1852), .CK(clk), .RN(n7022),
.QN(n2415) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1851), .CK(clk), .RN(n7022),
.QN(n2441) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1850), .CK(clk), .RN(n7022),
.QN(n2445) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1849), .CK(clk), .RN(n7022),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1848), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1847), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1846), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1951), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1950), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1949), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1948), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1947), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1946), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1945), .CK(clk), .RN(n7021),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1944), .CK(clk), .RN(n7020),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2112), .CK(clk), .RN(n7026), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2111), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2110), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2109), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2108), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2107), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2106), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2105), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2104), .CK(clk), .RN(n7040), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2103), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2102), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2101), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2100), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2099), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2098), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2097), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2096), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2095), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2094), .CK(clk), .RN(n7039), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2093), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2092), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2091), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2090), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2089), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2088), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2087), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2086), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2085), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2084), .CK(clk), .RN(n7038), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2083), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2082), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2081), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1741), .CK(clk), .RN(
n7037), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n7036), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1740), .CK(clk), .RN(
n7036), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1781), .CK(clk), .RN(n7036), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1739), .CK(clk), .RN(
n7036), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1738), .CK(clk), .RN(
n7035), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1775), .CK(clk), .RN(n7034), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n7034), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1737), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1772), .CK(clk), .RN(n7034), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n7033), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1736), .CK(clk), .RN(
n7033), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1769), .CK(clk), .RN(n7033), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n7033), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1735), .CK(clk), .RN(
n7033), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1765), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1734), .CK(clk), .RN(
n7032), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1788), .CK(clk), .RN(n6961),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n7031), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1742), .CK(clk), .RN(
n7031), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1862), .CK(clk), .RN(n7031),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1960), .CK(clk), .RN(n7031),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n7030), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1749), .CK(clk), .RN(
n7030), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1876), .CK(clk), .RN(n7030),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1975), .CK(clk), .RN(
n7030), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1974), .CK(clk), .RN(n7030),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n7030), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1746), .CK(clk), .RN(
n7030), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1870), .CK(clk), .RN(n7029),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1969), .CK(clk), .RN(
n7029), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1968), .CK(clk), .RN(n7029),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1789), .CK(clk), .RN(n6962),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n7029), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1743), .CK(clk), .RN(
n7029), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1963), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1962), .CK(clk), .RN(n7040),
.Q(FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n2391), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1745), .CK(clk), .RN(
n2392), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1868), .CK(clk), .RN(n2393),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2015), .CK(clk), .RN(n2391), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1967), .CK(clk), .RN(
n7041), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1966), .CK(clk), .RN(n7041),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1790), .CK(clk), .RN(n6962),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n7041), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1744), .CK(clk), .RN(
n7009), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1866), .CK(clk), .RN(n7009),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2012), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1965), .CK(clk), .RN(
n7009), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1964), .CK(clk), .RN(n7009),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1747), .CK(clk), .RN(
n7009), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1872), .CK(clk), .RN(n7008),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2021), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1971), .CK(clk), .RN(
n7008), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1970), .CK(clk), .RN(n7008),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1760), .CK(clk), .RN(
n7008), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1898), .CK(clk), .RN(n7008),
.QN(n2435) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1997), .CK(clk), .RN(
n7007), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1996), .CK(clk), .RN(n7007),
.Q(FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1758), .CK(clk), .RN(
n7007), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1894), .CK(clk), .RN(n7007),
.QN(n2439) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1992), .CK(clk), .RN(n7006),
.Q(FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1751), .CK(clk), .RN(
n7006), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1880), .CK(clk), .RN(n7006),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1978), .CK(clk), .RN(n7006),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1748), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1874), .CK(clk), .RN(n7005),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1972), .CK(clk), .RN(n7005),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1756), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1890), .CK(clk), .RN(n7004),
.QN(n2419) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1989), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1988), .CK(clk), .RN(n7004),
.Q(FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1753), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1884), .CK(clk), .RN(n7003),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1983), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1982), .CK(clk), .RN(n7003),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1750), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1878), .CK(clk), .RN(n7003),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2030), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1977), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1976), .CK(clk), .RN(n7002),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1754), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1886), .CK(clk), .RN(n7002),
.QN(n2446) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1984), .CK(clk), .RN(n7002),
.Q(FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1752), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1882), .CK(clk), .RN(n7001),
.QN(n2453) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2036), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1981), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1980), .CK(clk), .RN(n7001),
.Q(FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1909), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1844), .CK(clk), .RN(n7000),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1943), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1942), .CK(clk), .RN(n7000),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2079), .CK(clk), .RN(
n6966), .Q(FPADDSUB_bit_shift_SHT2) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1761), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1900), .CK(clk), .RN(n6999),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2063), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n1999), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1998), .CK(clk), .RN(n6999),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1723), .CK(clk), .RN(n6999),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1762), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1902), .CK(clk), .RN(n7020),
.QN(n2282) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2001), .CK(clk), .RN(
n7020), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2000), .CK(clk), .RN(n7020),
.Q(FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1724), .CK(clk), .RN(n7020),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n7020), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1757), .CK(clk), .RN(
n7020), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1892), .CK(clk), .RN(n7013),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2051), .CK(clk), .RN(n7042), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1991), .CK(clk), .RN(
n7013), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1990), .CK(clk), .RN(n7019),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1719), .CK(clk), .RN(n7013),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n4493), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1764), .CK(clk), .RN(
n7014), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1906), .CK(clk), .RN(n7018),
.QN(n2281) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2005), .CK(clk), .RN(
n7018), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2004), .CK(clk), .RN(n7018),
.Q(FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1726), .CK(clk), .RN(n7018),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n7018), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1763), .CK(clk), .RN(
n7018), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1904), .CK(clk), .RN(n7018),
.QN(n2428) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2069), .CK(clk), .RN(n7017), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2003), .CK(clk), .RN(
n7017), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2002), .CK(clk), .RN(n7017),
.Q(FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n7017), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1755), .CK(clk), .RN(
n7017), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1888), .CK(clk), .RN(n7017),
.QN(n2436) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1987), .CK(clk), .RN(
n7016), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1986), .CK(clk), .RN(n7016),
.Q(FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1717), .CK(clk), .RN(n7016),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n7016), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1759), .CK(clk), .RN(
n7016), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1896), .CK(clk), .RN(n7016),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2057), .CK(clk), .RN(n7016), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1995), .CK(clk), .RN(
n7016), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1994), .CK(clk), .RN(n7015),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1721), .CK(clk), .RN(n7015),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1695), .CK(clk), .RN(n7015),
.Q(cordic_result[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1716), .CK(clk), .RN(n7015),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1715), .CK(clk), .RN(n7015),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1718), .CK(clk), .RN(n7015),
.Q(cordic_result[8]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1787), .CK(clk), .RN(n6984),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1624), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MY[31]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1677), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[19]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1671), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[13]), .QN(n2469) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1667), .CK(clk),
.RN(n7056), .Q(DP_OP_501J223_127_5235_n944), .QN(n6754) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1659), .CK(clk),
.RN(n7056), .Q(n2481), .QN(n2482) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1657), .CK(clk),
.RN(n7055), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1598), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[22]), .QN(n2400) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1645), .CK(clk),
.RN(n7051), .Q(n6753), .QN(n6771) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1639), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MY[13]), .QN(n2483) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1632), .CK(clk),
.RN(n7058), .Q(DP_OP_501J223_127_5235_n903), .QN(n6765) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1630), .CK(clk),
.RN(n7051), .Q(FPMULT_Op_MY[4]), .QN(n2488) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1627), .CK(clk),
.RN(n7052), .Q(n2220), .QN(n2477) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1625), .CK(
clk), .RN(n4494), .Q(FPMULT_zero_flag), .QN(n6904) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1551), .CK(clk),
.RN(n4493), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1540), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[11]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1537), .CK(clk),
.RN(n4495), .Q(FPMULT_P_Sgf[8]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1536), .CK(clk),
.RN(n4495), .Q(FPMULT_P_Sgf[7]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1535), .CK(clk),
.RN(n7013), .Q(FPMULT_P_Sgf[6]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1531), .CK(clk),
.RN(n7042), .Q(FPMULT_P_Sgf[2]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1529), .CK(clk),
.RN(n4493), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1621), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1576), .CK(clk), .RN(n7048), .Q(mult_result[31]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1584), .CK(clk), .RN(n7052), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1583), .CK(clk), .RN(n7058), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1582), .CK(clk), .RN(n7045), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1581), .CK(clk), .RN(n7045), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1580), .CK(clk), .RN(n7045), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1579), .CK(clk), .RN(n7045), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1578), .CK(clk), .RN(n7045), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1577), .CK(clk), .RN(n7045), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1504), .CK(clk), .RN(n7045), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1503), .CK(clk), .RN(n7045), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1502), .CK(clk), .RN(n7045), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1501), .CK(clk), .RN(n7045), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1500), .CK(clk), .RN(n7044), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1499), .CK(clk), .RN(n7044), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1498), .CK(clk), .RN(n7044), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1497), .CK(clk), .RN(n7044), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1496), .CK(clk), .RN(n7044), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1495), .CK(clk), .RN(n7044), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1494), .CK(clk), .RN(n7044), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1493), .CK(clk), .RN(n7044), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1492), .CK(clk), .RN(n7044), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1491), .CK(clk), .RN(n7044), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1490), .CK(clk), .RN(n7043), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1489), .CK(clk), .RN(n7043), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1488), .CK(clk), .RN(n7043), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1487), .CK(clk), .RN(n7043), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1486), .CK(clk), .RN(n7043), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1485), .CK(clk), .RN(n7043), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1484), .CK(clk), .RN(n7043), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1483), .CK(clk), .RN(n7043), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1481), .CK(clk), .RN(n7043), .Q(mult_result[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1478), .CK(clk), .RN(
n6969), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1477), .CK(clk), .RN(
n6969), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1475), .CK(clk), .RN(
n6969), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1474), .CK(clk), .RN(
n6969), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(
n6988), .Q(result_add_subt[23]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1472), .CK(clk), .RN(
n6988), .Q(result_add_subt[24]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1471), .CK(clk), .RN(
n6988), .Q(result_add_subt[25]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1470), .CK(clk), .RN(
n6988), .Q(result_add_subt[26]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1469), .CK(clk), .RN(
n6989), .Q(result_add_subt[27]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1468), .CK(clk), .RN(
n6989), .Q(result_add_subt[28]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1467), .CK(clk), .RN(
n6989), .Q(result_add_subt[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1460), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1459), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1458), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1456), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1455), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1454), .CK(clk), .RN(
n6997), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1451), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1450), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1449), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1444), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1440), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1439), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1436), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1435), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1434), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n6971),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1431), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1430), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1429), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1426), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1425), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1424), .CK(clk), .RN(
n4492), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1421), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1420), .CK(clk), .RN(n6972),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1419), .CK(clk), .RN(
n4490), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1412), .CK(clk), .RN(n6973), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1411), .CK(clk), .RN(n6989), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1409), .CK(clk), .RN(
n6989), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n6973), .Q(result_add_subt[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1407), .CK(clk), .RN(n6973),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1406), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n6973), .Q(result_add_subt[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1404), .CK(clk), .RN(n6973),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1403), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n6973), .Q(result_add_subt[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1401), .CK(clk), .RN(n6973),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1400), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n6974), .Q(result_add_subt[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1398), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1397), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n6974), .Q(result_add_subt[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1395), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1394), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n6974), .Q(result_add_subt[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1392), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1391), .CK(clk), .RN(
n6985), .QN(n6854) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n6974), .Q(result_add_subt[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1389), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1388), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1386), .CK(clk), .RN(n6974),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1385), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1383), .CK(clk), .RN(n6975),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1382), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n6975), .Q(result_add_subt[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1380), .CK(clk), .RN(n6975),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1379), .CK(clk), .RN(
n6975), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n6975), .Q(result_add_subt[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1377), .CK(clk), .RN(n6975),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1376), .CK(clk), .RN(
n6985), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n6975), .Q(result_add_subt[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1374), .CK(clk), .RN(n6975),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1373), .CK(clk), .RN(
n6975), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n6976), .Q(result_add_subt[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1371), .CK(clk), .RN(n6976),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1370), .CK(clk), .RN(
n6976), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1368), .CK(clk), .RN(n6976),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1367), .CK(clk), .RN(
n6976), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1365), .CK(clk), .RN(n6976),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1364), .CK(clk), .RN(
n6976), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n6977),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n6977), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1360), .CK(clk), .RN(n6977), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1359), .CK(clk), .RN(n6977),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1358), .CK(clk), .RN(n6977),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(
n6984), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1356), .CK(clk), .RN(
n6977), .Q(result_add_subt[31]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n6977),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n6977), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1353), .CK(clk), .RN(n6977), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1330), .CK(clk), .RN(
n6997), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(
n6984), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n6914), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(
n6989), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1318), .CK(clk), .RN(
n6989), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(
n6984), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n6913), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n6978),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(
n6978), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n6912), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(
n6984), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n6911), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(
n6984), .QN(n6855) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n6979),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n6910), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(
n6980), .QN(n6814) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1280), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(
n6980), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n6980),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n6909), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(
n6981), .QN(n6815) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1267), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1263), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1259), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n6981),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1255), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1251), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1247), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1243), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n6908), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n6982),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n6907), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1231), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1227), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1223), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1219), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n6983),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1215), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n6984),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n6984),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n6984),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n6984),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1207), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1180), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n6867) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7067), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_14_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_15_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15])
);
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n2493), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6905), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13])
);
CMPR32X2TS DP_OP_234J223_132_4955_U6 ( .A(DP_OP_234J223_132_4955_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J223_132_4955_n6), .CO(
DP_OP_234J223_132_4955_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J223_132_4955_U4 ( .A(DP_OP_234J223_132_4955_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J223_132_4955_n4), .CO(
DP_OP_234J223_132_4955_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J223_132_4955_U3 ( .A(DP_OP_234J223_132_4955_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J223_132_4955_n3), .CO(
DP_OP_234J223_132_4955_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS intadd_512_U9 ( .A(intadd_512_A_0_), .B(intadd_512_B_0_), .C(
intadd_512_CI), .CO(intadd_512_n8), .S(intadd_512_SUM_0_) );
CMPR32X2TS intadd_512_U8 ( .A(intadd_512_A_1_), .B(intadd_512_B_1_), .C(
intadd_512_n8), .CO(intadd_512_n7), .S(intadd_512_SUM_1_) );
CMPR32X2TS intadd_512_U7 ( .A(intadd_512_A_2_), .B(intadd_512_B_2_), .C(
intadd_512_n7), .CO(intadd_512_n6), .S(intadd_512_SUM_2_) );
CMPR32X2TS intadd_512_U6 ( .A(intadd_512_A_3_), .B(intadd_512_B_3_), .C(
intadd_512_n6), .CO(intadd_512_n5), .S(intadd_512_SUM_3_) );
CMPR32X2TS intadd_512_U4 ( .A(intadd_512_A_5_), .B(intadd_512_B_5_), .C(
intadd_512_n4), .CO(intadd_512_n3), .S(intadd_512_SUM_5_) );
CMPR32X2TS intadd_512_U2 ( .A(intadd_512_A_7_), .B(intadd_512_B_7_), .C(
intadd_512_n2), .CO(intadd_512_n1), .S(intadd_512_SUM_7_) );
CMPR32X2TS intadd_513_U9 ( .A(intadd_513_A_0_), .B(intadd_513_B_0_), .C(
intadd_513_CI), .CO(intadd_513_n8), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_513_U8 ( .A(mult_x_311_n37), .B(intadd_513_B_1_), .C(
intadd_513_n8), .CO(intadd_513_n7), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_513_U6 ( .A(mult_x_311_n29), .B(mult_x_311_n23), .C(
intadd_513_n6), .CO(intadd_513_n5), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_513_U5 ( .A(mult_x_311_n22), .B(mult_x_311_n18), .C(
intadd_513_n5), .CO(intadd_513_n4), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_513_U4 ( .A(mult_x_311_n17), .B(mult_x_311_n15), .C(
intadd_513_n4), .CO(intadd_513_n3), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_513_U3 ( .A(mult_x_311_n14), .B(intadd_513_B_6_), .C(
intadd_513_n3), .CO(intadd_513_n2), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_513_U2 ( .A(intadd_513_A_7_), .B(intadd_513_B_7_), .C(
intadd_513_n2), .CO(intadd_513_n1), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_514_U9 ( .A(intadd_514_A_0_), .B(intadd_514_B_0_), .C(
intadd_514_CI), .CO(intadd_514_n8), .S(intadd_514_SUM_0_) );
CMPR32X2TS intadd_514_U8 ( .A(intadd_514_A_1_), .B(intadd_514_B_1_), .C(
intadd_514_n8), .CO(intadd_514_n7), .S(intadd_514_SUM_1_) );
CMPR32X2TS intadd_514_U7 ( .A(intadd_514_A_2_), .B(intadd_514_B_2_), .C(
intadd_514_n7), .CO(intadd_514_n6), .S(intadd_514_SUM_2_) );
CMPR32X2TS intadd_514_U6 ( .A(intadd_514_A_3_), .B(intadd_514_B_3_), .C(
intadd_514_n6), .CO(intadd_514_n5), .S(intadd_514_SUM_3_) );
CMPR32X2TS intadd_514_U4 ( .A(intadd_514_A_5_), .B(intadd_514_B_5_), .C(
intadd_514_n4), .CO(intadd_514_n3), .S(intadd_514_SUM_5_) );
CMPR32X2TS intadd_514_U2 ( .A(intadd_514_A_7_), .B(intadd_514_B_7_), .C(
intadd_514_n2), .CO(intadd_514_n1), .S(intadd_514_SUM_7_) );
CMPR32X2TS intadd_515_U8 ( .A(intadd_515_A_0_), .B(intadd_515_B_0_), .C(
intadd_515_CI), .CO(intadd_515_n7), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_515_U7 ( .A(mult_x_309_n37), .B(intadd_515_B_1_), .C(
intadd_515_n7), .CO(intadd_515_n6), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_515_U5 ( .A(mult_x_309_n29), .B(mult_x_309_n23), .C(
intadd_515_n5), .CO(intadd_515_n4), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_518_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(intadd_517_B_1_),
.C(intadd_518_n3), .CO(intadd_518_n2), .S(intadd_518_SUM_1_) );
CMPR32X2TS intadd_518_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n6782), .C(
intadd_518_n2), .CO(intadd_518_n1), .S(intadd_518_SUM_2_) );
CMPR42X1TS DP_OP_500J223_126_4510_U122 ( .A(DP_OP_500J223_126_4510_n137),
.B(DP_OP_500J223_126_4510_n180), .C(DP_OP_500J223_126_4510_n134), .D(
DP_OP_500J223_126_4510_n187), .ICI(DP_OP_500J223_126_4510_n131), .S(
DP_OP_500J223_126_4510_n129), .ICO(DP_OP_500J223_126_4510_n127), .CO(
DP_OP_500J223_126_4510_n128) );
CMPR42X1TS DP_OP_500J223_126_4510_U118 ( .A(DP_OP_500J223_126_4510_n124),
.B(DP_OP_500J223_126_4510_n178), .C(DP_OP_500J223_126_4510_n121), .D(
DP_OP_500J223_126_4510_n125), .ICI(DP_OP_500J223_126_4510_n120), .S(
DP_OP_500J223_126_4510_n117), .ICO(DP_OP_500J223_126_4510_n115), .CO(
DP_OP_500J223_126_4510_n116) );
CMPR42X2TS DP_OP_500J223_126_4510_U115 ( .A(DP_OP_500J223_126_4510_n170),
.B(DP_OP_500J223_126_4510_n118), .C(DP_OP_500J223_126_4510_n112), .D(
DP_OP_500J223_126_4510_n119), .ICI(DP_OP_500J223_126_4510_n115), .S(
DP_OP_500J223_126_4510_n110), .ICO(DP_OP_500J223_126_4510_n108), .CO(
DP_OP_500J223_126_4510_n109) );
CMPR42X2TS DP_OP_500J223_126_4510_U113 ( .A(DP_OP_500J223_126_4510_n162),
.B(DP_OP_500J223_126_4510_n155), .C(DP_OP_500J223_126_4510_n107), .D(
DP_OP_500J223_126_4510_n111), .ICI(DP_OP_500J223_126_4510_n108), .S(
DP_OP_500J223_126_4510_n105), .ICO(DP_OP_500J223_126_4510_n103), .CO(
DP_OP_500J223_126_4510_n104) );
CMPR42X2TS DP_OP_500J223_126_4510_U112 ( .A(DP_OP_500J223_126_4510_n161),
.B(DP_OP_500J223_126_4510_n154), .C(DP_OP_500J223_126_4510_n147), .D(
DP_OP_500J223_126_4510_n106), .ICI(DP_OP_500J223_126_4510_n103), .S(
DP_OP_500J223_126_4510_n102), .ICO(DP_OP_500J223_126_4510_n100), .CO(
DP_OP_500J223_126_4510_n101) );
CMPR42X1TS DP_OP_502J223_128_4510_U125 ( .A(DP_OP_502J223_128_4510_n174),
.B(DP_OP_502J223_128_4510_n138), .C(DP_OP_502J223_128_4510_n141), .D(
DP_OP_502J223_128_4510_n181), .ICI(DP_OP_502J223_128_4510_n188), .S(
DP_OP_502J223_128_4510_n136), .ICO(DP_OP_502J223_128_4510_n134), .CO(
DP_OP_502J223_128_4510_n135) );
CMPR42X1TS DP_OP_502J223_128_4510_U121 ( .A(DP_OP_502J223_128_4510_n151),
.B(DP_OP_502J223_128_4510_n158), .C(DP_OP_502J223_128_4510_n132), .D(
DP_OP_502J223_128_4510_n165), .ICI(DP_OP_502J223_128_4510_n130), .S(
DP_OP_502J223_128_4510_n126), .ICO(DP_OP_502J223_128_4510_n124), .CO(
DP_OP_502J223_128_4510_n125) );
CMPR42X1TS DP_OP_502J223_128_4510_U118 ( .A(DP_OP_502J223_128_4510_n178),
.B(DP_OP_502J223_128_4510_n171), .C(DP_OP_502J223_128_4510_n121), .D(
DP_OP_502J223_128_4510_n125), .ICI(DP_OP_502J223_128_4510_n120), .S(
DP_OP_502J223_128_4510_n117), .ICO(DP_OP_502J223_128_4510_n115), .CO(
DP_OP_502J223_128_4510_n116) );
CMPR42X2TS DP_OP_502J223_128_4510_U112 ( .A(DP_OP_502J223_128_4510_n161),
.B(DP_OP_502J223_128_4510_n154), .C(DP_OP_502J223_128_4510_n147), .D(
DP_OP_502J223_128_4510_n106), .ICI(DP_OP_502J223_128_4510_n103), .S(
DP_OP_502J223_128_4510_n102), .ICO(DP_OP_502J223_128_4510_n100), .CO(
DP_OP_502J223_128_4510_n101) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_Result[3]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[5]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_Result[2]) );
DFFRX2TS R_60 ( .D(n2284), .CK(clk), .RN(n2393), .Q(n6917) );
DFFRX2TS R_61 ( .D(n6957), .CK(clk), .RN(n2392), .Q(n6916) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1864), .CK(clk), .RN(n7028),
.QN(n6876) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1954), .CK(clk), .RN(
n7033), .QN(n6838) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1689), .CK(clk), .RN(n7043), .Q(
FPMULT_FSM_selector_A), .QN(n6845) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1691), .CK(clk), .RN(n7012),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n6787) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1622), .CK(clk), .RN(n7049), .Q(
FPMULT_FSM_selector_B[1]), .QN(n6784) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1959), .CK(clk), .RN(
n7037), .QN(n6783) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2138), .CK(clk), .RN(n7025),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n6782) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1350), .CK(clk), .RN(
n6989), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n6766) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2137), .CK(clk), .RN(n7024),
.Q(FPSENCOS_cont_var_out[0]), .QN(n6756) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n7026), .Q(NaN_flag)
);
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1693), .CK(clk), .RN(n7012),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n6790) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1692), .CK(clk), .RN(n7012),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n6757) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[3]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[2]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6870), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]) );
CMPR32X2TS intadd_515_U2 ( .A(mult_x_309_n14), .B(intadd_515_B_6_), .C(
intadd_515_n2), .CO(intadd_515_n1), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_512_U5 ( .A(intadd_512_A_4_), .B(intadd_512_B_4_), .C(
intadd_512_n5), .CO(intadd_512_n4), .S(intadd_512_SUM_4_) );
CMPR32X2TS intadd_512_U3 ( .A(intadd_512_A_6_), .B(intadd_512_B_6_), .C(
intadd_512_n3), .CO(intadd_512_n2), .S(intadd_512_SUM_6_) );
CMPR32X2TS intadd_514_U5 ( .A(intadd_514_A_4_), .B(intadd_514_B_4_), .C(
intadd_514_n5), .CO(intadd_514_n4), .S(intadd_514_SUM_4_) );
CMPR32X2TS intadd_514_U3 ( .A(intadd_514_A_6_), .B(intadd_514_B_6_), .C(
intadd_514_n3), .CO(intadd_514_n2), .S(intadd_514_SUM_6_) );
CMPR32X2TS intadd_513_U7 ( .A(mult_x_311_n36), .B(mult_x_311_n30), .C(
intadd_513_n7), .CO(intadd_513_n6), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_515_U6 ( .A(mult_x_309_n36), .B(mult_x_309_n30), .C(
intadd_515_n6), .CO(intadd_515_n5), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_515_U4 ( .A(mult_x_309_n22), .B(mult_x_309_n18), .C(
intadd_515_n4), .CO(intadd_515_n3), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR42X2TS DP_OP_499J223_125_1651_U242 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
DP_OP_499J223_125_1651_n252), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .D(
DP_OP_499J223_125_1651_n250), .ICI(DP_OP_499J223_125_1651_n281), .S(
DP_OP_499J223_125_1651_n249), .ICO(DP_OP_499J223_125_1651_n247), .CO(
DP_OP_499J223_125_1651_n248) );
CMPR42X2TS DP_OP_499J223_125_1651_U239 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .C(
DP_OP_499J223_125_1651_n241), .D(DP_OP_499J223_125_1651_n278), .ICI(
DP_OP_499J223_125_1651_n302), .S(DP_OP_499J223_125_1651_n240), .ICO(
DP_OP_499J223_125_1651_n238), .CO(DP_OP_499J223_125_1651_n239) );
CMPR42X2TS DP_OP_499J223_125_1651_U238 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .C(
DP_OP_499J223_125_1651_n238), .D(DP_OP_499J223_125_1651_n277), .ICI(
DP_OP_499J223_125_1651_n301), .S(DP_OP_499J223_125_1651_n237), .ICO(
DP_OP_499J223_125_1651_n235), .CO(DP_OP_499J223_125_1651_n236) );
CMPR42X2TS DP_OP_499J223_125_1651_U237 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .C(
DP_OP_499J223_125_1651_n235), .D(DP_OP_499J223_125_1651_n276), .ICI(
DP_OP_499J223_125_1651_n300), .S(DP_OP_499J223_125_1651_n234), .ICO(
DP_OP_499J223_125_1651_n232), .CO(DP_OP_499J223_125_1651_n233) );
CMPR42X2TS DP_OP_499J223_125_1651_U234 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .C(
DP_OP_499J223_125_1651_n273), .D(DP_OP_499J223_125_1651_n297), .ICI(
DP_OP_499J223_125_1651_n226), .S(DP_OP_499J223_125_1651_n225), .ICO(
DP_OP_499J223_125_1651_n223), .CO(DP_OP_499J223_125_1651_n224) );
CMPR42X2TS DP_OP_499J223_125_1651_U233 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .C(
DP_OP_499J223_125_1651_n272), .D(DP_OP_499J223_125_1651_n296), .ICI(
DP_OP_499J223_125_1651_n223), .S(DP_OP_499J223_125_1651_n222), .ICO(
DP_OP_499J223_125_1651_n220), .CO(DP_OP_499J223_125_1651_n221) );
CMPR42X2TS DP_OP_499J223_125_1651_U232 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .C(
DP_OP_499J223_125_1651_n271), .D(DP_OP_499J223_125_1651_n295), .ICI(
DP_OP_499J223_125_1651_n220), .S(DP_OP_499J223_125_1651_n219), .ICO(
DP_OP_499J223_125_1651_n217), .CO(DP_OP_499J223_125_1651_n218) );
CMPR42X2TS DP_OP_499J223_125_1651_U231 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .C(
DP_OP_499J223_125_1651_n270), .D(DP_OP_499J223_125_1651_n294), .ICI(
DP_OP_499J223_125_1651_n217), .S(DP_OP_499J223_125_1651_n216), .ICO(
DP_OP_499J223_125_1651_n214), .CO(DP_OP_499J223_125_1651_n215) );
CMPR42X2TS DP_OP_499J223_125_1651_U230 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .C(
DP_OP_499J223_125_1651_n269), .D(DP_OP_499J223_125_1651_n293), .ICI(
DP_OP_499J223_125_1651_n214), .S(DP_OP_499J223_125_1651_n213), .ICO(
DP_OP_499J223_125_1651_n211), .CO(DP_OP_499J223_125_1651_n212) );
CMPR42X2TS DP_OP_499J223_125_1651_U229 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(
DP_OP_499J223_125_1651_n268), .D(DP_OP_499J223_125_1651_n292), .ICI(
DP_OP_499J223_125_1651_n211), .S(DP_OP_499J223_125_1651_n210), .ICO(
DP_OP_499J223_125_1651_n208), .CO(DP_OP_499J223_125_1651_n209) );
CMPR42X2TS DP_OP_499J223_125_1651_U228 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .C(n2213),
.D(n2264), .ICI(DP_OP_499J223_125_1651_n208), .S(
DP_OP_499J223_125_1651_n207), .ICO(DP_OP_499J223_125_1651_n205), .CO(
DP_OP_499J223_125_1651_n206) );
CMPR42X2TS DP_OP_499J223_125_1651_U227 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_499J223_125_1651_n266), .D(n2265), .ICI(
DP_OP_499J223_125_1651_n205), .S(DP_OP_499J223_125_1651_n204), .ICO(
DP_OP_499J223_125_1651_n202), .CO(DP_OP_499J223_125_1651_n203) );
CMPR42X2TS DP_OP_501J223_127_5235_U432 ( .A(DP_OP_501J223_127_5235_n503),
.B(DP_OP_501J223_127_5235_n509), .C(DP_OP_501J223_127_5235_n473), .D(
DP_OP_501J223_127_5235_n468), .ICI(DP_OP_501J223_127_5235_n467), .S(
DP_OP_501J223_127_5235_n464), .ICO(DP_OP_501J223_127_5235_n462), .CO(
DP_OP_501J223_127_5235_n463) );
CMPR42X2TS DP_OP_501J223_127_5235_U427 ( .A(DP_OP_501J223_127_5235_n495),
.B(DP_OP_501J223_127_5235_n460), .C(DP_OP_501J223_127_5235_n454), .D(
DP_OP_501J223_127_5235_n458), .ICI(DP_OP_501J223_127_5235_n455), .S(
DP_OP_501J223_127_5235_n452), .ICO(DP_OP_501J223_127_5235_n450), .CO(
DP_OP_501J223_127_5235_n451) );
CMPR42X2TS DP_OP_501J223_127_5235_U426 ( .A(DP_OP_501J223_127_5235_n500),
.B(DP_OP_501J223_127_5235_n494), .C(DP_OP_501J223_127_5235_n488), .D(
DP_OP_501J223_127_5235_n453), .ICI(DP_OP_501J223_127_5235_n450), .S(
DP_OP_501J223_127_5235_n449), .ICO(DP_OP_501J223_127_5235_n447), .CO(
DP_OP_501J223_127_5235_n448) );
CMPR42X2TS DP_OP_501J223_127_5235_U159 ( .A(DP_OP_501J223_127_5235_n190),
.B(DP_OP_501J223_127_5235_n247), .C(DP_OP_501J223_127_5235_n193), .D(
DP_OP_501J223_127_5235_n263), .ICI(DP_OP_501J223_127_5235_n191), .S(
DP_OP_501J223_127_5235_n188), .ICO(DP_OP_501J223_127_5235_n186), .CO(
DP_OP_501J223_127_5235_n187) );
CMPR42X2TS DP_OP_501J223_127_5235_U156 ( .A(DP_OP_501J223_127_5235_n262),
.B(DP_OP_501J223_127_5235_n186), .C(DP_OP_501J223_127_5235_n246), .D(
DP_OP_501J223_127_5235_n254), .ICI(DP_OP_501J223_127_5235_n183), .S(
DP_OP_501J223_127_5235_n181), .ICO(DP_OP_501J223_127_5235_n179), .CO(
DP_OP_501J223_127_5235_n180) );
CMPR42X2TS DP_OP_501J223_127_5235_U153 ( .A(DP_OP_501J223_127_5235_n245),
.B(DP_OP_501J223_127_5235_n182), .C(DP_OP_501J223_127_5235_n261), .D(
DP_OP_501J223_127_5235_n179), .ICI(DP_OP_501J223_127_5235_n176), .S(
DP_OP_501J223_127_5235_n173), .ICO(DP_OP_501J223_127_5235_n171), .CO(
DP_OP_501J223_127_5235_n172) );
CMPR42X2TS DP_OP_501J223_127_5235_U150 ( .A(DP_OP_501J223_127_5235_n174),
.B(DP_OP_501J223_127_5235_n236), .C(DP_OP_501J223_127_5235_n244), .D(
DP_OP_501J223_127_5235_n168), .ICI(DP_OP_501J223_127_5235_n252), .S(
DP_OP_501J223_127_5235_n166), .ICO(DP_OP_501J223_127_5235_n164), .CO(
DP_OP_501J223_127_5235_n165) );
CMPR42X2TS DP_OP_501J223_127_5235_U149 ( .A(DP_OP_501J223_127_5235_n228),
.B(DP_OP_501J223_127_5235_n171), .C(DP_OP_501J223_127_5235_n260), .D(
DP_OP_501J223_127_5235_n175), .ICI(DP_OP_501J223_127_5235_n166), .S(
DP_OP_501J223_127_5235_n163), .ICO(DP_OP_501J223_127_5235_n161), .CO(
DP_OP_501J223_127_5235_n162) );
CMPR42X2TS DP_OP_501J223_127_5235_U147 ( .A(DP_OP_501J223_127_5235_n167),
.B(DP_OP_501J223_127_5235_n235), .C(DP_OP_501J223_127_5235_n259), .D(
DP_OP_501J223_127_5235_n164), .ICI(DP_OP_501J223_127_5235_n243), .S(
DP_OP_501J223_127_5235_n157), .ICO(DP_OP_501J223_127_5235_n155), .CO(
DP_OP_501J223_127_5235_n156) );
CMPR42X2TS DP_OP_501J223_127_5235_U143 ( .A(DP_OP_501J223_127_5235_n151),
.B(DP_OP_501J223_127_5235_n250), .C(DP_OP_501J223_127_5235_n234), .D(
DP_OP_501J223_127_5235_n242), .ICI(DP_OP_501J223_127_5235_n159), .S(
DP_OP_501J223_127_5235_n147), .ICO(DP_OP_501J223_127_5235_n145), .CO(
DP_OP_501J223_127_5235_n146) );
CMPR42X2TS DP_OP_501J223_127_5235_U142 ( .A(DP_OP_501J223_127_5235_n149),
.B(DP_OP_501J223_127_5235_n155), .C(DP_OP_501J223_127_5235_n156), .D(
DP_OP_501J223_127_5235_n152), .ICI(DP_OP_501J223_127_5235_n147), .S(
DP_OP_501J223_127_5235_n144), .ICO(DP_OP_501J223_127_5235_n142), .CO(
DP_OP_501J223_127_5235_n143) );
CMPR42X2TS DP_OP_501J223_127_5235_U140 ( .A(DP_OP_501J223_127_5235_n150),
.B(DP_OP_501J223_127_5235_n241), .C(DP_OP_501J223_127_5235_n141), .D(
DP_OP_501J223_127_5235_n225), .ICI(DP_OP_501J223_127_5235_n145), .S(
DP_OP_501J223_127_5235_n139), .ICO(DP_OP_501J223_127_5235_n137), .CO(
DP_OP_501J223_127_5235_n138) );
CMPR42X2TS DP_OP_501J223_127_5235_U139 ( .A(DP_OP_501J223_127_5235_n233),
.B(DP_OP_501J223_127_5235_n148), .C(DP_OP_501J223_127_5235_n146), .D(
DP_OP_501J223_127_5235_n139), .ICI(DP_OP_501J223_127_5235_n142), .S(
DP_OP_501J223_127_5235_n136), .ICO(DP_OP_501J223_127_5235_n134), .CO(
DP_OP_501J223_127_5235_n135) );
CMPR42X2TS DP_OP_501J223_127_5235_U138 ( .A(DP_OP_501J223_127_5235_n200),
.B(DP_OP_501J223_127_5235_n208), .C(DP_OP_501J223_127_5235_n232), .D(
DP_OP_501J223_127_5235_n140), .ICI(DP_OP_501J223_127_5235_n216), .S(
DP_OP_501J223_127_5235_n133), .ICO(DP_OP_501J223_127_5235_n131), .CO(
DP_OP_501J223_127_5235_n132) );
CMPR42X2TS DP_OP_501J223_127_5235_U137 ( .A(DP_OP_501J223_127_5235_n224),
.B(DP_OP_501J223_127_5235_n137), .C(DP_OP_501J223_127_5235_n138), .D(
DP_OP_501J223_127_5235_n133), .ICI(DP_OP_501J223_127_5235_n134), .S(
DP_OP_501J223_127_5235_n130), .ICO(DP_OP_501J223_127_5235_n128), .CO(
DP_OP_501J223_127_5235_n129) );
CMPR42X2TS DP_OP_501J223_127_5235_U135 ( .A(DP_OP_501J223_127_5235_n207),
.B(DP_OP_501J223_127_5235_n131), .C(DP_OP_501J223_127_5235_n127), .D(
DP_OP_501J223_127_5235_n132), .ICI(DP_OP_501J223_127_5235_n128), .S(
DP_OP_501J223_127_5235_n125), .ICO(DP_OP_501J223_127_5235_n123), .CO(
DP_OP_501J223_127_5235_n124) );
CMPR42X2TS DP_OP_501J223_127_5235_U134 ( .A(DP_OP_501J223_127_5235_n214),
.B(DP_OP_501J223_127_5235_n198), .C(DP_OP_501J223_127_5235_n206), .D(
DP_OP_501J223_127_5235_n126), .ICI(DP_OP_501J223_127_5235_n123), .S(
DP_OP_501J223_127_5235_n122), .ICO(DP_OP_501J223_127_5235_n120), .CO(
DP_OP_501J223_127_5235_n121) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1832), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n6748) );
DFFRXLTS R_41 ( .D(n1694), .CK(clk), .RN(n2365), .Q(n6926) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1333), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n6800) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1279), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1250), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1300), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1272), .CK(clk), .RN(n6994),
.Q(FPADDSUB_DMP_SFG[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1234), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1323), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1307), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1286), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[1]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1293), .CK(clk), .RN(n6993),
.Q(FPADDSUB_DMP_SFG[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1336), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1334), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1337), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1315), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1410), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1658), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[0]), .QN(n2221) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n7040), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8])
);
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_513_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9])
);
DFFRXLTS R_23 ( .D(n1567), .CK(clk), .RN(n2392), .Q(n6938) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1608), .CK(clk),
.RN(n7054), .Q(FPMULT_Add_result[12]), .QN(n6886) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1958), .CK(clk), .RN(
n7036), .Q(FPSENCOS_d_ff2_X[24]), .QN(n6873) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1513), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n6759) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1676), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[18]), .QN(n2491) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1678), .CK(clk),
.RN(n7050), .Q(FPMULT_Op_MX[20]), .QN(n2478) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1838), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1836), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDY_EWSW[7]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2075), .CK(clk), .RN(
n6966), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2263) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1827), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1816), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1834), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1340), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1823), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n2459) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1824), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n2410) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1830), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n2467) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1815), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1831), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n2455) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1821), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n2409) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2076), .CK(clk), .RN(
n6966), .Q(FPADDSUB_shift_value_SHT2_EWR[3]), .QN(n6785) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1807), .CK(clk), .RN(n6962), .Q(FPADDSUB_Data_array_SWR[20]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1808), .CK(clk), .RN(n6961), .Q(FPADDSUB_Data_array_SWR[21]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1809), .CK(clk), .RN(n6967), .Q(FPADDSUB_Data_array_SWR[22]) );
DFFRX2TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n7060), .CK(clk), .RN(n6959), .Q(
ready_add_subt) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1262), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[11]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1505), .CK(
clk), .RN(n7052), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1507), .CK(
clk), .RN(n7048), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1266), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1810), .CK(clk), .RN(n6967), .Q(FPADDSUB_Data_array_SWR[23]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1820), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n2438) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1349), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1835), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n2442) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1210), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1218), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SFG[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1222), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[19]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1230), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[17]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1242), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[13]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1840), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n2397) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1214), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1226), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1258), .CK(clk), .RN(n6995),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1800), .CK(clk), .RN(n6965), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1246), .CK(clk), .RN(n6996),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1206), .CK(clk), .RN(n6997),
.Q(FPADDSUB_DMP_SFG[22]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1466), .CK(clk), .RN(
n6989), .QN(n2451) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2077), .CK(clk), .RN(
n6966), .Q(FPADDSUB_shift_value_SHT2_EWR[2]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1511), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n2399) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n6959),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n6850) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1345), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n6791) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1343), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n6821) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1933), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n2270) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1930), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n2230) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1919), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n2232) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1509), .CK(
clk), .RN(n7050), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n2450) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1929), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n2231) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1921), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n2274) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1916), .CK(clk), .RN(
n6959), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n6811) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1915), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n6804) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1939), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n2273) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1924), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n2432) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1923), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n2272) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1332), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n6758) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2148), .CK(clk), .RN(
n6959), .Q(FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n6829) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1855), .CK(clk), .RN(
n7032), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1857), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1940), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n2434) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1797), .CK(clk), .RN(n6968), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1585), .CK(clk), .RN(
n7050), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1854), .CK(clk), .RN(
n7032), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1861), .CK(clk), .RN(
n7037), .Q(FPSENCOS_d_ff2_Y[23]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1341), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n6795) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1516), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1518), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1520), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1522), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1524), .CK(
clk), .RN(n7046), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1526), .CK(
clk), .RN(n7058), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1428), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1448), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1517), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1519), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1521), .CK(
clk), .RN(n7052), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1523), .CK(
clk), .RN(n7048), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1525), .CK(
clk), .RN(n7050), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1527), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n1556), .CK(clk),
.RN(n7013), .Q(FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n1559), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n1562), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n1564), .CK(clk),
.RN(n4493), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1941), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n2275) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1686), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1858), .CK(clk), .RN(
n7035), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1859), .CK(clk), .RN(
n7035), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1860), .CK(clk), .RN(
n7036), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1198), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n6776) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n6777) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1688), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1934), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n2269) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1793), .CK(clk), .RN(n6963),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n6969),
.Q(FPADDSUB_DMP_EXP_EWSW[26]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1463), .CK(clk), .RN(n6969),
.Q(FPADDSUB_DMP_EXP_EWSW[25]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n6796) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1348), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n6793) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1553), .CK(clk),
.RN(n7012), .Q(FPMULT_P_Sgf[24]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1911), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n6810) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1811), .CK(clk), .RN(n6967), .Q(FPADDSUB_Data_array_SWR[24]), .QN(n6816) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1912), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n6812) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n6999),
.Q(operation_reg[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1344), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n6780) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1794), .CK(clk), .RN(n6964),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1352), .CK(clk), .RN(n6990),
.Q(FPADDSUB_OP_FLAG_SFG) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1791), .CK(clk), .RN(n6969),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1792), .CK(clk), .RN(n6961),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1656), .CK(clk),
.RN(n7053), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1681), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1654), .CK(clk),
.RN(n7053), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1733), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1588), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1590), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1591), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1592), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1593), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1973), .CK(clk), .RN(
n7005), .QN(n2417) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1979), .CK(clk), .RN(
n7006), .QN(n2425) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1993), .CK(clk), .RN(
n7007), .QN(n2422) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1649), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1339), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n6799) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1201), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n6773) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1202), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n6778) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1196), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n6779) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1197), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n6774) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1199), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n6775) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2058), .CK(clk), .RN(n7016), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2046), .CK(clk), .RN(n7017), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2070), .CK(clk), .RN(n7018), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2073), .CK(clk), .RN(n4495), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2052), .CK(clk), .RN(n7020), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2067), .CK(clk), .RN(n6999), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2064), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2037), .CK(clk), .RN(n7001), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2043), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2031), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2040), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2049), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2025), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2034), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2055), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2061), .CK(clk), .RN(n7008), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2022), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2013), .CK(clk), .RN(n7009), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2016), .CK(clk), .RN(n2393), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2010), .CK(clk), .RN(n7029), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2019), .CK(clk), .RN(n7029), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2028), .CK(clk), .RN(n7030), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2007), .CK(clk), .RN(n7031), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1727), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Xn[31]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1770), .CK(clk), .RN(n7033), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1985), .CK(clk), .RN(
n7002), .QN(n2449) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2045), .CK(clk), .RN(n7017), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2072), .CK(clk), .RN(n7018), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2039), .CK(clk), .RN(n7003), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2048), .CK(clk), .RN(n7004), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2060), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2009), .CK(clk), .RN(n7028), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2018), .CK(clk), .RN(n7029), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2027), .CK(clk), .RN(n7030), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2006), .CK(clk), .RN(n7031), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1784), .CK(clk), .RN(n7036), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2078), .CK(clk), .RN(
n6991), .Q(FPADDSUB_left_right_SHT2), .QN(n2235) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1418), .CK(clk), .RN(
n4497), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1548), .CK(clk),
.RN(n7011), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1438), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1423), .CK(clk), .RN(
n4487), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1433), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1443), .CK(clk), .RN(
n6998), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1331), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n2256) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1936), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n2465) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1913), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n2464) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1728), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1453), .CK(clk), .RN(
n6997), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1530), .CK(clk),
.RN(n4493), .Q(FPMULT_P_Sgf[1]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1538), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[9]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1542), .CK(clk),
.RN(n7012), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1713), .CK(clk), .RN(n7015),
.Q(cordic_result[13]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1710), .CK(clk), .RN(n7015),
.Q(cordic_result[16]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1712), .CK(clk), .RN(n7015),
.Q(cordic_result[14]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1714), .CK(clk), .RN(n7015),
.Q(cordic_result[12]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1725), .CK(clk), .RN(n7017),
.Q(cordic_result[1]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1696), .CK(clk), .RN(n7031),
.Q(cordic_result[30]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1697), .CK(clk), .RN(n7032),
.Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1698), .CK(clk), .RN(n7033),
.Q(cordic_result[28]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1699), .CK(clk), .RN(n7033),
.Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1700), .CK(clk), .RN(n7034),
.Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1701), .CK(clk), .RN(n7035),
.Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1702), .CK(clk), .RN(n7036),
.Q(cordic_result[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1703), .CK(clk), .RN(n7036),
.Q(cordic_result[23]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n6974), .Q(result_add_subt[4]), .QN(n2280) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n7026), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n7041), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n4495), .Q(
dataA[29]) );
DFFRX1TS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n7026), .Q(
dataB[29]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2116), .CK(clk), .RN(n7022), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2129), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2131), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2133), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1597), .CK(clk),
.RN(n7053), .Q(FPMULT_Add_result[23]), .QN(n6898) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2118), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2122), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2124), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1596), .CK(clk),
.RN(n7053), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n7026), .Q(
dataB[27]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2128), .CK(clk), .RN(n7024), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1833), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1841), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1822), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n2448) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1829), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n2398) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1843), .CK(clk), .RN(
n6967), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2143), .CK(clk), .RN(
n4486), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n7059) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1918), .CK(clk), .RN(
n6959), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n6805) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1826), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n2460) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1828), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n2461) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1825), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n2466) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1842), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n2433) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1803), .CK(clk), .RN(n6963), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n6964), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1804), .CK(clk), .RN(n6968), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1839), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDY_EWSW[4]), .QN(n6761) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1806), .CK(clk), .RN(n6963), .Q(FPADDSUB_Data_array_SWR[19]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1818), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n2421) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1817), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n2423) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n6439), .CK(clk),
.RN(n7025), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1914), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n2215) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1932), .CK(clk), .RN(
n6968), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n2234) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1814), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n2430) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1347), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]), .QN(n6760) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1927), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n2233) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1928), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n2413) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1796), .CK(clk), .RN(n6965),
.Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1795), .CK(clk), .RN(n6968),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1922), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n2271) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1813), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n2412) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1917), .CK(clk), .RN(
n6959), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n6803) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1937), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n6813) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1798), .CK(clk), .RN(n6965), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1506), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n1563), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n1560), .CK(clk),
.RN(n7042), .Q(FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n1558), .CK(clk),
.RN(n7010), .Q(FPMULT_P_Sgf[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1931), .CK(clk), .RN(
n6965), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n2407) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1464), .CK(clk), .RN(n6969),
.Q(FPADDSUB_DMP_EXP_EWSW[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1685), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1683), .CK(clk),
.RN(n7050), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1812), .CK(clk), .RN(n6967), .Q(FPADDSUB_Data_array_SWR[25]), .QN(n2504) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n1557), .CK(clk),
.RN(n7013), .Q(FPMULT_P_Sgf[28]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1805), .CK(clk), .RN(n6968), .Q(FPADDSUB_Data_array_SWR[18]), .QN(n6842) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2149), .CK(
clk), .RN(n6959), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n6826) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1190), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n6858) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1925), .CK(clk), .RN(
n6964), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n2408) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1193), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n6860) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1192), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n6859) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1682), .CK(clk),
.RN(n7051), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1195), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n6856) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2191), .CK(
clk), .RN(n6959), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n6772) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1655), .CK(clk),
.RN(n7053), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1935), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n2411) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n7028),
.Q(operation_reg[1]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1184), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n6823) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1182), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n6843) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1188), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n6807) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1186), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n6817) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1203), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n6861) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1194), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n6863) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1773), .CK(clk), .RN(n7034), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1767), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1779), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1776), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1785), .CK(clk), .RN(n7037), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1782), .CK(clk), .RN(n7036), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1730), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1729), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n6978), .QN(n6834) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n6980), .QN(n6836) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n6976), .QN(n6831) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n6976), .QN(n6830) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n6980), .QN(n6837) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1544), .CK(clk),
.RN(n2365), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1546), .CK(clk),
.RN(n2365), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1552), .CK(clk),
.RN(n2365), .Q(FPMULT_P_Sgf[23]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n1554), .CK(clk),
.RN(n2365), .Q(FPMULT_P_Sgf[25]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1476), .CK(clk), .RN(
n6969), .QN(n6820) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n7024),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n2266) );
DFFRXLTS R_17 ( .D(n1575), .CK(clk), .RN(n2365), .Q(n6943) );
DFFRXLTS R_19 ( .D(n6956), .CK(clk), .RN(n7010), .Q(n6941) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1720), .CK(clk), .RN(n7011),
.Q(cordic_result[6]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1722), .CK(clk), .RN(n7010),
.Q(cordic_result[4]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1709), .CK(clk), .RN(n4498),
.Q(cordic_result[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1706), .CK(clk), .RN(n4496),
.Q(cordic_result[20]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1707), .CK(clk), .RN(n7011),
.Q(cordic_result[19]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1705), .CK(clk), .RN(n7010),
.Q(cordic_result[21]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1708), .CK(clk), .RN(n2393),
.Q(cordic_result[18]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1711), .CK(clk), .RN(n7041),
.Q(cordic_result[15]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1704), .CK(clk), .RN(n2365),
.Q(cordic_result[22]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1342), .CK(clk), .RN(
n6986), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n6819) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1549), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1547), .CK(clk),
.RN(n4496), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1543), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1532), .CK(clk),
.RN(n7019), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1550), .CK(clk),
.RN(n7013), .Q(FPMULT_P_Sgf[21]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1539), .CK(clk),
.RN(n4498), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1534), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[5]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n7026), .Q(
dataB[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1545), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1541), .CK(clk),
.RN(n7042), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1533), .CK(clk),
.RN(n4495), .Q(FPMULT_P_Sgf[4]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1731), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intAS) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2140), .CK(clk), .RN(n7025),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n6768) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2127), .CK(clk), .RN(n7023), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1620), .CK(clk), .RN(
n7053), .Q(FPMULT_Add_result[0]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n7042), .Q(
dataB[23]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n7027), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n7027), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n7026), .Q(
dataB[26]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1778), .CK(clk), .RN(n7035), .Q(
FPSENCOS_d_ff_Xn[25]), .QN(n2452) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1766), .CK(clk), .RN(n7032), .Q(
FPSENCOS_d_ff_Xn[29]), .QN(n2431) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2054), .CK(clk), .RN(n7007), .Q(
FPSENCOS_d_ff_Xn[6]), .QN(n2440) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2033), .CK(clk), .RN(n7006), .Q(
FPSENCOS_d_ff_Xn[13]), .QN(n2424) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2024), .CK(clk), .RN(n7005), .Q(
FPSENCOS_d_ff_Xn[16]), .QN(n2414) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2042), .CK(clk), .RN(n7002), .Q(
FPSENCOS_d_ff_Xn[10]), .QN(n2447) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2066), .CK(clk), .RN(n7020), .Q(
FPSENCOS_d_ff_Xn[2]), .QN(n2401) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n7027), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n7027), .Q(
dataA[27]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n4495), .Q(
dataB[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1413), .CK(clk), .RN(n6973),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1684), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1687), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n1555), .CK(clk),
.RN(n7014), .Q(FPMULT_P_Sgf[26]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1204), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n6755) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1652), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1594), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1589), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1653), .CK(clk),
.RN(n7053), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n6970),
.Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1651), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1961), .CK(clk), .RN(
n7031), .QN(n2416) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1865), .CK(clk), .RN(
n7029), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1899), .CK(clk), .RN(
n7008), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1895), .CK(clk), .RN(
n7007), .Q(FPSENCOS_d_ff2_Y[6]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1891), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Y[8]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1887), .CK(clk), .RN(
n7002), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1883), .CK(clk), .RN(
n7001), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1903), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1907), .CK(clk), .RN(
n4493), .Q(FPSENCOS_d_ff2_Y[0]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1905), .CK(clk), .RN(
n7018), .Q(FPSENCOS_d_ff2_Y[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1889), .CK(clk), .RN(
n7017), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1863), .CK(clk), .RN(
n7031), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1877), .CK(clk), .RN(
n7030), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1871), .CK(clk), .RN(
n7029), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1869), .CK(clk), .RN(
n2392), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1867), .CK(clk), .RN(
n7009), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1873), .CK(clk), .RN(
n7008), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1881), .CK(clk), .RN(
n7006), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1875), .CK(clk), .RN(
n7005), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1885), .CK(clk), .RN(
n7004), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1879), .CK(clk), .RN(
n7003), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1845), .CK(clk), .RN(
n7000), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1901), .CK(clk), .RN(
n6999), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1893), .CK(clk), .RN(
n7019), .Q(FPSENCOS_d_ff2_Y[7]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1897), .CK(clk), .RN(
n7016), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1191), .CK(clk), .RN(
n6991), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n6862) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1908), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff_Yn[31]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1189), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n6809) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1187), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n6808) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1185), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n6818) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1183), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n6824) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1181), .CK(clk), .RN(
n6992), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n6844) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1650), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1732), .CK(clk), .RN(n7000), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11), .CK(clk), .QN(DP_OP_496J223_122_3236_n147) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1926), .CK(clk), .RN(
n6961), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n2279) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1938), .CK(clk), .RN(
n6966), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n2278) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1920), .CK(clk), .RN(
n6962), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n2277) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n6979), .Q(n2276) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1637), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MY[11]), .QN(n2219) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1635), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MY[9]), .QN(n2225) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1666), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[8]), .QN(n2259) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1679), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MX[21]), .QN(n2255) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1628), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MY[2]), .QN(n2248) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1680), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MX[22]), .QN(n2239) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1669), .CK(clk),
.RN(n7057), .Q(n2403), .QN(n6767) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2146), .CK(clk), .RN(
n6959), .Q(n7077), .QN(n6915) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1647), .CK(clk),
.RN(n7051), .Q(n2228), .QN(n2237) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1648), .CK(clk),
.RN(n7046), .Q(n2223), .QN(n2238) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1638), .CK(clk),
.RN(n7051), .Q(FPMULT_Op_MY[12]), .QN(n2484) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1668), .CK(clk),
.RN(n7057), .Q(n6750), .QN(n6769) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1665), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[7]), .QN(n6794) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1641), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MY[15]), .QN(n2214) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1633), .CK(clk),
.RN(n7052), .Q(n6764), .QN(n6770) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1629), .CK(clk),
.RN(n7050), .Q(FPMULT_Op_MY[3]), .QN(n2260) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6828), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10])
);
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7064), .CK(clk), .Q(FPMULT_Sgf_operation_Result[0]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6906), .CK(clk), .Q(FPMULT_Sgf_operation_Result[1]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10])
);
DFFQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]) );
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n2490), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n6827), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2])
);
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4])
);
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11])
);
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7065), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]) );
DFFRXLTS R_0 ( .D(n1569), .CK(clk), .RN(n2393), .Q(n6954) );
DFFSX1TS R_1 ( .D(FPMULT_Sgf_operation_Result[40]), .CK(clk), .SN(n2392),
.Q(n6953) );
DFFRXLTS R_3 ( .D(n1573), .CK(clk), .RN(n2392), .Q(n6952) );
DFFSX1TS R_4 ( .D(FPMULT_Sgf_operation_Result[44]), .CK(clk), .SN(n2392),
.Q(n6951) );
DFFRXLTS R_6 ( .D(n1570), .CK(clk), .RN(n2391), .Q(n6950) );
DFFSX1TS R_7 ( .D(FPMULT_Sgf_operation_Result[41]), .CK(clk), .SN(n2392),
.Q(n6949) );
DFFRXLTS R_9 ( .D(n1565), .CK(clk), .RN(n2391), .Q(n6948) );
DFFSX1TS R_10 ( .D(FPMULT_Sgf_operation_Result[36]), .CK(clk), .SN(n2393),
.Q(n6947) );
DFFSX1TS R_12 ( .D(n7076), .CK(clk), .SN(n6973), .Q(n6946), .QN(n6857) );
DFFSX1TS R_13 ( .D(n7073), .CK(clk), .SN(n6972), .QN(n6848) );
DFFSX1TS R_14 ( .D(n7075), .CK(clk), .SN(n6973), .Q(n6945), .QN(n6847) );
DFFSX1TS R_15 ( .D(n7074), .CK(clk), .SN(n6972), .Q(n6944), .QN(n6846) );
DFFSX1TS R_16 ( .D(n7072), .CK(clk), .SN(n6969), .Q(n6763), .QN(n6822) );
DFFSX1TS R_18 ( .D(FPMULT_Sgf_operation_Result[46]), .CK(clk), .SN(n2391),
.Q(n6942) );
DFFRXLTS R_20 ( .D(n1571), .CK(clk), .RN(n2391), .Q(n6940) );
DFFSX1TS R_21 ( .D(FPMULT_Sgf_operation_Result[42]), .CK(clk), .SN(n2393),
.Q(n6939) );
DFFSX1TS R_24 ( .D(FPMULT_Sgf_operation_Result[38]), .CK(clk), .SN(n2393),
.Q(n6937) );
DFFRXLTS R_26 ( .D(n1574), .CK(clk), .RN(n2391), .Q(n6936) );
DFFSX1TS R_27 ( .D(FPMULT_Sgf_operation_Result[45]), .CK(clk), .SN(n2392),
.Q(n6935) );
DFFRXLTS R_29 ( .D(n1568), .CK(clk), .RN(n2391), .Q(n6934) );
DFFSX1TS R_30 ( .D(FPMULT_Sgf_operation_Result[39]), .CK(clk), .SN(n2393),
.Q(n6933) );
DFFRXLTS R_32 ( .D(n1561), .CK(clk), .RN(n7042), .Q(n6932) );
DFFSX1TS R_33 ( .D(FPMULT_Sgf_operation_Result[32]), .CK(clk), .SN(n7010),
.Q(n6931) );
DFFRXLTS R_35 ( .D(n1566), .CK(clk), .RN(n2391), .Q(n6930) );
DFFSX1TS R_36 ( .D(FPMULT_Sgf_operation_Result[37]), .CK(clk), .SN(n2392),
.Q(n6929) );
DFFRXLTS R_38 ( .D(n1572), .CK(clk), .RN(n2391), .Q(n6928) );
DFFSX1TS R_39 ( .D(FPMULT_Sgf_operation_Result[43]), .CK(clk), .SN(n2393),
.Q(n6927) );
DFFSX1TS R_42 ( .D(FPMULT_Sgf_operation_Result[47]), .CK(clk), .SN(n2365),
.Q(n6925) );
DFFRXLTS R_43 ( .D(n6958), .CK(clk), .RN(n7012), .Q(n6924) );
DFFRX1TS R_46 ( .D(n6922), .CK(clk), .RN(n4494), .Q(
DP_OP_501J223_127_5235_n897) );
DFFSX1TS R_50 ( .D(n6921), .CK(clk), .SN(n7041), .Q(n7070) );
DFFSX1TS R_58 ( .D(n6919), .CK(clk), .SN(n4496), .Q(n7069) );
DFFRX1TS R_59 ( .D(n6918), .CK(clk), .RN(n7028), .Q(n7068) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12])
);
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1690), .CK(clk), .RN(n7020),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n6751) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]) );
DFFSX2TS R_45 ( .D(n6923), .CK(clk), .SN(n7048), .Q(n7062), .QN(n6955) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1618), .CK(clk), .RN(
n7053), .Q(FPMULT_Add_result[2]), .QN(n6896) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1619), .CK(clk), .RN(
n7053), .Q(FPMULT_Add_result[1]), .QN(n6897) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1623), .CK(clk), .RN(n4494), .Q(
FPMULT_FSM_selector_B[0]), .QN(n6781) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1617), .CK(clk), .RN(
n7053), .Q(FPMULT_Add_result[3]), .QN(n6895) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1616), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[4]), .QN(n6894) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1609), .CK(clk),
.RN(n7054), .Q(FPMULT_Add_result[11]), .QN(n6887) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n7026), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n6797) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1612), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[8]), .QN(n6890) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1615), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[5]), .QN(n6893) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n7025), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .QN(n6786) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1611), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[9]), .QN(n6889) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1610), .CK(clk),
.RN(n7054), .Q(FPMULT_Add_result[10]), .QN(n6888) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1607), .CK(clk),
.RN(n7054), .Q(FPMULT_Add_result[13]), .QN(n6885) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1614), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[6]), .QN(n6892) );
DFFRX1TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2136), .CK(clk), .RN(n7024),
.Q(FPSENCOS_cont_var_out[1]), .QN(n6802) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1613), .CK(clk), .RN(
n7054), .Q(FPMULT_Add_result[7]), .QN(n6891) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1338), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n6752) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1605), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[15]), .QN(n6883) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1953), .CK(clk), .RN(
n7032), .Q(FPSENCOS_d_ff2_X[29]), .QN(n6871) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1955), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_X[27]), .QN(n6872) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1956), .CK(clk), .RN(
n7034), .Q(FPSENCOS_d_ff2_X[26]), .QN(n6875) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1957), .CK(clk), .RN(
n7035), .Q(FPSENCOS_d_ff2_X[25]), .QN(n6874) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1604), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[16]), .QN(n6882) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2080), .CK(clk), .RN(n7037),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n6825) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1603), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[17]), .QN(n6881) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1856), .CK(clk), .RN(
n7033), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n6841) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1952), .CK(clk), .RN(
n7031), .Q(FPSENCOS_d_ff2_X[30]), .QN(n6851) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1602), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[18]), .QN(n6880) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1508), .CK(
clk), .RN(n7051), .Q(FPMULT_Sgf_normalized_result[3]), .QN(n6788) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1515), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n6865) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1601), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[19]), .QN(n6879) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1320), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n6869) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1319), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n6801) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1512), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[7]), .QN(n6866) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1510), .CK(
clk), .RN(n7046), .Q(FPMULT_Sgf_normalized_result[5]), .QN(n6792) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1600), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[20]), .QN(n6878) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1595), .CK(clk), .RN(
n7049), .Q(FPMULT_exp_oper_result[8]), .QN(n6762) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1586), .CK(clk), .RN(
n7058), .Q(underflow_flag_mult), .QN(n6864) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1599), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[21]), .QN(n6877) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n6975), .Q(result_add_subt[6]), .QN(n6839) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n6978), .Q(result_add_subt[7]), .QN(n6840) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1335), .CK(clk), .RN(
n6988), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n7063) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1662), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[4]), .QN(n2480) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1661), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[3]), .QN(n2216) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1643), .CK(clk),
.RN(n7050), .Q(FPMULT_Op_MY[17]), .QN(n2463) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1674), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[16]), .QN(n2406) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1528), .CK(clk), .RN(n7048), .Q(
FPMULT_FSM_selector_C) );
DFFSX1TS R_51 ( .D(n6920), .CK(clk), .SN(n7011), .Q(n7071) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1837), .CK(clk), .RN(
n6963), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1802), .CK(clk), .RN(n6964), .Q(FPADDSUB_Data_array_SWR[15]), .QN(n2418) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n6979), .QN(n6835) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n6977), .QN(n6833) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1363), .CK(clk), .RN(
n6976), .QN(n6832) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n6990),
.Q(FPADDSUB_ADD_OVRFLW_NRM), .QN(n6806) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1636), .CK(clk),
.RN(n7058), .Q(n2201), .QN(n2240) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1675), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[17]), .QN(n2405) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1317), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n6853) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]) );
ADDFHX2TS DP_OP_26J223_129_1325_U2 ( .A(n6766), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .CI(DP_OP_26J223_129_1325_n2), .CO(
DP_OP_26J223_129_1325_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1205), .CK(clk), .RN(
n6990), .Q(FPADDSUB_DmP_mant_SFG_SWR[0]), .QN(n6798) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]) );
DFFX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(n2210) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_Result[4]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1642), .CK(clk),
.RN(n7052), .Q(FPMULT_Op_MY[16]), .QN(n2199) );
MDFFHQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D0(DP_OP_501J223_127_5235_n630), .D1(1'b1), .S0(
DP_OP_501J223_127_5235_n723), .CK(clk), .Q(n6746) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1321), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n6868) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1606), .CK(clk),
.RN(n7055), .Q(FPMULT_Add_result[14]), .QN(n6884) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1514), .CK(
clk), .RN(n7047), .Q(FPMULT_Sgf_normalized_result[9]), .QN(n6789) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(
n6989), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[4]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6])
);
DFFQX4TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n7066), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[0]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]) );
DFFHQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]) );
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10])
);
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1])
);
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
DFFHQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n2497), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]) );
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2])
);
DFFHQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]) );
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3])
);
DFFQX2TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]) );
DFFQX4TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1640), .CK(clk),
.RN(n7058), .Q(FPMULT_Op_MY[14]), .QN(n2226) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5])
);
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1631), .CK(clk),
.RN(n7046), .Q(FPMULT_Op_MY[5]), .QN(n2198) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1646), .CK(clk),
.RN(n7050), .QN(n2194) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1634), .CK(clk),
.RN(n7048), .Q(FPMULT_Op_MY[8]), .QN(n2236) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1644), .CK(clk),
.RN(n7050), .Q(n6749), .QN(n2217) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1670), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[12]), .QN(n2261) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1672), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[14]), .QN(n2257) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1660), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[2]), .QN(n2258) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1673), .CK(clk),
.RN(n7057), .Q(FPMULT_Op_MX[15]), .QN(n2479) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1663), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[5]), .QN(n2458) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1316), .CK(clk), .RN(
n6987), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1664), .CK(clk),
.RN(n7056), .Q(FPMULT_Op_MX[6]), .QN(n2420) );
CMPR32X2TS DP_OP_26J223_129_1325_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n6766), .C(DP_OP_26J223_129_1325_n18), .CO(DP_OP_26J223_129_1325_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J223_129_1325_U8 ( .A(DP_OP_26J223_129_1325_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J223_129_1325_n8), .CO(
DP_OP_26J223_129_1325_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J223_129_1325_U7 ( .A(DP_OP_26J223_129_1325_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J223_129_1325_n7), .CO(
DP_OP_26J223_129_1325_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J223_129_1325_U6 ( .A(DP_OP_26J223_129_1325_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J223_129_1325_n6), .CO(
DP_OP_26J223_129_1325_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1819), .CK(clk), .RN(
n6960), .Q(FPADDSUB_intDY_EWSW[24]) );
CMPR32X2TS DP_OP_234J223_132_4955_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_234J223_132_4955_n22), .CO(
DP_OP_234J223_132_4955_n9), .S(FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_26J223_129_1325_U5 ( .A(DP_OP_26J223_129_1325_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J223_129_1325_n5), .CO(
DP_OP_26J223_129_1325_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_234J223_132_4955_U9 ( .A(DP_OP_234J223_132_4955_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J223_132_4955_n9), .CO(
DP_OP_234J223_132_4955_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_26J223_129_1325_U4 ( .A(n6766), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J223_129_1325_n4), .CO(
DP_OP_26J223_129_1325_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR42X1TS DP_OP_502J223_128_4510_U115 ( .A(DP_OP_502J223_128_4510_n170),
.B(DP_OP_502J223_128_4510_n118), .C(DP_OP_502J223_128_4510_n112), .D(
DP_OP_502J223_128_4510_n119), .ICI(DP_OP_502J223_128_4510_n115), .S(
DP_OP_502J223_128_4510_n110), .ICO(DP_OP_502J223_128_4510_n108), .CO(
DP_OP_502J223_128_4510_n109) );
CMPR32X2TS DP_OP_234J223_132_4955_U8 ( .A(DP_OP_234J223_132_4955_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J223_132_4955_n8), .CO(
DP_OP_234J223_132_4955_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_26J223_129_1325_U3 ( .A(n6766), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J223_129_1325_n3), .CO(
DP_OP_26J223_129_1325_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_234J223_132_4955_U7 ( .A(DP_OP_234J223_132_4955_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J223_132_4955_n7), .CO(
DP_OP_234J223_132_4955_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS intadd_518_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n6768), .C(
intadd_518_CI), .CO(intadd_518_n3), .S(intadd_518_SUM_0_) );
CMPR32X2TS intadd_517_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n6768), .C(
intadd_517_CI), .CO(intadd_517_n3), .S(intadd_517_SUM_0_) );
CMPR42X1TS DP_OP_501J223_127_5235_U433 ( .A(DP_OP_501J223_127_5235_n521),
.B(DP_OP_501J223_127_5235_n491), .C(DP_OP_501J223_127_5235_n497), .D(
DP_OP_501J223_127_5235_n515), .ICI(DP_OP_501J223_127_5235_n471), .S(
DP_OP_501J223_127_5235_n467), .ICO(DP_OP_501J223_127_5235_n465), .CO(
DP_OP_501J223_127_5235_n466) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2144), .CK(clk), .RN(
n6990), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n2501) );
CMPR42X1TS DP_OP_501J223_127_5235_U434 ( .A(DP_OP_501J223_127_5235_n510),
.B(DP_OP_501J223_127_5235_n474), .C(DP_OP_501J223_127_5235_n478), .D(
DP_OP_501J223_127_5235_n475), .ICI(DP_OP_501J223_127_5235_n472), .S(
DP_OP_501J223_127_5235_n470), .ICO(DP_OP_501J223_127_5235_n468), .CO(
DP_OP_501J223_127_5235_n469) );
CMPR32X2TS intadd_517_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(intadd_517_B_1_),
.C(intadd_517_n3), .CO(intadd_517_n2), .S(intadd_517_SUM_1_) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1799), .CK(clk), .RN(n6964), .Q(FPADDSUB_Data_array_SWR[12]) );
CMPR32X2TS intadd_517_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n6782), .C(
intadd_517_n2), .CO(intadd_517_n1), .S(intadd_517_SUM_2_) );
CMPR32X2TS DP_OP_234J223_132_4955_U5 ( .A(DP_OP_234J223_132_4955_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J223_132_4955_n5), .CO(
DP_OP_234J223_132_4955_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS intadd_516_U4 ( .A(n6944), .B(FPADDSUB_DMP_EXP_EWSW[24]), .C(
intadd_516_CI), .CO(intadd_516_n3), .S(intadd_516_SUM_0_) );
CMPR32X2TS intadd_515_U3 ( .A(mult_x_309_n17), .B(mult_x_309_n15), .C(
intadd_515_n3), .CO(intadd_515_n2), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_516_U3 ( .A(n6945), .B(FPADDSUB_DMP_EXP_EWSW[25]), .C(
intadd_516_n3), .CO(intadd_516_n2), .S(intadd_516_SUM_1_) );
CMPR32X2TS intadd_516_U2 ( .A(n6946), .B(FPADDSUB_DMP_EXP_EWSW[26]), .C(
intadd_516_n2), .CO(intadd_516_n1), .S(intadd_516_SUM_2_) );
CMPR32X2TS DP_OP_234J223_132_4955_U2 ( .A(n2382), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J223_132_4955_n2), .CO(DP_OP_234J223_132_4955_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CLKMX2X2TS U2217 ( .A(FPMULT_P_Sgf[29]), .B(n3287), .S0(n6260), .Y(n1558) );
XOR2X1TS U2218 ( .A(n4186), .B(n4185), .Y(FPMULT_Sgf_operation_Result[36])
);
XNOR2X1TS U2219 ( .A(n5564), .B(n5563), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
XOR2X2TS U2220 ( .A(n3278), .B(n3344), .Y(FPMULT_Sgf_operation_Result[42])
);
CLKBUFX2TS U2221 ( .A(n6290), .Y(n2284) );
NAND2X1TS U2222 ( .A(n3570), .B(n2429), .Y(n3561) );
AOI21X2TS U2223 ( .A0(n4181), .A1(n3419), .B0(n3357), .Y(n3421) );
OAI21X1TS U2224 ( .A0(n3597), .A1(n3594), .B0(n3595), .Y(n3593) );
OAI32X1TS U2225 ( .A0(n6714), .A1(FPADDSUB_intDX_EWSW[31]), .A2(n6717), .B0(
FPADDSUB_Shift_reg_FLAGS_7_6), .B1(FPADDSUB_OP_FLAG_EXP), .Y(n6715) );
AOI21X1TS U2226 ( .A0(n4181), .A1(n3254), .B0(n3253), .Y(n3278) );
AOI222X1TS U2227 ( .A0(n2302), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n4735) );
AOI222X1TS U2228 ( .A0(n2302), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n4725) );
AOI222X1TS U2229 ( .A0(n2302), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n4715) );
AOI222X1TS U2230 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n4749)
);
AOI222X1TS U2231 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n4722) );
AOI222X1TS U2232 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n4719) );
AOI222X1TS U2233 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n4712) );
AOI222X1TS U2234 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n4721), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n4716) );
AOI222X1TS U2235 ( .A0(n6562), .A1(cordic_result[0]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[0]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[0]), .Y(n5121)
);
AOI222X1TS U2236 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n4729) );
AOI222X1TS U2237 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n4727) );
AOI222X1TS U2238 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n4738) );
AOI222X1TS U2239 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n4728) );
AOI222X1TS U2240 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n4734) );
AOI222X1TS U2241 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n4733) );
AOI222X1TS U2242 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n4737), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n4726) );
AOI222X1TS U2243 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n4736), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n4732) );
AOI222X1TS U2244 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n4746)
);
AOI222X1TS U2245 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n4744)
);
AOI222X1TS U2246 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n4741)
);
AOI222X1TS U2247 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n4739)
);
AOI222X1TS U2248 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n4742)
);
AOI222X1TS U2249 ( .A0(n4731), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n4745)
);
AOI222X1TS U2250 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n4740)
);
AOI222X1TS U2251 ( .A0(n4731), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n4933), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n4743)
);
AOI222X1TS U2252 ( .A0(n6430), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n4713) );
AOI222X1TS U2253 ( .A0(n4731), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n4717) );
AOI222X1TS U2254 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n4747), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n4724) );
AOI222X1TS U2255 ( .A0(n6469), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n4721), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n4718) );
AOI222X1TS U2256 ( .A0(n6431), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n4721), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n4714) );
AOI222X1TS U2257 ( .A0(n6431), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n4730), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n4721), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n4720) );
AOI21X1TS U2258 ( .A0(n2375), .A1(n3415), .B0(n3414), .Y(n3416) );
XNOR2X1TS U2259 ( .A(n4457), .B(n4332), .Y(n4333) );
AOI222X1TS U2260 ( .A0(n6453), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n4933), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n6427), .Y(n4934)
);
AOI222X1TS U2261 ( .A0(n5141), .A1(cordic_result[8]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[8]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[8]), .Y(n5123)
);
AOI222X1TS U2262 ( .A0(n5141), .A1(cordic_result[3]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[3]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[3]), .Y(n5124)
);
AOI222X1TS U2263 ( .A0(n5141), .A1(cordic_result[2]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[2]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[2]), .Y(n5129)
);
AOI222X1TS U2264 ( .A0(n5141), .A1(cordic_result[7]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[7]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[7]), .Y(n5128)
);
AOI222X1TS U2265 ( .A0(n5141), .A1(cordic_result[9]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[9]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[9]), .Y(n5142)
);
AOI222X1TS U2266 ( .A0(n5141), .A1(cordic_result[5]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[5]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[5]), .Y(n5125)
);
AOI222X1TS U2267 ( .A0(n5141), .A1(cordic_result[11]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[11]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[11]), .Y(n5127) );
AOI222X1TS U2268 ( .A0(n5141), .A1(cordic_result[10]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[10]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[10]), .Y(n5119) );
XNOR2X2TS U2269 ( .A(n4328), .B(n4327), .Y(n4329) );
AOI22X1TS U2270 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2338),
.B1(n5358), .Y(n5360) );
BUFX3TS U2271 ( .A(n6518), .Y(n6494) );
INVX3TS U2272 ( .A(n2347), .Y(n2206) );
BUFX3TS U2273 ( .A(n6444), .Y(n6449) );
NAND2X1TS U2274 ( .A(n3770), .B(n3775), .Y(n3755) );
INVX2TS U2275 ( .A(n3423), .Y(n3424) );
CLKBUFX2TS U2276 ( .A(n6608), .Y(n6613) );
BUFX3TS U2277 ( .A(n6444), .Y(n6448) );
AOI21X2TS U2278 ( .A0(n4457), .A1(n4450), .B0(n4452), .Y(n4448) );
CLKBUFX2TS U2279 ( .A(n6414), .Y(n6445) );
AOI21X1TS U2280 ( .A0(n3571), .A1(n3549), .B0(n3548), .Y(n3550) );
BUFX3TS U2281 ( .A(n4997), .Y(n6549) );
CLKBUFX2TS U2282 ( .A(n4996), .Y(n5053) );
INVX2TS U2283 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n6656) );
NOR2X1TS U2284 ( .A(n3556), .B(n3565), .Y(n3549) );
INVX2TS U2285 ( .A(n3556), .Y(n3575) );
BUFX3TS U2286 ( .A(n4721), .Y(n4931) );
INVX2TS U2287 ( .A(n5232), .Y(n2347) );
INVX1TS U2288 ( .A(n3574), .Y(n3562) );
INVX2TS U2289 ( .A(n5232), .Y(n5399) );
OAI21X2TS U2290 ( .A0(n3778), .A1(n3784), .B0(n3779), .Y(n3771) );
NAND2X2TS U2291 ( .A(n4174), .B(n4176), .Y(n3422) );
NAND2X2TS U2292 ( .A(n4174), .B(n3356), .Y(n3417) );
BUFX3TS U2293 ( .A(n4674), .Y(n4697) );
NAND2X1TS U2294 ( .A(DP_OP_501J223_127_5235_n449), .B(
DP_OP_501J223_127_5235_n451), .Y(n3779) );
NAND2X1TS U2295 ( .A(DP_OP_501J223_127_5235_n470), .B(
DP_OP_501J223_127_5235_n476), .Y(n3800) );
NAND2X1TS U2296 ( .A(DP_OP_501J223_127_5235_n448), .B(n3752), .Y(n3774) );
NAND2X1TS U2297 ( .A(DP_OP_501J223_127_5235_n121), .B(n3547), .Y(n3566) );
NAND2X1TS U2298 ( .A(DP_OP_502J223_128_4510_n117), .B(
DP_OP_502J223_128_4510_n122), .Y(n5508) );
NOR2X1TS U2299 ( .A(DP_OP_502J223_128_4510_n123), .B(
DP_OP_502J223_128_4510_n128), .Y(n5512) );
NOR2X1TS U2300 ( .A(DP_OP_500J223_126_4510_n123), .B(
DP_OP_500J223_126_4510_n128), .Y(n5585) );
NOR2X1TS U2301 ( .A(DP_OP_501J223_127_5235_n448), .B(n3752), .Y(n3763) );
INVX6TS U2302 ( .A(n3406), .Y(n4176) );
NOR2X6TS U2303 ( .A(DP_OP_501J223_127_5235_n136), .B(
DP_OP_501J223_127_5235_n143), .Y(n3589) );
CMPR32X2TS U2304 ( .A(n3973), .B(n3972), .C(n3971), .CO(n3975), .S(n3969) );
NOR2X2TS U2305 ( .A(DP_OP_501J223_127_5235_n130), .B(
DP_OP_501J223_127_5235_n135), .Y(n3583) );
NAND2X2TS U2306 ( .A(DP_OP_501J223_127_5235_n452), .B(
DP_OP_501J223_127_5235_n456), .Y(n3784) );
NOR2X6TS U2307 ( .A(DP_OP_501J223_127_5235_n144), .B(
DP_OP_501J223_127_5235_n153), .Y(n3594) );
NAND2X2TS U2308 ( .A(DP_OP_501J223_127_5235_n124), .B(
DP_OP_501J223_127_5235_n122), .Y(n3574) );
NOR2X2TS U2309 ( .A(DP_OP_502J223_128_4510_n110), .B(
DP_OP_502J223_128_4510_n116), .Y(n5502) );
NAND2X2TS U2310 ( .A(DP_OP_501J223_127_5235_n464), .B(
DP_OP_501J223_127_5235_n469), .Y(n3795) );
NOR2X1TS U2311 ( .A(n5236), .B(n6521), .Y(n5315) );
NOR2X1TS U2312 ( .A(n2371), .B(n3840), .Y(n3758) );
NOR2X6TS U2313 ( .A(n4179), .B(n4182), .Y(n4174) );
CLKBUFX2TS U2314 ( .A(n5427), .Y(n6708) );
OR2X2TS U2315 ( .A(n6339), .B(n6343), .Y(n6382) );
NAND2BX2TS U2316 ( .AN(n3302), .B(n3301), .Y(n5143) );
NOR2X4TS U2317 ( .A(operation[1]), .B(n5103), .Y(n4996) );
OR2X2TS U2318 ( .A(n6350), .B(operation[1]), .Y(n4581) );
BUFX3TS U2319 ( .A(n4558), .Y(n4723) );
NOR2X2TS U2320 ( .A(n6557), .B(n6562), .Y(n4985) );
CMPR32X2TS U2321 ( .A(n3757), .B(n3756), .C(DP_OP_501J223_127_5235_n447),
.CO(n3759), .S(n3752) );
CMPR32X2TS U2322 ( .A(n3553), .B(n3552), .C(DP_OP_501J223_127_5235_n120),
.CO(n3554), .S(n3547) );
CMPR32X2TS U2323 ( .A(n3962), .B(n3961), .C(n3960), .CO(n3970), .S(n3957) );
NOR2X1TS U2324 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n4485) );
NAND2X1TS U2325 ( .A(n6787), .B(FPMULT_FS_Module_state_reg[0]), .Y(n5454) );
INVX2TS U2326 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n2316) );
NOR2X1TS U2327 ( .A(n4175), .B(n3354), .Y(n3355) );
NOR2X1TS U2328 ( .A(n4175), .B(n3250), .Y(n3251) );
BUFX3TS U2329 ( .A(n5427), .Y(n6668) );
BUFX3TS U2330 ( .A(n6439), .Y(n6415) );
NOR2X2TS U2331 ( .A(n3406), .B(n3354), .Y(n3356) );
BUFX3TS U2332 ( .A(n5015), .Y(n5103) );
OAI21X2TS U2333 ( .A0(n2576), .A1(n2575), .B0(n2574), .Y(n6706) );
BUFX3TS U2334 ( .A(n4984), .Y(n6562) );
CLKBUFX2TS U2335 ( .A(n6607), .Y(n6615) );
NOR2X2TS U2336 ( .A(DP_OP_501J223_127_5235_n173), .B(
DP_OP_501J223_127_5235_n180), .Y(n3607) );
AND2X2TS U2337 ( .A(n6023), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6607) );
NAND2X2TS U2338 ( .A(n3904), .B(n3903), .Y(n4011) );
BUFX3TS U2339 ( .A(n5422), .Y(n5427) );
BUFX3TS U2340 ( .A(n6438), .Y(n6450) );
NAND2X2TS U2341 ( .A(DP_OP_501J223_127_5235_n163), .B(
DP_OP_501J223_127_5235_n172), .Y(n3604) );
NAND2X2TS U2342 ( .A(n3062), .B(n3061), .Y(n4325) );
NOR2X4TS U2343 ( .A(n6337), .B(n6358), .Y(n4984) );
OA21X2TS U2344 ( .A0(n5452), .A1(n3280), .B0(n3279), .Y(n5478) );
CMPR32X2TS U2345 ( .A(n3824), .B(n3823), .C(n3822), .CO(
DP_OP_501J223_127_5235_n453), .S(DP_OP_501J223_127_5235_n454) );
CMPR32X2TS U2346 ( .A(n3918), .B(n3917), .C(n3916), .CO(n3939), .S(n3906) );
CMPR32X2TS U2347 ( .A(n3950), .B(n3949), .C(n3948), .CO(n3958), .S(n3943) );
AND4X1TS U2348 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n3292), .Y(n3293) );
CMPR32X2TS U2349 ( .A(n3886), .B(n3885), .C(n3884), .CO(n3903), .S(n4016) );
INVX2TS U2350 ( .A(n6372), .Y(intadd_517_B_1_) );
INVX2TS U2351 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .Y(n5422) );
INVX2TS U2352 ( .A(FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n6354) );
OR2X2TS U2353 ( .A(DP_OP_501J223_127_5235_n181), .B(
DP_OP_501J223_127_5235_n187), .Y(n2499) );
CMPR32X2TS U2354 ( .A(n3833), .B(n3832), .C(n3831), .CO(
DP_OP_501J223_127_5235_n471), .S(DP_OP_501J223_127_5235_n472) );
INVX2TS U2355 ( .A(n4588), .Y(n4595) );
CLKBUFX2TS U2356 ( .A(n4554), .Y(n6438) );
INVX3TS U2357 ( .A(n3283), .Y(n3059) );
OAI22X1TS U2358 ( .A0(n3968), .A1(n3953), .B0(n3966), .B1(n2394), .Y(n3973)
);
ADDFHX1TS U2359 ( .A(n3667), .B(n3666), .CI(DP_OP_501J223_127_5235_n158),
.CO(DP_OP_501J223_127_5235_n148), .S(DP_OP_501J223_127_5235_n149) );
CMPR32X2TS U2360 ( .A(n3930), .B(n3929), .C(n3928), .CO(n3944), .S(n3942) );
CMPR32X2TS U2361 ( .A(n3876), .B(n3875), .C(n3874), .CO(n3905), .S(n3904) );
ADDHXLTS U2362 ( .A(n3837), .B(n3836), .CO(DP_OP_501J223_127_5235_n478), .S(
DP_OP_501J223_127_5235_n479) );
CMPR32X2TS U2363 ( .A(n4254), .B(n4253), .C(n4252), .CO(
DP_OP_502J223_128_4510_n130), .S(DP_OP_502J223_128_4510_n131) );
CMPR32X2TS U2364 ( .A(n4358), .B(n4359), .C(n4357), .CO(
DP_OP_500J223_126_4510_n130), .S(DP_OP_500J223_126_4510_n131) );
CMPR32X2TS U2365 ( .A(n3873), .B(n3872), .C(n3871), .CO(n3917), .S(n3874) );
NOR2X1TS U2366 ( .A(n2412), .B(FPADDSUB_intDX_EWSW[30]), .Y(n2570) );
CMPR32X2TS U2367 ( .A(n3733), .B(n3732), .C(n3731), .CO(n3741), .S(n3739) );
NOR2X1TS U2368 ( .A(n2334), .B(n3692), .Y(n3652) );
CMPR32X2TS U2369 ( .A(n3892), .B(n3891), .C(n3890), .CO(n3885), .S(n4019) );
NAND2X1TS U2370 ( .A(n2758), .B(n2761), .Y(n2759) );
NAND2X1TS U2371 ( .A(n2772), .B(n2790), .Y(n2773) );
NAND2X1TS U2372 ( .A(n3111), .B(n3131), .Y(n3112) );
NAND2X1TS U2373 ( .A(n4891), .B(n4890), .Y(n4898) );
INVX2TS U2374 ( .A(n6373), .Y(n6371) );
NOR2X2TS U2375 ( .A(DP_OP_501J223_127_5235_n188), .B(n3499), .Y(n3615) );
INVX2TS U2376 ( .A(n2340), .Y(n2341) );
INVX2TS U2377 ( .A(n4425), .Y(n4554) );
INVX2TS U2378 ( .A(n5273), .Y(n5238) );
OAI22X1TS U2379 ( .A0(n2334), .A1(n3698), .B0(n2335), .B1(n3697), .Y(n3666)
);
OAI22X1TS U2380 ( .A0(n3707), .A1(n3700), .B0(n2335), .B1(n3699), .Y(
DP_OP_501J223_127_5235_n235) );
INVX2TS U2381 ( .A(n6733), .Y(n6623) );
CMPR32X2TS U2382 ( .A(n3899), .B(n3924), .C(n3923), .CO(n3928), .S(n3925) );
CMPR32X2TS U2383 ( .A(n4571), .B(n4570), .C(n4569), .CO(
DP_OP_502J223_128_4510_n111), .S(DP_OP_502J223_128_4510_n112) );
CMPR32X2TS U2384 ( .A(n4313), .B(n4312), .C(n4311), .CO(
DP_OP_500J223_126_4510_n111), .S(DP_OP_500J223_126_4510_n112) );
BUFX3TS U2385 ( .A(FPSENCOS_cont_iter_out[2]), .Y(n6372) );
INVX2TS U2386 ( .A(n7059), .Y(n2340) );
NAND2X1TS U2387 ( .A(n3139), .B(n3138), .Y(n3140) );
INVX2TS U2388 ( .A(n7077), .Y(n6733) );
CLKBUFX2TS U2389 ( .A(n4203), .Y(n3353) );
NAND2X1TS U2390 ( .A(n4786), .B(n4785), .Y(n5815) );
NAND2X1TS U2391 ( .A(n6346), .B(n6347), .Y(n6336) );
NAND4BXLTS U2392 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(n4671), .D(n6786), .Y(
n4425) );
NOR2X1TS U2393 ( .A(n6306), .B(n6304), .Y(n2984) );
OAI22X1TS U2394 ( .A0(n3968), .A1(n3877), .B0(n3866), .B1(n3967), .Y(n3871)
);
NAND2X1TS U2395 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(n6351),
.Y(n6012) );
OAI22X1TS U2396 ( .A0(n3706), .A1(n3700), .B0(n3707), .B1(n3699), .Y(
DP_OP_501J223_127_5235_n234) );
OAI22X1TS U2397 ( .A0(n3968), .A1(n3913), .B0(n3919), .B1(n2394), .Y(n3924)
);
NAND2X1TS U2398 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(n6772),
.Y(n6351) );
NAND2X1TS U2399 ( .A(n3858), .B(n3857), .Y(n3859) );
NAND2X1TS U2400 ( .A(n3026), .B(n3025), .Y(n3027) );
NAND2X1TS U2401 ( .A(n3043), .B(n2498), .Y(n3044) );
INVX4TS U2402 ( .A(n3641), .Y(n2387) );
OAI22X1TS U2403 ( .A0(n3703), .A1(n3698), .B0(n2332), .B1(n3697), .Y(
DP_OP_501J223_127_5235_n229) );
XNOR2X1TS U2404 ( .A(n2395), .B(n3896), .Y(n3877) );
BUFX3TS U2405 ( .A(n3967), .Y(n2394) );
NOR2X2TS U2406 ( .A(n3130), .B(n3132), .Y(n3135) );
NOR2X1TS U2407 ( .A(n2385), .B(n3692), .Y(n3669) );
XNOR2X1TS U2408 ( .A(n2395), .B(n3937), .Y(n3919) );
CLKBUFX2TS U2409 ( .A(n5546), .Y(n2381) );
XNOR2X1TS U2410 ( .A(n2395), .B(n3921), .Y(n3913) );
XNOR2X1TS U2411 ( .A(n3921), .B(n2205), .Y(n3887) );
NOR2X1TS U2412 ( .A(n6790), .B(FPMULT_FS_Module_state_reg[2]), .Y(n4574) );
CLKBUFX2TS U2413 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n5340) );
CLKBUFX2TS U2414 ( .A(n4195), .Y(n3005) );
INVX4TS U2415 ( .A(n3460), .Y(n2386) );
INVX2TS U2416 ( .A(n2250), .Y(n2320) );
INVX12TS U2417 ( .A(n3707), .Y(n2333) );
NAND2X1TS U2418 ( .A(n5225), .B(n7063), .Y(n4810) );
NOR2X1TS U2419 ( .A(n2303), .B(n5544), .Y(n4559) );
NOR2X1TS U2420 ( .A(n3748), .B(FPMULT_Op_MY[11]), .Y(n3745) );
NAND2X2TS U2421 ( .A(n3102), .B(n3107), .Y(n3130) );
OAI22X1TS U2422 ( .A0(n2385), .A1(n3700), .B0(n2332), .B1(n3699), .Y(n3681)
);
XNOR2X1TS U2423 ( .A(n3963), .B(n2308), .Y(n3920) );
NAND2X1TS U2424 ( .A(n4226), .B(n2942), .Y(n6254) );
INVX6TS U2425 ( .A(n3465), .Y(n2385) );
ADDHXLTS U2426 ( .A(n6570), .B(n6572), .CO(n4251), .S(n4244) );
INVX4TS U2427 ( .A(n3363), .Y(n2314) );
INVX4TS U2428 ( .A(n3647), .Y(n3695) );
NAND2X2TS U2429 ( .A(n2205), .B(DP_OP_501J223_127_5235_n723), .Y(n3901) );
INVX4TS U2430 ( .A(n3867), .Y(n3692) );
NOR2X2TS U2431 ( .A(n3679), .B(n3696), .Y(n3684) );
XNOR2X1TS U2432 ( .A(n3896), .B(n2205), .Y(n3898) );
CLKXOR2X2TS U2433 ( .A(n4307), .B(n4287), .Y(n4288) );
XNOR2X1TS U2434 ( .A(n2196), .B(n3716), .Y(n3717) );
CLKXOR2X2TS U2435 ( .A(n3816), .B(n3726), .Y(n3727) );
NAND2X1TS U2436 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MY[5]), .Y(n4793) );
NAND2X1TS U2437 ( .A(n6564), .B(n6757), .Y(n3279) );
INVX2TS U2438 ( .A(n2812), .Y(n2997) );
NAND2X1TS U2439 ( .A(n2222), .B(n3514), .Y(n3458) );
INVX4TS U2440 ( .A(n3465), .Y(n3703) );
INVX2TS U2441 ( .A(n6747), .Y(n2913) );
INVX4TS U2442 ( .A(n3649), .Y(n3696) );
ADDHXLTS U2443 ( .A(n3728), .B(n3865), .CO(n3466), .S(n3461) );
ADDHXLTS U2444 ( .A(n5638), .B(n2345), .CO(n4442), .S(n4250) );
AOI21X2TS U2445 ( .A0(n3464), .A1(n2249), .B0(n3516), .Y(n3459) );
INVX4TS U2446 ( .A(n3678), .Y(n3699) );
AOI21X2TS U2447 ( .A0(n6075), .A1(n6071), .B0(n4265), .Y(n6095) );
OAI21X1TS U2448 ( .A0(n3817), .A1(n3814), .B0(n3818), .Y(n3748) );
XNOR2X1TS U2449 ( .A(n2940), .B(n2939), .Y(n2942) );
XNOR2X2TS U2450 ( .A(n3532), .B(n3531), .Y(n3963) );
INVX6TS U2451 ( .A(n3480), .Y(n3679) );
INVX2TS U2452 ( .A(n2253), .Y(n2331) );
NAND2X1TS U2453 ( .A(FPMULT_Op_MY[9]), .B(n6585), .Y(n3814) );
OAI21X2TS U2454 ( .A0(n3645), .A1(n3541), .B0(n3540), .Y(n3546) );
INVX4TS U2455 ( .A(n3491), .Y(n3700) );
AOI21X2TS U2456 ( .A0(n4285), .A1(n4290), .B0(n4284), .Y(n4307) );
NAND3X1TS U2457 ( .A(n4807), .B(n4689), .C(n4688), .Y(n4811) );
NAND2X1TS U2458 ( .A(n6584), .B(n6753), .Y(n3721) );
NOR2X1TS U2459 ( .A(n6584), .B(n6753), .Y(n3719) );
NAND2X1TS U2460 ( .A(n2456), .B(n3536), .Y(n3537) );
NOR2X4TS U2461 ( .A(n3521), .B(n3520), .Y(n3653) );
CLKINVX6TS U2462 ( .A(n3625), .Y(n3657) );
NOR2X2TS U2463 ( .A(n4172), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
NOR2X1TS U2464 ( .A(n3541), .B(n3542), .Y(n3475) );
NAND2X2TS U2465 ( .A(n3951), .B(n3522), .Y(n3627) );
NOR2X1TS U2466 ( .A(n5221), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4809) );
OAI21X1TS U2467 ( .A0(n3540), .A1(n3542), .B0(n3543), .Y(n3474) );
ADDHX1TS U2468 ( .A(n3677), .B(n3860), .CO(n3678), .S(n3491) );
INVX2TS U2469 ( .A(n4231), .Y(DP_OP_499J223_125_1651_n268) );
INVX6TS U2470 ( .A(n3534), .Y(n3645) );
NAND2X1TS U2471 ( .A(n4299), .B(n4298), .Y(n4300) );
NOR2X6TS U2472 ( .A(n3951), .B(n3522), .Y(n3626) );
CLKXOR2X2TS U2473 ( .A(n4166), .B(n4163), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
NOR2X4TS U2474 ( .A(n3340), .B(n3223), .Y(n3341) );
ADDFHX2TS U2475 ( .A(n6572), .B(n6567), .CI(n3632), .CO(n3646), .S(n3664) );
OAI21X1TS U2476 ( .A0(n5915), .A1(n6788), .B0(n5850), .Y(n5890) );
INVX6TS U2477 ( .A(n4229), .Y(DP_OP_499J223_125_1651_n297) );
INVX2TS U2478 ( .A(n4235), .Y(DP_OP_499J223_125_1651_n270) );
INVX2TS U2479 ( .A(n4227), .Y(DP_OP_499J223_125_1651_n295) );
INVX1TS U2480 ( .A(n3535), .Y(n3643) );
CMPR32X2TS U2481 ( .A(n3729), .B(FPMULT_Op_MX[20]), .C(n2287), .CO(n3533),
.S(n3492) );
NAND2X1TS U2482 ( .A(n6753), .B(FPMULT_Op_MY[13]), .Y(n4343) );
INVX2TS U2483 ( .A(n4214), .Y(DP_OP_499J223_125_1651_n271) );
NOR2X1TS U2484 ( .A(n2315), .B(FPMULT_Op_MY[13]), .Y(n4342) );
NAND2XLTS U2485 ( .A(n2244), .B(n3507), .Y(n3508) );
OR2X4TS U2486 ( .A(n3921), .B(n3457), .Y(n2222) );
OAI21X2TS U2487 ( .A0(n2968), .A1(n2965), .B0(n2966), .Y(n2882) );
OAI21X2TS U2488 ( .A0(n3527), .A1(n3506), .B0(n3510), .Y(n3509) );
XNOR2X1TS U2489 ( .A(n4144), .B(n4143), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
NOR2X2TS U2490 ( .A(n3328), .B(n3329), .Y(n3332) );
NAND2X2TS U2491 ( .A(n6570), .B(n6579), .Y(n3642) );
INVX2TS U2492 ( .A(n6277), .Y(DP_OP_499J223_125_1651_n278) );
NAND2X1TS U2493 ( .A(n3896), .B(n3444), .Y(n3485) );
NAND2X1TS U2494 ( .A(n2972), .B(n2971), .Y(n2973) );
NAND2X1TS U2495 ( .A(n2914), .B(n2926), .Y(n2915) );
NAND2X1TS U2496 ( .A(n3243), .B(n3242), .Y(n3244) );
NAND2X1TS U2497 ( .A(n3208), .B(n3212), .Y(n3209) );
NAND2X1TS U2498 ( .A(n3511), .B(n3510), .Y(n3512) );
INVX2TS U2499 ( .A(n2194), .Y(n5647) );
NAND2X2TS U2500 ( .A(n3914), .B(n3450), .Y(n3462) );
AOI21X1TS U2501 ( .A0(n3240), .A1(n3232), .B0(n3231), .Y(n3236) );
NAND2X1TS U2502 ( .A(n2934), .B(n2933), .Y(n2935) );
NAND2X1TS U2503 ( .A(n4135), .B(n4134), .Y(n4156) );
CLKAND2X2TS U2504 ( .A(n2677), .B(n2836), .Y(n2678) );
NAND2X6TS U2505 ( .A(n2885), .B(n2878), .Y(n2989) );
NOR2X2TS U2506 ( .A(n3322), .B(n3315), .Y(n3316) );
NAND2X1TS U2507 ( .A(n2949), .B(n2948), .Y(n2950) );
CMPR32X2TS U2508 ( .A(n6585), .B(n5643), .C(n3456), .CO(n3513), .S(n3450) );
NAND2X1TS U2509 ( .A(n3237), .B(n3239), .Y(n3162) );
NAND2X1TS U2510 ( .A(n2251), .B(n3447), .Y(n3448) );
NAND2X1TS U2511 ( .A(n2899), .B(n2898), .Y(n2900) );
NAND2X1TS U2512 ( .A(n3127), .B(n3143), .Y(n3128) );
NAND2XLTS U2513 ( .A(n2218), .B(n3453), .Y(n3454) );
NOR2X6TS U2514 ( .A(n3274), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n3311)
);
NAND2X1TS U2515 ( .A(n3092), .B(n3144), .Y(n3093) );
INVX4TS U2516 ( .A(n2208), .Y(n2209) );
OAI21X2TS U2517 ( .A0(n3114), .A1(n3142), .B0(n3144), .Y(n3129) );
AOI21X2TS U2518 ( .A0(n4067), .A1(n4079), .B0(n4084), .Y(n4171) );
OAI21X2TS U2519 ( .A0(n3525), .A1(n3528), .B0(n3529), .Y(n3438) );
NAND2X2TS U2520 ( .A(n2889), .B(n2888), .Y(n2890) );
NOR2X2TS U2521 ( .A(n2924), .B(n2928), .Y(n2930) );
NOR2X2TS U2522 ( .A(n3526), .B(n3528), .Y(n3439) );
NAND2X6TS U2523 ( .A(n6568), .B(FPMULT_Op_MX[12]), .Y(n3467) );
INVX4TS U2524 ( .A(n2945), .Y(n2962) );
CMPR32X2TS U2525 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .B(n2730), .C(n2729), .CO(n4238), .S(n2724) );
CMPR32X2TS U2526 ( .A(n3449), .B(n5644), .C(n6595), .CO(n3456), .S(n3444) );
INVX2TS U2527 ( .A(n3147), .Y(n3114) );
NOR2X2TS U2528 ( .A(DP_OP_501J223_127_5235_n903), .B(n2291), .Y(n3528) );
XNOR2X2TS U2529 ( .A(n4155), .B(n4154), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
INVX6TS U2530 ( .A(n2931), .Y(n2208) );
NAND2XLTS U2531 ( .A(n3079), .B(n3076), .Y(n2811) );
NAND2X1TS U2532 ( .A(n3075), .B(n2808), .Y(n2788) );
NAND2X1TS U2533 ( .A(n4200), .B(n4199), .Y(n4201) );
NOR2X4TS U2534 ( .A(n3211), .B(n3213), .Y(n3215) );
INVX2TS U2535 ( .A(n3506), .Y(n3511) );
BUFX4TS U2536 ( .A(n6749), .Y(n2291) );
OAI21X2TS U2537 ( .A0(n4150), .A1(n4149), .B0(n4148), .Y(n4155) );
OR2X2TS U2538 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .Y(n2244) );
INVX4TS U2539 ( .A(n2194), .Y(n6595) );
AND2X2TS U2540 ( .A(n2722), .B(n2739), .Y(n3061) );
NOR2X1TS U2541 ( .A(n3258), .B(n3257), .Y(n3221) );
INVX4TS U2542 ( .A(n6771), .Y(n2315) );
NAND2X2TS U2543 ( .A(n4095), .B(n4094), .Y(n4141) );
NOR2X6TS U2544 ( .A(n3126), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n3145)
);
OR2X2TS U2545 ( .A(FPMULT_Op_MY[13]), .B(n2283), .Y(n2444) );
NAND2X2TS U2546 ( .A(n3126), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n3143)
);
NAND2X2TS U2547 ( .A(n2676), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(n2836)
);
NAND2X1TS U2548 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .Y(n3507) );
NOR2X6TS U2549 ( .A(n2841), .B(n2840), .Y(n2923) );
INVX2TS U2550 ( .A(n3431), .Y(n3442) );
NAND2X2TS U2551 ( .A(n6594), .B(n6587), .Y(n3453) );
NAND2X2TS U2552 ( .A(n6593), .B(n2286), .Y(n3447) );
NOR2X1TS U2553 ( .A(n2856), .B(n2855), .Y(n2847) );
NOR2X6TS U2554 ( .A(n2838), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n2932)
);
NOR2X6TS U2555 ( .A(n2676), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(n2840)
);
OR2X4TS U2556 ( .A(n2807), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n3079) );
NAND2X2TS U2557 ( .A(n4044), .B(n4043), .Y(n4148) );
INVX4TS U2558 ( .A(n2226), .Y(n6593) );
OAI21X1TS U2559 ( .A0(n2862), .A1(n2855), .B0(n2858), .Y(n2846) );
NAND2X1TS U2560 ( .A(n3198), .B(n3195), .Y(n3186) );
NAND2X1TS U2561 ( .A(n3088), .B(n3116), .Y(n3089) );
NAND2X1TS U2562 ( .A(n3158), .B(n3165), .Y(n3159) );
AOI21X2TS U2563 ( .A0(n3153), .A1(n3152), .B0(n3151), .Y(n3160) );
NAND2X2TS U2564 ( .A(n4031), .B(n4030), .Y(n4037) );
NOR2X2TS U2565 ( .A(n2867), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n2871) );
NAND2X1TS U2566 ( .A(n2826), .B(n2823), .Y(n2820) );
OR2X2TS U2567 ( .A(n4040), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .Y(
n4043) );
NAND2X2TS U2568 ( .A(n2698), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n2737)
);
OR2X4TS U2569 ( .A(n2637), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n4200) );
NOR2X2TS U2570 ( .A(n2861), .B(n2856), .Y(n2863) );
NAND2X4TS U2571 ( .A(n3203), .B(n3202), .Y(n3260) );
NAND2X1TS U2572 ( .A(n2784), .B(n2800), .Y(n2785) );
NAND2X2TS U2573 ( .A(n2622), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n2732) );
NAND2X2TS U2574 ( .A(n2637), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n4199) );
NAND2X2TS U2575 ( .A(n2719), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n2734) );
XOR2X2TS U2576 ( .A(n2779), .B(n2688), .Y(n2689) );
INVX6TS U2577 ( .A(n2667), .Y(n2649) );
INVX2TS U2578 ( .A(n2804), .Y(n2779) );
OAI21X2TS U2579 ( .A0(n3166), .A1(n2200), .B0(n3165), .Y(n3167) );
NAND2X2TS U2580 ( .A(n3178), .B(n3177), .Y(n3181) );
INVX2TS U2581 ( .A(n2823), .Y(n2824) );
OR2X4TS U2582 ( .A(n2819), .B(n2818), .Y(n2826) );
ADDFHX2TS U2583 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]), .B(
n2849), .CI(n2848), .CO(n2850), .S(n2832) );
NAND2X4TS U2584 ( .A(n2593), .B(n2592), .Y(n2625) );
NAND2X2TS U2585 ( .A(n2607), .B(n2606), .Y(n2661) );
NAND2X2TS U2586 ( .A(n2598), .B(n2597), .Y(n2603) );
NAND2X2TS U2587 ( .A(n2653), .B(n2652), .Y(n2660) );
AND2X6TS U2588 ( .A(n2585), .B(n2611), .Y(n2404) );
NOR2X4TS U2589 ( .A(n2602), .B(n2604), .Y(n2666) );
NOR2X4TS U2590 ( .A(n2652), .B(n2653), .Y(n2662) );
INVX4TS U2591 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(n3329) );
OR2X4TS U2592 ( .A(n2680), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .Y(n2696) );
INVX2TS U2593 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n3085) );
INVX2TS U2594 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n2781) );
INVX2TS U2595 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n2672)
);
INVX3TS U2596 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n2605)
);
INVX4TS U2597 ( .A(FPMULT_Sgf_operation_Result[0]), .Y(n2700) );
INVX2TS U2598 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n2579) );
INVX2TS U2599 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n2651)
);
OR2X1TS U2600 ( .A(n4135), .B(n4134), .Y(n4158) );
INVX6TS U2601 ( .A(n2211), .Y(n2872) );
XNOR2X1TS U2602 ( .A(n4115), .B(n4114), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
NOR2XLTS U2603 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n3297) );
XNOR2X1TS U2604 ( .A(n2395), .B(n3914), .Y(n3866) );
NOR2X1TS U2605 ( .A(n4855), .B(n5742), .Y(n4846) );
AOI21X1TS U2606 ( .A0(n2196), .A1(n3715), .B0(n3710), .Y(n3713) );
XNOR2X1TS U2607 ( .A(n3821), .B(n3820), .Y(n2202) );
INVX2TS U2608 ( .A(n3635), .Y(n3469) );
NAND2X2TS U2609 ( .A(n2584), .B(n2703), .Y(n2615) );
NAND2X2TS U2610 ( .A(n3091), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n3144) );
XNOR2X1TS U2611 ( .A(n2395), .B(n3963), .Y(n3953) );
XNOR2X1TS U2612 ( .A(n3963), .B(n2205), .Y(n3868) );
NAND2X1TS U2613 ( .A(FPMULT_Op_MY[13]), .B(n2220), .Y(n3441) );
NOR2X1TS U2614 ( .A(n3848), .B(n2396), .Y(n3832) );
NAND2X2TS U2615 ( .A(n2738), .B(n2737), .Y(n2740) );
INVX2TS U2616 ( .A(n2202), .Y(n2296) );
NOR2X1TS U2617 ( .A(n2486), .B(n3705), .Y(DP_OP_501J223_127_5235_n250) );
OAI21XLTS U2618 ( .A0(n4377), .A1(n6197), .B0(n4376), .Y(n4378) );
NOR2X4TS U2619 ( .A(n2196), .B(n3440), .Y(n3476) );
OAI21XLTS U2620 ( .A0(n4811), .A1(n6799), .B0(n2256), .Y(n4812) );
OAI22X1TS U2621 ( .A0(n2320), .A1(n5545), .B0(n2379), .B1(n5544), .Y(
DP_OP_502J223_128_4510_n180) );
BUFX8TS U2622 ( .A(n3931), .Y(n2395) );
CMPR42X1TS U2623 ( .A(DP_OP_500J223_126_4510_n150), .B(
DP_OP_500J223_126_4510_n157), .C(DP_OP_500J223_126_4510_n185), .D(
DP_OP_500J223_126_4510_n164), .ICI(DP_OP_500J223_126_4510_n171), .S(
DP_OP_500J223_126_4510_n120), .ICO(DP_OP_500J223_126_4510_n118), .CO(
DP_OP_500J223_126_4510_n119) );
OR3X1TS U2624 ( .A(n4941), .B(n4946), .C(n4944), .Y(n4943) );
NOR2X4TS U2625 ( .A(n3020), .B(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(
n5909) );
NAND2X2TS U2626 ( .A(FPMULT_Op_MX[15]), .B(n6569), .Y(n3635) );
CLKINVX6TS U2627 ( .A(n2324), .Y(n2325) );
OR2X1TS U2628 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2262) );
OAI21XLTS U2629 ( .A0(n5222), .A1(n5221), .B0(n5220), .Y(n5223) );
NOR2X1TS U2630 ( .A(n4175), .B(n3334), .Y(n3335) );
INVX2TS U2631 ( .A(n3369), .Y(n2377) );
AOI21X2TS U2632 ( .A0(n6246), .A1(n2944), .B0(n2943), .Y(n6242) );
CMPR42X1TS U2633 ( .A(DP_OP_502J223_128_4510_n162), .B(
DP_OP_502J223_128_4510_n155), .C(DP_OP_502J223_128_4510_n107), .D(
DP_OP_502J223_128_4510_n111), .ICI(DP_OP_502J223_128_4510_n108), .S(
DP_OP_502J223_128_4510_n105), .ICO(DP_OP_502J223_128_4510_n103), .CO(
DP_OP_502J223_128_4510_n104) );
NOR2XLTS U2634 ( .A(n6843), .B(FPADDSUB_DMP_SFG[21]), .Y(n4411) );
OAI21X1TS U2635 ( .A0(n6095), .A1(n6089), .B0(n6090), .Y(n6066) );
INVX2TS U2636 ( .A(n2478), .Y(n2285) );
NOR2XLTS U2637 ( .A(n3566), .B(n3557), .Y(n3558) );
NOR2X2TS U2638 ( .A(DP_OP_501J223_127_5235_n121), .B(n3547), .Y(n3565) );
NOR2XLTS U2639 ( .A(n5652), .B(n5651), .Y(n4478) );
OR2X1TS U2640 ( .A(DP_OP_501J223_127_5235_n477), .B(n3741), .Y(n2494) );
OAI21X1TS U2641 ( .A0(n6118), .A1(n4403), .B0(n4402), .Y(n6138) );
NOR2X1TS U2642 ( .A(n3343), .B(n3344), .Y(n3347) );
NOR2X2TS U2643 ( .A(n3413), .B(DP_OP_499J223_125_1651_n297), .Y(n3403) );
AOI21X1TS U2644 ( .A0(n3771), .A1(n3775), .B0(n3753), .Y(n3754) );
NOR2X1TS U2645 ( .A(n3737), .B(n3736), .Y(n3809) );
OR2X1TS U2646 ( .A(n3497), .B(n3496), .Y(n2495) );
OR2X1TS U2647 ( .A(n5182), .B(n5181), .Y(n5605) );
BUFX3TS U2648 ( .A(n4985), .Y(n5118) );
OAI21XLTS U2649 ( .A0(n5816), .A1(n5817), .B0(n4764), .Y(intadd_514_A_2_) );
AOI21X1TS U2650 ( .A0(n3571), .A1(n3575), .B0(n3562), .Y(n3563) );
OAI21XLTS U2651 ( .A0(n5664), .A1(n5663), .B0(n5665), .Y(n4965) );
BUFX3TS U2652 ( .A(n4697), .Y(n4708) );
AND2X2TS U2653 ( .A(n6342), .B(n6350), .Y(n4994) );
OAI21X1TS U2654 ( .A0(n5594), .A1(n5597), .B0(n5595), .Y(n5592) );
AOI31X1TS U2655 ( .A0(n6364), .A1(n6768), .A2(intadd_517_B_1_), .B0(n6413),
.Y(n4558) );
AOI21X2TS U2656 ( .A0(n3986), .A1(n2475), .B0(n3959), .Y(n3983) );
CLKINVX3TS U2657 ( .A(n2577), .Y(n5291) );
NAND2X1TS U2658 ( .A(n4028), .B(n4027), .Y(n4029) );
OAI21X1TS U2659 ( .A0(n5573), .A1(n5565), .B0(n5570), .Y(n5569) );
CLKINVX3TS U2660 ( .A(n2238), .Y(n2383) );
CLKBUFX2TS U2661 ( .A(n4483), .Y(n2364) );
CLKINVX3TS U2662 ( .A(n5478), .Y(n6260) );
BUFX3TS U2663 ( .A(n5937), .Y(n6624) );
CLKINVX3TS U2664 ( .A(n6550), .Y(n5052) );
OAI21XLTS U2665 ( .A0(n5762), .A1(n4930), .B0(n4929), .Y(mult_x_311_n14) );
NOR2XLTS U2666 ( .A(n6664), .B(n6648), .Y(n6649) );
INVX2TS U2667 ( .A(n6615), .Y(n6617) );
BUFX3TS U2668 ( .A(n4723), .Y(n6414) );
CLKBUFX2TS U2669 ( .A(n6382), .Y(n6380) );
OAI21XLTS U2670 ( .A0(n6433), .A1(n6838), .B0(n6436), .Y(n6434) );
BUFX3TS U2671 ( .A(n4554), .Y(n6444) );
INVX1TS U2672 ( .A(result_add_subt[23]), .Y(n6524) );
INVX1TS U2673 ( .A(result_add_subt[25]), .Y(n6527) );
OAI211XLTS U2674 ( .A0(n2363), .A1(n6887), .B0(n4634), .C0(n4633), .Y(n1515)
);
XOR2X2TS U2675 ( .A(n3342), .B(n2265), .Y(FPMULT_Sgf_operation_Result[47])
);
XOR2X1TS U2676 ( .A(n3430), .B(n2264), .Y(FPMULT_Sgf_operation_Result[46])
);
OAI211XLTS U2677 ( .A0(n5087), .A1(n6426), .B0(n5071), .C0(n5070), .Y(n1920)
);
OAI211XLTS U2678 ( .A0(n5116), .A1(n6401), .B0(n5081), .C0(n5080), .Y(n1938)
);
OAI21XLTS U2679 ( .A0(n5876), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
n4575), .Y(n1620) );
CLKINVX3TS U2680 ( .A(n5478), .Y(n6956) );
OAI211XLTS U2681 ( .A0(n5110), .A1(n2449), .B0(n5089), .C0(n5088), .Y(n1931)
);
OAI21XLTS U2682 ( .A0(n6371), .A1(n6362), .B0(n4686), .Y(n2131) );
OAI211XLTS U2683 ( .A0(n5087), .A1(n6838), .B0(n5049), .C0(n5048), .Y(n1913)
);
OAI211XLTS U2684 ( .A0(n5067), .A1(n6441), .B0(n5066), .C0(n5065), .Y(n1910)
);
OAI21XLTS U2685 ( .A0(n5393), .A1(n5389), .B0(n5233), .Y(n1811) );
OAI211XLTS U2686 ( .A0(n2361), .A1(n6878), .B0(n4608), .C0(n4607), .Y(n1524)
);
OAI211XLTS U2687 ( .A0(n5110), .A1(n6421), .B0(n5061), .C0(n5060), .Y(n1923)
);
OAI211XLTS U2688 ( .A0(n2362), .A1(n6891), .B0(n4631), .C0(n4630), .Y(n1511)
);
OAI211XLTS U2689 ( .A0(n5067), .A1(n2419), .B0(n5029), .C0(n5028), .Y(n1835)
);
OAI211XLTS U2690 ( .A0(n5393), .A1(n5381), .B0(n5336), .C0(n5335), .Y(n1808)
);
NOR2X2TS U2691 ( .A(n2491), .B(n2217), .Y(n7067) );
OAI21XLTS U2692 ( .A0(n2277), .A1(n5436), .B0(n5421), .Y(n1221) );
OAI21XLTS U2693 ( .A0(n2525), .A1(n5436), .B0(n5431), .Y(n1241) );
OAI21XLTS U2694 ( .A0(n2230), .A1(n5433), .B0(n5413), .Y(n1257) );
OAI21XLTS U2695 ( .A0(n6692), .A1(n5433), .B0(n2578), .Y(n1275) );
OAI21XLTS U2696 ( .A0(n2275), .A1(n5433), .B0(n5408), .Y(n1296) );
OAI21XLTS U2697 ( .A0(n2273), .A1(n5312), .B0(n5307), .Y(n1312) );
OAI21XLTS U2698 ( .A0(n7060), .A1(n6554), .B0(n5145), .Y(n1356) );
OAI21XLTS U2699 ( .A0(n2270), .A1(n5312), .B0(n5296), .Y(n1374) );
OAI21XLTS U2700 ( .A0(n2432), .A1(n5310), .B0(n5297), .Y(n1389) );
OAI21XLTS U2701 ( .A0(n2279), .A1(n5310), .B0(n5287), .Y(n1404) );
OAI21XLTS U2702 ( .A0(n4710), .A1(n6832), .B0(n4698), .Y(op_result[12]) );
OAI21XLTS U2703 ( .A0(n4670), .A1(n6644), .B0(n4702), .Y(op_result[19]) );
AO21X4TS U2704 ( .A0(n3505), .A1(n3439), .B0(n3438), .Y(n2196) );
OR2X4TS U2705 ( .A(n2844), .B(n2843), .Y(n2197) );
INVX2TS U2706 ( .A(n4748), .Y(n2301) );
INVX2TS U2707 ( .A(n6005), .Y(n2356) );
NAND2X2TS U2708 ( .A(n3122), .B(n3121), .Y(n2200) );
CLKINVX3TS U2709 ( .A(n2468), .Y(n6455) );
INVX2TS U2710 ( .A(n2224), .Y(n2322) );
INVX2TS U2711 ( .A(n2243), .Y(n2308) );
OR2X1TS U2712 ( .A(n2977), .B(n4235), .Y(n2203) );
OR2X2TS U2713 ( .A(n3006), .B(n3005), .Y(n2204) );
INVX2TS U2714 ( .A(n3253), .Y(n3345) );
XNOR2X1TS U2715 ( .A(n4337), .B(n4336), .Y(n4338) );
BUFX8TS U2716 ( .A(n4337), .Y(n4181) );
BUFX12TS U2717 ( .A(n4337), .Y(n2375) );
MX2X2TS U2718 ( .A(FPMULT_P_Sgf[34]), .B(n4463), .S0(n6958), .Y(n1563) );
INVX2TS U2719 ( .A(n3337), .Y(n3428) );
CLKMX2X2TS U2720 ( .A(FPMULT_P_Sgf[28]), .B(n4424), .S0(n6290), .Y(n1557) );
BUFX16TS U2721 ( .A(n3163), .Y(n3406) );
CLKMX2X2TS U2722 ( .A(FPMULT_P_Sgf[27]), .B(n4320), .S0(n6956), .Y(n1556) );
CLKMX2X2TS U2723 ( .A(FPMULT_P_Sgf[26]), .B(n5904), .S0(n6290), .Y(n1555) );
CLKMX2X2TS U2724 ( .A(FPMULT_P_Sgf[25]), .B(n5914), .S0(n6958), .Y(n1554) );
CLKMX2X2TS U2725 ( .A(FPMULT_P_Sgf[23]), .B(n5929), .S0(n6956), .Y(n1552) );
CLKMX2X2TS U2726 ( .A(FPMULT_P_Sgf[21]), .B(n6311), .S0(n6956), .Y(n1550) );
CLKMX2X2TS U2727 ( .A(FPMULT_P_Sgf[22]), .B(n6281), .S0(n6956), .Y(n1551) );
CLKMX2X2TS U2728 ( .A(FPMULT_P_Sgf[20]), .B(n6302), .S0(n6956), .Y(n1549) );
CLKMX2X2TS U2729 ( .A(FPMULT_P_Sgf[18]), .B(n6291), .S0(n6957), .Y(n1547) );
INVX2TS U2730 ( .A(n3588), .Y(n3597) );
OAI21X1TS U2731 ( .A0(n6305), .A1(n6304), .B0(n6303), .Y(n6310) );
NOR2X2TS U2732 ( .A(n2754), .B(n3052), .Y(n2757) );
NOR2X4TS U2733 ( .A(n3583), .B(n3578), .Y(n3570) );
NOR2X4TS U2734 ( .A(DP_OP_499J223_125_1651_n203), .B(n3110), .Y(n3132) );
NOR2X4TS U2735 ( .A(DP_OP_501J223_127_5235_n154), .B(
DP_OP_501J223_127_5235_n162), .Y(n3599) );
XNOR2X1TS U2736 ( .A(n3777), .B(n3776), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9) );
XNOR2X2TS U2737 ( .A(n2997), .B(n2814), .Y(n2982) );
OAI21X2TS U2738 ( .A0(n5500), .A1(n5482), .B0(n5481), .Y(n5486) );
OAI21X1TS U2739 ( .A0(n5500), .A1(n5492), .B0(n5491), .Y(n5496) );
NOR2X2TS U2740 ( .A(n2325), .B(n3699), .Y(DP_OP_501J223_127_5235_n232) );
ADDHX2TS U2741 ( .A(n3669), .B(n3668), .CO(DP_OP_501J223_127_5235_n150), .S(
DP_OP_501J223_127_5235_n151) );
INVX2TS U2742 ( .A(n4205), .Y(n3410) );
CLKMX2X2TS U2743 ( .A(FPMULT_Add_result[22]), .B(n5857), .S0(n5931), .Y(
n1598) );
CLKMX2X2TS U2744 ( .A(FPMULT_Add_result[21]), .B(n5859), .S0(n5873), .Y(
n1599) );
INVX2TS U2745 ( .A(n4204), .Y(DP_OP_499J223_125_1651_n301) );
ADDHX2TS U2746 ( .A(n3676), .B(n3675), .CO(n3671), .S(
DP_OP_501J223_127_5235_n178) );
XOR2X1TS U2747 ( .A(n6166), .B(n6165), .Y(n6171) );
OR2X2TS U2748 ( .A(n3739), .B(n3738), .Y(n2500) );
INVX4TS U2749 ( .A(n5315), .Y(n5389) );
INVX2TS U2750 ( .A(n4220), .Y(DP_OP_499J223_125_1651_n302) );
INVX4TS U2751 ( .A(n6629), .Y(n2374) );
CLKMX2X2TS U2752 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n5933), .Y(n1595) );
NOR2X4TS U2753 ( .A(n6521), .B(n5386), .Y(n5232) );
OR2X4TS U2754 ( .A(n5392), .B(n5236), .Y(n5237) );
OR2X2TS U2755 ( .A(DP_OP_500J223_126_4510_n129), .B(
DP_OP_500J223_126_4510_n135), .Y(n5591) );
INVX1TS U2756 ( .A(n5143), .Y(n5144) );
NOR2X4TS U2757 ( .A(n2874), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n2945)
);
ADDFHX1TS U2758 ( .A(n3956), .B(n3955), .CI(n3954), .CO(n3960), .S(n3948) );
INVX4TS U2759 ( .A(n2322), .Y(n5424) );
NAND4BX1TS U2760 ( .AN(n6018), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n6019) );
AOI2BB1X1TS U2761 ( .A0N(n2340), .A1N(FPADDSUB_LZD_output_NRM2_EW[1]), .B0(
n6015), .Y(n1409) );
INVX4TS U2762 ( .A(n2322), .Y(n5434) );
AOI211X1TS U2763 ( .A0(n5231), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n4818),
.C0(n4817), .Y(n4821) );
CLKMX2X2TS U2764 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n5933), .Y(n1588) );
OR2X2TS U2765 ( .A(DP_OP_502J223_128_4510_n129), .B(
DP_OP_502J223_128_4510_n135), .Y(n2472) );
NAND2X2TS U2766 ( .A(n3655), .B(n3654), .Y(n3656) );
AOI31X2TS U2767 ( .A0(n5214), .A1(n5213), .A2(n5212), .B0(n2341), .Y(n6016)
);
AOI2BB2X1TS U2768 ( .B0(FPSENCOS_d_ff2_X[30]), .B1(n6435), .A0N(n6435),
.A1N(FPSENCOS_d_ff2_X[30]), .Y(n4557) );
INVX4TS U2769 ( .A(n2577), .Y(n5308) );
AOI2BB2X1TS U2770 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n6466), .A0N(n6466),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n6467) );
INVX4TS U2771 ( .A(n2577), .Y(n5313) );
NOR2X4TS U2772 ( .A(n6706), .B(n6668), .Y(n2224) );
OAI22X1TS U2773 ( .A0(n3901), .A1(n3868), .B0(n2368), .B1(
DP_OP_501J223_127_5235_n723), .Y(n3912) );
BUFX4TS U2774 ( .A(n4995), .Y(n6550) );
AOI2BB2X1TS U2775 ( .B0(n6438), .B1(n6432), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n6464), .Y(n1947) );
INVX3TS U2776 ( .A(n3653), .Y(n3655) );
AOI2BB2X1TS U2777 ( .B0(n6444), .B1(n6460), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n6464), .Y(n1849) );
INVX2TS U2778 ( .A(n3626), .Y(n3628) );
AO21X1TS U2779 ( .A0(FPSENCOS_d_ff3_LUT_out[13]), .A1(n6408), .B0(n6366),
.Y(n2121) );
OAI21X1TS U2780 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n6455), .B0(n5013),
.Y(n4760) );
NAND2BX1TS U2781 ( .AN(n3900), .B(n2308), .Y(n3893) );
NAND2X4TS U2782 ( .A(n3521), .B(n3520), .Y(n3654) );
XOR2X1TS U2783 ( .A(n6756), .B(n6360), .Y(n2137) );
AO21X1TS U2784 ( .A0(n5660), .A1(n5659), .B0(n5661), .Y(n5449) );
OAI2BB2XLTS U2785 ( .B0(n6442), .B1(n6396), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[0]), .Y(n2004) );
OR2X4TS U2786 ( .A(n3937), .B(FPMULT_Op_MY[11]), .Y(n3522) );
AO21X1TS U2787 ( .A0(n5770), .A1(n5769), .B0(n5771), .Y(n4895) );
OAI2BB2XLTS U2788 ( .B0(n6442), .B1(n6399), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[2]), .Y(n2000) );
OAI211X1TS U2789 ( .A0(n5460), .A1(n6787), .B0(n5459), .C0(n5458), .Y(n1693)
);
AOI31X1TS U2790 ( .A0(n4692), .A1(n5218), .A2(n4691), .B0(n4690), .Y(n4693)
);
OAI21X1TS U2791 ( .A0(n4470), .A1(n6007), .B0(n6006), .Y(n4471) );
OAI21X1TS U2792 ( .A0(n6008), .A1(n6007), .B0(n6006), .Y(n6010) );
AO22X1TS U2793 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1435) );
INVX4TS U2794 ( .A(n5637), .Y(n2350) );
AO22X1TS U2795 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1440) );
AO22X1TS U2796 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1425) );
AO22X1TS U2797 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n6003),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1455) );
AO22X1TS U2798 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1430) );
OAI21X1TS U2799 ( .A0(n6185), .A1(n6100), .B0(n6099), .Y(n6105) );
AO22X1TS U2800 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1445) );
AO22X1TS U2801 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n6003),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1420) );
AO22X1TS U2802 ( .A0(n6710), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n6709),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1450) );
AO21X1TS U2803 ( .A0(n5448), .A1(n5446), .B0(n5445), .Y(n4972) );
AO22X1TS U2804 ( .A0(n6635), .A1(n6622), .B0(n6625), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1474) );
AO22X1TS U2805 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n6382), .B1(
Data_1[15]), .Y(n2097) );
INVX4TS U2806 ( .A(n6444), .Y(n6442) );
AO22X1TS U2807 ( .A0(n6710), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n6709), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1359) );
OAI21X1TS U2808 ( .A0(n6185), .A1(n6052), .B0(n6051), .Y(n6056) );
OAI21X1TS U2809 ( .A0(n6185), .A1(n6029), .B0(n6028), .Y(n6033) );
AO22X1TS U2810 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n6382), .B1(
Data_1[18]), .Y(n2094) );
AO22X1TS U2811 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2326), .Y(n5943) );
INVX4TS U2812 ( .A(n5935), .Y(n2382) );
AO22X4TS U2813 ( .A0(operation[1]), .A1(n6336), .B0(begin_operation), .B1(
n4994), .Y(n5461) );
AND2X2TS U2814 ( .A(n5207), .B(n4812), .Y(n5215) );
AO22X1TS U2815 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2326), .B0(
FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n5957), .Y(n5938) );
AOI31X1TS U2816 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(n5207), .A2(n6758),
.B0(n5206), .Y(n5214) );
AO22X1TS U2817 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2342), .Y(n5950) );
AO22X1TS U2818 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2342), .Y(n5953) );
AO22X1TS U2819 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n2342), .Y(n5941) );
AND3X2TS U2820 ( .A(n5276), .B(n5275), .C(n5274), .Y(n5396) );
AO21X1TS U2821 ( .A0(n4468), .A1(n4467), .B0(n4466), .Y(intadd_515_B_6_) );
INVX8TS U2822 ( .A(n2368), .Y(n2205) );
INVX4TS U2823 ( .A(n6439), .Y(n6413) );
INVX4TS U2824 ( .A(n5265), .Y(n5372) );
INVX4TS U2825 ( .A(n5265), .Y(n5379) );
INVX4TS U2826 ( .A(n2815), .Y(n2825) );
CLKINVX1TS U2827 ( .A(n6339), .Y(n6341) );
CLKBUFX2TS U2828 ( .A(n3288), .Y(n2326) );
INVX4TS U2829 ( .A(FPADDSUB_left_right_SHT2), .Y(n5984) );
INVX4TS U2830 ( .A(n5876), .Y(n5899) );
INVX4TS U2831 ( .A(n6392), .Y(n6528) );
AND2X4TS U2832 ( .A(n4473), .B(n4485), .Y(n5637) );
INVX2TS U2833 ( .A(n3542), .Y(n3544) );
INVX4TS U2834 ( .A(DP_OP_501J223_127_5235_n630), .Y(n3900) );
INVX4TS U2835 ( .A(n6392), .Y(n6539) );
NOR2X1TS U2836 ( .A(n5205), .B(FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n5206) );
NAND2BX1TS U2837 ( .AN(n5780), .B(n2287), .Y(n5785) );
INVX6TS U2838 ( .A(n3467), .Y(n3482) );
INVX4TS U2839 ( .A(n3453), .Y(n3433) );
NAND2X1TS U2840 ( .A(n5326), .B(FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n5322) );
INVX4TS U2841 ( .A(n6354), .Y(n6022) );
OAI21X1TS U2842 ( .A0(n4371), .A1(n4517), .B0(n4370), .Y(n4372) );
OAI21X1TS U2843 ( .A0(n4529), .A1(n4533), .B0(n4530), .Y(n4255) );
INVX4TS U2844 ( .A(n6354), .Y(n6730) );
AOI2BB1X1TS U2845 ( .A0N(n5204), .A1N(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n5205) );
INVX4TS U2846 ( .A(n5340), .Y(n5326) );
OR2X2TS U2847 ( .A(n4133), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .Y(
n4134) );
NOR2X1TS U2848 ( .A(n2554), .B(FPADDSUB_intDY_EWSW[16]), .Y(n2507) );
ADDHX2TS U2849 ( .A(n2315), .B(n6764), .CO(n3449), .S(n3440) );
NAND3BX1TS U2850 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n4660),
.C(n4992), .Y(n4661) );
CLKMX2X2TS U2851 ( .A(n6936), .B(n6935), .S0(n6917), .Y(n1574) );
NAND2BX1TS U2852 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n2537) );
OAI21X1TS U2853 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n2467), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n2532) );
CLKMX2X2TS U2854 ( .A(n6932), .B(n6931), .S0(n6916), .Y(n1561) );
INVX4TS U2855 ( .A(n2248), .Y(n2286) );
ADDHX2TS U2856 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .CO(n3729), .S(
n3728) );
CLKMX2X2TS U2857 ( .A(n6950), .B(n6949), .S0(n6917), .Y(n1570) );
CLKMX2X2TS U2858 ( .A(n6954), .B(n6953), .S0(n6917), .Y(n1569) );
CLKMX2X2TS U2859 ( .A(n6940), .B(n6939), .S0(n6917), .Y(n1571) );
CLKMX2X2TS U2860 ( .A(n6930), .B(n6929), .S0(n6916), .Y(n1566) );
CLKMX2X2TS U2861 ( .A(n6938), .B(n6937), .S0(n6916), .Y(n1567) );
CLKMX2X2TS U2862 ( .A(n6928), .B(n6927), .S0(n6917), .Y(n1572) );
CLKMX2X2TS U2863 ( .A(n6934), .B(n6933), .S0(n6916), .Y(n1568) );
INVX2TS U2864 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n2849) );
CLKMX2X2TS U2865 ( .A(n6926), .B(n6925), .S0(n6924), .Y(n1694) );
INVX2TS U2866 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(n2726)
);
CLKMX2X2TS U2867 ( .A(n6948), .B(n6947), .S0(n6916), .Y(n1565) );
CLKMX2X2TS U2868 ( .A(n6952), .B(n6951), .S0(n6917), .Y(n1573) );
INVX2TS U2869 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(n2830)
);
INVX2TS U2870 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n2829) );
INVX2TS U2871 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(n3223)
);
INVX4TS U2872 ( .A(operation[1]), .Y(n6342) );
XOR2X2TS U2873 ( .A(n3421), .B(n3420), .Y(FPMULT_Sgf_operation_Result[44])
);
XOR2X2TS U2874 ( .A(n3416), .B(DP_OP_499J223_125_1651_n297), .Y(
FPMULT_Sgf_operation_Result[40]) );
AOI21X2TS U2875 ( .A0(n4181), .A1(n3404), .B0(n3403), .Y(n3405) );
XOR2X2TS U2876 ( .A(n4448), .B(n4447), .Y(n4449) );
INVX3TS U2877 ( .A(n3357), .Y(n3418) );
NOR2X2TS U2878 ( .A(n3417), .B(n3420), .Y(n3359) );
NOR2X2TS U2879 ( .A(n3422), .B(DP_OP_499J223_125_1651_n299), .Y(n3409) );
XNOR2X2TS U2880 ( .A(n3286), .B(n3285), .Y(n3287) );
INVX3TS U2881 ( .A(n4420), .Y(n3060) );
AOI21X2TS U2882 ( .A0(n3571), .A1(n2429), .B0(n2457), .Y(n3560) );
NAND2X2TS U2883 ( .A(n3570), .B(n3549), .Y(n3551) );
AO21X1TS U2884 ( .A0(n3562), .A1(n3559), .B0(n3558), .Y(n2457) );
NOR2X2TS U2885 ( .A(n3565), .B(n3557), .Y(n3559) );
OR2X2TS U2886 ( .A(n3137), .B(DP_OP_496J223_122_3236_n147), .Y(n3139) );
OAI21X1TS U2887 ( .A0(n6252), .A1(n6251), .B0(n6250), .Y(n6257) );
NAND2X2TS U2888 ( .A(DP_OP_501J223_127_5235_n173), .B(
DP_OP_501J223_127_5235_n180), .Y(n3608) );
OR2X4TS U2889 ( .A(DP_OP_501J223_127_5235_n163), .B(
DP_OP_501J223_127_5235_n172), .Y(n3501) );
OAI21X1TS U2890 ( .A0(n3798), .A1(n3794), .B0(n3795), .Y(n3793) );
OR2X2TS U2891 ( .A(n3004), .B(n4232), .Y(n2471) );
NOR2X1TS U2892 ( .A(n3326), .B(n3350), .Y(n3327) );
OAI21X1TS U2893 ( .A0(n3787), .A1(n3769), .B0(n3768), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11) );
OAI211X1TS U2894 ( .A0(n5400), .A1(n5399), .B0(n5398), .C0(n5397), .Y(n1809)
);
INVX2TS U2895 ( .A(n2213), .Y(n4232) );
OAI21X2TS U2896 ( .A0(n3983), .A1(n3979), .B0(n3980), .Y(n3978) );
ADDFHX2TS U2897 ( .A(n3652), .B(n3651), .CI(n3650), .CO(
DP_OP_501J223_127_5235_n126), .S(DP_OP_501J223_127_5235_n127) );
OAI211X1TS U2898 ( .A0(n5399), .A1(n5349), .B0(n5321), .C0(n5320), .Y(n1804)
);
NOR2X4TS U2899 ( .A(n3003), .B(n3002), .Y(n2994) );
OAI211X1TS U2900 ( .A0(n5385), .A1(n5237), .B0(n5332), .C0(n5331), .Y(n1787)
);
INVX2TS U2901 ( .A(n3612), .Y(n3500) );
OAI211X1TS U2902 ( .A0(n5389), .A1(n5349), .B0(n5245), .C0(n5244), .Y(n1805)
);
OAI211X1TS U2903 ( .A0(n5237), .A1(n5349), .B0(n5334), .C0(n5333), .Y(n1803)
);
OAI211X1TS U2904 ( .A0(n5381), .A1(n5349), .B0(n5348), .C0(n5347), .Y(n1802)
);
OAI21X1TS U2905 ( .A0(n3774), .A1(n3765), .B0(n3764), .Y(n3766) );
OAI211X1TS U2906 ( .A0(n5381), .A1(n5370), .B0(n5369), .C0(n5368), .Y(n1801)
);
OAI211X1TS U2907 ( .A0(n5389), .A1(n5365), .B0(n5281), .C0(n5280), .Y(n1807)
);
INVX2TS U2908 ( .A(n3763), .Y(n3775) );
OAI211X1TS U2909 ( .A0(n5399), .A1(n5377), .B0(n5376), .C0(n5375), .Y(n1798)
);
NOR2X2TS U2910 ( .A(n3789), .B(n3794), .Y(n3744) );
AO22X1TS U2911 ( .A0(n4271), .A1(n4499), .B0(FPADDSUB_ADD_OVRFLW_NRM), .B1(
n6711), .Y(n1351) );
OAI211X1TS U2912 ( .A0(n5389), .A1(n5261), .B0(n5257), .C0(n5256), .Y(n1793)
);
OAI211X1TS U2913 ( .A0(n5389), .A1(n5353), .B0(n5268), .C0(n5267), .Y(n1795)
);
XOR2X1TS U2914 ( .A(n5584), .B(n5583), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
OAI211X1TS U2915 ( .A0(n5399), .A1(n5353), .B0(n5352), .C0(n5351), .Y(n1794)
);
OAI211X1TS U2916 ( .A0(n5380), .A1(n5399), .B0(n5357), .C0(n5356), .Y(n1791)
);
OAI211X1TS U2917 ( .A0(n5380), .A1(n5389), .B0(n5264), .C0(n5263), .Y(n1792)
);
OAI21X2TS U2918 ( .A0(n3789), .A1(n3795), .B0(n3790), .Y(n3743) );
OAI211X1TS U2919 ( .A0(n5381), .A1(n5377), .B0(n5338), .C0(n5337), .Y(n1796)
);
INVX4TS U2920 ( .A(n2917), .Y(DP_OP_499J223_125_1651_n274) );
OAI211X1TS U2921 ( .A0(n5385), .A1(n5399), .B0(n5343), .C0(n5342), .Y(n1788)
);
OAI211X1TS U2922 ( .A0(n5389), .A1(n5377), .B0(n5284), .C0(n5283), .Y(n1799)
);
OAI211X1TS U2923 ( .A0(n5389), .A1(n5282), .B0(n5272), .C0(n5271), .Y(n1800)
);
INVX4TS U2924 ( .A(n4233), .Y(DP_OP_499J223_125_1651_n296) );
INVX3TS U2925 ( .A(n4209), .Y(DP_OP_499J223_125_1651_n294) );
INVX12TS U2926 ( .A(n2333), .Y(n2334) );
NAND2X2TS U2927 ( .A(DP_OP_501J223_127_5235_n188), .B(n3499), .Y(n3616) );
OAI21X1TS U2928 ( .A0(n4004), .A1(n4010), .B0(n4011), .Y(n4009) );
XOR2X1TS U2929 ( .A(n5589), .B(n5588), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
XOR2X1TS U2930 ( .A(n5511), .B(n5510), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
NOR2X1TS U2931 ( .A(n2325), .B(n3692), .Y(n3552) );
AO21X1TS U2932 ( .A0(result_add_subt[4]), .A1(n6354), .B0(n3303), .Y(n1387)
);
OAI21X1TS U2933 ( .A0(n5500), .A1(n5487), .B0(n5497), .Y(n3398) );
OAI21X1TS U2934 ( .A0(n5510), .A1(n5507), .B0(n5508), .Y(n5506) );
OAI21X2TS U2935 ( .A0(n4005), .A1(n4011), .B0(n4006), .Y(n3907) );
NOR2X2TS U2936 ( .A(n4005), .B(n4010), .Y(n3908) );
INVX3TS U2937 ( .A(n6270), .Y(DP_OP_499J223_125_1651_n277) );
ADDHX2TS U2938 ( .A(n3674), .B(n3673), .CO(DP_OP_501J223_127_5235_n169), .S(
n3670) );
MX2X2TS U2939 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(n5936), .S0(n6260),
.Y(n1585) );
INVX6TS U2940 ( .A(n3460), .Y(n3709) );
NOR2X4TS U2941 ( .A(n3906), .B(n3905), .Y(n4005) );
NAND2X2TS U2942 ( .A(n3906), .B(n3905), .Y(n4006) );
NOR2X4TS U2943 ( .A(n3942), .B(n3941), .Y(n3995) );
OR2X2TS U2944 ( .A(DP_OP_500J223_126_4510_n101), .B(n5192), .Y(n2487) );
CLKINVX6TS U2945 ( .A(n2252), .Y(n2354) );
BUFX12TS U2946 ( .A(n3219), .Y(n3333) );
NAND2X2TS U2947 ( .A(n3942), .B(n3941), .Y(n3996) );
XOR2X1TS U2948 ( .A(n5598), .B(n5597), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
OR2X2TS U2949 ( .A(n3958), .B(n3957), .Y(n2475) );
AFHCINX2TS U2950 ( .CIN(n4015), .B(n4016), .A(n4017), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5), .CO(n4013) );
XOR2X1TS U2951 ( .A(n5603), .B(n5602), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
OR2X2TS U2952 ( .A(n3944), .B(n3943), .Y(n2476) );
NOR2X4TS U2953 ( .A(n3904), .B(n3903), .Y(n4010) );
OAI21X1TS U2954 ( .A0(n6810), .A1(n5426), .B0(n5402), .Y(n1458) );
AOI2BB1X1TS U2955 ( .A0N(n6022), .A1N(overflow_flag_addsubt), .B0(n6017),
.Y(n1411) );
OAI21X1TS U2956 ( .A0(n6812), .A1(n5426), .B0(n5401), .Y(n1459) );
OAI21X1TS U2957 ( .A0(n2568), .A1(n5426), .B0(n5406), .Y(n1460) );
OAI21X1TS U2958 ( .A0(n2215), .A1(n5426), .B0(n5416), .Y(n1461) );
OAI21X1TS U2959 ( .A0(n2273), .A1(n5426), .B0(n5425), .Y(n1310) );
OAI21X1TS U2960 ( .A0(n2270), .A1(n5433), .B0(n5412), .Y(n1253) );
OAI21X1TS U2961 ( .A0(n2552), .A1(n5433), .B0(n5432), .Y(n1249) );
OAI21X1TS U2962 ( .A0(n6811), .A1(n5426), .B0(n5404), .Y(n1463) );
OAI21X1TS U2963 ( .A0(n6804), .A1(n5426), .B0(n5403), .Y(n1462) );
OAI21X1TS U2964 ( .A0(n2413), .A1(n5436), .B0(n5423), .Y(n1245) );
OAI21X1TS U2965 ( .A0(n2233), .A1(n5433), .B0(n5429), .Y(n1261) );
OAI21X1TS U2966 ( .A0(n2278), .A1(n5426), .B0(n5407), .Y(n1326) );
OAI21X1TS U2967 ( .A0(n2526), .A1(n5426), .B0(n3399), .Y(n1303) );
OAI21X1TS U2968 ( .A0(n2432), .A1(n5436), .B0(n5414), .Y(n1233) );
OAI21X1TS U2969 ( .A0(n5144), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n6017),
.Y(n5145) );
OAI21X1TS U2970 ( .A0(n2274), .A1(n5436), .B0(n5428), .Y(n1229) );
OAI21X1TS U2971 ( .A0(n2516), .A1(n5433), .B0(n5430), .Y(n1265) );
OAI21X1TS U2972 ( .A0(n6803), .A1(n5426), .B0(n5415), .Y(n1464) );
OAI21X1TS U2973 ( .A0(n2271), .A1(n5436), .B0(n5435), .Y(n1225) );
OAI21X1TS U2974 ( .A0(n2272), .A1(n5436), .B0(n5411), .Y(n1217) );
OAI21X1TS U2975 ( .A0(n2279), .A1(n5436), .B0(n5409), .Y(n1213) );
OAI21X1TS U2976 ( .A0(n2231), .A1(n5433), .B0(n5420), .Y(n1269) );
OAI21X1TS U2977 ( .A0(n2232), .A1(n5436), .B0(n5419), .Y(n1209) );
OAI21X1TS U2978 ( .A0(n2234), .A1(n5433), .B0(n5417), .Y(n1282) );
OAI21X1TS U2979 ( .A0(n2434), .A1(n5433), .B0(n5410), .Y(n1289) );
XOR2X1TS U2980 ( .A(n5529), .B(n5528), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
OAI211X1TS U2981 ( .A0(n5052), .A1(n2415), .B0(n5005), .C0(n5004), .Y(n1819)
);
OAI211X1TS U2982 ( .A0(n5067), .A1(n2439), .B0(n5033), .C0(n5032), .Y(n1837)
);
OAI211X1TS U2983 ( .A0(n5110), .A1(n6418), .B0(n5051), .C0(n5050), .Y(n1926)
);
OAI21X2TS U2984 ( .A0(n5502), .A1(n5508), .B0(n5503), .Y(n3395) );
XOR2X1TS U2985 ( .A(n5524), .B(n5523), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
CLKMX2X2TS U2986 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n5933), .Y(n1587) );
AOI222X1TS U2987 ( .A0(n5167), .A1(cordic_result[19]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[19]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[19]), .Y(n5133) );
OAI21X1TS U2988 ( .A0(n2274), .A1(n5310), .B0(n5305), .Y(n1392) );
AOI222X1TS U2989 ( .A0(n5167), .A1(cordic_result[12]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[12]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[12]), .Y(n5126) );
AOI222X1TS U2990 ( .A0(n5167), .A1(cordic_result[17]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[17]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[17]), .Y(n5122) );
OAI21X1TS U2991 ( .A0(n6813), .A1(n5310), .B0(n5286), .Y(n1386) );
AOI222X1TS U2992 ( .A0(n5167), .A1(cordic_result[14]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[14]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[14]), .Y(n5120) );
OAI21X1TS U2993 ( .A0(n2525), .A1(n5310), .B0(n5303), .Y(n1383) );
OAI21X1TS U2994 ( .A0(n2413), .A1(n5312), .B0(n5301), .Y(n1380) );
OAI211X1TS U2995 ( .A0(n5087), .A1(n6872), .B0(n5023), .C0(n5022), .Y(n1914)
);
OAI211X1TS U2996 ( .A0(n5087), .A1(n6871), .B0(n5021), .C0(n5020), .Y(n1912)
);
OAI21X1TS U2997 ( .A0(n2552), .A1(n5312), .B0(n5302), .Y(n1377) );
OAI211X1TS U2998 ( .A0(n5110), .A1(n6423), .B0(n5091), .C0(n5090), .Y(n1922)
);
NAND3BX1TS U2999 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n6020), .C(n6019),
.Y(n6021) );
OAI21X1TS U3000 ( .A0(n2230), .A1(n5312), .B0(n5298), .Y(n1371) );
OAI211X1TS U3001 ( .A0(n5067), .A1(n2436), .B0(n5041), .C0(n5040), .Y(n1834)
);
AOI222X1TS U3002 ( .A0(n6562), .A1(cordic_result[1]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[1]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[1]), .Y(n5117)
);
OAI21X1TS U3003 ( .A0(n2233), .A1(n5312), .B0(n5306), .Y(n1368) );
OAI21X1TS U3004 ( .A0(n2516), .A1(n5312), .B0(n5304), .Y(n1365) );
OAI21X1TS U3005 ( .A0(n2278), .A1(n5312), .B0(n5293), .Y(n1328) );
NAND3X1TS U3006 ( .A(n6482), .B(n6481), .C(n6480), .Y(n1832) );
NAND3X1TS U3007 ( .A(n6476), .B(n6475), .C(n6486), .Y(n1838) );
NAND3X1TS U3008 ( .A(n6478), .B(n6477), .C(n6480), .Y(n1836) );
NAND3X1TS U3009 ( .A(n6493), .B(n6492), .C(n6491), .Y(n1827) );
NAND3X1TS U3010 ( .A(n6512), .B(n6511), .C(n6515), .Y(n1816) );
OAI21X1TS U3011 ( .A0(n4821), .A1(n7059), .B0(n4820), .Y(n1318) );
OAI211X1TS U3012 ( .A0(n5116), .A1(n6402), .B0(n5057), .C0(n5056), .Y(n1937)
);
NAND3X1TS U3013 ( .A(n6504), .B(n6503), .C(n6502), .Y(n1823) );
NAND3X1TS U3014 ( .A(n6501), .B(n6500), .C(n6506), .Y(n1824) );
NAND3X1TS U3015 ( .A(n6484), .B(n6483), .C(n6497), .Y(n1830) );
OAI211X1TS U3016 ( .A0(n5052), .A1(n2453), .B0(n5003), .C0(n5002), .Y(n1831)
);
NAND3X1TS U3017 ( .A(n6508), .B(n6507), .C(n6506), .Y(n1821) );
AOI222X1TS U3018 ( .A0(n5291), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n6846),
.B1(n6708), .C0(FPADDSUB_intDX_EWSW[24]), .C1(n4321), .Y(n7074) );
OAI211X1TS U3019 ( .A0(n5087), .A1(n6873), .B0(n5017), .C0(n5016), .Y(n1917)
);
OAI211X1TS U3020 ( .A0(n5052), .A1(n6457), .B0(n5011), .C0(n5010), .Y(n1820)
);
AOI222X1TS U3021 ( .A0(n5424), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n6822),
.B1(n6708), .C0(FPADDSUB_intDX_EWSW[23]), .C1(n5291), .Y(n7072) );
OAI21X1TS U3022 ( .A0(n2269), .A1(n5312), .B0(n5311), .Y(n1305) );
OAI211X1TS U3023 ( .A0(n5110), .A1(n6417), .B0(n5079), .C0(n5078), .Y(n1927)
);
NAND3X1TS U3024 ( .A(n6473), .B(n6472), .C(n6491), .Y(n1840) );
OAI21X1TS U3025 ( .A0(n2275), .A1(n2323), .B0(n5295), .Y(n1298) );
OAI211X1TS U3026 ( .A0(n5116), .A1(n6409), .B0(n5059), .C0(n5058), .Y(n1932)
);
OAI21X1TS U3027 ( .A0(n4821), .A1(n2336), .B0(n4819), .Y(n2077) );
AOI222X1TS U3028 ( .A0(n5291), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n6857),
.B1(n6708), .C0(FPADDSUB_intDX_EWSW[26]), .C1(n4321), .Y(n7076) );
OAI211X1TS U3029 ( .A0(n5116), .A1(n6407), .B0(n5055), .C0(n5054), .Y(n1933)
);
OAI211X1TS U3030 ( .A0(n5110), .A1(n6410), .B0(n5073), .C0(n5072), .Y(n1930)
);
OAI211X1TS U3031 ( .A0(n5052), .A1(n2445), .B0(n5007), .C0(n5006), .Y(n1817)
);
OAI211X1TS U3032 ( .A0(n5087), .A1(n2416), .B0(n5075), .C0(n5074), .Y(n1919)
);
OAI21X1TS U3033 ( .A0(n2434), .A1(n2323), .B0(n5294), .Y(n1291) );
OAI211X1TS U3034 ( .A0(n5110), .A1(n6412), .B0(n5099), .C0(n5098), .Y(n1929)
);
OAI211X1TS U3035 ( .A0(n5087), .A1(n6425), .B0(n5086), .C0(n5085), .Y(n1921)
);
OAI211X1TS U3036 ( .A0(n5087), .A1(n6874), .B0(n5025), .C0(n5024), .Y(n1916)
);
OAI211X1TS U3037 ( .A0(n5087), .A1(n6875), .B0(n5027), .C0(n5026), .Y(n1915)
);
OAI211X1TS U3038 ( .A0(n5052), .A1(n2441), .B0(n5009), .C0(n5008), .Y(n1818)
);
OAI211X1TS U3039 ( .A0(n5116), .A1(n6399), .B0(n5083), .C0(n5082), .Y(n1939)
);
OAI211X1TS U3040 ( .A0(n5110), .A1(n6420), .B0(n5096), .C0(n5095), .Y(n1924)
);
OAI21X1TS U3041 ( .A0(n2234), .A1(n2323), .B0(n5299), .Y(n1284) );
OAI211X1TS U3042 ( .A0(n5067), .A1(n2435), .B0(n5043), .C0(n5042), .Y(n1839)
);
OAI211X1TS U3043 ( .A0(n5116), .A1(n6398), .B0(n5105), .C0(n5104), .Y(n1940)
);
OAI21X1TS U3044 ( .A0(n6692), .A1(n2323), .B0(n5314), .Y(n1277) );
OAI211X1TS U3045 ( .A0(n5067), .A1(n2428), .B0(n5037), .C0(n5036), .Y(n1842)
);
NAND3X1TS U3046 ( .A(n6499), .B(n6498), .C(n6497), .Y(n1825) );
NAND3X1TS U3047 ( .A(n6490), .B(n6489), .C(n6502), .Y(n1828) );
OAI21X1TS U3048 ( .A0(n2231), .A1(n2323), .B0(n5300), .Y(n1271) );
NAND3X1TS U3049 ( .A(n6496), .B(n6495), .C(n6502), .Y(n1826) );
OAI211X1TS U3050 ( .A0(n5087), .A1(n6783), .B0(n5047), .C0(n5046), .Y(n1918)
);
OAI211X1TS U3051 ( .A0(n5067), .A1(n2281), .B0(n5045), .C0(n5044), .Y(n1843)
);
NAND3X1TS U3052 ( .A(n6488), .B(n6487), .C(n6486), .Y(n1829) );
OAI211X1TS U3053 ( .A0(n5052), .A1(n6876), .B0(n5001), .C0(n5000), .Y(n1822)
);
OAI211X1TS U3054 ( .A0(n5067), .A1(n2282), .B0(n5035), .C0(n5034), .Y(n1841)
);
OAI211X1TS U3055 ( .A0(n5116), .A1(n6396), .B0(n5069), .C0(n5068), .Y(n1941)
);
OAI211X1TS U3056 ( .A0(n5116), .A1(n6406), .B0(n5115), .C0(n5114), .Y(n1934)
);
OAI211X1TS U3057 ( .A0(n5067), .A1(n6851), .B0(n5019), .C0(n5018), .Y(n1911)
);
OAI21X1TS U3058 ( .A0(n6761), .A1(n5312), .B0(n5285), .Y(n1237) );
OAI211X1TS U3059 ( .A0(n5110), .A1(n2417), .B0(n5102), .C0(n5101), .Y(n1925)
);
OAI211X1TS U3060 ( .A0(n5110), .A1(n2425), .B0(n5109), .C0(n5108), .Y(n1928)
);
OAI211X1TS U3061 ( .A0(n5116), .A1(n2422), .B0(n5093), .C0(n5092), .Y(n1935)
);
OAI211X1TS U3062 ( .A0(n5116), .A1(n6404), .B0(n5077), .C0(n5076), .Y(n1936)
);
OAI21X1TS U3063 ( .A0(n2215), .A1(n2323), .B0(n5289), .Y(n1413) );
OAI21X1TS U3064 ( .A0(n2277), .A1(n5310), .B0(n5292), .Y(n1398) );
ADDFHX1TS U3065 ( .A(n3912), .B(n3911), .CI(n3910), .CO(n3926), .S(n3916) );
OAI21X1TS U3066 ( .A0(n2232), .A1(n5310), .B0(n5290), .Y(n1407) );
OAI21X1TS U3067 ( .A0(n2271), .A1(n5310), .B0(n5309), .Y(n1395) );
OAI21X1TS U3068 ( .A0(n2272), .A1(n5310), .B0(n5288), .Y(n1401) );
AOI222X1TS U3069 ( .A0(n4984), .A1(cordic_result[27]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[27]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[27]), .Y(n5163) );
NAND2X4TS U3070 ( .A(n2874), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n2961)
);
AOI222X1TS U3071 ( .A0(n5167), .A1(cordic_result[20]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[20]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[20]), .Y(n5168) );
AOI222X1TS U3072 ( .A0(n4984), .A1(cordic_result[26]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[26]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[26]), .Y(n5165) );
AOI222X1TS U3073 ( .A0(n4984), .A1(cordic_result[28]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[28]), .C0(n4985), .C1(FPSENCOS_d_ff_Yn[28]), .Y(n5159) );
AOI222X1TS U3074 ( .A0(n5167), .A1(cordic_result[24]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[24]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[24]), .Y(n5162) );
OR2X2TS U3075 ( .A(DP_OP_502J223_128_4510_n101), .B(n5149), .Y(n5494) );
OAI21X1TS U3076 ( .A0(n6364), .A1(n4989), .B0(n4988), .Y(n2128) );
AOI2BB2X1TS U3077 ( .B0(n6448), .B1(n6465), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n6464), .Y(n1847) );
AO22X1TS U3078 ( .A0(n6471), .A1(n6467), .B0(n6470), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1846) );
OAI211X1TS U3079 ( .A0(n2363), .A1(n6889), .B0(n4636), .C0(n4635), .Y(n1513)
);
OAI21X1TS U3080 ( .A0(n4696), .A1(n5238), .B0(n4694), .Y(n2075) );
OAI211X1TS U3081 ( .A0(n2362), .A1(n6885), .B0(n4629), .C0(n4628), .Y(n1517)
);
OAI211X1TS U3082 ( .A0(n2361), .A1(n6892), .B0(n4644), .C0(n4643), .Y(n1510)
);
AOI31X1TS U3083 ( .A0(n6704), .A1(n6703), .A2(n6702), .B0(n2323), .Y(n6705)
);
OAI21X1TS U3084 ( .A0(n4696), .A1(n2341), .B0(n4695), .Y(n1330) );
OAI211X1TS U3085 ( .A0(n2361), .A1(n6877), .B0(n4616), .C0(n4615), .Y(n1525)
);
OAI211X1TS U3086 ( .A0(n2361), .A1(n6879), .B0(n4597), .C0(n4596), .Y(n1523)
);
OAI211X1TS U3087 ( .A0(n2361), .A1(n6881), .B0(n4618), .C0(n4617), .Y(n1521)
);
OAI211X1TS U3088 ( .A0(n2361), .A1(n6883), .B0(n4606), .C0(n4605), .Y(n1519)
);
AO22X1TS U3089 ( .A0(n6471), .A1(n4557), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1944) );
NAND3X1TS U3090 ( .A(n6514), .B(n6513), .C(n6515), .Y(n1815) );
OAI211X1TS U3091 ( .A0(n2362), .A1(n6880), .B0(n4620), .C0(n4619), .Y(n1522)
);
OAI211X1TS U3092 ( .A0(n2363), .A1(n6882), .B0(n4614), .C0(n4613), .Y(n1520)
);
OAI211X1TS U3093 ( .A0(n2362), .A1(n6884), .B0(n4612), .C0(n4611), .Y(n1518)
);
OAI211X1TS U3094 ( .A0(n2361), .A1(n6895), .B0(n4625), .C0(n4624), .Y(n1507)
);
AOI2BB2X1TS U3095 ( .B0(n6438), .B1(n6437), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n6459), .Y(n1945) );
OAI211X1TS U3096 ( .A0(n2363), .A1(n6893), .B0(n4627), .C0(n4626), .Y(n1509)
);
OAI211X1TS U3097 ( .A0(n2362), .A1(n6888), .B0(n4592), .C0(n4591), .Y(n1514)
);
OAI211X1TS U3098 ( .A0(n2363), .A1(n6894), .B0(n4594), .C0(n4593), .Y(n1508)
);
OAI211X1TS U3099 ( .A0(n2362), .A1(n6890), .B0(n4604), .C0(n4603), .Y(n1512)
);
NAND3X1TS U3100 ( .A(n6517), .B(n6516), .C(n6515), .Y(n1814) );
NAND2X2TS U3101 ( .A(n3855), .B(n3854), .Y(n3856) );
AO22X1TS U3102 ( .A0(n6464), .A1(n6434), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1946) );
AO22X1TS U3103 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n6447), .Y(n1887) );
OAI21X1TS U3104 ( .A0(n4799), .A1(n5826), .B0(n5828), .Y(n4800) );
NAND2X2TS U3105 ( .A(n3478), .B(n3477), .Y(n3479) );
AO22X1TS U3106 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n6447), .Y(n1883) );
AO22X1TS U3107 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n2302), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n6447), .Y(n1903) );
OAI211X1TS U3108 ( .A0(n2362), .A1(n6896), .B0(n4599), .C0(n4598), .Y(n1506)
);
AO22X1TS U3109 ( .A0(n6471), .A1(n6462), .B0(n6470), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1848) );
AO22X1TS U3110 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n2302), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n6454), .Y(n1873) );
AO22X1TS U3111 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n6447), .Y(n1889) );
AO22X1TS U3112 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n4731), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n6468), .Y(n1865) );
AO22X1TS U3113 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n2302), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n6468), .Y(n1863) );
AO22X1TS U3114 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n4731), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n6447), .Y(n1877) );
AO21X1TS U3115 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n6408), .B0(n6365),
.Y(n2123) );
AO22X1TS U3116 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n6469), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n6454), .Y(n1871) );
AO22X1TS U3117 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n6447), .Y(n1897) );
AO22X1TS U3118 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n6447), .Y(n1893) );
AO22X1TS U3119 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n4748), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n6447), .Y(n1901) );
AO22X1TS U3120 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n6431), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n6454), .Y(n1869) );
AO22X1TS U3121 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n6469), .B0(n6468), .B1(
FPSENCOS_d_ff_Yn[31]), .Y(n1845) );
AO22X1TS U3122 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n6430), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n6468), .Y(n1867) );
AO22X1TS U3123 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n6454), .Y(n1879) );
OR2X2TS U3124 ( .A(n5197), .B(n5196), .Y(n5555) );
AO22X1TS U3125 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n6447), .Y(n1885) );
AO22X1TS U3126 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n6430), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n6447), .Y(n1875) );
AO22X1TS U3127 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n6454), .Y(n1881) );
AO22X1TS U3128 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n6453), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n6468), .Y(n1860) );
AO22X1TS U3129 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n6431), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n6454), .Y(n1859) );
AO22X1TS U3130 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n6453), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n6454), .Y(n1858) );
OAI211X1TS U3131 ( .A0(n4651), .A1(n2400), .B0(n4650), .C0(n4649), .Y(n1527)
);
OAI211X1TS U3132 ( .A0(n2361), .A1(n6886), .B0(n4601), .C0(n4600), .Y(n1516)
);
AO22X1TS U3133 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n2302), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n6454), .Y(n1854) );
AO22X1TS U3134 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n6431), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n6454), .Y(n1857) );
AO22X1TS U3135 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n6431), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n6454), .Y(n1855) );
OAI211X1TS U3136 ( .A0(n2362), .A1(n6897), .B0(n4640), .C0(n4639), .Y(n1505)
);
OAI21X1TS U3137 ( .A0(n4758), .A1(n5238), .B0(n4756), .Y(n2076) );
OAI21X1TS U3138 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(n4816), .B0(n5213),
.Y(n4817) );
OAI21X1TS U3139 ( .A0(n4758), .A1(n7059), .B0(n4757), .Y(n1322) );
AO22X1TS U3140 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n6453), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n6452), .Y(n1905) );
OAI211X1TS U3141 ( .A0(n6449), .A1(n6902), .B0(n4987), .C0(n4980), .Y(n2126)
);
INVX6TS U3142 ( .A(n3638), .Y(n3697) );
AO22X1TS U3143 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n6452), .Y(n1891) );
AO22X1TS U3144 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n6469), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n6452), .Y(n1907) );
AO22X1TS U3145 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n6446), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n6452), .Y(n1895) );
INVX6TS U3146 ( .A(n3665), .Y(n3698) );
AO22X1TS U3147 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n4748), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n6452), .Y(n1899) );
OAI211X1TS U3148 ( .A0(n6362), .A1(n6371), .B0(n4761), .C0(n4760), .Y(n2127)
);
OR2X2TS U3149 ( .A(n5154), .B(n5153), .Y(n5484) );
NAND2BX1TS U3150 ( .AN(n3900), .B(n2395), .Y(n3870) );
AOI222X1TS U3151 ( .A0(n4748), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n6427), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n4931), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n4932) );
XNOR2X1TS U3152 ( .A(n3951), .B(n2395), .Y(n3932) );
OAI21X1TS U3153 ( .A0(n6461), .A1(n6841), .B0(n6463), .Y(n6462) );
AOI211X1TS U3154 ( .A0(n4642), .A1(n6898), .B0(n4587), .C0(n4586), .Y(n1621)
);
OAI21X1TS U3155 ( .A0(n4861), .A1(n5723), .B0(n5725), .Y(n4862) );
OAI211X1TS U3156 ( .A0(n6449), .A1(n6900), .B0(n4823), .C0(n6363), .Y(n2132)
);
AO22X1TS U3157 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4731), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n6452), .Y(n1861) );
OAI211X1TS U3158 ( .A0(n6448), .A1(n6901), .B0(n4823), .C0(n4989), .Y(n2130)
);
OAI21X1TS U3159 ( .A0(n6371), .A1(n6367), .B0(n4750), .Y(n2116) );
NOR2X4TS U3160 ( .A(n4998), .B(n6345), .Y(n4999) );
NOR2X1TS U3161 ( .A(n6664), .B(n6663), .Y(n6665) );
NOR2X1TS U3162 ( .A(n6664), .B(n6636), .Y(n6637) );
OAI21X1TS U3163 ( .A0(n4759), .A1(n6362), .B0(n4752), .Y(n2129) );
NOR2X1TS U3164 ( .A(n6664), .B(n6639), .Y(n6640) );
XNOR2X1TS U3165 ( .A(n3951), .B(n2205), .Y(n3883) );
NOR2X1TS U3166 ( .A(n6664), .B(n6642), .Y(n6643) );
NOR2X1TS U3167 ( .A(n6664), .B(n6628), .Y(n6630) );
NOR2X1TS U3168 ( .A(n6727), .B(n6718), .Y(n6719) );
NOR2X1TS U3169 ( .A(n6664), .B(n6645), .Y(n6646) );
NOR2X1TS U3170 ( .A(n6727), .B(n6720), .Y(n6721) );
NOR2X1TS U3171 ( .A(n6727), .B(n6723), .Y(n6724) );
OAI21X1TS U3172 ( .A0(n4967), .A1(n4966), .B0(n4965), .Y(mult_x_309_n22) );
AOI2BB2X1TS U3173 ( .B0(n5987), .B1(n6006), .A0N(n6014), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n1196) );
AOI2BB2X1TS U3174 ( .B0(n5991), .B1(n6006), .A0N(n6009), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1199) );
NOR2X1TS U3175 ( .A(n5720), .B(n5721), .Y(n5697) );
AO22X1TS U3176 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n6428), .B0(n6375),
.B1(n6374), .Y(n2115) );
OAI21X1TS U3177 ( .A0(n4915), .A1(n5766), .B0(n5767), .Y(n4916) );
OAI21X1TS U3178 ( .A0(n5763), .A1(n4928), .B0(n5761), .Y(n4929) );
ADDHX2TS U3179 ( .A(n3664), .B(n2307), .CO(n3638), .S(n3665) );
NOR2X1TS U3180 ( .A(n5823), .B(n5824), .Y(n5802) );
AO22X1TS U3181 ( .A0(n6448), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1870) );
NAND3X1TS U3182 ( .A(n6384), .B(n6338), .C(n6348), .Y(n6340) );
AO22X1TS U3183 ( .A0(n4554), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1900) );
NOR2X1TS U3184 ( .A(n6664), .B(n6632), .Y(n6633) );
OAI21X1TS U3185 ( .A0(n6360), .A1(n6756), .B0(FPSENCOS_cont_var_out[1]), .Y(
n4553) );
AO22X1TS U3186 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1878) );
NOR2X1TS U3187 ( .A(n6664), .B(n6653), .Y(n6654) );
AO22X1TS U3188 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1866) );
OAI21X1TS U3189 ( .A0(n5815), .A1(n5812), .B0(n5813), .Y(n4790) );
AO22X1TS U3190 ( .A0(n6448), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1872) );
AO22X1TS U3191 ( .A0(n4554), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1892) );
AO22X1TS U3192 ( .A0(n2357), .A1(n5956), .B0(n5960), .B1(n5955), .Y(n6648)
);
CLKINVX2TS U3193 ( .A(n4590), .Y(n4646) );
AO22X1TS U3194 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1874) );
AO22X1TS U3195 ( .A0(n6471), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1868) );
AO22X1TS U3196 ( .A0(n6471), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n6470), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1844) );
NAND2BX1TS U3197 ( .AN(n6358), .B(n6348), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
INVX3TS U3198 ( .A(n3514), .Y(n3515) );
AO22X1TS U3199 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1880) );
AO22X1TS U3200 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n6612), .B0(
mult_result[3]), .B1(n6614), .Y(n1501) );
AO22X1TS U3201 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n6612), .B0(
mult_result[4]), .B1(n6614), .Y(n1500) );
AO22X1TS U3202 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n6612), .B0(
mult_result[5]), .B1(n6614), .Y(n1499) );
AO22X1TS U3203 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n6616), .B0(
mult_result[6]), .B1(n6614), .Y(n1498) );
AO22X1TS U3204 ( .A0(n6471), .A1(intadd_518_SUM_0_), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[24]), .Y(n1950) );
AO22X1TS U3205 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n6616), .B0(
mult_result[7]), .B1(n6614), .Y(n1497) );
AO22X1TS U3206 ( .A0(n6438), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1884) );
AO22X1TS U3207 ( .A0(n6471), .A1(n4556), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[23]), .Y(n1951) );
AOI2BB2X1TS U3208 ( .B0(n5988), .B1(n6006), .A0N(n6009), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n1197) );
AO22X1TS U3209 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n6616), .B0(
mult_result[8]), .B1(n6618), .Y(n1496) );
AO22X1TS U3210 ( .A0(n6471), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1862) );
AO22X1TS U3211 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n6616), .B0(
mult_result[9]), .B1(n6618), .Y(n1495) );
AO22X1TS U3212 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n6616), .B0(
mult_result[10]), .B1(n6618), .Y(n1494) );
AO22X1TS U3213 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n6616), .B0(
mult_result[11]), .B1(n6618), .Y(n1493) );
AO22X1TS U3214 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n6616), .B0(
mult_result[12]), .B1(n6618), .Y(n1492) );
AO22X1TS U3215 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n6616), .B0(
mult_result[13]), .B1(n6618), .Y(n1491) );
AO22X1TS U3216 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n6616), .B0(
mult_result[14]), .B1(n6618), .Y(n1490) );
AO22X1TS U3217 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n6616), .B0(
mult_result[15]), .B1(n6618), .Y(n1489) );
NOR2X1TS U3218 ( .A(n2306), .B(n5609), .Y(n5191) );
AO22X1TS U3219 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n6619), .B0(
mult_result[16]), .B1(n6618), .Y(n1488) );
AO22X1TS U3220 ( .A0(n2357), .A1(n5961), .B0(n5960), .B1(n5959), .Y(n6663)
);
AO22X1TS U3221 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n6619), .B0(
mult_result[17]), .B1(n6617), .Y(n1487) );
AO22X1TS U3222 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n6619), .B0(
mult_result[18]), .B1(n6617), .Y(n1486) );
OAI21X1TS U3223 ( .A0(n5658), .A1(n5655), .B0(n5656), .Y(n4977) );
AO22X1TS U3224 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n6619), .B0(
mult_result[19]), .B1(n6617), .Y(n1485) );
AO22X1TS U3225 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n6619), .B0(
mult_result[22]), .B1(n6618), .Y(n1481) );
NOR2X1TS U3226 ( .A(n6005), .B(n6004), .Y(n6011) );
AO22X1TS U3227 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n6619), .B0(
mult_result[20]), .B1(n6617), .Y(n1484) );
AO22X1TS U3228 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n6619), .B0(
mult_result[21]), .B1(n6617), .Y(n1483) );
OAI21X1TS U3229 ( .A0(n5668), .A1(n4952), .B0(n5669), .Y(n4953) );
AO22X1TS U3230 ( .A0(n6438), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n6544), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1732) );
AO22X1TS U3231 ( .A0(n6619), .A1(FPMULT_Sgf_normalized_result[2]), .B0(
mult_result[2]), .B1(n6617), .Y(n1502) );
AO22X1TS U3232 ( .A0(n6471), .A1(intadd_518_SUM_2_), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[26]), .Y(n1948) );
AO22X1TS U3233 ( .A0(n6619), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n6617), .Y(n1504) );
AO22X1TS U3234 ( .A0(n6471), .A1(intadd_518_SUM_1_), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_x_out[25]), .Y(n1949) );
AO22X1TS U3235 ( .A0(n6464), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n6451), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1876) );
AO22X1TS U3236 ( .A0(n6464), .A1(n6370), .B0(n6428), .B1(
FPSENCOS_d_ff3_LUT_out[23]), .Y(n2117) );
NOR2X1TS U3237 ( .A(n6727), .B(n6726), .Y(n6729) );
NAND4BX1TS U3238 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n3297), .C(n3296),
.D(n3295), .Y(n3298) );
AO22X1TS U3239 ( .A0(n6449), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n6544), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1896) );
AO22X1TS U3240 ( .A0(n6619), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n6617), .Y(n1503) );
AO22X1TS U3241 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n6379), .B1(
Data_1[0]), .Y(n2112) );
NOR2X1TS U3242 ( .A(n4583), .B(n4582), .Y(n1692) );
OAI21X1TS U3243 ( .A0(n5732), .A1(n5731), .B0(n5733), .Y(n4838) );
AO22X1TS U3244 ( .A0(n6005), .A1(n5958), .B0(n5960), .B1(n5957), .Y(n6632)
);
INVX2TS U3245 ( .A(n5637), .Y(n2349) );
AND3X2TS U3246 ( .A(n5329), .B(n5328), .C(n5327), .Y(n5382) );
NOR2X1TS U3247 ( .A(n2304), .B(n5537), .Y(n5147) );
NAND2BX1TS U3248 ( .AN(n3900), .B(n2205), .Y(n3902) );
AO22X1TS U3249 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n6377), .B1(
Data_1[10]), .Y(n2102) );
AO22X1TS U3250 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n6383), .B1(
Data_1[25]), .Y(n2087) );
AO22X1TS U3251 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n6377), .B1(
Data_1[9]), .Y(n2103) );
AO22X1TS U3252 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n6383), .B1(
Data_1[24]), .Y(n2088) );
AO22X1TS U3253 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n6377), .B1(
Data_1[8]), .Y(n2104) );
OAI222X1TS U3254 ( .A0(n2336), .A1(FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n5450), .B1(FPADDSUB_Raw_mant_NRM_SWR[13]), .C0(FPADDSUB_DmP_mant_SHT1_SW[11]), .C1(
n6713), .Y(n5282) );
NAND3X1TS U3255 ( .A(n5248), .B(n5247), .C(n5246), .Y(n5261) );
AO22X1TS U3256 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n6377), .B1(
Data_1[11]), .Y(n2101) );
OAI21X1TS U3257 ( .A0(n4898), .A1(n4897), .B0(n4896), .Y(n4899) );
AND3X2TS U3258 ( .A(n5254), .B(n5253), .C(n5252), .Y(n5355) );
AO22X1TS U3259 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n6377), .B1(
Data_1[12]), .Y(n2100) );
AO22X1TS U3260 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n6377), .B1(
Data_1[7]), .Y(n2105) );
AO22X1TS U3261 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n6377), .B1(
Data_1[6]), .Y(n2106) );
AO22X1TS U3262 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n6383), .B1(
Data_1[31]), .Y(n2081) );
AO22X1TS U3263 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n6383), .B1(
Data_1[16]), .Y(n2096) );
AO22X1TS U3264 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n6377), .B1(
Data_1[5]), .Y(n2107) );
AO22X1TS U3265 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n6377), .B1(
Data_1[13]), .Y(n2099) );
AO22X1TS U3266 ( .A0(n6378), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n6377), .B1(
Data_1[14]), .Y(n2098) );
AO22X1TS U3267 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n6383), .B1(
Data_1[29]), .Y(n2083) );
AO22X1TS U3268 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n6383), .B1(
Data_1[28]), .Y(n2084) );
NAND3X1TS U3269 ( .A(n5318), .B(n5317), .C(n5316), .Y(n5370) );
NOR2X1TS U3270 ( .A(n2357), .B(n4469), .Y(n4472) );
AO22X1TS U3271 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n6382), .B1(
Data_1[27]), .Y(n2085) );
OAI21X1TS U3272 ( .A0(n4920), .A1(n4919), .B0(n4918), .Y(n4921) );
AO22X1TS U3273 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n6383), .B1(
Data_1[26]), .Y(n2086) );
AO22X1TS U3274 ( .A0(n6384), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n6383), .B1(
Data_1[30]), .Y(n2082) );
AND3X2TS U3275 ( .A(n5203), .B(n5202), .C(n5201), .Y(n5393) );
AND2X2TS U3276 ( .A(n4908), .B(n4906), .Y(n5762) );
AO22X1TS U3277 ( .A0(n6376), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n6379), .B1(
Data_1[4]), .Y(n2108) );
AO22X1TS U3278 ( .A0(n6376), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n6379), .B1(
Data_1[1]), .Y(n2111) );
OAI21X1TS U3279 ( .A0(n6610), .A1(underflow_flag_mult), .B0(n6609), .Y(n6611) );
AO22X1TS U3280 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n6380), .B1(
Data_1[21]), .Y(n2091) );
AO22X1TS U3281 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n6380), .B1(
Data_1[19]), .Y(n2093) );
NOR2X1TS U3282 ( .A(n5608), .B(n2344), .Y(n4354) );
AO22X1TS U3283 ( .A0(n6376), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n6379), .B1(
Data_1[3]), .Y(n2109) );
AO22X1TS U3284 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n6380), .B1(
Data_1[20]), .Y(n2092) );
AO22X1TS U3285 ( .A0(n6376), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n6379), .B1(
Data_1[2]), .Y(n2110) );
INVX2TS U3286 ( .A(n6415), .Y(n6431) );
NOR2X1TS U3287 ( .A(n5180), .B(n5622), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
AO22X1TS U3288 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n6380), .B1(
Data_1[23]), .Y(n2089) );
AO22X1TS U3289 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n6379), .B1(
Data_1[22]), .Y(n2090) );
AO22X1TS U3290 ( .A0(n6381), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n6380), .B1(
Data_1[17]), .Y(n2095) );
INVX2TS U3291 ( .A(n6415), .Y(n4731) );
OAI21X1TS U3292 ( .A0(n6108), .A1(n6107), .B0(n6106), .Y(n6110) );
OAI21X1TS U3293 ( .A0(n6108), .A1(n6035), .B0(n6053), .Y(n6037) );
INVX3TS U3294 ( .A(n6444), .Y(n6456) );
NAND3X1TS U3295 ( .A(n4940), .B(n5675), .C(n4939), .Y(n5679) );
OAI21X1TS U3296 ( .A0(n5700), .A1(n5699), .B0(n5698), .Y(n5701) );
XOR2X1TS U3297 ( .A(n4036), .B(n4038), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
OAI21X1TS U3298 ( .A0(n6205), .A1(n6199), .B0(n6200), .Y(n6190) );
AOI31X1TS U3299 ( .A0(n6787), .A1(n4550), .A2(n5451), .B0(
FPMULT_FSM_selector_C), .Y(n4551) );
OR2X2TS U3300 ( .A(n3896), .B(n3444), .Y(n2247) );
NOR2X4TS U3301 ( .A(n6260), .B(n6020), .Y(n5933) );
BUFX3TS U3302 ( .A(n5238), .Y(n2336) );
OAI21X1TS U3303 ( .A0(n5754), .A1(n5781), .B0(n5756), .Y(n5753) );
OAI21X1TS U3304 ( .A0(n5805), .A1(n5804), .B0(n5803), .Y(n5806) );
OR2X2TS U3305 ( .A(n5443), .B(n4961), .Y(n4962) );
NAND3BX1TS U3306 ( .AN(n4430), .B(n4429), .C(n4427), .Y(n4428) );
INVX2TS U3307 ( .A(n5637), .Y(n6606) );
INVX2TS U3308 ( .A(n5637), .Y(n5641) );
XOR2X2TS U3309 ( .A(n4346), .B(n4345), .Y(n4347) );
INVX2TS U3310 ( .A(n5637), .Y(n5639) );
INVX2TS U3311 ( .A(n5637), .Y(n5934) );
XNOR2X2TS U3312 ( .A(n3646), .B(n2346), .Y(n3648) );
OAI21X1TS U3313 ( .A0(n4685), .A1(n6650), .B0(n4705), .Y(op_result[17]) );
OAI21X1TS U3314 ( .A0(n4670), .A1(n6655), .B0(n4704), .Y(op_result[16]) );
OAI21X1TS U3315 ( .A0(n4668), .A1(n6652), .B0(n4706), .Y(op_result[13]) );
OAI21X1TS U3316 ( .A0(n4710), .A1(n6830), .B0(n4709), .Y(op_result[14]) );
OAI21X1TS U3317 ( .A0(n4668), .A1(n6638), .B0(n4701), .Y(op_result[18]) );
OAI21X1TS U3318 ( .A0(n4710), .A1(n6634), .B0(n4703), .Y(op_result[15]) );
OAI21X1TS U3319 ( .A0(n4670), .A1(n6641), .B0(n4699), .Y(op_result[21]) );
OAI21X1TS U3320 ( .A0(n4685), .A1(n6647), .B0(n4700), .Y(op_result[20]) );
NOR2X1TS U3321 ( .A(n4905), .B(n4907), .Y(n4904) );
AO22XLTS U3322 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n6743),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1370) );
NOR2X1TS U3323 ( .A(n5651), .B(n4935), .Y(intadd_515_B_0_) );
NOR2X1TS U3324 ( .A(n4973), .B(n4948), .Y(n4949) );
CLKBUFX3TS U3325 ( .A(n4488), .Y(n4494) );
NAND2X2TS U3326 ( .A(n4344), .B(n4343), .Y(n4346) );
AND2X2TS U3327 ( .A(n4341), .B(n4345), .Y(n4348) );
AND2X2TS U3328 ( .A(n4584), .B(FPMULT_FS_Module_state_reg[1]), .Y(n4588) );
INVX2TS U3329 ( .A(n5478), .Y(n6957) );
OAI211X2TS U3330 ( .A0(n2504), .A1(n4280), .B0(n4279), .C0(n5967), .Y(n5957)
);
NAND2X4TS U3331 ( .A(n2822), .B(n2826), .Y(n2856) );
OAI211X2TS U3332 ( .A0(n6816), .A1(n4280), .B0(n4275), .C0(n5967), .Y(n5959)
);
NAND2BX1TS U3333 ( .AN(FPSENCOS_d_ff2_Y[23]), .B(n6455), .Y(intadd_517_CI)
);
NOR2X1TS U3334 ( .A(n4572), .B(n5549), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
AND2X2TS U3335 ( .A(n2317), .B(FPADDSUB_OP_FLAG_SFG), .Y(n6024) );
NOR2X4TS U3336 ( .A(n6232), .B(FPADDSUB_OP_FLAG_SFG), .Y(n4499) );
NAND2BX1TS U3337 ( .AN(n4579), .B(n1694), .Y(n4576) );
NAND2XLTS U3338 ( .A(n5273), .B(n6796), .Y(n5276) );
INVX2TS U3339 ( .A(n3748), .Y(n3749) );
NAND2BX1TS U3340 ( .AN(n5847), .B(n5846), .Y(n5849) );
NAND2BX1TS U3341 ( .AN(n6566), .B(n6565), .Y(n1690) );
OAI21X1TS U3342 ( .A0(n1694), .A1(n4579), .B0(n5455), .Y(n4580) );
NOR2X1TS U3343 ( .A(n4831), .B(n4832), .Y(n4836) );
NAND2BX1TS U3344 ( .AN(n5744), .B(n5743), .Y(n5746) );
OAI21XLTS U3345 ( .A0(n4670), .A1(n6540), .B0(n4678), .Y(op_result[29]) );
OAI21XLTS U3346 ( .A0(n4668), .A1(n6537), .B0(n4680), .Y(op_result[28]) );
OAI21XLTS U3347 ( .A0(n4668), .A1(n6526), .B0(n4657), .Y(op_result[24]) );
OAI21XLTS U3348 ( .A0(n4670), .A1(n6533), .B0(n4682), .Y(op_result[27]) );
OAI21XLTS U3349 ( .A0(n4668), .A1(n6530), .B0(n4676), .Y(op_result[26]) );
OAI21XLTS U3350 ( .A0(n4685), .A1(n6527), .B0(n4679), .Y(op_result[25]) );
OAI21XLTS U3351 ( .A0(n4710), .A1(n6631), .B0(n4677), .Y(op_result[22]) );
OAI21XLTS U3352 ( .A0(n4685), .A1(n6554), .B0(n4675), .Y(op_result[31]) );
OAI21XLTS U3353 ( .A0(n4685), .A1(n2451), .B0(n4684), .Y(op_result[30]) );
OAI21XLTS U3354 ( .A0(n4710), .A1(n6524), .B0(n4681), .Y(op_result[23]) );
OAI21XLTS U3355 ( .A0(n4670), .A1(n2367), .B0(n4669), .Y(op_result[0]) );
OAI21XLTS U3356 ( .A0(n4710), .A1(n6835), .B0(n4665), .Y(op_result[1]) );
OAI21XLTS U3357 ( .A0(n4668), .A1(n6834), .B0(n4664), .Y(op_result[2]) );
OAI21XLTS U3358 ( .A0(n4685), .A1(n6833), .B0(n4667), .Y(op_result[3]) );
OAI21XLTS U3359 ( .A0(n4710), .A1(n2280), .B0(n4663), .Y(op_result[4]) );
OAI21XLTS U3360 ( .A0(n4710), .A1(n6836), .B0(n4655), .Y(op_result[5]) );
OAI21XLTS U3361 ( .A0(n4668), .A1(n6659), .B0(n4659), .Y(op_result[8]) );
OAI21XLTS U3362 ( .A0(n4685), .A1(n6831), .B0(n4658), .Y(op_result[10]) );
OAI21XLTS U3363 ( .A0(n4670), .A1(n6837), .B0(n4652), .Y(op_result[9]) );
OAI21XLTS U3364 ( .A0(n4685), .A1(n6839), .B0(n4653), .Y(op_result[6]) );
OAI21XLTS U3365 ( .A0(n4668), .A1(n6840), .B0(n4654), .Y(op_result[7]) );
OAI21XLTS U3366 ( .A0(n4670), .A1(n6662), .B0(n4656), .Y(op_result[11]) );
INVX2TS U3367 ( .A(n2316), .Y(n2317) );
OAI21X1TS U3368 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n6012), .Y(n6335) );
OR2X4TS U3369 ( .A(n6623), .B(n6713), .Y(n5265) );
OAI211X1TS U3370 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n2442), .B0(n2535), .C0(
n2538), .Y(n2549) );
OR2X2TS U3371 ( .A(n3817), .B(n3815), .Y(n2402) );
NAND3X1TS U3372 ( .A(n6364), .B(n6768), .C(intadd_517_B_1_), .Y(n4711) );
INVX1TS U3373 ( .A(n5452), .Y(n4550) );
NOR2X1TS U3374 ( .A(n5905), .B(FPMULT_Sgf_normalized_result[2]), .Y(n5906)
);
OAI21X1TS U3375 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n4545), .Y(n4546) );
NAND3X1TS U3376 ( .A(n5735), .B(FPMULT_Op_MY[14]), .C(FPMULT_Op_MX[13]), .Y(
n5741) );
OAI21X2TS U3377 ( .A0(n3365), .A1(n3371), .B0(n3366), .Y(n4437) );
NAND2X2TS U3378 ( .A(n2218), .B(n2251), .Y(n3435) );
ADDFHX2TS U3379 ( .A(DP_OP_501J223_127_5235_n944), .B(n2292), .CI(n3533),
.CO(n3632), .S(n3677) );
NAND2BX1TS U3380 ( .AN(n4924), .B(intadd_513_A_7_), .Y(n4427) );
NOR2X4TS U3381 ( .A(n4044), .B(n4043), .Y(n4149) );
NOR2X1TS U3382 ( .A(n4769), .B(n4770), .Y(n4774) );
OAI21X1TS U3383 ( .A0(n6181), .A1(n6200), .B0(n6182), .Y(n4257) );
BUFX3TS U3384 ( .A(n6656), .Y(n6738) );
NOR2X1TS U3385 ( .A(n2533), .B(FPADDSUB_intDY_EWSW[10]), .Y(n2534) );
NAND3X1TS U3386 ( .A(n2442), .B(n2535), .C(FPADDSUB_intDX_EWSW[8]), .Y(n2536) );
OAI211X2TS U3387 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n2455), .B0(n2545),
.C0(n2531), .Y(n2547) );
OAI211X2TS U3388 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n2459), .B0(n2515),
.C0(n2506), .Y(n2551) );
AOI211X1TS U3389 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n2568), .B0(n2570),
.C0(n2567), .Y(n2572) );
NOR2X1TS U3390 ( .A(n2560), .B(FPADDSUB_intDY_EWSW[24]), .Y(n2561) );
NAND3X1TS U3391 ( .A(n2423), .B(n2562), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n2564) );
NAND2X2TS U3392 ( .A(n4574), .B(n6757), .Y(n5452) );
ADDFHX2TS U3393 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2]), .B(
n4042), .CI(n4041), .CO(n4045), .S(n4044) );
NOR2X1TS U3394 ( .A(n5851), .B(n5891), .Y(n5852) );
NOR2X1TS U3395 ( .A(n5851), .B(n6792), .Y(n5853) );
OR2X2TS U3396 ( .A(n4160), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .Y(
n4161) );
NOR2X1TS U3397 ( .A(n2292), .B(n2228), .Y(n4248) );
NAND3X1TS U3398 ( .A(n5453), .B(n6757), .C(n6787), .Y(n5456) );
AND2X2TS U3399 ( .A(n3372), .B(n3371), .Y(n3375) );
ADDFHX2TS U3400 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9]), .B(
n4099), .CI(n4098), .CO(n4100), .S(n4095) );
NAND3X1TS U3401 ( .A(n6318), .B(n6317), .C(n6316), .Y(n6918) );
NAND2BX1TS U3402 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n2535) );
OR2X2TS U3403 ( .A(n2481), .B(FPMULT_Op_MX[13]), .Y(n2246) );
OAI21X1TS U3404 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n2461), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n2541) );
NAND2BX1TS U3405 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n2531) );
NAND2BX1TS U3406 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n2508) );
OR2X2TS U3407 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n2454) );
NAND2BX1TS U3408 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n2506) );
NAND2BX1TS U3409 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n2562) );
INVX2TS U3410 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n2671) );
NAND2BX1TS U3411 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n2563) );
NAND2BX1TS U3412 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n2559) );
INVX3TS U3413 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(n4040)
);
CLKINVX2TS U3414 ( .A(result_add_subt[24]), .Y(n6526) );
CLKINVX2TS U3415 ( .A(result_add_subt[29]), .Y(n6540) );
OR2X2TS U3416 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n5221) );
CLKINVX2TS U3417 ( .A(result_add_subt[26]), .Y(n6530) );
CLKINVX2TS U3418 ( .A(result_add_subt[28]), .Y(n6537) );
CLKINVX2TS U3419 ( .A(result_add_subt[27]), .Y(n6533) );
NOR2X1TS U3420 ( .A(n6762), .B(n6845), .Y(FPMULT_S_Oper_A_exp[8]) );
INVX1TS U3421 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n6558) );
CLKINVX2TS U3422 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n6013) );
OAI21X1TS U3423 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n2438), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n2511) );
OAI21X1TS U3424 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n2448), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n2505) );
NAND3X1TS U3425 ( .A(n4242), .B(n4241), .C(n4240), .Y(n4243) );
INVX4TS U3426 ( .A(operation[2]), .Y(n6350) );
INVX2TS U3427 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n3119) );
INVX6TS U3428 ( .A(n2208), .Y(n2207) );
INVX6TS U3429 ( .A(n2843), .Y(n2931) );
AOI21X4TS U3430 ( .A0(n3267), .A1(n3221), .B0(n3220), .Y(n3228) );
INVX4TS U3431 ( .A(n6545), .Y(n4998) );
AOI21X2TS U3432 ( .A0(n2757), .A1(n3051), .B0(n2756), .Y(n2760) );
OR2X2TS U3433 ( .A(n3646), .B(n2403), .Y(n3659) );
INVX2TS U3434 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n2650) );
ADDFHX4TS U3435 ( .A(n2651), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6]), .CI(
n2650), .CO(n2652), .S(n2607) );
OAI21X4TS U3436 ( .A0(n2922), .A1(n2918), .B0(n2919), .Y(n2940) );
OAI21X4TS U3437 ( .A0(n2731), .A1(n2734), .B0(n2732), .Y(n4223) );
AOI21X2TS U3438 ( .A0(n2997), .A1(n2996), .B0(n2995), .Y(n3001) );
AOI21X2TS U3439 ( .A0(n3017), .A1(n3016), .B0(n3011), .Y(n3014) );
NOR2X2TS U3440 ( .A(n4889), .B(n4869), .Y(n4871) );
OAI21X1TS U3441 ( .A0(n4139), .A1(n4116), .B0(n4119), .Y(n4115) );
INVX6TS U3442 ( .A(n4122), .Y(n4139) );
XOR2X1TS U3443 ( .A(n5573), .B(n5572), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
OAI21X1TS U3444 ( .A0(n5710), .A1(n5707), .B0(n5708), .Y(n4852) );
NOR2X4TS U3445 ( .A(n6342), .B(n5015), .Y(n6545) );
NAND2X2TS U3446 ( .A(n5550), .B(n5555), .Y(n5200) );
ADDFX2TS U3447 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]), .B(
n4073), .CI(n4072), .CO(n4074), .S(n4071) );
NOR2X2TS U3448 ( .A(n4167), .B(n4081), .Y(n4083) );
NOR2X4TS U3449 ( .A(n2584), .B(n2703), .Y(n2614) );
OAI21X1TS U3450 ( .A0(n4455), .A1(n4454), .B0(n4453), .Y(n4456) );
NOR2X8TS U3451 ( .A(n4454), .B(n4459), .Y(n3072) );
NAND2X4TS U3452 ( .A(n2819), .B(n2818), .Y(n2823) );
NAND2X4TS U3453 ( .A(n2783), .B(n2782), .Y(n2800) );
NOR2X6TS U3454 ( .A(n3157), .B(n3156), .Y(n3166) );
NOR2X6TS U3455 ( .A(n2762), .B(n3052), .Y(n2764) );
NOR2X8TS U3456 ( .A(n2837), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n2928)
);
OA21X4TS U3457 ( .A0(n2859), .A1(n2858), .B0(n2857), .Y(n2860) );
OR2X6TS U3458 ( .A(n2855), .B(n2859), .Y(n2861) );
NAND2X4TS U3459 ( .A(n4943), .B(n4942), .Y(n5442) );
OAI21X2TS U3460 ( .A0(n6166), .A1(n4411), .B0(n4410), .Y(n6146) );
INVX4TS U3461 ( .A(n3282), .Y(n4421) );
NAND2X4TS U3462 ( .A(n2470), .B(n3016), .Y(n2751) );
OR2X4TS U3463 ( .A(DP_OP_499J223_125_1651_n237), .B(
DP_OP_499J223_125_1651_n239), .Y(n3016) );
XOR2X1TS U3464 ( .A(n3992), .B(n3991), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10) );
NAND2BX4TS U3465 ( .AN(n4806), .B(n4755), .Y(n4690) );
NOR2X4TS U3466 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n5208) );
OAI21X1TS U3467 ( .A0(n5583), .A1(n5580), .B0(n5581), .Y(n5579) );
AND2X4TS U3468 ( .A(n6017), .B(n5143), .Y(n6629) );
XNOR2X2TS U3469 ( .A(n4078), .B(n4077), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
ADDFHX2TS U3470 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8]), .B(
n2817), .CI(n2816), .CO(n2818), .S(n2674) );
CMPR42X4TS U3471 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .C(
DP_OP_499J223_125_1651_n247), .D(DP_OP_499J223_125_1651_n280), .ICI(
DP_OP_499J223_125_1651_n304), .S(DP_OP_499J223_125_1651_n246), .ICO(
DP_OP_499J223_125_1651_n244), .CO(DP_OP_499J223_125_1651_n245) );
ADDFHX4TS U3472 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4]), .B(
n2596), .CI(n2595), .CO(n2597), .S(n2593) );
NOR2X4TS U3473 ( .A(n2598), .B(n2597), .Y(n2604) );
NOR2X8TS U3474 ( .A(n3070), .B(n4208), .Y(n4459) );
ADDFHX4TS U3475 ( .A(n3085), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]), .CI(
n2716), .CO(n3087), .S(n2798) );
XNOR2X4TS U3476 ( .A(n3577), .B(n3576), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12) );
AOI21X2TS U3477 ( .A0(n3452), .A1(n2251), .B0(n3451), .Y(n3455) );
AOI21X4TS U3478 ( .A0(n2444), .A1(n3442), .B0(n3432), .Y(n3446) );
INVX6TS U3479 ( .A(n3658), .Y(n2335) );
ADDFHX4TS U3480 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]), .B(
n2605), .CI(n2715), .CO(n2606), .S(n2598) );
NAND2X6TS U3481 ( .A(n2657), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(n2889)
);
INVX2TS U3482 ( .A(n4452), .Y(n4455) );
OAI211X1TS U3483 ( .A0(n5380), .A1(n5237), .B0(n5345), .C0(n5344), .Y(n1790)
);
OAI21X1TS U3484 ( .A0(n3265), .A1(n3257), .B0(n3260), .Y(n3220) );
NOR2X4TS U3485 ( .A(n3203), .B(n3202), .Y(n3257) );
ADDFHX2TS U3486 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]), .B(
n3223), .CI(n3222), .CO(n3224), .S(n3203) );
OAI21X1TS U3487 ( .A0(n5500), .A1(n5157), .B0(n5156), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
INVX4TS U3488 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n2582)
);
NAND2X4TS U3489 ( .A(n2244), .B(n3511), .Y(n3526) );
OAI22X2TS U3490 ( .A0(n2386), .A1(n3696), .B0(n3703), .B1(n3695), .Y(
DP_OP_501J223_127_5235_n219) );
INVX4TS U3491 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n2591)
);
ADDFHX4TS U3492 ( .A(n2210), .B(n2591), .CI(n2711), .CO(n2592), .S(n2589) );
NAND2X2TS U3493 ( .A(n2620), .B(n2619), .Y(n2621) );
OAI21X1TS U3494 ( .A0(n5921), .A1(n5917), .B0(n5918), .Y(n5913) );
NAND2X4TS U3495 ( .A(n2881), .B(n2880), .Y(n2883) );
ADDFHX4TS U3496 ( .A(n3155), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]), .CI(
n3154), .CO(n3156), .S(n3122) );
ADDFHX2TS U3497 ( .A(n3176), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]), .CI(
n3175), .CO(n3177), .S(n3157) );
INVX4TS U3498 ( .A(n5386), .Y(n5236) );
OAI211X1TS U3499 ( .A0(n5399), .A1(n5365), .B0(n5364), .C0(n5363), .Y(n1806)
);
ADDFHX2TS U3500 ( .A(n4050), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]), .CI(
n4049), .CO(n4051), .S(n4046) );
XNOR2X2TS U3501 ( .A(n4067), .B(n4062), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
XOR2X2TS U3502 ( .A(n3236), .B(n3235), .Y(n4205) );
OR2X4TS U3503 ( .A(n3172), .B(n3171), .Y(n3173) );
INVX4TS U3504 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n2684) );
NOR2X8TS U3505 ( .A(n3069), .B(n4234), .Y(n4454) );
NOR2X4TS U3506 ( .A(n2832), .B(n2831), .Y(n2855) );
NAND2X4TS U3507 ( .A(n2680), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .Y(n2695) );
OR2X4TS U3508 ( .A(n2787), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n3075)
);
ADDFHX2TS U3509 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]), .B(n3329), .CI(n3201), .CO(n3202), .S(n3185) );
NOR2X8TS U3510 ( .A(DP_OP_499J223_125_1651_n227), .B(
DP_OP_499J223_125_1651_n225), .Y(n3040) );
NOR2X4TS U3511 ( .A(n3229), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n3308)
);
AOI21X2TS U3512 ( .A0(n3152), .A1(n3170), .B0(n3168), .Y(n3125) );
INVX2TS U3513 ( .A(n3168), .Y(n3150) );
NAND2X6TS U3514 ( .A(n3066), .B(n3065), .Y(n4330) );
NOR2X6TS U3515 ( .A(n3068), .B(n3067), .Y(n4190) );
OAI22X4TS U3516 ( .A0(n3709), .A1(n3693), .B0(n3708), .B1(n3694), .Y(n3662)
);
OAI2BB1X4TS U3517 ( .A0N(n2864), .A1N(n2863), .B0(n2212), .Y(n2211) );
OA21X4TS U3518 ( .A0(n2862), .A1(n2861), .B0(n2860), .Y(n2212) );
NOR2X6TS U3519 ( .A(n2970), .B(n2886), .Y(n2878) );
INVX4TS U3520 ( .A(n4228), .Y(DP_OP_499J223_125_1651_n272) );
XOR2X4TS U3521 ( .A(n3003), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n2213) );
OAI21X2TS U3522 ( .A0(n6285), .A1(n6282), .B0(n6286), .Y(n6292) );
AOI21X4TS U3523 ( .A0(n2955), .A1(n2953), .B0(n2725), .Y(n2968) );
CLKXOR2X4TS U3524 ( .A(n2740), .B(n2739), .Y(n3065) );
INVX6TS U3525 ( .A(n4206), .Y(DP_OP_499J223_125_1651_n299) );
OR2X4TS U3526 ( .A(n3914), .B(n3450), .Y(n2249) );
OAI22X2TS U3527 ( .A0(n2334), .A1(n3694), .B0(n2335), .B1(n3693), .Y(
DP_OP_501J223_127_5235_n208) );
INVX8TS U3528 ( .A(n6770), .Y(n6584) );
CMPR42X2TS U3529 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .C(
DP_OP_499J223_125_1651_n229), .D(DP_OP_499J223_125_1651_n274), .ICI(
n3410), .S(DP_OP_499J223_125_1651_n228), .ICO(
DP_OP_499J223_125_1651_n226), .CO(DP_OP_499J223_125_1651_n227) );
NAND2X2TS U3530 ( .A(n4032), .B(n4037), .Y(n4036) );
INVX4TS U3531 ( .A(n3012), .Y(n2749) );
OAI22X1TS U3532 ( .A0(n3968), .A1(n3866), .B0(n3913), .B1(n2394), .Y(n3911)
);
NAND2X4TS U3533 ( .A(n3864), .B(n3967), .Y(n3968) );
NOR2X2TS U3534 ( .A(n3993), .B(n3995), .Y(n3989) );
NOR2X4TS U3535 ( .A(n3940), .B(n3939), .Y(n3993) );
CMPR42X2TS U3536 ( .A(DP_OP_501J223_127_5235_n229), .B(
DP_OP_501J223_127_5235_n184), .C(DP_OP_501J223_127_5235_n178), .D(
DP_OP_501J223_127_5235_n237), .ICI(DP_OP_501J223_127_5235_n253), .S(
DP_OP_501J223_127_5235_n176), .ICO(DP_OP_501J223_127_5235_n174), .CO(
DP_OP_501J223_127_5235_n175) );
ADDFHX2TS U3537 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]), .B(n3183), .CI(n3182), .CO(n3184), .S(n3178) );
NOR2X6TS U3538 ( .A(n3321), .B(n3315), .Y(n3317) );
NAND2X4TS U3539 ( .A(n3229), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n3310)
);
XOR2X4TS U3540 ( .A(n3640), .B(n3639), .Y(n3641) );
INVX4TS U3541 ( .A(n2664), .Y(n2646) );
OAI21X2TS U3542 ( .A0(n6267), .A1(n6263), .B0(n6264), .Y(n6246) );
NAND2X4TS U3543 ( .A(DP_OP_499J223_125_1651_n228), .B(
DP_OP_499J223_125_1651_n230), .Y(n3025) );
NOR2X8TS U3544 ( .A(DP_OP_499J223_125_1651_n228), .B(
DP_OP_499J223_125_1651_n230), .Y(n3024) );
OAI21X1TS U3545 ( .A0(n3787), .A1(n3783), .B0(n3784), .Y(n3782) );
CMPR42X2TS U3546 ( .A(DP_OP_501J223_127_5235_n508), .B(
DP_OP_501J223_127_5235_n465), .C(DP_OP_501J223_127_5235_n462), .D(
DP_OP_501J223_127_5235_n459), .ICI(DP_OP_501J223_127_5235_n466), .S(
DP_OP_501J223_127_5235_n457), .ICO(DP_OP_501J223_127_5235_n455), .CO(
DP_OP_501J223_127_5235_n456) );
INVX4TS U3547 ( .A(n2240), .Y(n6588) );
INVX4TS U3548 ( .A(n4208), .Y(DP_OP_499J223_125_1651_n303) );
NAND2X4TS U3549 ( .A(DP_OP_499J223_125_1651_n243), .B(
DP_OP_499J223_125_1651_n245), .Y(n2999) );
CMPR42X4TS U3550 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .C(
DP_OP_499J223_125_1651_n244), .D(DP_OP_499J223_125_1651_n279), .ICI(
DP_OP_499J223_125_1651_n303), .S(DP_OP_499J223_125_1651_n243), .ICO(
DP_OP_499J223_125_1651_n241), .CO(DP_OP_499J223_125_1651_n242) );
OR2X8TS U3551 ( .A(DP_OP_499J223_125_1651_n243), .B(
DP_OP_499J223_125_1651_n245), .Y(n2998) );
INVX8TS U3552 ( .A(n2766), .Y(n3051) );
NOR2X8TS U3553 ( .A(n2783), .B(n2782), .Y(n2802) );
ADDFHX4TS U3554 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]), .B(n2781), .CI(n2780), .CO(n2782), .S(n2686) );
OAI21X4TS U3555 ( .A0(n3233), .A1(n3213), .B0(n3212), .Y(n3214) );
NOR2X8TS U3556 ( .A(DP_OP_499J223_125_1651_n218), .B(
DP_OP_499J223_125_1651_n216), .Y(n2762) );
NAND2X4TS U3557 ( .A(DP_OP_499J223_125_1651_n216), .B(
DP_OP_499J223_125_1651_n218), .Y(n2761) );
NOR2X6TS U3558 ( .A(n3101), .B(n3104), .Y(n3107) );
NOR2X4TS U3559 ( .A(n3330), .B(n3329), .Y(n3331) );
OAI21X1TS U3560 ( .A0(n3787), .A1(n3773), .B0(n3772), .Y(n3777) );
XNOR2X4TS U3561 ( .A(n3028), .B(n3027), .Y(n3036) );
XOR2X2TS U3562 ( .A(n4060), .B(n4059), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
NAND2X4TS U3563 ( .A(n3069), .B(n4234), .Y(n4453) );
ADDFHX4TS U3564 ( .A(n2672), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7]), .CI(
n2671), .CO(n2673), .S(n2653) );
NOR2X2TS U3565 ( .A(n5502), .B(n5507), .Y(n3396) );
ADDHX1TS U3566 ( .A(n4340), .B(n4339), .CO(DP_OP_502J223_128_4510_n132), .S(
n4253) );
OR2X8TS U3567 ( .A(n3058), .B(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(
n3284) );
NAND2X2TS U3568 ( .A(n4146), .B(n4148), .Y(n4147) );
AOI21X4TS U3569 ( .A0(n4416), .A1(n4413), .B0(n4270), .Y(n6148) );
OAI21X4TS U3570 ( .A0(n6168), .A1(n6162), .B0(n6163), .Y(n4416) );
OAI21X4TS U3571 ( .A0(n6047), .A1(n6041), .B0(n6042), .Y(n6075) );
XNOR2X1TS U3572 ( .A(n3914), .B(n2205), .Y(n3897) );
OAI22X2TS U3573 ( .A0(n3703), .A1(n3696), .B0(n2331), .B1(n3695), .Y(n3672)
);
NAND2X4TS U3574 ( .A(FPMULT_Op_MY[12]), .B(DP_OP_501J223_127_5235_n897), .Y(
n3431) );
OAI21X4TS U3575 ( .A0(n4322), .A1(n4324), .B0(n4325), .Y(n3063) );
OR2X4TS U3576 ( .A(n6594), .B(FPMULT_Op_MY[3]), .Y(n2218) );
INVX6TS U3577 ( .A(n2214), .Y(n6594) );
OAI21X4TS U3578 ( .A0(n3380), .A1(n4431), .B0(n4433), .Y(n3383) );
NAND2X4TS U3579 ( .A(DP_OP_501J223_127_5235_n903), .B(n6955), .Y(n3371) );
AOI21X4TS U3580 ( .A0(n2246), .A1(n3482), .B0(n3468), .Y(n3488) );
OAI22X2TS U3581 ( .A0(n2331), .A1(n3698), .B0(n3679), .B1(n3697), .Y(n3683)
);
OAI21X2TS U3582 ( .A0(n4563), .A1(n4439), .B0(n4438), .Y(n2241) );
NAND2X1TS U3583 ( .A(n3361), .B(n4433), .Y(n3362) );
OAI21X2TS U3584 ( .A0(n4434), .A1(n4433), .B0(n4432), .Y(n4435) );
OR2X8TS U3585 ( .A(DP_OP_499J223_125_1651_n234), .B(
DP_OP_499J223_125_1651_n236), .Y(n2470) );
NAND2X4TS U3586 ( .A(DP_OP_499J223_125_1651_n234), .B(
DP_OP_499J223_125_1651_n236), .Y(n3012) );
XOR2X2TS U3587 ( .A(n4178), .B(n4177), .Y(FPMULT_Sgf_operation_Result[37])
);
OA21X1TS U3588 ( .A0(n5599), .A1(n5602), .B0(n5600), .Y(n5597) );
OAI21X1TS U3589 ( .A0(n5573), .A1(n5561), .B0(n5560), .Y(n5564) );
OAI21X2TS U3590 ( .A0(n3787), .A1(n3755), .B0(n3754), .Y(n3762) );
OAI211X1TS U3591 ( .A0(n5237), .A1(n5377), .B0(n5360), .C0(n5359), .Y(n1797)
);
NOR2X4TS U3592 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n4810), .Y(n5219) );
NAND2X4TS U3593 ( .A(DP_OP_499J223_125_1651_n210), .B(
DP_OP_499J223_125_1651_n212), .Y(n2790) );
NOR2X4TS U3594 ( .A(n3406), .B(n3400), .Y(n3402) );
AOI21X4TS U3595 ( .A0(n2649), .A1(n2626), .B0(n2594), .Y(n2601) );
XOR2X2TS U3596 ( .A(n3426), .B(DP_OP_499J223_125_1651_n299), .Y(
FPMULT_Sgf_operation_Result[38]) );
OAI21X4TS U3597 ( .A0(n3995), .A1(n4000), .B0(n3996), .Y(n3988) );
NAND2X4TS U3598 ( .A(n3940), .B(n3939), .Y(n4000) );
XNOR2X4TS U3599 ( .A(n3637), .B(n3636), .Y(n2243) );
AOI21X4TS U3600 ( .A0(n2375), .A1(n3339), .B0(n3338), .Y(n3342) );
XOR2X4TS U3601 ( .A(n3277), .B(n3276), .Y(n4227) );
AO21X4TS U3602 ( .A0(n4173), .A1(n3336), .B0(n3335), .Y(n3337) );
NOR2X6TS U3603 ( .A(n3406), .B(n3334), .Y(n3336) );
OR2X4TS U3604 ( .A(n2636), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n4211) );
NAND2X4TS U3605 ( .A(DP_OP_499J223_125_1651_n237), .B(
DP_OP_499J223_125_1651_n239), .Y(n3015) );
AO21X4TS U3606 ( .A0(n4173), .A1(n3356), .B0(n3355), .Y(n3357) );
XNOR2X4TS U3607 ( .A(n3582), .B(n3581), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11) );
OAI21X2TS U3608 ( .A0(n3587), .A1(n3583), .B0(n3584), .Y(n3582) );
OAI21X4TS U3609 ( .A0(n3519), .A1(n3518), .B0(n3517), .Y(n3625) );
NAND2X4TS U3610 ( .A(n2222), .B(n2249), .Y(n3518) );
INVX6TS U3611 ( .A(n2236), .Y(n5644) );
NAND2X4TS U3612 ( .A(n3284), .B(n4421), .Y(n4323) );
INVX4TS U3613 ( .A(n4145), .Y(n4150) );
XNOR2X4TS U3614 ( .A(n4040), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .Y(
n4031) );
AOI21X4TS U3615 ( .A0(n4173), .A1(n3402), .B0(n3401), .Y(n3413) );
OAI21X4TS U3616 ( .A0(n4166), .A1(n4165), .B0(n4164), .Y(n4172) );
AOI21X4TS U3617 ( .A0(n2204), .A1(n5925), .B0(n3007), .Y(n3008) );
AOI21X4TS U3618 ( .A0(n2881), .A1(n2882), .B0(n2744), .Y(n2812) );
OR2X4TS U3619 ( .A(DP_OP_499J223_125_1651_n249), .B(n2743), .Y(n2881) );
XOR2X4TS U3620 ( .A(n3001), .B(n3000), .Y(n3004) );
NAND2X4TS U3621 ( .A(DP_OP_499J223_125_1651_n249), .B(n2743), .Y(n2880) );
ADDFHX2TS U3622 ( .A(n3689), .B(n3688), .CI(n3687), .CO(
DP_OP_501J223_127_5235_n191), .S(n3497) );
AOI21X2TS U3623 ( .A0(n3050), .A1(n3051), .B0(n3049), .Y(n3056) );
NAND2X4TS U3624 ( .A(n2787), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n2808)
);
OAI21X4TS U3625 ( .A0(n3105), .A1(n3104), .B0(n3103), .Y(n3106) );
OAI21X2TS U3626 ( .A0(n3261), .A1(n3260), .B0(n3259), .Y(n3262) );
NOR2X6TS U3627 ( .A(n3225), .B(n3224), .Y(n3261) );
XNOR2X2TS U3628 ( .A(n4172), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
NOR2X2TS U3629 ( .A(n3427), .B(n2264), .Y(n3339) );
AOI21X4TS U3630 ( .A0(n2864), .A1(n2847), .B0(n2846), .Y(n2854) );
NOR2X4TS U3631 ( .A(n2945), .B(n2947), .Y(n2885) );
XOR2X1TS U3632 ( .A(n3983), .B(n3982), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12) );
XOR2X4TS U3633 ( .A(n3125), .B(n3124), .Y(n3126) );
XOR2X2TS U3634 ( .A(n2694), .B(n2693), .Y(n2698) );
NOR2X4TS U3635 ( .A(n2698), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n2736)
);
XOR2X4TS U3636 ( .A(n3014), .B(n3013), .Y(n3020) );
NOR2X8TS U3637 ( .A(n2876), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n2970)
);
AOI21X4TS U3638 ( .A0(n2244), .A1(n3437), .B0(n3436), .Y(n3525) );
XOR2X1TS U3639 ( .A(n3587), .B(n3586), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10) );
AOI21X2TS U3640 ( .A0(n4181), .A1(n3347), .B0(n3346), .Y(n3349) );
XOR2X4TS U3641 ( .A(n2610), .B(n2609), .Y(n2642) );
AOI21X4TS U3642 ( .A0(n2649), .A1(n2666), .B0(n2664), .Y(n2610) );
NOR2X4TS U3643 ( .A(n3345), .B(n3344), .Y(n3346) );
XOR2X4TS U3644 ( .A(n2601), .B(n2600), .Y(n2641) );
NOR2X4TS U3645 ( .A(n3423), .B(DP_OP_499J223_125_1651_n299), .Y(n3408) );
AOI21X4TS U3646 ( .A0(n4173), .A1(n4176), .B0(n3407), .Y(n3423) );
XOR2X4TS U3647 ( .A(n2872), .B(n2869), .Y(n2875) );
XOR2X4TS U3648 ( .A(n3349), .B(n3348), .Y(FPMULT_Sgf_operation_Result[43])
);
OAI21X4TS U3649 ( .A0(n2736), .A1(n2739), .B0(n2737), .Y(n2777) );
NAND2X2TS U3650 ( .A(n2721), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n2739)
);
XOR2X4TS U3651 ( .A(n3341), .B(n3270), .Y(n2265) );
XOR2X4TS U3652 ( .A(n3228), .B(n3227), .Y(n3229) );
NOR2X2TS U3653 ( .A(n3412), .B(DP_OP_499J223_125_1651_n297), .Y(n3404) );
XNOR2X4TS U3654 ( .A(n3863), .B(n2307), .Y(n3967) );
XOR2X4TS U3655 ( .A(n2916), .B(n2915), .Y(n2917) );
XOR2X4TS U3656 ( .A(n3056), .B(n3055), .Y(n3062) );
XOR2X4TS U3657 ( .A(n3360), .B(DP_OP_499J223_125_1651_n292), .Y(
FPMULT_Sgf_operation_Result[45]) );
AOI21X2TS U3658 ( .A0(n2375), .A1(n3359), .B0(n3358), .Y(n3360) );
OAI21X4TS U3659 ( .A0(n2947), .A1(n2961), .B0(n2948), .Y(n2884) );
NOR2X6TS U3660 ( .A(n2875), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n2947)
);
NOR2X4TS U3661 ( .A(n3418), .B(n3420), .Y(n3358) );
XOR2X4TS U3662 ( .A(n2854), .B(n2853), .Y(n2874) );
XOR2X4TS U3663 ( .A(n3459), .B(n3458), .Y(n3460) );
AOI21X4TS U3664 ( .A0(n3486), .A1(n2247), .B0(n3445), .Y(n3519) );
OAI21X4TS U3665 ( .A0(DP_OP_501J223_127_5235_n630), .A1(n3476), .B0(n3477),
.Y(n3486) );
XOR2X4TS U3666 ( .A(n3206), .B(n3205), .Y(n3207) );
AOI21X4TS U3667 ( .A0(n3267), .A1(n3200), .B0(n3199), .Y(n3206) );
INVX4TS U3668 ( .A(n3265), .Y(n3199) );
NOR2X4TS U3669 ( .A(n3428), .B(n2264), .Y(n3338) );
XOR2X4TS U3670 ( .A(n3319), .B(n3230), .Y(n4233) );
INVX8TS U3671 ( .A(n3333), .Y(n3319) );
AOI21X4TS U3672 ( .A0(n6157), .A1(n6153), .B0(n4269), .Y(n6168) );
OAI21X4TS U3673 ( .A0(n6130), .A1(n6124), .B0(n6125), .Y(n6157) );
OAI21X4TS U3674 ( .A0(n6120), .A1(n6114), .B0(n6115), .Y(n6140) );
OAI21X4TS U3675 ( .A0(n6085), .A1(n6079), .B0(n6080), .Y(n6177) );
NOR2X2TS U3676 ( .A(n3709), .B(n3692), .Y(n3663) );
MX2X1TS U3677 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
ADDHXLTS U3678 ( .A(DP_OP_501J223_127_5235_n944), .B(n2292), .CO(n3813), .S(
n3730) );
CMPR22X2TS U3679 ( .A(n3863), .B(n3648), .CO(n3647), .S(n3649) );
ADDHX1TS U3680 ( .A(n3684), .B(n3683), .CO(DP_OP_501J223_127_5235_n184), .S(
n3682) );
NAND2X1TS U3681 ( .A(n2249), .B(n3462), .Y(n3463) );
ADDHX1TS U3682 ( .A(n3839), .B(n3838), .CO(DP_OP_501J223_127_5235_n482), .S(
n3731) );
NAND2X2TS U3683 ( .A(n4317), .B(n2485), .Y(n3039) );
MX2X1TS U3684 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U3685 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
NOR2X4TS U3686 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .B(n2657),
.Y(n2841) );
NOR2X2TS U3687 ( .A(n3142), .B(n3145), .Y(n3148) );
NAND2X1TS U3688 ( .A(n2246), .B(n3481), .Y(n3483) );
OAI21X1TS U3689 ( .A0(n3816), .A1(n2402), .B0(n3749), .Y(n3750) );
NAND2X1TS U3690 ( .A(n3819), .B(n3818), .Y(n3820) );
NAND2X1TS U3691 ( .A(n3725), .B(n3814), .Y(n3726) );
INVX2TS U3692 ( .A(n3815), .Y(n3725) );
NOR2X2TS U3693 ( .A(n3626), .B(n3653), .Y(n3524) );
AOI222X1TS U3694 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n6813), .B0(n2524), .B1(
n2523), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n2465), .Y(n2528) );
AOI2BB2XLTS U3695 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n2397), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n2522), .Y(n2523) );
CLKAND2X2TS U3696 ( .A(n6568), .B(FPMULT_Op_MY[4]), .Y(n4770) );
CLKAND2X2TS U3697 ( .A(FPMULT_Op_MX[12]), .B(n2290), .Y(n4832) );
NAND2X1TS U3698 ( .A(n3530), .B(n3529), .Y(n3531) );
INVX2TS U3699 ( .A(n3528), .Y(n3530) );
INVX2TS U3700 ( .A(n2345), .Y(n3840) );
ADDHX1TS U3701 ( .A(n3835), .B(n3834), .CO(DP_OP_501J223_127_5235_n473), .S(
DP_OP_501J223_127_5235_n474) );
NOR2X2TS U3702 ( .A(n2325), .B(n3697), .Y(n3651) );
INVX4TS U3703 ( .A(n3539), .Y(n3693) );
INVX4TS U3704 ( .A(n3660), .Y(n3694) );
ADDFHX2TS U3705 ( .A(n3682), .B(n3681), .CI(n3680), .CO(
DP_OP_501J223_127_5235_n182), .S(DP_OP_501J223_127_5235_n183) );
NAND2X2TS U3706 ( .A(n2245), .B(n2454), .Y(n3471) );
OAI2BB2XLTS U3707 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n2541), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n2461), .Y(n2542) );
OAI2BB2XLTS U3708 ( .B0(n2540), .B1(n2547), .A0N(n2539), .A1N(n2538), .Y(
n2543) );
AOI21X2TS U3709 ( .A0(n2809), .A1(n3075), .B0(n3078), .Y(n2810) );
NAND2X4TS U3710 ( .A(n5461), .B(n6335), .Y(n5015) );
AOI21X1TS U3711 ( .A0(n5853), .A1(n5890), .B0(n5852), .Y(n5882) );
NOR2X2TS U3712 ( .A(n4323), .B(n4324), .Y(n3064) );
NAND2X2TS U3713 ( .A(n2245), .B(n3635), .Y(n3636) );
CLKAND2X2TS U3714 ( .A(n2311), .B(FPADDSUB_Data_array_SWR[18]), .Y(n4479) );
CLKAND2X2TS U3715 ( .A(n6809), .B(FPADDSUB_DMP_SFG[14]), .Y(n4396) );
NOR3X1TS U3716 ( .A(FPSENCOS_cont_var_out[0]), .B(n6802), .C(n4998), .Y(
n4997) );
BUFX3TS U3717 ( .A(n5053), .Y(n6509) );
MX2X1TS U3718 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U3719 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
INVX2TS U3720 ( .A(n3984), .Y(n3959) );
XNOR2X1TS U3721 ( .A(n3937), .B(n2205), .Y(n3882) );
INVX2TS U3722 ( .A(n3788), .Y(n3798) );
NAND2X1TS U3723 ( .A(n5647), .B(FPMULT_Op_MX[19]), .Y(n5671) );
OAI21X2TS U3724 ( .A0(n4066), .A1(n4065), .B0(n4064), .Y(n4084) );
OAI21X2TS U3725 ( .A0(n2662), .A1(n2661), .B0(n2660), .Y(n2663) );
OAI21X2TS U3726 ( .A0(n2646), .A1(n2659), .B0(n2661), .Y(n2647) );
NOR2X4TS U3727 ( .A(n2593), .B(n2592), .Y(n2602) );
CLKAND2X2TS U3728 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MY[14]), .Y(n4828) );
ADDHXLTS U3729 ( .A(n2285), .B(n2287), .CO(n3718), .S(n3714) );
NAND2X1TS U3730 ( .A(n3711), .B(n3720), .Y(n3712) );
INVX2TS U3731 ( .A(n3721), .Y(n3710) );
NOR2X1TS U3732 ( .A(n4297), .B(n4291), .Y(n4285) );
INVX2TS U3733 ( .A(n4221), .Y(n2624) );
ADDFHX2TS U3734 ( .A(n2368), .B(n3934), .CI(n3933), .CO(n3949), .S(n3929) );
INVX2TS U3735 ( .A(n3956), .Y(n3934) );
ADDFHX2TS U3736 ( .A(n3828), .B(n3827), .CI(n3826), .CO(
DP_OP_501J223_127_5235_n458), .S(DP_OP_501J223_127_5235_n459) );
INVX2TS U3737 ( .A(n3718), .Y(n3846) );
INVX2TS U3738 ( .A(n3714), .Y(n3847) );
INVX2TS U3739 ( .A(n3729), .Y(n3849) );
NAND2X1TS U3740 ( .A(n3715), .B(n3721), .Y(n3716) );
INVX4TS U3741 ( .A(n3493), .Y(n3701) );
OAI32X1TS U3742 ( .A0(n2530), .A1(n2529), .A2(n2528), .B0(n2527), .B1(n2529),
.Y(n2548) );
OAI22X1TS U3743 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2518), .B0(n2526), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n2529) );
NOR2X1TS U3744 ( .A(FPADDSUB_Raw_mant_NRM_SWR[22]), .B(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n5220) );
NOR2X1TS U3745 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n5224) );
OAI31X1TS U3746 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n6795), .A2(n5209),
.B0(n7063), .Y(n5211) );
INVX2TS U3747 ( .A(n5208), .Y(n5209) );
INVX2TS U3748 ( .A(n6186), .Y(n6231) );
OAI21X1TS U3749 ( .A0(n6186), .A1(n4260), .B0(n4259), .Y(n6034) );
NAND2X1TS U3750 ( .A(FPMULT_Sgf_normalized_result[3]), .B(
FPMULT_Sgf_normalized_result[2]), .Y(n5850) );
NAND3XLTS U3751 ( .A(n5838), .B(FPMULT_Op_MY[2]), .C(n2481), .Y(n5844) );
INVX2TS U3752 ( .A(n3973), .Y(n3961) );
OAI22X1TS U3753 ( .A0(n3883), .A1(n3901), .B0(n3868), .B1(
DP_OP_501J223_127_5235_n723), .Y(n3876) );
OAI22X1TS U3754 ( .A0(n2373), .A1(n3840), .B0(n2371), .B1(n2345), .Y(n3756)
);
NOR2X1TS U3755 ( .A(n2325), .B(n3695), .Y(DP_OP_501J223_127_5235_n214) );
NOR2X2TS U3756 ( .A(DP_OP_501J223_127_5235_n124), .B(
DP_OP_501J223_127_5235_n122), .Y(n3556) );
INVX4TS U3757 ( .A(n3484), .Y(n3702) );
NAND2X2TS U3758 ( .A(n2247), .B(n3485), .Y(n3487) );
AO22XLTS U3759 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2329), .Y(n4482) );
AO22XLTS U3760 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n2329), .B0(
FPADDSUB_Data_array_SWR[3]), .B1(n2342), .Y(n5942) );
AOI211X2TS U3761 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2312), .B0(n5948),
.C0(n5947), .Y(n5992) );
NOR2X4TS U3762 ( .A(n2622), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n2731) );
INVX4TS U3763 ( .A(n2216), .Y(n6569) );
INVX2TS U3764 ( .A(n5315), .Y(n2337) );
AO22XLTS U3765 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[1]), .B1(n2342), .Y(n5939) );
OR2X1TS U3766 ( .A(n5340), .B(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n5316) );
AOI2BB2XLTS U3767 ( .B0(n2360), .B1(n2256), .A0N(n2340), .A1N(
FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n5234) );
BUFX3TS U3768 ( .A(n5158), .Y(n5169) );
NOR2X2TS U3769 ( .A(n6562), .B(n6556), .Y(n5158) );
INVX2TS U3770 ( .A(n4502), .Y(n4519) );
INVX2TS U3771 ( .A(n2337), .Y(n2338) );
INVX2TS U3772 ( .A(n5237), .Y(n2353) );
AOI21X2TS U3773 ( .A0(n6155), .A1(n4409), .B0(n4408), .Y(n6166) );
CLKAND2X2TS U3774 ( .A(n6824), .B(FPADDSUB_DMP_SFG[20]), .Y(n4408) );
INVX2TS U3775 ( .A(n6089), .Y(n6091) );
CLKAND2X2TS U3776 ( .A(n6862), .B(FPADDSUB_DMP_SFG[12]), .Y(n4392) );
INVX2TS U3777 ( .A(n6041), .Y(n6043) );
CLKAND2X2TS U3778 ( .A(n6818), .B(FPADDSUB_DMP_SFG[18]), .Y(n4404) );
CLKAND2X2TS U3779 ( .A(n6808), .B(FPADDSUB_DMP_SFG[16]), .Y(n4400) );
AO21XLTS U3780 ( .A0(n5742), .A1(n5741), .B0(n5740), .Y(intadd_512_CI) );
AO21XLTS U3781 ( .A0(n5716), .A1(n5715), .B0(n5714), .Y(intadd_512_A_0_) );
OR2X1TS U3782 ( .A(n5454), .B(n5460), .Y(n4579) );
NAND3XLTS U3783 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[29]), .Y(n6329) );
AOI31XLTS U3784 ( .A0(n6327), .A1(n6326), .A2(n6325), .B0(n6332), .Y(n6330)
);
NOR3BX2TS U3785 ( .AN(n2298), .B(n6371), .C(n6369), .Y(n6358) );
NOR3XLTS U3786 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n6314) );
NOR2X1TS U3787 ( .A(n3970), .B(n3969), .Y(n3979) );
NAND2X1TS U3788 ( .A(n3970), .B(n3969), .Y(n3980) );
AOI21X2TS U3789 ( .A0(n3988), .A1(n2476), .B0(n3945), .Y(n3946) );
INVX2TS U3790 ( .A(n3990), .Y(n3945) );
INVX2TS U3791 ( .A(n4013), .Y(n4004) );
OAI22X1TS U3792 ( .A0(n3887), .A1(n3901), .B0(n3882), .B1(
DP_OP_501J223_127_5235_n723), .Y(n3891) );
ADDHX1TS U3793 ( .A(n3895), .B(n3894), .CO(n4020), .S(n4022) );
OAI22X1TS U3794 ( .A0(n3887), .A1(DP_OP_501J223_127_5235_n723), .B0(n3901),
.B1(n3897), .Y(n3895) );
NOR2X2TS U3795 ( .A(n3759), .B(n3758), .Y(n3765) );
INVX2TS U3796 ( .A(n3774), .Y(n3753) );
NAND2X1TS U3797 ( .A(n3759), .B(n3758), .Y(n3764) );
NOR2X2TS U3798 ( .A(n3783), .B(n3778), .Y(n3770) );
INVX2TS U3799 ( .A(n3771), .Y(n3772) );
NOR2X4TS U3800 ( .A(DP_OP_501J223_127_5235_n449), .B(
DP_OP_501J223_127_5235_n451), .Y(n3778) );
NOR2X2TS U3801 ( .A(DP_OP_501J223_127_5235_n452), .B(
DP_OP_501J223_127_5235_n456), .Y(n3783) );
NOR2X4TS U3802 ( .A(DP_OP_501J223_127_5235_n464), .B(
DP_OP_501J223_127_5235_n469), .Y(n3794) );
INVX2TS U3803 ( .A(n3804), .Y(n3742) );
NOR2X2TS U3804 ( .A(DP_OP_501J223_127_5235_n470), .B(
DP_OP_501J223_127_5235_n476), .Y(n3799) );
INVX2TS U3805 ( .A(n3571), .Y(n3572) );
NOR2X4TS U3806 ( .A(DP_OP_501J223_127_5235_n129), .B(
DP_OP_501J223_127_5235_n125), .Y(n3578) );
INVX2TS U3807 ( .A(n3620), .Y(n3498) );
INVX2TS U3808 ( .A(n3461), .Y(n3704) );
AO22XLTS U3809 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n3288), .B0(
FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n5959), .Y(n4360) );
AO22XLTS U3810 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n2343), .Y(n4361) );
AOI2BB2X1TS U3811 ( .B0(n2573), .B1(n2572), .A0N(n2571), .A1N(n2570), .Y(
n2574) );
NOR2BX1TS U3812 ( .AN(n2558), .B(n2557), .Y(n2576) );
OAI221XLTS U3813 ( .A0(n2413), .A1(FPADDSUB_intDY_EWSW[13]), .B0(n2411),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n6670), .Y(n6675) );
OAI221XLTS U3814 ( .A0(n6811), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2408),
.B1(FPADDSUB_intDY_EWSW[16]), .C0(n6686), .Y(n6700) );
BUFX3TS U3815 ( .A(n2322), .Y(n5312) );
BUFX3TS U3816 ( .A(n2322), .Y(n5310) );
BUFX3TS U3817 ( .A(n5118), .Y(n5136) );
BUFX3TS U3818 ( .A(n5158), .Y(n5137) );
BUFX3TS U3819 ( .A(n5118), .Y(n5139) );
BUFX3TS U3820 ( .A(n5158), .Y(n5140) );
AND3X1TS U3821 ( .A(n5260), .B(n5259), .C(n5258), .Y(n5380) );
INVX2TS U3822 ( .A(n2252), .Y(n2355) );
INVX2TS U3823 ( .A(n2337), .Y(n2339) );
AND3X1TS U3824 ( .A(n5324), .B(n5323), .C(n5322), .Y(n5385) );
MX2X1TS U3825 ( .A(FPMULT_Add_result[23]), .B(n5855), .S0(n5931), .Y(n1597)
);
NAND4XLTS U3826 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n6018) );
XNOR2X1TS U3827 ( .A(n4014), .B(n4013), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6) );
NAND2X1TS U3828 ( .A(n4012), .B(n4011), .Y(n4014) );
INVX2TS U3829 ( .A(n4010), .Y(n4012) );
INVX2TS U3830 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(n2817)
);
NAND2X1TS U3831 ( .A(n4057), .B(n4056), .Y(n4064) );
OR2X2TS U3832 ( .A(n2684), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(n2685) );
AOI21X2TS U3833 ( .A0(n4108), .A1(n4107), .B0(n4106), .Y(n4119) );
INVX2TS U3834 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n3183) );
INVX2TS U3835 ( .A(n3485), .Y(n3445) );
OAI21X2TS U3836 ( .A0(n4039), .A1(n4038), .B0(n4037), .Y(n4145) );
INVX2TS U3837 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n4030) );
NAND2X1TS U3838 ( .A(n2822), .B(n2815), .Y(n2675) );
AOI21X1TS U3839 ( .A0(n4067), .A1(n4061), .B0(n4053), .Y(n4060) );
NOR2X2TS U3840 ( .A(n4071), .B(n4070), .Y(n4167) );
NOR2X1TS U3841 ( .A(n3271), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n3305) );
NAND2X1TS U3842 ( .A(n3271), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n3304) );
OAI21X2TS U3843 ( .A0(n3150), .A1(n3164), .B0(n2200), .Y(n3151) );
INVX2TS U3844 ( .A(n3181), .Y(n3197) );
OR2X2TS U3845 ( .A(n3178), .B(n3177), .Y(n3194) );
INVX2TS U3846 ( .A(n3115), .Y(n3084) );
INVX2TS U3847 ( .A(n3817), .Y(n3819) );
NOR2X2TS U3848 ( .A(FPMULT_Op_MY[9]), .B(n6585), .Y(n3815) );
NOR2X1TS U3849 ( .A(n3722), .B(n3719), .Y(n3724) );
OAI21X1TS U3850 ( .A0(n3722), .A1(n3721), .B0(n3720), .Y(n3723) );
INVX2TS U3851 ( .A(n3722), .Y(n3711) );
NAND2X2TS U3852 ( .A(n3921), .B(n3457), .Y(n3514) );
INVX2TS U3853 ( .A(n3462), .Y(n3516) );
INVX2TS U3854 ( .A(n3519), .Y(n3464) );
NAND2X1TS U3855 ( .A(n2481), .B(FPMULT_Op_MX[13]), .Y(n3481) );
NAND2BXLTS U3856 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n2520) );
OR2X2TS U3857 ( .A(n2581), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2586) );
NAND2X1TS U3858 ( .A(n4153), .B(n4152), .Y(n4154) );
XNOR2X1TS U3859 ( .A(n2728), .B(n6746), .Y(n4236) );
NAND2X1TS U3860 ( .A(n4035), .B(n4033), .Y(n2728) );
OR2X1TS U3861 ( .A(n2703), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n2704) );
NAND2X1TS U3862 ( .A(n2868), .B(n2870), .Y(n2869) );
NAND2X1TS U3863 ( .A(n2692), .B(n2691), .Y(n2694) );
NAND2X1TS U3864 ( .A(n2654), .B(n2660), .Y(n2655) );
NAND2X2TS U3865 ( .A(n2589), .B(n2588), .Y(n2632) );
XOR2X1TS U3866 ( .A(n4171), .B(n4170), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
INVX2TS U3867 ( .A(n4225), .Y(DP_OP_499J223_125_1651_n276) );
INVX2TS U3868 ( .A(n4203), .Y(DP_OP_499J223_125_1651_n293) );
NAND2X1TS U3869 ( .A(n3226), .B(n3259), .Y(n3227) );
NAND2X1TS U3870 ( .A(n3204), .B(n3260), .Y(n3205) );
AOI21X2TS U3871 ( .A0(n4437), .A1(n4436), .B0(n4435), .Y(n4563) );
NOR2X1TS U3872 ( .A(n4434), .B(n4431), .Y(n4436) );
NAND2X1TS U3873 ( .A(n6588), .B(n5646), .Y(n4561) );
NAND2X1TS U3874 ( .A(n5644), .B(FPMULT_Op_MY[2]), .Y(n4433) );
INVX2TS U3875 ( .A(n3507), .Y(n3436) );
INVX2TS U3876 ( .A(n3510), .Y(n3437) );
NAND2X1TS U3877 ( .A(DP_OP_501J223_127_5235_n903), .B(n2291), .Y(n3529) );
INVX2TS U3878 ( .A(n3447), .Y(n3451) );
INVX2TS U3879 ( .A(n3441), .Y(n3432) );
CLKAND2X2TS U3880 ( .A(n6569), .B(FPMULT_Op_MY[2]), .Y(n4766) );
ADDHXLTS U3881 ( .A(n6572), .B(n6567), .CO(n3747), .S(n3825) );
INVX2TS U3882 ( .A(n3719), .Y(n3715) );
ADDFHX2TS U3883 ( .A(n3672), .B(n3671), .CI(n3670), .CO(
DP_OP_501J223_127_5235_n167), .S(DP_OP_501J223_127_5235_n168) );
INVX2TS U3884 ( .A(n3481), .Y(n3468) );
NAND2X1TS U3885 ( .A(n2344), .B(FPMULT_Op_MX[5]), .Y(n3536) );
CLKAND2X2TS U3886 ( .A(n4305), .B(n2463), .Y(n4303) );
NAND2X4TS U3887 ( .A(n2587), .B(n2586), .Y(n2628) );
INVX2TS U3888 ( .A(n6746), .Y(n2727) );
NAND2X1TS U3889 ( .A(n2608), .B(n2661), .Y(n2609) );
OR2X1TS U3890 ( .A(n2713), .B(n2712), .Y(n2938) );
NAND2X1TS U3891 ( .A(n2705), .B(n2704), .Y(n2908) );
NAND2X2TS U3892 ( .A(n2875), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n2948)
);
INVX4TS U3893 ( .A(n2992), .Y(n2964) );
OAI21X2TS U3894 ( .A0(n2755), .A1(n3052), .B0(n3053), .Y(n2756) );
INVX2TS U3895 ( .A(n2808), .Y(n3078) );
INVX2TS U3896 ( .A(n2841), .Y(n2888) );
NAND2X1TS U3897 ( .A(n2742), .B(n2741), .Y(n2966) );
XNOR2X1TS U3898 ( .A(n2697), .B(n2904), .Y(n2721) );
NAND2X1TS U3899 ( .A(n2696), .B(n2695), .Y(n2697) );
INVX2TS U3900 ( .A(n3023), .Y(n3034) );
NOR2X1TS U3901 ( .A(n4903), .B(n5760), .Y(n4889) );
CLKAND2X2TS U3902 ( .A(DP_OP_501J223_127_5235_n944), .B(n5644), .Y(n4870) );
ADDHX1TS U3903 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .B(
DP_OP_499J223_125_1651_n202), .CO(n3137), .S(n3110) );
INVX2TS U3904 ( .A(n2789), .Y(n2771) );
NAND2X1TS U3905 ( .A(n3275), .B(n3309), .Y(n3276) );
NAND2X1TS U3906 ( .A(DP_OP_499J223_125_1651_n203), .B(n3110), .Y(n3131) );
NOR2X6TS U3907 ( .A(n3207), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n3213)
);
OAI21X2TS U3908 ( .A0(n3191), .A1(n3211), .B0(n3233), .Y(n3192) );
NAND2X2TS U3909 ( .A(n3207), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n3212)
);
CMPR42X1TS U3910 ( .A(DP_OP_502J223_128_4510_n150), .B(
DP_OP_502J223_128_4510_n157), .C(DP_OP_502J223_128_4510_n185), .D(
DP_OP_502J223_128_4510_n164), .ICI(DP_OP_502J223_128_4510_n124), .S(
DP_OP_502J223_128_4510_n120), .ICO(DP_OP_502J223_128_4510_n118), .CO(
DP_OP_502J223_128_4510_n119) );
INVX2TS U3911 ( .A(n3363), .Y(n2313) );
INVX2TS U3912 ( .A(n3937), .Y(n3952) );
NOR2X2TS U3913 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n3506) );
NAND2X2TS U3914 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n3510) );
INVX4TS U3915 ( .A(n3505), .Y(n3527) );
NAND2X1TS U3916 ( .A(n3643), .B(n3642), .Y(n3644) );
INVX2TS U3917 ( .A(n3489), .Y(n3633) );
NAND2X1TS U3918 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n3489) );
INVX2TS U3919 ( .A(n3488), .Y(n3634) );
INVX2TS U3920 ( .A(n3446), .Y(n3452) );
NAND2X1TS U3921 ( .A(n4848), .B(n4847), .Y(n5710) );
INVX2TS U3922 ( .A(n3825), .Y(n3843) );
INVX2TS U3923 ( .A(n3747), .Y(n3842) );
ADDHX1TS U3924 ( .A(n3830), .B(n3829), .CO(DP_OP_501J223_127_5235_n460), .S(
n3826) );
OAI22X1TS U3925 ( .A0(n3848), .A1(n3844), .B0(n3852), .B1(n3845), .Y(n3823)
);
INVX2TS U3926 ( .A(n3730), .Y(n3845) );
INVX2TS U3927 ( .A(n3813), .Y(n3844) );
NOR2X1TS U3928 ( .A(n2486), .B(n3701), .Y(DP_OP_501J223_127_5235_n241) );
OAI22X1TS U3929 ( .A0(n3706), .A1(n3698), .B0(n2334), .B1(n3697), .Y(
DP_OP_501J223_127_5235_n225) );
CMPR42X1TS U3930 ( .A(DP_OP_501J223_127_5235_n203), .B(
DP_OP_501J223_127_5235_n211), .C(DP_OP_501J223_127_5235_n169), .D(
DP_OP_501J223_127_5235_n219), .ICI(DP_OP_501J223_127_5235_n227), .S(
DP_OP_501J223_127_5235_n160), .ICO(DP_OP_501J223_127_5235_n158), .CO(
DP_OP_501J223_127_5235_n159) );
NOR2X1TS U3931 ( .A(n2332), .B(n3692), .Y(DP_OP_501J223_127_5235_n203) );
INVX6TS U3932 ( .A(n3631), .Y(n3707) );
INVX4TS U3933 ( .A(n3658), .Y(n3708) );
ADDHX1TS U3934 ( .A(n3686), .B(n3685), .CO(n3680), .S(
DP_OP_501J223_127_5235_n190) );
ADDHX1TS U3935 ( .A(n3691), .B(n3690), .CO(DP_OP_501J223_127_5235_n193), .S(
n3687) );
ADDHX1TS U3936 ( .A(n3492), .B(n2205), .CO(n3493), .S(n3484) );
NAND2X4TS U3937 ( .A(n2196), .B(n3440), .Y(n3477) );
NOR2X2TS U3938 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .Y(n3542) );
AOI21X2TS U3939 ( .A0(n2456), .A1(n3473), .B0(n3472), .Y(n3540) );
INVX2TS U3940 ( .A(n3642), .Y(n3473) );
INVX2TS U3941 ( .A(n3536), .Y(n3472) );
NAND2X1TS U3942 ( .A(n2456), .B(n3643), .Y(n3541) );
NAND2X1TS U3943 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .Y(n3543) );
INVX2TS U3944 ( .A(n4288), .Y(n2318) );
INVX2TS U3945 ( .A(n4288), .Y(n2319) );
NAND2X1TS U3946 ( .A(n4293), .B(n4292), .Y(n4294) );
NOR2X1TS U3947 ( .A(n2239), .B(n4968), .Y(n4969) );
NOR2X1TS U3948 ( .A(n5446), .B(n5671), .Y(n4941) );
OR2X4TS U3949 ( .A(n2582), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .Y(
n2620) );
NAND2X1TS U3950 ( .A(n2599), .B(n2603), .Y(n2600) );
INVX2TS U3951 ( .A(n4199), .Y(n2638) );
OR2X1TS U3952 ( .A(n2700), .B(n2727), .Y(n2903) );
NOR2X6TS U3953 ( .A(n2642), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n2897)
);
NAND2X2TS U3954 ( .A(n2642), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n2898)
);
INVX4TS U3955 ( .A(n4197), .Y(n4213) );
NOR2XLTS U3956 ( .A(n4518), .B(n4371), .Y(n4373) );
NAND2X1TS U3957 ( .A(n3098), .B(n3103), .Y(n3099) );
OR2X1TS U3958 ( .A(n2721), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n2722)
);
NAND2X1TS U3959 ( .A(n3054), .B(n3053), .Y(n3055) );
NOR2X4TS U3960 ( .A(n3062), .B(n3061), .Y(n4324) );
CLKAND2X2TS U3961 ( .A(n6863), .B(FPADDSUB_DMP_SFG[9]), .Y(n4384) );
OR2X1TS U3962 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n6031) );
OA21X1TS U3963 ( .A0(n4871), .A1(n4870), .B0(n4891), .Y(n5774) );
NAND2X1TS U3964 ( .A(n3323), .B(n3322), .Y(n3324) );
NAND2X1TS U3965 ( .A(n3234), .B(n3233), .Y(n3235) );
NAND2X1TS U3966 ( .A(n3256), .B(n3310), .Y(n3230) );
NAND2X1TS U3967 ( .A(n3352), .B(n3351), .Y(n3354) );
NAND2X1TS U3968 ( .A(n4205), .B(n4206), .Y(n3400) );
CMPR42X1TS U3969 ( .A(DP_OP_502J223_128_4510_n137), .B(
DP_OP_502J223_128_4510_n180), .C(DP_OP_502J223_128_4510_n187), .D(
DP_OP_502J223_128_4510_n134), .ICI(DP_OP_502J223_128_4510_n131), .S(
DP_OP_502J223_128_4510_n129), .ICO(DP_OP_502J223_128_4510_n127), .CO(
DP_OP_502J223_128_4510_n128) );
OR2X1TS U3970 ( .A(DP_OP_501J223_127_5235_n903), .B(n6955), .Y(n3372) );
INVX2TS U3971 ( .A(n3951), .Y(n3965) );
ADDFX2TS U3972 ( .A(n3927), .B(n3926), .CI(n3925), .CO(n3941), .S(n3940) );
XNOR2X2TS U3973 ( .A(n3634), .B(n3490), .Y(n3860) );
NAND2X1TS U3974 ( .A(n2454), .B(n3489), .Y(n3490) );
NAND2X1TS U3975 ( .A(n2444), .B(n3441), .Y(n3443) );
AO21XLTS U3976 ( .A0(n5693), .A1(n5691), .B0(n5692), .Y(n4865) );
AO21XLTS U3977 ( .A0(n5798), .A1(n5796), .B0(n5797), .Y(n4803) );
OAI21XLTS U3978 ( .A0(n5835), .A1(n5834), .B0(n5836), .Y(n4776) );
CMPR42X1TS U3979 ( .A(DP_OP_501J223_127_5235_n511), .B(
DP_OP_501J223_127_5235_n523), .C(DP_OP_501J223_127_5235_n517), .D(
DP_OP_501J223_127_5235_n482), .ICI(DP_OP_501J223_127_5235_n479), .S(
DP_OP_501J223_127_5235_n477), .ICO(DP_OP_501J223_127_5235_n475), .CO(
DP_OP_501J223_127_5235_n476) );
OAI22X1TS U3980 ( .A0(n3850), .A1(n3851), .B0(n2293), .B1(n3849), .Y(n3732)
);
ADDHX1TS U3981 ( .A(n3735), .B(n3734), .CO(n3738), .S(n3737) );
OAI22X1TS U3982 ( .A0(n2294), .A1(n3851), .B0(n2370), .B1(n3849), .Y(n3736)
);
INVX2TS U3983 ( .A(n3728), .Y(n3851) );
NOR2XLTS U3984 ( .A(n2325), .B(n3693), .Y(n3553) );
OR2X1TS U3985 ( .A(n2291), .B(FPMULT_Op_MY[12]), .Y(n4341) );
INVX4TS U3986 ( .A(n2237), .Y(n6585) );
NOR2X1TS U3987 ( .A(n4975), .B(n4973), .Y(n5443) );
NOR2X1TS U3988 ( .A(n4962), .B(n4963), .Y(n5444) );
OA21X1TS U3989 ( .A0(FPMULT_Op_MX[19]), .A1(n2315), .B0(n5445), .Y(n5440) );
NAND2X1TS U3990 ( .A(n5224), .B(n5220), .Y(n4808) );
NOR2BX1TS U3991 ( .AN(n2556), .B(n2555), .Y(n2557) );
NAND2BX1TS U3992 ( .AN(n2554), .B(n2553), .Y(n2555) );
AOI221X1TS U3993 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n2412), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n2430), .C0(n2569), .Y(n2571) );
NAND4XLTS U3994 ( .A(n6697), .B(n6696), .C(n6695), .D(n6694), .Y(n6698) );
AOI221X1TS U3995 ( .A0(n2432), .A1(FPADDSUB_intDY_EWSW[17]), .B0(
FPADDSUB_intDY_EWSW[24]), .B1(n6803), .C0(n6693), .Y(n6694) );
OAI221X1TS U3996 ( .A0(n2407), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2269),
.B1(FPADDSUB_intDY_EWSW[7]), .C0(n6677), .Y(n6684) );
NAND2X1TS U3997 ( .A(n5978), .B(n5977), .Y(n5981) );
NAND2X1TS U3998 ( .A(n5976), .B(n5975), .Y(n5980) );
NAND2X1TS U3999 ( .A(n5984), .B(n5979), .Y(n6627) );
AOI31XLTS U4000 ( .A0(n6758), .A1(n6800), .A2(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B0(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n5222) );
NAND2X4TS U4001 ( .A(n2623), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n4221) );
NAND2X4TS U4002 ( .A(n2641), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n4216) );
NOR2X6TS U4003 ( .A(n2641), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n4215) );
INVX2TS U4004 ( .A(n2896), .Y(n4219) );
INVX4TS U4005 ( .A(n2406), .Y(n6579) );
OAI21XLTS U4006 ( .A0(n6213), .A1(n6198), .B0(n6197), .Y(n6203) );
OAI21XLTS U4007 ( .A0(n4519), .A1(n4518), .B0(n4517), .Y(n4522) );
MX2X1TS U4008 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U4009 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U4010 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
NOR2X1TS U4011 ( .A(n5882), .B(n5854), .Y(n5880) );
NAND3XLTS U4012 ( .A(n5757), .B(FPMULT_Op_MY[8]), .C(FPMULT_Op_MX[7]), .Y(
n5759) );
NAND2X4TS U4013 ( .A(n3249), .B(n4207), .Y(n4175) );
INVX2TS U4014 ( .A(n4196), .Y(DP_OP_499J223_125_1651_n292) );
AO21XLTS U4015 ( .A0(n5714), .A1(n5711), .B0(n5712), .Y(n4826) );
AO21XLTS U4016 ( .A0(n5816), .A1(n5817), .B0(n5818), .Y(n4764) );
AO21XLTS U4017 ( .A0(n5477), .A1(n5476), .B0(n5816), .Y(intadd_514_A_0_) );
AO21XLTS U4018 ( .A0(n5845), .A1(n5844), .B0(n5843), .Y(intadd_514_CI) );
OAI22X1TS U4019 ( .A0(n3965), .A1(n3974), .B0(n3964), .B1(n3639), .Y(n3972)
);
AO21XLTS U4020 ( .A0(n3968), .A1(n2394), .B0(n3966), .Y(n3971) );
OR2X1TS U4021 ( .A(n3974), .B(n3639), .Y(n2473) );
NAND2X1TS U4022 ( .A(n3958), .B(n3957), .Y(n3984) );
NAND2X1TS U4023 ( .A(n3944), .B(n3943), .Y(n3990) );
INVX2TS U4024 ( .A(n4000), .Y(n3994) );
INVX2TS U4025 ( .A(n3987), .Y(n4003) );
INVX2TS U4026 ( .A(n3993), .Y(n4001) );
CLKAND2X2TS U4027 ( .A(n2346), .B(n5642), .Y(intadd_513_A_7_) );
AO21XLTS U4028 ( .A0(n4925), .A1(n4926), .B0(n4924), .Y(n4426) );
NOR2X2TS U4029 ( .A(DP_OP_501J223_127_5235_n457), .B(
DP_OP_501J223_127_5235_n463), .Y(n3789) );
NAND2X1TS U4030 ( .A(DP_OP_501J223_127_5235_n457), .B(
DP_OP_501J223_127_5235_n463), .Y(n3790) );
NAND2X1TS U4031 ( .A(DP_OP_501J223_127_5235_n477), .B(n3741), .Y(n3804) );
NAND2X1TS U4032 ( .A(n3739), .B(n3738), .Y(n3806) );
OAI21X1TS U4033 ( .A0(n3809), .A1(n3856), .B0(n3810), .Y(n3807) );
NAND2X1TS U4034 ( .A(n3737), .B(n3736), .Y(n3810) );
INVX2TS U4035 ( .A(n3554), .Y(n3557) );
OAI21X1TS U4036 ( .A0(n3574), .A1(n3565), .B0(n3566), .Y(n3548) );
NAND2X2TS U4037 ( .A(DP_OP_501J223_127_5235_n129), .B(
DP_OP_501J223_127_5235_n125), .Y(n3579) );
NAND2X4TS U4038 ( .A(DP_OP_501J223_127_5235_n144), .B(
DP_OP_501J223_127_5235_n153), .Y(n3595) );
NAND2X2TS U4039 ( .A(DP_OP_501J223_127_5235_n136), .B(
DP_OP_501J223_127_5235_n143), .Y(n3590) );
INVX2TS U4040 ( .A(n3604), .Y(n3502) );
NAND2X2TS U4041 ( .A(DP_OP_501J223_127_5235_n154), .B(
DP_OP_501J223_127_5235_n162), .Y(n3600) );
NAND2X2TS U4042 ( .A(DP_OP_501J223_127_5235_n181), .B(
DP_OP_501J223_127_5235_n187), .Y(n3612) );
OAI21X2TS U4043 ( .A0(n3615), .A1(n3618), .B0(n3616), .Y(n3613) );
NAND2X1TS U4044 ( .A(n3497), .B(n3496), .Y(n3620) );
ADDHX1TS U4045 ( .A(n3495), .B(n3494), .CO(n3688), .S(n3623) );
INVX2TS U4046 ( .A(n2253), .Y(n2332) );
INVX2TS U4047 ( .A(n3466), .Y(n3705) );
NAND2X2TS U4048 ( .A(n5143), .B(n6022), .Y(n6626) );
AND2X2TS U4049 ( .A(n2720), .B(n2734), .Y(n6275) );
OR2X1TS U4050 ( .A(n2719), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n2720) );
XOR2X2TS U4051 ( .A(n2735), .B(n2734), .Y(n6276) );
NAND2X2TS U4052 ( .A(n2733), .B(n2732), .Y(n2735) );
XNOR2X1TS U4053 ( .A(n4224), .B(n4223), .Y(n6274) );
NAND2X1TS U4054 ( .A(n4222), .B(n4221), .Y(n4224) );
INVX2TS U4055 ( .A(rst), .Y(n4491) );
OAI21XLTS U4056 ( .A0(n4581), .A1(n5456), .B0(n4673), .Y(operation_ready) );
MX2X1TS U4057 ( .A(Data_2[5]), .B(FPMULT_Op_MY[5]), .S0(n2350), .Y(n1631) );
MX2X1TS U4058 ( .A(Data_2[12]), .B(n5650), .S0(n2350), .Y(n1638) );
MX2X1TS U4059 ( .A(Data_2[22]), .B(n2383), .S0(n2350), .Y(n1648) );
MX2X1TS U4060 ( .A(Data_2[21]), .B(n2228), .S0(n2350), .Y(n1647) );
MX2X1TS U4061 ( .A(Data_1[11]), .B(n2403), .S0(n5934), .Y(n1669) );
MX2X1TS U4062 ( .A(Data_1[22]), .B(FPMULT_Op_MX[22]), .S0(n5639), .Y(n1680)
);
MX2X1TS U4063 ( .A(Data_2[10]), .B(n2201), .S0(n2350), .Y(n1636) );
MX2X1TS U4064 ( .A(Data_2[2]), .B(FPMULT_Op_MY[2]), .S0(n2349), .Y(n1628) );
MX2X1TS U4065 ( .A(Data_2[16]), .B(FPMULT_Op_MY[16]), .S0(n2369), .Y(n1642)
);
MX2X1TS U4066 ( .A(Data_2[18]), .B(n6749), .S0(n2349), .Y(n1644) );
MX2X1TS U4067 ( .A(Data_1[21]), .B(FPMULT_Op_MX[21]), .S0(n5639), .Y(n1679)
);
MX2X1TS U4068 ( .A(Data_1[8]), .B(FPMULT_Op_MX[8]), .S0(n5639), .Y(n1666) );
MX2X1TS U4069 ( .A(Data_1[12]), .B(FPMULT_Op_MX[12]), .S0(n2350), .Y(n1670)
);
MX2X1TS U4070 ( .A(Data_1[17]), .B(FPMULT_Op_MX[17]), .S0(n5934), .Y(n1675)
);
MX2X1TS U4071 ( .A(Data_2[9]), .B(n5643), .S0(n2350), .Y(n1635) );
MX2X1TS U4072 ( .A(Data_2[11]), .B(n5642), .S0(n5645), .Y(n1637) );
AOI21X1TS U4073 ( .A0(n3771), .A1(n3767), .B0(n3766), .Y(n3768) );
NAND2X1TS U4074 ( .A(n3770), .B(n3767), .Y(n3769) );
NOR2X1TS U4075 ( .A(n3763), .B(n3765), .Y(n3767) );
AO21XLTS U4076 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n7059), .B0(n6016),
.Y(n1314) );
MX2X1TS U4077 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n5641), .Y(n1650)
);
MX2X1TS U4078 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n5641), .Y(n1651)
);
MX2X1TS U4079 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n6606), .Y(n1653)
);
MX2X1TS U4080 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n5933), .Y(n1589) );
MX2X1TS U4081 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n5933), .Y(n1594) );
MX2X1TS U4082 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n5934), .Y(n1652)
);
MX2X1TS U4083 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n2349), .Y(n1687)
);
MX2X1TS U4084 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n5641), .Y(n1684)
);
NOR3BXLTS U4085 ( .AN(begin_operation), .B(n6342), .C(n6341), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
MX2X1TS U4086 ( .A(FPMULT_P_Sgf[4]), .B(FPMULT_Sgf_operation_Result[4]),
.S0(n2284), .Y(n1533) );
MX2X1TS U4087 ( .A(FPMULT_P_Sgf[12]), .B(n6273), .S0(n6958), .Y(n1541) );
MX2X1TS U4088 ( .A(FPMULT_P_Sgf[16]), .B(n6258), .S0(n6957), .Y(n1545) );
MX2X1TS U4089 ( .A(FPMULT_P_Sgf[5]), .B(n6259), .S0(n6956), .Y(n1534) );
MX2X1TS U4090 ( .A(FPMULT_P_Sgf[10]), .B(n6262), .S0(n6956), .Y(n1539) );
MX2X1TS U4091 ( .A(FPMULT_P_Sgf[3]), .B(FPMULT_Sgf_operation_Result[3]),
.S0(n6958), .Y(n1532) );
MX2X1TS U4092 ( .A(FPMULT_P_Sgf[14]), .B(n6268), .S0(n6957), .Y(n1543) );
XOR2XLTS U4093 ( .A(n6213), .B(n6212), .Y(n6220) );
AOI222X1TS U4094 ( .A0(n4984), .A1(cordic_result[22]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[22]), .C0(n4985), .C1(FPSENCOS_d_ff_Yn[22]), .Y(n5166) );
AOI222X1TS U4095 ( .A0(n5167), .A1(cordic_result[15]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[15]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[15]), .Y(n5130) );
AOI222X1TS U4096 ( .A0(n5167), .A1(cordic_result[18]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[18]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[18]), .Y(n5134) );
AOI222X1TS U4097 ( .A0(n4984), .A1(cordic_result[21]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[21]), .C0(n4985), .C1(FPSENCOS_d_ff_Yn[21]), .Y(n5170) );
AOI222X1TS U4098 ( .A0(n5141), .A1(cordic_result[4]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[4]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[4]), .Y(n5131)
);
AOI222X1TS U4099 ( .A0(n5141), .A1(cordic_result[6]), .B0(n5140), .B1(
FPSENCOS_d_ff_Xn[6]), .C0(n5139), .C1(FPSENCOS_d_ff_Yn[6]), .Y(n5135)
);
MX2X1TS U4100 ( .A(n6943), .B(n6942), .S0(n6941), .Y(n1575) );
MX2X1TS U4101 ( .A(FPMULT_P_Sgf[17]), .B(n6245), .S0(n6958), .Y(n1546) );
MX2X1TS U4102 ( .A(FPMULT_P_Sgf[15]), .B(n6249), .S0(n6957), .Y(n1544) );
MX2X1TS U4103 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n5641), .Y(n1655)
);
NAND2BXLTS U4104 ( .AN(n6352), .B(n6351), .Y(n2191) );
MX2X1TS U4105 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n5934), .Y(n1682)
);
MX2X1TS U4106 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n6606), .Y(n1683)
);
MX2X1TS U4107 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n2369), .Y(n1685)
);
CLKAND2X2TS U4108 ( .A(n4461), .B(n4460), .Y(n2427) );
XOR2XLTS U4109 ( .A(n4514), .B(n4513), .Y(n4516) );
MX2X1TS U4110 ( .A(Data_2[8]), .B(n5644), .S0(n2350), .Y(n1634) );
MX2X1TS U4111 ( .A(FPMULT_FSM_add_overflow_flag), .B(n5932), .S0(n5931), .Y(
n1596) );
AOI222X1TS U4112 ( .A0(n5167), .A1(cordic_result[16]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[16]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[16]), .Y(n5138) );
AOI222X1TS U4113 ( .A0(n5167), .A1(cordic_result[13]), .B0(n5137), .B1(
FPSENCOS_d_ff_Xn[13]), .C0(n5136), .C1(FPSENCOS_d_ff_Yn[13]), .Y(n5132) );
MX2X1TS U4114 ( .A(FPMULT_P_Sgf[13]), .B(n6241), .S0(n2284), .Y(n1542) );
MX2X1TS U4115 ( .A(FPMULT_P_Sgf[9]), .B(n6261), .S0(n6957), .Y(n1538) );
MX2X1TS U4116 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_Sgf_operation_Result[1]),
.S0(n6958), .Y(n1530) );
MX2X1TS U4117 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n6713), .Y(n1443) );
MX2X1TS U4118 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1433) );
MX2X1TS U4119 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n2340), .Y(n1423) );
MX2X1TS U4120 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1438) );
MX2X1TS U4121 ( .A(FPMULT_P_Sgf[19]), .B(n6298), .S0(n6290), .Y(n1548) );
MX2X1TS U4122 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n6713), .Y(n1418) );
OAI21XLTS U4123 ( .A0(n5265), .A1(n2356), .B0(n2336), .Y(n2078) );
MX2X1TS U4124 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n5934), .Y(n1649)
);
MX2X1TS U4125 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n5933), .Y(n1593) );
MX2X1TS U4126 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n5933), .Y(n1592) );
MX2X1TS U4127 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n5933), .Y(n1591) );
MX2X1TS U4128 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n5933), .Y(n1590) );
MX2X1TS U4129 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n6606), .Y(n1654)
);
MX2X1TS U4130 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n5934), .Y(n1681)
);
MX2X1TS U4131 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n5641), .Y(n1656)
);
MX2X1TS U4132 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_OP_FLAG_SHT2), .S0(
n6014), .Y(n1352) );
MX2X1TS U4133 ( .A(FPMULT_P_Sgf[24]), .B(n5922), .S0(n6957), .Y(n1553) );
XOR2XLTS U4134 ( .A(n4519), .B(n4506), .Y(n4510) );
MX2X1TS U4135 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n5934), .Y(n1688)
);
MX2X1TS U4136 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n5641), .Y(n1686)
);
CLKMX2X2TS U4137 ( .A(FPMULT_P_Sgf[33]), .B(n4449), .S0(n6956), .Y(n1562) );
MX2X1TS U4138 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1448) );
MX2X1TS U4139 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1428) );
AO21XLTS U4140 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n6353), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(n2148) );
AO21XLTS U4141 ( .A0(n2299), .A1(n6344), .B0(n6343), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
XOR2XLTS U4142 ( .A(n6083), .B(n6082), .Y(n6088) );
XOR2XLTS U4143 ( .A(n6229), .B(n6228), .Y(n6236) );
CLKAND2X2TS U4144 ( .A(n6335), .B(n6355), .Y(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
AOI32X1TS U4145 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n5265), .A2(
n7059), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n5379), .Y(n4819)
);
MX2X1TS U4146 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DMP_SHT2_EWSW[22]),
.S0(n6624), .Y(n1206) );
MX2X1TS U4147 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DMP_SHT2_EWSW[16]),
.S0(n5962), .Y(n1246) );
MX2X1TS U4148 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DMP_SHT2_EWSW[14]),
.S0(n6014), .Y(n1258) );
MX2X1TS U4149 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DMP_SHT2_EWSW[20]),
.S0(n5937), .Y(n1226) );
MX2X1TS U4150 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DMP_SHT2_EWSW[18]),
.S0(n6009), .Y(n1214) );
MX2X1TS U4151 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DMP_SHT2_EWSW[13]),
.S0(n6624), .Y(n1242) );
MX2X1TS U4152 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DMP_SHT2_EWSW[17]),
.S0(n6624), .Y(n1230) );
MX2X1TS U4153 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DMP_SHT2_EWSW[19]),
.S0(n6710), .Y(n1222) );
MX2X1TS U4154 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DMP_SHT2_EWSW[21]),
.S0(n6014), .Y(n1218) );
MX2X1TS U4155 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DMP_SHT2_EWSW[15]),
.S0(n6624), .Y(n1210) );
MX2X1TS U4156 ( .A(FPADDSUB_Raw_mant_NRM_SWR[0]), .B(
FPADDSUB_DmP_mant_SFG_SWR[0]), .S0(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(
n1349) );
MX2X1TS U4157 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DMP_SHT2_EWSW[12]),
.S0(n6624), .Y(n1266) );
MX2X1TS U4158 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DMP_SHT2_EWSW[11]),
.S0(n6624), .Y(n1254) );
MX2X1TS U4159 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DMP_SHT2_EWSW[10]),
.S0(n6624), .Y(n1262) );
XOR2XLTS U4160 ( .A(n6185), .B(n6184), .Y(n6194) );
MX2X1TS U4161 ( .A(Data_1[16]), .B(FPMULT_Op_MX[16]), .S0(n5641), .Y(n1674)
);
MX2X1TS U4162 ( .A(Data_1[6]), .B(FPMULT_Op_MX[6]), .S0(n5934), .Y(n1664) );
MX2X1TS U4163 ( .A(Data_2[17]), .B(n5648), .S0(n2349), .Y(n1643) );
MX2X1TS U4164 ( .A(Data_1[3]), .B(FPMULT_Op_MX[3]), .S0(n6606), .Y(n1661) );
MX2X1TS U4165 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n5641), .Y(n1678)
);
MX2X1TS U4166 ( .A(Data_1[15]), .B(FPMULT_Op_MX[15]), .S0(n6606), .Y(n1673)
);
MX2X1TS U4167 ( .A(Data_1[4]), .B(FPMULT_Op_MX[4]), .S0(n5641), .Y(n1662) );
MX2X1TS U4168 ( .A(Data_1[18]), .B(n5640), .S0(n6606), .Y(n1676) );
MX2X1TS U4169 ( .A(FPMULT_Add_result[12]), .B(n5879), .S0(n5899), .Y(n1608)
);
XOR2XLTS U4170 ( .A(n5500), .B(n5499), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
XOR2X1TS U4171 ( .A(n3787), .B(n3786), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7) );
NAND2X1TS U4172 ( .A(n3785), .B(n3784), .Y(n3786) );
XOR2X1TS U4173 ( .A(n3598), .B(n3597), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8) );
NAND2X1TS U4174 ( .A(n3596), .B(n3595), .Y(n3598) );
INVX2TS U4175 ( .A(n3594), .Y(n3596) );
MX2X1TS U4176 ( .A(Data_1[0]), .B(FPMULT_Op_MX[0]), .S0(n5934), .Y(n1658) );
XOR2XLTS U4177 ( .A(n6093), .B(n6092), .Y(n6098) );
XOR2XLTS U4178 ( .A(n6045), .B(n6044), .Y(n6050) );
MX2X1TS U4179 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DMP_SHT2_EWSW[0]), .S0(
n6014), .Y(n1293) );
MX2X1TS U4180 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DMP_SHT2_EWSW[1]), .S0(
n6014), .Y(n1286) );
MX2X1TS U4181 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DMP_SHT2_EWSW[2]), .S0(
n6014), .Y(n1307) );
MX2X1TS U4182 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DMP_SHT2_EWSW[3]), .S0(
n6014), .Y(n1323) );
MX2X1TS U4183 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DMP_SHT2_EWSW[4]), .S0(
n6014), .Y(n1234) );
MX2X1TS U4184 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DMP_SHT2_EWSW[5]), .S0(
n6014), .Y(n1272) );
MX2X1TS U4185 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DMP_SHT2_EWSW[6]), .S0(
n5937), .Y(n1238) );
MX2X1TS U4186 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DMP_SHT2_EWSW[7]), .S0(
n5937), .Y(n1300) );
MX2X1TS U4187 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DMP_SHT2_EWSW[8]), .S0(
n5937), .Y(n1250) );
MX2X1TS U4188 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DMP_SHT2_EWSW[9]), .S0(
n5937), .Y(n1279) );
AO21X1TS U4189 ( .A0(result_add_subt[7]), .A1(n6354), .B0(n4276), .Y(n1306)
);
AO21X1TS U4190 ( .A0(result_add_subt[6]), .A1(n6354), .B0(n4282), .Y(n1384)
);
MX2X1TS U4191 ( .A(FPMULT_Add_result[20]), .B(n5861), .S0(n5873), .Y(n1600)
);
XOR2XLTS U4192 ( .A(n6128), .B(n6127), .Y(n6133) );
MX2X1TS U4193 ( .A(FPMULT_Add_result[19]), .B(n5863), .S0(n5873), .Y(n1601)
);
XOR2XLTS U4194 ( .A(n6118), .B(n6117), .Y(n6123) );
MX2X1TS U4195 ( .A(FPMULT_Add_result[18]), .B(n5865), .S0(n5873), .Y(n1602)
);
MX2X1TS U4196 ( .A(FPMULT_Add_result[17]), .B(n5867), .S0(n5873), .Y(n1603)
);
MX2X1TS U4197 ( .A(FPMULT_Add_result[16]), .B(n5869), .S0(n5873), .Y(n1604)
);
MX2X1TS U4198 ( .A(FPMULT_Add_result[15]), .B(n5871), .S0(n5873), .Y(n1605)
);
MX2X1TS U4199 ( .A(FPMULT_Add_result[7]), .B(n5893), .S0(n5899), .Y(n1613)
);
OAI31X1TS U4200 ( .A0(n6360), .A1(FPSENCOS_cont_var_out[1]), .A2(n6756),
.B0(n4553), .Y(n2136) );
MX2X1TS U4201 ( .A(FPMULT_Add_result[14]), .B(n5874), .S0(n5931), .Y(n1606)
);
MX2X1TS U4202 ( .A(FPMULT_Add_result[6]), .B(n5895), .S0(n5931), .Y(n1614)
);
MX2X1TS U4203 ( .A(FPMULT_Add_result[13]), .B(n5877), .S0(n5931), .Y(n1607)
);
MX2X1TS U4204 ( .A(FPMULT_Add_result[10]), .B(n5885), .S0(n5899), .Y(n1610)
);
MX2X1TS U4205 ( .A(FPMULT_Add_result[9]), .B(n5887), .S0(n5931), .Y(n1611)
);
MX2X1TS U4206 ( .A(FPMULT_Add_result[5]), .B(n5897), .S0(n5899), .Y(n1615)
);
MX2X1TS U4207 ( .A(FPMULT_Add_result[8]), .B(n5889), .S0(n5899), .Y(n1612)
);
MX2X1TS U4208 ( .A(FPMULT_Add_result[11]), .B(n5881), .S0(n5899), .Y(n1609)
);
MX2X1TS U4209 ( .A(FPMULT_Add_result[4]), .B(n5900), .S0(n5899), .Y(n1616)
);
MX2X1TS U4210 ( .A(FPMULT_Add_result[3]), .B(n5907), .S0(n5899), .Y(n1617)
);
INVX2TS U4211 ( .A(n5915), .Y(n5905) );
MX2X1TS U4212 ( .A(FPMULT_Add_result[1]), .B(n5923), .S0(n5899), .Y(n1619)
);
MX2X1TS U4213 ( .A(FPMULT_Add_result[2]), .B(n5916), .S0(n5931), .Y(n1618)
);
OR2X1TS U4214 ( .A(n5758), .B(n5777), .Y(intadd_513_B_1_) );
OAI21XLTS U4215 ( .A0(n6765), .A1(n6794), .B0(n5757), .Y(n5473) );
CLKAND2X2TS U4216 ( .A(n5679), .B(n5678), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
OAI21XLTS U4217 ( .A0(n2478), .A1(n5677), .B0(n5676), .Y(n5678) );
NAND2X1TS U4218 ( .A(n3981), .B(n3980), .Y(n3982) );
NAND4XLTS U4219 ( .A(n7071), .B(n7070), .C(n7069), .D(n6331), .Y(n6333) );
NAND3XLTS U4220 ( .A(n2299), .B(n6373), .C(n6372), .Y(n6359) );
INVX2TS U4221 ( .A(n4209), .Y(n3348) );
NAND2X1TS U4222 ( .A(n4176), .B(n4175), .Y(n4177) );
AOI21X1TS U4223 ( .A0(n4181), .A1(n4174), .B0(n4173), .Y(n4178) );
XOR2X1TS U4224 ( .A(n4194), .B(n4193), .Y(FPMULT_Sgf_operation_Result[32])
);
NAND2X1TS U4225 ( .A(n4192), .B(n4191), .Y(n4193) );
AOI21X1TS U4226 ( .A0(n4457), .A1(n4331), .B0(n4189), .Y(n4194) );
XOR2X1TS U4227 ( .A(n3411), .B(n3410), .Y(FPMULT_Sgf_operation_Result[39])
);
AOI21X1TS U4228 ( .A0(n2375), .A1(n3409), .B0(n3408), .Y(n3411) );
AOI21X1TS U4229 ( .A0(n4181), .A1(n3425), .B0(n3424), .Y(n3426) );
AOI21X1TS U4230 ( .A0(n2375), .A1(n3429), .B0(n3337), .Y(n3430) );
NAND2X1TS U4231 ( .A(n4184), .B(n4183), .Y(n4185) );
AOI21X1TS U4232 ( .A0(n2375), .A1(n4335), .B0(n4180), .Y(n4186) );
XOR2X1TS U4233 ( .A(n3405), .B(DP_OP_499J223_125_1651_n296), .Y(
FPMULT_Sgf_operation_Result[41]) );
XOR2XLTS U4234 ( .A(n5516), .B(n5515), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
CLKAND2X2TS U4235 ( .A(n5467), .B(n5466), .Y(n6827) );
XNOR2X1TS U4236 ( .A(n3978), .B(n3977), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13) );
NAND2X1TS U4237 ( .A(n2474), .B(n3976), .Y(n3977) );
NAND2X1TS U4238 ( .A(n3975), .B(n2473), .Y(n3976) );
XNOR2X1TS U4239 ( .A(n3986), .B(n3985), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11) );
NAND2X1TS U4240 ( .A(n2475), .B(n3984), .Y(n3985) );
NAND2X1TS U4241 ( .A(n2476), .B(n3990), .Y(n3991) );
AOI21X1TS U4242 ( .A0(n4003), .A1(n3989), .B0(n3988), .Y(n3992) );
XOR2X1TS U4243 ( .A(n3999), .B(n3998), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9) );
NAND2X1TS U4244 ( .A(n3997), .B(n3996), .Y(n3998) );
AOI21X1TS U4245 ( .A0(n4003), .A1(n4001), .B0(n3994), .Y(n3999) );
INVX2TS U4246 ( .A(n3995), .Y(n3997) );
XNOR2X1TS U4247 ( .A(n4003), .B(n4002), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8) );
NAND2X1TS U4248 ( .A(n4001), .B(n4000), .Y(n4002) );
XNOR2X1TS U4249 ( .A(n4009), .B(n4008), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7) );
INVX2TS U4250 ( .A(n4005), .Y(n4007) );
OAI22X1TS U4251 ( .A0(n3883), .A1(DP_OP_501J223_127_5235_n723), .B0(n3901),
.B1(n3882), .Y(n4017) );
CLKAND2X2TS U4252 ( .A(n2489), .B(n4029), .Y(n2490) );
OAI21XLTS U4253 ( .A0(n2484), .A1(n2469), .B0(n5735), .Y(n5474) );
OAI21XLTS U4254 ( .A0(n7062), .A1(n2482), .B0(n5838), .Y(n5475) );
XNOR2X1TS U4255 ( .A(n3762), .B(n3761), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10) );
NAND2X1TS U4256 ( .A(n3760), .B(n3764), .Y(n3761) );
NAND2X1TS U4257 ( .A(n3775), .B(n3774), .Y(n3776) );
INVX2TS U4258 ( .A(n3770), .Y(n3773) );
XNOR2X1TS U4259 ( .A(n3782), .B(n3781), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8) );
NAND2X1TS U4260 ( .A(n3780), .B(n3779), .Y(n3781) );
INVX2TS U4261 ( .A(n3778), .Y(n3780) );
XNOR2X1TS U4262 ( .A(n3793), .B(n3792), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6) );
NAND2X1TS U4263 ( .A(n3791), .B(n3790), .Y(n3792) );
INVX2TS U4264 ( .A(n3789), .Y(n3791) );
XOR2X1TS U4265 ( .A(n3798), .B(n3797), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5) );
INVX2TS U4266 ( .A(n3794), .Y(n3796) );
XOR2X1TS U4267 ( .A(n3803), .B(n3802), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4) );
NAND2X1TS U4268 ( .A(n3801), .B(n3800), .Y(n3803) );
XNOR2X1TS U4269 ( .A(n3805), .B(n2426), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3) );
NAND2X1TS U4270 ( .A(n2494), .B(n3804), .Y(n3805) );
XNOR2X1TS U4271 ( .A(n3808), .B(n3807), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2) );
NAND2X1TS U4272 ( .A(n2500), .B(n3806), .Y(n3808) );
XOR2X1TS U4273 ( .A(n3812), .B(n3856), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1) );
NAND2X1TS U4274 ( .A(n3811), .B(n3810), .Y(n3812) );
INVX2TS U4275 ( .A(n3809), .Y(n3811) );
CLKAND2X2TS U4276 ( .A(n2492), .B(n3856), .Y(n2493) );
INVX2TS U4277 ( .A(n3565), .Y(n3567) );
NAND2X1TS U4278 ( .A(n3575), .B(n3574), .Y(n3576) );
INVX2TS U4279 ( .A(n3570), .Y(n3573) );
NAND2X1TS U4280 ( .A(n3580), .B(n3579), .Y(n3581) );
INVX2TS U4281 ( .A(n3578), .Y(n3580) );
NAND2X1TS U4282 ( .A(n3585), .B(n3584), .Y(n3586) );
INVX2TS U4283 ( .A(n3583), .Y(n3585) );
XNOR2X1TS U4284 ( .A(n3593), .B(n3592), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9) );
NAND2X1TS U4285 ( .A(n3591), .B(n3590), .Y(n3592) );
INVX2TS U4286 ( .A(n3589), .Y(n3591) );
XOR2X1TS U4287 ( .A(n3603), .B(n3602), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7) );
NAND2X1TS U4288 ( .A(n3601), .B(n3600), .Y(n3603) );
INVX2TS U4289 ( .A(n3599), .Y(n3601) );
XNOR2X1TS U4290 ( .A(n3606), .B(n3605), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6) );
XOR2X1TS U4291 ( .A(n3611), .B(n3610), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5) );
NAND2X1TS U4292 ( .A(n3609), .B(n3608), .Y(n3611) );
INVX2TS U4293 ( .A(n3607), .Y(n3609) );
XNOR2X1TS U4294 ( .A(n3614), .B(n3613), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4) );
NAND2X1TS U4295 ( .A(n2499), .B(n3612), .Y(n3614) );
XOR2X1TS U4296 ( .A(n3619), .B(n3618), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3) );
NAND2X1TS U4297 ( .A(n3617), .B(n3616), .Y(n3619) );
XNOR2X1TS U4298 ( .A(n3622), .B(n3621), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2) );
NAND2X1TS U4299 ( .A(n2495), .B(n3620), .Y(n3622) );
CLKAND2X2TS U4300 ( .A(n2496), .B(n3859), .Y(n2497) );
OAI21XLTS U4301 ( .A0(n5573), .A1(n5200), .B0(n5199), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
CLKAND2X2TS U4302 ( .A(n5471), .B(n5470), .Y(n6828) );
AO21XLTS U4303 ( .A0(n4474), .A1(n5672), .B0(n4937), .Y(intadd_515_B_1_) );
AO22XLTS U4304 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1207) );
AO22XLTS U4305 ( .A0(n6744), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n6743),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1208) );
AO22XLTS U4306 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1211) );
AO22XLTS U4307 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n6738),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1212) );
AO22XLTS U4308 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n6740),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1215) );
AO22XLTS U4309 ( .A0(n6739), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1216) );
AO22XLTS U4310 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1219) );
AO22XLTS U4311 ( .A0(n6739), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1220) );
AO22XLTS U4312 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1223) );
AO22XLTS U4313 ( .A0(n6739), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1224) );
AO22XLTS U4314 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n6740),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1227) );
AO22XLTS U4315 ( .A0(n6739), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1228) );
AO22XLTS U4316 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1231) );
AO22XLTS U4317 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1232) );
AO22XLTS U4318 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(
FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n6733), .Y(n6907) );
AO22XLTS U4319 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n6736), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1236) );
AO22XLTS U4320 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(
FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n6733), .Y(n6908) );
AO22XLTS U4321 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n6736), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1240) );
AO22XLTS U4322 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1243) );
AO22XLTS U4323 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1244) );
AO22XLTS U4324 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1247) );
AO22XLTS U4325 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1248) );
AO22XLTS U4326 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1251) );
AO22XLTS U4327 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n6736), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1252) );
AO22XLTS U4328 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1255) );
AO22XLTS U4329 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1256) );
AO22XLTS U4330 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1259) );
AO22XLTS U4331 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1260) );
AO22XLTS U4332 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n6733),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1263) );
AO22XLTS U4333 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n6736),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1264) );
AO22XLTS U4334 ( .A0(n6737), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n6733),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1267) );
AO22XLTS U4335 ( .A0(n6742), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n6732),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1268) );
AO22XLTS U4336 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(
FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n6733), .Y(n6909) );
AO22XLTS U4337 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1274) );
AO22XLTS U4338 ( .A0(n6734), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n6732), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1276) );
AO22XLTS U4339 ( .A0(n7077), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n6915),
.B1(FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1280) );
AO22XLTS U4340 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1281) );
AO22XLTS U4341 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(
FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n6740), .Y(n6910) );
AO22XLTS U4342 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1288) );
AO22XLTS U4343 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(
FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n6740), .Y(n6911) );
AO22XLTS U4344 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1295) );
AO22XLTS U4345 ( .A0(n6734), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n6732), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1297) );
AO22XLTS U4346 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n6733), .Y(n6912) );
AO22XLTS U4347 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1302) );
AO22XLTS U4348 ( .A0(n6734), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n6732), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1304) );
AO22XLTS U4349 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n6740), .Y(n6913) );
AO22XLTS U4350 ( .A0(n6734), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n6732), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1309) );
AO22XLTS U4351 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n6743), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1311) );
AO22XLTS U4352 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n6740), .Y(n6914) );
AO22XLTS U4353 ( .A0(n6744), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n6743), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1325) );
AO22XLTS U4354 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n6743), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1327) );
AO22XLTS U4355 ( .A0(n7077), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n6735), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1353) );
AO22XLTS U4356 ( .A0(n6744), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n6743), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1354) );
AO22XLTS U4357 ( .A0(n6713), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n2341), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n1357) );
AO22XLTS U4358 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_SIGN_FLAG_SFG), .B0(n6711), .B1(FPADDSUB_SIGN_FLAG_NRM), .Y(
n1358) );
AO22XLTS U4359 ( .A0(n7077), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n6735), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1360) );
AO22XLTS U4360 ( .A0(n6744), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n6743), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1361) );
AO22XLTS U4361 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n6743),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1364) );
AO22XLTS U4362 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n6743),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1367) );
AO22XLTS U4363 ( .A0(n6744), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n6743), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1373) );
AO22XLTS U4364 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1376) );
AO22XLTS U4365 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1379) );
AO22XLTS U4366 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n6656), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1382) );
AO22XLTS U4367 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n6656), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1385) );
AO22XLTS U4368 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[17]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1388) );
AO22XLTS U4369 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1394) );
AO22XLTS U4370 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n6656),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1397) );
AO22XLTS U4371 ( .A0(n6657), .A1(FPADDSUB_DmP_EXP_EWSW[18]), .B0(n6741),
.B1(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1400) );
AO22XLTS U4372 ( .A0(n6741), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(n6635),
.B1(FPADDSUB_DmP_EXP_EWSW[15]), .Y(n1403) );
AO22XLTS U4373 ( .A0(n6635), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n6738),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1406) );
AO22XLTS U4374 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[30]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[7]),
.Y(n1419) );
AO22XLTS U4375 ( .A0(n7077), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1421) );
AO22XLTS U4376 ( .A0(n6657), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n6741),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1422) );
AO22XLTS U4377 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[29]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[6]),
.Y(n1424) );
AO22XLTS U4378 ( .A0(n7077), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1426) );
AO22XLTS U4379 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1427) );
AO22XLTS U4380 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[28]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[5]),
.Y(n1429) );
AO22XLTS U4381 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1431) );
AO22XLTS U4382 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1432) );
AO22XLTS U4383 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[27]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[4]),
.Y(n1434) );
AO22XLTS U4384 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1436) );
AO22XLTS U4385 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1437) );
AO22XLTS U4386 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[26]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[3]),
.Y(n1439) );
AO22XLTS U4387 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n6735),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1441) );
AO22XLTS U4388 ( .A0(n6657), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1442) );
AO22XLTS U4389 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[25]), .B0(n2316), .B1(FPADDSUB_DMP_exp_NRM_EW[2]),
.Y(n1444) );
AO22XLTS U4390 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n6740),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1446) );
AO22XLTS U4391 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1447) );
AO22XLTS U4392 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n6740),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1451) );
AO22XLTS U4393 ( .A0(n6635), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n6625),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1452) );
AO22XLTS U4394 ( .A0(n6623), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n6733),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1456) );
AO22XLTS U4395 ( .A0(n6635), .A1(n6620), .B0(n6625), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1475) );
OAI21XLTS U4396 ( .A0(n6848), .A1(n6763), .B0(intadd_516_CI), .Y(n6620) );
AO22XLTS U4397 ( .A0(n6635), .A1(intadd_516_SUM_1_), .B0(n6625), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1477) );
AO22XLTS U4398 ( .A0(n6739), .A1(intadd_516_SUM_2_), .B0(n6736), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1478) );
NOR2XLTS U4399 ( .A(n4588), .B(FPMULT_Sgf_normalized_result[23]), .Y(n4586)
);
MX2X1TS U4400 ( .A(FPMULT_P_Sgf[0]), .B(FPMULT_Sgf_operation_Result[0]),
.S0(n2284), .Y(n1529) );
MX2X1TS U4401 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_Sgf_operation_Result[2]),
.S0(n2284), .Y(n1531) );
MX2X1TS U4402 ( .A(FPMULT_P_Sgf[6]), .B(n6275), .S0(n6956), .Y(n1535) );
MX2X1TS U4403 ( .A(FPMULT_P_Sgf[7]), .B(n6276), .S0(n6957), .Y(n1536) );
MX2X1TS U4404 ( .A(FPMULT_P_Sgf[8]), .B(n6274), .S0(n2284), .Y(n1537) );
MX2X1TS U4405 ( .A(FPMULT_P_Sgf[11]), .B(n6277), .S0(n6958), .Y(n1540) );
MX2X1TS U4406 ( .A(Data_2[1]), .B(n2220), .S0(n2349), .Y(n1627) );
MX2X1TS U4407 ( .A(Data_2[3]), .B(FPMULT_Op_MY[3]), .S0(n2349), .Y(n1629) );
MX2X1TS U4408 ( .A(Data_2[4]), .B(n5646), .S0(n2369), .Y(n1630) );
MX2X1TS U4409 ( .A(Data_2[6]), .B(DP_OP_501J223_127_5235_n903), .S0(n2350),
.Y(n1632) );
MX2X1TS U4410 ( .A(Data_2[7]), .B(n6764), .S0(n2369), .Y(n1633) );
MX2X1TS U4411 ( .A(Data_2[13]), .B(n5649), .S0(n2369), .Y(n1639) );
MX2X1TS U4412 ( .A(Data_2[14]), .B(FPMULT_Op_MY[14]), .S0(n2349), .Y(n1640)
);
MX2X1TS U4413 ( .A(Data_2[15]), .B(FPMULT_Op_MY[15]), .S0(n2349), .Y(n1641)
);
MX2X1TS U4414 ( .A(Data_2[19]), .B(n6753), .S0(n2349), .Y(n1645) );
MX2X1TS U4415 ( .A(Data_2[20]), .B(n5647), .S0(n5645), .Y(n1646) );
AO22XLTS U4416 ( .A0(n5637), .A1(Data_1[31]), .B0(n6606), .B1(
FPMULT_Op_MX[31]), .Y(n1657) );
MX2X1TS U4417 ( .A(Data_1[1]), .B(n2481), .S0(n5639), .Y(n1659) );
MX2X1TS U4418 ( .A(Data_1[2]), .B(FPMULT_Op_MX[2]), .S0(n5639), .Y(n1660) );
MX2X1TS U4419 ( .A(Data_1[5]), .B(n5638), .S0(n5639), .Y(n1663) );
MX2X1TS U4420 ( .A(Data_1[7]), .B(FPMULT_Op_MX[7]), .S0(n5639), .Y(n1665) );
MX2X1TS U4421 ( .A(Data_1[9]), .B(DP_OP_501J223_127_5235_n944), .S0(n5639),
.Y(n1667) );
MX2X1TS U4422 ( .A(Data_1[10]), .B(n6750), .S0(n5639), .Y(n1668) );
MX2X1TS U4423 ( .A(Data_1[13]), .B(FPMULT_Op_MX[13]), .S0(n2369), .Y(n1671)
);
MX2X1TS U4424 ( .A(Data_1[14]), .B(FPMULT_Op_MX[14]), .S0(n2350), .Y(n1672)
);
MX2X1TS U4425 ( .A(Data_1[19]), .B(FPMULT_Op_MX[19]), .S0(n6606), .Y(n1677)
);
AO22XLTS U4426 ( .A0(n5637), .A1(Data_2[31]), .B0(n6606), .B1(
FPMULT_Op_MY[31]), .Y(n1624) );
OAI21XLTS U4427 ( .A0(n5265), .A1(n4578), .B0(n5450), .Y(n2079) );
OAI21XLTS U4428 ( .A0(n6455), .A1(n6783), .B0(intadd_518_CI), .Y(n4556) );
NOR2XLTS U4429 ( .A(n6371), .B(intadd_517_B_1_), .Y(n4555) );
OAI21XLTS U4430 ( .A0(n6455), .A1(n6369), .B0(n6368), .Y(n6370) );
OAI31X1TS U4431 ( .A0(n6364), .A1(n6768), .A2(n6367), .B0(n6363), .Y(n6365)
);
NOR2X4TS U4432 ( .A(DP_OP_499J223_125_1651_n215), .B(
DP_OP_499J223_125_1651_n213), .Y(n2789) );
NAND2X4TS U4433 ( .A(DP_OP_499J223_125_1651_n204), .B(
DP_OP_499J223_125_1651_n206), .Y(n3103) );
NOR2X6TS U4434 ( .A(n2607), .B(n2606), .Y(n2659) );
BUFX4TS U4435 ( .A(n3935), .Y(n2389) );
NOR2X4TS U4436 ( .A(n3589), .B(n3594), .Y(n3504) );
OAI22X2TS U4437 ( .A0(n2386), .A1(n3694), .B0(n2385), .B1(n3693), .Y(n3668)
);
OAI21X2TS U4438 ( .A0(n2928), .A1(n2927), .B0(n2926), .Y(n2929) );
NAND2X4TS U4439 ( .A(n2837), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n2926)
);
NAND2X4TS U4440 ( .A(n3058), .B(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(
n3283) );
NAND2X4TS U4441 ( .A(DP_OP_501J223_127_5235_n130), .B(
DP_OP_501J223_127_5235_n135), .Y(n3584) );
INVX2TS U4442 ( .A(n4195), .Y(DP_OP_499J223_125_1651_n266) );
ADDFHX2TS U4443 ( .A(n3120), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]), .CI(
n3119), .CO(n3121), .S(n3086) );
CMPR42X2TS U4444 ( .A(DP_OP_501J223_127_5235_n251), .B(
DP_OP_501J223_127_5235_n161), .C(DP_OP_501J223_127_5235_n160), .D(
DP_OP_501J223_127_5235_n165), .ICI(DP_OP_501J223_127_5235_n157), .S(
DP_OP_501J223_127_5235_n154), .ICO(DP_OP_501J223_127_5235_n152), .CO(
DP_OP_501J223_127_5235_n153) );
OAI21X1TS U4445 ( .A0(n3527), .A1(n3526), .B0(n3525), .Y(n3532) );
XNOR2X4TS U4446 ( .A(n3487), .B(n3486), .Y(n2253) );
INVX4TS U4447 ( .A(n2221), .Y(n6568) );
AND3X2TS U4448 ( .A(n4588), .B(n6260), .C(FPMULT_FSM_selector_C), .Y(n2227)
);
OR2X1TS U4449 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_P_Sgf[6]), .Y(n2229) );
INVX2TS U4450 ( .A(n5617), .Y(n2309) );
XOR2X1TS U4451 ( .A(n3713), .B(n3712), .Y(n2242) );
INVX2TS U4452 ( .A(n2486), .Y(n2324) );
OR2X4TS U4453 ( .A(n3640), .B(n3639), .Y(n2486) );
OR2X2TS U4454 ( .A(FPMULT_Op_MX[15]), .B(n6569), .Y(n2245) );
CLKXOR2X2TS U4455 ( .A(n3380), .B(n3362), .Y(n3363) );
CLKXOR2X2TS U4456 ( .A(n4563), .B(n4441), .Y(n2250) );
OR2X2TS U4457 ( .A(n6593), .B(n2286), .Y(n2251) );
OR2X2TS U4458 ( .A(n5386), .B(n5392), .Y(n2252) );
OAI21X1TS U4459 ( .A0(n4307), .A1(n4306), .B0(n4303), .Y(n2254) );
NOR2BX2TS U4460 ( .AN(n4590), .B(n6260), .Y(n4589) );
INVX2TS U4461 ( .A(n5238), .Y(n5330) );
NAND2X1TS U4462 ( .A(n5951), .B(n2311), .Y(n5969) );
INVX2TS U4463 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n5951) );
NOR2X4TS U4464 ( .A(n5326), .B(n6806), .Y(n5387) );
XNOR2X4TS U4465 ( .A(n3340), .B(n3223), .Y(n2264) );
OR3X1TS U4466 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n6785), .C(n4274),
.Y(n2267) );
OR2X1TS U4467 ( .A(FPMULT_P_Sgf[7]), .B(FPMULT_P_Sgf[11]), .Y(n2268) );
XNOR2X2TS U4468 ( .A(n3483), .B(n3482), .Y(n3899) );
INVX2TS U4469 ( .A(n5478), .Y(n6290) );
INVX2TS U4470 ( .A(n5637), .Y(n5645) );
BUFX3TS U4471 ( .A(FPADDSUB_left_right_SHT2), .Y(n6005) );
OAI21X2TS U4472 ( .A0(n6306), .A1(n6303), .B0(n6307), .Y(n2983) );
OA21X1TS U4473 ( .A0(n5525), .A1(n5528), .B0(n5526), .Y(n5523) );
OAI21X2TS U4474 ( .A0(n5520), .A1(n5523), .B0(n5521), .Y(n5518) );
AOI21X4TS U4475 ( .A0(n2218), .A1(n3451), .B0(n3433), .Y(n3434) );
ADDFHX2TS U4476 ( .A(n3663), .B(n3662), .CI(n3661), .CO(
DP_OP_501J223_127_5235_n140), .S(DP_OP_501J223_127_5235_n141) );
OAI21X1TS U4477 ( .A0(n3587), .A1(n3561), .B0(n3560), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15) );
OAI21X2TS U4478 ( .A0(n3587), .A1(n3573), .B0(n3572), .Y(n3577) );
OAI21X2TS U4479 ( .A0(n3587), .A1(n3551), .B0(n3550), .Y(n3555) );
OAI21X2TS U4480 ( .A0(n3587), .A1(n3564), .B0(n3563), .Y(n3569) );
INVX2TS U4481 ( .A(n2477), .Y(n2283) );
NAND2X1TS U4482 ( .A(n6584), .B(n2283), .Y(n3366) );
NOR2X2TS U4483 ( .A(n6584), .B(n2220), .Y(n3365) );
INVX2TS U4484 ( .A(n2259), .Y(n2287) );
INVX2TS U4485 ( .A(n2225), .Y(n5643) );
INVX2TS U4486 ( .A(n2198), .Y(n2289) );
INVX2TS U4487 ( .A(n2199), .Y(n2290) );
INVX4TS U4488 ( .A(n2255), .Y(n2292) );
INVX2TS U4489 ( .A(n2242), .Y(n2293) );
INVX2TS U4490 ( .A(n2242), .Y(n2294) );
INVX2TS U4491 ( .A(n2202), .Y(n2295) );
INVX2TS U4492 ( .A(n4484), .Y(n2297) );
INVX2TS U4493 ( .A(n2297), .Y(n2298) );
INVX2TS U4494 ( .A(n2297), .Y(n2299) );
INVX2TS U4495 ( .A(n6455), .Y(n2300) );
INVX2TS U4496 ( .A(n6415), .Y(n4748) );
INVX2TS U4497 ( .A(n2301), .Y(n2302) );
INVX2TS U4498 ( .A(n2241), .Y(n2303) );
INVX2TS U4499 ( .A(n2241), .Y(n2304) );
INVX2TS U4500 ( .A(n2254), .Y(n2305) );
INVX2TS U4501 ( .A(n2254), .Y(n2306) );
INVX2TS U4502 ( .A(n2243), .Y(n2307) );
INVX4TS U4503 ( .A(n2309), .Y(n2310) );
INVX2TS U4504 ( .A(n2262), .Y(n2311) );
INVX2TS U4505 ( .A(n2262), .Y(n2312) );
INVX2TS U4506 ( .A(n2250), .Y(n2321) );
INVX2TS U4507 ( .A(n2224), .Y(n2323) );
INVX2TS U4508 ( .A(n2219), .Y(n5642) );
INVX2TS U4509 ( .A(n2267), .Y(n2327) );
INVX2TS U4510 ( .A(n2267), .Y(n2328) );
INVX2TS U4511 ( .A(n5974), .Y(n2329) );
INVX2TS U4512 ( .A(n5974), .Y(n2330) );
OAI22X2TS U4513 ( .A0(n3707), .A1(n3696), .B0(n3708), .B1(n3695), .Y(n3661)
);
NOR2X1TS U4514 ( .A(n2335), .B(n3692), .Y(DP_OP_501J223_127_5235_n200) );
OAI22X1TS U4515 ( .A0(n3707), .A1(n3702), .B0(n2335), .B1(n3701), .Y(
DP_OP_501J223_127_5235_n244) );
XOR2X4TS U4516 ( .A(n3657), .B(n3656), .Y(n3658) );
INVX2TS U4517 ( .A(n5969), .Y(n2342) );
INVX2TS U4518 ( .A(n5969), .Y(n2343) );
INVX2TS U4519 ( .A(n2405), .Y(n2344) );
INVX2TS U4520 ( .A(n6767), .Y(n2345) );
INVX2TS U4521 ( .A(n6767), .Y(n2346) );
INVX2TS U4522 ( .A(n2347), .Y(n2348) );
INVX2TS U4523 ( .A(n5237), .Y(n2351) );
INVX2TS U4524 ( .A(n5237), .Y(n2352) );
INVX2TS U4525 ( .A(n2356), .Y(n2357) );
INVX2TS U4526 ( .A(n5387), .Y(n2358) );
INVX2TS U4527 ( .A(n2358), .Y(n2359) );
INVX2TS U4528 ( .A(n2358), .Y(n2360) );
INVX2TS U4529 ( .A(n2227), .Y(n2361) );
INVX2TS U4530 ( .A(n2227), .Y(n2362) );
INVX2TS U4531 ( .A(n2227), .Y(n2363) );
AOI32X1TS U4532 ( .A0(FPSENCOS_d_ff3_sign_out), .A1(n6547), .A2(
FPSENCOS_cont_var_out[0]), .B0(n6546), .B1(n6547), .Y(n1731) );
NOR3XLTS U4533 ( .A(n5648), .B(FPMULT_Op_MY[24]), .C(FPMULT_Op_MY[23]), .Y(
n6596) );
AOI21X2TS U4534 ( .A0(n5330), .A1(n6821), .B0(n5242), .Y(n5361) );
AOI21X2TS U4535 ( .A0(n5387), .A1(n6791), .B0(n5341), .Y(n5378) );
AOI21X2TS U4536 ( .A0(n5325), .A1(n6799), .B0(n5270), .Y(n5367) );
AOI21X2TS U4537 ( .A0(n5330), .A1(n6800), .B0(n5255), .Y(n5350) );
AOI211X1TS U4538 ( .A0(n2545), .A1(n2544), .B0(n2543), .C0(n2542), .Y(n2546)
);
INVX2TS U4539 ( .A(n3373), .Y(n5540) );
ADDHX1TS U4540 ( .A(n3881), .B(n3880), .CO(n3875), .S(n3884) );
MXI2X2TS U4541 ( .A(Data_2[0]), .B(DP_OP_501J223_127_5235_n897), .S0(n2369),
.Y(n6923) );
INVX2TS U4542 ( .A(n5637), .Y(n2369) );
NOR2X2TS U4543 ( .A(n5748), .B(n5747), .Y(n5754) );
INVX2TS U4544 ( .A(rst), .Y(n2365) );
CLKBUFX2TS U4545 ( .A(n7019), .Y(n7012) );
NAND3X2TS U4546 ( .A(n4485), .B(n6757), .C(n6787), .Y(n4489) );
CMPR42X1TS U4547 ( .A(DP_OP_500J223_126_4510_n174), .B(
DP_OP_500J223_126_4510_n138), .C(DP_OP_500J223_126_4510_n141), .D(
DP_OP_500J223_126_4510_n181), .ICI(DP_OP_500J223_126_4510_n188), .S(
DP_OP_500J223_126_4510_n136), .ICO(DP_OP_500J223_126_4510_n134), .CO(
DP_OP_500J223_126_4510_n135) );
ADDHX1TS U4548 ( .A(n4350), .B(n4349), .CO(DP_OP_500J223_126_4510_n137), .S(
DP_OP_500J223_126_4510_n138) );
OAI21X1TS U4549 ( .A0(n5770), .A1(n5769), .B0(n4895), .Y(mult_x_311_n22) );
OAI21X2TS U4550 ( .A0(n4888), .A1(n4887), .B0(n4913), .Y(n5769) );
AOI32X1TS U4551 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n5265), .A2(
n7059), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n5379), .Y(n4694)
);
AOI32X1TS U4552 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n5265), .A2(
n7059), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n5379), .Y(n4756)
);
ADDFHX2TS U4553 ( .A(n4239), .B(n4238), .CI(n4237), .CO(
DP_OP_499J223_125_1651_n250), .S(n2742) );
ADDHX1TS U4554 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .B(n4236), .CO(DP_OP_499J223_125_1651_n252), .S(n4239) );
AOI21X2TS U4555 ( .A0(n2312), .A1(FPADDSUB_Data_array_SWR[25]), .B0(n4480),
.Y(n4470) );
INVX2TS U4556 ( .A(n4581), .Y(n4666) );
OAI21X2TS U4557 ( .A0(n4901), .A1(n4900), .B0(n4899), .Y(n5766) );
INVX2TS U4558 ( .A(n6849), .Y(n2366) );
INVX2TS U4559 ( .A(n2276), .Y(n2367) );
CLKBUFX3TS U4560 ( .A(n7041), .Y(n7028) );
BUFX3TS U4561 ( .A(n7013), .Y(n7041) );
XNOR2X1TS U4562 ( .A(n3951), .B(n2308), .Y(n3909) );
XNOR2X1TS U4563 ( .A(n3937), .B(n2308), .Y(n3862) );
XNOR2X1TS U4564 ( .A(n3896), .B(n2308), .Y(n3888) );
XNOR2X1TS U4565 ( .A(n3914), .B(n2308), .Y(n3879) );
XNOR2X1TS U4566 ( .A(n3921), .B(n2308), .Y(n3869) );
XOR2X1TS U4567 ( .A(n3860), .B(n2307), .Y(n3861) );
AOI222X1TS U4568 ( .A0(n6562), .A1(cordic_result[30]), .B0(n5158), .B1(
FPSENCOS_d_ff_Xn[30]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[30]), .Y(n4986) );
CLKBUFX3TS U4569 ( .A(n4491), .Y(n4498) );
CLKBUFX3TS U4570 ( .A(n4491), .Y(n7010) );
CLKBUFX3TS U4571 ( .A(n4491), .Y(n4496) );
OAI2BB2XLTS U4572 ( .B0(n6393), .B1(n2451), .A0N(n6387), .A1N(
FPSENCOS_d_ff_Yn[30]), .Y(n1730) );
AOI222X1TS U4573 ( .A0(n4984), .A1(cordic_result[23]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[23]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[23]), .Y(n5160) );
AOI222X1TS U4574 ( .A0(n4984), .A1(cordic_result[25]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[25]), .C0(n4985), .C1(FPSENCOS_d_ff_Yn[25]), .Y(n5161) );
AOI222X1TS U4575 ( .A0(n4984), .A1(cordic_result[29]), .B0(n5169), .B1(
FPSENCOS_d_ff_Xn[29]), .C0(n5118), .C1(FPSENCOS_d_ff_Yn[29]), .Y(n5164) );
OR2X1TS U4576 ( .A(n6863), .B(FPADDSUB_DMP_SFG[9]), .Y(n4385) );
INVX2TS U4577 ( .A(FPADDSUB_intDX_EWSW[6]), .Y(n2525) );
NOR3XLTS U4578 ( .A(n6579), .B(FPMULT_Op_MX[24]), .C(FPMULT_Op_MX[23]), .Y(
n6580) );
INVX2TS U4579 ( .A(FPADDSUB_intDX_EWSW[16]), .Y(n2552) );
CLKMX2X2TS U4580 ( .A(FPMULT_P_Sgf[31]), .B(n4333), .S0(n6290), .Y(n1560) );
AOI21X2TS U4581 ( .A0(n2360), .A1(n6799), .B0(n5266), .Y(n5358) );
OAI22X1TS U4582 ( .A0(n3965), .A1(n3964), .B0(n3974), .B1(n3952), .Y(n3962)
);
OAI22X1TS U4583 ( .A0(n3974), .A1(n3915), .B0(n3964), .B1(n3922), .Y(n3923)
);
OAI22X1TS U4584 ( .A0(n3974), .A1(n3938), .B0(n3964), .B1(n3952), .Y(n3954)
);
OAI22X1TS U4585 ( .A0(n3974), .A1(DP_OP_501J223_127_5235_n630), .B0(n3964),
.B1(n3915), .Y(n3910) );
OAI22X1TS U4586 ( .A0(n3974), .A1(n3922), .B0(n3964), .B1(n3938), .Y(n3933)
);
NOR2BX1TS U4587 ( .AN(n3900), .B(n3964), .Y(n3872) );
NAND2X2TS U4588 ( .A(n3964), .B(n3867), .Y(n3974) );
AOI21X2TS U4589 ( .A0(n5387), .A1(n6800), .B0(n5269), .Y(n5366) );
INVX2TS U4590 ( .A(n3899), .Y(n2368) );
NOR2X2TS U4591 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n5915) );
OAI221X1TS U4592 ( .A0(FPADDSUB_intDX_EWSW[4]), .A1(n6761), .B0(n6813), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n6688), .Y(n6699) );
AOI221X1TS U4593 ( .A0(n2270), .A1(FPADDSUB_intDY_EWSW[8]), .B0(
FPADDSUB_intDY_EWSW[30]), .B1(n6810), .C0(n6687), .Y(n6688) );
AOI32X1TS U4594 ( .A0(n2466), .A1(n2508), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n2410), .Y(n2509) );
NOR4X2TS U4595 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n4993) );
OAI221X1TS U4596 ( .A0(n6812), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n2278),
.B1(FPADDSUB_intDY_EWSW[3]), .C0(n6685), .Y(n6701) );
NOR4BX4TS U4597 ( .AN(n4671), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .D(n6786), .Y(n6337) );
NOR2X1TS U4598 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n4552) );
OAI221X1TS U4599 ( .A0(n2464), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n6804),
.B1(FPADDSUB_intDY_EWSW[26]), .C0(n6671), .Y(n6674) );
AOI222X1TS U4600 ( .A0(n5291), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n6847),
.B1(n6668), .C0(FPADDSUB_intDX_EWSW[25]), .C1(n4321), .Y(n7075) );
OAI221X1TS U4601 ( .A0(n6805), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2434),
.B1(FPADDSUB_intDY_EWSW[1]), .C0(n6679), .Y(n6682) );
OAI221XLTS U4602 ( .A0(n2232), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n2272),
.B1(FPADDSUB_intDY_EWSW[18]), .C0(n6678), .Y(n6683) );
OAI221X1TS U4603 ( .A0(n2215), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n2279),
.B1(FPADDSUB_intDY_EWSW[15]), .C0(n6669), .Y(n6676) );
AOI222X1TS U4604 ( .A0(n5291), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n6848),
.B1(n6668), .C0(FPADDSUB_intDX_EWSW[23]), .C1(n4321), .Y(n7073) );
AOI211X2TS U4605 ( .A0(n2341), .A1(n6820), .B0(n6015), .C0(n2359), .Y(n5235)
);
OAI221XLTS U4606 ( .A0(n2231), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n2275),
.B1(FPADDSUB_intDY_EWSW[0]), .C0(n6672), .Y(n6673) );
AOI221X1TS U4607 ( .A0(n2233), .A1(FPADDSUB_intDY_EWSW[14]), .B0(
FPADDSUB_intDY_EWSW[20]), .B1(n2274), .C0(n6690), .Y(n6696) );
OAI221XLTS U4608 ( .A0(n2277), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2234),
.B1(FPADDSUB_intDY_EWSW[9]), .C0(n6680), .Y(n6681) );
AOI221X1TS U4609 ( .A0(n2273), .A1(FPADDSUB_intDY_EWSW[2]), .B0(
FPADDSUB_intDY_EWSW[5]), .B1(n6692), .C0(n6691), .Y(n6695) );
INVX2TS U4610 ( .A(n3717), .Y(n2370) );
NOR2X1TS U4611 ( .A(n3841), .B(n2403), .Y(n3835) );
OAI22X1TS U4612 ( .A0(n2294), .A1(n2346), .B0(n2370), .B1(n3840), .Y(
DP_OP_501J223_127_5235_n491) );
OAI22X1TS U4613 ( .A0(n2294), .A1(n3843), .B0(n3841), .B1(n3842), .Y(n3834)
);
NOR2X1TS U4614 ( .A(n3841), .B(n3843), .Y(n3837) );
OAI22X1TS U4615 ( .A0(n2294), .A1(n3845), .B0(n3841), .B1(n3844), .Y(n3836)
);
NOR2X1TS U4616 ( .A(n3841), .B(n3851), .Y(n3854) );
NOR2X1TS U4617 ( .A(n3841), .B(n3847), .Y(n3735) );
OAI22X1TS U4618 ( .A0(n2293), .A1(n3847), .B0(n3841), .B1(n3846), .Y(n3733)
);
INVX2TS U4619 ( .A(n3717), .Y(n3841) );
NAND2X1TS U4620 ( .A(n6595), .B(n5644), .Y(n3720) );
NOR2X2TS U4621 ( .A(n5647), .B(n5644), .Y(n3722) );
NOR2X2TS U4622 ( .A(n5644), .B(n2286), .Y(n4431) );
NAND2X1TS U4623 ( .A(n5643), .B(n6587), .Y(n4432) );
INVX4TS U4624 ( .A(n2260), .Y(n6587) );
NAND2X1TS U4625 ( .A(n6585), .B(n6594), .Y(n4292) );
NOR2X2TS U4626 ( .A(n6585), .B(n6594), .Y(n4291) );
INVX2TS U4627 ( .A(n3746), .Y(n2371) );
NOR2X1TS U4628 ( .A(n3852), .B(n3842), .Y(n3757) );
NOR2X1TS U4629 ( .A(n3852), .B(n3844), .Y(DP_OP_501J223_127_5235_n500) );
NOR2X1TS U4630 ( .A(n3852), .B(n3846), .Y(n3824) );
NOR2X1TS U4631 ( .A(n3852), .B(n3849), .Y(n3830) );
OAI21X2TS U4632 ( .A0(n3816), .A1(n2402), .B0(n3745), .Y(n3746) );
INVX2TS U4633 ( .A(n3746), .Y(n3852) );
INVX2TS U4634 ( .A(n3727), .Y(n2372) );
OAI22X1TS U4635 ( .A0(n2296), .A1(n2345), .B0(n2372), .B1(n3840), .Y(n3822)
);
OAI22X1TS U4636 ( .A0(n2296), .A1(n3847), .B0(n2372), .B1(n3846), .Y(
DP_OP_501J223_127_5235_n510) );
OAI22X1TS U4637 ( .A0(n3850), .A1(n3845), .B0(n2294), .B1(n3844), .Y(n3833)
);
OAI22X1TS U4638 ( .A0(n2296), .A1(n3845), .B0(n2372), .B1(n3844), .Y(
DP_OP_501J223_127_5235_n503) );
OAI22X1TS U4639 ( .A0(n2295), .A1(n3843), .B0(n3850), .B1(n3842), .Y(n3828)
);
OAI22X1TS U4640 ( .A0(n3850), .A1(n2345), .B0(n2294), .B1(n3840), .Y(n3829)
);
OAI22X1TS U4641 ( .A0(n2295), .A1(n3851), .B0(n3850), .B1(n3849), .Y(
DP_OP_501J223_127_5235_n517) );
OAI22X1TS U4642 ( .A0(n3850), .A1(n3847), .B0(n2293), .B1(n3846), .Y(
DP_OP_501J223_127_5235_n511) );
INVX2TS U4643 ( .A(n3727), .Y(n3850) );
INVX2TS U4644 ( .A(n3751), .Y(n2373) );
OAI22X1TS U4645 ( .A0(n2373), .A1(n2346), .B0(n2296), .B1(n3840), .Y(
DP_OP_501J223_127_5235_n488) );
OAI22X1TS U4646 ( .A0(n2373), .A1(n3842), .B0(n3852), .B1(n3843), .Y(
DP_OP_501J223_127_5235_n494) );
OAI22X1TS U4647 ( .A0(n3848), .A1(n3843), .B0(n2296), .B1(n3842), .Y(
DP_OP_501J223_127_5235_n495) );
OAI22X1TS U4648 ( .A0(n3848), .A1(n3851), .B0(n2296), .B1(n3849), .Y(n3831)
);
OAI22X1TS U4649 ( .A0(n3848), .A1(n3846), .B0(n3852), .B1(n3847), .Y(
DP_OP_501J223_127_5235_n508) );
OAI22X1TS U4650 ( .A0(n3848), .A1(n3849), .B0(n3852), .B1(n3851), .Y(
DP_OP_501J223_127_5235_n515) );
OAI22X2TS U4651 ( .A0(n3848), .A1(n3845), .B0(n2296), .B1(n3844), .Y(n3827)
);
XNOR2X2TS U4652 ( .A(n3750), .B(FPMULT_Op_MY[11]), .Y(n3751) );
INVX2TS U4653 ( .A(n3751), .Y(n3848) );
INVX2TS U4654 ( .A(n6629), .Y(n6728) );
INVX2TS U4655 ( .A(n4347), .Y(n2376) );
INVX2TS U4656 ( .A(n4347), .Y(n5614) );
INVX2TS U4657 ( .A(n3369), .Y(n5542) );
CLKXOR2X2TS U4658 ( .A(n3368), .B(n3371), .Y(n3369) );
CLKBUFX2TS U4659 ( .A(n5621), .Y(n2378) );
OAI21X1TS U4660 ( .A0(n4301), .A1(n4297), .B0(n4298), .Y(n4295) );
CLKBUFX2TS U4661 ( .A(n5548), .Y(n2379) );
NAND2X1TS U4662 ( .A(n3381), .B(n4432), .Y(n3382) );
CLKBUFX2TS U4663 ( .A(n5619), .Y(n2380) );
OAI21X1TS U4664 ( .A0(n4563), .A1(n4562), .B0(n4561), .Y(n4568) );
NOR2X2TS U4665 ( .A(n3279), .B(FPMULT_FS_Module_state_reg[1]), .Y(
FPMULT_FSM_exp_operation_A_S) );
INVX2TS U4666 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n5935) );
NAND2X1TS U4667 ( .A(n2383), .B(n6588), .Y(n3818) );
NOR2X2TS U4668 ( .A(n2383), .B(n6588), .Y(n3817) );
ADDFX2TS U4669 ( .A(n6588), .B(n6586), .CI(n3513), .CO(n3520), .S(n3457) );
NAND2X1TS U4670 ( .A(n6586), .B(n2290), .Y(n4305) );
INVX2TS U4671 ( .A(n2238), .Y(n6586) );
BUFX3TS U4672 ( .A(n3679), .Y(n2384) );
NOR2X1TS U4673 ( .A(n2384), .B(n3704), .Y(n3857) );
OAI22X1TS U4674 ( .A0(n2332), .A1(n3704), .B0(n2384), .B1(n3705), .Y(n3624)
);
NOR2X1TS U4675 ( .A(n3679), .B(n3702), .Y(n3495) );
OAI22X2TS U4676 ( .A0(n3693), .A1(n2384), .B0(n3694), .B1(n2332), .Y(n3673)
);
NOR2X1TS U4677 ( .A(n3679), .B(n3692), .Y(n3674) );
NOR2X1TS U4678 ( .A(n3679), .B(n3700), .Y(n3691) );
OAI22X1TS U4679 ( .A0(n2331), .A1(n3702), .B0(n3679), .B1(n3701), .Y(n3690)
);
NOR2X2TS U4680 ( .A(n3694), .B(n2384), .Y(n3675) );
NOR2X1TS U4681 ( .A(n3679), .B(n3698), .Y(n3686) );
OAI22X1TS U4682 ( .A0(n2331), .A1(n3700), .B0(n3679), .B1(n3699), .Y(n3685)
);
OAI22X2TS U4683 ( .A0(n2331), .A1(n3696), .B0(n3679), .B1(n3695), .Y(n3676)
);
OAI22X1TS U4684 ( .A0(n2385), .A1(n3704), .B0(n2332), .B1(n3705), .Y(n3496)
);
OAI22X1TS U4685 ( .A0(n2385), .A1(n3694), .B0(n3693), .B1(n2332), .Y(
DP_OP_501J223_127_5235_n211) );
OAI22X1TS U4686 ( .A0(n3703), .A1(n3702), .B0(n2332), .B1(n3701), .Y(
DP_OP_501J223_127_5235_n247) );
OAI22X2TS U4687 ( .A0(n2386), .A1(n3704), .B0(n2385), .B1(n3705), .Y(n3499)
);
OAI22X1TS U4688 ( .A0(n3709), .A1(n3698), .B0(n3703), .B1(n3697), .Y(
DP_OP_501J223_127_5235_n228) );
OAI22X1TS U4689 ( .A0(n3709), .A1(n3695), .B0(n2335), .B1(n3696), .Y(n3667)
);
OAI22X1TS U4690 ( .A0(n2386), .A1(n3697), .B0(n2335), .B1(n3698), .Y(
DP_OP_501J223_127_5235_n227) );
OAI22X1TS U4691 ( .A0(n2386), .A1(n3705), .B0(n2335), .B1(n3704), .Y(
DP_OP_501J223_127_5235_n254) );
OAI22X1TS U4692 ( .A0(n3709), .A1(n3699), .B0(n3708), .B1(n3700), .Y(
DP_OP_501J223_127_5235_n236) );
OAI22X1TS U4693 ( .A0(n3709), .A1(n3701), .B0(n2335), .B1(n3702), .Y(
DP_OP_501J223_127_5235_n245) );
OAI22X1TS U4694 ( .A0(n2386), .A1(n3702), .B0(n3703), .B1(n3701), .Y(
DP_OP_501J223_127_5235_n246) );
OAI22X1TS U4695 ( .A0(n2386), .A1(n3700), .B0(n2385), .B1(n3699), .Y(
DP_OP_501J223_127_5235_n237) );
OAI22X1TS U4696 ( .A0(n2387), .A1(n3693), .B0(n2325), .B1(n3694), .Y(
DP_OP_501J223_127_5235_n206) );
NOR2X1TS U4697 ( .A(n2387), .B(n3692), .Y(DP_OP_501J223_127_5235_n198) );
OAI22X1TS U4698 ( .A0(n2387), .A1(n3697), .B0(n2325), .B1(n3698), .Y(
DP_OP_501J223_127_5235_n224) );
OAI22X1TS U4699 ( .A0(n2387), .A1(n3694), .B0(n2334), .B1(n3693), .Y(
DP_OP_501J223_127_5235_n207) );
OAI22X1TS U4700 ( .A0(n2387), .A1(n3695), .B0(n2325), .B1(n3696), .Y(n3650)
);
OAI22X1TS U4701 ( .A0(n2387), .A1(n3705), .B0(n2486), .B1(n3704), .Y(
DP_OP_501J223_127_5235_n251) );
OAI22X1TS U4702 ( .A0(n2387), .A1(n3704), .B0(n2334), .B1(n3705), .Y(
DP_OP_501J223_127_5235_n252) );
OAI22X1TS U4703 ( .A0(n3706), .A1(n3701), .B0(n2486), .B1(n3702), .Y(
DP_OP_501J223_127_5235_n242) );
INVX2TS U4704 ( .A(n3641), .Y(n3706) );
BUFX3TS U4705 ( .A(n4995), .Y(n2388) );
AOI31XLTS U4706 ( .A0(n6323), .A1(n6322), .A2(n6321), .B0(dataB[27]), .Y(
n6334) );
CLKBUFX3TS U4707 ( .A(n4490), .Y(n4497) );
CLKBUFX3TS U4708 ( .A(n4490), .Y(n4487) );
CLKBUFX3TS U4709 ( .A(n4490), .Y(n4492) );
CLKBUFX3TS U4710 ( .A(n4490), .Y(n4486) );
NOR2X4TS U4711 ( .A(n2299), .B(rst), .Y(n4490) );
CLKXOR2X2TS U4712 ( .A(n5815), .B(n5814), .Y(n5832) );
CLKXOR2X2TS U4713 ( .A(n5710), .B(n5709), .Y(n5729) );
NOR4X1TS U4714 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n6920) );
NOR4X1TS U4715 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n6921) );
NOR2XLTS U4716 ( .A(n2229), .B(n2268), .Y(n4541) );
NOR2X2TS U4717 ( .A(n5699), .B(n4824), .Y(n5711) );
NOR2X2TS U4718 ( .A(n5804), .B(n4762), .Y(n5817) );
NOR2X2TS U4719 ( .A(FPSENCOS_d_ff2_X[29]), .B(n6436), .Y(n6435) );
OAI33X4TS U4720 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[1]), .A1(
FPSENCOS_d_ff1_operation_out), .A2(n6558), .B0(n2266), .B1(n6825),
.B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n6559) );
NOR4X1TS U4721 ( .A(FPMULT_P_Sgf[20]), .B(FPMULT_P_Sgf[21]), .C(
FPMULT_P_Sgf[18]), .D(FPMULT_P_Sgf[19]), .Y(n4548) );
NOR2X2TS U4722 ( .A(n6794), .B(n2225), .Y(n5750) );
NOR2X2TS U4723 ( .A(n2482), .B(n2477), .Y(n5841) );
NOR2X2TS U4724 ( .A(n2469), .B(n2483), .Y(n5738) );
AOI21X2TS U4725 ( .A0(n4476), .A1(n4475), .B0(n4956), .Y(n5652) );
AOI22X2TS U4726 ( .A0(n4884), .A1(n4883), .B0(n4882), .B1(n5748), .Y(n5770)
);
AOI22X2TS U4727 ( .A0(n5442), .A1(n5441), .B0(n5440), .B1(n7067), .Y(n5660)
);
OAI211XLTS U4728 ( .A0(n4554), .A1(n6903), .B0(n4823), .C0(n4980), .Y(n2120)
);
AOI21X2TS U4729 ( .A0(n6375), .A1(n6372), .B0(n5013), .Y(n4823) );
OAI21XLTS U4730 ( .A0(n5774), .A1(n5773), .B0(n5775), .Y(n4878) );
AOI21X2TS U4731 ( .A0(n4892), .A1(n4868), .B0(n4897), .Y(n5773) );
AOI21X2TS U4732 ( .A0(n6364), .A1(intadd_517_B_1_), .B0(n6367), .Y(n6366) );
NOR2X4TS U4733 ( .A(n6455), .B(FPSENCOS_cont_iter_out[3]), .Y(n6364) );
AOI22X2TS U4734 ( .A0(n5690), .A1(n5689), .B0(n5688), .B1(n5687), .Y(n5721)
);
OAI21X2TS U4735 ( .A0(FPMULT_Op_MX[18]), .A1(n2291), .B0(n5439), .Y(n5667)
);
OAI21X2TS U4736 ( .A0(n4923), .A1(n4922), .B0(n4921), .Y(n5763) );
OAI21X2TS U4737 ( .A0(n4792), .A1(n4791), .B0(n4790), .Y(n5827) );
OAI21X2TS U4738 ( .A0(n4854), .A1(n4853), .B0(n4852), .Y(n5724) );
OAI21X2TS U4739 ( .A0(n4767), .A1(n4766), .B0(n4786), .Y(n5835) );
NOR2X1TS U4740 ( .A(n4784), .B(n4765), .Y(n4767) );
NAND2X1TS U4741 ( .A(n4767), .B(n4766), .Y(n4786) );
OAI21X2TS U4742 ( .A0(n4829), .A1(n4828), .B0(n4848), .Y(n5732) );
NOR2X1TS U4743 ( .A(n4846), .B(n4827), .Y(n4829) );
NAND2X1TS U4744 ( .A(n4829), .B(n4828), .Y(n4848) );
AOI22X2TS U4745 ( .A0(n5795), .A1(n5794), .B0(n5793), .B1(n5792), .Y(n5824)
);
AOI22X2TS U4746 ( .A0(n5762), .A1(n4910), .B0(n4909), .B1(n4908), .Y(n5765)
);
OAI22X2TS U4747 ( .A0(n4960), .A1(n4959), .B0(n4958), .B1(n4957), .Y(n5663)
);
NOR2X1TS U4748 ( .A(n4950), .B(n4949), .Y(n4960) );
NOR2X4TS U4749 ( .A(n6768), .B(n2300), .Y(n6373) );
NAND2BX4TS U4750 ( .AN(n6003), .B(n6627), .Y(n5963) );
INVX4TS U4751 ( .A(n6624), .Y(n6003) );
NOR2X2TS U4752 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n6199) );
NOR2X2TS U4753 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n6181) );
NOR2X2TS U4754 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4534) );
NOR2X1TS U4755 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n4811), .Y(n4755) );
NOR2XLTS U4756 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n5631) );
AOI21X2TS U4757 ( .A0(n2312), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n4480),
.Y(n6008) );
CLKMX2X2TS U4758 ( .A(FPMULT_P_Sgf[35]), .B(n4338), .S0(n6957), .Y(n1564) );
CLKMX2X2TS U4759 ( .A(FPMULT_P_Sgf[30]), .B(n4329), .S0(n6290), .Y(n1559) );
AOI22X2TS U4760 ( .A0(n5325), .A1(n6791), .B0(n5243), .B1(n5238), .Y(n5362)
);
OAI211XLTS U4761 ( .A0(n2400), .A1(n2363), .B0(n4623), .C0(n4622), .Y(n1526)
);
NOR3X1TS U4762 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n6617), .Y(n6609) );
OAI21XLTS U4763 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n2433), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n2519) );
NOR2X2TS U4764 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_517_n1), .Y(n6461) );
NOR2X2TS U4765 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n6463), .Y(n6466) );
NAND2X1TS U4766 ( .A(FPMULT_Sgf_normalized_result[5]), .B(
FPMULT_Sgf_normalized_result[4]), .Y(n5891) );
OA22X1TS U4767 ( .A0(n2409), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n2438), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n2515) );
NOR2X2TS U4768 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n5218) );
NOR4X1TS U4769 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(
FPADDSUB_Raw_mant_NRM_SWR[1]), .C(FPADDSUB_Raw_mant_NRM_SWR[0]), .D(
n5230), .Y(n4691) );
NOR2X1TS U4770 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(n4814), .Y(n5231) );
NOR2X1TS U4771 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n5217), .Y(n5210) );
OAI21X2TS U4772 ( .A0(n2336), .A1(FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(n5234),
.Y(n5349) );
NOR2BX2TS U4773 ( .AN(n4993), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n4671) );
NAND2X1TS U4774 ( .A(FPMULT_Sgf_normalized_result[6]), .B(
FPMULT_Sgf_normalized_result[7]), .Y(n5851) );
INVX2TS U4775 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4274) );
CLKBUFX2TS U4776 ( .A(n3935), .Y(n2390) );
OAI22X1TS U4777 ( .A0(n3909), .A1(n3936), .B0(n3920), .B1(n2390), .Y(n3927)
);
OAI22X1TS U4778 ( .A0(n3909), .A1(n2390), .B0(n3936), .B1(n3862), .Y(n3918)
);
AO21X1TS U4779 ( .A0(n3936), .A1(n2390), .B0(n2243), .Y(n3955) );
OAI22X2TS U4780 ( .A0(n3936), .A1(n3920), .B0(n2390), .B1(n2243), .Y(n3956)
);
OAI22X1TS U4781 ( .A0(n3936), .A1(n3869), .B0(n2390), .B1(n3862), .Y(n3873)
);
OAI22X1TS U4782 ( .A0(n3936), .A1(n3879), .B0(n3869), .B1(n2389), .Y(n3881)
);
OAI22X1TS U4783 ( .A0(n3936), .A1(n3888), .B0(n3879), .B1(n2389), .Y(n3890)
);
OAI22X1TS U4784 ( .A0(n3936), .A1(n3889), .B0(n2389), .B1(n3888), .Y(n3894)
);
NOR2BX1TS U4785 ( .AN(n3900), .B(n2389), .Y(n4026) );
NAND2X4TS U4786 ( .A(n3861), .B(n2389), .Y(n3936) );
XNOR2X1TS U4787 ( .A(n3860), .B(n2205), .Y(n3935) );
BUFX3TS U4788 ( .A(n7013), .Y(n2391) );
BUFX3TS U4789 ( .A(n7014), .Y(n2392) );
BUFX3TS U4790 ( .A(n7011), .Y(n2393) );
NOR2X2TS U4791 ( .A(FPMULT_FSM_selector_C), .B(n4648), .Y(n4590) );
OAI22X1TS U4792 ( .A0(n3932), .A1(n2394), .B0(n3968), .B1(n3919), .Y(n3930)
);
OAI22X1TS U4793 ( .A0(n3932), .A1(n3968), .B0(n3953), .B1(n2394), .Y(n3950)
);
OAI22X1TS U4794 ( .A0(n3968), .A1(n3878), .B0(n3877), .B1(n3967), .Y(n3886)
);
OAI22X1TS U4795 ( .A0(n3968), .A1(n3966), .B0(n3870), .B1(n3967), .Y(n3880)
);
NOR2BX1TS U4796 ( .AN(n3900), .B(n3967), .Y(n3892) );
INVX2TS U4797 ( .A(n2395), .Y(n3966) );
XNOR2X1TS U4798 ( .A(n2395), .B(n3900), .Y(n3878) );
XOR2X1TS U4799 ( .A(n2395), .B(n3863), .Y(n3864) );
ADDHX1TS U4800 ( .A(n3659), .B(n3931), .CO(n3539), .S(n3660) );
OA22X1TS U4801 ( .A0(n2398), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n2461), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n2545) );
OR2X1TS U4802 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n4413) );
OR2X1TS U4803 ( .A(n6808), .B(FPADDSUB_DMP_SFG[16]), .Y(n4401) );
OR2X1TS U4804 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n6062) );
OR2X1TS U4805 ( .A(n6809), .B(FPADDSUB_DMP_SFG[14]), .Y(n4397) );
OR2X1TS U4806 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n6153) );
OR2X1TS U4807 ( .A(n6824), .B(FPADDSUB_DMP_SFG[20]), .Y(n4409) );
OR2X1TS U4808 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n6136) );
OR2X1TS U4809 ( .A(n6818), .B(FPADDSUB_DMP_SFG[18]), .Y(n4405) );
OAI211XLTS U4810 ( .A0(n2397), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n2521), .C0(
n2520), .Y(n2524) );
OAI21XLTS U4811 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n2397), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n2522) );
OAI32X4TS U4812 ( .A0(n5387), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .A2(n2336),
.B0(n5386), .B1(n2360), .Y(n6522) );
AOI21X2TS U4813 ( .A0(n2312), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n4480),
.Y(n6001) );
OR2X1TS U4814 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n6071) );
NAND2X1TS U4815 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n6070) );
OR2X1TS U4816 ( .A(n6862), .B(FPADDSUB_DMP_SFG[12]), .Y(n4393) );
NAND2X1TS U4817 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n6042) );
AOI21X2TS U4818 ( .A0(n2312), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n4480),
.Y(n5996) );
AOI211X4TS U4819 ( .A0(n5944), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n5948),
.C0(n4479), .Y(n5989) );
NAND3X1TS U4820 ( .A(n4274), .B(n5951), .C(FPADDSUB_shift_value_SHT2_EWR[3]),
.Y(n5966) );
CLKBUFX2TS U4821 ( .A(n3853), .Y(n2396) );
NOR2X1TS U4822 ( .A(n3852), .B(n2396), .Y(DP_OP_501J223_127_5235_n521) );
NOR2X1TS U4823 ( .A(n3841), .B(n2396), .Y(n3855) );
NOR2X1TS U4824 ( .A(n3706), .B(n2396), .Y(DP_OP_501J223_127_5235_n260) );
NOR2X1TS U4825 ( .A(n2486), .B(n2396), .Y(DP_OP_501J223_127_5235_n259) );
NOR2X1TS U4826 ( .A(n2295), .B(n3853), .Y(DP_OP_501J223_127_5235_n523) );
NOR2X1TS U4827 ( .A(n2384), .B(n3853), .Y(n3858) );
NOR2X1TS U4828 ( .A(n3707), .B(n3853), .Y(DP_OP_501J223_127_5235_n261) );
NOR2X1TS U4829 ( .A(n3709), .B(n3853), .Y(DP_OP_501J223_127_5235_n263) );
NOR2X1TS U4830 ( .A(n3850), .B(n3853), .Y(n3838) );
NOR2X1TS U4831 ( .A(n3703), .B(n3853), .Y(n3689) );
NOR2X1TS U4832 ( .A(n2331), .B(n3853), .Y(n3494) );
NOR2X1TS U4833 ( .A(n2293), .B(n3853), .Y(n3734) );
NOR3X1TS U4834 ( .A(n2568), .B(n2567), .C(FPADDSUB_intDY_EWSW[28]), .Y(n2569) );
OAI2BB2XLTS U4835 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n2505), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n2448), .Y(n2514) );
NOR3X2TS U4836 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n4690), .Y(n4753) );
NOR2XLTS U4837 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4692) );
INVX2TS U4838 ( .A(n7077), .Y(n6735) );
INVX2TS U4839 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n2866) );
NAND2X2TS U4840 ( .A(n2443), .B(n3431), .Y(DP_OP_501J223_127_5235_n630) );
INVX2TS U4841 ( .A(n3963), .Y(n3639) );
INVX2TS U4842 ( .A(DP_OP_501J223_127_5235_n723), .Y(n3865) );
NAND2X4TS U4843 ( .A(n2437), .B(n3467), .Y(DP_OP_501J223_127_5235_n723) );
AO21X1TS U4844 ( .A0(n2500), .A1(n3807), .B0(n3740), .Y(n2426) );
AND2X2TS U4845 ( .A(n3575), .B(n3559), .Y(n2429) );
OR2X1TS U4846 ( .A(n6568), .B(FPMULT_Op_MX[12]), .Y(n2437) );
OR2X1TS U4847 ( .A(FPMULT_Op_MY[12]), .B(DP_OP_501J223_127_5235_n897), .Y(
n2443) );
OR2X2TS U4848 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[5]), .Y(n2456) );
INVX2TS U4849 ( .A(n2458), .Y(n5638) );
OR2X1TS U4850 ( .A(n4225), .B(n2906), .Y(n2462) );
OR2X1TS U4851 ( .A(n3975), .B(n2473), .Y(n2474) );
INVX2TS U4852 ( .A(n2483), .Y(n5649) );
INVX2TS U4853 ( .A(n2484), .Y(n5650) );
OR2X2TS U4854 ( .A(n3035), .B(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(
n2485) );
INVX2TS U4855 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(n2780) );
OR2X1TS U4856 ( .A(n4028), .B(n4027), .Y(n2489) );
OR2X1TS U4857 ( .A(n3855), .B(n3854), .Y(n2492) );
OR2X1TS U4858 ( .A(n3858), .B(n3857), .Y(n2496) );
NAND2X2TS U4859 ( .A(DP_OP_499J223_125_1651_n222), .B(
DP_OP_499J223_125_1651_n224), .Y(n2498) );
OR2X1TS U4860 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2502) );
AND2X2TS U4861 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n3293), .Y(n2503) );
INVX2TS U4862 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n2816) );
NOR2X4TS U4863 ( .A(n2659), .B(n2662), .Y(n2665) );
NOR2X2TS U4864 ( .A(n4057), .B(n4056), .Y(n4066) );
INVX2TS U4865 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n3155) );
OR2X4TS U4866 ( .A(n2668), .B(n2667), .Y(n2669) );
INVX2TS U4867 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(n2682) );
INVX2TS U4868 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n3176) );
NAND2X1TS U4869 ( .A(n2833), .B(n2858), .Y(n2834) );
AOI21X1TS U4870 ( .A0(n4035), .A1(n6746), .B0(n4034), .Y(n4038) );
INVX2TS U4871 ( .A(n2695), .Y(n2681) );
NOR2X1TS U4872 ( .A(n6748), .B(FPADDSUB_intDX_EWSW[11]), .Y(n2533) );
NAND2X1TS U4873 ( .A(n2852), .B(n2857), .Y(n2853) );
INVX2TS U4874 ( .A(n6274), .Y(DP_OP_499J223_125_1651_n281) );
INVX2TS U4875 ( .A(n4207), .Y(DP_OP_499J223_125_1651_n300) );
NAND2X1TS U4876 ( .A(n3123), .B(n2200), .Y(n3124) );
NOR2X2TS U4877 ( .A(n5643), .B(n6587), .Y(n4434) );
OAI21X1TS U4878 ( .A0(n3816), .A1(n3815), .B0(n3814), .Y(n3821) );
NAND2X1TS U4879 ( .A(n3628), .B(n3627), .Y(n3629) );
INVX2TS U4880 ( .A(n2775), .Y(n2776) );
NAND2X1TS U4881 ( .A(n3194), .B(n3181), .Y(n3179) );
OA21XLTS U4882 ( .A0(n4564), .A1(n4561), .B0(n4565), .Y(n4438) );
NOR2X1TS U4883 ( .A(n4793), .B(n5845), .Y(n4784) );
NAND2X1TS U4884 ( .A(n3544), .B(n3543), .Y(n3545) );
OR2X1TS U4885 ( .A(n2705), .B(n2704), .Y(n2909) );
NAND2X1TS U4886 ( .A(n3137), .B(DP_OP_496J223_122_3236_n147), .Y(n3138) );
INVX2TS U4887 ( .A(n4250), .Y(n5536) );
NAND2X1TS U4888 ( .A(n3367), .B(n3366), .Y(n3368) );
OAI22X1TS U4889 ( .A0(n3850), .A1(n3843), .B0(n2294), .B1(n3842), .Y(
DP_OP_501J223_127_5235_n497) );
NOR2X1TS U4890 ( .A(n3841), .B(n3845), .Y(n3839) );
OAI22X1TS U4891 ( .A0(n2387), .A1(n3696), .B0(n2334), .B1(n3695), .Y(
DP_OP_501J223_127_5235_n216) );
OAI22X1TS U4892 ( .A0(n2387), .A1(n3702), .B0(n2334), .B1(n3701), .Y(
DP_OP_501J223_127_5235_n243) );
OAI22X1TS U4893 ( .A0(n2334), .A1(n3704), .B0(n2335), .B1(n3705), .Y(
DP_OP_501J223_127_5235_n253) );
INVX2TS U4894 ( .A(n3476), .Y(n3478) );
NOR2XLTS U4895 ( .A(n4534), .B(n4529), .Y(n4256) );
NAND2X1TS U4896 ( .A(n2962), .B(n2961), .Y(n2963) );
INVX2TS U4897 ( .A(n6101), .Y(n6103) );
INVX2TS U4898 ( .A(n3180), .Y(n3239) );
INVX2TS U4899 ( .A(n3308), .Y(n3256) );
OAI22X1TS U4900 ( .A0(n3848), .A1(n3847), .B0(n2295), .B1(n3846), .Y(
DP_OP_501J223_127_5235_n509) );
OAI22X1TS U4901 ( .A0(n2387), .A1(n3699), .B0(n2486), .B1(n3700), .Y(
DP_OP_501J223_127_5235_n233) );
NOR2X1TS U4902 ( .A(n3708), .B(n3853), .Y(DP_OP_501J223_127_5235_n262) );
CMPR42X1TS U4903 ( .A(DP_OP_500J223_126_4510_n151), .B(
DP_OP_500J223_126_4510_n158), .C(DP_OP_500J223_126_4510_n132), .D(
DP_OP_500J223_126_4510_n165), .ICI(DP_OP_500J223_126_4510_n130), .S(
DP_OP_500J223_126_4510_n126), .ICO(DP_OP_500J223_126_4510_n124), .CO(
DP_OP_500J223_126_4510_n125) );
INVX4TS U4904 ( .A(n4302), .Y(n5617) );
OR2X1TS U4905 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n6173) );
NOR2XLTS U4906 ( .A(n6861), .B(FPADDSUB_DMP_SFG[0]), .Y(n4369) );
CLKXOR2X4TS U4907 ( .A(n3114), .B(n3093), .Y(n4220) );
INVX4TS U4908 ( .A(n2480), .Y(n6570) );
NAND2X1TS U4909 ( .A(n5489), .B(n5494), .Y(n5152) );
INVX2TS U4910 ( .A(n3806), .Y(n3740) );
NAND2X1TS U4911 ( .A(n5567), .B(n2487), .Y(n5195) );
OAI21XLTS U4912 ( .A0(n4535), .A1(n4534), .B0(n4533), .Y(n4537) );
INVX2TS U4913 ( .A(n4210), .Y(n4198) );
OAI21XLTS U4914 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n5631), .B0(n5630), .Y(
n5632) );
AND2X2TS U4915 ( .A(n4687), .B(n4809), .Y(n5207) );
OR2X1TS U4916 ( .A(n5340), .B(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n5252) );
INVX2TS U4917 ( .A(n3979), .Y(n3981) );
OR2X1TS U4918 ( .A(n3389), .B(n3388), .Y(n5531) );
INVX2TS U4919 ( .A(n3783), .Y(n3785) );
INVX2TS U4920 ( .A(n3281), .Y(n4423) );
OR2X1TS U4921 ( .A(n5340), .B(FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n5246) );
BUFX3TS U4922 ( .A(n6549), .Y(n6510) );
OR2X1TS U4923 ( .A(n5465), .B(n5464), .Y(n5467) );
NAND2X1TS U4924 ( .A(n4007), .B(n4006), .Y(n4008) );
NAND2X1TS U4925 ( .A(n3796), .B(n3795), .Y(n3797) );
NAND2X1TS U4926 ( .A(n3567), .B(n3566), .Y(n3568) );
NAND2X1TS U4927 ( .A(n3501), .B(n3604), .Y(n3606) );
OAI21X1TS U4928 ( .A0(n5573), .A1(n5553), .B0(n5552), .Y(n5557) );
OR2X1TS U4929 ( .A(n5469), .B(n5468), .Y(n5471) );
NAND2X1TS U4930 ( .A(n6148), .B(n6867), .Y(n4271) );
INVX2TS U4931 ( .A(n2463), .Y(n5648) );
INVX2TS U4932 ( .A(FPSENCOS_d_ff2_X[14]), .Y(n6417) );
INVX2TS U4933 ( .A(FPSENCOS_d_ff2_X[20]), .Y(n6425) );
XNOR2X1TS U4934 ( .A(n3398), .B(n3397), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
OAI32X1TS U4935 ( .A0(n6456), .A1(FPSENCOS_cont_iter_out[3]), .A2(n4555),
.B0(n4554), .B1(n6899), .Y(n2114) );
INVX2TS U4937 ( .A(FPADDSUB_intDX_EWSW[5]), .Y(n6692) );
OAI21X1TS U4938 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n2466), .B0(n2508), .Y(
n2550) );
NOR2X1TS U4939 ( .A(n2460), .B(FPADDSUB_intDX_EWSW[17]), .Y(n2554) );
AOI22X1TS U4940 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n2460), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n2507), .Y(n2510) );
OAI32X1TS U4941 ( .A0(n2550), .A1(n2551), .A2(n2510), .B0(n2509), .B1(n2551),
.Y(n2513) );
OAI2BB2XLTS U4942 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n2511), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n2438), .Y(n2512) );
AOI211X1TS U4943 ( .A0(n2515), .A1(n2514), .B0(n2513), .C0(n2512), .Y(n2558)
);
INVX2TS U4944 ( .A(FPADDSUB_intDX_EWSW[10]), .Y(n2516) );
AOI21X1TS U4945 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n2516), .B0(n2533), .Y(
n2538) );
OAI2BB1X1TS U4946 ( .A0N(n2465), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n2517) );
OAI22X1TS U4947 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2517), .B0(n6692), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n2530) );
INVX2TS U4948 ( .A(FPADDSUB_intDX_EWSW[7]), .Y(n2526) );
OAI2BB1X1TS U4949 ( .A0N(n2526), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n2518) );
OAI2BB2XLTS U4950 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n2519), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n2433), .Y(n2521) );
AOI22X1TS U4951 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n2526), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n2525), .Y(n2527) );
OAI2BB2XLTS U4952 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n2532), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n2467), .Y(n2544) );
AOI22X1TS U4953 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n6748), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n2534), .Y(n2540) );
AOI21X1TS U4954 ( .A0(n2537), .A1(n2536), .B0(n2547), .Y(n2539) );
OAI31X1TS U4955 ( .A0(n2549), .A1(n2548), .A2(n2547), .B0(n2546), .Y(n2556)
);
AOI211X1TS U4956 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n2552), .B0(n2551),
.C0(n2550), .Y(n2553) );
OAI21X1TS U4957 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n2423), .B0(n2562), .Y(
n2565) );
NOR2X1TS U4958 ( .A(n2421), .B(FPADDSUB_intDX_EWSW[25]), .Y(n2560) );
INVX2TS U4959 ( .A(FPADDSUB_intDX_EWSW[28]), .Y(n2568) );
NOR2X1TS U4960 ( .A(n2430), .B(FPADDSUB_intDX_EWSW[29]), .Y(n2567) );
NAND4BBX1TS U4961 ( .AN(n2565), .BN(n2560), .C(n2572), .D(n2559), .Y(n2575)
);
AOI22X1TS U4962 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n2421), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n2561), .Y(n2566) );
OAI211X1TS U4963 ( .A0(n2566), .A1(n2565), .B0(n2564), .C0(n2563), .Y(n2573)
);
NAND2X2TS U4964 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .B(n6706), .Y(n2577) );
BUFX3TS U4965 ( .A(n2577), .Y(n5433) );
BUFX3TS U4966 ( .A(n6708), .Y(n6714) );
BUFX3TS U4967 ( .A(n6714), .Y(n5418) );
AOI22X1TS U4968 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n5418), .Y(n2578) );
NOR2X2TS U4969 ( .A(n6751), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6564) );
INVX4TS U4970 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(n2580)
);
INVX4TS U4971 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(n2581)
);
NOR2X8TS U4972 ( .A(n2587), .B(n2586), .Y(n2629) );
ADDFHX4TS U4973 ( .A(n2579), .B(n2580), .CI(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2]), .CO(
n2588), .S(n2587) );
NOR2X8TS U4974 ( .A(n2589), .B(n2588), .Y(n2631) );
NOR2X4TS U4975 ( .A(n2629), .B(n2631), .Y(n2585) );
XNOR2X4TS U4976 ( .A(n2581), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2584) );
NAND2X4TS U4977 ( .A(n2582), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .Y(
n2619) );
INVX2TS U4978 ( .A(n2619), .Y(n2583) );
AOI21X4TS U4979 ( .A0(n2700), .A1(n2620), .B0(n2583), .Y(n2617) );
OAI21X4TS U4980 ( .A0(n2614), .A1(n2617), .B0(n2615), .Y(n2611) );
OAI21X4TS U4981 ( .A0(n2631), .A1(n2628), .B0(n2632), .Y(n2590) );
NOR2X8TS U4982 ( .A(n2404), .B(n2590), .Y(n2667) );
INVX4TS U4983 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n2596) );
INVX2TS U4984 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n2595)
);
INVX4TS U4985 ( .A(n2602), .Y(n2626) );
INVX2TS U4986 ( .A(n2625), .Y(n2594) );
INVX2TS U4987 ( .A(n2604), .Y(n2599) );
OAI21X4TS U4988 ( .A0(n2604), .A1(n2625), .B0(n2603), .Y(n2664) );
INVX2TS U4989 ( .A(n2659), .Y(n2608) );
NOR2X4TS U4990 ( .A(n4215), .B(n2897), .Y(n2644) );
INVX4TS U4991 ( .A(n2611), .Y(n2630) );
INVX2TS U4992 ( .A(n2629), .Y(n2612) );
NAND2X2TS U4993 ( .A(n2612), .B(n2628), .Y(n2613) );
XOR2X4TS U4994 ( .A(n2630), .B(n2613), .Y(n2623) );
OR2X4TS U4995 ( .A(n2623), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n4222) );
INVX2TS U4996 ( .A(n2614), .Y(n2616) );
NAND2X2TS U4997 ( .A(n2616), .B(n2615), .Y(n2618) );
XOR2X4TS U4998 ( .A(n2618), .B(n2617), .Y(n2622) );
XNOR2X4TS U4999 ( .A(n2621), .B(n2700), .Y(n2719) );
AOI21X4TS U5000 ( .A0(n4222), .A1(n4223), .B0(n2624), .Y(n4197) );
NAND2X2TS U5001 ( .A(n2626), .B(n2625), .Y(n2627) );
XOR2X4TS U5002 ( .A(n2667), .B(n2627), .Y(n2637) );
OAI21X4TS U5003 ( .A0(n2630), .A1(n2629), .B0(n2628), .Y(n2635) );
INVX2TS U5004 ( .A(n2631), .Y(n2633) );
NAND2X2TS U5005 ( .A(n2633), .B(n2632), .Y(n2634) );
XNOR2X4TS U5006 ( .A(n2635), .B(n2634), .Y(n2636) );
NAND2X2TS U5007 ( .A(n4200), .B(n4211), .Y(n2640) );
NAND2X4TS U5008 ( .A(n2636), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n4210) );
AOI21X4TS U5009 ( .A0(n4200), .A1(n4198), .B0(n2638), .Y(n2639) );
OAI21X4TS U5010 ( .A0(n4197), .A1(n2640), .B0(n2639), .Y(n2896) );
OAI21X4TS U5011 ( .A0(n2897), .A1(n4216), .B0(n2898), .Y(n2643) );
AOI21X4TS U5012 ( .A0(n2644), .A1(n2896), .B0(n2643), .Y(n2843) );
INVX2TS U5013 ( .A(n2666), .Y(n2645) );
NOR2X2TS U5014 ( .A(n2645), .B(n2659), .Y(n2648) );
AOI21X2TS U5015 ( .A0(n2649), .A1(n2648), .B0(n2647), .Y(n2656) );
INVX2TS U5016 ( .A(n2662), .Y(n2654) );
XOR2X4TS U5017 ( .A(n2656), .B(n2655), .Y(n2657) );
INVX2TS U5018 ( .A(n2889), .Y(n2658) );
AOI21X4TS U5019 ( .A0(n2931), .A1(n2888), .B0(n2658), .Y(n2679) );
AOI21X4TS U5020 ( .A0(n2665), .A1(n2664), .B0(n2663), .Y(n2670) );
NAND2X4TS U5021 ( .A(n2666), .B(n2665), .Y(n2668) );
NAND2X8TS U5022 ( .A(n2670), .B(n2669), .Y(n2864) );
OR2X4TS U5023 ( .A(n2674), .B(n2673), .Y(n2822) );
NAND2X4TS U5024 ( .A(n2674), .B(n2673), .Y(n2815) );
XNOR2X4TS U5025 ( .A(n2864), .B(n2675), .Y(n2676) );
INVX2TS U5026 ( .A(n2840), .Y(n2677) );
XOR2X4TS U5027 ( .A(n2679), .B(n2678), .Y(n6747) );
NOR2X6TS U5028 ( .A(DP_OP_499J223_125_1651_n231), .B(
DP_OP_499J223_125_1651_n233), .Y(n3030) );
NOR2X4TS U5029 ( .A(n3024), .B(n3030), .Y(n2753) );
OR2X2TS U5030 ( .A(DP_OP_499J223_125_1651_n246), .B(
DP_OP_499J223_125_1651_n248), .Y(n2996) );
NAND2X2TS U5031 ( .A(n2998), .B(n2996), .Y(n2747) );
XNOR2X4TS U5032 ( .A(n2684), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(n2683) );
NOR2X4TS U5033 ( .A(n2683), .B(n2682), .Y(n2690) );
INVX4TS U5034 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .Y(n2680) );
AOI21X4TS U5035 ( .A0(n2696), .A1(n2904), .B0(n2681), .Y(n2693) );
NAND2X2TS U5036 ( .A(n2683), .B(n2682), .Y(n2691) );
OAI21X4TS U5037 ( .A0(n2690), .A1(n2693), .B0(n2691), .Y(n2804) );
NOR2X8TS U5038 ( .A(n2686), .B(n2685), .Y(n2799) );
INVX2TS U5039 ( .A(n2799), .Y(n2687) );
NAND2X6TS U5040 ( .A(n2686), .B(n2685), .Y(n2801) );
NAND2X2TS U5041 ( .A(n2687), .B(n2801), .Y(n2688) );
OR2X4TS U5042 ( .A(n2689), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n2778)
);
NAND2X4TS U5043 ( .A(n2689), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n2775)
);
NAND2X1TS U5044 ( .A(n2778), .B(n2775), .Y(n2699) );
INVX2TS U5045 ( .A(n2690), .Y(n2692) );
XNOR2X2TS U5046 ( .A(n2699), .B(n2777), .Y(n3067) );
INVX2TS U5047 ( .A(n3067), .Y(n2743) );
INVX2TS U5048 ( .A(FPMULT_Sgf_operation_Result[1]), .Y(n2703) );
XNOR2X1TS U5049 ( .A(n2703), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n2702) );
NOR2X1TS U5050 ( .A(n2702), .B(n2682), .Y(n2891) );
INVX2TS U5051 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .Y(n2904) );
NAND2X1TS U5052 ( .A(n2700), .B(n2727), .Y(n2902) );
INVX2TS U5053 ( .A(n2902), .Y(n2701) );
AOI21X1TS U5054 ( .A0(n2903), .A1(n2904), .B0(n2701), .Y(n2894) );
NAND2X1TS U5055 ( .A(n2702), .B(n2682), .Y(n2892) );
OAI21X2TS U5056 ( .A0(n2891), .A1(n2894), .B0(n2892), .Y(n2911) );
INVX2TS U5057 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n2707) );
INVX2TS U5058 ( .A(n2908), .Y(n2706) );
AOI21X2TS U5059 ( .A0(n2911), .A1(n2909), .B0(n2706), .Y(n2922) );
INVX2TS U5060 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n2711) );
INVX2TS U5061 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(n2710) );
CMPR32X2TS U5062 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .B(n2707), .C(n2780), .CO(n2708), .S(n2705) );
NOR2X1TS U5063 ( .A(n2709), .B(n2708), .Y(n2918) );
NAND2X1TS U5064 ( .A(n2709), .B(n2708), .Y(n2919) );
INVX2TS U5065 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(n2716) );
CMPR32X2TS U5066 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .B(n2711), .C(n2710), .CO(n2712), .S(n2709) );
NAND2X1TS U5067 ( .A(n2713), .B(n2712), .Y(n2937) );
INVX2TS U5068 ( .A(n2937), .Y(n2714) );
AOI21X4TS U5069 ( .A0(n2940), .A1(n2938), .B0(n2714), .Y(n2960) );
INVX2TS U5070 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[5]), .Y(n2715) );
INVX2TS U5071 ( .A(n2715), .Y(n6259) );
CMPR32X2TS U5072 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .B(n2596), .C(n2716), .CO(n2717), .S(n2713) );
NOR2X1TS U5073 ( .A(n2718), .B(n2717), .Y(n2956) );
NAND2X1TS U5074 ( .A(n2718), .B(n2717), .Y(n2957) );
OAI21X4TS U5075 ( .A0(n2960), .A1(n2956), .B0(n2957), .Y(n2955) );
CMPR32X2TS U5076 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .B(n2715), .C(n3120), .CO(n2730), .S(n2718) );
INVX2TS U5077 ( .A(n6275), .Y(n2729) );
INVX2TS U5078 ( .A(n3061), .Y(n2723) );
OR2X2TS U5079 ( .A(n2724), .B(n2723), .Y(n2953) );
NAND2X1TS U5080 ( .A(n2724), .B(n2723), .Y(n2952) );
INVX2TS U5081 ( .A(n2952), .Y(n2725) );
OR2X4TS U5082 ( .A(n2726), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .Y(
n4035) );
NAND2X4TS U5083 ( .A(n2726), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .Y(
n4033) );
INVX2TS U5084 ( .A(n2731), .Y(n2733) );
INVX2TS U5085 ( .A(n6276), .Y(n4237) );
INVX2TS U5086 ( .A(n2736), .Y(n2738) );
INVX2TS U5087 ( .A(n3065), .Y(n2741) );
NOR2X2TS U5088 ( .A(n2742), .B(n2741), .Y(n2965) );
INVX2TS U5089 ( .A(n2880), .Y(n2744) );
NAND2X2TS U5090 ( .A(DP_OP_499J223_125_1651_n246), .B(
DP_OP_499J223_125_1651_n248), .Y(n2813) );
INVX2TS U5091 ( .A(n2813), .Y(n2995) );
INVX2TS U5092 ( .A(n2999), .Y(n2745) );
AOI21X4TS U5093 ( .A0(n2998), .A1(n2995), .B0(n2745), .Y(n2746) );
OAI21X4TS U5094 ( .A0(n2747), .A1(n2812), .B0(n2746), .Y(n2987) );
OR2X4TS U5095 ( .A(DP_OP_499J223_125_1651_n240), .B(
DP_OP_499J223_125_1651_n242), .Y(n2986) );
NAND2X2TS U5096 ( .A(DP_OP_499J223_125_1651_n240), .B(
DP_OP_499J223_125_1651_n242), .Y(n2985) );
INVX2TS U5097 ( .A(n2985), .Y(n2748) );
AOI21X4TS U5098 ( .A0(n2987), .A1(n2986), .B0(n2748), .Y(n3010) );
INVX2TS U5099 ( .A(n3015), .Y(n3011) );
AOI21X4TS U5100 ( .A0(n2470), .A1(n3011), .B0(n2749), .Y(n2750) );
OAI21X4TS U5101 ( .A0(n2751), .A1(n3010), .B0(n2750), .Y(n3023) );
NAND2X4TS U5102 ( .A(DP_OP_499J223_125_1651_n231), .B(
DP_OP_499J223_125_1651_n233), .Y(n3031) );
OAI21X4TS U5103 ( .A0(n3024), .A1(n3031), .B0(n3025), .Y(n2752) );
AOI21X4TS U5104 ( .A0(n2753), .A1(n3023), .B0(n2752), .Y(n2766) );
NOR2X6TS U5105 ( .A(DP_OP_499J223_125_1651_n222), .B(
DP_OP_499J223_125_1651_n224), .Y(n3042) );
NOR2X4TS U5106 ( .A(n3040), .B(n3042), .Y(n3050) );
INVX2TS U5107 ( .A(n3050), .Y(n2754) );
NOR2X6TS U5108 ( .A(DP_OP_499J223_125_1651_n219), .B(
DP_OP_499J223_125_1651_n221), .Y(n3052) );
NAND2X4TS U5109 ( .A(DP_OP_499J223_125_1651_n225), .B(
DP_OP_499J223_125_1651_n227), .Y(n3047) );
OAI21X4TS U5110 ( .A0(n3042), .A1(n3047), .B0(n2498), .Y(n3049) );
INVX2TS U5111 ( .A(n3049), .Y(n2755) );
NAND2X4TS U5112 ( .A(DP_OP_499J223_125_1651_n219), .B(
DP_OP_499J223_125_1651_n221), .Y(n3053) );
INVX2TS U5113 ( .A(n2762), .Y(n2758) );
XOR2X4TS U5114 ( .A(n2760), .B(n2759), .Y(n3066) );
NOR2X4TS U5115 ( .A(n3066), .B(n3065), .Y(n4188) );
NAND2X2TS U5116 ( .A(n2764), .B(n3050), .Y(n2767) );
OAI21X4TS U5117 ( .A0(n2762), .A1(n3053), .B0(n2761), .Y(n2763) );
AOI21X4TS U5118 ( .A0(n2764), .A1(n3049), .B0(n2763), .Y(n2765) );
OAI21X4TS U5119 ( .A0(n2767), .A1(n2766), .B0(n2765), .Y(n2768) );
CLKINVX12TS U5120 ( .A(n2768), .Y(n3109) );
INVX16TS U5121 ( .A(n3109), .Y(n3136) );
NAND2X4TS U5122 ( .A(DP_OP_499J223_125_1651_n213), .B(
DP_OP_499J223_125_1651_n215), .Y(n2791) );
NAND2X2TS U5123 ( .A(n2791), .B(n2771), .Y(n2769) );
XNOR2X4TS U5124 ( .A(n3136), .B(n2769), .Y(n3068) );
NOR2X4TS U5125 ( .A(n4188), .B(n4190), .Y(n4450) );
INVX2TS U5126 ( .A(n2791), .Y(n2770) );
AOI21X4TS U5127 ( .A0(n3136), .A1(n2771), .B0(n2770), .Y(n2774) );
NOR2X8TS U5128 ( .A(DP_OP_499J223_125_1651_n210), .B(
DP_OP_499J223_125_1651_n212), .Y(n2792) );
INVX2TS U5129 ( .A(n2792), .Y(n2772) );
XOR2X4TS U5130 ( .A(n2774), .B(n2773), .Y(n3069) );
AOI21X4TS U5131 ( .A0(n2778), .A1(n2777), .B0(n2776), .Y(n3082) );
INVX6TS U5132 ( .A(n3082), .Y(n2809) );
OAI21X4TS U5133 ( .A0(n2779), .A1(n2799), .B0(n2801), .Y(n2786) );
INVX4TS U5134 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n2796) );
INVX2TS U5135 ( .A(n2802), .Y(n2784) );
XNOR2X4TS U5136 ( .A(n2786), .B(n2785), .Y(n2787) );
XNOR2X4TS U5137 ( .A(n2809), .B(n2788), .Y(n4234) );
NOR2X4TS U5138 ( .A(n2789), .B(n2792), .Y(n3102) );
OAI21X4TS U5139 ( .A0(n2792), .A1(n2791), .B0(n2790), .Y(n3108) );
AOI21X4TS U5140 ( .A0(n3136), .A1(n3102), .B0(n3108), .Y(n2795) );
NOR2X8TS U5141 ( .A(DP_OP_499J223_125_1651_n207), .B(
DP_OP_499J223_125_1651_n209), .Y(n3101) );
INVX2TS U5142 ( .A(n3101), .Y(n2793) );
NAND2X4TS U5143 ( .A(DP_OP_499J223_125_1651_n207), .B(
DP_OP_499J223_125_1651_n209), .Y(n3105) );
NAND2X2TS U5144 ( .A(n2793), .B(n3105), .Y(n2794) );
XOR2X4TS U5145 ( .A(n2795), .B(n2794), .Y(n3070) );
ADDFHX4TS U5146 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]), .B(n2796), .CI(n2710), .CO(n2797), .S(n2783) );
NOR2X4TS U5147 ( .A(n2798), .B(n2797), .Y(n3115) );
NAND2X4TS U5148 ( .A(n2798), .B(n2797), .Y(n3117) );
NAND2X2TS U5149 ( .A(n3084), .B(n3117), .Y(n2806) );
NOR2X4TS U5150 ( .A(n2799), .B(n2802), .Y(n2805) );
OAI21X4TS U5151 ( .A0(n2802), .A1(n2801), .B0(n2800), .Y(n2803) );
AOI21X4TS U5152 ( .A0(n2805), .A1(n2804), .B0(n2803), .Y(n3171) );
INVX8TS U5153 ( .A(n3171), .Y(n3152) );
XNOR2X4TS U5154 ( .A(n2806), .B(n3152), .Y(n2807) );
NAND2X4TS U5155 ( .A(n2807), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n3076) );
XOR2X4TS U5156 ( .A(n2811), .B(n2810), .Y(n4208) );
NAND2X4TS U5157 ( .A(n4450), .B(n3072), .Y(n3074) );
NAND2X1TS U5158 ( .A(n2996), .B(n2813), .Y(n2814) );
AOI21X4TS U5159 ( .A0(n2864), .A1(n2822), .B0(n2825), .Y(n2821) );
XOR2X4TS U5160 ( .A(n2821), .B(n2820), .Y(n2837) );
INVX2TS U5161 ( .A(n2856), .Y(n2828) );
AOI21X4TS U5162 ( .A0(n2826), .A1(n2825), .B0(n2824), .Y(n2862) );
INVX2TS U5163 ( .A(n2862), .Y(n2827) );
AOI21X4TS U5164 ( .A0(n2864), .A1(n2828), .B0(n2827), .Y(n2835) );
INVX2TS U5165 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n2848) );
CMPR32X2TS U5166 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]), .B(
n2830), .C(n2829), .CO(n2831), .S(n2819) );
INVX2TS U5167 ( .A(n2855), .Y(n2833) );
NAND2X2TS U5168 ( .A(n2832), .B(n2831), .Y(n2858) );
XOR2X4TS U5169 ( .A(n2835), .B(n2834), .Y(n2838) );
NOR2X8TS U5170 ( .A(n2928), .B(n2932), .Y(n2842) );
OAI21X4TS U5171 ( .A0(n2889), .A1(n2840), .B0(n2836), .Y(n2925) );
NAND2X2TS U5172 ( .A(n2838), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n2933)
);
OAI21X4TS U5173 ( .A0(n2932), .A1(n2926), .B0(n2933), .Y(n2839) );
AOI21X4TS U5174 ( .A0(n2842), .A1(n2925), .B0(n2839), .Y(n2845) );
NAND2X4TS U5175 ( .A(n2842), .B(n2923), .Y(n2844) );
NAND2X8TS U5176 ( .A(n2845), .B(n2197), .Y(n2992) );
INVX2TS U5177 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n2865) );
NOR2X4TS U5178 ( .A(n2851), .B(n2850), .Y(n2859) );
INVX2TS U5179 ( .A(n2859), .Y(n2852) );
NAND2X2TS U5180 ( .A(n2851), .B(n2850), .Y(n2857) );
CMPR32X2TS U5181 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]), .B(
n2866), .C(n2865), .CO(n2867), .S(n2851) );
INVX2TS U5182 ( .A(n2871), .Y(n2868) );
NAND2X2TS U5183 ( .A(n2867), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n2870) );
OAI21X4TS U5184 ( .A0(n2872), .A1(n2871), .B0(n2870), .Y(n2873) );
XNOR2X4TS U5185 ( .A(n2873), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]), .Y(
n2876) );
INVX2TS U5186 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(n2886)
);
NAND2X4TS U5187 ( .A(n2876), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n2971)
);
NOR2X4TS U5188 ( .A(n2971), .B(n2886), .Y(n2877) );
AOI21X4TS U5189 ( .A0(n2884), .A1(n2878), .B0(n2877), .Y(n2991) );
OAI21X4TS U5190 ( .A0(n2964), .A1(n2989), .B0(n2991), .Y(n2879) );
INVX2TS U5191 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(n2990)
);
XNOR2X4TS U5192 ( .A(n2879), .B(n2990), .Y(n4231) );
NOR2X2TS U5193 ( .A(n2982), .B(n4231), .Y(n6306) );
XNOR2X1TS U5194 ( .A(n2883), .B(n2882), .Y(n2981) );
AOI21X4TS U5195 ( .A0(n2992), .A1(n2885), .B0(n2884), .Y(n2974) );
OAI21X4TS U5196 ( .A0(n2974), .A1(n2970), .B0(n2971), .Y(n2887) );
XNOR2X4TS U5197 ( .A(n2887), .B(n2886), .Y(n4230) );
NOR2X2TS U5198 ( .A(n2981), .B(n4230), .Y(n6304) );
XNOR2X4TS U5199 ( .A(n2207), .B(n2890), .Y(n4225) );
INVX1TS U5200 ( .A(n2891), .Y(n2893) );
NAND2X1TS U5201 ( .A(n2893), .B(n2892), .Y(n2895) );
XOR2X1TS U5202 ( .A(n2895), .B(n2894), .Y(n2906) );
OAI21X4TS U5203 ( .A0(n4219), .A1(n4215), .B0(n4216), .Y(n2901) );
INVX2TS U5204 ( .A(n2897), .Y(n2899) );
XNOR2X4TS U5205 ( .A(n2901), .B(n2900), .Y(n6270) );
NAND2X1TS U5206 ( .A(n2903), .B(n2902), .Y(n2905) );
XNOR2X1TS U5207 ( .A(n2905), .B(n2904), .Y(n6269) );
NAND2X1TS U5208 ( .A(n6270), .B(n6269), .Y(n6271) );
INVX2TS U5209 ( .A(n6271), .Y(n6239) );
NAND2X1TS U5210 ( .A(n4225), .B(n2906), .Y(n6238) );
INVX2TS U5211 ( .A(n6238), .Y(n2907) );
AOI21X1TS U5212 ( .A0(n2462), .A1(n6239), .B0(n2907), .Y(n6267) );
NAND2X1TS U5213 ( .A(n2909), .B(n2908), .Y(n2910) );
XNOR2X1TS U5214 ( .A(n2911), .B(n2910), .Y(n2912) );
NOR2X1TS U5215 ( .A(n2913), .B(n2912), .Y(n6263) );
NAND2X1TS U5216 ( .A(n2913), .B(n2912), .Y(n6264) );
AOI21X4TS U5217 ( .A0(n2209), .A1(n2923), .B0(n2925), .Y(n2916) );
INVX2TS U5218 ( .A(n2928), .Y(n2914) );
INVX2TS U5219 ( .A(n2918), .Y(n2920) );
NAND2X1TS U5220 ( .A(n2920), .B(n2919), .Y(n2921) );
XOR2X1TS U5221 ( .A(n2922), .B(n2921), .Y(n2941) );
NOR2X2TS U5222 ( .A(n2917), .B(n2941), .Y(n6251) );
INVX2TS U5223 ( .A(n2923), .Y(n2924) );
INVX2TS U5224 ( .A(n2925), .Y(n2927) );
AOI21X2TS U5225 ( .A0(n2209), .A1(n2930), .B0(n2929), .Y(n2936) );
INVX2TS U5226 ( .A(n2932), .Y(n2934) );
XOR2X4TS U5227 ( .A(n2936), .B(n2935), .Y(n4226) );
NAND2X1TS U5228 ( .A(n2938), .B(n2937), .Y(n2939) );
NOR2X2TS U5229 ( .A(n4226), .B(n2942), .Y(n6253) );
NOR2X1TS U5230 ( .A(n6251), .B(n6253), .Y(n2944) );
NAND2X1TS U5231 ( .A(n2917), .B(n2941), .Y(n6250) );
OAI21X1TS U5232 ( .A0(n6253), .A1(n6250), .B0(n6254), .Y(n2943) );
INVX2TS U5233 ( .A(n2961), .Y(n2946) );
AOI21X4TS U5234 ( .A0(n2992), .A1(n2962), .B0(n2946), .Y(n2951) );
INVX2TS U5235 ( .A(n2947), .Y(n2949) );
XOR2X4TS U5236 ( .A(n2951), .B(n2950), .Y(n4214) );
NAND2X1TS U5237 ( .A(n2953), .B(n2952), .Y(n2954) );
XNOR2X1TS U5238 ( .A(n2955), .B(n2954), .Y(n2976) );
NOR2X2TS U5239 ( .A(n4214), .B(n2976), .Y(n6285) );
INVX2TS U5240 ( .A(n2956), .Y(n2958) );
NAND2X1TS U5241 ( .A(n2958), .B(n2957), .Y(n2959) );
XOR2X1TS U5242 ( .A(n2960), .B(n2959), .Y(n2975) );
XOR2X4TS U5243 ( .A(n2964), .B(n2963), .Y(n4228) );
NOR2X1TS U5244 ( .A(n2975), .B(n4228), .Y(n6243) );
NOR2X1TS U5245 ( .A(n6285), .B(n6243), .Y(n6293) );
INVX2TS U5246 ( .A(n2965), .Y(n2967) );
NAND2X1TS U5247 ( .A(n2967), .B(n2966), .Y(n2969) );
XOR2X1TS U5248 ( .A(n2969), .B(n2968), .Y(n2977) );
INVX2TS U5249 ( .A(n2970), .Y(n2972) );
XOR2X4TS U5250 ( .A(n2974), .B(n2973), .Y(n4235) );
NAND2X1TS U5251 ( .A(n6293), .B(n2203), .Y(n2980) );
NAND2X1TS U5252 ( .A(n4228), .B(n2975), .Y(n6282) );
NAND2X1TS U5253 ( .A(n4214), .B(n2976), .Y(n6286) );
NAND2X1TS U5254 ( .A(n4235), .B(n2977), .Y(n6295) );
INVX2TS U5255 ( .A(n6295), .Y(n2978) );
AOI21X1TS U5256 ( .A0(n6292), .A1(n2203), .B0(n2978), .Y(n2979) );
OAI21X4TS U5257 ( .A0(n6242), .A1(n2980), .B0(n2979), .Y(n6299) );
NAND2X1TS U5258 ( .A(n2981), .B(n4230), .Y(n6303) );
NAND2X1TS U5259 ( .A(n2982), .B(n4231), .Y(n6307) );
AOI21X4TS U5260 ( .A0(n2984), .A1(n6299), .B0(n2983), .Y(n5924) );
NAND2X1TS U5261 ( .A(n2986), .B(n2985), .Y(n2988) );
XNOR2X1TS U5262 ( .A(n2988), .B(n2987), .Y(n3006) );
NOR2X4TS U5263 ( .A(n2989), .B(n2990), .Y(n2993) );
AOI2BB2X4TS U5264 ( .B0(n2993), .B1(n2992), .A0N(n2991), .A1N(n2990), .Y(
n3003) );
INVX2TS U5265 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n3002) );
XNOR2X4TS U5266 ( .A(n2994), .B(n2866), .Y(n4195) );
NAND2X1TS U5267 ( .A(n2999), .B(n2998), .Y(n3000) );
NAND2X2TS U5268 ( .A(n2204), .B(n2471), .Y(n3009) );
NAND2X1TS U5269 ( .A(n3004), .B(n4232), .Y(n6278) );
INVX2TS U5270 ( .A(n6278), .Y(n5925) );
NAND2X1TS U5271 ( .A(n3006), .B(n3005), .Y(n5926) );
INVX2TS U5272 ( .A(n5926), .Y(n3007) );
OAI21X4TS U5273 ( .A0(n5924), .A1(n3009), .B0(n3008), .Y(n5908) );
INVX2TS U5274 ( .A(n3010), .Y(n3017) );
NAND2X1TS U5275 ( .A(n2470), .B(n3012), .Y(n3013) );
NAND2X1TS U5276 ( .A(n3016), .B(n3015), .Y(n3018) );
XNOR2X2TS U5277 ( .A(n3018), .B(n3017), .Y(n3019) );
NOR2X2TS U5278 ( .A(n3019), .B(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .Y(
n5917) );
NOR2X2TS U5279 ( .A(n5909), .B(n5917), .Y(n3022) );
NAND2X2TS U5280 ( .A(n3019), .B(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .Y(
n5918) );
NAND2X2TS U5281 ( .A(n3020), .B(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(
n5910) );
OAI21X2TS U5282 ( .A0(n5909), .A1(n5918), .B0(n5910), .Y(n3021) );
AOI21X4TS U5283 ( .A0(n5908), .A1(n3022), .B0(n3021), .Y(n4314) );
OAI21X2TS U5284 ( .A0(n3034), .A1(n3030), .B0(n3031), .Y(n3028) );
INVX2TS U5285 ( .A(n3024), .Y(n3026) );
NOR2X2TS U5286 ( .A(n3036), .B(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(
n3029) );
INVX4TS U5287 ( .A(n3029), .Y(n4317) );
INVX2TS U5288 ( .A(n3030), .Y(n3032) );
NAND2X2TS U5289 ( .A(n3032), .B(n3031), .Y(n3033) );
XOR2X2TS U5290 ( .A(n3034), .B(n3033), .Y(n3035) );
NAND2X2TS U5291 ( .A(n3035), .B(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(
n5901) );
INVX2TS U5292 ( .A(n5901), .Y(n4315) );
NAND2X2TS U5293 ( .A(n3036), .B(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(
n4316) );
INVX2TS U5294 ( .A(n4316), .Y(n3037) );
AOI21X2TS U5295 ( .A0(n4317), .A1(n4315), .B0(n3037), .Y(n3038) );
OAI21X4TS U5296 ( .A0(n4314), .A1(n3039), .B0(n3038), .Y(n3281) );
INVX2TS U5297 ( .A(n3040), .Y(n3046) );
INVX2TS U5298 ( .A(n3047), .Y(n3041) );
AOI21X4TS U5299 ( .A0(n3051), .A1(n3046), .B0(n3041), .Y(n3045) );
INVX2TS U5300 ( .A(n3042), .Y(n3043) );
XOR2X4TS U5301 ( .A(n3045), .B(n3044), .Y(n3058) );
NAND2X2TS U5302 ( .A(n3047), .B(n3046), .Y(n3048) );
XNOR2X4TS U5303 ( .A(n3051), .B(n3048), .Y(n3057) );
NOR2X2TS U5304 ( .A(n3057), .B(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(
n3282) );
INVX2TS U5305 ( .A(n3052), .Y(n3054) );
NAND2X2TS U5306 ( .A(n3057), .B(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(
n4420) );
AOI21X4TS U5307 ( .A0(n3284), .A1(n3060), .B0(n3059), .Y(n4322) );
AOI21X4TS U5308 ( .A0(n3281), .A1(n3064), .B0(n3063), .Y(n4187) );
NAND2X2TS U5309 ( .A(n3068), .B(n3067), .Y(n4191) );
OAI21X4TS U5310 ( .A0(n4190), .A1(n4330), .B0(n4191), .Y(n4452) );
NAND2X2TS U5311 ( .A(n3070), .B(n4208), .Y(n4460) );
OAI21X4TS U5312 ( .A0(n4459), .A1(n4453), .B0(n4460), .Y(n3071) );
AOI21X4TS U5313 ( .A0(n3072), .A1(n4452), .B0(n3071), .Y(n3073) );
OAI21X4TS U5314 ( .A0(n3074), .A1(n4187), .B0(n3073), .Y(n4337) );
NAND2X2TS U5315 ( .A(n3079), .B(n3075), .Y(n3081) );
INVX2TS U5316 ( .A(n3076), .Y(n3077) );
AOI21X4TS U5317 ( .A0(n3079), .A1(n3078), .B0(n3077), .Y(n3080) );
OAI21X4TS U5318 ( .A0(n3082), .A1(n3081), .B0(n3080), .Y(n3147) );
INVX2TS U5319 ( .A(n3117), .Y(n3083) );
AOI21X4TS U5320 ( .A0(n3152), .A1(n3084), .B0(n3083), .Y(n3090) );
INVX4TS U5321 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n3120) );
NOR2X6TS U5322 ( .A(n3087), .B(n3086), .Y(n3118) );
INVX2TS U5323 ( .A(n3118), .Y(n3088) );
NAND2X2TS U5324 ( .A(n3087), .B(n3086), .Y(n3116) );
XOR2X4TS U5325 ( .A(n3090), .B(n3089), .Y(n3091) );
NOR2X4TS U5326 ( .A(n3091), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n3142) );
INVX2TS U5327 ( .A(n3142), .Y(n3092) );
INVX2TS U5328 ( .A(n3102), .Y(n3094) );
NOR2X2TS U5329 ( .A(n3094), .B(n3101), .Y(n3097) );
INVX2TS U5330 ( .A(n3108), .Y(n3095) );
OAI21X4TS U5331 ( .A0(n3095), .A1(n3101), .B0(n3105), .Y(n3096) );
AOI21X4TS U5332 ( .A0(n3136), .A1(n3097), .B0(n3096), .Y(n3100) );
NOR2X8TS U5333 ( .A(DP_OP_499J223_125_1651_n204), .B(
DP_OP_499J223_125_1651_n206), .Y(n3104) );
INVX2TS U5334 ( .A(n3104), .Y(n3098) );
XOR2X4TS U5335 ( .A(n3100), .B(n3099), .Y(n3247) );
NOR2X4TS U5336 ( .A(n4220), .B(n3247), .Y(n4179) );
AOI21X4TS U5337 ( .A0(n3108), .A1(n3107), .B0(n3106), .Y(n3133) );
OAI21X4TS U5338 ( .A0(n3109), .A1(n3130), .B0(n3133), .Y(n3113) );
INVX2TS U5339 ( .A(n3132), .Y(n3111) );
XNOR2X4TS U5340 ( .A(n3113), .B(n3112), .Y(n3248) );
NOR2X4TS U5341 ( .A(n3115), .B(n3118), .Y(n3170) );
OAI21X4TS U5342 ( .A0(n3118), .A1(n3117), .B0(n3116), .Y(n3168) );
INVX2TS U5343 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n3154)
);
NOR2X6TS U5344 ( .A(n3121), .B(n3122), .Y(n3164) );
INVX2TS U5345 ( .A(n3164), .Y(n3123) );
INVX2TS U5346 ( .A(n3145), .Y(n3127) );
XNOR2X4TS U5347 ( .A(n3129), .B(n3128), .Y(n4204) );
NOR2X6TS U5348 ( .A(n3248), .B(n4204), .Y(n4182) );
OAI21X4TS U5349 ( .A0(n3133), .A1(n3132), .B0(n3131), .Y(n3134) );
AOI21X4TS U5350 ( .A0(n3136), .A1(n3135), .B0(n3134), .Y(n3141) );
XOR2X4TS U5351 ( .A(n3141), .B(n3140), .Y(n3249) );
OAI21X4TS U5352 ( .A0(n3145), .A1(n3144), .B0(n3143), .Y(n3146) );
AOI21X4TS U5353 ( .A0(n3148), .A1(n3147), .B0(n3146), .Y(n3217) );
INVX8TS U5354 ( .A(n3217), .Y(n3240) );
INVX2TS U5355 ( .A(n3170), .Y(n3149) );
NOR2X2TS U5356 ( .A(n3149), .B(n3164), .Y(n3153) );
INVX2TS U5357 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n3175)
);
INVX2TS U5358 ( .A(n3166), .Y(n3158) );
NAND2X2TS U5359 ( .A(n3157), .B(n3156), .Y(n3165) );
XOR2X4TS U5360 ( .A(n3160), .B(n3159), .Y(n3161) );
NAND2X6TS U5361 ( .A(n3161), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n3237)
);
NOR2X4TS U5362 ( .A(n3161), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n3180)
);
XNOR2X4TS U5363 ( .A(n3240), .B(n3162), .Y(n4207) );
NOR2X4TS U5364 ( .A(n3249), .B(n4207), .Y(n3163) );
NOR2X6TS U5365 ( .A(n3164), .B(n3166), .Y(n3169) );
AOI21X4TS U5366 ( .A0(n3168), .A1(n3169), .B0(n3167), .Y(n3174) );
NAND2X4TS U5367 ( .A(n3170), .B(n3169), .Y(n3172) );
NAND2X8TS U5368 ( .A(n3174), .B(n3173), .Y(n3267) );
INVX2TS U5369 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n3182)
);
XNOR2X4TS U5370 ( .A(n3267), .B(n3179), .Y(n3189) );
NOR2X6TS U5371 ( .A(n3189), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n3241)
);
NOR2X4TS U5372 ( .A(n3180), .B(n3241), .Y(n3232) );
INVX2TS U5373 ( .A(n3232), .Y(n3188) );
AOI21X4TS U5374 ( .A0(n3267), .A1(n3194), .B0(n3197), .Y(n3187) );
INVX2TS U5375 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n3201)
);
OR2X4TS U5376 ( .A(n3185), .B(n3184), .Y(n3198) );
NAND2X2TS U5377 ( .A(n3185), .B(n3184), .Y(n3195) );
XOR2X4TS U5378 ( .A(n3187), .B(n3186), .Y(n3190) );
NOR2X8TS U5379 ( .A(n3190), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n3211)
);
NOR2X2TS U5380 ( .A(n3188), .B(n3211), .Y(n3193) );
NAND2X2TS U5381 ( .A(n3189), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n3242)
);
OAI21X4TS U5382 ( .A0(n3237), .A1(n3241), .B0(n3242), .Y(n3231) );
INVX2TS U5383 ( .A(n3231), .Y(n3191) );
NAND2X4TS U5384 ( .A(n3190), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n3233)
);
AOI21X2TS U5385 ( .A0(n3240), .A1(n3193), .B0(n3192), .Y(n3210) );
NAND2X4TS U5386 ( .A(n3194), .B(n3198), .Y(n3258) );
INVX2TS U5387 ( .A(n3258), .Y(n3200) );
INVX2TS U5388 ( .A(n3195), .Y(n3196) );
AOI21X4TS U5389 ( .A0(n3198), .A1(n3197), .B0(n3196), .Y(n3265) );
INVX2TS U5390 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n3222) );
INVX2TS U5391 ( .A(n3257), .Y(n3204) );
INVX2TS U5392 ( .A(n3213), .Y(n3208) );
XOR2X4TS U5393 ( .A(n3210), .B(n3209), .Y(n4229) );
NAND2X4TS U5394 ( .A(n3215), .B(n3232), .Y(n3218) );
AOI21X4TS U5395 ( .A0(n3215), .A1(n3231), .B0(n3214), .Y(n3216) );
OAI21X4TS U5396 ( .A0(n3218), .A1(n3217), .B0(n3216), .Y(n3219) );
INVX2TS U5397 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n3270)
);
INVX2TS U5398 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n3269) );
INVX2TS U5399 ( .A(n3261), .Y(n3226) );
NAND2X2TS U5400 ( .A(n3225), .B(n3224), .Y(n3259) );
NAND2X1TS U5401 ( .A(n4229), .B(n4233), .Y(n3246) );
INVX2TS U5402 ( .A(n3211), .Y(n3234) );
INVX2TS U5403 ( .A(n3237), .Y(n3238) );
AOI21X4TS U5404 ( .A0(n3240), .A1(n3239), .B0(n3238), .Y(n3245) );
INVX2TS U5405 ( .A(n3241), .Y(n3243) );
XOR2X4TS U5406 ( .A(n3245), .B(n3244), .Y(n4206) );
NOR2X2TS U5407 ( .A(n3246), .B(n3400), .Y(n3352) );
INVX2TS U5408 ( .A(n3352), .Y(n3250) );
NOR2X4TS U5409 ( .A(n3406), .B(n3250), .Y(n3252) );
NAND2X2TS U5410 ( .A(n4174), .B(n3252), .Y(n3343) );
INVX2TS U5411 ( .A(n3343), .Y(n3254) );
NAND2X4TS U5412 ( .A(n3247), .B(n4220), .Y(n4334) );
NAND2X2TS U5413 ( .A(n3248), .B(n4204), .Y(n4183) );
OAI21X4TS U5414 ( .A0(n4182), .A1(n4334), .B0(n4183), .Y(n4173) );
AO21X4TS U5415 ( .A0(n4173), .A1(n3252), .B0(n3251), .Y(n3253) );
INVX2TS U5416 ( .A(n3310), .Y(n3255) );
AOI21X4TS U5417 ( .A0(n3333), .A1(n3256), .B0(n3255), .Y(n3277) );
OR2X4TS U5418 ( .A(n3257), .B(n3261), .Y(n3264) );
NOR2X2TS U5419 ( .A(n3264), .B(n3258), .Y(n3268) );
INVX2TS U5420 ( .A(n3262), .Y(n3263) );
OAI21X4TS U5421 ( .A0(n3265), .A1(n3264), .B0(n3263), .Y(n3266) );
AOI21X4TS U5422 ( .A0(n3268), .A1(n3267), .B0(n3266), .Y(n3306) );
CMPR32X2TS U5423 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]), .B(
n3270), .C(n3269), .CO(n3271), .S(n3225) );
INVX2TS U5424 ( .A(n3305), .Y(n3272) );
NAND2X2TS U5425 ( .A(n3272), .B(n3304), .Y(n3273) );
XOR2X4TS U5426 ( .A(n3306), .B(n3273), .Y(n3274) );
INVX2TS U5427 ( .A(n3311), .Y(n3275) );
NAND2X2TS U5428 ( .A(n3274), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n3309)
);
INVX2TS U5429 ( .A(n4227), .Y(n3344) );
NAND2X1TS U5430 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FSM_add_overflow_flag), .Y(n3280) );
OAI21X1TS U5431 ( .A0(n4423), .A1(n3282), .B0(n4420), .Y(n3286) );
NAND2X1TS U5432 ( .A(n3284), .B(n3283), .Y(n3285) );
INVX2TS U5433 ( .A(FPADDSUB_bit_shift_SHT2), .Y(n4578) );
NOR2X2TS U5434 ( .A(n2311), .B(n4578), .Y(n4480) );
AOI22X1TS U5435 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n2342), .Y(n3290) );
INVX2TS U5436 ( .A(n5966), .Y(n3288) );
NOR2X4TS U5437 ( .A(n4274), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n5944)
);
NAND2X2TS U5438 ( .A(n5951), .B(n5944), .Y(n5974) );
AOI22X1TS U5439 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2326), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2329), .Y(n3289) );
OAI211X1TS U5440 ( .A0(n5996), .A1(n2263), .B0(n3290), .C0(n3289), .Y(n5956)
);
NOR2X2TS U5441 ( .A(n6785), .B(n4578), .Y(n5948) );
AOI22X1TS U5442 ( .A0(FPADDSUB_Data_array_SWR[23]), .A1(n5944), .B0(
FPADDSUB_Data_array_SWR[19]), .B1(n2312), .Y(n3291) );
NAND2BX1TS U5443 ( .AN(n5948), .B(n3291), .Y(n5955) );
NAND2X2TS U5444 ( .A(n2263), .B(n6005), .Y(n6007) );
INVX2TS U5445 ( .A(n6007), .Y(n4281) );
AOI22X1TS U5446 ( .A0(n5956), .A1(n2235), .B0(n5955), .B1(n4281), .Y(n5991)
);
NOR2X4TS U5447 ( .A(n2263), .B(n4578), .Y(n5979) );
NAND2X2TS U5448 ( .A(n6005), .B(n5979), .Y(n5999) );
AND4X1TS U5449 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n3292) );
XNOR2X2TS U5450 ( .A(DP_OP_26J223_129_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n3302) );
OAI2BB1X4TS U5451 ( .A0N(n2503), .A1N(n3302), .B0(n6022), .Y(n3294) );
INVX4TS U5452 ( .A(n3294), .Y(n6017) );
INVX2TS U5453 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n3296) );
INVX2TS U5454 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n3295) );
NOR2X1TS U5455 ( .A(n3298), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n3299) );
NOR2BX1TS U5456 ( .AN(n3299), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n3300)
);
NOR2BX2TS U5457 ( .AN(n3300), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n3301)
);
AOI21X1TS U5458 ( .A0(n5991), .A1(n5999), .B0(n6660), .Y(n3303) );
OAI21X4TS U5459 ( .A0(n3306), .A1(n3305), .B0(n3304), .Y(n3307) );
XNOR2X4TS U5460 ( .A(n3307), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .Y(
n3312) );
NOR2X8TS U5461 ( .A(n3312), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n3321)
);
NOR2X4TS U5462 ( .A(n3308), .B(n3311), .Y(n3314) );
OAI21X4TS U5463 ( .A0(n3311), .A1(n3310), .B0(n3309), .Y(n3318) );
AOI21X4TS U5464 ( .A0(n3333), .A1(n3314), .B0(n3318), .Y(n3325) );
NAND2X4TS U5465 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .B(n3312),
.Y(n3322) );
OAI21X4TS U5466 ( .A0(n3321), .A1(n3325), .B0(n3322), .Y(n3313) );
INVX2TS U5467 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n3315) );
XNOR2X4TS U5468 ( .A(n3313), .B(n3315), .Y(n4203) );
NAND2X4TS U5469 ( .A(n3314), .B(n3317), .Y(n3328) );
AOI21X4TS U5470 ( .A0(n3318), .A1(n3317), .B0(n3316), .Y(n3330) );
OAI21X4TS U5471 ( .A0(n3319), .A1(n3328), .B0(n3330), .Y(n3320) );
XNOR2X4TS U5472 ( .A(n3320), .B(n3329), .Y(n4196) );
NAND2X1TS U5473 ( .A(n3353), .B(n4196), .Y(n3326) );
INVX2TS U5474 ( .A(n3321), .Y(n3323) );
XOR2X4TS U5475 ( .A(n3325), .B(n3324), .Y(n4209) );
NAND2X1TS U5476 ( .A(n4209), .B(n4227), .Y(n3350) );
NAND2X1TS U5477 ( .A(n3327), .B(n3352), .Y(n3334) );
NAND2X2TS U5478 ( .A(n4174), .B(n3336), .Y(n3427) );
AOI21X4TS U5479 ( .A0(n3333), .A1(n3332), .B0(n3331), .Y(n3340) );
INVX2TS U5480 ( .A(n3350), .Y(n3351) );
INVX2TS U5481 ( .A(n3353), .Y(n3420) );
NOR2X2TS U5482 ( .A(DP_OP_502J223_128_4510_n117), .B(
DP_OP_502J223_128_4510_n122), .Y(n5507) );
INVX2TS U5483 ( .A(n4437), .Y(n3380) );
INVX2TS U5484 ( .A(n4431), .Y(n3361) );
INVX2TS U5485 ( .A(n3364), .Y(n5545) );
INVX2TS U5486 ( .A(n3365), .Y(n3367) );
ADDHXLTS U5487 ( .A(n2481), .B(FPMULT_Op_MX[7]), .CO(n3370), .S(n3364) );
INVX2TS U5488 ( .A(n3370), .Y(n5544) );
OAI22X1TS U5489 ( .A0(n2313), .A1(n5545), .B0(n2377), .B1(n5544), .Y(n3379)
);
INVX2TS U5490 ( .A(n3375), .Y(n5535) );
NOR2X1TS U5491 ( .A(n5535), .B(n5540), .Y(n4352) );
INVX2TS U5492 ( .A(n3374), .Y(n5543) );
INVX2TS U5493 ( .A(n3375), .Y(n4572) );
ADDHXLTS U5494 ( .A(FPMULT_Op_MX[2]), .B(n2287), .CO(n3376), .S(n3374) );
INVX2TS U5495 ( .A(n3376), .Y(n5541) );
OAI22X1TS U5496 ( .A0(n5542), .A1(n5543), .B0(n4572), .B1(n5541), .Y(n4351)
);
NOR2X1TS U5497 ( .A(n4572), .B(n5543), .Y(n3387) );
OAI22X1TS U5498 ( .A0(n5542), .A1(n5545), .B0(n5535), .B1(n5544), .Y(n3386)
);
NOR2X1TS U5499 ( .A(DP_OP_502J223_128_4510_n136), .B(n3393), .Y(n5520) );
CMPR32X2TS U5500 ( .A(n3379), .B(n3378), .C(n3377), .CO(n3393), .S(n3392) );
INVX2TS U5501 ( .A(n4434), .Y(n3381) );
CLKXOR2X4TS U5502 ( .A(n3383), .B(n3382), .Y(n5548) );
INVX2TS U5503 ( .A(n3384), .Y(n5549) );
ADDHXLTS U5504 ( .A(n6568), .B(FPMULT_Op_MX[6]), .CO(n3385), .S(n3384) );
INVX2TS U5505 ( .A(n3385), .Y(n5547) );
OAI22X1TS U5506 ( .A0(n5548), .A1(n5549), .B0(n2314), .B1(n5547), .Y(n3391)
);
NOR2X1TS U5507 ( .A(n3392), .B(n3391), .Y(n5525) );
ADDHX1TS U5508 ( .A(n3387), .B(n3386), .CO(n3377), .S(n3389) );
OAI22X1TS U5509 ( .A0(n2313), .A1(n5549), .B0(n2377), .B1(n5547), .Y(n3388)
);
OAI22X1TS U5510 ( .A0(n2377), .A1(n5549), .B0(n4572), .B1(n5547), .Y(n5465)
);
NOR2X1TS U5511 ( .A(n5535), .B(n5545), .Y(n5464) );
NAND2X1TS U5512 ( .A(n5465), .B(n5464), .Y(n5466) );
INVX2TS U5513 ( .A(n5466), .Y(n5532) );
NAND2X1TS U5514 ( .A(n3389), .B(n3388), .Y(n5530) );
INVX2TS U5515 ( .A(n5530), .Y(n3390) );
AOI21X1TS U5516 ( .A0(n5531), .A1(n5532), .B0(n3390), .Y(n5528) );
NAND2X1TS U5517 ( .A(n3392), .B(n3391), .Y(n5526) );
NAND2X1TS U5518 ( .A(DP_OP_502J223_128_4510_n136), .B(n3393), .Y(n5521) );
NAND2X1TS U5519 ( .A(DP_OP_502J223_128_4510_n129), .B(
DP_OP_502J223_128_4510_n135), .Y(n5517) );
INVX2TS U5520 ( .A(n5517), .Y(n3394) );
AOI21X2TS U5521 ( .A0(n5518), .A1(n2472), .B0(n3394), .Y(n5515) );
NAND2X1TS U5522 ( .A(DP_OP_502J223_128_4510_n123), .B(
DP_OP_502J223_128_4510_n128), .Y(n5513) );
OAI21X2TS U5523 ( .A0(n5515), .A1(n5512), .B0(n5513), .Y(n5501) );
NAND2X1TS U5524 ( .A(DP_OP_502J223_128_4510_n110), .B(
DP_OP_502J223_128_4510_n116), .Y(n5503) );
AOI21X4TS U5525 ( .A0(n3396), .A1(n5501), .B0(n3395), .Y(n5500) );
NOR2X2TS U5526 ( .A(DP_OP_502J223_128_4510_n109), .B(
DP_OP_502J223_128_4510_n105), .Y(n5487) );
NAND2X2TS U5527 ( .A(DP_OP_502J223_128_4510_n109), .B(
DP_OP_502J223_128_4510_n105), .Y(n5497) );
OR2X2TS U5528 ( .A(DP_OP_502J223_128_4510_n102), .B(
DP_OP_502J223_128_4510_n104), .Y(n5489) );
NAND2X1TS U5529 ( .A(DP_OP_502J223_128_4510_n102), .B(
DP_OP_502J223_128_4510_n104), .Y(n5148) );
NAND2X1TS U5530 ( .A(n5489), .B(n5148), .Y(n3397) );
BUFX3TS U5531 ( .A(n2577), .Y(n5426) );
AOI22X1TS U5532 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n4321), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n6714), .Y(n3399) );
NAND2X2TS U5533 ( .A(n4174), .B(n3402), .Y(n3412) );
NOR2X2TS U5534 ( .A(n4175), .B(n3400), .Y(n3401) );
INVX2TS U5535 ( .A(n4175), .Y(n3407) );
INVX2TS U5536 ( .A(n3412), .Y(n3415) );
INVX2TS U5537 ( .A(n3413), .Y(n3414) );
INVX2TS U5538 ( .A(n3417), .Y(n3419) );
INVX2TS U5539 ( .A(n3422), .Y(n3425) );
INVX2TS U5540 ( .A(n3427), .Y(n3429) );
OAI21X4TS U5541 ( .A0(n3446), .A1(n3435), .B0(n3434), .Y(n3505) );
XNOR2X4TS U5542 ( .A(n3443), .B(n3442), .Y(n3896) );
XNOR2X4TS U5543 ( .A(n3452), .B(n3448), .Y(n3914) );
CLKXOR2X4TS U5544 ( .A(n3455), .B(n3454), .Y(n3921) );
XNOR2X4TS U5545 ( .A(n3464), .B(n3463), .Y(n3465) );
AOI21X4TS U5546 ( .A0(n2245), .A1(n3633), .B0(n3469), .Y(n3470) );
OAI21X4TS U5547 ( .A0(n3488), .A1(n3471), .B0(n3470), .Y(n3534) );
NOR2X8TS U5548 ( .A(n6570), .B(n6579), .Y(n3535) );
AOI21X4TS U5549 ( .A0(n3534), .A1(n3475), .B0(n3474), .Y(n3853) );
XNOR2X4TS U5550 ( .A(n3900), .B(n3479), .Y(n3480) );
AOI21X4TS U5551 ( .A0(n2495), .A1(n3621), .B0(n3498), .Y(n3618) );
AOI21X4TS U5552 ( .A0(n3613), .A1(n2499), .B0(n3500), .Y(n3610) );
OAI21X4TS U5553 ( .A0(n3610), .A1(n3607), .B0(n3608), .Y(n3605) );
AOI21X4TS U5554 ( .A0(n3605), .A1(n3501), .B0(n3502), .Y(n3602) );
OAI21X4TS U5555 ( .A0(n3602), .A1(n3599), .B0(n3600), .Y(n3588) );
OAI21X4TS U5556 ( .A0(n3589), .A1(n3595), .B0(n3590), .Y(n3503) );
AOI21X4TS U5557 ( .A0(n3504), .A1(n3588), .B0(n3503), .Y(n3587) );
XNOR2X4TS U5558 ( .A(n3509), .B(n3508), .Y(n3951) );
CLKXOR2X4TS U5559 ( .A(n3527), .B(n3512), .Y(n3937) );
XNOR2X4TS U5560 ( .A(n3937), .B(FPMULT_Op_MY[11]), .Y(n3521) );
AOI21X4TS U5561 ( .A0(n2222), .A1(n3516), .B0(n3515), .Y(n3517) );
OAI21X4TS U5562 ( .A0(n3626), .A1(n3654), .B0(n3627), .Y(n3523) );
AOI21X4TS U5563 ( .A0(n3524), .A1(n3625), .B0(n3523), .Y(n3640) );
INVX4TS U5564 ( .A(n6769), .Y(n6572) );
INVX4TS U5565 ( .A(n2239), .Y(n6567) );
OAI21X4TS U5566 ( .A0(n3645), .A1(n3535), .B0(n3642), .Y(n3538) );
XNOR2X4TS U5567 ( .A(n3538), .B(n3537), .Y(n3931) );
XNOR2X4TS U5568 ( .A(n3546), .B(n3545), .Y(n3867) );
OAI21X4TS U5569 ( .A0(n3584), .A1(n3578), .B0(n3579), .Y(n3571) );
XNOR2X4TS U5570 ( .A(n3555), .B(n3557), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14) );
NAND2X2TS U5571 ( .A(n3570), .B(n3575), .Y(n3564) );
XNOR2X4TS U5572 ( .A(n3569), .B(n3568), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13) );
INVX2TS U5573 ( .A(n3615), .Y(n3617) );
AFHCINX2TS U5574 ( .CIN(n3859), .B(n3623), .A(n3624), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1), .CO(n3621) );
OAI21X4TS U5575 ( .A0(n3657), .A1(n3653), .B0(n3654), .Y(n3630) );
XNOR2X4TS U5576 ( .A(n3630), .B(n3629), .Y(n3631) );
AOI21X4TS U5577 ( .A0(n3634), .A1(n2454), .B0(n3633), .Y(n3637) );
CLKXOR2X4TS U5578 ( .A(n3645), .B(n3644), .Y(n3863) );
AOI21X4TS U5579 ( .A0(n2196), .A1(n3724), .B0(n3723), .Y(n3816) );
AOI21X4TS U5580 ( .A0(n2494), .A1(n2426), .B0(n3742), .Y(n3802) );
OAI21X4TS U5581 ( .A0(n3802), .A1(n3799), .B0(n3800), .Y(n3788) );
AOI21X4TS U5582 ( .A0(n3744), .A1(n3788), .B0(n3743), .Y(n3787) );
INVX2TS U5583 ( .A(n3765), .Y(n3760) );
INVX2TS U5584 ( .A(n3799), .Y(n3801) );
XNOR2X4TS U5585 ( .A(n3867), .B(n3931), .Y(n3964) );
INVX2TS U5586 ( .A(n3896), .Y(n3915) );
XNOR2X1TS U5587 ( .A(n3900), .B(n2308), .Y(n3889) );
OAI22X1TS U5588 ( .A0(n3936), .A1(n2243), .B0(n2390), .B1(n3893), .Y(n4023)
);
OAI22X1TS U5589 ( .A0(n3901), .A1(n3898), .B0(n3897), .B1(
DP_OP_501J223_127_5235_n723), .Y(n4025) );
OAI22X1TS U5590 ( .A0(n3901), .A1(n3900), .B0(n3898), .B1(
DP_OP_501J223_127_5235_n723), .Y(n4028) );
NAND2X1TS U5591 ( .A(n3902), .B(n3901), .Y(n4027) );
INVX2TS U5592 ( .A(n4029), .Y(n4024) );
AOI21X4TS U5593 ( .A0(n3908), .A1(n4013), .B0(n3907), .Y(n3987) );
INVX2TS U5594 ( .A(n3914), .Y(n3922) );
INVX2TS U5595 ( .A(n3921), .Y(n3938) );
NAND2X2TS U5596 ( .A(n3989), .B(n2476), .Y(n3947) );
OAI21X4TS U5597 ( .A0(n3987), .A1(n3947), .B0(n3946), .Y(n3986) );
AFHCONX2TS U5598 ( .A(n4020), .B(n4019), .CI(n4018), .CON(n4015), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4) );
AFHCINX2TS U5599 ( .CIN(n4021), .B(n4022), .A(n4023), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3), .CO(n4018) );
AFHCONX2TS U5600 ( .A(n4026), .B(n4025), .CI(n4024), .CON(n4021), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2) );
NOR2X4TS U5601 ( .A(n4031), .B(n4030), .Y(n4039) );
INVX2TS U5602 ( .A(n4039), .Y(n4032) );
INVX2TS U5603 ( .A(n4033), .Y(n4034) );
INVX2TS U5604 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(n4042)
);
INVX2TS U5605 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .Y(n4041) );
INVX2TS U5606 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .Y(n4050)
);
INVX2TS U5607 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .Y(n4049) );
NOR2X4TS U5608 ( .A(n4046), .B(n4045), .Y(n4151) );
NOR2X2TS U5609 ( .A(n4149), .B(n4151), .Y(n4048) );
NAND2X2TS U5610 ( .A(n4046), .B(n4045), .Y(n4152) );
OAI21X2TS U5611 ( .A0(n4151), .A1(n4148), .B0(n4152), .Y(n4047) );
AOI21X4TS U5612 ( .A0(n4145), .A1(n4048), .B0(n4047), .Y(n4086) );
INVX4TS U5613 ( .A(n4086), .Y(n4067) );
INVX2TS U5614 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .Y(n4055)
);
INVX2TS U5615 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .Y(n4054) );
NOR2X2TS U5616 ( .A(n4052), .B(n4051), .Y(n4063) );
INVX2TS U5617 ( .A(n4063), .Y(n4061) );
NAND2X2TS U5618 ( .A(n4052), .B(n4051), .Y(n4065) );
INVX2TS U5619 ( .A(n4065), .Y(n4053) );
INVX2TS U5620 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(n4069)
);
INVX2TS U5621 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .Y(n4068) );
CMPR32X2TS U5622 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]), .B(
n4055), .C(n4054), .CO(n4056), .S(n4052) );
INVX2TS U5623 ( .A(n4066), .Y(n4058) );
NAND2X1TS U5624 ( .A(n4058), .B(n4064), .Y(n4059) );
NAND2X1TS U5625 ( .A(n4061), .B(n4065), .Y(n4062) );
NOR2X2TS U5626 ( .A(n4063), .B(n4066), .Y(n4079) );
INVX2TS U5627 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(n4073)
);
INVX2TS U5628 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .Y(n4072) );
CMPR32X2TS U5629 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]), .B(
n4069), .C(n4068), .CO(n4070), .S(n4057) );
NAND2X2TS U5630 ( .A(n4071), .B(n4070), .Y(n4168) );
OAI21X1TS U5631 ( .A0(n4171), .A1(n4167), .B0(n4168), .Y(n4078) );
INVX2TS U5632 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(n4089)
);
INVX2TS U5633 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .Y(n4088) );
NOR2X4TS U5634 ( .A(n4075), .B(n4074), .Y(n4081) );
INVX2TS U5635 ( .A(n4081), .Y(n4076) );
NAND2X2TS U5636 ( .A(n4075), .B(n4074), .Y(n4080) );
NAND2X1TS U5637 ( .A(n4076), .B(n4080), .Y(n4077) );
NAND2X2TS U5638 ( .A(n4079), .B(n4083), .Y(n4087) );
OAI21X1TS U5639 ( .A0(n4081), .A1(n4168), .B0(n4080), .Y(n4082) );
AOI21X2TS U5640 ( .A0(n4084), .A1(n4083), .B0(n4082), .Y(n4085) );
OAI21X4TS U5641 ( .A0(n4087), .A1(n4086), .B0(n4085), .Y(n4122) );
INVX2TS U5642 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(n4091)
);
INVX2TS U5643 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .Y(n4090) );
CMPR32X2TS U5644 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]), .B(
n4089), .C(n4088), .CO(n4092), .S(n4075) );
NOR2X2TS U5645 ( .A(n4093), .B(n4092), .Y(n4138) );
INVX2TS U5646 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(n4099)
);
INVX2TS U5647 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .Y(n4098) );
CMPR32X2TS U5648 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]), .B(
n4091), .C(n4090), .CO(n4094), .S(n4093) );
NOR2X4TS U5649 ( .A(n4095), .B(n4094), .Y(n4140) );
NOR2X2TS U5650 ( .A(n4138), .B(n4140), .Y(n4104) );
INVX2TS U5651 ( .A(n4104), .Y(n4097) );
NAND2X2TS U5652 ( .A(n4093), .B(n4092), .Y(n4137) );
OAI21X4TS U5653 ( .A0(n4140), .A1(n4137), .B0(n4141), .Y(n4108) );
INVX2TS U5654 ( .A(n4108), .Y(n4096) );
OAI21X1TS U5655 ( .A0(n4139), .A1(n4097), .B0(n4096), .Y(n4103) );
INVX2TS U5656 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .Y(n4110) );
INVX2TS U5657 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .Y(
n4109) );
OR2X4TS U5658 ( .A(n4101), .B(n4100), .Y(n4107) );
NAND2X2TS U5659 ( .A(n4101), .B(n4100), .Y(n4105) );
NAND2X1TS U5660 ( .A(n4107), .B(n4105), .Y(n4102) );
XNOR2X1TS U5661 ( .A(n4103), .B(n4102), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
NAND2X2TS U5662 ( .A(n4104), .B(n4107), .Y(n4116) );
INVX2TS U5663 ( .A(n4105), .Y(n4106) );
INVX2TS U5664 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .Y(
n4123) );
CMPR32X2TS U5665 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10]), .B(
n4110), .C(n4109), .CO(n4111), .S(n4101) );
NOR2X2TS U5666 ( .A(n4112), .B(n4111), .Y(n4118) );
INVX2TS U5667 ( .A(n4118), .Y(n4113) );
NAND2X1TS U5668 ( .A(n4112), .B(n4111), .Y(n4117) );
NAND2X1TS U5669 ( .A(n4113), .B(n4117), .Y(n4114) );
NOR2X2TS U5670 ( .A(n4116), .B(n4118), .Y(n4121) );
OAI21X2TS U5671 ( .A0(n4119), .A1(n4118), .B0(n4117), .Y(n4120) );
AOI21X4TS U5672 ( .A0(n4122), .A1(n4121), .B0(n4120), .Y(n4132) );
INVX2TS U5673 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
n4133) );
XNOR2X1TS U5674 ( .A(n4133), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .Y(
n4125) );
CMPR32X2TS U5675 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11]), .B(
DP_OP_496J223_122_3236_n147), .C(n4123), .CO(n4124), .S(n4112) );
NOR2X2TS U5676 ( .A(n4125), .B(n4124), .Y(n4131) );
INVX2TS U5677 ( .A(n4131), .Y(n4126) );
NAND2X2TS U5678 ( .A(n4125), .B(n4124), .Y(n4130) );
NAND2X1TS U5679 ( .A(n4126), .B(n4130), .Y(n4127) );
XOR2X1TS U5680 ( .A(n4132), .B(n4127), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
INVX2TS U5681 ( .A(n4138), .Y(n4128) );
NAND2X1TS U5682 ( .A(n4128), .B(n4137), .Y(n4129) );
XOR2X1TS U5683 ( .A(n4139), .B(n4129), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
OAI21X4TS U5684 ( .A0(n4132), .A1(n4131), .B0(n4130), .Y(n4159) );
INVX2TS U5685 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(
n4160) );
XNOR2X1TS U5686 ( .A(n4160), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .Y(
n4135) );
NAND2X1TS U5687 ( .A(n4158), .B(n4156), .Y(n4136) );
XNOR2X1TS U5688 ( .A(n4159), .B(n4136), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
OAI21X1TS U5689 ( .A0(n4139), .A1(n4138), .B0(n4137), .Y(n4144) );
INVX2TS U5690 ( .A(n4140), .Y(n4142) );
NAND2X1TS U5691 ( .A(n4142), .B(n4141), .Y(n4143) );
INVX2TS U5692 ( .A(n4149), .Y(n4146) );
XOR2X4TS U5693 ( .A(n4150), .B(n4147), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
INVX2TS U5694 ( .A(n4151), .Y(n4153) );
INVX2TS U5695 ( .A(n4156), .Y(n4157) );
AOI21X4TS U5696 ( .A0(n4159), .A1(n4158), .B0(n4157), .Y(n4166) );
NOR2X1TS U5697 ( .A(n4161), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]), .Y(
n4165) );
INVX2TS U5698 ( .A(n4165), .Y(n4162) );
NAND2X1TS U5699 ( .A(n4161), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]), .Y(
n4164) );
NAND2X1TS U5700 ( .A(n4162), .B(n4164), .Y(n4163) );
INVX2TS U5701 ( .A(n4167), .Y(n4169) );
NAND2X1TS U5702 ( .A(n4169), .B(n4168), .Y(n4170) );
INVX2TS U5703 ( .A(n4179), .Y(n4335) );
INVX2TS U5704 ( .A(n4334), .Y(n4180) );
INVX2TS U5705 ( .A(n4182), .Y(n4184) );
INVX4TS U5706 ( .A(n4187), .Y(n4457) );
INVX2TS U5707 ( .A(n4188), .Y(n4331) );
INVX2TS U5708 ( .A(n4330), .Y(n4189) );
INVX2TS U5709 ( .A(n4190), .Y(n4192) );
AOI21X4TS U5710 ( .A0(n4213), .A1(n4211), .B0(n4198), .Y(n4202) );
XOR2X4TS U5711 ( .A(n4202), .B(n4201), .Y(n6262) );
INVX4TS U5712 ( .A(n6262), .Y(DP_OP_499J223_125_1651_n279) );
NAND2X2TS U5713 ( .A(n4211), .B(n4210), .Y(n4212) );
XNOR2X4TS U5714 ( .A(n4213), .B(n4212), .Y(n6261) );
INVX2TS U5715 ( .A(n6261), .Y(DP_OP_499J223_125_1651_n280) );
INVX2TS U5716 ( .A(n4215), .Y(n4217) );
NAND2X2TS U5717 ( .A(n4217), .B(n4216), .Y(n4218) );
XOR2X4TS U5718 ( .A(n4219), .B(n4218), .Y(n6277) );
INVX4TS U5719 ( .A(n4226), .Y(DP_OP_499J223_125_1651_n273) );
INVX4TS U5720 ( .A(n4230), .Y(DP_OP_499J223_125_1651_n269) );
INVX2TS U5721 ( .A(n4234), .Y(DP_OP_499J223_125_1651_n304) );
NOR4X1TS U5722 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n4242) );
NOR4X1TS U5723 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n4241) );
NOR4X1TS U5724 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n4240) );
NOR4X1TS U5725 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n4243),
.Y(n6919) );
INVX2TS U5726 ( .A(n4244), .Y(n5538) );
NOR2X1TS U5727 ( .A(n4572), .B(n5538), .Y(n4247) );
ADDHXLTS U5728 ( .A(n6569), .B(DP_OP_501J223_127_5235_n944), .CO(n4245), .S(
n3373) );
INVX2TS U5729 ( .A(n4245), .Y(n5539) );
OAI22X1TS U5730 ( .A0(n2377), .A1(n5540), .B0(n5535), .B1(n5539), .Y(n4246)
);
ADDHX1TS U5731 ( .A(n4247), .B(n4246), .CO(DP_OP_502J223_128_4510_n137), .S(
DP_OP_502J223_128_4510_n138) );
NAND2X2TS U5732 ( .A(n6567), .B(n2383), .Y(n4975) );
NAND2X1TS U5733 ( .A(n2292), .B(n6585), .Y(n4963) );
OA21X1TS U5734 ( .A0(n4248), .A1(n4975), .B0(n4963), .Y(n4468) );
NOR2X1TS U5735 ( .A(n6567), .B(n2383), .Y(n4464) );
OAI21X1TS U5736 ( .A0(n4468), .A1(n4464), .B0(n4975), .Y(n4249) );
OR2X2TS U5737 ( .A(intadd_515_n1), .B(n4249), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11) );
OAI2BB1X2TS U5738 ( .A0N(intadd_515_n1), .A1N(n4249), .B0(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
INVX2TS U5739 ( .A(n2491), .Y(n5640) );
OAI22X1TS U5740 ( .A0(n2314), .A1(n5540), .B0(n2377), .B1(n5539), .Y(n4254)
);
NOR2X1TS U5741 ( .A(n5535), .B(n5536), .Y(n4340) );
INVX2TS U5742 ( .A(n4251), .Y(n5537) );
OAI22X1TS U5743 ( .A0(n5542), .A1(n5538), .B0(n4572), .B1(n5537), .Y(n4339)
);
OAI22X1TS U5744 ( .A0(n5548), .A1(n5543), .B0(n2314), .B1(n5541), .Y(n4252)
);
NOR2X1TS U5745 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4503) );
NAND2X1TS U5746 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4511) );
NAND2X1TS U5747 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n4504) );
OAI21X1TS U5748 ( .A0(n4503), .A1(n4511), .B0(n4504), .Y(n4523) );
NOR2X2TS U5749 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4529) );
NAND2X1TS U5750 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n4533) );
NAND2X1TS U5751 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n4530) );
AOI21X1TS U5752 ( .A0(n4523), .A1(n4256), .B0(n4255), .Y(n6186) );
NOR2X1TS U5753 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6214) );
NOR2X2TS U5754 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6209) );
NOR2X1TS U5755 ( .A(n6214), .B(n6209), .Y(n6188) );
NOR2X1TS U5756 ( .A(n6199), .B(n6181), .Y(n4258) );
NAND2X1TS U5757 ( .A(n6188), .B(n4258), .Y(n4260) );
NAND2X1TS U5758 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6226) );
NAND2X1TS U5759 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6210) );
OAI21X1TS U5760 ( .A0(n6209), .A1(n6226), .B0(n6210), .Y(n6187) );
NAND2X1TS U5761 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n6200) );
NAND2X1TS U5762 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n6182) );
AOI21X1TS U5763 ( .A0(n6187), .A1(n4258), .B0(n4257), .Y(n4259) );
NOR2X1TS U5764 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n6035) );
INVX2TS U5765 ( .A(n6035), .Y(n6054) );
NAND2X1TS U5766 ( .A(n6054), .B(n6031), .Y(n6107) );
NOR2X2TS U5767 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n6101) );
NOR2X1TS U5768 ( .A(n6107), .B(n6101), .Y(n4264) );
NAND2X1TS U5769 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n6053) );
INVX2TS U5770 ( .A(n6053), .Y(n4262) );
NAND2X1TS U5771 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n6030) );
INVX2TS U5772 ( .A(n6030), .Y(n4261) );
AOI21X1TS U5773 ( .A0(n6031), .A1(n4262), .B0(n4261), .Y(n6106) );
NAND2X1TS U5774 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n6102) );
OAI21X1TS U5775 ( .A0(n6106), .A1(n6101), .B0(n6102), .Y(n4263) );
AOI21X2TS U5776 ( .A0(n6034), .A1(n4264), .B0(n4263), .Y(n6047) );
NOR2X1TS U5777 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n6041) );
INVX2TS U5778 ( .A(n6070), .Y(n4265) );
NOR2X1TS U5779 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n6089) );
NAND2X1TS U5780 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n6090) );
NAND2X1TS U5781 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n6061) );
INVX2TS U5782 ( .A(n6061), .Y(n4266) );
AOI21X4TS U5783 ( .A0(n6066), .A1(n6062), .B0(n4266), .Y(n6085) );
NOR2X1TS U5784 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]),
.Y(n6079) );
NAND2X1TS U5785 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n6080) );
NAND2X1TS U5786 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n6172) );
INVX2TS U5787 ( .A(n6172), .Y(n4267) );
AOI21X4TS U5788 ( .A0(n6177), .A1(n6173), .B0(n4267), .Y(n6120) );
NOR2X1TS U5789 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]),
.Y(n6114) );
NAND2X1TS U5790 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n6115) );
NAND2X1TS U5791 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n6135) );
INVX2TS U5792 ( .A(n6135), .Y(n4268) );
AOI21X4TS U5793 ( .A0(n6140), .A1(n6136), .B0(n4268), .Y(n6130) );
NOR2X1TS U5794 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]),
.Y(n6124) );
NAND2X1TS U5795 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n6125) );
NAND2X1TS U5796 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n6152) );
INVX2TS U5797 ( .A(n6152), .Y(n4269) );
NOR2X1TS U5798 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]),
.Y(n6162) );
NAND2X1TS U5799 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n6163) );
NAND2X1TS U5800 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n4412) );
INVX2TS U5801 ( .A(n4412), .Y(n4270) );
BUFX3TS U5802 ( .A(n2316), .Y(n6232) );
BUFX3TS U5803 ( .A(n2316), .Y(n6711) );
AOI22X1TS U5804 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2327), .B0(
FPADDSUB_Data_array_SWR[17]), .B1(n2326), .Y(n4273) );
AOI22X1TS U5805 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2329), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n2342), .Y(n4272) );
OAI211X1TS U5806 ( .A0(n4470), .A1(n2263), .B0(n4273), .C0(n4272), .Y(n5961)
);
NAND2X1TS U5807 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n4274), .Y(n4280)
);
AOI22X1TS U5808 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n5944), .B0(
FPADDSUB_Data_array_SWR[16]), .B1(n2312), .Y(n4275) );
NAND2X1TS U5809 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(n5948), .Y(n5967)
);
AOI22X1TS U5810 ( .A0(n5961), .A1(n5984), .B0(n5959), .B1(n4281), .Y(n5987)
);
AOI21X1TS U5811 ( .A0(n5987), .A1(n5999), .B0(n6728), .Y(n4276) );
AOI22X1TS U5812 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2343), .Y(n4278) );
AOI22X1TS U5813 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2329), .Y(n4277) );
OAI211X1TS U5814 ( .A0(n6008), .A1(n2263), .B0(n4278), .C0(n4277), .Y(n5958)
);
AOI22X1TS U5815 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n5944), .B0(
FPADDSUB_Data_array_SWR[17]), .B1(n2311), .Y(n4279) );
AOI22X1TS U5816 ( .A0(n5958), .A1(n5984), .B0(n5957), .B1(n4281), .Y(n5988)
);
AOI21X1TS U5817 ( .A0(n5988), .A1(n5999), .B0(n6728), .Y(n4282) );
NOR2X4TS U5818 ( .A(n5647), .B(n6593), .Y(n4297) );
NAND2X2TS U5819 ( .A(n6749), .B(n5650), .Y(n4345) );
OAI21X4TS U5820 ( .A0(n4342), .A1(n4345), .B0(n4343), .Y(n4290) );
NAND2X2TS U5821 ( .A(n6595), .B(n6593), .Y(n4298) );
OAI21X1TS U5822 ( .A0(n4291), .A1(n4298), .B0(n4292), .Y(n4284) );
NOR2X2TS U5823 ( .A(n6586), .B(n2290), .Y(n4306) );
INVX2TS U5824 ( .A(n4306), .Y(n4286) );
NAND2X1TS U5825 ( .A(n4286), .B(n4305), .Y(n4287) );
INVX2TS U5826 ( .A(n4289), .Y(n5610) );
INVX2TS U5827 ( .A(n4290), .Y(n4301) );
INVX2TS U5828 ( .A(n4291), .Y(n4293) );
CLKXOR2X4TS U5829 ( .A(n4295), .B(n4294), .Y(n5621) );
ADDHXLTS U5830 ( .A(n6579), .B(n6567), .CO(n4296), .S(n4289) );
INVX2TS U5831 ( .A(n4296), .Y(n5609) );
OAI22X1TS U5832 ( .A0(n2318), .A1(n5610), .B0(n5621), .B1(n5609), .Y(n4313)
);
INVX2TS U5833 ( .A(n4297), .Y(n4299) );
XOR2X1TS U5834 ( .A(n4301), .B(n4300), .Y(n4302) );
OAI22X1TS U5835 ( .A0(n5621), .A1(n2344), .B0(n2310), .B1(n2405), .Y(n4364)
);
INVX2TS U5836 ( .A(n4304), .Y(n5616) );
NOR2X2TS U5837 ( .A(n2305), .B(n5616), .Y(n4363) );
OAI21X1TS U5838 ( .A0(n4307), .A1(n4306), .B0(n4305), .Y(n4308) );
CLKXOR2X4TS U5839 ( .A(n4308), .B(n5648), .Y(n5619) );
INVX2TS U5840 ( .A(n4309), .Y(n5612) );
ADDHXLTS U5841 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[21]), .CO(n4310), .S(
n4309) );
INVX2TS U5842 ( .A(n4310), .Y(n5611) );
OAI22X1TS U5843 ( .A0(n5619), .A1(n5612), .B0(n2319), .B1(n5611), .Y(n4311)
);
INVX2TS U5844 ( .A(n4314), .Y(n5903) );
AOI21X1TS U5845 ( .A0(n5903), .A1(n2485), .B0(n4315), .Y(n4319) );
NAND2X1TS U5846 ( .A(n4317), .B(n4316), .Y(n4318) );
XOR2X1TS U5847 ( .A(n4319), .B(n4318), .Y(n4320) );
INVX2TS U5848 ( .A(n2323), .Y(n4321) );
INVX2TS U5849 ( .A(n5478), .Y(n6958) );
OAI21X1TS U5850 ( .A0(n4423), .A1(n4323), .B0(n4322), .Y(n4328) );
INVX2TS U5851 ( .A(n4324), .Y(n4326) );
NAND2X1TS U5852 ( .A(n4326), .B(n4325), .Y(n4327) );
NAND2X1TS U5853 ( .A(n4331), .B(n4330), .Y(n4332) );
NAND2X1TS U5854 ( .A(n4335), .B(n4334), .Y(n4336) );
INVX2TS U5855 ( .A(n4348), .Y(n5180) );
NOR2X1TS U5856 ( .A(n5180), .B(n5610), .Y(n4350) );
INVX2TS U5857 ( .A(n4342), .Y(n4344) );
INVX2TS U5858 ( .A(n4348), .Y(n5608) );
OAI22X1TS U5859 ( .A0(n5614), .A1(n5612), .B0(n5608), .B1(n5611), .Y(n4349)
);
ADDHX1TS U5860 ( .A(n4352), .B(n4351), .CO(DP_OP_502J223_128_4510_n141), .S(
n3378) );
OAI22X1TS U5861 ( .A0(n5614), .A1(n5610), .B0(n5180), .B1(n5609), .Y(n4353)
);
OAI22X1TS U5862 ( .A0(n5617), .A1(n5612), .B0(n2376), .B1(n5611), .Y(n4359)
);
ADDHXLTS U5863 ( .A(n4354), .B(n4353), .CO(DP_OP_500J223_126_4510_n132), .S(
n4358) );
INVX2TS U5864 ( .A(n4355), .Y(n5615) );
ADDHXLTS U5865 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[20]), .CO(n4356), .S(
n4355) );
INVX2TS U5866 ( .A(n4356), .Y(n5613) );
OAI22X1TS U5867 ( .A0(n5621), .A1(n5615), .B0(n5617), .B1(n5613), .Y(n4357)
);
NOR2X2TS U5868 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(
FPADDSUB_left_right_SHT2), .Y(n5960) );
INVX2TS U5869 ( .A(n5960), .Y(n5954) );
AOI211X1TS U5870 ( .A0(FPADDSUB_Data_array_SWR[4]), .A1(n2330), .B0(n4361),
.C0(n4360), .Y(n4469) );
OAI22X1TS U5871 ( .A0(n4470), .A1(n5954), .B0(n4469), .B1(n2356), .Y(n4362)
);
NOR2X4TS U5872 ( .A(n6013), .B(n6022), .Y(n5937) );
BUFX3TS U5873 ( .A(n5937), .Y(n6009) );
OA22X1TS U5874 ( .A0(n4362), .A1(n5963), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n1180) );
NOR3X2TS U5875 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n4992) );
NOR4BX1TS U5876 ( .AN(n4992), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n4483) );
AND3X2TS U5877 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n2364),
.C(n6797), .Y(n6439) );
NOR2X1TS U5878 ( .A(n2305), .B(n5613), .Y(n4367) );
OAI22X1TS U5879 ( .A0(n2318), .A1(n2344), .B0(n5621), .B1(n2405), .Y(n4366)
);
ADDHX1TS U5880 ( .A(n4364), .B(n4363), .CO(n4365), .S(n4312) );
CMPR32X2TS U5881 ( .A(n4367), .B(n4366), .C(n4365), .CO(
DP_OP_500J223_126_4510_n106), .S(DP_OP_500J223_126_4510_n107) );
BUFX3TS U5882 ( .A(n6024), .Y(n6237) );
NAND2X1TS U5883 ( .A(n6755), .B(n6798), .Y(n4513) );
NAND2X1TS U5884 ( .A(n6861), .B(FPADDSUB_DMP_SFG[0]), .Y(n4368) );
OAI21X1TS U5885 ( .A0(n4513), .A1(n4369), .B0(n4368), .Y(n4502) );
NOR2X1TS U5886 ( .A(n6778), .B(FPADDSUB_DMP_SFG[1]), .Y(n4518) );
NOR2X1TS U5887 ( .A(n6773), .B(FPADDSUB_DMP_SFG[2]), .Y(n4371) );
NAND2X1TS U5888 ( .A(n6778), .B(FPADDSUB_DMP_SFG[1]), .Y(n4517) );
NAND2X1TS U5889 ( .A(n6773), .B(FPADDSUB_DMP_SFG[2]), .Y(n4370) );
AOI21X1TS U5890 ( .A0(n4502), .A1(n4373), .B0(n4372), .Y(n4528) );
NOR2X1TS U5891 ( .A(n6777), .B(FPADDSUB_DMP_SFG[3]), .Y(n6221) );
NOR2X1TS U5892 ( .A(n6775), .B(FPADDSUB_DMP_SFG[4]), .Y(n4375) );
NOR2X1TS U5893 ( .A(n6221), .B(n4375), .Y(n6196) );
NOR2X1TS U5894 ( .A(n6776), .B(FPADDSUB_DMP_SFG[5]), .Y(n6198) );
NOR2X1TS U5895 ( .A(n6774), .B(FPADDSUB_DMP_SFG[6]), .Y(n4377) );
NOR2X1TS U5896 ( .A(n6198), .B(n4377), .Y(n4379) );
NAND2X1TS U5897 ( .A(n6196), .B(n4379), .Y(n4381) );
NAND2X1TS U5898 ( .A(n6777), .B(FPADDSUB_DMP_SFG[3]), .Y(n6222) );
NAND2X1TS U5899 ( .A(n6775), .B(FPADDSUB_DMP_SFG[4]), .Y(n4374) );
OAI21X1TS U5900 ( .A0(n4375), .A1(n6222), .B0(n4374), .Y(n6195) );
NAND2X1TS U5901 ( .A(n6776), .B(FPADDSUB_DMP_SFG[5]), .Y(n6197) );
NAND2X1TS U5902 ( .A(n6774), .B(FPADDSUB_DMP_SFG[6]), .Y(n4376) );
AOI21X1TS U5903 ( .A0(n6195), .A1(n4379), .B0(n4378), .Y(n4380) );
OAI21X1TS U5904 ( .A0(n4528), .A1(n4381), .B0(n4380), .Y(n6025) );
NOR2X1TS U5905 ( .A(n6779), .B(FPADDSUB_DMP_SFG[7]), .Y(n6052) );
NOR2X1TS U5906 ( .A(n6856), .B(FPADDSUB_DMP_SFG[8]), .Y(n4383) );
NOR2X1TS U5907 ( .A(n6052), .B(n4383), .Y(n6026) );
NAND2X1TS U5908 ( .A(n6026), .B(n4385), .Y(n6100) );
NOR2X1TS U5909 ( .A(n6860), .B(FPADDSUB_DMP_SFG[10]), .Y(n4387) );
NOR2X1TS U5910 ( .A(n6100), .B(n4387), .Y(n4389) );
NAND2X1TS U5911 ( .A(n6779), .B(FPADDSUB_DMP_SFG[7]), .Y(n6051) );
NAND2X1TS U5912 ( .A(n6856), .B(FPADDSUB_DMP_SFG[8]), .Y(n4382) );
OAI21X1TS U5913 ( .A0(n4383), .A1(n6051), .B0(n4382), .Y(n6027) );
AOI21X1TS U5914 ( .A0(n6027), .A1(n4385), .B0(n4384), .Y(n6099) );
NAND2X1TS U5915 ( .A(n6860), .B(FPADDSUB_DMP_SFG[10]), .Y(n4386) );
OAI21X1TS U5916 ( .A0(n6099), .A1(n4387), .B0(n4386), .Y(n4388) );
AOI21X2TS U5917 ( .A0(n6025), .A1(n4389), .B0(n4388), .Y(n6045) );
NOR2X1TS U5918 ( .A(n6859), .B(FPADDSUB_DMP_SFG[11]), .Y(n4391) );
NAND2X1TS U5919 ( .A(n6859), .B(FPADDSUB_DMP_SFG[11]), .Y(n4390) );
OAI21X4TS U5920 ( .A0(n6045), .A1(n4391), .B0(n4390), .Y(n6073) );
AOI21X4TS U5921 ( .A0(n6073), .A1(n4393), .B0(n4392), .Y(n6093) );
NOR2X1TS U5922 ( .A(n6858), .B(FPADDSUB_DMP_SFG[13]), .Y(n4395) );
NAND2X1TS U5923 ( .A(n6858), .B(FPADDSUB_DMP_SFG[13]), .Y(n4394) );
OAI21X4TS U5924 ( .A0(n6093), .A1(n4395), .B0(n4394), .Y(n6064) );
AOI21X4TS U5925 ( .A0(n6064), .A1(n4397), .B0(n4396), .Y(n6083) );
NOR2X1TS U5926 ( .A(n6807), .B(FPADDSUB_DMP_SFG[15]), .Y(n4399) );
NAND2X1TS U5927 ( .A(n6807), .B(FPADDSUB_DMP_SFG[15]), .Y(n4398) );
OAI21X4TS U5928 ( .A0(n6083), .A1(n4399), .B0(n4398), .Y(n6175) );
AOI21X4TS U5929 ( .A0(n6175), .A1(n4401), .B0(n4400), .Y(n6118) );
NOR2X1TS U5930 ( .A(n6817), .B(FPADDSUB_DMP_SFG[17]), .Y(n4403) );
NAND2X1TS U5931 ( .A(n6817), .B(FPADDSUB_DMP_SFG[17]), .Y(n4402) );
AOI21X4TS U5932 ( .A0(n6138), .A1(n4405), .B0(n4404), .Y(n6128) );
NOR2X1TS U5933 ( .A(n6823), .B(FPADDSUB_DMP_SFG[19]), .Y(n4407) );
NAND2X1TS U5934 ( .A(n6823), .B(FPADDSUB_DMP_SFG[19]), .Y(n4406) );
OAI21X4TS U5935 ( .A0(n6128), .A1(n4407), .B0(n4406), .Y(n6155) );
NAND2X1TS U5936 ( .A(n6843), .B(FPADDSUB_DMP_SFG[21]), .Y(n4410) );
NAND2X1TS U5937 ( .A(n4413), .B(n4412), .Y(n4415) );
INVX2TS U5938 ( .A(n4415), .Y(n4414) );
XNOR2X1TS U5939 ( .A(n6146), .B(n4414), .Y(n4419) );
XNOR2X1TS U5940 ( .A(n4416), .B(n4415), .Y(n4417) );
BUFX3TS U5941 ( .A(n4499), .Y(n6158) );
BUFX3TS U5942 ( .A(n2316), .Y(n6191) );
AOI22X1TS U5943 ( .A0(n4417), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[24]),
.B1(n6191), .Y(n4418) );
OAI2BB1X1TS U5944 ( .A0N(n6237), .A1N(n4419), .B0(n4418), .Y(n1315) );
NAND2X1TS U5945 ( .A(n4421), .B(n4420), .Y(n4422) );
XOR2X1TS U5946 ( .A(n4423), .B(n4422), .Y(n4424) );
NAND2X2TS U5947 ( .A(FPSENCOS_cont_iter_out[3]), .B(n6372), .Y(n6369) );
NAND2X2TS U5948 ( .A(n6450), .B(n6369), .Y(n6367) );
INVX2TS U5949 ( .A(n6367), .Y(n6375) );
NAND2X2TS U5950 ( .A(n6450), .B(intadd_517_B_1_), .Y(n6362) );
NOR2X2TS U5951 ( .A(n6782), .B(n6362), .Y(n5013) );
NAND2X1TS U5952 ( .A(FPSENCOS_cont_iter_out[1]), .B(n6375), .Y(n4980) );
AOI22X1TS U5953 ( .A0(n2201), .A1(n2346), .B0(n5642), .B1(n6572), .Y(n4430)
);
NAND2X1TS U5954 ( .A(FPMULT_Op_MY[11]), .B(DP_OP_501J223_127_5235_n944), .Y(
n4925) );
NAND2X1TS U5955 ( .A(n2346), .B(n5643), .Y(n4926) );
NAND2X1TS U5956 ( .A(n6588), .B(n6572), .Y(n4924) );
OAI21X1TS U5957 ( .A0(n4925), .A1(n4926), .B0(n4426), .Y(n4429) );
NAND2X1TS U5958 ( .A(n4428), .B(n4427), .Y(intadd_513_B_7_) );
OAI2BB2XLTS U5959 ( .B0(intadd_513_B_7_), .B1(n4430), .A0N(n4429), .A1N(
n4428), .Y(intadd_513_B_6_) );
INVX2TS U5960 ( .A(n2488), .Y(n5646) );
NOR2X2TS U5961 ( .A(n6588), .B(n5646), .Y(n4562) );
NOR2X2TS U5962 ( .A(n5642), .B(n2289), .Y(n4564) );
OR2X2TS U5963 ( .A(n4562), .B(n4564), .Y(n4439) );
NAND2X1TS U5964 ( .A(n5642), .B(n2289), .Y(n4565) );
NOR2X1TS U5965 ( .A(n2303), .B(n5541), .Y(n4445) );
INVX2TS U5966 ( .A(n4562), .Y(n4440) );
NAND2X1TS U5967 ( .A(n4440), .B(n4561), .Y(n4441) );
INVX2TS U5968 ( .A(n4442), .Y(n5534) );
OAI22X1TS U5969 ( .A0(n2320), .A1(n5536), .B0(n5548), .B1(n5534), .Y(n4444)
);
OAI22X1TS U5970 ( .A0(n5548), .A1(n5536), .B0(n2314), .B1(n5534), .Y(n4560)
);
CMPR32X2TS U5971 ( .A(n4445), .B(n4444), .C(n4443), .CO(
DP_OP_502J223_128_4510_n106), .S(DP_OP_502J223_128_4510_n107) );
INVX2TS U5972 ( .A(n4454), .Y(n4446) );
NAND2X1TS U5973 ( .A(n4446), .B(n4453), .Y(n4447) );
INVX2TS U5974 ( .A(n4450), .Y(n4451) );
NOR2X1TS U5975 ( .A(n4451), .B(n4454), .Y(n4458) );
AO21X4TS U5976 ( .A0(n4458), .A1(n4457), .B0(n4456), .Y(n4462) );
INVX2TS U5977 ( .A(n4459), .Y(n4461) );
XOR2X4TS U5978 ( .A(n4462), .B(n2427), .Y(n4463) );
XOR2X1TS U5979 ( .A(n6567), .B(n2383), .Y(n4467) );
INVX2TS U5980 ( .A(n4464), .Y(n4465) );
AOI21X1TS U5981 ( .A0(n4975), .A1(n4465), .B0(n4468), .Y(n4466) );
OAI2BB2XLTS U5982 ( .B0(n6022), .B1(n2451), .A0N(
FPADDSUB_exp_rslt_NRM2_EW1[7]), .A1N(n6017), .Y(n1466) );
NAND2X2TS U5983 ( .A(n5999), .B(n6624), .Y(n5998) );
INVX2TS U5984 ( .A(n5998), .Y(n6006) );
OA22X1TS U5985 ( .A0(n4472), .A1(n4471), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(n1205) );
INVX2TS U5986 ( .A(n5454), .Y(n4473) );
BUFX3TS U5987 ( .A(n6444), .Y(n6459) );
OR2X1TS U5988 ( .A(FPSENCOS_d_ff3_LUT_out[27]), .B(n6459), .Y(n2113) );
NOR2X1TS U5989 ( .A(n2221), .B(n7062), .Y(n7064) );
NAND2X1TS U5990 ( .A(FPMULT_Op_MX[5]), .B(n2289), .Y(intadd_514_A_7_) );
NOR2X1TS U5991 ( .A(n2261), .B(n2484), .Y(n7066) );
NAND2X1TS U5992 ( .A(n5648), .B(n2344), .Y(intadd_512_A_7_) );
INVX2TS U5993 ( .A(n5671), .Y(n4474) );
INVX2TS U5994 ( .A(n6585), .Y(n4968) );
NOR2X1TS U5995 ( .A(n2491), .B(n4968), .Y(n5672) );
NAND2X2TS U5996 ( .A(FPMULT_Op_MX[19]), .B(n6753), .Y(n5445) );
NAND2X1TS U5997 ( .A(n5640), .B(n5647), .Y(n4938) );
NOR2X1TS U5998 ( .A(n5445), .B(n4938), .Y(n4937) );
NAND2X1TS U5999 ( .A(n2292), .B(n6753), .Y(n4476) );
NAND2X1TS U6000 ( .A(n6567), .B(n2291), .Y(n4475) );
NOR2X2TS U6001 ( .A(n4476), .B(n4475), .Y(n4956) );
NOR3X2TS U6002 ( .A(n4476), .B(n2217), .C(n2478), .Y(n5651) );
NAND2X1TS U6003 ( .A(FPMULT_Op_MX[18]), .B(n2223), .Y(n4948) );
NAND2X1TS U6004 ( .A(n6585), .B(FPMULT_Op_MX[19]), .Y(n4947) );
XNOR2X1TS U6005 ( .A(n4948), .B(n4947), .Y(n4477) );
NAND2X2TS U6006 ( .A(n6595), .B(FPMULT_Op_MX[20]), .Y(n4973) );
INVX2TS U6007 ( .A(n4973), .Y(n4971) );
XOR2X1TS U6008 ( .A(n4477), .B(n4971), .Y(n5653) );
OAI2BB2XLTS U6009 ( .B0(n4478), .B1(n5653), .A0N(n5651), .A1N(n5652), .Y(
mult_x_309_n36) );
OA22X1TS U6010 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[1]), .B0(n6730),
.B1(result_add_subt[24]), .Y(n1472) );
OA22X1TS U6011 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(n6730),
.B1(result_add_subt[23]), .Y(n1473) );
OAI22X1TS U6012 ( .A0(n6001), .A1(n2263), .B0(n2418), .B1(n5966), .Y(n4481)
);
AOI211X1TS U6013 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n2343), .B0(n4482),
.C0(n4481), .Y(n5990) );
OAI22X1TS U6014 ( .A0(n5989), .A1(n5954), .B0(n5990), .B1(n5984), .Y(n6653)
);
BUFX3TS U6015 ( .A(n5937), .Y(n5962) );
OA22X1TS U6016 ( .A0(n6653), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n1187) );
NOR3BX1TS U6017 ( .AN(n2364), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]),
.C(n6797), .Y(n4484) );
BUFX3TS U6018 ( .A(n4486), .Y(n6986) );
BUFX3TS U6019 ( .A(n7014), .Y(n6999) );
BUFX3TS U6020 ( .A(n4490), .Y(n6974) );
BUFX3TS U6021 ( .A(n4486), .Y(n6985) );
BUFX3TS U6022 ( .A(n4486), .Y(n6983) );
BUFX3TS U6023 ( .A(n4492), .Y(n6996) );
BUFX3TS U6024 ( .A(n4486), .Y(n6982) );
BUFX3TS U6025 ( .A(n7014), .Y(n7001) );
BUFX3TS U6026 ( .A(n4492), .Y(n6995) );
BUFX3TS U6027 ( .A(n4487), .Y(n6981) );
BUFX3TS U6028 ( .A(n4498), .Y(n7000) );
BUFX3TS U6029 ( .A(n4492), .Y(n6994) );
BUFX3TS U6030 ( .A(n4497), .Y(n6993) );
BUFX3TS U6031 ( .A(n4486), .Y(n6966) );
BUFX3TS U6032 ( .A(n4491), .Y(n7013) );
BUFX3TS U6033 ( .A(n4486), .Y(n6984) );
BUFX3TS U6034 ( .A(n4491), .Y(n7014) );
CLKBUFX2TS U6035 ( .A(n4489), .Y(n4488) );
BUFX3TS U6036 ( .A(n4494), .Y(n7048) );
BUFX3TS U6037 ( .A(n4494), .Y(n7051) );
BUFX3TS U6038 ( .A(n4494), .Y(n7052) );
BUFX3TS U6039 ( .A(n4488), .Y(n7056) );
BUFX3TS U6040 ( .A(n4486), .Y(n6987) );
BUFX3TS U6041 ( .A(n4491), .Y(n7019) );
BUFX3TS U6042 ( .A(n4490), .Y(n6972) );
BUFX3TS U6043 ( .A(n4492), .Y(n6971) );
BUFX3TS U6044 ( .A(n4492), .Y(n6998) );
BUFX3TS U6045 ( .A(n4490), .Y(n6970) );
CLKBUFX2TS U6046 ( .A(n4491), .Y(n7042) );
BUFX3TS U6047 ( .A(n7028), .Y(n7018) );
BUFX3TS U6048 ( .A(n4486), .Y(n6973) );
BUFX3TS U6049 ( .A(n4497), .Y(n6969) );
BUFX3TS U6050 ( .A(n4496), .Y(n7017) );
BUFX3TS U6051 ( .A(n4488), .Y(n7044) );
CLKBUFX2TS U6052 ( .A(n4491), .Y(n4495) );
BUFX3TS U6053 ( .A(n4498), .Y(n7016) );
BUFX3TS U6054 ( .A(n4488), .Y(n7045) );
BUFX3TS U6055 ( .A(n4498), .Y(n7015) );
BUFX3TS U6056 ( .A(n4488), .Y(n7057) );
BUFX3TS U6057 ( .A(n4498), .Y(n7002) );
BUFX3TS U6058 ( .A(n4492), .Y(n6968) );
BUFX3TS U6059 ( .A(n4487), .Y(n6967) );
BUFX3TS U6060 ( .A(n4494), .Y(n7046) );
BUFX3TS U6061 ( .A(n4488), .Y(n7047) );
BUFX3TS U6062 ( .A(n4497), .Y(n6989) );
BUFX3TS U6063 ( .A(n4489), .Y(n7049) );
BUFX3TS U6064 ( .A(n7050), .Y(n7043) );
BUFX3TS U6065 ( .A(n4487), .Y(n6976) );
BUFX3TS U6066 ( .A(n4487), .Y(n6977) );
BUFX3TS U6067 ( .A(n4487), .Y(n6979) );
BUFX3TS U6068 ( .A(n4487), .Y(n6980) );
BUFX3TS U6069 ( .A(n4487), .Y(n6975) );
BUFX3TS U6070 ( .A(n4487), .Y(n6978) );
BUFX3TS U6071 ( .A(n4496), .Y(n7033) );
BUFX3TS U6072 ( .A(n4496), .Y(n7032) );
BUFX3TS U6073 ( .A(n4489), .Y(n7055) );
BUFX3TS U6074 ( .A(n7019), .Y(n7031) );
BUFX3TS U6075 ( .A(n4488), .Y(n7054) );
BUFX3TS U6076 ( .A(n4489), .Y(n7053) );
BUFX3TS U6077 ( .A(n4494), .Y(n7050) );
CLKBUFX3TS U6078 ( .A(n4491), .Y(n7011) );
CLKBUFX2TS U6079 ( .A(n4491), .Y(n4493) );
BUFX3TS U6080 ( .A(n4490), .Y(n6961) );
BUFX3TS U6081 ( .A(n7011), .Y(n7025) );
BUFX3TS U6082 ( .A(n4492), .Y(n6997) );
BUFX3TS U6083 ( .A(n4497), .Y(n6990) );
BUFX3TS U6084 ( .A(n4498), .Y(n7024) );
BUFX3TS U6085 ( .A(n4496), .Y(n7023) );
BUFX3TS U6086 ( .A(n4496), .Y(n7022) );
CLKBUFX2TS U6087 ( .A(n7041), .Y(n7027) );
BUFX3TS U6088 ( .A(n7010), .Y(n7021) );
BUFX3TS U6089 ( .A(n7041), .Y(n7020) );
CLKBUFX3TS U6090 ( .A(n4498), .Y(n7040) );
BUFX3TS U6091 ( .A(n7011), .Y(n7039) );
BUFX3TS U6092 ( .A(n7010), .Y(n7038) );
BUFX3TS U6093 ( .A(n7011), .Y(n7037) );
BUFX3TS U6094 ( .A(n4497), .Y(n6959) );
BUFX3TS U6095 ( .A(n4496), .Y(n7036) );
BUFX3TS U6096 ( .A(n7010), .Y(n7035) );
BUFX3TS U6097 ( .A(n4492), .Y(n6960) );
BUFX3TS U6098 ( .A(n4498), .Y(n7026) );
BUFX3TS U6099 ( .A(n4497), .Y(n6988) );
BUFX3TS U6100 ( .A(n7028), .Y(n7009) );
BUFX3TS U6101 ( .A(n7010), .Y(n7008) );
BUFX3TS U6102 ( .A(n4494), .Y(n7058) );
BUFX3TS U6103 ( .A(n4490), .Y(n6963) );
BUFX3TS U6104 ( .A(n7013), .Y(n7006) );
BUFX3TS U6105 ( .A(n4498), .Y(n7005) );
BUFX3TS U6106 ( .A(n4486), .Y(n6964) );
BUFX3TS U6107 ( .A(n4496), .Y(n7004) );
BUFX3TS U6108 ( .A(n4487), .Y(n6965) );
BUFX3TS U6109 ( .A(n4497), .Y(n6992) );
BUFX3TS U6110 ( .A(n7011), .Y(n7003) );
BUFX3TS U6111 ( .A(n4497), .Y(n6991) );
BUFX3TS U6112 ( .A(n7028), .Y(n7007) );
BUFX3TS U6113 ( .A(n7019), .Y(n7030) );
BUFX3TS U6114 ( .A(n7010), .Y(n7034) );
BUFX3TS U6115 ( .A(n4497), .Y(n6962) );
BUFX3TS U6116 ( .A(n7011), .Y(n7029) );
BUFX3TS U6117 ( .A(n6852), .Y(n6625) );
OAI2BB2XLTS U6118 ( .B0(n6852), .B1(n6763), .A0N(n6625), .A1N(
FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1457) );
XNOR2X1TS U6119 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n6798), .Y(n4501) );
BUFX3TS U6120 ( .A(n4499), .Y(n6233) );
AOI22X1TS U6121 ( .A0(n6233), .A1(FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n6232), .Y(n4500) );
OAI2BB1X1TS U6122 ( .A0N(n6024), .A1N(n4501), .B0(n4500), .Y(n1348) );
INVX2TS U6123 ( .A(n4503), .Y(n4505) );
NAND2X1TS U6124 ( .A(n4505), .B(n4504), .Y(n4507) );
INVX2TS U6125 ( .A(n4507), .Y(n4506) );
XOR2X1TS U6126 ( .A(n4507), .B(n4511), .Y(n4508) );
AOI22X1TS U6127 ( .A0(n4508), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n6232), .Y(n4509) );
OAI2BB1X1TS U6128 ( .A0N(n6024), .A1N(n4510), .B0(n4509), .Y(n1346) );
OR2X1TS U6129 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n4512) );
CLKAND2X2TS U6130 ( .A(n4512), .B(n4511), .Y(n4514) );
AOI22X1TS U6131 ( .A0(n4514), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.B1(n6232), .Y(n4515) );
OAI2BB1X1TS U6132 ( .A0N(n6024), .A1N(n4516), .B0(n4515), .Y(n1347) );
INVX2TS U6133 ( .A(n4534), .Y(n4520) );
NAND2X1TS U6134 ( .A(n4520), .B(n4533), .Y(n4524) );
INVX2TS U6135 ( .A(n4524), .Y(n4521) );
XNOR2X1TS U6136 ( .A(n4522), .B(n4521), .Y(n4527) );
INVX2TS U6137 ( .A(n4523), .Y(n4535) );
XOR2X1TS U6138 ( .A(n4535), .B(n4524), .Y(n4525) );
AOI22X1TS U6139 ( .A0(n4525), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.B1(n6232), .Y(n4526) );
OAI2BB1X1TS U6140 ( .A0N(n6024), .A1N(n4527), .B0(n4526), .Y(n1345) );
INVX2TS U6141 ( .A(n4528), .Y(n6225) );
INVX2TS U6142 ( .A(n4529), .Y(n4531) );
NAND2X1TS U6143 ( .A(n4531), .B(n4530), .Y(n4536) );
INVX2TS U6144 ( .A(n4536), .Y(n4532) );
XNOR2X1TS U6145 ( .A(n6225), .B(n4532), .Y(n4540) );
XNOR2X1TS U6146 ( .A(n4537), .B(n4536), .Y(n4538) );
AOI22X1TS U6147 ( .A0(n4538), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.B1(n6232), .Y(n4539) );
OAI2BB1X1TS U6148 ( .A0N(n6024), .A1N(n4540), .B0(n4539), .Y(n1344) );
BUFX3TS U6149 ( .A(n5937), .Y(n6710) );
OAI2BB2XLTS U6150 ( .B0(n6449), .B1(n2415), .A0N(n6444), .A1N(
intadd_517_SUM_0_), .Y(n1852) );
NAND3X1TS U6151 ( .A(n6802), .B(FPSENCOS_cont_var_out[0]), .C(ready_add_subt), .Y(n6385) );
BUFX3TS U6152 ( .A(n6385), .Y(n6535) );
BUFX3TS U6153 ( .A(n6385), .Y(n6387) );
OAI2BB2XLTS U6154 ( .B0(n6535), .B1(n6540), .A0N(n6387), .A1N(
FPSENCOS_d_ff_Yn[29]), .Y(n1767) );
NOR4X1TS U6155 ( .A(FPMULT_P_Sgf[13]), .B(FPMULT_P_Sgf[17]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[16]), .Y(n4549) );
NOR4X1TS U6156 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_P_Sgf[5]), .C(
FPMULT_P_Sgf[3]), .D(FPMULT_P_Sgf[4]), .Y(n4544) );
NOR3XLTS U6157 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[0]), .C(
FPMULT_P_Sgf[2]), .Y(n4543) );
NOR4X1TS U6158 ( .A(FPMULT_P_Sgf[9]), .B(FPMULT_P_Sgf[10]), .C(
FPMULT_P_Sgf[14]), .D(FPMULT_P_Sgf[12]), .Y(n4542) );
AND4X1TS U6159 ( .A(n4544), .B(n4543), .C(n4542), .D(n4541), .Y(n4547) );
XOR2X1TS U6160 ( .A(FPMULT_Op_MY[31]), .B(FPMULT_Op_MX[31]), .Y(n6610) );
MXI2X1TS U6161 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n6610), .Y(n4545) );
AOI31X1TS U6162 ( .A0(n4549), .A1(n4548), .A2(n4547), .B0(n4546), .Y(n5451)
);
INVX2TS U6163 ( .A(n4551), .Y(n1528) );
BUFX3TS U6164 ( .A(n6387), .Y(n6393) );
OAI2BB2XLTS U6165 ( .B0(n6448), .B1(n2441), .A0N(n6448), .A1N(
intadd_517_SUM_1_), .Y(n1851) );
NAND3X2TS U6166 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n4552),
.C(n4671), .Y(n6346) );
NOR3BX2TS U6167 ( .AN(n6346), .B(n2298), .C(ready_add_subt), .Y(n6360) );
BUFX3TS U6168 ( .A(n6444), .Y(n6471) );
INVX2TS U6169 ( .A(n6449), .Y(n6544) );
NAND2X1TS U6170 ( .A(n6455), .B(n6783), .Y(intadd_518_CI) );
NOR2X2TS U6171 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_518_n1), .Y(n6433) );
NAND2X1TS U6172 ( .A(n6433), .B(n6838), .Y(n6436) );
NOR2X1TS U6173 ( .A(n2420), .B(n6765), .Y(n7065) );
BUFX3TS U6174 ( .A(n6414), .Y(n6427) );
OAI2BB2XLTS U6175 ( .B0(n6783), .B1(n6415), .A0N(FPSENCOS_d_ff_Xn[23]),
.A1N(n6427), .Y(n1959) );
OAI2BB2XLTS U6176 ( .B0(n6841), .B1(n6415), .A0N(FPSENCOS_d_ff_Yn[28]),
.A1N(n6427), .Y(n1856) );
OAI2BB2XLTS U6177 ( .B0(n6851), .B1(n6415), .A0N(FPSENCOS_d_ff_Xn[30]),
.A1N(n6427), .Y(n1952) );
OAI22X1TS U6178 ( .A0(n2320), .A1(n5538), .B0(n5548), .B1(n5537), .Y(n4571)
);
ADDHX1TS U6179 ( .A(n4560), .B(n4559), .CO(n4443), .S(n4570) );
INVX2TS U6180 ( .A(n4564), .Y(n4566) );
NAND2X1TS U6181 ( .A(n4566), .B(n4565), .Y(n4567) );
CLKXOR2X4TS U6182 ( .A(n4568), .B(n4567), .Y(n5546) );
OAI22X1TS U6183 ( .A0(n5546), .A1(n5540), .B0(n2321), .B1(n5539), .Y(n4569)
);
INVX2TS U6184 ( .A(n4573), .Y(n5622) );
INVX2TS U6185 ( .A(n4574), .Y(n5458) );
OR2X2TS U6186 ( .A(n5458), .B(n5454), .Y(n5876) );
NAND2X1TS U6187 ( .A(n5876), .B(FPMULT_Add_result[0]), .Y(n4575) );
NAND2X1TS U6188 ( .A(n6848), .B(n6763), .Y(intadd_516_CI) );
NOR3X1TS U6189 ( .A(n6757), .B(n6787), .C(FPMULT_FS_Module_state_reg[2]),
.Y(n6023) );
NAND2X1TS U6190 ( .A(n6023), .B(n6790), .Y(n6605) );
INVX2TS U6191 ( .A(n6605), .Y(n6020) );
INVX2TS U6192 ( .A(n5876), .Y(n5931) );
INVX2TS U6193 ( .A(n6564), .Y(n5460) );
OAI31X1TS U6194 ( .A0(n6020), .A1(n5899), .A2(n6784), .B0(n4576), .Y(n1622)
);
AOI211X1TS U6195 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4576), .B0(n6020),
.C0(n5873), .Y(n4577) );
INVX2TS U6196 ( .A(n4577), .Y(n1623) );
INVX2TS U6197 ( .A(intadd_514_SUM_0_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
INVX2TS U6198 ( .A(intadd_512_SUM_0_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
INVX2TS U6199 ( .A(n6923), .Y(n6922) );
INVX2TS U6200 ( .A(intadd_514_SUM_1_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
INVX2TS U6201 ( .A(intadd_512_SUM_1_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
BUFX3TS U6202 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n6713) );
INVX2TS U6203 ( .A(n2359), .Y(n5450) );
INVX2TS U6204 ( .A(intadd_514_SUM_2_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
INVX2TS U6205 ( .A(intadd_512_SUM_2_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
NAND2X1TS U6206 ( .A(n6757), .B(n6751), .Y(n5455) );
AOI21X1TS U6207 ( .A0(n2382), .A1(n6904), .B0(n4580), .Y(n4583) );
INVX2TS U6208 ( .A(n4581), .Y(n5457) );
AOI21X1TS U6209 ( .A0(begin_operation), .A1(n4666), .B0(n4494), .Y(n4582) );
INVX2TS U6210 ( .A(intadd_514_SUM_3_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
INVX2TS U6211 ( .A(intadd_512_SUM_3_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
NOR2X1TS U6212 ( .A(n5326), .B(FPADDSUB_ADD_OVRFLW_NRM), .Y(n5273) );
NAND2X1TS U6213 ( .A(n5452), .B(n5460), .Y(n4584) );
NAND2X1TS U6214 ( .A(n4588), .B(FPMULT_FSM_selector_C), .Y(n4585) );
OR2X2TS U6215 ( .A(n6260), .B(n4585), .Y(n4651) );
INVX2TS U6216 ( .A(n4651), .Y(n4621) );
BUFX3TS U6217 ( .A(n4595), .Y(n4648) );
NOR3X1TS U6218 ( .A(n6260), .B(n1575), .C(n4646), .Y(n4587) );
INVX2TS U6219 ( .A(intadd_514_SUM_4_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
INVX2TS U6220 ( .A(intadd_512_SUM_4_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
INVX2TS U6221 ( .A(n4589), .Y(n4609) );
AND2X2TS U6222 ( .A(n6260), .B(n4590), .Y(n4610) );
CLKBUFX2TS U6223 ( .A(n4610), .Y(n4602) );
AOI22X1TS U6224 ( .A0(n4637), .A1(n1561), .B0(n4602), .B1(FPMULT_P_Sgf[33]),
.Y(n4592) );
INVX2TS U6225 ( .A(n4651), .Y(n4642) );
BUFX3TS U6226 ( .A(n4595), .Y(n4638) );
AOI22X1TS U6227 ( .A0(n4632), .A1(FPMULT_Add_result[9]), .B0(
FPMULT_Sgf_normalized_result[9]), .B1(n4638), .Y(n4591) );
AOI22X1TS U6228 ( .A0(n4641), .A1(FPMULT_P_Sgf[26]), .B0(n4602), .B1(
FPMULT_P_Sgf[27]), .Y(n4594) );
AOI22X1TS U6229 ( .A0(n4642), .A1(FPMULT_Add_result[3]), .B0(
FPMULT_Sgf_normalized_result[3]), .B1(n4638), .Y(n4593) );
INVX2TS U6230 ( .A(n4609), .Y(n4641) );
AOI22X1TS U6231 ( .A0(n4641), .A1(n1570), .B0(n4602), .B1(n1571), .Y(n4597)
);
INVX2TS U6232 ( .A(n4651), .Y(n4632) );
AOI22X1TS U6233 ( .A0(n4632), .A1(FPMULT_Add_result[18]), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n4595), .Y(n4596) );
AOI22X1TS U6234 ( .A0(n4589), .A1(FPMULT_P_Sgf[24]), .B0(n4602), .B1(
FPMULT_P_Sgf[25]), .Y(n4599) );
AOI22X1TS U6235 ( .A0(n4642), .A1(FPMULT_Add_result[1]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n4638), .Y(n4598) );
AOI22X1TS U6236 ( .A0(n4589), .A1(FPMULT_P_Sgf[34]), .B0(n4602), .B1(
FPMULT_P_Sgf[35]), .Y(n4601) );
AOI22X1TS U6237 ( .A0(n4621), .A1(FPMULT_Add_result[11]), .B0(
FPMULT_Sgf_normalized_result[11]), .B1(n4595), .Y(n4600) );
AOI22X1TS U6238 ( .A0(n4637), .A1(FPMULT_P_Sgf[30]), .B0(n4602), .B1(
FPMULT_P_Sgf[31]), .Y(n4604) );
AOI22X1TS U6239 ( .A0(n4621), .A1(FPMULT_Add_result[7]), .B0(
FPMULT_Sgf_normalized_result[7]), .B1(n4638), .Y(n4603) );
AOI22X1TS U6240 ( .A0(n4637), .A1(n1566), .B0(n4610), .B1(n1567), .Y(n4606)
);
AOI22X1TS U6241 ( .A0(n4642), .A1(FPMULT_Add_result[14]), .B0(
FPMULT_Sgf_normalized_result[14]), .B1(n4595), .Y(n4605) );
AOI22X1TS U6242 ( .A0(n4641), .A1(n1571), .B0(n4610), .B1(n1572), .Y(n4608)
);
AOI22X1TS U6243 ( .A0(n4621), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_Sgf_normalized_result[19]), .B1(n4648), .Y(n4607) );
INVX2TS U6244 ( .A(n4609), .Y(n4637) );
BUFX3TS U6245 ( .A(n4610), .Y(n4645) );
AOI22X1TS U6246 ( .A0(n4641), .A1(n1565), .B0(n4645), .B1(n1566), .Y(n4612)
);
AOI22X1TS U6247 ( .A0(n4632), .A1(FPMULT_Add_result[13]), .B0(
FPMULT_Sgf_normalized_result[13]), .B1(n4595), .Y(n4611) );
AOI22X1TS U6248 ( .A0(n4637), .A1(n1567), .B0(n4645), .B1(n1568), .Y(n4614)
);
AOI22X1TS U6249 ( .A0(n4642), .A1(FPMULT_Add_result[15]), .B0(
FPMULT_Sgf_normalized_result[15]), .B1(n4595), .Y(n4613) );
AOI22X1TS U6250 ( .A0(n4637), .A1(n1572), .B0(n4645), .B1(n1573), .Y(n4616)
);
AOI22X1TS U6251 ( .A0(n4632), .A1(FPMULT_Add_result[20]), .B0(
FPMULT_Sgf_normalized_result[20]), .B1(n4648), .Y(n4615) );
AOI22X1TS U6252 ( .A0(n4637), .A1(n1568), .B0(n4645), .B1(n1569), .Y(n4618)
);
AOI22X1TS U6253 ( .A0(n4621), .A1(FPMULT_Add_result[16]), .B0(
FPMULT_Sgf_normalized_result[16]), .B1(n4648), .Y(n4617) );
AOI22X1TS U6254 ( .A0(n4641), .A1(n1569), .B0(n4645), .B1(n1570), .Y(n4620)
);
AOI22X1TS U6255 ( .A0(n4632), .A1(FPMULT_Add_result[17]), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n4595), .Y(n4619) );
AOI22X1TS U6256 ( .A0(n4641), .A1(n1573), .B0(n1574), .B1(n4610), .Y(n4623)
);
AOI22X1TS U6257 ( .A0(n4621), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Sgf_normalized_result[21]), .B1(n4648), .Y(n4622) );
AOI22X1TS U6258 ( .A0(n4637), .A1(FPMULT_P_Sgf[25]), .B0(n4610), .B1(
FPMULT_P_Sgf[26]), .Y(n4625) );
AOI22X1TS U6259 ( .A0(n4632), .A1(FPMULT_Add_result[2]), .B0(
FPMULT_Sgf_normalized_result[2]), .B1(n4638), .Y(n4624) );
AOI22X1TS U6260 ( .A0(n4641), .A1(FPMULT_P_Sgf[27]), .B0(n4610), .B1(
FPMULT_P_Sgf[28]), .Y(n4627) );
AOI22X1TS U6261 ( .A0(n4621), .A1(FPMULT_Add_result[4]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n4638), .Y(n4626) );
AOI22X1TS U6262 ( .A0(n4637), .A1(FPMULT_P_Sgf[35]), .B0(n4645), .B1(n1565),
.Y(n4629) );
AOI22X1TS U6263 ( .A0(n4642), .A1(FPMULT_Add_result[12]), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n4648), .Y(n4628) );
AOI22X1TS U6264 ( .A0(n4641), .A1(FPMULT_P_Sgf[29]), .B0(n4645), .B1(
FPMULT_P_Sgf[30]), .Y(n4631) );
AOI22X1TS U6265 ( .A0(n4632), .A1(FPMULT_Add_result[6]), .B0(
FPMULT_Sgf_normalized_result[6]), .B1(n4638), .Y(n4630) );
AOI22X1TS U6266 ( .A0(n4589), .A1(FPMULT_P_Sgf[33]), .B0(n4610), .B1(
FPMULT_P_Sgf[34]), .Y(n4634) );
AOI22X1TS U6267 ( .A0(n4621), .A1(FPMULT_Add_result[10]), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n4638), .Y(n4633) );
AOI22X1TS U6268 ( .A0(n4637), .A1(FPMULT_P_Sgf[31]), .B0(n4610), .B1(n1561),
.Y(n4636) );
AOI22X1TS U6269 ( .A0(n4642), .A1(FPMULT_Add_result[8]), .B0(
FPMULT_Sgf_normalized_result[8]), .B1(n4638), .Y(n4635) );
AOI22X1TS U6270 ( .A0(FPMULT_P_Sgf[23]), .A1(n4589), .B0(n4645), .B1(
FPMULT_P_Sgf[24]), .Y(n4640) );
AOI22X1TS U6271 ( .A0(n4632), .A1(FPMULT_Add_result[0]), .B0(
FPMULT_Sgf_normalized_result[0]), .B1(n4638), .Y(n4639) );
AOI22X1TS U6272 ( .A0(n4641), .A1(FPMULT_P_Sgf[28]), .B0(n4645), .B1(
FPMULT_P_Sgf[29]), .Y(n4644) );
AOI22X1TS U6273 ( .A0(n4642), .A1(FPMULT_Add_result[5]), .B0(
FPMULT_Sgf_normalized_result[5]), .B1(n4595), .Y(n4643) );
AOI22X1TS U6274 ( .A0(n4645), .A1(n1575), .B0(n2227), .B1(
FPMULT_Add_result[23]), .Y(n4650) );
NOR3BX1TS U6275 ( .AN(n1574), .B(n6260), .C(n4646), .Y(n4647) );
AOI21X1TS U6276 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4648), .B0(
n4647), .Y(n4649) );
INVX2TS U6277 ( .A(n4994), .Y(n4668) );
NOR2X4TS U6278 ( .A(operation[2]), .B(n6342), .Y(n4674) );
AOI22X1TS U6279 ( .A0(n4674), .A1(cordic_result[9]), .B0(n4707), .B1(
mult_result[9]), .Y(n4652) );
AOI22X1TS U6280 ( .A0(cordic_result[6]), .A1(n4674), .B0(n4707), .B1(
mult_result[6]), .Y(n4653) );
AOI22X1TS U6281 ( .A0(n4674), .A1(cordic_result[7]), .B0(n4707), .B1(
mult_result[7]), .Y(n4654) );
AOI22X1TS U6282 ( .A0(n4674), .A1(cordic_result[5]), .B0(n4707), .B1(
mult_result[5]), .Y(n4655) );
INVX2TS U6283 ( .A(result_add_subt[11]), .Y(n6662) );
AOI22X1TS U6284 ( .A0(n4674), .A1(cordic_result[11]), .B0(n4707), .B1(
mult_result[11]), .Y(n4656) );
INVX2TS U6285 ( .A(n4994), .Y(n4685) );
INVX2TS U6286 ( .A(n4581), .Y(n4683) );
AOI22X1TS U6287 ( .A0(cordic_result[24]), .A1(n4674), .B0(n5457), .B1(
mult_result[24]), .Y(n4657) );
AOI22X1TS U6288 ( .A0(n4674), .A1(cordic_result[10]), .B0(n4683), .B1(
mult_result[10]), .Y(n4658) );
INVX2TS U6289 ( .A(result_add_subt[8]), .Y(n6659) );
AOI22X1TS U6290 ( .A0(n4674), .A1(cordic_result[8]), .B0(n5457), .B1(
mult_result[8]), .Y(n4659) );
NOR2XLTS U6291 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n4660) );
NOR3BX1TS U6292 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n4661), .Y(n6339) );
NOR3BX1TS U6293 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(n4661), .Y(n6343) );
BUFX3TS U6294 ( .A(n6382), .Y(n6379) );
INVX2TS U6295 ( .A(n6379), .Y(n6384) );
AOI32X1TS U6296 ( .A0(n6379), .A1(operation[0]), .A2(operation[1]), .B0(
FPSENCOS_d_ff1_operation_out), .B1(n6384), .Y(n4662) );
INVX2TS U6297 ( .A(n4662), .Y(n2080) );
INVX2TS U6298 ( .A(n6915), .Y(busy) );
INVX2TS U6299 ( .A(intadd_514_SUM_5_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
CLKBUFX2TS U6300 ( .A(n4674), .Y(n4672) );
AOI22X1TS U6301 ( .A0(cordic_result[4]), .A1(n4672), .B0(n4707), .B1(
mult_result[4]), .Y(n4663) );
AOI22X1TS U6302 ( .A0(n4672), .A1(cordic_result[2]), .B0(n4707), .B1(
mult_result[2]), .Y(n4664) );
INVX2TS U6303 ( .A(n4994), .Y(n4670) );
AOI22X1TS U6304 ( .A0(cordic_result[1]), .A1(n4672), .B0(n5457), .B1(
mult_result[1]), .Y(n4665) );
AOI22X1TS U6305 ( .A0(n4672), .A1(cordic_result[3]), .B0(n4707), .B1(
mult_result[3]), .Y(n4667) );
AOI22X1TS U6306 ( .A0(n4672), .A1(cordic_result[0]), .B0(n4683), .B1(
mult_result[0]), .Y(n4669) );
INVX2TS U6307 ( .A(intadd_512_SUM_5_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
NOR2X1TS U6308 ( .A(n6751), .B(n6790), .Y(n5453) );
AOI22X1TS U6309 ( .A0(n4994), .A1(ready_add_subt), .B0(n6337), .B1(n4672),
.Y(n4673) );
INVX2TS U6310 ( .A(result_add_subt[31]), .Y(n6554) );
AOI22X1TS U6311 ( .A0(cordic_result[31]), .A1(n4697), .B0(n4666), .B1(
mult_result[31]), .Y(n4675) );
AOI22X1TS U6312 ( .A0(cordic_result[26]), .A1(n4697), .B0(n4683), .B1(
mult_result[26]), .Y(n4676) );
INVX2TS U6313 ( .A(result_add_subt[22]), .Y(n6631) );
AOI22X1TS U6314 ( .A0(cordic_result[22]), .A1(n4697), .B0(n5457), .B1(
mult_result[22]), .Y(n4677) );
AOI22X1TS U6315 ( .A0(cordic_result[29]), .A1(n4697), .B0(n4666), .B1(
mult_result[29]), .Y(n4678) );
AOI22X1TS U6316 ( .A0(cordic_result[25]), .A1(n4697), .B0(n4683), .B1(
mult_result[25]), .Y(n4679) );
AOI22X1TS U6317 ( .A0(cordic_result[28]), .A1(n4697), .B0(n5457), .B1(
mult_result[28]), .Y(n4680) );
AOI22X1TS U6318 ( .A0(cordic_result[23]), .A1(n4697), .B0(n4666), .B1(
mult_result[23]), .Y(n4681) );
AOI22X1TS U6319 ( .A0(cordic_result[27]), .A1(n4697), .B0(n4683), .B1(
mult_result[27]), .Y(n4682) );
AOI22X1TS U6320 ( .A0(cordic_result[30]), .A1(n4697), .B0(n4666), .B1(
mult_result[30]), .Y(n4684) );
NOR2X2TS U6321 ( .A(n6367), .B(FPSENCOS_cont_iter_out[1]), .Y(n4990) );
AOI22X1TS U6322 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n6456), .B0(n6372),
.B1(n4990), .Y(n4686) );
INVX2TS U6323 ( .A(n4808), .Y(n4687) );
NAND2X2TS U6324 ( .A(n5207), .B(n2256), .Y(n4806) );
NOR2X1TS U6325 ( .A(FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4807) );
NOR2X1TS U6326 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n4689) );
NOR2BX1TS U6327 ( .AN(n5208), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n4688)
);
INVX2TS U6328 ( .A(n4753), .Y(n5217) );
NAND2X1TS U6329 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n5210), .Y(n4816) );
NAND2X1TS U6330 ( .A(n6796), .B(n6760), .Y(n5230) );
NOR2BX1TS U6331 ( .AN(n4816), .B(n4693), .Y(n4696) );
NAND2X1TS U6332 ( .A(n5326), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n4695)
);
INVX2TS U6333 ( .A(intadd_514_SUM_6_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
INVX2TS U6334 ( .A(n4994), .Y(n4710) );
INVX2TS U6335 ( .A(n4581), .Y(n4707) );
AOI22X1TS U6336 ( .A0(cordic_result[12]), .A1(n4708), .B0(n4666), .B1(
mult_result[12]), .Y(n4698) );
INVX2TS U6337 ( .A(result_add_subt[21]), .Y(n6641) );
AOI22X1TS U6338 ( .A0(cordic_result[21]), .A1(n4708), .B0(n4666), .B1(
mult_result[21]), .Y(n4699) );
INVX2TS U6339 ( .A(result_add_subt[20]), .Y(n6647) );
AOI22X1TS U6340 ( .A0(n4708), .A1(cordic_result[20]), .B0(n4683), .B1(
mult_result[20]), .Y(n4700) );
INVX2TS U6341 ( .A(result_add_subt[18]), .Y(n6638) );
AOI22X1TS U6342 ( .A0(cordic_result[18]), .A1(n4708), .B0(n5457), .B1(
mult_result[18]), .Y(n4701) );
INVX2TS U6343 ( .A(result_add_subt[19]), .Y(n6644) );
AOI22X1TS U6344 ( .A0(n4708), .A1(cordic_result[19]), .B0(n4683), .B1(
mult_result[19]), .Y(n4702) );
INVX2TS U6345 ( .A(result_add_subt[15]), .Y(n6634) );
AOI22X1TS U6346 ( .A0(cordic_result[15]), .A1(n4708), .B0(n4666), .B1(
mult_result[15]), .Y(n4703) );
INVX2TS U6347 ( .A(result_add_subt[16]), .Y(n6655) );
AOI22X1TS U6348 ( .A0(cordic_result[16]), .A1(n4708), .B0(n4683), .B1(
mult_result[16]), .Y(n4704) );
INVX2TS U6349 ( .A(result_add_subt[17]), .Y(n6650) );
AOI22X1TS U6350 ( .A0(n4708), .A1(cordic_result[17]), .B0(n5457), .B1(
mult_result[17]), .Y(n4705) );
INVX2TS U6351 ( .A(result_add_subt[13]), .Y(n6652) );
AOI22X1TS U6352 ( .A0(cordic_result[13]), .A1(n4708), .B0(n4683), .B1(
mult_result[13]), .Y(n4706) );
AOI22X1TS U6353 ( .A0(cordic_result[14]), .A1(n4708), .B0(n5457), .B1(
mult_result[14]), .Y(n4709) );
INVX2TS U6354 ( .A(intadd_512_SUM_6_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
BUFX3TS U6355 ( .A(n4723), .Y(n4730) );
NOR2X2TS U6356 ( .A(n6413), .B(n4711), .Y(n4721) );
INVX2TS U6357 ( .A(n4712), .Y(n1752) );
INVX2TS U6358 ( .A(n4713), .Y(n1749) );
INVX2TS U6359 ( .A(n4714), .Y(n1747) );
INVX2TS U6360 ( .A(n4715), .Y(n1753) );
INVX2TS U6361 ( .A(n4716), .Y(n1751) );
INVX2TS U6362 ( .A(n4717), .Y(n1750) );
INVX2TS U6363 ( .A(n4718), .Y(n1745) );
INVX2TS U6364 ( .A(n4719), .Y(n1746) );
INVX2TS U6365 ( .A(n4720), .Y(n1748) );
BUFX3TS U6366 ( .A(n4723), .Y(n4737) );
INVX2TS U6367 ( .A(n4722), .Y(n1734) );
BUFX3TS U6368 ( .A(n4723), .Y(n4747) );
INVX2TS U6369 ( .A(n4724), .Y(n1754) );
INVX2TS U6370 ( .A(n6415), .Y(n6469) );
BUFX3TS U6371 ( .A(n4931), .Y(n4736) );
INVX2TS U6372 ( .A(n4725), .Y(n1742) );
INVX2TS U6373 ( .A(n4726), .Y(n1743) );
INVX2TS U6374 ( .A(n4727), .Y(n1737) );
INVX2TS U6375 ( .A(n4728), .Y(n1739) );
INVX2TS U6376 ( .A(n4729), .Y(n1735) );
INVX2TS U6377 ( .A(n4732), .Y(n1744) );
INVX2TS U6378 ( .A(n4733), .Y(n1741) );
INVX2TS U6379 ( .A(n4734), .Y(n1740) );
INVX2TS U6380 ( .A(n4735), .Y(n1736) );
INVX2TS U6381 ( .A(n4738), .Y(n1738) );
BUFX3TS U6382 ( .A(n4931), .Y(n4933) );
INVX2TS U6383 ( .A(n4739), .Y(n1761) );
INVX2TS U6384 ( .A(n4740), .Y(n1763) );
INVX2TS U6385 ( .A(n4741), .Y(n1756) );
INVX2TS U6386 ( .A(n4742), .Y(n1762) );
INVX2TS U6387 ( .A(n4743), .Y(n1759) );
INVX2TS U6388 ( .A(n4744), .Y(n1758) );
INVX2TS U6389 ( .A(n4745), .Y(n1757) );
INVX2TS U6390 ( .A(n4746), .Y(n1760) );
INVX2TS U6391 ( .A(n4749), .Y(n1755) );
NOR2X2TS U6392 ( .A(FPSENCOS_cont_iter_out[1]), .B(n6442), .Y(n4759) );
NAND2X1TS U6393 ( .A(n6455), .B(n6369), .Y(n6368) );
AOI22X1TS U6394 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n6456), .B0(n4759),
.B1(n6368), .Y(n4750) );
AOI21X1TS U6395 ( .A0(n6455), .A1(n6372), .B0(FPSENCOS_cont_iter_out[3]),
.Y(n4751) );
AOI22X1TS U6396 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n6456), .B0(n4759),
.B1(n4751), .Y(n4752) );
NAND3X2TS U6397 ( .A(n4753), .B(n5218), .C(n6780), .Y(n4814) );
NOR4X1TS U6398 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(n4814), .C(n5230), .D(
n6793), .Y(n4754) );
AOI2BB1X1TS U6399 ( .A0N(n4755), .A1N(n4806), .B0(n4754), .Y(n4758) );
NAND2X1TS U6400 ( .A(n5326), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n4757)
);
AOI22X1TS U6401 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n6456), .B0(n6364),
.B1(n4759), .Y(n4761) );
AOI21X1TS U6402 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n6782), .B0(n6362),
.Y(n4822) );
AOI21X1TS U6403 ( .A0(n6372), .A1(n6375), .B0(n4822), .Y(n4987) );
INVX2TS U6404 ( .A(intadd_514_n1), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11) );
INVX2TS U6405 ( .A(intadd_514_SUM_7_), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
NAND2X1TS U6406 ( .A(n6569), .B(n6955), .Y(n5477) );
NAND2X1TS U6407 ( .A(FPMULT_Op_MX[2]), .B(n2220), .Y(n5476) );
NOR2X2TS U6408 ( .A(n5477), .B(n5476), .Y(n5816) );
NAND2X2TS U6409 ( .A(n6570), .B(n2220), .Y(n4788) );
NOR2X2TS U6410 ( .A(n4788), .B(n5477), .Y(n5804) );
AOI22X1TS U6411 ( .A0(n6569), .A1(n2220), .B0(n6570), .B1(n6955), .Y(n4762)
);
NOR2X2TS U6412 ( .A(n2258), .B(n2248), .Y(n4769) );
NAND2X1TS U6413 ( .A(n2481), .B(n6587), .Y(n4773) );
XNOR2X1TS U6414 ( .A(n4769), .B(n4773), .Y(n4763) );
XOR2X1TS U6415 ( .A(n4763), .B(n4770), .Y(n5818) );
NAND2X1TS U6416 ( .A(n6587), .B(n6568), .Y(n5845) );
AOI22X1TS U6417 ( .A0(FPMULT_Op_MX[2]), .A1(n6587), .B0(n6568), .B1(n2289),
.Y(n4765) );
INVX2TS U6418 ( .A(n5835), .Y(n4778) );
NAND2X1TS U6419 ( .A(FPMULT_Op_MX[5]), .B(n6955), .Y(n4768) );
NOR2X2TS U6420 ( .A(n4788), .B(n4768), .Y(n5812) );
INVX2TS U6421 ( .A(n5812), .Y(n4791) );
OAI2BB1X1TS U6422 ( .A0N(n4788), .A1N(n4768), .B0(n4791), .Y(n5834) );
INVX2TS U6423 ( .A(n5834), .Y(n4777) );
INVX2TS U6424 ( .A(n4769), .Y(n4772) );
INVX2TS U6425 ( .A(n4770), .Y(n4771) );
OAI22X1TS U6426 ( .A0(n4774), .A1(n4773), .B0(n4772), .B1(n4771), .Y(n5803)
);
NAND2X2TS U6427 ( .A(n2481), .B(FPMULT_Op_MY[4]), .Y(n5807) );
XOR2X1TS U6428 ( .A(n5804), .B(n5807), .Y(n4775) );
XOR2X1TS U6429 ( .A(n5803), .B(n4775), .Y(n5836) );
OAI21X1TS U6430 ( .A0(n4778), .A1(n4777), .B0(n4776), .Y(intadd_514_A_3_) );
NAND2X1TS U6431 ( .A(n6587), .B(n6570), .Y(n4779) );
NOR2X1TS U6432 ( .A(n4793), .B(n4779), .Y(n5788) );
AOI21X1TS U6433 ( .A0(n4793), .A1(n4779), .B0(n5788), .Y(n4781) );
NAND2X1TS U6434 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[5]), .Y(n4787) );
INVX2TS U6435 ( .A(n4787), .Y(n4780) );
NAND2X1TS U6436 ( .A(n4781), .B(n4780), .Y(n5789) );
INVX2TS U6437 ( .A(n4781), .Y(n4782) );
NAND2X1TS U6438 ( .A(n4782), .B(n4787), .Y(n4783) );
NAND2X1TS U6439 ( .A(n5789), .B(n4783), .Y(n5826) );
INVX2TS U6440 ( .A(n5826), .Y(n4801) );
INVX2TS U6441 ( .A(n4784), .Y(n4785) );
INVX2TS U6442 ( .A(n5815), .Y(n4792) );
NOR2X2TS U6443 ( .A(n4788), .B(n4787), .Y(n5792) );
AOI22X1TS U6444 ( .A0(n2220), .A1(FPMULT_Op_MX[5]), .B0(n6570), .B1(
FPMULT_Op_MY[2]), .Y(n4789) );
NOR2X1TS U6445 ( .A(n5792), .B(n4789), .Y(n5813) );
INVX2TS U6446 ( .A(n5827), .Y(n4799) );
NOR2X1TS U6447 ( .A(n5807), .B(n4793), .Y(n4796) );
AOI22X1TS U6448 ( .A0(n2481), .A1(n2289), .B0(FPMULT_Op_MY[4]), .B1(
FPMULT_Op_MX[2]), .Y(n4794) );
NOR2X1TS U6449 ( .A(n4796), .B(n4794), .Y(n5811) );
INVX2TS U6450 ( .A(n6569), .Y(n4795) );
NOR2X1TS U6451 ( .A(n4795), .B(n2260), .Y(n5810) );
NAND2X1TS U6452 ( .A(n5811), .B(n5810), .Y(n5809) );
INVX2TS U6453 ( .A(n4796), .Y(n4797) );
NAND2X1TS U6454 ( .A(n5809), .B(n4797), .Y(n5795) );
NAND2X1TS U6455 ( .A(FPMULT_Op_MY[4]), .B(n6569), .Y(n5791) );
XNOR2X1TS U6456 ( .A(n5792), .B(n5791), .Y(n4798) );
XNOR2X1TS U6457 ( .A(n5795), .B(n4798), .Y(n5828) );
OAI21X1TS U6458 ( .A0(n4801), .A1(n5827), .B0(n4800), .Y(intadd_514_A_5_) );
AOI22X1TS U6459 ( .A0(FPMULT_Op_MY[4]), .A1(FPMULT_Op_MX[5]), .B0(n6570),
.B1(n2289), .Y(n4802) );
NAND2X1TS U6460 ( .A(FPMULT_Op_MY[4]), .B(n6570), .Y(n5797) );
NOR2X1TS U6461 ( .A(n5797), .B(intadd_514_A_7_), .Y(n5820) );
NOR2X1TS U6462 ( .A(n4802), .B(n5820), .Y(n4805) );
NAND2X1TS U6463 ( .A(n6569), .B(n2289), .Y(n5796) );
NAND2X1TS U6464 ( .A(n6587), .B(FPMULT_Op_MX[5]), .Y(n5798) );
OAI21X1TS U6465 ( .A0(n5796), .A1(n5798), .B0(n4803), .Y(n4804) );
NAND2X1TS U6466 ( .A(n4804), .B(n4805), .Y(n5821) );
OAI21X1TS U6467 ( .A0(n4805), .A1(n4804), .B0(n5821), .Y(intadd_514_B_6_) );
INVX2TS U6468 ( .A(intadd_512_n1), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N11) );
NOR3BX2TS U6469 ( .AN(n4807), .B(n4806), .C(FPADDSUB_Raw_mant_NRM_SWR[16]),
.Y(n5225) );
OAI22X1TS U6470 ( .A0(n4809), .A1(n4808), .B0(n5208), .B1(n4810), .Y(n4818)
);
AOI21X1TS U6471 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n6793), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4813) );
OAI32X1TS U6472 ( .A0(n4814), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .A2(n4813),
.B0(n6791), .B1(n4814), .Y(n4815) );
AOI211X2TS U6473 ( .A0(n5219), .A1(FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n5215), .C0(n4815), .Y(n5213) );
NAND2X1TS U6474 ( .A(n7059), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n4820)
);
INVX2TS U6475 ( .A(n4990), .Y(n4989) );
NAND2X1TS U6476 ( .A(n4822), .B(n6768), .Y(n6363) );
INVX2TS U6477 ( .A(intadd_512_SUM_7_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
NAND2X1TS U6478 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MY[12]), .Y(n5716) );
NAND2X1TS U6479 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MY[13]), .Y(n5715) );
NOR2X2TS U6480 ( .A(n5716), .B(n5715), .Y(n5714) );
NAND2X2TS U6481 ( .A(n6579), .B(n5649), .Y(n4850) );
NOR2X2TS U6482 ( .A(n4850), .B(n5716), .Y(n5699) );
AOI22X1TS U6483 ( .A0(FPMULT_Op_MX[15]), .A1(FPMULT_Op_MY[13]), .B0(n6579),
.B1(FPMULT_Op_MY[12]), .Y(n4824) );
NOR2X2TS U6484 ( .A(n2257), .B(n2226), .Y(n4831) );
NAND2X1TS U6485 ( .A(FPMULT_Op_MX[13]), .B(n6594), .Y(n4835) );
XNOR2X1TS U6486 ( .A(n4831), .B(n4835), .Y(n4825) );
XOR2X1TS U6487 ( .A(n4825), .B(n4832), .Y(n5712) );
OAI21X1TS U6488 ( .A0(n5714), .A1(n5711), .B0(n4826), .Y(intadd_512_A_2_) );
NAND2X2TS U6489 ( .A(FPMULT_Op_MX[14]), .B(n5648), .Y(n4855) );
NAND2X1TS U6490 ( .A(n6594), .B(FPMULT_Op_MX[12]), .Y(n5742) );
AOI22X1TS U6491 ( .A0(FPMULT_Op_MX[14]), .A1(FPMULT_Op_MY[15]), .B0(
FPMULT_Op_MX[12]), .B1(n5648), .Y(n4827) );
INVX2TS U6492 ( .A(n5732), .Y(n4840) );
NAND2X1TS U6493 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MX[17]), .Y(n4830) );
NOR2X2TS U6494 ( .A(n4850), .B(n4830), .Y(n5707) );
INVX2TS U6495 ( .A(n5707), .Y(n4853) );
OAI2BB1X1TS U6496 ( .A0N(n4850), .A1N(n4830), .B0(n4853), .Y(n5731) );
INVX2TS U6497 ( .A(n5731), .Y(n4839) );
INVX2TS U6498 ( .A(n4831), .Y(n4834) );
INVX2TS U6499 ( .A(n4832), .Y(n4833) );
OAI22X1TS U6500 ( .A0(n4836), .A1(n4835), .B0(n4834), .B1(n4833), .Y(n5698)
);
NAND2X2TS U6501 ( .A(FPMULT_Op_MX[13]), .B(n2290), .Y(n5702) );
XOR2X1TS U6502 ( .A(n5699), .B(n5702), .Y(n4837) );
XOR2X1TS U6503 ( .A(n5698), .B(n4837), .Y(n5733) );
OAI21X1TS U6504 ( .A0(n4840), .A1(n4839), .B0(n4838), .Y(intadd_512_A_3_) );
NAND2X1TS U6505 ( .A(n6594), .B(n6579), .Y(n4841) );
NOR2X1TS U6506 ( .A(n4855), .B(n4841), .Y(n5683) );
AOI21X1TS U6507 ( .A0(n4855), .A1(n4841), .B0(n5683), .Y(n4843) );
NAND2X1TS U6508 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MX[17]), .Y(n4849) );
INVX2TS U6509 ( .A(n4849), .Y(n4842) );
NAND2X1TS U6510 ( .A(n4843), .B(n4842), .Y(n5684) );
INVX2TS U6511 ( .A(n4843), .Y(n4844) );
NAND2X1TS U6512 ( .A(n4844), .B(n4849), .Y(n4845) );
NAND2X1TS U6513 ( .A(n5684), .B(n4845), .Y(n5723) );
INVX2TS U6514 ( .A(n5723), .Y(n4863) );
INVX2TS U6515 ( .A(n4846), .Y(n4847) );
INVX2TS U6516 ( .A(n5710), .Y(n4854) );
NOR2X2TS U6517 ( .A(n4850), .B(n4849), .Y(n5687) );
AOI22X1TS U6518 ( .A0(n6579), .A1(FPMULT_Op_MY[14]), .B0(FPMULT_Op_MY[13]),
.B1(n2344), .Y(n4851) );
NOR2X1TS U6519 ( .A(n5687), .B(n4851), .Y(n5708) );
INVX2TS U6520 ( .A(n5724), .Y(n4861) );
NOR2X1TS U6521 ( .A(n5702), .B(n4855), .Y(n4858) );
AOI22X1TS U6522 ( .A0(FPMULT_Op_MX[13]), .A1(n5648), .B0(n2290), .B1(
FPMULT_Op_MX[14]), .Y(n4856) );
NOR2X1TS U6523 ( .A(n4858), .B(n4856), .Y(n5706) );
INVX2TS U6524 ( .A(n6594), .Y(n4857) );
NOR2X1TS U6525 ( .A(n2479), .B(n4857), .Y(n5705) );
NAND2X1TS U6526 ( .A(n5706), .B(n5705), .Y(n5704) );
INVX2TS U6527 ( .A(n4858), .Y(n4859) );
NAND2X1TS U6528 ( .A(n5704), .B(n4859), .Y(n5690) );
NAND2X1TS U6529 ( .A(n2290), .B(FPMULT_Op_MX[15]), .Y(n5686) );
XNOR2X1TS U6530 ( .A(n5687), .B(n5686), .Y(n4860) );
XNOR2X1TS U6531 ( .A(n5690), .B(n4860), .Y(n5725) );
OAI21X1TS U6532 ( .A0(n4863), .A1(n5724), .B0(n4862), .Y(intadd_512_A_5_) );
AOI22X1TS U6533 ( .A0(n5648), .A1(n6579), .B0(n2290), .B1(n2344), .Y(n4864)
);
NAND2X1TS U6534 ( .A(n2290), .B(n6579), .Y(n5692) );
NOR2X1TS U6535 ( .A(n5692), .B(intadd_512_A_7_), .Y(n5717) );
NOR2X1TS U6536 ( .A(n4864), .B(n5717), .Y(n4867) );
NAND2X1TS U6537 ( .A(n6594), .B(FPMULT_Op_MX[17]), .Y(n5691) );
NAND2X1TS U6538 ( .A(n5648), .B(FPMULT_Op_MX[15]), .Y(n5693) );
OAI21X1TS U6539 ( .A0(n5691), .A1(n5693), .B0(n4865), .Y(n4866) );
NAND2X1TS U6540 ( .A(n4866), .B(n4867), .Y(n5718) );
OAI21X1TS U6541 ( .A0(n4867), .A1(n4866), .B0(n5718), .Y(intadd_512_B_6_) );
NOR2X1TS U6542 ( .A(n2304), .B(n5539), .Y(DP_OP_502J223_128_4510_n161) );
NAND2X2TS U6543 ( .A(n6584), .B(n6572), .Y(n4892) );
NAND2X1TS U6544 ( .A(DP_OP_501J223_127_5235_n903), .B(n2345), .Y(n4868) );
NOR2X2TS U6545 ( .A(n4892), .B(n4868), .Y(n4897) );
INVX2TS U6546 ( .A(n5773), .Y(n4880) );
NAND2X2TS U6547 ( .A(n2287), .B(n5642), .Y(n4903) );
NAND2X1TS U6548 ( .A(FPMULT_Op_MX[6]), .B(n5643), .Y(n5760) );
AOI22X1TS U6549 ( .A0(n5642), .A1(FPMULT_Op_MX[6]), .B0(FPMULT_Op_MX[8]),
.B1(FPMULT_Op_MY[9]), .Y(n4869) );
NAND2X1TS U6550 ( .A(n4871), .B(n4870), .Y(n4891) );
INVX2TS U6551 ( .A(n5774), .Y(n4879) );
NAND2X1TS U6552 ( .A(DP_OP_501J223_127_5235_n903), .B(
DP_OP_501J223_127_5235_n944), .Y(n5783) );
NOR2X2TS U6553 ( .A(n4892), .B(n5783), .Y(n5748) );
NAND2X2TS U6554 ( .A(FPMULT_Op_MX[7]), .B(n6588), .Y(n4885) );
XOR2X1TS U6555 ( .A(n5748), .B(n4885), .Y(n4877) );
NAND2X1TS U6556 ( .A(n2287), .B(n5644), .Y(n5749) );
NAND2X1TS U6557 ( .A(FPMULT_Op_MX[6]), .B(n6588), .Y(n4873) );
NAND2X1TS U6558 ( .A(n5749), .B(n4873), .Y(n4872) );
NAND2X1TS U6559 ( .A(n4872), .B(n5750), .Y(n4876) );
INVX2TS U6560 ( .A(n5749), .Y(n4874) );
INVX2TS U6561 ( .A(n4873), .Y(n5751) );
NAND2X1TS U6562 ( .A(n4874), .B(n5751), .Y(n4875) );
NAND2X1TS U6563 ( .A(n4876), .B(n4875), .Y(n4883) );
XNOR2X1TS U6564 ( .A(n4877), .B(n4883), .Y(n5775) );
OAI21X1TS U6565 ( .A0(n4880), .A1(n4879), .B0(n4878), .Y(mult_x_311_n29) );
INVX2TS U6566 ( .A(n5748), .Y(n4881) );
NAND2X1TS U6567 ( .A(n4881), .B(n4885), .Y(n4884) );
INVX2TS U6568 ( .A(n4885), .Y(n4882) );
NOR2X1TS U6569 ( .A(n4885), .B(n4903), .Y(n4911) );
AOI22X1TS U6570 ( .A0(FPMULT_Op_MX[7]), .A1(n5642), .B0(FPMULT_Op_MX[8]),
.B1(n6588), .Y(n4886) );
NOR2X1TS U6571 ( .A(n4911), .B(n4886), .Y(n4888) );
NOR2X1TS U6572 ( .A(n2225), .B(n6754), .Y(n4887) );
NAND2X1TS U6573 ( .A(n4888), .B(n4887), .Y(n4913) );
INVX2TS U6574 ( .A(n4889), .Y(n4890) );
NAND2X1TS U6575 ( .A(n2345), .B(n5644), .Y(n4907) );
NOR2X2TS U6576 ( .A(n4892), .B(n4907), .Y(n4920) );
AOI22X1TS U6577 ( .A0(n6584), .A1(n2346), .B0(n6572), .B1(FPMULT_Op_MY[8]),
.Y(n4893) );
NOR2X1TS U6578 ( .A(n4920), .B(n4893), .Y(n4896) );
XOR2X1TS U6579 ( .A(n4896), .B(n4897), .Y(n4894) );
XNOR2X1TS U6580 ( .A(n4898), .B(n4894), .Y(n5771) );
INVX2TS U6581 ( .A(n4898), .Y(n4901) );
INVX2TS U6582 ( .A(n4897), .Y(n4900) );
INVX2TS U6583 ( .A(n5766), .Y(n4917) );
NAND2X1TS U6584 ( .A(FPMULT_Op_MY[9]), .B(n6572), .Y(n4902) );
NOR2X1TS U6585 ( .A(n4903), .B(n4902), .Y(n4905) );
NAND2X1TS U6586 ( .A(n4903), .B(n4902), .Y(n4910) );
NAND2X1TS U6587 ( .A(n4904), .B(n4910), .Y(n4908) );
INVX2TS U6588 ( .A(n4905), .Y(n4906) );
INVX2TS U6589 ( .A(n4907), .Y(n4909) );
INVX2TS U6590 ( .A(n5765), .Y(n4915) );
INVX2TS U6591 ( .A(n4911), .Y(n4912) );
NAND2X1TS U6592 ( .A(n4913), .B(n4912), .Y(n4918) );
NAND2X1TS U6593 ( .A(DP_OP_501J223_127_5235_n944), .B(n6588), .Y(n4923) );
XOR2X1TS U6594 ( .A(n4920), .B(n4923), .Y(n4914) );
XNOR2X1TS U6595 ( .A(n4918), .B(n4914), .Y(n5767) );
OAI21X1TS U6596 ( .A0(n4917), .A1(n5765), .B0(n4916), .Y(mult_x_311_n17) );
INVX2TS U6597 ( .A(n4920), .Y(n4922) );
INVX2TS U6598 ( .A(n4923), .Y(n4919) );
INVX2TS U6599 ( .A(n5763), .Y(n4930) );
INVX2TS U6600 ( .A(n5762), .Y(n4928) );
XNOR2X1TS U6601 ( .A(n4925), .B(n4924), .Y(n4927) );
XOR2X1TS U6602 ( .A(n4927), .B(n4926), .Y(n5761) );
NOR2X1TS U6603 ( .A(n2303), .B(n5547), .Y(DP_OP_502J223_128_4510_n185) );
INVX2TS U6604 ( .A(n4932), .Y(n1733) );
INVX2TS U6605 ( .A(n4934), .Y(n1764) );
AOI22X1TS U6606 ( .A0(n2292), .A1(n2291), .B0(n2285), .B1(n6753), .Y(n4935)
);
INVX2TS U6607 ( .A(n5445), .Y(n4936) );
NAND2X2TS U6608 ( .A(n4936), .B(n7067), .Y(n5674) );
NAND2X1TS U6609 ( .A(n5674), .B(n2291), .Y(n5677) );
NAND2X1TS U6610 ( .A(n5677), .B(n2285), .Y(n4940) );
AOI21X1TS U6611 ( .A0(n5445), .A1(n4938), .B0(n4937), .Y(n5675) );
NAND2X1TS U6612 ( .A(n5674), .B(n2478), .Y(n4939) );
OAI21X1TS U6613 ( .A0(n5674), .A1(n2478), .B0(n5679), .Y(intadd_515_A_0_) );
NAND2X2TS U6614 ( .A(n2383), .B(FPMULT_Op_MX[21]), .Y(n5446) );
AOI22X1TS U6615 ( .A0(n2292), .A1(n6595), .B0(n2383), .B1(FPMULT_Op_MX[19]),
.Y(n4946) );
NAND2X1TS U6616 ( .A(n6567), .B(n6753), .Y(n4944) );
INVX2TS U6617 ( .A(n4941), .Y(n4942) );
INVX2TS U6618 ( .A(n4943), .Y(n4945) );
OAI22X2TS U6619 ( .A0(n5442), .A1(n4946), .B0(n4945), .B1(n4944), .Y(n5668)
);
INVX2TS U6620 ( .A(n5668), .Y(n4954) );
INVX2TS U6621 ( .A(n7067), .Y(n5439) );
INVX2TS U6622 ( .A(n5667), .Y(n4952) );
AOI21X1TS U6623 ( .A0(n4973), .A1(n4948), .B0(n4947), .Y(n4950) );
NAND2X1TS U6624 ( .A(n6585), .B(n2285), .Y(n4958) );
XOR2X1TS U6625 ( .A(n4956), .B(n4958), .Y(n4951) );
XOR2X1TS U6626 ( .A(n4960), .B(n4951), .Y(n5669) );
OAI21X1TS U6627 ( .A0(n4954), .A1(n5667), .B0(n4953), .Y(mult_x_309_n29) );
INVX2TS U6628 ( .A(n4958), .Y(n4955) );
NOR2X1TS U6629 ( .A(n4956), .B(n4955), .Y(n4959) );
INVX2TS U6630 ( .A(n4956), .Y(n4957) );
INVX2TS U6631 ( .A(n5663), .Y(n4967) );
AOI22X1TS U6632 ( .A0(n6567), .A1(n5647), .B0(n2383), .B1(n2285), .Y(n4961)
);
AOI21X2TS U6633 ( .A0(n4963), .A1(n4962), .B0(n5444), .Y(n5664) );
INVX2TS U6634 ( .A(n5664), .Y(n4966) );
XOR2X1TS U6635 ( .A(n5440), .B(n7067), .Y(n4964) );
XOR2X1TS U6636 ( .A(n5442), .B(n4964), .Y(n5665) );
OAI21X1TS U6637 ( .A0(n2285), .A1(n6595), .B0(n4969), .Y(n4974) );
XOR2X1TS U6638 ( .A(n5647), .B(n2285), .Y(n4970) );
OAI22X2TS U6639 ( .A0(n4974), .A1(n4971), .B0(n4970), .B1(n4969), .Y(n5448)
);
OAI21X2TS U6640 ( .A0(n5446), .A1(n5448), .B0(n4972), .Y(n5658) );
INVX2TS U6641 ( .A(n5658), .Y(n4979) );
NAND2X1TS U6642 ( .A(n4974), .B(n4973), .Y(n5655) );
INVX2TS U6643 ( .A(n5655), .Y(n4978) );
XNOR2X1TS U6644 ( .A(n2292), .B(n6585), .Y(n4976) );
XOR2X1TS U6645 ( .A(n4976), .B(n4975), .Y(n5656) );
OAI21X1TS U6646 ( .A0(n4979), .A1(n4978), .B0(n4977), .Y(mult_x_309_n14) );
INVX2TS U6647 ( .A(n4980), .Y(n4981) );
AOI211X1TS U6648 ( .A0(n6456), .A1(FPSENCOS_d_ff3_LUT_out[21]), .B0(n6366),
.C0(n4981), .Y(n4982) );
INVX2TS U6649 ( .A(n4982), .Y(n2118) );
XNOR2X1TS U6650 ( .A(n2266), .B(FPSENCOS_d_ff1_operation_out), .Y(n4983) );
CLKXOR2X2TS U6651 ( .A(n6558), .B(n4983), .Y(n6557) );
INVX2TS U6652 ( .A(n6557), .Y(n6556) );
INVX2TS U6653 ( .A(n4986), .Y(n1696) );
NOR2X2TS U6654 ( .A(n4987), .B(n6768), .Y(n5012) );
AOI21X1TS U6655 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n6442), .B0(n5012),
.Y(n4988) );
AOI211X1TS U6656 ( .A0(n6456), .A1(FPSENCOS_d_ff3_LUT_out[9]), .B0(n5012),
.C0(n4990), .Y(n4991) );
INVX2TS U6657 ( .A(n4991), .Y(n2124) );
NAND3X1TS U6658 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n4993),
.C(n4992), .Y(n6347) );
NOR3X2TS U6659 ( .A(n6756), .B(n4998), .C(FPSENCOS_cont_var_out[1]), .Y(
n4995) );
BUFX3TS U6660 ( .A(n5015), .Y(n6505) );
AOI22X1TS U6661 ( .A0(Data_2[21]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n6505), .Y(n5001) );
BUFX3TS U6662 ( .A(n6549), .Y(n5039) );
NOR2X1TS U6663 ( .A(n6756), .B(n6802), .Y(n5463) );
INVX2TS U6664 ( .A(n5463), .Y(n6345) );
BUFX3TS U6665 ( .A(n4999), .Y(n5038) );
AOI22X1TS U6666 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n5000) );
BUFX3TS U6667 ( .A(n4996), .Y(n6518) );
BUFX3TS U6668 ( .A(n5103), .Y(n6479) );
AOI22X1TS U6669 ( .A0(Data_2[12]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n6479), .Y(n5003) );
AOI22X1TS U6670 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n5002) );
BUFX3TS U6671 ( .A(n5103), .Y(n6548) );
AOI22X1TS U6672 ( .A0(Data_2[24]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n6548), .Y(n5005) );
AOI22X1TS U6673 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n5004) );
AOI22X1TS U6674 ( .A0(Data_2[26]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n6548), .Y(n5007) );
AOI22X1TS U6675 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[26]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n5006) );
AOI22X1TS U6676 ( .A0(Data_2[25]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n6548), .Y(n5009) );
AOI22X1TS U6677 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n5008) );
INVX2TS U6678 ( .A(FPSENCOS_d_ff3_sh_y_out[23]), .Y(n6457) );
AOI22X1TS U6679 ( .A0(Data_2[23]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n6548), .Y(n5011) );
AOI22X1TS U6680 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[23]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n5010) );
AOI211X1TS U6681 ( .A0(n6456), .A1(FPSENCOS_d_ff3_LUT_out[12]), .B0(n5013),
.C0(n5012), .Y(n5014) );
INVX2TS U6682 ( .A(n5014), .Y(n2122) );
BUFX3TS U6683 ( .A(n5052), .Y(n5087) );
BUFX3TS U6684 ( .A(n5053), .Y(n5084) );
BUFX3TS U6685 ( .A(n5015), .Y(n5100) );
AOI22X1TS U6686 ( .A0(Data_1[24]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n5100), .Y(n5017) );
BUFX3TS U6687 ( .A(n6549), .Y(n5094) );
BUFX3TS U6688 ( .A(n4999), .Y(n5097) );
AOI22X1TS U6689 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[24]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n5016) );
BUFX3TS U6690 ( .A(n5052), .Y(n5067) );
BUFX3TS U6691 ( .A(n5103), .Y(n5062) );
AOI22X1TS U6692 ( .A0(Data_1[30]), .A1(n4996), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n5062), .Y(n5019) );
BUFX3TS U6693 ( .A(n6549), .Y(n5064) );
BUFX3TS U6694 ( .A(n4999), .Y(n5063) );
AOI22X1TS U6695 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[30]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n5018) );
AOI22X1TS U6696 ( .A0(Data_1[29]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n5062), .Y(n5021) );
AOI22X1TS U6697 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[29]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n5020) );
AOI22X1TS U6698 ( .A0(Data_1[27]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n5062), .Y(n5023) );
AOI22X1TS U6699 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n5022) );
AOI22X1TS U6700 ( .A0(Data_1[25]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n5062), .Y(n5025) );
AOI22X1TS U6701 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[25]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n5024) );
AOI22X1TS U6702 ( .A0(Data_1[26]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n5062), .Y(n5027) );
AOI22X1TS U6703 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[26]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n5026) );
AOI22X1TS U6704 ( .A0(Data_2[8]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n6479), .Y(n5029) );
AOI22X1TS U6705 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[8]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n5028) );
AOI22X1TS U6706 ( .A0(Data_2[10]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n6479), .Y(n5031) );
AOI22X1TS U6707 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[10]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n5030) );
OAI211X1TS U6708 ( .A0(n5067), .A1(n2446), .B0(n5031), .C0(n5030), .Y(n1833)
);
AOI22X1TS U6709 ( .A0(Data_2[6]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n6479), .Y(n5033) );
AOI22X1TS U6710 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n5032) );
AOI22X1TS U6711 ( .A0(Data_2[2]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n5062), .Y(n5035) );
AOI22X1TS U6712 ( .A0(n5064), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n5063),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n5034) );
AOI22X1TS U6713 ( .A0(Data_2[1]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n5062), .Y(n5037) );
AOI22X1TS U6714 ( .A0(n5064), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n5063),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n5036) );
AOI22X1TS U6715 ( .A0(Data_2[9]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n6479), .Y(n5041) );
AOI22X1TS U6716 ( .A0(n5039), .A1(FPSENCOS_d_ff3_sh_x_out[9]), .B0(n5038),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n5040) );
AOI22X1TS U6717 ( .A0(Data_2[4]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n6479), .Y(n5043) );
AOI22X1TS U6718 ( .A0(n5064), .A1(FPSENCOS_d_ff3_sh_x_out[4]), .B0(n5063),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n5042) );
AOI22X1TS U6719 ( .A0(Data_2[0]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n5062), .Y(n5045) );
AOI22X1TS U6720 ( .A0(n5064), .A1(FPSENCOS_d_ff3_sh_x_out[0]), .B0(n5063),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n5044) );
AOI22X1TS U6721 ( .A0(Data_1[23]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n5100), .Y(n5047) );
AOI22X1TS U6722 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[23]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n5046) );
AOI22X1TS U6723 ( .A0(Data_1[28]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n5062), .Y(n5049) );
AOI22X1TS U6724 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[28]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n5048) );
BUFX3TS U6725 ( .A(n5052), .Y(n5110) );
INVX2TS U6726 ( .A(FPSENCOS_d_ff2_X[15]), .Y(n6418) );
BUFX3TS U6727 ( .A(n5053), .Y(n5106) );
AOI22X1TS U6728 ( .A0(Data_1[15]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n5100), .Y(n5051) );
BUFX3TS U6729 ( .A(n6549), .Y(n5107) );
BUFX3TS U6730 ( .A(n4999), .Y(n5113) );
AOI22X1TS U6731 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n5050) );
BUFX3TS U6732 ( .A(n5052), .Y(n5116) );
INVX2TS U6733 ( .A(FPSENCOS_d_ff2_X[8]), .Y(n6407) );
BUFX3TS U6734 ( .A(n5053), .Y(n5112) );
BUFX3TS U6735 ( .A(n5103), .Y(n5111) );
AOI22X1TS U6736 ( .A0(Data_1[8]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n5111), .Y(n5055) );
AOI22X1TS U6737 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[8]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n5054) );
INVX2TS U6738 ( .A(FPSENCOS_d_ff2_X[4]), .Y(n6402) );
AOI22X1TS U6739 ( .A0(Data_1[4]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n5103), .Y(n5057) );
BUFX3TS U6740 ( .A(n4999), .Y(n6474) );
AOI22X1TS U6741 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n5056) );
INVX2TS U6742 ( .A(FPSENCOS_d_ff2_X[9]), .Y(n6409) );
AOI22X1TS U6743 ( .A0(Data_1[9]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n5111), .Y(n5059) );
AOI22X1TS U6744 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n5058) );
INVX2TS U6745 ( .A(FPSENCOS_d_ff2_X[18]), .Y(n6421) );
AOI22X1TS U6746 ( .A0(Data_1[18]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n5100), .Y(n5061) );
AOI22X1TS U6747 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n5060) );
INVX2TS U6748 ( .A(FPSENCOS_d_ff2_X[31]), .Y(n6441) );
AOI22X1TS U6749 ( .A0(Data_1[31]), .A1(n4996), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n5062), .Y(n5066) );
AOI22X1TS U6750 ( .A0(n5064), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n5063), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n5065) );
INVX2TS U6751 ( .A(FPSENCOS_d_ff2_X[0]), .Y(n6396) );
AOI22X1TS U6752 ( .A0(n5112), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n5103), .Y(n5069) );
AOI22X1TS U6753 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[0]), .B0(
FPSENCOS_d_ff2_Z[0]), .B1(n6474), .Y(n5068) );
INVX2TS U6754 ( .A(FPSENCOS_d_ff2_X[21]), .Y(n6426) );
AOI22X1TS U6755 ( .A0(Data_1[21]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n5100), .Y(n5071) );
AOI22X1TS U6756 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n5070) );
INVX2TS U6757 ( .A(FPSENCOS_d_ff2_X[11]), .Y(n6410) );
AOI22X1TS U6758 ( .A0(Data_1[11]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n5111), .Y(n5073) );
AOI22X1TS U6759 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n5072) );
AOI22X1TS U6760 ( .A0(Data_1[22]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n5100), .Y(n5075) );
AOI22X1TS U6761 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n5074) );
INVX2TS U6762 ( .A(FPSENCOS_d_ff2_X[5]), .Y(n6404) );
AOI22X1TS U6763 ( .A0(Data_1[5]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n5111), .Y(n5077) );
BUFX3TS U6764 ( .A(n6549), .Y(n6485) );
AOI22X1TS U6765 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n5076) );
AOI22X1TS U6766 ( .A0(Data_1[14]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n5111), .Y(n5079) );
AOI22X1TS U6767 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n5078) );
INVX2TS U6768 ( .A(FPSENCOS_d_ff2_X[3]), .Y(n6401) );
AOI22X1TS U6769 ( .A0(Data_1[3]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n5103), .Y(n5081) );
AOI22X1TS U6770 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n5080) );
INVX2TS U6771 ( .A(FPSENCOS_d_ff2_X[2]), .Y(n6399) );
AOI22X1TS U6772 ( .A0(Data_1[2]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n5103), .Y(n5083) );
AOI22X1TS U6773 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n5082) );
AOI22X1TS U6774 ( .A0(Data_1[20]), .A1(n5084), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n5100), .Y(n5086) );
AOI22X1TS U6775 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n5085) );
AOI22X1TS U6776 ( .A0(Data_1[10]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n5111), .Y(n5089) );
AOI22X1TS U6777 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[10]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n5088) );
INVX2TS U6778 ( .A(FPSENCOS_d_ff2_X[19]), .Y(n6423) );
AOI22X1TS U6779 ( .A0(Data_1[19]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n5100), .Y(n5091) );
AOI22X1TS U6780 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n5090) );
AOI22X1TS U6781 ( .A0(Data_1[6]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n5111), .Y(n5093) );
AOI22X1TS U6782 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n5092) );
INVX2TS U6783 ( .A(FPSENCOS_d_ff2_X[17]), .Y(n6420) );
AOI22X1TS U6784 ( .A0(Data_1[17]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n5100), .Y(n5096) );
AOI22X1TS U6785 ( .A0(n5094), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n5095) );
INVX2TS U6786 ( .A(FPSENCOS_d_ff2_X[12]), .Y(n6412) );
AOI22X1TS U6787 ( .A0(Data_1[12]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n5111), .Y(n5099) );
AOI22X1TS U6788 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[12]), .B0(n5097), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n5098) );
AOI22X1TS U6789 ( .A0(Data_1[16]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n5100), .Y(n5102) );
AOI22X1TS U6790 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n5101) );
INVX2TS U6791 ( .A(FPSENCOS_d_ff2_X[1]), .Y(n6398) );
AOI22X1TS U6792 ( .A0(Data_1[1]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n5103), .Y(n5105) );
AOI22X1TS U6793 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n6474), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n5104) );
AOI22X1TS U6794 ( .A0(Data_1[13]), .A1(n5106), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n5111), .Y(n5109) );
AOI22X1TS U6795 ( .A0(n5107), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n5108) );
INVX2TS U6796 ( .A(FPSENCOS_d_ff2_X[7]), .Y(n6406) );
AOI22X1TS U6797 ( .A0(Data_1[7]), .A1(n5112), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n5111), .Y(n5115) );
AOI22X1TS U6798 ( .A0(n6485), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n5113), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n5114) );
INVX2TS U6799 ( .A(n5117), .Y(n1725) );
BUFX3TS U6800 ( .A(n6562), .Y(n5141) );
INVX2TS U6801 ( .A(n5119), .Y(n1716) );
BUFX3TS U6802 ( .A(n6562), .Y(n5167) );
INVX2TS U6803 ( .A(n5120), .Y(n1712) );
INVX2TS U6804 ( .A(n5121), .Y(n1726) );
INVX2TS U6805 ( .A(n5122), .Y(n1709) );
INVX2TS U6806 ( .A(n5123), .Y(n1718) );
INVX2TS U6807 ( .A(n5124), .Y(n1723) );
INVX2TS U6808 ( .A(n5125), .Y(n1721) );
INVX2TS U6809 ( .A(n5126), .Y(n1714) );
INVX2TS U6810 ( .A(n5127), .Y(n1715) );
INVX2TS U6811 ( .A(n5128), .Y(n1719) );
INVX2TS U6812 ( .A(n5129), .Y(n1724) );
INVX2TS U6813 ( .A(n5130), .Y(n1711) );
INVX2TS U6814 ( .A(n5131), .Y(n1722) );
INVX2TS U6815 ( .A(n5132), .Y(n1713) );
INVX2TS U6816 ( .A(n5133), .Y(n1707) );
INVX2TS U6817 ( .A(n5134), .Y(n1708) );
INVX2TS U6818 ( .A(n5135), .Y(n1720) );
INVX2TS U6819 ( .A(n5138), .Y(n1710) );
INVX2TS U6820 ( .A(n5142), .Y(n1717) );
INVX2TS U6821 ( .A(n6354), .Y(n7060) );
OAI22X1TS U6822 ( .A0(n2381), .A1(n5534), .B0(n2304), .B1(n5536), .Y(n5146)
);
NOR2X1TS U6823 ( .A(n5152), .B(n5487), .Y(n5479) );
CMPR32X2TS U6824 ( .A(n5147), .B(n5146), .C(DP_OP_502J223_128_4510_n100),
.CO(n5154), .S(n5149) );
NOR2X1TS U6825 ( .A(n2304), .B(n5534), .Y(n5153) );
NAND2X1TS U6826 ( .A(n5479), .B(n5484), .Y(n5157) );
INVX2TS U6827 ( .A(n5148), .Y(n5488) );
NAND2X1TS U6828 ( .A(DP_OP_502J223_128_4510_n101), .B(n5149), .Y(n5493) );
INVX2TS U6829 ( .A(n5493), .Y(n5150) );
AOI21X1TS U6830 ( .A0(n5488), .A1(n5494), .B0(n5150), .Y(n5151) );
OAI21X1TS U6831 ( .A0(n5152), .A1(n5497), .B0(n5151), .Y(n5480) );
NAND2X1TS U6832 ( .A(n5154), .B(n5153), .Y(n5483) );
INVX2TS U6833 ( .A(n5483), .Y(n5155) );
AOI21X1TS U6834 ( .A0(n5480), .A1(n5484), .B0(n5155), .Y(n5156) );
INVX2TS U6835 ( .A(n5159), .Y(n1698) );
INVX2TS U6836 ( .A(n5160), .Y(n1703) );
INVX2TS U6837 ( .A(n5161), .Y(n1701) );
INVX2TS U6838 ( .A(n5162), .Y(n1702) );
INVX2TS U6839 ( .A(n5163), .Y(n1699) );
INVX2TS U6840 ( .A(n5164), .Y(n1697) );
INVX2TS U6841 ( .A(n5165), .Y(n1700) );
INVX2TS U6842 ( .A(n5166), .Y(n1704) );
INVX2TS U6843 ( .A(n5168), .Y(n1706) );
INVX2TS U6844 ( .A(n5170), .Y(n1705) );
NOR2X1TS U6845 ( .A(n5608), .B(n5612), .Y(n5173) );
OAI22X1TS U6846 ( .A0(n2376), .A1(n5615), .B0(n5180), .B1(n5613), .Y(n5172)
);
NOR2X2TS U6847 ( .A(DP_OP_500J223_126_4510_n110), .B(
DP_OP_500J223_126_4510_n116), .Y(n5575) );
NOR2X2TS U6848 ( .A(DP_OP_500J223_126_4510_n117), .B(
DP_OP_500J223_126_4510_n122), .Y(n5580) );
NOR2X1TS U6849 ( .A(n5575), .B(n5580), .Y(n5189) );
ADDHXLTS U6850 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[19]), .CO(n4304), .S(
n5171) );
INVX2TS U6851 ( .A(n5171), .Y(n5618) );
OAI22X1TS U6852 ( .A0(n2310), .A1(n5618), .B0(n2376), .B1(n5616), .Y(n5176)
);
ADDHX1TS U6853 ( .A(n5173), .B(n5172), .CO(DP_OP_500J223_126_4510_n141), .S(
n5175) );
NOR2X1TS U6854 ( .A(n5180), .B(n5615), .Y(n5179) );
OAI22X1TS U6855 ( .A0(n5614), .A1(n5618), .B0(n5608), .B1(n5616), .Y(n5178)
);
NOR2X1TS U6856 ( .A(DP_OP_500J223_126_4510_n136), .B(n5186), .Y(n5594) );
CMPR32X2TS U6857 ( .A(n5176), .B(n5175), .C(n5174), .CO(n5186), .S(n5185) );
ADDHXLTS U6858 ( .A(FPMULT_Op_MX[12]), .B(n5640), .CO(n5177), .S(n4573) );
INVX2TS U6859 ( .A(n5177), .Y(n5620) );
OAI22X1TS U6860 ( .A0(n5621), .A1(n5622), .B0(n5617), .B1(n5620), .Y(n5184)
);
NOR2X2TS U6861 ( .A(n5185), .B(n5184), .Y(n5599) );
ADDHX1TS U6862 ( .A(n5179), .B(n5178), .CO(n5174), .S(n5182) );
OAI22X1TS U6863 ( .A0(n2310), .A1(n5622), .B0(n2376), .B1(n5620), .Y(n5181)
);
OAI22X1TS U6864 ( .A0(n2376), .A1(n5622), .B0(n5180), .B1(n5620), .Y(n5469)
);
NOR2X1TS U6865 ( .A(n5608), .B(n5618), .Y(n5468) );
NAND2X1TS U6866 ( .A(n5469), .B(n5468), .Y(n5470) );
INVX2TS U6867 ( .A(n5470), .Y(n5606) );
NAND2X1TS U6868 ( .A(n5182), .B(n5181), .Y(n5604) );
INVX2TS U6869 ( .A(n5604), .Y(n5183) );
AOI21X1TS U6870 ( .A0(n5605), .A1(n5606), .B0(n5183), .Y(n5602) );
NAND2X1TS U6871 ( .A(n5185), .B(n5184), .Y(n5600) );
NAND2X1TS U6872 ( .A(DP_OP_500J223_126_4510_n136), .B(n5186), .Y(n5595) );
NAND2X1TS U6873 ( .A(DP_OP_500J223_126_4510_n129), .B(
DP_OP_500J223_126_4510_n135), .Y(n5590) );
INVX2TS U6874 ( .A(n5590), .Y(n5187) );
AOI21X2TS U6875 ( .A0(n5592), .A1(n5591), .B0(n5187), .Y(n5588) );
NAND2X1TS U6876 ( .A(DP_OP_500J223_126_4510_n123), .B(
DP_OP_500J223_126_4510_n128), .Y(n5586) );
OAI21X2TS U6877 ( .A0(n5588), .A1(n5585), .B0(n5586), .Y(n5574) );
NAND2X2TS U6878 ( .A(DP_OP_500J223_126_4510_n117), .B(
DP_OP_500J223_126_4510_n122), .Y(n5581) );
NAND2X1TS U6879 ( .A(DP_OP_500J223_126_4510_n110), .B(
DP_OP_500J223_126_4510_n116), .Y(n5576) );
OAI21X1TS U6880 ( .A0(n5575), .A1(n5581), .B0(n5576), .Y(n5188) );
AOI21X4TS U6881 ( .A0(n5189), .A1(n5574), .B0(n5188), .Y(n5573) );
OR2X2TS U6882 ( .A(DP_OP_500J223_126_4510_n102), .B(
DP_OP_500J223_126_4510_n104), .Y(n5567) );
OAI22X1TS U6883 ( .A0(n5619), .A1(n2405), .B0(n2306), .B1(FPMULT_Op_MX[17]),
.Y(n5190) );
NOR2X2TS U6884 ( .A(DP_OP_500J223_126_4510_n109), .B(
DP_OP_500J223_126_4510_n105), .Y(n5565) );
NOR2X1TS U6885 ( .A(n5195), .B(n5565), .Y(n5550) );
CMPR32X2TS U6886 ( .A(n5191), .B(n5190), .C(DP_OP_500J223_126_4510_n100),
.CO(n5197), .S(n5192) );
NOR2X1TS U6887 ( .A(n2306), .B(n2405), .Y(n5196) );
NAND2X2TS U6888 ( .A(DP_OP_500J223_126_4510_n109), .B(
DP_OP_500J223_126_4510_n105), .Y(n5570) );
NAND2X1TS U6889 ( .A(DP_OP_500J223_126_4510_n102), .B(
DP_OP_500J223_126_4510_n104), .Y(n5566) );
INVX2TS U6890 ( .A(n5566), .Y(n5558) );
NAND2X1TS U6891 ( .A(DP_OP_500J223_126_4510_n101), .B(n5192), .Y(n5562) );
INVX2TS U6892 ( .A(n5562), .Y(n5193) );
AOI21X1TS U6893 ( .A0(n5558), .A1(n2487), .B0(n5193), .Y(n5194) );
OAI21X1TS U6894 ( .A0(n5195), .A1(n5570), .B0(n5194), .Y(n5551) );
NAND2X1TS U6895 ( .A(n5197), .B(n5196), .Y(n5554) );
INVX2TS U6896 ( .A(n5554), .Y(n5198) );
AOI21X1TS U6897 ( .A0(n5551), .A1(n5555), .B0(n5198), .Y(n5199) );
NAND2X1TS U6898 ( .A(n5330), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n5203) );
NAND2X1TS U6899 ( .A(n2360), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n5202) );
NAND2X1TS U6900 ( .A(n5326), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n5201) );
AOI21X1TS U6901 ( .A0(n6801), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n5204) );
AOI22X1TS U6902 ( .A0(n5225), .A1(n5211), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n5210), .Y(n5212) );
OAI32X4TS U6903 ( .A0(n6016), .A1(n2340), .A2(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(n2336), .B1(n6016), .Y(n5386)
);
INVX2TS U6904 ( .A(n5215), .Y(n5216) );
OAI211X1TS U6905 ( .A0(n5218), .A1(n5217), .B0(n6713), .C0(n5216), .Y(n5229)
);
INVX2TS U6906 ( .A(n5219), .Y(n5227) );
AOI22X1TS U6907 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[14]), .A1(n5225), .B0(n5224),
.B1(n5223), .Y(n5226) );
OAI31X1TS U6908 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n6752), .A2(n5227),
.B0(n5226), .Y(n5228) );
AOI211X2TS U6909 ( .A0(n5231), .A1(n5230), .B0(n5229), .C0(n5228), .Y(n6015)
);
INVX2TS U6910 ( .A(n5265), .Y(n5394) );
OR2X2TS U6911 ( .A(n5235), .B(n5394), .Y(n6521) );
OA22X1TS U6912 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n5450), .B0(n5238),
.B1(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n5395) );
AOI22X1TS U6913 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n2348),
.B1(n5395), .Y(n5233) );
NAND2X2TS U6914 ( .A(n5235), .B(n5265), .Y(n5392) );
INVX2TS U6915 ( .A(n5238), .Y(n5325) );
NAND2X1TS U6916 ( .A(n5325), .B(n6780), .Y(n5241) );
NAND2X1TS U6917 ( .A(n2359), .B(n6869), .Y(n5240) );
OR2X1TS U6918 ( .A(n6713), .B(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n5239) );
NAND3X1TS U6919 ( .A(n5241), .B(n5240), .C(n5239), .Y(n5365) );
INVX2TS U6920 ( .A(n5365), .Y(n5319) );
AOI22X1TS U6921 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2351),
.B1(n5319), .Y(n5245) );
OAI22X1TS U6922 ( .A0(n5450), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(FPADDSUB_DmP_mant_SHT1_SW[17]),
.Y(n5242) );
MXI2X1TS U6923 ( .A(FPADDSUB_DmP_mant_SHT1_SW[19]), .B(
FPADDSUB_Raw_mant_NRM_SWR[21]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]),
.Y(n5243) );
AOI22X1TS U6924 ( .A0(n2206), .A1(n5361), .B0(n2354), .B1(n5362), .Y(n5244)
);
NAND2X1TS U6925 ( .A(n5325), .B(n6868), .Y(n5248) );
NAND2X1TS U6926 ( .A(n5387), .B(n6821), .Y(n5247) );
NAND2X1TS U6927 ( .A(n5325), .B(n6758), .Y(n5251) );
NAND2X1TS U6928 ( .A(n2360), .B(n6795), .Y(n5250) );
OR2X1TS U6929 ( .A(n5340), .B(FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n5249) );
NAND3X1TS U6930 ( .A(n5251), .B(n5250), .C(n5249), .Y(n5353) );
INVX2TS U6931 ( .A(n5353), .Y(n5262) );
AOI22X1TS U6932 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2352),
.B1(n5262), .Y(n5257) );
NAND2X1TS U6933 ( .A(n2360), .B(n6819), .Y(n5254) );
NAND2X1TS U6934 ( .A(n5330), .B(n2256), .Y(n5253) );
OAI22X1TS U6935 ( .A0(n6713), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n5450), .Y(n5255) );
AOI22X1TS U6936 ( .A0(n2348), .A1(n5355), .B0(n2354), .B1(n5350), .Y(n5256)
);
NAND2X1TS U6937 ( .A(n5387), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n5260) );
NAND2X1TS U6938 ( .A(n5330), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n5259) );
NAND2X1TS U6939 ( .A(n5326), .B(FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n5258) );
INVX2TS U6940 ( .A(n5261), .Y(n5354) );
AOI22X1TS U6941 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n2348),
.B1(n5354), .Y(n5264) );
AOI22X1TS U6942 ( .A0(n2354), .A1(n5262), .B0(n2351), .B1(n5355), .Y(n5263)
);
OAI22X1TS U6943 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n2336), .B0(n2340),
.B1(FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n5266) );
AOI22X1TS U6944 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n2353),
.B1(n5358), .Y(n5268) );
AOI222X4TS U6945 ( .A0(n6814), .A1(n7059), .B0(n7063), .B1(n5325), .C0(n6752), .C1(n2360), .Y(n5371) );
AOI22X1TS U6946 ( .A0(n5232), .A1(n5350), .B0(n2355), .B1(n5371), .Y(n5267)
);
AOI222X4TS U6947 ( .A0(n6815), .A1(n2341), .B0(n6752), .B1(n5330), .C0(n7063), .C1(n5387), .Y(n5374) );
AOI22X1TS U6948 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n2206),
.B1(n5374), .Y(n5272) );
OAI22X1TS U6949 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n5238), .B0(n2340),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n5269) );
OAI22X1TS U6950 ( .A0(n6713), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .B1(n5450), .Y(n5270) );
AOI22X1TS U6951 ( .A0(n2354), .A1(n5366), .B0(n2351), .B1(n5367), .Y(n5271)
);
NAND2X1TS U6952 ( .A(n5387), .B(n6853), .Y(n5275) );
NAND2X1TS U6953 ( .A(n5326), .B(n6854), .Y(n5274) );
AOI22X1TS U6954 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n5396),
.B1(n2353), .Y(n5281) );
NAND2X1TS U6955 ( .A(n5325), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n5279) );
NAND2X1TS U6956 ( .A(n2359), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n5278) );
NAND2X1TS U6957 ( .A(n5326), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n5277) );
NAND3X1TS U6958 ( .A(n5279), .B(n5278), .C(n5277), .Y(n5388) );
AOI22X1TS U6959 ( .A0(n2206), .A1(n5362), .B0(n2355), .B1(n5388), .Y(n5280)
);
OAI222X4TS U6960 ( .A0(n5238), .A1(FPADDSUB_Raw_mant_NRM_SWR[13]), .B0(n5450), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_DmP_mant_SHT1_SW[10]), .C1(
n6713), .Y(n5377) );
INVX2TS U6961 ( .A(n5282), .Y(n5373) );
AOI22X1TS U6962 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2206),
.B1(n5373), .Y(n5284) );
AOI22X1TS U6963 ( .A0(n2355), .A1(n5367), .B0(n2352), .B1(n5374), .Y(n5283)
);
AOI22X1TS U6964 ( .A0(FPADDSUB_intDX_EWSW[4]), .A1(n5313), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n6714), .Y(n5285) );
BUFX3TS U6965 ( .A(n6714), .Y(n5405) );
AOI22X1TS U6966 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n5405), .Y(n5286) );
AOI22X1TS U6967 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n5405), .Y(n5287) );
AOI22X1TS U6968 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n5405), .Y(n5288) );
AOI22X1TS U6969 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n5405), .Y(n5289) );
AOI22X1TS U6970 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n5405), .Y(n5290) );
AOI22X1TS U6971 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n5291), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n5405), .Y(n5292) );
AOI22X1TS U6972 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n5418), .Y(n5293) );
AOI22X1TS U6973 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n6829), .Y(n5294) );
AOI22X1TS U6974 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n6829), .Y(n5295) );
AOI22X1TS U6975 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n5418), .Y(n5296) );
AOI22X1TS U6976 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n5405), .Y(n5297) );
AOI22X1TS U6977 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n5418), .Y(n5298) );
AOI22X1TS U6978 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n5422), .Y(n5299) );
AOI22X1TS U6979 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n5427), .Y(n5300) );
AOI22X1TS U6980 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n5418), .Y(n5301) );
AOI22X1TS U6981 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n5418), .Y(n5302) );
AOI22X1TS U6982 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n5405), .Y(n5303) );
AOI22X1TS U6983 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n5418), .Y(n5304) );
AOI22X1TS U6984 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n5405), .Y(n5305) );
AOI22X1TS U6985 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n5418), .Y(n5306) );
AOI22X1TS U6986 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n5422), .Y(n5307) );
AOI22X1TS U6987 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n5308), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n5418), .Y(n5309) );
AOI22X1TS U6988 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n5422), .Y(n5311) );
AOI22X1TS U6989 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n5313), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n6714), .Y(n5314) );
AOI22X1TS U6990 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2353),
.B1(n5361), .Y(n5321) );
NAND2X1TS U6991 ( .A(n5330), .B(n6795), .Y(n5318) );
NAND2X1TS U6992 ( .A(n2360), .B(n6758), .Y(n5317) );
INVX2TS U6993 ( .A(n5370), .Y(n5346) );
AOI22X1TS U6994 ( .A0(n2338), .A1(n5346), .B0(n2354), .B1(n5319), .Y(n5320)
);
NAND2X1TS U6995 ( .A(n2360), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n5324) );
NAND2X1TS U6996 ( .A(n5330), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n5323) );
AOI22X1TS U6997 ( .A0(n5325), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n5379),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n5332) );
NAND2X1TS U6998 ( .A(n5387), .B(n6796), .Y(n5329) );
NAND2X1TS U6999 ( .A(n5325), .B(n6853), .Y(n5328) );
NAND2X1TS U7000 ( .A(n5326), .B(n6855), .Y(n5327) );
OAI2BB2X1TS U7001 ( .B0(n5450), .B1(n6793), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[24]), .A1N(n5330), .Y(n5339) );
AOI21X1TS U7002 ( .A0(n2354), .A1(n5382), .B0(n5339), .Y(n5331) );
AOI22X1TS U7003 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2206),
.B1(n5346), .Y(n5334) );
AOI22X1TS U7004 ( .A0(n2338), .A1(n5366), .B0(n2354), .B1(n5361), .Y(n5333)
);
INVX2TS U7005 ( .A(n2354), .Y(n5381) );
AOI22X1TS U7006 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n2351),
.B1(n5388), .Y(n5336) );
AOI22X1TS U7007 ( .A0(n2338), .A1(n5362), .B0(n2348), .B1(n5396), .Y(n5335)
);
AOI22X1TS U7008 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2353),
.B1(n5371), .Y(n5338) );
AOI22X1TS U7009 ( .A0(n2339), .A1(n5350), .B0(n2206), .B1(n5358), .Y(n5337)
);
AOI22X1TS U7010 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n2339),
.B1(n5339), .Y(n5343) );
OAI22X1TS U7011 ( .A0(n2336), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(n5340),
.B1(FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n5341) );
AOI22X1TS U7012 ( .A0(n2355), .A1(n5378), .B0(n2351), .B1(n5382), .Y(n5342)
);
AOI22X1TS U7013 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2339),
.B1(n5382), .Y(n5345) );
AOI22X1TS U7014 ( .A0(n2348), .A1(n5378), .B0(n2355), .B1(n5354), .Y(n5344)
);
AOI22X1TS U7015 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2338),
.B1(n5367), .Y(n5348) );
AOI22X1TS U7016 ( .A0(n2206), .A1(n5366), .B0(n2351), .B1(n5346), .Y(n5347)
);
AOI22X1TS U7017 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2339),
.B1(n5355), .Y(n5352) );
AOI22X1TS U7018 ( .A0(n2355), .A1(n5358), .B0(n2352), .B1(n5350), .Y(n5351)
);
AOI22X1TS U7019 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2338),
.B1(n5378), .Y(n5357) );
AOI22X1TS U7020 ( .A0(n2355), .A1(n5355), .B0(n2353), .B1(n5354), .Y(n5356)
);
AOI22X1TS U7021 ( .A0(n2206), .A1(n5371), .B0(n2355), .B1(n5373), .Y(n5359)
);
AOI22X1TS U7022 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n2338),
.B1(n5361), .Y(n5364) );
AOI22X1TS U7023 ( .A0(n2354), .A1(n5396), .B0(n2353), .B1(n5362), .Y(n5363)
);
AOI22X1TS U7024 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2339),
.B1(n5374), .Y(n5369) );
AOI22X1TS U7025 ( .A0(n2206), .A1(n5367), .B0(n2351), .B1(n5366), .Y(n5368)
);
AOI22X1TS U7026 ( .A0(n5372), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2339),
.B1(n5371), .Y(n5376) );
AOI22X1TS U7027 ( .A0(n2355), .A1(n5374), .B0(n2352), .B1(n5373), .Y(n5375)
);
AOI22X1TS U7028 ( .A0(n5379), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2352),
.B1(n5378), .Y(n5384) );
AOI2BB2X1TS U7029 ( .B0(n2206), .B1(n5382), .A0N(n5381), .A1N(n5380), .Y(
n5383) );
OAI211X1TS U7030 ( .A0(n5385), .A1(n5389), .B0(n5384), .C0(n5383), .Y(n1789)
);
INVX2TS U7031 ( .A(n5388), .Y(n5400) );
OAI22X1TS U7032 ( .A0(n5400), .A1(n5389), .B0(n5393), .B1(n5399), .Y(n5390)
);
AOI21X1TS U7033 ( .A0(n5394), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n5390),
.Y(n5391) );
OAI21X1TS U7034 ( .A0(n6522), .A1(n5392), .B0(n5391), .Y(n1810) );
AOI2BB2X1TS U7035 ( .B0(n5394), .B1(FPADDSUB_Data_array_SWR[22]), .A0N(n5237), .A1N(n5393), .Y(n5398) );
AOI22X1TS U7036 ( .A0(n2339), .A1(n5396), .B0(n2354), .B1(n5395), .Y(n5397)
);
AOI22X1TS U7037 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n6668), .Y(n5401) );
AOI22X1TS U7038 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n6668), .Y(n5402) );
AOI22X1TS U7039 ( .A0(FPADDSUB_intDY_EWSW[26]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[26]), .B1(n6668), .Y(n5403) );
AOI22X1TS U7040 ( .A0(FPADDSUB_intDY_EWSW[25]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[25]), .B1(n6668), .Y(n5404) );
AOI22X1TS U7041 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n5405), .Y(n5406) );
AOI22X1TS U7042 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n5422), .Y(n5407) );
AOI22X1TS U7043 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n5422), .Y(n5408) );
BUFX3TS U7044 ( .A(n2577), .Y(n5436) );
AOI22X1TS U7045 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n5427), .Y(n5409) );
AOI22X1TS U7046 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n5427), .Y(n5410) );
AOI22X1TS U7047 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n5427), .Y(n5411) );
AOI22X1TS U7048 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n6708), .Y(n5412) );
AOI22X1TS U7049 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n6714), .Y(n5413) );
AOI22X1TS U7050 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n5422), .Y(n5414) );
AOI22X1TS U7051 ( .A0(FPADDSUB_intDY_EWSW[24]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[24]), .B1(n6668), .Y(n5415) );
AOI22X1TS U7052 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n6668), .Y(n5416) );
AOI22X1TS U7053 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n6708), .Y(n5417) );
AOI22X1TS U7054 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n5418), .Y(n5419) );
AOI22X1TS U7055 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n5427), .Y(n5420) );
AOI22X1TS U7056 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n5427), .Y(n5421) );
AOI22X1TS U7057 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n5422), .Y(n5423) );
AOI22X1TS U7058 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n5424), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n5422), .Y(n5425) );
AOI22X1TS U7059 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n5427), .Y(n5428) );
AOI22X1TS U7060 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n2224), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n5427), .Y(n5429) );
AOI22X1TS U7061 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4321), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n6714), .Y(n5430) );
AOI22X1TS U7062 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n6829), .Y(n5431) );
AOI22X1TS U7063 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n6714), .Y(n5432) );
AOI22X1TS U7064 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n5434), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n6829), .Y(n5435) );
NOR2X1TS U7065 ( .A(n2305), .B(n5611), .Y(DP_OP_500J223_126_4510_n161) );
NAND2X1TS U7066 ( .A(n5750), .B(n6770), .Y(n5437) );
NAND2X1TS U7067 ( .A(FPMULT_Op_MX[6]), .B(n5644), .Y(n5778) );
NOR2X1TS U7068 ( .A(n5437), .B(n5778), .Y(n5758) );
NOR2X1TS U7069 ( .A(n6794), .B(n6770), .Y(n5472) );
INVX2TS U7070 ( .A(n5472), .Y(n5779) );
NOR2X1TS U7071 ( .A(n5779), .B(n5778), .Y(n5777) );
NOR2X1TS U7072 ( .A(n2305), .B(n5620), .Y(DP_OP_500J223_126_4510_n185) );
INVX2TS U7073 ( .A(n5440), .Y(n5438) );
NAND2X1TS U7074 ( .A(n5439), .B(n5438), .Y(n5441) );
NOR2X2TS U7075 ( .A(n5444), .B(n5443), .Y(n5659) );
XNOR2X1TS U7076 ( .A(n5446), .B(n5445), .Y(n5447) );
XNOR2X1TS U7077 ( .A(n5448), .B(n5447), .Y(n5661) );
OAI21X1TS U7078 ( .A0(n5660), .A1(n5659), .B0(n5449), .Y(mult_x_309_n17) );
AND3X2TS U7079 ( .A(n6756), .B(FPSENCOS_cont_var_out[1]), .C(ready_add_subt),
.Y(n6386) );
INVX2TS U7080 ( .A(n6386), .Y(n6538) );
NOR2XLTS U7081 ( .A(n6347), .B(n6538), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
OAI21XLTS U7082 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n6766), .B0(n5450),
.Y(n1350) );
OAI222X1TS U7083 ( .A0(n6787), .A1(n5455), .B0(n5454), .B1(n5453), .C0(n5452), .C1(n5451), .Y(n1691) );
AOI21X1TS U7084 ( .A0(ack_operation), .A1(n5457), .B0(n5456), .Y(n6566) );
AOI21X1TS U7085 ( .A0(FPMULT_zero_flag), .A1(n2382), .B0(n6566), .Y(n5459)
);
NOR3X1TS U7086 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .C(n6772), .Y(n6352) );
AOI31XLTS U7087 ( .A0(n5461), .A1(n6351), .A2(n6850), .B0(n6352), .Y(n5462)
);
OAI21XLTS U7088 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
n6012), .B0(n5462), .Y(n2149) );
OAI21XLTS U7089 ( .A0(n5463), .A1(n6346), .B0(n6442), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
NAND2X1TS U7090 ( .A(n5472), .B(n7065), .Y(n5780) );
NAND2X1TS U7091 ( .A(FPMULT_Op_MX[6]), .B(n6584), .Y(n5757) );
CLKAND2X2TS U7092 ( .A(n5780), .B(n5473), .Y(n6870) );
NAND2X1TS U7093 ( .A(n5738), .B(n7066), .Y(n5739) );
NAND2X1TS U7094 ( .A(n5649), .B(FPMULT_Op_MX[12]), .Y(n5735) );
CLKAND2X2TS U7095 ( .A(n5739), .B(n5474), .Y(n6905) );
NAND2X1TS U7096 ( .A(n5841), .B(n7064), .Y(n5842) );
NAND2X1TS U7097 ( .A(n2220), .B(n6568), .Y(n5838) );
CLKAND2X2TS U7098 ( .A(n5842), .B(n5475), .Y(n6906) );
BUFX3TS U7099 ( .A(n6735), .Y(n6740) );
INVX2TS U7100 ( .A(n5479), .Y(n5482) );
INVX2TS U7101 ( .A(n5480), .Y(n5481) );
NAND2X1TS U7102 ( .A(n5484), .B(n5483), .Y(n5485) );
XNOR2X1TS U7103 ( .A(n5486), .B(n5485), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
INVX2TS U7104 ( .A(n5487), .Y(n5498) );
NAND2X1TS U7105 ( .A(n5498), .B(n5489), .Y(n5492) );
INVX2TS U7106 ( .A(n5497), .Y(n5490) );
AOI21X1TS U7107 ( .A0(n5490), .A1(n5489), .B0(n5488), .Y(n5491) );
NAND2X1TS U7108 ( .A(n5494), .B(n5493), .Y(n5495) );
XNOR2X1TS U7109 ( .A(n5496), .B(n5495), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
NAND2X1TS U7110 ( .A(n5498), .B(n5497), .Y(n5499) );
INVX2TS U7111 ( .A(n5501), .Y(n5510) );
INVX2TS U7112 ( .A(n5502), .Y(n5504) );
NAND2X1TS U7113 ( .A(n5504), .B(n5503), .Y(n5505) );
XNOR2X1TS U7114 ( .A(n5506), .B(n5505), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
INVX2TS U7115 ( .A(n5507), .Y(n5509) );
NAND2X1TS U7116 ( .A(n5509), .B(n5508), .Y(n5511) );
INVX2TS U7117 ( .A(n5512), .Y(n5514) );
NAND2X1TS U7118 ( .A(n5514), .B(n5513), .Y(n5516) );
NAND2X1TS U7119 ( .A(n2472), .B(n5517), .Y(n5519) );
XNOR2X1TS U7120 ( .A(n5519), .B(n5518), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
INVX2TS U7121 ( .A(n5520), .Y(n5522) );
NAND2X1TS U7122 ( .A(n5522), .B(n5521), .Y(n5524) );
INVX2TS U7123 ( .A(n5525), .Y(n5527) );
NAND2X1TS U7124 ( .A(n5527), .B(n5526), .Y(n5529) );
NAND2X1TS U7125 ( .A(n5531), .B(n5530), .Y(n5533) );
XNOR2X1TS U7126 ( .A(n5533), .B(n5532), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
OAI22X1TS U7127 ( .A0(n5546), .A1(n5536), .B0(n2321), .B1(n5534), .Y(
DP_OP_502J223_128_4510_n147) );
OAI22X1TS U7128 ( .A0(n2314), .A1(n5536), .B0(n2377), .B1(n5534), .Y(
DP_OP_502J223_128_4510_n150) );
OAI22X1TS U7129 ( .A0(n2377), .A1(n5536), .B0(n5535), .B1(n5534), .Y(
DP_OP_502J223_128_4510_n151) );
OAI22X1TS U7130 ( .A0(n5546), .A1(n5537), .B0(n2303), .B1(n5538), .Y(
DP_OP_502J223_128_4510_n154) );
OAI22X1TS U7131 ( .A0(n5546), .A1(n5538), .B0(n2321), .B1(n5537), .Y(
DP_OP_502J223_128_4510_n155) );
OAI22X1TS U7132 ( .A0(n5548), .A1(n5538), .B0(n2314), .B1(n5537), .Y(
DP_OP_502J223_128_4510_n157) );
OAI22X1TS U7133 ( .A0(n2313), .A1(n5538), .B0(n2377), .B1(n5537), .Y(
DP_OP_502J223_128_4510_n158) );
OAI22X1TS U7134 ( .A0(n5546), .A1(n5539), .B0(n2304), .B1(n5540), .Y(
DP_OP_502J223_128_4510_n162) );
OAI22X1TS U7135 ( .A0(n2321), .A1(n5540), .B0(n2379), .B1(n5539), .Y(
DP_OP_502J223_128_4510_n164) );
OAI22X1TS U7136 ( .A0(n5548), .A1(n5540), .B0(n2314), .B1(n5539), .Y(
DP_OP_502J223_128_4510_n165) );
OAI22X1TS U7137 ( .A0(n2381), .A1(n5541), .B0(n2304), .B1(n5543), .Y(
DP_OP_502J223_128_4510_n170) );
OAI22X1TS U7138 ( .A0(n2381), .A1(n5543), .B0(n2321), .B1(n5541), .Y(
DP_OP_502J223_128_4510_n171) );
OAI22X1TS U7139 ( .A0(n2321), .A1(n5543), .B0(n2379), .B1(n5541), .Y(
DP_OP_502J223_128_4510_n172) );
OAI22X1TS U7140 ( .A0(n2313), .A1(n5543), .B0(n2377), .B1(n5541), .Y(
DP_OP_502J223_128_4510_n174) );
OAI22X1TS U7141 ( .A0(n5546), .A1(n5544), .B0(n2304), .B1(n5545), .Y(
DP_OP_502J223_128_4510_n178) );
OAI22X1TS U7142 ( .A0(n5546), .A1(n5545), .B0(n2320), .B1(n5544), .Y(
DP_OP_502J223_128_4510_n179) );
OAI22X1TS U7143 ( .A0(n5548), .A1(n5545), .B0(n2314), .B1(n5544), .Y(
DP_OP_502J223_128_4510_n181) );
OAI22X1TS U7144 ( .A0(n5546), .A1(n5547), .B0(n2303), .B1(n5549), .Y(
DP_OP_502J223_128_4510_n186) );
OAI22X1TS U7145 ( .A0(n5546), .A1(n5549), .B0(n2321), .B1(n5547), .Y(
DP_OP_502J223_128_4510_n187) );
OAI22X1TS U7146 ( .A0(n2320), .A1(n5549), .B0(n5548), .B1(n5547), .Y(
DP_OP_502J223_128_4510_n188) );
INVX2TS U7147 ( .A(n5550), .Y(n5553) );
INVX2TS U7148 ( .A(n5551), .Y(n5552) );
NAND2X1TS U7149 ( .A(n5555), .B(n5554), .Y(n5556) );
XNOR2X1TS U7150 ( .A(n5557), .B(n5556), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
INVX2TS U7151 ( .A(n5565), .Y(n5571) );
NAND2X1TS U7152 ( .A(n5571), .B(n5567), .Y(n5561) );
INVX2TS U7153 ( .A(n5570), .Y(n5559) );
AOI21X1TS U7154 ( .A0(n5559), .A1(n5567), .B0(n5558), .Y(n5560) );
NAND2X1TS U7155 ( .A(n2487), .B(n5562), .Y(n5563) );
NAND2X1TS U7156 ( .A(n5567), .B(n5566), .Y(n5568) );
XNOR2X1TS U7157 ( .A(n5569), .B(n5568), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
NAND2X1TS U7158 ( .A(n5571), .B(n5570), .Y(n5572) );
INVX2TS U7159 ( .A(n5574), .Y(n5583) );
INVX2TS U7160 ( .A(n5575), .Y(n5577) );
NAND2X1TS U7161 ( .A(n5577), .B(n5576), .Y(n5578) );
XNOR2X1TS U7162 ( .A(n5579), .B(n5578), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
INVX2TS U7163 ( .A(n5580), .Y(n5582) );
NAND2X1TS U7164 ( .A(n5582), .B(n5581), .Y(n5584) );
INVX2TS U7165 ( .A(n5585), .Y(n5587) );
NAND2X1TS U7166 ( .A(n5587), .B(n5586), .Y(n5589) );
NAND2X1TS U7167 ( .A(n5591), .B(n5590), .Y(n5593) );
XNOR2X1TS U7168 ( .A(n5593), .B(n5592), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
INVX2TS U7169 ( .A(n5594), .Y(n5596) );
NAND2X1TS U7170 ( .A(n5596), .B(n5595), .Y(n5598) );
INVX2TS U7171 ( .A(n5599), .Y(n5601) );
NAND2X1TS U7172 ( .A(n5601), .B(n5600), .Y(n5603) );
NAND2X1TS U7173 ( .A(n5605), .B(n5604), .Y(n5607) );
XNOR2X1TS U7174 ( .A(n5607), .B(n5606), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
OAI22X1TS U7175 ( .A0(n5619), .A1(FPMULT_Op_MX[17]), .B0(n2318), .B1(n2405),
.Y(DP_OP_500J223_126_4510_n147) );
OAI22X1TS U7176 ( .A0(n5617), .A1(n2344), .B0(n2376), .B1(n2405), .Y(
DP_OP_500J223_126_4510_n150) );
OAI22X1TS U7177 ( .A0(n2376), .A1(FPMULT_Op_MX[17]), .B0(n5608), .B1(n2405),
.Y(DP_OP_500J223_126_4510_n151) );
OAI22X1TS U7178 ( .A0(n5619), .A1(n5609), .B0(n2305), .B1(n5610), .Y(
DP_OP_500J223_126_4510_n154) );
OAI22X1TS U7179 ( .A0(n5619), .A1(n5610), .B0(n2319), .B1(n5609), .Y(
DP_OP_500J223_126_4510_n155) );
OAI22X1TS U7180 ( .A0(n5621), .A1(n5610), .B0(n5617), .B1(n5609), .Y(
DP_OP_500J223_126_4510_n157) );
OAI22X1TS U7181 ( .A0(n2310), .A1(n5610), .B0(n2376), .B1(n5609), .Y(
DP_OP_500J223_126_4510_n158) );
OAI22X1TS U7182 ( .A0(n5619), .A1(n5611), .B0(n2306), .B1(n5612), .Y(
DP_OP_500J223_126_4510_n162) );
OAI22X1TS U7183 ( .A0(n2319), .A1(n5612), .B0(n2378), .B1(n5611), .Y(
DP_OP_500J223_126_4510_n164) );
OAI22X1TS U7184 ( .A0(n5621), .A1(n5612), .B0(n5617), .B1(n5611), .Y(
DP_OP_500J223_126_4510_n165) );
OAI22X1TS U7185 ( .A0(n2380), .A1(n5613), .B0(n2306), .B1(n5615), .Y(
DP_OP_500J223_126_4510_n170) );
OAI22X1TS U7186 ( .A0(n2380), .A1(n5615), .B0(n2319), .B1(n5613), .Y(
DP_OP_500J223_126_4510_n171) );
OAI22X1TS U7187 ( .A0(n2319), .A1(n5615), .B0(n2378), .B1(n5613), .Y(
DP_OP_500J223_126_4510_n172) );
OAI22X1TS U7188 ( .A0(n2310), .A1(n5615), .B0(n2376), .B1(n5613), .Y(
DP_OP_500J223_126_4510_n174) );
OAI22X1TS U7189 ( .A0(n2380), .A1(n5616), .B0(n2306), .B1(n5618), .Y(
DP_OP_500J223_126_4510_n178) );
OAI22X1TS U7190 ( .A0(n5619), .A1(n5618), .B0(n2319), .B1(n5616), .Y(
DP_OP_500J223_126_4510_n179) );
OAI22X1TS U7191 ( .A0(n2318), .A1(n5618), .B0(n5621), .B1(n5616), .Y(
DP_OP_500J223_126_4510_n180) );
OAI22X1TS U7192 ( .A0(n5621), .A1(n5618), .B0(n2310), .B1(n5616), .Y(
DP_OP_500J223_126_4510_n181) );
OAI22X1TS U7193 ( .A0(n5619), .A1(n5620), .B0(n2306), .B1(n5622), .Y(
DP_OP_500J223_126_4510_n186) );
OAI22X1TS U7194 ( .A0(n5619), .A1(n5622), .B0(n2319), .B1(n5620), .Y(
DP_OP_500J223_126_4510_n187) );
OAI22X1TS U7195 ( .A0(n2319), .A1(n5622), .B0(n2378), .B1(n5620), .Y(
DP_OP_500J223_126_4510_n188) );
NOR3BX1TS U7196 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n5623) );
XOR2X1TS U7197 ( .A(n2382), .B(n5623), .Y(DP_OP_234J223_132_4955_n15) );
OR2X2TS U7198 ( .A(FPMULT_FSM_selector_B[1]), .B(n6781), .Y(n5630) );
OAI2BB1X1TS U7199 ( .A0N(FPMULT_Op_MY[29]), .A1N(n6784), .B0(n5630), .Y(
n5624) );
XOR2X1TS U7200 ( .A(n2382), .B(n5624), .Y(DP_OP_234J223_132_4955_n16) );
OAI2BB1X1TS U7201 ( .A0N(FPMULT_Op_MY[28]), .A1N(n6784), .B0(n5630), .Y(
n5625) );
XOR2X1TS U7202 ( .A(n2382), .B(n5625), .Y(DP_OP_234J223_132_4955_n17) );
OAI2BB1X1TS U7203 ( .A0N(FPMULT_Op_MY[27]), .A1N(n6784), .B0(n5630), .Y(
n5626) );
XOR2X1TS U7204 ( .A(n2382), .B(n5626), .Y(DP_OP_234J223_132_4955_n18) );
OAI2BB1X1TS U7205 ( .A0N(FPMULT_Op_MY[26]), .A1N(n6784), .B0(n5630), .Y(
n5627) );
XOR2X1TS U7206 ( .A(n2382), .B(n5627), .Y(DP_OP_234J223_132_4955_n19) );
OAI2BB1X1TS U7207 ( .A0N(FPMULT_Op_MY[25]), .A1N(n6784), .B0(n5630), .Y(
n5628) );
XOR2X1TS U7208 ( .A(n2382), .B(n5628), .Y(DP_OP_234J223_132_4955_n20) );
OAI2BB1X1TS U7209 ( .A0N(FPMULT_Op_MY[24]), .A1N(n6784), .B0(n5630), .Y(
n5629) );
XOR2X1TS U7210 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n5629), .Y(
DP_OP_234J223_132_4955_n21) );
XOR2X1TS U7211 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n5632), .Y(
DP_OP_234J223_132_4955_n22) );
NOR2BX1TS U7212 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5633) );
XOR2X1TS U7213 ( .A(n6766), .B(n5633), .Y(DP_OP_26J223_129_1325_n14) );
NOR2BX1TS U7214 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5634) );
XOR2X1TS U7215 ( .A(n6766), .B(n5634), .Y(DP_OP_26J223_129_1325_n15) );
NOR2BX1TS U7216 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5635) );
XOR2X1TS U7217 ( .A(n6766), .B(n5635), .Y(DP_OP_26J223_129_1325_n16) );
NOR2BX1TS U7218 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n5636) );
XOR2X1TS U7219 ( .A(n6766), .B(n5636), .Y(DP_OP_26J223_129_1325_n17) );
XOR2X1TS U7220 ( .A(n6766), .B(n2502), .Y(DP_OP_26J223_129_1325_n18) );
XOR2X1TS U7221 ( .A(n5652), .B(n5651), .Y(n5654) );
XNOR2X1TS U7222 ( .A(n5654), .B(n5653), .Y(mult_x_309_n37) );
XNOR2X1TS U7223 ( .A(n5656), .B(n5655), .Y(n5657) );
XNOR2X1TS U7224 ( .A(n5658), .B(n5657), .Y(mult_x_309_n15) );
XOR2X1TS U7225 ( .A(n5660), .B(n5659), .Y(n5662) );
XNOR2X1TS U7226 ( .A(n5662), .B(n5661), .Y(mult_x_309_n18) );
XOR2X1TS U7227 ( .A(n5664), .B(n5663), .Y(n5666) );
XOR2X1TS U7228 ( .A(n5666), .B(n5665), .Y(mult_x_309_n23) );
XOR2X1TS U7229 ( .A(n5668), .B(n5667), .Y(n5670) );
XNOR2X1TS U7230 ( .A(n5670), .B(n5669), .Y(mult_x_309_n30) );
NAND2X1TS U7231 ( .A(FPMULT_Op_MX[18]), .B(n6753), .Y(n5682) );
NOR2BX1TS U7232 ( .AN(n5682), .B(n5671), .Y(n5673) );
XOR2X1TS U7233 ( .A(n5673), .B(n5672), .Y(intadd_515_CI) );
INVX2TS U7234 ( .A(n5674), .Y(n5680) );
AOI21X1TS U7235 ( .A0(n5680), .A1(n2478), .B0(n5675), .Y(n5676) );
NAND2X1TS U7236 ( .A(n2291), .B(FPMULT_Op_MX[19]), .Y(n5681) );
AOI21X1TS U7237 ( .A0(n5682), .A1(n5681), .B0(n5680), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1) );
NOR2BX2TS U7238 ( .AN(n5684), .B(n5683), .Y(n5720) );
INVX2TS U7239 ( .A(n5687), .Y(n5685) );
NAND2X1TS U7240 ( .A(n5685), .B(n5686), .Y(n5689) );
INVX2TS U7241 ( .A(n5686), .Y(n5688) );
XNOR2X1TS U7242 ( .A(n5692), .B(n5691), .Y(n5694) );
XOR2X1TS U7243 ( .A(n5694), .B(n5693), .Y(n5719) );
INVX2TS U7244 ( .A(n5721), .Y(n5696) );
INVX2TS U7245 ( .A(n5720), .Y(n5695) );
OAI22X1TS U7246 ( .A0(n5697), .A1(n5719), .B0(n5696), .B1(n5695), .Y(
intadd_512_A_6_) );
INVX2TS U7247 ( .A(n5699), .Y(n5703) );
INVX2TS U7248 ( .A(n5702), .Y(n5700) );
OAI21X1TS U7249 ( .A0(n5703), .A1(n5702), .B0(n5701), .Y(n5728) );
OAI21X1TS U7250 ( .A0(n5706), .A1(n5705), .B0(n5704), .Y(n5727) );
XNOR2X1TS U7251 ( .A(n5708), .B(n5707), .Y(n5709) );
ACHCINX2TS U7252 ( .CIN(n5728), .A(n5727), .B(n5729), .CO(intadd_512_A_4_)
);
XNOR2X1TS U7253 ( .A(n5711), .B(n5714), .Y(n5713) );
XOR2X1TS U7254 ( .A(n5713), .B(n5712), .Y(intadd_512_A_1_) );
NOR2BX1TS U7255 ( .AN(n5718), .B(n5717), .Y(intadd_512_B_7_) );
XOR2X1TS U7256 ( .A(n5720), .B(n5719), .Y(n5722) );
XNOR2X1TS U7257 ( .A(n5722), .B(n5721), .Y(intadd_512_B_5_) );
XOR2X1TS U7258 ( .A(n5724), .B(n5723), .Y(n5726) );
XNOR2X1TS U7259 ( .A(n5726), .B(n5725), .Y(intadd_512_B_4_) );
XOR2X1TS U7260 ( .A(n5728), .B(n5727), .Y(n5730) );
XNOR2X1TS U7261 ( .A(n5730), .B(n5729), .Y(intadd_512_B_3_) );
XOR2X1TS U7262 ( .A(n5732), .B(n5731), .Y(n5734) );
XOR2X1TS U7263 ( .A(n5734), .B(n5733), .Y(intadd_512_B_2_) );
NAND2X1TS U7264 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MX[12]), .Y(n5737) );
INVX2TS U7265 ( .A(n5737), .Y(n5736) );
NOR2X1TS U7266 ( .A(n5741), .B(n5742), .Y(n5740) );
AOI21X1TS U7267 ( .A0(n5736), .A1(n5738), .B0(n5740), .Y(intadd_512_B_1_) );
OAI21X1TS U7268 ( .A0(n2484), .A1(n2257), .B0(n5739), .Y(n5743) );
XNOR2X1TS U7269 ( .A(n5738), .B(n5737), .Y(n5745) );
NOR2X1TS U7270 ( .A(n5739), .B(n2257), .Y(n5744) );
AOI21X1TS U7271 ( .A0(n5743), .A1(n5745), .B0(n5744), .Y(intadd_512_B_0_) );
XNOR2X1TS U7272 ( .A(n5746), .B(n5745), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
NAND2X1TS U7273 ( .A(FPMULT_Op_MX[8]), .B(n6584), .Y(n5782) );
NOR2X2TS U7274 ( .A(n5783), .B(n5782), .Y(n5781) );
AOI22X1TS U7275 ( .A0(DP_OP_501J223_127_5235_n944), .A1(n6584), .B0(
DP_OP_501J223_127_5235_n903), .B1(n6572), .Y(n5747) );
XNOR2X1TS U7276 ( .A(n5750), .B(n5749), .Y(n5752) );
XOR2X1TS U7277 ( .A(n5752), .B(n5751), .Y(n5756) );
OAI2BB1X1TS U7278 ( .A0N(n5781), .A1N(n5754), .B0(n5753), .Y(mult_x_311_n36)
);
XOR2X1TS U7279 ( .A(n5754), .B(n5781), .Y(n5755) );
XOR2X1TS U7280 ( .A(n5756), .B(n5755), .Y(mult_x_311_n37) );
AOI21X1TS U7281 ( .A0(n5760), .A1(n5759), .B0(n5758), .Y(intadd_513_A_0_) );
XNOR2X1TS U7282 ( .A(n5762), .B(n5761), .Y(n5764) );
XOR2X1TS U7283 ( .A(n5764), .B(n5763), .Y(mult_x_311_n15) );
XOR2X1TS U7284 ( .A(n5766), .B(n5765), .Y(n5768) );
XNOR2X1TS U7285 ( .A(n5768), .B(n5767), .Y(mult_x_311_n18) );
XNOR2X1TS U7286 ( .A(n5770), .B(n5769), .Y(n5772) );
XOR2X1TS U7287 ( .A(n5772), .B(n5771), .Y(mult_x_311_n23) );
XOR2X1TS U7288 ( .A(n5774), .B(n5773), .Y(n5776) );
XOR2X1TS U7289 ( .A(n5776), .B(n5775), .Y(mult_x_311_n30) );
AOI21X1TS U7290 ( .A0(n5779), .A1(n5778), .B0(n5777), .Y(n5786) );
OAI21X1TS U7291 ( .A0(n6765), .A1(n2259), .B0(n5780), .Y(n5784) );
OAI2BB1X1TS U7292 ( .A0N(n5786), .A1N(n5784), .B0(n5785), .Y(intadd_513_B_0_) );
AOI21X1TS U7293 ( .A0(n5783), .A1(n5782), .B0(n5781), .Y(intadd_513_CI) );
NAND2X1TS U7294 ( .A(n5785), .B(n5784), .Y(n5787) );
XNOR2X1TS U7295 ( .A(n5787), .B(n5786), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
NOR2BX2TS U7296 ( .AN(n5789), .B(n5788), .Y(n5823) );
INVX2TS U7297 ( .A(n5792), .Y(n5790) );
NAND2X1TS U7298 ( .A(n5790), .B(n5791), .Y(n5794) );
INVX2TS U7299 ( .A(n5791), .Y(n5793) );
XNOR2X1TS U7300 ( .A(n5797), .B(n5796), .Y(n5799) );
XOR2X1TS U7301 ( .A(n5799), .B(n5798), .Y(n5822) );
INVX2TS U7302 ( .A(n5824), .Y(n5801) );
INVX2TS U7303 ( .A(n5823), .Y(n5800) );
OAI22X1TS U7304 ( .A0(n5802), .A1(n5822), .B0(n5801), .B1(n5800), .Y(
intadd_514_A_6_) );
INVX2TS U7305 ( .A(n5804), .Y(n5808) );
INVX2TS U7306 ( .A(n5807), .Y(n5805) );
OAI21X1TS U7307 ( .A0(n5808), .A1(n5807), .B0(n5806), .Y(n5831) );
OAI21X1TS U7308 ( .A0(n5811), .A1(n5810), .B0(n5809), .Y(n5830) );
XNOR2X1TS U7309 ( .A(n5813), .B(n5812), .Y(n5814) );
ACHCINX2TS U7310 ( .CIN(n5831), .A(n5830), .B(n5832), .CO(intadd_514_A_4_)
);
XNOR2X1TS U7311 ( .A(n5817), .B(n5816), .Y(n5819) );
XOR2X1TS U7312 ( .A(n5819), .B(n5818), .Y(intadd_514_A_1_) );
NOR2BX1TS U7313 ( .AN(n5821), .B(n5820), .Y(intadd_514_B_7_) );
XOR2X1TS U7314 ( .A(n5823), .B(n5822), .Y(n5825) );
XNOR2X1TS U7315 ( .A(n5825), .B(n5824), .Y(intadd_514_B_5_) );
XOR2X1TS U7316 ( .A(n5827), .B(n5826), .Y(n5829) );
XNOR2X1TS U7317 ( .A(n5829), .B(n5828), .Y(intadd_514_B_4_) );
XOR2X1TS U7318 ( .A(n5831), .B(n5830), .Y(n5833) );
XNOR2X1TS U7319 ( .A(n5833), .B(n5832), .Y(intadd_514_B_3_) );
XOR2X1TS U7320 ( .A(n5835), .B(n5834), .Y(n5837) );
XOR2X1TS U7321 ( .A(n5837), .B(n5836), .Y(intadd_514_B_2_) );
NAND2X1TS U7322 ( .A(FPMULT_Op_MY[2]), .B(n6568), .Y(n5840) );
INVX2TS U7323 ( .A(n5840), .Y(n5839) );
NOR2X1TS U7324 ( .A(n5844), .B(n5845), .Y(n5843) );
AOI21X1TS U7325 ( .A0(n5839), .A1(n5841), .B0(n5843), .Y(intadd_514_B_1_) );
OAI21X1TS U7326 ( .A0(n7062), .A1(n2258), .B0(n5842), .Y(n5846) );
XNOR2X1TS U7327 ( .A(n5841), .B(n5840), .Y(n5848) );
NOR2X1TS U7328 ( .A(n5842), .B(n2258), .Y(n5847) );
AOI21X1TS U7329 ( .A0(n5846), .A1(n5848), .B0(n5847), .Y(intadd_514_B_0_) );
XNOR2X1TS U7330 ( .A(n5849), .B(n5848), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
NOR2X1TS U7331 ( .A(n6759), .B(n6789), .Y(n5883) );
NAND2X1TS U7332 ( .A(n5883), .B(FPMULT_Sgf_normalized_result[10]), .Y(n5854)
);
INVX2TS U7333 ( .A(n5876), .Y(n5873) );
AHHCINX2TS U7334 ( .A(FPMULT_Sgf_normalized_result[22]), .CIN(n5856), .S(
n5857), .CO(n5930) );
AHHCONX2TS U7335 ( .A(FPMULT_Sgf_normalized_result[21]), .CI(n5858), .CON(
n5856), .S(n5859) );
AHHCINX2TS U7336 ( .A(FPMULT_Sgf_normalized_result[20]), .CIN(n5860), .S(
n5861), .CO(n5858) );
AHHCONX2TS U7337 ( .A(FPMULT_Sgf_normalized_result[19]), .CI(n5862), .CON(
n5860), .S(n5863) );
AHHCINX2TS U7338 ( .A(FPMULT_Sgf_normalized_result[18]), .CIN(n5864), .S(
n5865), .CO(n5862) );
AHHCONX2TS U7339 ( .A(FPMULT_Sgf_normalized_result[17]), .CI(n5866), .CON(
n5864), .S(n5867) );
AHHCINX2TS U7340 ( .A(FPMULT_Sgf_normalized_result[16]), .CIN(n5868), .S(
n5869), .CO(n5866) );
AHHCONX2TS U7341 ( .A(FPMULT_Sgf_normalized_result[15]), .CI(n5870), .CON(
n5868), .S(n5871) );
AHHCINX2TS U7342 ( .A(FPMULT_Sgf_normalized_result[14]), .CIN(n5872), .S(
n5874), .CO(n5870) );
AHHCONX2TS U7343 ( .A(FPMULT_Sgf_normalized_result[13]), .CI(n5875), .CON(
n5872), .S(n5877) );
AHHCINX2TS U7344 ( .A(FPMULT_Sgf_normalized_result[12]), .CIN(n5878), .S(
n5879), .CO(n5875) );
AHHCONX2TS U7345 ( .A(FPMULT_Sgf_normalized_result[11]), .CI(n5880), .CON(
n5878), .S(n5881) );
INVX2TS U7346 ( .A(n5882), .Y(n5888) );
NAND2X1TS U7347 ( .A(n5888), .B(n5883), .Y(n5884) );
XOR2X1TS U7348 ( .A(n5884), .B(n6865), .Y(n5885) );
NAND2X1TS U7349 ( .A(n5888), .B(FPMULT_Sgf_normalized_result[8]), .Y(n5886)
);
XOR2X1TS U7350 ( .A(n5886), .B(n6789), .Y(n5887) );
XNOR2X1TS U7351 ( .A(n5888), .B(n6759), .Y(n5889) );
INVX2TS U7352 ( .A(n5890), .Y(n5898) );
OAI21X1TS U7353 ( .A0(n5898), .A1(n6792), .B0(n5891), .Y(n5894) );
NAND2X1TS U7354 ( .A(n5894), .B(FPMULT_Sgf_normalized_result[6]), .Y(n5892)
);
XOR2X1TS U7355 ( .A(n5892), .B(n6866), .Y(n5893) );
XNOR2X1TS U7356 ( .A(n5894), .B(n2399), .Y(n5895) );
NAND2X1TS U7357 ( .A(n5898), .B(n2450), .Y(n5896) );
XNOR2X1TS U7358 ( .A(n5896), .B(n6792), .Y(n5897) );
XOR2X1TS U7359 ( .A(n5898), .B(FPMULT_Sgf_normalized_result[4]), .Y(n5900)
);
NAND2X1TS U7360 ( .A(n2485), .B(n5901), .Y(n5902) );
XNOR2X1TS U7361 ( .A(n5903), .B(n5902), .Y(n5904) );
XOR2X1TS U7362 ( .A(n5906), .B(n6788), .Y(n5907) );
INVX2TS U7363 ( .A(n5908), .Y(n5921) );
INVX2TS U7364 ( .A(n5909), .Y(n5911) );
NAND2X1TS U7365 ( .A(n5911), .B(n5910), .Y(n5912) );
XNOR2X1TS U7366 ( .A(n5913), .B(n5912), .Y(n5914) );
XOR2X1TS U7367 ( .A(n5915), .B(FPMULT_Sgf_normalized_result[2]), .Y(n5916)
);
INVX2TS U7368 ( .A(n5917), .Y(n5919) );
NAND2X1TS U7369 ( .A(n5919), .B(n5918), .Y(n5920) );
XOR2X1TS U7370 ( .A(n5921), .B(n5920), .Y(n5922) );
XNOR2X1TS U7371 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n5923) );
INVX2TS U7372 ( .A(n5924), .Y(n6280) );
AOI21X1TS U7373 ( .A0(n6280), .A1(n2471), .B0(n5925), .Y(n5928) );
NAND2X1TS U7374 ( .A(n2204), .B(n5926), .Y(n5927) );
XOR2X1TS U7375 ( .A(n5928), .B(n5927), .Y(n5929) );
ADDHXLTS U7376 ( .A(FPMULT_Sgf_normalized_result[23]), .B(n5930), .CO(n5932),
.S(n5855) );
NAND2X1TS U7377 ( .A(n6605), .B(n6845), .Y(n1689) );
XNOR2X2TS U7378 ( .A(DP_OP_234J223_132_4955_n1), .B(n5935), .Y(n5936) );
MX2X1TS U7379 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1453) );
BUFX3TS U7380 ( .A(n5937), .Y(n6014) );
AOI211X1TS U7381 ( .A0(FPADDSUB_Data_array_SWR[5]), .A1(n2330), .B0(n5939),
.C0(n5938), .Y(n6004) );
OAI22X1TS U7382 ( .A0(n6004), .A1(n5984), .B0(n6008), .B1(n5954), .Y(n6628)
);
OA22X1TS U7383 ( .A0(n6628), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n1181) );
OAI2BB2XLTS U7384 ( .B0(n5989), .B1(n2263), .A0N(FPADDSUB_Data_array_SWR[10]), .A1N(n2326), .Y(n5940) );
AOI211X1TS U7385 ( .A0(FPADDSUB_Data_array_SWR[6]), .A1(n2329), .B0(n5941),
.C0(n5940), .Y(n6000) );
OAI22X1TS U7386 ( .A0(n6000), .A1(n5984), .B0(n6001), .B1(n5954), .Y(n6639)
);
OA22X1TS U7387 ( .A0(n6639), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n1182) );
AOI211X1TS U7388 ( .A0(FPADDSUB_shift_value_SHT2_EWR[4]), .A1(n5955), .B0(
n5943), .C0(n5942), .Y(n5997) );
OAI22X1TS U7389 ( .A0(n5997), .A1(n5984), .B0(n5996), .B1(n5954), .Y(n6645)
);
OA22X1TS U7390 ( .A0(n6645), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n1183) );
INVX2TS U7391 ( .A(n5944), .Y(n5946) );
NOR2X1TS U7392 ( .A(n2504), .B(n5946), .Y(n5945) );
AOI211X2TS U7393 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2312), .B0(n5948),
.C0(n5945), .Y(n5994) );
NOR2X1TS U7394 ( .A(n6816), .B(n5946), .Y(n5947) );
OAI2BB2XLTS U7395 ( .B0(n5992), .B1(n2263), .A0N(FPADDSUB_Data_array_SWR[12]), .A1N(n2326), .Y(n5949) );
AOI211X1TS U7396 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n2330), .B0(n5950),
.C0(n5949), .Y(n5995) );
OAI22X1TS U7397 ( .A0(n5994), .A1(n5954), .B0(n5995), .B1(n5984), .Y(n6642)
);
OA22X1TS U7398 ( .A0(n6642), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n1184) );
OAI2BB2XLTS U7399 ( .B0(n5994), .B1(n2263), .A0N(FPADDSUB_Data_array_SWR[13]), .A1N(n2326), .Y(n5952) );
AOI211X1TS U7400 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2330), .B0(n5953),
.C0(n5952), .Y(n5993) );
OAI22X1TS U7401 ( .A0(n5993), .A1(n5984), .B0(n5992), .B1(n5954), .Y(n6636)
);
OA22X1TS U7402 ( .A0(n6636), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n1185) );
OA22X1TS U7403 ( .A0(n6648), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n1186) );
OA22X1TS U7404 ( .A0(n6632), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n1188) );
OA22X1TS U7405 ( .A0(n6663), .A1(n5963), .B0(n5962), .B1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n1189) );
AOI21X1TS U7406 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n2343), .B0(n5979),
.Y(n5965) );
AOI22X1TS U7407 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n2330), .Y(n5964) );
OAI211X1TS U7408 ( .A0(n6842), .A1(n5966), .B0(n5965), .C0(n5964), .Y(n5985)
);
NOR2BX1TS U7409 ( .AN(n5967), .B(n5979), .Y(n5973) );
AOI22X1TS U7410 ( .A0(FPADDSUB_Data_array_SWR[23]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[19]), .B1(n2330), .Y(n5968) );
OAI211X1TS U7411 ( .A0(n2418), .A1(n5969), .B0(n5973), .C0(n5968), .Y(n5986)
);
AOI22X1TS U7412 ( .A0(n2357), .A1(n5985), .B0(n5986), .B1(n2356), .Y(n6651)
);
MXI2X1TS U7413 ( .A(n6651), .B(n6858), .S0(n6003), .Y(n1190) );
AOI21X1TS U7414 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n3288), .B0(n5979),
.Y(n5971) );
AOI22X1TS U7415 ( .A0(FPADDSUB_Data_array_SWR[23]), .A1(n2328), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2343), .Y(n5970) );
OAI211X1TS U7416 ( .A0(n2418), .A1(n5974), .B0(n5971), .C0(n5970), .Y(n5982)
);
AOI22X1TS U7417 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n2343), .Y(n5972) );
OAI211X1TS U7418 ( .A0(n6842), .A1(n5974), .B0(n5973), .C0(n5972), .Y(n5983)
);
AOI22X1TS U7419 ( .A0(n2357), .A1(n5982), .B0(n5983), .B1(n2235), .Y(n6667)
);
MXI2X1TS U7420 ( .A(n6667), .B(n6862), .S0(n6003), .Y(n1191) );
AOI22X1TS U7421 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2343), .B0(
FPADDSUB_Data_array_SWR[24]), .B1(n2328), .Y(n5976) );
AOI22X1TS U7422 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[16]), .B1(n2330), .Y(n5975) );
AOI22X1TS U7423 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n3288), .B0(
FPADDSUB_Data_array_SWR[25]), .B1(n2328), .Y(n5978) );
AOI22X1TS U7424 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2330), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n2343), .Y(n5977) );
AOI221X1TS U7425 ( .A0(n2357), .A1(n5980), .B0(n5984), .B1(n5981), .C0(n5979), .Y(n6661) );
MXI2X1TS U7426 ( .A(n6661), .B(n6859), .S0(n6003), .Y(n1192) );
AOI221X1TS U7427 ( .A0(n6005), .A1(n5981), .B0(n2235), .B1(n5980), .C0(n5979), .Y(n6666) );
MXI2X1TS U7428 ( .A(n6666), .B(n6860), .S0(n6003), .Y(n1193) );
AOI22X1TS U7429 ( .A0(n6005), .A1(n5983), .B0(n5982), .B1(n2235), .Y(n6725)
);
MXI2X1TS U7430 ( .A(n6725), .B(n6863), .S0(n6003), .Y(n1194) );
AOI22X1TS U7431 ( .A0(n6005), .A1(n5986), .B0(n5985), .B1(n2356), .Y(n6658)
);
MXI2X1TS U7432 ( .A(n6658), .B(n6856), .S0(n6003), .Y(n1195) );
OAI22X1TS U7433 ( .A0(n5990), .A1(n2357), .B0(n6007), .B1(n5989), .Y(n6726)
);
OA22X1TS U7434 ( .A0(n6726), .A1(n5998), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1198) );
OAI22X1TS U7435 ( .A0(n5993), .A1(n6005), .B0(n6007), .B1(n5992), .Y(n6718)
);
OA22X1TS U7436 ( .A0(n6718), .A1(n5998), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1200) );
OAI22X1TS U7437 ( .A0(n5995), .A1(n6005), .B0(n5994), .B1(n6007), .Y(n6720)
);
OA22X1TS U7438 ( .A0(n6720), .A1(n5998), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1201) );
OAI22X1TS U7439 ( .A0(n5997), .A1(n2357), .B0(n6007), .B1(n5996), .Y(n6723)
);
OA22X1TS U7440 ( .A0(n6723), .A1(n5998), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n1202) );
INVX2TS U7441 ( .A(n5999), .Y(n6727) );
OAI22X1TS U7442 ( .A0(n6001), .A1(n6007), .B0(n2357), .B1(n6000), .Y(n6002)
);
NOR2X1TS U7443 ( .A(n6727), .B(n6002), .Y(n6722) );
MXI2X1TS U7444 ( .A(n6722), .B(n6861), .S0(n6003), .Y(n1203) );
OA22X1TS U7445 ( .A0(n6011), .A1(n6010), .B0(n6009), .B1(
FPADDSUB_DmP_mant_SFG_SWR[1]), .Y(n1204) );
OAI32X4TS U7446 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n6012), .B1(n6826),
.Y(n6353) );
MXI2X1TS U7447 ( .A(n6013), .B(n6232), .S0(n6353), .Y(n2144) );
OAI22X1TS U7448 ( .A0(FPMULT_Exp_module_Data_S[8]), .A1(n6021), .B0(n6020),
.B1(n6864), .Y(n1586) );
OA22X1TS U7449 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B0(n6022),
.B1(result_add_subt[29]), .Y(n1467) );
OA22X1TS U7450 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B0(n6022),
.B1(result_add_subt[28]), .Y(n1468) );
OA22X1TS U7451 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B0(n6022),
.B1(result_add_subt[27]), .Y(n1469) );
OA22X1TS U7452 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B0(n6022),
.B1(result_add_subt[26]), .Y(n1470) );
OA22X1TS U7453 ( .A0(n6626), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(n6022),
.B1(result_add_subt[25]), .Y(n1471) );
OR4X2TS U7454 ( .A(n6617), .B(FPMULT_Exp_module_Overflow_flag_A), .C(
FPMULT_exp_oper_result[8]), .D(underflow_flag_mult), .Y(n6608) );
INVX2TS U7455 ( .A(n6613), .Y(n6619) );
BUFX3TS U7456 ( .A(n6024), .Y(n6134) );
INVX2TS U7457 ( .A(n6025), .Y(n6185) );
INVX2TS U7458 ( .A(n6026), .Y(n6029) );
INVX2TS U7459 ( .A(n6027), .Y(n6028) );
NAND2X1TS U7460 ( .A(n6031), .B(n6030), .Y(n6036) );
INVX2TS U7461 ( .A(n6036), .Y(n6032) );
XNOR2X1TS U7462 ( .A(n6033), .B(n6032), .Y(n6040) );
INVX2TS U7463 ( .A(n6034), .Y(n6108) );
XNOR2X1TS U7464 ( .A(n6037), .B(n6036), .Y(n6038) );
AOI22X1TS U7465 ( .A0(n6038), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[11]),
.B1(n6711), .Y(n6039) );
OAI2BB1X1TS U7466 ( .A0N(n6134), .A1N(n6040), .B0(n6039), .Y(n1338) );
NAND2X1TS U7467 ( .A(n6043), .B(n6042), .Y(n6046) );
INVX2TS U7468 ( .A(n6046), .Y(n6044) );
XOR2X1TS U7469 ( .A(n6047), .B(n6046), .Y(n6048) );
AOI22X1TS U7470 ( .A0(n6048), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[13]),
.B1(n6711), .Y(n6049) );
OAI2BB1X1TS U7471 ( .A0N(n6134), .A1N(n6050), .B0(n6049), .Y(n1336) );
NAND2X1TS U7472 ( .A(n6054), .B(n6053), .Y(n6057) );
INVX2TS U7473 ( .A(n6057), .Y(n6055) );
XNOR2X1TS U7474 ( .A(n6056), .B(n6055), .Y(n6060) );
XOR2X1TS U7475 ( .A(n6108), .B(n6057), .Y(n6058) );
AOI22X1TS U7476 ( .A0(n6058), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[10]),
.B1(n6711), .Y(n6059) );
OAI2BB1X1TS U7477 ( .A0N(n6134), .A1N(n6060), .B0(n6059), .Y(n1339) );
NAND2X1TS U7478 ( .A(n6062), .B(n6061), .Y(n6065) );
INVX2TS U7479 ( .A(n6065), .Y(n6063) );
XNOR2X1TS U7480 ( .A(n6064), .B(n6063), .Y(n6069) );
XNOR2X1TS U7481 ( .A(n6066), .B(n6065), .Y(n6067) );
AOI22X1TS U7482 ( .A0(n6067), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[16]),
.B1(n6711), .Y(n6068) );
OAI2BB1X1TS U7483 ( .A0N(n6134), .A1N(n6069), .B0(n6068), .Y(n1333) );
NAND2X1TS U7484 ( .A(n6071), .B(n6070), .Y(n6074) );
INVX2TS U7485 ( .A(n6074), .Y(n6072) );
XNOR2X1TS U7486 ( .A(n6073), .B(n6072), .Y(n6078) );
XNOR2X1TS U7487 ( .A(n6075), .B(n6074), .Y(n6076) );
AOI22X1TS U7488 ( .A0(n6076), .A1(n4499), .B0(FPADDSUB_Raw_mant_NRM_SWR[14]),
.B1(n6711), .Y(n6077) );
OAI2BB1X1TS U7489 ( .A0N(n6134), .A1N(n6078), .B0(n6077), .Y(n1335) );
INVX2TS U7490 ( .A(n6079), .Y(n6081) );
NAND2X1TS U7491 ( .A(n6081), .B(n6080), .Y(n6084) );
INVX2TS U7492 ( .A(n6084), .Y(n6082) );
XOR2X1TS U7493 ( .A(n6085), .B(n6084), .Y(n6086) );
AOI22X1TS U7494 ( .A0(n6086), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n6191), .Y(n6087) );
OAI2BB1X1TS U7495 ( .A0N(n6134), .A1N(n6088), .B0(n6087), .Y(n1332) );
NAND2X1TS U7496 ( .A(n6091), .B(n6090), .Y(n6094) );
INVX2TS U7497 ( .A(n6094), .Y(n6092) );
XOR2X1TS U7498 ( .A(n6095), .B(n6094), .Y(n6096) );
AOI22X1TS U7499 ( .A0(n6096), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B1(n6711), .Y(n6097) );
OAI2BB1X1TS U7500 ( .A0N(n6134), .A1N(n6098), .B0(n6097), .Y(n1334) );
NAND2X1TS U7501 ( .A(n6103), .B(n6102), .Y(n6109) );
INVX2TS U7502 ( .A(n6109), .Y(n6104) );
XNOR2X1TS U7503 ( .A(n6105), .B(n6104), .Y(n6113) );
XNOR2X1TS U7504 ( .A(n6110), .B(n6109), .Y(n6111) );
AOI22X1TS U7505 ( .A0(n6111), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[12]),
.B1(n6711), .Y(n6112) );
OAI2BB1X1TS U7506 ( .A0N(n6134), .A1N(n6113), .B0(n6112), .Y(n1337) );
INVX2TS U7507 ( .A(n6114), .Y(n6116) );
NAND2X1TS U7508 ( .A(n6116), .B(n6115), .Y(n6119) );
INVX2TS U7509 ( .A(n6119), .Y(n6117) );
XOR2X1TS U7510 ( .A(n6120), .B(n6119), .Y(n6121) );
AOI22X1TS U7511 ( .A0(n6121), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n6191), .Y(n6122) );
OAI2BB1X1TS U7512 ( .A0N(n6134), .A1N(n6123), .B0(n6122), .Y(n1321) );
INVX2TS U7513 ( .A(n6124), .Y(n6126) );
NAND2X1TS U7514 ( .A(n6126), .B(n6125), .Y(n6129) );
INVX2TS U7515 ( .A(n6129), .Y(n6127) );
XOR2X1TS U7516 ( .A(n6130), .B(n6129), .Y(n6131) );
AOI22X1TS U7517 ( .A0(n6131), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[21]),
.B1(n6191), .Y(n6132) );
OAI2BB1X1TS U7518 ( .A0N(n6134), .A1N(n6133), .B0(n6132), .Y(n1319) );
NAND2X1TS U7519 ( .A(n6136), .B(n6135), .Y(n6139) );
INVX2TS U7520 ( .A(n6139), .Y(n6137) );
XNOR2X1TS U7521 ( .A(n6138), .B(n6137), .Y(n6143) );
XNOR2X1TS U7522 ( .A(n6140), .B(n6139), .Y(n6141) );
AOI22X1TS U7523 ( .A0(n6141), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n6191), .Y(n6142) );
OAI2BB1X1TS U7524 ( .A0N(n6237), .A1N(n6143), .B0(n6142), .Y(n1320) );
OR2X1TS U7525 ( .A(n6844), .B(FPADDSUB_DMP_SFG[22]), .Y(n6145) );
CLKAND2X2TS U7526 ( .A(n6844), .B(FPADDSUB_DMP_SFG[22]), .Y(n6144) );
AOI21X1TS U7527 ( .A0(n6146), .A1(n6145), .B0(n6144), .Y(n6147) );
XOR2X1TS U7528 ( .A(n6147), .B(n6867), .Y(n6151) );
XOR2X1TS U7529 ( .A(n6148), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n6149) );
AOI22X1TS U7530 ( .A0(n6149), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n6191), .Y(n6150) );
OAI2BB1X1TS U7531 ( .A0N(n6237), .A1N(n6151), .B0(n6150), .Y(n1410) );
NAND2X1TS U7532 ( .A(n6153), .B(n6152), .Y(n6156) );
INVX2TS U7533 ( .A(n6156), .Y(n6154) );
XNOR2X1TS U7534 ( .A(n6155), .B(n6154), .Y(n6161) );
XNOR2X1TS U7535 ( .A(n6157), .B(n6156), .Y(n6159) );
AOI22X1TS U7536 ( .A0(n6159), .A1(n6158), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n6191), .Y(n6160) );
OAI2BB1X1TS U7537 ( .A0N(n6237), .A1N(n6161), .B0(n6160), .Y(n1317) );
INVX2TS U7538 ( .A(n6162), .Y(n6164) );
NAND2X1TS U7539 ( .A(n6164), .B(n6163), .Y(n6167) );
INVX2TS U7540 ( .A(n6167), .Y(n6165) );
XOR2X1TS U7541 ( .A(n6168), .B(n6167), .Y(n6169) );
AOI22X1TS U7542 ( .A0(n6169), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.B1(n6191), .Y(n6170) );
OAI2BB1X1TS U7543 ( .A0N(n6237), .A1N(n6171), .B0(n6170), .Y(n1316) );
NAND2X1TS U7544 ( .A(n6173), .B(n6172), .Y(n6176) );
INVX2TS U7545 ( .A(n6176), .Y(n6174) );
XNOR2X1TS U7546 ( .A(n6175), .B(n6174), .Y(n6180) );
XNOR2X1TS U7547 ( .A(n6177), .B(n6176), .Y(n6178) );
AOI22X1TS U7548 ( .A0(n6178), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[18]),
.B1(n6191), .Y(n6179) );
OAI2BB1X1TS U7549 ( .A0N(n6237), .A1N(n6180), .B0(n6179), .Y(n1331) );
INVX2TS U7550 ( .A(n6181), .Y(n6183) );
NAND2X1TS U7551 ( .A(n6183), .B(n6182), .Y(n6189) );
INVX2TS U7552 ( .A(n6189), .Y(n6184) );
AOI21X1TS U7553 ( .A0(n6231), .A1(n6188), .B0(n6187), .Y(n6205) );
XNOR2X1TS U7554 ( .A(n6190), .B(n6189), .Y(n6192) );
AOI22X1TS U7555 ( .A0(n6192), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[9]),
.B1(n6191), .Y(n6193) );
OAI2BB1X1TS U7556 ( .A0N(n6237), .A1N(n6194), .B0(n6193), .Y(n1340) );
AOI21X1TS U7557 ( .A0(n6225), .A1(n6196), .B0(n6195), .Y(n6213) );
INVX2TS U7558 ( .A(n6199), .Y(n6201) );
NAND2X1TS U7559 ( .A(n6201), .B(n6200), .Y(n6204) );
INVX2TS U7560 ( .A(n6204), .Y(n6202) );
XNOR2X1TS U7561 ( .A(n6203), .B(n6202), .Y(n6208) );
XOR2X1TS U7562 ( .A(n6205), .B(n6204), .Y(n6206) );
AOI22X1TS U7563 ( .A0(n6206), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[8]),
.B1(n6232), .Y(n6207) );
OAI2BB1X1TS U7564 ( .A0N(n6237), .A1N(n6208), .B0(n6207), .Y(n1341) );
INVX2TS U7565 ( .A(n6209), .Y(n6211) );
NAND2X1TS U7566 ( .A(n6211), .B(n6210), .Y(n6216) );
INVX2TS U7567 ( .A(n6216), .Y(n6212) );
INVX2TS U7568 ( .A(n6214), .Y(n6227) );
INVX2TS U7569 ( .A(n6226), .Y(n6215) );
AOI21X1TS U7570 ( .A0(n6231), .A1(n6227), .B0(n6215), .Y(n6217) );
XOR2X1TS U7571 ( .A(n6217), .B(n6216), .Y(n6218) );
AOI22X1TS U7572 ( .A0(n6218), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.B1(n6232), .Y(n6219) );
OAI2BB1X1TS U7573 ( .A0N(n6237), .A1N(n6220), .B0(n6219), .Y(n1342) );
INVX2TS U7574 ( .A(n6221), .Y(n6224) );
INVX2TS U7575 ( .A(n6222), .Y(n6223) );
AOI21X1TS U7576 ( .A0(n6225), .A1(n6224), .B0(n6223), .Y(n6229) );
NAND2X1TS U7577 ( .A(n6227), .B(n6226), .Y(n6230) );
INVX2TS U7578 ( .A(n6230), .Y(n6228) );
XNOR2X1TS U7579 ( .A(n6231), .B(n6230), .Y(n6234) );
AOI22X1TS U7580 ( .A0(n6234), .A1(n6233), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n6232), .Y(n6235) );
OAI2BB1X1TS U7581 ( .A0N(n6237), .A1N(n6236), .B0(n6235), .Y(n1343) );
NAND2X1TS U7582 ( .A(n2462), .B(n6238), .Y(n6240) );
XNOR2X1TS U7583 ( .A(n6240), .B(n6239), .Y(n6241) );
INVX2TS U7584 ( .A(n6242), .Y(n6294) );
INVX2TS U7585 ( .A(n6243), .Y(n6284) );
NAND2X1TS U7586 ( .A(n6284), .B(n6282), .Y(n6244) );
XNOR2X1TS U7587 ( .A(n6294), .B(n6244), .Y(n6245) );
INVX2TS U7588 ( .A(n6246), .Y(n6252) );
INVX2TS U7589 ( .A(n6251), .Y(n6247) );
NAND2X1TS U7590 ( .A(n6247), .B(n6250), .Y(n6248) );
XOR2X1TS U7591 ( .A(n6252), .B(n6248), .Y(n6249) );
INVX2TS U7592 ( .A(n6253), .Y(n6255) );
NAND2X1TS U7593 ( .A(n6255), .B(n6254), .Y(n6256) );
XNOR2X1TS U7594 ( .A(n6257), .B(n6256), .Y(n6258) );
INVX2TS U7595 ( .A(n6263), .Y(n6265) );
NAND2X1TS U7596 ( .A(n6265), .B(n6264), .Y(n6266) );
XOR2X1TS U7597 ( .A(n6267), .B(n6266), .Y(n6268) );
OR2X1TS U7598 ( .A(n6270), .B(n6269), .Y(n6272) );
CLKAND2X2TS U7599 ( .A(n6272), .B(n6271), .Y(n6273) );
NAND2X1TS U7600 ( .A(n6278), .B(n2471), .Y(n6279) );
XNOR2X1TS U7601 ( .A(n6280), .B(n6279), .Y(n6281) );
INVX2TS U7602 ( .A(n6282), .Y(n6283) );
AOI21X1TS U7603 ( .A0(n6294), .A1(n6284), .B0(n6283), .Y(n6289) );
INVX2TS U7604 ( .A(n6285), .Y(n6287) );
NAND2X1TS U7605 ( .A(n6287), .B(n6286), .Y(n6288) );
XOR2X1TS U7606 ( .A(n6289), .B(n6288), .Y(n6291) );
AOI21X1TS U7607 ( .A0(n6294), .A1(n6293), .B0(n6292), .Y(n6297) );
NAND2X1TS U7608 ( .A(n2203), .B(n6295), .Y(n6296) );
XOR2X1TS U7609 ( .A(n6297), .B(n6296), .Y(n6298) );
INVX2TS U7610 ( .A(n6299), .Y(n6305) );
INVX2TS U7611 ( .A(n6304), .Y(n6300) );
NAND2X1TS U7612 ( .A(n6300), .B(n6303), .Y(n6301) );
XOR2X1TS U7613 ( .A(n6305), .B(n6301), .Y(n6302) );
INVX2TS U7614 ( .A(n6306), .Y(n6308) );
NAND2X1TS U7615 ( .A(n6308), .B(n6307), .Y(n6309) );
XNOR2X1TS U7616 ( .A(n6310), .B(n6309), .Y(n6311) );
NOR4X1TS U7617 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n6318) );
NOR4X1TS U7618 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n6317) );
NOR4X1TS U7619 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n6315) );
NOR4X1TS U7620 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n6313) );
NOR4X1TS U7621 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n6312) );
AND4X1TS U7622 ( .A(n6315), .B(n6314), .C(n6313), .D(n6312), .Y(n6316) );
NOR4BX1TS U7623 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n6323) );
NOR4X1TS U7624 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n6322) );
NAND4XLTS U7625 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n6320) );
NAND4XLTS U7626 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n6319) );
OR3X1TS U7627 ( .A(n7068), .B(n6320), .C(n6319), .Y(n6324) );
NOR3X1TS U7628 ( .A(dataB[29]), .B(dataB[31]), .C(n6324), .Y(n6321) );
NOR4X1TS U7629 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n6327) );
NOR4X1TS U7630 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n6326) );
NOR4BX1TS U7631 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataA[31]),
.D(n7068), .Y(n6325) );
NOR2X1TS U7632 ( .A(operation_reg[1]), .B(n6324), .Y(n6332) );
NAND4XLTS U7633 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n6328) );
OAI31X1TS U7634 ( .A0(n6330), .A1(n6329), .A2(n6328), .B0(dataB[27]), .Y(
n6331) );
OAI2BB2XLTS U7635 ( .B0(n6334), .B1(n6333), .A0N(n6332), .A1N(
operation_reg[0]), .Y(NaN_reg) );
INVX2TS U7636 ( .A(n6353), .Y(n6355) );
NOR4X1TS U7637 ( .A(n6450), .B(n2298), .C(n6415), .D(n6336), .Y(n6338) );
OAI2BB1X1TS U7638 ( .A0N(operation[1]), .A1N(ack_operation), .B0(n6337), .Y(
n6348) );
AOI32X1TS U7639 ( .A0(begin_operation), .A1(n6340), .A2(operation[1]), .B0(
n6341), .B1(n6340), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
OR2X1TS U7640 ( .A(n6369), .B(n6371), .Y(n6344) );
OAI22X1TS U7641 ( .A0(n6386), .A1(n6347), .B0(n6346), .B1(n6345), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
OR2X1TS U7642 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n6349) );
AO22XLTS U7643 ( .A0(operation[2]), .A1(n6349), .B0(n6350), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U7644 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n6350),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
AOI22X1TS U7645 ( .A0(n6355), .A1(n6714), .B0(n6741), .B1(n6353), .Y(n2147)
);
AOI22X1TS U7646 ( .A0(n6355), .A1(n6741), .B0(n6740), .B1(n6353), .Y(n2146)
);
OAI2BB2XLTS U7647 ( .B0(n6353), .B1(n6740), .A0N(n6353), .A1N(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2145) );
AOI22X1TS U7648 ( .A0(n6355), .A1(n6711), .B0(n2341), .B1(n6353), .Y(n2143)
);
AOI22X1TS U7649 ( .A0(n6355), .A1(n7059), .B0(n6354), .B1(n6353), .Y(n2142)
);
NAND2X1TS U7650 ( .A(n2299), .B(n6455), .Y(n6356) );
OA21XLTS U7651 ( .A0(n2299), .A1(FPSENCOS_cont_iter_out[0]), .B0(n6356), .Y(
n2141) );
AOI22X1TS U7652 ( .A0(n2299), .A1(n6373), .B0(n6768), .B1(n6356), .Y(n2140)
);
NAND2X1TS U7653 ( .A(n2299), .B(n6373), .Y(n6357) );
AOI32X1TS U7654 ( .A0(n2299), .A1(n6372), .A2(n6373), .B0(intadd_517_B_1_),
.B1(n6357), .Y(n2139) );
AOI21X1TS U7655 ( .A0(n6782), .A1(n6359), .B0(n6358), .Y(n2138) );
BUFX3TS U7656 ( .A(n6380), .Y(n6383) );
OAI2BB2XLTS U7657 ( .B0(n6379), .B1(n6558), .A0N(n6383), .A1N(region_flag[0]), .Y(n2135) );
OAI2BB2XLTS U7658 ( .B0(n6379), .B1(n2266), .A0N(n6383), .A1N(region_flag[1]), .Y(n2134) );
AOI22X1TS U7659 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n6456), .B0(
FPSENCOS_cont_iter_out[1]), .B1(n6366), .Y(n6361) );
NAND2X1TS U7660 ( .A(n6361), .B(n6363), .Y(n2133) );
INVX2TS U7661 ( .A(n6448), .Y(n6408) );
OAI2BB1X1TS U7662 ( .A0N(FPSENCOS_d_ff3_LUT_out[8]), .A1N(n6408), .B0(n6362),
.Y(n2125) );
OAI2BB1X1TS U7663 ( .A0N(FPSENCOS_d_ff3_LUT_out[19]), .A1N(n6408), .B0(n6367), .Y(n2119) );
BUFX3TS U7664 ( .A(n6449), .Y(n6464) );
INVX2TS U7665 ( .A(n6448), .Y(n6428) );
AOI22X1TS U7666 ( .A0(n6373), .A1(intadd_517_B_1_), .B0(n6372), .B1(n6371),
.Y(n6374) );
INVX2TS U7667 ( .A(n6382), .Y(n6376) );
INVX2TS U7668 ( .A(n6382), .Y(n6378) );
BUFX3TS U7669 ( .A(n6380), .Y(n6377) );
INVX2TS U7670 ( .A(n6382), .Y(n6381) );
INVX2TS U7671 ( .A(n6386), .Y(n6390) );
INVX2TS U7672 ( .A(n6386), .Y(n6542) );
OAI2BB2XLTS U7673 ( .B0(n6390), .B1(n2367), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[0]), .Y(n2074) );
BUFX3TS U7674 ( .A(n6385), .Y(n6391) );
OAI2BB2XLTS U7675 ( .B0(n6391), .B1(n2367), .A0N(n6387), .A1N(
FPSENCOS_d_ff_Yn[0]), .Y(n2073) );
AND3X2TS U7676 ( .A(n6756), .B(n6802), .C(ready_add_subt), .Y(n6388) );
INVX2TS U7677 ( .A(n6388), .Y(n6523) );
INVX2TS U7678 ( .A(n6388), .Y(n6553) );
OAI2BB2XLTS U7679 ( .B0(n6523), .B1(n2367), .A0N(n6553), .A1N(
FPSENCOS_d_ff_Xn[0]), .Y(n2072) );
INVX2TS U7680 ( .A(n6386), .Y(n6543) );
OAI2BB2XLTS U7681 ( .B0(n6543), .B1(n6835), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[1]), .Y(n2071) );
BUFX3TS U7682 ( .A(n6387), .Y(n6389) );
OAI2BB2XLTS U7683 ( .B0(n6389), .B1(n6835), .A0N(n6387), .A1N(
FPSENCOS_d_ff_Yn[1]), .Y(n2070) );
BUFX3TS U7684 ( .A(n6388), .Y(n6392) );
INVX1TS U7685 ( .A(FPSENCOS_d_ff_Xn[1]), .Y(n6397) );
AOI22X1TS U7686 ( .A0(n6392), .A1(n6835), .B0(n6397), .B1(n6539), .Y(n2069)
);
INVX2TS U7687 ( .A(n6386), .Y(n6531) );
OAI2BB2XLTS U7688 ( .B0(n6390), .B1(n6834), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[2]), .Y(n2068) );
BUFX3TS U7689 ( .A(n6387), .Y(n6534) );
OAI2BB2XLTS U7690 ( .B0(n6391), .B1(n6834), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[2]), .Y(n2067) );
AOI22X1TS U7691 ( .A0(n6392), .A1(n6834), .B0(n2401), .B1(n6539), .Y(n2066)
);
OAI2BB2XLTS U7692 ( .B0(n6390), .B1(n6833), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[3]), .Y(n2065) );
OAI2BB2XLTS U7693 ( .B0(n6389), .B1(n6833), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[3]), .Y(n2064) );
INVX1TS U7694 ( .A(FPSENCOS_d_ff_Xn[3]), .Y(n6400) );
AOI22X1TS U7695 ( .A0(n6392), .A1(n6833), .B0(n6400), .B1(n6539), .Y(n2063)
);
OAI2BB2XLTS U7696 ( .B0(n6543), .B1(n2280), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[4]), .Y(n2062) );
OAI2BB2XLTS U7697 ( .B0(n6389), .B1(n2280), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[4]), .Y(n2061) );
OAI2BB2XLTS U7698 ( .B0(n6523), .B1(n2280), .A0N(n6553), .A1N(
FPSENCOS_d_ff_Xn[4]), .Y(n2060) );
INVX2TS U7699 ( .A(n6386), .Y(n6395) );
OAI2BB2XLTS U7700 ( .B0(n6543), .B1(n6836), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[5]), .Y(n2059) );
BUFX3TS U7701 ( .A(n6387), .Y(n6443) );
OAI2BB2XLTS U7702 ( .B0(n6389), .B1(n6836), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[5]), .Y(n2058) );
INVX1TS U7703 ( .A(FPSENCOS_d_ff_Xn[5]), .Y(n6403) );
AOI22X1TS U7704 ( .A0(n6388), .A1(n6836), .B0(n6403), .B1(n6539), .Y(n2057)
);
OAI2BB2XLTS U7705 ( .B0(n6543), .B1(n6839), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[6]), .Y(n2056) );
OAI2BB2XLTS U7706 ( .B0(n6389), .B1(n6839), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[6]), .Y(n2055) );
AOI22X1TS U7707 ( .A0(n6388), .A1(n6839), .B0(n2440), .B1(n6539), .Y(n2054)
);
OAI2BB2XLTS U7708 ( .B0(n6543), .B1(n6840), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[7]), .Y(n2053) );
OAI2BB2XLTS U7709 ( .B0(n6389), .B1(n6840), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[7]), .Y(n2052) );
INVX1TS U7710 ( .A(FPSENCOS_d_ff_Xn[7]), .Y(n6405) );
AOI22X1TS U7711 ( .A0(n6388), .A1(n6840), .B0(n6405), .B1(n6539), .Y(n2051)
);
OAI2BB2XLTS U7712 ( .B0(n6543), .B1(n6659), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[8]), .Y(n2050) );
OAI2BB2XLTS U7713 ( .B0(n6389), .B1(n6659), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[8]), .Y(n2049) );
INVX2TS U7714 ( .A(n6388), .Y(n6555) );
OAI2BB2XLTS U7715 ( .B0(n6555), .B1(n6659), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[8]), .Y(n2048) );
OAI2BB2XLTS U7716 ( .B0(n6543), .B1(n6837), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[9]), .Y(n2047) );
OAI2BB2XLTS U7717 ( .B0(n6389), .B1(n6837), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[9]), .Y(n2046) );
OAI2BB2XLTS U7718 ( .B0(n6555), .B1(n6837), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[9]), .Y(n2045) );
OAI2BB2XLTS U7719 ( .B0(n6543), .B1(n6831), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[10]), .Y(n2044) );
OAI2BB2XLTS U7720 ( .B0(n6389), .B1(n6831), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[10]), .Y(n2043) );
BUFX3TS U7721 ( .A(n6392), .Y(n6541) );
AOI22X1TS U7722 ( .A0(n6541), .A1(n6831), .B0(n2447), .B1(n6528), .Y(n2042)
);
OAI2BB2XLTS U7723 ( .B0(n6543), .B1(n6662), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[11]), .Y(n2041) );
OAI2BB2XLTS U7724 ( .B0(n6393), .B1(n6662), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[11]), .Y(n2040) );
OAI2BB2XLTS U7725 ( .B0(n6555), .B1(n6662), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[11]), .Y(n2039) );
INVX2TS U7726 ( .A(n6386), .Y(n6394) );
OAI2BB2XLTS U7727 ( .B0(n6394), .B1(n6832), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[12]), .Y(n2038) );
OAI2BB2XLTS U7728 ( .B0(n6393), .B1(n6832), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[12]), .Y(n2037) );
INVX1TS U7729 ( .A(FPSENCOS_d_ff_Xn[12]), .Y(n6411) );
AOI22X1TS U7730 ( .A0(n6541), .A1(n6832), .B0(n6411), .B1(n6528), .Y(n2036)
);
OAI2BB2XLTS U7731 ( .B0(n6394), .B1(n6652), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[13]), .Y(n2035) );
OAI2BB2XLTS U7732 ( .B0(n6393), .B1(n6652), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[13]), .Y(n2034) );
AOI22X1TS U7733 ( .A0(n6392), .A1(n6652), .B0(n2424), .B1(n6528), .Y(n2033)
);
OAI2BB2XLTS U7734 ( .B0(n6394), .B1(n6830), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[14]), .Y(n2032) );
OAI2BB2XLTS U7735 ( .B0(n6393), .B1(n6830), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[14]), .Y(n2031) );
INVX1TS U7736 ( .A(FPSENCOS_d_ff_Xn[14]), .Y(n6416) );
AOI22X1TS U7737 ( .A0(n6541), .A1(n6830), .B0(n6416), .B1(n6528), .Y(n2030)
);
OAI2BB2XLTS U7738 ( .B0(n6394), .B1(n6634), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[15]), .Y(n2029) );
OAI2BB2XLTS U7739 ( .B0(n6389), .B1(n6634), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[15]), .Y(n2028) );
OAI2BB2XLTS U7740 ( .B0(n6555), .B1(n6634), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[15]), .Y(n2027) );
OAI2BB2XLTS U7741 ( .B0(n6394), .B1(n6655), .A0N(n6390), .A1N(
FPSENCOS_d_ff_Zn[16]), .Y(n2026) );
OAI2BB2XLTS U7742 ( .B0(n6393), .B1(n6655), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[16]), .Y(n2025) );
AOI22X1TS U7743 ( .A0(n6392), .A1(n6655), .B0(n2414), .B1(n6539), .Y(n2024)
);
OAI2BB2XLTS U7744 ( .B0(n6394), .B1(n6650), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[17]), .Y(n2023) );
OAI2BB2XLTS U7745 ( .B0(n6393), .B1(n6650), .A0N(n6391), .A1N(
FPSENCOS_d_ff_Yn[17]), .Y(n2022) );
INVX1TS U7746 ( .A(FPSENCOS_d_ff_Xn[17]), .Y(n6419) );
AOI22X1TS U7747 ( .A0(n6392), .A1(n6650), .B0(n6419), .B1(n6539), .Y(n2021)
);
OAI2BB2XLTS U7748 ( .B0(n6394), .B1(n6638), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[18]), .Y(n2020) );
OAI2BB2XLTS U7749 ( .B0(n6393), .B1(n6638), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[18]), .Y(n2019) );
OAI2BB2XLTS U7750 ( .B0(n6555), .B1(n6638), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[18]), .Y(n2018) );
OAI2BB2XLTS U7751 ( .B0(n6394), .B1(n6644), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[19]), .Y(n2017) );
OAI2BB2XLTS U7752 ( .B0(n6393), .B1(n6644), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[19]), .Y(n2016) );
INVX1TS U7753 ( .A(FPSENCOS_d_ff_Xn[19]), .Y(n6422) );
AOI22X1TS U7754 ( .A0(n6392), .A1(n6644), .B0(n6422), .B1(n6539), .Y(n2015)
);
OAI2BB2XLTS U7755 ( .B0(n6394), .B1(n6647), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[20]), .Y(n2014) );
OAI2BB2XLTS U7756 ( .B0(n6393), .B1(n6647), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[20]), .Y(n2013) );
INVX1TS U7757 ( .A(FPSENCOS_d_ff_Xn[20]), .Y(n6424) );
AOI22X1TS U7758 ( .A0(n6541), .A1(n6647), .B0(n6424), .B1(n6539), .Y(n2012)
);
OAI2BB2XLTS U7759 ( .B0(n6394), .B1(n6641), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[21]), .Y(n2011) );
OAI2BB2XLTS U7760 ( .B0(n6535), .B1(n6641), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[21]), .Y(n2010) );
OAI2BB2XLTS U7761 ( .B0(n6555), .B1(n6641), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[21]), .Y(n2009) );
OAI2BB2XLTS U7762 ( .B0(n6538), .B1(n6631), .A0N(n6395), .A1N(
FPSENCOS_d_ff_Zn[22]), .Y(n2008) );
OAI2BB2XLTS U7763 ( .B0(n6535), .B1(n6631), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[22]), .Y(n2007) );
OAI2BB2XLTS U7764 ( .B0(n6555), .B1(n6631), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[22]), .Y(n2006) );
OAI2BB2XLTS U7765 ( .B0(n6396), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[0]), .A1N(
n6427), .Y(n2005) );
AOI22X1TS U7766 ( .A0(n6414), .A1(n6397), .B0(n6398), .B1(n6413), .Y(n2003)
);
OAI2BB2XLTS U7767 ( .B0(n6442), .B1(n6398), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[1]), .Y(n2002) );
AOI22X1TS U7768 ( .A0(n6414), .A1(n2401), .B0(n6399), .B1(n6413), .Y(n2001)
);
AOI22X1TS U7769 ( .A0(n6414), .A1(n6400), .B0(n6401), .B1(n6413), .Y(n1999)
);
OAI2BB2XLTS U7770 ( .B0(n6442), .B1(n6401), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1998) );
BUFX3TS U7771 ( .A(n6445), .Y(n6468) );
OAI2BB2XLTS U7772 ( .B0(n6402), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[4]), .A1N(
n6468), .Y(n1997) );
INVX2TS U7773 ( .A(n6448), .Y(n6429) );
OAI2BB2XLTS U7774 ( .B0(n6429), .B1(n6402), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[4]), .Y(n1996) );
AOI22X1TS U7775 ( .A0(n6414), .A1(n6403), .B0(n6404), .B1(n6413), .Y(n1995)
);
INVX2TS U7776 ( .A(n6448), .Y(n6440) );
OAI2BB2XLTS U7777 ( .B0(n6429), .B1(n6404), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1994) );
AOI22X1TS U7778 ( .A0(n6414), .A1(n2440), .B0(n2422), .B1(n6413), .Y(n1993)
);
OAI2BB2XLTS U7779 ( .B0(n6429), .B1(n2422), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[6]), .Y(n1992) );
AOI22X1TS U7780 ( .A0(n6414), .A1(n6405), .B0(n6406), .B1(n2302), .Y(n1991)
);
OAI2BB2XLTS U7781 ( .B0(n6429), .B1(n6406), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1990) );
OAI2BB2XLTS U7782 ( .B0(n6407), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[8]), .A1N(
n6468), .Y(n1989) );
OAI2BB2XLTS U7783 ( .B0(n6429), .B1(n6407), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[8]), .Y(n1988) );
OAI2BB2XLTS U7784 ( .B0(n6409), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[9]), .A1N(
n6468), .Y(n1987) );
OAI2BB2XLTS U7785 ( .B0(n6429), .B1(n6409), .A0N(n6408), .A1N(
FPSENCOS_d_ff3_sh_x_out[9]), .Y(n1986) );
BUFX3TS U7786 ( .A(n6414), .Y(n6452) );
AOI22X1TS U7787 ( .A0(n6452), .A1(n2447), .B0(n2449), .B1(n6413), .Y(n1985)
);
INVX2TS U7788 ( .A(n6449), .Y(n6470) );
OAI2BB2XLTS U7789 ( .B0(n6470), .B1(n2449), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[10]), .Y(n1984) );
OAI2BB2XLTS U7790 ( .B0(n6410), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[11]),
.A1N(n6427), .Y(n1983) );
OAI2BB2XLTS U7791 ( .B0(n6470), .B1(n6410), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1982) );
AOI22X1TS U7792 ( .A0(n6452), .A1(n6411), .B0(n6412), .B1(n6413), .Y(n1981)
);
OAI2BB2XLTS U7793 ( .B0(n6442), .B1(n6412), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[12]), .Y(n1980) );
AOI22X1TS U7794 ( .A0(n6452), .A1(n2424), .B0(n2425), .B1(n6413), .Y(n1979)
);
OAI2BB2XLTS U7795 ( .B0(n6470), .B1(n2425), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1978) );
INVX2TS U7796 ( .A(n6415), .Y(n6430) );
AOI22X1TS U7797 ( .A0(n4723), .A1(n6416), .B0(n6417), .B1(n6469), .Y(n1977)
);
OAI2BB2XLTS U7798 ( .B0(n6429), .B1(n6417), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1976) );
OAI2BB2XLTS U7799 ( .B0(n6418), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[15]),
.A1N(n6468), .Y(n1975) );
OAI2BB2XLTS U7800 ( .B0(n6470), .B1(n6418), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1974) );
AOI22X1TS U7801 ( .A0(n4723), .A1(n2414), .B0(n2417), .B1(n6431), .Y(n1973)
);
OAI2BB2XLTS U7802 ( .B0(n6470), .B1(n2417), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1972) );
AOI22X1TS U7803 ( .A0(n4723), .A1(n6419), .B0(n6420), .B1(n6430), .Y(n1971)
);
OAI2BB2XLTS U7804 ( .B0(n6429), .B1(n6420), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1970) );
OAI2BB2XLTS U7805 ( .B0(n6421), .B1(n6439), .A0N(FPSENCOS_d_ff_Xn[18]),
.A1N(n6427), .Y(n1969) );
OAI2BB2XLTS U7806 ( .B0(n6470), .B1(n6421), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1968) );
AOI22X1TS U7807 ( .A0(n6452), .A1(n6422), .B0(n6423), .B1(n6453), .Y(n1967)
);
OAI2BB2XLTS U7808 ( .B0(n6470), .B1(n6423), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1966) );
AOI22X1TS U7809 ( .A0(n4723), .A1(n6424), .B0(n6425), .B1(n6431), .Y(n1965)
);
OAI2BB2XLTS U7810 ( .B0(n6442), .B1(n6425), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1964) );
OAI2BB2XLTS U7811 ( .B0(n6426), .B1(n6439), .A0N(FPSENCOS_d_ff_Xn[21]),
.A1N(n6427), .Y(n1963) );
OAI2BB2XLTS U7812 ( .B0(n6429), .B1(n6426), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[21]), .Y(n1962) );
OAI2BB2XLTS U7813 ( .B0(n2416), .B1(n2301), .A0N(FPSENCOS_d_ff_Xn[22]),
.A1N(n6427), .Y(n1961) );
OAI2BB2XLTS U7814 ( .B0(n6429), .B1(n2416), .A0N(n6428), .A1N(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1960) );
INVX1TS U7815 ( .A(FPSENCOS_d_ff_Xn[24]), .Y(n6525) );
AOI22X1TS U7816 ( .A0(n4723), .A1(n6525), .B0(n6873), .B1(n4731), .Y(n1958)
);
AOI22X1TS U7817 ( .A0(n6445), .A1(n2452), .B0(n6874), .B1(n6431), .Y(n1957)
);
INVX1TS U7818 ( .A(FPSENCOS_d_ff_Xn[26]), .Y(n6529) );
AOI22X1TS U7819 ( .A0(n4558), .A1(n6529), .B0(n6875), .B1(n4731), .Y(n1956)
);
INVX1TS U7820 ( .A(FPSENCOS_d_ff_Xn[27]), .Y(n6532) );
AOI22X1TS U7821 ( .A0(n6445), .A1(n6532), .B0(n6872), .B1(n6431), .Y(n1955)
);
INVX1TS U7822 ( .A(FPSENCOS_d_ff_Xn[28]), .Y(n6536) );
AOI22X1TS U7823 ( .A0(n4723), .A1(n6536), .B0(n6838), .B1(n4731), .Y(n1954)
);
AOI22X1TS U7824 ( .A0(n6414), .A1(n2431), .B0(n6871), .B1(n4731), .Y(n1953)
);
AOI21X1TS U7825 ( .A0(intadd_518_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n6433),
.Y(n6432) );
AOI21X1TS U7826 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n6436), .B0(n6435), .Y(
n6437) );
OAI2BB2XLTS U7827 ( .B0(n6441), .B1(n6439), .A0N(n6468), .A1N(
FPSENCOS_d_ff_Xn[31]), .Y(n1943) );
OAI2BB2XLTS U7828 ( .B0(n6442), .B1(n6441), .A0N(n6440), .A1N(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1942) );
OAI2BB2XLTS U7829 ( .B0(n6538), .B1(n6554), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[31]), .Y(n1909) );
OAI2BB2XLTS U7830 ( .B0(n6535), .B1(n6554), .A0N(n6443), .A1N(
FPSENCOS_d_ff_Yn[31]), .Y(n1908) );
OAI2BB2XLTS U7831 ( .B0(n6450), .B1(n2281), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[0]), .Y(n1906) );
OAI2BB2XLTS U7832 ( .B0(n6450), .B1(n2428), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[1]), .Y(n1904) );
BUFX3TS U7833 ( .A(n6445), .Y(n6447) );
OAI2BB2XLTS U7834 ( .B0(n6450), .B1(n2282), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[2]), .Y(n1902) );
OAI2BB2XLTS U7835 ( .B0(n4554), .B1(n2435), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[4]), .Y(n1898) );
INVX2TS U7836 ( .A(n6439), .Y(n6446) );
OAI2BB2XLTS U7837 ( .B0(n6450), .B1(n2439), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[6]), .Y(n1894) );
INVX2TS U7838 ( .A(n6449), .Y(n6451) );
OAI2BB2XLTS U7839 ( .B0(n6450), .B1(n2419), .A0N(n6444), .A1N(
FPSENCOS_d_ff2_Y[8]), .Y(n1890) );
OAI2BB2XLTS U7840 ( .B0(n4554), .B1(n2436), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[9]), .Y(n1888) );
OAI2BB2XLTS U7841 ( .B0(n6450), .B1(n2446), .A0N(n6459), .A1N(
FPSENCOS_d_ff2_Y[10]), .Y(n1886) );
OAI2BB2XLTS U7842 ( .B0(n4554), .B1(n2453), .A0N(n6444), .A1N(
FPSENCOS_d_ff2_Y[12]), .Y(n1882) );
BUFX3TS U7843 ( .A(n6445), .Y(n6454) );
INVX2TS U7844 ( .A(n6415), .Y(n6453) );
OAI2BB2XLTS U7845 ( .B0(n6450), .B1(n6876), .A0N(n6449), .A1N(
FPSENCOS_d_ff2_Y[21]), .Y(n1864) );
NAND2X1TS U7846 ( .A(FPSENCOS_d_ff2_Y[23]), .B(n2300), .Y(n6458) );
AOI32X1TS U7847 ( .A0(intadd_517_CI), .A1(n6449), .A2(n6458), .B0(n6457),
.B1(n6456), .Y(n1853) );
OAI2BB2XLTS U7848 ( .B0(n4554), .B1(n2445), .A0N(n6459), .A1N(
intadd_517_SUM_2_), .Y(n1850) );
AOI21X1TS U7849 ( .A0(intadd_517_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n6461),
.Y(n6460) );
NAND2X1TS U7850 ( .A(n6461), .B(n6841), .Y(n6463) );
AOI21X1TS U7851 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n6463), .B0(n6466), .Y(
n6465) );
AOI22X1TS U7852 ( .A0(Data_2[3]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n6479), .Y(n6473) );
AOI22X1TS U7853 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n6485),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n6472) );
NAND2X1TS U7854 ( .A(n6474), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n6491) );
AOI22X1TS U7855 ( .A0(Data_2[5]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n6479), .Y(n6476) );
AOI22X1TS U7856 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n6485),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n6475) );
NAND2X1TS U7857 ( .A(n6474), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n6486) );
AOI22X1TS U7858 ( .A0(Data_2[7]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n6479), .Y(n6478) );
AOI22X1TS U7859 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n6477) );
NAND2X1TS U7860 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n6480) );
AOI22X1TS U7861 ( .A0(Data_2[11]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n6479), .Y(n6482) );
AOI22X1TS U7862 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n6485),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n6481) );
AOI22X1TS U7863 ( .A0(Data_2[13]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n6505), .Y(n6484) );
AOI22X1TS U7864 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n6483) );
NAND2X1TS U7865 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n6497) );
AOI22X1TS U7866 ( .A0(Data_2[14]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n6505), .Y(n6488) );
AOI22X1TS U7867 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n6485),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n6487) );
AOI22X1TS U7868 ( .A0(Data_2[15]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n6505), .Y(n6490) );
AOI22X1TS U7869 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n6489) );
NAND2X1TS U7870 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n6502) );
AOI22X1TS U7871 ( .A0(Data_2[16]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n6505), .Y(n6493) );
AOI22X1TS U7872 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n6492) );
AOI22X1TS U7873 ( .A0(Data_2[17]), .A1(n6494), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n6505), .Y(n6496) );
AOI22X1TS U7874 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n6495) );
AOI22X1TS U7875 ( .A0(Data_2[18]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n6505), .Y(n6499) );
AOI22X1TS U7876 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n6498) );
AOI22X1TS U7877 ( .A0(Data_2[19]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n6505), .Y(n6501) );
AOI22X1TS U7878 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n6500) );
NAND2X1TS U7879 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n6506) );
AOI22X1TS U7880 ( .A0(Data_2[20]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n6505), .Y(n6504) );
AOI22X1TS U7881 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n6503) );
AOI22X1TS U7882 ( .A0(Data_2[22]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n6505), .Y(n6508) );
AOI22X1TS U7883 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n6507) );
AOI22X1TS U7884 ( .A0(Data_2[27]), .A1(n6509), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n6548), .Y(n6512) );
AOI22X1TS U7885 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n6510),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n6511) );
NAND2X1TS U7886 ( .A(n4999), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n6515) );
AOI22X1TS U7887 ( .A0(Data_2[28]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n6548), .Y(n6514) );
AOI22X1TS U7888 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n6549),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n6513) );
AOI22X1TS U7889 ( .A0(Data_2[29]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n6548), .Y(n6517) );
AOI22X1TS U7890 ( .A0(n6550), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n6549),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n6516) );
AOI22X1TS U7891 ( .A0(Data_2[30]), .A1(n6518), .B0(FPADDSUB_intDY_EWSW[30]),
.B1(n6548), .Y(n6520) );
AOI22X1TS U7892 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n6549),
.B1(FPSENCOS_d_ff3_sh_x_out[30]), .Y(n6519) );
NAND2X1TS U7893 ( .A(n6520), .B(n6519), .Y(n1813) );
OAI22X1TS U7894 ( .A0(n6522), .A1(n6521), .B0(n5265), .B1(n2504), .Y(n1812)
);
OAI2BB2XLTS U7895 ( .B0(n6538), .B1(n6524), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[23]), .Y(n1786) );
OAI2BB2XLTS U7896 ( .B0(n6535), .B1(n6524), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[23]), .Y(n1785) );
OAI2BB2XLTS U7897 ( .B0(n6555), .B1(n6524), .A0N(n6523), .A1N(
FPSENCOS_d_ff_Xn[23]), .Y(n1784) );
OAI2BB2XLTS U7898 ( .B0(n6538), .B1(n6526), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[24]), .Y(n1783) );
OAI2BB2XLTS U7899 ( .B0(n6535), .B1(n6526), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[24]), .Y(n1782) );
AOI22X1TS U7900 ( .A0(n6541), .A1(n6526), .B0(n6525), .B1(n6528), .Y(n1781)
);
OAI2BB2XLTS U7901 ( .B0(n6538), .B1(n6527), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[25]), .Y(n1780) );
OAI2BB2XLTS U7902 ( .B0(n6535), .B1(n6527), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[25]), .Y(n1779) );
AOI22X1TS U7903 ( .A0(n6541), .A1(n6527), .B0(n2452), .B1(n6528), .Y(n1778)
);
OAI2BB2XLTS U7904 ( .B0(n6538), .B1(n6530), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[26]), .Y(n1777) );
OAI2BB2XLTS U7905 ( .B0(n6535), .B1(n6530), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[26]), .Y(n1776) );
AOI22X1TS U7906 ( .A0(n6541), .A1(n6530), .B0(n6529), .B1(n6528), .Y(n1775)
);
OAI2BB2XLTS U7907 ( .B0(n6538), .B1(n6533), .A0N(n6531), .A1N(
FPSENCOS_d_ff_Zn[27]), .Y(n1774) );
OAI2BB2XLTS U7908 ( .B0(n6535), .B1(n6533), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[27]), .Y(n1773) );
AOI22X1TS U7909 ( .A0(n6541), .A1(n6533), .B0(n6532), .B1(n6528), .Y(n1772)
);
OAI2BB2XLTS U7910 ( .B0(n6538), .B1(n6537), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[28]), .Y(n1771) );
OAI2BB2XLTS U7911 ( .B0(n6535), .B1(n6537), .A0N(n6534), .A1N(
FPSENCOS_d_ff_Yn[28]), .Y(n1770) );
AOI22X1TS U7912 ( .A0(n6541), .A1(n6537), .B0(n6536), .B1(n6528), .Y(n1769)
);
OAI2BB2XLTS U7913 ( .B0(n6538), .B1(n6540), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[29]), .Y(n1768) );
AOI22X1TS U7914 ( .A0(n6541), .A1(n6540), .B0(n2431), .B1(n6528), .Y(n1766)
);
OAI2BB2XLTS U7915 ( .B0(n6543), .B1(n2451), .A0N(n6542), .A1N(
FPSENCOS_d_ff_Zn[30]), .Y(n1765) );
AOI22X1TS U7916 ( .A0(operation[0]), .A1(n4996), .B0(FPADDSUB_intAS), .B1(
n6548), .Y(n6547) );
OAI21XLTS U7917 ( .A0(FPSENCOS_cont_var_out[0]), .A1(FPSENCOS_d_ff3_sign_out), .B0(n6545), .Y(n6546) );
OAI2BB2XLTS U7918 ( .B0(n6555), .B1(n2451), .A0N(n6553), .A1N(
FPSENCOS_d_ff_Xn[30]), .Y(n1729) );
AOI22X1TS U7919 ( .A0(Data_2[31]), .A1(n4996), .B0(FPADDSUB_intDY_EWSW[31]),
.B1(n6548), .Y(n6552) );
AOI22X1TS U7920 ( .A0(n2388), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n6549),
.B1(FPSENCOS_d_ff3_sh_x_out[31]), .Y(n6551) );
NAND2X1TS U7921 ( .A(n6552), .B(n6551), .Y(n1728) );
OAI2BB2XLTS U7922 ( .B0(n6555), .B1(n6554), .A0N(n6553), .A1N(
FPSENCOS_d_ff_Xn[31]), .Y(n1727) );
AOI22X1TS U7923 ( .A0(n6557), .A1(FPSENCOS_d_ff_Xn[31]), .B0(
FPSENCOS_d_ff_Yn[31]), .B1(n6556), .Y(n6560) );
XOR2X1TS U7924 ( .A(n6560), .B(n6559), .Y(n6561) );
OAI2BB2XLTS U7925 ( .B0(n6562), .B1(n6561), .A0N(n6562), .A1N(
cordic_result[31]), .Y(n1695) );
NOR2XLTS U7926 ( .A(n6757), .B(n6787), .Y(n6563) );
OAI22X1TS U7927 ( .A0(n6564), .A1(n6563), .B0(n6751), .B1(n6787), .Y(n6565)
);
NOR4X1TS U7928 ( .A(n6567), .B(n2346), .C(FPMULT_Op_MX[7]), .D(
DP_OP_501J223_127_5235_n944), .Y(n6576) );
NOR4X1TS U7929 ( .A(n6569), .B(n2481), .C(n6568), .D(FPMULT_Op_MX[2]), .Y(
n6575) );
NOR4X1TS U7930 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[5]), .C(
FPMULT_Op_MX[18]), .D(n6570), .Y(n6574) );
NOR4X1TS U7931 ( .A(n2292), .B(n6572), .C(n2287), .D(FPMULT_Op_MX[19]), .Y(
n6573) );
NAND4XLTS U7932 ( .A(n6576), .B(n6575), .C(n6574), .D(n6573), .Y(n6603) );
NOR4X1TS U7933 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_Op_MX[27]), .C(
FPMULT_Op_MX[26]), .D(FPMULT_Op_MX[25]), .Y(n6583) );
NOR4X1TS U7934 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[13]), .C(
FPMULT_Op_MX[12]), .D(FPMULT_Op_MX[14]), .Y(n6582) );
NOR4X1TS U7935 ( .A(n2285), .B(FPMULT_Op_MX[17]), .C(FPMULT_Op_MX[30]), .D(
FPMULT_Op_MX[29]), .Y(n6581) );
NAND4XLTS U7936 ( .A(n6583), .B(n6582), .C(n6581), .D(n6580), .Y(n6602) );
NOR4X1TS U7937 ( .A(n2383), .B(n2228), .C(n5642), .D(n6584), .Y(n6592) );
NOR4X1TS U7938 ( .A(DP_OP_501J223_127_5235_n903), .B(n2220), .C(n6955), .D(
n2291), .Y(n6591) );
NOR4X1TS U7939 ( .A(n2289), .B(FPMULT_Op_MY[4]), .C(n6587), .D(
FPMULT_Op_MY[2]), .Y(n6590) );
NOR4X1TS U7940 ( .A(n2201), .B(n5643), .C(FPMULT_Op_MY[8]), .D(n6753), .Y(
n6589) );
NAND4XLTS U7941 ( .A(n6592), .B(n6591), .C(n6590), .D(n6589), .Y(n6601) );
NOR4X1TS U7942 ( .A(FPMULT_Op_MY[28]), .B(FPMULT_Op_MY[27]), .C(
FPMULT_Op_MY[26]), .D(FPMULT_Op_MY[25]), .Y(n6599) );
NOR4X1TS U7943 ( .A(n2290), .B(n6594), .C(FPMULT_Op_MY[14]), .D(
FPMULT_Op_MY[12]), .Y(n6598) );
NOR4X1TS U7944 ( .A(n6595), .B(FPMULT_Op_MY[13]), .C(FPMULT_Op_MY[30]), .D(
FPMULT_Op_MY[29]), .Y(n6597) );
NAND4XLTS U7945 ( .A(n6599), .B(n6598), .C(n6597), .D(n6596), .Y(n6600) );
OA22X1TS U7946 ( .A0(n6603), .A1(n6602), .B0(n6601), .B1(n6600), .Y(n6604)
);
OAI2BB2XLTS U7947 ( .B0(n6605), .B1(n6604), .A0N(n6605), .A1N(
FPMULT_zero_flag), .Y(n1625) );
OA22X1TS U7948 ( .A0(n6615), .A1(mult_result[23]), .B0(
FPMULT_exp_oper_result[0]), .B1(n6613), .Y(n1584) );
OA22X1TS U7949 ( .A0(n6607), .A1(mult_result[24]), .B0(
FPMULT_exp_oper_result[1]), .B1(n6608), .Y(n1583) );
OA22X1TS U7950 ( .A0(n6607), .A1(mult_result[25]), .B0(
FPMULT_exp_oper_result[2]), .B1(n6608), .Y(n1582) );
OA22X1TS U7951 ( .A0(n6607), .A1(mult_result[26]), .B0(
FPMULT_exp_oper_result[3]), .B1(n6608), .Y(n1581) );
OA22X1TS U7952 ( .A0(n6607), .A1(mult_result[27]), .B0(
FPMULT_exp_oper_result[4]), .B1(n6608), .Y(n1580) );
OA22X1TS U7953 ( .A0(n6607), .A1(mult_result[28]), .B0(
FPMULT_exp_oper_result[5]), .B1(n6608), .Y(n1579) );
OA22X1TS U7954 ( .A0(n6615), .A1(mult_result[29]), .B0(
FPMULT_exp_oper_result[6]), .B1(n6608), .Y(n1578) );
OA22X1TS U7955 ( .A0(n6615), .A1(mult_result[30]), .B0(
FPMULT_exp_oper_result[7]), .B1(n6608), .Y(n1577) );
INVX2TS U7956 ( .A(n6615), .Y(n6614) );
OAI2BB1X1TS U7957 ( .A0N(mult_result[31]), .A1N(n6614), .B0(n6611), .Y(n1576) );
INVX2TS U7958 ( .A(n6613), .Y(n6612) );
INVX2TS U7959 ( .A(n6613), .Y(n6616) );
INVX2TS U7960 ( .A(n6615), .Y(n6618) );
INVX2TS U7961 ( .A(n6738), .Y(n6739) );
BUFX3TS U7962 ( .A(n6656), .Y(n6741) );
BUFX3TS U7963 ( .A(n6656), .Y(n6736) );
INVX2TS U7964 ( .A(n6738), .Y(n6635) );
INVX2TS U7965 ( .A(n6741), .Y(n6731) );
OAI2BB2XLTS U7966 ( .B0(n6739), .B1(n6820), .A0N(n6731), .A1N(
intadd_516_SUM_0_), .Y(n1476) );
XNOR2X1TS U7967 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(
FPADDSUB_DmP_EXP_EWSW[27]), .Y(n6621) );
XOR2X1TS U7968 ( .A(intadd_516_n1), .B(n6621), .Y(n6622) );
AO22XLTS U7969 ( .A0(n2317), .A1(FPADDSUB_DMP_SFG[23]), .B0(n2501), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1454) );
INVX2TS U7970 ( .A(n6624), .Y(n6709) );
AO22XLTS U7971 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(
FPADDSUB_DMP_SFG[24]), .B0(n2501), .B1(FPADDSUB_DMP_exp_NRM_EW[1]),
.Y(n1449) );
INVX2TS U7972 ( .A(n6738), .Y(n6657) );
OA21XLTS U7973 ( .A0(n7060), .A1(underflow_flag_addsubt), .B0(n6626), .Y(
n1412) );
INVX2TS U7974 ( .A(n6627), .Y(n6664) );
INVX4TS U7975 ( .A(n6629), .Y(n6660) );
OAI22X1TS U7976 ( .A0(n7060), .A1(n6631), .B0(n6630), .B1(n6660), .Y(n1408)
);
OAI22X1TS U7977 ( .A0(n2366), .A1(n6634), .B0(n6633), .B1(n2374), .Y(n1405)
);
OAI22X1TS U7978 ( .A0(n7060), .A1(n6638), .B0(n6637), .B1(n6660), .Y(n1402)
);
OAI22X1TS U7979 ( .A0(n2366), .A1(n6641), .B0(n6640), .B1(n2374), .Y(n1399)
);
OAI22X1TS U7980 ( .A0(n2366), .A1(n6644), .B0(n6643), .B1(n6660), .Y(n1396)
);
OAI22X1TS U7981 ( .A0(n2366), .A1(n6647), .B0(n6646), .B1(n2374), .Y(n1393)
);
OAI2BB2XLTS U7982 ( .B0(n6739), .B1(n6854), .A0N(n6731), .A1N(
FPADDSUB_DmP_EXP_EWSW[20]), .Y(n1391) );
OAI22X1TS U7983 ( .A0(n2366), .A1(n6650), .B0(n6649), .B1(n2374), .Y(n1390)
);
OAI22X1TS U7984 ( .A0(n2366), .A1(n6652), .B0(n6651), .B1(n6660), .Y(n1381)
);
OAI22X1TS U7985 ( .A0(n2366), .A1(n6655), .B0(n6654), .B1(n6660), .Y(n1378)
);
OAI22X1TS U7986 ( .A0(n2366), .A1(n6659), .B0(n6658), .B1(n2374), .Y(n1375)
);
INVX2TS U7987 ( .A(n6738), .Y(n6744) );
BUFX3TS U7988 ( .A(n6738), .Y(n6743) );
OAI22X1TS U7989 ( .A0(n2366), .A1(n6662), .B0(n6661), .B1(n2374), .Y(n1372)
);
OAI22X1TS U7990 ( .A0(n6730), .A1(n6830), .B0(n6665), .B1(n6660), .Y(n1369)
);
OAI22X1TS U7991 ( .A0(n6730), .A1(n6831), .B0(n6666), .B1(n6728), .Y(n1366)
);
OAI22X1TS U7992 ( .A0(n7060), .A1(n6832), .B0(n6667), .B1(n2374), .Y(n1363)
);
CLKXOR2X2TS U7993 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n6717) );
NOR2BX1TS U7994 ( .AN(FPADDSUB_intDX_EWSW[31]), .B(n6668), .Y(n6716) );
AOI22X1TS U7995 ( .A0(n2215), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n2279), .B1(
FPADDSUB_intDY_EWSW[15]), .Y(n6669) );
AOI22X1TS U7996 ( .A0(n2413), .A1(FPADDSUB_intDY_EWSW[13]), .B0(n2411), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n6670) );
AOI22X1TS U7997 ( .A0(n2464), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n6804), .B1(
FPADDSUB_intDY_EWSW[26]), .Y(n6671) );
AOI22X1TS U7998 ( .A0(n2231), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n2275), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n6672) );
NOR4X1TS U7999 ( .A(n6676), .B(n6675), .C(n6674), .D(n6673), .Y(n6704) );
AOI22X1TS U8000 ( .A0(n2407), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2269), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n6677) );
AOI22X1TS U8001 ( .A0(n2232), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n2272), .B1(
FPADDSUB_intDY_EWSW[18]), .Y(n6678) );
AOI22X1TS U8002 ( .A0(n6805), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2434), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n6679) );
AOI22X1TS U8003 ( .A0(n2277), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2234), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n6680) );
NOR4X1TS U8004 ( .A(n6684), .B(n6683), .C(n6682), .D(n6681), .Y(n6703) );
AOI22X1TS U8005 ( .A0(n6812), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n2278), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n6685) );
AOI22X1TS U8006 ( .A0(n6811), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2408), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n6686) );
OAI22X1TS U8007 ( .A0(n2270), .A1(FPADDSUB_intDY_EWSW[8]), .B0(n6810), .B1(
FPADDSUB_intDY_EWSW[30]), .Y(n6687) );
OAI22X1TS U8008 ( .A0(n2230), .A1(FPADDSUB_intDY_EWSW[11]), .B0(n2271), .B1(
FPADDSUB_intDY_EWSW[19]), .Y(n6689) );
AOI221X1TS U8009 ( .A0(n2230), .A1(FPADDSUB_intDY_EWSW[11]), .B0(
FPADDSUB_intDY_EWSW[19]), .B1(n2271), .C0(n6689), .Y(n6697) );
OAI22X1TS U8010 ( .A0(n2233), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n2274), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n6690) );
OAI22X1TS U8011 ( .A0(n2273), .A1(FPADDSUB_intDY_EWSW[2]), .B0(n6692), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n6691) );
OAI22X1TS U8012 ( .A0(n2432), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n6803), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n6693) );
NOR4X1TS U8013 ( .A(n6701), .B(n6700), .C(n6699), .D(n6698), .Y(n6702) );
OAI22X1TS U8014 ( .A0(n6706), .A1(n6717), .B0(n6716), .B1(n6705), .Y(n6707)
);
OAI2BB1X1TS U8015 ( .A0N(FPADDSUB_SIGN_FLAG_EXP), .A1N(n6708), .B0(n6707),
.Y(n1362) );
AOI21X1TS U8016 ( .A0(n6717), .A1(n6716), .B0(n6715), .Y(n1355) );
OAI22X1TS U8017 ( .A0(n6730), .A1(n6833), .B0(n6719), .B1(n2374), .Y(n1329)
);
OAI22X1TS U8018 ( .A0(n6730), .A1(n6834), .B0(n6721), .B1(n6660), .Y(n1313)
);
INVX2TS U8019 ( .A(n6738), .Y(n6734) );
BUFX3TS U8020 ( .A(n6738), .Y(n6732) );
OAI22X1TS U8021 ( .A0(n6730), .A1(n2367), .B0(n6722), .B1(n2374), .Y(n1299)
);
OAI22X1TS U8022 ( .A0(n6730), .A1(n6835), .B0(n6724), .B1(n2374), .Y(n1292)
);
OAI2BB2XLTS U8023 ( .B0(n6739), .B1(n6855), .A0N(n6731), .A1N(
FPADDSUB_DmP_EXP_EWSW[1]), .Y(n1290) );
OAI22X1TS U8024 ( .A0(n6730), .A1(n6837), .B0(n6725), .B1(n6660), .Y(n1285)
);
OAI2BB2XLTS U8025 ( .B0(n6739), .B1(n6814), .A0N(n6731), .A1N(
FPADDSUB_DmP_EXP_EWSW[9]), .Y(n1283) );
OAI22X1TS U8026 ( .A0(n6730), .A1(n6836), .B0(n6729), .B1(n6660), .Y(n1278)
);
OAI2BB2XLTS U8027 ( .B0(n6739), .B1(n6815), .A0N(n6731), .A1N(
FPADDSUB_DmP_EXP_EWSW[12]), .Y(n1270) );
INVX2TS U8028 ( .A(n6738), .Y(n6742) );
INVX2TS U8029 ( .A(n6733), .Y(n6737) );
CMPR42X2TS U8030 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .C(n6747),
.D(DP_OP_499J223_125_1651_n299), .ICI(DP_OP_499J223_125_1651_n232),
.S(DP_OP_499J223_125_1651_n231), .ICO(DP_OP_499J223_125_1651_n229),
.CO(DP_OP_499J223_125_1651_n230) );
CMPR42X1TS U8031 ( .A(DP_OP_502J223_128_4510_n172), .B(
DP_OP_502J223_128_4510_n186), .C(DP_OP_502J223_128_4510_n179), .D(
DP_OP_502J223_128_4510_n127), .ICI(DP_OP_502J223_128_4510_n126), .S(
DP_OP_502J223_128_4510_n123), .ICO(DP_OP_502J223_128_4510_n121), .CO(
DP_OP_502J223_128_4510_n122) );
CMPR42X1TS U8032 ( .A(DP_OP_500J223_126_4510_n172), .B(
DP_OP_500J223_126_4510_n186), .C(DP_OP_500J223_126_4510_n179), .D(
DP_OP_500J223_126_4510_n127), .ICI(DP_OP_500J223_126_4510_n126), .S(
DP_OP_500J223_126_4510_n123), .ICO(DP_OP_500J223_126_4510_n121), .CO(
DP_OP_500J223_126_4510_n122) );
endmodule
|
module M95XXX_DRV(
C,
D,
Q,
S,
W,
HOLD,
VCC,
VSS
);
//-------------------------------------
input Q;
output C,D,S,W,HOLD,VCC,VSS;
//-------------------------------------
integer i,j,n;
integer add_bytes,instructionA8;
reg C,D,S,W,HOLD,VCC,VSS;
reg[7:0] sr,read_dat;
reg[7:0] data;
reg[3*8-1:0] d_address;
//-------------------------------------
initial begin
if (`MEM_ADDR_BITS <= 9)
add_bytes = 1;
else if (9 < `MEM_ADDR_BITS && `MEM_ADDR_BITS <= 16)
add_bytes = 2;
else if (16 < `MEM_ADDR_BITS && `MEM_ADDR_BITS <= 24)
add_bytes = 3;
else
add_bytes = 2;
if (`MEM_ADDR_BITS == 9)
instructionA8 = 1;
else
instructionA8 = 0;
VSS = 1'b0;
VCC = 1'b1;
#100;
S = 1'b1;
#100;
S = 1'b0; ///HOLD and /W are not driven before this instruction. Model will warn to user.
#100;
VCC = 1'b0;
#100;
VCC = 1'b1;
#100;
S = 1'b1;
W = 1'b1; ///W is driven high
HOLD = 1'b1; ///HOLD is driven high
#100;
//---------------------------------------
$display("======================================================================");
$display("== TESTING1: READ/WRITE STATUS REGISTER INSTRUCTION VERIFICATION. ==");
$display("======================================================================");
W = 1;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b1111_1111);
READ_STATUS_REGISTER; //should be "0000_0011"
//bit0(WIP) is "1" during the WRSR cycle. bit1(WEL) is "1". bit 4,5,6 are always "0"
// #(M95XXX_SIM.M95XXX_Macro_mux.tW);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "1000_1100"
//bit0(WIP) is "0" and bit1(WEL) is reset when WRSR cycle is completed.
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000);
READ_STATUS_REGISTER; //should be "1000_1111"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "0000_0000"
W = 0;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b1111_1111);
READ_STATUS_REGISTER; //should be "0000_0011"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "1000_1100"
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000);
//W = 0, SRWD = 1, enter "HPM" this "WRSR" instruction is not executed and self-time WRSR cycle is not initiated.
READ_STATUS_REGISTER; //should be "1000_1110"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "1000_1110"
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0011);
READ_STATUS_REGISTER; //should be "1000_1110"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "1000_1110"
W = 1;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0011);
READ_STATUS_REGISTER; //should be "1000_1111"
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_STATUS_REGISTER; //should be "0000_0000"
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//---------------------------------------
$display("=======================================================");
$display("== TESTING2: MEMORY ARRAY READ/WRITE VERIFICATION. ==");
$display("=======================================================");
W = 1;
// READ_DATA_BYTES(2,`MEM_ADDR_BITS'h3ff);
READ_DATA_BYTES(2,{`MEM_ADDR_BITS {1'b1}});
WRITE_ENABLE;
// WRITE_DATA_IN(64,`DATA_BITS'h55,`MEM_ADDR_BITS'h3ff);
WRITE_DATA_IN(`PAGE_SIZE,`DATA_BITS'h55,{`MEM_ADDR_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
// READ_DATA_BYTES(34,`MEM_ADDR_BITS'h3df);
READ_DATA_BYTES(`PAGE_SIZE+2,{`MEM_ADDR_BITS {1'b1}}-`PAGE_SIZE);
WRITE_DATA_IN(`PAGE_SIZE,`DATA_BITS'h55,{`MEM_ADDR_BITS {1'b1}}); //This Write Enable Instruction will not be executed.
WRITE_ENABLE;
WRITE_DATA_IN(2,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//WRITE WITH POLLING (RDSR)
$display("=WRITE WITH POLLING (loop on read status register)");
WRITE_ENABLE;
WRITE_DATA_IN(2,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGE_SIZE-1);
POLLING_WITH_SEL_LOOP_ON_RDSR_DESEL; // replacing TW by polling routine #(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//WRITE WITH POLLING (RDSR)
$display("=WRITE WITH POLLING (loop on select read status register deselect)");
WRITE_ENABLE;
WRITE_DATA_IN(2,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGE_SIZE-1);
POLLING_WITH_LOOP_ON_SEL_RDSR_DESEL; // replacing TW by polling routine #(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_DATA_IN(2,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGE_SIZE-1);
READ_STATUS_REGISTER; //should be "0000_0000"
#4.991e6;
READ_STATUS_REGISTER; //should be "0000_0000"
#500
READ_STATUS_REGISTER; //should be "0000_0000"
#10
READ_STATUS_REGISTER; //should be "0000_0000"
READ_STATUS_REGISTER; //should be "0000_0000"
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//---------------------------------------
$display("===================================================================================================");
$display("== TESTING3: ALL INSTRUCTIONS (except RDSR) ARE NOT EXECUTED WHILE WRITE CYCLE IS IN PROGRESS. ==");
$display("===================================================================================================");
W = 1;
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h11,{`MEM_ADDR_BITS {1'b0}});
WRITE_ENABLE;
WRITE_DISABLE;
WRITE_STATUS_REGISTER(8'b1000_0111);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
WRITE_DATA_IN(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}});
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//---------------------------------------
$display("===================================================================================================");
$display("== TESTING 3A: RANDOM TESTS ==");
$display("===================================================================================================");
W = 1;
//--------------------------------------------------------
//Enable and disable test with write data when disabled(rejected)
WRITE_ENABLE;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_DISABLE;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_DATA_IN(1,`DATA_BITS'h11,{`MEM_ADDR_BITS {1'b0}}); //rejected
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h11,{`MEM_ADDR_BITS {1'b0}});
WRITE_STATUS_REGISTER(8'b1000_0111); //rejected
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(4,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//Wrap around Test for write an read
WRITE_ENABLE;
WRITE_DATA_IN(3,`DATA_BITS'h55,{`MEM_ADDR_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(4,{`MEM_ADDR_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
READ_DATA_BYTES(4,{`MEM_ADDR_BITS {1'b1}}-`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//Read at the ID boundry and write beyond the boundry
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b0,{`PAGE_OFFSET_BITS {1'b1}}); //read beyond the ID boundry
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'h23,{`PAGE_OFFSET_BITS {1'b1}}); //2 written byte rejected beyond the boundry
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(3,1'b0,{`PAGE_OFFSET_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'h23,{`PAGE_OFFSET_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(3,1'b0,{`PAGE_OFFSET_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//write and read the entire ID page
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK({`PAGE_OFFSET_BITS {1'b1}}+1,1'b0,`DATA_BITS'hAA,{`PAGE_OFFSET_BITS {1'b0}}); //write the entire ID PAGE to 0xAA //{`PAGE_OFFSET_BITS {1'b1}}+1
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS({`PAGE_OFFSET_BITS {1'b1}}+1,1'b0,{`PAGE_OFFSET_BITS {1'b0}}); //read the whole ID PAGE
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//write and read LOCK ID STATUS
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(1,1'b1,`DATA_BITS'h02,`MEM_ADDR_BITS'h400); //write lock ID, accepted cause only 1 byte sent
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b1,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write lock id when it is already lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write ID memory when it is lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,{`PAGE_OFFSET_BITS {1'b1}});
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//write when memory disabled and a write polling the read status
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}});
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW/2);
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW/2);
READ_STATUS_REGISTER;
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
WRITE_DATA_IN(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}}); //rejected, write disabled
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//write when memory disabled and a write polling the read status,alternating clk fininsh on zero or one
WRITE_ENABLE;
WRITE_DATA_INh(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}});
READ_STATUS_REGISTER;
#(M95XXX_SIM.M95XXX_Macro_mux.tW/2);
READ_STATUS_REGISTERh;
#(M95XXX_SIM.M95XXX_Macro_mux.tW/2);
READ_STATUS_REGISTER;
READ_DATA_BYTESh(1,{`MEM_ADDR_BITS {1'b0}});
WRITE_DATA_IN(1,`DATA_BITS'h22,{`MEM_ADDR_BITS {1'b0}}); //rejected, write disabled
READ_STATUS_REGISTERh;
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_DATA_INh(`PAGE_SIZE,`DATA_BITS'h55,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTESh(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
WRITE_ENABLE;
WRITE_DATA_INh(`PAGE_SIZE/4,`DATA_BITS'h33,`PAGE_SIZE/2);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTESh(`PAGE_SIZE,{`MEM_ADDR_BITS {1'b0}});
READ_DATA_BYTES(`PAGE_SIZE,{{`MEM_ADDR_BITS-2 {1'b1}},2'b00});
WRITE_ENABLEh;
WRITE_DATA_INh(1,`DATA_BITS'hAA,{`MEM_ADDR_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,{`MEM_ADDR_BITS {1'b1}});
READ_DATA_BYTESh(1,{`MEM_ADDR_BITS {1'b0}});
//--------------------------------------------------------
//write and read LOCK ID STATUS, alternating clk fininsh on zero or one
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCKh(1,1'b1,`DATA_BITS'h02,`MEM_ADDR_BITS'h400); //write lock ID, accepted cause only 1 byte sent
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLEh;
WRITE_ID_PAGE_OR_LOCK(2,1'b1,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write lock id when it is already lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLEh;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write ID memory when it is lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,{`PAGE_OFFSET_BITS {1'b1}});
READ_ID_PAGE_OR_LOCK_STATUSh(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//--------------------------------------------------------
//--------------------------------------------------------
//---------------------------------------
$display("=========================================================================");
$display("== TESTING4: VERIFICATION OF ADDRESS INSIDE A WRITE PROTECTED ARRAY. ==");
$display("=========================================================================");
$display("------------------------------------------");
$display("-- Note: Memory Array is not Protected. --");
$display("------------------------------------------");
W = 1;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000); //No block of memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'h99,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("-------------------------------------------------------");
$display("-- Note: Upper quarter of Memory Array is Protected. --");
$display("-------------------------------------------------------");
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0100); //Upper quarter of memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'haa,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("----------------------------------------------------");
$display("-- Note: Upper half of Memory Array is Protected. --");
$display("----------------------------------------------------");
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_1000); //Upper half of memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hbb,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("--------------------------------------------");
$display("-- Note: Whole Memory Array is Protected. --");
$display("--------------------------------------------");
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_1100); //whole memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/2*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(2,`MEM_ADDR_BITS'd`PAGES/4*3*`PAGE_SIZE-1);
WRITE_ENABLE;
WRITE_DATA_IN(1,`DATA_BITS'hcc,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_DATA_BYTES(1,`MEM_ADDR_BITS'd`PAGES*`PAGE_SIZE-1);
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
//---------------------------------------
if (`IDPAGE)
begin
//---------------------------------------
$display("\n=====================================================");
$display("== TESTING5: MEMORY ID ARRAY READ/WRITE VERIFICATION. ==");
$display("========================================+++==========\n");
#20000;
W = 1;
$display("-------------------------------------------------------------");
$display("-- Note: Whole Memory Array is Protected --");
$display("-------------------------------------------------------------");
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_1100); //whole memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(1,1'b1,`DATA_BITS'ha5,`MEM_ADDR_BITS'h7ff); //write lock id when it bp1,bp0 = (1,1), not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,`MEM_ADDR_BITS'h3ff); //write ID memory when it bp1,bp0 = (1,1), not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000); //whole memory is protected
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
$display("\n-------------------------------------------------");
$display("-- Note: READ/WRITE MEMORY ID. --");
$display("-------------------------------------------------");
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b0,{`PAGE_OFFSET_BITS {1'b1}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'h23,{`PAGE_OFFSET_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b0,{`PAGE_OFFSET_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(3,1'b0,`DATA_BITS'hAA,{`PAGE_OFFSET_BITS {1'b1}}); //write the entire ID PAGE to 0xAA
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b0,{`PAGE_OFFSET_BITS {1'b1}}); //read the whole ID PAGE
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(`PAGE_SIZE,1'b0,`DATA_BITS'hAA,{`PAGE_OFFSET_BITS {1'b0}}); //write the entire ID PAGE to 0xAA
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ID_PAGE_OR_LOCK(`PAGE_SIZE,1'b0,`DATA_BITS'h55,{`PAGE_OFFSET_BITS {1'b1}}); //This Write Enable Instruction will not be executed.
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write last byte in page and first byte wrap
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(5,1'b0,`DATA_BITS'h13,`PAGE_OFFSET_BITS'h0A); //write starting at loc 0x13 location for 5 bytes
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(`PAGE_SIZE,1'b0,{`PAGE_OFFSET_BITS {1'b0}}); //read the whole ID PAGE
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("-------------------------------------------------------------------------------");
$display("-- Note: WRITE LOCK ID AND READ/WRITE MEMORY ID --");
$display("-------------------------------------------------------------------------------");
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b1,`DATA_BITS'h02,{`MEM_ADDR_BITS {1'b1}}); //write LOCK ID, not accepted cause more than 1 byte
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(1,1'b1,`DATA_BITS'h02,`MEM_ADDR_BITS'h400); //write lock ID, accepted cause only 1 byte sent
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
READ_ID_PAGE_OR_LOCK_STATUS(2,1'b1,`MEM_ADDR_BITS'h400); //read lock status twice
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b1,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write lock id when it is already lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
WRITE_ID_PAGE_OR_LOCK(2,1'b0,`DATA_BITS'ha5,{`MEM_ADDR_BITS {1'b1}}); //write ID memory when it is lock, not accepted
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
end
//---------------------------------------
$display("==============================================");
if (`IDPAGE)
$display("== TESTING6: HOLD CONDITION VERIFICATION. ==");
else
$display("== TESTING5: HOLD CONDITION VERIFICATION. ==");
$display("==============================================");
W = 1;
WRITE_ENABLE;
WRITE_STATUS_REGISTER(8'b0000_0000);
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
WRITE_ENABLE;
//////////////////////////Write Data Instruction
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time - data in setup time
//////////////////////////
//************************
HOLD = 1'b0; //HOLD driven low when CLK=1, Pause right now
D = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data in setup time
#(M95XXX_SIM.M95XXX_Macro_mux.tHLCH); //clock low hold time after "HOLD" active
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK-50);
HOLD = 1'b0;
#25;
HOLD = 1'b1; //HOLD driven high when C=1, Resume next CLK falling edge
#25;
//************************
HOLD = 1'b0; //HOLD driven high same as CLK falling edge, Pause
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
for(i=0;i<add_bytes*8-1;i=i+1)
begin
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
C = 1'b1;
//#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK-40);
HOLD = 1'b1; //HOLD driven high when C=1, no effect
#20;
HOLD = 1'b0; //HOLD driven low when C=1 no effect
#20
HOLD = 1'b1; //HOLD driven high when C=1, and sametime C is driven low, Resume
//------------------------
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHL);
HOLD = 1'b0; //HOLD driven low when C=0, hold start
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
for(i=0;i<4;i=i+1)
begin
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
HOLD = 1'b1; //HOLD driven high when C=0, hold end
//#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tHHCH);
//------------------------
C = 1'b1; //D0 of instruction code, latched in
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
HOLD = 1'b0; //HOLD driven low when C=1, next C falling edge start
for(i=0;i<4;i=i+1)
begin
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
HOLD = 1'b1; //HOLD driven high when C=1, next falling edge stop
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//------------------------
//*********************************************************************
// ---Write Memory Instruction code with a changing /HOLD signal ---
//*********************************************************************
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
//D = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
//C = 1'b1;
//#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
//C = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
//----------------------//indicate destination address
d_address = {`MEM_ADDR_BITS {1'b0}};
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = d_address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------//write data
n = 32; //the number of data bytes
data = 8'h29; //indicate data value
for(i=0;i<=n-1;i=i+1)
begin
for(j=0;j<=7;j=j+1)
begin
D = data[7-j];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
#(M95XXX_SIM.M95XXX_Macro_mux.tW);
//----------------------//Write Instruction Over
READ_DATA_BYTES_HD(16,1'b0,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
$display("-------------------------------------------------------------------------------");
$display("-- Note: READ MEMORY ID WITH HOLDS --");
$display("-------------------------------------------------------------------------------");
if (`IDPAGE) begin
READ_DATA_BYTES_HD(16,1'b1,{`MEM_ADDR_BITS {1'b0}});
#(M95XXX_SIM.M95XXX_Macro_mux.tSHQZ);
end
$display("======================================================");
if (`IDPAGE)
$display("== TESTING7: THE VIOLATED AC TIMING VERIFICATION. ==");
else
$display("== TESTING6: THE VIOLATED AC TIMING VERIFICATION. ==");
$display("======================================================");
//Following code executes unmeaning operation. It is only used for checking the AC Timing out of spec.
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL - 1); //violated the /S not active hold time //violated the clock high time
S = 1'b0;
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL - 1); //violated the /S active setup time //violated the clock low time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL);
D = ~D; //change the value on "D" input pin
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH - 1); //violated the Data In Setup Time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHDX - 1); //violated the Data In Hold Time
D = ~D; //change the value on "D" input pin
#(M95XXX_SIM.M95XXX_Macro_mux.tCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH - 1); //violated the /S Active Hold Time //violated the clock high time
S = 1'b1;
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL - 1); //violated the /S Active Setup Time //violated the clock low time //violated /S Deselest Time
C = 1'b1;
#1; //violated the /S not active hold time
S = 1'b0;
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCL);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHL); //Clock Low Set-Up Time before /HOLD Active = 0s
HOLD = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tHLCH - 1); //violated the CLock Low Hold Time after /HOLD Active //violated the clock low time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCH);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHH); //Clock Low Set-Up Time before /HOLD Not Active = 0s
HOLD = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tHHCH - 1); //violated the CLock Low Hold Time after /HOLD Not Active //violated the clock low time
C = 1'b1;
#100;
S = 1'b1;
#200;
if (!`VALID_PRT)
begin
$display("\n######################################################################");
$display(" ERROR: Part Choosen is NOT a valid Part ");
$display("######################################################################\n");
end
$display("\n######################################################################");
$display(" TESTS DONE ");
$display("######################################################################\n");
$stop; //testing completed
end
//===============================================
//Stimuli task definition
//===============================================
`define logicbit 1'b0
task WRITE_ENABLEi;
input initclk;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
for(i=0;i<=7;i=i+1)
begin
if((i==5)||(i==6)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time, and /S active setup time with #(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH)
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK); //Clock High Time
if (i==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_ENABLE;
WRITE_ENABLEi(`logicbit);
endtask
task WRITE_ENABLEh;
WRITE_ENABLEi(1'b1);
endtask
//===============================================
task WRITE_DISABLEi;
input initclk;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if(i==5) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_DISABLE;
WRITE_DISABLEi(`logicbit);
endtask
task WRITE_DISABLEh;
WRITE_DISABLEi(1'b1);
endtask
//===============================================
task READ_STATUS_REGISTERi;
input initclk;
begin
//----------------------instruction
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==5)||(i==7)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read status register
for(i=0;i<=7;i=i+1)
begin
C = 1'b1;
sr = {sr[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: STATUS_REGISTER = [%b]",$realtime,sr);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task READ_STATUS_REGISTER;
READ_STATUS_REGISTERi(`logicbit);
endtask
task READ_STATUS_REGISTERh;
READ_STATUS_REGISTERi(1'b1);
endtask
//===============================================
task POLLING_WITH_SEL_LOOP_ON_RDSR_DESEL;
begin
//----------------------instruction
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==5)||(i==7)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read status register
sr = 03;
while (sr != 0)
begin
for(i=0;i<=7;i=i+1)
begin
C = 1'b1;
sr = {sr[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: STATUS_REGISTER = [%b]",$realtime,sr);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
//===============================================
task POLLING_WITH_LOOP_ON_SEL_RDSR_DESEL;
begin
//----------------------instruction
if (C==1) C=1'b0;
sr = 03;
while (sr != 0)
begin
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==5)||(i==7)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read status register
for(i=0;i<=7;i=i+1)
begin
C = 1'b1;
sr = {sr[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: STATUS_REGISTER = [%b]",$realtime,sr);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
end
endtask
//===============================================
task WRITE_STATUS_REGISTERi;
input[7:0] sr_data;
input initclk;
begin
//----------------------instruction
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL);
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
for(i=0;i<=7;i=i+1)
begin
if(i==7) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------write status register
for(i=0;i<=7;i=i+1)
begin
D = sr_data[7-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_STATUS_REGISTER;
input[7:0] sr_data;
begin
WRITE_STATUS_REGISTERi(sr_data,`logicbit);
end
endtask
task WRITE_STATUS_REGISTERh;
input[7:0] sr_data;
begin
WRITE_STATUS_REGISTERi(sr_data,1'b1);
end
endtask
//===============================================
task READ_DATA_BYTESi;
input n;
input[23:0] address;
input initclk;
integer j,n;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==6)||(i==7)) D = 1'b1;
else if ((instructionA8==1)&&(i==4)) D = address[`MEM_ADDR_BITS-1];
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1) C = 1'b0; else C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (C==0) C = 1'b1; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1) C = 1'b0; else C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (C==0) C = 1'b1; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read data bytes
for(i=1;i<=n;i=i+1)
begin
// address = U_M95XXX.memory_address[`MEM_ADDR_BITS-1:0];
for(j=0;j<=7;j=j+1)
begin
if (C==1) C = 1'b0; else C = 1'b1;
// read_dat = {read_dat[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
read_dat = {read_dat[6:0],Q};
address = U_M95XXX.memory_address[`MEM_ADDR_BITS-1:0];
if (i==n&&j==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: READ RESULT: ADDRESS = [%h], DATA = [%h]\n",$realtime,address,read_dat);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task READ_DATA_BYTES;
input n;
input[23:0] address;
integer n;
begin
READ_DATA_BYTESi(n,address,`logicbit);
end
endtask
task READ_DATA_BYTESh;
input n;
input[23:0] address;
integer n;
begin
READ_DATA_BYTESi(n,address,1'b1);
end
endtask
//===============================================
task WRITE_DATA_INi;
input n; //the number of data byte that be written in
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
input initclk;
integer j,n;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if(i==6) D = 1'b1;
else if ((instructionA8==1)&&(i==4)) D = address[`MEM_ADDR_BITS-1];
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1)
C = 1'b0;
else
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (C==0)
C = 1'b1;
else
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1)
C = 1'b0;
else
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (C==0)
C = 1'b1;
else
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------write data
for(i=0;i<=n-1;i=i+1)
begin
for(j=0;j<=7;j=j+1)
begin
D = data[7-j];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
if (C==1) C = 1'b0; else C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==n-1&&j==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
end
//----------------------
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_DATA_IN;
input n; //the number of data byte that be written in
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
integer n;
begin
WRITE_DATA_INi(n,data,address,`logicbit);
end
endtask
task WRITE_DATA_INh;
input n; //the number of data byte that be written in
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
integer n;
begin
WRITE_DATA_INi(n,data,address,1'b1);
end
endtask
//===============================================
task WRITE_ID_PAGE_OR_LOCKi;
input n; //the number of data byte that be written in
input idn_lock;
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
input initclk;
integer j,n;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==0||i==6)) D = 1'b1;
// else if ((instructionA8==1)&&(i==4)) D = address[`MEM_ADDR_BITS-1];
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
if((address[10])&&(!idn_lock))
begin
$display("%t: ERROR: A10 set for lock on a Write ID Operation!",$realtime);
$display("%t: WARNING: Setting A10 to Zero for Write ID Operation!\n",$realtime);
address[10] = 1'b0;
end
else if((!address[10])&&(idn_lock))
begin
$display("%t: ERROR: A10 set for a Write ID on a Lock ID Operation!",$realtime);
$display("%t: WARNING: Setting A10 to one for Lock ID Operation!\n",$realtime);
address[10] = 1'b1;
end
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------write data
for(i=0;i<=n-1;i=i+1)
begin
for(j=0;j<=7;j=j+1)
begin
D = data[7-j];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==n-1&&j==7) C = initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
end
//----------------------
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task WRITE_ID_PAGE_OR_LOCK;
input n; //the number of data byte that be written in
input idn_lock;
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
integer n;
begin
WRITE_ID_PAGE_OR_LOCKi(n,idn_lock,data,address,`logicbit);
end
endtask
task WRITE_ID_PAGE_OR_LOCKh;
input n; //the number of data byte that be written in
input idn_lock;
input[7:0] data; //the data written in memory
input[23:0] address; //the accessed location's address
integer n;
begin
WRITE_ID_PAGE_OR_LOCKi(n,idn_lock,data,address,1'b1);
end
endtask
//===============================================
task READ_ID_PAGE_OR_LOCK_STATUSi;
input n;
input idn_status;
input[23:0] address;
input initclk;
integer j,n;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((i==0)||(i==6)||(i==7)) D = 1'b1;
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
if((address[10])&&(!idn_status))
begin
$display("%t: ERROR: A10 set for Read Lock Status on a Read ID Operation!",$realtime);
$display("%t: WARNING: Setting A10 to Zero for Read ID Operation!\n",$realtime);
address[10] = 1'b0;
end
else if((!address[10])&&(idn_status))
begin
$display("%t: ERROR: A10 set for Read ID Operation on a Read Lock Status Operation!",$realtime);
$display("%t: WARNING: Setting A10 to one for Read Lock Status Operation!\n",$realtime);
address[10] = 1'b1;
end
// address[`MEM_ADDR_BITS-1:`MEM_ADDR_BITS-`PAGE_ADDR_BITS] = {`PAGE_ADDR_BITS{1'b0}};
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read data bytes
for(i=1;i<=n;i=i+1)
begin
address = U_M95XXX.memory_address[`MEM_ADDR_BITS-`PAGE_ADDR_BITS-1:0];
for(j=0;j<=7;j=j+1)
begin
C = 1'b1;
read_dat = {read_dat[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
if (i==n&&j==7) C =initclk; else C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK);
end
$display("%t: READ RESULT: ADDRESS = [%h], DATA = [%h]\n",$realtime,address,read_dat);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
task READ_ID_PAGE_OR_LOCK_STATUS;
input n;
input idn_status;
input[23:0] address;
integer n;
begin
READ_ID_PAGE_OR_LOCK_STATUSi(n,idn_status,address,`logicbit);
end
endtask
task READ_ID_PAGE_OR_LOCK_STATUSh;
input n;
input idn_status;
input[23:0] address;
integer n;
begin
READ_ID_PAGE_OR_LOCK_STATUSi(n,idn_status,address,1'b1);
end
endtask
//===============================================
task READ_DATA_BYTES_HD;
input n;
input id;
input[23:0] address;
integer j,n,k;
reg id;
begin
if (C==1) C=1'b0;
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSL); ///S not active hold time
S = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tSLCH-M95XXX_SIM.M95XXX_Macro_mux.tDVCH); ///S active setup time
for(i=0;i<=7;i=i+1)
begin
if((id==1)&&(i==0)) D = 1'b1;
else if((i==6)||(i==7)) D = 1'b1;
else if ((instructionA8==1)&&(i==4)) D = address[`MEM_ADDR_BITS-1];
else D = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
//----------------------address
for(i=0;i<=add_bytes*8-1;i=i+1)
begin
D = address[add_bytes*8-1-i];
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH); //data setup time
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tDVCH);
//----------------------read data bytes
for(i=1;i<=n;i=i+1)
begin
address = U_M95XXX.memory_address[`MEM_ADDR_BITS-1:0];
for(j=0;j<=7;j=j+1)
begin
C = 1'b1;
read_dat = {read_dat[6:0],Q};
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-40);
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHL); //clk low setup time before "HOLD" active
//---------------------------------------------
HOLD = 1'b0; //HOLD Condition start
for(k=0;k<1;k=k+1)
begin
//#60;
#(M95XXX_SIM.M95XXX_Macro_mux.tHLCH); //clk low hold time after "HOLD" active
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tCLHL-M95XXX_SIM.M95XXX_Macro_mux.tHLCH);
C = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tH_CLK);
C = 1'b0;
//#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-40);
#(M95XXX_SIM.M95XXX_Macro_mux.tCLHL); //clk low setup time before "HOLD" active
end
HOLD = 1'b1; //HOLD Condition end
//#60;
#(M95XXX_SIM.M95XXX_Macro_mux.tHLCH); //clk low hold time after "HOLD" active
#(M95XXX_SIM.M95XXX_Macro_mux.tL_CLK-M95XXX_SIM.M95XXX_Macro_mux.tCLHL-M95XXX_SIM.M95XXX_Macro_mux.tHLCH);
//---------------------------------------------
end
$display("%t: READ RESULT: ADDRESS = [%h], DATA = [%h]\n",$realtime,address,read_dat);
end
#(M95XXX_SIM.M95XXX_Macro_mux.tCHSH); ///S active hold time
S = 1'b1;
#(M95XXX_SIM.M95XXX_Macro_mux.tSHSL); ///S Deselect time
end
endtask
//===============================================
endmodule
|
module altera_primitive_sync_fifo_24in_24out_16depth (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [23:0] data;
input rdreq;
input sclr;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [23:0] q;
output [3:0] usedw;
wire sub_wire0;
wire [3:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire [23:0] sub_wire4;
wire sub_wire5;
wire almost_full = sub_wire0;
wire [3:0] usedw = sub_wire1[3:0];
wire empty = sub_wire2;
wire almost_empty = sub_wire3;
wire [23:0] q = sub_wire4[23:0];
wire full = sub_wire5;
scfifo scfifo_component (
.rdreq (rdreq),
.sclr (sclr),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.almost_empty (sub_wire3),
.q (sub_wire4),
.full (sub_wire5));
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 2,
scfifo_component.almost_full_value = 14,
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 24,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
|
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module regfile(input wire clock,
input wire enable,
input wire [ 4:0] rdaddress_a,
input wire [ 4:0] rdaddress_b,
// Write port
input wire wren,
input wire [ 4:0] wraddress,
input wire [31:0] data,
// Read ports
output reg [31:0] qa, // One clock cycle delayed
output reg [31:0] qb // One clock cycle delayed
);
reg [31:0] regs [31:0];
always @(posedge clock)
if (enable) begin
if (wren)
regs[wraddress] <= data;
qa <= regs[rdaddress_a];
qb <= regs[rdaddress_b];
end
reg [7:0] i;
initial begin
i = 0;
repeat (32) begin
regs[i] = 0 /*{4{i}}*/;
i = i + 1;
end
end
endmodule
|
module sky130_fd_sc_ls__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module sky130_fd_sc_lp__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
|
module jbi_int_arb (/*AUTOARG*/
// Outputs
sct0rdq_dec_count, sct1rdq_dec_count, sct2rdq_dec_count, sct3rdq_dec_count,
piorqq_req_adv, pioackq_req_adv, dbg_req_adv, int_req, have_trans_waiting,
int_requestors, int_req_type, jbi_log_arb_myreq, jbi_log_arb_reqtype,
// Inputs
sct0rdq_data1_4, sct0rdq_trans_count, sct0rdq_ue_err, sct0rdq_unmapped_error,
sct1rdq_data1_4, sct1rdq_trans_count, sct1rdq_ue_err, sct1rdq_unmapped_error,
sct2rdq_data1_4, sct2rdq_trans_count, sct2rdq_ue_err, sct2rdq_unmapped_error,
sct3rdq_data1_4, sct3rdq_trans_count, sct3rdq_ue_err, sct3rdq_unmapped_error,
piorqq_req, piorqq_req_rw, piorqq_req_dest, pioackq_req, pioackq_ack_nack,
dbg_req_transparent, dbg_req_arbitrate, dbg_req_priority, int_granted,
parked_on_us, ok_send_address_pkt, ok_send_data_pkt_to_4,
ok_send_data_pkt_to_5, csr_jbi_debug_arb_aggr_arb, clk, rst_l
);
`include "jbi_mout.h"
// SCT0 RDQ.
input sct0rdq_data1_4; // If asserted, RD16 read return, else RD64 read return.
input [3:0] sct0rdq_trans_count; // Number of transactions in the queue.
output sct0rdq_dec_count; // When asserted, decrement the transactions count.
input sct0rdq_ue_err; // When asserted, data at top-of-queue has an Uncorrectable Error.
input sct0rdq_unmapped_error; // State for cache to install the data or unmapped error flag.
// SCT1 RDQ.
input sct1rdq_data1_4; // If asserted, RD16 read return, else RD64 read return.
input [3:0] sct1rdq_trans_count; // Number of transactions in the queue.
output sct1rdq_dec_count; // When asserted, decrement the transactions count.
input sct1rdq_ue_err; // When asserted, data at top-of-queue has an Uncorrectable Error.
input sct1rdq_unmapped_error; // State for cache to install the data or unmapped error flag.
// SCT2 RDQ.
input sct2rdq_data1_4; // If asserted, RD16 read return, else RD64 read return.
input [3:0] sct2rdq_trans_count; // Number of transactions in the queue.
output sct2rdq_dec_count; // When asserted, decrement the transactions count.
input sct2rdq_ue_err; // When asserted, data at top-of-queue has an Uncorrectable Error.
input sct2rdq_unmapped_error; // State for cache to install the data or unmapped error flag.
// SCT3 RDQ.
input sct3rdq_data1_4; // If asserted, RD16 read return, else RD64 read return.
input [3:0] sct3rdq_trans_count; // Number of transactions in the queue.
output sct3rdq_dec_count; // When asserted, decrement the transactions count.
input sct3rdq_ue_err; // When asserted, data at top-of-queue has an Uncorrectable Error.
input sct3rdq_unmapped_error; // State for cache to install the data or unmapped error flag.
// PIO RQQ.
input piorqq_req; // The PIORQQ has a valid request.
input piorqq_req_rw; // If asserted, next request is read request, else it is a write request.
input [1:0] piorqq_req_dest; // If request is a write, this signal tell to which device (0 AID0, 1 AID4, 2 AID5, 3 AID Other).
output piorqq_req_adv; // When asserted, pop the transaction header from the PIORQQ_REQ queue.
// PIO ACKQ.
input pioackq_req; // The PIOACKQ has a valid request.
input pioackq_ack_nack; // If asserted, top-of-queue has an INT ACK request, else it is an INT NACK request.
output pioackq_req_adv; // When asserted, pop the transaction header from the PIOACKQ queue.
// DEBUG ACKQ.
input dbg_req_transparent; // The Debug Info queue has valid request and wants it sent without impacting the JBus flow.
input dbg_req_arbitrate; // The Debug Info queue has valid request and wants fair round robin arbitration.
input dbg_req_priority; // The Debug Info queue has valid request and needs it sent right away.
output dbg_req_adv; // When asserted, pop the transaction header from the Debug Info queue.
// JBus Arbiter.
output int_req;
// Arb Timeout support.
output have_trans_waiting; // There is at least one transaction that needs to go to JBus (not AOK/DOK flow controlled).
// JBus Packet Controller.
output [6:0] int_requestors; // Current internal requestor (At most one bit of int_requestors[] is asserted at a time).
output [3:0] int_req_type;
input int_granted;
input parked_on_us;
// Flow Control.
input ok_send_address_pkt;
input ok_send_data_pkt_to_4;
input ok_send_data_pkt_to_5;
// CSRs and errors.
input csr_jbi_debug_arb_aggr_arb; // AGGR_ARB bit of JBI_DEBUG_ARB register.
output [2:0] jbi_log_arb_myreq; // "Arbitration Timeout Error" data log, MYREQ
output [2:0] jbi_log_arb_reqtype; // "Arbitration Timeout Error" data log, REQTYPE.
// Clock and reset.
input clk;
input rst_l;
// Wires and Regs.
wire [6:0] last_granted;
reg [3:0] int_req_type;
// Forming the requests.
wire [6:0] req_in;
assign req_in[LRQ_SCT0RDQ_BIT] = (sct0rdq_trans_count != 1'b0);
assign req_in[LRQ_SCT1RDQ_BIT] = (sct1rdq_trans_count != 1'b0);
assign req_in[LRQ_SCT2RDQ_BIT] = (sct2rdq_trans_count != 1'b0);
assign req_in[LRQ_SCT3RDQ_BIT] = (sct3rdq_trans_count != 1'b0);
assign req_in[LRQ_PIORQQ_BIT] = piorqq_req;
assign req_in[LRQ_PIOACKQ_BIT] = pioackq_req;
assign req_in[LRQ_DBGQ_BIT] = (dbg_req_transparent && parked_on_us &&
(!req_in[LRQ_SCT0RDQ_BIT] && !req_in[LRQ_SCT1RDQ_BIT] && !req_in[LRQ_SCT2RDQ_BIT] &&
!req_in[LRQ_SCT3RDQ_BIT] && !req_in[LRQ_PIORQQ_BIT] && !req_in[LRQ_PIOACKQ_BIT])) ||
dbg_req_arbitrate || dbg_req_priority;
// Conditioning requests with AOK/DOK.
wire [6:0] req_cond;
assign req_cond[LRQ_SCT0RDQ_BIT] = req_in[LRQ_SCT0RDQ_BIT];
assign req_cond[LRQ_SCT1RDQ_BIT] = req_in[LRQ_SCT1RDQ_BIT];
assign req_cond[LRQ_SCT2RDQ_BIT] = req_in[LRQ_SCT2RDQ_BIT];
assign req_cond[LRQ_SCT3RDQ_BIT] = req_in[LRQ_SCT3RDQ_BIT];
assign req_cond[LRQ_PIORQQ_BIT] = req_in[LRQ_PIORQQ_BIT] && (
(piorqq_req_rw && ok_send_address_pkt) || // NCRD requires AOK_ON.
(!piorqq_req_rw && ok_send_address_pkt && (piorqq_req_dest == `JBI_PRQQ_DEST_4) && ok_send_data_pkt_to_4) || // NCWR to AID 4 requires AOK_ON and DOK_ON(4).
(!piorqq_req_rw && ok_send_address_pkt && (piorqq_req_dest == `JBI_PRQQ_DEST_5) && ok_send_data_pkt_to_5) || // NCWR to AID 5 requires AOK_ON and DOK_ON(5).
(!piorqq_req_rw && ok_send_address_pkt && (piorqq_req_dest == `JBI_PRQQ_DEST_0)) || // NCWR to AID 0 requires AOK_ON.
(!piorqq_req_rw && ok_send_address_pkt && (piorqq_req_dest == `JBI_PRQQ_DEST_OTH)) // NCWR to AIDs 1,2,3,6, and 7 require AOK_ON.
);
assign req_cond[LRQ_PIOACKQ_BIT] = req_in[LRQ_PIOACKQ_BIT];
assign req_cond[LRQ_DBGQ_BIT] = req_in[LRQ_DBGQ_BIT];
// Create the internal request signal to the JBus Arbiter.
wire single_cycle_req = (int_req_type == T_RD16) ||
(int_req_type == T_NCRD) ||
(int_req_type == T_INTACK) ||
(int_req_type == T_INTNACK);
wire no_req_needed = single_cycle_req && parked_on_us;
assign int_req = ((| req_cond) && !no_req_needed) || csr_jbi_debug_arb_aggr_arb;
// Internal Arbiter.
//
// Two level arbiter. First level is round-robin, no hold. Second level
// is priority to dbg queue when 'dbg_req_priority' asserted.
//
// First level arbiter (round-robin, no hold).
// (Note: At most one bit of int_requestors[] is asserted at a time).
wire [6:0] int_requestors_l1;
assign int_requestors_l1[6] = req_cond[6] && (
(last_granted[0] ) ||
(last_granted[1] && !( { req_cond[ 0] })) ||
(last_granted[2] && !(| { req_cond[1:0] })) ||
(last_granted[3] && !(| { req_cond[2:0] })) ||
(last_granted[4] && !(| { req_cond[3:0] })) ||
(last_granted[5] && !(| { req_cond[4:0] })) ||
(last_granted[6] && !(| { req_cond[5:0] })));
assign int_requestors_l1[5] = req_cond[5] && (
(last_granted[6] ) ||
(last_granted[0] && !( { req_cond[6] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6] })) ||
(last_granted[2] && !(| { req_cond[1:0], req_cond[6] })) ||
(last_granted[3] && !(| { req_cond[2:0], req_cond[6] })) ||
(last_granted[4] && !(| { req_cond[3:0], req_cond[6] })) ||
(last_granted[5] && !(| { req_cond[4:0], req_cond[6] })));
assign int_requestors_l1[4] = req_cond[4] && (
(last_granted[5] ) ||
(last_granted[6] && !( { req_cond[ 5] })) ||
(last_granted[0] && !(| { req_cond[6:5] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6:5] })) ||
(last_granted[2] && !(| { req_cond[1:0], req_cond[6:5] })) ||
(last_granted[3] && !(| { req_cond[2:0], req_cond[6:5] })) ||
(last_granted[4] && !(| { req_cond[3:0], req_cond[6:5] })));
assign int_requestors_l1[3] = req_cond[3] && (
(last_granted[4] ) ||
(last_granted[5] && !( { req_cond[ 4] })) ||
(last_granted[6] && !(| { req_cond[5:4] })) ||
(last_granted[0] && !(| { req_cond[6:4] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6:4] })) ||
(last_granted[2] && !(| { req_cond[1:0], req_cond[6:4] })) ||
(last_granted[3] && !(| { req_cond[2:0], req_cond[6:4] })));
assign int_requestors_l1[2] = req_cond[2] && (
(last_granted[3] ) ||
(last_granted[4] && !( { req_cond[ 3] })) ||
(last_granted[5] && !(| { req_cond[4:3] })) ||
(last_granted[6] && !(| { req_cond[5:3] })) ||
(last_granted[0] && !(| { req_cond[6:3] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6:3] })) ||
(last_granted[2] && !(| { req_cond[1:0], req_cond[6:3] })));
assign int_requestors_l1[1] = req_cond[1] && (
(last_granted[2] ) ||
(last_granted[3] && !( { req_cond[ 2] })) ||
(last_granted[4] && !(| { req_cond[3:2] })) ||
(last_granted[5] && !(| { req_cond[4:2] })) ||
(last_granted[6] && !(| { req_cond[5:2] })) ||
(last_granted[0] && !(| { req_cond[6:2] })) ||
(last_granted[1] && !(| { req_cond[ 0], req_cond[6:2] })));
assign int_requestors_l1[0] = req_cond[0] && (
(last_granted[1] ) ||
(last_granted[2] && !( { req_cond[ 1] })) ||
(last_granted[3] && !(| { req_cond[2:1] })) ||
(last_granted[4] && !(| { req_cond[3:1] })) ||
(last_granted[5] && !(| { req_cond[4:1] })) ||
(last_granted[6] && !(| { req_cond[5:1] })) ||
(last_granted[0] && !(| { req_cond[6:1] })));
//
// Second level arbitration (priority to dbg queue when 'dbg_req_priority' asserted).
assign int_requestors = dbg_req_priority? (7'b000_0001 << LRQ_DBGQ_BIT): int_requestors_l1;
// Track the last granted request 'last_granted' to aid the round-robin algorithm.
wire [6:0] next_last_granted = int_requestors;
wire last_granted_en = int_granted;
dffrle_ns #(6) last_granted_reg (.din(next_last_granted[6:1]), .en(last_granted_en), .q(last_granted[6:1]), .rst_l(rst_l), .clk(clk));
dffsle_ns last_granted_reg0 (.din(next_last_granted[0]), .en(last_granted_en), .q(last_granted[0]), .set_l(rst_l), .clk(clk));
// Determine the transaction type of the 'int_requestors'.
// (Note: At most one bit of int_requestors[] is asserted at a time).
always @(/*AS*/int_requestors or pioackq_ack_nack or piorqq_req_dest
or piorqq_req_rw or sct0rdq_data1_4 or sct0rdq_ue_err
or sct0rdq_unmapped_error or sct1rdq_data1_4 or sct1rdq_ue_err
or sct1rdq_unmapped_error or sct2rdq_data1_4 or sct2rdq_ue_err
or sct2rdq_unmapped_error or sct3rdq_data1_4 or sct3rdq_ue_err
or sct3rdq_unmapped_error) begin
case (1'b1)
int_requestors[LRQ_SCT0RDQ_BIT]: int_req_type = (!sct0rdq_data1_4)? T_RD64: (sct0rdq_ue_err || sct0rdq_unmapped_error)? T_RDER: T_RD16; // SCT0 RDQ.
int_requestors[LRQ_SCT1RDQ_BIT]: int_req_type = (!sct1rdq_data1_4)? T_RD64: (sct1rdq_ue_err || sct1rdq_unmapped_error)? T_RDER: T_RD16; // SCT1 RDQ.
int_requestors[LRQ_SCT2RDQ_BIT]: int_req_type = (!sct2rdq_data1_4)? T_RD64: (sct2rdq_ue_err || sct2rdq_unmapped_error)? T_RDER: T_RD16; // SCT2 RDQ.
int_requestors[LRQ_SCT3RDQ_BIT]: int_req_type = (!sct3rdq_data1_4)? T_RD64: (sct3rdq_ue_err || sct3rdq_unmapped_error)? T_RDER: T_RD16; // SCT3 RDQ.
int_requestors[LRQ_PIORQQ_BIT]: int_req_type = (piorqq_req_rw)? T_NCRD: (piorqq_req_dest == `JBI_PRQQ_DEST_0)? T_NCWR0: // PIO RQQ.
(piorqq_req_dest == `JBI_PRQQ_DEST_4)? T_NCWR4:
(piorqq_req_dest == `JBI_PRQQ_DEST_5)? T_NCWR5:
T_NCWR_OTHER;
int_requestors[LRQ_PIOACKQ_BIT]: int_req_type = (pioackq_ack_nack)? T_INTACK: T_INTNACK; // PIO ACKQ.
int_requestors[LRQ_DBGQ_BIT]: int_req_type = T_RD16; // DEBUG INFO.
default: int_req_type = T_NONE;
endcase
end
// Decrement transaction counters.
assign sct0rdq_dec_count = int_requestors[LRQ_SCT0RDQ_BIT] && int_granted;
assign sct1rdq_dec_count = int_requestors[LRQ_SCT1RDQ_BIT] && int_granted;
assign sct2rdq_dec_count = int_requestors[LRQ_SCT2RDQ_BIT] && int_granted;
assign sct3rdq_dec_count = int_requestors[LRQ_SCT3RDQ_BIT] && int_granted;
assign piorqq_req_adv = int_requestors[LRQ_PIORQQ_BIT] && int_granted;
assign pioackq_req_adv = int_requestors[LRQ_PIOACKQ_BIT] && int_granted;
assign dbg_req_adv = int_requestors[LRQ_DBGQ_BIT] && int_granted;
// "Arbitration Timeout Error" data to log.
//
// Encode the 'int_requestors' into 'jbi_log_arb_myreq'.
reg [2:0] jbi_log_arb_myreq_m1;
always @(/*AS*/int_requestors) begin
case (1'b1)
int_requestors[LRQ_PIORQQ_BIT]: jbi_log_arb_myreq_m1 = 3'b001; // PioReqQ
int_requestors[LRQ_PIOACKQ_BIT]: jbi_log_arb_myreq_m1 = 3'b010; // PioAckQ
int_requestors[LRQ_SCT0RDQ_BIT]: jbi_log_arb_myreq_m1 = 3'b011; // SCT0RdQ
int_requestors[LRQ_SCT1RDQ_BIT]: jbi_log_arb_myreq_m1 = 3'b100; // SCT1RdQ
int_requestors[LRQ_SCT2RDQ_BIT]: jbi_log_arb_myreq_m1 = 3'b101; // SCT2RdQ
int_requestors[LRQ_SCT3RDQ_BIT]: jbi_log_arb_myreq_m1 = 3'b110; // SCT3RdQ
int_requestors[LRQ_DBGQ_BIT]: jbi_log_arb_myreq_m1 = 3'b111; // DbgQ
default: jbi_log_arb_myreq_m1 = 3'b000; // None or PioReqQ held by AOK/DOK flow control.
endcase
end
wire [2:0] next_jbi_log_arb_myreq = jbi_log_arb_myreq_m1;
dff_ns #(3) jbi_log_arb_myreq_reg (.din(next_jbi_log_arb_myreq), .q(jbi_log_arb_myreq), .clk(clk));
//
// Encode the 'int_requestors' into 'jbi_log_arb_reqtype'.
reg [2:0] jbi_log_arb_reqtype_m1;
always @(/*AS*/int_requestors or piorqq_req_dest or piorqq_req_rw) begin
case (1'b1)
int_requestors[LRQ_PIORQQ_BIT]: jbi_log_arb_reqtype_m1 = (piorqq_req_rw)? 3'b001: // NCRD
(piorqq_req_dest == `JBI_PRQQ_DEST_0)? 3'b100: // NCWR to aid0
(piorqq_req_dest == `JBI_PRQQ_DEST_4)? 3'b101: // NCWR to aid4
(piorqq_req_dest == `JBI_PRQQ_DEST_5)? 3'b110: // NCWR to aid5
3'b111; // NCWR to aid-other
default: jbi_log_arb_reqtype_m1 = 3'b000; // Empty
endcase
end
wire [2:0] next_jbi_log_arb_reqtype = jbi_log_arb_reqtype_m1;
dff_ns #(3) jbi_log_arb_reqtype_reg (.din(next_jbi_log_arb_reqtype), .q(jbi_log_arb_reqtype), .clk(clk));
// "Arbitration Timeout Error" counter support.
assign have_trans_waiting = req_in[LRQ_SCT0RDQ_BIT] || req_in[LRQ_SCT1RDQ_BIT] || req_in[LRQ_SCT2RDQ_BIT] || req_in[LRQ_SCT3RDQ_BIT] ||
req_in[LRQ_PIORQQ_BIT] || req_in[LRQ_PIOACKQ_BIT] || (req_in[LRQ_DBGQ_BIT] && !dbg_req_transparent);
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Check: Exactly 1 bit is set in 'last_granted[]'.
always @(posedge clk) begin
if (rst_l && !(last_granted == 7'b000_0001 || last_granted == 7'b000_0010 || last_granted == 7'b000_0100 ||
last_granted == 7'b000_1000 || last_granted == 7'b001_0000 || last_granted == 7'b010_0000 ||
last_granted == 7'b100_0000)) begin
$dispmon ("jbi_mout_jbi_int_arb", 49, "%d %m: ERROR - Exactly one bit must be set in 'last_granted[]' (%b).", $time, last_granted);
end
end
// Check: At most one bit can be set in 'int_requestors[]'.
always @(posedge clk) begin
if (rst_l && !(int_requestors == 7'b000_0000 ||
int_requestors == 7'b000_0001 || int_requestors == 7'b000_0010 || int_requestors == 7'b000_0100 ||
int_requestors == 7'b000_1000 || int_requestors == 7'b001_0000 || int_requestors == 7'b010_0000 ||
int_requestors == 7'b100_0000)) begin
$dispmon ("jbi_mout_jbi_int_arb", 49, "%d %m: ERROR - At most one bit can be set in 'int_requestors[]' (%b).", $time, int_requestors);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
|
module rominout2 (
address_a,
address_b,
clock,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input clock;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
|
module top();
// Inputs are registered
reg SLEEP;
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_isobufsrc dut (.SLEEP(SLEEP), .A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module sky130_fd_sc_lp__busreceiver (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
|
module testbench();
// inputs
reg clk, rst;
reg [9:0] deposit, price;
reg [4:0] select;
reg deposited, selected, cancel, maintenance;
// outputs
wire refund, refundall, depositall;
wire [4:0] product;
wire [9:0] change;
wire [2:0] state;
// instantiation
vm myVM(
.clk(clk),
.rst(rst),
.deposit(deposit),
.deposited(deposited),
.select(select),
.selected(selected),
.price(price),
.cancel(cancel),
.maintenance(maintenance),
.refund(refund),
.refundall(refundall),
.depositall(depositall),
.product(product),
.change(change),
.state(state)
);
// for future use
// initial begin
// $display("time: rst, clk");
// $monitor(" %0d: %b, %b", $time, rst, clk);
// end
initial begin
clk= 0;
#5;
forever #5 clk = ~clk;
end
initial begin
rst= 0;
deposited= 0; deposit= 0; selected= 0; select= 'bx; price= 0;
cancel= 0; maintenance= 0;
#10;
#10 rst= 1;
// simulate overflow, insert payment more than threshold value
#20 deposited= 1; deposit= 100;
#20 deposited= 1; deposit= 200;
#20 deposited= 1; deposit= 200;
#20 deposited= 1; deposit= 1;
#20 deposited= 0;
#20;
// simulate cancel
#20 cancel= 1;
#20 cancel= 0;
#20;
// simulate purchase
#20 deposited= 1; deposit= 10;
#20 deposited= 1; deposit= 100;
#20 deposited= 1; deposit= 20;
#10 deposited= 0;
#20 selected= 1; select= 10;
#20 selected= 0; select= 'bx;
#20;
// simulate maintenance changing price
#20 maintenance= 1;
#20 selected= 1; select = 0; price= 10;
#20 selected= 1; select = 31; price= 10;
#20 selected= 1; select = 1; price= 15;
#20 selected= 1; select = 2; price= 10;
#20 selected= 1; select = 3; price= 20;
#20 selected= 1; select = 4; price= 10;
#20 selected= 1; select = 5; price= 15;
#20 selected= 1; select = 6; price= 15;
#20 selected= 1; select = 7; price= 15;
#20 selected= 1; select = 8; price= 10;
#20 selected= 1; select = 9; price= 10;
#20 selected= 1; select = 10; price= 10;
#20 selected= 1; select = 11; price= 10;
#20 selected= 1; select = 12; price= 10;
#20 selected= 1; select = 13; price= 10;
#20 selected= 1; select = 14; price= 10;
#20 selected= 1; select = 15; price= 10;
#20 selected= 1; select = 16; price= 10;
#20 selected= 1; select = 17; price= 10;
#20 selected= 1; select = 18; price= 10;
#20 selected= 1; select = 19; price= 10;
#20 selected= 1; select = 20; price= 10;
#20 selected= 1; select = 21; price= 10;
#20 selected= 1; select = 22; price= 10;
#20 selected= 1; select = 23; price= 10;
#20 selected= 1; select = 24; price= 10;
#20 selected= 1; select = 25; price= 10;
#20 selected= 1; select = 26; price= 10;
#20 selected= 1; select = 27; price= 10;
#20 selected= 1; select = 28; price= 20;
#20 selected= 1; select = 29; price= 20;
#20 selected= 1; select = 30; price= 20;
#20 selected= 1; select = 31; price= 99;
#20 selected= 0; select= 'bx; maintenance = 0;
#20;
// simulate purchase after changing price, item 30, from RM10 to RM2 (balance RM28)
#20 deposited= 1; deposit= 200;
#20 deposited= 1; deposit= 500;
#20 deposited= 1; deposit= 100;
#20 deposited= 0;
#20 selected= 1; select= 30;
#20 selected= 0; select= 'bx;
#20 selected= 1; select= 3;
#20 selected= 0; select= 'bx;
#200 $stop;
end
endmodule
|
module tb_blake2();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 2;
// API for the dut.
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_write_read;
reg [7 : 0] tb_address;
reg [31 : 0] tb_data_in;
wire [31 : 0] tb_data_out;
wire tb_error;
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg error_found;
reg [31 : 0] read_data;
reg [511 : 0] extracted_data;
reg display_cycle_ctr;
reg display_read_write;
//----------------------------------------------------------------
// Blake2 device under test.
//----------------------------------------------------------------
blake2 dut(
// Clock and reset.
.clk(tb_clk),
.reset_n(tb_reset_n),
// Control.
.cs(tb_cs),
.we(tb_write_read),
// Data ports.
.address(tb_address),
.write_data(tb_data_in),
.read_data(tb_data_out),
.error(tb_error)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end // dut_monitor
//----------------------------------------------------------------
// reset_dut
//----------------------------------------------------------------
task reset_dut();
begin
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// dump_dut_state
//
// Dump the internal state of the dut to std out.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("");
$display("DUT internal state");
$display("------------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result();
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// init_dut()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_dut();
begin
// Set clock, reset and DUT input signals to
// defined values at simulation start.
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 0;
tb_cs = 0;
tb_write_read = 0;
tb_address = 8'h00;
tb_data_in = 32'h00000000;
end
endtask // init_dut
//----------------------------------------------------------------
// blake2_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : blake2_test
$display(" -- Testbench for blake2 started --");
init_dut();
reset_dut();
$display("State at init after reset:");
dump_dut_state();
display_test_result();
$display("*** blake2 simulation done.");
$finish;
end // blake2_test
endmodule
|
module sky130_fd_sc_hd__lpflow_inputiso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
|
module sky130_fd_sc_ls__a21oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__a21oi_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
|
module sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
|
module sky130_fd_sc_hs__sdfsbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_s_pg `UNIT_DELAY u_df_p_s_pg0 (buf_Q , mux_out, CLK, SET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
|
module Uart_tx(
input clk,
input rst_n,
input [3:0] num, //一帧数据有几位由num来决定
input sel_data, //波特率技计数中心点（采集数据的使能信号）
input [7:0] rx_data,
output reg rs232_tx
);
always @(posedge clk or negedge rst_n)
if(!rst_n)
rs232_tx <= 1'b1;
else
if(sel_data) //检测波特率采样中心点（使能信号）
case(num) //检测要发送的一帧数据有几位？
0: rs232_tx <= 1'b0; //开始位为低电平
1: rs232_tx <= rx_data[0];
2: rs232_tx <= rx_data[1];
3: rs232_tx <= rx_data[2];
4: rs232_tx <= rx_data[3];
5: rs232_tx <= rx_data[4];
6: rs232_tx <= rx_data[5];
7: rs232_tx <= rx_data[6];
8: rs232_tx <= rx_data[7];
9: rs232_tx <= 1'b1; //结束位为高电平
default: rs232_tx <= 1'b1; //在其他情况下一直处于拉高电平状态
endcase
endmodule
|
module tb;
// ============================================================================
reg CLK;
initial CLK <= 1'b0;
always #0.5 CLK <= !CLK;
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK) rst_sr <= rst_sr >> 1;
wire RST;
assign RST = rst_sr[0];
// ============================================================================
initial begin
$dumpfile("waveforms.vcd");
$dumpvars;
end
integer cycle_cnt;
initial cycle_cnt <= 0;
always @(posedge CLK)
if (!RST) cycle_cnt <= cycle_cnt + 1;
always @(posedge CLK)
if (!RST && cycle_cnt >= 10000)
$finish;
// ============================================================================
reg clk_r;
always @(posedge CLK)
if (RST) clk_r <= 1'b0;
else clk_r <= !clk_r;
wire CLK1 = CLK;
wire CLK2 = clk_r;
// ============================================================================
wire s_dat;
oserdes_test #
(
.DATA_WIDTH (8),
.DATA_RATE ("SDR"),
.ERROR_HOLD (4)
)
trx_path
(
.CLK (CLK),
.CLK1 (CLK1),
.CLK2 (CLK2),
.RST (RST),
.IO_DAT (s_dat)
);
endmodule
|
module sky130_fd_sc_ls__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module BusArbiter
#(
parameter bus_width=32,
parameter bus_max_devices=16 // -1, since device #0 can't be used
)
(
input clk,
inout [bus_width-1:0] data_lines,
inout [bus_max_devices-1:0] receiver_device, // one-hot
inout [bus_max_devices-1:0] buffer_full, // hold your horses (raised by receiving device)
input [bus_max_devices-1:0] write_request, // priority queue: LSBs first, 0 is invalid
output reg [bus_max_devices-1:0] voice // one-hot signalling
);
// device can hold the bus as long as it has to, and we need this
// register to know when we can assign voice to another device
reg [bus_max_devices-1:0] operating_device=0;
generate
genvar device;
for (device=1; device<bus_max_devices; device=device+1) begin: voice_gen
always @(negedge clk)
// update voice when device has ended its transaction
if (!operating_device || operating_device&&(~write_request[operating_device])) begin
voice[device]=write_request[device] && !write_request[device-1:0];
operating_device=voice; // TODO Will it synthesize?
end
end
endgenerate
always @(clk) begin
if (clk)
$display("BusArbiter: + posedge clk on bus");
else
$display("BusArbiter: - negedge clk on bus");
$display("BusArbiter: bus_data_lines: %b",data_lines);
$display("BusArbiter: bus_receiver_device: %b",receiver_device);
$display("BusArbiter: bus_buffer_full: %b",buffer_full);
$display("BusArbiter: bus_write_request: %b",write_request);
$display("BusArbiter: bus_voice: %b",voice);
$display("BusArbiter: operating_device: %b",operating_device);
end
endmodule
|
module BusWriter
#(
parameter bus_width=32, // compatible with default bus width
parameter device_id=1 // bit position in bus_voice or bus_receiver, ie. device_id 6 -> sixth bit
)
(
// bus side
input clk,
output [bus_width-1:0] bus_data,
output [bus_max_devices-1:0] bus_receiver,
input [bus_max_devices-1:0] bus_buffer_full,
output [bus_max_devices-1:0] bus_write_request,
input [bus_max_devices-1:0] bus_voice,
// device side
input [bus_width-1:0] client_data,
input [bus_max_devices-1:0] client_target_addr,
input client_enqueue, // save client_data and client_target_addr in FIFOs
output client_buffer_empty, // true, if FIFO empty (all data sent)
output client_buffer_full // true, if FIFO full
);
wire voice=bus_voice[device_id];
wire receiver_buffer_full=bus_buffer_full[bus_receiver];
// negedge copies of FIFO data
wire [bus_width-1:0] buffer_out_net;
reg [bus_width-1:0] buffer_out_reg;
wire [bus_max_devices-1:0] receiver_addr_net;
reg [bus_max_devices-1:0] receiver_addr_reg;
wire client_buffer_full_net;
reg client_buffer_full_reg;
wire client_buffer_empty_net;
reg client_buffer_empty_reg=1;
always @(negedge clk) begin
buffer_out_reg<=buffer_out_net;
receiver_addr_reg<=receiver_addr_net;
client_buffer_full_reg<=client_buffer_full_net;
client_buffer_empty_reg<=client_buffer_empty_net;
end
assign bus_receiver=voice ? receiver_addr_reg : 'bz;
assign bus_data=voice ? buffer_out_reg : 'bz;
assign client_buffer_empty=client_buffer_empty_reg;
assign client_buffer_full=client_buffer_full_reg;
wire wreq=~client_buffer_empty && ~receiver_buffer_full;
generate
genvar id;
for (id=0; id<bus_max_devices; id=id+1) begin: wreq_highz
assign bus_write_request[id]=id==device_id ? wreq : 'bz;
end
endgenerate
wire buffer_next=voice && ~receiver_buffer_full && ~client_buffer_empty;
wire clear=0;
FIFO
#(
.data_width(bus_width),
.size(bus_buffer_size),
.device_id(device_id)
) buffer
(
.data_in(client_data),
.data_out(buffer_out_net),
.clk(clk),
.next(buffer_next),
.insert(client_enqueue),
.clear(clear),
.full(client_buffer_full_net),
.empty(client_buffer_empty_net)
);
wire recv_addresses_buffer_full;
wire recv_addresses_buffer_empty;
FIFO
#(
.data_width(bus_max_devices),
.size(bus_buffer_size),
.device_id(device_id<<1)
) recv_addresses
(
.data_in(client_target_addr),
.data_out(receiver_addr_net),
.clk(clk),
.next(buffer_next),
.insert(client_enqueue),
.clear(clear),
.full(recv_addresses_buffer_full),
.empty(recv_addresses_buffer_empty)
);
always @(clk) begin
if (clk) begin
$display("BusWriter %d: buffer.next=%b",device_id,buffer_next);
$display("BusWriter %d: buffer.insert=%b",device_id,client_enqueue);
$display("BusWriter %d: buffer.full=%b",device_id,client_buffer_full);
$display("BusWriter %d: buffer.client_buffer_empty=%b",device_id,client_buffer_empty);
$display("BusWriter %d: buffer.data_in=%b",device_id,client_data);
$display("BusWriter %d: recv_addresses.data_in=%b",device_id,client_target_addr);
end
else begin
for (int i=0; i<4; i=i+1) begin
$display("BusWriter %d: mem[%d]=%b",device_id,i,buffer.mem[i]);
end
if (receiver_addr_reg==0 && voice)
$display("BusWriter %d: --MAJOR SCREWUP-- Sending to address 0",device_id);
end
end
endmodule
|
module BusReader
#(
parameter bus_width=32, // compatible with default bus width
parameter bus_max_devices=16,
parameter bus_buffer_size=32,
parameter device_id=1 // bit position in bus_voice or bus_receiver, ie. device_id 6 -> sixth bit
)
(
// bus side
input clk,
input [bus_width-1:0] bus_data,
input [bus_max_devices-1:0] bus_receiver,
output [bus_max_devices-1:0] bus_buffer_full,
input [bus_max_devices-1:0] bus_voice,
// device side
output [bus_width-1:0] client_data,
output [bus_max_devices-1:0] client_source_addr,
input client_next, // save client_data and client_source_addr in FIFOs
output client_buffer_empty, // true, if FIFO empty (all data read)
output client_buffer_full // true, if FIFO full
);
wire data_on_bus=bus_receiver[device_id] && bus_voice;
assign bus_buffer_full[device_id]=client_buffer_full;
wire clear=0;
FIFO
#(
.data_width(bus_width),
.size(bus_buffer_size),
.device_id(device_id)
) buffer
(
.data_in(bus_data),
.data_out(client_data),
.clk(clk),
.next(client_next),
.insert(data_on_bus),
.clear(clear),
.full(client_buffer_full),
.empty(client_buffer_empty)
);
wire sender_addresses_buffer_full;
wire sender_addresses_buffer_empty;
FIFO
#(
.data_width(bus_max_devices),
.size(bus_buffer_size),
.device_id(device_id<<1)
) sender_addresses
(
.data_in(bus_voice),
.data_out(client_source_addr),
.clk(clk),
.next(client_next),
.insert(data_on_bus),
.clear(clear),
.full(sender_addresses_buffer_full),
.empty(sender_addresses_buffer_empty)
);
always @(posedge clk) begin
if (data_on_bus && client_source_addr==0)
$display("BusReader %d: --MAJOR SCREWUP-- Received data from address 0",device_id);
end
endmodule
|
module BusClient
#(
parameter bus_width=32, // compatible with default bus width
parameter bus_max_devices=16,
parameter bus_buffer_size=32,
parameter device_id=1 // bit position in bus_voice or bus_receiver, ie. device_id 6 -> sixth bit
)
(
// bus side
input clk,
inout [bus_width-1:0] bus_data,
inout [bus_max_devices-1:0] bus_receiver,
inout [bus_max_devices-1:0] bus_write_request,
inout [bus_max_devices-1:0] bus_buffer_full,
input [bus_max_devices-1:0] bus_voice,
// device side
output [bus_width-1:0] client_data_in,
output [bus_max_devices-1:0] client_source_addr,
input [bus_width-1:0] client_data_out,
input [bus_max_devices-1:0] client_destination_addr,
input client_read_next,
input client_send_next,
output client_input_buffer_empty,
output client_input_buffer_full,
output client_output_buffer_empty,
output client_output_buffer_full
);
BusReader
#(
.bus_width(bus_width),
.bus_max_devices(bus_max_devices),
.bus_buffer_size(bus_buffer_size),
.device_id(device_id)
) reader
(
clk,
bus_data,
bus_receiver,
bus_buffer_full,
bus_voice,
client_data_in,
client_source_addr,
client_read_next,
client_input_buffer_empty,
client_input_buffer_full
);
BusWriter
#(
.bus_width(bus_width),
.bus_max_devices(bus_max_devices),
.bus_buffer_size(bus_buffer_size),
.device_id(device_id)
) writer
(
clk,
bus_data,
bus_receiver,
bus_buffer_full,
bus_write_request,
bus_voice,
client_data_out,
client_destination_addr,
client_send_next,
client_output_buffer_empty,
client_output_buffer_full
);
always @(negedge clk) begin
$display("BusClient %d: words in in_buffer: %d",device_id,reader.buffer.words_inside);
$display("BusClient %d: words in out_buffer: %d",device_id,writer.buffer.words_inside);
end
endmodule
|
module BusTester
#(
// bus-related
parameter bus_width=32,
parameter bus_max_devices=16,
parameter bus_buffer_size=32,
parameter device_id=1,
parameter send_to=2
)
(
// bus side
input clk,
inout [bus_width-1:0] bus_data,
inout [bus_max_devices-1:0] bus_receiver,
inout [bus_max_devices-1:0] bus_write_request,
inout [bus_max_devices-1:0] bus_buffer_full,
input [bus_max_devices-1:0] bus_voice
);
wire [bus_width-1:0] bus_in;
wire [bus_max_devices-1:0] bus_source;
wire [bus_width-1:0] bus_out;
reg [bus_max_devices-1:0] bus_target;
wire bus_next; // read next from FIFO
wire bus_send;
wire bus_input_empty;
wire bus_input_full;
wire bus_output_empty;
wire bus_output_full;
BusClient
#(
.bus_width(bus_width),
.bus_max_devices(bus_max_devices),
.bus_buffer_size(bus_buffer_size),
.device_id(device_id)
) bus_client
(
clk,
bus_data,
bus_receiver,
bus_write_request,
bus_buffer_full,
bus_voice,
bus_in,
bus_source,
bus_out,
bus_target,
bus_next,
bus_send,
bus_input_empty,
bus_input_full,
bus_output_empty,
bus_output_full
);
reg [31:0] counter;
assign bus_out=counter;
assign bus_target=1<<send_to;
always @(negedge clk) begin
if (device_id==2) begin
bus_send<=1;
bus_next<=0;
counter<=counter+1;
$display("BusTester %d: sending %d to %d",device_id,bus_out,bus_target);
end
else if (device_id==8) begin
bus_send<=0;
if (~bus_input_empty) begin
bus_next<=1;
$display("BusTester %d: received %d from %d",device_id,bus_in,bus_source);
end
else begin
bus_next<=0;
$display("BusTester %d: input buffer empty",device_id);
end
end
else
$display("BusTester: id==%d",device_id);
end
endmodule
|
module BusTestRig
#(
parameter bus_width=32,
parameter bus_max_devices=16 // -1, since device #0 can't be used
)
(
input clk
);
// bus
tri [bus_width-1:0] bus_data_lines;
tri [bus_max_devices-1:0] bus_receiver_device;
tri [bus_max_devices-1:0] bus_buffer_full;
wire [bus_max_devices-1:0] bus_write_request;
wire [bus_max_devices-1:0] bus_voice;
BusArbiter bus_arbiter
(
clk,
bus_data_lines,
bus_receiver_device,
bus_buffer_full,
bus_write_request,
bus_voice
);
BusTester
#(
.bus_width(32),
.bus_max_devices(16),
.device_id(2),
.send_to(8)
) test_module_1
(
clk,
bus_data_lines,
bus_receiver_device,
bus_write_request,
bus_buffer_full,
bus_voice
);
BusTester
#(
.bus_width(32),
.bus_max_devices(16),
.device_id(8),
.send_to(2)
) test_module_2
(
clk,
bus_data_lines,
bus_receiver_device,
bus_write_request,
bus_buffer_full,
bus_voice
);
endmodule
|
module convolve_kernel_fcud
#(parameter
ID = 1,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_3_max_dsp_32 convolve_kernel_ap_fmul_3_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
module vhdl_boolean_test;
vhdl_boolean dut();
initial begin
if(dut.true_val != \true ) begin
$display("FAILED true 1");
$finish();
end
if(!dut.true_val) begin
$display("FAILED true 2");
$finish();
end
if(dut.false_val != \false ) begin
$display("FAILED false 1");
$finish();
end
if(dut.false_val) begin
$display("FAILED false 2");
$finish();
end
if(!dut.and1) begin
$display("FAILED and1");
$finish();
end
if(dut.and2) begin
$display("FAILED and2");
$finish();
end
if(dut.and3) begin
$display("FAILED and3");
$finish();
end
if(!dut.or1) begin
$display("FAILED or1");
$finish();
end
if(dut.or2) begin
$display("FAILED or2");
$finish();
end
if(dut.or3) begin
$display("FAILED or3");
$finish();
end
if(!dut.not1) begin
$display("FAILED not1");
$finish();
end
if(dut.not2) begin
$display("FAILED not2");
$finish();
end
$display("PASSED");
end
endmodule
|
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
|
module LAG_pl_status (output_port,
allocated_pl,
allocated_pl_valid,
pl_status,
pl_blocked);
parameter np = 5;
parameter integer links[np][2] = '{'{2,2}, '{2,2}, '{2,2}, '{2,2}, '{2,2} };
parameter ln_num = 2; //ln_num = maximum number of links per trunk
input output_port_t output_port [np-1:0][ln_num-1:0];
input [np-1:0][ln_num-1:0][ln_num-1:0] allocated_pl; // allocated PL ID
input [np-1:0][ln_num-1:0] allocated_pl_valid; // holding allocated PL?
input [np-1:0][ln_num-1:0] pl_status; // blocked/ready status for each output PL
output [np-1:0][ln_num-1:0] pl_blocked;
logic [np-1:0][ln_num-1:0] b, current_pl_blocked;
genvar ip,pl,op;
generate
for (ip=0; ip<np; ip++) begin:il
for (pl=0; pl<links[ip][IN]; pl++) begin:vl
//assign current_pl[ip][pl] = (allocated_pl_valid[ip][pl]) ? allocated_pl[ip][pl] : pl_requested[ip][pl];
unary_select_pair #(.input_port(ip), .WA(np), .WB(ln_num), .links(links)) blocked_mux
(output_port[ip][pl],
allocated_pl[ip][pl],
pl_status,
current_pl_blocked[ip][pl]);
assign b[ip][pl] = current_pl_blocked[ip][pl];
assign pl_blocked[ip][pl] = (LAG_route_valid_input_pl (ip,pl)) ? b[ip][pl] : 1'b0;
end
end
endgenerate
endmodule
|
module i2cSlaveTop (
clk,
rst,
sda,
scl,
myReg0
);
input clk;
input rst;
inout sda;
input scl;
output [7:0] myReg0;
i2cSlave u_i2cSlave(
.clk(clk),
.rst(rst),
.sda(sda),
.scl(scl),
.myReg0(myReg0),
.myReg1(),
.myReg2(),
.myReg3(),
.myReg4(8'h12),
.myReg5(8'h34),
.myReg6(8'h56),
.myReg7(8'h78)
);
endmodule
|
module tb;
reg clk;
reg rst_n;
// sync counter
integer sync_cnt;
bit pre_sync;
// DUT connections
wire [ 6:0] rd_addr;
tri0 [31:0] rd_data;
wire [ 6:0] wr_addr;
wire [31:0] wr_data;
wire wr_stb;
reg sync_stb;
reg [31:0] ch_enas;
wire [ 7:0] out_data;
wire out_stb_addr;
wire out_stb_mix;
// channels memory
reg [31:0] channels_mem [0:127];
// test data
channel_data chans[0:31];
// generation fifos
reg [7:0] mix_fifo[$];
reg [7:0] addr_fifo[$];
// init tb data structures
initial
begin : chans_create
int i;
for(i=0;i<32;i++) chans[i] = new;
mix_fifo.delete();
addr_fifo.delete();
end
// clock and reset gen
initial
begin
rst_n = 1'b0;
clk = 1'b1;
forever #(`HALF_CLK) clk = ~clk;
end
//
initial
begin
#(1);
repeat (3) @(posedge clk);
rst_n <= 1'b1;
end
// sync generator
initial
begin
sync_cnt = 0;
pre_sync = 1'b0;
sync_stb = 1'b0;
end
//
always @(posedge clk)
if( !rst_n )
begin
sync_cnt <= 637;
pre_sync <= 1'b0;
sync_stb <= 1'b0;
end
else
begin
if( sync_cnt<(640-1) )
sync_cnt <= sync_cnt + 1;
else
sync_cnt <= 0;
pre_sync <= !sync_cnt;
sync_stb <= pre_sync;
end
// channels memory emulator
reg [31:0] rd_data_reg;
assign rd_data = rd_data_reg;
//
always @(posedge clk)
rd_data_reg <= channels_mem[rd_addr];
//
always @(posedge clk)
if( wr_stb )
channels_mem[wr_addr] <= wr_data;
// fill queues off the output data
always @(posedge clk)
if( out_stb_mix ) mix_fifo.push_back(out_data);
//
always @(posedge clk)
if( out_stb_addr ) addr_fifo.push_back(out_data);
// channel generator/checker
always @(posedge clk)
if( sync_stb )
begin : chans
int i;
// if there was previous iteration, check it
// init channels for new iteration
for(i=0;i<32;i++)
begin
chans[i].init();
channels_mem[i*4+0] = chans[i].get_word(0);
channels_mem[i*4+1] = chans[i].get_word(1);
channels_mem[i*4+2] = chans[i].get_word(2);
channels_mem[i*4+3] = chans[i].get_word(3);
chans[i].update();
end
end
always @(posedge clk)
ch_enas = 32'hFFFF_FFFF;
// DUT
chan_ctrl chan_ctrl
(
.clk (clk ),
.rst_n(rst_n),
.rd_addr(rd_addr),
.rd_data(rd_data),
.wr_addr(wr_addr),
.wr_data(wr_data),
.wr_stb (wr_stb ),
.sync_stb(sync_stb),
.ch_enas(ch_enas),
.out_data (out_data ),
.out_stb_addr(out_stb_addr),
.out_stb_mix (out_stb_mix )
);
endmodule
|
module top (
input clk,
input [15:0] sw,
output [15:0] led,
// not used
input rx,
output tx
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [5:0] addr;
wire ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(7)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(ram_out),
.ram_in(ram_in)
);
RAM256X1S #(
.INIT(256'h96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5)
) ram0 (
.WCLK(clk),
.A({sw[0], addr}),
.O(ram_out),
.D(ram_in),
.WE(1'b1)
);
endmodule
|
module sky130_fd_sc_lp__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module system_ov7670_controller_1_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
module outputs
wire [58 : 0] client_request_get;
wire [39 : 0] server_response_get;
wire RDY_client_request_get,
RDY_client_response_put,
RDY_ecpRx,
RDY_ecpTx,
RDY_macAddr,
RDY_server_request_put,
RDY_server_response_get,
ecpRx,
ecpTx;
// inlined wires
wire eDoReq_1$wget,
eDoReq_1$whas,
ecpEgress_1$wget,
ecpEgress_1$whas,
ecpIngress_1$wget,
ecpIngress_1$whas,
edpFsm_abort$wget,
edpFsm_abort$whas,
edpFsm_start_reg_1_1$wget,
edpFsm_start_reg_1_1$whas,
edpFsm_start_wire$wget,
edpFsm_start_wire$whas,
edpFsm_state_fired_1$wget,
edpFsm_state_fired_1$whas,
edpFsm_state_overlap_pw$whas,
edpFsm_state_set_pw$whas;
// register doInFlight
reg doInFlight;
wire doInFlight$D_IN, doInFlight$EN;
// register eAddr
reg [31 : 0] eAddr;
wire [31 : 0] eAddr$D_IN;
wire eAddr$EN;
// register eDAddr
reg [47 : 0] eDAddr;
wire [47 : 0] eDAddr$D_IN;
wire eDAddr$EN;
// register eDMH
reg [31 : 0] eDMH;
wire [31 : 0] eDMH$D_IN;
wire eDMH$EN;
// register eData
reg [31 : 0] eData;
wire [31 : 0] eData$D_IN;
wire eData$EN;
// register eDoReq
reg eDoReq;
wire eDoReq$D_IN, eDoReq$EN;
// register eMAddr
reg [47 : 0] eMAddr;
wire [47 : 0] eMAddr$D_IN;
wire eMAddr$EN;
// register ePli
reg [15 : 0] ePli;
wire [15 : 0] ePli$D_IN;
wire ePli$EN;
// register eTyp
reg [15 : 0] eTyp;
wire [15 : 0] eTyp$D_IN;
wire eTyp$EN;
// register ecpEgress
reg ecpEgress;
wire ecpEgress$D_IN, ecpEgress$EN;
// register ecpIngress
reg ecpIngress;
wire ecpIngress$D_IN, ecpIngress$EN;
// register edpFsm_start_reg
reg edpFsm_start_reg;
wire edpFsm_start_reg$D_IN, edpFsm_start_reg$EN;
// register edpFsm_start_reg_1
reg edpFsm_start_reg_1;
wire edpFsm_start_reg_1$D_IN, edpFsm_start_reg_1$EN;
// register edpFsm_state_can_overlap
reg edpFsm_state_can_overlap;
wire edpFsm_state_can_overlap$D_IN, edpFsm_state_can_overlap$EN;
// register edpFsm_state_fired
reg edpFsm_state_fired;
wire edpFsm_state_fired$D_IN, edpFsm_state_fired$EN;
// register edpFsm_state_mkFSMstate
reg [3 : 0] edpFsm_state_mkFSMstate;
reg [3 : 0] edpFsm_state_mkFSMstate$D_IN;
wire edpFsm_state_mkFSMstate$EN;
// register eeDat
reg [31 : 0] eeDat;
wire [31 : 0] eeDat$D_IN;
wire eeDat$EN;
// register eeDmh
reg [31 : 0] eeDmh;
wire [31 : 0] eeDmh$D_IN;
wire eeDmh$EN;
// register eeMDst
reg [47 : 0] eeMDst;
wire [47 : 0] eeMDst$D_IN;
wire eeMDst$EN;
// register eePli
reg [15 : 0] eePli;
reg [15 : 0] eePli$D_IN;
wire eePli$EN;
// register isWrtResp
reg isWrtResp;
wire isWrtResp$D_IN, isWrtResp$EN;
// register lastResp
reg [44 : 0] lastResp;
wire [44 : 0] lastResp$D_IN;
wire lastResp$EN;
// register lastTag
reg [8 : 0] lastTag;
wire [8 : 0] lastTag$D_IN;
wire lastTag$EN;
// register ptr
reg [3 : 0] ptr;
wire [3 : 0] ptr$D_IN;
wire ptr$EN;
// register uMAddr
reg [47 : 0] uMAddr;
wire [47 : 0] uMAddr$D_IN;
wire uMAddr$EN;
// ports of submodule cpReqF
wire [58 : 0] cpReqF$D_IN, cpReqF$D_OUT;
wire cpReqF$CLR, cpReqF$DEQ, cpReqF$EMPTY_N, cpReqF$ENQ, cpReqF$FULL_N;
// ports of submodule cpRespF
wire [39 : 0] cpRespF$D_IN, cpRespF$D_OUT;
wire cpRespF$CLR, cpRespF$DEQ, cpRespF$EMPTY_N, cpRespF$ENQ, cpRespF$FULL_N;
// ports of submodule dcpReqF
reg [78 : 0] dcpReqF$D_IN;
wire [78 : 0] dcpReqF$D_OUT;
wire dcpReqF$CLR, dcpReqF$DEQ, dcpReqF$EMPTY_N, dcpReqF$ENQ, dcpReqF$FULL_N;
// ports of submodule dcpRespF
wire [44 : 0] dcpRespF$D_IN, dcpRespF$D_OUT;
wire dcpRespF$CLR,
dcpRespF$DEQ,
dcpRespF$EMPTY_N,
dcpRespF$ENQ,
dcpRespF$FULL_N;
// ports of submodule eMAddrF
wire [47 : 0] eMAddrF$D_IN, eMAddrF$D_OUT;
wire eMAddrF$CLR, eMAddrF$DEQ, eMAddrF$EMPTY_N, eMAddrF$ENQ, eMAddrF$FULL_N;
// ports of submodule ecpReqF
wire [39 : 0] ecpReqF$D_IN, ecpReqF$D_OUT;
wire ecpReqF$CLR, ecpReqF$DEQ, ecpReqF$EMPTY_N, ecpReqF$ENQ, ecpReqF$FULL_N;
// ports of submodule ecpRespF
reg [39 : 0] ecpRespF$D_IN;
wire [39 : 0] ecpRespF$D_OUT;
wire ecpRespF$CLR,
ecpRespF$DEQ,
ecpRespF$EMPTY_N,
ecpRespF$ENQ,
ecpRespF$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_cp_to_dcp_response,
WILL_FIRE_RL_dcp_to_cp_request,
WILL_FIRE_RL_ecp_ingress,
WILL_FIRE_RL_edpFsm_action_l243c16,
WILL_FIRE_RL_edpFsm_action_l244c16,
WILL_FIRE_RL_edpFsm_fsm_start,
WILL_FIRE_RL_edpFsm_idle_l235c3,
WILL_FIRE_RL_edpFsm_idle_l235c3_1;
// inputs to muxes for submodule ports
reg [44 : 0] MUX_dcpRespF$enq_1__VAL_1;
wire [44 : 0] MUX_dcpRespF$enq_1__VAL_2;
wire [39 : 0] MUX_ecpRespF$enq_1__VAL_1,
MUX_ecpRespF$enq_1__VAL_2,
MUX_ecpRespF$enq_1__VAL_3,
MUX_ecpRespF$enq_1__VAL_4,
MUX_ecpRespF$enq_1__VAL_5,
MUX_ecpRespF$enq_1__VAL_6,
MUX_ecpRespF$enq_1__VAL_7;
wire MUX_dcpRespF$enq_1__SEL_1,
MUX_doInFlight$write_1__SEL_1,
MUX_edpFsm_start_reg$write_1__SEL_2,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_1,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5,
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6;
// remaining internal signals
reg [7 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10;
reg [1 : 0] CASE_ecpRespFD_OUT_BITS_19_TO_18_3_0_ecpRespF_ETC__q3,
CASE_ecpRespFD_OUT_BITS_29_TO_28_3_0_ecpRespF_ETC__q2,
CASE_ecpRespFD_OUT_BITS_39_TO_38_3_0_ecpRespF_ETC__q1,
CASE_ecpRespFD_OUT_BITS_9_TO_8_3_0_ecpRespFD_ETC__q4,
CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q8,
CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q7,
CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q6,
CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q9;
reg CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q5;
wire [47 : 0] x__h3828, x__h5559, x__h5600, x__h5655, y__h5621, y__h5666;
wire [31 : 0] bedw__h2322;
wire [15 : 0] x__h5688, x__h5756;
wire [7 : 0] IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465;
wire [3 : 0] x__h2347;
wire IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152,
IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150,
dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463,
dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464,
dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155,
dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196,
eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100,
edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253;
// action method server_request_put
assign RDY_server_request_put = ecpReqF$FULL_N ;
// actionvalue method server_response_get
assign server_response_get =
{ CASE_ecpRespFD_OUT_BITS_39_TO_38_3_0_ecpRespF_ETC__q1,
ecpRespF$D_OUT[37:30],
CASE_ecpRespFD_OUT_BITS_29_TO_28_3_0_ecpRespF_ETC__q2,
ecpRespF$D_OUT[27:20],
CASE_ecpRespFD_OUT_BITS_19_TO_18_3_0_ecpRespF_ETC__q3,
ecpRespF$D_OUT[17:10],
CASE_ecpRespFD_OUT_BITS_9_TO_8_3_0_ecpRespFD_ETC__q4,
ecpRespF$D_OUT[7:0] } ;
assign RDY_server_response_get = ecpRespF$EMPTY_N ;
// actionvalue method client_request_get
assign client_request_get = cpReqF$D_OUT ;
assign RDY_client_request_get = cpReqF$EMPTY_N ;
// action method client_response_put
assign RDY_client_response_put = cpRespF$FULL_N ;
// action method macAddr
assign RDY_macAddr = 1'd1 ;
// value method ecpRx
assign ecpRx = ecpIngress ;
assign RDY_ecpRx = 1'd1 ;
// value method ecpTx
assign ecpTx = ecpEgress ;
assign RDY_ecpTx = 1'd1 ;
// submodule cpReqF
FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(cpReqF$D_IN),
.ENQ(cpReqF$ENQ),
.DEQ(cpReqF$DEQ),
.CLR(cpReqF$CLR),
.D_OUT(cpReqF$D_OUT),
.FULL_N(cpReqF$FULL_N),
.EMPTY_N(cpReqF$EMPTY_N));
// submodule cpRespF
FIFO2 #(.width(32'd40), .guarded(32'd1)) cpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(cpRespF$D_IN),
.ENQ(cpRespF$ENQ),
.DEQ(cpRespF$DEQ),
.CLR(cpRespF$CLR),
.D_OUT(cpRespF$D_OUT),
.FULL_N(cpRespF$FULL_N),
.EMPTY_N(cpRespF$EMPTY_N));
// submodule dcpReqF
FIFO2 #(.width(32'd79), .guarded(32'd1)) dcpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(dcpReqF$D_IN),
.ENQ(dcpReqF$ENQ),
.DEQ(dcpReqF$DEQ),
.CLR(dcpReqF$CLR),
.D_OUT(dcpReqF$D_OUT),
.FULL_N(dcpReqF$FULL_N),
.EMPTY_N(dcpReqF$EMPTY_N));
// submodule dcpRespF
FIFO2 #(.width(32'd45), .guarded(32'd1)) dcpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(dcpRespF$D_IN),
.ENQ(dcpRespF$ENQ),
.DEQ(dcpRespF$DEQ),
.CLR(dcpRespF$CLR),
.D_OUT(dcpRespF$D_OUT),
.FULL_N(dcpRespF$FULL_N),
.EMPTY_N(dcpRespF$EMPTY_N));
// submodule eMAddrF
FIFO2 #(.width(32'd48), .guarded(32'd1)) eMAddrF(.RST(RST_N),
.CLK(CLK),
.D_IN(eMAddrF$D_IN),
.ENQ(eMAddrF$ENQ),
.DEQ(eMAddrF$DEQ),
.CLR(eMAddrF$CLR),
.D_OUT(eMAddrF$D_OUT),
.FULL_N(eMAddrF$FULL_N),
.EMPTY_N(eMAddrF$EMPTY_N));
// submodule ecpReqF
FIFO2 #(.width(32'd40), .guarded(32'd1)) ecpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(ecpReqF$D_IN),
.ENQ(ecpReqF$ENQ),
.DEQ(ecpReqF$DEQ),
.CLR(ecpReqF$CLR),
.D_OUT(ecpReqF$D_OUT),
.FULL_N(ecpReqF$FULL_N),
.EMPTY_N(ecpReqF$EMPTY_N));
// submodule ecpRespF
FIFO2 #(.width(32'd40), .guarded(32'd1)) ecpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(ecpRespF$D_IN),
.ENQ(ecpRespF$ENQ),
.DEQ(ecpRespF$DEQ),
.CLR(ecpRespF$CLR),
.D_OUT(ecpRespF$D_OUT),
.FULL_N(ecpRespF$FULL_N),
.EMPTY_N(ecpRespF$EMPTY_N));
// rule RL_ecp_ingress
assign WILL_FIRE_RL_ecp_ingress = ecpReqF$EMPTY_N && !eDoReq ;
// rule RL_dcp_to_cp_request
assign WILL_FIRE_RL_dcp_to_cp_request =
dcpReqF$EMPTY_N &&
IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152 ;
// rule RL_cp_to_dcp_response
assign WILL_FIRE_RL_cp_to_dcp_response =
dcpRespF$FULL_N && cpRespF$EMPTY_N &&
!WILL_FIRE_RL_dcp_to_cp_request ;
// rule RL_edpFsm_action_l243c16
assign WILL_FIRE_RL_edpFsm_action_l243c16 =
ecpRespF$FULL_N && !isWrtResp &&
edpFsm_state_mkFSMstate == 4'd4 ;
// rule RL_edpFsm_action_l244c16
assign WILL_FIRE_RL_edpFsm_action_l244c16 =
ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd6 ;
// rule RL_edpFsm_fsm_start
assign WILL_FIRE_RL_edpFsm_fsm_start =
edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 &&
(!edpFsm_start_reg_1 || edpFsm_state_fired) &&
edpFsm_start_reg ;
// rule RL_edpFsm_idle_l235c3
assign WILL_FIRE_RL_edpFsm_idle_l235c3 =
!edpFsm_start_wire$whas && edpFsm_state_mkFSMstate == 4'd5 ;
// rule RL_edpFsm_idle_l235c3_1
assign WILL_FIRE_RL_edpFsm_idle_l235c3_1 =
!edpFsm_start_wire$whas && edpFsm_state_mkFSMstate == 4'd7 ;
// inputs to muxes for submodule ports
assign MUX_dcpRespF$enq_1__SEL_1 =
WILL_FIRE_RL_dcp_to_cp_request &&
dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155 ;
assign MUX_doInFlight$write_1__SEL_1 =
WILL_FIRE_RL_dcp_to_cp_request &&
(dcpReqF$D_OUT[78:77] == 2'd0 && dcpReqF$D_OUT[40] ||
dcpReqF$D_OUT[78:77] != 2'd0 &&
(dcpReqF$D_OUT[78:77] == 2'd1 && dcpReqF$D_OUT[76] ||
dcpReqF$D_OUT[78:77] != 2'd1 && dcpReqF$D_OUT[44])) ;
assign MUX_edpFsm_start_reg$write_1__SEL_2 =
edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 &&
(!edpFsm_start_reg_1 || edpFsm_state_fired) &&
!edpFsm_start_reg &&
eMAddrF$EMPTY_N &&
dcpRespF$EMPTY_N ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_1 =
WILL_FIRE_RL_edpFsm_idle_l235c3_1 ||
WILL_FIRE_RL_edpFsm_idle_l235c3 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 =
ecpRespF$FULL_N && edpFsm_start_wire$whas &&
edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 =
ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd1 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 =
ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd2 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 =
ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd3 ;
assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 =
ecpRespF$FULL_N && isWrtResp && edpFsm_state_mkFSMstate == 4'd4 ;
always@(dcpReqF$D_OUT or lastResp)
begin
case (dcpReqF$D_OUT[78:77])
2'd0:
MUX_dcpRespF$enq_1__VAL_1 =
{ 2'd0,
dcpReqF$D_OUT[40],
32'h40000001,
dcpReqF$D_OUT[39:32],
2'd0 };
2'd1:
MUX_dcpRespF$enq_1__VAL_1 =
{ dcpReqF$D_OUT[78:77],
32'hAAAAAAAA,
dcpReqF$D_OUT[76],
dcpReqF$D_OUT[71:64],
2'd0 };
default: MUX_dcpRespF$enq_1__VAL_1 =
{ (lastResp[44:43] == 2'd0 || lastResp[44:43] == 2'd1) ?
lastResp[44:43] :
2'd2,
lastResp[42:0] };
endcase
end
assign MUX_dcpRespF$enq_1__VAL_2 =
{ 2'd2,
doInFlight,
cpRespF$D_OUT[31:0],
cpRespF$D_OUT[39:32],
2'd0 } ;
assign MUX_ecpRespF$enq_1__VAL_1 =
{ 2'd0,
eeMDst[23:16],
2'd0,
eeMDst[31:24],
2'd0,
eeMDst[39:32],
2'd0,
eeMDst[47:40] } ;
assign MUX_ecpRespF$enq_1__VAL_2 =
{ 2'd0,
uMAddr[39:32],
2'd0,
uMAddr[47:40],
2'd0,
eeMDst[7:0],
2'd0,
eeMDst[15:8] } ;
assign MUX_ecpRespF$enq_1__VAL_3 =
{ 2'd0,
uMAddr[7:0],
2'd0,
uMAddr[15:8],
2'd0,
uMAddr[23:16],
2'd0,
uMAddr[31:24] } ;
assign MUX_ecpRespF$enq_1__VAL_4 =
{ 2'd0, eePli[7:0], 2'd0, eePli[15:8], 20'd65776 } ;
assign MUX_ecpRespF$enq_1__VAL_5 =
{ 2'd1,
eeDmh[31:24],
2'd0,
eeDmh[23:16],
2'd0,
eeDmh[15:8],
2'd0,
eeDmh[7:0] } ;
assign MUX_ecpRespF$enq_1__VAL_6 =
{ 2'd0,
eeDmh[31:24],
2'd0,
eeDmh[23:16],
2'd0,
eeDmh[15:8],
2'd0,
eeDmh[7:0] } ;
assign MUX_ecpRespF$enq_1__VAL_7 =
{ 2'd1,
eeDat[7:0],
2'd0,
eeDat[15:8],
2'd0,
eeDat[23:16],
2'd0,
eeDat[31:24] } ;
// inlined wires
assign eDoReq_1$wget =
(eDAddr == 48'hFFFFFFFFFFFF || eDAddr == uMAddr) &&
eTyp == 16'hF040 &&
(ePli == 16'd10 && ptr == 4'd5 ||
ePli == 16'd14 && ptr == 4'd6) ;
assign eDoReq_1$whas = WILL_FIRE_RL_ecp_ingress ;
assign ecpIngress_1$wget = 1'd1 ;
assign ecpIngress_1$whas = WILL_FIRE_RL_ecp_ingress ;
assign ecpEgress_1$wget =
edpFsm_state_mkFSMstate != 4'd0 &&
edpFsm_state_mkFSMstate != 4'd5 &&
edpFsm_state_mkFSMstate != 4'd7 ||
edpFsm_start_reg_1 && !edpFsm_state_fired ||
edpFsm_start_reg ;
assign ecpEgress_1$whas = 1'd1 ;
assign edpFsm_start_wire$wget = 1'd1 ;
assign edpFsm_start_wire$whas =
WILL_FIRE_RL_edpFsm_fsm_start ||
edpFsm_start_reg_1 && !edpFsm_state_fired ;
assign edpFsm_start_reg_1_1$wget = 1'd1 ;
assign edpFsm_start_reg_1_1$whas = edpFsm_start_wire$whas ;
assign edpFsm_abort$wget = 1'b0 ;
assign edpFsm_abort$whas = 1'b0 ;
assign edpFsm_state_fired_1$wget = 1'd1 ;
assign edpFsm_state_fired_1$whas = edpFsm_state_set_pw$whas ;
assign edpFsm_state_set_pw$whas =
WILL_FIRE_RL_edpFsm_idle_l235c3_1 ||
WILL_FIRE_RL_edpFsm_idle_l235c3 ||
WILL_FIRE_RL_edpFsm_action_l244c16 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 ;
assign edpFsm_state_overlap_pw$whas = 1'b0 ;
// register doInFlight
assign doInFlight$D_IN = MUX_doInFlight$write_1__SEL_1 ;
assign doInFlight$EN =
WILL_FIRE_RL_dcp_to_cp_request &&
(dcpReqF$D_OUT[78:77] == 2'd0 && dcpReqF$D_OUT[40] ||
dcpReqF$D_OUT[78:77] != 2'd0 &&
(dcpReqF$D_OUT[78:77] == 2'd1 && dcpReqF$D_OUT[76] ||
dcpReqF$D_OUT[78:77] != 2'd1 && dcpReqF$D_OUT[44])) ||
WILL_FIRE_RL_cp_to_dcp_response ;
// register eAddr
assign eAddr$D_IN = bedw__h2322 ;
assign eAddr$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd5 ;
// register eDAddr
assign eDAddr$D_IN = (ptr == 4'd0) ? x__h3828 : x__h5600 ;
assign eDAddr$EN =
WILL_FIRE_RL_ecp_ingress && (ptr == 4'd0 || ptr == 4'd1) ;
// register eDMH
assign eDMH$D_IN = bedw__h2322 ;
assign eDMH$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd4 ;
// register eData
assign eData$D_IN = bedw__h2322 ;
assign eData$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd6 ;
// register eDoReq
assign eDoReq$D_IN = WILL_FIRE_RL_ecp_ingress && eDoReq_1$wget ;
assign eDoReq$EN = 1'd1 ;
// register eMAddr
assign eMAddr$D_IN = (ptr == 4'd1) ? x__h5559 : x__h5655 ;
assign eMAddr$EN =
WILL_FIRE_RL_ecp_ingress && (ptr == 4'd1 || ptr == 4'd2) ;
// register ePli
assign ePli$D_IN = x__h5756 ;
assign ePli$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd3 ;
// register eTyp
assign eTyp$D_IN = x__h5688 ;
assign eTyp$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd3 ;
// register ecpEgress
assign ecpEgress$D_IN = ecpEgress_1$wget ;
assign ecpEgress$EN = 1'd1 ;
// register ecpIngress
assign ecpIngress$D_IN = WILL_FIRE_RL_ecp_ingress ;
assign ecpIngress$EN = 1'd1 ;
// register edpFsm_start_reg
assign edpFsm_start_reg$D_IN = !WILL_FIRE_RL_edpFsm_fsm_start ;
assign edpFsm_start_reg$EN =
WILL_FIRE_RL_edpFsm_fsm_start ||
MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register edpFsm_start_reg_1
assign edpFsm_start_reg_1$D_IN = edpFsm_start_wire$whas ;
assign edpFsm_start_reg_1$EN = 1'd1 ;
// register edpFsm_state_can_overlap
assign edpFsm_state_can_overlap$D_IN =
edpFsm_state_set_pw$whas || edpFsm_state_can_overlap ;
assign edpFsm_state_can_overlap$EN = 1'd1 ;
// register edpFsm_state_fired
assign edpFsm_state_fired$D_IN = edpFsm_state_set_pw$whas ;
assign edpFsm_state_fired$EN = 1'd1 ;
// register edpFsm_state_mkFSMstate
always@(MUX_edpFsm_state_mkFSMstate$write_1__SEL_1 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 or
WILL_FIRE_RL_edpFsm_action_l243c16 or
WILL_FIRE_RL_edpFsm_action_l244c16)
begin
case (1'b1) // synopsys parallel_case
MUX_edpFsm_state_mkFSMstate$write_1__SEL_1:
edpFsm_state_mkFSMstate$D_IN = 4'd0;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2:
edpFsm_state_mkFSMstate$D_IN = 4'd1;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3:
edpFsm_state_mkFSMstate$D_IN = 4'd2;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4:
edpFsm_state_mkFSMstate$D_IN = 4'd3;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5:
edpFsm_state_mkFSMstate$D_IN = 4'd4;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6:
edpFsm_state_mkFSMstate$D_IN = 4'd5;
WILL_FIRE_RL_edpFsm_action_l243c16: edpFsm_state_mkFSMstate$D_IN = 4'd6;
WILL_FIRE_RL_edpFsm_action_l244c16: edpFsm_state_mkFSMstate$D_IN = 4'd7;
default: edpFsm_state_mkFSMstate$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign edpFsm_state_mkFSMstate$EN =
WILL_FIRE_RL_edpFsm_idle_l235c3_1 ||
WILL_FIRE_RL_edpFsm_idle_l235c3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16 ;
// register eeDat
assign eeDat$D_IN = dcpRespF$D_OUT[41:10] ;
assign eeDat$EN =
MUX_edpFsm_start_reg$write_1__SEL_2 &&
dcpRespF$D_OUT[44:43] != 2'd1 ;
// register eeDmh
assign eeDmh$D_IN =
{ dcpRespF$D_OUT[9:2],
CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10,
16'h0 } ;
assign eeDmh$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register eeMDst
assign eeMDst$D_IN = eMAddrF$D_OUT ;
assign eeMDst$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register eePli
always@(dcpRespF$D_OUT)
begin
case (dcpRespF$D_OUT[44:43])
2'd0: eePli$D_IN = 16'd10;
2'd1: eePli$D_IN = 16'd6;
default: eePli$D_IN = 16'd10;
endcase
end
assign eePli$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register isWrtResp
assign isWrtResp$D_IN = dcpRespF$D_OUT[44:43] == 2'd1 ;
assign isWrtResp$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ;
// register lastResp
assign lastResp$D_IN = MUX_dcpRespF$enq_1__VAL_2 ;
assign lastResp$EN = WILL_FIRE_RL_cp_to_dcp_response && !doInFlight ;
// register lastTag
assign lastTag$D_IN =
{ dcpReqF$D_OUT[78:77] != 2'd0,
(dcpReqF$D_OUT[78:77] == 2'd1) ?
dcpReqF$D_OUT[71:64] :
dcpReqF$D_OUT[39:32] } ;
assign lastTag$EN =
WILL_FIRE_RL_dcp_to_cp_request &&
(dcpReqF$D_OUT[78:77] == 2'd0 && !dcpReqF$D_OUT[40] ||
dcpReqF$D_OUT[78:77] != 2'd0 &&
(dcpReqF$D_OUT[78:77] == 2'd1 &&
(!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 ||
!lastTag[8]) &&
!dcpReqF$D_OUT[76] ||
dcpReqF$D_OUT[78:77] != 2'd1 &&
(!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 ||
!lastTag[8]) &&
!dcpReqF$D_OUT[44])) ;
// register ptr
assign ptr$D_IN =
(x__h2347 == 4'd0) ? ((ptr == 4'd15) ? ptr : ptr + 4'd1) : 4'd0 ;
assign ptr$EN = WILL_FIRE_RL_ecp_ingress ;
// register uMAddr
assign uMAddr$D_IN = macAddr_u ;
assign uMAddr$EN = EN_macAddr ;
// submodule cpReqF
assign cpReqF$D_IN =
{ dcpReqF$D_OUT[78:77] != 2'd1,
(dcpReqF$D_OUT[78:77] == 2'd1) ?
{ dcpReqF$D_OUT[23:2],
dcpReqF$D_OUT[75:72],
dcpReqF$D_OUT[63:32] } :
{ 24'hAAAAAA,
dcpReqF$D_OUT[39:32],
dcpReqF$D_OUT[23:2],
dcpReqF$D_OUT[43:40] } } ;
assign cpReqF$ENQ =
WILL_FIRE_RL_dcp_to_cp_request && dcpReqF$D_OUT[78:77] != 2'd0 &&
dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196 ;
assign cpReqF$DEQ = EN_client_request_get ;
assign cpReqF$CLR = 1'b0 ;
// submodule cpRespF
assign cpRespF$D_IN = client_response_put ;
assign cpRespF$ENQ = EN_client_response_put ;
assign cpRespF$DEQ = WILL_FIRE_RL_cp_to_dcp_response ;
assign cpRespF$CLR = 1'b0 ;
// submodule dcpReqF
always@(eDMH or eAddr or eData)
begin
case (eDMH[13:12])
2'd0: dcpReqF$D_IN = { 38'h0AAAAAAAAA, eDMH[14], eDMH[7:0], eAddr };
2'd1:
dcpReqF$D_IN = { eDMH[13:12], eDMH[14], eDMH[11:0], eData, eAddr };
default: dcpReqF$D_IN = { 34'h2AAAAAAAA, eDMH[14], eDMH[11:0], eAddr };
endcase
end
assign dcpReqF$ENQ =
eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100 &&
eDoReq &&
(eDMH[13:12] == 2'd0 || eDMH[13:12] == 2'd1 ||
eDMH[13:12] == 2'd2) ;
assign dcpReqF$DEQ = WILL_FIRE_RL_dcp_to_cp_request ;
assign dcpReqF$CLR = 1'b0 ;
// submodule dcpRespF
assign dcpRespF$D_IN =
MUX_dcpRespF$enq_1__SEL_1 ?
MUX_dcpRespF$enq_1__VAL_1 :
MUX_dcpRespF$enq_1__VAL_2 ;
assign dcpRespF$ENQ =
WILL_FIRE_RL_dcp_to_cp_request &&
dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155 ||
WILL_FIRE_RL_cp_to_dcp_response ;
assign dcpRespF$DEQ = MUX_edpFsm_start_reg$write_1__SEL_2 ;
assign dcpRespF$CLR = 1'b0 ;
// submodule eMAddrF
assign eMAddrF$D_IN = eMAddr ;
assign eMAddrF$ENQ =
eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100 &&
eDoReq ;
assign eMAddrF$DEQ = MUX_edpFsm_start_reg$write_1__SEL_2 ;
assign eMAddrF$CLR = 1'b0 ;
// submodule ecpReqF
assign ecpReqF$D_IN =
{ CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q6,
server_request_put[37:30],
CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q7,
server_request_put[27:20],
CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q8,
server_request_put[17:10],
CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q9,
server_request_put[7:0] } ;
assign ecpReqF$ENQ = EN_server_request_put ;
assign ecpReqF$DEQ = WILL_FIRE_RL_ecp_ingress ;
assign ecpReqF$CLR = 1'b0 ;
// submodule ecpRespF
always@(MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 or
MUX_ecpRespF$enq_1__VAL_1 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 or
MUX_ecpRespF$enq_1__VAL_2 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 or
MUX_ecpRespF$enq_1__VAL_3 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 or
MUX_ecpRespF$enq_1__VAL_4 or
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 or
MUX_ecpRespF$enq_1__VAL_5 or
WILL_FIRE_RL_edpFsm_action_l243c16 or
MUX_ecpRespF$enq_1__VAL_6 or
WILL_FIRE_RL_edpFsm_action_l244c16 or MUX_ecpRespF$enq_1__VAL_7)
begin
case (1'b1) // synopsys parallel_case
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_1;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_2;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_3;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_4;
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_5;
WILL_FIRE_RL_edpFsm_action_l243c16:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_6;
WILL_FIRE_RL_edpFsm_action_l244c16:
ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_7;
default: ecpRespF$D_IN = 40'hAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign ecpRespF$ENQ =
MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16 ;
assign ecpRespF$DEQ = EN_server_response_get ;
assign ecpRespF$CLR = 1'b0 ;
// remaining internal signals
assign IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152 =
(dcpReqF$D_OUT[78:77] == 2'd0) ?
dcpRespF$FULL_N :
(dcpReqF$D_OUT[78:77] == 2'd1 ||
!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 ||
!lastTag[8] ||
dcpReqF$D_OUT[44] ||
dcpRespF$FULL_N) &&
IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150 ;
assign IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150 =
(dcpReqF$D_OUT[78:77] == 2'd1) ?
dcpRespF$FULL_N &&
(dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 &&
lastTag[8] &&
!dcpReqF$D_OUT[76] ||
cpReqF$FULL_N) :
dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 &&
lastTag[8] &&
!dcpReqF$D_OUT[44] ||
cpReqF$FULL_N ;
assign IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465 =
dcpRespF$D_OUT[42] ? 8'h70 : 8'h30 ;
assign bedw__h2322 =
{ x__h5688, ecpReqF$D_OUT[27:20], ecpReqF$D_OUT[37:30] } ;
assign dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 =
dcpReqF$D_OUT[39:32] == lastTag[7:0] ;
assign dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 =
dcpReqF$D_OUT[71:64] == lastTag[7:0] ;
assign dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155 =
dcpReqF$D_OUT[78:77] == 2'd0 || dcpReqF$D_OUT[78:77] == 2'd1 ||
dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 &&
lastTag[8] &&
!dcpReqF$D_OUT[44] ;
assign dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196 =
dcpReqF$D_OUT[78:77] == 2'd1 &&
(!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 ||
!lastTag[8] ||
dcpReqF$D_OUT[76]) ||
dcpReqF$D_OUT[78:77] != 2'd1 &&
(!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 ||
!lastTag[8] ||
dcpReqF$D_OUT[44]) ;
assign eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100 =
eMAddrF$FULL_N &&
CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q5 ;
assign edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 =
edpFsm_state_mkFSMstate == 4'd0 ||
edpFsm_state_mkFSMstate == 4'd5 ||
edpFsm_state_mkFSMstate == 4'd7 ;
assign x__h2347 =
{ ecpReqF$D_OUT[39:38] != 2'd0,
ecpReqF$D_OUT[29:28] != 2'd0,
ecpReqF$D_OUT[19:18] != 2'd0,
ecpReqF$D_OUT[9:8] != 2'd0 } ;
assign x__h3828 = { bedw__h2322, 16'h0 } ;
assign x__h5559 = { x__h5756, 32'h0 } ;
assign x__h5600 = eDAddr | y__h5621 ;
assign x__h5655 = eMAddr | y__h5666 ;
assign x__h5688 = { ecpReqF$D_OUT[7:0], ecpReqF$D_OUT[17:10] } ;
assign x__h5756 = { ecpReqF$D_OUT[27:20], ecpReqF$D_OUT[37:30] } ;
assign y__h5621 = { 32'h0, x__h5688 } ;
assign y__h5666 = { 16'd0, bedw__h2322 } ;
always@(ecpRespF$D_OUT)
begin
case (ecpRespF$D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_ecpRespFD_OUT_BITS_39_TO_38_3_0_ecpRespF_ETC__q1 =
ecpRespF$D_OUT[39:38];
2'd3: CASE_ecpRespFD_OUT_BITS_39_TO_38_3_0_ecpRespF_ETC__q1 = 2'd3;
endcase
end
always@(ecpRespF$D_OUT)
begin
case (ecpRespF$D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_ecpRespFD_OUT_BITS_29_TO_28_3_0_ecpRespF_ETC__q2 =
ecpRespF$D_OUT[29:28];
2'd3: CASE_ecpRespFD_OUT_BITS_29_TO_28_3_0_ecpRespF_ETC__q2 = 2'd3;
endcase
end
always@(ecpRespF$D_OUT)
begin
case (ecpRespF$D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_ecpRespFD_OUT_BITS_19_TO_18_3_0_ecpRespF_ETC__q3 =
ecpRespF$D_OUT[19:18];
2'd3: CASE_ecpRespFD_OUT_BITS_19_TO_18_3_0_ecpRespF_ETC__q3 = 2'd3;
endcase
end
always@(ecpRespF$D_OUT)
begin
case (ecpRespF$D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_ecpRespFD_OUT_BITS_9_TO_8_3_0_ecpRespFD_ETC__q4 =
ecpRespF$D_OUT[9:8];
2'd3: CASE_ecpRespFD_OUT_BITS_9_TO_8_3_0_ecpRespFD_ETC__q4 = 2'd3;
endcase
end
always@(eDMH or dcpReqF$FULL_N)
begin
case (eDMH[13:12])
2'd0, 2'd1:
CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q5 =
dcpReqF$FULL_N;
default: CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q5 =
eDMH[13:12] != 2'd2 || dcpReqF$FULL_N;
endcase
end
always@(server_request_put)
begin
case (server_request_put[39:38])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q6 =
server_request_put[39:38];
2'd3: CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q6 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[29:28])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q7 =
server_request_put[29:28];
2'd3: CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q7 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[19:18])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q8 =
server_request_put[19:18];
2'd3: CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q8 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[9:8])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q9 =
server_request_put[9:8];
2'd3: CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q9 = 2'd3;
endcase
end
always@(dcpRespF$D_OUT or
IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465)
begin
case (dcpRespF$D_OUT[44:43])
2'd0:
CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 =
IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465;
2'd1:
CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 =
dcpRespF$D_OUT[10] ? 8'h70 : 8'h30;
default: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 =
IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
doInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
eDoReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
ecpEgress <= `BSV_ASSIGNMENT_DELAY 1'd0;
ecpIngress <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
edpFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
edpFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
lastTag <= `BSV_ASSIGNMENT_DELAY 9'd170;
ptr <= `BSV_ASSIGNMENT_DELAY 4'd0;
end
else
begin
if (doInFlight$EN)
doInFlight <= `BSV_ASSIGNMENT_DELAY doInFlight$D_IN;
if (eDoReq$EN) eDoReq <= `BSV_ASSIGNMENT_DELAY eDoReq$D_IN;
if (ecpEgress$EN) ecpEgress <= `BSV_ASSIGNMENT_DELAY ecpEgress$D_IN;
if (ecpIngress$EN)
ecpIngress <= `BSV_ASSIGNMENT_DELAY ecpIngress$D_IN;
if (edpFsm_start_reg$EN)
edpFsm_start_reg <= `BSV_ASSIGNMENT_DELAY edpFsm_start_reg$D_IN;
if (edpFsm_start_reg_1$EN)
edpFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY edpFsm_start_reg_1$D_IN;
if (edpFsm_state_can_overlap$EN)
edpFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
edpFsm_state_can_overlap$D_IN;
if (edpFsm_state_fired$EN)
edpFsm_state_fired <= `BSV_ASSIGNMENT_DELAY edpFsm_state_fired$D_IN;
if (edpFsm_state_mkFSMstate$EN)
edpFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
edpFsm_state_mkFSMstate$D_IN;
if (lastTag$EN) lastTag <= `BSV_ASSIGNMENT_DELAY lastTag$D_IN;
if (ptr$EN) ptr <= `BSV_ASSIGNMENT_DELAY ptr$D_IN;
end
if (eAddr$EN) eAddr <= `BSV_ASSIGNMENT_DELAY eAddr$D_IN;
if (eDAddr$EN) eDAddr <= `BSV_ASSIGNMENT_DELAY eDAddr$D_IN;
if (eDMH$EN) eDMH <= `BSV_ASSIGNMENT_DELAY eDMH$D_IN;
if (eData$EN) eData <= `BSV_ASSIGNMENT_DELAY eData$D_IN;
if (eMAddr$EN) eMAddr <= `BSV_ASSIGNMENT_DELAY eMAddr$D_IN;
if (ePli$EN) ePli <= `BSV_ASSIGNMENT_DELAY ePli$D_IN;
if (eTyp$EN) eTyp <= `BSV_ASSIGNMENT_DELAY eTyp$D_IN;
if (eeDat$EN) eeDat <= `BSV_ASSIGNMENT_DELAY eeDat$D_IN;
if (eeDmh$EN) eeDmh <= `BSV_ASSIGNMENT_DELAY eeDmh$D_IN;
if (eeMDst$EN) eeMDst <= `BSV_ASSIGNMENT_DELAY eeMDst$D_IN;
if (eePli$EN) eePli <= `BSV_ASSIGNMENT_DELAY eePli$D_IN;
if (isWrtResp$EN) isWrtResp <= `BSV_ASSIGNMENT_DELAY isWrtResp$D_IN;
if (lastResp$EN) lastResp <= `BSV_ASSIGNMENT_DELAY lastResp$D_IN;
if (uMAddr$EN) uMAddr <= `BSV_ASSIGNMENT_DELAY uMAddr$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
doInFlight = 1'h0;
eAddr = 32'hAAAAAAAA;
eDAddr = 48'hAAAAAAAAAAAA;
eDMH = 32'hAAAAAAAA;
eData = 32'hAAAAAAAA;
eDoReq = 1'h0;
eMAddr = 48'hAAAAAAAAAAAA;
ePli = 16'hAAAA;
eTyp = 16'hAAAA;
ecpEgress = 1'h0;
ecpIngress = 1'h0;
edpFsm_start_reg = 1'h0;
edpFsm_start_reg_1 = 1'h0;
edpFsm_state_can_overlap = 1'h0;
edpFsm_state_fired = 1'h0;
edpFsm_state_mkFSMstate = 4'hA;
eeDat = 32'hAAAAAAAA;
eeDmh = 32'hAAAAAAAA;
eeMDst = 48'hAAAAAAAAAAAA;
eePli = 16'hAAAA;
isWrtResp = 1'h0;
lastResp = 45'h0AAAAAAAAAAA;
lastTag = 9'h0AA;
ptr = 4'hA;
uMAddr = 48'hAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 &&
(MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 237, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l237c14] and\n [RL_edpFsm_action_l238c14, RL_edpFsm_action_l239c14,\n RL_edpFsm_action_l241c16, RL_edpFsm_action_l243c16,\n RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 &&
(MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 238, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l238c14] and\n [RL_edpFsm_action_l239c14, RL_edpFsm_action_l241c16,\n RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 &&
(MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 239, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l239c14] and\n [RL_edpFsm_action_l241c16, RL_edpFsm_action_l243c16,\n RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 &&
(WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 241, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l241c16] and\n [RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_edpFsm_action_l243c16 &&
WILL_FIRE_RL_edpFsm_action_l244c16)
$display("Error: \"bsv/eth/EDCP.bsv\", line 243, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l243c16] and\n [RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 &&
(MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 ||
MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 ||
WILL_FIRE_RL_edpFsm_action_l243c16 ||
WILL_FIRE_RL_edpFsm_action_l244c16))
$display("Error: \"bsv/eth/EDCP.bsv\", line 236, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l236c14] and\n [RL_edpFsm_action_l237c14, RL_edpFsm_action_l238c14,\n RL_edpFsm_action_l239c14, RL_edpFsm_action_l241c16,\n RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n");
end
// synopsys translate_on
endmodule
|
module sky130_fd_sc_hs__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hs__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hs__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hs__fill base ();
endmodule
|
module adapter_dpb_ppfifo #(
parameter MEM_DEPTH = 9,
parameter DATA_WIDTH = 32
)(
input clk,
input rst,
input i_ppfifo_2_mem_en,
input i_mem_2_ppfifo_stb,
input i_cancel_write_stb,
output reg [31:0] o_num_reads,
output o_idle,
//User Memory Interface
input i_bram_we,
input [MEM_DEPTH - 1: 0] i_bram_addr,
input [DATA_WIDTH - 1: 0] i_bram_din,
output [DATA_WIDTH - 1: 0] o_bram_dout,
output o_bram_valid,
//Ping Pong FIFO Interface
input ppfifo_clk,
input [1:0] i_write_ready,
output reg [1:0] o_write_activate,
input [23:0] i_write_size,
output reg o_write_stb,
output [DATA_WIDTH - 1:0] o_write_data,
input i_read_ready,
output reg o_read_activate,
input [23:0] i_read_size,
input [DATA_WIDTH - 1:0] i_read_data,
output reg o_read_stb
);
//local parameters
localparam MEM_SIZE = (2 ** MEM_DEPTH);
//States
localparam IDLE = 0;
localparam WRITE_SETUP = 1;
localparam WRITE = 2;
localparam READ = 3;
//registes/wires
wire w_pf_rd_en;
wire w_pf_wr_stb;
wire w_pf_cancel_stb;
reg [3:0] state;
reg [23:0] count;
reg r_we;
reg [MEM_DEPTH - 1: 0] r_addr;
reg [3:0] mem_wait_count;
reg [23:0] prev_mem_addr;
//submodules
cross_clock_enable p_en_r (
.rst (rst ),
.in_en (i_ppfifo_2_mem_en ),
.out_clk (ppfifo_clk ),
.out_en (w_pf_rd_en )
);
cross_clock_strobe p_stb_w (
.rst (rst ),
.in_clk (clk ),
.in_stb (i_mem_2_ppfifo_stb ),
.out_clk (ppfifo_clk ),
.out_stb (w_pf_wr_stb )
);
cross_clock_strobe p_stb_cncl_w (
.rst (rst ),
.in_clk (clk ),
.in_stb (i_cancel_write_stb ),
.out_clk (ppfifo_clk ),
.out_stb (w_pf_cancel_stb )
);
//Read/Write Data to a local buffer
dpb #(
.DATA_WIDTH (DATA_WIDTH ),
.ADDR_WIDTH (MEM_DEPTH )
) local_buffer (
.clka (clk ),
.wea (i_bram_we ),
.addra (i_bram_addr ),
.douta (o_bram_dout ),
.dina (i_bram_din ),
.clkb (ppfifo_clk ),
.web (r_we ),
.addrb (r_addr ),
.dinb (i_read_data ),
.doutb (o_write_data )
);
//assign o_write_data = 32'h01234567;
//asynchronous logic
assign o_idle = (state == IDLE);
//synchronous logic
assign o_bram_valid = ((prev_mem_addr == i_bram_addr) && (mem_wait_count == `MEM_WAIT));
always @ (posedge clk) begin
if (rst) begin
mem_wait_count <= `MEM_WAIT;
prev_mem_addr <= 0;
end
else begin
if (prev_mem_addr != i_bram_addr) begin
mem_wait_count <= 0;
prev_mem_addr <= i_bram_addr;
end
else begin
if (mem_wait_count < `MEM_WAIT) begin
mem_wait_count <= mem_wait_count + 1;
end
end
end
end
always @ (posedge ppfifo_clk) begin
o_read_stb <= 0;
o_write_stb <= 0;
r_we <= 0;
if (rst || w_pf_cancel_stb) begin
o_write_activate <= 0;
o_read_activate <= 0;
o_num_reads <= 0;
count <= 0;
r_addr <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
o_read_activate <= 0;
o_write_activate <= 0;
r_addr <= 0;
count <= 0;
if (w_pf_wr_stb) begin
//Load the memory data into the PPFIFO
state <= WRITE_SETUP;
end
else if (w_pf_rd_en) begin
if (i_read_ready) begin
o_read_activate <= 1;
state <= READ;
end
end
end
WRITE_SETUP: begin
if ((i_write_ready > 0) && (o_write_activate == 0)) begin
if (i_write_ready[0]) begin
o_write_activate[0] <= 1;
end
else begin
o_write_activate[1] <= 1;
end
state <= WRITE;
end
end
WRITE: begin
if (count < i_write_size) begin
r_addr <= r_addr + 1;
o_write_stb <= 1;
count <= count + 1;
end
else begin
o_write_activate <= 0;
state <= IDLE;
end
end
READ: begin
//Memory Interface
r_we <= 1;
if (r_we) begin
if (count < i_read_size) begin
o_read_stb <= 1;
count <= count + 1;
o_num_reads <= o_num_reads + 1;
end
else begin
//Done Reading
o_read_activate <= 0;
state <= IDLE;
r_we <= 0;
end
end
if (o_read_stb) begin
//Delay incrementing the address
r_addr <= r_addr + 1;
end
end
default: begin
//Shouldn't get here
state <= IDLE;
end
endcase
end
end
endmodule
|
module e203_soc_top(
// This clock should comes from the crystal pad generated high speed clock (16MHz)
input hfextclk,
output hfxoscen,// The signal to enable the crystal pad generated clock
// This clock should comes from the crystal pad generated low speed clock (32.768KHz)
input lfextclk,
output lfxoscen,// The signal to enable the crystal pad generated clock
// The JTAG TCK is input, need to be pull-up
input io_pads_jtag_TCK_i_ival,
// The JTAG TMS is input, need to be pull-up
input io_pads_jtag_TMS_i_ival,
// The JTAG TDI is input, need to be pull-up
input io_pads_jtag_TDI_i_ival,
// The JTAG TDO is output have enable
output io_pads_jtag_TDO_o_oval,
output io_pads_jtag_TDO_o_oe,
// The GPIO are all bidir pad have enables
input io_pads_gpio_0_i_ival,
output io_pads_gpio_0_o_oval,
output io_pads_gpio_0_o_oe,
output io_pads_gpio_0_o_ie,
output io_pads_gpio_0_o_pue,
output io_pads_gpio_0_o_ds,
input io_pads_gpio_1_i_ival,
output io_pads_gpio_1_o_oval,
output io_pads_gpio_1_o_oe,
output io_pads_gpio_1_o_ie,
output io_pads_gpio_1_o_pue,
output io_pads_gpio_1_o_ds,
input io_pads_gpio_2_i_ival,
output io_pads_gpio_2_o_oval,
output io_pads_gpio_2_o_oe,
output io_pads_gpio_2_o_ie,
output io_pads_gpio_2_o_pue,
output io_pads_gpio_2_o_ds,
input io_pads_gpio_3_i_ival,
output io_pads_gpio_3_o_oval,
output io_pads_gpio_3_o_oe,
output io_pads_gpio_3_o_ie,
output io_pads_gpio_3_o_pue,
output io_pads_gpio_3_o_ds,
input io_pads_gpio_4_i_ival,
output io_pads_gpio_4_o_oval,
output io_pads_gpio_4_o_oe,
output io_pads_gpio_4_o_ie,
output io_pads_gpio_4_o_pue,
output io_pads_gpio_4_o_ds,
input io_pads_gpio_5_i_ival,
output io_pads_gpio_5_o_oval,
output io_pads_gpio_5_o_oe,
output io_pads_gpio_5_o_ie,
output io_pads_gpio_5_o_pue,
output io_pads_gpio_5_o_ds,
input io_pads_gpio_6_i_ival,
output io_pads_gpio_6_o_oval,
output io_pads_gpio_6_o_oe,
output io_pads_gpio_6_o_ie,
output io_pads_gpio_6_o_pue,
output io_pads_gpio_6_o_ds,
input io_pads_gpio_7_i_ival,
output io_pads_gpio_7_o_oval,
output io_pads_gpio_7_o_oe,
output io_pads_gpio_7_o_ie,
output io_pads_gpio_7_o_pue,
output io_pads_gpio_7_o_ds,
input io_pads_gpio_8_i_ival,
output io_pads_gpio_8_o_oval,
output io_pads_gpio_8_o_oe,
output io_pads_gpio_8_o_ie,
output io_pads_gpio_8_o_pue,
output io_pads_gpio_8_o_ds,
input io_pads_gpio_9_i_ival,
output io_pads_gpio_9_o_oval,
output io_pads_gpio_9_o_oe,
output io_pads_gpio_9_o_ie,
output io_pads_gpio_9_o_pue,
output io_pads_gpio_9_o_ds,
input io_pads_gpio_10_i_ival,
output io_pads_gpio_10_o_oval,
output io_pads_gpio_10_o_oe,
output io_pads_gpio_10_o_ie,
output io_pads_gpio_10_o_pue,
output io_pads_gpio_10_o_ds,
input io_pads_gpio_11_i_ival,
output io_pads_gpio_11_o_oval,
output io_pads_gpio_11_o_oe,
output io_pads_gpio_11_o_ie,
output io_pads_gpio_11_o_pue,
output io_pads_gpio_11_o_ds,
input io_pads_gpio_12_i_ival,
output io_pads_gpio_12_o_oval,
output io_pads_gpio_12_o_oe,
output io_pads_gpio_12_o_ie,
output io_pads_gpio_12_o_pue,
output io_pads_gpio_12_o_ds,
input io_pads_gpio_13_i_ival,
output io_pads_gpio_13_o_oval,
output io_pads_gpio_13_o_oe,
output io_pads_gpio_13_o_ie,
output io_pads_gpio_13_o_pue,
output io_pads_gpio_13_o_ds,
input io_pads_gpio_14_i_ival,
output io_pads_gpio_14_o_oval,
output io_pads_gpio_14_o_oe,
output io_pads_gpio_14_o_ie,
output io_pads_gpio_14_o_pue,
output io_pads_gpio_14_o_ds,
input io_pads_gpio_15_i_ival,
output io_pads_gpio_15_o_oval,
output io_pads_gpio_15_o_oe,
output io_pads_gpio_15_o_ie,
output io_pads_gpio_15_o_pue,
output io_pads_gpio_15_o_ds,
input io_pads_gpio_16_i_ival,
output io_pads_gpio_16_o_oval,
output io_pads_gpio_16_o_oe,
output io_pads_gpio_16_o_ie,
output io_pads_gpio_16_o_pue,
output io_pads_gpio_16_o_ds,
input io_pads_gpio_17_i_ival,
output io_pads_gpio_17_o_oval,
output io_pads_gpio_17_o_oe,
output io_pads_gpio_17_o_ie,
output io_pads_gpio_17_o_pue,
output io_pads_gpio_17_o_ds,
input io_pads_gpio_18_i_ival,
output io_pads_gpio_18_o_oval,
output io_pads_gpio_18_o_oe,
output io_pads_gpio_18_o_ie,
output io_pads_gpio_18_o_pue,
output io_pads_gpio_18_o_ds,
input io_pads_gpio_19_i_ival,
output io_pads_gpio_19_o_oval,
output io_pads_gpio_19_o_oe,
output io_pads_gpio_19_o_ie,
output io_pads_gpio_19_o_pue,
output io_pads_gpio_19_o_ds,
input io_pads_gpio_20_i_ival,
output io_pads_gpio_20_o_oval,
output io_pads_gpio_20_o_oe,
output io_pads_gpio_20_o_ie,
output io_pads_gpio_20_o_pue,
output io_pads_gpio_20_o_ds,
input io_pads_gpio_21_i_ival,
output io_pads_gpio_21_o_oval,
output io_pads_gpio_21_o_oe,
output io_pads_gpio_21_o_ie,
output io_pads_gpio_21_o_pue,
output io_pads_gpio_21_o_ds,
input io_pads_gpio_22_i_ival,
output io_pads_gpio_22_o_oval,
output io_pads_gpio_22_o_oe,
output io_pads_gpio_22_o_ie,
output io_pads_gpio_22_o_pue,
output io_pads_gpio_22_o_ds,
input io_pads_gpio_23_i_ival,
output io_pads_gpio_23_o_oval,
output io_pads_gpio_23_o_oe,
output io_pads_gpio_23_o_ie,
output io_pads_gpio_23_o_pue,
output io_pads_gpio_23_o_ds,
input io_pads_gpio_24_i_ival,
output io_pads_gpio_24_o_oval,
output io_pads_gpio_24_o_oe,
output io_pads_gpio_24_o_ie,
output io_pads_gpio_24_o_pue,
output io_pads_gpio_24_o_ds,
input io_pads_gpio_25_i_ival,
output io_pads_gpio_25_o_oval,
output io_pads_gpio_25_o_oe,
output io_pads_gpio_25_o_ie,
output io_pads_gpio_25_o_pue,
output io_pads_gpio_25_o_ds,
input io_pads_gpio_26_i_ival,
output io_pads_gpio_26_o_oval,
output io_pads_gpio_26_o_oe,
output io_pads_gpio_26_o_ie,
output io_pads_gpio_26_o_pue,
output io_pads_gpio_26_o_ds,
input io_pads_gpio_27_i_ival,
output io_pads_gpio_27_o_oval,
output io_pads_gpio_27_o_oe,
output io_pads_gpio_27_o_ie,
output io_pads_gpio_27_o_pue,
output io_pads_gpio_27_o_ds,
input io_pads_gpio_28_i_ival,
output io_pads_gpio_28_o_oval,
output io_pads_gpio_28_o_oe,
output io_pads_gpio_28_o_ie,
output io_pads_gpio_28_o_pue,
output io_pads_gpio_28_o_ds,
input io_pads_gpio_29_i_ival,
output io_pads_gpio_29_o_oval,
output io_pads_gpio_29_o_oe,
output io_pads_gpio_29_o_ie,
output io_pads_gpio_29_o_pue,
output io_pads_gpio_29_o_ds,
input io_pads_gpio_30_i_ival,
output io_pads_gpio_30_o_oval,
output io_pads_gpio_30_o_oe,
output io_pads_gpio_30_o_ie,
output io_pads_gpio_30_o_pue,
output io_pads_gpio_30_o_ds,
input io_pads_gpio_31_i_ival,
output io_pads_gpio_31_o_oval,
output io_pads_gpio_31_o_oe,
output io_pads_gpio_31_o_ie,
output io_pads_gpio_31_o_pue,
output io_pads_gpio_31_o_ds,
//QSPI SCK and CS is output without enable
output io_pads_qspi_sck_o_oval,
output io_pads_qspi_cs_0_o_oval,
//QSPI DQ is bidir I/O with enable, and need pull-up enable
input io_pads_qspi_dq_0_i_ival,
output io_pads_qspi_dq_0_o_oval,
output io_pads_qspi_dq_0_o_oe,
output io_pads_qspi_dq_0_o_ie,
output io_pads_qspi_dq_0_o_pue,
output io_pads_qspi_dq_0_o_ds,
input io_pads_qspi_dq_1_i_ival,
output io_pads_qspi_dq_1_o_oval,
output io_pads_qspi_dq_1_o_oe,
output io_pads_qspi_dq_1_o_ie,
output io_pads_qspi_dq_1_o_pue,
output io_pads_qspi_dq_1_o_ds,
input io_pads_qspi_dq_2_i_ival,
output io_pads_qspi_dq_2_o_oval,
output io_pads_qspi_dq_2_o_oe,
output io_pads_qspi_dq_2_o_ie,
output io_pads_qspi_dq_2_o_pue,
output io_pads_qspi_dq_2_o_ds,
input io_pads_qspi_dq_3_i_ival,
output io_pads_qspi_dq_3_o_oval,
output io_pads_qspi_dq_3_o_oe,
output io_pads_qspi_dq_3_o_ie,
output io_pads_qspi_dq_3_o_pue,
output io_pads_qspi_dq_3_o_ds,
// Erst is input need to be pull-up by default
input io_pads_aon_erst_n_i_ival,
// dbgmode are inputs need to be pull-up by default
input io_pads_dbgmode0_n_i_ival,
input io_pads_dbgmode1_n_i_ival,
input io_pads_dbgmode2_n_i_ival,
// BootRom is input need to be pull-up by default
input io_pads_bootrom_n_i_ival,
// dwakeup is input need to be pull-up by default
input io_pads_aon_pmu_dwakeup_n_i_ival,
// PMU output is just output without enable
output io_pads_aon_pmu_padrst_o_oval,
output io_pads_aon_pmu_vddpaden_o_oval
);
wire sysper_icb_cmd_valid;
wire sysper_icb_cmd_ready;
wire sysfio_icb_cmd_valid;
wire sysfio_icb_cmd_ready;
wire sysmem_icb_cmd_valid;
wire sysmem_icb_cmd_ready;
e203_subsys_top u_e203_subsys_top(
.core_mhartid (1'b0),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (1'b0),
.ext2itcm_icb_cmd_ready (),
.ext2itcm_icb_cmd_addr (`E203_ITCM_ADDR_WIDTH'b0 ),
.ext2itcm_icb_cmd_read (1'b0 ),
.ext2itcm_icb_cmd_wdata (32'b0),
.ext2itcm_icb_cmd_wmask (4'b0),
.ext2itcm_icb_rsp_valid (),
.ext2itcm_icb_rsp_ready (1'b0),
.ext2itcm_icb_rsp_err (),
.ext2itcm_icb_rsp_rdata (),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (1'b0),
.ext2dtcm_icb_cmd_ready (),
.ext2dtcm_icb_cmd_addr (`E203_DTCM_ADDR_WIDTH'b0 ),
.ext2dtcm_icb_cmd_read (1'b0 ),
.ext2dtcm_icb_cmd_wdata (32'b0),
.ext2dtcm_icb_cmd_wmask (4'b0),
.ext2dtcm_icb_rsp_valid (),
.ext2dtcm_icb_rsp_ready (1'b0),
.ext2dtcm_icb_rsp_err (),
.ext2dtcm_icb_rsp_rdata (),
`endif//}
.sysper_icb_cmd_valid (sysper_icb_cmd_valid),
.sysper_icb_cmd_ready (sysper_icb_cmd_ready),
.sysper_icb_cmd_read (),
.sysper_icb_cmd_addr (),
.sysper_icb_cmd_wdata (),
.sysper_icb_cmd_wmask (),
.sysper_icb_rsp_valid (sysper_icb_cmd_valid),
.sysper_icb_rsp_ready (sysper_icb_cmd_ready),
.sysper_icb_rsp_err (1'b0 ),
.sysper_icb_rsp_rdata (32'b0),
.sysfio_icb_cmd_valid(sysfio_icb_cmd_valid),
.sysfio_icb_cmd_ready(sysfio_icb_cmd_ready),
.sysfio_icb_cmd_read (),
.sysfio_icb_cmd_addr (),
.sysfio_icb_cmd_wdata(),
.sysfio_icb_cmd_wmask(),
.sysfio_icb_rsp_valid(sysfio_icb_cmd_valid),
.sysfio_icb_rsp_ready(sysfio_icb_cmd_ready),
.sysfio_icb_rsp_err (1'b0 ),
.sysfio_icb_rsp_rdata(32'b0),
.sysmem_icb_cmd_valid(sysmem_icb_cmd_valid),
.sysmem_icb_cmd_ready(sysmem_icb_cmd_ready),
.sysmem_icb_cmd_read (),
.sysmem_icb_cmd_addr (),
.sysmem_icb_cmd_wdata(),
.sysmem_icb_cmd_wmask(),
.sysmem_icb_rsp_valid(sysmem_icb_cmd_valid),
.sysmem_icb_rsp_ready(sysmem_icb_cmd_ready),
.sysmem_icb_rsp_err (1'b0 ),
.sysmem_icb_rsp_rdata(32'b0),
.io_pads_jtag_TCK_i_ival (io_pads_jtag_TCK_i_ival ),
.io_pads_jtag_TCK_o_oval (),
.io_pads_jtag_TCK_o_oe (),
.io_pads_jtag_TCK_o_ie (),
.io_pads_jtag_TCK_o_pue (),
.io_pads_jtag_TCK_o_ds (),
.io_pads_jtag_TMS_i_ival (io_pads_jtag_TMS_i_ival ),
.io_pads_jtag_TMS_o_oval (),
.io_pads_jtag_TMS_o_oe (),
.io_pads_jtag_TMS_o_ie (),
.io_pads_jtag_TMS_o_pue (),
.io_pads_jtag_TMS_o_ds (),
.io_pads_jtag_TDI_i_ival (io_pads_jtag_TDI_i_ival ),
.io_pads_jtag_TDI_o_oval (),
.io_pads_jtag_TDI_o_oe (),
.io_pads_jtag_TDI_o_ie (),
.io_pads_jtag_TDI_o_pue (),
.io_pads_jtag_TDI_o_ds (),
.io_pads_jtag_TDO_i_ival (1'b1 ),
.io_pads_jtag_TDO_o_oval (io_pads_jtag_TDO_o_oval ),
.io_pads_jtag_TDO_o_oe (io_pads_jtag_TDO_o_oe ),
.io_pads_jtag_TDO_o_ie (),
.io_pads_jtag_TDO_o_pue (),
.io_pads_jtag_TDO_o_ds (),
.io_pads_jtag_TRST_n_i_ival (1'b1 ),
.io_pads_jtag_TRST_n_o_oval (),
.io_pads_jtag_TRST_n_o_oe (),
.io_pads_jtag_TRST_n_o_ie (),
.io_pads_jtag_TRST_n_o_pue (),
.io_pads_jtag_TRST_n_o_ds (),
.test_mode(1'b0),
.test_iso_override(1'b0),
.io_pads_gpio_0_i_ival (io_pads_gpio_0_i_ival & io_pads_gpio_0_o_ie),
.io_pads_gpio_0_o_oval (io_pads_gpio_0_o_oval),
.io_pads_gpio_0_o_oe (io_pads_gpio_0_o_oe),
.io_pads_gpio_0_o_ie (io_pads_gpio_0_o_ie),
.io_pads_gpio_0_o_pue (io_pads_gpio_0_o_pue),
.io_pads_gpio_0_o_ds (io_pads_gpio_0_o_ds),
.io_pads_gpio_1_i_ival (io_pads_gpio_1_i_ival & io_pads_gpio_1_o_ie),
.io_pads_gpio_1_o_oval (io_pads_gpio_1_o_oval),
.io_pads_gpio_1_o_oe (io_pads_gpio_1_o_oe),
.io_pads_gpio_1_o_ie (io_pads_gpio_1_o_ie),
.io_pads_gpio_1_o_pue (io_pads_gpio_1_o_pue),
.io_pads_gpio_1_o_ds (io_pads_gpio_1_o_ds),
.io_pads_gpio_2_i_ival (io_pads_gpio_2_i_ival & io_pads_gpio_2_o_ie),
.io_pads_gpio_2_o_oval (io_pads_gpio_2_o_oval),
.io_pads_gpio_2_o_oe (io_pads_gpio_2_o_oe),
.io_pads_gpio_2_o_ie (io_pads_gpio_2_o_ie),
.io_pads_gpio_2_o_pue (io_pads_gpio_2_o_pue),
.io_pads_gpio_2_o_ds (io_pads_gpio_2_o_ds),
.io_pads_gpio_3_i_ival (io_pads_gpio_3_i_ival & io_pads_gpio_3_o_ie),
.io_pads_gpio_3_o_oval (io_pads_gpio_3_o_oval),
.io_pads_gpio_3_o_oe (io_pads_gpio_3_o_oe),
.io_pads_gpio_3_o_ie (io_pads_gpio_3_o_ie),
.io_pads_gpio_3_o_pue (io_pads_gpio_3_o_pue),
.io_pads_gpio_3_o_ds (io_pads_gpio_3_o_ds),
.io_pads_gpio_4_i_ival (io_pads_gpio_4_i_ival & io_pads_gpio_4_o_ie),
.io_pads_gpio_4_o_oval (io_pads_gpio_4_o_oval),
.io_pads_gpio_4_o_oe (io_pads_gpio_4_o_oe),
.io_pads_gpio_4_o_ie (io_pads_gpio_4_o_ie),
.io_pads_gpio_4_o_pue (io_pads_gpio_4_o_pue),
.io_pads_gpio_4_o_ds (io_pads_gpio_4_o_ds),
.io_pads_gpio_5_i_ival (io_pads_gpio_5_i_ival & io_pads_gpio_5_o_ie),
.io_pads_gpio_5_o_oval (io_pads_gpio_5_o_oval),
.io_pads_gpio_5_o_oe (io_pads_gpio_5_o_oe),
.io_pads_gpio_5_o_ie (io_pads_gpio_5_o_ie),
.io_pads_gpio_5_o_pue (io_pads_gpio_5_o_pue),
.io_pads_gpio_5_o_ds (io_pads_gpio_5_o_ds),
.io_pads_gpio_6_i_ival (io_pads_gpio_6_i_ival & io_pads_gpio_6_o_ie),
.io_pads_gpio_6_o_oval (io_pads_gpio_6_o_oval),
.io_pads_gpio_6_o_oe (io_pads_gpio_6_o_oe),
.io_pads_gpio_6_o_ie (io_pads_gpio_6_o_ie),
.io_pads_gpio_6_o_pue (io_pads_gpio_6_o_pue),
.io_pads_gpio_6_o_ds (io_pads_gpio_6_o_ds),
.io_pads_gpio_7_i_ival (io_pads_gpio_7_i_ival & io_pads_gpio_7_o_ie),
.io_pads_gpio_7_o_oval (io_pads_gpio_7_o_oval),
.io_pads_gpio_7_o_oe (io_pads_gpio_7_o_oe),
.io_pads_gpio_7_o_ie (io_pads_gpio_7_o_ie),
.io_pads_gpio_7_o_pue (io_pads_gpio_7_o_pue),
.io_pads_gpio_7_o_ds (io_pads_gpio_7_o_ds),
.io_pads_gpio_8_i_ival (io_pads_gpio_8_i_ival & io_pads_gpio_8_o_ie),
.io_pads_gpio_8_o_oval (io_pads_gpio_8_o_oval),
.io_pads_gpio_8_o_oe (io_pads_gpio_8_o_oe),
.io_pads_gpio_8_o_ie (io_pads_gpio_8_o_ie),
.io_pads_gpio_8_o_pue (io_pads_gpio_8_o_pue),
.io_pads_gpio_8_o_ds (io_pads_gpio_8_o_ds),
.io_pads_gpio_9_i_ival (io_pads_gpio_9_i_ival & io_pads_gpio_9_o_ie),
.io_pads_gpio_9_o_oval (io_pads_gpio_9_o_oval),
.io_pads_gpio_9_o_oe (io_pads_gpio_9_o_oe),
.io_pads_gpio_9_o_ie (io_pads_gpio_9_o_ie),
.io_pads_gpio_9_o_pue (io_pads_gpio_9_o_pue),
.io_pads_gpio_9_o_ds (io_pads_gpio_9_o_ds),
.io_pads_gpio_10_i_ival (io_pads_gpio_10_i_ival & io_pads_gpio_10_o_ie),
.io_pads_gpio_10_o_oval (io_pads_gpio_10_o_oval),
.io_pads_gpio_10_o_oe (io_pads_gpio_10_o_oe),
.io_pads_gpio_10_o_ie (io_pads_gpio_10_o_ie),
.io_pads_gpio_10_o_pue (io_pads_gpio_10_o_pue),
.io_pads_gpio_10_o_ds (io_pads_gpio_10_o_ds),
.io_pads_gpio_11_i_ival (io_pads_gpio_11_i_ival & io_pads_gpio_11_o_ie),
.io_pads_gpio_11_o_oval (io_pads_gpio_11_o_oval),
.io_pads_gpio_11_o_oe (io_pads_gpio_11_o_oe),
.io_pads_gpio_11_o_ie (io_pads_gpio_11_o_ie),
.io_pads_gpio_11_o_pue (io_pads_gpio_11_o_pue),
.io_pads_gpio_11_o_ds (io_pads_gpio_11_o_ds),
.io_pads_gpio_12_i_ival (io_pads_gpio_12_i_ival & io_pads_gpio_12_o_ie),
.io_pads_gpio_12_o_oval (io_pads_gpio_12_o_oval),
.io_pads_gpio_12_o_oe (io_pads_gpio_12_o_oe),
.io_pads_gpio_12_o_ie (io_pads_gpio_12_o_ie),
.io_pads_gpio_12_o_pue (io_pads_gpio_12_o_pue),
.io_pads_gpio_12_o_ds (io_pads_gpio_12_o_ds),
.io_pads_gpio_13_i_ival (io_pads_gpio_13_i_ival & io_pads_gpio_13_o_ie),
.io_pads_gpio_13_o_oval (io_pads_gpio_13_o_oval),
.io_pads_gpio_13_o_oe (io_pads_gpio_13_o_oe),
.io_pads_gpio_13_o_ie (io_pads_gpio_13_o_ie),
.io_pads_gpio_13_o_pue (io_pads_gpio_13_o_pue),
.io_pads_gpio_13_o_ds (io_pads_gpio_13_o_ds),
.io_pads_gpio_14_i_ival (io_pads_gpio_14_i_ival & io_pads_gpio_14_o_ie),
.io_pads_gpio_14_o_oval (io_pads_gpio_14_o_oval),
.io_pads_gpio_14_o_oe (io_pads_gpio_14_o_oe),
.io_pads_gpio_14_o_ie (io_pads_gpio_14_o_ie),
.io_pads_gpio_14_o_pue (io_pads_gpio_14_o_pue),
.io_pads_gpio_14_o_ds (io_pads_gpio_14_o_ds),
.io_pads_gpio_15_i_ival (io_pads_gpio_15_i_ival & io_pads_gpio_15_o_ie),
.io_pads_gpio_15_o_oval (io_pads_gpio_15_o_oval),
.io_pads_gpio_15_o_oe (io_pads_gpio_15_o_oe),
.io_pads_gpio_15_o_ie (io_pads_gpio_15_o_ie),
.io_pads_gpio_15_o_pue (io_pads_gpio_15_o_pue),
.io_pads_gpio_15_o_ds (io_pads_gpio_15_o_ds),
.io_pads_gpio_16_i_ival (io_pads_gpio_16_i_ival & io_pads_gpio_16_o_ie),
.io_pads_gpio_16_o_oval (io_pads_gpio_16_o_oval),
.io_pads_gpio_16_o_oe (io_pads_gpio_16_o_oe),
.io_pads_gpio_16_o_ie (io_pads_gpio_16_o_ie),
.io_pads_gpio_16_o_pue (io_pads_gpio_16_o_pue),
.io_pads_gpio_16_o_ds (io_pads_gpio_16_o_ds),
.io_pads_gpio_17_i_ival (io_pads_gpio_17_i_ival & io_pads_gpio_17_o_ie),
.io_pads_gpio_17_o_oval (io_pads_gpio_17_o_oval),
.io_pads_gpio_17_o_oe (io_pads_gpio_17_o_oe),
.io_pads_gpio_17_o_ie (io_pads_gpio_17_o_ie),
.io_pads_gpio_17_o_pue (io_pads_gpio_17_o_pue),
.io_pads_gpio_17_o_ds (io_pads_gpio_17_o_ds),
.io_pads_gpio_18_i_ival (io_pads_gpio_18_i_ival & io_pads_gpio_18_o_ie),
.io_pads_gpio_18_o_oval (io_pads_gpio_18_o_oval),
.io_pads_gpio_18_o_oe (io_pads_gpio_18_o_oe),
.io_pads_gpio_18_o_ie (io_pads_gpio_18_o_ie),
.io_pads_gpio_18_o_pue (io_pads_gpio_18_o_pue),
.io_pads_gpio_18_o_ds (io_pads_gpio_18_o_ds),
.io_pads_gpio_19_i_ival (io_pads_gpio_19_i_ival & io_pads_gpio_19_o_ie),
.io_pads_gpio_19_o_oval (io_pads_gpio_19_o_oval),
.io_pads_gpio_19_o_oe (io_pads_gpio_19_o_oe),
.io_pads_gpio_19_o_ie (io_pads_gpio_19_o_ie),
.io_pads_gpio_19_o_pue (io_pads_gpio_19_o_pue),
.io_pads_gpio_19_o_ds (io_pads_gpio_19_o_ds),
.io_pads_gpio_20_i_ival (io_pads_gpio_20_i_ival & io_pads_gpio_20_o_ie),
.io_pads_gpio_20_o_oval (io_pads_gpio_20_o_oval),
.io_pads_gpio_20_o_oe (io_pads_gpio_20_o_oe),
.io_pads_gpio_20_o_ie (io_pads_gpio_20_o_ie),
.io_pads_gpio_20_o_pue (io_pads_gpio_20_o_pue),
.io_pads_gpio_20_o_ds (io_pads_gpio_20_o_ds),
.io_pads_gpio_21_i_ival (io_pads_gpio_21_i_ival & io_pads_gpio_21_o_ie),
.io_pads_gpio_21_o_oval (io_pads_gpio_21_o_oval),
.io_pads_gpio_21_o_oe (io_pads_gpio_21_o_oe),
.io_pads_gpio_21_o_ie (io_pads_gpio_21_o_ie),
.io_pads_gpio_21_o_pue (io_pads_gpio_21_o_pue),
.io_pads_gpio_21_o_ds (io_pads_gpio_21_o_ds),
.io_pads_gpio_22_i_ival (io_pads_gpio_22_i_ival & io_pads_gpio_22_o_ie),
.io_pads_gpio_22_o_oval (io_pads_gpio_22_o_oval),
.io_pads_gpio_22_o_oe (io_pads_gpio_22_o_oe),
.io_pads_gpio_22_o_ie (io_pads_gpio_22_o_ie),
.io_pads_gpio_22_o_pue (io_pads_gpio_22_o_pue),
.io_pads_gpio_22_o_ds (io_pads_gpio_22_o_ds),
.io_pads_gpio_23_i_ival (io_pads_gpio_23_i_ival & io_pads_gpio_23_o_ie),
.io_pads_gpio_23_o_oval (io_pads_gpio_23_o_oval),
.io_pads_gpio_23_o_oe (io_pads_gpio_23_o_oe),
.io_pads_gpio_23_o_ie (io_pads_gpio_23_o_ie),
.io_pads_gpio_23_o_pue (io_pads_gpio_23_o_pue),
.io_pads_gpio_23_o_ds (io_pads_gpio_23_o_ds),
.io_pads_gpio_24_i_ival (io_pads_gpio_24_i_ival & io_pads_gpio_24_o_ie),
.io_pads_gpio_24_o_oval (io_pads_gpio_24_o_oval),
.io_pads_gpio_24_o_oe (io_pads_gpio_24_o_oe),
.io_pads_gpio_24_o_ie (io_pads_gpio_24_o_ie),
.io_pads_gpio_24_o_pue (io_pads_gpio_24_o_pue),
.io_pads_gpio_24_o_ds (io_pads_gpio_24_o_ds),
.io_pads_gpio_25_i_ival (io_pads_gpio_25_i_ival & io_pads_gpio_25_o_ie),
.io_pads_gpio_25_o_oval (io_pads_gpio_25_o_oval),
.io_pads_gpio_25_o_oe (io_pads_gpio_25_o_oe),
.io_pads_gpio_25_o_ie (io_pads_gpio_25_o_ie),
.io_pads_gpio_25_o_pue (io_pads_gpio_25_o_pue),
.io_pads_gpio_25_o_ds (io_pads_gpio_25_o_ds),
.io_pads_gpio_26_i_ival (io_pads_gpio_26_i_ival & io_pads_gpio_26_o_ie),
.io_pads_gpio_26_o_oval (io_pads_gpio_26_o_oval),
.io_pads_gpio_26_o_oe (io_pads_gpio_26_o_oe),
.io_pads_gpio_26_o_ie (io_pads_gpio_26_o_ie),
.io_pads_gpio_26_o_pue (io_pads_gpio_26_o_pue),
.io_pads_gpio_26_o_ds (io_pads_gpio_26_o_ds),
.io_pads_gpio_27_i_ival (io_pads_gpio_27_i_ival & io_pads_gpio_27_o_ie),
.io_pads_gpio_27_o_oval (io_pads_gpio_27_o_oval),
.io_pads_gpio_27_o_oe (io_pads_gpio_27_o_oe),
.io_pads_gpio_27_o_ie (io_pads_gpio_27_o_ie),
.io_pads_gpio_27_o_pue (io_pads_gpio_27_o_pue),
.io_pads_gpio_27_o_ds (io_pads_gpio_27_o_ds),
.io_pads_gpio_28_i_ival (io_pads_gpio_28_i_ival & io_pads_gpio_28_o_ie),
.io_pads_gpio_28_o_oval (io_pads_gpio_28_o_oval),
.io_pads_gpio_28_o_oe (io_pads_gpio_28_o_oe),
.io_pads_gpio_28_o_ie (io_pads_gpio_28_o_ie),
.io_pads_gpio_28_o_pue (io_pads_gpio_28_o_pue),
.io_pads_gpio_28_o_ds (io_pads_gpio_28_o_ds),
.io_pads_gpio_29_i_ival (io_pads_gpio_29_i_ival & io_pads_gpio_29_o_ie),
.io_pads_gpio_29_o_oval (io_pads_gpio_29_o_oval),
.io_pads_gpio_29_o_oe (io_pads_gpio_29_o_oe),
.io_pads_gpio_29_o_ie (io_pads_gpio_29_o_ie),
.io_pads_gpio_29_o_pue (io_pads_gpio_29_o_pue),
.io_pads_gpio_29_o_ds (io_pads_gpio_29_o_ds),
.io_pads_gpio_30_i_ival (io_pads_gpio_30_i_ival & io_pads_gpio_30_o_ie),
.io_pads_gpio_30_o_oval (io_pads_gpio_30_o_oval),
.io_pads_gpio_30_o_oe (io_pads_gpio_30_o_oe),
.io_pads_gpio_30_o_ie (io_pads_gpio_30_o_ie),
.io_pads_gpio_30_o_pue (io_pads_gpio_30_o_pue),
.io_pads_gpio_30_o_ds (io_pads_gpio_30_o_ds),
.io_pads_gpio_31_i_ival (io_pads_gpio_31_i_ival & io_pads_gpio_31_o_ie),
.io_pads_gpio_31_o_oval (io_pads_gpio_31_o_oval),
.io_pads_gpio_31_o_oe (io_pads_gpio_31_o_oe),
.io_pads_gpio_31_o_ie (io_pads_gpio_31_o_ie),
.io_pads_gpio_31_o_pue (io_pads_gpio_31_o_pue),
.io_pads_gpio_31_o_ds (io_pads_gpio_31_o_ds),
.io_pads_qspi_sck_i_ival (1'b1 ),
.io_pads_qspi_sck_o_oval (io_pads_qspi_sck_o_oval ),
.io_pads_qspi_sck_o_oe (),
.io_pads_qspi_sck_o_ie (),
.io_pads_qspi_sck_o_pue (),
.io_pads_qspi_sck_o_ds (),
.io_pads_qspi_dq_0_i_ival (io_pads_qspi_dq_0_i_ival & io_pads_qspi_dq_0_o_ie),
.io_pads_qspi_dq_0_o_oval (io_pads_qspi_dq_0_o_oval),
.io_pads_qspi_dq_0_o_oe (io_pads_qspi_dq_0_o_oe ),
.io_pads_qspi_dq_0_o_ie (io_pads_qspi_dq_0_o_ie ),
.io_pads_qspi_dq_0_o_pue (io_pads_qspi_dq_0_o_pue ),
.io_pads_qspi_dq_0_o_ds (io_pads_qspi_dq_0_o_ds ),
.io_pads_qspi_dq_1_i_ival (io_pads_qspi_dq_1_i_ival & io_pads_qspi_dq_1_o_ie),
.io_pads_qspi_dq_1_o_oval (io_pads_qspi_dq_1_o_oval),
.io_pads_qspi_dq_1_o_oe (io_pads_qspi_dq_1_o_oe ),
.io_pads_qspi_dq_1_o_ie (io_pads_qspi_dq_1_o_ie ),
.io_pads_qspi_dq_1_o_pue (io_pads_qspi_dq_1_o_pue ),
.io_pads_qspi_dq_1_o_ds (io_pads_qspi_dq_1_o_ds ),
.io_pads_qspi_dq_2_i_ival (io_pads_qspi_dq_2_i_ival & io_pads_qspi_dq_2_o_ie),
.io_pads_qspi_dq_2_o_oval (io_pads_qspi_dq_2_o_oval),
.io_pads_qspi_dq_2_o_oe (io_pads_qspi_dq_2_o_oe ),
.io_pads_qspi_dq_2_o_ie (io_pads_qspi_dq_2_o_ie ),
.io_pads_qspi_dq_2_o_pue (io_pads_qspi_dq_2_o_pue ),
.io_pads_qspi_dq_2_o_ds (io_pads_qspi_dq_2_o_ds ),
.io_pads_qspi_dq_3_i_ival (io_pads_qspi_dq_3_i_ival & io_pads_qspi_dq_3_o_ie),
.io_pads_qspi_dq_3_o_oval (io_pads_qspi_dq_3_o_oval),
.io_pads_qspi_dq_3_o_oe (io_pads_qspi_dq_3_o_oe ),
.io_pads_qspi_dq_3_o_ie (io_pads_qspi_dq_3_o_ie ),
.io_pads_qspi_dq_3_o_pue (io_pads_qspi_dq_3_o_pue ),
.io_pads_qspi_dq_3_o_ds (io_pads_qspi_dq_3_o_ds ),
.io_pads_qspi_cs_0_i_ival (1'b1),
.io_pads_qspi_cs_0_o_oval (io_pads_qspi_cs_0_o_oval),
.io_pads_qspi_cs_0_o_oe (),
.io_pads_qspi_cs_0_o_ie (),
.io_pads_qspi_cs_0_o_pue (),
.io_pads_qspi_cs_0_o_ds (),
.hfextclk (hfextclk),
.hfxoscen (hfxoscen),
.lfextclk (lfextclk),
.lfxoscen (lfxoscen),
.io_pads_aon_erst_n_i_ival (io_pads_aon_erst_n_i_ival ),
.io_pads_aon_erst_n_o_oval (),
.io_pads_aon_erst_n_o_oe (),
.io_pads_aon_erst_n_o_ie (),
.io_pads_aon_erst_n_o_pue (),
.io_pads_aon_erst_n_o_ds (),
.io_pads_aon_pmu_dwakeup_n_i_ival (io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_aon_pmu_dwakeup_n_o_oval (),
.io_pads_aon_pmu_dwakeup_n_o_oe (),
.io_pads_aon_pmu_dwakeup_n_o_ie (),
.io_pads_aon_pmu_dwakeup_n_o_pue (),
.io_pads_aon_pmu_dwakeup_n_o_ds (),
.io_pads_aon_pmu_vddpaden_i_ival (1'b1 ),
.io_pads_aon_pmu_vddpaden_o_oval (io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_aon_pmu_vddpaden_o_oe (),
.io_pads_aon_pmu_vddpaden_o_ie (),
.io_pads_aon_pmu_vddpaden_o_pue (),
.io_pads_aon_pmu_vddpaden_o_ds (),
.io_pads_aon_pmu_padrst_i_ival (1'b1 ),
.io_pads_aon_pmu_padrst_o_oval (io_pads_aon_pmu_padrst_o_oval ),
.io_pads_aon_pmu_padrst_o_oe (),
.io_pads_aon_pmu_padrst_o_ie (),
.io_pads_aon_pmu_padrst_o_pue (),
.io_pads_aon_pmu_padrst_o_ds (),
.io_pads_bootrom_n_i_ival (io_pads_bootrom_n_i_ival),
.io_pads_bootrom_n_o_oval (),
.io_pads_bootrom_n_o_oe (),
.io_pads_bootrom_n_o_ie (),
.io_pads_bootrom_n_o_pue (),
.io_pads_bootrom_n_o_ds (),
.io_pads_dbgmode0_n_i_ival (io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (io_pads_dbgmode2_n_i_ival)
);
endmodule
|
module ii2dcam
#( parameter CDEP = `CDEP , // CAM depth (k-entries, power of 2)
parameter PWID = `PWID , // pattern width (9-bits multiply)
parameter PIPE = `PIPE , // pipelined?
parameter REGI = `REGI , // register inputs?
parameter REGO = `REGO ) // register outputs?
( input clk , // clock
input rst , // global reset
input wEnb , // write enable
input [`log2(CDEP)+9:0] wAddr , // write address
input [PWID*9-1:0] mPatt , // match pattern
input [PWID*9-1:0] wPatt , // write pattern
output match , // match
output [`log2(CDEP)+9:0] mAddr ); // match indicators
// register inputs
reg wEnbR ;
reg [`log2(CDEP)+9:0] wAddrR;
reg [PWID*9-1:0] mPattR;
reg [PWID*9-1:0] wPattR;
wire wEnbI ;
wire [`log2(CDEP)+9:0] wAddrI;
wire [PWID*9-1:0] mPattI;
wire [PWID*9-1:0] wPattI;
always @(posedge clk, posedge rst)
if (rst) {wEnbR,wAddrR,mPattR,wPattR} <= {(`log2(CDEP)+18*PWID+11){1'b0}};
else {wEnbR,wAddrR,mPattR,wPattR} <=
{wEnb ,wAddr ,mPatt ,wPatt } ;
assign {wEnbI,wAddrI,mPattI,wPattI} = REGI ?
{wEnbR,wAddrR,mPattR,wPattR} :
{wEnb ,wAddr ,mPatt ,wPatt } ;
// register outputs
reg matchR;
reg [`log2(CDEP)+9:0] mAddrR;
wire matchI;
wire [`log2(CDEP)+9:0] mAddrI;
always @(posedge clk, posedge rst)
if (rst) {matchR,mAddrR} <= {(`log2(CDEP)+11){1'b0}};
else {matchR,mAddrR} <=
{matchI,mAddrI} ;
assign {match ,mAddr } = REGO ?
{matchR,mAddrR} :
{matchI,mAddrI} ;
// instantiate slices of ii2dcam9b for each 9-bits of pattern
wire [CDEP*1024-1:0] mIndc_i [PWID-1:0];
genvar gi;
generate
for (gi=0 ; gi<PWID ; gi=gi+1) begin: STG
// instantiate ii2dcam9b
ii2dcam9b #( .CDEP (CDEP ), // depth (k-entries)
.PIPE (PIPE )) // pipelined?
ii2dcam9bi ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb (wEnbI ), // write enable // input
.wAddr(wAddrI ), // write address // input [`log2(DEP)+9:0]
.mPatt(mPattI[gi*9 +: 9]), // match pattern // input [8 :0]
.wPatt(wPattI[gi*9 +: 9]), // write pattern // input [8 :0]
.mIndc(mIndc_i[gi] )); // match indicators // output [DEP*1024-1:0]
end
endgenerate
// cascading by AND'ing matches
integer i;
reg [CDEP*1024-1:0] mIndc; // match one-hot
always @(*) begin
mIndc = {(CDEP*1024){1'b1}};
for (i=0; i<PWID; i=i+1)
mIndc = mIndc & mIndc_i[i];
end
// binary match (priority encoded) with CDEPx1k width
`ifdef SIM
pe_bhv #( .OHW(CDEP*1024) ) // behavioural priority encoder
`else
pe_cam // generated automatically by ./pe script
`endif
pe_cam_inst (
.clk(clk ), // clock for pipelined priority encoder
.rst(rst ), // registers reset for pipelined priority encoder
.oht(mIndc ), // one-hot match input / in : [ CDEP -1:0]
.bin(mAddrI), // first match index / out: [`log2(CDEP)-1:0]
.vld(matchI) // match indicator / out
);
endmodule
|
module Clk_Wizard
(
// Clock out ports
output VGA_clock,
output Main_clock,
// Status and control signals
input resetn,
output locked,
// Clock in ports
input Clock_Board
);
Clk_Wizard_clk_wiz inst
(
// Clock out ports
.VGA_clock(VGA_clock),
.Main_clock(Main_clock),
// Status and control signals
.resetn(resetn),
.locked(locked),
// Clock in ports
.Clock_Board(Clock_Board)
);
endmodule
|
module fifo
#(
parameter adr_width = 4,
parameter dat_width = 8
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
reg [1:0] orden;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(posedge clk)
begin
if(wr&&!rd)
begin
orden = 2'b01;
end
if(!wr&&rd)
begin
orden = 2'b10;
end
if(wr&&rd)
begin
orden = 2'b11;
end
end
//always @(posedge reset or posedge wr or posedge rd)
always @(posedge clk)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case (orden)
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule
|
module or DMA consumes DWORD
// communication with link/phys layers
output [ 1:0] phy_speed, // 0 - not ready, 1..3 - negotiated speed (Now 0/2)
output gtx_ready, // How to use it?
output xmit_ok, // received R_OK after transmission
output xmit_err, // Error during/after sending of a FIS (got R_ERR)
output x_rdy_collision, // X_RDY/X_RDY collision on interface
output syncesc_recv, // Where to get it?
input pcmd_st_cleared, // PxCMD.ST 1->0 transition by software
input syncesc_send, // Send sync escape
output syncesc_send_done, // "SYNC escape until the interface is quiescent..."
input comreset_send, // Not possible yet?
output cominit_got,
input set_offline, // electrically idle
input send_R_OK, // Should it be originated in this layer SM?
input send_R_ERR,
// additional errors from SATA layers (single-clock pulses):
output serr_DT, // RWC: Transport state transition error
output serr_DS, // RWC: Link sequence error
output serr_DH, // RWC: Handshake Error (i.e. Device got CRC error)
output serr_DC, // RWC: CRC error in Link layer
output serr_DB, // RWC: 10B to 8B decode error
output serr_DW, // RWC: COMMWAKE signal was detected
output serr_DI, // RWC: PHY Internal Error
// sirq_PRC,
output serr_EE, // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
output serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
output serr_EC, // RWC: Persistent Communication or Data Integrity Error
output serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
output serr_EM, // RWC: Communication between the device and host was lost but re-established
output serr_EI, // RWC: Recovered Data integrity Error
// additional control signals for SATA layers
input [3:0] sctl_ipm, // Interface power management transitions allowed // @SuppressThisWarning Veditor Unused (yet)
input [3:0] sctl_spd, // Interface maximal speed // @SuppressThisWarning Veditor Unused (yet)
// Device high speed pads and clock inputs
// ref clk from an external source, shall be connected to pads
input wire extclk_p,
input wire extclk_n,
// sata link data pins
output wire txp_out,
output wire txn_out,
input wire rxp_in,
input wire rxn_in,
output debug_is_data, // @clk (sata clk) - last symbol was data output
output debug_dmatp, // @clk (sata clk) - received CODE_DMATP
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
output datascope_clk,
output [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we,
output [31:0] datascope_di,
`endif
`ifdef USE_DRP
input drp_rst,
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [14:0] drp_addr,
input [15:0] drp_di,
output drp_rdy,
output [15:0] drp_do ,
`endif
output [FREQ_METER_WIDTH - 1:0] xclk_period, // relative (to 2*clk) xclk period
output [31:0] debug_phy,
output [31:0] debug_link,
input hclk // just for testing
);
localparam PHY_SPEED = 2; // SATA2
localparam FIFO_ADDR_WIDTH = 9;
localparam D2H_TYPE_DMA = 0;
localparam D2H_TYPE_FIS_HEAD = 1;
localparam D2H_TYPE_OK = 2;
localparam D2H_TYPE_ERR = 3;
localparam H2D_TYPE_FIS_DATA = 0; // @SuppressThisWarning VEditor unused
localparam H2D_TYPE_FIS_HEAD = 1;
localparam H2D_TYPE_FIS_LAST = 2;
`ifdef SIMULATION
`ifdef CHECK_LOW_H2D_FIFO
localparam H2D_FIFO_THRESHOLD = 4; // to test h2d_ready - will turn off frequently, much earlier than fifo almost full
`endif
`endif
wire phy_ready; // active when GTX gets aligned output
wire link_established; // Received 3 back-to-back non-ALIGNp
wire [31:0] ll_h2d_data_in;
wire [1:0] ll_h2d_mask_in;
wire ll_strobe_out;
wire ll_h2d_last;
wire [1:0] h2d_type_out;
wire [31:0] ll_d2h_data_out;
wire [ 1:0] ll_d2h_mask_out;
wire ll_d2h_valid;
wire ll_d2h_almost_full;
reg [1:0] d2h_type_in;
reg fis_over_r; // push 1 more DWORD (ignore) + type (ERR/OK) when received FIS is done/error
reg ll_frame_req; // -> link // request for a new frame transition
wire ll_frame_ackn; // acknowledge for ll_frame_req
wire ll_incom_start; // link -> // if started an incoming transaction assuming this and next 2 are single-cycle
wire ll_incom_done; // link -> // if incoming transition was completed
wire ll_incom_invalidate; // link -> // if incoming transition had errors
reg ll_incom_invalidate_r; // error delayed by 1 clock - if eof was incorrect (because of earlier data error)
// let last data dword to pass through
wire ll_link_reset = ~phy_ready; // -> link // oob sequence is reinitiated and link now is not established or rxelecidle //TODO Alexey:mb it shall be independent
wire [DATA_BYTE_WIDTH*8 - 1:0] ph2ll_data_out;
wire [DATA_BYTE_WIDTH - 1:0] ph2ll_charisk_out; // charisk
wire [DATA_BYTE_WIDTH - 1:0] ph2ll_err_out; // disperr | notintable
wire [DATA_BYTE_WIDTH*8 - 1:0] ll2ph_data_in;
wire [DATA_BYTE_WIDTH - 1:0] ll2ph_charisk_in; // charisk
wire [FIFO_ADDR_WIDTH-1:0] h2d_raddr;
wire [1:0] h2d_fifo_re_regen;
wire [FIFO_ADDR_WIDTH-1:0] h2d_waddr;
wire [FIFO_ADDR_WIDTH:0] h2d_fill;
wire h2d_nempty;
wire [FIFO_ADDR_WIDTH-1:0] d2h_raddr;
wire [1:0] d2h_fifo_re_regen;
wire [FIFO_ADDR_WIDTH-1:0] d2h_waddr;
wire [FIFO_ADDR_WIDTH:0] d2h_fill;
wire d2h_nempty;
wire h2d_fifo_rd = h2d_nempty && ll_strobe_out; // TODO: check latency in link.v
// wire h2d_fifo_wr = h2d_valid;
//2016.12.10
wire h2d_fifo_wr = h2d_valid && h2d_ready; // or should valid depend on ready in the fis_transmit?
wire d2h_fifo_rd = d2h_valid && d2h_ready;
wire d2h_fifo_wr = ll_d2h_valid || fis_over_r; // fis_over_r will push FIS end to FIFO
reg h2d_pending; // HBA started sending FIS to fifo
wire rxelsfull;
wire rxelsempty;
wire xclk; // output receive clock, just to measure frequency
wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer
wire [31:0] debug_phy0;
`ifdef USE_DATASCOPE
wire [31:0] datascope0_di;
`endif
assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);
assign d2h_valid = d2h_nempty;
assign d2h_many = |d2h_fill[FIFO_ADDR_WIDTH:3]; //
// assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH:3]);
// 2016:12:10 sometimes overflow happened because of a BUG
`ifdef SIMULATION
`ifdef CHECK_LOW_H2D_FIFO
assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && (h2d_fill < ((1 << BITS_TO_START_XMIT) + H2D_FIFO_THRESHOLD ));
`else
assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH-1:3]); // same as with synthesis
`endif
`else
assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH-1:3]);
`endif
assign ll_d2h_almost_full = d2h_fill[FIFO_ADDR_WIDTH] || &d2h_fill[FIFO_ADDR_WIDTH-1:6]; // 63 dwords (maybe use :5?) - time to tell device to stop
// assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));
// Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits
//assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP];
// assign phy_speed = phy_ready ? PHY_SPEED:0;
// assign serr_DB = phy_ready && (|ph2ll_err_out);
// assign serr_DH = phy_ready && (xmit_err);
assign phy_speed = link_established ? PHY_SPEED:0;
assign serr_DB = link_established && (|ph2ll_err_out);
assign serr_DH = link_established && (xmit_err);
//
// not yet assigned errors
/// assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error
/// assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error
/// assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer
assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
// assign serr_DS = phy_ready && (0); // RWC: Link sequence error
// assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_EE = phy_ready && (rxelsfull || rxelsempty);
assign serr_DI = phy_ready && (0); // rxelsfull); // RWC: PHY Internal Error // just debugging
assign serr_EP = phy_ready && (0); // rxelsempty); // RWC: Protocol Error - a violation of SATA protocol detected // just debugging
assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error
assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface)
assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established
assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error
reg [1:0] debug_last_d2h_type_in;
reg [1:0] debug_last_d2h_type;
always @ (posedge clk) begin
if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in;
if (d2h_fifo_rd) debug_last_d2h_type<= d2h_type;
end
assign debug_phy = debug_phy0;
`ifdef USE_DATASCOPE
`ifdef DATASCOPE_INCOMING_RAW
assign datascope_di = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx
`else
// Mix transmitted alignes pair, but only to the closest group of 6 primitives
reg dbg_was_link5; // alignes pair sent
wire dbg_was_link5_xclk; // alignes pair sent
always @ (posedge datascope_clk) begin
if (dbg_was_link5_xclk) dbg_was_link5 <= 1;
else if (datascope_we) dbg_was_link5 <= 0;
end
pulse_cross_clock #(
.EXTRA_DLY(0)
) dbg_was_link5_i (
.rst (rst), // input
.src_clk (clk), // input
.dst_clk (datascope_clk), // input
.in_pulse (debug_link[5]), // input// is actually a two-cycle
.out_pulse (dbg_was_link5_xclk), // output
.busy() // output
);
assign datascope_di = {dbg_was_link5,datascope0_di[30:0]};// aligns_pair tx
`endif
`endif
link #(
.DATA_BYTE_WIDTH(4)
) link (
.rst (rst), // input wire
.clk (clk), // input wire
// data inputs from transport layer
.data_in (ll_h2d_data_in), // input[31:0] wire // input data stream (if any data during OOB setting => ignored)
// TODO, for now not supported, all mask bits are assumed to be set
.data_mask_in (ll_h2d_mask_in), // input[1:0] wire
.data_strobe_out (ll_strobe_out), // output wire // buffer read strobe
.data_last_in (ll_h2d_last), // input wire // transaction's last data budle pulse
.data_val_in (h2d_nempty), // input wire // read data is valid (if 0 while last pulse wasn't received => need to hold the line)
.data_out (ll_d2h_data_out), // output[31:0] wire // read data, same as related inputs
.data_mask_out (ll_d2h_mask_out), // output[1:0] wire // same thing - all 1s for now. TODO
.data_val_out (ll_d2h_valid), // output wire // count every data bundle read by transport layer, even if busy flag is set // let the transport layer handle oveflows by himself
.data_busy_in (ll_d2h_almost_full), // input wire // transport layer tells if its inner buffer is almost full
.data_last_out (), // ll_d2h_last), // output wire not used
.frame_req (ll_frame_req), // input wire // request for a new frame transmission
.frame_busy (), // ll_frame_busy), // output wire // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now
.frame_ack (ll_frame_ackn), // ll_frame_ack), // output wire // LL tells if the request is transmitting
.frame_rej (x_rdy_collision), // output wire // or if it was cancelled because of simultanious incoming transmission
.frame_done_good (xmit_ok), // output wire // TL tell if the outcoming transaction is done and how it was done
.frame_done_bad (xmit_err), // output wire
.incom_start (ll_incom_start), // output wire // if started an incoming transaction
.incom_done (ll_incom_done), // output wire // if incoming transition was completed
.incom_invalidate (ll_incom_invalidate), // output wire // if incoming transition had errors
.incom_sync_escape(syncesc_recv), // output wire - received sync escape
.incom_ack_good (send_R_OK), // input wire // transport layer responds on a completion of a FIS
.incom_ack_bad (send_R_ERR), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
.link_reset (ll_link_reset), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current receiving session
.link_established (link_established), // output wire
.link_bad_crc (serr_DC), // output wire // Bad CRC at EOF
// inputs from phy
.phy_ready (phy_ready), // input wire // phy is ready - link is established
// data-primitives stream from phy
.phy_data_in (ph2ll_data_out), // input[31:0] wire // phy_data_in
.phy_isk_in (ph2ll_charisk_out), // input[3:0] wire // charisk
.phy_err_in (ph2ll_err_out), // input[3:0] wire // disperr | notintable
// to phy
.phy_data_out (ll2ph_data_in), // output[31:0] wire
.phy_isk_out (ll2ph_charisk_in), // output[3:0] wire // charisk
.debug_is_data (debug_is_data), // output reg @clk (sata clk) - last symbol was data output
.debug_dmatp (debug_dmatp), // output reg @clk (sata clk) - received CODE_DMATP
.debug_out (debug_link)
);
always @ (posedge clk) begin
ll_incom_invalidate_r <= ll_incom_invalidate;
// FIS receive D2H
// add head if ll_d2h_valid and (d2h_type_in == D2H_TYPE_OK) || (d2h_type_in == D2H_TYPE_ERR)? Or signal some internal error
if (rst || ll_incom_start) d2h_type_in <= D2H_TYPE_FIS_HEAD; // FIS head
else if (ll_d2h_valid) d2h_type_in <= D2H_TYPE_DMA; // FIS BODY
else if (ll_incom_done || ll_incom_invalidate_r) d2h_type_in <= ll_incom_invalidate_r ? D2H_TYPE_ERR: D2H_TYPE_OK;
if (rst) fis_over_r <= 0;
else fis_over_r <= (ll_incom_done || ll_incom_invalidate_r) && (d2h_type_in == D2H_TYPE_DMA); // make sure it is only once
// Second - generate internal error?
// FIS transmit H2D
// Start if all FIS is in FIFO (last word received) or at least that many is in FIFO
if (rst || ll_frame_req) h2d_pending <= 0; // ?
else if ((h2d_type == H2D_TYPE_FIS_HEAD) && h2d_fifo_wr) h2d_pending <= 1;
if (rst) ll_frame_req <= 0;
// else ll_frame_req <= ll_frame_req_w;
else if (h2d_pending &&
(((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) ||
(|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]))) ll_frame_req <= 1;
else if (ll_frame_ackn) ll_frame_req <= 0;
end
sata_phy #(
`ifdef USE_DATASCOPE
.ADDRESS_BITS (ADDRESS_BITS), // for datascope
.DATASCOPE_START_BIT (DATASCOPE_START_BIT),
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS),
`endif
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.ELASTIC_DEPTH (ELASTIC_DEPTH),
.ELASTIC_OFFSET (ELASTIC_OFFSET)
) phy (
.extrst (exrst), // input wire
.clk (clk), // output wire
.rst (rst), // output wire
.reliable_clk (reliable_clk), // input wire
.phy_ready (phy_ready), // output wire
.gtx_ready (gtx_ready), // output wire
.debug_cnt (), // output[11:0] wire
.extclk_p (extclk_p), // input wire
.extclk_n (extclk_n), // input wire
.txp_out (txp_out), // output wire
.txn_out (txn_out), // output wire
.rxp_in (rxp_in), // input wire
.rxn_in (rxn_in), // input wire
.ll_data_out (ph2ll_data_out), // output[31:0] wire
.ll_charisk_out (ph2ll_charisk_out), // output[3:0] wire
.ll_err_out (ph2ll_err_out), // output[3:0] wire
.ll_data_in (ll2ph_data_in), // input[31:0] wire
.ll_charisk_in (ll2ph_charisk_in), // input[3:0] wire
.set_offline (set_offline), // input
.comreset_send (comreset_send), // input
.cominit_got (cominit_got), // output wire
.comwake_got (serr_DW), // output wire
.rxelsfull (rxelsfull), // output wire
.rxelsempty (rxelsempty), // output wire
.cplllock_debug (),
.usrpll_locked_debug (),
.re_aligned (serr_DS), // output reg
.xclk (xclk), // output receive clock, just to measure frequency
`ifdef USE_DATASCOPE
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope0_di), // output[31:0]
.datascope_trig (ll_incom_invalidate ), // ll_frame_ackn), // input datascope external trigger
// .datascope_trig (debug_link[4:0] == 'h0a), // state_send_eof // input datascope external trigger
/// .datascope_trig (debug_link[4:0] == 'h02), // state_rcvr_goodcrc // input datascope external trigger
//debug_link
`endif
`ifdef USE_DRP
.drp_rst (drp_rst), // input
.drp_clk (drp_clk), // input
.drp_en (drp_en), // input
.drp_we (drp_we), // input
.drp_addr (drp_addr), // input[14:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy), // output
.drp_do (drp_do), // output[15:0]
`endif
.debug_sata (debug_phy0)
,.debug_detected_alignp(debug_detected_alignp)
);
fifo_sameclock_control #(
.WIDTH(9)
) fifo_h2d_control_i (
.clk (clk), // input
.rst (rst || pcmd_st_cleared), // input
.wr (h2d_fifo_wr), // input
.rd (h2d_fifo_rd), // input
.nempty (h2d_nempty), // output
.fill_in (h2d_fill), // output[9:0]
.mem_wa (h2d_waddr), // output[8:0] reg
.mem_ra (h2d_raddr), // output[8:0] reg
.mem_re (h2d_fifo_re_regen[0]), // output
.mem_regen(h2d_fifo_re_regen[1]), // output
.over (), // output reg
.under () //h2d_under) // output reg
);
ram18p_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (5),
.LOG2WIDTH_RD (5)
) fifo_h2d_i (
.rclk (clk), // input
.raddr (h2d_raddr), // input[8:0]
.ren (h2d_fifo_re_regen[0]), // input
.regen (h2d_fifo_re_regen[1]), // input
.data_out ({h2d_type_out, ll_h2d_mask_in, ll_h2d_data_in}), // output[35:0]
.wclk (clk), // input
.waddr (h2d_waddr), // input[8:0]
.we (h2d_fifo_wr), // input
.web (4'hf), // input[3:0]
.data_in ({h2d_type,h2d_mask,h2d_data}) // input[35:0]
);
fifo_sameclock_control #(
.WIDTH(9)
) fifo_d2h_control_i (
.clk (clk), // input
.rst (rst || pcmd_st_cleared), // input
.wr (d2h_fifo_wr), // input
.rd (d2h_fifo_rd), // input
.nempty (d2h_nempty), // output
.fill_in (d2h_fill), // output[9:0]
.mem_wa (d2h_waddr), // output[8:0] reg
.mem_ra (d2h_raddr), // output[8:0] reg
.mem_re (d2h_fifo_re_regen[0]), // output
.mem_regen(d2h_fifo_re_regen[1]), // output
.over (), //d2h_over), // output reg
.under () // output reg
);
ram18p_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (5),
.LOG2WIDTH_RD (5)
) fifo_d2h_i (
.rclk (clk), // input
.raddr (d2h_raddr), // input[8:0]
.ren (d2h_fifo_re_regen[0]), // input
.regen (d2h_fifo_re_regen[1]), // input
.data_out ({d2h_type, d2h_mask, d2h_data}), // output[35:0]
.wclk (clk), // input
.waddr (d2h_waddr), // input[8:0]
.we (d2h_fifo_wr), // input
.web (4'hf), // input[3:0]
.data_in ({d2h_type_in, ll_d2h_mask_out, ll_d2h_data_out}) // input[35:0]
);
freq_meter #(
.WIDTH (FREQ_METER_WIDTH),
.PRESCALE (1)
) freq_meter_i (
.rst (rst), // input
.clk (clk), // input
.xclk (xclk), // hclk), //xclk), // input
.dout (xclk_period) // output[11:0] reg
);
endmodule
|
module omsp_dbg_uart (
// OUTPUTs
dbg_addr, // Debug register address
dbg_din, // Debug register data input
dbg_rd, // Debug register data read
dbg_uart_txd, // Debug interface: UART TXD
dbg_wr, // Debug register data write
// INPUTs
dbg_dout, // Debug register data output
dbg_rd_rdy, // Debug register data is ready for read
dbg_uart_rxd, // Debug interface: UART RXD
mclk, // Main system clock
mem_burst, // Burst on going
mem_burst_end, // End TX/RX burst
mem_burst_rd, // Start TX burst
mem_burst_wr, // Start RX burst
mem_bw, // Burst byte width
por // Power on reset
);
// OUTPUTs
//=========
output [5:0] dbg_addr; // Debug register address
output [15:0] dbg_din; // Debug register data input
output dbg_rd; // Debug register data read
output dbg_uart_txd; // Debug interface: UART TXD
output dbg_wr; // Debug register data write
// INPUTs
//=========
input [15:0] dbg_dout; // Debug register data output
input dbg_rd_rdy; // Debug register data is ready for read
input dbg_uart_rxd; // Debug interface: UART RXD
input mclk; // Main system clock
input mem_burst; // Burst on going
input mem_burst_end; // End TX/RX burst
input mem_burst_rd; // Start TX burst
input mem_burst_wr; // Start RX burst
input mem_bw; // Burst byte width
input por; // Power on reset
//=============================================================================
// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
//=============================================================================
// Synchronize RXD input & buffer
//--------------------------------
reg [3:0] rxd_sync;
always @ (posedge mclk or posedge por)
if (por) rxd_sync <= 4'h0;
else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
// Majority decision
//------------------------
reg rxd_maj;
wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} +
{1'b0, rxd_sync[2]} +
{1'b0, rxd_sync[3]};
wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
always @ (posedge mclk or posedge por)
if (por) rxd_maj <= 1'b0;
else rxd_maj <= rxd_maj_nxt;
wire rxd_s = rxd_maj;
wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
wire rxd_re = ~rxd_maj & rxd_maj_nxt;
//=============================================================================
// 2) UART STATE MACHINE
//=============================================================================
// Receive state
//------------------------
reg [2:0] uart_state;
reg [2:0] uart_state_nxt;
wire sync_done;
wire xfer_done;
reg [19:0] xfer_buf;
// State machine definition
parameter RX_SYNC = 3'h0;
parameter RX_CMD = 3'h1;
parameter RX_DATA1 = 3'h2;
parameter RX_DATA2 = 3'h3;
parameter TX_DATA1 = 3'h4;
parameter TX_DATA2 = 3'h5;
// State transition
always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
case (uart_state)
RX_SYNC : uart_state_nxt = RX_CMD;
RX_CMD : uart_state_nxt = mem_burst_wr ?
(mem_bw ? RX_DATA2 : RX_DATA1) :
mem_burst_rd ?
(mem_bw ? TX_DATA2 : TX_DATA1) :
(xfer_buf[`DBG_UART_WR] ?
(xfer_buf[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) :
(xfer_buf[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1));
RX_DATA1 : uart_state_nxt = RX_DATA2;
RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
(mem_bw ? RX_DATA2 : RX_DATA1) :
RX_CMD;
TX_DATA1 : uart_state_nxt = TX_DATA2;
TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
(mem_bw ? TX_DATA2 : TX_DATA1) :
RX_CMD;
default : uart_state_nxt = RX_CMD;
endcase
// State machine
always @(posedge mclk or posedge por)
if (por) uart_state <= RX_SYNC;
else if (xfer_done | sync_done |
mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
// Utility signals
wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
//=============================================================================
// 3) UART SYNCHRONIZATION
//=============================================================================
// After POR, the host needs to fist send a synchronization character (0x80)
// If this feature doesn't work properly, it is possible to disable it by
// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
reg sync_busy;
always @ (posedge mclk or posedge por)
if (por) sync_busy <= 1'b0;
else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1;
else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0;
assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy;
`ifdef DBG_UART_AUTO_SYNC
reg [14:0] sync_cnt;
always @ (posedge mclk or posedge por)
if (por) sync_cnt <= 15'h7ff8;
else if (sync_busy) sync_cnt <= sync_cnt+15'h0001;
wire [11:0] bit_cnt_max = sync_cnt[14:3];
`else
wire [11:0] bit_cnt_max = `DBG_UART_CNT;
`endif
//=============================================================================
// 4) UART RECEIVE / TRANSMIT
//=============================================================================
// Transfer counter
//------------------------
reg [3:0] xfer_bit;
reg [11:0] xfer_cnt;
wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt==12'h000);
assign xfer_done = (xfer_bit==4'hb);
always @ (posedge mclk or posedge por)
if (por) xfer_bit <= 4'h0;
else if (txd_start | rxd_start) xfer_bit <= 4'h1;
else if (xfer_done) xfer_bit <= 4'h0;
else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
always @ (posedge mclk or posedge por)
if (por) xfer_cnt <= 12'h000;
else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[11:1]};
else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
else xfer_cnt <= xfer_cnt+12'hfff;
// Receive/Transmit buffer
//-------------------------
wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
always @ (posedge mclk or posedge por)
if (por) xfer_buf <= 18'h00000;
else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
// Generate TXD output
//------------------------
reg dbg_uart_txd;
always @ (posedge mclk or posedge por)
if (por) dbg_uart_txd <= 1'b1;
else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0];
//=============================================================================
// 5) INTERFACE TO DEBUG REGISTERS
//=============================================================================
reg [5:0] dbg_addr;
always @ (posedge mclk or posedge por)
if (por) dbg_addr <= 6'h00;
else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR];
reg dbg_bw;
always @ (posedge mclk or posedge por)
if (por) dbg_bw <= 1'b0;
else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW];
wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf[18:11]} :
{xfer_buf[18:11], xfer_buf[8:1]};
wire dbg_wr = (xfer_done & (uart_state==RX_DATA2));
wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
(cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd;
endmodule
|
module usb_121pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("20.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("60.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("60.000000 MHz"),
.phase_shift1("8333 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
module sonic_sensor(
input clk,
input rst,
input req,
output busy,
inout sig,
output [31:0] out_data
output [3:0] led;
);
parameter STATE_INIT = 0,
STATE_IDLE = 1,
STATE_OUT_SIG = 2,
STATE_OUT_END = 3,
STATE_WAIT750 = 4,
STATE_IN_SIG_WAIT = 5,
STATE_IN_SIG = 6,
STATE_IN_SIG_END = 7,
STATE_WAIT200 = 8;
reg [3:0] state;
reg [31:0] echo;
reg [32:0] counter;
reg [31:0] result;
wire count_5u;
wire count_750u;
wire count_200u;
wire time_out;
wire echo_fl;
//for debug
// assign count_5u = counter == 249;
// assign count_750u = counter == 37;
// assign count_200u = counter == 10;
// assign echo_fl = (counter > 25)? 1 : 0;
// assign time_out = counter == 10;
assign count_5u = counter == 499;
assign count_750u = counter == 74998;
assign count_200u = counter == 19999;
assign time_out = counter == 2000;
assign echo_fl = (echo > 1850000)? 1 : 0;
assign sig = (state == STATE_OUT_SIG)? 1 : 1'bZ;
assign busy = (state > STATE_IDLE)?1 : 0;
//state unit
always @(posedge clk)
begin
if(rst)
state <= 0;
else case(state)
STATE_INIT: state <= STATE_IDLE;
STATE_IDLE:if(req) state <= STATE_OUT_SIG;
STATE_OUT_SIG:if(count_5u) state <= STATE_OUT_END;
STATE_OUT_END: state <= STATE_WAIT750;
STATE_WAIT750:if(count_750u) state <= STATE_IN_SIG_WAIT;
STATE_IN_SIG_WAIT: state <= STATE_IN_SIG;
STATE_IN_SIG:begin
if(echo_fl || sig == 0) state <= STATE_IN_SIG_END;
else if(echo == 0 && time_out) state <= STATE_INIT;
end
STATE_IN_SIG_END: state <= STATE_WAIT200;
STATE_WAIT200:if(count_200u) state <= STATE_IDLE;
endcase
end
//counter
always @(posedge clk)
begin
if(rst)
counter <= 0;
else
case(state)
STATE_OUT_SIG: counter <= counter + 1;
STATE_WAIT750: counter <= counter + 1;
STATE_IN_SIG : counter <= counter + 1;
STATE_WAIT200: counter <= counter + 1;
default counter <= 0;
endcase
end
//output
always @(posedge clk)
begin
if(rst)
echo <= 0;
else if(state == STATE_IN_SIG)begin
echo <= echo + 1;
end
else
echo <= 0;
end
always @(posedge clk)begin
if(rst)
result <= 0;
else if(state == STATE_IN_SIG_END)
result <= echo;
end
assign out_data = result[31:0];
assign led = state;
endmodule
|
module mig_7series_v2_0_ddr_phy_wrlvl_off_delay #
(
parameter TCQ = 100,
parameter tCK = 3636,
parameter nCK_PER_CLK = 2,
parameter CLK_PERIOD = 4,
parameter PO_INITIAL_DLY= 46,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter N_CTL_LANES = 3
)
(
input clk,
input rst,
input pi_fine_dly_dec_done,
input cmd_delay_start,
// Control lane being shifted using Phaser_Out fine delay taps
output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt,
// Inc/dec Phaser_Out fine delay line
output reg po_s2_incdec_f,
output reg po_en_s2_f,
// Inc/dec Phaser_Out coarse delay line
output reg po_s2_incdec_c,
output reg po_en_s2_c,
// Completed adjusting delays for dq, dqs for tdqss
output po_ck_addr_cmd_delay_done,
// completed decrementing initialPO delays
output po_dec_done,
output phy_ctl_rdy_dly
);
localparam TAP_LIMIT = 63;
// PO fine delay tap resolution change by frequency. tCK > 2500, need
// twice the amount of taps
// localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY;
// coarse delay tap is added DQ/DQS to meet the TDQSS specification.
localparam TDQSS_DLY = (tCK > 2500 )? 2: 1;
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] po_delay_cnt_r;
reg po_cnt_inc;
reg cmd_delay_start_r1;
reg cmd_delay_start_r2;
reg cmd_delay_start_r3;
reg cmd_delay_start_r4;
reg cmd_delay_start_r5;
reg cmd_delay_start_r6;
reg po_delay_done;
reg po_delay_done_r1;
reg po_delay_done_r2;
reg po_delay_done_r3;
reg po_delay_done_r4;
reg pi_fine_dly_dec_done_r;
reg po_en_stg2_c;
reg po_en_stg2_f;
reg po_stg2_incdec_c;
reg po_stg2_f_incdec;
reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r;
reg [DQS_CNT_WIDTH:0] lane_cnt_po_r;
reg [5:0] delay_cnt_r;
always @(posedge clk) begin
cmd_delay_start_r1 <= #TCQ cmd_delay_start;
cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1;
cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2;
cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3;
cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4;
cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5;
pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done;
end
assign phy_ctl_rdy_dly = cmd_delay_start_r6;
// logic for decrementing initial fine delay taps for all PO
// Decrement done for add, ctrl and data phaser outs
assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4;
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 || po_delay_done) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end else if (po_delay_cnt_r > 6'd0) begin
po_en_stg2_f <= #TCQ ~po_en_stg2_f;
end
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0))
// set all the PO delays to 31. Decrement from 46 to 31.
// Requirement comes from dqs_found logic
po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31);
else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0))
po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1;
always @(posedge clk)
if (rst)
lane_cnt_po_r <= #TCQ 'd0;
else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1))
lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1;
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 )
po_delay_done <= #TCQ 1'b0;
else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0))
po_delay_done <= #TCQ 1'b1;
always @(posedge clk) begin
po_delay_done_r1 <= #TCQ po_delay_done;
po_delay_done_r2 <= #TCQ po_delay_done_r1;
po_delay_done_r3 <= #TCQ po_delay_done_r2;
po_delay_done_r4 <= #TCQ po_delay_done_r3;
end
// logic to select between all PO delays and data path delay.
always @(posedge clk) begin
po_s2_incdec_f <= #TCQ po_stg2_f_incdec;
po_en_s2_f <= #TCQ po_en_stg2_f;
end
// Logic to add 1/4 taps amount of delay to data path for tdqss.
// After all the initial PO delays are decremented the 1/4 delay will
// be added. Coarse delay taps will be added here .
// Delay added only to data path
assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r
: delay_done_r4;
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin
po_stg2_incdec_c <= #TCQ 1'b1;
po_en_stg2_c <= #TCQ 1'b0;
end else if (delay_cnt_r > 6'd0) begin
po_en_stg2_c <= #TCQ ~po_en_stg2_c;
end
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0))
delay_cnt_r <= #TCQ TDQSS_DLY;
else if ( po_en_stg2_c && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
always @(posedge clk)
if (rst)
lane_cnt_dqs_c_r <= #TCQ 'd0;
else if ( po_en_stg2_c && (delay_cnt_r == 6'd1))
lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1;
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r)
delay_done <= #TCQ 1'b0;
else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0))
delay_done <= #TCQ 1'b1;
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
always @(posedge clk) begin
po_s2_incdec_c <= #TCQ po_stg2_incdec_c;
po_en_s2_c <= #TCQ po_en_stg2_c;
ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r;
end
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(GPIO_I,
GPIO_O,
GPIO_T,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *) input [63:0]GPIO_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *) output [63:0]GPIO_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *) output [63:0]GPIO_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_1_FCLK_CLK0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 49999947, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_1_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_1_FCLK_CLK0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB0_PORT_INDCTL_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "design_1_processing_system7_0_1.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={26} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS18} bidis={5} ioBank={Vcco_p1} clockFreq={166.666489} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p0} clockFreq={99.999893} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={49} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I(GPIO_I),
.GPIO_O(GPIO_O),
.GPIO_T(GPIO_T),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED),
.TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED),
.TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(NLW_inst_USB0_PORT_INDCTL_UNCONNECTED[1:0]),
.USB0_VBUS_PWRFAULT(1'b0),
.USB0_VBUS_PWRSELECT(NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
|
module axis_rate_limit #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [7:0] rate_num,
input wire [7:0] rate_denom,
input wire rate_by_frame
);
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [23:0] acc_reg = 0, acc_next;
reg pause;
reg frame_reg = 0, frame_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
always @* begin
acc_next = acc_reg;
pause = 0;
frame_next = frame_reg & ~input_axis_tlast;
if (acc_reg >= rate_num) begin
acc_next = acc_reg - rate_num;
end
if (input_axis_tready & input_axis_tvalid) begin
// read input
frame_next = ~input_axis_tlast;
acc_next = acc_reg + (rate_denom - rate_num);
end
if (acc_next >= rate_num) begin
if (rate_by_frame) begin
pause = ~frame_next;
end else begin
pause = 1;
end
end
input_axis_tready_next = output_axis_tready_int_early & ~pause;
output_axis_tdata_int = input_axis_tdata;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
acc_reg <= 0;
frame_reg <= 0;
input_axis_tready_reg <= 0;
end else begin
acc_reg <= acc_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
|
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n1654, Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM,
SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489,
n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n769, n770, n771, n772, n773, n774, n775, n776,
n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809,
n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n866, n867, n868, n869, n870, n871, DP_OP_15J49_123_3372_n8,
DP_OP_15J49_123_3372_n7, DP_OP_15J49_123_3372_n6,
DP_OP_15J49_123_3372_n5, DP_OP_15J49_123_3372_n4, intadd_51_B_12_,
intadd_51_B_11_, intadd_51_B_10_, intadd_51_B_9_, intadd_51_B_8_,
intadd_51_B_7_, intadd_51_B_6_, intadd_51_B_5_, intadd_51_B_4_,
intadd_51_B_3_, intadd_51_B_2_, intadd_51_B_1_, intadd_51_B_0_,
intadd_51_CI, intadd_51_SUM_12_, intadd_51_SUM_11_, intadd_51_SUM_10_,
intadd_51_SUM_9_, intadd_51_SUM_8_, intadd_51_SUM_7_,
intadd_51_SUM_6_, intadd_51_SUM_5_, intadd_51_SUM_4_,
intadd_51_SUM_3_, intadd_51_SUM_2_, intadd_51_SUM_1_,
intadd_51_SUM_0_, intadd_51_n13, intadd_51_n12, intadd_51_n11,
intadd_51_n10, intadd_51_n9, intadd_51_n8, intadd_51_n7, intadd_51_n6,
intadd_51_n5, intadd_51_n4, intadd_51_n3, intadd_51_n2, intadd_51_n1,
intadd_52_A_2_, intadd_52_A_1_, intadd_52_B_2_, intadd_52_B_1_,
intadd_52_B_0_, intadd_52_CI, intadd_52_SUM_2_, intadd_52_SUM_1_,
intadd_52_SUM_0_, intadd_52_n3, intadd_52_n2, intadd_52_n1,
intadd_53_A_2_, intadd_53_A_1_, intadd_53_B_1_, intadd_53_B_0_,
intadd_53_CI, intadd_53_SUM_2_, intadd_53_SUM_1_, intadd_53_SUM_0_,
intadd_53_n3, intadd_53_n2, intadd_53_n1, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1382, n1383, n1384, n1385, n1386, n1387, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1508, n1509, n1510, n1512, n1513,
n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523,
n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533,
n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543,
n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593,
n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603,
n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613,
n1614, n1615, n1616, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1653;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:2] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1621), .QN(
n893) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1619), .Q(
intAS) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1620),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1643),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1622),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1634),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1642), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1626), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1644), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1625), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1649), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1626), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1636), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1644), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1623), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1635), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1637), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1626), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1639), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1623), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1649), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1642), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1648), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1635), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n918), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1627), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1628), .QN(n899)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1630), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1629), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n970), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1632), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n970), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1632), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n918), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1632), .Q(
DMP_SFG[2]), .QN(n1600) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n970), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1627), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1628), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1631), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1630), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1632), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1629), .Q(
DMP_SFG[6]), .QN(n1601) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1632), .Q(
DMP_SFG[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n918), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1627), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1628), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n970), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1627), .Q(
DMP_SFG[10]), .QN(n1556) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1632), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n918), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1628), .Q(
DMP_SFG[11]), .QN(n1555) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1628), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1631), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1630), .Q(
DMP_SFG[12]), .QN(n1562) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1630), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1629), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1631), .Q(
DMP_SFG[13]), .QN(n1561) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n970), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1632), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1629), .Q(
DMP_SFG[14]), .QN(n1565) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n918), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1627), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1631), .Q(
DMP_SFG[15]), .QN(n1583) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1629), .Q(
DMP_SFG[16]), .QN(n1582) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1630), .Q(
DMP_SFG[17]), .QN(n1595) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1632), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1632), .Q(
DMP_SFG[18]), .QN(n1594) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1623), .Q(
DMP_SFG[19]), .QN(n1604) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1635), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1649), .Q(
DMP_SFG[20]), .QN(n1603) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1637), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1626), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1642), .Q(
DMP_SFG[21]), .QN(n1615) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1622), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1639), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1639), .Q(
DMP_SFG[22]), .QN(n1614) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1623), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1640), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1647), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1645), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1646), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1634), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1636), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1638), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1625), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1643), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1641), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1618), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1647), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1648), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1622), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1635), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n1637), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n1626), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1639), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1623), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1640), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1649), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1648), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1644), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1634), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1636), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1638), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1625), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1643), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1641), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1625), .QN(
n894) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1643), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1641), .QN(
n895) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1618), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1637), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1626), .QN(
n897) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1622), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1639), .QN(
n883) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1623), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1640), .QN(
n896) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1639), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1623), .QN(
n881) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1640), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1649), .QN(
n898) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1642), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1644), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1634), .QN(
n892) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1636), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1625),
.QN(n882) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1643), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1641),
.QN(n900) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1618), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1647),
.QN(n879) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1645), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1646),
.QN(n901) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1637), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1646), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1635), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n1625), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1640), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1633), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1634), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1641), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1633), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1642), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1639), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1618), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1641), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n550), .CK(clk), .RN(n1648), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1639), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1643), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1634), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1640), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1622), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1622), .Q(
LZD_output_NRM2_EW[3]), .QN(n1566) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1640), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1626), .Q(
LZD_output_NRM2_EW[2]), .QN(n1563) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1635), .Q(
LZD_output_NRM2_EW[1]), .QN(n1557) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1637), .Q(
LZD_output_NRM2_EW[4]), .QN(n1567) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1638), .Q(
DmP_mant_SFG_SWR[0]), .QN(n958) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1625), .Q(
DmP_mant_SFG_SWR[1]), .QN(n959) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[2]), .QN(n960) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[3]), .QN(n961) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1618), .Q(
DmP_mant_SFG_SWR[4]), .QN(n962) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1625), .Q(
DmP_mant_SFG_SWR[6]), .QN(n967) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[7]), .QN(n965) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[8]), .QN(n964) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[16]), .QN(n950) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1645), .Q(
DmP_mant_SFG_SWR[17]), .QN(n951) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1646), .Q(
DmP_mant_SFG_SWR[18]), .QN(n952) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[19]), .QN(n953) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1634), .Q(
DmP_mant_SFG_SWR[20]), .QN(n954) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1636), .Q(
DmP_mant_SFG_SWR[21]), .QN(n955) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1638), .Q(
DmP_mant_SFG_SWR[22]), .QN(n956) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[23]), .QN(n1599) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1649), .Q(
DmP_mant_SFG_SWR[24]), .QN(n1612) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1648), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1616) );
CMPR32X2TS intadd_51_U14 ( .A(n1556), .B(intadd_51_B_0_), .C(intadd_51_CI),
.CO(intadd_51_n13), .S(intadd_51_SUM_0_) );
CMPR32X2TS intadd_51_U13 ( .A(n1555), .B(intadd_51_B_1_), .C(intadd_51_n13),
.CO(intadd_51_n12), .S(intadd_51_SUM_1_) );
CMPR32X2TS intadd_51_U12 ( .A(n1562), .B(intadd_51_B_2_), .C(intadd_51_n12),
.CO(intadd_51_n11), .S(intadd_51_SUM_2_) );
CMPR32X2TS intadd_51_U11 ( .A(n1561), .B(intadd_51_B_3_), .C(intadd_51_n11),
.CO(intadd_51_n10), .S(intadd_51_SUM_3_) );
CMPR32X2TS intadd_51_U10 ( .A(n1565), .B(intadd_51_B_4_), .C(intadd_51_n10),
.CO(intadd_51_n9), .S(intadd_51_SUM_4_) );
CMPR32X2TS intadd_51_U9 ( .A(n1583), .B(intadd_51_B_5_), .C(intadd_51_n9),
.CO(intadd_51_n8), .S(intadd_51_SUM_5_) );
CMPR32X2TS intadd_51_U8 ( .A(n1582), .B(intadd_51_B_6_), .C(intadd_51_n8),
.CO(intadd_51_n7), .S(intadd_51_SUM_6_) );
CMPR32X2TS intadd_51_U7 ( .A(n1595), .B(intadd_51_B_7_), .C(intadd_51_n7),
.CO(intadd_51_n6), .S(intadd_51_SUM_7_) );
CMPR32X2TS intadd_51_U6 ( .A(n1594), .B(intadd_51_B_8_), .C(intadd_51_n6),
.CO(intadd_51_n5), .S(intadd_51_SUM_8_) );
CMPR32X2TS intadd_51_U5 ( .A(n1604), .B(intadd_51_B_9_), .C(intadd_51_n5),
.CO(intadd_51_n4), .S(intadd_51_SUM_9_) );
CMPR32X2TS intadd_51_U4 ( .A(n1603), .B(intadd_51_B_10_), .C(intadd_51_n4),
.CO(intadd_51_n3), .S(intadd_51_SUM_10_) );
CMPR32X2TS intadd_51_U3 ( .A(n1615), .B(intadd_51_B_11_), .C(intadd_51_n3),
.CO(intadd_51_n2), .S(intadd_51_SUM_11_) );
CMPR32X2TS intadd_51_U2 ( .A(n1614), .B(intadd_51_B_12_), .C(intadd_51_n2),
.CO(intadd_51_n1), .S(intadd_51_SUM_12_) );
CMPR32X2TS intadd_52_U4 ( .A(n1601), .B(intadd_52_B_0_), .C(intadd_52_CI),
.CO(intadd_52_n3), .S(intadd_52_SUM_0_) );
CMPR32X2TS intadd_52_U3 ( .A(intadd_52_A_1_), .B(intadd_52_B_1_), .C(
intadd_52_n3), .CO(intadd_52_n2), .S(intadd_52_SUM_1_) );
CMPR32X2TS intadd_52_U2 ( .A(intadd_52_A_2_), .B(intadd_52_B_2_), .C(
intadd_52_n2), .CO(intadd_52_n1), .S(intadd_52_SUM_2_) );
CMPR32X2TS intadd_53_U4 ( .A(n1600), .B(intadd_53_B_0_), .C(intadd_53_CI),
.CO(intadd_53_n3), .S(intadd_53_SUM_0_) );
CMPR32X2TS intadd_53_U3 ( .A(intadd_53_A_1_), .B(intadd_53_B_1_), .C(
intadd_53_n3), .CO(intadd_53_n2), .S(intadd_53_SUM_1_) );
CMPR32X2TS intadd_53_U2 ( .A(intadd_53_A_2_), .B(n923), .C(intadd_53_n2),
.CO(intadd_53_n1), .S(intadd_53_SUM_2_) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1633), .Q(
Data_array_SWR[10]), .QN(n1611) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1635), .Q(
DmP_EXP_EWSW[25]), .QN(n1610) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n970), .Q(
DMP_EXP_EWSW[26]), .QN(n1609) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1625), .Q(
DmP_EXP_EWSW[26]), .QN(n1605) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n971), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1602) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1629), .Q(
DMP_EXP_EWSW[25]), .QN(n1597) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1626), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1596) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1621), .Q(
intDY_EWSW[0]), .QN(n1585) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1649), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1581) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n972), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1580) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1624),
.Q(intDY_EWSW[27]), .QN(n1579) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1622),
.Q(intDY_EWSW[23]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1621),
.Q(intDY_EWSW[28]), .QN(n1578) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1624), .Q(
intDY_EWSW[7]), .QN(n1577) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1619), .Q(
intDY_EWSW[4]), .QN(n1574) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1647), .Q(
intDY_EWSW[2]), .QN(n1573) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1620), .Q(
intDY_EWSW[9]), .QN(n1570) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1618), .Q(
intDY_EWSW[6]), .QN(n1569) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1620), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1564) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1648),
.Q(intDX_EWSW[28]), .QN(n1559) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1642), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1554) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1645), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1552) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1648), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1551) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1646), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1548) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1642), .Q(
shift_value_SHT2_EWR[3]), .QN(n1547) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1637), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1546) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1645), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1545) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[26]), .QN(n1544) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1633), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1542) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1626), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1541) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1540) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1630), .Q(
DMP_EXP_EWSW[24]), .QN(n1539) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1636), .Q(
DmP_EXP_EWSW[24]), .QN(n1538) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1643),
.Q(intDY_EWSW[19]), .QN(n1536) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1620),
.Q(intDY_EWSW[16]), .QN(n1534) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n1621), .Q(
intDY_EWSW[5]), .QN(n1532) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1636), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1530) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1634), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1529) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n1639), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1527) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1644), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1525) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n1635), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1523) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n1642), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1522) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n917), .Q(
intDY_EWSW[24]), .QN(n1519) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1517) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1637), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1515) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1620),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1636), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1647), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1645), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1639), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1635), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1645), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1644), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1634), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1636), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1638), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1625), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1643), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1641), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1618), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1647), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1645), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1646), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1644), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1646), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1648), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1636), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1623), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1637), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n1638), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1646), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1633), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1633), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1635), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1637), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1626), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1622), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1639), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1640), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1623), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1640), .Q(
final_result_ieee[31]) );
DFFSX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n880), .CK(clk), .SN(n972), .Q(
n1651), .QN(n1650) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1620), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1531) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1625), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1593) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1649), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1518) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1621), .Q(
intDY_EWSW[8]), .QN(n1589) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1621),
.Q(intDY_EWSW[22]), .QN(n1535) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1634),
.Q(intDY_EWSW[30]), .QN(n1591) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1639),
.Q(intDY_EWSW[29]), .QN(n1537) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1625),
.Q(intDY_EWSW[26]), .QN(n1590) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1642),
.Q(intDY_EWSW[25]), .QN(n1584) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n918), .Q(
intDY_EWSW[21]), .QN(n1572) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1619),
.Q(intDY_EWSW[18]), .QN(n1592) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n1646),
.Q(intDY_EWSW[17]), .QN(n1587) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n1624),
.Q(intDY_EWSW[15]), .QN(n1586) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1643),
.Q(intDY_EWSW[14]), .QN(n1533) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1640),
.Q(intDY_EWSW[13]), .QN(n1571) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n917), .Q(
intDY_EWSW[12]), .QN(n1575) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1619), .Q(
intDY_EWSW[3]), .QN(n1568) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n918), .Q(
intDY_EWSW[1]), .QN(n1588) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1632),
.Q(intDX_EWSW[25]), .QN(n1543) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[24]), .QN(n1608) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[16]), .QN(n1558) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1621), .Q(
intDX_EWSW[7]), .QN(n1528) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1620), .Q(
intDX_EWSW[6]), .QN(n1553) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1636), .Q(
intDX_EWSW[5]), .QN(n1549) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1623), .Q(
intDX_EWSW[4]), .QN(n1524) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1619), .Q(
shift_value_SHT2_EWR[4]), .QN(n1550) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1621), .Q(
Data_array_SWR[23]), .QN(n1598) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1637), .Q(
Data_array_SWR[14]), .QN(n1607) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1618), .Q(
Data_array_SWR[12]), .QN(n1606) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1619), .Q(
n1520), .QN(n1613) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n917), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1621),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n918), .Q(
intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1619), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n917), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1621), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1624), .Q(
intDX_EWSW[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1635), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1621),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1621), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1620), .Q(
intDX_EWSW[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1624), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1633), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n1646), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1644), .Q(
intDX_EWSW[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1623), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[29]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1640), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1624), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1622), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1645), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1620), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1624), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n1619), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1622), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1627), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n918), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1628), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[31]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1521) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1630),
.Q(intDY_EWSW[10]), .QN(n876) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1631), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1618), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1647), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1625), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1624),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1623), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1639), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1640), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1638),
.Q(intDY_EWSW[11]), .QN(n1560) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1620),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1621),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1621),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1638),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n918), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1639),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1626), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1620), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1625), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1648), .Q(
Data_array_SWR[20]) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1619), .Q(
n1654), .QN(n1653) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1641), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1516) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1649), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1641), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1618), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1640), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1618), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1623), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n1634), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1649), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1638), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1623), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1622), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1620),
.Q(intDY_EWSW[20]), .QN(n1576) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1647), .Q(
DmP_mant_SFG_SWR[5]), .QN(n966) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1645), .Q(
DmP_mant_SFG_SWR[9]), .QN(n963) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1625), .Q(
DmP_EXP_EWSW[23]), .QN(n957) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1648), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n1624), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1645), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1643), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1640), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1623), .Q(
DmP_EXP_EWSW[27]) );
ADDFX1TS DP_OP_15J49_123_3372_U8 ( .A(n1557), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J49_123_3372_n8), .CO(DP_OP_15J49_123_3372_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J49_123_3372_U7 ( .A(n1563), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J49_123_3372_n7), .CO(DP_OP_15J49_123_3372_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J49_123_3372_U6 ( .A(n1566), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J49_123_3372_n6), .CO(DP_OP_15J49_123_3372_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J49_123_3372_U5 ( .A(n1567), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J49_123_3372_n5), .CO(DP_OP_15J49_123_3372_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1646), .Q(
OP_FLAG_SFG), .QN(n1526) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1624), .Q(
Shift_reg_FLAGS_7[1]), .QN(n877) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1648), .Q(
Shift_reg_FLAGS_7[0]), .QN(n872) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1619), .Q(
Shift_reg_FLAGS_7_6), .QN(n968) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1621), .Q(
left_right_SHT2), .QN(n878) );
AOI222X1TS U897 ( .A0(n1439), .A1(left_right_SHT2), .B0(Data_array_SWR[7]),
.B1(n940), .C0(n1438), .C1(n1455), .Y(n1501) );
NAND2X4TS U898 ( .A(n924), .B(n872), .Y(n1374) );
AOI222X4TS U899 ( .A0(Data_array_SWR[14]), .A1(n942), .B0(Data_array_SWR[22]), .B1(n1472), .C0(Data_array_SWR[18]), .C1(n944), .Y(n1423) );
AOI222X4TS U900 ( .A0(Data_array_SWR[24]), .A1(n1433), .B0(
Data_array_SWR[20]), .B1(n1448), .C0(Data_array_SWR[16]), .C1(n1447),
.Y(n1476) );
AOI222X4TS U901 ( .A0(Data_array_SWR[21]), .A1(n1448), .B0(
Data_array_SWR[17]), .B1(n1447), .C0(Data_array_SWR[25]), .C1(n1433),
.Y(n1470) );
AOI222X4TS U902 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n911), .B0(n913), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1254), .C1(DmP_mant_SHT1_SW[17]), .Y(n1234) );
NOR2X4TS U903 ( .A(n1205), .B(n1264), .Y(n1206) );
AOI211X2TS U904 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1172), .B0(n1306), .C0(
n1171), .Y(n1187) );
OAI222X1TS U905 ( .A0(n1611), .A1(n1351), .B0(n946), .B1(n1342), .C0(n910),
.C1(n1341), .Y(n781) );
OAI222X1TS U906 ( .A0(n1351), .A1(n1607), .B0(n946), .B1(n1340), .C0(n910),
.C1(n1334), .Y(n785) );
OAI222X1TS U907 ( .A0(n1598), .A1(n1351), .B0(n946), .B1(n1331), .C0(n910),
.C1(n1330), .Y(n794) );
AOI211X1TS U908 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n1387), .B0(n1335), .C0(
n1265), .Y(n1329) );
NAND3X1TS U909 ( .A(n1157), .B(n1300), .C(Raw_mant_NRM_SWR[1]), .Y(n1294) );
OAI211X1TS U910 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1163), .B0(n1299), .C0(
n1552), .Y(n1164) );
OAI21X1TS U911 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1155), .Y(n1156) );
BUFX3TS U912 ( .A(n1047), .Y(n873) );
INVX3TS U913 ( .A(n1351), .Y(n1185) );
INVX3TS U914 ( .A(n908), .Y(n875) );
INVX1TS U915 ( .A(LZD_output_NRM2_EW[0]), .Y(n1288) );
INVX1TS U916 ( .A(DMP_SFG[7]), .Y(intadd_52_A_1_) );
OAI222X1TS U917 ( .A0(n1606), .A1(n1351), .B0(n946), .B1(n1341), .C0(n910),
.C1(n1340), .Y(n783) );
INVX3TS U918 ( .A(n1184), .Y(n946) );
BUFX3TS U919 ( .A(n1203), .Y(n910) );
CLKBUFX3TS U920 ( .A(n1190), .Y(n1269) );
AND2X2TS U921 ( .A(n1186), .B(n1351), .Y(n1184) );
AOI222X1TS U922 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n911), .B0(n913), .B1(n933),
.C0(n1254), .C1(n925), .Y(n1261) );
AOI222X1TS U923 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n912), .B0(n914), .B1(
DmP_mant_SHT1_SW[19]), .C0(n1254), .C1(DmP_mant_SHT1_SW[20]), .Y(n1250) );
AOI222X1TS U924 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n912), .B0(n913), .B1(n931),
.C0(n1335), .C1(n927), .Y(n1245) );
AOI222X1TS U925 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n912), .B0(n914), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1254), .C1(DmP_mant_SHT1_SW[18]), .Y(n1253) );
INVX3TS U926 ( .A(n1338), .Y(n912) );
NAND3X1TS U927 ( .A(n1178), .B(n1164), .C(n1295), .Y(n1306) );
INVX3TS U928 ( .A(n1150), .Y(n1382) );
INVX3TS U929 ( .A(n1150), .Y(n1093) );
INVX3TS U930 ( .A(n1146), .Y(n1380) );
INVX3TS U931 ( .A(n1146), .Y(n1073) );
NOR2X4TS U932 ( .A(n1046), .B(n968), .Y(n1047) );
AOI32X1TS U933 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1351), .A2(n1387), .B0(
shift_value_SHT2_EWR[2]), .B1(n1348), .Y(n1350) );
AO22XLTS U934 ( .A0(n1321), .A1(add_subt), .B0(n921), .B1(intAS), .Y(n830)
);
AOI211XLTS U935 ( .A0(intDY_EWSW[16]), .A1(n1558), .B0(n1033), .C0(n1103),
.Y(n1025) );
BUFX3TS U936 ( .A(n1321), .Y(n874) );
OAI211X2TS U937 ( .A0(intDX_EWSW[20]), .A1(n1576), .B0(n1038), .C0(n1024),
.Y(n1033) );
INVX3TS U938 ( .A(n887), .Y(n914) );
INVX3TS U939 ( .A(OP_FLAG_SFG), .Y(n1407) );
OAI211X2TS U940 ( .A0(intDX_EWSW[12]), .A1(n1575), .B0(n1019), .C0(n1005),
.Y(n1021) );
INVX3TS U941 ( .A(n1654), .Y(n1376) );
NAND4XLTS U942 ( .A(n1521), .B(n1516), .C(n1515), .D(n1545), .Y(n1303) );
NAND3X1TS U943 ( .A(n1546), .B(n1522), .C(n1517), .Y(n1292) );
CLKINVX2TS U944 ( .A(DMP_SFG[8]), .Y(intadd_52_A_2_) );
INVX3TS U945 ( .A(n1651), .Y(n1406) );
INVX4TS U946 ( .A(rst), .Y(n918) );
NAND2X1TS U947 ( .A(n1155), .B(n1527), .Y(n1162) );
AOI2BB2XLTS U948 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1407), .A0N(n1526), .A1N(
DmP_mant_SFG_SWR[12]), .Y(intadd_51_CI) );
AOI2BB2XLTS U949 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n1407), .A0N(n1526), .A1N(
DmP_mant_SFG_SWR[14]), .Y(intadd_51_B_2_) );
NAND2BXLTS U950 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n996) );
AOI2BB2XLTS U951 ( .B0(intDX_EWSW[3]), .B1(n1568), .A0N(intDY_EWSW[2]),
.A1N(n998), .Y(n999) );
NAND2BXLTS U952 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1011) );
NAND3XLTS U953 ( .A(n1589), .B(n1009), .C(intDX_EWSW[8]), .Y(n1010) );
NAND2BXLTS U954 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1030) );
NOR2XLTS U955 ( .A(n1041), .B(intDY_EWSW[24]), .Y(n983) );
NAND2BXLTS U956 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n984) );
NAND2BXLTS U957 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1009) );
NAND2BXLTS U958 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1005) );
NAND2BXLTS U959 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1024) );
CLKAND2X2TS U960 ( .A(n1447), .B(shift_value_SHT2_EWR[4]), .Y(n1440) );
NOR2XLTS U961 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(n1173) );
AOI32X1TS U962 ( .A0(n1516), .A1(n1183), .A2(n1166), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1183), .Y(n1167) );
NAND2X1TS U963 ( .A(n1177), .B(n1518), .Y(n1170) );
NAND2X1TS U964 ( .A(n1165), .B(n1523), .Y(n1293) );
OAI2BB2XLTS U965 ( .B0(intDY_EWSW[22]), .B1(n1034), .A0N(intDX_EWSW[23]),
.A1N(n938), .Y(n1035) );
NAND2BXLTS U966 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n985) );
NAND3XLTS U967 ( .A(n1590), .B(n984), .C(intDX_EWSW[26]), .Y(n986) );
NAND2BXLTS U968 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1039) );
NAND3BXLTS U969 ( .AN(n1028), .B(n1026), .C(n1025), .Y(n1044) );
AOI222X4TS U970 ( .A0(Data_array_SWR[21]), .A1(n944), .B0(Data_array_SWR[17]), .B1(n942), .C0(Data_array_SWR[25]), .C1(n1472), .Y(n1416) );
NAND2BXLTS U971 ( .AN(n1273), .B(n1310), .Y(n1274) );
NAND3XLTS U972 ( .A(n1309), .B(exp_rslt_NRM2_EW1[4]), .C(n1272), .Y(n1273)
);
OR2X1TS U973 ( .A(n981), .B(n1271), .Y(n1280) );
NAND2BXLTS U974 ( .AN(n1310), .B(n978), .Y(n981) );
NAND4BXLTS U975 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n976), .C(n975), .D(n974),
.Y(n977) );
INVX2TS U976 ( .A(n886), .Y(n923) );
AO22XLTS U977 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n1407), .B0(n1403), .B1(n967),
.Y(n886) );
NOR2XLTS U978 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(n1176) );
AO21XLTS U979 ( .A0(n1518), .A1(n1540), .B0(n1293), .Y(n1301) );
AOI221X1TS U980 ( .A0(n1535), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]), .B1(
n938), .C0(n1105), .Y(n1106) );
OAI21XLTS U981 ( .A0(n1552), .A1(n1338), .B0(n1232), .Y(n1233) );
AOI222X1TS U982 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n912), .B0(n914), .B1(n932),
.C0(n1254), .C1(DmP_mant_SHT1_SW[10]), .Y(n1248) );
AOI222X1TS U983 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n912), .B0(n914), .B1(n926),
.C0(n1254), .C1(n929), .Y(n1215) );
AOI222X1TS U984 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n912), .B0(n914), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1254), .C1(n926), .Y(n1220) );
AOI222X1TS U985 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n912), .B0(n914), .B1(n925),
.C0(n1254), .C1(DmP_mant_SHT1_SW[8]), .Y(n1223) );
AOI222X1TS U986 ( .A0(n1270), .A1(DMP_SFG[1]), .B0(n1270), .B1(n919), .C0(
DMP_SFG[1]), .C1(n919), .Y(intadd_53_CI) );
AOI222X1TS U987 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n911), .B0(n930), .B1(n1254), .C0(n913), .C1(n928), .Y(n1242) );
AOI222X1TS U988 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n912), .B0(n914), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1254), .C1(DmP_mant_SHT1_SW[16]), .Y(n1241) );
OAI21XLTS U989 ( .A0(n1542), .A1(n1338), .B0(n1228), .Y(n1229) );
AO22XLTS U990 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n1403), .B0(n1407), .B1(n961),
.Y(n885) );
CLKAND2X2TS U991 ( .A(n1602), .B(n1276), .Y(n1277) );
NOR2XLTS U992 ( .A(n1279), .B(n1274), .Y(n1278) );
AOI2BB2XLTS U993 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n1407), .A0N(n1526), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_51_B_3_) );
AO22XLTS U994 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n1403), .B0(n1407), .B1(n965),
.Y(n884) );
AOI2BB2XLTS U995 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1407), .A0N(n1526), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_51_B_1_) );
NAND3XLTS U996 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1531), .C(n1564), .Y(n1312) );
OAI21XLTS U997 ( .A0(n1540), .A1(n1338), .B0(n1337), .Y(n1339) );
AOI222X1TS U998 ( .A0(n1435), .A1(n875), .B0(Data_array_SWR[8]), .B1(n903),
.C0(n1434), .C1(n1454), .Y(n1487) );
OAI21XLTS U999 ( .A0(n1529), .A1(n1158), .B0(n1294), .Y(n1159) );
NOR2XLTS U1000 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1153)
);
NAND4XLTS U1001 ( .A(n1296), .B(n1295), .C(n1294), .D(n1301), .Y(n1297) );
BUFX4TS U1002 ( .A(n1049), .Y(n1145) );
AO22XLTS U1003 ( .A0(n1320), .A1(intDY_EWSW[20]), .B0(n922), .B1(Data_Y[20]),
.Y(n808) );
AO22XLTS U1004 ( .A0(n1491), .A1(DmP_mant_SFG_SWR[11]), .B0(n1497), .B1(
n1490), .Y(n477) );
AO22XLTS U1005 ( .A0(n949), .A1(DmP_EXP_EWSW[20]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U1006 ( .A0(n949), .A1(DmP_EXP_EWSW[17]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U1007 ( .A0(n949), .A1(DmP_EXP_EWSW[16]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U1008 ( .A0(n949), .A1(DmP_EXP_EWSW[19]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[19]), .Y(n571) );
AO22XLTS U1009 ( .A0(n949), .A1(DmP_EXP_EWSW[15]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U1010 ( .A0(n949), .A1(DmP_EXP_EWSW[21]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U1011 ( .A0(n1520), .A1(DmP_EXP_EWSW[2]), .B0(n1378), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U1012 ( .A0(n949), .A1(DmP_EXP_EWSW[22]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
AO22XLTS U1013 ( .A0(n949), .A1(DmP_EXP_EWSW[18]), .B0(n1379), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U1014 ( .A0(n1520), .A1(DmP_EXP_EWSW[10]), .B0(n1378), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1015 ( .A0(n1520), .A1(DmP_EXP_EWSW[8]), .B0(n1378), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
OAI21XLTS U1016 ( .A0(n1258), .A1(n946), .B0(n1257), .Y(n791) );
OAI211XLTS U1017 ( .A0(n1241), .A1(n946), .B0(n1240), .C0(n1239), .Y(n788)
);
OAI211XLTS U1018 ( .A0(n1223), .A1(n946), .B0(n1222), .C0(n1221), .Y(n780)
);
AOI2BB2XLTS U1019 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1343), .A0N(n1248),
.A1N(n910), .Y(n1221) );
AO22XLTS U1020 ( .A0(n1321), .A1(Data_X[19]), .B0(n1327), .B1(intDX_EWSW[19]), .Y(n843) );
AO22XLTS U1021 ( .A0(n922), .A1(Data_X[30]), .B0(n1327), .B1(intDX_EWSW[30]),
.Y(n832) );
AO22XLTS U1022 ( .A0(n1325), .A1(Data_X[10]), .B0(n1322), .B1(intDX_EWSW[10]), .Y(n852) );
AO22XLTS U1023 ( .A0(n1328), .A1(Data_X[2]), .B0(n1327), .B1(intDX_EWSW[2]),
.Y(n860) );
AO22XLTS U1024 ( .A0(n874), .A1(Data_X[22]), .B0(n1324), .B1(intDX_EWSW[22]),
.Y(n840) );
AO22XLTS U1025 ( .A0(n1328), .A1(Data_X[14]), .B0(n1322), .B1(intDX_EWSW[14]), .Y(n848) );
AO22XLTS U1026 ( .A0(n1328), .A1(Data_X[20]), .B0(n1320), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1027 ( .A0(n1323), .A1(Data_X[12]), .B0(n1319), .B1(intDX_EWSW[12]), .Y(n850) );
AO22XLTS U1028 ( .A0(n874), .A1(Data_Y[31]), .B0(n921), .B1(intDY_EWSW[31]),
.Y(n797) );
AO22XLTS U1029 ( .A0(n1324), .A1(intDY_EWSW[11]), .B0(n874), .B1(Data_Y[11]),
.Y(n817) );
OAI21XLTS U1030 ( .A0(n938), .A1(n1382), .B0(n1094), .Y(n730) );
AO22XLTS U1031 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[10]), .B0(n1497), .B1(
n1489), .Y(n478) );
AO22XLTS U1032 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[12]), .B0(n1493), .B1(
n1492), .Y(n476) );
AO22XLTS U1033 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[13]), .B0(n1493), .B1(
n1494), .Y(n475) );
AO22XLTS U1034 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[14]), .B0(n1497), .B1(
n1495), .Y(n474) );
AO22XLTS U1035 ( .A0(n1498), .A1(DmP_mant_SFG_SWR[15]), .B0(n1493), .B1(
n1496), .Y(n473) );
AO22XLTS U1036 ( .A0(n1497), .A1(DMP_SHT2_EWSW[0]), .B0(n1498), .B1(
DMP_SFG[0]), .Y(n717) );
AO22XLTS U1037 ( .A0(n1326), .A1(intDY_EWSW[10]), .B0(n922), .B1(Data_Y[10]),
.Y(n818) );
AO22XLTS U1038 ( .A0(n874), .A1(Data_X[31]), .B0(n1324), .B1(intDX_EWSW[31]),
.Y(n831) );
AO22XLTS U1039 ( .A0(n1497), .A1(DMP_SHT2_EWSW[1]), .B0(n1374), .B1(
DMP_SFG[1]), .Y(n714) );
AO22XLTS U1040 ( .A0(n1509), .A1(DMP_SHT2_EWSW[5]), .B0(n1512), .B1(
DMP_SFG[5]), .Y(n702) );
AO22XLTS U1041 ( .A0(n1509), .A1(DMP_SHT2_EWSW[9]), .B0(n1512), .B1(
DMP_SFG[9]), .Y(n690) );
OAI211XLTS U1042 ( .A0(n1220), .A1(n946), .B0(n1202), .C0(n1201), .Y(n775)
);
AOI2BB2XLTS U1043 ( .B0(n1650), .B1(intadd_51_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1402), .Y(n524) );
OAI211XLTS U1044 ( .A0(n1253), .A1(n946), .B0(n1252), .C0(n1251), .Y(n790)
);
AO22XLTS U1045 ( .A0(n1328), .A1(Data_X[27]), .B0(n1322), .B1(intDX_EWSW[27]), .Y(n835) );
AO22XLTS U1046 ( .A0(n1325), .A1(Data_X[29]), .B0(n1322), .B1(intDX_EWSW[29]), .Y(n833) );
AO22XLTS U1047 ( .A0(n1323), .A1(Data_X[18]), .B0(n1320), .B1(intDX_EWSW[18]), .Y(n844) );
AOI2BB2XLTS U1048 ( .B0(n1650), .B1(intadd_51_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1402), .Y(n523) );
AO22XLTS U1049 ( .A0(n1321), .A1(Data_X[0]), .B0(n1327), .B1(intDX_EWSW[0]),
.Y(n862) );
OAI211XLTS U1050 ( .A0(n1242), .A1(n946), .B0(n1238), .C0(n1237), .Y(n786)
);
AOI2BB2XLTS U1051 ( .B0(n1650), .B1(intadd_51_SUM_0_), .A0N(
Raw_mant_NRM_SWR[12]), .A1N(n1402), .Y(n530) );
AO22XLTS U1052 ( .A0(n1323), .A1(Data_X[9]), .B0(n921), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1053 ( .A0(n1328), .A1(Data_X[1]), .B0(n1320), .B1(intDX_EWSW[1]),
.Y(n861) );
AO22XLTS U1054 ( .A0(n874), .A1(Data_X[11]), .B0(n1320), .B1(intDX_EWSW[11]),
.Y(n851) );
AO22XLTS U1055 ( .A0(n1328), .A1(Data_X[17]), .B0(n1319), .B1(intDX_EWSW[17]), .Y(n845) );
AOI2BB2XLTS U1056 ( .B0(n1650), .B1(intadd_51_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1650), .Y(n522) );
AO22XLTS U1057 ( .A0(n874), .A1(Data_X[8]), .B0(n1319), .B1(intDX_EWSW[8]),
.Y(n854) );
OAI21XLTS U1058 ( .A0(n1551), .A1(n1269), .B0(n1268), .Y(n793) );
AO22XLTS U1059 ( .A0(n1323), .A1(Data_X[15]), .B0(n921), .B1(intDX_EWSW[15]),
.Y(n847) );
AO22XLTS U1060 ( .A0(n874), .A1(Data_X[23]), .B0(n921), .B1(intDX_EWSW[23]),
.Y(n839) );
AO22XLTS U1061 ( .A0(n1323), .A1(Data_X[13]), .B0(n1324), .B1(intDX_EWSW[13]), .Y(n849) );
AO22XLTS U1062 ( .A0(n922), .A1(Data_X[21]), .B0(n1319), .B1(intDX_EWSW[21]),
.Y(n841) );
AO22XLTS U1063 ( .A0(n1321), .A1(Data_X[3]), .B0(n1324), .B1(intDX_EWSW[3]),
.Y(n859) );
AO22XLTS U1064 ( .A0(n1323), .A1(Data_X[4]), .B0(n1320), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1065 ( .A0(n874), .A1(Data_X[5]), .B0(n1324), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1066 ( .A0(n922), .A1(Data_X[6]), .B0(n1322), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1067 ( .A0(n922), .A1(Data_X[7]), .B0(n1319), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1068 ( .A0(n874), .A1(Data_X[16]), .B0(n921), .B1(intDX_EWSW[16]),
.Y(n846) );
AO22XLTS U1069 ( .A0(n1322), .A1(intDX_EWSW[24]), .B0(n1323), .B1(Data_X[24]), .Y(n838) );
AO22XLTS U1070 ( .A0(n1320), .A1(intDX_EWSW[25]), .B0(n1328), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1071 ( .A0(n1319), .A1(intDY_EWSW[1]), .B0(n1328), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1072 ( .A0(n1324), .A1(intDY_EWSW[3]), .B0(n874), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1073 ( .A0(n1324), .A1(intDY_EWSW[12]), .B0(n1323), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1074 ( .A0(n1319), .A1(intDY_EWSW[13]), .B0(n922), .B1(Data_Y[13]),
.Y(n815) );
AO22XLTS U1075 ( .A0(n1327), .A1(intDY_EWSW[14]), .B0(n922), .B1(Data_Y[14]),
.Y(n814) );
AO22XLTS U1076 ( .A0(n1322), .A1(intDY_EWSW[15]), .B0(n922), .B1(Data_Y[15]),
.Y(n813) );
AO22XLTS U1077 ( .A0(n1320), .A1(intDY_EWSW[17]), .B0(n922), .B1(Data_Y[17]),
.Y(n811) );
AO22XLTS U1078 ( .A0(n921), .A1(intDY_EWSW[18]), .B0(n922), .B1(Data_Y[18]),
.Y(n810) );
AO22XLTS U1079 ( .A0(n1324), .A1(intDY_EWSW[21]), .B0(n922), .B1(Data_Y[21]),
.Y(n807) );
AO22XLTS U1080 ( .A0(n1322), .A1(intDY_EWSW[25]), .B0(n1328), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1081 ( .A0(n921), .A1(intDY_EWSW[26]), .B0(n1323), .B1(Data_Y[26]),
.Y(n802) );
AO22XLTS U1082 ( .A0(n1327), .A1(intDY_EWSW[29]), .B0(n922), .B1(Data_Y[29]),
.Y(n799) );
AO22XLTS U1083 ( .A0(n1319), .A1(intDY_EWSW[30]), .B0(n1328), .B1(Data_Y[30]), .Y(n798) );
AO22XLTS U1084 ( .A0(n1327), .A1(intDY_EWSW[22]), .B0(n1323), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1085 ( .A0(n921), .A1(intDY_EWSW[8]), .B0(n874), .B1(Data_Y[8]),
.Y(n820) );
NOR2XLTS U1086 ( .A(n1412), .B(SIGN_FLAG_SHT1SHT2), .Y(n1281) );
AO22XLTS U1087 ( .A0(final_result_ieee[10]), .A1(n1471), .B0(n1428), .B1(
n1492), .Y(n511) );
AO22XLTS U1088 ( .A0(n1428), .A1(n1496), .B0(final_result_ieee[13]), .B1(
n1471), .Y(n506) );
AO22XLTS U1089 ( .A0(n1428), .A1(n1489), .B0(final_result_ieee[8]), .B1(
n1471), .Y(n507) );
AO22XLTS U1090 ( .A0(n1428), .A1(n1495), .B0(final_result_ieee[12]), .B1(
n1471), .Y(n508) );
AO22XLTS U1091 ( .A0(n1428), .A1(n1490), .B0(final_result_ieee[9]), .B1(
n1471), .Y(n509) );
AO22XLTS U1092 ( .A0(n1428), .A1(n1494), .B0(final_result_ieee[11]), .B1(
n1471), .Y(n510) );
AO22XLTS U1093 ( .A0(n1324), .A1(intDY_EWSW[24]), .B0(n1328), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1094 ( .A0(n1326), .A1(intDY_EWSW[5]), .B0(n874), .B1(Data_Y[5]),
.Y(n823) );
AO22XLTS U1095 ( .A0(n1327), .A1(intDY_EWSW[16]), .B0(n922), .B1(Data_Y[16]),
.Y(n812) );
AO22XLTS U1096 ( .A0(n1326), .A1(intDY_EWSW[19]), .B0(n922), .B1(Data_Y[19]),
.Y(n809) );
AO22XLTS U1097 ( .A0(n1327), .A1(intDX_EWSW[26]), .B0(n1323), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1098 ( .A0(n1325), .A1(Data_X[28]), .B0(n1327), .B1(intDX_EWSW[28]), .Y(n834) );
OAI21XLTS U1099 ( .A0(n1314), .A1(n982), .B0(n1312), .Y(n870) );
AOI2BB2XLTS U1100 ( .B0(beg_OP), .B1(n1531), .A0N(n1531), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n982) );
AO22XLTS U1101 ( .A0(n1322), .A1(intDY_EWSW[6]), .B0(n874), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1102 ( .A0(n1319), .A1(intDY_EWSW[9]), .B0(n1328), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1103 ( .A0(n921), .A1(intDY_EWSW[2]), .B0(n1323), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1104 ( .A0(n1322), .A1(intDY_EWSW[4]), .B0(n1328), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1105 ( .A0(n1319), .A1(intDY_EWSW[7]), .B0(n1328), .B1(Data_Y[7]),
.Y(n821) );
AO22XLTS U1106 ( .A0(n1326), .A1(intDY_EWSW[28]), .B0(n1323), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1107 ( .A0(n1320), .A1(intDY_EWSW[23]), .B0(n1323), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1108 ( .A0(n1326), .A1(intDY_EWSW[27]), .B0(n874), .B1(Data_Y[27]),
.Y(n801) );
AO22XLTS U1109 ( .A0(n1320), .A1(intDY_EWSW[0]), .B0(n1325), .B1(Data_Y[0]),
.Y(n828) );
AO21XLTS U1110 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1387), .B0(n1307), .Y(n513) );
AO21XLTS U1111 ( .A0(LZD_output_NRM2_EW[0]), .A1(n1387), .B0(n1336), .Y(n515) );
AOI2BB1XLTS U1112 ( .A0N(Shift_reg_FLAGS_7[1]), .A1N(LZD_output_NRM2_EW[3]),
.B0(n1353), .Y(n516) );
AO22XLTS U1113 ( .A0(n1493), .A1(ZERO_FLAG_SHT2), .B0(n1512), .B1(
ZERO_FLAG_SFG), .Y(n555) );
OAI21XLTS U1114 ( .A0(n1535), .A1(n1380), .B0(n1051), .Y(n566) );
OAI21XLTS U1115 ( .A0(n1572), .A1(n1380), .B0(n1058), .Y(n568) );
OAI21XLTS U1116 ( .A0(n1536), .A1(n1380), .B0(n1052), .Y(n572) );
OAI21XLTS U1117 ( .A0(n1592), .A1(n1380), .B0(n1064), .Y(n574) );
OAI21XLTS U1118 ( .A0(n1587), .A1(n1380), .B0(n1057), .Y(n576) );
OAI21XLTS U1119 ( .A0(n1586), .A1(n1073), .B0(n1072), .Y(n580) );
AO22XLTS U1120 ( .A0(n1520), .A1(DmP_EXP_EWSW[14]), .B0(n1379), .B1(n930),
.Y(n581) );
OAI21XLTS U1121 ( .A0(n1533), .A1(n1073), .B0(n1050), .Y(n582) );
AO22XLTS U1122 ( .A0(n1520), .A1(DmP_EXP_EWSW[13]), .B0(n1379), .B1(n928),
.Y(n583) );
OAI21XLTS U1123 ( .A0(n1571), .A1(n1073), .B0(n1059), .Y(n584) );
AO22XLTS U1124 ( .A0(n1520), .A1(DmP_EXP_EWSW[12]), .B0(n1379), .B1(n927),
.Y(n585) );
OAI21XLTS U1125 ( .A0(n1575), .A1(n1073), .B0(n1066), .Y(n586) );
AO22XLTS U1126 ( .A0(n1520), .A1(DmP_EXP_EWSW[11]), .B0(n1378), .B1(n931),
.Y(n587) );
OAI21XLTS U1127 ( .A0(n1112), .A1(n1073), .B0(n1069), .Y(n588) );
OAI21XLTS U1128 ( .A0(n876), .A1(n1073), .B0(n1060), .Y(n590) );
AO22XLTS U1129 ( .A0(n1520), .A1(DmP_EXP_EWSW[9]), .B0(n1378), .B1(n932),
.Y(n591) );
OAI21XLTS U1130 ( .A0(n1570), .A1(n1073), .B0(n1062), .Y(n592) );
OAI21XLTS U1131 ( .A0(n1589), .A1(n1073), .B0(n1067), .Y(n594) );
AO22XLTS U1132 ( .A0(n1520), .A1(DmP_EXP_EWSW[7]), .B0(n1378), .B1(n925),
.Y(n595) );
OAI21XLTS U1133 ( .A0(n1577), .A1(n1073), .B0(n1063), .Y(n596) );
AO22XLTS U1134 ( .A0(n1520), .A1(DmP_EXP_EWSW[6]), .B0(n1378), .B1(n933),
.Y(n597) );
OAI21XLTS U1135 ( .A0(n1569), .A1(n1073), .B0(n1055), .Y(n598) );
AO22XLTS U1136 ( .A0(n1520), .A1(DmP_EXP_EWSW[5]), .B0(n1378), .B1(n934),
.Y(n599) );
OAI21XLTS U1137 ( .A0(n1532), .A1(n1073), .B0(n1054), .Y(n600) );
AO22XLTS U1138 ( .A0(n1520), .A1(DmP_EXP_EWSW[4]), .B0(n1378), .B1(n929),
.Y(n601) );
OAI21XLTS U1139 ( .A0(n1574), .A1(n1073), .B0(n1056), .Y(n602) );
AO22XLTS U1140 ( .A0(n1520), .A1(DmP_EXP_EWSW[3]), .B0(n1378), .B1(n926),
.Y(n603) );
OAI21XLTS U1141 ( .A0(n1568), .A1(n1131), .B0(n1070), .Y(n604) );
OAI21XLTS U1142 ( .A0(n1573), .A1(n1131), .B0(n1068), .Y(n606) );
AO22XLTS U1143 ( .A0(n1520), .A1(DmP_EXP_EWSW[1]), .B0(n1378), .B1(n935),
.Y(n607) );
OAI21XLTS U1144 ( .A0(n1588), .A1(n1131), .B0(n1065), .Y(n608) );
AO22XLTS U1145 ( .A0(n949), .A1(DmP_EXP_EWSW[0]), .B0(n1385), .B1(n936), .Y(
n609) );
OAI21XLTS U1146 ( .A0(n1585), .A1(n1131), .B0(n1048), .Y(n610) );
AO22XLTS U1147 ( .A0(n1509), .A1(DMP_SHT2_EWSW[29]), .B0(n1512), .B1(
DMP_SFG[29]), .Y(n618) );
AO22XLTS U1148 ( .A0(n1491), .A1(DMP_SFG[22]), .B0(n1497), .B1(
DMP_SHT2_EWSW[22]), .Y(n651) );
AO22XLTS U1149 ( .A0(n1491), .A1(DMP_SFG[21]), .B0(n1493), .B1(
DMP_SHT2_EWSW[21]), .Y(n654) );
AO22XLTS U1150 ( .A0(n1491), .A1(DMP_SFG[20]), .B0(n1497), .B1(
DMP_SHT2_EWSW[20]), .Y(n657) );
AO22XLTS U1151 ( .A0(n1491), .A1(DMP_SFG[19]), .B0(n1493), .B1(
DMP_SHT2_EWSW[19]), .Y(n660) );
AO22XLTS U1152 ( .A0(n1491), .A1(DMP_SFG[17]), .B0(n1493), .B1(
DMP_SHT2_EWSW[17]), .Y(n666) );
AO22XLTS U1153 ( .A0(n1491), .A1(DMP_SFG[15]), .B0(n1497), .B1(
DMP_SHT2_EWSW[15]), .Y(n672) );
AO22XLTS U1154 ( .A0(n1491), .A1(DMP_SFG[13]), .B0(n1493), .B1(
DMP_SHT2_EWSW[13]), .Y(n678) );
AO22XLTS U1155 ( .A0(n1491), .A1(DMP_SFG[11]), .B0(n1497), .B1(
DMP_SHT2_EWSW[11]), .Y(n684) );
AO22XLTS U1156 ( .A0(n1491), .A1(DMP_SFG[6]), .B0(n1493), .B1(
DMP_SHT2_EWSW[6]), .Y(n699) );
OAI21XLTS U1157 ( .A0(n1135), .A1(n1049), .B0(n1131), .Y(n1133) );
AO22XLTS U1158 ( .A0(n1373), .A1(n1372), .B0(ZERO_FLAG_EXP), .B1(n1049), .Y(
n721) );
OAI21XLTS U1159 ( .A0(n1591), .A1(n1382), .B0(n1085), .Y(n723) );
OAI21XLTS U1160 ( .A0(n1537), .A1(n1382), .B0(n1084), .Y(n724) );
OAI21XLTS U1161 ( .A0(n1578), .A1(n1382), .B0(n1082), .Y(n725) );
OAI21XLTS U1162 ( .A0(n1579), .A1(n1382), .B0(n1083), .Y(n726) );
OAI21XLTS U1163 ( .A0(n1535), .A1(n1093), .B0(n1075), .Y(n731) );
OAI21XLTS U1164 ( .A0(n1572), .A1(n1093), .B0(n1079), .Y(n732) );
OAI21XLTS U1165 ( .A0(n1536), .A1(n1093), .B0(n1088), .Y(n734) );
OAI21XLTS U1166 ( .A0(n1592), .A1(n1093), .B0(n1074), .Y(n735) );
OAI21XLTS U1167 ( .A0(n1534), .A1(n1093), .B0(n1089), .Y(n737) );
OAI21XLTS U1168 ( .A0(n1586), .A1(n1093), .B0(n1081), .Y(n738) );
OAI21XLTS U1169 ( .A0(n1533), .A1(n1093), .B0(n1078), .Y(n739) );
OAI21XLTS U1170 ( .A0(n1571), .A1(n1093), .B0(n1080), .Y(n740) );
OAI21XLTS U1171 ( .A0(n1575), .A1(n1093), .B0(n1076), .Y(n741) );
OAI21XLTS U1172 ( .A0(n1112), .A1(n1093), .B0(n1090), .Y(n742) );
OAI21XLTS U1173 ( .A0(n876), .A1(n1148), .B0(n1147), .Y(n743) );
OAI21XLTS U1174 ( .A0(n1570), .A1(n1148), .B0(n1141), .Y(n744) );
OAI21XLTS U1175 ( .A0(n1589), .A1(n1148), .B0(n1138), .Y(n745) );
OAI21XLTS U1176 ( .A0(n1577), .A1(n1148), .B0(n1139), .Y(n746) );
OAI21XLTS U1177 ( .A0(n1569), .A1(n1148), .B0(n1140), .Y(n747) );
OAI21XLTS U1178 ( .A0(n1532), .A1(n1148), .B0(n1144), .Y(n748) );
OAI21XLTS U1179 ( .A0(n1574), .A1(n1148), .B0(n1143), .Y(n749) );
OAI21XLTS U1180 ( .A0(n1573), .A1(n1148), .B0(n1142), .Y(n751) );
OAI21XLTS U1181 ( .A0(n1588), .A1(n1382), .B0(n1086), .Y(n752) );
OAI21XLTS U1182 ( .A0(n1585), .A1(n1093), .B0(n1087), .Y(n753) );
AO22XLTS U1183 ( .A0(n1317), .A1(busy), .B0(n1316), .B1(n924), .Y(n866) );
INVX3TS U1184 ( .A(n907), .Y(n1387) );
AOI22X1TS U1185 ( .A0(n1316), .A1(n1650), .B0(n1317), .B1(n924), .Y(n880) );
OR2X1TS U1186 ( .A(n907), .B(Shift_amount_SHT1_EWR[0]), .Y(n887) );
OR2X1TS U1187 ( .A(n908), .B(n1458), .Y(n888) );
OR2X1TS U1188 ( .A(shift_value_SHT2_EWR[4]), .B(n1427), .Y(n889) );
OR2X1TS U1189 ( .A(n875), .B(n1458), .Y(n890) );
OR3X1TS U1190 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1547), .Y(n891) );
INVX2TS U1191 ( .A(n947), .Y(n948) );
INVX2TS U1192 ( .A(n888), .Y(n902) );
INVX2TS U1193 ( .A(n888), .Y(n903) );
INVX2TS U1194 ( .A(n1325), .Y(n1326) );
INVX2TS U1195 ( .A(n1428), .Y(n904) );
INVX2TS U1196 ( .A(n1428), .Y(n905) );
INVX2TS U1197 ( .A(Shift_reg_FLAGS_7[1]), .Y(n906) );
INVX2TS U1198 ( .A(n877), .Y(n907) );
INVX2TS U1199 ( .A(n878), .Y(n908) );
INVX2TS U1200 ( .A(left_right_SHT2), .Y(n909) );
INVX2TS U1201 ( .A(n1338), .Y(n911) );
CLKINVX3TS U1202 ( .A(n887), .Y(n913) );
INVX2TS U1203 ( .A(n948), .Y(n915) );
INVX2TS U1204 ( .A(n915), .Y(n916) );
OAI21XLTS U1205 ( .A0(n1579), .A1(n1073), .B0(n1071), .Y(n560) );
OAI211XLTS U1206 ( .A0(n1193), .A1(n946), .B0(n1192), .C0(n1191), .Y(n772)
);
BUFX4TS U1207 ( .A(n1374), .Y(n1512) );
INVX2TS U1208 ( .A(rst), .Y(n917) );
OAI211XLTS U1209 ( .A0(n987), .A1(n1096), .B0(n986), .C0(n985), .Y(n992) );
OAI21X2TS U1210 ( .A0(intDX_EWSW[26]), .A1(n1590), .B0(n984), .Y(n1096) );
INVX2TS U1211 ( .A(n885), .Y(n919) );
INVX2TS U1212 ( .A(n884), .Y(n920) );
INVX2TS U1213 ( .A(n1325), .Y(n921) );
INVX4TS U1214 ( .A(n1326), .Y(n922) );
NOR2X4TS U1215 ( .A(shift_value_SHT2_EWR[4]), .B(left_right_SHT2), .Y(n1455)
);
OAI21XLTS U1216 ( .A0(n1342), .A1(n910), .B0(n1263), .Y(n779) );
OAI21XLTS U1217 ( .A0(n1258), .A1(n910), .B0(n1236), .Y(n789) );
OAI211XLTS U1218 ( .A0(n1220), .A1(n910), .B0(n1219), .C0(n1218), .Y(n773)
);
OAI211XLTS U1219 ( .A0(n1215), .A1(n910), .B0(n1214), .C0(n1213), .Y(n774)
);
OAI211XLTS U1220 ( .A0(n1223), .A1(n910), .B0(n1211), .C0(n1210), .Y(n778)
);
OAI211XLTS U1221 ( .A0(n1261), .A1(n910), .B0(n1208), .C0(n1207), .Y(n777)
);
AOI221X1TS U1222 ( .A0(n1576), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1572), .C0(n1104), .Y(n1107) );
OAI21XLTS U1223 ( .A0(n1576), .A1(n1380), .B0(n1061), .Y(n570) );
OAI21XLTS U1224 ( .A0(n1576), .A1(n1093), .B0(n1092), .Y(n733) );
BUFX4TS U1225 ( .A(n1498), .Y(n1491) );
BUFX4TS U1226 ( .A(n1146), .Y(n1149) );
BUFX4TS U1227 ( .A(n1627), .Y(n1624) );
BUFX4TS U1228 ( .A(n1628), .Y(n1619) );
BUFX4TS U1229 ( .A(n1631), .Y(n1620) );
BUFX4TS U1230 ( .A(n1629), .Y(n1621) );
BUFX3TS U1231 ( .A(n917), .Y(n971) );
INVX2TS U1232 ( .A(n893), .Y(n924) );
AOI2BB2X2TS U1233 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1403), .A0N(OP_FLAG_SFG),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1399) );
AOI222X4TS U1234 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n911), .B0(n914), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1254), .C1(DmP_mant_SHT1_SW[21]), .Y(n1266) );
INVX2TS U1235 ( .A(n898), .Y(n925) );
INVX2TS U1236 ( .A(n897), .Y(n926) );
BUFX4TS U1237 ( .A(n1651), .Y(n1409) );
INVX2TS U1238 ( .A(n900), .Y(n927) );
INVX2TS U1239 ( .A(n879), .Y(n928) );
INVX2TS U1240 ( .A(n883), .Y(n929) );
INVX2TS U1241 ( .A(n901), .Y(n930) );
INVX2TS U1242 ( .A(n882), .Y(n931) );
INVX2TS U1243 ( .A(n892), .Y(n932) );
INVX2TS U1244 ( .A(n881), .Y(n933) );
INVX2TS U1245 ( .A(n896), .Y(n934) );
INVX2TS U1246 ( .A(n895), .Y(n935) );
INVX2TS U1247 ( .A(n894), .Y(n936) );
INVX2TS U1248 ( .A(n899), .Y(n937) );
AOI211X1TS U1249 ( .A0(n1176), .A1(n1175), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1182) );
INVX2TS U1250 ( .A(intDY_EWSW[23]), .Y(n938) );
INVX2TS U1251 ( .A(n890), .Y(n939) );
INVX2TS U1252 ( .A(n890), .Y(n940) );
INVX2TS U1253 ( .A(n889), .Y(n941) );
INVX2TS U1254 ( .A(n889), .Y(n942) );
INVX2TS U1255 ( .A(n891), .Y(n943) );
INVX2TS U1256 ( .A(n891), .Y(n944) );
INVX2TS U1257 ( .A(n1184), .Y(n945) );
INVX4TS U1258 ( .A(n1498), .Y(n1493) );
INVX4TS U1259 ( .A(n1498), .Y(n1497) );
INVX3TS U1260 ( .A(n1651), .Y(n1402) );
INVX4TS U1261 ( .A(n1374), .Y(n1509) );
INVX4TS U1262 ( .A(n1374), .Y(n1514) );
INVX2TS U1263 ( .A(n1653), .Y(n947) );
AOI222X4TS U1264 ( .A0(Data_array_SWR[24]), .A1(n1472), .B0(
Data_array_SWR[20]), .B1(n944), .C0(Data_array_SWR[16]), .C1(n942),
.Y(n1415) );
OAI211XLTS U1265 ( .A0(n1248), .A1(n945), .B0(n1247), .C0(n1246), .Y(n782)
);
AOI222X1TS U1266 ( .A0(n1430), .A1(n909), .B0(Data_array_SWR[9]), .B1(n903),
.C0(n1429), .C1(n1454), .Y(n1488) );
AOI222X1TS U1267 ( .A0(n1430), .A1(left_right_SHT2), .B0(Data_array_SWR[9]),
.B1(n940), .C0(n1429), .C1(n1455), .Y(n1499) );
AOI32X1TS U1268 ( .A0(n1592), .A1(n1030), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1536), .Y(n1031) );
AOI221X1TS U1269 ( .A0(n1592), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1536), .C0(n1103), .Y(n1108) );
AOI221X1TS U1270 ( .A0(n1591), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1587), .C0(n1102), .Y(n1109) );
AOI221X1TS U1271 ( .A0(intDX_EWSW[30]), .A1(n1591), .B0(intDX_EWSW[29]),
.B1(n1537), .C0(n989), .Y(n991) );
AOI221X1TS U1272 ( .A0(n876), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1112), .C0(n1111), .Y(n1117) );
AOI221X1TS U1273 ( .A0(n1573), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1568), .C0(n1120), .Y(n1125) );
AOI221X1TS U1274 ( .A0(n1533), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1586), .C0(n1114), .Y(n1115) );
AOI221X1TS U1275 ( .A0(n1575), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1571), .C0(n1113), .Y(n1116) );
OAI31XLTS U1276 ( .A0(n1373), .A1(n1135), .A2(n1382), .B0(n1134), .Y(n720)
);
NOR2X2TS U1277 ( .A(n957), .B(DMP_EXP_EWSW[23]), .Y(n1358) );
XNOR2X2TS U1278 ( .A(DMP_exp_NRM2_EW[0]), .B(n1288), .Y(n1308) );
XNOR2X2TS U1279 ( .A(DMP_exp_NRM2_EW[6]), .B(n979), .Y(n1310) );
XNOR2X2TS U1280 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J49_123_3372_n4), .Y(
n1309) );
NOR2X4TS U1281 ( .A(shift_value_SHT2_EWR[4]), .B(n875), .Y(n1454) );
BUFX4TS U1282 ( .A(n972), .Y(n1639) );
BUFX4TS U1283 ( .A(n971), .Y(n1625) );
BUFX4TS U1284 ( .A(n972), .Y(n1623) );
BUFX4TS U1285 ( .A(n971), .Y(n1641) );
BUFX4TS U1286 ( .A(n972), .Y(n1640) );
BUFX4TS U1287 ( .A(n971), .Y(n1643) );
BUFX3TS U1288 ( .A(n917), .Y(n972) );
AOI2BB2X2TS U1289 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n1407), .A0N(n1407),
.A1N(DmP_mant_SFG_SWR[10]), .Y(intadd_52_B_2_) );
NOR2XLTS U1290 ( .A(n1007), .B(intDY_EWSW[10]), .Y(n1008) );
NOR2X4TS U1291 ( .A(n1412), .B(n1411), .Y(n1428) );
OAI2BB1X2TS U1292 ( .A0N(n1278), .A1N(n1277), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1411) );
AOI22X2TS U1293 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n1405), .B0(n1403), .B1(n963), .Y(intadd_52_B_1_) );
AOI22X2TS U1294 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1405), .B0(n1403), .B1(n966), .Y(intadd_53_B_1_) );
BUFX4TS U1295 ( .A(OP_FLAG_SFG), .Y(n1403) );
AOI222X4TS U1296 ( .A0(DMP_SFG[5]), .A1(n920), .B0(DMP_SFG[5]), .B1(n1284),
.C0(n920), .C1(n1284), .Y(intadd_52_CI) );
AOI222X4TS U1297 ( .A0(DMP_SFG[9]), .A1(n1399), .B0(DMP_SFG[9]), .B1(n1287),
.C0(n1399), .C1(n1287), .Y(intadd_51_B_0_) );
AOI222X1TS U1298 ( .A0(n1449), .A1(n909), .B0(n903), .B1(Data_array_SWR[5]),
.C0(n1450), .C1(n1454), .Y(n1483) );
AOI222X1TS U1299 ( .A0(n1449), .A1(n908), .B0(Data_array_SWR[5]), .B1(n940),
.C0(n1450), .C1(n1455), .Y(n1503) );
AOI222X1TS U1300 ( .A0(n1457), .A1(n875), .B0(n903), .B1(Data_array_SWR[4]),
.C0(n1456), .C1(n1454), .Y(n1482) );
AOI222X1TS U1301 ( .A0(n1457), .A1(n908), .B0(Data_array_SWR[4]), .B1(n940),
.C0(n1456), .C1(n1455), .Y(n1504) );
AOI222X1TS U1302 ( .A0(n1439), .A1(n875), .B0(Data_array_SWR[7]), .B1(n903),
.C0(n1438), .C1(n1454), .Y(n1485) );
AOI222X1TS U1303 ( .A0(n1444), .A1(n909), .B0(Data_array_SWR[6]), .B1(n903),
.C0(n1443), .C1(n1454), .Y(n1484) );
AOI222X1TS U1304 ( .A0(n1444), .A1(left_right_SHT2), .B0(Data_array_SWR[6]),
.B1(n940), .C0(n1443), .C1(n1455), .Y(n1502) );
OAI21XLTS U1305 ( .A0(n1334), .A1(n946), .B0(n1231), .Y(n787) );
AOI222X4TS U1306 ( .A0(Data_array_SWR[23]), .A1(n1472), .B0(
Data_array_SWR[19]), .B1(n944), .C0(Data_array_SWR[15]), .C1(n942),
.Y(n1419) );
AOI222X1TS U1307 ( .A0(n1435), .A1(left_right_SHT2), .B0(Data_array_SWR[8]),
.B1(n940), .C0(n1434), .C1(n1455), .Y(n1500) );
AOI221X1TS U1308 ( .A0(n1590), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1579), .C0(n1096), .Y(n1100) );
NOR2X2TS U1309 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1564), .Y(n1314) );
OAI21X2TS U1310 ( .A0(intDX_EWSW[18]), .A1(n1592), .B0(n1030), .Y(n1103) );
NOR3X1TS U1311 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1304) );
OAI211XLTS U1312 ( .A0(n1245), .A1(n945), .B0(n1244), .C0(n1243), .Y(n784)
);
NOR2X4TS U1313 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1447) );
OAI21XLTS U1314 ( .A0(intDX_EWSW[1]), .A1(n1588), .B0(intDX_EWSW[0]), .Y(
n995) );
OAI211XLTS U1315 ( .A0(intDX_EWSW[8]), .A1(n1589), .B0(n1009), .C0(n1012),
.Y(n1023) );
OAI21XLTS U1316 ( .A0(intDX_EWSW[13]), .A1(n1571), .B0(intDX_EWSW[12]), .Y(
n1006) );
OAI21XLTS U1317 ( .A0(intDX_EWSW[21]), .A1(n1572), .B0(intDX_EWSW[20]), .Y(
n1027) );
OAI21XLTS U1318 ( .A0(intDX_EWSW[3]), .A1(n1568), .B0(intDX_EWSW[2]), .Y(
n998) );
OAI211XLTS U1319 ( .A0(n1568), .A1(intDX_EWSW[3]), .B0(n997), .C0(n996), .Y(
n1000) );
INVX2TS U1320 ( .A(n1613), .Y(n949) );
NOR2XLTS U1321 ( .A(n1560), .B(intDX_EWSW[11]), .Y(n1007) );
OAI21XLTS U1322 ( .A0(intDX_EWSW[15]), .A1(n1586), .B0(intDX_EWSW[14]), .Y(
n1015) );
NOR2XLTS U1323 ( .A(n1028), .B(intDY_EWSW[16]), .Y(n1029) );
NOR2XLTS U1324 ( .A(n1308), .B(exp_rslt_NRM2_EW1[1]), .Y(n976) );
OAI21XLTS U1325 ( .A0(intDX_EWSW[23]), .A1(n938), .B0(intDX_EWSW[22]), .Y(
n1034) );
NOR2XLTS U1326 ( .A(n977), .B(n1309), .Y(n978) );
AOI31XLTS U1327 ( .A0(n1168), .A1(Raw_mant_NRM_SWR[16]), .A2(n1546), .B0(
n1167), .Y(n1169) );
OAI21XLTS U1328 ( .A0(n1518), .A1(n1338), .B0(n1332), .Y(n1333) );
OAI21XLTS U1329 ( .A0(n1523), .A1(n1264), .B0(n1259), .Y(n1260) );
OAI21XLTS U1330 ( .A0(n1596), .A1(n1264), .B0(n1224), .Y(n1225) );
OAI211XLTS U1331 ( .A0(n1351), .A1(n1550), .B0(n1290), .C0(n1161), .Y(n767)
);
OAI21XLTS U1332 ( .A0(n1534), .A1(n1380), .B0(n1053), .Y(n578) );
OAI21XLTS U1333 ( .A0(n1587), .A1(n1093), .B0(n1077), .Y(n736) );
OAI21XLTS U1334 ( .A0(n1568), .A1(n1148), .B0(n1136), .Y(n750) );
OAI211XLTS U1335 ( .A0(n1215), .A1(n945), .B0(n1198), .C0(n1197), .Y(n776)
);
OAI21XLTS U1336 ( .A0(n1331), .A1(n910), .B0(n1227), .Y(n792) );
NOR2XLTS U1337 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n969) );
AOI32X4TS U1338 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n969), .B1(n1564), .Y(n1317)
);
INVX2TS U1339 ( .A(n1317), .Y(n1316) );
INVX1TS U1340 ( .A(DMP_SFG[3]), .Y(intadd_53_A_1_) );
INVX1TS U1341 ( .A(DMP_SFG[4]), .Y(intadd_53_A_2_) );
BUFX3TS U1342 ( .A(n917), .Y(n1632) );
CLKBUFX2TS U1343 ( .A(n918), .Y(n970) );
BUFX3TS U1344 ( .A(n972), .Y(n1633) );
BUFX3TS U1345 ( .A(n971), .Y(n1634) );
BUFX3TS U1346 ( .A(n972), .Y(n1635) );
BUFX3TS U1347 ( .A(n971), .Y(n1636) );
BUFX3TS U1348 ( .A(n972), .Y(n1637) );
BUFX3TS U1349 ( .A(n971), .Y(n1638) );
BUFX3TS U1350 ( .A(n972), .Y(n1626) );
BUFX3TS U1351 ( .A(n917), .Y(n1629) );
BUFX3TS U1352 ( .A(n917), .Y(n1630) );
BUFX3TS U1353 ( .A(n918), .Y(n1631) );
BUFX3TS U1354 ( .A(n971), .Y(n1645) );
BUFX3TS U1355 ( .A(n918), .Y(n1628) );
BUFX3TS U1356 ( .A(n972), .Y(n1622) );
BUFX3TS U1357 ( .A(n972), .Y(n1649) );
BUFX3TS U1358 ( .A(n971), .Y(n1618) );
BUFX3TS U1359 ( .A(n918), .Y(n1627) );
BUFX3TS U1360 ( .A(n971), .Y(n1646) );
BUFX3TS U1361 ( .A(n972), .Y(n1642) );
BUFX3TS U1362 ( .A(n972), .Y(n1648) );
BUFX3TS U1363 ( .A(n971), .Y(n1644) );
BUFX3TS U1364 ( .A(n971), .Y(n1647) );
INVX4TS U1365 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1471) );
AO22XLTS U1366 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1471), .B1(zero_flag), .Y(n552) );
INVX2TS U1367 ( .A(DP_OP_15J49_123_3372_n4), .Y(n973) );
NAND2X1TS U1368 ( .A(n1581), .B(n973), .Y(n979) );
INVX2TS U1369 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n975) );
INVX2TS U1370 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n974) );
INVX2TS U1371 ( .A(n979), .Y(n980) );
NAND2X1TS U1372 ( .A(n1580), .B(n980), .Y(n1275) );
XNOR2X1TS U1373 ( .A(DMP_exp_NRM2_EW[7]), .B(n1275), .Y(n1271) );
NAND2X2TS U1374 ( .A(n1280), .B(Shift_reg_FLAGS_7[0]), .Y(n1311) );
OA22X1TS U1375 ( .A0(n1311), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n757) );
OA22X1TS U1376 ( .A0(n1311), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n760) );
OA22X1TS U1377 ( .A0(n1311), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n759) );
OA22X1TS U1378 ( .A0(n1311), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n758) );
INVX4TS U1379 ( .A(n1376), .Y(busy) );
OAI21XLTS U1380 ( .A0(n947), .A1(n875), .B0(n1387), .Y(n829) );
NOR2X1TS U1381 ( .A(n1584), .B(intDX_EWSW[25]), .Y(n1041) );
AOI22X1TS U1382 ( .A0(intDX_EWSW[25]), .A1(n1584), .B0(intDX_EWSW[24]), .B1(
n983), .Y(n987) );
NOR2X1TS U1383 ( .A(n1591), .B(intDX_EWSW[30]), .Y(n990) );
NOR2X1TS U1384 ( .A(n1537), .B(intDX_EWSW[29]), .Y(n988) );
AOI211X1TS U1385 ( .A0(intDY_EWSW[28]), .A1(n1559), .B0(n990), .C0(n988),
.Y(n1040) );
NOR3X1TS U1386 ( .A(n1559), .B(n988), .C(intDY_EWSW[28]), .Y(n989) );
AOI2BB2X1TS U1387 ( .B0(n992), .B1(n1040), .A0N(n991), .A1N(n990), .Y(n1045)
);
NOR2X1TS U1388 ( .A(n1587), .B(intDX_EWSW[17]), .Y(n1028) );
INVX2TS U1389 ( .A(intDY_EWSW[11]), .Y(n1112) );
OAI22X1TS U1390 ( .A0(n876), .A1(intDX_EWSW[10]), .B0(n1112), .B1(
intDX_EWSW[11]), .Y(n1111) );
INVX2TS U1391 ( .A(n1111), .Y(n1012) );
OAI2BB1X1TS U1392 ( .A0N(n1549), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n993) );
OAI22X1TS U1393 ( .A0(intDY_EWSW[4]), .A1(n993), .B0(n1549), .B1(
intDY_EWSW[5]), .Y(n1004) );
OAI2BB1X1TS U1394 ( .A0N(n1528), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n994) );
OAI22X1TS U1395 ( .A0(intDY_EWSW[6]), .A1(n994), .B0(n1528), .B1(
intDY_EWSW[7]), .Y(n1003) );
OAI2BB2XLTS U1396 ( .B0(intDY_EWSW[0]), .B1(n995), .A0N(intDX_EWSW[1]),
.A1N(n1588), .Y(n997) );
AOI222X1TS U1397 ( .A0(intDY_EWSW[4]), .A1(n1524), .B0(n1000), .B1(n999),
.C0(intDY_EWSW[5]), .C1(n1549), .Y(n1002) );
AOI22X1TS U1398 ( .A0(intDY_EWSW[7]), .A1(n1528), .B0(intDY_EWSW[6]), .B1(
n1553), .Y(n1001) );
OAI32X1TS U1399 ( .A0(n1004), .A1(n1003), .A2(n1002), .B0(n1001), .B1(n1003),
.Y(n1022) );
OA22X1TS U1400 ( .A0(n1533), .A1(intDX_EWSW[14]), .B0(n1586), .B1(
intDX_EWSW[15]), .Y(n1019) );
OAI2BB2XLTS U1401 ( .B0(intDY_EWSW[12]), .B1(n1006), .A0N(intDX_EWSW[13]),
.A1N(n1571), .Y(n1018) );
AOI22X1TS U1402 ( .A0(intDX_EWSW[11]), .A1(n1560), .B0(intDX_EWSW[10]), .B1(
n1008), .Y(n1014) );
AOI21X1TS U1403 ( .A0(n1011), .A1(n1010), .B0(n1021), .Y(n1013) );
OAI2BB2XLTS U1404 ( .B0(n1014), .B1(n1021), .A0N(n1013), .A1N(n1012), .Y(
n1017) );
OAI2BB2XLTS U1405 ( .B0(intDY_EWSW[14]), .B1(n1015), .A0N(intDX_EWSW[15]),
.A1N(n1586), .Y(n1016) );
AOI211X1TS U1406 ( .A0(n1019), .A1(n1018), .B0(n1017), .C0(n1016), .Y(n1020)
);
OAI31X1TS U1407 ( .A0(n1023), .A1(n1022), .A2(n1021), .B0(n1020), .Y(n1026)
);
OA22X1TS U1408 ( .A0(n1535), .A1(intDX_EWSW[22]), .B0(n938), .B1(
intDX_EWSW[23]), .Y(n1038) );
OAI2BB2XLTS U1409 ( .B0(intDY_EWSW[20]), .B1(n1027), .A0N(intDX_EWSW[21]),
.A1N(n1572), .Y(n1037) );
AOI22X1TS U1410 ( .A0(intDX_EWSW[17]), .A1(n1587), .B0(intDX_EWSW[16]), .B1(
n1029), .Y(n1032) );
OAI32X1TS U1411 ( .A0(n1103), .A1(n1033), .A2(n1032), .B0(n1031), .B1(n1033),
.Y(n1036) );
AOI211X1TS U1412 ( .A0(n1038), .A1(n1037), .B0(n1036), .C0(n1035), .Y(n1043)
);
NAND4BBX1TS U1413 ( .AN(n1096), .BN(n1041), .C(n1040), .D(n1039), .Y(n1042)
);
AOI32X1TS U1414 ( .A0(n1045), .A1(n1044), .A2(n1043), .B0(n1042), .B1(n1045),
.Y(n1046) );
AND2X2TS U1415 ( .A(Shift_reg_FLAGS_7_6), .B(n1046), .Y(n1146) );
INVX2TS U1416 ( .A(n1146), .Y(n1131) );
INVX2TS U1417 ( .A(Shift_reg_FLAGS_7_6), .Y(n1049) );
BUFX3TS U1418 ( .A(n1049), .Y(n1091) );
AOI22X1TS U1419 ( .A0(intDX_EWSW[0]), .A1(n1047), .B0(DmP_EXP_EWSW[0]), .B1(
n1091), .Y(n1048) );
BUFX3TS U1420 ( .A(n1145), .Y(n1132) );
AOI22X1TS U1421 ( .A0(intDX_EWSW[14]), .A1(n1047), .B0(DmP_EXP_EWSW[14]),
.B1(n1132), .Y(n1050) );
BUFX3TS U1422 ( .A(n1145), .Y(n1315) );
AOI22X1TS U1423 ( .A0(intDX_EWSW[22]), .A1(n1047), .B0(DmP_EXP_EWSW[22]),
.B1(n1315), .Y(n1051) );
AOI22X1TS U1424 ( .A0(intDX_EWSW[19]), .A1(n1047), .B0(DmP_EXP_EWSW[19]),
.B1(n1315), .Y(n1052) );
AOI22X1TS U1425 ( .A0(intDX_EWSW[16]), .A1(n873), .B0(DmP_EXP_EWSW[16]),
.B1(n1315), .Y(n1053) );
AOI22X1TS U1426 ( .A0(intDX_EWSW[5]), .A1(n873), .B0(DmP_EXP_EWSW[5]), .B1(
n1132), .Y(n1054) );
AOI22X1TS U1427 ( .A0(intDX_EWSW[6]), .A1(n873), .B0(DmP_EXP_EWSW[6]), .B1(
n1132), .Y(n1055) );
AOI22X1TS U1428 ( .A0(intDX_EWSW[4]), .A1(n873), .B0(DmP_EXP_EWSW[4]), .B1(
n1132), .Y(n1056) );
AOI22X1TS U1429 ( .A0(intDX_EWSW[17]), .A1(n873), .B0(DmP_EXP_EWSW[17]),
.B1(n1315), .Y(n1057) );
AOI22X1TS U1430 ( .A0(intDX_EWSW[21]), .A1(n873), .B0(DmP_EXP_EWSW[21]),
.B1(n1315), .Y(n1058) );
AOI22X1TS U1431 ( .A0(intDX_EWSW[13]), .A1(n873), .B0(DmP_EXP_EWSW[13]),
.B1(n1315), .Y(n1059) );
AOI22X1TS U1432 ( .A0(intDX_EWSW[10]), .A1(n873), .B0(DmP_EXP_EWSW[10]),
.B1(n1091), .Y(n1060) );
AOI22X1TS U1433 ( .A0(intDX_EWSW[20]), .A1(n873), .B0(DmP_EXP_EWSW[20]),
.B1(n1315), .Y(n1061) );
AOI22X1TS U1434 ( .A0(intDX_EWSW[9]), .A1(n873), .B0(DmP_EXP_EWSW[9]), .B1(
n1132), .Y(n1062) );
BUFX3TS U1435 ( .A(n873), .Y(n1150) );
AOI22X1TS U1436 ( .A0(intDX_EWSW[7]), .A1(n1150), .B0(DmP_EXP_EWSW[7]), .B1(
n1132), .Y(n1063) );
AOI22X1TS U1437 ( .A0(intDX_EWSW[18]), .A1(n1150), .B0(DmP_EXP_EWSW[18]),
.B1(n1315), .Y(n1064) );
AOI22X1TS U1438 ( .A0(intDX_EWSW[1]), .A1(n1150), .B0(DmP_EXP_EWSW[1]), .B1(
n1132), .Y(n1065) );
AOI22X1TS U1439 ( .A0(intDX_EWSW[12]), .A1(n1150), .B0(DmP_EXP_EWSW[12]),
.B1(n1132), .Y(n1066) );
AOI22X1TS U1440 ( .A0(intDX_EWSW[8]), .A1(n1150), .B0(DmP_EXP_EWSW[8]), .B1(
n1132), .Y(n1067) );
AOI22X1TS U1441 ( .A0(intDX_EWSW[2]), .A1(n1150), .B0(DmP_EXP_EWSW[2]), .B1(
n1132), .Y(n1068) );
AOI22X1TS U1442 ( .A0(intDX_EWSW[11]), .A1(n1150), .B0(DmP_EXP_EWSW[11]),
.B1(n1132), .Y(n1069) );
AOI22X1TS U1443 ( .A0(intDX_EWSW[3]), .A1(n1150), .B0(DmP_EXP_EWSW[3]), .B1(
n1132), .Y(n1070) );
AOI22X1TS U1444 ( .A0(DmP_EXP_EWSW[27]), .A1(n1315), .B0(intDX_EWSW[27]),
.B1(n1150), .Y(n1071) );
AOI22X1TS U1445 ( .A0(intDX_EWSW[15]), .A1(n1047), .B0(DmP_EXP_EWSW[15]),
.B1(n1315), .Y(n1072) );
BUFX3TS U1446 ( .A(n1146), .Y(n1137) );
AOI22X1TS U1447 ( .A0(intDX_EWSW[18]), .A1(n1149), .B0(DMP_EXP_EWSW[18]),
.B1(n1091), .Y(n1074) );
AOI22X1TS U1448 ( .A0(intDX_EWSW[22]), .A1(n1149), .B0(DMP_EXP_EWSW[22]),
.B1(n1091), .Y(n1075) );
AOI22X1TS U1449 ( .A0(intDX_EWSW[12]), .A1(n1149), .B0(DMP_EXP_EWSW[12]),
.B1(n1145), .Y(n1076) );
AOI22X1TS U1450 ( .A0(intDX_EWSW[17]), .A1(n1137), .B0(DMP_EXP_EWSW[17]),
.B1(n1091), .Y(n1077) );
AOI22X1TS U1451 ( .A0(intDX_EWSW[14]), .A1(n1149), .B0(DMP_EXP_EWSW[14]),
.B1(n1145), .Y(n1078) );
AOI22X1TS U1452 ( .A0(intDX_EWSW[21]), .A1(n1149), .B0(DMP_EXP_EWSW[21]),
.B1(n1091), .Y(n1079) );
AOI22X1TS U1453 ( .A0(intDX_EWSW[13]), .A1(n1149), .B0(DMP_EXP_EWSW[13]),
.B1(n1145), .Y(n1080) );
AOI22X1TS U1454 ( .A0(intDX_EWSW[15]), .A1(n1149), .B0(DMP_EXP_EWSW[15]),
.B1(n1145), .Y(n1081) );
AOI22X1TS U1455 ( .A0(intDX_EWSW[28]), .A1(n1137), .B0(DMP_EXP_EWSW[28]),
.B1(n1091), .Y(n1082) );
AOI22X1TS U1456 ( .A0(n937), .A1(n1315), .B0(intDX_EWSW[27]), .B1(n1137),
.Y(n1083) );
AOI22X1TS U1457 ( .A0(intDX_EWSW[29]), .A1(n1137), .B0(DMP_EXP_EWSW[29]),
.B1(n1091), .Y(n1084) );
AOI22X1TS U1458 ( .A0(intDX_EWSW[30]), .A1(n1149), .B0(DMP_EXP_EWSW[30]),
.B1(n1091), .Y(n1085) );
AOI22X1TS U1459 ( .A0(intDX_EWSW[1]), .A1(n1149), .B0(DMP_EXP_EWSW[1]), .B1(
n1049), .Y(n1086) );
AOI22X1TS U1460 ( .A0(intDX_EWSW[0]), .A1(n1137), .B0(DMP_EXP_EWSW[0]), .B1(
n1049), .Y(n1087) );
AOI22X1TS U1461 ( .A0(intDX_EWSW[19]), .A1(n1137), .B0(DMP_EXP_EWSW[19]),
.B1(n1091), .Y(n1088) );
AOI22X1TS U1462 ( .A0(intDX_EWSW[16]), .A1(n1137), .B0(DMP_EXP_EWSW[16]),
.B1(n1091), .Y(n1089) );
AOI22X1TS U1463 ( .A0(intDX_EWSW[11]), .A1(n1149), .B0(DMP_EXP_EWSW[11]),
.B1(n1091), .Y(n1090) );
AOI22X1TS U1464 ( .A0(intDX_EWSW[20]), .A1(n1137), .B0(DMP_EXP_EWSW[20]),
.B1(n1091), .Y(n1092) );
AOI22X1TS U1465 ( .A0(DMP_EXP_EWSW[23]), .A1(n1315), .B0(intDX_EWSW[23]),
.B1(n1137), .Y(n1094) );
OAI22X1TS U1466 ( .A0(n1588), .A1(intDX_EWSW[1]), .B0(n1584), .B1(
intDX_EWSW[25]), .Y(n1095) );
AOI221X1TS U1467 ( .A0(n1588), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1584), .C0(n1095), .Y(n1101) );
OAI22X1TS U1468 ( .A0(n1578), .A1(intDX_EWSW[28]), .B0(n1537), .B1(
intDX_EWSW[29]), .Y(n1097) );
AOI221X1TS U1469 ( .A0(n1578), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1537), .C0(n1097), .Y(n1099) );
AOI2BB2XLTS U1470 ( .B0(intDX_EWSW[7]), .B1(n1577), .A0N(n1577), .A1N(
intDX_EWSW[7]), .Y(n1098) );
NAND4XLTS U1471 ( .A(n1101), .B(n1100), .C(n1099), .D(n1098), .Y(n1130) );
OAI22X1TS U1472 ( .A0(n1591), .A1(intDX_EWSW[30]), .B0(n1587), .B1(
intDX_EWSW[17]), .Y(n1102) );
OAI22X1TS U1473 ( .A0(n1576), .A1(intDX_EWSW[20]), .B0(n1572), .B1(
intDX_EWSW[21]), .Y(n1104) );
OAI22X1TS U1474 ( .A0(n1535), .A1(intDX_EWSW[22]), .B0(n938), .B1(
intDX_EWSW[23]), .Y(n1105) );
NAND4XLTS U1475 ( .A(n1109), .B(n1108), .C(n1107), .D(n1106), .Y(n1129) );
OAI22X1TS U1476 ( .A0(n1519), .A1(intDX_EWSW[24]), .B0(n1570), .B1(
intDX_EWSW[9]), .Y(n1110) );
AOI221X1TS U1477 ( .A0(n1519), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1570), .C0(n1110), .Y(n1118) );
OAI22X1TS U1478 ( .A0(n1575), .A1(intDX_EWSW[12]), .B0(n1571), .B1(
intDX_EWSW[13]), .Y(n1113) );
OAI22X1TS U1479 ( .A0(n1533), .A1(intDX_EWSW[14]), .B0(n1586), .B1(
intDX_EWSW[15]), .Y(n1114) );
NAND4XLTS U1480 ( .A(n1118), .B(n1117), .C(n1116), .D(n1115), .Y(n1128) );
OAI22X1TS U1481 ( .A0(n1534), .A1(intDX_EWSW[16]), .B0(n1585), .B1(
intDX_EWSW[0]), .Y(n1119) );
AOI221X1TS U1482 ( .A0(n1534), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1585), .C0(n1119), .Y(n1126) );
OAI22X1TS U1483 ( .A0(n1573), .A1(intDX_EWSW[2]), .B0(n1568), .B1(
intDX_EWSW[3]), .Y(n1120) );
OAI22X1TS U1484 ( .A0(n1574), .A1(intDX_EWSW[4]), .B0(n1532), .B1(
intDX_EWSW[5]), .Y(n1121) );
AOI221X1TS U1485 ( .A0(n1574), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1532), .C0(n1121), .Y(n1124) );
OAI22X1TS U1486 ( .A0(n1589), .A1(intDX_EWSW[8]), .B0(n1569), .B1(
intDX_EWSW[6]), .Y(n1122) );
AOI221X1TS U1487 ( .A0(n1589), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1569), .C0(n1122), .Y(n1123) );
NAND4XLTS U1488 ( .A(n1126), .B(n1125), .C(n1124), .D(n1123), .Y(n1127) );
NOR4X1TS U1489 ( .A(n1130), .B(n1129), .C(n1128), .D(n1127), .Y(n1373) );
CLKXOR2X2TS U1490 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1371) );
INVX2TS U1491 ( .A(n1371), .Y(n1135) );
AOI22X1TS U1492 ( .A0(intDX_EWSW[31]), .A1(n1133), .B0(SIGN_FLAG_EXP), .B1(
n1132), .Y(n1134) );
INVX2TS U1493 ( .A(n873), .Y(n1148) );
AOI22X1TS U1494 ( .A0(intDX_EWSW[3]), .A1(n1137), .B0(DMP_EXP_EWSW[3]), .B1(
n1145), .Y(n1136) );
AOI22X1TS U1495 ( .A0(intDX_EWSW[8]), .A1(n1137), .B0(DMP_EXP_EWSW[8]), .B1(
n1145), .Y(n1138) );
AOI22X1TS U1496 ( .A0(intDX_EWSW[7]), .A1(n1149), .B0(DMP_EXP_EWSW[7]), .B1(
n1145), .Y(n1139) );
AOI22X1TS U1497 ( .A0(intDX_EWSW[6]), .A1(n1149), .B0(DMP_EXP_EWSW[6]), .B1(
n1145), .Y(n1140) );
AOI22X1TS U1498 ( .A0(intDX_EWSW[9]), .A1(n1149), .B0(DMP_EXP_EWSW[9]), .B1(
n1145), .Y(n1141) );
AOI22X1TS U1499 ( .A0(intDX_EWSW[2]), .A1(n1149), .B0(DMP_EXP_EWSW[2]), .B1(
n1145), .Y(n1142) );
AOI22X1TS U1500 ( .A0(intDX_EWSW[4]), .A1(n1149), .B0(DMP_EXP_EWSW[4]), .B1(
n1145), .Y(n1143) );
AOI22X1TS U1501 ( .A0(intDX_EWSW[5]), .A1(n1146), .B0(DMP_EXP_EWSW[5]), .B1(
n1145), .Y(n1144) );
AOI22X1TS U1502 ( .A0(intDX_EWSW[10]), .A1(n1146), .B0(DMP_EXP_EWSW[10]),
.B1(n1145), .Y(n1147) );
AOI222X1TS U1503 ( .A0(n1150), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1049), .C0(intDY_EWSW[23]), .C1(n1137), .Y(n1151) );
INVX2TS U1504 ( .A(n1151), .Y(n564) );
NAND2X2TS U1505 ( .A(n906), .B(n916), .Y(n1351) );
NOR2BX2TS U1506 ( .AN(n1304), .B(n1303), .Y(n1168) );
NOR2BX1TS U1507 ( .AN(n1168), .B(Raw_mant_NRM_SWR[18]), .Y(n1291) );
NOR2BX1TS U1508 ( .AN(n1291), .B(n1292), .Y(n1165) );
NOR2X2TS U1509 ( .A(Raw_mant_NRM_SWR[13]), .B(n1293), .Y(n1177) );
NOR2X2TS U1510 ( .A(Raw_mant_NRM_SWR[12]), .B(n1170), .Y(n1298) );
NAND2X1TS U1511 ( .A(n1298), .B(n1525), .Y(n1152) );
NOR2X1TS U1512 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1154)
);
NOR3X1TS U1513 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1152),
.Y(n1155) );
OAI22X1TS U1514 ( .A0(n1153), .A1(n1152), .B0(n1154), .B1(n1162), .Y(n1160)
);
NOR2X1TS U1515 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1157)
);
NOR2X2TS U1516 ( .A(Raw_mant_NRM_SWR[6]), .B(n1162), .Y(n1299) );
NAND2X1TS U1517 ( .A(n1299), .B(n1154), .Y(n1158) );
OAI21X1TS U1518 ( .A0(n1157), .A1(n1158), .B0(n1156), .Y(n1181) );
INVX2TS U1519 ( .A(n1158), .Y(n1300) );
OAI31X1TS U1520 ( .A0(n1160), .A1(n1181), .A2(n1159), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1290) );
NAND3XLTS U1521 ( .A(n947), .B(Shift_amount_SHT1_EWR[4]), .C(n1387), .Y(
n1161) );
INVX2TS U1522 ( .A(n1162), .Y(n1172) );
AOI22X1TS U1523 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1168), .B0(n1298), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1178) );
OAI32X1TS U1524 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1529), .B0(n1551), .B1(Raw_mant_NRM_SWR[3]), .Y(n1163) );
NAND2X1TS U1525 ( .A(Raw_mant_NRM_SWR[12]), .B(n1177), .Y(n1295) );
NAND2X1TS U1526 ( .A(Raw_mant_NRM_SWR[14]), .B(n1165), .Y(n1183) );
AOI32X1TS U1527 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1515), .A2(n1548), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1515), .Y(n1166) );
OAI31X1TS U1528 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1170), .A2(n1530), .B0(
n1169), .Y(n1171) );
NAND2X2TS U1529 ( .A(n907), .B(n1187), .Y(n1338) );
NOR2BX1TS U1530 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1194) );
BUFX3TS U1531 ( .A(n1194), .Y(n1335) );
AOI22X1TS U1532 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n912), .B0(n1335), .B1(n936), .Y(n1193) );
NOR2X1TS U1533 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1174) );
AOI32X1TS U1534 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1174), .A2(n1173), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1174), .Y(n1175) );
INVX2TS U1535 ( .A(n1177), .Y(n1179) );
OAI31X1TS U1536 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1518), .A2(n1179), .B0(
n1178), .Y(n1180) );
NOR4BX2TS U1537 ( .AN(n1183), .B(n1182), .C(n1181), .D(n1180), .Y(n1205) );
NOR2X1TS U1538 ( .A(n1205), .B(n906), .Y(n1307) );
AOI21X1TS U1539 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n906), .B0(n1307), .Y(
n1186) );
BUFX3TS U1540 ( .A(n1185), .Y(n1348) );
NOR2X2TS U1541 ( .A(n1185), .B(n1186), .Y(n1345) );
NOR2X4TS U1542 ( .A(n1187), .B(n906), .Y(n1336) );
AOI22X1TS U1543 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1336), .B0(n1335), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1189) );
AOI22X1TS U1544 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n911), .B0(n913), .B1(n935),
.Y(n1188) );
NAND2X1TS U1545 ( .A(n1189), .B(n1188), .Y(n1212) );
AOI22X1TS U1546 ( .A0(n1348), .A1(Data_array_SWR[1]), .B0(n1345), .B1(n1212),
.Y(n1192) );
NAND2X1TS U1547 ( .A(n1205), .B(n1336), .Y(n1190) );
INVX2TS U1548 ( .A(n1269), .Y(n1343) );
NAND2X1TS U1549 ( .A(Raw_mant_NRM_SWR[23]), .B(n1343), .Y(n1191) );
BUFX3TS U1550 ( .A(n1194), .Y(n1254) );
AOI22X1TS U1551 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1336), .B0(n1335), .B1(
n933), .Y(n1196) );
AOI22X1TS U1552 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n911), .B0(n913), .B1(n934),
.Y(n1195) );
NAND2X1TS U1553 ( .A(n1196), .B(n1195), .Y(n1209) );
AOI22X1TS U1554 ( .A0(n1348), .A1(Data_array_SWR[5]), .B0(n1345), .B1(n1209),
.Y(n1198) );
NAND2X1TS U1555 ( .A(Raw_mant_NRM_SWR[19]), .B(n1343), .Y(n1197) );
AOI22X1TS U1556 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1336), .B0(n1335), .B1(
n934), .Y(n1200) );
AOI22X1TS U1557 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n911), .B0(n913), .B1(n929),
.Y(n1199) );
NAND2X1TS U1558 ( .A(n1200), .B(n1199), .Y(n1204) );
AOI22X1TS U1559 ( .A0(n1348), .A1(Data_array_SWR[4]), .B0(n1345), .B1(n1204),
.Y(n1202) );
NAND2X1TS U1560 ( .A(Raw_mant_NRM_SWR[20]), .B(n1343), .Y(n1201) );
INVX2TS U1561 ( .A(n1345), .Y(n1203) );
AOI22X1TS U1562 ( .A0(n1348), .A1(Data_array_SWR[6]), .B0(n1184), .B1(n1204),
.Y(n1208) );
INVX2TS U1563 ( .A(n1336), .Y(n1264) );
NAND2X1TS U1564 ( .A(Raw_mant_NRM_SWR[16]), .B(n1206), .Y(n1207) );
AOI22X1TS U1565 ( .A0(n1348), .A1(Data_array_SWR[7]), .B0(n1184), .B1(n1209),
.Y(n1211) );
NAND2X1TS U1566 ( .A(Raw_mant_NRM_SWR[15]), .B(n1206), .Y(n1210) );
AOI22X1TS U1567 ( .A0(n1348), .A1(Data_array_SWR[3]), .B0(n1184), .B1(n1212),
.Y(n1214) );
NAND2X1TS U1568 ( .A(Raw_mant_NRM_SWR[19]), .B(n1206), .Y(n1213) );
AOI22X1TS U1569 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1336), .B0(n1335), .B1(
n935), .Y(n1217) );
AOI22X1TS U1570 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n911), .B0(n913), .B1(n936),
.Y(n1216) );
NAND2X1TS U1571 ( .A(n1217), .B(n1216), .Y(n1344) );
AOI22X1TS U1572 ( .A0(n1348), .A1(Data_array_SWR[2]), .B0(n1184), .B1(n1344),
.Y(n1219) );
NAND2X1TS U1573 ( .A(Raw_mant_NRM_SWR[20]), .B(n1206), .Y(n1218) );
AOI22X1TS U1574 ( .A0(n1348), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1206), .Y(n1222) );
AOI22X1TS U1575 ( .A0(n913), .A1(DmP_mant_SHT1_SW[21]), .B0(n1335), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1224) );
AOI21X1TS U1576 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n912), .B0(n1225), .Y(n1331)
);
OAI22X1TS U1577 ( .A0(n1250), .A1(n945), .B0(n1593), .B1(n1269), .Y(n1226)
);
AOI21X1TS U1578 ( .A0(n1185), .A1(Data_array_SWR[21]), .B0(n1226), .Y(n1227)
);
AOI22X1TS U1579 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1336), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1335), .Y(n1228) );
AOI21X1TS U1580 ( .A0(n930), .A1(n914), .B0(n1229), .Y(n1334) );
INVX2TS U1581 ( .A(n1206), .Y(n1255) );
OAI22X1TS U1582 ( .A0(n1234), .A1(n1203), .B0(n1541), .B1(n1255), .Y(n1230)
);
AOI21X1TS U1583 ( .A0(n1185), .A1(Data_array_SWR[16]), .B0(n1230), .Y(n1231)
);
AOI22X1TS U1584 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1336), .B0(n1335), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1232) );
AOI21X1TS U1585 ( .A0(n914), .A1(DmP_mant_SHT1_SW[18]), .B0(n1233), .Y(n1258) );
OAI22X1TS U1586 ( .A0(n1234), .A1(n945), .B0(n1541), .B1(n1269), .Y(n1235)
);
AOI21X1TS U1587 ( .A0(n1185), .A1(Data_array_SWR[18]), .B0(n1235), .Y(n1236)
);
AOI22X1TS U1588 ( .A0(n1185), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1206), .Y(n1238) );
OA22X1TS U1589 ( .A0(n1542), .A1(n1269), .B0(n1241), .B1(n1203), .Y(n1237)
);
AOI22X1TS U1590 ( .A0(n1348), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1206), .Y(n1240) );
OA22X1TS U1591 ( .A0(n1527), .A1(n1269), .B0(n1253), .B1(n1203), .Y(n1239)
);
AOI22X1TS U1592 ( .A0(n1348), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1206), .Y(n1244) );
OA22X1TS U1593 ( .A0(n1518), .A1(n1269), .B0(n1242), .B1(n1203), .Y(n1243)
);
AOI22X1TS U1594 ( .A0(n1348), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1206), .Y(n1247) );
OA22X1TS U1595 ( .A0(n1540), .A1(n1269), .B0(n1245), .B1(n1203), .Y(n1246)
);
AOI22X1TS U1596 ( .A0(n1185), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1206), .Y(n1252) );
OA22X1TS U1597 ( .A0(n1552), .A1(n1269), .B0(n1250), .B1(n1203), .Y(n1251)
);
OAI22X1TS U1598 ( .A0(n1266), .A1(n1203), .B0(n1551), .B1(n1255), .Y(n1256)
);
AOI21X1TS U1599 ( .A0(n1185), .A1(Data_array_SWR[20]), .B0(n1256), .Y(n1257)
);
AOI22X1TS U1600 ( .A0(n913), .A1(DmP_mant_SHT1_SW[8]), .B0(n1335), .B1(n932),
.Y(n1259) );
AOI21X1TS U1601 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n912), .B0(n1260), .Y(n1342) );
OAI22X1TS U1602 ( .A0(n1261), .A1(n945), .B0(n1517), .B1(n1269), .Y(n1262)
);
AOI21X1TS U1603 ( .A0(n1185), .A1(Data_array_SWR[8]), .B0(n1262), .Y(n1263)
);
OAI22X1TS U1604 ( .A0(n1596), .A1(n1338), .B0(n1529), .B1(n1264), .Y(n1265)
);
OAI22X1TS U1605 ( .A0(n1329), .A1(n1203), .B0(n1266), .B1(n945), .Y(n1267)
);
AOI21X1TS U1606 ( .A0(n1185), .A1(Data_array_SWR[22]), .B0(n1267), .Y(n1268)
);
AOI22X1TS U1607 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n1403), .B0(n1407), .B1(n960), .Y(n1391) );
NAND2X1TS U1608 ( .A(n1391), .B(DMP_SFG[0]), .Y(n1394) );
INVX2TS U1609 ( .A(n1394), .Y(n1270) );
INVX2TS U1610 ( .A(n1271), .Y(n1279) );
AND4X1TS U1611 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1308), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1272) );
INVX2TS U1612 ( .A(n1275), .Y(n1276) );
OAI2BB2XLTS U1613 ( .B0(n1411), .B1(n1279), .A0N(n872), .A1N(
final_result_ieee[30]), .Y(n754) );
INVX2TS U1614 ( .A(n1280), .Y(n1412) );
OAI2BB2XLTS U1615 ( .B0(n1281), .B1(n1411), .A0N(n872), .A1N(
final_result_ieee[31]), .Y(n543) );
INVX4TS U1616 ( .A(OP_FLAG_SFG), .Y(n1405) );
AOI22X1TS U1617 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1407), .B0(n1403), .B1(n962), .Y(intadd_53_B_0_) );
AOI21X1TS U1618 ( .A0(intadd_53_A_1_), .A1(intadd_53_B_1_), .B0(
intadd_53_B_0_), .Y(n1282) );
AOI2BB2X1TS U1619 ( .B0(DMP_SFG[2]), .B1(n1282), .A0N(intadd_53_A_1_), .A1N(
intadd_53_B_1_), .Y(n1283) );
AOI222X1TS U1620 ( .A0(n1283), .A1(intadd_53_A_2_), .B0(n1283), .B1(n923),
.C0(intadd_53_A_2_), .C1(n923), .Y(n1284) );
AOI22X1TS U1621 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n1405), .B0(n1403), .B1(n964), .Y(intadd_52_B_0_) );
AOI21X1TS U1622 ( .A0(intadd_52_A_1_), .A1(intadd_52_B_1_), .B0(
intadd_52_B_0_), .Y(n1285) );
AOI2BB2X1TS U1623 ( .B0(DMP_SFG[6]), .B1(n1285), .A0N(intadd_52_A_1_), .A1N(
intadd_52_B_1_), .Y(n1286) );
AOI222X1TS U1624 ( .A0(n1286), .A1(intadd_52_A_2_), .B0(n1286), .B1(
intadd_52_B_2_), .C0(intadd_52_A_2_), .C1(intadd_52_B_2_), .Y(n1287)
);
INVX2TS U1625 ( .A(n1288), .Y(n1289) );
NAND2X1TS U1626 ( .A(n1554), .B(n1289), .Y(DP_OP_15J49_123_3372_n8) );
MX2X1TS U1627 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n611) );
MX2X1TS U1628 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n907),
.Y(n616) );
MX2X1TS U1629 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n621) );
MX2X1TS U1630 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n626) );
MX2X1TS U1631 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n631) );
MX2X1TS U1632 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n636) );
MX2X1TS U1633 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n641) );
MX2X1TS U1634 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n907),
.Y(n646) );
OAI2BB1X1TS U1635 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n877), .B0(n1290), .Y(
n512) );
OAI32X1TS U1636 ( .A0(n1387), .A1(Raw_mant_NRM_SWR[14]), .A2(n1292), .B0(
n1291), .B1(n1387), .Y(n1296) );
AOI21X1TS U1637 ( .A0(n1298), .A1(Raw_mant_NRM_SWR[10]), .B0(n1297), .Y(
n1353) );
AOI22X1TS U1638 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1300), .B0(n1299), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1302) );
OAI211XLTS U1639 ( .A0(n1304), .A1(n1303), .B0(n1302), .C0(n1301), .Y(n1305)
);
OAI21X1TS U1640 ( .A0(n1306), .A1(n1305), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1349) );
OAI2BB1X1TS U1641 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1387), .B0(n1349),
.Y(n514) );
OA22X1TS U1642 ( .A0(n1311), .A1(n1308), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n761) );
OA22X1TS U1643 ( .A0(n1311), .A1(n1309), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n756) );
OA22X1TS U1644 ( .A0(n1311), .A1(n1310), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n755) );
OA21XLTS U1645 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1411),
.Y(n558) );
INVX2TS U1646 ( .A(n1314), .Y(n1313) );
AOI22X1TS U1647 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1313), .B1(n1531), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1648 ( .A(n1313), .B(n1312), .Y(n871) );
AOI22X1TS U1649 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1314), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1531), .Y(n1318) );
AO22XLTS U1650 ( .A0(n1316), .A1(Shift_reg_FLAGS_7_6), .B0(n1317), .B1(n1318), .Y(n869) );
AOI22X1TS U1651 ( .A0(n1317), .A1(n1315), .B0(n1613), .B1(n1316), .Y(n868)
);
AOI22X1TS U1652 ( .A0(n1317), .A1(n1613), .B0(n916), .B1(n1316), .Y(n867) );
CLKBUFX2TS U1653 ( .A(n1651), .Y(n1392) );
AOI22X1TS U1654 ( .A0(n1317), .A1(n1651), .B0(n1387), .B1(n1316), .Y(n864)
);
AOI22X1TS U1655 ( .A0(n1317), .A1(n1387), .B0(n872), .B1(n1316), .Y(n863) );
AND2X2TS U1656 ( .A(beg_OP), .B(n1318), .Y(n1321) );
INVX2TS U1657 ( .A(n1325), .Y(n1319) );
BUFX3TS U1658 ( .A(n1321), .Y(n1325) );
INVX2TS U1659 ( .A(n1325), .Y(n1320) );
BUFX3TS U1660 ( .A(n1321), .Y(n1328) );
BUFX3TS U1661 ( .A(n1321), .Y(n1323) );
INVX2TS U1662 ( .A(n1325), .Y(n1327) );
INVX2TS U1663 ( .A(n1325), .Y(n1322) );
INVX2TS U1664 ( .A(n1325), .Y(n1324) );
AOI21X1TS U1665 ( .A0(n912), .A1(Raw_mant_NRM_SWR[0]), .B0(n914), .Y(n1330)
);
OAI2BB2XLTS U1666 ( .B0(n1330), .B1(n946), .A0N(n1185), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI2BB2XLTS U1667 ( .B0(n1329), .B1(n946), .A0N(n1185), .A1N(
Data_array_SWR[24]), .Y(n795) );
AOI22X1TS U1668 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1336), .B0(n1335), .B1(
n928), .Y(n1332) );
AOI21X1TS U1669 ( .A0(n914), .A1(n927), .B0(n1333), .Y(n1340) );
AOI22X1TS U1670 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1336), .B0(n1335), .B1(
n931), .Y(n1337) );
AOI21X1TS U1671 ( .A0(n914), .A1(DmP_mant_SHT1_SW[10]), .B0(n1339), .Y(n1341) );
AOI22X1TS U1672 ( .A0(n1348), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1343), .Y(n1347) );
AOI22X1TS U1673 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n912), .B0(n1345), .B1(
n1344), .Y(n1346) );
NAND2X1TS U1674 ( .A(n1347), .B(n1346), .Y(n771) );
NAND2X1TS U1675 ( .A(n1350), .B(n1349), .Y(n770) );
AOI21X1TS U1676 ( .A0(n947), .A1(Shift_amount_SHT1_EWR[3]), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1352) );
OAI22X1TS U1677 ( .A0(n1353), .A1(n1352), .B0(n1351), .B1(n1547), .Y(n769)
);
INVX2TS U1678 ( .A(n1613), .Y(n1375) );
AOI21X1TS U1679 ( .A0(DMP_EXP_EWSW[23]), .A1(n957), .B0(n1358), .Y(n1354) );
AOI2BB2XLTS U1680 ( .B0(n1375), .B1(n1354), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1375), .Y(n766) );
NOR2X1TS U1681 ( .A(n1538), .B(DMP_EXP_EWSW[24]), .Y(n1357) );
AOI21X1TS U1682 ( .A0(DMP_EXP_EWSW[24]), .A1(n1538), .B0(n1357), .Y(n1355)
);
XNOR2X1TS U1683 ( .A(n1358), .B(n1355), .Y(n1356) );
AO22XLTS U1684 ( .A0(n1375), .A1(n1356), .B0(n1613), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
OAI22X1TS U1685 ( .A0(n1358), .A1(n1357), .B0(DmP_EXP_EWSW[24]), .B1(n1539),
.Y(n1361) );
NAND2X1TS U1686 ( .A(DmP_EXP_EWSW[25]), .B(n1597), .Y(n1362) );
OAI21XLTS U1687 ( .A0(DmP_EXP_EWSW[25]), .A1(n1597), .B0(n1362), .Y(n1359)
);
XNOR2X1TS U1688 ( .A(n1361), .B(n1359), .Y(n1360) );
AO22XLTS U1689 ( .A0(n1375), .A1(n1360), .B0(n1385), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AOI22X1TS U1690 ( .A0(DMP_EXP_EWSW[25]), .A1(n1610), .B0(n1362), .B1(n1361),
.Y(n1365) );
NOR2X1TS U1691 ( .A(n1605), .B(DMP_EXP_EWSW[26]), .Y(n1366) );
AOI21X1TS U1692 ( .A0(DMP_EXP_EWSW[26]), .A1(n1605), .B0(n1366), .Y(n1363)
);
XNOR2X1TS U1693 ( .A(n1365), .B(n1363), .Y(n1364) );
AO22XLTS U1694 ( .A0(n1375), .A1(n1364), .B0(n1377), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
OAI22X1TS U1695 ( .A0(n1366), .A1(n1365), .B0(DmP_EXP_EWSW[26]), .B1(n1609),
.Y(n1368) );
XNOR2X1TS U1696 ( .A(DmP_EXP_EWSW[27]), .B(n937), .Y(n1367) );
XOR2XLTS U1697 ( .A(n1368), .B(n1367), .Y(n1369) );
AO22XLTS U1698 ( .A0(n1375), .A1(n1369), .B0(n1378), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
OAI222X1TS U1699 ( .A0(n1380), .A1(n1608), .B0(n1539), .B1(
Shift_reg_FLAGS_7_6), .C0(n1519), .C1(n1382), .Y(n729) );
OAI222X1TS U1700 ( .A0(n1380), .A1(n1543), .B0(n1597), .B1(
Shift_reg_FLAGS_7_6), .C0(n1584), .C1(n1382), .Y(n728) );
OAI222X1TS U1701 ( .A0(n1380), .A1(n1544), .B0(n1609), .B1(
Shift_reg_FLAGS_7_6), .C0(n1590), .C1(n1382), .Y(n727) );
OAI21XLTS U1702 ( .A0(n1371), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1370) );
AOI21X1TS U1703 ( .A0(n1371), .A1(intDX_EWSW[31]), .B0(n1370), .Y(n1372) );
AO21XLTS U1704 ( .A0(OP_FLAG_EXP), .A1(n1049), .B0(n1372), .Y(n722) );
AO22XLTS U1705 ( .A0(n1375), .A1(DMP_EXP_EWSW[0]), .B0(n1379), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1706 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1376), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
BUFX3TS U1707 ( .A(n1374), .Y(n1498) );
AO22XLTS U1708 ( .A0(n1375), .A1(DMP_EXP_EWSW[1]), .B0(n1385), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1709 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n916), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1710 ( .A0(n1375), .A1(DMP_EXP_EWSW[2]), .B0(n1377), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1711 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1376), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
BUFX3TS U1712 ( .A(n1498), .Y(n1486) );
AO22XLTS U1713 ( .A0(n1486), .A1(DMP_SFG[2]), .B0(n1497), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
INVX4TS U1714 ( .A(n1613), .Y(n1384) );
AO22XLTS U1715 ( .A0(n1384), .A1(DMP_EXP_EWSW[3]), .B0(n1378), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1716 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n948), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1717 ( .A0(n1486), .A1(DMP_SFG[3]), .B0(n1493), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1718 ( .A0(n1384), .A1(DMP_EXP_EWSW[4]), .B0(n1379), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1719 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1653), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1720 ( .A0(n1486), .A1(DMP_SFG[4]), .B0(n1493), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
AO22XLTS U1721 ( .A0(n1384), .A1(DMP_EXP_EWSW[5]), .B0(n1385), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1722 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n948), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1723 ( .A0(n1384), .A1(DMP_EXP_EWSW[6]), .B0(n1377), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1724 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1653), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
AO22XLTS U1725 ( .A0(n1384), .A1(DMP_EXP_EWSW[7]), .B0(n1378), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1726 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n948), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1727 ( .A0(n1486), .A1(DMP_SFG[7]), .B0(n1497), .B1(
DMP_SHT2_EWSW[7]), .Y(n696) );
AO22XLTS U1728 ( .A0(n1384), .A1(DMP_EXP_EWSW[8]), .B0(n1379), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1729 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1653), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1730 ( .A0(n1486), .A1(DMP_SFG[8]), .B0(n1497), .B1(
DMP_SHT2_EWSW[8]), .Y(n693) );
AO22XLTS U1731 ( .A0(n1384), .A1(DMP_EXP_EWSW[9]), .B0(n1613), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1732 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n948), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1733 ( .A0(n1384), .A1(DMP_EXP_EWSW[10]), .B0(n1613), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
AO22XLTS U1734 ( .A0(n915), .A1(DMP_SHT1_EWSW[10]), .B0(n1376), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1735 ( .A0(n1486), .A1(DMP_SFG[10]), .B0(n1493), .B1(
DMP_SHT2_EWSW[10]), .Y(n687) );
BUFX3TS U1736 ( .A(n1613), .Y(n1377) );
AO22XLTS U1737 ( .A0(n1384), .A1(DMP_EXP_EWSW[11]), .B0(n1377), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1738 ( .A0(n915), .A1(DMP_SHT1_EWSW[11]), .B0(n1376), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1739 ( .A0(n1384), .A1(DMP_EXP_EWSW[12]), .B0(n1377), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1740 ( .A0(busy), .A1(DMP_SHT1_EWSW[12]), .B0(n1653), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1741 ( .A0(n1486), .A1(DMP_SFG[12]), .B0(n1493), .B1(
DMP_SHT2_EWSW[12]), .Y(n681) );
AO22XLTS U1742 ( .A0(n1384), .A1(DMP_EXP_EWSW[13]), .B0(n1377), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1743 ( .A0(busy), .A1(DMP_SHT1_EWSW[13]), .B0(n948), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1744 ( .A0(n1384), .A1(DMP_EXP_EWSW[14]), .B0(n1377), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1745 ( .A0(busy), .A1(DMP_SHT1_EWSW[14]), .B0(n1376), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1746 ( .A0(n1486), .A1(DMP_SFG[14]), .B0(n1497), .B1(
DMP_SHT2_EWSW[14]), .Y(n675) );
AO22XLTS U1747 ( .A0(n1384), .A1(DMP_EXP_EWSW[15]), .B0(n1377), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1748 ( .A0(busy), .A1(DMP_SHT1_EWSW[15]), .B0(n1376), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1749 ( .A0(n1384), .A1(DMP_EXP_EWSW[16]), .B0(n1377), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1750 ( .A0(n1654), .A1(DMP_SHT1_EWSW[16]), .B0(n1376), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1751 ( .A0(n1486), .A1(DMP_SFG[16]), .B0(n1509), .B1(
DMP_SHT2_EWSW[16]), .Y(n669) );
INVX4TS U1752 ( .A(n1613), .Y(n1386) );
AO22XLTS U1753 ( .A0(n1386), .A1(DMP_EXP_EWSW[17]), .B0(n1377), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1754 ( .A0(n1654), .A1(DMP_SHT1_EWSW[17]), .B0(n1376), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1755 ( .A0(n1386), .A1(DMP_EXP_EWSW[18]), .B0(n1377), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1756 ( .A0(n1654), .A1(DMP_SHT1_EWSW[18]), .B0(n1376), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1757 ( .A0(n1486), .A1(DMP_SFG[18]), .B0(n1514), .B1(
DMP_SHT2_EWSW[18]), .Y(n663) );
AO22XLTS U1758 ( .A0(n1386), .A1(DMP_EXP_EWSW[19]), .B0(n1377), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1759 ( .A0(n1654), .A1(DMP_SHT1_EWSW[19]), .B0(n1376), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1760 ( .A0(n1386), .A1(DMP_EXP_EWSW[20]), .B0(n1377), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1761 ( .A0(n1654), .A1(DMP_SHT1_EWSW[20]), .B0(n1376), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1762 ( .A0(n1386), .A1(DMP_EXP_EWSW[21]), .B0(n1377), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1763 ( .A0(n1654), .A1(DMP_SHT1_EWSW[21]), .B0(n1653), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
BUFX3TS U1764 ( .A(n1613), .Y(n1385) );
AO22XLTS U1765 ( .A0(n1386), .A1(DMP_EXP_EWSW[22]), .B0(n1385), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1766 ( .A0(n1654), .A1(DMP_SHT1_EWSW[22]), .B0(n948), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1767 ( .A0(n1386), .A1(DMP_EXP_EWSW[23]), .B0(n1385), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1768 ( .A0(n947), .A1(DMP_SHT1_EWSW[23]), .B0(n1653), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1769 ( .A0(n1509), .A1(DMP_SHT2_EWSW[23]), .B0(n1374), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1770 ( .A0(n1402), .A1(DMP_SFG[23]), .B0(n1392), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1771 ( .A0(n1386), .A1(DMP_EXP_EWSW[24]), .B0(n1385), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1772 ( .A0(n947), .A1(DMP_SHT1_EWSW[24]), .B0(n948), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1773 ( .A0(n1497), .A1(DMP_SHT2_EWSW[24]), .B0(n1374), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1774 ( .A0(n1402), .A1(DMP_SFG[24]), .B0(n1392), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1775 ( .A0(n1386), .A1(DMP_EXP_EWSW[25]), .B0(n1385), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1776 ( .A0(n947), .A1(DMP_SHT1_EWSW[25]), .B0(n1653), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1777 ( .A0(n1509), .A1(DMP_SHT2_EWSW[25]), .B0(n1374), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1778 ( .A0(n1402), .A1(DMP_SFG[25]), .B0(n1392), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1779 ( .A0(n1386), .A1(DMP_EXP_EWSW[26]), .B0(n1385), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1780 ( .A0(n1654), .A1(DMP_SHT1_EWSW[26]), .B0(n948), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1781 ( .A0(n1509), .A1(DMP_SHT2_EWSW[26]), .B0(n1374), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1782 ( .A0(n1402), .A1(DMP_SFG[26]), .B0(n1392), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1783 ( .A0(n1386), .A1(n937), .B0(n1385), .B1(DMP_SHT1_EWSW[27]),
.Y(n630) );
AO22XLTS U1784 ( .A0(n947), .A1(DMP_SHT1_EWSW[27]), .B0(n1653), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1785 ( .A0(n1493), .A1(DMP_SHT2_EWSW[27]), .B0(n1512), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1786 ( .A0(n1402), .A1(DMP_SFG[27]), .B0(n1409), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1787 ( .A0(n1386), .A1(DMP_EXP_EWSW[28]), .B0(n1385), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1788 ( .A0(n915), .A1(DMP_SHT1_EWSW[28]), .B0(n916), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1789 ( .A0(n1514), .A1(DMP_SHT2_EWSW[28]), .B0(n1486), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1790 ( .A0(n1402), .A1(DMP_SFG[28]), .B0(n1409), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1791 ( .A0(n1386), .A1(DMP_EXP_EWSW[29]), .B0(n1385), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1792 ( .A0(n947), .A1(DMP_SHT1_EWSW[29]), .B0(n1653), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1793 ( .A0(n1402), .A1(DMP_SFG[29]), .B0(n1409), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1794 ( .A0(n1520), .A1(DMP_EXP_EWSW[30]), .B0(n1385), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1795 ( .A0(n915), .A1(DMP_SHT1_EWSW[30]), .B0(n1376), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1796 ( .A0(n1497), .A1(DMP_SHT2_EWSW[30]), .B0(n1498), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1797 ( .A0(n1402), .A1(DMP_SFG[30]), .B0(n1409), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
BUFX3TS U1798 ( .A(n1613), .Y(n1378) );
BUFX3TS U1799 ( .A(n1613), .Y(n1379) );
OAI222X1TS U1800 ( .A0(n1382), .A1(n1608), .B0(n1538), .B1(
Shift_reg_FLAGS_7_6), .C0(n1519), .C1(n1380), .Y(n563) );
OAI222X1TS U1801 ( .A0(n1382), .A1(n1543), .B0(n1610), .B1(
Shift_reg_FLAGS_7_6), .C0(n1584), .C1(n1380), .Y(n562) );
OAI222X1TS U1802 ( .A0(n1382), .A1(n1544), .B0(n1605), .B1(
Shift_reg_FLAGS_7_6), .C0(n1590), .C1(n1380), .Y(n561) );
NAND2X1TS U1803 ( .A(n1412), .B(Shift_reg_FLAGS_7[0]), .Y(n1383) );
OAI2BB1X1TS U1804 ( .A0N(underflow_flag), .A1N(n1471), .B0(n1383), .Y(n559)
);
AO22XLTS U1805 ( .A0(n1386), .A1(ZERO_FLAG_EXP), .B0(n1613), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
AO22XLTS U1806 ( .A0(n947), .A1(ZERO_FLAG_SHT1), .B0(n948), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1807 ( .A0(n1402), .A1(ZERO_FLAG_SFG), .B0(n1409), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1808 ( .A0(n907), .A1(ZERO_FLAG_NRM), .B0(n1387), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1809 ( .A0(n1384), .A1(OP_FLAG_EXP), .B0(n1613), .B1(OP_FLAG_SHT1),
.Y(n551) );
AO22XLTS U1810 ( .A0(n915), .A1(OP_FLAG_SHT1), .B0(n1376), .B1(OP_FLAG_SHT2),
.Y(n550) );
AO22XLTS U1811 ( .A0(n1491), .A1(OP_FLAG_SFG), .B0(n1509), .B1(OP_FLAG_SHT2),
.Y(n549) );
AO22XLTS U1812 ( .A0(n1386), .A1(SIGN_FLAG_EXP), .B0(n1385), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1813 ( .A0(n915), .A1(SIGN_FLAG_SHT1), .B0(n916), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1814 ( .A0(n1493), .A1(SIGN_FLAG_SHT2), .B0(n1498), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1815 ( .A0(n1402), .A1(SIGN_FLAG_SFG), .B0(n1392), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1816 ( .A0(n907), .A1(SIGN_FLAG_NRM), .B0(n1387), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n544) );
AOI22X1TS U1817 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n958), .Y(n1389) );
AOI22X1TS U1818 ( .A0(n1406), .A1(n1389), .B0(n1529), .B1(n1651), .Y(n542)
);
AOI22X1TS U1819 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1407), .B0(n1403), .B1(n959), .Y(n1390) );
AOI22X1TS U1820 ( .A0(n1406), .A1(n1390), .B0(n1596), .B1(n1651), .Y(n541)
);
OAI21XLTS U1821 ( .A0(n1391), .A1(DMP_SFG[0]), .B0(n1394), .Y(n1393) );
AOI22X1TS U1822 ( .A0(n1406), .A1(n1393), .B0(n1551), .B1(n1392), .Y(n540)
);
XNOR2X1TS U1823 ( .A(DMP_SFG[1]), .B(n1394), .Y(n1395) );
XNOR2X1TS U1824 ( .A(n1395), .B(n919), .Y(n1396) );
AOI22X1TS U1825 ( .A0(n1406), .A1(n1396), .B0(n1593), .B1(n1651), .Y(n539)
);
AOI2BB2XLTS U1826 ( .B0(n1650), .B1(intadd_53_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n1402), .Y(n538) );
AOI22X1TS U1827 ( .A0(n1650), .A1(intadd_53_SUM_1_), .B0(n1552), .B1(n1651),
.Y(n537) );
AOI22X1TS U1828 ( .A0(n1650), .A1(intadd_53_SUM_2_), .B0(n1541), .B1(n1409),
.Y(n536) );
XNOR2X1TS U1829 ( .A(DMP_SFG[5]), .B(n920), .Y(n1397) );
XNOR2X1TS U1830 ( .A(intadd_53_n1), .B(n1397), .Y(n1398) );
AOI22X1TS U1831 ( .A0(n1650), .A1(n1398), .B0(n1527), .B1(n1409), .Y(n535)
);
AOI22X1TS U1832 ( .A0(n1650), .A1(intadd_52_SUM_0_), .B0(n1530), .B1(n1409),
.Y(n534) );
AOI22X1TS U1833 ( .A0(n1650), .A1(intadd_52_SUM_1_), .B0(n1542), .B1(n1409),
.Y(n533) );
AOI22X1TS U1834 ( .A0(n1650), .A1(intadd_52_SUM_2_), .B0(n1525), .B1(n1409),
.Y(n532) );
XNOR2X1TS U1835 ( .A(DMP_SFG[9]), .B(n1399), .Y(n1400) );
XNOR2X1TS U1836 ( .A(intadd_52_n1), .B(n1400), .Y(n1401) );
AOI22X1TS U1837 ( .A0(n1650), .A1(n1401), .B0(n1518), .B1(n1409), .Y(n531)
);
AOI22X1TS U1838 ( .A0(n1406), .A1(intadd_51_SUM_1_), .B0(n1540), .B1(n1409),
.Y(n529) );
AOI22X1TS U1839 ( .A0(n1406), .A1(intadd_51_SUM_2_), .B0(n1523), .B1(n1409),
.Y(n528) );
AOI22X1TS U1840 ( .A0(n1406), .A1(intadd_51_SUM_3_), .B0(n1522), .B1(n1409),
.Y(n527) );
AOI22X1TS U1841 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1405), .B0(n1403), .B1(
n950), .Y(intadd_51_B_4_) );
AOI22X1TS U1842 ( .A0(n1406), .A1(intadd_51_SUM_4_), .B0(n1517), .B1(n1392),
.Y(n526) );
AOI22X1TS U1843 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1405), .B0(n1403), .B1(
n951), .Y(intadd_51_B_5_) );
AOI22X1TS U1844 ( .A0(n1406), .A1(intadd_51_SUM_5_), .B0(n1546), .B1(n1651),
.Y(n525) );
AOI22X1TS U1845 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n1405), .B0(n1403), .B1(
n952), .Y(intadd_51_B_6_) );
AOI22X1TS U1846 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1405), .B0(n1403), .B1(
n953), .Y(intadd_51_B_7_) );
AOI22X1TS U1847 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1405), .B0(n1403), .B1(
n954), .Y(intadd_51_B_8_) );
AOI22X1TS U1848 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n955), .Y(intadd_51_B_9_) );
AOI22X1TS U1849 ( .A0(n1406), .A1(intadd_51_SUM_9_), .B0(n1548), .B1(n1651),
.Y(n521) );
AOI22X1TS U1850 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n956), .Y(intadd_51_B_10_) );
AOI22X1TS U1851 ( .A0(n1406), .A1(intadd_51_SUM_10_), .B0(n1545), .B1(n1651),
.Y(n520) );
AOI22X1TS U1852 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n1599), .Y(intadd_51_B_11_) );
AOI22X1TS U1853 ( .A0(n1406), .A1(intadd_51_SUM_11_), .B0(n1515), .B1(n1651),
.Y(n519) );
AOI22X1TS U1854 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1405), .B0(OP_FLAG_SFG),
.B1(n1612), .Y(intadd_51_B_12_) );
AOI22X1TS U1855 ( .A0(n1406), .A1(intadd_51_SUM_12_), .B0(n1516), .B1(n1651),
.Y(n518) );
AOI22X1TS U1856 ( .A0(DmP_mant_SFG_SWR[25]), .A1(OP_FLAG_SFG), .B0(n1407),
.B1(n1616), .Y(n1408) );
XNOR2X1TS U1857 ( .A(intadd_51_n1), .B(n1408), .Y(n1410) );
AOI22X1TS U1858 ( .A0(n1650), .A1(n1410), .B0(n1521), .B1(n1409), .Y(n517)
);
AND3X4TS U1859 ( .A(shift_value_SHT2_EWR[2]), .B(n1550), .C(
shift_value_SHT2_EWR[3]), .Y(n1472) );
NAND2X1TS U1860 ( .A(shift_value_SHT2_EWR[2]), .B(n1547), .Y(n1427) );
NAND2X1TS U1861 ( .A(n1447), .B(n1550), .Y(n1458) );
AOI22X1TS U1862 ( .A0(Data_array_SWR[12]), .A1(n902), .B0(Data_array_SWR[13]), .B1(n939), .Y(n1413) );
OAI221X1TS U1863 ( .A0(n908), .A1(n1415), .B0(n909), .B1(n1416), .C0(n1413),
.Y(n1492) );
AOI22X1TS U1864 ( .A0(Data_array_SWR[12]), .A1(n939), .B0(Data_array_SWR[13]), .B1(n902), .Y(n1414) );
OAI221X1TS U1865 ( .A0(left_right_SHT2), .A1(n1416), .B0(n875), .B1(n1415),
.C0(n1414), .Y(n1494) );
AOI22X1TS U1866 ( .A0(Data_array_SWR[22]), .A1(n943), .B0(Data_array_SWR[18]), .B1(n942), .Y(n1420) );
AOI22X1TS U1867 ( .A0(Data_array_SWR[14]), .A1(n939), .B0(Data_array_SWR[11]), .B1(n902), .Y(n1417) );
OAI221X1TS U1868 ( .A0(left_right_SHT2), .A1(n1419), .B0(n875), .B1(n1420),
.C0(n1417), .Y(n1490) );
AOI22X1TS U1869 ( .A0(Data_array_SWR[14]), .A1(n902), .B0(Data_array_SWR[11]), .B1(n939), .Y(n1418) );
OAI221X1TS U1870 ( .A0(n908), .A1(n1420), .B0(n909), .B1(n1419), .C0(n1418),
.Y(n1495) );
AOI22X1TS U1871 ( .A0(Data_array_SWR[23]), .A1(n943), .B0(Data_array_SWR[19]), .B1(n942), .Y(n1424) );
AOI22X1TS U1872 ( .A0(Data_array_SWR[10]), .A1(n902), .B0(Data_array_SWR[15]), .B1(n939), .Y(n1421) );
OAI221X1TS U1873 ( .A0(n908), .A1(n1423), .B0(n909), .B1(n1424), .C0(n1421),
.Y(n1489) );
AOI22X1TS U1874 ( .A0(Data_array_SWR[10]), .A1(n939), .B0(Data_array_SWR[15]), .B1(n902), .Y(n1422) );
OAI221X1TS U1875 ( .A0(left_right_SHT2), .A1(n1424), .B0(n875), .B1(n1423),
.C0(n1422), .Y(n1496) );
AOI22X1TS U1876 ( .A0(Data_array_SWR[17]), .A1(n944), .B0(Data_array_SWR[13]), .B1(n941), .Y(n1426) );
AOI22X1TS U1877 ( .A0(Data_array_SWR[21]), .A1(n1472), .B0(
Data_array_SWR[25]), .B1(n1440), .Y(n1425) );
NAND2X1TS U1878 ( .A(n1426), .B(n1425), .Y(n1430) );
NOR2X1TS U1879 ( .A(shift_value_SHT2_EWR[2]), .B(n1547), .Y(n1433) );
INVX2TS U1880 ( .A(n1427), .Y(n1448) );
INVX2TS U1881 ( .A(n1476), .Y(n1429) );
OAI2BB2XLTS U1882 ( .B0(n1488), .B1(n904), .A0N(final_result_ieee[7]), .A1N(
n1471), .Y(n505) );
OAI2BB2XLTS U1883 ( .B0(n1499), .B1(n905), .A0N(final_result_ieee[14]),
.A1N(n1471), .Y(n504) );
AOI22X1TS U1884 ( .A0(Data_array_SWR[12]), .A1(n942), .B0(Data_array_SWR[16]), .B1(n943), .Y(n1432) );
AOI22X1TS U1885 ( .A0(Data_array_SWR[24]), .A1(n1440), .B0(
Data_array_SWR[20]), .B1(n1472), .Y(n1431) );
NAND2X1TS U1886 ( .A(n1432), .B(n1431), .Y(n1435) );
INVX2TS U1887 ( .A(n1470), .Y(n1434) );
OAI2BB2XLTS U1888 ( .B0(n1487), .B1(n905), .A0N(final_result_ieee[6]), .A1N(
n1471), .Y(n503) );
OAI2BB2XLTS U1889 ( .B0(n1500), .B1(n905), .A0N(final_result_ieee[15]),
.A1N(n1471), .Y(n502) );
AOI22X1TS U1890 ( .A0(Data_array_SWR[15]), .A1(n944), .B0(Data_array_SWR[11]), .B1(n942), .Y(n1437) );
AOI22X1TS U1891 ( .A0(Data_array_SWR[23]), .A1(n1440), .B0(
Data_array_SWR[19]), .B1(n1472), .Y(n1436) );
NAND2X1TS U1892 ( .A(n1437), .B(n1436), .Y(n1439) );
AOI22X1TS U1893 ( .A0(Data_array_SWR[22]), .A1(n1448), .B0(
Data_array_SWR[18]), .B1(n1447), .Y(n1464) );
INVX2TS U1894 ( .A(n1464), .Y(n1438) );
OAI2BB2XLTS U1895 ( .B0(n1485), .B1(n905), .A0N(final_result_ieee[5]), .A1N(
n1471), .Y(n501) );
OAI2BB2XLTS U1896 ( .B0(n1501), .B1(n905), .A0N(final_result_ieee[16]),
.A1N(n1471), .Y(n500) );
AOI22X1TS U1897 ( .A0(Data_array_SWR[14]), .A1(n944), .B0(Data_array_SWR[10]), .B1(n941), .Y(n1442) );
AOI22X1TS U1898 ( .A0(Data_array_SWR[22]), .A1(n1440), .B0(
Data_array_SWR[18]), .B1(n1472), .Y(n1441) );
NAND2X1TS U1899 ( .A(n1442), .B(n1441), .Y(n1444) );
AOI22X1TS U1900 ( .A0(Data_array_SWR[23]), .A1(n1448), .B0(
Data_array_SWR[19]), .B1(n1447), .Y(n1461) );
INVX2TS U1901 ( .A(n1461), .Y(n1443) );
OAI2BB2XLTS U1902 ( .B0(n1484), .B1(n905), .A0N(final_result_ieee[4]), .A1N(
n872), .Y(n499) );
OAI2BB2XLTS U1903 ( .B0(n1502), .B1(n905), .A0N(final_result_ieee[17]),
.A1N(n872), .Y(n498) );
AOI22X1TS U1904 ( .A0(Data_array_SWR[21]), .A1(n1447), .B0(
Data_array_SWR[25]), .B1(n1448), .Y(n1453) );
AOI22X1TS U1905 ( .A0(Data_array_SWR[13]), .A1(n943), .B0(Data_array_SWR[9]),
.B1(n941), .Y(n1446) );
NAND2X1TS U1906 ( .A(Data_array_SWR[17]), .B(n1472), .Y(n1445) );
OAI211X1TS U1907 ( .A0(n1453), .A1(n1550), .B0(n1446), .C0(n1445), .Y(n1449)
);
AO22X1TS U1908 ( .A0(Data_array_SWR[24]), .A1(n1448), .B0(Data_array_SWR[20]), .B1(n1447), .Y(n1450) );
OAI2BB2XLTS U1909 ( .B0(n1483), .B1(n904), .A0N(final_result_ieee[3]), .A1N(
n872), .Y(n497) );
OAI2BB2XLTS U1910 ( .B0(n1503), .B1(n904), .A0N(final_result_ieee[18]),
.A1N(n872), .Y(n496) );
AOI22X1TS U1911 ( .A0(Data_array_SWR[12]), .A1(n944), .B0(Data_array_SWR[8]),
.B1(n941), .Y(n1452) );
AOI22X1TS U1912 ( .A0(Data_array_SWR[16]), .A1(n1472), .B0(
shift_value_SHT2_EWR[4]), .B1(n1450), .Y(n1451) );
NAND2X1TS U1913 ( .A(n1452), .B(n1451), .Y(n1457) );
INVX2TS U1914 ( .A(n1453), .Y(n1456) );
OAI2BB2XLTS U1915 ( .B0(n1482), .B1(n905), .A0N(final_result_ieee[2]), .A1N(
n872), .Y(n495) );
OAI2BB2XLTS U1916 ( .B0(n1504), .B1(n905), .A0N(final_result_ieee[19]),
.A1N(n872), .Y(n494) );
AOI22X1TS U1917 ( .A0(Data_array_SWR[15]), .A1(n1472), .B0(
Data_array_SWR[11]), .B1(n943), .Y(n1460) );
INVX2TS U1918 ( .A(n1458), .Y(n1473) );
AOI22X1TS U1919 ( .A0(Data_array_SWR[7]), .A1(n941), .B0(Data_array_SWR[3]),
.B1(n1473), .Y(n1459) );
OAI211X1TS U1920 ( .A0(n1461), .A1(n1550), .B0(n1460), .C0(n1459), .Y(n1465)
);
AOI22X1TS U1921 ( .A0(Data_array_SWR[22]), .A1(n939), .B0(n909), .B1(n1465),
.Y(n1481) );
OAI2BB2XLTS U1922 ( .B0(n1481), .B1(n904), .A0N(final_result_ieee[1]), .A1N(
n872), .Y(n493) );
AOI22X1TS U1923 ( .A0(Data_array_SWR[14]), .A1(n1472), .B0(
Data_array_SWR[10]), .B1(n943), .Y(n1463) );
AOI22X1TS U1924 ( .A0(Data_array_SWR[6]), .A1(n941), .B0(Data_array_SWR[2]),
.B1(n1473), .Y(n1462) );
OAI211X1TS U1925 ( .A0(n1464), .A1(n1550), .B0(n1463), .C0(n1462), .Y(n1466)
);
AOI22X1TS U1926 ( .A0(Data_array_SWR[23]), .A1(n940), .B0(n909), .B1(n1466),
.Y(n1480) );
OAI2BB2XLTS U1927 ( .B0(n1480), .B1(n904), .A0N(final_result_ieee[0]), .A1N(
n872), .Y(n492) );
AOI22X1TS U1928 ( .A0(Data_array_SWR[22]), .A1(n903), .B0(left_right_SHT2),
.B1(n1465), .Y(n1505) );
OAI2BB2XLTS U1929 ( .B0(n1505), .B1(n904), .A0N(final_result_ieee[20]),
.A1N(n872), .Y(n491) );
AOI22X1TS U1930 ( .A0(Data_array_SWR[23]), .A1(n902), .B0(left_right_SHT2),
.B1(n1466), .Y(n1506) );
OAI2BB2XLTS U1931 ( .B0(n1506), .B1(n904), .A0N(final_result_ieee[21]),
.A1N(n872), .Y(n490) );
AOI22X1TS U1932 ( .A0(Data_array_SWR[13]), .A1(n1472), .B0(Data_array_SWR[9]), .B1(n943), .Y(n1469) );
AOI22X1TS U1933 ( .A0(Data_array_SWR[5]), .A1(n941), .B0(Data_array_SWR[1]),
.B1(n1473), .Y(n1468) );
OAI211X1TS U1934 ( .A0(n1470), .A1(n1550), .B0(n1469), .C0(n1468), .Y(n1478)
);
AOI22X1TS U1935 ( .A0(Data_array_SWR[24]), .A1(n903), .B0(left_right_SHT2),
.B1(n1478), .Y(n1508) );
OAI2BB2XLTS U1936 ( .B0(n1508), .B1(n904), .A0N(final_result_ieee[22]),
.A1N(n1471), .Y(n489) );
AOI22X1TS U1937 ( .A0(Data_array_SWR[12]), .A1(n1472), .B0(Data_array_SWR[8]), .B1(n944), .Y(n1475) );
AOI22X1TS U1938 ( .A0(Data_array_SWR[4]), .A1(n942), .B0(Data_array_SWR[0]),
.B1(n1473), .Y(n1474) );
OAI211X1TS U1939 ( .A0(n1476), .A1(n1550), .B0(n1475), .C0(n1474), .Y(n1510)
);
AOI22X1TS U1940 ( .A0(Data_array_SWR[25]), .A1(n940), .B0(n909), .B1(n1510),
.Y(n1477) );
AOI22X1TS U1941 ( .A0(n1514), .A1(n1477), .B0(n1491), .B1(n958), .Y(n488) );
AOI22X1TS U1942 ( .A0(Data_array_SWR[24]), .A1(n940), .B0(n875), .B1(n1478),
.Y(n1479) );
AOI22X1TS U1943 ( .A0(n1514), .A1(n1479), .B0(n1491), .B1(n959), .Y(n487) );
AOI22X1TS U1944 ( .A0(n1514), .A1(n1480), .B0(n1491), .B1(n960), .Y(n486) );
AOI22X1TS U1945 ( .A0(n1514), .A1(n1481), .B0(n1512), .B1(n961), .Y(n485) );
AOI22X1TS U1946 ( .A0(n1509), .A1(n1482), .B0(n1486), .B1(n962), .Y(n484) );
AOI22X1TS U1947 ( .A0(n1514), .A1(n1483), .B0(n966), .B1(n1512), .Y(n483) );
AOI22X1TS U1948 ( .A0(n1514), .A1(n1484), .B0(n1491), .B1(n967), .Y(n482) );
AOI22X1TS U1949 ( .A0(n1509), .A1(n1485), .B0(n1512), .B1(n965), .Y(n481) );
AOI22X1TS U1950 ( .A0(n1509), .A1(n1487), .B0(n1486), .B1(n964), .Y(n480) );
AOI22X1TS U1951 ( .A0(n1509), .A1(n1488), .B0(n963), .B1(n1512), .Y(n479) );
AOI22X1TS U1952 ( .A0(n1509), .A1(n1499), .B0(n1512), .B1(n950), .Y(n472) );
AOI22X1TS U1953 ( .A0(n1509), .A1(n1500), .B0(n1512), .B1(n951), .Y(n471) );
AOI22X1TS U1954 ( .A0(n1509), .A1(n1501), .B0(n1512), .B1(n952), .Y(n470) );
AOI22X1TS U1955 ( .A0(n1514), .A1(n1502), .B0(n1512), .B1(n953), .Y(n469) );
AOI22X1TS U1956 ( .A0(n1514), .A1(n1503), .B0(n1512), .B1(n954), .Y(n468) );
AOI22X1TS U1957 ( .A0(n1514), .A1(n1504), .B0(n1374), .B1(n955), .Y(n467) );
AOI22X1TS U1958 ( .A0(n1514), .A1(n1505), .B0(n1374), .B1(n956), .Y(n466) );
AOI22X1TS U1959 ( .A0(n1514), .A1(n1506), .B0(n1374), .B1(n1599), .Y(n465)
);
AOI22X1TS U1960 ( .A0(n1514), .A1(n1508), .B0(n1374), .B1(n1612), .Y(n464)
);
AOI22X1TS U1961 ( .A0(Data_array_SWR[25]), .A1(n903), .B0(left_right_SHT2),
.B1(n1510), .Y(n1513) );
AOI22X1TS U1962 ( .A0(n1514), .A1(n1513), .B0(n1512), .B1(n1616), .Y(n463)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk20.tcl_GeArN16R4P4_syn.sdf");
endmodule
|
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop = conf_word[1];
// divide subcarrier frequency by 4
wire hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
hi_sniffer he(
pck0, ck_1356meg, ck_1356megb,
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
adc_d, he_adc_clk,
he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
cross_hi, cross_lo,
he_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_flite hfl(
pck0, ck_1356meg, ck_1356megb,
hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
adc_d, hfl_adc_clk,
hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
cross_hi, cross_lo,
hfl_dbg,
hi_simulate_mod_type
);
// Major modes:
// 000 -- HF reader, transmitting to tag; modulation depth selectable
// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 010 -- HF simulated tag
// 011 -- HF ISO14443-A
// 100 -- HF Snoop
// 101 -- Felica modem, reusing HF reader
// 110 -- none
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, hfl_ssp_clk, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, hfl_ssp_din, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, hfl_ssp_frame, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, hfl_dbg, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
module sky130_fd_sc_hdll__a32oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module ddr3_s4_amphy (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
oct_ctl_rs_value,
oct_ctl_rt_value,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_clk_n,
dll_reference_clk,
dqs_delay_ctrl_export,
aux_scan_clk_reset_n,
aux_scan_clk,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
mem_reset_n,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
reset_request_n,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqsn);
input [23:0] local_address;
input local_write_req;
input local_read_req;
input local_burstbegin;
input [31:0] local_wdata;
input [3:0] local_be;
input [2:0] local_size;
input [13:0] oct_ctl_rs_value;
input [13:0] oct_ctl_rt_value;
input global_reset_n;
input pll_ref_clk;
input soft_reset_n;
output local_ready;
output [31:0] local_rdata;
output local_rdata_valid;
output local_refresh_ack;
output local_init_done;
output reset_phy_clk_n;
output dll_reference_clk;
output [5:0] dqs_delay_ctrl_export;
output aux_scan_clk_reset_n;
output aux_scan_clk;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [12:0] mem_addr;
output [2:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [0:0] mem_dm;
output mem_reset_n;
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
output reset_request_n;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [7:0] mem_dq;
inout [0:0] mem_dqs;
inout [0:0] mem_dqsn;
endmodule
|
module deserializer_gen_test(
output rxd,
output clk
);
reg rxd_buf;
reg clk_buf;
reg [7:0] data_buf;
assign clk = clk_buf;
assign rxd = rxd_buf;
integer data_src;
integer i;
integer j;
initial
begin
rxd_buf = 0;
clk_buf = 1;
data_src = $fopen("test_serializer/data/serial_vector.txt", "rb");
#100;
for(i = 0; i < 16*(8+4); i = i + 1)
begin
#1;
data_buf = $fgetc(data_src);
if(data_buf == "1") rxd_buf = 1;
if(data_buf == "0") rxd_buf = 0;
#1;
clk_buf = 0;
#2;
clk_buf = 1;
end
#2;
clk_buf = 0;
#2;
clk_buf = 1;
#2;
clk_buf = 0;
#2;
clk_buf = 1;
#2;
clk_buf = 0;
#2;
clk_buf = 1;
$fclose(data_src);
end
endmodule
|
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_lp__dlxbn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule
|
module jaxa (
autostart_external_connection_export,
clk_clk,
controlflagsin_external_connection_export,
controlflagsout_external_connection_export,
creditcount_external_connection_export,
errorstatus_external_connection_export,
linkdisable_external_connection_export,
linkstart_external_connection_export,
linkstatus_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
outstandingcount_external_connection_export,
pll_0_outclk0_clk,
receiveactivity_external_connection_export,
receiveclock_external_connection_export,
receivefifodatacount_external_connection_export,
receivefifodataout_external_connection_export,
receivefifoempty_external_connection_export,
receivefifofull_external_connection_export,
receivefiforeadenable_external_connection_export,
spacewiredatain_external_connection_export,
spacewiredataout_external_connection_export,
spacewirestrobein_external_connection_export,
spacewirestrobeout_external_connection_export,
statisticalinformation_0_external_connection_export,
statisticalinformation_1_external_connection_export,
statisticalinformationclear_external_connection_export,
tickin_external_connection_export,
tickout_external_connection_export,
timein_external_connection_export,
timeout_external_connection_export,
transmitactivity_external_connection_export,
transmitclock_external_connection_export,
transmitclockdividevalue_external_connection_export,
transmitfifodatacount_external_connection_export,
transmitfifodatain_external_connection_export,
transmitfifofull_external_connection_export,
transmitfifowriteenable_external_connection_export);
output autostart_external_connection_export;
input clk_clk;
output [1:0] controlflagsin_external_connection_export;
input [1:0] controlflagsout_external_connection_export;
input [5:0] creditcount_external_connection_export;
input [7:0] errorstatus_external_connection_export;
output linkdisable_external_connection_export;
output linkstart_external_connection_export;
input [15:0] linkstatus_external_connection_export;
output [12:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [7:0] memory_mem_dq;
inout memory_mem_dqs;
inout memory_mem_dqs_n;
output memory_mem_odt;
output memory_mem_dm;
input memory_oct_rzqin;
input [5:0] outstandingcount_external_connection_export;
output pll_0_outclk0_clk;
input receiveactivity_external_connection_export;
output receiveclock_external_connection_export;
input receivefifodatacount_external_connection_export;
input [8:0] receivefifodataout_external_connection_export;
input receivefifoempty_external_connection_export;
input receivefifofull_external_connection_export;
output receivefiforeadenable_external_connection_export;
output spacewiredatain_external_connection_export;
input spacewiredataout_external_connection_export;
output spacewirestrobein_external_connection_export;
input spacewirestrobeout_external_connection_export;
input [31:0] statisticalinformation_0_external_connection_export;
output [7:0] statisticalinformation_1_external_connection_export;
output statisticalinformationclear_external_connection_export;
output tickin_external_connection_export;
input tickout_external_connection_export;
output [5:0] timein_external_connection_export;
input [5:0] timeout_external_connection_export;
input transmitactivity_external_connection_export;
output transmitclock_external_connection_export;
output [5:0] transmitclockdividevalue_external_connection_export;
input [5:0] transmitfifodatacount_external_connection_export;
output [8:0] transmitfifodatain_external_connection_export;
input transmitfifofull_external_connection_export;
output transmitfifowriteenable_external_connection_export;
endmodule
|
module address_decode (
sys_clk,
nreset,
wb_adr,
wb_ack_uart,
wb_ack_timer,
wb_ack_ctrl,
wb_stb,
wb_dat_uart_o,
wb_dat_timer_o,
wb_dat_ctrl_i,
sram_stb,
uart0_stb,
timer_stb,
local_stb,
wb_ack,
wb_dat_i
);
`include "regs.vh"
input sys_clk;
input nreset;
input [31:0] wb_adr;
input wb_ack_uart;
input wb_ack_timer;
input wb_ack_ctrl;
input wb_stb;
input [7:0] wb_dat_uart_o;
input [31:0] wb_dat_timer_o;
input [31:0] wb_dat_ctrl_i;
output sram_stb;
output uart0_stb;
output timer_stb;
output local_stb;
output wb_ack;
output [31:0] wb_dat_i;
wire [31:0] uart0_addr = `LM32_UART0_BASE_ADDR;
wire [31:0] timer_addr = `LM32_TIMER_BASE_ADDR;
// Decode address for peripheral targets
wire sram_sel = ~wb_adr[31];
// Decode addresses on top 8 bits, and on 4K pages (first 16)
// This assumption is specific to this project's address mapping,
// and may need to change if ported to a different project, with
// different mappings to get correct resolution.
wire uart0_sel = (wb_adr[31:24] == uart0_addr[31:24] && wb_adr[15:12] == uart0_addr[15:12]) ? 1'b1 : 1'b0;
wire timer_sel = (wb_adr[31:24] == timer_addr[31:24] && wb_adr[15:12] == timer_addr[15:12]) ? 1'b1 : 1'b0;
// Local register decode for any address not in the above selects.
// The controller will always acknowledge, so this mops up all unused
// addresses
wire local_sel = ~uart0_sel & ~timer_sel & ~sram_sel;
// Generate strobes (i.e. 'chip selects') for relevant peripheral
assign sram_stb = wb_stb & sram_sel;
assign uart0_stb = wb_stb & uart0_sel;
assign timer_stb = wb_stb & timer_sel;
assign local_stb = wb_stb & local_sel;
// Combine all acks (including dummy ACK) to send back to CPU.
assign wb_ack = wb_ack_ctrl | wb_ack_uart | wb_ack_timer;
// Multiplex read data from peripherals to return to CPU. If no peripheral
// selected, data is a dummy pattern to aid diagnostics. Controller
// handles both SRAM and local accesses.
assign wb_dat_i = (sram_sel | local_sel) ? wb_dat_ctrl_i :
uart0_sel ? {{24'h000000, wb_dat_uart_o}} :
timer_sel ? wb_dat_timer_o :
32'hcccccccc;
endmodule
|
module sky130_fd_sc_hd__clkinvlp (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module bg4_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/bg4-new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
|
module Clock70HMz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock70HMz_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
module transform_memory(
clk,
rst,
i_valid,
i_transize,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_valid,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rst;
input i_valid;
input signed [1:0] i_transize;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
input signed [15:0] i_8;
input signed [15:0] i_9;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
input signed [15:0] i_16;
input signed [15:0] i_17;
input signed [15:0] i_18;
input signed [15:0] i_19;
input signed [15:0] i_20;
input signed [15:0] i_21;
input signed [15:0] i_22;
input signed [15:0] i_23;
input signed [15:0] i_24;
input signed [15:0] i_25;
input signed [15:0] i_26;
input signed [15:0] i_27;
input signed [15:0] i_28;
input signed [15:0] i_29;
input signed [15:0] i_30;
input signed [15:0] i_31;
output reg o_valid;
output signed [15:0] o_0;
output signed [15:0] o_1;
output signed [15:0] o_2;
output signed [15:0] o_3;
output signed [15:0] o_4;
output signed [15:0] o_5;
output signed [15:0] o_6;
output signed [15:0] o_7;
output signed [15:0] o_8;
output signed [15:0] o_9;
output signed [15:0] o_10;
output signed [15:0] o_11;
output signed [15:0] o_12;
output signed [15:0] o_13;
output signed [15:0] o_14;
output signed [15:0] o_15;
output signed [15:0] o_16;
output signed [15:0] o_17;
output signed [15:0] o_18;
output signed [15:0] o_19;
output signed [15:0] o_20;
output signed [15:0] o_21;
output signed [15:0] o_22;
output signed [15:0] o_23;
output signed [15:0] o_24;
output signed [15:0] o_25;
output signed [15:0] o_26;
output signed [15:0] o_27;
output signed [15:0] o_28;
output signed [15:0] o_29;
output signed [15:0] o_30;
output signed [15:0] o_31;
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
wire wen;
wire enable;
wire [4:0] counter;
wire [4:0] badd_0 ;
wire [4:0] badd_1 ;
wire [4:0] badd_2 ;
wire [4:0] badd_3 ;
wire [4:0] badd_4 ;
wire [4:0] badd_5 ;
wire [4:0] badd_6 ;
wire [4:0] badd_7 ;
wire [4:0] badd_8 ;
wire [4:0] badd_9 ;
wire [4:0] badd_10;
wire [4:0] badd_11;
wire [4:0] badd_12;
wire [4:0] badd_13;
wire [4:0] badd_14;
wire [4:0] badd_15;
wire [4:0] badd_16;
wire [4:0] badd_17;
wire [4:0] badd_18;
wire [4:0] badd_19;
wire [4:0] badd_20;
wire [4:0] badd_21;
wire [4:0] badd_22;
wire [4:0] badd_23;
wire [4:0] badd_24;
wire [4:0] badd_25;
wire [4:0] badd_26;
wire [4:0] badd_27;
wire [4:0] badd_28;
wire [4:0] badd_29;
wire [4:0] badd_30;
wire [4:0] badd_31;
wire [4:0] add_0 ;
wire [4:0] add_1 ;
wire [4:0] add_2 ;
wire [4:0] add_3 ;
wire [4:0] add_4 ;
wire [4:0] add_5 ;
wire [4:0] add_6 ;
wire [4:0] add_7 ;
wire [4:0] add_8 ;
wire [4:0] add_9 ;
wire [4:0] add_10;
wire [4:0] add_11;
wire [4:0] add_12;
wire [4:0] add_13;
wire [4:0] add_14;
wire [4:0] add_15;
wire [4:0] add_16;
wire [4:0] add_17;
wire [4:0] add_18;
wire [4:0] add_19;
wire [4:0] add_20;
wire [4:0] add_21;
wire [4:0] add_22;
wire [4:0] add_23;
wire [4:0] add_24;
wire [4:0] add_25;
wire [4:0] add_26;
wire [4:0] add_27;
wire [4:0] add_28;
wire [4:0] add_29;
wire [4:0] add_30;
wire [4:0] add_31;
wire signed [15:0] i_m_0 ;
wire signed [15:0] i_m_1 ;
wire signed [15:0] i_m_2 ;
wire signed [15:0] i_m_3 ;
wire signed [15:0] i_m_4 ;
wire signed [15:0] i_m_5 ;
wire signed [15:0] i_m_6 ;
wire signed [15:0] i_m_7 ;
wire signed [15:0] i_m_8 ;
wire signed [15:0] i_m_9 ;
wire signed [15:0] i_m_10;
wire signed [15:0] i_m_11;
wire signed [15:0] i_m_12;
wire signed [15:0] i_m_13;
wire signed [15:0] i_m_14;
wire signed [15:0] i_m_15;
wire signed [15:0] i_m_16;
wire signed [15:0] i_m_17;
wire signed [15:0] i_m_18;
wire signed [15:0] i_m_19;
wire signed [15:0] i_m_20;
wire signed [15:0] i_m_21;
wire signed [15:0] i_m_22;
wire signed [15:0] i_m_23;
wire signed [15:0] i_m_24;
wire signed [15:0] i_m_25;
wire signed [15:0] i_m_26;
wire signed [15:0] i_m_27;
wire signed [15:0] i_m_28;
wire signed [15:0] i_m_29;
wire signed [15:0] i_m_30;
wire signed [15:0] i_m_31;
wire signed [15:0] o_m_0 ;
wire signed [15:0] o_m_1 ;
wire signed [15:0] o_m_2 ;
wire signed [15:0] o_m_3 ;
wire signed [15:0] o_m_4 ;
wire signed [15:0] o_m_5 ;
wire signed [15:0] o_m_6 ;
wire signed [15:0] o_m_7 ;
wire signed [15:0] o_m_8 ;
wire signed [15:0] o_m_9 ;
wire signed [15:0] o_m_10;
wire signed [15:0] o_m_11;
wire signed [15:0] o_m_12;
wire signed [15:0] o_m_13;
wire signed [15:0] o_m_14;
wire signed [15:0] o_m_15;
wire signed [15:0] o_m_16;
wire signed [15:0] o_m_17;
wire signed [15:0] o_m_18;
wire signed [15:0] o_m_19;
wire signed [15:0] o_m_20;
wire signed [15:0] o_m_21;
wire signed [15:0] o_m_22;
wire signed [15:0] o_m_23;
wire signed [15:0] o_m_24;
wire signed [15:0] o_m_25;
wire signed [15:0] o_m_26;
wire signed [15:0] o_m_27;
wire signed [15:0] o_m_28;
wire signed [15:0] o_m_29;
wire signed [15:0] o_m_30;
wire signed [15:0] o_m_31;
wire signed [15:0] i_s_0 ;
wire signed [15:0] i_s_1 ;
wire signed [15:0] i_s_2 ;
wire signed [15:0] i_s_3 ;
wire signed [15:0] i_s_4 ;
wire signed [15:0] i_s_5 ;
wire signed [15:0] i_s_6 ;
wire signed [15:0] i_s_7 ;
wire signed [15:0] i_s_8 ;
wire signed [15:0] i_s_9 ;
wire signed [15:0] i_s_10;
wire signed [15:0] i_s_11;
wire signed [15:0] i_s_12;
wire signed [15:0] i_s_13;
wire signed [15:0] i_s_14;
wire signed [15:0] i_s_15;
wire signed [15:0] i_s_16;
wire signed [15:0] i_s_17;
wire signed [15:0] i_s_18;
wire signed [15:0] i_s_19;
wire signed [15:0] i_s_20;
wire signed [15:0] i_s_21;
wire signed [15:0] i_s_22;
wire signed [15:0] i_s_23;
wire signed [15:0] i_s_24;
wire signed [15:0] i_s_25;
wire signed [15:0] i_s_26;
wire signed [15:0] i_s_27;
wire signed [15:0] i_s_28;
wire signed [15:0] i_s_29;
wire signed [15:0] i_s_30;
wire signed [15:0] i_s_31;
wire signed [15:0] o_s_0 ;
wire signed [15:0] o_s_1 ;
wire signed [15:0] o_s_2 ;
wire signed [15:0] o_s_3 ;
wire signed [15:0] o_s_4 ;
wire signed [15:0] o_s_5 ;
wire signed [15:0] o_s_6 ;
wire signed [15:0] o_s_7 ;
wire signed [15:0] o_s_8 ;
wire signed [15:0] o_s_9 ;
wire signed [15:0] o_s_10;
wire signed [15:0] o_s_11;
wire signed [15:0] o_s_12;
wire signed [15:0] o_s_13;
wire signed [15:0] o_s_14;
wire signed [15:0] o_s_15;
wire signed [15:0] o_s_16;
wire signed [15:0] o_s_17;
wire signed [15:0] o_s_18;
wire signed [15:0] o_s_19;
wire signed [15:0] o_s_20;
wire signed [15:0] o_s_21;
wire signed [15:0] o_s_22;
wire signed [15:0] o_s_23;
wire signed [15:0] o_s_24;
wire signed [15:0] o_s_25;
wire signed [15:0] o_s_26;
wire signed [15:0] o_s_27;
wire signed [15:0] o_s_28;
wire signed [15:0] o_s_29;
wire signed [15:0] o_s_30;
wire signed [15:0] o_s_31;
// ********************************************
//
// Reg DECLARATION
//
// ********************************************
reg o_chose;
reg wen_0;
reg wen_1;
reg enable_0;
reg signed [15:0] i_r_0;
reg signed [15:0] i_r_1;
reg signed [15:0] i_r_2;
reg signed [15:0] i_r_3;
reg signed [15:0] i_r_4;
reg signed [15:0] i_r_5;
reg signed [15:0] i_r_6;
reg signed [15:0] i_r_7;
reg signed [15:0] i_r_8;
reg signed [15:0] i_r_9;
reg signed [15:0] i_r_10;
reg signed [15:0] i_r_11;
reg signed [15:0] i_r_12;
reg signed [15:0] i_r_13;
reg signed [15:0] i_r_14;
reg signed [15:0] i_r_15;
reg signed [15:0] i_r_16;
reg signed [15:0] i_r_17;
reg signed [15:0] i_r_18;
reg signed [15:0] i_r_19;
reg signed [15:0] i_r_20;
reg signed [15:0] i_r_21;
reg signed [15:0] i_r_22;
reg signed [15:0] i_r_23;
reg signed [15:0] i_r_24;
reg signed [15:0] i_r_25;
reg signed [15:0] i_r_26;
reg signed [15:0] i_r_27;
reg signed [15:0] i_r_28;
reg signed [15:0] i_r_29;
reg signed [15:0] i_r_30;
reg signed [15:0] i_r_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign i_m_0 =wen_1?o_s_0 :i_0 ;
assign i_m_1 =wen_1?o_s_1 :i_1 ;
assign i_m_2 =wen_1?o_s_2 :i_2 ;
assign i_m_3 =wen_1?o_s_3 :i_3 ;
assign i_m_4 =wen_1?o_s_4 :i_4 ;
assign i_m_5 =wen_1?o_s_5 :i_5 ;
assign i_m_6 =wen_1?o_s_6 :i_6 ;
assign i_m_7 =wen_1?o_s_7 :i_7 ;
assign i_m_8 =wen_1?o_s_8 :i_8 ;
assign i_m_9 =wen_1?o_s_9 :i_9 ;
assign i_m_10=wen_1?o_s_10:i_10;
assign i_m_11=wen_1?o_s_11:i_11;
assign i_m_12=wen_1?o_s_12:i_12;
assign i_m_13=wen_1?o_s_13:i_13;
assign i_m_14=wen_1?o_s_14:i_14;
assign i_m_15=wen_1?o_s_15:i_15;
assign i_m_16=wen_1?o_s_16:i_16;
assign i_m_17=wen_1?o_s_17:i_17;
assign i_m_18=wen_1?o_s_18:i_18;
assign i_m_19=wen_1?o_s_19:i_19;
assign i_m_20=wen_1?o_s_20:i_20;
assign i_m_21=wen_1?o_s_21:i_21;
assign i_m_22=wen_1?o_s_22:i_22;
assign i_m_23=wen_1?o_s_23:i_23;
assign i_m_24=wen_1?o_s_24:i_24;
assign i_m_25=wen_1?o_s_25:i_25;
assign i_m_26=wen_1?o_s_26:i_26;
assign i_m_27=wen_1?o_s_27:i_27;
assign i_m_28=wen_1?o_s_28:i_28;
assign i_m_29=wen_1?o_s_29:i_29;
assign i_m_30=wen_1?o_s_30:i_30;
assign i_m_31=wen_1?o_s_31:i_31;
assign i_s_0 =wen_0?16'b0:o_m_0 ;
assign i_s_1 =wen_0?16'b0:o_m_1 ;
assign i_s_2 =wen_0?16'b0:o_m_2 ;
assign i_s_3 =wen_0?16'b0:o_m_3 ;
assign i_s_4 =wen_0?16'b0:o_m_4 ;
assign i_s_5 =wen_0?16'b0:o_m_5 ;
assign i_s_6 =wen_0?16'b0:o_m_6 ;
assign i_s_7 =wen_0?16'b0:o_m_7 ;
assign i_s_8 =wen_0?16'b0:o_m_8 ;
assign i_s_9 =wen_0?16'b0:o_m_9 ;
assign i_s_10=wen_0?16'b0:o_m_10;
assign i_s_11=wen_0?16'b0:o_m_11;
assign i_s_12=wen_0?16'b0:o_m_12;
assign i_s_13=wen_0?16'b0:o_m_13;
assign i_s_14=wen_0?16'b0:o_m_14;
assign i_s_15=wen_0?16'b0:o_m_15;
assign i_s_16=wen_0?16'b0:o_m_16;
assign i_s_17=wen_0?16'b0:o_m_17;
assign i_s_18=wen_0?16'b0:o_m_18;
assign i_s_19=wen_0?16'b0:o_m_19;
assign i_s_20=wen_0?16'b0:o_m_20;
assign i_s_21=wen_0?16'b0:o_m_21;
assign i_s_22=wen_0?16'b0:o_m_22;
assign i_s_23=wen_0?16'b0:o_m_23;
assign i_s_24=wen_0?16'b0:o_m_24;
assign i_s_25=wen_0?16'b0:o_m_25;
assign i_s_26=wen_0?16'b0:o_m_26;
assign i_s_27=wen_0?16'b0:o_m_27;
assign i_s_28=wen_0?16'b0:o_m_28;
assign i_s_29=wen_0?16'b0:o_m_29;
assign i_s_30=wen_0?16'b0:o_m_30;
assign i_s_31=wen_0?16'b0:o_m_31;
assign o_0 =o_chose?o_m_0: 16'b0;
assign o_1 =o_chose?o_m_1: 16'b0;
assign o_2 =o_chose?o_m_2: 16'b0;
assign o_3 =o_chose?o_m_3: 16'b0;
assign o_4 =o_chose?o_m_4: 16'b0;
assign o_5 =o_chose?o_m_5: 16'b0;
assign o_6 =o_chose?o_m_6: 16'b0;
assign o_7 =o_chose?o_m_7: 16'b0;
assign o_8 =o_chose?o_m_8: 16'b0;
assign o_9 =o_chose?o_m_9: 16'b0;
assign o_10 =o_chose?o_m_10:16'b0;
assign o_11 =o_chose?o_m_11:16'b0;
assign o_12 =o_chose?o_m_12:16'b0;
assign o_13 =o_chose?o_m_13:16'b0;
assign o_14 =o_chose?o_m_14:16'b0;
assign o_15 =o_chose?o_m_15:16'b0;
assign o_16 =o_chose?o_m_16:16'b0;
assign o_17 =o_chose?o_m_17:16'b0;
assign o_18 =o_chose?o_m_18:16'b0;
assign o_19 =o_chose?o_m_19:16'b0;
assign o_20 =o_chose?o_m_20:16'b0;
assign o_21 =o_chose?o_m_21:16'b0;
assign o_22 =o_chose?o_m_22:16'b0;
assign o_23 =o_chose?o_m_23:16'b0;
assign o_24 =o_chose?o_m_24:16'b0;
assign o_25 =o_chose?o_m_25:16'b0;
assign o_26 =o_chose?o_m_26:16'b0;
assign o_27 =o_chose?o_m_27:16'b0;
assign o_28 =o_chose?o_m_28:16'b0;
assign o_29 =o_chose?o_m_29:16'b0;
assign o_30 =o_chose?o_m_30:16'b0;
assign o_31 =o_chose?o_m_31:16'b0;
always@(*)
o_valid=o_chose;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
o_chose<=1'b0;
else
if(i_transize==2'b00)
o_chose<=i_valid;
else
o_chose<=wen_1;
always@(posedge clk or negedge rst)
if(!rst)
enable_0<=1'b0;
else
enable_0<=enable;
always@(posedge clk or negedge rst)
if(!rst)
wen_0<=1'b0;
else
wen_0<=wen;
always@(posedge clk or negedge rst)
if(!rst)
wen_1<=1'b0;
else
wen_1<=wen_0;
always@(posedge clk or negedge rst)
if(!rst)
begin
i_r_0<=16'b0;
i_r_1<=16'b0;
i_r_2<=16'b0;
i_r_3<=16'b0;
i_r_4<=16'b0;
i_r_5<=16'b0;
i_r_6<=16'b0;
i_r_7<=16'b0;
i_r_8<=16'b0;
i_r_9<=16'b0;
i_r_10<=16'b0;
i_r_11<=16'b0;
i_r_12<=16'b0;
i_r_13<=16'b0;
i_r_14<=16'b0;
i_r_15<=16'b0;
i_r_16<=16'b0;
i_r_17<=16'b0;
i_r_18<=16'b0;
i_r_19<=16'b0;
i_r_20<=16'b0;
i_r_21<=16'b0;
i_r_22<=16'b0;
i_r_23<=16'b0;
i_r_24<=16'b0;
i_r_25<=16'b0;
i_r_26<=16'b0;
i_r_27<=16'b0;
i_r_28<=16'b0;
i_r_29<=16'b0;
i_r_30<=16'b0;
i_r_31<=16'b0;
end
else
begin
i_r_0 <= i_m_0 ;
i_r_1 <= i_m_1 ;
i_r_2 <= i_m_2 ;
i_r_3 <= i_m_3 ;
i_r_4 <= i_m_4 ;
i_r_5 <= i_m_5 ;
i_r_6 <= i_m_6 ;
i_r_7 <= i_m_7 ;
i_r_8 <= i_m_8 ;
i_r_9 <= i_m_9 ;
i_r_10<= i_m_10;
i_r_11<= i_m_11;
i_r_12<= i_m_12;
i_r_13<= i_m_13;
i_r_14<= i_m_14;
i_r_15<= i_m_15;
i_r_16<= i_m_16;
i_r_17<= i_m_17;
i_r_18<= i_m_18;
i_r_19<= i_m_19;
i_r_20<= i_m_20;
i_r_21<= i_m_21;
i_r_22<= i_m_22;
i_r_23<= i_m_23;
i_r_24<= i_m_24;
i_r_25<= i_m_25;
i_r_26<= i_m_26;
i_r_27<= i_m_27;
i_r_28<= i_m_28;
i_r_29<= i_m_29;
i_r_30<= i_m_30;
i_r_31<= i_m_31;
end
// ********************************************
//
// Sub Modules
//
// ********************************************
ctrl_transmemory ctrl_transmemory_0(
clk,
rst,
i_valid,
i_transize,
wen,
enable,
counter
);
addr add0_0(
clk,
rst,
enable,
wen,
counter,
i_transize,
badd_0 ,
badd_1 ,
badd_2 ,
badd_3 ,
badd_4 ,
badd_5 ,
badd_6 ,
badd_7 ,
badd_8 ,
badd_9 ,
badd_10,
badd_11,
badd_12,
badd_13,
badd_14,
badd_15,
badd_16,
badd_17,
badd_18,
badd_19,
badd_20,
badd_21,
badd_22,
badd_23,
badd_24,
badd_25,
badd_26,
badd_27,
badd_28,
badd_29,
badd_30,
badd_31,
add_0 ,
add_1 ,
add_2 ,
add_3 ,
add_4 ,
add_5 ,
add_6 ,
add_7 ,
add_8 ,
add_9 ,
add_10,
add_11,
add_12,
add_13,
add_14,
add_15,
add_16,
add_17,
add_18,
add_19,
add_20,
add_21,
add_22,
add_23,
add_24,
add_25,
add_26,
add_27,
add_28,
add_29,
add_30,
add_31
);
mux_32 mux_32_0(
badd_0,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_0
);
mux_32 mux_32_1(
badd_1,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_1
);
mux_32 mux_32_2(
badd_2,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_2
);
mux_32 mux_32_3(
badd_3,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_3
);
mux_32 mux_32_4(
badd_4,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_4
);
mux_32 mux_32_5(
badd_5,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_5
);
mux_32 mux_32_6(
badd_6,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_6
);
mux_32 mux_32_7(
badd_7,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_7
);
mux_32 mux_32_8(
badd_8,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_8
);
mux_32 mux_32_9(
badd_9,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_9
);
mux_32 mux_32_10(
badd_10,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_10
);
mux_32 mux_32_11(
badd_11,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_11
);
mux_32 mux_32_12(
badd_12,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_12
);
mux_32 mux_32_13(
badd_13,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_13
);
mux_32 mux_32_14(
badd_14,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_14
);
mux_32 mux_32_15(
badd_15,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_15
);
mux_32 mux_32_16(
badd_16,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_16
);
mux_32 mux_32_17(
badd_17,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_17
);
mux_32 mux_32_18(
badd_18,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_18
);
mux_32 mux_32_19(
badd_19,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_19
);
mux_32 mux_32_20(
badd_20,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_20
);
mux_32 mux_32_21(
badd_21,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_21
);
mux_32 mux_32_22(
badd_22,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_22
);
mux_32 mux_32_23(
badd_23,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_23
);
mux_32 mux_32_24(
badd_24,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_24
);
mux_32 mux_32_25(
badd_25,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_25
);
mux_32 mux_32_26(
badd_26,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_26
);
mux_32 mux_32_27(
badd_27,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_27
);
mux_32 mux_32_28(
badd_28,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_28
);
mux_32 mux_32_29(
badd_29,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_29
);
mux_32 mux_32_30(
badd_30,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_30
);
mux_32 mux_32_31(
badd_31,
i_r_0 ,
i_r_1 ,
i_r_2 ,
i_r_3 ,
i_r_4 ,
i_r_5 ,
i_r_6 ,
i_r_7 ,
i_r_8 ,
i_r_9 ,
i_r_10,
i_r_11,
i_r_12,
i_r_13,
i_r_14,
i_r_15,
i_r_16,
i_r_17,
i_r_18,
i_r_19,
i_r_20,
i_r_21,
i_r_22,
i_r_23,
i_r_24,
i_r_25,
i_r_26,
i_r_27,
i_r_28,
i_r_29,
i_r_30,
i_r_31,
o_m_31
);
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_0(.data_o(o_s_0),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_0),.data_i(i_s_0),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_1(.data_o(o_s_1),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_1),.data_i(i_s_1),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_2(.data_o(o_s_2),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_2),.data_i(i_s_2),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_3(.data_o(o_s_3),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_3),.data_i(i_s_3),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_4(.data_o(o_s_4),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_4),.data_i(i_s_4),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_5(.data_o(o_s_5),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_5),.data_i(i_s_5),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_6(.data_o(o_s_6),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_6),.data_i(i_s_6),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_7(.data_o(o_s_7),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_7),.data_i(i_s_7),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_8(.data_o(o_s_8),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_8),.data_i(i_s_8),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_9(.data_o(o_s_9),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_9),.data_i(i_s_9),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_10(.data_o(o_s_10),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_10),.data_i(i_s_10),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_11(.data_o(o_s_11),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_11),.data_i(i_s_11),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_12(.data_o(o_s_12),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_12),.data_i(i_s_12),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_13(.data_o(o_s_13),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_13),.data_i(i_s_13),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_14(.data_o(o_s_14),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_14),.data_i(i_s_14),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_15(.data_o(o_s_15),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_15),.data_i(i_s_15),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_16(.data_o(o_s_16),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_16),.data_i(i_s_16),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_17(.data_o(o_s_17),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_17),.data_i(i_s_17),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_18(.data_o(o_s_18),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_18),.data_i(i_s_18),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_19(.data_o(o_s_19),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_19),.data_i(i_s_19),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_20(.data_o(o_s_20),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_20),.data_i(i_s_20),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_21(.data_o(o_s_21),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_21),.data_i(i_s_21),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_22(.data_o(o_s_22),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_22),.data_i(i_s_22),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_23(.data_o(o_s_23),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_23),.data_i(i_s_23),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_24(.data_o(o_s_24),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_24),.data_i(i_s_24),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_25(.data_o(o_s_25),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_25),.data_i(i_s_25),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_26(.data_o(o_s_26),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_26),.data_i(i_s_26),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_27(.data_o(o_s_27),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_27),.data_i(i_s_27),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_28(.data_o(o_s_28),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_28),.data_i(i_s_28),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_29(.data_o(o_s_29),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_29),.data_i(i_s_29),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_30(.data_o(o_s_30),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_30),.data_i(i_s_30),.oen_i(!wen_1));
ram_1p #(.Addr_Width(5), .Word_Width(16)) ram_1p_31(.data_o(o_s_31),.clk(clk),.cen_i(!enable_0),.wen_i(wen_0),.addr_i(add_31),.data_i(i_s_31),.oen_i(!wen_1));
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module raycaster(
wb_clk,
wb_rst,
// WB Slave
wb_adr_i, wb_dat_i,
wb_we_i, wb_cyc_i, wb_stb_i,
wb_cti_i, wb_bte_i,
wb_dat_o, wb_ack_o, wb_err_o, wb_rty_o,
// WB Master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
m_wb_cti_o, m_wb_bte_o,
// Interrupt
irq_o
);
// = Parameters =
// --
// = Ports =
input wb_clk;
input wb_rst;
// Wishbone Slave
input [7:0] wb_adr_i;
input [7:0] wb_dat_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
input [2:0] wb_cti_i;
input [1:0] wb_bte_i;
output [7:0] wb_dat_o; // constantly sampling gpio in bus
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
// Wishbone master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
//
output irq_o;
// --
// = Wires =
wire [31:0] cache_hits;
wire [31:0] cache_miss;
wire [511:0] pm;
wire [511:0] mm;
wire [127:0] test;
// Slave -> Controller
wire rayc_start ;
wire rayc_lol ;
wire [31:0] ray_buf_adr ;
wire [31:0] ray_buf_count ;
wire [31:0] octree_adr ;
wire [31:0] fb_adr ;
wire rayc_finished;
// Controller <-> Master
wire [31:0] ctrl_wb_adr_o;
wire [3:0] ctrl_wb_sel_o;
wire ctrl_wb_we_o ;
wire [31:0] ctrl_wb_dat_i;
wire [31:0] ctrl_wb_dat_o;
wire ctrl_wb_cyc_o;
wire ctrl_wb_stb_o;
wire ctrl_wb_ack_i;
wire [2:0] ctrl_wb_cti_o;
wire [1:0] ctrl_wb_bte_o;
// Cores
`ifdef CORE0
wire c0_start ;
wire [31:0] c0_root_adr ;
wire [2:0] c0_dir_mask ;
wire [31:0] c0_tx0 ;
wire [31:0] c0_ty0 ;
wire [31:0] c0_tz0 ;
wire [31:0] c0_tx1 ;
wire [31:0] c0_ty1 ;
wire [31:0] c0_tz1 ;
wire [31:0] c0_wb_adr_o;
wire [31:0] c0_wb_dat_i;
wire c0_wb_cyc_o;
wire c0_wb_stb_o;
wire c0_wb_ack_i;
wire c0_finished ;
wire c0_leaf ;
wire [31:0] c0_final_t ;
wire [4:0] c0_final_level ;
`endif
`ifdef CORE1
wire c1_start ;
wire [31:0] c1_root_adr ;
wire [2:0] c1_dir_mask ;
wire [31:0] c1_tx0 ;
wire [31:0] c1_ty0 ;
wire [31:0] c1_tz0 ;
wire [31:0] c1_tx1 ;
wire [31:0] c1_ty1 ;
wire [31:0] c1_tz1 ;
wire [31:0] c1_wb_adr_o;
wire [31:0] c1_wb_dat_i;
wire c1_wb_cyc_o;
wire c1_wb_stb_o;
wire c1_wb_ack_i;
wire c1_finished ;
wire c1_leaf ;
wire [31:0] c1_final_t ;
wire [4:0] c1_final_level ;
`endif
`ifdef CORE2
wire c2_start ;
wire [31:0] c2_root_adr ;
wire [2:0] c2_dir_mask ;
wire [31:0] c2_tx0 ;
wire [31:0] c2_ty0 ;
wire [31:0] c2_tz0 ;
wire [31:0] c2_tx1 ;
wire [31:0] c2_ty1 ;
wire [31:0] c2_tz1 ;
wire [31:0] c2_wb_adr_o;
wire [31:0] c2_wb_dat_i;
wire c2_wb_cyc_o;
wire c2_wb_stb_o;
wire c2_wb_ack_i;
wire c2_finished ;
wire c2_leaf ;
wire [31:0] c2_final_t ;
wire [4:0] c2_final_level ;
`endif
`ifdef CORE3
wire c3_start ;
wire [31:0] c3_root_adr ;
wire [2:0] c3_dir_mask ;
wire [31:0] c3_tx0 ;
wire [31:0] c3_ty0 ;
wire [31:0] c3_tz0 ;
wire [31:0] c3_tx1 ;
wire [31:0] c3_ty1 ;
wire [31:0] c3_tz1 ;
wire [31:0] c3_wb_adr_o;
wire [31:0] c3_wb_dat_i;
wire c3_wb_cyc_o;
wire c3_wb_stb_o;
wire c3_wb_ack_i;
wire c3_finished ;
wire c3_leaf ;
wire [31:0] c3_final_t ;
wire [4:0] c3_final_level ;
`endif
// --
// = Raycast Control =
raycast_ctrl raycast_ctrl
(
.clk (wb_clk),
.rst (wb_rst),
.rayc_start_i (rayc_start ),
.rayc_lol_i (rayc_lol ),
.ray_buf_adr_i (ray_buf_adr ),
.ray_buf_count_i (ray_buf_count),
.octree_adr_i (octree_adr ),
.fb_adr_i (fb_adr ),
.pm_i (pm),
.mm_i (mm),
.test_o (test),
.m_wb_adr_o (ctrl_wb_adr_o),
.m_wb_sel_o (ctrl_wb_sel_o),
.m_wb_we_o (ctrl_wb_we_o ),
.m_wb_dat_o (ctrl_wb_dat_o),
.m_wb_dat_i (ctrl_wb_dat_i),
.m_wb_cyc_o (ctrl_wb_cyc_o),
.m_wb_stb_o (ctrl_wb_stb_o),
.m_wb_ack_i (ctrl_wb_ack_i),
.m_wb_cti_o (ctrl_wb_cti_o),
.m_wb_bte_o (ctrl_wb_bte_o),
/* .ctrl_adr_o (ctrl_adr),
.ray_data_req_o (ray_data_req ),
.ray_data_ack_i (ray_data_ack ),
.ray_data_i (ray_data ),
.fb_w_req_o (fb_w_req ),
.fb_w_dat_o (fb_w_dat ),
.fb_w_ack_i (fb_w_ack ),*/
`ifdef CORE0
.c0_start_o (c0_start ),
.c0_root_adr_o (c0_root_adr),
.c0_dir_mask_o (c0_dir_mask),
.c0_tx0_o (c0_tx0 ),
.c0_ty0_o (c0_ty0 ),
.c0_tz0_o (c0_tz0 ),
.c0_tx1_o (c0_tx1 ),
.c0_ty1_o (c0_ty1 ),
.c0_tz1_o (c0_tz1 ),
.c0_finished_i (c0_finished),
.c0_leaf_i (c0_leaf),
.c0_final_t_i (c0_final_t),
.c0_final_level_i (c0_final_level),
`endif
`ifdef CORE1
.c1_start_o (c1_start ),
.c1_root_adr_o (c1_root_adr),
.c1_dir_mask_o (c1_dir_mask),
.c1_tx0_o (c1_tx0 ),
.c1_ty0_o (c1_ty0 ),
.c1_tz0_o (c1_tz0 ),
.c1_tx1_o (c1_tx1 ),
.c1_ty1_o (c1_ty1 ),
.c1_tz1_o (c1_tz1 ),
.c1_finished_i (c1_finished),
.c1_leaf_i (c1_leaf),
.c1_final_t_i (c1_final_t),
.c1_final_level_i (c1_final_level),
`endif
`ifdef CORE2
.c2_start_o (c2_start ),
.c2_root_adr_o (c2_root_adr),
.c2_dir_mask_o (c2_dir_mask),
.c2_tx0_o (c2_tx0 ),
.c2_ty0_o (c2_ty0 ),
.c2_tz0_o (c2_tz0 ),
.c2_tx1_o (c2_tx1 ),
.c2_ty1_o (c2_ty1 ),
.c2_tz1_o (c2_tz1 ),
.c2_finished_i (c2_finished),
.c2_leaf_i (c2_leaf),
.c2_final_t_i (c2_final_t),
.c2_final_level_i (c2_final_level),
`endif
`ifdef CORE3
.c3_start_o (c3_start ),
.c3_root_adr_o (c3_root_adr),
.c3_dir_mask_o (c3_dir_mask),
.c3_tx0_o (c3_tx0 ),
.c3_ty0_o (c3_ty0 ),
.c3_tz0_o (c3_tz0 ),
.c3_tx1_o (c3_tx1 ),
.c3_ty1_o (c3_ty1 ),
.c3_tz1_o (c3_tz1 ),
.c3_finished_i (c3_finished),
.c3_leaf_i (c3_leaf),
.c3_final_t_i (c3_final_t),
.c3_final_level_i (c3_final_level),
`endif
.rayc_finished_o (rayc_finished)
);
// --
// = Raycast master interface =
raycast_master raycast_master
(
// .cache_hits (cache_hits),
// .cache_miss (cache_miss),
.m_wb_adr_o (m_wb_adr_o ),
.m_wb_sel_o (m_wb_sel_o ),
.m_wb_we_o (m_wb_we_o ),
.m_wb_dat_o (m_wb_dat_o ),
.m_wb_dat_i (m_wb_dat_i ),
.m_wb_cyc_o (m_wb_cyc_o ),
.m_wb_stb_o (m_wb_stb_o ),
.m_wb_ack_i (m_wb_ack_i ),
.m_wb_err_i (m_wb_err_i ),
.m_wb_cti_o (m_wb_cti_o ),
.m_wb_bte_o (m_wb_bte_o ),
.ctrl_wb_adr_i (ctrl_wb_adr_o),
.ctrl_wb_sel_i (ctrl_wb_sel_o),
.ctrl_wb_we_i (ctrl_wb_we_o ),
.ctrl_wb_dat_o (ctrl_wb_dat_i),
.ctrl_wb_dat_i (ctrl_wb_dat_o),
.ctrl_wb_cyc_i (ctrl_wb_cyc_o),
.ctrl_wb_stb_i (ctrl_wb_stb_o),
.ctrl_wb_ack_o (ctrl_wb_ack_i),
.ctrl_wb_cti_i (ctrl_wb_cti_o),
.ctrl_wb_bte_i (ctrl_wb_bte_o),
`ifdef CORE0
.c0_wb_adr_i (c0_wb_adr_o),
.c0_wb_dat_o (c0_wb_dat_i),
.c0_wb_cyc_i (c0_wb_cyc_o),
.c0_wb_stb_i (c0_wb_stb_o),
.c0_wb_ack_o (c0_wb_ack_i),
`endif
`ifdef CORE1
.c1_wb_adr_i (c1_wb_adr_o),
.c1_wb_dat_o (c1_wb_dat_i),
.c1_wb_cyc_i (c1_wb_cyc_o),
.c1_wb_stb_i (c1_wb_stb_o),
.c1_wb_ack_o (c1_wb_ack_i),
`endif
`ifdef CORE2
.c2_wb_adr_i (c2_wb_adr_o),
.c2_wb_dat_o (c2_wb_dat_i),
.c2_wb_cyc_i (c2_wb_cyc_o),
.c2_wb_stb_i (c2_wb_stb_o),
.c2_wb_ack_o (c2_wb_ack_i),
`endif
`ifdef CORE3
.c3_wb_adr_i (c3_wb_adr_o),
.c3_wb_dat_o (c3_wb_dat_i),
.c3_wb_cyc_i (c3_wb_cyc_o),
.c3_wb_stb_i (c3_wb_stb_o),
.c3_wb_ack_o (c3_wb_ack_i),
`endif
.wb_clk (wb_clk ),
.wb_rst (wb_rst )
);
// --
// = Raycast slave interface =
raycast_slave raycast_slave
(
.wb_clk (wb_clk ),
.wb_rst (wb_rst ),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_we_i (wb_we_i ),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_cti_i (wb_cti_i),
.wb_bte_i (wb_bte_i),
.wb_dat_o (wb_dat_o),
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
.wb_rty_o (wb_rty_o),
.rayc_start_o (rayc_start ),
.rayc_lol_o (rayc_lol ),
.ray_buf_adr_o (ray_buf_adr ),
.ray_buf_count_o (ray_buf_count),
.octree_adr_o (octree_adr ),
.fb_adr_o (fb_adr ),
.rayc_finished_i (rayc_finished),
.cache_hits_i (cache_hits),
.cache_miss_i (cache_miss),
.irq_o (irq_o),
.pm_o (pm),
.mm_o (mm),
.test_i (test)
);
// --
// = Raycast cores =
`ifdef CORE0
raycast_core core0
(
.clk (wb_clk ),
.rst (wb_rst ),
.start_i (c0_start ),
.root_adr_i (c0_root_adr ),
.dir_mask_i (c0_dir_mask ),
.tx0_i (c0_tx0 ),
.ty0_i (c0_ty0 ),
.tz0_i (c0_tz0 ),
.tx1_i (c0_tx1 ),
.ty1_i (c0_ty1 ),
.tz1_i (c0_tz1 ),
.m_wb_adr_o (c0_wb_adr_o),
.m_wb_dat_i (c0_wb_dat_i),
.m_wb_cyc_o (c0_wb_cyc_o),
.m_wb_stb_o (c0_wb_stb_o),
.m_wb_ack_i (c0_wb_ack_i),
.finished_o (c0_finished ),
.leaf_o (c0_leaf),
.t_o (c0_final_t ),
.level_o (c0_final_level )
);
`endif
`ifdef CORE1
raycast_core core1
(
.clk (wb_clk ),
.rst (wb_rst ),
.start_i (c1_start ),
.root_adr_i (c1_root_adr ),
.dir_mask_i (c1_dir_mask ),
.tx0_i (c1_tx0 ),
.ty0_i (c1_ty0 ),
.tz0_i (c1_tz0 ),
.tx1_i (c1_tx1 ),
.ty1_i (c1_ty1 ),
.tz1_i (c1_tz1 ),
.m_wb_adr_o (c1_wb_adr_o),
.m_wb_dat_i (c1_wb_dat_i),
.m_wb_cyc_o (c1_wb_cyc_o),
.m_wb_stb_o (c1_wb_stb_o),
.m_wb_ack_i (c1_wb_ack_i),
.finished_o (c1_finished ),
.leaf_o (c1_leaf),
.t_o (c1_final_t ),
.level_o (c1_final_level )
);
`endif
`ifdef CORE2
raycast_core core2
(
.clk (wb_clk ),
.rst (wb_rst ),
.start_i (c2_start ),
.root_adr_i (c2_root_adr ),
.dir_mask_i (c2_dir_mask ),
.tx0_i (c2_tx0 ),
.ty0_i (c2_ty0 ),
.tz0_i (c2_tz0 ),
.tx1_i (c2_tx1 ),
.ty1_i (c2_ty1 ),
.tz1_i (c2_tz1 ),
.m_wb_adr_o (c2_wb_adr_o),
.m_wb_dat_i (c2_wb_dat_i),
.m_wb_cyc_o (c2_wb_cyc_o),
.m_wb_stb_o (c2_wb_stb_o),
.m_wb_ack_i (c2_wb_ack_i),
.finished_o (c2_finished ),
.leaf_o (c2_leaf),
.t_o (c2_final_t ),
.level_o (c2_final_level )
);
`endif
`ifdef CORE3
raycast_core core3
(
.clk (wb_clk ),
.rst (wb_rst ),
.start_i (c3_start ),
.root_adr_i (c3_root_adr ),
.dir_mask_i (c3_dir_mask ),
.tx0_i (c3_tx0 ),
.ty0_i (c3_ty0 ),
.tz0_i (c3_tz0 ),
.tx1_i (c3_tx1 ),
.ty1_i (c3_ty1 ),
.tz1_i (c3_tz1 ),
.m_wb_adr_o (c3_wb_adr_o),
.m_wb_dat_i (c3_wb_dat_i),
.m_wb_cyc_o (c3_wb_cyc_o),
.m_wb_stb_o (c3_wb_stb_o),
.m_wb_ack_i (c3_wb_ack_i),
.finished_o (c3_finished ),
.leaf_o (c3_leaf),
.t_o (c3_final_t ),
.level_o (c3_final_level )
);
`endif
// --
endmodule
|
module TimeHoldOver_Qsys (
input wire clk_clk, // clk.clk
output wire epcs_flash_controller_dclk, // epcs_flash_controller.dclk
output wire epcs_flash_controller_sce, // .sce
output wire epcs_flash_controller_sdo, // .sdo
input wire epcs_flash_controller_data0, // .data0
output wire io_update_ctrl_export, // io_update_ctrl.export
input wire ocxo_lock_export, // ocxo_lock.export
output wire [8:0] on_chip_rst_and_pps_switch_export, // on_chip_rst_and_pps_switch.export
input wire pps_interrupt_export, // pps_interrupt.export
input wire reset_reset_n, // reset.reset_n
output wire [11:0] sdram_controller_addr, // sdram_controller.addr
output wire [1:0] sdram_controller_ba, // .ba
output wire sdram_controller_cas_n, // .cas_n
output wire sdram_controller_cke, // .cke
output wire sdram_controller_cs_n, // .cs_n
inout wire [15:0] sdram_controller_dq, // .dq
output wire [1:0] sdram_controller_dqm, // .dqm
output wire sdram_controller_ras_n, // .ras_n
output wire sdram_controller_we_n, // .we_n
input wire timer_ecc_fault_itr_export, // timer_ecc_fault_itr.export
output wire [192:0] timer_interface_coe_sec_cnt_set_data_out, // timer_interface.coe_sec_cnt_set_data_out
input wire [191:0] timer_interface_coe_sec_cnt_get_data_in, // .coe_sec_cnt_get_data_in
output wire [96:0] timer_interface_coe_ns_cnt_set_data_out, // .coe_ns_cnt_set_data_out
input wire [95:0] timer_interface_coe_ns_cnt_get_data_in, // .coe_ns_cnt_get_data_in
output wire [24:0] timer_interface_coe_ctrl_cnt_set_out, // .coe_ctrl_cnt_set_out
input wire [23:0] timer_interface_coe_ctrl_cnt_get_in, // .coe_ctrl_cnt_get_in
input wire [23:0] timer_interface_coe_err_cnt_in, // .coe_err_cnt_in
input wire [55:0] timer_interface_coe_utc_time_in, // .coe_utc_time_in
output wire [8:0] timer_interface_coe_time_zone_set_out, // .coe_time_zone_set_out
input wire [7:0] timer_interface_coe_time_zone_get_in, // .coe_time_zone_get_in
output wire [16:0] timer_interface_coe_leap_cnt_set_out, // .coe_leap_cnt_set_out
input wire [15:0] timer_interface_coe_leap_cnt_get_in, // .coe_leap_cnt_get_in
output wire [64:0] timer_interface_coe_leap_occur_set_out, // .coe_leap_occur_set_out
input wire [63:0] timer_interface_coe_leap_occur_get_in, // .coe_leap_occur_get_in
output wire [64:0] timer_interface_coe_dst_ingress_set_out, // .coe_dst_ingress_set_out
input wire [63:0] timer_interface_coe_dst_ingress_get_in, // .coe_dst_ingress_get_in
output wire [64:0] timer_interface_coe_dst_engress_set_out, // .coe_dst_engress_set_out
input wire [63:0] timer_interface_coe_dst_engress_get_in, // .coe_dst_engress_get_in
input wire [7:0] timer_interface_coe_leap_direct_get_in, // .coe_leap_direct_get_in
output wire [8:0] timer_interface_coe_leap_direct_set_out, // .coe_leap_direct_set_out
input wire timer_interface_coe_io_update_in, // .coe_io_update_in
input wire [7:0] timer_interface_coe_time_quality_get_in, // .coe_time_quality_get_in
output wire [8:0] timer_interface_coe_time_quality_set_out, // .coe_time_quality_set_out
input wire uart_0_external_connection_rxd, // uart_0_external_connection.rxd
output wire uart_0_external_connection_txd, // .txd
input wire uart_1_external_connection_rxd, // uart_1_external_connection.rxd
output wire uart_1_external_connection_txd, // .txd
input wire uart_2_external_connection_rxd, // uart_2_external_connection.rxd
output wire uart_2_external_connection_txd, // .txd
input wire uart_3_external_connection_rxd, // uart_3_external_connection.rxd
output wire uart_3_external_connection_txd // .txd
);
wire [31:0] nios2_gen2_0_data_master_readdata; // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
wire nios2_gen2_0_data_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
wire nios2_gen2_0_data_master_debugaccess; // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
wire [24:0] nios2_gen2_0_data_master_address; // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
wire [3:0] nios2_gen2_0_data_master_byteenable; // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
wire nios2_gen2_0_data_master_read; // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
wire nios2_gen2_0_data_master_readdatavalid; // mm_interconnect_0:nios2_gen2_0_data_master_readdatavalid -> nios2_gen2_0:d_readdatavalid
wire nios2_gen2_0_data_master_write; // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
wire [31:0] nios2_gen2_0_data_master_writedata; // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
wire [31:0] nios2_gen2_0_instruction_master_readdata; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
wire nios2_gen2_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
wire [24:0] nios2_gen2_0_instruction_master_address; // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
wire nios2_gen2_0_instruction_master_read; // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
wire nios2_gen2_0_instruction_master_readdatavalid; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdatavalid -> nios2_gen2_0:i_readdatavalid
wire [31:0] mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata; // avalon_mapped_timer_reg_buf_0:avs_readdata -> mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata
wire [4:0] mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_address; // mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_address -> avalon_mapped_timer_reg_buf_0:avs_address
wire mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_read; // mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_read -> avalon_mapped_timer_reg_buf_0:avs_read_n
wire mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_write; // mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_write -> avalon_mapped_timer_reg_buf_0:avs_write_n
wire [31:0] mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata; // mm_interconnect_0:avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata -> avalon_mapped_timer_reg_buf_0:avs_writedata
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata; // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
wire mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_chipselect -> epcs_flash_controller_0:chipselect
wire [31:0] mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata; // epcs_flash_controller_0:readdata -> mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_readdata
wire [8:0] mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_address -> epcs_flash_controller_0:address
wire mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_read -> epcs_flash_controller_0:read_n
wire mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_write -> epcs_flash_controller_0:write_n
wire [31:0] mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata; // mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_writedata -> epcs_flash_controller_0:writedata
wire mm_interconnect_0_onchip_rst_and_pps_switch_s1_chipselect; // mm_interconnect_0:onchip_rst_and_pps_switch_s1_chipselect -> onchip_rst_and_pps_switch:chipselect
wire [31:0] mm_interconnect_0_onchip_rst_and_pps_switch_s1_readdata; // onchip_rst_and_pps_switch:readdata -> mm_interconnect_0:onchip_rst_and_pps_switch_s1_readdata
wire [1:0] mm_interconnect_0_onchip_rst_and_pps_switch_s1_address; // mm_interconnect_0:onchip_rst_and_pps_switch_s1_address -> onchip_rst_and_pps_switch:address
wire mm_interconnect_0_onchip_rst_and_pps_switch_s1_write; // mm_interconnect_0:onchip_rst_and_pps_switch_s1_write -> onchip_rst_and_pps_switch:write_n
wire [31:0] mm_interconnect_0_onchip_rst_and_pps_switch_s1_writedata; // mm_interconnect_0:onchip_rst_and_pps_switch_s1_writedata -> onchip_rst_and_pps_switch:writedata
wire mm_interconnect_0_io_update_s1_chipselect; // mm_interconnect_0:io_update_s1_chipselect -> io_update:chipselect
wire [31:0] mm_interconnect_0_io_update_s1_readdata; // io_update:readdata -> mm_interconnect_0:io_update_s1_readdata
wire [1:0] mm_interconnect_0_io_update_s1_address; // mm_interconnect_0:io_update_s1_address -> io_update:address
wire mm_interconnect_0_io_update_s1_write; // mm_interconnect_0:io_update_s1_write -> io_update:write_n
wire [31:0] mm_interconnect_0_io_update_s1_writedata; // mm_interconnect_0:io_update_s1_writedata -> io_update:writedata
wire mm_interconnect_0_ocxo_lock_s1_chipselect; // mm_interconnect_0:ocxo_lock_s1_chipselect -> ocxo_lock:chipselect
wire [31:0] mm_interconnect_0_ocxo_lock_s1_readdata; // ocxo_lock:readdata -> mm_interconnect_0:ocxo_lock_s1_readdata
wire [1:0] mm_interconnect_0_ocxo_lock_s1_address; // mm_interconnect_0:ocxo_lock_s1_address -> ocxo_lock:address
wire mm_interconnect_0_ocxo_lock_s1_write; // mm_interconnect_0:ocxo_lock_s1_write -> ocxo_lock:write_n
wire [31:0] mm_interconnect_0_ocxo_lock_s1_writedata; // mm_interconnect_0:ocxo_lock_s1_writedata -> ocxo_lock:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [11:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_pps_interrupt_s1_chipselect; // mm_interconnect_0:pps_interrupt_s1_chipselect -> pps_interrupt:chipselect
wire [31:0] mm_interconnect_0_pps_interrupt_s1_readdata; // pps_interrupt:readdata -> mm_interconnect_0:pps_interrupt_s1_readdata
wire [1:0] mm_interconnect_0_pps_interrupt_s1_address; // mm_interconnect_0:pps_interrupt_s1_address -> pps_interrupt:address
wire mm_interconnect_0_pps_interrupt_s1_write; // mm_interconnect_0:pps_interrupt_s1_write -> pps_interrupt:write_n
wire [31:0] mm_interconnect_0_pps_interrupt_s1_writedata; // mm_interconnect_0:pps_interrupt_s1_writedata -> pps_interrupt:writedata
wire mm_interconnect_0_timer_ecc_fault_itr_s1_chipselect; // mm_interconnect_0:timer_ecc_fault_itr_s1_chipselect -> timer_ecc_fault_itr:chipselect
wire [31:0] mm_interconnect_0_timer_ecc_fault_itr_s1_readdata; // timer_ecc_fault_itr:readdata -> mm_interconnect_0:timer_ecc_fault_itr_s1_readdata
wire [1:0] mm_interconnect_0_timer_ecc_fault_itr_s1_address; // mm_interconnect_0:timer_ecc_fault_itr_s1_address -> timer_ecc_fault_itr:address
wire mm_interconnect_0_timer_ecc_fault_itr_s1_write; // mm_interconnect_0:timer_ecc_fault_itr_s1_write -> timer_ecc_fault_itr:write_n
wire [31:0] mm_interconnect_0_timer_ecc_fault_itr_s1_writedata; // mm_interconnect_0:timer_ecc_fault_itr_s1_writedata -> timer_ecc_fault_itr:writedata
wire mm_interconnect_0_sdram_controller_0_s1_chipselect; // mm_interconnect_0:sdram_controller_0_s1_chipselect -> sdram_controller_0:az_cs
wire [15:0] mm_interconnect_0_sdram_controller_0_s1_readdata; // sdram_controller_0:za_data -> mm_interconnect_0:sdram_controller_0_s1_readdata
wire mm_interconnect_0_sdram_controller_0_s1_waitrequest; // sdram_controller_0:za_waitrequest -> mm_interconnect_0:sdram_controller_0_s1_waitrequest
wire [21:0] mm_interconnect_0_sdram_controller_0_s1_address; // mm_interconnect_0:sdram_controller_0_s1_address -> sdram_controller_0:az_addr
wire mm_interconnect_0_sdram_controller_0_s1_read; // mm_interconnect_0:sdram_controller_0_s1_read -> sdram_controller_0:az_rd_n
wire [1:0] mm_interconnect_0_sdram_controller_0_s1_byteenable; // mm_interconnect_0:sdram_controller_0_s1_byteenable -> sdram_controller_0:az_be_n
wire mm_interconnect_0_sdram_controller_0_s1_readdatavalid; // sdram_controller_0:za_valid -> mm_interconnect_0:sdram_controller_0_s1_readdatavalid
wire mm_interconnect_0_sdram_controller_0_s1_write; // mm_interconnect_0:sdram_controller_0_s1_write -> sdram_controller_0:az_wr_n
wire [15:0] mm_interconnect_0_sdram_controller_0_s1_writedata; // mm_interconnect_0:sdram_controller_0_s1_writedata -> sdram_controller_0:az_data
wire mm_interconnect_0_uart_0_s1_chipselect; // mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
wire [15:0] mm_interconnect_0_uart_0_s1_readdata; // uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
wire [2:0] mm_interconnect_0_uart_0_s1_address; // mm_interconnect_0:uart_0_s1_address -> uart_0:address
wire mm_interconnect_0_uart_0_s1_read; // mm_interconnect_0:uart_0_s1_read -> uart_0:read_n
wire mm_interconnect_0_uart_0_s1_begintransfer; // mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
wire mm_interconnect_0_uart_0_s1_write; // mm_interconnect_0:uart_0_s1_write -> uart_0:write_n
wire [15:0] mm_interconnect_0_uart_0_s1_writedata; // mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
wire mm_interconnect_0_uart_1_s1_chipselect; // mm_interconnect_0:uart_1_s1_chipselect -> uart_1:chipselect
wire [15:0] mm_interconnect_0_uart_1_s1_readdata; // uart_1:readdata -> mm_interconnect_0:uart_1_s1_readdata
wire [2:0] mm_interconnect_0_uart_1_s1_address; // mm_interconnect_0:uart_1_s1_address -> uart_1:address
wire mm_interconnect_0_uart_1_s1_read; // mm_interconnect_0:uart_1_s1_read -> uart_1:read_n
wire mm_interconnect_0_uart_1_s1_begintransfer; // mm_interconnect_0:uart_1_s1_begintransfer -> uart_1:begintransfer
wire mm_interconnect_0_uart_1_s1_write; // mm_interconnect_0:uart_1_s1_write -> uart_1:write_n
wire [15:0] mm_interconnect_0_uart_1_s1_writedata; // mm_interconnect_0:uart_1_s1_writedata -> uart_1:writedata
wire mm_interconnect_0_uart_2_s1_chipselect; // mm_interconnect_0:uart_2_s1_chipselect -> uart_2:chipselect
wire [15:0] mm_interconnect_0_uart_2_s1_readdata; // uart_2:readdata -> mm_interconnect_0:uart_2_s1_readdata
wire [2:0] mm_interconnect_0_uart_2_s1_address; // mm_interconnect_0:uart_2_s1_address -> uart_2:address
wire mm_interconnect_0_uart_2_s1_read; // mm_interconnect_0:uart_2_s1_read -> uart_2:read_n
wire mm_interconnect_0_uart_2_s1_begintransfer; // mm_interconnect_0:uart_2_s1_begintransfer -> uart_2:begintransfer
wire mm_interconnect_0_uart_2_s1_write; // mm_interconnect_0:uart_2_s1_write -> uart_2:write_n
wire [15:0] mm_interconnect_0_uart_2_s1_writedata; // mm_interconnect_0:uart_2_s1_writedata -> uart_2:writedata
wire mm_interconnect_0_uart_3_s1_chipselect; // mm_interconnect_0:uart_3_s1_chipselect -> uart_3:chipselect
wire [15:0] mm_interconnect_0_uart_3_s1_readdata; // uart_3:readdata -> mm_interconnect_0:uart_3_s1_readdata
wire [2:0] mm_interconnect_0_uart_3_s1_address; // mm_interconnect_0:uart_3_s1_address -> uart_3:address
wire mm_interconnect_0_uart_3_s1_read; // mm_interconnect_0:uart_3_s1_read -> uart_3:read_n
wire mm_interconnect_0_uart_3_s1_begintransfer; // mm_interconnect_0:uart_3_s1_begintransfer -> uart_3:begintransfer
wire mm_interconnect_0_uart_3_s1_write; // mm_interconnect_0:uart_3_s1_write -> uart_3:write_n
wire [15:0] mm_interconnect_0_uart_3_s1_writedata; // mm_interconnect_0:uart_3_s1_writedata -> uart_3:writedata
wire irq_mapper_receiver0_irq; // uart_0:irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // uart_1:irq -> irq_mapper:receiver1_irq
wire irq_mapper_receiver2_irq; // uart_2:irq -> irq_mapper:receiver2_irq
wire irq_mapper_receiver3_irq; // uart_3:irq -> irq_mapper:receiver3_irq
wire irq_mapper_receiver4_irq; // pps_interrupt:irq -> irq_mapper:receiver4_irq
wire irq_mapper_receiver5_irq; // timer_ecc_fault_itr:irq -> irq_mapper:receiver5_irq
wire irq_mapper_receiver6_irq; // ocxo_lock:irq -> irq_mapper:receiver6_irq
wire irq_mapper_receiver7_irq; // epcs_flash_controller_0:irq -> irq_mapper:receiver7_irq
wire [31:0] nios2_gen2_0_irq_irq; // irq_mapper:sender_irq -> nios2_gen2_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [avalon_mapped_timer_reg_buf_0:csi_reset_n, epcs_flash_controller_0:reset_n, io_update:reset_n, irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, ocxo_lock:reset_n, onchip_memory2_0:reset, onchip_rst_and_pps_switch:reset_n, pps_interrupt:reset_n, rst_translator:in_reset, sdram_controller_0:reset_n, timer_ecc_fault_itr:reset_n, uart_0:reset_n, uart_1:reset_n, uart_2:reset_n, uart_3:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [epcs_flash_controller_0:reset_req, nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire nios2_gen2_0_debug_reset_request_reset; // nios2_gen2_0:debug_reset_request -> rst_controller:reset_in1
TimeHoldOver_Qsys_avalon_mapped_timer_reg_buf_0 avalon_mapped_timer_reg_buf_0 (
.csi_clk (clk_clk), // clock.clk
.csi_reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.coe_sec_cnt_set_data_out (timer_interface_coe_sec_cnt_set_data_out), // timer_interface.coe_sec_cnt_set_data_out
.coe_sec_cnt_get_data_in (timer_interface_coe_sec_cnt_get_data_in), // .coe_sec_cnt_get_data_in
.coe_ns_cnt_set_data_out (timer_interface_coe_ns_cnt_set_data_out), // .coe_ns_cnt_set_data_out
.coe_ns_cnt_get_data_in (timer_interface_coe_ns_cnt_get_data_in), // .coe_ns_cnt_get_data_in
.coe_ctrl_cnt_set_out (timer_interface_coe_ctrl_cnt_set_out), // .coe_ctrl_cnt_set_out
.coe_ctrl_cnt_get_in (timer_interface_coe_ctrl_cnt_get_in), // .coe_ctrl_cnt_get_in
.coe_err_cnt_in (timer_interface_coe_err_cnt_in), // .coe_err_cnt_in
.coe_utc_time_in (timer_interface_coe_utc_time_in), // .coe_utc_time_in
.coe_time_zone_set_out (timer_interface_coe_time_zone_set_out), // .coe_time_zone_set_out
.coe_time_zone_get_in (timer_interface_coe_time_zone_get_in), // .coe_time_zone_get_in
.coe_leap_cnt_set_out (timer_interface_coe_leap_cnt_set_out), // .coe_leap_cnt_set_out
.coe_leap_cnt_get_in (timer_interface_coe_leap_cnt_get_in), // .coe_leap_cnt_get_in
.coe_leap_occur_set_out (timer_interface_coe_leap_occur_set_out), // .coe_leap_occur_set_out
.coe_leap_occur_get_in (timer_interface_coe_leap_occur_get_in), // .coe_leap_occur_get_in
.coe_dst_ingress_set_out (timer_interface_coe_dst_ingress_set_out), // .coe_dst_ingress_set_out
.coe_dst_ingress_get_in (timer_interface_coe_dst_ingress_get_in), // .coe_dst_ingress_get_in
.coe_dst_engress_set_out (timer_interface_coe_dst_engress_set_out), // .coe_dst_engress_set_out
.coe_dst_engress_get_in (timer_interface_coe_dst_engress_get_in), // .coe_dst_engress_get_in
.coe_leap_direct_get_in (timer_interface_coe_leap_direct_get_in), // .coe_leap_direct_get_in
.coe_leap_direct_set_out (timer_interface_coe_leap_direct_set_out), // .coe_leap_direct_set_out
.coe_io_update_in (timer_interface_coe_io_update_in), // .coe_io_update_in
.coe_time_quality_get_in (timer_interface_coe_time_quality_get_in), // .coe_time_quality_get_in
.coe_time_quality_set_out (timer_interface_coe_time_quality_set_out), // .coe_time_quality_set_out
.avs_address (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_address), // avalon_slave_0.address
.avs_read_n (~mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_read), // .read_n
.avs_readdata (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata), // .readdata
.avs_write_n (~mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_write), // .write_n
.avs_writedata (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata) // .writedata
);
TimeHoldOver_Qsys_epcs_flash_controller_0 epcs_flash_controller_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.address (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address), // epcs_control_port.address
.chipselect (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect), // .chipselect
.read_n (~mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read), // .read_n
.readdata (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata), // .readdata
.write_n (~mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write), // .write_n
.writedata (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata), // .writedata
.irq (irq_mapper_receiver7_irq), // irq.irq
.dclk (epcs_flash_controller_dclk), // external.export
.sce (epcs_flash_controller_sce), // .export
.sdo (epcs_flash_controller_sdo), // .export
.data0 (epcs_flash_controller_data0) // .export
);
TimeHoldOver_Qsys_io_update io_update (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_io_update_s1_address), // s1.address
.write_n (~mm_interconnect_0_io_update_s1_write), // .write_n
.writedata (mm_interconnect_0_io_update_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_io_update_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_io_update_s1_readdata), // .readdata
.out_port (io_update_ctrl_export) // external_connection.export
);
TimeHoldOver_Qsys_nios2_gen2_0 nios2_gen2_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_gen2_0_data_master_address), // data_master.address
.d_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.d_read (nios2_gen2_0_data_master_read), // .read
.d_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_gen2_0_data_master_write), // .write
.d_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.d_readdatavalid (nios2_gen2_0_data_master_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_gen2_0_instruction_master_address), // instruction_master.address
.i_read (nios2_gen2_0_instruction_master_read), // .read
.i_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.i_readdatavalid (nios2_gen2_0_instruction_master_readdatavalid), // .readdatavalid
.irq (nios2_gen2_0_irq_irq), // irq.irq
.debug_reset_request (nios2_gen2_0_debug_reset_request_reset), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
TimeHoldOver_Qsys_ocxo_lock ocxo_lock (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_ocxo_lock_s1_address), // s1.address
.write_n (~mm_interconnect_0_ocxo_lock_s1_write), // .write_n
.writedata (mm_interconnect_0_ocxo_lock_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_ocxo_lock_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_ocxo_lock_s1_readdata), // .readdata
.in_port (ocxo_lock_export), // external_connection.export
.irq (irq_mapper_receiver6_irq) // irq.irq
);
TimeHoldOver_Qsys_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
TimeHoldOver_Qsys_onchip_rst_and_pps_switch onchip_rst_and_pps_switch (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_onchip_rst_and_pps_switch_s1_address), // s1.address
.write_n (~mm_interconnect_0_onchip_rst_and_pps_switch_s1_write), // .write_n
.writedata (mm_interconnect_0_onchip_rst_and_pps_switch_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_onchip_rst_and_pps_switch_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_onchip_rst_and_pps_switch_s1_readdata), // .readdata
.out_port (on_chip_rst_and_pps_switch_export) // external_connection.export
);
TimeHoldOver_Qsys_pps_interrupt pps_interrupt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pps_interrupt_s1_address), // s1.address
.write_n (~mm_interconnect_0_pps_interrupt_s1_write), // .write_n
.writedata (mm_interconnect_0_pps_interrupt_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pps_interrupt_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pps_interrupt_s1_readdata), // .readdata
.in_port (pps_interrupt_export), // external_connection.export
.irq (irq_mapper_receiver4_irq) // irq.irq
);
TimeHoldOver_Qsys_sdram_controller_0 sdram_controller_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_controller_0_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_controller_0_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_controller_0_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_controller_0_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_controller_0_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_controller_0_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_controller_0_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_controller_0_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_controller_0_s1_waitrequest), // .waitrequest
.zs_addr (sdram_controller_addr), // wire.export
.zs_ba (sdram_controller_ba), // .export
.zs_cas_n (sdram_controller_cas_n), // .export
.zs_cke (sdram_controller_cke), // .export
.zs_cs_n (sdram_controller_cs_n), // .export
.zs_dq (sdram_controller_dq), // .export
.zs_dqm (sdram_controller_dqm), // .export
.zs_ras_n (sdram_controller_ras_n), // .export
.zs_we_n (sdram_controller_we_n) // .export
);
TimeHoldOver_Qsys_pps_interrupt timer_ecc_fault_itr (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_timer_ecc_fault_itr_s1_address), // s1.address
.write_n (~mm_interconnect_0_timer_ecc_fault_itr_s1_write), // .write_n
.writedata (mm_interconnect_0_timer_ecc_fault_itr_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_timer_ecc_fault_itr_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_timer_ecc_fault_itr_s1_readdata), // .readdata
.in_port (timer_ecc_fault_itr_export), // external_connection.export
.irq (irq_mapper_receiver5_irq) // irq.irq
);
TimeHoldOver_Qsys_uart_0 uart_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_0_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_0_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_0_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_0_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.rxd (uart_0_external_connection_rxd), // external_connection.export
.txd (uart_0_external_connection_txd), // .export
.irq (irq_mapper_receiver0_irq) // irq.irq
);
TimeHoldOver_Qsys_uart_0 uart_1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_1_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_1_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_1_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_1_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_1_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_1_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_1_s1_readdata), // .readdata
.rxd (uart_1_external_connection_rxd), // external_connection.export
.txd (uart_1_external_connection_txd), // .export
.irq (irq_mapper_receiver1_irq) // irq.irq
);
TimeHoldOver_Qsys_uart_0 uart_2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_2_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_2_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_2_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_2_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_2_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_2_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_2_s1_readdata), // .readdata
.rxd (uart_2_external_connection_rxd), // external_connection.export
.txd (uart_2_external_connection_txd), // .export
.irq (irq_mapper_receiver2_irq) // irq.irq
);
TimeHoldOver_Qsys_uart_0 uart_3 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_3_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_3_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_3_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_3_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_3_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_3_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_3_s1_readdata), // .readdata
.rxd (uart_3_external_connection_rxd), // external_connection.export
.txd (uart_3_external_connection_txd), // .export
.irq (irq_mapper_receiver3_irq) // irq.irq
);
TimeHoldOver_Qsys_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_gen2_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_data_master_address (nios2_gen2_0_data_master_address), // nios2_gen2_0_data_master.address
.nios2_gen2_0_data_master_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.nios2_gen2_0_data_master_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.nios2_gen2_0_data_master_read (nios2_gen2_0_data_master_read), // .read
.nios2_gen2_0_data_master_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.nios2_gen2_0_data_master_readdatavalid (nios2_gen2_0_data_master_readdatavalid), // .readdatavalid
.nios2_gen2_0_data_master_write (nios2_gen2_0_data_master_write), // .write
.nios2_gen2_0_data_master_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.nios2_gen2_0_data_master_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.nios2_gen2_0_instruction_master_address (nios2_gen2_0_instruction_master_address), // nios2_gen2_0_instruction_master.address
.nios2_gen2_0_instruction_master_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.nios2_gen2_0_instruction_master_read (nios2_gen2_0_instruction_master_read), // .read
.nios2_gen2_0_instruction_master_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.nios2_gen2_0_instruction_master_readdatavalid (nios2_gen2_0_instruction_master_readdatavalid), // .readdatavalid
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_address (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_address), // avalon_mapped_timer_reg_buf_0_avalon_slave_0.address
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_write (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_write), // .write
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_read (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_read), // .read
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata), // .readdata
.avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata (mm_interconnect_0_avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata), // .writedata
.epcs_flash_controller_0_epcs_control_port_address (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address), // epcs_flash_controller_0_epcs_control_port.address
.epcs_flash_controller_0_epcs_control_port_write (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write), // .write
.epcs_flash_controller_0_epcs_control_port_read (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read), // .read
.epcs_flash_controller_0_epcs_control_port_readdata (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata), // .readdata
.epcs_flash_controller_0_epcs_control_port_writedata (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata), // .writedata
.epcs_flash_controller_0_epcs_control_port_chipselect (mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect), // .chipselect
.io_update_s1_address (mm_interconnect_0_io_update_s1_address), // io_update_s1.address
.io_update_s1_write (mm_interconnect_0_io_update_s1_write), // .write
.io_update_s1_readdata (mm_interconnect_0_io_update_s1_readdata), // .readdata
.io_update_s1_writedata (mm_interconnect_0_io_update_s1_writedata), // .writedata
.io_update_s1_chipselect (mm_interconnect_0_io_update_s1_chipselect), // .chipselect
.nios2_gen2_0_debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // nios2_gen2_0_debug_mem_slave.address
.nios2_gen2_0_debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.nios2_gen2_0_debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.nios2_gen2_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.nios2_gen2_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.nios2_gen2_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.nios2_gen2_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.ocxo_lock_s1_address (mm_interconnect_0_ocxo_lock_s1_address), // ocxo_lock_s1.address
.ocxo_lock_s1_write (mm_interconnect_0_ocxo_lock_s1_write), // .write
.ocxo_lock_s1_readdata (mm_interconnect_0_ocxo_lock_s1_readdata), // .readdata
.ocxo_lock_s1_writedata (mm_interconnect_0_ocxo_lock_s1_writedata), // .writedata
.ocxo_lock_s1_chipselect (mm_interconnect_0_ocxo_lock_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.onchip_rst_and_pps_switch_s1_address (mm_interconnect_0_onchip_rst_and_pps_switch_s1_address), // onchip_rst_and_pps_switch_s1.address
.onchip_rst_and_pps_switch_s1_write (mm_interconnect_0_onchip_rst_and_pps_switch_s1_write), // .write
.onchip_rst_and_pps_switch_s1_readdata (mm_interconnect_0_onchip_rst_and_pps_switch_s1_readdata), // .readdata
.onchip_rst_and_pps_switch_s1_writedata (mm_interconnect_0_onchip_rst_and_pps_switch_s1_writedata), // .writedata
.onchip_rst_and_pps_switch_s1_chipselect (mm_interconnect_0_onchip_rst_and_pps_switch_s1_chipselect), // .chipselect
.pps_interrupt_s1_address (mm_interconnect_0_pps_interrupt_s1_address), // pps_interrupt_s1.address
.pps_interrupt_s1_write (mm_interconnect_0_pps_interrupt_s1_write), // .write
.pps_interrupt_s1_readdata (mm_interconnect_0_pps_interrupt_s1_readdata), // .readdata
.pps_interrupt_s1_writedata (mm_interconnect_0_pps_interrupt_s1_writedata), // .writedata
.pps_interrupt_s1_chipselect (mm_interconnect_0_pps_interrupt_s1_chipselect), // .chipselect
.sdram_controller_0_s1_address (mm_interconnect_0_sdram_controller_0_s1_address), // sdram_controller_0_s1.address
.sdram_controller_0_s1_write (mm_interconnect_0_sdram_controller_0_s1_write), // .write
.sdram_controller_0_s1_read (mm_interconnect_0_sdram_controller_0_s1_read), // .read
.sdram_controller_0_s1_readdata (mm_interconnect_0_sdram_controller_0_s1_readdata), // .readdata
.sdram_controller_0_s1_writedata (mm_interconnect_0_sdram_controller_0_s1_writedata), // .writedata
.sdram_controller_0_s1_byteenable (mm_interconnect_0_sdram_controller_0_s1_byteenable), // .byteenable
.sdram_controller_0_s1_readdatavalid (mm_interconnect_0_sdram_controller_0_s1_readdatavalid), // .readdatavalid
.sdram_controller_0_s1_waitrequest (mm_interconnect_0_sdram_controller_0_s1_waitrequest), // .waitrequest
.sdram_controller_0_s1_chipselect (mm_interconnect_0_sdram_controller_0_s1_chipselect), // .chipselect
.timer_ecc_fault_itr_s1_address (mm_interconnect_0_timer_ecc_fault_itr_s1_address), // timer_ecc_fault_itr_s1.address
.timer_ecc_fault_itr_s1_write (mm_interconnect_0_timer_ecc_fault_itr_s1_write), // .write
.timer_ecc_fault_itr_s1_readdata (mm_interconnect_0_timer_ecc_fault_itr_s1_readdata), // .readdata
.timer_ecc_fault_itr_s1_writedata (mm_interconnect_0_timer_ecc_fault_itr_s1_writedata), // .writedata
.timer_ecc_fault_itr_s1_chipselect (mm_interconnect_0_timer_ecc_fault_itr_s1_chipselect), // .chipselect
.uart_0_s1_address (mm_interconnect_0_uart_0_s1_address), // uart_0_s1.address
.uart_0_s1_write (mm_interconnect_0_uart_0_s1_write), // .write
.uart_0_s1_read (mm_interconnect_0_uart_0_s1_read), // .read
.uart_0_s1_readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.uart_0_s1_writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.uart_0_s1_begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.uart_0_s1_chipselect (mm_interconnect_0_uart_0_s1_chipselect), // .chipselect
.uart_1_s1_address (mm_interconnect_0_uart_1_s1_address), // uart_1_s1.address
.uart_1_s1_write (mm_interconnect_0_uart_1_s1_write), // .write
.uart_1_s1_read (mm_interconnect_0_uart_1_s1_read), // .read
.uart_1_s1_readdata (mm_interconnect_0_uart_1_s1_readdata), // .readdata
.uart_1_s1_writedata (mm_interconnect_0_uart_1_s1_writedata), // .writedata
.uart_1_s1_begintransfer (mm_interconnect_0_uart_1_s1_begintransfer), // .begintransfer
.uart_1_s1_chipselect (mm_interconnect_0_uart_1_s1_chipselect), // .chipselect
.uart_2_s1_address (mm_interconnect_0_uart_2_s1_address), // uart_2_s1.address
.uart_2_s1_write (mm_interconnect_0_uart_2_s1_write), // .write
.uart_2_s1_read (mm_interconnect_0_uart_2_s1_read), // .read
.uart_2_s1_readdata (mm_interconnect_0_uart_2_s1_readdata), // .readdata
.uart_2_s1_writedata (mm_interconnect_0_uart_2_s1_writedata), // .writedata
.uart_2_s1_begintransfer (mm_interconnect_0_uart_2_s1_begintransfer), // .begintransfer
.uart_2_s1_chipselect (mm_interconnect_0_uart_2_s1_chipselect), // .chipselect
.uart_3_s1_address (mm_interconnect_0_uart_3_s1_address), // uart_3_s1.address
.uart_3_s1_write (mm_interconnect_0_uart_3_s1_write), // .write
.uart_3_s1_read (mm_interconnect_0_uart_3_s1_read), // .read
.uart_3_s1_readdata (mm_interconnect_0_uart_3_s1_readdata), // .readdata
.uart_3_s1_writedata (mm_interconnect_0_uart_3_s1_writedata), // .writedata
.uart_3_s1_begintransfer (mm_interconnect_0_uart_3_s1_begintransfer), // .begintransfer
.uart_3_s1_chipselect (mm_interconnect_0_uart_3_s1_chipselect) // .chipselect
);
TimeHoldOver_Qsys_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.receiver3_irq (irq_mapper_receiver3_irq), // receiver3.irq
.receiver4_irq (irq_mapper_receiver4_irq), // receiver4.irq
.receiver5_irq (irq_mapper_receiver5_irq), // receiver5.irq
.receiver6_irq (irq_mapper_receiver6_irq), // receiver6.irq
.receiver7_irq (irq_mapper_receiver7_irq), // receiver7.irq
.sender_irq (nios2_gen2_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (nios2_gen2_0_debug_reset_request_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module fifo_w16_d2_A_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
|
module fifo_w16_d2_A (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
fifo_w16_d2_A_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_fifo_w16_d2_A_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
module usb_system_mm_interconnect_0 (
input wire clk_clk_clk, // clk_clk.clk
input wire clocks_c0_clk, // clocks_c0.clk
input wire cpu_reset_n_reset_bridge_in_reset_reset, // cpu_reset_n_reset_bridge_in_reset.reset
input wire sdram_reset_reset_bridge_in_reset_reset, // sdram_reset_reset_bridge_in_reset.reset
input wire [28:0] cpu_data_master_address, // cpu_data_master.address
output wire cpu_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_data_master_byteenable, // .byteenable
input wire cpu_data_master_read, // .read
output wire [31:0] cpu_data_master_readdata, // .readdata
input wire cpu_data_master_write, // .write
input wire [31:0] cpu_data_master_writedata, // .writedata
input wire cpu_data_master_debugaccess, // .debugaccess
input wire [28:0] cpu_instruction_master_address, // cpu_instruction_master.address
output wire cpu_instruction_master_waitrequest, // .waitrequest
input wire cpu_instruction_master_read, // .read
output wire [31:0] cpu_instruction_master_readdata, // .readdata
output wire [21:0] clock_crossing_io_s0_address, // clock_crossing_io_s0.address
output wire clock_crossing_io_s0_write, // .write
output wire clock_crossing_io_s0_read, // .read
input wire [31:0] clock_crossing_io_s0_readdata, // .readdata
output wire [31:0] clock_crossing_io_s0_writedata, // .writedata
output wire [0:0] clock_crossing_io_s0_burstcount, // .burstcount
output wire [3:0] clock_crossing_io_s0_byteenable, // .byteenable
input wire clock_crossing_io_s0_readdatavalid, // .readdatavalid
input wire clock_crossing_io_s0_waitrequest, // .waitrequest
output wire clock_crossing_io_s0_debugaccess, // .debugaccess
output wire [1:0] clocks_pll_slave_address, // clocks_pll_slave.address
output wire clocks_pll_slave_write, // .write
output wire clocks_pll_slave_read, // .read
input wire [31:0] clocks_pll_slave_readdata, // .readdata
output wire [31:0] clocks_pll_slave_writedata, // .writedata
output wire [8:0] cpu_jtag_debug_module_address, // cpu_jtag_debug_module.address
output wire cpu_jtag_debug_module_write, // .write
output wire cpu_jtag_debug_module_read, // .read
input wire [31:0] cpu_jtag_debug_module_readdata, // .readdata
output wire [31:0] cpu_jtag_debug_module_writedata, // .writedata
output wire [3:0] cpu_jtag_debug_module_byteenable, // .byteenable
input wire cpu_jtag_debug_module_waitrequest, // .waitrequest
output wire cpu_jtag_debug_module_debugaccess, // .debugaccess
output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address
output wire jtag_uart_avalon_jtag_slave_write, // .write
output wire jtag_uart_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] keycode_s1_address, // keycode_s1.address
output wire keycode_s1_write, // .write
input wire [31:0] keycode_s1_readdata, // .readdata
output wire [31:0] keycode_s1_writedata, // .writedata
output wire keycode_s1_chipselect, // .chipselect
output wire [24:0] sdram_s1_address, // sdram_s1.address
output wire sdram_s1_write, // .write
output wire sdram_s1_read, // .read
input wire [31:0] sdram_s1_readdata, // .readdata
output wire [31:0] sdram_s1_writedata, // .writedata
output wire [3:0] sdram_s1_byteenable, // .byteenable
input wire sdram_s1_readdatavalid, // .readdatavalid
input wire sdram_s1_waitrequest, // .waitrequest
output wire sdram_s1_chipselect // .chipselect
);
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
wire [28:0] cpu_data_master_translator_avalon_universal_master_0_address; // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_lock; // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
wire cpu_data_master_translator_avalon_universal_master_0_read; // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_data_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_data_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_data_master_agent:rp_startofpacket
wire [104:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_data_master_agent:rp_data
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel
wire rsp_mux_src_ready; // cpu_data_master_agent:rp_ready -> rsp_mux:src_ready
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
wire [28:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> cpu_instruction_master_agent:rp_valid
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
wire [104:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> cpu_instruction_master_agent:rp_data
wire [5:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel
wire rsp_mux_001_src_ready; // cpu_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
wire [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire [28:0] jtag_uart_avalon_jtag_slave_agent_m0_address; // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire jtag_uart_avalon_jtag_slave_agent_m0_write; // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire jtag_uart_avalon_jtag_slave_agent_m0_lock; // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_avalon_jtag_slave_agent_m0_read; // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire [105:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
wire [105:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
wire [104:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire cpu_jtag_debug_module_agent_m0_waitrequest; // cpu_jtag_debug_module_translator:uav_waitrequest -> cpu_jtag_debug_module_agent:m0_waitrequest
wire [2:0] cpu_jtag_debug_module_agent_m0_burstcount; // cpu_jtag_debug_module_agent:m0_burstcount -> cpu_jtag_debug_module_translator:uav_burstcount
wire [31:0] cpu_jtag_debug_module_agent_m0_writedata; // cpu_jtag_debug_module_agent:m0_writedata -> cpu_jtag_debug_module_translator:uav_writedata
wire [28:0] cpu_jtag_debug_module_agent_m0_address; // cpu_jtag_debug_module_agent:m0_address -> cpu_jtag_debug_module_translator:uav_address
wire cpu_jtag_debug_module_agent_m0_write; // cpu_jtag_debug_module_agent:m0_write -> cpu_jtag_debug_module_translator:uav_write
wire cpu_jtag_debug_module_agent_m0_lock; // cpu_jtag_debug_module_agent:m0_lock -> cpu_jtag_debug_module_translator:uav_lock
wire cpu_jtag_debug_module_agent_m0_read; // cpu_jtag_debug_module_agent:m0_read -> cpu_jtag_debug_module_translator:uav_read
wire [31:0] cpu_jtag_debug_module_agent_m0_readdata; // cpu_jtag_debug_module_translator:uav_readdata -> cpu_jtag_debug_module_agent:m0_readdata
wire cpu_jtag_debug_module_agent_m0_readdatavalid; // cpu_jtag_debug_module_translator:uav_readdatavalid -> cpu_jtag_debug_module_agent:m0_readdatavalid
wire cpu_jtag_debug_module_agent_m0_debugaccess; // cpu_jtag_debug_module_agent:m0_debugaccess -> cpu_jtag_debug_module_translator:uav_debugaccess
wire [3:0] cpu_jtag_debug_module_agent_m0_byteenable; // cpu_jtag_debug_module_agent:m0_byteenable -> cpu_jtag_debug_module_translator:uav_byteenable
wire cpu_jtag_debug_module_agent_rf_source_endofpacket; // cpu_jtag_debug_module_agent:rf_source_endofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_endofpacket
wire cpu_jtag_debug_module_agent_rf_source_valid; // cpu_jtag_debug_module_agent:rf_source_valid -> cpu_jtag_debug_module_agent_rsp_fifo:in_valid
wire cpu_jtag_debug_module_agent_rf_source_startofpacket; // cpu_jtag_debug_module_agent:rf_source_startofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_startofpacket
wire [105:0] cpu_jtag_debug_module_agent_rf_source_data; // cpu_jtag_debug_module_agent:rf_source_data -> cpu_jtag_debug_module_agent_rsp_fifo:in_data
wire cpu_jtag_debug_module_agent_rf_source_ready; // cpu_jtag_debug_module_agent_rsp_fifo:in_ready -> cpu_jtag_debug_module_agent:rf_source_ready
wire cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> cpu_jtag_debug_module_agent:rf_sink_endofpacket
wire cpu_jtag_debug_module_agent_rsp_fifo_out_valid; // cpu_jtag_debug_module_agent_rsp_fifo:out_valid -> cpu_jtag_debug_module_agent:rf_sink_valid
wire cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> cpu_jtag_debug_module_agent:rf_sink_startofpacket
wire [105:0] cpu_jtag_debug_module_agent_rsp_fifo_out_data; // cpu_jtag_debug_module_agent_rsp_fifo:out_data -> cpu_jtag_debug_module_agent:rf_sink_data
wire cpu_jtag_debug_module_agent_rsp_fifo_out_ready; // cpu_jtag_debug_module_agent:rf_sink_ready -> cpu_jtag_debug_module_agent_rsp_fifo:out_ready
wire cpu_jtag_debug_module_agent_rdata_fifo_src_valid; // cpu_jtag_debug_module_agent:rdata_fifo_src_valid -> cpu_jtag_debug_module_agent:rdata_fifo_sink_valid
wire [33:0] cpu_jtag_debug_module_agent_rdata_fifo_src_data; // cpu_jtag_debug_module_agent:rdata_fifo_src_data -> cpu_jtag_debug_module_agent:rdata_fifo_sink_data
wire cpu_jtag_debug_module_agent_rdata_fifo_src_ready; // cpu_jtag_debug_module_agent:rdata_fifo_sink_ready -> cpu_jtag_debug_module_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> cpu_jtag_debug_module_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> cpu_jtag_debug_module_agent:cp_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> cpu_jtag_debug_module_agent:cp_startofpacket
wire [104:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> cpu_jtag_debug_module_agent:cp_data
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> cpu_jtag_debug_module_agent:cp_channel
wire cmd_mux_001_src_ready; // cpu_jtag_debug_module_agent:cp_ready -> cmd_mux_001:src_ready
wire clocks_pll_slave_agent_m0_waitrequest; // clocks_pll_slave_translator:uav_waitrequest -> clocks_pll_slave_agent:m0_waitrequest
wire [2:0] clocks_pll_slave_agent_m0_burstcount; // clocks_pll_slave_agent:m0_burstcount -> clocks_pll_slave_translator:uav_burstcount
wire [31:0] clocks_pll_slave_agent_m0_writedata; // clocks_pll_slave_agent:m0_writedata -> clocks_pll_slave_translator:uav_writedata
wire [28:0] clocks_pll_slave_agent_m0_address; // clocks_pll_slave_agent:m0_address -> clocks_pll_slave_translator:uav_address
wire clocks_pll_slave_agent_m0_write; // clocks_pll_slave_agent:m0_write -> clocks_pll_slave_translator:uav_write
wire clocks_pll_slave_agent_m0_lock; // clocks_pll_slave_agent:m0_lock -> clocks_pll_slave_translator:uav_lock
wire clocks_pll_slave_agent_m0_read; // clocks_pll_slave_agent:m0_read -> clocks_pll_slave_translator:uav_read
wire [31:0] clocks_pll_slave_agent_m0_readdata; // clocks_pll_slave_translator:uav_readdata -> clocks_pll_slave_agent:m0_readdata
wire clocks_pll_slave_agent_m0_readdatavalid; // clocks_pll_slave_translator:uav_readdatavalid -> clocks_pll_slave_agent:m0_readdatavalid
wire clocks_pll_slave_agent_m0_debugaccess; // clocks_pll_slave_agent:m0_debugaccess -> clocks_pll_slave_translator:uav_debugaccess
wire [3:0] clocks_pll_slave_agent_m0_byteenable; // clocks_pll_slave_agent:m0_byteenable -> clocks_pll_slave_translator:uav_byteenable
wire clocks_pll_slave_agent_rf_source_endofpacket; // clocks_pll_slave_agent:rf_source_endofpacket -> clocks_pll_slave_agent_rsp_fifo:in_endofpacket
wire clocks_pll_slave_agent_rf_source_valid; // clocks_pll_slave_agent:rf_source_valid -> clocks_pll_slave_agent_rsp_fifo:in_valid
wire clocks_pll_slave_agent_rf_source_startofpacket; // clocks_pll_slave_agent:rf_source_startofpacket -> clocks_pll_slave_agent_rsp_fifo:in_startofpacket
wire [105:0] clocks_pll_slave_agent_rf_source_data; // clocks_pll_slave_agent:rf_source_data -> clocks_pll_slave_agent_rsp_fifo:in_data
wire clocks_pll_slave_agent_rf_source_ready; // clocks_pll_slave_agent_rsp_fifo:in_ready -> clocks_pll_slave_agent:rf_source_ready
wire clocks_pll_slave_agent_rsp_fifo_out_endofpacket; // clocks_pll_slave_agent_rsp_fifo:out_endofpacket -> clocks_pll_slave_agent:rf_sink_endofpacket
wire clocks_pll_slave_agent_rsp_fifo_out_valid; // clocks_pll_slave_agent_rsp_fifo:out_valid -> clocks_pll_slave_agent:rf_sink_valid
wire clocks_pll_slave_agent_rsp_fifo_out_startofpacket; // clocks_pll_slave_agent_rsp_fifo:out_startofpacket -> clocks_pll_slave_agent:rf_sink_startofpacket
wire [105:0] clocks_pll_slave_agent_rsp_fifo_out_data; // clocks_pll_slave_agent_rsp_fifo:out_data -> clocks_pll_slave_agent:rf_sink_data
wire clocks_pll_slave_agent_rsp_fifo_out_ready; // clocks_pll_slave_agent:rf_sink_ready -> clocks_pll_slave_agent_rsp_fifo:out_ready
wire clocks_pll_slave_agent_rdata_fifo_src_valid; // clocks_pll_slave_agent:rdata_fifo_src_valid -> clocks_pll_slave_agent:rdata_fifo_sink_valid
wire [33:0] clocks_pll_slave_agent_rdata_fifo_src_data; // clocks_pll_slave_agent:rdata_fifo_src_data -> clocks_pll_slave_agent:rdata_fifo_sink_data
wire clocks_pll_slave_agent_rdata_fifo_src_ready; // clocks_pll_slave_agent:rdata_fifo_sink_ready -> clocks_pll_slave_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> clocks_pll_slave_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> clocks_pll_slave_agent:cp_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> clocks_pll_slave_agent:cp_startofpacket
wire [104:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> clocks_pll_slave_agent:cp_data
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> clocks_pll_slave_agent:cp_channel
wire cmd_mux_002_src_ready; // clocks_pll_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire clock_crossing_io_s0_agent_m0_waitrequest; // clock_crossing_io_s0_translator:uav_waitrequest -> clock_crossing_io_s0_agent:m0_waitrequest
wire [2:0] clock_crossing_io_s0_agent_m0_burstcount; // clock_crossing_io_s0_agent:m0_burstcount -> clock_crossing_io_s0_translator:uav_burstcount
wire [31:0] clock_crossing_io_s0_agent_m0_writedata; // clock_crossing_io_s0_agent:m0_writedata -> clock_crossing_io_s0_translator:uav_writedata
wire [28:0] clock_crossing_io_s0_agent_m0_address; // clock_crossing_io_s0_agent:m0_address -> clock_crossing_io_s0_translator:uav_address
wire clock_crossing_io_s0_agent_m0_write; // clock_crossing_io_s0_agent:m0_write -> clock_crossing_io_s0_translator:uav_write
wire clock_crossing_io_s0_agent_m0_lock; // clock_crossing_io_s0_agent:m0_lock -> clock_crossing_io_s0_translator:uav_lock
wire clock_crossing_io_s0_agent_m0_read; // clock_crossing_io_s0_agent:m0_read -> clock_crossing_io_s0_translator:uav_read
wire [31:0] clock_crossing_io_s0_agent_m0_readdata; // clock_crossing_io_s0_translator:uav_readdata -> clock_crossing_io_s0_agent:m0_readdata
wire clock_crossing_io_s0_agent_m0_readdatavalid; // clock_crossing_io_s0_translator:uav_readdatavalid -> clock_crossing_io_s0_agent:m0_readdatavalid
wire clock_crossing_io_s0_agent_m0_debugaccess; // clock_crossing_io_s0_agent:m0_debugaccess -> clock_crossing_io_s0_translator:uav_debugaccess
wire [3:0] clock_crossing_io_s0_agent_m0_byteenable; // clock_crossing_io_s0_agent:m0_byteenable -> clock_crossing_io_s0_translator:uav_byteenable
wire clock_crossing_io_s0_agent_rf_source_endofpacket; // clock_crossing_io_s0_agent:rf_source_endofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_endofpacket
wire clock_crossing_io_s0_agent_rf_source_valid; // clock_crossing_io_s0_agent:rf_source_valid -> clock_crossing_io_s0_agent_rsp_fifo:in_valid
wire clock_crossing_io_s0_agent_rf_source_startofpacket; // clock_crossing_io_s0_agent:rf_source_startofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_startofpacket
wire [105:0] clock_crossing_io_s0_agent_rf_source_data; // clock_crossing_io_s0_agent:rf_source_data -> clock_crossing_io_s0_agent_rsp_fifo:in_data
wire clock_crossing_io_s0_agent_rf_source_ready; // clock_crossing_io_s0_agent_rsp_fifo:in_ready -> clock_crossing_io_s0_agent:rf_source_ready
wire clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket; // clock_crossing_io_s0_agent_rsp_fifo:out_endofpacket -> clock_crossing_io_s0_agent:rf_sink_endofpacket
wire clock_crossing_io_s0_agent_rsp_fifo_out_valid; // clock_crossing_io_s0_agent_rsp_fifo:out_valid -> clock_crossing_io_s0_agent:rf_sink_valid
wire clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket; // clock_crossing_io_s0_agent_rsp_fifo:out_startofpacket -> clock_crossing_io_s0_agent:rf_sink_startofpacket
wire [105:0] clock_crossing_io_s0_agent_rsp_fifo_out_data; // clock_crossing_io_s0_agent_rsp_fifo:out_data -> clock_crossing_io_s0_agent:rf_sink_data
wire clock_crossing_io_s0_agent_rsp_fifo_out_ready; // clock_crossing_io_s0_agent:rf_sink_ready -> clock_crossing_io_s0_agent_rsp_fifo:out_ready
wire clock_crossing_io_s0_agent_rdata_fifo_src_valid; // clock_crossing_io_s0_agent:rdata_fifo_src_valid -> clock_crossing_io_s0_agent:rdata_fifo_sink_valid
wire [33:0] clock_crossing_io_s0_agent_rdata_fifo_src_data; // clock_crossing_io_s0_agent:rdata_fifo_src_data -> clock_crossing_io_s0_agent:rdata_fifo_sink_data
wire clock_crossing_io_s0_agent_rdata_fifo_src_ready; // clock_crossing_io_s0_agent:rdata_fifo_sink_ready -> clock_crossing_io_s0_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> clock_crossing_io_s0_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> clock_crossing_io_s0_agent:cp_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> clock_crossing_io_s0_agent:cp_startofpacket
wire [104:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> clock_crossing_io_s0_agent:cp_data
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> clock_crossing_io_s0_agent:cp_channel
wire cmd_mux_003_src_ready; // clock_crossing_io_s0_agent:cp_ready -> cmd_mux_003:src_ready
wire keycode_s1_agent_m0_waitrequest; // keycode_s1_translator:uav_waitrequest -> keycode_s1_agent:m0_waitrequest
wire [2:0] keycode_s1_agent_m0_burstcount; // keycode_s1_agent:m0_burstcount -> keycode_s1_translator:uav_burstcount
wire [31:0] keycode_s1_agent_m0_writedata; // keycode_s1_agent:m0_writedata -> keycode_s1_translator:uav_writedata
wire [28:0] keycode_s1_agent_m0_address; // keycode_s1_agent:m0_address -> keycode_s1_translator:uav_address
wire keycode_s1_agent_m0_write; // keycode_s1_agent:m0_write -> keycode_s1_translator:uav_write
wire keycode_s1_agent_m0_lock; // keycode_s1_agent:m0_lock -> keycode_s1_translator:uav_lock
wire keycode_s1_agent_m0_read; // keycode_s1_agent:m0_read -> keycode_s1_translator:uav_read
wire [31:0] keycode_s1_agent_m0_readdata; // keycode_s1_translator:uav_readdata -> keycode_s1_agent:m0_readdata
wire keycode_s1_agent_m0_readdatavalid; // keycode_s1_translator:uav_readdatavalid -> keycode_s1_agent:m0_readdatavalid
wire keycode_s1_agent_m0_debugaccess; // keycode_s1_agent:m0_debugaccess -> keycode_s1_translator:uav_debugaccess
wire [3:0] keycode_s1_agent_m0_byteenable; // keycode_s1_agent:m0_byteenable -> keycode_s1_translator:uav_byteenable
wire keycode_s1_agent_rf_source_endofpacket; // keycode_s1_agent:rf_source_endofpacket -> keycode_s1_agent_rsp_fifo:in_endofpacket
wire keycode_s1_agent_rf_source_valid; // keycode_s1_agent:rf_source_valid -> keycode_s1_agent_rsp_fifo:in_valid
wire keycode_s1_agent_rf_source_startofpacket; // keycode_s1_agent:rf_source_startofpacket -> keycode_s1_agent_rsp_fifo:in_startofpacket
wire [105:0] keycode_s1_agent_rf_source_data; // keycode_s1_agent:rf_source_data -> keycode_s1_agent_rsp_fifo:in_data
wire keycode_s1_agent_rf_source_ready; // keycode_s1_agent_rsp_fifo:in_ready -> keycode_s1_agent:rf_source_ready
wire keycode_s1_agent_rsp_fifo_out_endofpacket; // keycode_s1_agent_rsp_fifo:out_endofpacket -> keycode_s1_agent:rf_sink_endofpacket
wire keycode_s1_agent_rsp_fifo_out_valid; // keycode_s1_agent_rsp_fifo:out_valid -> keycode_s1_agent:rf_sink_valid
wire keycode_s1_agent_rsp_fifo_out_startofpacket; // keycode_s1_agent_rsp_fifo:out_startofpacket -> keycode_s1_agent:rf_sink_startofpacket
wire [105:0] keycode_s1_agent_rsp_fifo_out_data; // keycode_s1_agent_rsp_fifo:out_data -> keycode_s1_agent:rf_sink_data
wire keycode_s1_agent_rsp_fifo_out_ready; // keycode_s1_agent:rf_sink_ready -> keycode_s1_agent_rsp_fifo:out_ready
wire keycode_s1_agent_rdata_fifo_src_valid; // keycode_s1_agent:rdata_fifo_src_valid -> keycode_s1_agent:rdata_fifo_sink_valid
wire [33:0] keycode_s1_agent_rdata_fifo_src_data; // keycode_s1_agent:rdata_fifo_src_data -> keycode_s1_agent:rdata_fifo_sink_data
wire keycode_s1_agent_rdata_fifo_src_ready; // keycode_s1_agent:rdata_fifo_sink_ready -> keycode_s1_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> keycode_s1_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> keycode_s1_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> keycode_s1_agent:cp_startofpacket
wire [104:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> keycode_s1_agent:cp_data
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> keycode_s1_agent:cp_channel
wire cmd_mux_004_src_ready; // keycode_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire sdram_s1_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_agent:m0_waitrequest
wire [2:0] sdram_s1_agent_m0_burstcount; // sdram_s1_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
wire [31:0] sdram_s1_agent_m0_writedata; // sdram_s1_agent:m0_writedata -> sdram_s1_translator:uav_writedata
wire [28:0] sdram_s1_agent_m0_address; // sdram_s1_agent:m0_address -> sdram_s1_translator:uav_address
wire sdram_s1_agent_m0_write; // sdram_s1_agent:m0_write -> sdram_s1_translator:uav_write
wire sdram_s1_agent_m0_lock; // sdram_s1_agent:m0_lock -> sdram_s1_translator:uav_lock
wire sdram_s1_agent_m0_read; // sdram_s1_agent:m0_read -> sdram_s1_translator:uav_read
wire [31:0] sdram_s1_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_agent:m0_readdata
wire sdram_s1_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_agent:m0_readdatavalid
wire sdram_s1_agent_m0_debugaccess; // sdram_s1_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
wire [3:0] sdram_s1_agent_m0_byteenable; // sdram_s1_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
wire sdram_s1_agent_rf_source_endofpacket; // sdram_s1_agent:rf_source_endofpacket -> sdram_s1_agent_rsp_fifo:in_endofpacket
wire sdram_s1_agent_rf_source_valid; // sdram_s1_agent:rf_source_valid -> sdram_s1_agent_rsp_fifo:in_valid
wire sdram_s1_agent_rf_source_startofpacket; // sdram_s1_agent:rf_source_startofpacket -> sdram_s1_agent_rsp_fifo:in_startofpacket
wire [105:0] sdram_s1_agent_rf_source_data; // sdram_s1_agent:rf_source_data -> sdram_s1_agent_rsp_fifo:in_data
wire sdram_s1_agent_rf_source_ready; // sdram_s1_agent_rsp_fifo:in_ready -> sdram_s1_agent:rf_source_ready
wire sdram_s1_agent_rsp_fifo_out_endofpacket; // sdram_s1_agent_rsp_fifo:out_endofpacket -> sdram_s1_agent:rf_sink_endofpacket
wire sdram_s1_agent_rsp_fifo_out_valid; // sdram_s1_agent_rsp_fifo:out_valid -> sdram_s1_agent:rf_sink_valid
wire sdram_s1_agent_rsp_fifo_out_startofpacket; // sdram_s1_agent_rsp_fifo:out_startofpacket -> sdram_s1_agent:rf_sink_startofpacket
wire [105:0] sdram_s1_agent_rsp_fifo_out_data; // sdram_s1_agent_rsp_fifo:out_data -> sdram_s1_agent:rf_sink_data
wire sdram_s1_agent_rsp_fifo_out_ready; // sdram_s1_agent:rf_sink_ready -> sdram_s1_agent_rsp_fifo:out_ready
wire sdram_s1_agent_rdata_fifo_src_valid; // sdram_s1_agent:rdata_fifo_src_valid -> sdram_s1_agent_rdata_fifo:in_valid
wire [33:0] sdram_s1_agent_rdata_fifo_src_data; // sdram_s1_agent:rdata_fifo_src_data -> sdram_s1_agent_rdata_fifo:in_data
wire sdram_s1_agent_rdata_fifo_src_ready; // sdram_s1_agent_rdata_fifo:in_ready -> sdram_s1_agent:rdata_fifo_src_ready
wire sdram_s1_agent_rdata_fifo_out_valid; // sdram_s1_agent_rdata_fifo:out_valid -> sdram_s1_agent:rdata_fifo_sink_valid
wire [33:0] sdram_s1_agent_rdata_fifo_out_data; // sdram_s1_agent_rdata_fifo:out_data -> sdram_s1_agent:rdata_fifo_sink_data
wire sdram_s1_agent_rdata_fifo_out_ready; // sdram_s1_agent:rdata_fifo_sink_ready -> sdram_s1_agent_rdata_fifo:out_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sdram_s1_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sdram_s1_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sdram_s1_agent:cp_startofpacket
wire [104:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sdram_s1_agent:cp_data
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sdram_s1_agent:cp_channel
wire cmd_mux_005_src_ready; // sdram_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire cpu_data_master_agent_cp_endofpacket; // cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire cpu_data_master_agent_cp_valid; // cpu_data_master_agent:cp_valid -> router:sink_valid
wire cpu_data_master_agent_cp_startofpacket; // cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [104:0] cpu_data_master_agent_cp_data; // cpu_data_master_agent:cp_data -> router:sink_data
wire cpu_data_master_agent_cp_ready; // router:sink_ready -> cpu_data_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [104:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [5:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire cpu_instruction_master_agent_cp_endofpacket; // cpu_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire cpu_instruction_master_agent_cp_valid; // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid
wire cpu_instruction_master_agent_cp_startofpacket; // cpu_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire [104:0] cpu_instruction_master_agent_cp_data; // cpu_instruction_master_agent:cp_data -> router_001:sink_data
wire cpu_instruction_master_agent_cp_ready; // router_001:sink_ready -> cpu_instruction_master_agent:cp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire [104:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire [5:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [104:0] jtag_uart_avalon_jtag_slave_agent_rp_data; // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire [104:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire [5:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire cpu_jtag_debug_module_agent_rp_endofpacket; // cpu_jtag_debug_module_agent:rp_endofpacket -> router_003:sink_endofpacket
wire cpu_jtag_debug_module_agent_rp_valid; // cpu_jtag_debug_module_agent:rp_valid -> router_003:sink_valid
wire cpu_jtag_debug_module_agent_rp_startofpacket; // cpu_jtag_debug_module_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [104:0] cpu_jtag_debug_module_agent_rp_data; // cpu_jtag_debug_module_agent:rp_data -> router_003:sink_data
wire cpu_jtag_debug_module_agent_rp_ready; // router_003:sink_ready -> cpu_jtag_debug_module_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [104:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire [5:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire clocks_pll_slave_agent_rp_endofpacket; // clocks_pll_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire clocks_pll_slave_agent_rp_valid; // clocks_pll_slave_agent:rp_valid -> router_004:sink_valid
wire clocks_pll_slave_agent_rp_startofpacket; // clocks_pll_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [104:0] clocks_pll_slave_agent_rp_data; // clocks_pll_slave_agent:rp_data -> router_004:sink_data
wire clocks_pll_slave_agent_rp_ready; // router_004:sink_ready -> clocks_pll_slave_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [104:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire [5:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire clock_crossing_io_s0_agent_rp_endofpacket; // clock_crossing_io_s0_agent:rp_endofpacket -> router_005:sink_endofpacket
wire clock_crossing_io_s0_agent_rp_valid; // clock_crossing_io_s0_agent:rp_valid -> router_005:sink_valid
wire clock_crossing_io_s0_agent_rp_startofpacket; // clock_crossing_io_s0_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [104:0] clock_crossing_io_s0_agent_rp_data; // clock_crossing_io_s0_agent:rp_data -> router_005:sink_data
wire clock_crossing_io_s0_agent_rp_ready; // router_005:sink_ready -> clock_crossing_io_s0_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire [104:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire keycode_s1_agent_rp_endofpacket; // keycode_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire keycode_s1_agent_rp_valid; // keycode_s1_agent:rp_valid -> router_006:sink_valid
wire keycode_s1_agent_rp_startofpacket; // keycode_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [104:0] keycode_s1_agent_rp_data; // keycode_s1_agent:rp_data -> router_006:sink_data
wire keycode_s1_agent_rp_ready; // router_006:sink_ready -> keycode_s1_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [104:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire sdram_s1_agent_rp_endofpacket; // sdram_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire sdram_s1_agent_rp_valid; // sdram_s1_agent:rp_valid -> router_007:sink_valid
wire sdram_s1_agent_rp_startofpacket; // sdram_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [104:0] sdram_s1_agent_rp_data; // sdram_s1_agent:rp_data -> router_007:sink_data
wire sdram_s1_agent_rp_ready; // router_007:sink_ready -> sdram_s1_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [104:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire [5:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [104:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [104:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire [5:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [104:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [5:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [104:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [5:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [104:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [5:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire [104:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
wire [5:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
wire [104:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
wire [5:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src1_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [104:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire [104:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire [104:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
wire [5:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [104:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire [104:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
wire [5:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [104:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [104:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> crosser:in_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> crosser:in_startofpacket
wire [104:0] cmd_demux_src5_data; // cmd_demux:src5_data -> crosser:in_data
wire [5:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> crosser:in_channel
wire cmd_demux_src5_ready; // crosser:in_ready -> cmd_demux:src5_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_005:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_005:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [104:0] crosser_out_data; // crosser:out_data -> cmd_mux_005:sink0_data
wire [5:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_005:sink0_channel
wire crosser_out_ready; // cmd_mux_005:sink0_ready -> crosser:out_ready
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> crosser_001:in_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> crosser_001:in_valid
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> crosser_001:in_startofpacket
wire [104:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> crosser_001:in_data
wire [5:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> crosser_001:in_channel
wire cmd_demux_001_src2_ready; // crosser_001:in_ready -> cmd_demux_001:src2_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_005:sink1_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_005:sink1_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_005:sink1_startofpacket
wire [104:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_005:sink1_data
wire [5:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_005:sink1_channel
wire crosser_001_out_ready; // cmd_mux_005:sink1_ready -> crosser_001:out_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> crosser_002:in_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> crosser_002:in_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> crosser_002:in_startofpacket
wire [104:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> crosser_002:in_data
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> crosser_002:in_channel
wire rsp_demux_005_src0_ready; // crosser_002:in_ready -> rsp_demux_005:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink5_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink5_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink5_startofpacket
wire [104:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink5_data
wire [5:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink5_channel
wire crosser_002_out_ready; // rsp_mux:sink5_ready -> crosser_002:out_ready
wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> crosser_003:in_endofpacket
wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> crosser_003:in_valid
wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> crosser_003:in_startofpacket
wire [104:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> crosser_003:in_data
wire [5:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> crosser_003:in_channel
wire rsp_demux_005_src1_ready; // crosser_003:in_ready -> rsp_demux_005:src1_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux_001:sink2_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux_001:sink2_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux_001:sink2_startofpacket
wire [104:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux_001:sink2_data
wire [5:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux_001:sink2_channel
wire crosser_003_out_ready; // rsp_mux_001:sink2_ready -> crosser_003:out_ready
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_data_master_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_jtag_debug_module_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_jtag_debug_module_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.uav_read (cpu_jtag_debug_module_agent_m0_read), // .read
.uav_write (cpu_jtag_debug_module_agent_m0_write), // .write
.uav_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.uav_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.uav_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.uav_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_jtag_debug_module_address), // avalon_anti_slave_0.address
.av_write (cpu_jtag_debug_module_write), // .write
.av_read (cpu_jtag_debug_module_read), // .read
.av_readdata (cpu_jtag_debug_module_readdata), // .readdata
.av_writedata (cpu_jtag_debug_module_writedata), // .writedata
.av_byteenable (cpu_jtag_debug_module_byteenable), // .byteenable
.av_waitrequest (cpu_jtag_debug_module_waitrequest), // .waitrequest
.av_debugaccess (cpu_jtag_debug_module_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) clocks_pll_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clocks_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (clocks_pll_slave_agent_m0_burstcount), // .burstcount
.uav_read (clocks_pll_slave_agent_m0_read), // .read
.uav_write (clocks_pll_slave_agent_m0_write), // .write
.uav_waitrequest (clocks_pll_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (clocks_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (clocks_pll_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (clocks_pll_slave_agent_m0_readdata), // .readdata
.uav_writedata (clocks_pll_slave_agent_m0_writedata), // .writedata
.uav_lock (clocks_pll_slave_agent_m0_lock), // .lock
.uav_debugaccess (clocks_pll_slave_agent_m0_debugaccess), // .debugaccess
.av_address (clocks_pll_slave_address), // avalon_anti_slave_0.address
.av_write (clocks_pll_slave_write), // .write
.av_read (clocks_pll_slave_read), // .read
.av_readdata (clocks_pll_slave_readdata), // .readdata
.av_writedata (clocks_pll_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) clock_crossing_io_s0_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_crossing_io_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (clock_crossing_io_s0_agent_m0_burstcount), // .burstcount
.uav_read (clock_crossing_io_s0_agent_m0_read), // .read
.uav_write (clock_crossing_io_s0_agent_m0_write), // .write
.uav_waitrequest (clock_crossing_io_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_crossing_io_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_crossing_io_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (clock_crossing_io_s0_agent_m0_readdata), // .readdata
.uav_writedata (clock_crossing_io_s0_agent_m0_writedata), // .writedata
.uav_lock (clock_crossing_io_s0_agent_m0_lock), // .lock
.uav_debugaccess (clock_crossing_io_s0_agent_m0_debugaccess), // .debugaccess
.av_address (clock_crossing_io_s0_address), // avalon_anti_slave_0.address
.av_write (clock_crossing_io_s0_write), // .write
.av_read (clock_crossing_io_s0_read), // .read
.av_readdata (clock_crossing_io_s0_readdata), // .readdata
.av_writedata (clock_crossing_io_s0_writedata), // .writedata
.av_burstcount (clock_crossing_io_s0_burstcount), // .burstcount
.av_byteenable (clock_crossing_io_s0_byteenable), // .byteenable
.av_readdatavalid (clock_crossing_io_s0_readdatavalid), // .readdatavalid
.av_waitrequest (clock_crossing_io_s0_waitrequest), // .waitrequest
.av_debugaccess (clock_crossing_io_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) keycode_s1_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (keycode_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (keycode_s1_agent_m0_burstcount), // .burstcount
.uav_read (keycode_s1_agent_m0_read), // .read
.uav_write (keycode_s1_agent_m0_write), // .write
.uav_waitrequest (keycode_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (keycode_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (keycode_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (keycode_s1_agent_m0_readdata), // .readdata
.uav_writedata (keycode_s1_agent_m0_writedata), // .writedata
.uav_lock (keycode_s1_agent_m0_lock), // .lock
.uav_debugaccess (keycode_s1_agent_m0_debugaccess), // .debugaccess
.av_address (keycode_s1_address), // avalon_anti_slave_0.address
.av_write (keycode_s1_write), // .write
.av_readdata (keycode_s1_readdata), // .readdata
.av_writedata (keycode_s1_writedata), // .writedata
.av_chipselect (keycode_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_agent_m0_read), // .read
.uav_write (sdram_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_s1_write), // .write
.av_read (sdram_s1_read), // .read
.av_readdata (sdram_s1_readdata), // .readdata
.av_writedata (sdram_s1_writedata), // .writedata
.av_byteenable (sdram_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_s1_waitrequest), // .waitrequest
.av_chipselect (sdram_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_data_master_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_instruction_master_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_avalon_jtag_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_jtag_debug_module_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (cpu_jtag_debug_module_agent_m0_address), // m0.address
.m0_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.m0_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_jtag_debug_module_agent_m0_read), // .read
.m0_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.m0_write (cpu_jtag_debug_module_agent_m0_write), // .write
.rp_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_jtag_debug_module_agent_rp_ready), // .ready
.rp_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.rp_data (cpu_jtag_debug_module_agent_rp_data), // .data
.rp_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_jtag_debug_module_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_jtag_debug_module_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_jtag_debug_module_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (cpu_jtag_debug_module_agent_rf_source_data), // in.data
.in_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.in_ready (cpu_jtag_debug_module_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) clocks_pll_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (clocks_pll_slave_agent_m0_address), // m0.address
.m0_burstcount (clocks_pll_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (clocks_pll_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (clocks_pll_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (clocks_pll_slave_agent_m0_lock), // .lock
.m0_readdata (clocks_pll_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (clocks_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (clocks_pll_slave_agent_m0_read), // .read
.m0_waitrequest (clocks_pll_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (clocks_pll_slave_agent_m0_writedata), // .writedata
.m0_write (clocks_pll_slave_agent_m0_write), // .write
.rp_endofpacket (clocks_pll_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (clocks_pll_slave_agent_rp_ready), // .ready
.rp_valid (clocks_pll_slave_agent_rp_valid), // .valid
.rp_data (clocks_pll_slave_agent_rp_data), // .data
.rp_startofpacket (clocks_pll_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (clocks_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (clocks_pll_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (clocks_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (clocks_pll_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (clocks_pll_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (clocks_pll_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (clocks_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (clocks_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (clocks_pll_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (clocks_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (clocks_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (clocks_pll_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (clocks_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (clocks_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (clocks_pll_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) clocks_pll_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (clocks_pll_slave_agent_rf_source_data), // in.data
.in_valid (clocks_pll_slave_agent_rf_source_valid), // .valid
.in_ready (clocks_pll_slave_agent_rf_source_ready), // .ready
.in_startofpacket (clocks_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (clocks_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (clocks_pll_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (clocks_pll_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (clocks_pll_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (clocks_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) clock_crossing_io_s0_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (clock_crossing_io_s0_agent_m0_address), // m0.address
.m0_burstcount (clock_crossing_io_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (clock_crossing_io_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (clock_crossing_io_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (clock_crossing_io_s0_agent_m0_lock), // .lock
.m0_readdata (clock_crossing_io_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (clock_crossing_io_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (clock_crossing_io_s0_agent_m0_read), // .read
.m0_waitrequest (clock_crossing_io_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (clock_crossing_io_s0_agent_m0_writedata), // .writedata
.m0_write (clock_crossing_io_s0_agent_m0_write), // .write
.rp_endofpacket (clock_crossing_io_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (clock_crossing_io_s0_agent_rp_ready), // .ready
.rp_valid (clock_crossing_io_s0_agent_rp_valid), // .valid
.rp_data (clock_crossing_io_s0_agent_rp_data), // .data
.rp_startofpacket (clock_crossing_io_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (clock_crossing_io_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (clock_crossing_io_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (clock_crossing_io_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (clock_crossing_io_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (clock_crossing_io_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (clock_crossing_io_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (clock_crossing_io_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (clock_crossing_io_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (clock_crossing_io_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (clock_crossing_io_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (clock_crossing_io_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (clock_crossing_io_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (clock_crossing_io_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (clock_crossing_io_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (129),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) clock_crossing_io_s0_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (clock_crossing_io_s0_agent_rf_source_data), // in.data
.in_valid (clock_crossing_io_s0_agent_rf_source_valid), // .valid
.in_ready (clock_crossing_io_s0_agent_rf_source_ready), // .ready
.in_startofpacket (clock_crossing_io_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (clock_crossing_io_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (clock_crossing_io_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (clock_crossing_io_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (clock_crossing_io_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) keycode_s1_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (keycode_s1_agent_m0_address), // m0.address
.m0_burstcount (keycode_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (keycode_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (keycode_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (keycode_s1_agent_m0_lock), // .lock
.m0_readdata (keycode_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (keycode_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (keycode_s1_agent_m0_read), // .read
.m0_waitrequest (keycode_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (keycode_s1_agent_m0_writedata), // .writedata
.m0_write (keycode_s1_agent_m0_write), // .write
.rp_endofpacket (keycode_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (keycode_s1_agent_rp_ready), // .ready
.rp_valid (keycode_s1_agent_rp_valid), // .valid
.rp_data (keycode_s1_agent_rp_data), // .data
.rp_startofpacket (keycode_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (keycode_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (keycode_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (keycode_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (keycode_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (keycode_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (keycode_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (keycode_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (keycode_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (keycode_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (keycode_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (keycode_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (keycode_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (keycode_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (keycode_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (keycode_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (keycode_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) keycode_s1_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (keycode_s1_agent_rf_source_data), // in.data
.in_valid (keycode_s1_agent_rf_source_valid), // .valid
.in_ready (keycode_s1_agent_rf_source_ready), // .ready
.in_startofpacket (keycode_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (keycode_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (keycode_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (keycode_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (keycode_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (keycode_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (keycode_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sdram_s1_agent (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_agent_rp_ready), // .ready
.rp_valid (sdram_s1_agent_rp_valid), // .valid
.rp_data (sdram_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sdram_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rsp_fifo (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rf_source_data), // in.data
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rdata_fifo (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
usb_system_mm_interconnect_0_router router (
.sink_ready (cpu_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_agent_cp_valid), // .valid
.sink_data (cpu_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_001 router_001 (
.sink_ready (cpu_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_003 router_003 (
.sink_ready (cpu_jtag_debug_module_agent_rp_ready), // sink.ready
.sink_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.sink_data (cpu_jtag_debug_module_agent_rp_data), // .data
.sink_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_003 router_004 (
.sink_ready (clocks_pll_slave_agent_rp_ready), // sink.ready
.sink_valid (clocks_pll_slave_agent_rp_valid), // .valid
.sink_data (clocks_pll_slave_agent_rp_data), // .data
.sink_startofpacket (clocks_pll_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (clocks_pll_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_002 router_005 (
.sink_ready (clock_crossing_io_s0_agent_rp_ready), // sink.ready
.sink_valid (clock_crossing_io_s0_agent_rp_valid), // .valid
.sink_data (clock_crossing_io_s0_agent_rp_data), // .data
.sink_startofpacket (clock_crossing_io_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (clock_crossing_io_s0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_002 router_006 (
.sink_ready (keycode_s1_agent_rp_ready), // sink.ready
.sink_valid (keycode_s1_agent_rp_valid), // .valid
.sink_data (keycode_s1_agent_rp_data), // .data
.sink_startofpacket (keycode_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (keycode_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_003 router_007 (
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_agent_rp_valid), // .valid
.sink_data (sdram_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux_001 cmd_mux_005 (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket), // .endofpacket
.sink1_ready (crosser_001_out_ready), // sink1.ready
.sink1_valid (crosser_001_out_valid), // .valid
.sink1_channel (crosser_001_out_channel), // .channel
.sink1_data (crosser_001_out_data), // .data
.sink1_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux_001 rsp_demux_002 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux_001 rsp_demux_005 (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_demux_005_src1_valid), // .valid
.src1_data (rsp_demux_005_src1_data), // .data
.src1_channel (rsp_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_005_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (crosser_002_out_ready), // sink5.ready
.sink5_valid (crosser_002_out_valid), // .valid
.sink5_channel (crosser_002_out_channel), // .channel
.sink5_data (crosser_002_out_data), // .data
.sink5_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink5_endofpacket (crosser_002_out_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_002_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_002_src1_valid), // .valid
.sink1_channel (rsp_demux_002_src1_channel), // .channel
.sink1_data (rsp_demux_002_src1_data), // .data
.sink1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink2_ready (crosser_003_out_ready), // sink2.ready
.sink2_valid (crosser_003_out_valid), // .valid
.sink2_channel (crosser_003_out_channel), // .channel
.sink2_data (crosser_003_out_data), // .data
.sink2_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink2_endofpacket (crosser_003_out_endofpacket) // .endofpacket
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clocks_c0_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src5_ready), // in.ready
.in_valid (cmd_demux_src5_valid), // .valid
.in_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.in_channel (cmd_demux_src5_channel), // .channel
.in_data (cmd_demux_src5_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clocks_c0_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_001_src2_ready), // in.ready
.in_valid (cmd_demux_001_src2_valid), // .valid
.in_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.in_channel (cmd_demux_001_src2_channel), // .channel
.in_data (cmd_demux_001_src2_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (clocks_c0_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_005_src0_ready), // in.ready
.in_valid (rsp_demux_005_src0_valid), // .valid
.in_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_005_src0_channel), // .channel
.in_data (rsp_demux_005_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (clocks_c0_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_005_src1_ready), // in.ready
.in_valid (rsp_demux_005_src1_valid), // .valid
.in_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
.in_channel (rsp_demux_005_src1_channel), // .channel
.in_data (rsp_demux_005_src1_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
module sctag_tagdp_ctl( /*AUTOARG*/
// Outputs
triad0_muxsel_c3, triad1_muxsel_c3, triad2_muxsel_c3,
triad3_muxsel_c3, tag_quad_muxsel_c3, bist_vuad_wr_data,
bist_vuad_index, bist_vuad_vd, bist_vuad_write,
vuad_dp_diag_data_c7_buf, tagdp_mbctl_par_err_c3,
tagdp_tagctl_par_err_c3, tagdp_arbctl_par_err_c3, tag_error_c8,
so, lru_way_sel_c3, evict_c3, invalid_evict_c3,
// Inputs
vuad_dp_valid_c2, tag_parity_c2, tag_way_sel_c2,
vuad_tagdp_sel_c2_d1, bist_way_px, bist_enable_px,
arbdp_diag_wr_way_c2, arbctl_tecc_way_c2, arbctl_normal_tagacc_c2,
arbctl_tagdp_tecc_c2, arbctl_tagdp_perr_vld_c2, mbctl_hit_c3,
l2_dir_map_on, arbctl_l2tag_vld_c4, rst_tri_en, mbist_write_data,
mbist_l2v_index, mbist_l2v_vd, mbist_l2v_write,
vuad_dp_diag_data_c7, rclk, si, se, grst_l, arst_l, dbginit_l,
vuad_dp_used_c2, vuad_dp_alloc_c2, arbctl_evict_vld_c2
);
input [11:0] vuad_dp_valid_c2;
input [11:0] tag_parity_c2; // from tagdp.needs to be mapped
// @ the top level.
input [11:0] tag_way_sel_c2; // This can be a delayed version of the way selects.POST_3.0
input vuad_tagdp_sel_c2_d1; //POST_3.0
// Adding all the mux control logic for tagdp and tagl_dp into
// this block.
// All bist inputs come from a PX2 flop in the bist controller.
input [3:0] bist_way_px; // from tagbist
input bist_enable_px; // from tagbist
// calculations.
output [2:0] triad0_muxsel_c3;
output [2:0] triad1_muxsel_c3;
output [2:0] triad2_muxsel_c3;
output [2:0] triad3_muxsel_c3;
output [3:0] tag_quad_muxsel_c3 ; // to tagdp
input [3:0] arbdp_diag_wr_way_c2 ; // Wr or read way for tag Diagnostic Accesses.
input [3:0] arbctl_tecc_way_c2;
input arbctl_normal_tagacc_c2 ; // indicates that lru way from vuad is used for
// tag selection
input arbctl_tagdp_tecc_c2; // NEW_PIN . sel tecc way
input arbctl_tagdp_perr_vld_c2; // POST_2.0 PIN
input mbctl_hit_c3; // POST_2.0 PIN
input l2_dir_map_on; // NEW_PIN from csr
input arbctl_l2tag_vld_c4; // from tagctl
input rst_tri_en;
input [7:0] mbist_write_data; // POST_4.2 signals
output [7:0] bist_vuad_wr_data ; // POST_4.2 signals.
input [9:0] mbist_l2v_index; // POST_4.2 signals
input mbist_l2v_vd; // POST_4.2 signals
input mbist_l2v_write; // POST_4.2 signals
output [9:0] bist_vuad_index; // POST_4.2 signals
output bist_vuad_vd; // POST_4.2 signals
output bist_vuad_write; // POST_4.2 signals
input [25:0] vuad_dp_diag_data_c7 ; // POST_4.2 signals
output [25:0] vuad_dp_diag_data_c7_buf; // POST_4.2 signals
input rclk;
input si, se;
input grst_l;
input arst_l;
input dbginit_l;
output tagdp_mbctl_par_err_c3 ; // can be made a C3 signal.
output tagdp_tagctl_par_err_c3; // used to gate off eviction way
output tagdp_arbctl_par_err_c3; // used to gate off an eviction signal
output tag_error_c8; // to fbctl and csr.
output so;
input [11:0] vuad_dp_used_c2 ;
input [11:0] vuad_dp_alloc_c2 ;
output [11:0] lru_way_sel_c3;
// to tagdp
// All outputs are xmitted in C2 and used in C3.
// Buffer the following so that they can transmit to tagdp.
input arbctl_evict_vld_c2;
output evict_c3;
output invalid_evict_c3;
wire par_err_c2, par_err_c3;
wire tagdp_par_err_c4, tagdp_par_err_c5;
wire tag_error_c6, tag_error_c7 ;
wire [2:0] lru_triad0_muxsel_c2 ;
wire [2:0] lru_triad1_muxsel_c2 ;
wire [2:0] lru_triad2_muxsel_c2 ;
wire [2:0] lru_triad3_muxsel_c2 ;
wire [3:0] diag_wr_way_c3;
wire [3:0] diag_wr_way_c4;
wire [3:0] dec_lower_tag_way_c2;
wire [3:0] dec_high_tag_way_c2;
wire [3:0] bist_way_c1;
wire [3:0] bist_way_c2;
wire bist_enable_c1;
wire bist_enable_c2;
wire [3:0] lru_quad_muxsel_c2;
wire [3:0] lru_quad_muxsel_c3;
wire [2:0] tag_triad0_muxsel_c2 ;
wire [2:0] tag_triad1_muxsel_c2 ;
wire [2:0] tag_triad2_muxsel_c2 ;
wire [2:0] tag_triad3_muxsel_c2 ;
wire [2:0] dir_triad0_way_c2, dir_triad1_way_c2 ;
wire [2:0] dir_triad2_way_c2, dir_triad3_way_c2 ;
wire [2:0] tag_triad0_muxsel_c3;
wire [2:0] tag_triad1_muxsel_c3;
wire [2:0] tag_triad2_muxsel_c3;
wire [2:0] tag_triad3_muxsel_c3;
wire [3:0] dir_quad_way_c2;
wire [3:0] dir_quad_way_c3;
wire sel_bist_way_c2 ;
wire sel_diag_way_c4 ;
wire sel_tecc_way_c2 ;
wire [1:0] enc_high_tag_way_c2;
wire [1:0] enc_lower_tag_way_c2;
wire use_dec_sel_c2;
wire use_dec_sel_c3;
wire l2_dir_map_on_d1;
wire sel_dir_way_c2; // pick way indicated by addr<21:18>
wire [2:0] muxsel_triad0_way_c2 ;
wire [2:0] muxsel_triad1_way_c2 ;
wire [2:0] muxsel_triad2_way_c2 ;
wire [2:0] muxsel_triad3_way_c2 ;
wire nondep_tagdp_par_err_c3;
wire evict_vld_c3_1, evict_vld_c3_2;
wire evict_c3_1;
wire dbb_rst_l;
wire par_err_c3_2;
wire [11:0] lru_way_sel_c3_1;
wire [11:0] valid_c3;
// ----------------------\/ POST 4.2 repeater addition \/-------------------------
assign bist_vuad_wr_data = mbist_write_data ;
assign bist_vuad_write = mbist_l2v_write ;
assign bist_vuad_vd = mbist_l2v_vd ;
assign bist_vuad_index = mbist_l2v_index ;
assign vuad_dp_diag_data_c7_buf = vuad_dp_diag_data_c7 ;
// ----------------------\/ POST 4.2 repeater addition \/-------------------------
///////////////////////////////////////////////////////////////////
// Reset flop
///////////////////////////////////////////////////////////////////
dffrl_async #(1) reset_flop (.q(dbb_rst_l),
.clk(rclk),
.rst_l(arst_l),
.din(grst_l),
.se(se), .si(), .so());
dff_s #(1) ff_evict_c3_1
(.q (evict_vld_c3_1),
.din (arbctl_evict_vld_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_evict_c3_2
(.q (evict_vld_c3_2),
.din (arbctl_evict_vld_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign evict_c3 = evict_vld_c3_1 & ~par_err_c3 ;
assign evict_c3_1 = evict_vld_c3_2 & ~par_err_c3_2 ;
// evict qualification is performed in arbctl.
assign invalid_evict_c3 = |(lru_way_sel_c3_1 & ~valid_c3) ;
////////////////////////////////////////////
// The tag compare operation is a 27 bit
// compare. The overall Parity bit is
// not part of the compare.
//
// An error in any bit of the tag will cause
// the lkup operation to fail except for
// that in the overall parity bit.
// In case of an error in P, we need to
// turn off signalling a parity error.
//
// That is done using the not_hit_way_c2 signal
//assign tagdp_par_err_c2 = arbctl_tagdp_perr_vld_c2 & // inst vld from arbctl
// (|( tag_parity_c2 & not_hit_way_c2 )) ;
////////////////////////////////////////////
////////////////////////////////////////////
// An eviction is turned off if
// par_err_c3 is asserted. This is becuase
// the eviction could very well pick a way
// with a corrupted tag and this would end
// up in memory corruption.
////////////////////////////////////////////
// the following signal is used for reporting purposes only
assign par_err_c2 = arbctl_tagdp_perr_vld_c2 & |(tag_parity_c2 & vuad_dp_valid_c2);
// the following signals are used for control in the pipeline.
// In mbctl, tagctl, vuad, arbctl this par err signal is used
// for different purposes. In all cases it is used only for
// an EVICT instruction or for a miss.
// In mbctl, it is used in the insertion expression provided
// the instruction also misses the $ and FB.
dff_s #(1) ff_tagdp_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(par_err_c3), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_par_err_c3_2 (.din(par_err_c2), .clk(rclk),
.q(par_err_c3_2), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_mbctl_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(tagdp_mbctl_par_err_c3), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_tagctl_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(tagdp_tagctl_par_err_c3), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_arbctl_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(tagdp_arbctl_par_err_c3), .se(se), .si(), .so());
// In all the destination blocks, vuad, tagctl, mbctl and arbctl, this
// par_err signal is used only for a non-dep instruction.
// Dependents will not report a parity error at all.
// Hovewer, reporting is enabled for all hit cases that encounter a
// tag corruption.
assign nondep_tagdp_par_err_c3 = par_err_c3 & ~mbctl_hit_c3;
dff_s #(1) ff_tagdp_par_err_c4 (.din(nondep_tagdp_par_err_c3), .clk(rclk),
.q(tagdp_par_err_c4), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_par_err_c5 (.din(tagdp_par_err_c4), .clk(rclk),
.q(tagdp_par_err_c5), .se(se), .si(), .so());
dff_s #(1) ff_tag_error_c6 (.din(tagdp_par_err_c5), .clk(rclk),
.q(tag_error_c6), .se(se), .si(), .so());
dff_s #(1) ff_tag_error_c7 (.din(tag_error_c6), .clk(rclk),
.q(tag_error_c7), .se(se), .si(), .so());
dff_s #(1) ff_tag_error_c8 (.din(tag_error_c7), .clk(rclk),
.q(tag_error_c8), .se(se), .si(), .so());
/////////////////////////////////////////////
// Mux select generation to read
// out the evicted tag &
// 16:1 muxing of the tag read
//
// In C2 we generate the muxselects for all the
// 4 triads.
// These mux selects are generated for the following
// 2 categories of accesses.
// I)Normal accesses: sels generated by vuad_dp
// II) Direct Accesses: Diagnostic/direct mapped, BIST, tecc
//
// In C3 we generate the mux selects for the 4-1 mux in
// this block.
/////////////////////////////////////////////
dff_s #(1) ff_l2_dir_map_on_d1 (.din(l2_dir_map_on), .clk(rclk),
.q(l2_dir_map_on_d1), .se(se), .si(), .so());
dff_s #(4) ff_diag_way_c3 (.din(arbdp_diag_wr_way_c2[3:0]), .clk(rclk),
.q(diag_wr_way_c3[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_diag_way_c4 (.din(diag_wr_way_c3[3:0]), .clk(rclk),
.q(diag_wr_way_c4[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_lru_quad_muxsel_c2 (.din(lru_quad_muxsel_c2[3:0]), .clk(rclk),
.q(lru_quad_muxsel_c3[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_bist_way_c1 (.din(bist_way_px[3:0]), .clk(rclk),
.q(bist_way_c1[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_bist_way_c2 (.din(bist_way_c1[3:0]), .clk(rclk),
.q(bist_way_c2[3:0]), .se(se), .si(), .so());
dff_s #(1) ff_bist_enable_c1 (.din(bist_enable_px), .clk(rclk),
.q(bist_enable_c1), .se(se), .si(), .so());
dff_s #(1) ff_bist_enable_c2 (.din(bist_enable_c1), .clk(rclk),
.q(bist_enable_c2), .se(se), .si(), .so());
assign sel_bist_way_c2 = bist_enable_c2 ;
assign sel_diag_way_c4 = ~bist_enable_c2 & arbctl_l2tag_vld_c4;
assign sel_tecc_way_c2 = ~bist_enable_c2 & ~arbctl_l2tag_vld_c4 &
arbctl_tagdp_tecc_c2 ;
assign sel_dir_way_c2 = ~arbctl_tagdp_tecc_c2 & ~bist_enable_c2 &
~arbctl_l2tag_vld_c4 ;
mux4ds #(2) mux_way_low ( .dout (enc_lower_tag_way_c2[1:0]),
.in0(bist_way_c2[1:0]), // bist way c2
.in1(diag_wr_way_c4[1:0]), // diag way c4
.in2(arbctl_tecc_way_c2[1:0]),// tecc way c2( from a counter in arbdec)
.in3(arbdp_diag_wr_way_c2[1:0]),// addr_c2<19:18>
.sel0(sel_bist_way_c2), // bist way sel
.sel1(sel_diag_way_c4), // no bist way sel and diag sel.
.sel2(sel_tecc_way_c2), // tecc way
.sel3(sel_dir_way_c2)); // default is dir mapped way.
assign dec_lower_tag_way_c2[0] =(enc_lower_tag_way_c2 == 2'd0 ) ;
assign dec_lower_tag_way_c2[1] =(enc_lower_tag_way_c2 == 2'd1 ) ;
assign dec_lower_tag_way_c2[2] =(enc_lower_tag_way_c2 == 2'd2 ) ;
assign dec_lower_tag_way_c2[3] =(enc_lower_tag_way_c2 == 2'd3 ) ;
mux4ds #(2) mux_way_high (.dout (enc_high_tag_way_c2[1:0]),
.in0(bist_way_c2[3:2]), // bist way c2
.in1(diag_wr_way_c4[3:2]), // diag way c4
.in2(arbctl_tecc_way_c2[3:2]), // tecc way c2( from a counter in arbdec)
.in3(arbdp_diag_wr_way_c2[3:2]),// addr_c2<21:20>
.sel0(sel_bist_way_c2), // bist way sel
.sel1(sel_diag_way_c4), // no bist way sel and diag sel.
.sel2(sel_tecc_way_c2), // tecc
.sel3(sel_dir_way_c2)); // default is dir mapped way.
assign dec_high_tag_way_c2[0] = (enc_high_tag_way_c2 == 2'd0 ) ;
assign dec_high_tag_way_c2[1] = (enc_high_tag_way_c2 == 2'd1 ) ;
assign dec_high_tag_way_c2[2] = (enc_high_tag_way_c2 == 2'd2 ) ;
assign dec_high_tag_way_c2[3] = (enc_high_tag_way_c2 == 2'd3 ) ;
// Triad0 muxselects
// Tags in Triad0 correspond to way=0,1,2
assign dir_triad0_way_c2[0] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[0] ; // 0000
assign dir_triad0_way_c2[1] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[1] ; // 0001
assign dir_triad0_way_c2[2] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[2] ; // 0010
assign dir_quad_way_c2[0] = |( dir_triad0_way_c2 ) ;
assign muxsel_triad0_way_c2[1:0] = dir_triad0_way_c2[1:0];
assign muxsel_triad0_way_c2[2] = ~( dir_triad0_way_c2[1] |
dir_triad0_way_c2[0] ) ;
// Triad1 muxselects
// Tags in Triad1 correspond to way=3,4 or 12,5 or 13
assign dir_triad1_way_c2[0] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[3] ; // 0011
assign dir_triad1_way_c2[1] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[0] ; // 0100 or 1100
assign dir_triad1_way_c2[2] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[1] ; // 0101 or 1101
assign dir_quad_way_c2[1] = |( dir_triad1_way_c2 ) ;
assign muxsel_triad1_way_c2[1:0] = dir_triad1_way_c2[1:0];
assign muxsel_triad1_way_c2[2] = ~( dir_triad1_way_c2[1] |
dir_triad1_way_c2[0] ) ;
// Triad2 muxselects
// Tags in Triad2 correspond to way=6 or 14,7 or 15,8
assign dir_triad2_way_c2[0] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[2] ; // 0110 or 1110
assign dir_triad2_way_c2[1] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[3] ; // 0111 or 1111
assign dir_triad2_way_c2[2] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[0] ; // 1000
assign dir_quad_way_c2[2] = |( dir_triad2_way_c2 ) ;
assign muxsel_triad2_way_c2[1:0] = dir_triad2_way_c2[1:0];
assign muxsel_triad2_way_c2[2] = ~( dir_triad2_way_c2[1] |
dir_triad2_way_c2[0] ) ;
// Triad3 muxselects
// Tags in Triad3 correspond to way=9, 10, 11
assign dir_triad3_way_c2[0] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[1] ; // 1001
assign dir_triad3_way_c2[1] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[2] ; // 1010
assign dir_triad3_way_c2[2] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[3] ; // 1011
assign dir_quad_way_c2[3] = |( dir_triad3_way_c2 ) ;
assign use_dec_sel_c2 = ( ~arbctl_normal_tagacc_c2 |
bist_enable_c2 |
l2_dir_map_on_d1 ) ;
dff_s #(1) ff_use_dec_sel_c3 (.din(use_dec_sel_c2), .clk(rclk),
.q(use_dec_sel_c3), .se(se), .si(), .so());
assign muxsel_triad3_way_c2[1:0] = dir_triad3_way_c2[1:0];
assign muxsel_triad3_way_c2[2] = ~( dir_triad3_way_c2[1] |
dir_triad3_way_c2[0] ) ;
/////////
// TRIAD0
/////////
// Use a mux flop for the following to reduce the setup on lru_triad0_muxsel_c2
mux2ds #(3) mux_tag_triad0_muxsel_c2 ( .dout (tag_triad0_muxsel_c2[2:0]),
.in0(muxsel_triad0_way_c2[2:0]),
.in1(lru_triad0_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad0_muxsel_c2 (.din(tag_triad0_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad0_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad0_muxsel_c3[2:1] = tag_triad0_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad0_muxsel_c3[0] = tag_triad0_muxsel_c3[0] | rst_tri_en ;
/////////
// TRIAD1
/////////
// Use a mux flop for the following to reduce the setup on lru_triad1_muxsel_c2
mux2ds #(3) mux_tag_triad1_muxsel_c2 ( .dout (tag_triad1_muxsel_c2[2:0]),
.in0(muxsel_triad1_way_c2[2:0]),
.in1(lru_triad1_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad1_muxsel_c2 (.din(tag_triad1_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad1_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad1_muxsel_c3[2:1] = tag_triad1_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad1_muxsel_c3[0] = tag_triad1_muxsel_c3[0] | rst_tri_en ;
/////////
// TRIAD2
/////////
// Use a mux flop for the following to reduce the setup on lru_triad2_muxsel_c2
mux2ds #(3) mux_tag_triad2_muxsel_c2 ( .dout (tag_triad2_muxsel_c2[2:0]),
.in0(muxsel_triad2_way_c2[2:0]),
.in1(lru_triad2_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad2_muxsel_c2 (.din(tag_triad2_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad2_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad2_muxsel_c3[2:1] = tag_triad2_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad2_muxsel_c3[0] = tag_triad2_muxsel_c3[0] | rst_tri_en ;
/////////
// TRIAD3
/////////
// Use a mux flop for the following to reduce the setup on lru_triad3_muxsel_c2
mux2ds #(3) mux_tag_triad3_muxsel_c2 ( .dout (tag_triad3_muxsel_c2[2:0]),
.in0(muxsel_triad3_way_c2[2:0]),
.in1(lru_triad3_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad3_muxsel_c2 (.din(tag_triad3_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad3_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad3_muxsel_c3[2:1] = tag_triad3_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad3_muxsel_c3[0] = tag_triad3_muxsel_c3[0] | rst_tri_en ;
dff_s #(4) ff_dir_quad_way_c3 (.din(dir_quad_way_c2[3:0]), .clk(rclk),
.q(dir_quad_way_c3[3:0]), .se(se), .si(), .so());
/////////
// QUAD
/////////
// Use the C5 select from the diagnostic read/BIST or the C3 select from Lru.
assign tag_quad_muxsel_c3[0] = (( dir_quad_way_c3[0] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[0] ))
& ~rst_tri_en ;
assign tag_quad_muxsel_c3[1] = (( dir_quad_way_c3[1] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[1] ))
& ~rst_tri_en ;
assign tag_quad_muxsel_c3[2] = (( dir_quad_way_c3[2] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[2] ))
& ~rst_tri_en ;
assign tag_quad_muxsel_c3[3] = (( dir_quad_way_c3[3] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[3] ))
| rst_tri_en ;
//*****************************************************************************
// LRU state flop.
// * initialized to 1 on reset.
// * left shifted ( rotate) on every eviction.
// * else maintains its state.
//*****************************************************************************
wire lshift_lru_triad0;
wire no_lshift_lru_triad0;
wire [2:0] lru_state_lshift_triad0;
wire [2:0] lru_state_triad0 ;
wire [2:0] lru_state_triad0_p ;
wire lshift_lru_triad1;
wire no_lshift_lru_triad1;
wire [2:0] lru_state_lshift_triad1;
wire [2:0] lru_state_triad1 ;
wire [2:0] lru_state_triad1_p ;
wire lshift_lru_triad2;
wire no_lshift_lru_triad2;
wire [2:0] lru_state_lshift_triad2;
wire [2:0] lru_state_triad2 ;
wire [2:0] lru_state_triad2_p ;
wire lshift_lru_triad3;
wire no_lshift_lru_triad3;
wire [2:0] lru_state_lshift_triad3;
wire [2:0] lru_state_triad3 ;
wire [2:0] lru_state_triad3_p ;
wire pick_triad0;
wire pick_triad1;
wire pick_triad2;
wire pick_triad3;
wire [11:0] vec_unvuad_dp_used_c2;
wire [11:0] vec_unvuad_dp_alloc_c2;
wire sel_unvuad_dp_used_c2;
//wire vuad_dp_way_avail_c2;
wire vec_unalloc0to2_c2;
wire vec_unalloc3to5_c2;
wire vec_unalloc6to8_c2;
wire vec_unalloc9to11_c2;
wire vec_unused0to2_c2;
wire vec_unused3to5_c2;
wire vec_unused6to8_c2;
wire vec_unused9to11_c2;
wire [3:0] used_lru_quad_c2;
wire [2:0] used_lru_triad0_c2;
wire [2:0] used_lru_triad1_c2;
wire [2:0] used_lru_triad2_c2;
wire [2:0] used_lru_triad3_c2;
wire [3:0] alloc_lru_quad_c2;
wire [2:0] alloc_lru_triad0_c2;
wire [2:0] alloc_lru_triad1_c2;
wire [2:0] alloc_lru_triad2_c2;
wire [2:0] alloc_lru_triad3_c2;
wire [2:0] used_triad0_tagsel_c2;
wire [2:0] alloc_triad0_tagsel_c2;
wire [2:0] lru_triad0_tagsel_c2;
wire [2:0] used_triad1_tagsel_c2;
wire [2:0] alloc_triad1_tagsel_c2;
wire [2:0] lru_triad1_tagsel_c2;
wire [2:0] used_triad2_tagsel_c2;
wire [2:0] alloc_triad2_tagsel_c2;
wire [2:0] lru_triad2_tagsel_c2;
wire [2:0] used_triad3_tagsel_c2;
wire [2:0] alloc_triad3_tagsel_c2;
wire [2:0] lru_triad3_tagsel_c2;
wire [3:0] used_quad_sel_c2;
wire [3:0] alloc_quad_sel_c2;
wire [3:0] lru_quad_sel_c2;
wire [11:0] lru_way_sel_c2;
wire lshift_lru;
wire no_lshift_lru;
wire [3:0] lru_state_lshift;
wire [3:0] lru_state_p;
wire [3:0] lru_state;
wire init_lru_state;
wire [3:0] dec_lo_dir_way_c2;
wire [3:0] dec_hi_dir_way_c2;
wire [11:0] dec_dir_way_c2;
wire [11:0] evict_way_sel_c2;
wire [11:0] spec_alloc_c2, spec_alloc_c3;
wire [11:0] mod_alloc_c2;
////////////////////////////////////////////////////////////////////////////////
// LRU algorithm is used to select a way, out of 16 ways, to be evicted out of
// the L2 Cache. The algorithm used for the way select is not a tru LRU (Least
// Recently Used) algorithm but Round Robin arbitration. Round Robin arbitration
// is done in two stages by dividing 12 ways in 4 triads of 3 ways each
// Triad0[3:0] = Way[2:0],
// Triad1[3:0] = Way[5:3],
// Triad2[3:0] = Way[8:6],
// Triad3[3:0] = Way[11:9].
//
// First Round Robin is done within each quads to select one of the 3 ways
// and then Round Robin is done to select one of the four quads.
// A 4 bit one hot shift register maintains the state of the arbiter. An one
// at the bit location corresponding to a way represents highest priority for
// that way. Everytime an eviction takes place, state register is updated by
// shifting it left by one bit otherwise state of the register does not change.
// State register is used in C2 for the way selection and it is updated in the
// C3. On reset state rtegister is initialized to a state such that way0 has the
// highest priority.
//
// Way selection algorithm depends on the Used and Allocate bit of the VUAD
// array, read during C1, for the way selection. First priority is given to the
// ways that has not been Used and has not been Allocated for the eviction in
// the previous cycle. If there is no Unused and Unallocated way then a way that
// has not been previously Allocated is given preference.
// Note : Invalid bit is not used for the way selection as if a way is Invalid
// then its Used bit will not be set, so checking Invalid bit is
// redundant.
////////////////////////////////////////////////////////////////////////////////
// QUAD ANCHOR
assign init_lru_state = ~dbb_rst_l | ~dbginit_l ;
assign lshift_lru = evict_c3_1 & ~init_lru_state;
assign no_lshift_lru = ~evict_c3_1 & ~init_lru_state ;
assign lru_state_lshift = { lru_state[2:0], lru_state[3] } ;
mux3ds #(4) mux_lru_st (.dout (lru_state_p[3:0]),
.in0(4'b0001),
.in1(lru_state_lshift[3:0]),
.in2(lru_state[3:0]),
.sel0(init_lru_state),
.sel1(lshift_lru),
.sel2(no_lshift_lru));
dff_s #(4) ff_lru_state (.din(lru_state_p[3:0]),
.clk(rclk),
.q(lru_state[3:0]),
.se(se),
.si(),
.so());
// Triad0 ANCHOR
assign lshift_lru_triad0 = evict_c3_1 & pick_triad0 & ~init_lru_state;
assign no_lshift_lru_triad0 = ~( evict_c3_1 & pick_triad0 ) & ~init_lru_state ;
assign lru_state_lshift_triad0 = { lru_state_triad0[1:0], lru_state_triad0[2] } ;
mux3ds #(3) mux_lru_st_triad0 (.dout (lru_state_triad0_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad0[2:0]),
.in2(lru_state_triad0[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad0),
.sel2(no_lshift_lru_triad0));
dff_s #(3) ff_lru_state_triad0 (.din(lru_state_triad0_p[2:0]),
.clk(rclk),
.q(lru_state_triad0[2:0]),
.se(se),
.si(),
.so());
// Triad1 ANCHOR
assign lshift_lru_triad1 = evict_c3_1 & pick_triad1 & ~init_lru_state;
assign no_lshift_lru_triad1 = ~( evict_c3_1 & pick_triad1 ) & ~init_lru_state ;
assign lru_state_lshift_triad1 = { lru_state_triad1[1:0], lru_state_triad1[2] } ;
mux3ds #(3) mux_lru_st_triad1 (.dout (lru_state_triad1_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad1[2:0]),
.in2(lru_state_triad1[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad1),
.sel2(no_lshift_lru_triad1));
dff_s #(3) ff_lru_state_triad1 (.din(lru_state_triad1_p[2:0]),
.clk(rclk),
.q(lru_state_triad1[2:0]),
.se(se),
.si(),
.so());
// Triad2 ANCHOR
assign lshift_lru_triad2 = evict_c3_1 & pick_triad2 & ~init_lru_state;
assign no_lshift_lru_triad2 = ~( evict_c3_1 & pick_triad2 ) & ~init_lru_state ;
assign lru_state_lshift_triad2 = { lru_state_triad2[1:0], lru_state_triad2[2] } ;
mux3ds #(3) mux_lru_st_triad2 (.dout (lru_state_triad2_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad2[2:0]),
.in2(lru_state_triad2[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad2),
.sel2(no_lshift_lru_triad2));
dff_s #(3) ff_lru_state_triad2 (.din(lru_state_triad2_p[2:0]),
.clk(rclk),
.q(lru_state_triad2[2:0]),
.se(se),
.si(),
.so());
// Triad2 ANCHOR
assign lshift_lru_triad3 = evict_c3_1 & pick_triad3 & ~init_lru_state;
assign no_lshift_lru_triad3 = ~( evict_c3_1 & pick_triad3 ) & ~init_lru_state ;
assign lru_state_lshift_triad3 = { lru_state_triad3[1:0], lru_state_triad3[2] } ;
mux3ds #(3) mux_lru_st_triad3 (.dout (lru_state_triad3_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad3[2:0]),
.in2(lru_state_triad3[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad3),
.sel2(no_lshift_lru_triad3));
dff_s #(3) ff_lru_state_triad3 (.din(lru_state_triad3_p[2:0]),
.clk(rclk),
.q(lru_state_triad3[2:0]),
.se(se),
.si(),
.so());
//************************************************************************************
// LRU algorithm
// * 3 vectors are computed ( Invalid[15:0], Unused[15:0], Unallocated[15:0] )
// * On vector is selected based on the 3 select bits read out of the array in C1,
// invalid, unused, unallocated
// * A state register is used to decide which quadrant to pick.
// * The same state register picks a way in each of the 4 quadrants.
//************************************************************************************
//
// If an instruction in C2 sets the alloc bit, it needs to be bypassed
// to the instruction that immediately follows it. This is done speculatively
// using the spec_alloc_c3 signal if the instruction in C2 is to the same index
// as an instruction in C3.
assign spec_alloc_c2 = ( tag_way_sel_c2 & vuad_dp_valid_c2 ) ;
dff_s #(12) ff_spec_alloc_c3 (.din(spec_alloc_c2[11:0]),
.clk(rclk), .q(spec_alloc_c3[11:0]),
.se(se), .si(), .so());
assign mod_alloc_c2 = ( vuad_dp_alloc_c2 |
( spec_alloc_c3 & {12{vuad_tagdp_sel_c2_d1}} ) );
// 2-3 gates.
assign vec_unvuad_dp_used_c2 = ~vuad_dp_used_c2 & ~mod_alloc_c2 ;
assign vec_unvuad_dp_alloc_c2 = ~mod_alloc_c2 ;
assign sel_unvuad_dp_used_c2 = |( vec_unvuad_dp_used_c2) ; // WAY lock will be ORED to this
// 2-3 gates.
assign vec_unused0to2_c2 = |(vec_unvuad_dp_used_c2[2:0]);
assign vec_unused3to5_c2 = |(vec_unvuad_dp_used_c2[5:3]);
assign vec_unused6to8_c2 = |(vec_unvuad_dp_used_c2[8:6]);
assign vec_unused9to11_c2 = |(vec_unvuad_dp_used_c2[11:9]);
// vec_unallocxtoxc2 is used to select one of the four quads.
assign vec_unalloc0to2_c2 = |(vec_unvuad_dp_alloc_c2[2:0]);
assign vec_unalloc3to5_c2 = |(vec_unvuad_dp_alloc_c2[5:3]);
assign vec_unalloc6to8_c2 = |(vec_unvuad_dp_alloc_c2[8:6]);
assign vec_unalloc9to11_c2 = |(vec_unvuad_dp_alloc_c2[11:9]);
/////////////////////////////
//UNUSED ROUND ROBIN PICK
/////////////////////////////
assign used_lru_quad_c2 = { vec_unused9to11_c2,
vec_unused6to8_c2,
vec_unused3to5_c2,
vec_unused0to2_c2 } ;
assign used_lru_triad0_c2 = vec_unvuad_dp_used_c2[2:0] ;
assign used_lru_triad1_c2 = vec_unvuad_dp_used_c2[5:3] ;
assign used_lru_triad2_c2 = vec_unvuad_dp_used_c2[8:6] ;
assign used_lru_triad3_c2 = vec_unvuad_dp_used_c2[11:9] ;
/////////////////////////////
//UNALLOC ROUND ROBIN PICK
/////////////////////////////
assign alloc_lru_quad_c2 = { vec_unalloc9to11_c2,
vec_unalloc6to8_c2,
vec_unalloc3to5_c2,
vec_unalloc0to2_c2 } ;
assign alloc_lru_triad0_c2 = vec_unvuad_dp_alloc_c2[2:0] ;
assign alloc_lru_triad1_c2 = vec_unvuad_dp_alloc_c2[5:3] ;
assign alloc_lru_triad2_c2 = vec_unvuad_dp_alloc_c2[8:6] ;
assign alloc_lru_triad3_c2 = vec_unvuad_dp_alloc_c2[11:9] ;
/************ LRU way within triad0 ************************/
assign used_triad0_tagsel_c2[0] = used_lru_triad0_c2[0] &
( lru_state_triad0[0] |
( lru_state_triad0[1] & ~( used_lru_triad0_c2[1] |
used_lru_triad0_c2[2] ) ) |
( lru_state_triad0[2] & ~used_lru_triad0_c2[2] ) ) ;
assign used_triad0_tagsel_c2[1] = used_lru_triad0_c2[1] &
( lru_state_triad0[1] |
( lru_state_triad0[2] & ~( used_lru_triad0_c2[2] |
used_lru_triad0_c2[0] )) |
( lru_state_triad0[0] & ~used_lru_triad0_c2[0]) ) ;
assign used_triad0_tagsel_c2[2] = used_lru_triad0_c2[2] &
( lru_state_triad0[2] |
( lru_state_triad0[0] & ~(used_lru_triad0_c2[0] |
used_lru_triad0_c2[1])) |
( lru_state_triad0[1] & ~used_lru_triad0_c2[1] ) ) ;
assign alloc_triad0_tagsel_c2[0] = alloc_lru_triad0_c2[0] &
( lru_state_triad0[0] |
( lru_state_triad0[1] & ~( alloc_lru_triad0_c2[1] |
alloc_lru_triad0_c2[2] ) ) |
( lru_state_triad0[2] & ~alloc_lru_triad0_c2[2] ) ) ;
assign alloc_triad0_tagsel_c2[1] = alloc_lru_triad0_c2[1] &
( lru_state_triad0[1] |
( lru_state_triad0[2] & ~( alloc_lru_triad0_c2[2] |
alloc_lru_triad0_c2[0] )) |
( lru_state_triad0[0] & ~alloc_lru_triad0_c2[0]) ) ;
assign alloc_triad0_tagsel_c2[2] = alloc_lru_triad0_c2[2] &
( lru_state_triad0[2] |
( lru_state_triad0[0] & ~(alloc_lru_triad0_c2[0] |
alloc_lru_triad0_c2[1])) |
( lru_state_triad0[1] & ~alloc_lru_triad0_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad0 (.dout (lru_triad0_tagsel_c2[2:0]),
.in0(used_triad0_tagsel_c2[2:0]),
.in1(alloc_triad0_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad0_muxsel_c2[1:0] = lru_triad0_tagsel_c2[1:0] ;
assign lru_triad0_muxsel_c2[2] = ~( lru_triad0_tagsel_c2[1] | lru_triad0_tagsel_c2[0] ) ;
/************ LRU way within triad1 ************************/
assign used_triad1_tagsel_c2[0] = used_lru_triad1_c2[0] &
( lru_state_triad1[0] |
( lru_state_triad1[1] & ~( used_lru_triad1_c2[1] |
used_lru_triad1_c2[2] ) ) |
( lru_state_triad1[2] & ~used_lru_triad1_c2[2] ) ) ;
assign used_triad1_tagsel_c2[1] = used_lru_triad1_c2[1] &
( lru_state_triad1[1] |
( lru_state_triad1[2] & ~( used_lru_triad1_c2[2] |
used_lru_triad1_c2[0] )) |
( lru_state_triad1[0] & ~used_lru_triad1_c2[0]) ) ;
assign used_triad1_tagsel_c2[2] = used_lru_triad1_c2[2] &
( lru_state_triad1[2] |
( lru_state_triad1[0] & ~(used_lru_triad1_c2[0] |
used_lru_triad1_c2[1])) |
( lru_state_triad1[1] & ~used_lru_triad1_c2[1] ) ) ;
assign alloc_triad1_tagsel_c2[0] = alloc_lru_triad1_c2[0] &
( lru_state_triad1[0] |
( lru_state_triad1[1] & ~( alloc_lru_triad1_c2[1] |
alloc_lru_triad1_c2[2] ) ) |
( lru_state_triad1[2] & ~alloc_lru_triad1_c2[2] ) ) ;
assign alloc_triad1_tagsel_c2[1] = alloc_lru_triad1_c2[1] &
( lru_state_triad1[1] |
( lru_state_triad1[2] & ~( alloc_lru_triad1_c2[2] |
alloc_lru_triad1_c2[0] )) |
( lru_state_triad1[0] & ~alloc_lru_triad1_c2[0]) ) ;
assign alloc_triad1_tagsel_c2[2] = alloc_lru_triad1_c2[2] &
( lru_state_triad1[2] |
( lru_state_triad1[0] & ~(alloc_lru_triad1_c2[0] |
alloc_lru_triad1_c2[1])) |
( lru_state_triad1[1] & ~alloc_lru_triad1_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad1 (.dout (lru_triad1_tagsel_c2[2:0]),
.in0(used_triad1_tagsel_c2[2:0]),
.in1(alloc_triad1_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad1_muxsel_c2[1:0] = lru_triad1_tagsel_c2[1:0] ;
assign lru_triad1_muxsel_c2[2] = ~( lru_triad1_tagsel_c2[1] | lru_triad1_tagsel_c2[0] ) ;
/************ LRU way within triad2 ************************/
assign used_triad2_tagsel_c2[0] = used_lru_triad2_c2[0] &
( lru_state_triad2[0] |
( lru_state_triad2[1] & ~( used_lru_triad2_c2[1] |
used_lru_triad2_c2[2] ) ) |
( lru_state_triad2[2] & ~used_lru_triad2_c2[2] ) ) ;
assign used_triad2_tagsel_c2[1] = used_lru_triad2_c2[1] &
( lru_state_triad2[1] |
( lru_state_triad2[2] & ~( used_lru_triad2_c2[2] |
used_lru_triad2_c2[0] )) |
( lru_state_triad2[0] & ~used_lru_triad2_c2[0]) ) ;
assign used_triad2_tagsel_c2[2] = used_lru_triad2_c2[2] &
( lru_state_triad2[2] |
( lru_state_triad2[0] & ~(used_lru_triad2_c2[0] |
used_lru_triad2_c2[1])) |
( lru_state_triad2[1] & ~used_lru_triad2_c2[1] ) ) ;
assign alloc_triad2_tagsel_c2[0] = alloc_lru_triad2_c2[0] &
( lru_state_triad2[0] |
( lru_state_triad2[1] & ~( alloc_lru_triad2_c2[1] |
alloc_lru_triad2_c2[2] ) ) |
( lru_state_triad2[2] & ~alloc_lru_triad2_c2[2] ) ) ;
assign alloc_triad2_tagsel_c2[1] = alloc_lru_triad2_c2[1] &
( lru_state_triad2[1] |
( lru_state_triad2[2] & ~( alloc_lru_triad2_c2[2] |
alloc_lru_triad2_c2[0] )) |
( lru_state_triad2[0] & ~alloc_lru_triad2_c2[0]) ) ;
assign alloc_triad2_tagsel_c2[2] = alloc_lru_triad2_c2[2] &
( lru_state_triad2[2] |
( lru_state_triad2[0] & ~(alloc_lru_triad2_c2[0] |
alloc_lru_triad2_c2[1])) |
( lru_state_triad2[1] & ~alloc_lru_triad2_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad2 (.dout (lru_triad2_tagsel_c2[2:0]),
.in0(used_triad2_tagsel_c2[2:0]),
.in1(alloc_triad2_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad2_muxsel_c2[1:0] = lru_triad2_tagsel_c2[1:0] ;
assign lru_triad2_muxsel_c2[2] = ~( lru_triad2_tagsel_c2[1] | lru_triad2_tagsel_c2[0] ) ;
/************ LRU way within triad3 ************************/
assign used_triad3_tagsel_c2[0] = used_lru_triad3_c2[0] &
( lru_state_triad3[0] |
( lru_state_triad3[1] & ~( used_lru_triad3_c2[1] |
used_lru_triad3_c2[2] ) ) |
( lru_state_triad3[2] & ~used_lru_triad3_c2[2] ) ) ;
assign used_triad3_tagsel_c2[1] = used_lru_triad3_c2[1] &
( lru_state_triad3[1] |
( lru_state_triad3[2] & ~( used_lru_triad3_c2[2] |
used_lru_triad3_c2[0] )) |
( lru_state_triad3[0] & ~used_lru_triad3_c2[0]) ) ;
assign used_triad3_tagsel_c2[2] = used_lru_triad3_c2[2] &
( lru_state_triad3[2] |
( lru_state_triad3[0] & ~(used_lru_triad3_c2[0] |
used_lru_triad3_c2[1])) |
( lru_state_triad3[1] & ~used_lru_triad3_c2[1] ) ) ;
assign alloc_triad3_tagsel_c2[0] = alloc_lru_triad3_c2[0] &
( lru_state_triad3[0] |
( lru_state_triad3[1] & ~( alloc_lru_triad3_c2[1] |
alloc_lru_triad3_c2[2] ) ) |
( lru_state_triad3[2] & ~alloc_lru_triad3_c2[2] ) ) ;
assign alloc_triad3_tagsel_c2[1] = alloc_lru_triad3_c2[1] &
( lru_state_triad3[1] |
( lru_state_triad3[2] & ~( alloc_lru_triad3_c2[2] |
alloc_lru_triad3_c2[0] )) |
( lru_state_triad3[0] & ~alloc_lru_triad3_c2[0]) ) ;
assign alloc_triad3_tagsel_c2[2] = alloc_lru_triad3_c2[2] &
( lru_state_triad3[2] |
( lru_state_triad3[0] & ~(alloc_lru_triad3_c2[0] |
alloc_lru_triad3_c2[1])) |
( lru_state_triad3[1] & ~alloc_lru_triad3_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad3 (.dout (lru_triad3_tagsel_c2[2:0]),
.in0(used_triad3_tagsel_c2[2:0]),
.in1(alloc_triad3_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad3_muxsel_c2[1:0] = lru_triad3_tagsel_c2[1:0] ;
assign lru_triad3_muxsel_c2[2] = ~( lru_triad3_tagsel_c2[1] | lru_triad3_tagsel_c2[0] ) ;
/************ LRU quad ************************/
assign used_quad_sel_c2[0] = used_lru_quad_c2[0] &
( lru_state[0] |
( lru_state[1] & ~( used_lru_quad_c2[1] |
used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
( lru_state[2] & ~( used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
( lru_state[3] & ~(used_lru_quad_c2[3] )) ) ;
assign used_quad_sel_c2[1] = used_lru_quad_c2[1] &
( lru_state[1] |
( lru_state[2] & ~( used_lru_quad_c2[0] |
used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
( lru_state[3] & ~( used_lru_quad_c2[3] | used_lru_quad_c2[0] )) |
( lru_state[0] & ~(used_lru_quad_c2[0] )) ) ;
assign used_quad_sel_c2[2] = used_lru_quad_c2[2] &
( lru_state[2] |
( lru_state[3] & ~( used_lru_quad_c2[0] |
used_lru_quad_c2[1] | used_lru_quad_c2[3] )) |
( lru_state[0] & ~( used_lru_quad_c2[0] | used_lru_quad_c2[1] )) |
( lru_state[1] & ~(used_lru_quad_c2[1] )) ) ;
assign used_quad_sel_c2[3] = used_lru_quad_c2[3] &
( lru_state[3] |
( lru_state[0] & ~( used_lru_quad_c2[0] |
used_lru_quad_c2[1] | used_lru_quad_c2[2] )) |
( lru_state[1] & ~( used_lru_quad_c2[2] | used_lru_quad_c2[1] )) |
( lru_state[2] & ~(used_lru_quad_c2[2] )) ) ;
assign alloc_quad_sel_c2[0] = alloc_lru_quad_c2[0] &
( lru_state[0] |
( lru_state[1] & ~( alloc_lru_quad_c2[1] |
alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
( lru_state[2] & ~( alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
( lru_state[3] & ~(alloc_lru_quad_c2[3] )) ) ;
assign alloc_quad_sel_c2[1] = alloc_lru_quad_c2[1] &
( lru_state[1] |
( lru_state[2] & ~( alloc_lru_quad_c2[0] |
alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
( lru_state[3] & ~( alloc_lru_quad_c2[3] | alloc_lru_quad_c2[0] )) |
( lru_state[0] & ~(alloc_lru_quad_c2[0] )) ) ;
assign alloc_quad_sel_c2[2] = alloc_lru_quad_c2[2] &
( lru_state[2] |
( lru_state[3] & ~( alloc_lru_quad_c2[0] |
alloc_lru_quad_c2[1] | alloc_lru_quad_c2[3] )) |
( lru_state[0] & ~( alloc_lru_quad_c2[0] | alloc_lru_quad_c2[1] )) |
( lru_state[1] & ~(alloc_lru_quad_c2[1] )) ) ;
assign alloc_quad_sel_c2[3] = alloc_lru_quad_c2[3] &
( lru_state[3] |
( lru_state[0] & ~( alloc_lru_quad_c2[0] |
alloc_lru_quad_c2[1] | alloc_lru_quad_c2[2] )) |
( lru_state[1] & ~( alloc_lru_quad_c2[2] | alloc_lru_quad_c2[1] )) |
( lru_state[2] & ~(alloc_lru_quad_c2[2] )) ) ;
mux2ds #(4) mux_used_lru_quad (.dout (lru_quad_sel_c2[3:0]),
.in0(used_quad_sel_c2[3:0]),
.in1(alloc_quad_sel_c2[3:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_quad_muxsel_c2[2:0] = lru_quad_sel_c2[2:0] ;
assign lru_quad_muxsel_c2[3] = ~( lru_quad_sel_c2[2] | lru_quad_sel_c2[1] | lru_quad_sel_c2[0] ) ;
// lru_way_sel_c2 takes 14-15 gates to compute.
assign lru_way_sel_c2[2:0] = lru_triad0_tagsel_c2 & {3{lru_quad_sel_c2[0]}} ;
assign lru_way_sel_c2[5:3] = lru_triad1_tagsel_c2 & {3{lru_quad_sel_c2[1]}} ;
assign lru_way_sel_c2[8:6] = lru_triad2_tagsel_c2 & {3{lru_quad_sel_c2[2]}} ;
assign lru_way_sel_c2[11:9] = lru_triad3_tagsel_c2 & {3{lru_quad_sel_c2[3]}} ;
assign dec_lo_dir_way_c2[0] = ( arbdp_diag_wr_way_c2[1:0]==2'd0 ) ;
assign dec_lo_dir_way_c2[1] = ( arbdp_diag_wr_way_c2[1:0]==2'd1 ) ;
assign dec_lo_dir_way_c2[2] = ( arbdp_diag_wr_way_c2[1:0]==2'd2 ) ;
assign dec_lo_dir_way_c2[3] = ( arbdp_diag_wr_way_c2[1:0]==2'd3 ) ;
assign dec_hi_dir_way_c2[0] = ( arbdp_diag_wr_way_c2[3:2]==2'd0 ) ;
assign dec_hi_dir_way_c2[1] = ( arbdp_diag_wr_way_c2[3:2]==2'd1 ) ;
assign dec_hi_dir_way_c2[2] = ( arbdp_diag_wr_way_c2[3:2]==2'd2 ) ;
assign dec_hi_dir_way_c2[3] = ( arbdp_diag_wr_way_c2[3:2]==2'd3 ) ;
assign dec_dir_way_c2[0] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[0] ; // 0000
assign dec_dir_way_c2[1] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[1] ; // 0001
assign dec_dir_way_c2[2] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[2] ; // 0010
assign dec_dir_way_c2[3] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[3] ; // 0011
assign dec_dir_way_c2[4] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[0] ; // 0100 or 1100
assign dec_dir_way_c2[5] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[1] ; // 0101 or 1101
assign dec_dir_way_c2[6] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[2] ; // 0110 or 1110
assign dec_dir_way_c2[7] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[3] ; // 0111 or 1111
assign dec_dir_way_c2[8] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[0] ; // 1000
assign dec_dir_way_c2[9] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[1] ; // 1001
assign dec_dir_way_c2[10] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[2] ; // 1010
assign dec_dir_way_c2[11] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[3] ; // 1011
mux2ds #(12) mux_evict_way_sel_c2
(.dout (evict_way_sel_c2[11:0]),
.in0 (dec_dir_way_c2[11:0]), .sel0 (l2_dir_map_on_d1),
.in1 (lru_way_sel_c2[11:0]), .sel1 (~l2_dir_map_on_d1)
) ;
dff_s #(12) ff_lru_way_c3 (.din(evict_way_sel_c2[11:0]),
.clk(rclk),
.q(lru_way_sel_c3[11:0]),
.se(se),
.si(),
.so());
dff_s #(12) ff_lru_way_c3_1 (.din(evict_way_sel_c2[11:0]),
.clk(rclk),
.q(lru_way_sel_c3_1[11:0]),
.se(se),
.si(),
.so());
dff_s #(12) ff_valid_c3 (.din(vuad_dp_valid_c2[11:0]),
.clk(rclk),
.q(valid_c3[11:0]),
.se(se),
.si(),
.so());
assign pick_triad0 = |(lru_way_sel_c3_1[2:0] ) ;
assign pick_triad1 = |(lru_way_sel_c3_1[5:3] ) ;
assign pick_triad2 = |(lru_way_sel_c3_1[8:6] ) ;
assign pick_triad3 = |(lru_way_sel_c3_1[11:9]) ;
endmodule
|
module alu (
input [3:0] op,
input signed [31:0] a, b,
output signed [31:0] z,
output zero);
wire set;
wire [30:0] carry;
one_bit_alu alu0 (.op(op), .r(z[0 ]), .a(a[0 ]), .b(b[0 ]), .cin(1'b0 ), .cout(carry[0 ]), .less(set ));
one_bit_alu alu1 (.op(op), .r(z[1 ]), .a(a[1 ]), .b(b[1 ]), .cin(carry[0 ]), .cout(carry[1 ]), .less(1'b0));
one_bit_alu alu2 (.op(op), .r(z[2 ]), .a(a[2 ]), .b(b[2 ]), .cin(carry[1 ]), .cout(carry[2 ]), .less(1'b0));
one_bit_alu alu3 (.op(op), .r(z[3 ]), .a(a[3 ]), .b(b[3 ]), .cin(carry[2 ]), .cout(carry[3 ]), .less(1'b0));
one_bit_alu alu4 (.op(op), .r(z[4 ]), .a(a[4 ]), .b(b[4 ]), .cin(carry[3 ]), .cout(carry[4 ]), .less(1'b0));
one_bit_alu alu5 (.op(op), .r(z[5 ]), .a(a[5 ]), .b(b[5 ]), .cin(carry[4 ]), .cout(carry[5 ]), .less(1'b0));
one_bit_alu alu6 (.op(op), .r(z[6 ]), .a(a[6 ]), .b(b[6 ]), .cin(carry[5 ]), .cout(carry[6 ]), .less(1'b0));
one_bit_alu alu7 (.op(op), .r(z[7 ]), .a(a[7 ]), .b(b[7 ]), .cin(carry[6 ]), .cout(carry[7 ]), .less(1'b0));
one_bit_alu alu8 (.op(op), .r(z[8 ]), .a(a[8 ]), .b(b[8 ]), .cin(carry[7 ]), .cout(carry[8 ]), .less(1'b0));
one_bit_alu alu9 (.op(op), .r(z[9 ]), .a(a[9 ]), .b(b[9 ]), .cin(carry[8 ]), .cout(carry[9 ]), .less(1'b0));
one_bit_alu alu10 (.op(op), .r(z[10]), .a(a[10]), .b(b[10]), .cin(carry[9 ]), .cout(carry[10]), .less(1'b0));
one_bit_alu alu11 (.op(op), .r(z[11]), .a(a[11]), .b(b[11]), .cin(carry[10]), .cout(carry[11]), .less(1'b0));
one_bit_alu alu12 (.op(op), .r(z[12]), .a(a[12]), .b(b[12]), .cin(carry[11]), .cout(carry[12]), .less(1'b0));
one_bit_alu alu13 (.op(op), .r(z[13]), .a(a[13]), .b(b[13]), .cin(carry[12]), .cout(carry[13]), .less(1'b0));
one_bit_alu alu14 (.op(op), .r(z[14]), .a(a[14]), .b(b[14]), .cin(carry[13]), .cout(carry[14]), .less(1'b0));
one_bit_alu alu15 (.op(op), .r(z[15]), .a(a[15]), .b(b[15]), .cin(carry[14]), .cout(carry[15]), .less(1'b0));
one_bit_alu alu16 (.op(op), .r(z[16]), .a(a[16]), .b(b[16]), .cin(carry[15]), .cout(carry[16]), .less(1'b0));
one_bit_alu alu17 (.op(op), .r(z[17]), .a(a[17]), .b(b[17]), .cin(carry[16]), .cout(carry[17]), .less(1'b0));
one_bit_alu alu18 (.op(op), .r(z[18]), .a(a[18]), .b(b[18]), .cin(carry[17]), .cout(carry[18]), .less(1'b0));
one_bit_alu alu19 (.op(op), .r(z[19]), .a(a[19]), .b(b[19]), .cin(carry[18]), .cout(carry[19]), .less(1'b0));
one_bit_alu alu20 (.op(op), .r(z[20]), .a(a[20]), .b(b[20]), .cin(carry[19]), .cout(carry[20]), .less(1'b0));
one_bit_alu alu21 (.op(op), .r(z[21]), .a(a[21]), .b(b[21]), .cin(carry[20]), .cout(carry[21]), .less(1'b0));
one_bit_alu alu22 (.op(op), .r(z[22]), .a(a[22]), .b(b[22]), .cin(carry[21]), .cout(carry[22]), .less(1'b0));
one_bit_alu alu23 (.op(op), .r(z[23]), .a(a[23]), .b(b[23]), .cin(carry[22]), .cout(carry[23]), .less(1'b0));
one_bit_alu alu24 (.op(op), .r(z[24]), .a(a[24]), .b(b[24]), .cin(carry[23]), .cout(carry[24]), .less(1'b0));
one_bit_alu alu25 (.op(op), .r(z[25]), .a(a[25]), .b(b[25]), .cin(carry[24]), .cout(carry[25]), .less(1'b0));
one_bit_alu alu26 (.op(op), .r(z[26]), .a(a[26]), .b(b[26]), .cin(carry[25]), .cout(carry[26]), .less(1'b0));
one_bit_alu alu27 (.op(op), .r(z[27]), .a(a[27]), .b(b[27]), .cin(carry[26]), .cout(carry[27]), .less(1'b0));
one_bit_alu alu28 (.op(op), .r(z[28]), .a(a[28]), .b(b[28]), .cin(carry[27]), .cout(carry[28]), .less(1'b0));
one_bit_alu alu29 (.op(op), .r(z[29]), .a(a[29]), .b(b[29]), .cin(carry[28]), .cout(carry[29]), .less(1'b0));
one_bit_alu alu30 (.op(op), .r(z[30]), .a(a[30]), .b(b[30]), .cin(carry[29]), .cout(carry[30]), .less(1'b0));
one_bit_alu alu31 (.op(op), .r(z[31]), .a(a[31]), .b(b[31]), .cin(carry[30]), .set (set ), .less(1'b0));
nor (zero, z[0 ], z[1 ], z[2 ], z[3 ], z[4 ], z[5 ], z[6 ], z[7 ], z[8 ], z[9 ],
z[10], z[11], z[12], z[13], z[14], z[15], z[16], z[17], z[18], z[19],
z[20], z[21], z[22], z[23], z[24], z[25], z[26], z[27], z[28], z[29],
z[30], z[31]);
endmodule
|
module PIO_TO_CTRL (
clk,
rst_n,
req_compl_i,
compl_done_i,
cfg_to_turnoff,
cfg_turnoff_ok
);
input clk;
input rst_n;
input req_compl_i;
input compl_done_i;
input cfg_to_turnoff;
output cfg_turnoff_ok;
reg trn_pending;
reg cfg_turnoff_ok;
// * Check if completion is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
trn_pending <= 0;
end else begin
if (!trn_pending && req_compl_i)
trn_pending <= 1'b1;
else if (compl_done_i)
trn_pending <= 1'b0;
end
end
// * Turn-off OK if requested and no transaction is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
cfg_turnoff_ok <= 1'b0;
end else begin
if ( cfg_to_turnoff && !trn_pending)
cfg_turnoff_ok <= 1'b1;
else
cfg_turnoff_ok <= 1'b0;
end
end
endmodule
|
module arriagx_pmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Arria GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
|
module main;
reg p4VDC = 1;
wire p4VSW;
reg GND = 0;
reg SIM_RST = 1;
reg SIM_CLK = 1;
reg BLKUPL_n = 1; //input
reg BMGXM = 0; //input
reg BMGXP = 0; //input
reg BMGYM = 0; //input
reg BMGYP = 0; //input
reg BMGZM = 0; //input
reg BMGZP = 0; //input
reg CAURST = 0; //input
reg CDUFAL = 0; //input
reg CDUXM = 0; //input
reg CDUXP = 0; //input
reg CDUYM = 0; //input
reg CDUYP = 0; //input
reg CDUZM = 0; //input
reg CDUZP = 0; //input
reg CLOCK = 0;
reg CTLSAT = 0; //input
wire DBLTST; //monitor input
wire DKBSNC; //input
wire DKEND; //input
wire DKSTRT; //input
wire DOSCAL; //monitor input
reg FLTOUT = 0;
reg FREFUN = 0; //input
reg GATEX_n = 1; //input
reg GATEY_n = 1; //input
reg GATEZ_n = 1; //input
reg GCAPCL = 0; //input
reg GUIREL = 0; //input
reg HOLFUN = 0; //input
reg IMUCAG = 0; //input
reg IMUFAL = 0; //input
reg IMUOPR = 0; //input
reg IN3008 = 0; //input
reg IN3212 = 0; //input
reg IN3213 = 0; //input
reg IN3214 = 0; //input
reg IN3216 = 0; //input
reg IN3301 = 0; //input
reg ISSTOR = 0; //input
reg LEMATT = 0; //input
reg LFTOFF = 0; //input
reg LRIN0 = 0; //input
reg LRIN1 = 0; //input
reg LRRLSC = 0; //input
reg LVDAGD = 0; //input
reg MAINRS = 0; //input
wire MAMU; //monitor input
reg MANmP = 0; //input
reg MANmR = 0; //input
reg MANmY = 0; //input
reg MANpP = 0; //input
reg MANpR = 0; //input
reg MANpY = 0; //input
reg MARK = 0; //input
wire MDT01; //monitor input
wire MDT02; //monitor input
wire MDT03; //monitor input
wire MDT04; //monitor input
wire MDT05; //monitor input
wire MDT06; //monitor input
wire MDT07; //monitor input
wire MDT08; //monitor input
wire MDT09; //monitor input
wire MDT10; //monitor input
wire MDT11; //monitor input
wire MDT12; //monitor input
wire MDT13; //monitor input
wire MDT14; //monitor input
wire MDT15; //monitor input
wire MDT16; //monitor input
reg MKEY1 = 0; //input
reg MKEY2 = 0; //input
reg MKEY3 = 0; //input
reg MKEY4 = 0; //input
reg MKEY5 = 0; //input
wire MLDCH; //monitor input
wire MLOAD; //monitor input
wire MNHNC; //monitor input
wire MNHRPT; //monitor input
wire MNHSBF; //monitor input
reg MNIMmP = 0; //input
reg MNIMmR = 0; //input
reg MNIMmY = 0; //input
reg MNIMpP = 0; //input
reg MNIMpR = 0; //input
reg MNIMpY = 0; //input
wire MONPAR; //monitor input
wire MONWBK; //monitor input
wire MRDCH; //monitor input
wire MREAD; //monitor input
reg MRKREJ = 0; //input
reg MRKRST = 0; //input
wire MSTP; //monitor input
wire MSTRT; //monitor input
wire MTCSAI; //monitor input
reg MYCLMP = 0;
reg NAVRST = 0; //input
wire NHALGA; //monitor input
reg NHVFAL = 0; //input
reg NKEY1 = 0; //input
reg NKEY2 = 0; //input
reg NKEY3 = 0; //input
reg NKEY4 = 0; //input
reg NKEY5 = 0; //input
reg OPCDFL = 0; //input
reg OPMSW2 = 0; //input
reg OPMSW3 = 0; //input
reg PCHGOF = 0; //input
wire PIPAXm; //input
wire PIPAXp; //input
wire PIPAYm; //input
wire PIPAYp; //input
wire PIPAZm; //input
wire PIPAZp; //input
reg ROLGOF = 0; //input
reg RRIN0 = 0; //input
reg RRIN1 = 0; //input
reg RRPONA = 0; //input
reg RRRLSC = 0; //input
reg S4BSAB = 0; //input
reg SBYBUT = 0; //input
reg SCAFAL = 0;
reg SHAFTM = 0; //input
reg SHAFTP = 0; //input
reg SIGNX = 0; //input
reg SIGNY = 0; //input
reg SIGNZ = 0; //input
reg SMSEPR = 0; //input
reg SPSRDY = 0; //input
reg STRPRS = 0; //input
reg STRT2 = 0;
reg TEMPIN = 0; //input
reg TRANmX = 0; //input
reg TRANmY = 0; //input
reg TRANmZ = 0; //input
reg TRANpX = 0; //input
reg TRANpY = 0; //input
reg TRANpZ = 0; //input
reg TRNM = 0; //input
reg TRNP = 0; //input
reg TRST10 = 0; //input
reg TRST9 = 0; //input
reg ULLTHR = 0; //input
reg UPL0 = 0; //input
reg UPL1 = 0; //input
reg VFAIL = 0;
reg XLNK0 = 0; //input
reg XLNK1 = 0; //input
reg ZEROP = 0; //input
reg n2FSFAL = 0;
wire CDUXDP; //output
wire CDUXDM; //output
wire CDUYDP; //output
wire CDUYDM; //output
wire CDUZDP; //output
wire CDUZDM; //output
wire CLK; //output
wire COMACT; //output
wire DKDATA; // output
wire KYRLS; //output
wire MBR1; //monitor output
wire MBR2; //monitor output
wire MCTRAL_n; //monitor output
wire MGOJAM; //monitor output
wire MGP_n; //monitor output
wire MIIP; //monitor output
wire MINHL; //monitor output
wire MINKL; //monitor output
wire MNISQ; //monitor output
wire MON800; //monitor output
wire MONWT; //monitor output
wire MOSCAL_n; //monitor output
wire MPAL_n; //monitor output
wire MPIPAL_n; //monitor output
wire MRAG; //monitor output
wire MRCH; //monitor output
wire MREQIN; //monitor output
wire MRGG; //monitor output
wire MRLG; //monitor output
wire MRPTAL_n; //monitor output
wire MRSC; //monitor output
wire MRULOG; //monitor output
wire MSBSTP; //monitor input
wire MSCAFL_n; //monitor output
wire MSCDBL_n; //monitor output
wire MSP; //monitor output
wire MSQ10; //monitor output
wire MSQ11; //monitor output
wire MSQ12; //monitor output
wire MSQ13; //monitor output
wire MSQ14; //monitor output
wire MSQ16; //monitor output
wire MSQEXT; //monitor output
wire MST1; //monitor output
wire MST2; //monitor output
wire MST3; //monitor output
wire MSTPIT_n; //monitor output
wire MT01; //monitor output
wire MT02; //monitor output
wire MT03; //monitor output
wire MT04; //monitor output
wire MT05; //monitor output
wire MT06; //monitor output
wire MT07; //monitor output
wire MT08; //monitor output
wire MT09; //monitor output
wire MT10; //monitor output
wire MT11; //monitor output
wire MT12; //monitor output
wire MTCAL_n; //monitor output
wire MTCSA_n; //monitor output
wire MVFAIL_n; //monitor output
wire MWAG; //monitor output
wire MWARNF_n; //monitor output
wire MWATCH_n; //monitor output
wire MWBBEG; //monitor output
wire MWBG; //monitor output
wire MWCH; //monitor output
wire MWEBG; //monitor output
wire MWFBG; //monitor output
wire MWG; //monitor output
wire MWL01; //monitor output
wire MWL02; //monitor output
wire MWL03; //monitor output
wire MWL04; //monitor output
wire MWL05; //monitor output
wire MWL06; //monitor output
wire MWL07; //monitor output
wire MWL08; //monitor output
wire MWL09; //monitor output
wire MWL10; //monitor output
wire MWL11; //monitor output
wire MWL12; //monitor output
wire MWL13; //monitor output
wire MWL14; //monitor output
wire MWL15; //monitor output
wire MWL16; //monitor output
wire MWLG; //monitor output
wire MWQG; //monitor output
wire MWSG; //monitor output
wire MWYG; //monitor output
wire MWZG; //monitor output
wire OPEROR; //output
wire PIPASW; //output
wire PIPDAT; //output
wire RESTRT; //output
wire RLYB01; //output
wire RLYB02; //output
wire RLYB03; //output
wire RLYB04; //output
wire RLYB05; //output
wire RLYB06; //output
wire RLYB07; //output
wire RLYB08; //output
wire RLYB09; //output
wire RLYB10; //output
wire RLYB11; //output
wire RYWD12; //output
wire RYWD13; //output
wire RYWD14; //output
wire RYWD16; //output
wire SBYLIT; //output
wire SBYREL_n;
wire TMPCAU; //output
wire UPLACT; //output
wire VNFLSH; //output
assign p4VSW = p4VDC && SBYREL_n;
// PIPA spoofing -- simulate 3-3 moding on PIPA inputs, synced with PIPDAT
// and counting on PIPASW
reg [2:0] moding_counter = 3'b0;
always @(posedge PIPASW) begin
moding_counter = moding_counter + 3'b1;
if (moding_counter == 3'd6) begin
moding_counter = 3'b0;
end
end
assign PIPAXm = PIPDAT && (moding_counter >= 3'd3);
assign PIPAYm = PIPDAT && (moding_counter >= 3'd3);
assign PIPAZm = PIPDAT && (moding_counter >= 3'd3);
assign PIPAXp = PIPDAT && (moding_counter < 3'd3);
assign PIPAYp = PIPDAT && (moding_counter < 3'd3);
assign PIPAZp = PIPDAT && (moding_counter < 3'd3);
// PCM simulation
reg [4:0] pcm_counter = 5'd19;
reg dlk_clk = 1'b0;
reg [9:0] dlk_counter = 10'd1023;
always @(posedge CLK) begin
if (pcm_counter == 5'd20) begin
pcm_counter <= 5'b0;
end else begin
pcm_counter <= pcm_counter + 5'b1;
if (pcm_counter == 5'd0) begin
dlk_clk <= 1'b1;
dlk_counter <= dlk_counter + 10'b1;
end else if (pcm_counter == 5'd4) begin
dlk_clk <= 1'b0;
end
end
end
assign DKSTRT = dlk_clk && (dlk_counter == 10'd0);
assign DKBSNC = dlk_clk && (dlk_counter > 10'd0) && (dlk_counter < 10'd41);
assign DKEND = dlk_clk && (dlk_counter == 10'd41);
always #244.140625 CLOCK = !CLOCK;
`ifdef TARGET_FPGA
always #10 SIM_CLK = !SIM_CLK;
wire EPCS_CSN;
wire EPCS_ASDI;
wire EPCS_DCLK;
reg EPCS_DATA = 0;
fpga_agc AGC(VCC, GND, SIM_RST, SIM_CLK, ALGA, C24A, C25A, C26A, C27A, C30A, C37P, C40P, C41P, C42P, C43P, C44P, CA2_n, CA3_n, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CDUSTB_n, CH01, CH02, CH03, CH04, CH05, CH06, CH07, CH08, CH09, CH10, CH11, CH12, CH13, CH14, CH16, CHINC, CHINC_n, CLOCK, DINC, DINC_n, DLKPLS, E5, E6, E7_n, EPCS_DATA, FETCH0, FETCH0_n, FETCH1, HNDRPT, INCSET_n, INKL, INKL_n, INOTLD, KYRPT1, KYRPT2, MAMU, MCDU, MDT01, MDT02, MDT03, MDT04, MDT05, MDT06, MDT07, MDT08, MDT09, MDT10, MDT11, MDT12, MDT13, MDT14, MDT15, MDT16, MINC, MKRPT, MNHRPT, MNHSBF, MONPAR, MONPCH, MONWBK, MON_n, MSTP, MSTRTP, MTCSAI, OVNHRP, PCDU, PIPPLS_n, RADRPT, RCHAT_n, RCHBT_n, SBY, SHANC_n, SHIFT, SHIFT_n, STFET1_n, STORE1_n, STRT1, STRT2, UPRUPT, ZOUT_n, EPCS_ASDI, EPCS_DCLK, EPCS_CSN, MGOJAM, MT01, MT02, MT03, MT04, MT05, MT06, MT07, MT08, MT09, MT10, MT11, MT12);
`else
ch77_alarm_box RestartMonitor(SIM_RST, SIM_CLK, p4VSW, GND, MDT01, MT01, MDT02, MT05, MDT03, MT12, MDT04, MWL01, MDT05, MWL02, MDT06, MWL03, MDT07, MWL04, MDT08, MWL05, MDT09, MWL06, MDT10, MRCH, MDT11, MWCH, MDT12, MWSG, MDT13, MPAL_n, MDT14, MTCAL_n, MDT15, MRPTAL_n, MDT16, MWATCH_n, MNHSBF, MVFAIL_n, MNHNC, MCTRAL_n, MNHRPT, MSCAFL_n, MTCSAI, MSCDBL_n, MSTRT, MAMU, MSTP, MSBSTP, MRDCH, MLDCH, MONPAR, MONWBK, MLOAD, MREAD, NHALGA, DOSCAL, DBLTST);
agc AGC(p4VDC, p4VSW, GND, SIM_RST, SIM_CLK, BLKUPL_n, BMGXM, BMGXP, BMGYM, BMGYP, BMGZM, BMGZP, CAURST, CDUFAL, CDUXM, CDUXP, CDUYM, CDUYP, CDUZM, CDUZP, CLOCK, CTLSAT, DBLTST, DKBSNC, DKEND, DKSTRT, DOSCAL, FLTOUT, FREFUN, GATEX_n, GATEY_n, GATEZ_n, GCAPCL, GUIREL, HOLFUN, IMUCAG, IMUFAL, IMUOPR, IN3008, IN3212, IN3213, IN3214, IN3216, IN3301, ISSTOR, LEMATT, LFTOFF, LRIN0, LRIN1, LRRLSC, LVDAGD, MAINRS, MAMU, MANmP, MANmR, MANmY, MANpP, MANpR, MANpY, MARK, MDT01, MDT02, MDT03, MDT04, MDT05, MDT06, MDT07, MDT08, MDT09, MDT10, MDT11, MDT12, MDT13, MDT14, MDT15, MDT16, MKEY1, MKEY2, MKEY3, MKEY4, MKEY5, MLDCH, MLOAD, MNHNC, MNHRPT, MNHSBF, MNIMmP, MNIMmR, MNIMmY, MNIMpP, MNIMpR, MNIMpY, MONPAR, MONWBK, MRDCH, MREAD, MRKREJ, MRKRST, MSTP, MSTRT, MTCSAI, MYCLMP, NAVRST, NHALGA, NHVFAL, NKEY1, NKEY2, NKEY3, NKEY4, NKEY5, OPCDFL, OPMSW2, OPMSW3, PCHGOF, PIPAXm, PIPAXp, PIPAYm, PIPAYp, PIPAZm, PIPAZp, ROLGOF, RRIN0, RRIN1, RRPONA, RRRLSC, S4BSAB, SBYBUT, SCAFAL, SHAFTM, SHAFTP, SIGNX, SIGNY, SIGNZ, SMSEPR, SPSRDY, STRPRS, STRT2, TEMPIN, TRANmX, TRANmY, TRANmZ, TRANpX, TRANpY, TRANpZ, TRNM, TRNP, TRST10, TRST9, ULLTHR, UPL0, UPL1, VFAIL, XLNK0, XLNK1, ZEROP, n2FSFAL, CDUXDM, CDUXDP, CDUYDM, CDUYDP, CDUZDM, CDUZDP, CLK, COMACT, DKDATA, KYRLS, MBR1, MBR2, MCTRAL_n, MGOJAM, MGP_n, MIIP, MINHL, MINKL, MNISQ, MON800, MONWT, MOSCAL_n, MPAL_n, MPIPAL_n, MRAG, MRCH, MREQIN, MRGG, MRLG, MRPTAL_n, MRSC, MRULOG, MSCAFL_n, MSCDBL_n, MSP, MSQ10, MSQ11, MSQ12, MSQ13, MSQ14, MSQ16, MSQEXT, MST1, MST2, MST3, MSTPIT_n, MT01, MT02, MT03, MT04, MT05, MT06, MT07, MT08, MT09, MT10, MT11, MT12, MTCAL_n, MTCSA_n, MVFAIL_n, MWAG, MWARNF_n, MWATCH_n, MWBBEG, MWBG, MWCH, MWEBG, MWFBG, MWG, MWL01, MWL02, MWL03, MWL04, MWL05, MWL06, MWL07, MWL08, MWL09, MWL10, MWL11, MWL12, MWL13, MWL14, MWL15, MWL16, MWLG, MWQG, MWSG, MWYG, MWZG, OPEROR, PIPASW, PIPDAT, RESTRT, RLYB01, RLYB02, RLYB03, RLYB04, RLYB05, RLYB06, RLYB07, RLYB08, RLYB09, RLYB10, RLYB11, RYWD12, RYWD13, RYWD14, RYWD16, SBYLIT, SBYREL_n, TMPCAU, UPLACT, VNFLSH);
`endif
initial begin
$dumpfile("dump.lxt");
$dumpvars(0, main);
#5000 SIM_RST = 0;
#400000000 $finish;
end
endmodule
|
module sha256_axi4 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 8
)
(
// Users to add ports here
// User ports ends
output wire hash_complete,
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
sha256_axi4_slave # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) sha256_axi4_slave_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
//.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_MODE_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_BLOCK0 = 8'h10;
localparam ADDR_BLOCK15 = 8'h1f;
localparam ADDR_DIGEST0 = 8'h20;
localparam ADDR_DIGEST7 = 8'h27;
localparam CORE_NAME0 = 32'h73686132; // "sha2"
localparam CORE_NAME1 = 32'h2d323536; // "-256"
localparam CORE_VERSION = 32'h312e3830; // "1.80"
localparam MODE_SHA_224 = 1'h0;
localparam MODE_SHA_256 = 1'h1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg mode_reg;
reg mode_new;
reg mode_we;
reg ready_reg;
reg [31 : 0] block_reg [0 : 15];
reg block_we;
reg [255 : 0] digest_reg;
reg digest_valid_reg;
reg hash_complete_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire core_ready;
wire [511 : 0] core_block;
wire [255 : 0] core_digest;
wire core_digest_valid;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
block_reg[04], block_reg[05], block_reg[06], block_reg[07],
block_reg[08], block_reg[09], block_reg[10], block_reg[11],
block_reg[12], block_reg[13], block_reg[14], block_reg[15]};
assign s00_axi_rdata = tmp_read_data;
assign hash_complete = hash_complete_reg;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
sha256_core core(
.clk(s00_axi_aclk),
.reset_n(s00_axi_aresetn),
.init(init_reg),
.next(next_reg),
.mode(mode_reg),
.block(core_block),
.ready(core_ready),
.digest(core_digest),
.digest_valid(core_digest_valid)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge s00_axi_aclk or negedge s00_axi_aresetn)
begin : reg_update
integer i;
if (!s00_axi_aresetn)
begin
for (i = 0 ; i < 16 ; i = i + 1)
block_reg[i] <= 32'h0;
init_reg <= 1'h0;
next_reg <= 1'h0;
ready_reg <= 1'h0;
mode_reg <= MODE_SHA_256;
digest_reg <= 256'h0;
hash_complete_reg <= 1'h0;
digest_valid_reg <= 1'h0;
end
else
begin
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
init_reg <= init_new;
next_reg <= next_new;
if (mode_we)
mode_reg <= mode_new;
if (core_digest_valid)
begin
digest_reg <= core_digest;
hash_complete_reg <= 1'h1;
end
if (block_we)
begin
hash_complete_reg <= 1'h0;
block_reg[s00_axi_awaddr[3 : 0]] <= s00_axi_wdata;
end
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If s00_axi_awprot is enabled will either
// try to write to or read from the internal registers.
//----------------------------------------------------------------
always @*
begin : api_logic
init_new = 0;
next_new = 0;
mode_new = 0;
mode_we = 0;
block_we = 0;
tmp_read_data = 32'h0;
if (s00_axi_awprot)
begin
if (s00_axi_awvalid)
begin
if (s00_axi_awaddr == ADDR_CTRL)
begin
init_new = s00_axi_wdata[CTRL_INIT_BIT];
next_new = s00_axi_wdata[CTRL_NEXT_BIT];
mode_new = s00_axi_wdata[CTRL_MODE_BIT];
mode_we = 1;
end
if ((s00_axi_awaddr >= ADDR_BLOCK0) && (s00_axi_awaddr <= ADDR_BLOCK15))
begin
block_we = 1;
end
end // if (s00_axi_awvalid)
else
begin
if ((s00_axi_araddr >= ADDR_BLOCK0) && (s00_axi_araddr <= ADDR_BLOCK15))
tmp_read_data = block_reg[s00_axi_awaddr[3 : 0]];
if ((s00_axi_araddr >= ADDR_DIGEST0) && (s00_axi_araddr <= ADDR_DIGEST7))
begin
tmp_read_data = digest_reg[(7 - (s00_axi_araddr - ADDR_DIGEST0)) * 32 +: 32] ;
end
case (s00_axi_araddr)
// Read operations.
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {29'h0, mode_reg, next_reg, init_reg};
ADDR_STATUS:
tmp_read_data = {30'h0, digest_valid_reg, ready_reg};
default:
begin
end
endcase // case (s00_axi_awaddr)
end
end
end // addr_decoder
endmodule
|
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
module limbus_nios2_qsys_0_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
|
module limbus_nios2_qsys_0_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
break_on_reset <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
|
module limbus_nios2_qsys_0_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input reset_req;
input wren;
wire clocken;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.clocken0 (clocken),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
|
module limbus_nios2_qsys_0_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
reset_req,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input reset_req;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
//limbus_nios2_qsys_0_ociram_sp_ram, which is an nios_sp_ram
limbus_nios2_qsys_0_ociram_sp_ram_module limbus_nios2_qsys_0_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.reset_req (reset_req),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam limbus_nios2_qsys_0_ociram_sp_ram.lpm_file = "limbus_nios2_qsys_0_ociram_default_contents.dat";
`else
defparam limbus_nios2_qsys_0_ociram_sp_ram.lpm_file = "limbus_nios2_qsys_0_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam limbus_nios2_qsys_0_ociram_sp_ram.lpm_file = "limbus_nios2_qsys_0_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h10000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001d1d :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h10000000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
|
module limbus_nios2_qsys_0_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000000001;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
end
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 26: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 28: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 28: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 28: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 28: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
|
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