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module VGA_0 (
input wire iCLK, // clk.clk
output wire [9:0] VGA_R, // avalon_slave_0_export.export
output wire [9:0] VGA_G, // .export
output wire [9:0] VGA_B, // .export
output wire VGA_HS, // .export
output wire VGA_VS, // .export
output wire VGA_SYNC, // .export
output wire VGA_BLANK, // .export
output wire VGA_CLK, // .export
input wire iCLK_25, // .export
output wire [15:0] oDATA, // avalon_slave_0.readdata
input wire [15:0] iDATA, // .writedata
input wire [18:0] iADDR, // .address
input wire iWR, // .write
input wire iRD, // .read
input wire iCS, // .chipselect
input wire iRST_N // reset_n.reset_n
);
VGA_NIOS_CTRL #(
.RAM_SIZE (307200)
) vga_0 (
.iCLK (iCLK), // clk.clk
.VGA_R (VGA_R), // avalon_slave_0_export.export
.VGA_G (VGA_G), // .export
.VGA_B (VGA_B), // .export
.VGA_HS (VGA_HS), // .export
.VGA_VS (VGA_VS), // .export
.VGA_SYNC (VGA_SYNC), // .export
.VGA_BLANK (VGA_BLANK), // .export
.VGA_CLK (VGA_CLK), // .export
.iCLK_25 (iCLK_25), // .export
.oDATA (oDATA), // avalon_slave_0.readdata
.iDATA (iDATA), // .writedata
.iADDR (iADDR), // .address
.iWR (iWR), // .write
.iRD (iRD), // .read
.iCS (iCS), // .chipselect
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
module data_path(clk,
reset,
MIO_ready,
IorD,
IRWrite,
RegDst,
RegWrite,
MemtoReg,
ALUSrcA,
ALUSrcB,
PCSource,
PCWrite,
PCWriteCond,
Beq,
ALU_operation,
PC_Current,
data2CPU,
Inst_R,
data_out,
M_addr,
zero,
overflow,
CauseWrite,
IntCause,
EPCWrite,
Co0Write,
);
input clk,reset;
input MIO_ready,IorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Beq,CauseWrite,EPCWrite,Co0Write;
input [1:0] RegDst,ALUSrcB,IntCause;
input [2:0]ALU_operation,MemtoReg,PCSource;
input [31:0] data2CPU;
output [31:0] Inst_R,M_addr,data_out,PC_Current; //
output zero,overflow;
reg [31:0] Inst_R,ALU_Out,MDR,PC_Current,w_reg_data;
wire [1:0] RegDst,ALUSrcB,IntCause;
wire [31:0] reg_outA,reg_outB,r6out, epc_out; //regs
wire reset,rst,zero,overflow,IRWrite,MIO_ready,RegWrite,Beq,modificative,CauseWrite,EPCWrite,Co0Write;
//ALU
wire IorD,ALUSrcA,PCWrite,PCWriteCond;
wire [31:0] Alu_A,Alu_B,res;
wire [31:0] rdata_A, rdata_B, data_out, data2CPU,M_addr, rdata_co0;
wire [2:0] ALU_operation, MemtoReg, PCSource;
wire [15:0] imm;
wire [4:0] reg_Rs_addr_A,reg_Rt_addr_B,reg_rd_addr,reg_Wt_addr;
assign rst=reset;
// locked inst form memory
always @(posedge clk or posedge rst)begin
if(rst) begin
Inst_R<=0; end
else begin
if (IRWrite && MIO_ready) Inst_R<=data2CPU; else Inst_R<=Inst_R;
if (MIO_ready) MDR<=data2CPU;
ALU_Out<=res;
end
end
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
alu x_ALU(
.A(Alu_A),
.B(Alu_B),
.ALU_operation(ALU_operation),
.res(res),
.zero(zero),
.overflow(overflow) );
Regs reg_files( .clk(clk),
.rst(rst),
.reg_R_addr_A(reg_Rs_addr_A),
.reg_R_addr_B(reg_Rt_addr_B),
.reg_W_addr(reg_Wt_addr),
.wdata(w_reg_data),
.reg_we(RegWrite),
.rdata_A(rdata_A),
.rdata_B(rdata_B));
Coprocessor coprocessor0 (
.clk(clk),
.rst(rst),
.reg_R_addr(reg_Rt_addr_B),
.reg_W_addr(reg_W_addr),
.wdata(w_reg_data),
.pc_i(res),
.reg_we(Co0Write),
.EPCWrite(EPCWrite),
.CauseWrite(CauseWrite),
.IntCause(IntCause),
.rdata(rdata_co0),
.epc_o(epc_out)
);
//path with MUX++++++++++++++++++++++++++++++++++++++++++++++++++++++
// reg path
assign reg_Rs_addr_A=Inst_R[25:21]; //REG Source 1 rs
assign reg_Rt_addr_B=Inst_R[20:16]; //REG Source 2 or Destination rt
assign reg_rd_addr=Inst_R[15:11]; //REG Destination rd
assign imm=Inst_R[15:0]; //Immediate
// reg write data
always @(*)
case(MemtoReg)
3'b000: w_reg_data<=ALU_Out;
3'b001: w_reg_data<=MDR;
3'b010: w_reg_data<={imm,16'h0000};
3'b011: w_reg_data<=PC_Current;
3'b100: w_reg_data<=rdata_co0;
endcase
// reg write port addr
mux4to1_5 mux_w_reg_addr (
.a(reg_Rt_addr_B), //reg addr=IR[21:16]
.b(reg_rd_addr), //reg addr=IR[15:11], LW or lui
.c(5'b11111), //reg addr=$Ra(31) jr
.d(5'b00000), // not use
.sel(RegDst),
.o(reg_Wt_addr)
);
//---------------ALU path
mux2to1_32 mux_Alu_A (
.a(rdata_A), // reg out A
.b(PC_Current), // PC
.sel(ALUSrcA),
.o(Alu_A)
);
mux4to1_32 mux_Alu_B(
.a(rdata_B), //reg out B
.b(32'h00000004), //4 for PC+4
.c({{16{imm[15]}},imm}), //imm
.d({{14{imm[15]}},imm,2'b00}),// offset
.sel(ALUSrcB),
.o(Alu_B)
);
//pc Generator
//+++++++++++++++++++++++++++++++++++++++++++++++++
assign modificative=PCWrite||(PCWriteCond&&(~(zero||Beq)|(zero&&Beq)));
//(PCWriteCond&&zero)
always @(posedge clk or posedge reset)
begin
if (reset==1) // reset
PC_Current<=32'h30000000;
else if (modificative==1)begin
case(PCSource)
3'b000: if (MIO_ready) PC_Current <=res; // PC+4
3'b001: PC_Current <=ALU_Out; // branch
3'b010: PC_Current <={PC_Current[31:28],Inst_R[25:0],2'b00}; // jump
3'b011: PC_Current <=32'h30000180; // j$r
3'b100: PC_Current <=epc_out;
endcase
end
end
/* mux4to1_32 mux_pc_next(
.a(pc_4),
.b(branch_pc),
.c(jump_pc),
.d(jump_pc),
.sel({jump,zero&Beq}),
.o(pc_next)
);
*/
//---------------memory path
assign data_out=rdata_B; //data to store memory or IO
mux2to1_32 mux_M_addr (
.a(ALU_Out), //access memory
.b(PC_Current), //IF
.sel(IorD),
.o(M_addr)
);
endmodule
|
module sky130_fd_sc_ls__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
|
module roi(input clk, input [255:0] din, output [255:0] dout);
clb_FF clb_FF (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
clb_OUT clb_OUT (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
endmodule
|
module clb_FF (input clk, input [7:0] din, output [7:0] dout);
wire o6;
//assign dout[0] = o6;
(* LOC="SLICE_X67Y331", BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6));
(* LOC="SLICE_X67Y331", BEL="BFF" *)
FDPE ff (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(o6));
endmodule
|
module clb_OUT (input clk, input [7:0] din, output [7:0] dout);
wire o6;
assign dout[0] = o6;
(* LOC="SLICE_X67Y330", BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6));
(* LOC="SLICE_X67Y330", BEL="BFF" *)
FDPE ff (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(o6));
endmodule
|
module tse_mac_loopback (
ref_clk,
txp,
rxp
);
output ref_clk;
input txp;
output rxp;
reg clk_tmp;
initial
clk_tmp <= 1'b0;
always
#4 clk_tmp <= ~clk_tmp;
reg reconfig_clk_tmp;
initial
reconfig_clk_tmp <= 1'b0;
always
#20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
assign ref_clk = clk_tmp;
assign rxp=txp;
endmodule
|
module memory_system (
input clk,
input reset,
output stall,
input vm_enable,
input [31:0] ptbr,
input flush_tlb,
input [31:0] fetch_addr,
input fetch_request,
output fetch_data_valid,
input [31:0] dmem_addr,
input [31:0] dmem_write_data,
input [3:0] dmem_write_mask,
input dmem_request,
input dmem_request_type,
output dmem_data_valid,
output [31:0] request_data
);
localparam S_IDLE = 2'd0;
localparam S_TRANSLATE = 2'd1;
localparam S_MEM_ACCESS = 2'd2;
localparam MM_SELECT_TRANSLATER = 1'd1;
localparam MM_SELECT_ARBITER = 1'd0;
reg [1:0] state;
reg [1:0] next_state;
always @ (posedge clk) begin
if (reset)
state <= S_IDLE;
else
state <= next_state;
end
wire arbiter_stall;
wire arbiter_mem_enable;
wire arbiter_cmd;
wire [31:0] arbiter_addr;
wire [31:0] arbiter_write_data = dmem_write_data;
wire [3:0] arbiter_write_mask = dmem_write_mask;
wire [31:0] arbiter_read_data;
wire arbiter_data_valid;
arbiter arbit(.clk(clk), .reset(reset),
.request_data(request_data), .stall(arbiter_stall),
.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
.dmem_addr(dmem_addr), .dmem_write_data(dmem_write_data), .dmem_write_mask(dmem_write_mask),
.dmem_request(dmem_request), .dmem_request_type(dmem_request_type), .dmem_data_valid(dmem_data_valid),
.mem_addr(arbiter_addr), .mem_mask(arbiter_write_mask), .mem_enable(arbiter_mem_enable), .mem_cmd(arbiter_cmd),
.mem_data(arbiter_read_data), .mem_wdata(arbiter_write_data), .mem_valid(arbiter_data_valid));
wire translater_mem_enable;
wire translater_cmd = `MEM_CMD_READ;
wire [31:0] translater_addr;
wire [31:0] translater_write_data = dmem_write_data;
wire [3:0] translater_write_mask = dmem_write_mask;
wire [31:0] translater_read_data;
wire translater_data_valid;
wire [31:0] translated_addr;
wire translate_enable = vm_enable;
wire translation_complete;
wire launch_translation;
translater t(.clk(clk), .reset(reset),
.vm_enable(translate_enable), .launch_translation(launch_translation),
.physical_address(translated_addr), .virtual_address(arbiter_addr),
.translation_complete(translation_complete), .ptbr(ptbr), .flush_tlb(flush_tlb),
.translate_mem_enable(translater_mem_enable),
.translate_addr(translater_addr), .request_data(translater_read_data), .translate_data_valid(translater_data_valid));
wire mem_enable;
wire mem_cmd;
wire [31:0] mem_addr;
wire [31:0] mem_write_data;
wire [3:0] mem_write_mask;
wire [31:0] mem_data;
wire mem_valid;
wire mm_select;
memory_mux m(.select(mm_select),
.enable_0(arbiter_mem_enable), .command_0(arbiter_cmd), .address_0(arbiter_addr),
.write_data_0(arbiter_write_data), .write_mask_0(arbiter_write_mask),
.read_data_0(arbiter_read_data), /* .valid_0(), */
.enable_1(translater_mem_enable), .command_1(translater_cmd), .address_1(translater_addr),
.write_data_1(translater_write_data), .write_mask_1(translater_write_mask),
.read_data_1(translater_read_data), .valid_1(translater_data_valid),
.enable(mem_enable), .command(mem_cmd), .address(mem_addr),
.write_data(mem_write_data), .write_mask(mem_write_mask),
.read_data(mem_data), .valid(mem_valid));
assign request_data = mm_select ? translater_read_data : arbiter_read_data;
always @ (*) begin
case (state)
S_IDLE:
if (vm_enable && arbiter_mem_enable)
next_state = S_TRANSLATE;
else
next_state = S_IDLE;
S_TRANSLATE:
if (translation_complete)
next_state = S_MEM_ACCESS;
else
next_state = S_TRANSLATE;
S_MEM_ACCESS:
if (mem_valid)
next_state = S_IDLE;
else
next_state = S_MEM_ACCESS;
default:
next_state = S_IDLE;
endcase
end
wire translation_stall = (state != S_IDLE);
assign launch_translation = (next_state == S_TRANSLATE);
assign mm_select = state == S_TRANSLATE ? MM_SELECT_TRANSLATER : MM_SELECT_ARBITER;
assign arbiter_data_valid = vm_enable ? mem_valid : translation_complete && mem_valid;
wire [31:0] physical_address = (vm_enable && translation_complete) ? translated_addr : mem_addr;
assign stall = arbiter_stall || translation_stall;
/* actual memory device */
mem simmem(.clk(clk), .reset(reset),
.addr(physical_address), .mask(mem_write_mask), .enable(mem_enable),
.cmd(mem_cmd), .load_data(mem_data), .write_data(mem_write_data), .valid(mem_valid));
endmodule
|
module sky130_fd_sc_hdll__or4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module AddState(
input [1:0] idle_Allign2,
input [35:0] cout_Allign2,
input [35:0] zout_Allign2,
input [31:0] sout_Allign2,
input [1:0] modeout_Allign2,
input operationout_Allign2,
input NatLogFlagout_Allign2,
input [7:0] InsTag_Allign2,
input clock,
output reg [1:0] idle_AddState,
output reg [31:0] sout_AddState,
output reg [1:0] modeout_AddState,
output reg operationout_AddState,
output reg NatLogFlagout_AddState,
output reg [27:0] sum_AddState,
output reg [7:0] InsTag_AddState
);
parameter mode_circular =2'b01,
mode_linear =2'b00,
mode_hyperbolic=2'b11;
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Allign2[35];
assign z_exponent = zout_Allign2[34:27] - 127;
assign z_mantissa = {zout_Allign2[26:0]};
assign c_sign = cout_Allign2[35];
assign c_exponent = cout_Allign2[34:27] - 127;
assign c_mantissa = {cout_Allign2[26:0]};
always @ (posedge clock)
begin
InsTag_AddState <= InsTag_Allign2;
idle_AddState <= idle_Allign2;
modeout_AddState <= modeout_Allign2;
operationout_AddState <= operationout_Allign2;
NatLogFlagout_AddState <= NatLogFlagout_Allign2;
if (idle_Allign2 != put_idle) begin
sout_AddState[30:23] <= c_exponent;
sout_AddState[22:0] <= 0;
if (c_sign == z_sign) begin
sum_AddState <= c_mantissa + z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
if (c_mantissa >= z_mantissa) begin
sum_AddState <= c_mantissa - z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
sum_AddState <= z_mantissa - c_mantissa;
sout_AddState[31] <= z_sign;
end
end
end
else begin
sout_AddState <= sout_Allign2;
sum_AddState <= 0;
end
end
endmodule
|
module sky130_fd_sc_hdll__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
|
module genetico(conf_les, conf_outs, in, out);
input [10:0] conf_les[8:0];
input [3:0] conf_outs[1:0];
input [2:0] in;
output [1:0] out;
wire [8:0] le_out;
wire [11:0] all_inputs;
assign all_inputs = {le_out, in};
assign out = {all_inputs[conf_outs[1]], all_inputs[conf_outs[0]]};
logic_e le00(
.conf_func(conf_les[0][10:8]),
.conf_ins(conf_les[0][7:0]),
.all_inputs(all_inputs),
.out(le_out[0])
);
logic_e le10(
.conf_func(conf_les[1][10:8]),
.conf_ins(conf_les[1][7:0]),
.all_inputs(all_inputs),
.out(le_out[1])
);
logic_e le20(
.conf_func(conf_les[2][10:8]),
.conf_ins(conf_les[2][7:0]),
.all_inputs(all_inputs),
.out(le_out[2])
);
logic_e le01(
.conf_func(conf_les[3][10:8]),
.conf_ins(conf_les[3][7:0]),
.all_inputs(all_inputs),
.out(le_out[3])
);
logic_e le11(
.conf_func(conf_les[4][10:8]),
.conf_ins(conf_les[4][7:0]),
.all_inputs(all_inputs),
.out(le_out[4])
);
logic_e le21(
.conf_func(conf_les[5][10:8]),
.conf_ins(conf_les[5][7:0]),
.all_inputs(all_inputs),
.out(le_out[5])
);
logic_e le02(
.conf_func(conf_les[6][10:8]),
.conf_ins(conf_les[6][7:0]),
.all_inputs(all_inputs),
.out(le_out[6])
);
logic_e le12(
.conf_func(conf_les[7][10:8]),
.conf_ins(conf_les[7][7:0]),
.all_inputs(all_inputs),
.out(le_out[7])
);
logic_e le22(
.conf_func(conf_les[8][10:8]),
.conf_ins(conf_les[8][7:0]),
.all_inputs(all_inputs),
.out(le_out[8])
);
endmodule
|
module main(
`ifdef MK2
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
output [22:0] ROM_ADDR,
output ROM_CE,
input MCU_OVR,
/* debug */
output p113_out,
`endif
`ifdef MK3
input SNES_CIC_CLK,
/* Bus 1: 2x PSRAM, 64Mbit, 16bit, 70ns */
output [21:0] ROM_ADDR,
output ROM_1CE,
output ROM_2CE,
output ROM_ZZ,
/* debug */
output PM6_out,
output PN6_out,
input PT5_in,
`endif
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
inout [15:0] ROM_DATA,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
input SPI_SCK,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK
);
assign DAC_MCLK = 0;
assign DAC_LRCK = 0;
assign DAC_SDOUT = 0;
wire CLK2;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
reg [7:0] SNES_PARDr = 8'b11111111;
reg [7:0] SNES_READr = 8'b11111111;
reg [7:0] SNES_WRITEr = 8'b11111111;
reg [7:0] SNES_CPU_CLKr = 8'b00000000;
reg [7:0] SNES_ROMSELr = 8'b11111111;
reg [7:0] SNES_PULSEr = 8'b11111111;
reg [23:0] SNES_ADDRr [6:0];
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
wire SNES_PULSE_IN = SNES_READ_IN & SNES_WRITE_IN & ~SNES_CPU_CLK_IN;
wire SNES_PULSE_end = (SNES_PULSEr[6:1] == 6'b000011);
wire SNES_PARD_start = (SNES_PARDr[6:1] == 6'b111110);
wire SNES_PARD_end = (SNES_PARDr[6:1] == 6'b000001);
wire SNES_RD_start = (SNES_READr[6:1] == 6'b111110);
wire SNES_RD_end = (SNES_READr[6:1] == 6'b000001);
wire SNES_WR_end = (SNES_WRITEr[6:1] == 6'b000001);
wire SNES_cycle_start = (SNES_CPU_CLKr[6:1] == 6'b000001);
wire SNES_cycle_end = (SNES_CPU_CLKr[6:1] == 6'b111110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_READ_late = SNES_READr[5] & SNES_READr[4];
wire SNES_READ_narrow = SNES_READ | SNES_READ_late;
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
wire [23:0] SNES_ADDR = (SNES_ADDRr[6] & SNES_ADDRr[5]);
wire free_slot = SNES_PULSE_end | free_strobe;
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= ~ROM_HIT;
end
always @(posedge CLK2) begin
SNES_PULSEr <= {SNES_PULSEr[6:0], SNES_PULSE_IN};
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[6] <= SNES_ADDRr[5];
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
end
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY)
);
address snes_addr(
.CLK(CLK2),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.SNES_ROMSEL(SNES_ROMSEL),
.ROM_HIT(ROM_HIT),
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK)
);
parameter ST_IDLE = 5'b00001;
parameter ST_MCU_RD_ADDR = 5'b00010;
parameter ST_MCU_RD_END = 5'b00100;
parameter ST_MCU_WR_ADDR = 5'b01000;
parameter ST_MCU_WR_END = 5'b10000;
parameter SNES_DEAD_TIMEOUT = 17'd96000; // 1ms
parameter ROM_CYCLE_LEN = 4'd7; // ideally 70ns but close enough...
reg [4:0] STATE;
initial STATE = ST_IDLE;
assign SNES_DATA = ~SNES_READ ? (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
: 8'bZ;
reg [3:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
wire MCU_WE_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_WR_HIT = |(STATE & (ST_MCU_WR_ADDR | ST_MCU_WR_END));
wire MCU_RD_HIT = |(STATE & (ST_MCU_RD_ADDR | ST_MCU_RD_END));
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
`ifdef MK2
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST)
);
assign ROM_ADDR = MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_CE = 1'b0;
assign p113_out = 1'b0;
`endif
`ifdef MK3
pll snes_pll(
.inclk0(CLKIN),
.c0(CLK2),
.locked(DCM_LOCKED),
.areset(DCM_RST)
);
wire ROM_ADDR22;
assign ROM_ADDR22 = MCU_HIT ? ROM_ADDRr[1] : MAPPED_SNES_ADDR[1];
assign ROM_ADDR = MCU_HIT ? ROM_ADDRr[23:2] : MAPPED_SNES_ADDR[23:2];
assign ROM_ADDR0 = MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_ZZ = 1'b1;
assign ROM_1CE = ROM_ADDR22;
assign ROM_2CE = ~ROM_ADDR22;
`endif
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
// MCU r/w request
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 18'h0;
end
always @(posedge CLK2) begin
if(SNES_CPU_CLKr[1]) SNES_DEADr <= 1'b0;
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(free_slot | SNES_DEADr) begin
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END: begin
STATE <= ST_IDLE;
end
endcase
end
assign ROM_DATA[7:0] = ROM_ADDR0
?((ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:((ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = (ROM_HIT & IS_SAVERAM & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WE_HIT ? 1'b0
: 1'b1;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = ~ROM_ADDR0;
assign SNES_DATABUS_OE = (SNES_ROMSEL & ~IS_SAVERAM)
|(SNES_READ_narrow & SNES_WRITE);
assign SNES_DATABUS_DIR = ~SNES_READ;
assign SNES_IRQ = 1'b0;
/*
wire [35:0] CONTROL0;
icon icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
ila_srtc ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SNES_ADDR), // IN BUS [23:0]
.TRIG1(SNES_DATA), // IN BUS [7:0]
.TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
.TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(spi_byte_cnt[3:0])
);
*/
/*
ila_srtc ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
.TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
.TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
.TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(ST_MEM_DELAYr)
);
*/
endmodule
|
module pwm (
input clk,
input enable,
input [31:0] clk_period,
input [31:0] pwm_period,
output out
);
reg clk_out=1'b0;
reg [31:0] counter = 32'b0;
always @(posedge clk)
begin
if (enable == 1'b1)
begin
if (counter < pwm_period)
begin
clk_out <= 1'b1;
counter <= counter + 32'b1;
end
else
begin
if (counter < (clk_period-1))
begin
clk_out <= 1'b0;
counter <= counter + 32'b1;
end
else
begin
clk_out <= 1'b0;
counter <= 32'b0;
end
end //end if counter < pwm_period
end //end if(enable)
else
begin
if ((counter > 0) && (counter < pwm_period) ) //gracefully end the last pwm if it has begun
begin
clk_out <= 1'b1;
counter <= counter + 32'b1;
end
else
begin
clk_out <= 1'b0;
counter <= 32'b0;
end
end
end
assign out = clk_out;
endmodule
|
module test_top();
dbl_buf #(1,
2,3,
REG_WIDTH
+
64)
dbl_buf (.rst_l(rst_l),
.clk(clk),
.wr(dbl_buf_wr),
.din(c2i_packet),
.rd(dbl_buf_rd),
.dout(outdata_buf_in),
.vld(dbl_buf_vld),
.full(dbl_buf_full));
module_being_instanced MODULE_NAME (
.serial_in ({serial_in[87:72] } ),
.afo ({afo[87:72] } ),
.serial_out ({serial_out[87:72] } ),
.afi ({afi[87:72] } ),
.vrefcode_i_l ({net0527[0] ,net0527[1] ,net0527[2] ,net0527[3] ,
net0527[4] ,net0527[5] ,net0527[6] ,net0527[7] } ),
.vrefcode_i_r ({net0578[0] ,net0578[1] ,net0578[2] ,net0578[3] ,
net0578[4] ,net0578[5] ,net0578[6] ,net0578[7] } ),
.data_neg
({\dram_io_data_out[247] ,
\dram_io_data_out[246] ,
\dram_io_data_out[245] ,
\dram_io_data_out[244] ,
\dram_io_data_out[243] ,
\dram_io_data_out[242] ,
\dram_io_data_out[241] ,
\dram_io_data_out[240] ,
\dram_io_data_out[183] ,
\dram_io_data_out[182] ,
\dram_io_data_out[181] ,
\dram_io_data_out[180] ,
\dram_io_data_out[179] ,
\dram_io_data_out[178] ,
\dram_io_data_out[177] ,
\dram_io_data_out[176] } )
);
endmodule
|
module sky130_fd_sc_ls__mux2_4 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__mux2_4 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
|
module sky130_fd_sc_hd__fah (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__a211o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__and3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
|
module i2c_slave (
// external host interface
input wire SCL, // the SCL pin state
input wire SDA,
output reg SDA_pd,
input wire clk, // internal FPGA clock
input wire glbl_reset, // internal FPGA reset
// i2c configuration
input wire [7:0] i2c_device_addr,
// internal slave interface
output wire [7:0] reg_0, // 00-3F are write-only (from the host perspective)
output wire [7:0] reg_2,
input wire [7:0] reg_40, // 40-7F are read-only (from the host perspective)
input wire [7:0] reg_41,
input wire [7:0] reg_42,
input wire [7:0] reg_fc, // this is for version coding
input wire [7:0] reg_fd,
input wire [7:0] reg_fe,
input wire [7:0] reg_ff
);
// internal reset
wire reset;
sync_reset i2c_slave_reset(
.clk(clk),
.glbl_reset(glbl_reset),
.reset(reset) );
/////// I2C physical layer components
/// SDA is stable when SCL is high.
/// If SDA moves while SCL is high, this is considered a start or stop condition.
///
/// Otherwise, SDA can move around when SCL is low (this is where we suppress bits or
/// overdrive as needed). SDA is a wired-AND bus, so you only "drive" zero.
///
/// In an oversampled implementation, a rising and falling edge de-glitcher is needed
/// for SCL and SDA.
///
// rise fall time cycles computation:
// At 400kHz operation, 2.5us is a cycle. "chatter" from transition should be about
// 5% of total cycle time max (just rule of thumb), so 0.125us should be the equiv
// number of cycles.
// For the demo board, a 25 MHz clock is provided, and 0.125us ~ 4 cycles
// At 100kHz operation, 10us is a cycle, so 0.5us ~ 12 cycles
parameter TRF_CYCLES = 5'd4; // number of cycles for rise/fall time
////////////////
///// protocol-level state machine
////////////////
parameter I2C_START = 14'b1 << 0; // should only pass through this state for one cycle
parameter I2C_RESTART = 14'b1 << 1;
parameter I2C_DADDR = 14'b1 << 2;
parameter I2C_ACK_DADDR = 14'b1 << 3;
parameter I2C_ADDR = 14'b1 << 4;
parameter I2C_ACK_ADDR = 14'b1 << 5;
parameter I2C_WR_DATA = 14'b1 << 6;
parameter I2C_ACK_WR = 14'b1 << 7;
parameter I2C_END_WR = 14'b1 << 8;
parameter I2C_RD_DATA = 14'b1 << 9;
parameter I2C_ACK_RD = 14'b1 << 10;
parameter I2C_END_RD = 14'b1 << 11;
parameter I2C_END_RD2 = 14'b1 << 12;
parameter I2C_WAITSTOP = 14'b1 << 13;
parameter I2C_nSTATES = 14;
reg [(I2C_nSTATES-1):0] I2C_cstate = {{(I2C_nSTATES-1){1'b0}}, 1'b1}; //current and next states
reg [(I2C_nSTATES-1):0] I2C_nstate;
//`define SIMULATION
`ifdef SIMULATION
// synthesis translate_off
reg [8*20:1] I2C_state_ascii = "I2C_START ";
always @(I2C_cstate) begin
if (I2C_cstate == I2C_START) I2C_state_ascii <= "I2C_START ";
else if (I2C_cstate == I2C_RESTART) I2C_state_ascii <= "I2C_RESTART ";
else if (I2C_cstate == I2C_DADDR) I2C_state_ascii <= "I2C_DADDR ";
else if (I2C_cstate == I2C_ACK_DADDR) I2C_state_ascii <= "I2C_ACK_DADDR ";
else if (I2C_cstate == I2C_ADDR) I2C_state_ascii <= "I2C_ADDR ";
else if (I2C_cstate == I2C_ACK_ADDR) I2C_state_ascii <= "I2C_ACK_ADDR ";
else if (I2C_cstate == I2C_WR_DATA) I2C_state_ascii <= "I2C_WR_DATA ";
else if (I2C_cstate == I2C_ACK_WR) I2C_state_ascii <= "I2C_ACK_WR ";
else if (I2C_cstate == I2C_END_WR) I2C_state_ascii <= "I2C_END_WR ";
else if (I2C_cstate == I2C_RD_DATA) I2C_state_ascii <= "I2C_RD_DATA ";
else if (I2C_cstate == I2C_ACK_RD) I2C_state_ascii <= "I2C_ACK_RD ";
else if (I2C_cstate == I2C_END_RD) I2C_state_ascii <= "I2C_END_RD ";
else if (I2C_cstate == I2C_END_RD2) I2C_state_ascii <= "I2C_END_RD2 ";
else if (I2C_cstate == I2C_WAITSTOP) I2C_state_ascii <= "I2C_WAITSTOP ";
else I2C_state_ascii <= "WTF ";
end
// synthesis translate_on
`endif
reg [3:0] I2C_bitcnt;
reg [7:0] I2C_addr;
reg [7:0] I2C_daddr;
reg [7:0] I2C_wdata;
reg [7:0] I2C_rdata;
reg I2C_reg_update;
///// register block definitions
parameter RAM_WIDTH = 8;
parameter RAM_ADDR_BITS = 6; // note parameter width exception in reg_a* assign block below
reg [RAM_WIDTH-1:0] I2C_regblock [(2**RAM_ADDR_BITS)-1:0];
reg [RAM_WIDTH-1:0] I2C_regread_async;
wire [RAM_ADDR_BITS-1:0] I2C_ramaddr;
////////// code begins here
always @ (posedge clk) begin
if (reset || ((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_RISE))) // stop condition always resets
I2C_cstate <= I2C_START;
else
I2C_cstate <= I2C_nstate;
end
always @ (*) begin
case (I2C_cstate) //synthesis parallel_case full_case
I2C_START: begin // wait for the start condition
I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_DADDR : I2C_START;
end
I2C_RESTART: begin // repeated start moves immediately to DADDR
I2C_nstate = I2C_DADDR;
end
I2C_DADDR: begin // 8 bits to get the address
I2C_nstate = ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_DADDR : I2C_DADDR;
end
I2C_ACK_DADDR: begin // depending upon W/R bit state, go to one of two branches
I2C_nstate = (SCL_cstate == SCL_FALL) ?
(I2C_daddr[7:1] == i2c_device_addr[7:1]) ?
(I2C_daddr[0] == 1'b0 ? I2C_ADDR : I2C_RD_DATA) :
I2C_WAITSTOP : // !I2C_daddr match
I2C_ACK_DADDR; // !SCL_FALL
end
// device address branch
I2C_ADDR: begin
I2C_nstate = ((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_ADDR : I2C_ADDR;
end
I2C_ACK_ADDR: begin
I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_WR_DATA : I2C_ACK_ADDR;
end
// write branch
I2C_WR_DATA: begin // 8 bits to get the write data
I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_RESTART : // repeated start
((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_WR : I2C_WR_DATA;
end
I2C_ACK_WR: begin // trigger the ack response (pull SDA low until next falling edge)
// and stay in this state until the next falling edge of SCL
I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_END_WR : I2C_ACK_WR;
end
I2C_END_WR: begin // one-cycle state to update address+1, reset SDA pulldown
I2C_nstate = I2C_WR_DATA; // SCL is now low
end
// read branch
I2C_RD_DATA: begin // 8 bits to get the read data
I2C_nstate = ((SDA_cstate == SDA_FALL) && (SCL_cstate == SCL_HIGH)) ? I2C_RESTART : // repeated start
((I2C_bitcnt > 4'h7) && (SCL_cstate == SCL_FALL)) ? I2C_ACK_RD : I2C_RD_DATA;
end
I2C_ACK_RD: begin // wait for an (n)ack response
// need to sample (n)ack on a rising edge
I2C_nstate = (SCL_cstate == SCL_RISE) ? I2C_END_RD : I2C_ACK_RD;
end
I2C_END_RD: begin // if nack, just go to start state (don't explicitly check stop event)
// single cycle state for adr+1 update
I2C_nstate = (SDA_cstate == SDA_LOW) ? I2C_END_RD2 : I2C_START;
end
I2C_END_RD2: begin // before entering I2C_RD_DATA, we need to have seen a falling edge.
I2C_nstate = (SCL_cstate == SCL_FALL) ? I2C_RD_DATA : I2C_END_RD2;
end
// we're not the addressed device, so we just idle until we see a stop
I2C_WAITSTOP: begin
I2C_nstate = (((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_RISE))) ? // stop
I2C_START :
(((SCL_cstate == SCL_HIGH) && (SDA_cstate == SDA_FALL))) ? // or start
I2C_RESTART :
I2C_WAITSTOP;
end
endcase // case (cstate)
end
always @ (posedge clk) begin
if( reset ) begin
I2C_bitcnt <= 4'b0;
I2C_daddr <= 8'b0;
I2C_wdata <= 8'b0;
SDA_pd <= 1'b0;
I2C_reg_update <= 1'b0;
I2C_rdata <= 8'b0;
I2C_addr <= 8'b0; // this persists across transactions
end else begin
case (I2C_cstate) // synthesis parallel_case full_case
I2C_START: begin // everything in reset
I2C_bitcnt <= 4'b0;
I2C_daddr <= 8'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= 8'b0;
SDA_pd <= 1'b0;
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end
I2C_RESTART: begin
I2C_bitcnt <= 4'b0;
I2C_daddr <= 8'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= 8'b0;
SDA_pd <= 1'b0;
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end
// get my i2c device address (am I being talked to?)
I2C_DADDR: begin // shift in the address on rising edges of clock
if( SCL_cstate == SCL_RISE ) begin
I2C_bitcnt <= I2C_bitcnt + 4'b1;
I2C_daddr[7] <= I2C_daddr[6];
I2C_daddr[6] <= I2C_daddr[5];
I2C_daddr[5] <= I2C_daddr[4];
I2C_daddr[4] <= I2C_daddr[3];
I2C_daddr[3] <= I2C_daddr[2];
I2C_daddr[2] <= I2C_daddr[1];
I2C_daddr[1] <= I2C_daddr[0];
I2C_daddr[0] <= (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0;
end else begin // we're oversampled so we need a hold-state gutter
I2C_bitcnt <= I2C_bitcnt;
I2C_daddr <= I2C_daddr;
end // else: !if( SCL_cstate == SCL_RISE )
SDA_pd <= 1'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= 8'b0;
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end // case: I2C_DADDR
I2C_ACK_DADDR: begin
SDA_pd <= 1'b1; // active pull down ACK
I2C_daddr <= I2C_daddr;
I2C_bitcnt <= 4'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= I2C_regread_async;
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end
// get my i2c "write" address (what we want to access inside me)
I2C_ADDR: begin
if( SCL_cstate == SCL_RISE ) begin
I2C_bitcnt <= I2C_bitcnt + 4'b1;
I2C_addr[7] <= I2C_addr[6];
I2C_addr[6] <= I2C_addr[5];
I2C_addr[5] <= I2C_addr[4];
I2C_addr[4] <= I2C_addr[3];
I2C_addr[3] <= I2C_addr[2];
I2C_addr[2] <= I2C_addr[1];
I2C_addr[1] <= I2C_addr[0];
I2C_addr[0] <= (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0;
end else begin // we're oversampled so we need a hold-state gutter
I2C_bitcnt <= I2C_bitcnt;
I2C_addr <= I2C_addr;
end // else: !if( SCL_cstate == SCL_RISE )
SDA_pd <= 1'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= 8'b0;
I2C_reg_update <= 1'b0;
I2C_daddr <= I2C_daddr;
end // case: I2C_ADDR
I2C_ACK_ADDR: begin
SDA_pd <= 1'b1; // active pull down ACK
I2C_daddr <= I2C_daddr;
I2C_bitcnt <= 4'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= I2C_regread_async; // update my read data here
I2C_reg_update <= 1'b0;
I2C_addr <= I2C_addr;
end
// write branch
I2C_WR_DATA: begin // shift in data on rising edges of clock
if( SCL_cstate == SCL_RISE ) begin
I2C_bitcnt <= I2C_bitcnt + 4'b1;
I2C_wdata[7] <= I2C_wdata[6];
I2C_wdata[6] <= I2C_wdata[5];
I2C_wdata[5] <= I2C_wdata[4];
I2C_wdata[4] <= I2C_wdata[3];
I2C_wdata[3] <= I2C_wdata[2];
I2C_wdata[2] <= I2C_wdata[1];
I2C_wdata[1] <= I2C_wdata[0];
I2C_wdata[0] <= (SDA_cstate == SDA_HIGH) ? 1'b1 : 1'b0;
end else begin
I2C_bitcnt <= I2C_bitcnt; // hold state gutter
I2C_wdata <= I2C_wdata;
end // else: !if( SCL_cstate == SCL_RISE )
SDA_pd <= 1'b0;
I2C_daddr <= I2C_daddr;
I2C_reg_update <= 1'b0;
I2C_rdata <= I2C_rdata;
I2C_addr <= I2C_addr;
end // case: I2C_WR_DATA
I2C_ACK_WR: begin
SDA_pd <= 1'b1; // active pull down ACK
I2C_daddr <= I2C_daddr;
I2C_bitcnt <= 4'b0;
I2C_wdata <= I2C_wdata;
I2C_reg_update <= 1'b1; // write the data now (over and over again while in state)
I2C_rdata <= I2C_rdata;
I2C_addr <= I2C_addr;
end
I2C_END_WR: begin
SDA_pd <= 1'b0; // let SDA rise (host may look for this to know ack is done
I2C_addr <= I2C_addr + 8'b1; // this is a one-cycle state so this is safe
I2C_bitcnt <= 4'b0;
I2C_wdata <= 8'b0;
I2C_rdata <= I2C_rdata;
I2C_reg_update <= 1'b0;
I2C_daddr <= I2C_daddr;
end
// read branch
I2C_RD_DATA: begin // shift out data on falling edges of clock
SDA_pd <= I2C_rdata[7] ? 1'b0 : 1'b1;
if( SCL_cstate == SCL_RISE ) begin
I2C_bitcnt <= I2C_bitcnt + 4'b1;
end else begin
I2C_bitcnt <= I2C_bitcnt; // hold state gutter
end
if( SCL_cstate == SCL_FALL ) begin
I2C_rdata[7] <= I2C_rdata[6];
I2C_rdata[6] <= I2C_rdata[5];
I2C_rdata[5] <= I2C_rdata[4];
I2C_rdata[4] <= I2C_rdata[3];
I2C_rdata[3] <= I2C_rdata[2];
I2C_rdata[2] <= I2C_rdata[1];
I2C_rdata[1] <= I2C_rdata[0];
I2C_rdata[0] <= 1'b0;
end else begin
I2C_rdata <= I2C_rdata;
end // else: !if( SCL_cstate == SCL_RISE )
I2C_daddr <= I2C_daddr;
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_addr <= I2C_addr;
end // case: I2C_RD_DATA
I2C_ACK_RD: begin
SDA_pd <= 1'b0; // in ack state don't pull down, we are listening to host
I2C_daddr <= I2C_daddr;
I2C_bitcnt <= 4'b0;
I2C_rdata <= I2C_rdata;
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_addr <= I2C_addr;
end
I2C_END_RD: begin
SDA_pd <= 1'b0; // let SDA rise (host may look for this to know ack is done
I2C_addr <= I2C_addr + 8'b1; // this is a one-cycle state so this is safe
I2C_bitcnt <= 4'b0;
I2C_rdata <= I2C_rdata;
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_daddr <= I2C_daddr;
end
I2C_END_RD2: begin
SDA_pd <= 1'b0;
I2C_daddr <= 8'b0;
I2C_bitcnt <= 4'b0;
I2C_rdata <= I2C_regread_async; // update my read data here
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_addr <= I2C_addr;
end
I2C_WAITSTOP: begin
SDA_pd <= 1'b0;
I2C_daddr <= 8'b0;
I2C_bitcnt <= 4'b0;
I2C_rdata <= I2C_rdata;
I2C_reg_update <= 1'b0;
I2C_wdata <= I2C_wdata;
I2C_addr <= I2C_addr;
end
endcase // case (cstate)
end // else: !if( reset )
end // always @ (posedge clk or posedge reset)
////////////////////////////////////
///// register bank management /////
////////////////////////////////////
// main block update (write from I2C)
always @(posedge clk) begin
if (I2C_reg_update && ((I2C_addr[6] == 1'b0) && (I2C_addr[7] == 1'b0))) begin // I2C_addr < 8'h40
I2C_regblock[I2C_ramaddr] <= I2C_wdata;
end
end
assign I2C_ramaddr = I2C_addr[RAM_ADDR_BITS-1:0];
///////// ick, had to hard-code the width against RAM_ADDR_BITS which is parameterized
assign reg_0 = I2C_regblock[6'h0];
assign reg_2 = I2C_regblock[6'h2];
always @(*) begin
case (I2C_addr[7:0])
8'h40: begin
I2C_regread_async = reg_40;
end
8'h41: begin
I2C_regread_async = reg_41;
end
8'h42: begin
I2C_regread_async = reg_42;
end
8'hfc: begin
I2C_regread_async = reg_fc;
end
8'hfd: begin
I2C_regread_async = reg_fd;
end
8'hfe: begin
I2C_regread_async = reg_fe;
end
8'hff: begin
I2C_regread_async = reg_ff;
end
default: begin
I2C_regread_async = I2C_regblock[I2C_ramaddr];
end
endcase // case I2C_ramaddr
end // always @ (*)
///////////////////////////////////////////////////////////////
/////////// low level state machines //////////////////////////
///////////////////////////////////////////////////////////////
////////////////
///// SCL low-level sampling state machine
////////////////
parameter SCL_HIGH = 4'b1 << 0; // should only pass through this state for one cycle
parameter SCL_FALL = 4'b1 << 1;
parameter SCL_LOW = 4'b1 << 2;
parameter SCL_RISE = 4'b1 << 3;
parameter SCL_nSTATES = 4;
reg [(SCL_nSTATES-1):0] SCL_cstate = {{(SCL_nSTATES-1){1'b0}}, 1'b1}; //current and next states
reg [(SCL_nSTATES-1):0] SCL_nstate;
//`define SIMULATION
`ifdef SIMULATION
// synthesis translate_off
reg [8*20:1] SCL_state_ascii = "SCL_HIGH ";
always @(SCL_cstate) begin
if (SCL_cstate == SCL_HIGH) SCL_state_ascii <= "SCL_HIGH ";
else if (SCL_cstate == SCL_FALL) SCL_state_ascii <= "SCL_FALL ";
else if (SCL_cstate == SCL_LOW ) SCL_state_ascii <= "SCL_LOW ";
else if (SCL_cstate == SCL_RISE) SCL_state_ascii <= "SCL_RISE ";
else SCL_state_ascii <= "WTF ";
end
// synthesis translate_on
`endif
reg [4:0] SCL_rfcnt;
reg SCL_s, SCL_sync;
reg SDA_s, SDA_sync;
always @ (posedge clk) begin
if (reset)
SCL_cstate <= SCL_HIGH; // always start here even if it's wrong -- easier to test
else
SCL_cstate <= SCL_nstate;
end
always @ (*) begin
case (SCL_cstate) //synthesis parallel_case full_case
SCL_HIGH: begin
SCL_nstate = ((SCL_rfcnt > TRF_CYCLES) && (SCL_sync == 1'b0)) ? SCL_FALL : SCL_HIGH;
end
SCL_FALL: begin
SCL_nstate = SCL_LOW;
end
SCL_LOW: begin
SCL_nstate = ((SCL_rfcnt > TRF_CYCLES) && (SCL_sync == 1'b1)) ? SCL_RISE : SCL_LOW;
end
SCL_RISE: begin
SCL_nstate = SCL_HIGH;
end
endcase // case (cstate)
end // always @ (*)
always @ (posedge clk) begin
if( reset ) begin
SCL_rfcnt <= 5'b0;
end else begin
case (SCL_cstate) // synthesis parallel_case full_case
SCL_HIGH: begin
if( SCL_sync == 1'b1 ) begin
SCL_rfcnt <= 5'b0;
end else begin
SCL_rfcnt <= SCL_rfcnt + 5'b1;
end
end
SCL_FALL: begin
SCL_rfcnt <= 5'b0;
end
SCL_LOW: begin
if( SCL_sync == 1'b0 ) begin
SCL_rfcnt <= 5'b0;
end else begin
SCL_rfcnt <= SCL_rfcnt + 5'b1;
end
end
SCL_RISE: begin
SCL_rfcnt <= 5'b0;
end
endcase // case (cstate)
end // else: !if( reset )
end // always @ (posedge clk or posedge reset)
////////////////
///// SDA low-level sampling state machine
////////////////
parameter SDA_HIGH = 4'b1 << 0; // should only pass through this state for one cycle
parameter SDA_FALL = 4'b1 << 1;
parameter SDA_LOW = 4'b1 << 2;
parameter SDA_RISE = 4'b1 << 3;
parameter SDA_nSTATES = 4;
reg [(SDA_nSTATES-1):0] SDA_cstate = {{(SDA_nSTATES-1){1'b0}}, 1'b1}; //current and next states
reg [(SDA_nSTATES-1):0] SDA_nstate;
//`define SIMULATION
`ifdef SIMULATION
// synthesis translate_off
reg [8*20:1] SDA_state_ascii = "SDA_HIGH ";
always @(SDA_cstate) begin
if (SDA_cstate == SDA_HIGH) SDA_state_ascii <= "SDA_HIGH ";
else if (SDA_cstate == SDA_FALL) SDA_state_ascii <= "SDA_FALL ";
else if (SDA_cstate == SDA_LOW ) SDA_state_ascii <= "SDA_LOW ";
else if (SDA_cstate == SDA_RISE) SDA_state_ascii <= "SDA_RISE ";
else SDA_state_ascii <= "WTF ";
end
// synthesis translate_on
`endif
reg [4:0] SDA_rfcnt;
always @ (posedge clk) begin
if (reset)
SDA_cstate <= SDA_HIGH; // always start here even if it's wrong -- easier to test
else
SDA_cstate <= SDA_nstate;
end
always @ (*) begin
case (SDA_cstate) //synthesis parallel_case full_case
SDA_HIGH: begin
SDA_nstate = ((SDA_rfcnt > TRF_CYCLES) && (SDA_sync == 1'b0)) ? SDA_FALL : SDA_HIGH;
end
SDA_FALL: begin
SDA_nstate = SDA_LOW;
end
SDA_LOW: begin
SDA_nstate = ((SDA_rfcnt > TRF_CYCLES) && (SDA_sync == 1'b1)) ? SDA_RISE : SDA_LOW;
end
SDA_RISE: begin
SDA_nstate = SDA_HIGH;
end
endcase // case (cstate)
end // always @ (*)
always @ (posedge clk) begin
if( reset ) begin
SDA_rfcnt <= 5'b0;
end else begin
case (SDA_cstate) // synthesis parallel_case full_case
SDA_HIGH: begin
if( SDA_sync == 1'b1 ) begin
SDA_rfcnt <= 5'b0;
end else begin
SDA_rfcnt <= SDA_rfcnt + 5'b1;
end
end
SDA_FALL: begin
SDA_rfcnt <= 5'b0;
end
SDA_LOW: begin
if( SDA_sync == 1'b0 ) begin
SDA_rfcnt <= 5'b0;
end else begin
SDA_rfcnt <= SDA_rfcnt + 5'b1;
end
end
SDA_RISE: begin
SDA_rfcnt <= 5'b0;
end
endcase // case (cstate)
end // else: !if( reset )
end // always @ (posedge clk or posedge reset)
/////////////////////
/////// synchronizers
/////////////////////
always @ (posedge clk) begin
SCL_s <= SCL;
SCL_sync <= SCL_s;
SDA_s <= SDA;
SDA_sync <= SDA_s;
end // always @ (posedge clk or posedge reset)
endmodule
|
module test_xfcp_arb_2;
// Parameters
parameter PORTS = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS*8-1:0] up_xfcp_in_tdata = 0;
reg [PORTS-1:0] up_xfcp_in_tvalid = 0;
reg [PORTS-1:0] up_xfcp_in_tlast = 0;
reg [PORTS-1:0] up_xfcp_in_tuser = 0;
reg [PORTS-1:0] up_xfcp_out_tready = 0;
reg [7:0] down_xfcp_in_tdata = 0;
reg down_xfcp_in_tvalid = 0;
reg down_xfcp_in_tlast = 0;
reg down_xfcp_in_tuser = 0;
reg down_xfcp_out_tready = 0;
// Outputs
wire [PORTS-1:0] up_xfcp_in_tready;
wire [PORTS*8-1:0] up_xfcp_out_tdata;
wire [PORTS-1:0] up_xfcp_out_tvalid;
wire [PORTS-1:0] up_xfcp_out_tlast;
wire [PORTS-1:0] up_xfcp_out_tuser;
wire down_xfcp_in_tready;
wire [7:0] down_xfcp_out_tdata;
wire down_xfcp_out_tvalid;
wire down_xfcp_out_tlast;
wire down_xfcp_out_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
up_xfcp_in_tdata,
up_xfcp_in_tvalid,
up_xfcp_in_tlast,
up_xfcp_in_tuser,
up_xfcp_out_tready,
down_xfcp_in_tdata,
down_xfcp_in_tvalid,
down_xfcp_in_tlast,
down_xfcp_in_tuser,
down_xfcp_out_tready
);
$to_myhdl(
up_xfcp_in_tready,
up_xfcp_out_tdata,
up_xfcp_out_tvalid,
up_xfcp_out_tlast,
up_xfcp_out_tuser,
down_xfcp_in_tready,
down_xfcp_out_tdata,
down_xfcp_out_tvalid,
down_xfcp_out_tlast,
down_xfcp_out_tuser
);
// dump file
$dumpfile("test_xfcp_arb_2.lxt");
$dumpvars(0, test_xfcp_arb_2);
end
xfcp_arb #(
.PORTS(PORTS)
)
UUT (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(up_xfcp_in_tdata),
.up_xfcp_in_tvalid(up_xfcp_in_tvalid),
.up_xfcp_in_tready(up_xfcp_in_tready),
.up_xfcp_in_tlast(up_xfcp_in_tlast),
.up_xfcp_in_tuser(up_xfcp_in_tuser),
.up_xfcp_out_tdata(up_xfcp_out_tdata),
.up_xfcp_out_tvalid(up_xfcp_out_tvalid),
.up_xfcp_out_tready(up_xfcp_out_tready),
.up_xfcp_out_tlast(up_xfcp_out_tlast),
.up_xfcp_out_tuser(up_xfcp_out_tuser),
.down_xfcp_in_tdata(down_xfcp_in_tdata),
.down_xfcp_in_tvalid(down_xfcp_in_tvalid),
.down_xfcp_in_tready(down_xfcp_in_tready),
.down_xfcp_in_tlast(down_xfcp_in_tlast),
.down_xfcp_in_tuser(down_xfcp_in_tuser),
.down_xfcp_out_tdata(down_xfcp_out_tdata),
.down_xfcp_out_tvalid(down_xfcp_out_tvalid),
.down_xfcp_out_tready(down_xfcp_out_tready),
.down_xfcp_out_tlast(down_xfcp_out_tlast),
.down_xfcp_out_tuser(down_xfcp_out_tuser)
);
endmodule
|
module SCB_P4_v1_20_0 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("723379629.62963"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_379;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
tx
(.oe(tmpOE__tx_net),
.y({Net_656}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_379}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 2;
endmodule
|
module TCPWM_P4_v1_10_1 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
parameter PWMCountMode = 3;
parameter PWMReloadMode = 0;
parameter PWMReloadPresent = 0;
parameter PWMStartMode = 0;
parameter PWMStopMode = 0;
parameter PWMSwitchMode = 0;
parameter QuadIndexMode = 0;
parameter QuadPhiAMode = 3;
parameter QuadPhiBMode = 3;
parameter QuadStopMode = 0;
parameter TCCaptureMode = 0;
parameter TCCountMode = 3;
parameter TCReloadMode = 0;
parameter TCStartMode = 0;
parameter TCStopMode = 0;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(capture),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(count),
.reload(reload),
.stop(stop),
.start(start),
.clock(clock));
endmodule
|
module PWM_v3_0_2 (
pwm2,
tc,
clock,
reset,
pwm1,
interrupt,
capture,
kill,
enable,
trigger,
cmp_sel,
pwm,
ph1,
ph2);
output pwm2;
output tc;
input clock;
input reset;
output pwm1;
output interrupt;
input capture;
input kill;
input enable;
input trigger;
input cmp_sel;
output pwm;
output ph1;
output ph2;
parameter Resolution = 16;
B_PWM_v3_0 PWMUDB (
.reset(reset),
.clock(clock),
.tc(tc),
.pwm1(pwm1),
.pwm2(pwm2),
.interrupt(interrupt),
.kill(kill),
.capture(capture),
.enable(enable),
.cmp_sel(cmp_sel),
.trigger(trigger),
.pwm(pwm),
.ph1(ph1),
.ph2(ph2));
defparam PWMUDB.CaptureMode = 0;
defparam PWMUDB.CompareStatusEdgeSense = 1;
defparam PWMUDB.CompareType1 = 1;
defparam PWMUDB.CompareType2 = 1;
defparam PWMUDB.DeadBand = 0;
defparam PWMUDB.DitherOffset = 0;
defparam PWMUDB.EnableMode = 0;
defparam PWMUDB.KillMode = 0;
defparam PWMUDB.PWMMode = 1;
defparam PWMUDB.Resolution = 16;
defparam PWMUDB.RunMode = 0;
defparam PWMUDB.TriggerMode = 0;
defparam PWMUDB.UseStatus = 1;
endmodule
|
module TCPWM_P4_v1_10_3 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
parameter PWMCountMode = 3;
parameter PWMReloadMode = 0;
parameter PWMReloadPresent = 0;
parameter PWMStartMode = 0;
parameter PWMStopMode = 0;
parameter PWMSwitchMode = 0;
parameter QuadIndexMode = 0;
parameter QuadPhiAMode = 3;
parameter QuadPhiBMode = 3;
parameter QuadStopMode = 0;
parameter TCCaptureMode = 0;
parameter TCCountMode = 3;
parameter TCReloadMode = 0;
parameter TCStartMode = 0;
parameter TCStopMode = 0;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(capture),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(count),
.reload(reload),
.stop(stop),
.start(start),
.clock(clock));
endmodule
|
module SPI_Master_v2_40_4 (
clock,
reset,
miso,
sclk,
mosi,
ss,
rx_interrupt,
sdat,
tx_interrupt);
input clock;
input reset;
input miso;
output sclk;
output mosi;
output ss;
output rx_interrupt;
inout sdat;
output tx_interrupt;
parameter BidirectMode = 0;
parameter HighSpeedMode = 0;
parameter NumberOfDataBits = 8;
parameter ShiftDir = 0;
wire Net_257;
wire Net_273;
wire Net_274;
wire Net_244;
wire Net_239;
wire Net_253;
wire Net_161;
wire Net_276;
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_276 = Net_239;
cy_clock_v1_0
#(.id("e4da4994-29f1-40ba-bb7d-e88b51dcb21f/426fcbe0-714d-4404-8fa8-581ff40c30f1"),
.source_clock_id(""),
.divisor(0),
.period("500000000"),
.is_direct(0),
.is_digital(1))
IntClock
(.clock_out(Net_239));
B_SPI_Master_v2_40 BSPIM (
.sclk(sclk),
.ss(ss),
.miso(Net_244),
.clock(Net_276),
.reset(Net_273),
.rx_interpt(rx_interrupt),
.tx_enable(Net_253),
.mosi(mosi),
.tx_interpt(tx_interrupt));
defparam BSPIM.BidirectMode = 0;
defparam BSPIM.HighSpeedMode = 0;
defparam BSPIM.ModeCPHA = 0;
defparam BSPIM.ModePOL = 0;
defparam BSPIM.NumberOfDataBits = 8;
defparam BSPIM.ShiftDir = 0;
// VirtualMux_2 (cy_virtualmux_v1_0)
assign Net_244 = miso;
// VirtualMux_3 (cy_virtualmux_v1_0)
assign Net_273 = Net_274;
ZeroTerminal ZeroTerminal_1 (
.z(Net_274));
endmodule
|
module SCB_P4_v1_20_5 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("b3725c4c-8efb-44d3-a7b2-1035b9d0204d/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("17361111111.1111"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_379;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("b3725c4c-8efb-44d3-a7b2-1035b9d0204d/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_379}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 2;
endmodule
|
module TCPWM_P4_v1_10_6 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
parameter PWMCountMode = 3;
parameter PWMReloadMode = 0;
parameter PWMReloadPresent = 0;
parameter PWMStartMode = 0;
parameter PWMStopMode = 0;
parameter PWMSwitchMode = 0;
parameter QuadIndexMode = 0;
parameter QuadPhiAMode = 3;
parameter QuadPhiBMode = 3;
parameter QuadStopMode = 0;
parameter TCCaptureMode = 0;
parameter TCCountMode = 3;
parameter TCReloadMode = 0;
parameter TCStartMode = 0;
parameter TCStopMode = 0;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(capture),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(count),
.reload(reload),
.stop(stop),
.start(start),
.clock(clock));
endmodule
|
module top ;
wire Net_829;
wire Net_828;
wire Net_827;
wire Net_826;
wire Net_825;
wire Net_824;
wire Net_823;
wire Net_822;
wire Net_821;
wire Net_820;
wire Net_778;
wire Net_777;
wire Net_776;
wire Net_775;
wire Net_774;
wire Net_773;
wire Net_772;
wire Net_771;
wire Net_770;
wire Net_769;
wire Net_757;
wire Net_756;
wire Net_872;
wire Net_864;
wire Net_863;
wire Net_681;
wire Net_862;
wire Net_861;
wire Net_678;
wire Net_676;
wire Net_675;
wire Net_768;
wire Net_767;
wire Net_766;
wire Net_765;
wire Net_764;
wire Net_763;
wire Net_762;
wire Net_761;
wire Net_760;
wire Net_759;
wire Net_505;
wire Net_504;
wire Net_132;
wire Net_609;
wire Net_608;
wire Net_607;
wire Net_606;
wire Net_605;
wire Net_604;
wire Net_603;
wire Net_602;
wire Net_601;
wire Net_519;
wire Net_518;
wire Net_600;
wire Net_599;
wire Net_80;
wire Net_79;
wire Net_78;
wire Net_77;
wire Net_76;
wire Net_75;
wire Net_74;
wire Net_73;
wire Net_72;
wire Net_71;
wire Net_6;
wire Net_4;
wire Net_747;
wire Net_701;
wire Net_496;
wire Net_49;
wire Net_5;
SCB_P4_v1_20_0 UART_1 (
.sclk(Net_4),
.interrupt(Net_5),
.clock(1'b0));
cy_isr_v1_0
#(.int_type(2'b10))
isr
(.int_signal(Net_49));
TCPWM_P4_v1_10_1 Timer (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_49),
.ov(Net_76),
.un(Net_77),
.cc(Net_78),
.line(Net_79),
.line_n(Net_80),
.clock(Net_496));
defparam Timer.PWMCountMode = 3;
defparam Timer.PWMReloadMode = 0;
defparam Timer.PWMReloadPresent = 0;
defparam Timer.PWMStartMode = 0;
defparam Timer.PWMStopMode = 0;
defparam Timer.PWMSwitchMode = 0;
defparam Timer.QuadIndexMode = 0;
defparam Timer.QuadPhiAMode = 3;
defparam Timer.QuadPhiBMode = 3;
defparam Timer.QuadStopMode = 0;
defparam Timer.TCCaptureMode = 0;
defparam Timer.TCCountMode = 3;
defparam Timer.TCReloadMode = 0;
defparam Timer.TCStartMode = 0;
defparam Timer.TCStopMode = 0;
cy_isr_v1_0
#(.int_type(2'b10))
ISRUART
(.int_signal(Net_5));
PWM_v3_0_2 Gimbal (
.reset(1'b0),
.clock(Net_496),
.tc(Net_600),
.pwm1(Net_518),
.pwm2(Net_519),
.interrupt(Net_601),
.capture(1'b0),
.kill(1'b1),
.enable(1'b1),
.trigger(1'b0),
.cmp_sel(1'b0),
.pwm(Net_607),
.ph1(Net_608),
.ph2(Net_609));
defparam Gimbal.Resolution = 16;
cy_clock_v1_0
#(.id("77085c73-d3db-49de-a1ad-2dc98b341901"),
.source_clock_id(""),
.divisor(0),
.period("1000000000"),
.is_direct(0),
.is_digital(1))
Clock_2
(.clock_out(Net_496));
wire [0:0] tmpOE__L_Servo_net;
wire [0:0] tmpFB_0__L_Servo_net;
wire [0:0] tmpIO_0__L_Servo_net;
wire [0:0] tmpINTERRUPT_0__L_Servo_net;
electrical [0:0] tmpSIOVREF__L_Servo_net;
cy_psoc3_pins_v1_10
#(.id("52f31aa9-2f0a-497d-9a1f-1424095e13e6"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
L_Servo
(.oe(tmpOE__L_Servo_net),
.y({Net_504}),
.fb({tmpFB_0__L_Servo_net[0:0]}),
.io({tmpIO_0__L_Servo_net[0:0]}),
.siovref(tmpSIOVREF__L_Servo_net),
.interrupt({tmpINTERRUPT_0__L_Servo_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__L_Servo_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__R_Servo_net;
wire [0:0] tmpFB_0__R_Servo_net;
wire [0:0] tmpIO_0__R_Servo_net;
wire [0:0] tmpINTERRUPT_0__R_Servo_net;
electrical [0:0] tmpSIOVREF__R_Servo_net;
cy_psoc3_pins_v1_10
#(.id("b2308480-dcd7-4ee5-bbdc-18916ee367be"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
R_Servo
(.oe(tmpOE__R_Servo_net),
.y({Net_505}),
.fb({tmpFB_0__R_Servo_net[0:0]}),
.io({tmpIO_0__R_Servo_net[0:0]}),
.siovref(tmpSIOVREF__R_Servo_net),
.interrupt({tmpINTERRUPT_0__R_Servo_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__R_Servo_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
TCPWM_P4_v1_10_3 Wheels_1 (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_764),
.ov(Net_765),
.un(Net_766),
.cc(Net_767),
.line(Net_504),
.line_n(Net_768),
.clock(Net_496));
defparam Wheels_1.PWMCountMode = 3;
defparam Wheels_1.PWMReloadMode = 0;
defparam Wheels_1.PWMReloadPresent = 0;
defparam Wheels_1.PWMStartMode = 0;
defparam Wheels_1.PWMStopMode = 0;
defparam Wheels_1.PWMSwitchMode = 0;
defparam Wheels_1.QuadIndexMode = 0;
defparam Wheels_1.QuadPhiAMode = 3;
defparam Wheels_1.QuadPhiBMode = 3;
defparam Wheels_1.QuadStopMode = 0;
defparam Wheels_1.TCCaptureMode = 0;
defparam Wheels_1.TCCountMode = 3;
defparam Wheels_1.TCReloadMode = 0;
defparam Wheels_1.TCStartMode = 0;
defparam Wheels_1.TCStopMode = 0;
wire [0:0] tmpOE__GimbalP_net;
wire [0:0] tmpFB_0__GimbalP_net;
wire [0:0] tmpIO_0__GimbalP_net;
wire [0:0] tmpINTERRUPT_0__GimbalP_net;
electrical [0:0] tmpSIOVREF__GimbalP_net;
cy_psoc3_pins_v1_10
#(.id("8c1b8be6-e5e7-4bce-905a-4cfa28d02e70"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
GimbalP
(.oe(tmpOE__GimbalP_net),
.y({Net_518}),
.fb({tmpFB_0__GimbalP_net[0:0]}),
.io({tmpIO_0__GimbalP_net[0:0]}),
.siovref(tmpSIOVREF__GimbalP_net),
.interrupt({tmpINTERRUPT_0__GimbalP_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__GimbalP_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__GimbalT_net;
wire [0:0] tmpFB_0__GimbalT_net;
wire [0:0] tmpIO_0__GimbalT_net;
wire [0:0] tmpINTERRUPT_0__GimbalT_net;
electrical [0:0] tmpSIOVREF__GimbalT_net;
cy_psoc3_pins_v1_10
#(.id("c2106cdb-687e-44ec-9e29-5bc0f817d259"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
GimbalT
(.oe(tmpOE__GimbalT_net),
.y({Net_519}),
.fb({tmpFB_0__GimbalT_net[0:0]}),
.io({tmpIO_0__GimbalT_net[0:0]}),
.siovref(tmpSIOVREF__GimbalT_net),
.interrupt({tmpINTERRUPT_0__GimbalT_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__GimbalT_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
SPI_Master_v2_40_4 SPIM (
.mosi(Net_675),
.sclk(Net_676),
.ss(Net_747),
.miso(Net_678),
.clock(1'b0),
.reset(1'b0),
.rx_interrupt(Net_681),
.sdat(Net_863),
.tx_interrupt(Net_864));
defparam SPIM.BidirectMode = 0;
defparam SPIM.HighSpeedMode = 0;
defparam SPIM.NumberOfDataBits = 8;
defparam SPIM.ShiftDir = 0;
cy_isr_v1_0
#(.int_type(2'b10))
ISRSPI
(.int_signal(Net_872));
SCB_P4_v1_20_5 GPS_UART (
.sclk(Net_756),
.interrupt(Net_701),
.clock(1'b0));
cy_isr_v1_0
#(.int_type(2'b10))
ISR_UART_2
(.int_signal(Net_701));
wire [0:0] tmpOE__MISO_net;
wire [0:0] tmpIO_0__MISO_net;
wire [0:0] tmpINTERRUPT_0__MISO_net;
electrical [0:0] tmpSIOVREF__MISO_net;
cy_psoc3_pins_v1_10
#(.id("552faf00-97dc-47bf-ad14-15574b2c6e9b"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
MISO
(.oe(tmpOE__MISO_net),
.y({1'b0}),
.fb({Net_678}),
.io({tmpIO_0__MISO_net[0:0]}),
.siovref(tmpSIOVREF__MISO_net),
.interrupt({tmpINTERRUPT_0__MISO_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__MISO_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__MOSI_net;
wire [0:0] tmpFB_0__MOSI_net;
wire [0:0] tmpIO_0__MOSI_net;
wire [0:0] tmpINTERRUPT_0__MOSI_net;
electrical [0:0] tmpSIOVREF__MOSI_net;
cy_psoc3_pins_v1_10
#(.id("0e0c9380-6965-4440-8709-ce08a91e474c"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
MOSI
(.oe(tmpOE__MOSI_net),
.y({Net_675}),
.fb({tmpFB_0__MOSI_net[0:0]}),
.io({tmpIO_0__MOSI_net[0:0]}),
.siovref(tmpSIOVREF__MOSI_net),
.interrupt({tmpINTERRUPT_0__MOSI_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__MOSI_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__SCLK_net;
wire [0:0] tmpFB_0__SCLK_net;
wire [0:0] tmpIO_0__SCLK_net;
wire [0:0] tmpINTERRUPT_0__SCLK_net;
electrical [0:0] tmpSIOVREF__SCLK_net;
cy_psoc3_pins_v1_10
#(.id("7f71d314-4523-45d3-b07e-62700396d125"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
SCLK
(.oe(tmpOE__SCLK_net),
.y({Net_676}),
.fb({tmpFB_0__SCLK_net[0:0]}),
.io({tmpIO_0__SCLK_net[0:0]}),
.siovref(tmpSIOVREF__SCLK_net),
.interrupt({tmpINTERRUPT_0__SCLK_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__SCLK_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
TCPWM_P4_v1_10_6 Wheels_2 (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_774),
.ov(Net_775),
.un(Net_776),
.cc(Net_777),
.line(Net_505),
.line_n(Net_778),
.clock(Net_496));
defparam Wheels_2.PWMCountMode = 3;
defparam Wheels_2.PWMReloadMode = 0;
defparam Wheels_2.PWMReloadPresent = 0;
defparam Wheels_2.PWMStartMode = 0;
defparam Wheels_2.PWMStopMode = 0;
defparam Wheels_2.PWMSwitchMode = 0;
defparam Wheels_2.QuadIndexMode = 0;
defparam Wheels_2.QuadPhiAMode = 3;
defparam Wheels_2.QuadPhiBMode = 3;
defparam Wheels_2.QuadStopMode = 0;
defparam Wheels_2.TCCaptureMode = 0;
defparam Wheels_2.TCCountMode = 3;
defparam Wheels_2.TCReloadMode = 0;
defparam Wheels_2.TCStartMode = 0;
defparam Wheels_2.TCStopMode = 0;
CyControlReg_v1_70 VidMux (
.control_1(Net_820),
.control_2(Net_821),
.control_3(Net_822),
.control_0(Net_823),
.control_4(Net_824),
.control_5(Net_825),
.control_6(Net_826),
.control_7(Net_827),
.clock(1'b0),
.reset(1'b0));
defparam VidMux.Bit0Mode = 0;
defparam VidMux.Bit1Mode = 0;
defparam VidMux.Bit2Mode = 0;
defparam VidMux.Bit3Mode = 0;
defparam VidMux.Bit4Mode = 0;
defparam VidMux.Bit5Mode = 0;
defparam VidMux.Bit6Mode = 0;
defparam VidMux.Bit7Mode = 0;
defparam VidMux.BitValue = 0;
defparam VidMux.BusDisplay = 0;
defparam VidMux.ExtrReset = 0;
defparam VidMux.NumOutputs = 3;
wire [0:0] tmpOE__WIZ_RST_net;
wire [0:0] tmpFB_0__WIZ_RST_net;
wire [0:0] tmpIO_0__WIZ_RST_net;
wire [0:0] tmpINTERRUPT_0__WIZ_RST_net;
electrical [0:0] tmpSIOVREF__WIZ_RST_net;
cy_psoc3_pins_v1_10
#(.id("0685bd1c-6e36-4e2b-bb80-086b6cfb9431"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
WIZ_RST
(.oe(tmpOE__WIZ_RST_net),
.y({1'b0}),
.fb({tmpFB_0__WIZ_RST_net[0:0]}),
.io({tmpIO_0__WIZ_RST_net[0:0]}),
.siovref(tmpSIOVREF__WIZ_RST_net),
.interrupt({tmpINTERRUPT_0__WIZ_RST_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__WIZ_RST_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__WIZ_RDY_net;
wire [0:0] tmpFB_0__WIZ_RDY_net;
wire [0:0] tmpIO_0__WIZ_RDY_net;
wire [0:0] tmpINTERRUPT_0__WIZ_RDY_net;
electrical [0:0] tmpSIOVREF__WIZ_RDY_net;
cy_psoc3_pins_v1_10
#(.id("7f151c7d-1f6c-461e-9c68-16dcffc8e4d8"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
WIZ_RDY
(.oe(tmpOE__WIZ_RDY_net),
.y({1'b0}),
.fb({tmpFB_0__WIZ_RDY_net[0:0]}),
.io({tmpIO_0__WIZ_RDY_net[0:0]}),
.siovref(tmpSIOVREF__WIZ_RDY_net),
.interrupt({tmpINTERRUPT_0__WIZ_RDY_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__WIZ_RDY_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__WIZ_INT_net;
wire [0:0] tmpIO_0__WIZ_INT_net;
wire [0:0] tmpINTERRUPT_0__WIZ_INT_net;
electrical [0:0] tmpSIOVREF__WIZ_INT_net;
cy_psoc3_pins_v1_10
#(.id("f7e52380-b69e-4bcf-b0e7-b82bec578576"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
WIZ_INT
(.oe(tmpOE__WIZ_INT_net),
.y({1'b0}),
.fb({Net_872}),
.io({tmpIO_0__WIZ_INT_net[0:0]}),
.siovref(tmpSIOVREF__WIZ_INT_net),
.interrupt({tmpINTERRUPT_0__WIZ_INT_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__WIZ_INT_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__WIZ_SS_net;
wire [0:0] tmpFB_0__WIZ_SS_net;
wire [0:0] tmpIO_0__WIZ_SS_net;
wire [0:0] tmpINTERRUPT_0__WIZ_SS_net;
electrical [0:0] tmpSIOVREF__WIZ_SS_net;
cy_psoc3_pins_v1_10
#(.id("c5824ab3-47bc-41f7-b4a6-1015f51c5578"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
WIZ_SS
(.oe(tmpOE__WIZ_SS_net),
.y({1'b0}),
.fb({tmpFB_0__WIZ_SS_net[0:0]}),
.io({tmpIO_0__WIZ_SS_net[0:0]}),
.siovref(tmpSIOVREF__WIZ_SS_net),
.interrupt({tmpINTERRUPT_0__WIZ_SS_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__WIZ_SS_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
endmodule
|
module TestBench;
// Inputs
reg Clock;
reg Reset;
// Outputs
wire [7:0] oLed;
// Instantiate the Unit Under Test (UUT)
MiniAlu uut (
.Clock(Clock),
.Reset(Reset),
.oLed(oLed)
);
always
begin
#5 Clock = ! Clock;
end
initial begin
// Initialize Inputs
Clock = 0;
Reset = 0;
// Wait 100 ns for global reset to finish
#100;
Reset = 1;
#50
Reset = 0;
// Add stimulus here
end
endmodule
|
module lights_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
module testbench_CLA_Array();
localparam bits = 64;
reg[bits-1:0] a;
reg[bits-1:0] b;
reg cin;
wire[bits-1:0] result;
wire cout;
wire[bits:0] expectOutput;
reg errorFlag = 0;
integer i;
assign expectOutput = a + b + cin;
initial begin
a = 64'h1111111111111111;
b = 64'hffffffffffffffff;
cin = 1;
#10;
if ({cout,result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout,result}, expectOutput);
end
a = 64'h0000000000000000;
b = 64'hffffffffffffffff;
cin = 1;
#10;
if ({cout,result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout,result}, expectOutput);
end
a = 64'h1111111111111111;
b = 64'heeeeeeeeeeeeeeee;
cin = 1;
#10;
if ({cout,result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout,result}, expectOutput);
end
for(i = 0;i < 32'hffff; i = i+1) begin
a = {$random(), $random()};
b = {$random(), $random()};
cin = ($random()&1);
#10;
if ({cout,result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout,result}, expectOutput);
end
end
if (errorFlag === 0) begin
$display("Test passed");
end
else begin
$display("Test failed");
end
end
CLA_Array #16 cla(.a(a), .b(b), .cin(cin), .result(result), .cout(cout));
endmodule
|
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire sys_clk_p,
input wire sys_clk_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// Clock and reset
wire sys_clk_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_ibufgds_inst(
.I(sys_clk_p),
.IB(sys_clk_n),
.O(sys_clk_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 450 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCM_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.100),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(sys_clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
wire ledu_int;
wire ledl_int;
wire ledd_int;
wire ledr_int;
wire ledc_int;
wire [7:0] led_int;
wire uart_rxd_int;
wire uart_txd_int;
wire uart_rts_int;
wire uart_cts_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_txd,
uart_rts}),
.out({uart_txd_int,
uart_rts_int})
);
assign ledu = ledu_int;
assign ledl = ledl_int;
assign ledd = ledd_int;
assign ledr = ledr_int;
assign ledc = ledc_int;
assign led = led_int;
assign uart_rxd = uart_rxd_int;
assign uart_cts = uart_cts_int;
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk_125mhz(clk_125mhz_int),
.rst_125mhz(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.ledu(ledu_int),
.ledl(ledl_int),
.ledd(ledd_int),
.ledr(ledr_int),
.ledc(ledc_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts_int)
);
endmodule
|
module sky130_fd_sc_hs__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
|
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
phy_reset_n,
phy_mdc,
phy_mdio,
phy_tx_clk,
phy_tx_ctrl,
phy_tx_data,
phy_rx_clk,
phy_rx_ctrl,
phy_rx_data,
fan_pwm,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
output phy_reset_n;
output phy_mdc;
inout phy_mdio;
output phy_tx_clk;
output phy_tx_ctrl;
output [ 3:0] phy_tx_data;
input phy_rx_clk;
input phy_rx_ctrl;
input [ 3:0] phy_rx_data;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [12:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
// internal registers
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg dac_dma_rd = 'd0;
reg adc_data_cnt = 'd0;
reg adc_dma_wr = 'd0;
reg [31:0] adc_dma_wdata = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
wire dac_valid_1;
wire dac_enable_1;
wire [63:0] dac_dma_rdata;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
// assignments
assign mgt_clk_sel = 2'd0;
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
// instantiations
ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_sw_led (
.dio_t (gpio_t[12:0]),
.dio_i (gpio_o[12:0]),
.dio_o (gpio_i[12:0]),
.dio_p (gpio_bd));
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
always @(posedge dac_clk) begin
dac_dma_rd <= dac_valid_0 & dac_enable_0;
dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
end
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt;
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
end
2'b01: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
end
default: begin
adc_dma_wr <= 1'b1;
adc_dma_wdata <= {adc_data_1, adc_data_0};
end
endcase
end
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio_lcd_tri_io (gpio_lcd),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),
.mb_intr_08 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_dma_rd (dac_dma_rd),
.dac_dma_rdata (dac_dma_rdata),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.ref_clk (ref_clk),
.mdio_io (phy_mdio),
.mdio_mdc (phy_mdc),
.phy_rst_n (phy_reset_n),
.rgmii_rd (phy_rx_data),
.rgmii_rx_ctl (phy_rx_ctrl),
.rgmii_rxc (phy_rx_clk),
.rgmii_td (phy_tx_data),
.rgmii_tx_ctl (phy_tx_ctrl),
.rgmii_txc (phy_tx_clk),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
|
module async_fifo (
wrclk, wrreset, rdclk, rdreset,
// write path
space_avail, wrenb, wrdata,
// read path
read_req, data_avail,
data_valid, data_out);
parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
parameter ASYNC_FIFO_FULLTHRESHOLD = 4; // full when only 4 words remain
input wrclk, wrreset;
input rdclk, rdreset;
// Write path...
output space_avail;
input wrenb;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
// Read path...
input read_req;
output data_avail, data_valid;
output [ASYNC_FIFO_MAXDATA:0] data_out;
wire [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr, stable_rdptr;
wire [ASYNC_FIFO_MAXINDEX:0] ram_wraddr, ram_rdaddr;
wire [ASYNC_FIFO_MAXDATA:0] ram_wrdata, ram_rddata;
//
// Instantiate RAM...
//
async_fifo_ram ram (
wrclk, rdclk,
ram_wrenb, ram_wraddr, ram_wrdata,
ram_rdenb, ram_rdaddr, ram_rddata);
defparam ram.ASYNC_FIFO_MAXINDEX = ASYNC_FIFO_MAXINDEX;
defparam ram.ASYNC_FIFO_MAXDATA = ASYNC_FIFO_MAXDATA;
//
// Instantiate write path...
//
async_fifo_wrpath wrpath (
wrclk, wrreset,
space_avail, wrenb, wrdata,
ram_wrenb, ram_wraddr, ram_wrdata,
stable_wrptr, stable_rdptr);
defparam wrpath.ASYNC_FIFO_MAXINDEX = ASYNC_FIFO_MAXINDEX;
defparam wrpath.ASYNC_FIFO_MAXDATA = ASYNC_FIFO_MAXDATA;
defparam wrpath.ASYNC_FIFO_FULLTHRESHOLD = ASYNC_FIFO_FULLTHRESHOLD;
//
// Instantiate read path...
//
async_fifo_rdpath rdpath (
rdclk, rdreset,
read_req, data_avail,
data_valid, data_out,
ram_rdenb, ram_rdaddr, ram_rddata,
stable_wrptr, stable_rdptr);
defparam rdpath.ASYNC_FIFO_MAXINDEX = ASYNC_FIFO_MAXINDEX;
defparam rdpath.ASYNC_FIFO_MAXDATA = ASYNC_FIFO_MAXDATA;
endmodule
|
module async_fifo_wrpath (
clk, reset,
space_avail, data_valid, wrdata,
ram_wrenb, ram_wraddr, ram_wrdata,
stable_wrptr, stable_rdptr);
parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
parameter ASYNC_FIFO_FULLTHRESHOLD = 4;
input clk, reset;
// FIFO interface...
output space_avail;
input data_valid;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
// RAM interface...
output ram_wrenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_wraddr;
output [ASYNC_FIFO_MAXDATA:0] ram_wrdata;
// Sync interface...
output [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
input [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;
localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"
//
// Registers...
//
reg [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr, next_stable_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg space_avail, next_space_avail;
wire [ASYNC_FIFO_MAXINDEX+1:0] wrptr_plus1 = wrptr+1'b1;
wire [ASYNC_FIFO_MAXINDEX+1:0] fifo_depth = wrptr-rdptr;
wire [ASYNC_FIFO_MAXINDEX+1:0] gray_rdptr;
full_synchronizer #(WIDTH) sync_gray_rdptr (clk, reset, stable_rdptr, gray_rdptr);
//
// RAM interface...
//
wire ram_wrenb = data_valid;
wire [ASYNC_FIFO_MAXINDEX:0] ram_wraddr = wrptr[ASYNC_FIFO_MAXINDEX:0];
wire [ASYNC_FIFO_MAXDATA:0] ram_wrdata = wrdata;
//
// Sample stable singals...
//
initial
begin
stable_wrptr = 0;
rdptr = 0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stable_wrptr = 0;
rdptr = 0;
end
else
begin
stable_wrptr = next_stable_wrptr;
rdptr = next_rdptr;
end
end
always @(*)
begin
#1;
next_stable_wrptr = bin2gray(next_wrptr);
next_rdptr = gray2bin(gray_rdptr);
end
//
// Control logic...
//
initial
begin
space_avail = 0;
wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
space_avail = 1'b1;
wrptr = 0;
end
else
begin
space_avail = next_space_avail;
wrptr = next_wrptr;
// synthesis translate_off
if (data_valid)
begin
#1;
if (fifo_depth >= (1<<(ASYNC_FIFO_MAXINDEX+1)))
begin
$display ("%t: FIFO OVERFLOW!",$realtime);
$finish;
end
end
// synthesis translate_on
end
end
always @(*)
begin
#1;
next_space_avail = fifo_depth<((1<<(ASYNC_FIFO_MAXINDEX+1))-ASYNC_FIFO_FULLTHRESHOLD);
next_wrptr = (data_valid && space_avail) ? wrptr_plus1 : wrptr;
end
endmodule
|
module async_fifo_rdpath (
clk, reset,
read_req, data_avail,
data_valid, data_out,
ram_rdenb, ram_rdaddr, ram_rddata,
stable_wrptr, stable_rdptr);
parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;
input clk, reset;
// FIFO interface...
input read_req;
output data_avail, data_valid;
output [ASYNC_FIFO_MAXDATA:0] data_out;
// RAM interface...
output ram_rdenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;
input [ASYNC_FIFO_MAXDATA:0] ram_rddata;
// Sync interface...
input [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
output [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;
localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"
//
// Registers...
//
reg [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr, next_stable_rdptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;
reg data_avail, next_data_avail;
reg data_valid, next_data_valid;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg [ASYNC_FIFO_MAXDATA:0] data_out, next_data_out;
wire ram_rdenb = data_avail;
reg [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;
wire [ASYNC_FIFO_MAXINDEX+1:0] rdptr_plus1 = rdptr+1'b1;
wire [ASYNC_FIFO_MAXINDEX+1:0] gray_wrptr;
full_synchronizer #(WIDTH) sync_gray_wrptr (clk, reset, stable_wrptr, gray_wrptr);
//
// Sample stable singals...
//
initial
begin
stable_rdptr = 0;
wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stable_rdptr = 0;
wrptr = 0;
end
else
begin
stable_rdptr = next_stable_rdptr;
wrptr = next_wrptr;
end
end
always @(*)
begin
#1;
next_stable_rdptr = bin2gray(rdptr);
next_wrptr = gray2bin(gray_wrptr);
end
//
// Control logic...
//
initial
begin
rdptr = 0;
data_avail = 1'b0;
data_valid = 1'b0;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
rdptr = 0;
data_avail = 1'b0;
data_valid = 1'b0;
end
else
begin
rdptr = next_rdptr;
data_avail = next_data_avail;
data_valid = next_data_valid;
end
end
always @ (posedge clk) data_out = next_data_out;
always @(*)
begin
#1;
next_rdptr = rdptr;
next_data_out = {(ASYNC_FIFO_MAXDATA+1){data_avail}} & ram_rddata;
next_data_valid = 1'b0;
if (read_req && data_avail)
begin
next_data_valid = 1'b1;
next_rdptr = rdptr_plus1;
end
next_data_avail = (next_wrptr != next_rdptr);
ram_rdaddr = next_rdptr[ASYNC_FIFO_MAXINDEX:0];
end
endmodule
|
module async_fifo_ram (wrclk, rdclk, wrenb, wrptr, wrdata, rdenb, rdptr, rddata);
parameter ASYNC_FIFO_MAXINDEX = 4;
parameter ASYNC_FIFO_MAXDATA = 31;
input wrclk, rdclk;
input wrenb, rdenb;
input [ASYNC_FIFO_MAXINDEX:0] wrptr, rdptr;
input [ASYNC_FIFO_MAXDATA:0] wrdata;
output [ASYNC_FIFO_MAXDATA:0] rddata;
wire #1 dly_wrenb = wrenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_wrptr = wrptr;
wire [ASYNC_FIFO_MAXDATA:0] #1 dly_wrdata = wrdata;
wire #1 dly_rdenb = rdenb;
wire [ASYNC_FIFO_MAXINDEX:0] #1 dly_rdptr = rdptr;
reg [ASYNC_FIFO_MAXDATA:0] mem[0:(1<<(ASYNC_FIFO_MAXINDEX+1))-1];
reg [ASYNC_FIFO_MAXINDEX:0] rdptr_reg;
assign rddata = mem[rdptr_reg];
always @ (posedge wrclk)
begin
if (dly_wrenb) mem[dly_wrptr] = dly_wrdata;
end
always @ (posedge rdclk)
begin
rdptr_reg = dly_rdptr;
end
endmodule
|
module sky130_fd_sc_hdll__o21a_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hdll__o21a_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
|
module sky130_fd_sc_ls__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, B1, C1, or0_out, D1);
buf buf0 (X , and0_out_X );
endmodule
|
module sky130_fd_sc_hs__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
|
module sky130_fd_sc_ls__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
|
module bcdto7segment_dataflow(
input [3:0] x,
output [3:0] an,
output [6:0] seg
);
assign #2 an = x;
assign #1 seg[6] = (x[2]&(~x[1])&(~x[0]))|((~x[3])&(~x[2])&(~x[1])&x[0]);
assign #1 seg[5] = (x[2]&(~x[1])&x[0])|(x[2]&x[1]&(~x[0]));
assign #1 seg[4] = (~x[3])&(~x[2])&x[1]&(~x[0]);
assign #1 seg[3] = (x[2]&(~x[1])&(~x[0]))|(x[2]&x[1]&x[0])|((~x[3])&(~x[2])&(~x[1])&x[0]);
assign #1 seg[2] = (x[2]&(~x[1]))|x[0];
assign #1 seg[1] = (x[1]&x[0])|((~x[3])&(~x[2])&x[0])|((~x[3])&(~x[2])&x[1]);
assign #1 seg[0] = ((~x[3])&(~x[2])&(~x[1]))|(x[2]&x[1]&x[0]);
endmodule
|
module video_scaler_mul_kbM_MulnS_1(clk, ce, a, b, p);
input clk;
input ce;
input[28 - 1 : 0] a;
input[20 - 1 : 0] b;
output[48 - 1 : 0] p;
reg signed [28 - 1 : 0] a_reg0;
reg signed [20 - 1 : 0] b_reg0;
wire signed [48 - 1 : 0] tmp_product;
reg signed [48 - 1 : 0] buff0;
reg signed [48 - 1 : 0] buff1;
reg signed [48 - 1 : 0] buff2;
assign p = buff2;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
end
end
endmodule
|
module video_scaler_mul_kbM(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
video_scaler_mul_kbM_MulnS_1 video_scaler_mul_kbM_MulnS_1_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
module sky130_fd_sc_lp__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
|
module arrmul (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
// Defining integers: integer [name_of_integer] = value;
integer sgn;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
/**
* Temporary reg(s) to contain the partial products during
* multiplication
*/
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
// ===============================================================
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
$display("reg_A",reg_A);
$display("reg_B",reg_B);
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16a3=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
// ======================================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
`w8: // aluwmuleu AND `w8
begin
p_pdt8a[8:15]=reg_A[0:7];
p_pdt8a[0:7]=8'd0;
for(sgn=7; sgn>=0; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-sgn));
end
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[16:23];
p_pdt8b[0:7]=8'd0;
for(sgn=23; sgn>=16; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[32:39];
p_pdt8c[0:7]=8'd0;
for(sgn=39; sgn>=32; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[48:55];
p_pdt8d[0:7]=8'd0;
for(sgn=55; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[64:71];
p_pdt8e[0:7]=8'd0;
for(sgn=71; sgn>=64; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[80:87];
p_pdt8f[0:7]=8'd0;
for(sgn=87; sgn>=80; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[96:103];
p_pdt8g[0:7]=8'd0;
for(sgn=103; sgn>=96; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[112:119];
p_pdt8h[0:7]=8'd0;
for(sgn=119; sgn>=112; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
result[112:127]=p_pdt[112:127];
end
`w16: // aluwmuleu AND `w16
begin
p_pdt16a[16:31]=reg_A[0:15];
p_pdt16a[0:15]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:31]=p_pdt[0:31]+(reg_A[0:15]<<(15-sgn));
end
end
result[0:31]=p_pdt[0:31];
p_pdt16b[16:31]=reg_A[32:47];
p_pdt16b[0:15]=8'd0;
for(sgn=47; sgn>=32; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:63]=p_pdt[32:63]+(reg_A[32:47]<<(15-(sgn%16)));
end
end
result[32:63]=p_pdt[32:63];
p_pdt16c[16:31]=reg_A[64:79];
p_pdt16c[0:15]=8'd0;
for(sgn=79; sgn>=64; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:95]=p_pdt[64:95]+(reg_A[64:79]<<(15-(sgn%16)));
end
end
result[64:95]=p_pdt[64:95];
p_pdt16d[16:31]=reg_A[96:111];
p_pdt16d[0:15]=8'd0;
for(sgn=111; sgn>=96; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:127]=p_pdt[96:127]+(reg_A[96:111]<<(15-(sgn%16)));
end
end
result[96:127]=p_pdt[96:127];
end
default: // aluwmuleu AND Default
begin
result=128'd0;
end
endcase
end
/**
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
*/
// ======================================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
`w8: // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
for(sgn=31; sgn>=24; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
for(sgn=39; sgn>=33; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
for(sgn=55; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
for(sgn=79; sgn>=72; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
for(sgn=95; sgn>=88; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
for(sgn=111; sgn>=104; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
for(sgn=127; sgn>=120; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
result[112:127]=p_pdt[112:127];
end
`w16: // aluwmulou AND `w16
begin
p_pdt16a[16:31]=reg_A[16:31];
p_pdt16a[0:15]=8'd0;
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:31]=p_pdt[0:31]+(reg_A[16:31]<<(15-(sgn%16)));
end
end
result[0:31]=p_pdt[0:31];
p_pdt16b[16:31]=reg_A[48:63];
p_pdt16b[0:15]=8'd0;
for(sgn=63; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:63]=p_pdt[32:63]+(reg_A[48:63]<<(15-(sgn%16)));
end
end
result[32:63]=p_pdt[32:63];
p_pdt16c[16:31]=reg_A[80:95];
p_pdt16c[0:15]=8'd0;
for(sgn=95; sgn>=80; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:95]=p_pdt[64:95]+(reg_A[80:95]<<(15-(sgn%16)));
end
end
result[64:95]=p_pdt[64:95];
p_pdt16d[16:31]=reg_A[112:127];
p_pdt16d[0:15]=8'd0;
for(sgn=127; sgn>=112; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:127]=p_pdt[96:127]+(reg_A[112:127]<<(15-(sgn%16)));
end
end
result[96:127]=p_pdt[96:127];
end
default: // aluwmulou AND Default
begin
result=128'd0;
end
endcase
end
/**
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
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* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
*/
// ======================================================
// Signed Multiplication - odd subfields
`aluwmulos:
begin
case(ctrl_ww)
`w8: // aluwmulos AND `w8
begin
// Process the 1st byte
if(reg_A[8]==0)
begin
p_pdt8a[8:15]=reg_A[8:15];
end
else
begin
p_pdt8a[8:15]=1+~reg_A[8:15];
end
p_pdt8b[0:7]=8'd0;
if(reg_B[8]==0)
begin
p_pdt8a2[8:15]=reg_B[8:15];
end
else
begin
p_pdt8a2[8:15]=1+~reg_B[8:15];
end
p_pdt8b2[0:7]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(p_pdt8a2[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
end
if(reg_A[8]^reg_B[8])
begin
result[0:15]=1+~p_pdt[0:15];
end
else
begin
result[0:15]=p_pdt[0:15];
end
// Process the 2nd byte
if(reg_A[24]==0)
begin
p_pdt8b[8:15]=reg_A[24:31];
end
else
begin
p_pdt8b[8:15]=1+~reg_A[24:31];
end
p_pdt8b[0:7]=8'd0;
if(reg_B[24]==0)
begin
p_pdt8b2[8:15]=reg_B[24:31];
end
else
begin
p_pdt8b2[8:15]=1+~reg_B[24:31];
end
p_pdt8b2[0:7]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(p_pdt8b2[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
if(reg_A[24]^reg_B[24])
begin
result[16:31]=1+~p_pdt[16:31];
end
else
begin
result[16:31]=p_pdt[16:31];
end
// Process the 3rd byte
// Convert operand A to a positive number
if(reg_A[40]==0)
begin
p_pdt8c[8:15]=reg_A[40:47];
end
else
begin
p_pdt8c[8:15]=1+~reg_A[40:47];
end
p_pdt8c[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[40]==0)
begin
p_pdt8c2[8:15]=reg_B[40:47];
end
else
begin
p_pdt8c2[8:15]=1+~reg_B[40:47];
end
p_pdt8c2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8c2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[40]^reg_B[40])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:47]=1+~p_pdt[32:47];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:47]=p_pdt[32:47];
end
// Process the 4th byte
// Convert operand A to a positive number
if(reg_A[56]==0)
begin
p_pdt8d[8:15]=reg_A[56:63];
end
else
begin
p_pdt8d[8:15]=1+~reg_A[56:63];
end
p_pdt8d[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[56]==0)
begin
p_pdt8d2[8:15]=reg_B[56:63];
end
else
begin
p_pdt8d2[8:15]=1+~reg_B[56:63];
end
p_pdt8d2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8d2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[56]^reg_B[56])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[48:63]=1+~p_pdt[48:63];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[48:63]=p_pdt[48:63];
end
// Process the 5th byte
// Convert operand A to a positive number
if(reg_A[72]==0)
begin
p_pdt8e[8:15]=reg_A[72:79];
end
else
begin
p_pdt8e[8:15]=1+~reg_A[72:79];
end
p_pdt8e[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[72]==0)
begin
p_pdt8e2[8:15]=reg_B[72:79];
end
else
begin
p_pdt8e2[8:15]=1+~reg_B[72:79];
end
p_pdt8e2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8e2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[72]^reg_B[72])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:79]=1+~p_pdt[64:79];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:79]=p_pdt[64:79];
end
// Process the 6th byte
// Convert operand A to a positive number
if(reg_A[88]==0)
begin
p_pdt8f[8:15]=reg_A[88:95];
end
else
begin
p_pdt8f[8:15]=1+~reg_A[88:95];
end
p_pdt8f[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[88]==0)
begin
p_pdt8f2[8:15]=reg_B[88:95];
end
else
begin
p_pdt8f2[8:15]=1+~reg_B[88:95];
end
p_pdt8f2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8f2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[88]^reg_B[88])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[80:95]=1+~p_pdt[80:95];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[80:95]=p_pdt[80:95];
end
// Process the 7th byte
// Convert operand A to a positive number
if(reg_A[104]==0)
begin
p_pdt8g[8:15]=reg_A[104:111];
end
else
begin
p_pdt8g[8:15]=1+~reg_A[104:111];
end
p_pdt8g[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[104]==0)
begin
p_pdt8g2[8:15]=reg_B[104:111];
end
else
begin
p_pdt8g2[8:15]=1+~reg_B[104:111];
end
p_pdt8g2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8g2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[104]^reg_B[104])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:111]=1+~p_pdt[96:111];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:111]=p_pdt[96:111];
end
// Process the 8th byte
// Convert operand A to a positive number
if(reg_A[120]==0)
begin
p_pdt8h[8:15]=reg_A[120:127];
end
else
begin
p_pdt8h[8:15]=1+~reg_A[120:127];
end
p_pdt8h[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[120]==0)
begin
p_pdt8h2[8:15]=reg_B[120:127];
end
else
begin
p_pdt8h2[8:15]=1+~reg_B[120:127];
end
p_pdt8h2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8h2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[120]^reg_B[120])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[112:127]=1+~p_pdt[112:127];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[112:127]=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
end
`w16: // aluwmulos AND `w16
begin
// Process the first pair of bytes
// Convert operand A to a positive number
if(reg_A[16]==0)
begin
p_pdt16a[16:31]=reg_A[16:31];
end
else
begin
p_pdt16a[16:31]=1+~reg_A[16:31];
end
p_pdt16a[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[16]==0)
begin
p_pdt16a2[16:31]=reg_B[16:31];
end
else
begin
p_pdt16a2[16:31]=1+~reg_B[16:31];
end
p_pdt16a2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16a2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[16]^reg_B[16])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[0:31]=1+~p_pdt[0:31];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[0:31]=p_pdt[0:31];
end
// Process the second pair of bytes
// Convert operand A to a positive number
if(reg_A[48]==0)
begin
p_pdt16b[16:31]=reg_A[48:63];
end
else
begin
p_pdt16b[16:31]=1+~reg_A[48:63];
end
p_pdt16b[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[48]==0)
begin
p_pdt16b2[16:31]=reg_B[48:63];
end
else
begin
p_pdt16b2[16:31]=1+~reg_B[48:63];
end
p_pdt16b2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16b2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[48]^reg_B[48])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:63]=1+~p_pdt[32:63];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:63]=p_pdt[32:63];
end
// Process the third pair of bytes
// Convert operand A to a positive number
if(reg_A[80]==0)
begin
p_pdt16c[16:31]=reg_A[80:95];
end
else
begin
p_pdt16c[16:31]=1+~reg_A[80:95];
end
p_pdt16c[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[80]==0)
begin
p_pdt16c2[16:31]=reg_B[80:95];
end
else
begin
p_pdt16c2[16:31]=1+~reg_B[80:95];
end
p_pdt16c2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16c2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[80]^reg_B[80])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:95]=1+~p_pdt[64:95];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:95]=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Convert operand A to a positive number
if(reg_A[112]==0)
begin
p_pdt16d[16:31]=reg_A[112:127];
end
else
begin
p_pdt16d[16:31]=1+~reg_A[112:127];
end
p_pdt16d[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[112]==0)
begin
p_pdt16d2[16:31]=reg_B[112:127];
end
else
begin
p_pdt16d2[16:31]=1+~reg_B[112:127];
end
p_pdt16d2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16d2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[112]^reg_B[112])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:127]=1+~p_pdt[96:127];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:127]=p_pdt[96:127];
end
end
default: // aluwmulos AND Default
begin
result=128'd0;
end
endcase
end
// ======================================================
// Signed Multiplication - even subfields
`aluwmules:
begin
case(ctrl_ww)
`w8: // aluwmules AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[0:7];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[0:7];
if(reg_B[0]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[0:7];
end
else
begin
p_pdt8a2[8:15]=reg_B[0:7];
end
end
else
begin
p_pdt8a[8:15]=reg_A[0:7];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]=1+~p_pdt[0:15];
end
else
begin
result[0:15]=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[16:23];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[16:23];
if(reg_B[16]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[16:23];
end
else
begin
p_pdt8b2[8:15]=reg_B[16:23];
end
end
else
begin
p_pdt8b[8:15]=reg_A[16:23];
end
p_pdt8b[0:7]=8'd0;
$display("p_pdt8b[0:15]",p_pdt8b[0:15]);
$display("p_pdt8b2[0:15]",p_pdt8b2[0:15]);
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
$display("p_pdt[16:31]",p_pdt[16:31]);
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
$display("MINUSp_pdt[16:31]",p_pdt[16:31]);
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
$display("ADDp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
$display("ZEROp_pdt[16:31]",p_pdt[16:31]);
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]=1+~p_pdt[16:31];
$display("INVp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
result[16:31]=p_pdt[16:31];
$display("RESp_pdt[16:31]",p_pdt[16:31]);
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[32:39];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[32:39];
if(reg_B[32]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[32:39];
end
else
begin
p_pdt8c2[8:15]=reg_B[32:39];
end
end
else
begin
p_pdt8c[8:15]=reg_A[32:39];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]=1+~p_pdt[32:47];
end
else
begin
result[32:47]=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[48:55];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[48:55];
if(reg_B[48]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[48:55];
end
else
begin
p_pdt8d2[8:15]=reg_B[48:55];
end
end
else
begin
p_pdt8d[8:15]=reg_A[48:55];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]=1+~p_pdt[48:63];
end
else
begin
result[48:63]=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[64:71];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[64:71];
if(reg_B[64]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[64:71];
end
else
begin
p_pdt8e2[8:15]=reg_B[64:71];
end
end
else
begin
p_pdt8e[8:15]=reg_A[64:71];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]=1+~p_pdt[64:79];
end
else
begin
result[64:79]=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[80:87];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[80:87];
if(reg_B[80]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[80:87];
end
else
begin
p_pdt8f2[8:15]=reg_B[80:87];
end
end
else
begin
p_pdt8f[8:15]=reg_A[80:87];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]=1+~p_pdt[80:95];
end
else
begin
result[80:95]=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[96:103];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[96:103];
if(reg_B[96]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[96:103];
end
else
begin
p_pdt8g2[8:15]=reg_B[96:103];
end
end
else
begin
p_pdt8g[8:15]=reg_A[96:103];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]=1+~p_pdt[96:111];
end
else
begin
result[96:111]=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[112:119];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[112:119];
if(reg_B[112]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[112:119];
end
else
begin
p_pdt8h2[8:15]=reg_B[112:119];
end
end
else
begin
p_pdt8h[8:15]=reg_A[112:119];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]=1+~p_pdt[112:127];
end
else
begin
result[112:127]=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
/*
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
*/
end
`w16: // aluwmules AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[0:15];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[0:15];
if(reg_B[0]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[0:15];
end
else
begin
p_pdt16a2[16:31]=reg_B[0:15];
end
end
else
begin
p_pdt16a[16:31]=reg_A[0:15];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]=1+~p_pdt[0:31];
end
else
begin
result[0:31]=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[32:47];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[32:47];
if(reg_B[32]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[32:47];
end
else
begin
p_pdt16b2[16:31]=reg_B[32:47];
end
end
else
begin
p_pdt16b[16:31]=reg_A[0:15];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]=1+~p_pdt[32:63];
end
else
begin
result[32:63]=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[64:79];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[64:79];
if(reg_B[64]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[64:79];
end
else
begin
p_pdt16c2[16:31]=reg_B[64:79];
end
end
else
begin
p_pdt16c[16:31]=reg_A[64:79];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]=1+~p_pdt[64:95];
end
else
begin
result[64:95]=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[96:111];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[96:111];
if(reg_B[96]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[96:111];
end
else
begin
p_pdt16d2[16:31]=reg_B[96:111];
end
end
else
begin
p_pdt16d[16:31]=reg_A[96:111];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]=1+~p_pdt[96:127];
end
else
begin
result[96:127]=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result=128'd0;
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result=128'd0;
end
endcase
end
endmodule
|
module mc_crt
(
input mclock,
input reset_n,
input pixclk,
input crt_clock,
input crt_gnt,
input crt_req,
input [20:0] crt_org,
input [4:0] crt_page,
input [11:0] crt_ptch,
input [9:0] crt_x,
input [11:0] crt_y,
output reg crt_ready,
output reg crt_arb_req,
output reg [4:0] crt_arb_page,
output reg [20:0] crt_arb_addr
);
reg capt_req;
reg [20:0] capt_org;
reg [11:0] capt_ptch;
reg [9:0] capt_x;
reg [11:0] capt_y;
reg [4:0] capt_page;
reg req_sync_m1, req_sync_1, req_sync_2, req_sync_3;
reg gnt_sync_1, gnt_sync_2, gnt_sync_3;
reg [20:0] pmult, int_add;
reg final_grant; // patch signal, need to do real fix later
reg [1:0] requests;
reg hold_req;
wire req_toggle;
// Request capture logic and grant sync logic runs in crt_clock domain
// Might we be able to get rid of that first set of capture registers? We
// could if we went to more of a request/grant interface where he keeps the
// data around until we grant him. His requests are so long that having a
// bunch of little requests in a row is not a problem.
always @ (posedge pixclk or negedge reset_n) begin
if(!reset_n) begin
crt_ready <= 1'b1;
capt_req <= 1'b0;
capt_org <= 21'h0;
capt_ptch <= 12'b0;
capt_x <= 10'b0;
capt_y <= 12'b0;
capt_page <= 5'b0;
gnt_sync_1<= 1'b0;
gnt_sync_2<= 1'b0;
gnt_sync_3<= 1'b0;
end else if (crt_clock) begin
if (crt_req) begin
capt_req <= ~capt_req;
capt_org <= crt_org;
capt_ptch <= crt_ptch;
capt_x <= crt_x;
capt_y <= crt_y;
// crt_page==0 is 32 pages, else just # pages
capt_page <= crt_page - 5'b1;
crt_ready <= 1'b0;
end // if (crt_req==1'b1)
gnt_sync_1 <= final_grant;
gnt_sync_2 <= gnt_sync_1;
gnt_sync_3 <= gnt_sync_2;
if(gnt_sync_2 ^ gnt_sync_3) crt_ready <= 1'b1;
end // else: !if(!reset_n)
end // always @ (posedge crt_clock or negedge reset_n)
assign req_toggle = req_sync_2 ^ req_sync_3;
// Request synchronizers, translation logic and registers, and request FSM
// runs in mclock domain.
always @ (posedge mclock or negedge reset_n) begin
if(!reset_n) begin
// reset_n stuff
crt_arb_req <= 1'b0;
final_grant <= 1'b0; // this is now a toggle signal, I should rename it
requests <= 2'b0;
hold_req <= 1'b0;
pmult <= 21'b0;
int_add <= 21'b0;
req_sync_m1 <= 1'b0;
req_sync_1 <= 1'b0;
req_sync_2 <= 1'b0;
req_sync_3 <= 1'b0;
crt_arb_req <= 1'b0;
crt_arb_page <= 5'b0;
crt_arb_addr <= 21'b0;
end else begin
// Keep track of # of requests
case ({crt_gnt, req_toggle})
2'b01: requests <= requests + 2'b1;
2'b10: requests <= requests - 2'b1;
endcase
// Cycle 1, calculate 1st half of pitch
pmult <= (capt_y * {{4{capt_ptch[11]}}, capt_ptch});
// pmult <= (capt_y << 8);
int_add <= (capt_org + {{11{capt_x[9]}}, capt_x});
// Synchronize crt requests
req_sync_m1 <= capt_req; // this is a toggle signal, I should rename it
req_sync_1 <= req_sync_m1;
req_sync_2 <= req_sync_1;
req_sync_3 <= req_sync_2;
// When we get a request, we translate address, etc
// we better not get another request until this one ends, thus the sync
// logic, ready signal
if (hold_req && ~&requests[1]) begin
hold_req <= 0;
crt_arb_req <= 1'b1;
crt_arb_page <= capt_page;
crt_arb_addr <= pmult + int_add;
end else if(req_toggle && ~&requests[1]) begin
crt_arb_req <= 1'b1;
crt_arb_page <= capt_page;
crt_arb_addr <= pmult + int_add;
end else if(req_toggle && (&requests[1])) begin
hold_req <= 1;
end // if (req_sync_2==1'b1 && req_sync_3==1'b0)
if(crt_gnt) begin
crt_arb_req <= 1'b0;
final_grant <= ~final_grant;
end // if (crt_gnt==1'b1)
end // else: !if(!reset_n)
end // always @ (posedge mclock or negedge reset_n)
endmodule
|
module wb_intercon
(input wb_clk_i,
input wb_rst_i,
input [31:0] wb_iwmb_adr_i,
input [31:0] wb_iwmb_dat_i,
input [3:0] wb_iwmb_sel_i,
input wb_iwmb_we_i,
input wb_iwmb_cyc_i,
input wb_iwmb_stb_i,
input [2:0] wb_iwmb_cti_i,
input [1:0] wb_iwmb_bte_i,
output [31:0] wb_iwmb_dat_o,
output wb_iwmb_ack_o,
output wb_iwmb_err_o,
output wb_iwmb_rty_o,
input [31:0] wb_dwmb_adr_i,
input [31:0] wb_dwmb_dat_i,
input [3:0] wb_dwmb_sel_i,
input wb_dwmb_we_i,
input wb_dwmb_cyc_i,
input wb_dwmb_stb_i,
input [2:0] wb_dwmb_cti_i,
input [1:0] wb_dwmb_bte_i,
output [31:0] wb_dwmb_dat_o,
output wb_dwmb_ack_o,
output wb_dwmb_err_o,
output wb_dwmb_rty_o,
output [31:0] wb_uart_adr_o,
output [31:0] wb_uart_dat_o,
output [3:0] wb_uart_sel_o,
output wb_uart_we_o,
output wb_uart_cyc_o,
output wb_uart_stb_o,
output [2:0] wb_uart_cti_o,
output [1:0] wb_uart_bte_o,
input [31:0] wb_uart_dat_i,
input wb_uart_ack_i,
input wb_uart_err_i,
input wb_uart_rty_i,
output [31:0] wb_ram_adr_o,
output [31:0] wb_ram_dat_o,
output [3:0] wb_ram_sel_o,
output wb_ram_we_o,
output wb_ram_cyc_o,
output wb_ram_stb_o,
output [2:0] wb_ram_cti_o,
output [1:0] wb_ram_bte_o,
input [31:0] wb_ram_dat_i,
input wb_ram_ack_i,
input wb_ram_err_i,
input wb_ram_rty_i,
output [31:0] wb_rom_adr_o,
output [31:0] wb_rom_dat_o,
output [3:0] wb_rom_sel_o,
output wb_rom_we_o,
output wb_rom_cyc_o,
output wb_rom_stb_o,
output [2:0] wb_rom_cti_o,
output [1:0] wb_rom_bte_o,
input [31:0] wb_rom_dat_i,
input wb_rom_ack_i,
input wb_rom_err_i,
input wb_rom_rty_i);
wire [31:0] wb_m2s_iwmb_uart_adr;
wire [31:0] wb_m2s_iwmb_uart_dat;
wire [3:0] wb_m2s_iwmb_uart_sel;
wire wb_m2s_iwmb_uart_we;
wire wb_m2s_iwmb_uart_cyc;
wire wb_m2s_iwmb_uart_stb;
wire [2:0] wb_m2s_iwmb_uart_cti;
wire [1:0] wb_m2s_iwmb_uart_bte;
wire [31:0] wb_s2m_iwmb_uart_dat;
wire wb_s2m_iwmb_uart_ack;
wire wb_s2m_iwmb_uart_err;
wire wb_s2m_iwmb_uart_rty;
wire [31:0] wb_m2s_iwmb_ram_adr;
wire [31:0] wb_m2s_iwmb_ram_dat;
wire [3:0] wb_m2s_iwmb_ram_sel;
wire wb_m2s_iwmb_ram_we;
wire wb_m2s_iwmb_ram_cyc;
wire wb_m2s_iwmb_ram_stb;
wire [2:0] wb_m2s_iwmb_ram_cti;
wire [1:0] wb_m2s_iwmb_ram_bte;
wire [31:0] wb_s2m_iwmb_ram_dat;
wire wb_s2m_iwmb_ram_ack;
wire wb_s2m_iwmb_ram_err;
wire wb_s2m_iwmb_ram_rty;
wire [31:0] wb_m2s_iwmb_rom_adr;
wire [31:0] wb_m2s_iwmb_rom_dat;
wire [3:0] wb_m2s_iwmb_rom_sel;
wire wb_m2s_iwmb_rom_we;
wire wb_m2s_iwmb_rom_cyc;
wire wb_m2s_iwmb_rom_stb;
wire [2:0] wb_m2s_iwmb_rom_cti;
wire [1:0] wb_m2s_iwmb_rom_bte;
wire [31:0] wb_s2m_iwmb_rom_dat;
wire wb_s2m_iwmb_rom_ack;
wire wb_s2m_iwmb_rom_err;
wire wb_s2m_iwmb_rom_rty;
wire [31:0] wb_m2s_dwmb_uart_adr;
wire [31:0] wb_m2s_dwmb_uart_dat;
wire [3:0] wb_m2s_dwmb_uart_sel;
wire wb_m2s_dwmb_uart_we;
wire wb_m2s_dwmb_uart_cyc;
wire wb_m2s_dwmb_uart_stb;
wire [2:0] wb_m2s_dwmb_uart_cti;
wire [1:0] wb_m2s_dwmb_uart_bte;
wire [31:0] wb_s2m_dwmb_uart_dat;
wire wb_s2m_dwmb_uart_ack;
wire wb_s2m_dwmb_uart_err;
wire wb_s2m_dwmb_uart_rty;
wire [31:0] wb_m2s_dwmb_ram_adr;
wire [31:0] wb_m2s_dwmb_ram_dat;
wire [3:0] wb_m2s_dwmb_ram_sel;
wire wb_m2s_dwmb_ram_we;
wire wb_m2s_dwmb_ram_cyc;
wire wb_m2s_dwmb_ram_stb;
wire [2:0] wb_m2s_dwmb_ram_cti;
wire [1:0] wb_m2s_dwmb_ram_bte;
wire [31:0] wb_s2m_dwmb_ram_dat;
wire wb_s2m_dwmb_ram_ack;
wire wb_s2m_dwmb_ram_err;
wire wb_s2m_dwmb_ram_rty;
wire [31:0] wb_m2s_dwmb_rom_adr;
wire [31:0] wb_m2s_dwmb_rom_dat;
wire [3:0] wb_m2s_dwmb_rom_sel;
wire wb_m2s_dwmb_rom_we;
wire wb_m2s_dwmb_rom_cyc;
wire wb_m2s_dwmb_rom_stb;
wire [2:0] wb_m2s_dwmb_rom_cti;
wire [1:0] wb_m2s_dwmb_rom_bte;
wire [31:0] wb_s2m_dwmb_rom_dat;
wire wb_s2m_dwmb_rom_ack;
wire wb_s2m_dwmb_rom_err;
wire wb_s2m_dwmb_rom_rty;
wb_mux
#(.num_slaves (3),
.MATCH_ADDR ({32'h40000000, 32'h20000000, 32'h00000000}),
.MATCH_MASK ({32'hffffffe0, 32'hffff8000, 32'hffff8000}))
wb_mux_iwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_iwmb_adr_i),
.wbm_dat_i (wb_iwmb_dat_i),
.wbm_sel_i (wb_iwmb_sel_i),
.wbm_we_i (wb_iwmb_we_i),
.wbm_cyc_i (wb_iwmb_cyc_i),
.wbm_stb_i (wb_iwmb_stb_i),
.wbm_cti_i (wb_iwmb_cti_i),
.wbm_bte_i (wb_iwmb_bte_i),
.wbm_dat_o (wb_iwmb_dat_o),
.wbm_ack_o (wb_iwmb_ack_o),
.wbm_err_o (wb_iwmb_err_o),
.wbm_rty_o (wb_iwmb_rty_o),
.wbs_adr_o ({wb_m2s_iwmb_uart_adr, wb_m2s_iwmb_ram_adr, wb_m2s_iwmb_rom_adr}),
.wbs_dat_o ({wb_m2s_iwmb_uart_dat, wb_m2s_iwmb_ram_dat, wb_m2s_iwmb_rom_dat}),
.wbs_sel_o ({wb_m2s_iwmb_uart_sel, wb_m2s_iwmb_ram_sel, wb_m2s_iwmb_rom_sel}),
.wbs_we_o ({wb_m2s_iwmb_uart_we, wb_m2s_iwmb_ram_we, wb_m2s_iwmb_rom_we}),
.wbs_cyc_o ({wb_m2s_iwmb_uart_cyc, wb_m2s_iwmb_ram_cyc, wb_m2s_iwmb_rom_cyc}),
.wbs_stb_o ({wb_m2s_iwmb_uart_stb, wb_m2s_iwmb_ram_stb, wb_m2s_iwmb_rom_stb}),
.wbs_cti_o ({wb_m2s_iwmb_uart_cti, wb_m2s_iwmb_ram_cti, wb_m2s_iwmb_rom_cti}),
.wbs_bte_o ({wb_m2s_iwmb_uart_bte, wb_m2s_iwmb_ram_bte, wb_m2s_iwmb_rom_bte}),
.wbs_dat_i ({wb_s2m_iwmb_uart_dat, wb_s2m_iwmb_ram_dat, wb_s2m_iwmb_rom_dat}),
.wbs_ack_i ({wb_s2m_iwmb_uart_ack, wb_s2m_iwmb_ram_ack, wb_s2m_iwmb_rom_ack}),
.wbs_err_i ({wb_s2m_iwmb_uart_err, wb_s2m_iwmb_ram_err, wb_s2m_iwmb_rom_err}),
.wbs_rty_i ({wb_s2m_iwmb_uart_rty, wb_s2m_iwmb_ram_rty, wb_s2m_iwmb_rom_rty}));
wb_mux
#(.num_slaves (3),
.MATCH_ADDR ({32'h40000000, 32'h20000000, 32'h00000000}),
.MATCH_MASK ({32'hffffffe0, 32'hffff8000, 32'hffff8000}))
wb_mux_dwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_dwmb_adr_i),
.wbm_dat_i (wb_dwmb_dat_i),
.wbm_sel_i (wb_dwmb_sel_i),
.wbm_we_i (wb_dwmb_we_i),
.wbm_cyc_i (wb_dwmb_cyc_i),
.wbm_stb_i (wb_dwmb_stb_i),
.wbm_cti_i (wb_dwmb_cti_i),
.wbm_bte_i (wb_dwmb_bte_i),
.wbm_dat_o (wb_dwmb_dat_o),
.wbm_ack_o (wb_dwmb_ack_o),
.wbm_err_o (wb_dwmb_err_o),
.wbm_rty_o (wb_dwmb_rty_o),
.wbs_adr_o ({wb_m2s_dwmb_uart_adr, wb_m2s_dwmb_ram_adr, wb_m2s_dwmb_rom_adr}),
.wbs_dat_o ({wb_m2s_dwmb_uart_dat, wb_m2s_dwmb_ram_dat, wb_m2s_dwmb_rom_dat}),
.wbs_sel_o ({wb_m2s_dwmb_uart_sel, wb_m2s_dwmb_ram_sel, wb_m2s_dwmb_rom_sel}),
.wbs_we_o ({wb_m2s_dwmb_uart_we, wb_m2s_dwmb_ram_we, wb_m2s_dwmb_rom_we}),
.wbs_cyc_o ({wb_m2s_dwmb_uart_cyc, wb_m2s_dwmb_ram_cyc, wb_m2s_dwmb_rom_cyc}),
.wbs_stb_o ({wb_m2s_dwmb_uart_stb, wb_m2s_dwmb_ram_stb, wb_m2s_dwmb_rom_stb}),
.wbs_cti_o ({wb_m2s_dwmb_uart_cti, wb_m2s_dwmb_ram_cti, wb_m2s_dwmb_rom_cti}),
.wbs_bte_o ({wb_m2s_dwmb_uart_bte, wb_m2s_dwmb_ram_bte, wb_m2s_dwmb_rom_bte}),
.wbs_dat_i ({wb_s2m_dwmb_uart_dat, wb_s2m_dwmb_ram_dat, wb_s2m_dwmb_rom_dat}),
.wbs_ack_i ({wb_s2m_dwmb_uart_ack, wb_s2m_dwmb_ram_ack, wb_s2m_dwmb_rom_ack}),
.wbs_err_i ({wb_s2m_dwmb_uart_err, wb_s2m_dwmb_ram_err, wb_s2m_dwmb_rom_err}),
.wbs_rty_i ({wb_s2m_dwmb_uart_rty, wb_s2m_dwmb_ram_rty, wb_s2m_dwmb_rom_rty}));
wb_arbiter
#(.num_masters (2))
wb_arbiter_uart
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_uart_adr, wb_m2s_dwmb_uart_adr}),
.wbm_dat_i ({wb_m2s_iwmb_uart_dat, wb_m2s_dwmb_uart_dat}),
.wbm_sel_i ({wb_m2s_iwmb_uart_sel, wb_m2s_dwmb_uart_sel}),
.wbm_we_i ({wb_m2s_iwmb_uart_we, wb_m2s_dwmb_uart_we}),
.wbm_cyc_i ({wb_m2s_iwmb_uart_cyc, wb_m2s_dwmb_uart_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_uart_stb, wb_m2s_dwmb_uart_stb}),
.wbm_cti_i ({wb_m2s_iwmb_uart_cti, wb_m2s_dwmb_uart_cti}),
.wbm_bte_i ({wb_m2s_iwmb_uart_bte, wb_m2s_dwmb_uart_bte}),
.wbm_dat_o ({wb_s2m_iwmb_uart_dat, wb_s2m_dwmb_uart_dat}),
.wbm_ack_o ({wb_s2m_iwmb_uart_ack, wb_s2m_dwmb_uart_ack}),
.wbm_err_o ({wb_s2m_iwmb_uart_err, wb_s2m_dwmb_uart_err}),
.wbm_rty_o ({wb_s2m_iwmb_uart_rty, wb_s2m_dwmb_uart_rty}),
.wbs_adr_o (wb_uart_adr_o),
.wbs_dat_o (wb_uart_dat_o),
.wbs_sel_o (wb_uart_sel_o),
.wbs_we_o (wb_uart_we_o),
.wbs_cyc_o (wb_uart_cyc_o),
.wbs_stb_o (wb_uart_stb_o),
.wbs_cti_o (wb_uart_cti_o),
.wbs_bte_o (wb_uart_bte_o),
.wbs_dat_i (wb_uart_dat_i),
.wbs_ack_i (wb_uart_ack_i),
.wbs_err_i (wb_uart_err_i),
.wbs_rty_i (wb_uart_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_ram
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_ram_adr, wb_m2s_dwmb_ram_adr}),
.wbm_dat_i ({wb_m2s_iwmb_ram_dat, wb_m2s_dwmb_ram_dat}),
.wbm_sel_i ({wb_m2s_iwmb_ram_sel, wb_m2s_dwmb_ram_sel}),
.wbm_we_i ({wb_m2s_iwmb_ram_we, wb_m2s_dwmb_ram_we}),
.wbm_cyc_i ({wb_m2s_iwmb_ram_cyc, wb_m2s_dwmb_ram_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_ram_stb, wb_m2s_dwmb_ram_stb}),
.wbm_cti_i ({wb_m2s_iwmb_ram_cti, wb_m2s_dwmb_ram_cti}),
.wbm_bte_i ({wb_m2s_iwmb_ram_bte, wb_m2s_dwmb_ram_bte}),
.wbm_dat_o ({wb_s2m_iwmb_ram_dat, wb_s2m_dwmb_ram_dat}),
.wbm_ack_o ({wb_s2m_iwmb_ram_ack, wb_s2m_dwmb_ram_ack}),
.wbm_err_o ({wb_s2m_iwmb_ram_err, wb_s2m_dwmb_ram_err}),
.wbm_rty_o ({wb_s2m_iwmb_ram_rty, wb_s2m_dwmb_ram_rty}),
.wbs_adr_o (wb_ram_adr_o),
.wbs_dat_o (wb_ram_dat_o),
.wbs_sel_o (wb_ram_sel_o),
.wbs_we_o (wb_ram_we_o),
.wbs_cyc_o (wb_ram_cyc_o),
.wbs_stb_o (wb_ram_stb_o),
.wbs_cti_o (wb_ram_cti_o),
.wbs_bte_o (wb_ram_bte_o),
.wbs_dat_i (wb_ram_dat_i),
.wbs_ack_i (wb_ram_ack_i),
.wbs_err_i (wb_ram_err_i),
.wbs_rty_i (wb_ram_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_rom
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_rom_adr, wb_m2s_dwmb_rom_adr}),
.wbm_dat_i ({wb_m2s_iwmb_rom_dat, wb_m2s_dwmb_rom_dat}),
.wbm_sel_i ({wb_m2s_iwmb_rom_sel, wb_m2s_dwmb_rom_sel}),
.wbm_we_i ({wb_m2s_iwmb_rom_we, wb_m2s_dwmb_rom_we}),
.wbm_cyc_i ({wb_m2s_iwmb_rom_cyc, wb_m2s_dwmb_rom_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_rom_stb, wb_m2s_dwmb_rom_stb}),
.wbm_cti_i ({wb_m2s_iwmb_rom_cti, wb_m2s_dwmb_rom_cti}),
.wbm_bte_i ({wb_m2s_iwmb_rom_bte, wb_m2s_dwmb_rom_bte}),
.wbm_dat_o ({wb_s2m_iwmb_rom_dat, wb_s2m_dwmb_rom_dat}),
.wbm_ack_o ({wb_s2m_iwmb_rom_ack, wb_s2m_dwmb_rom_ack}),
.wbm_err_o ({wb_s2m_iwmb_rom_err, wb_s2m_dwmb_rom_err}),
.wbm_rty_o ({wb_s2m_iwmb_rom_rty, wb_s2m_dwmb_rom_rty}),
.wbs_adr_o (wb_rom_adr_o),
.wbs_dat_o (wb_rom_dat_o),
.wbs_sel_o (wb_rom_sel_o),
.wbs_we_o (wb_rom_we_o),
.wbs_cyc_o (wb_rom_cyc_o),
.wbs_stb_o (wb_rom_stb_o),
.wbs_cti_o (wb_rom_cti_o),
.wbs_bte_o (wb_rom_bte_o),
.wbs_dat_i (wb_rom_dat_i),
.wbs_ack_i (wb_rom_ack_i),
.wbs_err_i (wb_rom_err_i),
.wbs_rty_i (wb_rom_rty_i));
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
|
module Mem_I_D (
//cpu_read_write
//wb_input
dat_i,
adr_i,
we_i,
stb_i,
sel_i,
//wb_output
dat_o,
ack_o,
clk,
Signext
//W_En,
//Addr,
//D_In,
//D_Out
);
//cpu_read_write
input wire [31: 0] dat_i;
input wire [31: 0] adr_i;
input wire we_i;
input wire stb_i;
output reg [31: 0] dat_o;
output ack_o;
input clk;
input wire Signext;
input wire [3: 0] sel_i;
wire [1:0] byte_offset;
wire [12:0] ram_addr;
wire W_En;
wire [ 3: 0] W_sel;
wire [ 3: 0] wea;
assign ram_addr = adr_i[14:2];
assign byte_offset = adr_i[1:0];
// (* bram_map="yes" *)
// reg [31: 0] RAM[8191: 0];
wire [31: 0] tmp;
reg [31: 0] dina = 0;
reg first_rd = 0;
// initial begin
// $readmemb("../Coe/test_lh.coe",RAM);
// end
assign ack_o = stb_i;
assign W_En = stb_i & ack_o & we_i;
assign R_En = stb_i & ack_o & ~we_i ;
assign W_sel = sel_i << byte_offset;
//assign wea = {W_sel[0], W_sel[1], W_sel[2], W_sel[3]}&{4{W_En}};
assign wea = W_sel&{4{W_En}};
//wire mem_wr;
//assign mem_wr = stb_i && ack_o;
always @(*) begin
case({byte_offset,sel_i})
6'b001111:begin
dina <= dat_i;
dat_o <= tmp;
end
6'b000011:begin
//dina <= {dat_i[15:0], 16'h0};
//dat_o <= Signext?{16'h0, tmp[31:16]}:{{16{tmp[31]}}, tmp[31:16]};
dina <= {16'h0, dat_i[15:0]};
dat_o <= Signext?{16'h0, tmp[15:0]}:{{16{tmp[15]}}, tmp[15:0]};
end
6'b100011:begin
//dina <= {16'h0, dat_i[15:0]};
//dat_o <= Signext?{16'h0, tmp[15:0]}:{{16{tmp[15]}}, tmp[15:0]};
dina <= {dat_i[15:0], 16'h0};
dat_o <= Signext?{16'h0, tmp[31:16]}:{{16{tmp[31]}}, tmp[31:16]};
end
default:begin
dina <= dat_i;
dat_o <= tmp;
end
endcase
end
// always @(posedge clk) begin
// //if(W_En) begin //write
// //case({byte_offset,sel_i})
// //6'b001111: dina <= dat_i;//tmpReg2 <= dat_i; //sw
// //6'b000011: dina = {16'h0,dat_i};//tmpReg2 <= {dat_i[15:0], tmpReg[15:0]}; //sh byte_offset=0
// //6'b100011: dina = {dat_i,16'h0};//tmpReg2 <= {tmpReg[31:16], dat_i[15:0]}; //sh byte_offset=2
// //6'b000011: dina <= {dat_i[15:0],16'h0};//tmpReg2 <= {dat_i[15:0], tmpReg[15:0]}; //sh byte_offset=0
// //6'b000011: dina <= {dat_i[15:0], tmp[15:0]};
// //6'b100011: dina <= {16'h0,dat_i[15:0]};//tmpReg2 <= {tmpReg[31:16], dat_i[15:0]}; //sh byte_offset=2
// //6'b100011: dina <= {tmp[31:16], dat_i[15:0]};
// //endcase
// //RAM[ram_addr] <= tmpReg2;
// //end
// if(R_En) begin //read
// //dat_o = tmpReg;
//// case({byte_offset,sel_i})
//// 6'b001111: dat_o <= tmp; //lw
//// 6'b000011: dat_o <= Signext?{16'h0, tmp[31:16]}:{{16{tmp[31]}}, tmp[31:16]}; //lh & lhu byte_offset=0
//// 6'b100011: dat_o <= Signext?{16'h0, tmp[15:0]}:{{16{tmp[15]}}, tmp[15:0]}; //lh & lhu byte_offset=2
// //6'b000011: dat_o <= Signext?{16'h0, tmp[15:0]}:{{16{tmp[15]}}, tmp[15:0]}; //lh & lhu byte_offset=0
// //6'b100011: dat_o <= Signext?{16'h0, tmp[31:16]}:{{16{tmp[31]}}, tmp[31:16]}; //lh & lhu byte_offset=2
// //default: dat_o <= 32'hffff_ffff;
// //endcase
// first_rd = 1;
// end
// else first_rd = 0;
// end
Mem mem (
.clka(clk), // input clka
.wea(wea), // input [3 : 0] wea
.addra(adr_i), // input [31 : 0] addra
.dina(dina), // input [31 : 0] dina
.douta(tmp) // output [31 : 0] douta
);
/*
always @(posedge clk ) begin
if ( W_En ) begin
RAM[Addr] <= D_In;
end
else D_Out <= RAM[Addr];
end*/
endmodule
|
module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
|
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B_N = 1'b1;
#180 C = 1'b1;
#200 D = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B_N = 1'b0;
#300 C = 1'b0;
#320 D = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D = 1'b1;
#440 C = 1'b1;
#460 B_N = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D = 1'bx;
#560 C = 1'bx;
#580 B_N = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_hs__nand4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
|
module aes_encipher_block(
input wire clk,
input wire reset_n,
input wire next,
input wire keylen,
output wire [3 : 0] round,
input wire [127 : 0] round_key,
output wire [31 : 0] sboxw,
input wire [31 : 0] new_sboxw,
input wire [127 : 0] block,
output wire [127 : 0] new_block,
output wire ready
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
localparam NO_UPDATE = 3'h0;
localparam INIT_UPDATE = 3'h1;
localparam SBOX_UPDATE = 3'h2;
localparam MAIN_UPDATE = 3'h3;
localparam FINAL_UPDATE = 3'h4;
localparam CTRL_IDLE = 2'h0;
localparam CTRL_INIT = 2'h1;
localparam CTRL_SBOX = 2'h2;
localparam CTRL_MAIN = 2'h3;
//----------------------------------------------------------------
// Round functions with sub functions.
//----------------------------------------------------------------
function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction // gm2
function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction // gm3
function [31 : 0] mixw(input [31 : 0] w);
reg [7 : 0] b0, b1, b2, b3;
reg [7 : 0] mb0, mb1, mb2, mb3;
begin
b0 = w[31 : 24];
b1 = w[23 : 16];
b2 = w[15 : 08];
b3 = w[07 : 00];
mb0 = gm2(b0) ^ gm3(b1) ^ b2 ^ b3;
mb1 = b0 ^ gm2(b1) ^ gm3(b2) ^ b3;
mb2 = b0 ^ b1 ^ gm2(b2) ^ gm3(b3);
mb3 = gm3(b0) ^ b1 ^ b2 ^ gm2(b3);
mixw = {mb0, mb1, mb2, mb3};
end
endfunction // mixw
function [127 : 0] mixcolumns(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = mixw(w0);
ws1 = mixw(w1);
ws2 = mixw(w2);
ws3 = mixw(w3);
mixcolumns = {ws0, ws1, ws2, ws3};
end
endfunction // mixcolumns
function [127 : 0] shiftrows(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = {w0[31 : 24], w1[23 : 16], w2[15 : 08], w3[07 : 00]};
ws1 = {w1[31 : 24], w2[23 : 16], w3[15 : 08], w0[07 : 00]};
ws2 = {w2[31 : 24], w3[23 : 16], w0[15 : 08], w1[07 : 00]};
ws3 = {w3[31 : 24], w0[23 : 16], w1[15 : 08], w2[07 : 00]};
shiftrows = {ws0, ws1, ws2, ws3};
end
endfunction // shiftrows
function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
begin
addroundkey = data ^ rkey;
end
endfunction // addroundkey
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [1 : 0] sword_ctr_reg;
reg [1 : 0] sword_ctr_new;
reg sword_ctr_we;
reg sword_ctr_inc;
reg sword_ctr_rst;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_rst;
reg round_ctr_inc;
reg [127 : 0] block_new;
reg [31 : 0] block_w0_reg;
reg [31 : 0] block_w1_reg;
reg [31 : 0] block_w2_reg;
reg [31 : 0] block_w3_reg;
reg block_w0_we;
reg block_w1_we;
reg block_w2_we;
reg block_w3_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [1 : 0] enc_ctrl_reg;
reg [1 : 0] enc_ctrl_new;
reg enc_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [2 : 0] update_type;
reg [31 : 0] muxed_sboxw;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign round = round_ctr_reg;
assign sboxw = muxed_sboxw;
assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
block_w0_reg <= 32'h0;
block_w1_reg <= 32'h0;
block_w2_reg <= 32'h0;
block_w3_reg <= 32'h0;
sword_ctr_reg <= 2'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
enc_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (block_w0_we)
block_w0_reg <= block_new[127 : 096];
if (block_w1_we)
block_w1_reg <= block_new[095 : 064];
if (block_w2_we)
block_w2_reg <= block_new[063 : 032];
if (block_w3_we)
block_w3_reg <= block_new[031 : 000];
if (sword_ctr_we)
sword_ctr_reg <= sword_ctr_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (enc_ctrl_we)
enc_ctrl_reg <= enc_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// round_logic
//
// The logic needed to implement init, main and final rounds.
//----------------------------------------------------------------
always @*
begin : round_logic
reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
block_new = 128'h0;
muxed_sboxw = 32'h0;
block_w0_we = 1'b0;
block_w1_we = 1'b0;
block_w2_we = 1'b0;
block_w3_we = 1'b0;
old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
shiftrows_block = shiftrows(old_block);
mixcolumns_block = mixcolumns(shiftrows_block);
addkey_init_block = addroundkey(block, round_key);
addkey_main_block = addroundkey(mixcolumns_block, round_key);
addkey_final_block = addroundkey(shiftrows_block, round_key);
case (update_type)
INIT_UPDATE:
begin
block_new = addkey_init_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
SBOX_UPDATE:
begin
block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
case (sword_ctr_reg)
2'h0:
begin
muxed_sboxw = block_w0_reg;
block_w0_we = 1'b1;
end
2'h1:
begin
muxed_sboxw = block_w1_reg;
block_w1_we = 1'b1;
end
2'h2:
begin
muxed_sboxw = block_w2_reg;
block_w2_we = 1'b1;
end
2'h3:
begin
muxed_sboxw = block_w3_reg;
block_w3_we = 1'b1;
end
endcase // case (sbox_mux_ctrl_reg)
end
MAIN_UPDATE:
begin
block_new = addkey_main_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
FINAL_UPDATE:
begin
block_new = addkey_final_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
default:
begin
end
endcase // case (update_type)
end // round_logic
//----------------------------------------------------------------
// sword_ctr
//
// The subbytes word counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : sword_ctr
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b0;
if (sword_ctr_rst)
begin
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b1;
end
else if (sword_ctr_inc)
begin
sword_ctr_new = sword_ctr_reg + 1'b1;
sword_ctr_we = 1'b1;
end
end // sword_ctr
//----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_rst)
begin
round_ctr_new = 4'h0;
round_ctr_we = 1'b1;
end
else if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1'b1;
end
end // round_ctr
//----------------------------------------------------------------
// encipher_ctrl
//
// The FSM that controls the encipher operations.
//----------------------------------------------------------------
always @*
begin: encipher_ctrl
reg [3 : 0] num_rounds;
// Default assignments.
sword_ctr_inc = 1'b0;
sword_ctr_rst = 1'b0;
round_ctr_inc = 1'b0;
round_ctr_rst = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
update_type = NO_UPDATE;
enc_ctrl_new = CTRL_IDLE;
enc_ctrl_we = 1'b0;
if (keylen == AES_256_BIT_KEY)
begin
num_rounds = AES256_ROUNDS;
end
else
begin
num_rounds = AES128_ROUNDS;
end
case(enc_ctrl_reg)
CTRL_IDLE:
begin
if (next)
begin
round_ctr_rst = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
enc_ctrl_new = CTRL_INIT;
enc_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
round_ctr_inc = 1'b1;
sword_ctr_rst = 1'b1;
update_type = INIT_UPDATE;
enc_ctrl_new = CTRL_SBOX;
enc_ctrl_we = 1'b1;
end
CTRL_SBOX:
begin
sword_ctr_inc = 1'b1;
update_type = SBOX_UPDATE;
if (sword_ctr_reg == 2'h3)
begin
enc_ctrl_new = CTRL_MAIN;
enc_ctrl_we = 1'b1;
end
end
CTRL_MAIN:
begin
sword_ctr_rst = 1'b1;
round_ctr_inc = 1'b1;
if (round_ctr_reg < num_rounds)
begin
update_type = MAIN_UPDATE;
enc_ctrl_new = CTRL_SBOX;
enc_ctrl_we = 1'b1;
end
else
begin
update_type = FINAL_UPDATE;
ready_new = 1'b1;
ready_we = 1'b1;
enc_ctrl_new = CTRL_IDLE;
enc_ctrl_we = 1'b1;
end
end
default:
begin
// Empty. Just here to make the synthesis tool happy.
end
endcase // case (enc_ctrl_reg)
end // encipher_ctrl
endmodule
|
module samples an input bit, sigIn. It copies this output to sigOut, but delays state changes by a variable input, waitCnt, number of clock cycles. Only the most recent state change is stored.
This scheme fails for cases where the wait time is longer than half the signal period.
Ted Golfinopoulos, 9 August 2012
*/
parameter WAIT_CNT_SIZE=11;
input clk, sigIn;
input [WAIT_CNT_SIZE-1:0] waitCnt; //Delay time - number of clk cycles to delay state changes in output
output wire sigOut;
reg sigOutReg, sigInLast;
reg [WAIT_CNT_SIZE-1:0] timer; //Counter for timing delays for state changes to output.
initial begin
#0
sigInLast=1'b0;
sigOutReg=1'b0;
timer=1'b0;
end
//Check for state changes. Wait a specified delay time, and then impose the corresponding change in the output signal. Fails for the case where the delay time is longer than half the signal period.
always @(posedge clk) begin
//Check input. If there is a state change, reset timer and record new state.
if(sigInLast != sigIn) begin //Begin timer. Really want to begin timer on rising edge of sigIn.
timer=1'b0; //Reset timer
sigInLast=sigIn; //Update sigInLast register.
end
//Delay timer.
//If timer has been reset, start counting until wait limit is reached. Then, stop and update output.
//Output gets continually updated to registered input state in steady state.
if(timer<waitCnt) begin
timer=timer+1'b1;
end else begin //Leave timer locked at waitCnt
sigOutReg=sigInLast; //Update output signal.
end
end
assign sigOut=sigOutReg; //Tie output to corresponding register.
endmodule
|
module altpciexpav_stif_a2p_addrtrans
#(
parameter CB_A2P_ADDR_MAP_IS_FIXED = 1 ,
parameter CB_A2P_ADDR_MAP_NUM_ENTRIES = 1 ,
parameter CB_A2P_ADDR_MAP_PASS_THRU_BITS = 24 ,
parameter CG_AVALON_S_ADDR_WIDTH = 24 ,
parameter CG_PCI_ADDR_WIDTH = 64 ,
parameter CG_PCI_DATA_WIDTH = 64 ,
parameter [1023:0] CB_A2P_ADDR_MAP_FIXED_TABLE = 0,
parameter INTENDED_DEVICE_FAMILY = "Stratix" ,
parameter A2P_ADDR_TRANS_TR_OUTREG = 0,
parameter A2P_ADDR_TRANS_RA_OUTREG = 0
)
(
input PbaClk_i, // Clock For Avalon to PCI Trans
input PbaRstn_i, // Reset signal
input [CG_AVALON_S_ADDR_WIDTH-1:0] PbaAddress_i, // Must be a byte specific address
input [(CG_PCI_DATA_WIDTH/8)-1:0] PbaByteEnable_i, // ByteEnables
input PbaAddrVld_i, // Valid indication in
output reg [CG_PCI_ADDR_WIDTH-1:0] PciAddr_o, // Is a byte specific address
output reg [1:0] PciAddrSpace_o, // DAC Needed
output reg PciAddrVld_o, // Valid indication out (piped)
input CraClk_i, // Clock for register access port
input CraRstn_i, // Reset signal
input [11:2] AdTrAddress_i, // Register (DWORD) specific address
input [3:0] AdTrByteEnable_i,// Register Byte Enables
input AdTrWriteVld_i, // Valid Write Cycle in
input [31:0] AdTrWriteData_i, // Write Data in
input AdTrReadVld_i, // Read Valid in
output [31:0] AdTrReadData_o, // Read Data out
output AdTrReadVld_o // Read Valid out (piped)
) ;
wire [CG_PCI_ADDR_WIDTH-1:0] pci_address; // Is a byte specific address
reg [1:0] pci_address_space; // DAC Needed
reg pci_address_valid; // Valid indication out (piped)
wire [1:0] pci_address_space_d; // DAC Needed
wire pci_address_valid_d; // Valid indication out (piped)
reg [CG_PCI_ADDR_WIDTH-1:0] RawAddr ;
wire [CG_PCI_ADDR_WIDTH-1:0] RawAddr_d ;
// register input from var_trans
always @(posedge CraClk_i or negedge CraRstn_i)
begin
if(~CraRstn_i)
begin
RawAddr <= 0;
pci_address_space <= 0;
pci_address_valid <= 0;
end
else
begin
RawAddr <= RawAddr_d;
pci_address_space <= pci_address_space_d;
pci_address_valid <= pci_address_valid_d;
end
end
/*
// synthesis translate_off
// Validate the parameters to make sure they are valid
initial
begin
case (CB_A2P_ADDR_MAP_NUM_ENTRIES)
1 :
if (CG_AVALON_S_ADDR_WIDTH != CB_A2P_ADDR_MAP_PASS_THRU_BITS)
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
else if (CB_A2P_ADDR_MAP_IS_FIXED == 0)
begin
// Note: If this case is actually parameterized, simulation (and synthesis) crashes with a fatal error before
// you can even get this far.
$display("ERROR: CB_A2P_ADDR_MAP_NUM_ENTRIES (%d) must be 2 or greater when CB_A2P_ADDR_MAP_IS_FIXED is 0.",
CB_A2P_ADDR_MAP_NUM_ENTRIES) ;
$stop ;
end
2 :
if (CG_AVALON_S_ADDR_WIDTH != (CB_A2P_ADDR_MAP_PASS_THRU_BITS + 1))
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
4 :
if (CG_AVALON_S_ADDR_WIDTH != (CB_A2P_ADDR_MAP_PASS_THRU_BITS + 2))
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
8 :
if (CG_AVALON_S_ADDR_WIDTH != (CB_A2P_ADDR_MAP_PASS_THRU_BITS + 3))
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
16 :
if (CG_AVALON_S_ADDR_WIDTH != (CB_A2P_ADDR_MAP_PASS_THRU_BITS + 4))
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
32 :
if (CG_AVALON_S_ADDR_WIDTH != (CB_A2P_ADDR_MAP_PASS_THRU_BITS + 5))
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
else if (CB_A2P_ADDR_MAP_IS_FIXED != 0)
begin
$display("ERROR: CB_A2P_ADDR_MAP_NUM_ENTRIES (%d) must be 16 or less when CB_A2P_ADDR_MAP_IS_FIXED is 1.",
CB_A2P_ADDR_MAP_NUM_ENTRIES) ;
$stop ;
end
64 :
if (CG_AVALON_S_ADDR_WIDTH != (CB_A2P_ADDR_MAP_PASS_THRU_BITS + 6))
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
else if (CB_A2P_ADDR_MAP_IS_FIXED != 0)
begin
$display("ERROR: CB_A2P_ADDR_MAP_NUM_ENTRIES (%d) must be 16 or less when CB_A2P_ADDR_MAP_IS_FIXED is 1.",
CB_A2P_ADDR_MAP_NUM_ENTRIES) ;
$stop ;
end
128 :
if (CG_AVALON_S_ADDR_WIDTH != (CB_A2P_ADDR_MAP_PASS_THRU_BITS + 7))
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
else if (CB_A2P_ADDR_MAP_IS_FIXED != 0)
begin
$display("ERROR: CB_A2P_ADDR_MAP_NUM_ENTRIES (%d) must be 16 or less when CB_A2P_ADDR_MAP_IS_FIXED is 1.",
CB_A2P_ADDR_MAP_NUM_ENTRIES) ;
$stop ;
end
256 :
if (CG_AVALON_S_ADDR_WIDTH != (CB_A2P_ADDR_MAP_PASS_THRU_BITS + 8))
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
else if (CB_A2P_ADDR_MAP_IS_FIXED != 0)
begin
$display("ERROR: CB_A2P_ADDR_MAP_NUM_ENTRIES (%d) must be 16 or less when CB_A2P_ADDR_MAP_IS_FIXED is 1.",
CB_A2P_ADDR_MAP_NUM_ENTRIES) ;
$stop ;
end
512 :
if (CG_AVALON_S_ADDR_WIDTH != (CB_A2P_ADDR_MAP_PASS_THRU_BITS + 9))
begin
$display("ERROR: CG_AVALON_S_ADDR_WIDTH (%d) != log2(CB_A2P_ADDR_MAP_NUM_ENTRIES (%d)) + CB_A2P_ADDR_MAP_PASS_THRU_BITS (%d)",
CG_AVALON_S_ADDR_WIDTH, CB_A2P_ADDR_MAP_NUM_ENTRIES, CB_A2P_ADDR_MAP_PASS_THRU_BITS) ;
$stop ;
end
else if (CB_A2P_ADDR_MAP_IS_FIXED != 0)
begin
$display("ERROR: CB_A2P_ADDR_MAP_NUM_ENTRIES (%d) must be 16 or less when CB_A2P_ADDR_MAP_IS_FIXED is 1.",
CB_A2P_ADDR_MAP_NUM_ENTRIES) ;
$stop ;
end
default :
begin
$display("ERROR: CB_A2P_ADDR_MAP_NUM_ENTRIES (%d) must be a power of 2 in the range from 1 to 512.",
CB_A2P_ADDR_MAP_NUM_ENTRIES) ;
$stop ;
end
endcase // case(CB_A2P_ADDR_MAP_NUM_ENTRIES)
end
// synthesis translate_on
*/
// Address space definitions
localparam [1:0] ADSP_CONFIG = 2'b11 ;
localparam [1:0] ADSP_IO = 2'b10 ;
localparam [1:0] ADSP_MEM64 = 2'b01 ;
localparam [1:0] ADSP_MEM32 = 2'b00 ;
// Address that has been specifically indexed down to first enabled byte
wire [CG_AVALON_S_ADDR_WIDTH-1:0] ByteAddr ;
// Address directly from the translation tables before being manipulated for
// I/O and Config space specifics
// Function to create the byte specific address
function [CG_AVALON_S_ADDR_WIDTH-1:0] ModifyByteAddr ;
input [CG_AVALON_S_ADDR_WIDTH-1:0] PbaAddress ;
input [(CG_PCI_DATA_WIDTH/8)-1:0] PbaByteEnable ;
reg [7:0] FullBE ;
begin
ModifyByteAddr[CG_AVALON_S_ADDR_WIDTH-1:3] = PbaAddress[CG_AVALON_S_ADDR_WIDTH-1:3] ;
if (CG_PCI_DATA_WIDTH == 64)
FullBE = PbaByteEnable ;
else
FullBE = {4'b0000,PbaByteEnable} ;
casez (FullBE)
8'b???????1 :
ModifyByteAddr[2:0] = {PbaAddress[2],2'b00} ;
8'b??????10 :
ModifyByteAddr[2:0] = {PbaAddress[2],2'b01} ;
8'b?????100 :
ModifyByteAddr[2:0] = {PbaAddress[2],2'b10} ;
8'b????1000 :
ModifyByteAddr[2:0] = {PbaAddress[2],2'b11} ;
8'b???10000 :
ModifyByteAddr[2:0] = 3'b100 ;
8'b??100000 :
ModifyByteAddr[2:0] = 3'b101 ;
8'b?1000000 :
ModifyByteAddr[2:0] = 3'b110 ;
8'b10000000 :
ModifyByteAddr[2:0] = 3'b111 ;
default :
ModifyByteAddr[2:0] = PbaAddress[2:0] ;
endcase // casez(FullBE)
end
endfunction // ModifyByteAddr
// Function to modify the address as needed for Config and I/O Space
function [CG_PCI_ADDR_WIDTH-1:0] ModifyCfgIO ;
input [CG_PCI_ADDR_WIDTH-1:0] RawAddr ;
input [1:0] AddrSpace ;
begin
ModifyCfgIO = {CG_PCI_ADDR_WIDTH{1'b0}} ;
case (AddrSpace)
ADSP_CONFIG :
begin
// For Config Space we need to determine if it is type 0 or type 1
// If the bus number is 0, assume type 0, else type 1
if (RawAddr[23:16] == 8'h00)
begin
// Type 0 - Pass through Function Number and Register Number
// Downstream logic only wants a QWORD address in 64-bit mode
// otherwise DWORD address in 32-bit mode
if (CG_PCI_DATA_WIDTH == 64)
ModifyCfgIO[10:3] = RawAddr[10:3] ;
else
ModifyCfgIO[10:2] = RawAddr[10:2] ;
// Type 0 - One Hot Encode Device Number
if (RawAddr[15:11] < 21)
begin
ModifyCfgIO[RawAddr[15:11]+11] = 1'b1 ;
end
else
begin
ModifyCfgIO[10:3] = 8'h0;
// synthesis translate_off
$display("ERROR: Attempt to issue a Type 0 Cfg transaction to a device number that can't be One-Hot encoded in bits 31:11") ;
$stop ;
// synthesis translate_on
end // else: !if(RawAddr[15:11] < 20)
end // if (RawAddr[23:16] == 8'h00)
else
begin
// Type 1 - Set Type 1 bit
ModifyCfgIO[0] = 1'b1 ;
// Type 1 - Pass Through Bus Num, Device Num, Func Num, and Reg Num
// Downstream logic only wants a QWORD address in 64-bit mode
// otherwise DWORD address in 32-bit mode
if (CG_PCI_DATA_WIDTH == 64)
ModifyCfgIO[23:3] = RawAddr[23:3] ;
else
ModifyCfgIO[23:2] = RawAddr[23:2] ;
end // else: !if(RawAddr[23:16] == 8'h00)
end // case: ADSP_CONFIG
ADSP_IO :
begin
// The Byte enables have already been encoded pass them through
ModifyCfgIO = RawAddr ;
end
default :
begin
// Memory Space, Pass the address through, but clear the byte specific
// In 64-bit mode the memory space address should only be a QWORD
// address, in 32-bit mode it should be a DWORD address
if (CG_PCI_DATA_WIDTH == 64)
ModifyCfgIO[CG_PCI_ADDR_WIDTH-1:3] = RawAddr[CG_PCI_ADDR_WIDTH-1:3] ;
else
ModifyCfgIO[CG_PCI_ADDR_WIDTH-1:2] = RawAddr[CG_PCI_ADDR_WIDTH-1:2] ;
end
endcase // case(AddrSpace)
end
endfunction
assign ByteAddr = ModifyByteAddr(PbaAddress_i,PbaByteEnable_i) ;
generate
if (CB_A2P_ADDR_MAP_IS_FIXED == 0)
begin
altpciexpav_stif_a2p_vartrans
#(.CB_A2P_ADDR_MAP_NUM_ENTRIES(CB_A2P_ADDR_MAP_NUM_ENTRIES),
.CB_A2P_ADDR_MAP_PASS_THRU_BITS(CB_A2P_ADDR_MAP_PASS_THRU_BITS),
.CG_AVALON_S_ADDR_WIDTH(CG_AVALON_S_ADDR_WIDTH),
.CG_PCI_ADDR_WIDTH(CG_PCI_ADDR_WIDTH),
.INTENDED_DEVICE_FAMILY(INTENDED_DEVICE_FAMILY),
.A2P_ADDR_TRANS_TR_OUTREG(A2P_ADDR_TRANS_TR_OUTREG),
.A2P_ADDR_TRANS_RA_OUTREG(A2P_ADDR_TRANS_RA_OUTREG)
)
vartrans
(
.PbaClk_i(PbaClk_i),
.PbaRstn_i(PbaRstn_i),
.PbaAddress_i(ByteAddr),
.PbaAddrVld_i(PbaAddrVld_i),
.PciAddr_o(RawAddr_d),
.PciAddrSpace_o(pci_address_space_d),
.PciAddrVld_o(pci_address_valid_d),
.CraClk_i(CraClk_i),
.CraRstn_i(CraRstn_i),
.AdTrAddress_i(AdTrAddress_i),
.AdTrByteEnable_i(AdTrByteEnable_i),
.AdTrWriteVld_i(AdTrWriteVld_i),
.AdTrWriteData_i(AdTrWriteData_i),
.AdTrReadVld_i(AdTrReadVld_i),
.AdTrReadData_o(AdTrReadData_o),
.AdTrReadVld_o(AdTrReadVld_o)
) ;
end // if (CB_A2P_ADDR_MAP_IS_FIXED == 0)
else
begin
altpciexpav_stif_a2p_fixtrans
#(.CB_A2P_ADDR_MAP_NUM_ENTRIES(CB_A2P_ADDR_MAP_NUM_ENTRIES),
.CB_A2P_ADDR_MAP_PASS_THRU_BITS(CB_A2P_ADDR_MAP_PASS_THRU_BITS),
.CG_AVALON_S_ADDR_WIDTH(CG_AVALON_S_ADDR_WIDTH),
.CG_PCI_ADDR_WIDTH(CG_PCI_ADDR_WIDTH),
.CB_A2P_ADDR_MAP_FIXED_TABLE(CB_A2P_ADDR_MAP_FIXED_TABLE)
)
fixtrans
(
.PbaAddress_i(ByteAddr),
.PbaAddrVld_i(PbaAddrVld_i),
.PciAddr_o(RawAddr_d),
.PciAddrSpace_o(pci_address_space_d),
.PciAddrVld_o(pci_address_valid_d),
.AdTrAddress_i(AdTrAddress_i),
.AdTrReadVld_i(AdTrReadVld_i),
.AdTrReadData_o(AdTrReadData_o),
.AdTrReadVld_o(AdTrReadVld_o)
) ;
end // else: !if(CB_A2P_ADDR_MAP_IS_FIXED == 0)
endgenerate
assign pci_address = ModifyCfgIO(RawAddr,pci_address_space) ;
always @(posedge CraClk_i or negedge CraRstn_i)
begin
if(~CraRstn_i)
begin
PciAddr_o <= 0;
PciAddrSpace_o <= 0;
PciAddrVld_o <= 0;
end
else
begin
PciAddr_o <= pci_address;
PciAddrSpace_o <= pci_address_space;
PciAddrVld_o <= pci_address_valid;
end
end
endmodule
|
module sky130_fd_sc_hs__dfrtp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_df_p_r_no_pg u_df_p_r_no_pg0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
|
module sky130_fd_sc_hd__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module outputs)
// End of automatics
////////////////////////////////////////////////////////////////////////
// Code start here
////////////////////////////////////////////////////////////////////////
cluster_header cluster_header (/*AUTOINST*/
// Outputs
.dbginit_l(dbginit_l),
.cluster_grst_l(cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken(cluster_cken),
.arst_l(arst_l),
.grst_l(grst_l),
.adbginit_l(adbginit_l),
.gdbginit_l(gdbginit_l),
.si (si),
.se (se));
endmodule
|
module data_path(
//---------------channel data input-----------------------------------------
input [15:0] din16,
//---------------channel data output-----------------------------------------
output [31:0] dout32,
//---------------Register-----------------------------------------------------
input [31:0] control_reg,
output [63:0] freq_reg,
output [63:0] total_size,
//--------------Globe signal----------------------------------------------------
input data_path_rst,
input clk_50m,
input clk_pcie,
input adc_clk,
//---------------Control-----------------------------------------------------
input ddr3_fifo_full,
output fifo_empty,
output fifo_full,
output total_size_mannul_reset,
output fifo_rd_en
);
localparam BUFR_DIVIDE = 2;
BUFR #(
.BUFR_DIVIDE(BUFR_DIVIDE), // "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
.SIM_DEVICE("7SERIES") // Specify target device, "VIRTEX4" or "VIRTEX5"
) BUFR_clkdiv (
.O(clk_bufr), // Clock buffer output
.CE(1'b1), // Clock enable input
.CLR(1'b0), // Clock buffer reset input
.I(clk_pcie) // Clock buffer input
);
assign fifo_rd_en = control_reg[4] ? counter_fifo_rd_en : fifo16to32_rd_en;
assign fifo_empty = control_reg[4] ? counter_fifo_empty : fifo16to32_empty;
assign fifo_full = control_reg[4] ? counter_fifo_full : fifo16to32_full;
//--------------ÄÚ²¿¼Ä´æÆ÷-----------------------------------------------------------------------
wire [63:0] freq_det_q_d,freq_det_q_c;
reg [63:0] total_size_reg1;
reg [63:0] total_size_reg2;
wire [31:0] fifo16to32_dout;//16to32´®²¢×ª»»Êý¾ÝÊä³ö
wire [31:0] counter_data;//¼ÆÊýÆ÷Êý¾Ý
wire [31:0] counter_fifo_dout;//¼ÆÊýÆ÷Êý¾Ý»º³åÊä³ö
//--------------½»Ö¯½»»»---------------------------------------------
assign dout32 = control_reg[4] ? counter_fifo_dout :
(control_reg[5] ? fifo16to32_dout :
{fifo16to32_dout[7:0],fifo16to32_dout[15:8],
fifo16to32_dout[23:16],fifo16to32_dout[31:24]});
//--------------8 to 32---------------------------------------------------
wire rec_en = control_reg[1] ? 1'b0 : control_reg[0];
assign fifo16to32_rd_en = !fifo16to32_empty & !ddr3_fifo_full;
fifo8to32 fifo16to32_ch (
.rst(data_path_rst),
.wr_clk(adc_clk),
.rd_clk(clk_pcie),
.din(din16),
.wr_en(rec_en),
.rd_en(fifo16to32_rd_en),
.dout(fifo16to32_dout),
.full(fifo16to32_full),
.empty(fifo16to32_empty)
);
//------------------------µÝÔö²âÊÔ¼ÆÊýÆ÷----------------------------------------------
wire counter_ce = control_reg[7] & control_reg[4] & rec_en;
assign counter_fifo_rd_en = !counter_fifo_empty & !ddr3_fifo_full;
COUNTER_LOAD_MACRO #(
.COUNT_BY(48'h000000000001),
.DEVICE("7SERIES"),
.WIDTH_DATA(32)
) counter32_ch (
.Q(counter_data),
.CLK(clk_bufr),
.CE(counter_ce & (~data_path_rst)),
.DIRECTION(1'b1),
.LOAD(control_reg[18]),
.LOAD_DATA(counter_load_data),
.RST(data_path_rst)
);
counter_fifo counter_fifo_ch (
.rst(data_path_rst),
.wr_clk(clk_bufr),
.rd_clk(clk_pcie),
.din(counter_data),
.wr_en(counter_ce & (~data_path_rst)),
.rd_en(counter_fifo_rd_en),
.dout(counter_fifo_dout),
.full(counter_fifo_full),
.empty(counter_fifo_empty)
);
//------------------------Êý¾Ýͳ¼Æ----------------------------------------------
assign total_size_mannul_reset = control_reg[17];
assign total_size = control_reg[4] ? total_size_reg2 : total_size_reg1;
always @(posedge c_div or posedge data_path_rst)begin
if(data_path_rst)begin
total_size_reg1 <= 64'b0;
end
else if(!rec_en | total_size_mannul_reset)begin
total_size_reg1 <= 64'b0;
end
else begin
total_size_reg1 <= total_size_reg1 + 64'd8;
end
end
always @(posedge clk_bufr or posedge data_path_rst)begin
if(data_path_rst)begin
total_size_reg2 <= 64'b0;
end
else if(!counter_ce | total_size_mannul_reset)begin
total_size_reg2 <= 64'b0;
end
else begin
total_size_reg2 <= total_size_reg2 + 64'd32;
end
end
//------------------------ƵÂʼì²â----------------------------------------------
assign freq_reg = control_reg[4] ? (freq_det_q_c<<3) : (freq_det_q_d<<3);
Freq_Count_Top freq_det_d (
.sys_clk_50m(clk_50m),
.ch_c(c_div),
.freq_reg(freq_det_q_d),
.sys_rst_n(~data_path_rst)
);
Freq_Count_Top freq_det_c (
.sys_clk_50m(clk_50m),
.ch_c(clk_bufr),
.freq_reg(freq_det_q_c),
.sys_rst_n(~data_path_rst)
);
endmodule
|
module system_clock_splitter_1_0
(clk_in,
latch_edge,
clk_out);
input clk_in;
input latch_edge;
output clk_out;
wire clk_in;
wire clk_out;
wire latch_edge;
system_clock_splitter_1_0_clock_splitter U0
(.clk_in(clk_in),
.clk_out(clk_out),
.latch_edge(latch_edge));
endmodule
|
module system_clock_splitter_1_0_clock_splitter
(clk_out,
latch_edge,
clk_in);
output clk_out;
input latch_edge;
input clk_in;
wire clk_i_1_n_0;
wire clk_in;
wire clk_out;
wire last_edge;
wire latch_edge;
LUT3 #(
.INIT(8'h6F))
clk_i_1
(.I0(latch_edge),
.I1(last_edge),
.I2(clk_out),
.O(clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_reg
(.C(clk_in),
.CE(1'b1),
.D(clk_i_1_n_0),
.Q(clk_out),
.R(1'b0));
FDRE #(
.INIT(1'b0))
last_edge_reg
(.C(clk_in),
.CE(1'b1),
.D(latch_edge),
.Q(last_edge),
.R(1'b0));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__nand2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
|
module bw_clk_cclk_scanlasr_2x (so, sd, ck, r_l);
output so;
input sd, ck, r_l;
reg so_l;
assign so = ~so_l;
always @ ( ck or sd or r_l )
if (~(ck & r_l)) so_l <= ~sd ;
endmodule
|
module text_editor_keyboard_controller(
input sys_Clk,
input PS2_Clk,
input Reset,
inout PS2KeyboardData,
inout PS2KeyboardClk,
output reg [7:0] KeyData,
output reg KeyReleased
);
/************************************************************************
* LOCAL SIGNALS *
************************************************************************/
reg [1:0] state;
localparam
I = 2'b00,
BAT = 2'b01,
DATA = 2'b10,
UNK = 2'bXX;
wire [7:0] received_data;
wire received_data_en;
reg [7:0] previous_word;
reg send_command;
reg [7:0] the_command;
wire command_sent;
/************************************************************************
* PS2 KEYBOARD *
************************************************************************/
PS2_Controller PS2_Keyboard_Controller(
// Inputs
.CLOCK_50(PS2_Clk),
.reset(Reset),
.the_command(the_command),
.send_command(send_command),
// Bidirectionals
.PS2_CLK(PS2KeyboardClk), // PS2 Clock
.PS2_DAT(PS2KeyboardData), // PS2 Data
// Outputs
.command_was_sent(command_sent),
.error_communication_timed_out( ),
.received_data(received_data),
.received_data_en(received_data_en) // If 1 - new data has been received
);
/************************************************************************
* STATE MACHINE *
************************************************************************/
always @ (posedge sys_Clk, posedge Reset) begin: STATE_MACHINE
if(Reset) begin
state <= I;
previous_word <= 8'hXX;
send_command <= 1'bX;
the_command <= 8'hXX;
KeyData <= 8'hXX;
end else
case(state)
I: begin
state <= BAT;
KeyData <= 8'h00;
previous_word <= 8'h00;
KeyReleased <= 1'b0;
send_command <= 1'b1;
the_command <= 8'hFF; // RESET KEYBOARD
end
BAT: begin
if (command_sent) begin
send_command <= 1'b0;
end
case (received_data)
8'hAA: begin // SUCCESSFUL POST
state <= DATA;
end
8'hFC: begin
send_command <= 1'b1; // TRY TO POST AGAIN
end
default: begin
end
endcase
end
DATA: begin
if (command_sent) begin
send_command <= 1'b0;
end
if (KeyReleased) begin
KeyReleased <= 1'b0;
end
if (received_data_en) begin
previous_word <= received_data;
case(received_data)
8'hF0: begin
// Key Released
end
8'hFA: begin
// Acknowledge
end
8'hAA: begin
// Self Test Passed
end
8'hEE: begin
// Echo Response
end
8'hFE: begin
// Resend Request
end
8'h00: begin
// Error
end
8'hFF: begin
// Error
end
8'h12: begin
// Shift
end
8'h59: begin
// Shift
end
8'h58: begin
// Caps
end
8'h0D: begin
// Tab
end
8'h14: begin
// Ctrl
end
8'h11: begin
// Alt
end
8'hE0: begin
// Extra
end
8'h5A: begin
// Enter
end
default: begin
if (previous_word == 8'hF0) begin // IF PREV WORD WAS KEY RELEASED SCAN CODE
KeyData <= received_data;
KeyReleased <= 1'b1;
end
end
endcase
end
end
default:
state <= UNK;
endcase
end
endmodule
|
module sim_tb_top;
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter SIMULATION = "FALSE";
parameter BL_WIDTH = 8;
parameter PORT_MODE = "BI_MODE";
parameter DATA_MODE = 4'b0010;
parameter EYE_TEST = "FALSE";
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL";
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL";
// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter BEGIN_ADDRESS = 32'h00000000;
parameter END_ADDRESS = 32'h00000fff;
parameter PRBS_EADDR_MASK_POS = 32'hff000000;
parameter SEL_VICTIM_LINE = 11;
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3;
// # of memory Bank Address bits.
parameter CK_WIDTH = 1;
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 1;
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1;
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1;
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 5;
parameter DQ_CNT_WIDTH = 6;
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8;
parameter DM_WIDTH = 8;
// # of DM (data mask)
parameter DQ_WIDTH = 64;
// # of DQ (data)
parameter DQS_WIDTH = 8;
parameter DQS_CNT_WIDTH = 3;
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8;
// # of DQ per DQS
parameter ECC = "OFF";
parameter nBANK_MACHS = 4;
parameter RANKS = 1;
// # of Ranks.
parameter ROW_WIDTH = 14;
// # of memory Row Address bits.
parameter ADDR_WIDTH = 28;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
parameter USE_CS_PORT = 1;
// # = 1, When CS output is enabled
// = 0, When CS output is disabled
parameter USE_DM_PORT = 1;
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disbaled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1;
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0";
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0;
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8";
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ";
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 6;
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter CWL = 5;
// in number of clock cycles
// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
// DDR2 SDRAM: Can be ignored
parameter DDR2_DQSN_ENABLE = "YES";
// Enable differential DQS for DDR2
parameter OUTPUT_DRV = "HIGH";
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter RTT_NOM = "60";
// RTT_NOM (ODT) (Mode Register 1).
// # = "DISABLED" - RTT_NOM disabled,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF";
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter ADDR_CMD_MODE = "1T" ;
// # = "1T", "2T".
parameter REG_CTRL = "OFF";
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 2500;
// Input Clock Period
parameter CLKFBOUT_MULT = 2;
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1;
// write PLL VCO divisor
parameter CLKOUT0_DIVIDE = 2;
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 2;
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 32;
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 8;
// VCO output divisor for PLL output clock (CLKOUT3)
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tFAW = 30000;
// memory tRAW paramter in pS.
parameter tRAS = 35000;
// memory tRAS paramter in pS.
parameter tRCD = 13125;
// memory tRCD paramter in pS.
parameter tREFI = 7800000;
// memory tREFI paramter in pS.
parameter tRFC = 110000;
// memory tRFC paramter in pS.
parameter tRP = 13125;
// memory tRP paramter in pS.
parameter tRRD = 6000;
// memory tRRD paramter in pS.
parameter tRTP = 7500;
// memory tRTP paramter in pS.
parameter tWTR = 7500;
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000;
// memory tZQI paramter in nS.
parameter tZQCS = 64;
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "SIM_INIT_CAL_FULL" - Complete
// memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111;
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b1110;
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b1111;
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000;
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000;
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'hF;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'h0;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'hF;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'h0;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'h0;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'h3FE_3FE_3FE_2FF;
parameter PHY_1_BITLANES = 48'hFFF_FFE_000_000;
parameter PHY_2_BITLANES = 48'h3FE_3FE_3FE_2FF;
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_13;
parameter ADDR_MAP
= 192'h000_000_139_138_137_136_135_134_133_132_131_130_129_128_127_126;
parameter BANK_MAP = 36'h12B_12A_125;
parameter CAS_MAP = 12'h123;
parameter CKE_ODT_BYTE_MAP = 8'h13;
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_121;
parameter PARITY_MAP = 12'h000;
parameter RAS_MAP = 12'h124;
parameter WE_MAP = 12'h122;
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_20_21_22_23_00_01_02_03;
parameter DATA0_MAP = 96'h031_032_033_034_035_036_037_038;
parameter DATA1_MAP = 96'h021_022_023_024_025_026_027_028;
parameter DATA2_MAP = 96'h011_012_013_014_015_016_017_018;
parameter DATA3_MAP = 96'h000_001_002_003_004_005_006_007;
parameter DATA4_MAP = 96'h231_232_233_234_235_236_237_238;
parameter DATA5_MAP = 96'h221_222_223_224_225_226_227_228;
parameter DATA6_MAP = 96'h211_212_213_214_215_216_217_218;
parameter DATA7_MAP = 96'h200_201_202_203_204_205_206_207;
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000;
parameter MASK0_MAP = 108'h000_209_219_229_239_009_019_029_039;
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000;
parameter SLOT_0_CONFIG = 8'b0000_0001;
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000;
// Mapping of Ranks.
parameter MEM_ADDR_ORDER
= "BANK_ROW_COLUMN";
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IODELAY_HP_MODE = "ON";
// to phy_top
parameter IBUF_LPWR_MODE = "OFF";
// to phy_top
parameter WRLVL = "ON";
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "NORM";
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000;
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000;
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0;
// Calibration bank address will be used for
// calibration read and write operations
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IODELAY_GRP = "IODELAY_MIG";
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
parameter INPUT_CLK_TYPE = "DIFFERENTIAL";
// input clock type DIFFERNTIAL or SINGLE_ENDED
parameter RST_ACT_LOW = 1;
// =1 for active low reset,
// =0 for active high.
parameter CAL_WIDTH = "HALF";
parameter TCQ = 100;
parameter STARVE_LIMIT = 2;
// # = 2,3,4.
//***************************************************************************
// System clock and Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0;
// IODELAYCTRL reference clock frequency
parameter tCK = 2500;
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 4;
// # of memory CKs per fabric CLK
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DRAM_TYPE = "DDR3";
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00;
// Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00;
// Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00;
// Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00;
// Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00;
// Delay for data signal during Read operation
localparam MEMORY_WIDTH = 8;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam real SYSCLK_PERIOD = tCK;
// Number of DDR3 SDRAM controllers
localparam DDR3_COUNT = 1;
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_rst_n;
wire sys_rst;
wire [DDR3_COUNT-1:0] init_calib_complete_i;
wire [DDR3_COUNT-1:0] error_i;
reg sys_clk_i;
wire sys_clk_p;
wire sys_clk_n;
reg clk_ref_i;
wire clk_ref_p;
wire clk_ref_n;
wire ddr3_reset_n;
wire [DQ_WIDTH-1:0] ddr3_dq_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga;
wire [ROW_WIDTH-1:0] ddr3_addr_fpga;
wire [BANK_WIDTH-1:0] ddr3_ba_fpga;
wire ddr3_ras_n_fpga;
wire ddr3_cas_n_fpga;
wire ddr3_we_n_fpga;
wire [CKE_WIDTH-1:0] ddr3_cke_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_p_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_n_fpga;
wire error;
wire init_calib_complete;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_fpga;
wire [DM_WIDTH-1:0] ddr3_dm_fpga;
wire [RANKS-1:0] ddr3_odt_fpga;
wire sda;
wire scl;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram_tmp;
reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp;
reg [RANKS-1:0] ddr3_odt_sdram_tmp;
wire [DQ_WIDTH-1:0] ddr3_dq_sdram;
reg [ROW_WIDTH-1:0] ddr3_addr_sdram;
reg [BANK_WIDTH-1:0] ddr3_ba_sdram;
reg ddr3_ras_n_sdram;
reg ddr3_cas_n_sdram;
reg ddr3_we_n_sdram;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram;
wire [RANKS-1:0] ddr3_odt_sdram;
reg [CKE_WIDTH-1:0] ddr3_cke_sdram;
wire [DM_WIDTH-1:0] ddr3_dm_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_p_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_n_sdram;
//**************************************************************************//
//**************************************************************************//
// Reset Generation
//**************************************************************************//
initial begin
sys_rst_n = 1'b0;
#120000
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
//**************************************************************************//
// Clock Generation
//**************************************************************************//
initial
sys_clk_i = 1'b0;
always
sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;
assign sys_clk_p = sys_clk_i;
assign sys_clk_n = ~sys_clk_i;
initial
clk_ref_i = 1'b0;
always
clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
assign clk_ref_p = clk_ref_i;
assign clk_ref_n = ~clk_ref_i;
always @( * ) begin
ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga;
ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga;
ddr3_addr_sdram <= #(TPROP_PCB_CTRL) ddr3_addr_fpga;
ddr3_ba_sdram <= #(TPROP_PCB_CTRL) ddr3_ba_fpga;
ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga;
ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga;
ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga;
ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga;
end
always @( * )
ddr3_cs_n_sdram_tmp <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga;
assign ddr3_cs_n_sdram = ddr3_cs_n_sdram_tmp;
always @( * )
ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga;//DM signal generation
assign ddr3_dm_sdram = ddr3_dm_sdram_tmp;
always @( * )
ddr3_odt_sdram_tmp <= #(TPROP_PCB_CTRL) ddr3_odt_fpga;
assign ddr3_odt_sdram = ddr3_odt_sdram_tmp;
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT ("OFF")
)
u_delay_dq
(
.A (ddr3_dq_fpga[dqwd]),
.B (ddr3_dq_sdram[dqwd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
// For ECC ON case error is inserted on LSB bit from DRAM to FPGA
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT (ECC)
)
u_delay_dq_0
(
.A (ddr3_dq_fpga[0]),
.B (ddr3_dq_sdram[0]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_p
(
.A (ddr3_dqs_p_fpga[dqswd]),
.B (ddr3_dqs_p_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_n
(
.A (ddr3_dqs_n_fpga[dqswd]),
.B (ddr3_dqs_n_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
endgenerate
example_top #
(
.SIMULATION (SIMULATION),
.BL_WIDTH (BL_WIDTH),
.PORT_MODE (PORT_MODE),
.DATA_MODE (DATA_MODE),
.EYE_TEST (EYE_TEST),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_PER_DM (DQ_PER_DM),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.AL (AL),
.nAL (nAL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CL (CL),
.CWL (CWL),
.OUTPUT_DRV (OUTPUT_DRV),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.REG_CTRL (REG_CTRL),
.CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.tFAW (tFAW),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.WRLVL (WRLVL),
.ORDERING (ORDERING),
.IODELAY_GRP (IODELAY_GRP),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.RST_ACT_LOW (RST_ACT_LOW),
.CAL_WIDTH (CAL_WIDTH),
.TCQ (TCQ),
.STARVE_LIMIT (STARVE_LIMIT),
.REFCLK_FREQ (REFCLK_FREQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.DEBUG_PORT (DEBUG_PORT),
.DRAM_TYPE (DRAM_TYPE)
)
u_ip_top
(
.ddr3_dq (ddr3_dq_fpga),
.ddr3_dqs_n (ddr3_dqs_n_fpga),
.ddr3_dqs_p (ddr3_dqs_p_fpga),
.ddr3_addr (ddr3_addr_fpga),
.ddr3_ba (ddr3_ba_fpga),
.ddr3_ras_n (ddr3_ras_n_fpga),
.ddr3_cas_n (ddr3_cas_n_fpga),
.ddr3_we_n (ddr3_we_n_fpga),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_ck_p (ddr3_ck_p_fpga),
.ddr3_ck_n (ddr3_ck_n_fpga),
.ddr3_cke (ddr3_cke_fpga),
.ddr3_cs_n (ddr3_cs_n_fpga),
.ddr3_dm (ddr3_dm_fpga),
.ddr3_odt (ddr3_odt_fpga),
.sda (sda),
.scl (scl),
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.error (error_i),
.init_calib_complete (init_calib_complete_i),
.sys_rst (sys_rst)
);
//**************************************************************************//
// Memory Models instantiations
//**************************************************************************//
genvar r,i;
generate
for (r = 0; r < CS_WIDTH; r = r + 1) begin: mem_rnk
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
endgenerate
assign error = | error_i;
assign init_calib_complete = & init_calib_complete_i;
//***************************************************************************
// Reporting the test case status
//***************************************************************************
initial
begin : Logging
fork
begin : calibration_done
wait (init_calib_complete);
$display("Calibration Done");
#50000000;
if (!error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
#1000000000;
if (!init_calib_complete) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
module rcswitch_send(
input clk,
input rst,
input send,
input [39:0] addr,
input [39:0] chan,
input [15:0] stat,
output ready,
output out
);
reg r_out;
reg r_ready;
reg [7:0] pos;
reg [127:0] msg;
initial begin
r_ready <= 1;
r_out <= 0;
pos <= 0;
msg <= 0;
end
always @(posedge clk or posedge rst) begin
if(rst) begin
r_ready <= 1;
r_out <= 0;
pos <= 0;
end
else begin
// start a new message
if(send && pos == 0) begin
pos <= 128;
r_ready <= 0;
msg[127:0] <= {addr[39:0], chan[39:0], stat[15:0], 32'b10000000_00000000_00000000_00000000};
end
// shift out the bits for the message
else if(pos > 0) begin
pos <= pos - 1;
r_out <= msg >> pos;
// message is done - prepare for repeat
if(pos == 0) begin
r_ready <= 1;
r_out <= 0;
pos <= 0;
end
else begin
r_ready <= 0;
end
end
else begin
msg <= ~msg;
end
end
end
assign ready = r_ready;
assign out = r_out;
endmodule
|
module tri_state_detect (
input clk,
input rst,
input in,
output [31:0] count_h,
output [31:0] count_l,
output detected
);
reg [31:0] ticks;
reg [31:0] t1;
reg [31:0] t2;
reg synced;
reg [31:0] r_count_h;
reg [31:0] r_count_l;
initial begin
ticks <= 0;
t1 <= 0;
t2 <= 0;
synced <= 0;
r_count_h <= 0;
r_count_l <= 0;
end
always @(posedge clk or posedge rst) begin
if(rst) begin
ticks <= 0;
end
else begin
ticks <= ticks + 1;
end
end
always @(negedge in or posedge rst) begin
if(rst) begin
t2 <= 0;
end
else begin
if(t1 > 0) begin
t2 <= ticks;
end
end
end
always @(posedge in or posedge rst) begin
if(rst) begin
t1 <= 0;
r_count_h <= 0;
r_count_l <= 0;
synced <= 0;
end
else begin
if(t2 > t1) begin
r_count_h = t2 - t1;
r_count_l = ticks - t2;
synced <= 1;
end
else begin
synced <= 0;
end
t1 <= ticks;
end
end
assign count_h = r_count_h;
assign count_l = r_count_l;
assign detected = (synced & in);
endmodule
|
module rcswitch_receive(
input clk,
input rst,
input in,
output [39:0] addr,
output [39:0] chan,
output [15:0] stat,
output ready
);
reg [8:0] count;
reg [95:0] msg;
reg [39:0] r_addr;
reg [39:0] r_chan;
reg [15:0] r_stat;
reg r_ready;
initial begin
count <= 0;
msg <= 0;
r_addr <= 0;
r_chan <= 0;
r_stat <= 0;
r_ready <= 0;
end
wire [31:0] count_h;
wire [31:0] count_l;
wire detected;
tri_state_detect tsd_inst (
.clk(clk),
.rst(rst),
.in(in),
.count_h(count_h),
.count_l(count_l),
.detected(detected)
);
always @(posedge detected or posedge rst) begin
if(rst) begin
count <= 0;
r_addr <= 0;
r_chan <= 0;
r_stat <= 0;
r_ready <= 0;
end
else begin
// detected SYNC
if(count_h * 10 < count_l) begin
count <= 0;
msg <= 0;
end
// detected 1000
else if(count_h < count_l) begin
msg <= (msg << 4) | 96'b1000;
count <= count + 1;
end
// detected 1110
else if(count_l < count_h) begin
msg <= (msg << 4) | 96'b1110;
count <= count + 1;
end
// message complete?
if(count == 24) begin
{r_addr[39:0], r_chan[39:0], r_stat[15:0]} <= msg;
r_ready <= 1;
count <= 0;
msg <= 0;
end
else begin
r_ready <= 0;
end
end
end
assign ready = r_ready;
assign addr = r_addr;
assign chan = r_chan;
assign stat = r_stat;
endmodule
|
module sky130_fd_sc_hs__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
|
module B_SPI_HFC_Slave_v0_1(
input wire reset, /* System Reset */
input wire clock, /* System Clk - 2x Bit rate */
input wire mosi, /* SPI MOSI input */
input wire rde, /* rx data effective */
input wire sclk, /* SPI SCLK input */
input wire ss, /* SPI SS input */
output wire miso, /* SPI MISO output */
output reg tde, /* tx data effective */
output wire tx_interpt, /* Status Register Interrupt output */
output wire rx_interpt, /* Status Register Interrupt output */
output wire tx_drq, /* tx DMA request */
output wire rx_drq /* rx DMA request */
);
/* bit order: default is MSb first (i.e Shift Left and ShiftLeft in static configuration is = 0) */
/* DO NOT CHANGE these two parameters. They define constants */
localparam SPIS_MSB_FIRST = 1'b0;
localparam SPIS_LSB_FIRST = 1'b1;
/* Status register bits */
localparam SPIS_STS_SPI_DONE_BIT = 3'd0;
localparam SPIS_STS_TX_BUFFER_NOT_FULL_BIT = 3'd1;
localparam SPIS_STS_TX_BUFFER_EMPTY_BIT = 3'd2;
localparam SPIS_STS_BYTE_COMPLETE_BIT = 3'd6;
localparam SPIS_STS_RX_BUFFER_NOT_EMPTY_BIT = 3'd3;
localparam SPIS_STS_RX_BUFFER_EMPTY_BIT = 3'd4;
localparam SPIS_STS_RX_FIFO_OVERRUN_BIT = 3'd5;
localparam SPIS_STS_RX_FIFO_FULL_BIT = 3'd6;
/* Index for Bidirectional Mode Control Register bit */
localparam CTRL_TX_PERMISSION = 1'b0;
/* Counter initialization bit */
localparam CTRL_CNT_INIT = 1'b1;
parameter [0:0] ShiftDir = SPIS_MSB_FIRST;
/* set to 2-8 bits only. Default is 8 bits */
parameter [6:0] NumberOfDataBits = 7'd8;
/* Default is rising edge mode */
parameter [0:0] ModeCPHA = 1'b0;
parameter [0:0] ModePOL = 1'b0;
localparam [2:0] dp8MsbVal = (NumberOfDataBits % 8) - 3'd1;
localparam [7:0] dpMask = (NumberOfDataBits == 8) ? 8'd255 :
(NumberOfDataBits == 7) ? 8'd127 :
(NumberOfDataBits == 6) ? 8'd63 :
(NumberOfDataBits == 5) ? 8'd31 :
(NumberOfDataBits == 4) ? 8'd15 :
(NumberOfDataBits == 3) ? 8'd7 :
(NumberOfDataBits == 2) ? 8'd3 : 8'd0;
/* This value get's truncated to 3 bits */
localparam [2:0] dp16MsbVal = (NumberOfDataBits % 8) - 4'd9;
localparam [7:0] dp16MOSIMask = (NumberOfDataBits == 16) ? 8'd255 :
(NumberOfDataBits == 15) ? 8'd127 :
(NumberOfDataBits == 14) ? 8'd63 :
(NumberOfDataBits == 13) ? 8'd31 :
(NumberOfDataBits == 12) ? 8'd15 :
(NumberOfDataBits == 11) ? 8'd7 :
(NumberOfDataBits == 10) ? 8'd3 :
/*(NumberOfDataBits == 9) ? */ 8'd1 ;
localparam [1:0] dynShiftDir = (ShiftDir == SPIS_MSB_FIRST) ? 2'd1 : 2'd2;
localparam [1:0] dp16MSBSIChoice = (ShiftDir == SPIS_MSB_FIRST) ? `SC_SI_A_CHAIN : `SC_SI_A_ROUTE;
localparam [1:0] dp16LSBSIChoice = (ShiftDir == SPIS_MSB_FIRST) ? `SC_SI_A_ROUTE : `SC_SI_A_CHAIN;
/* RX FIFO is loaded on the negedge of SCLK */
localparam f1_edge = `SC_FIFO_CLK1_NEG;
/* Datapath selection local parameters */
localparam SR8 = 8'd8;
localparam SR16 = 8'd16;
/* datapath configurations */
localparam dp8_config = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
dpMask, 8'hFF, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dp8MsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC__ADD, 4'h00, f1_edge, `SC_FIFO_CLK0_POS,
`SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,`SC_FIFO__EDGE,
`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,`SC_WRK16CAT_DSBL /*CFG17-16: */
};
localparam dp16_config_msb = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
dp16MOSIMask, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
dp16MSBSIChoice, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dp16MsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC__ADD, 4'h00, f1_edge, `SC_FIFO_CLK0_POS,
`SC_FIFO_CLK__DP, `SC_FIFO_CAP_AX,
`SC_FIFO__EDGE, `SC_FIFO_ASYNC, `SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
localparam dp16_config_lsb = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
dp16LSBSIChoice, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC__ADD, 4'h00, f1_edge, `SC_FIFO_CLK0_POS,
`SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO__EDGE, `SC_FIFO_ASYNC, `SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
/* Status Register inputs from the PLD/DP's */
wire [6:0] tx_status;
wire [6:0] rx_status;
/* Master Out Slave In from the Datapath.
Selects between mosi_dp8 and mosi_dp16 based on NUM_BITS */
wire miso_from_dp;
/* One compare output of the counter which signals
when to load received data into the FIFO */
wire dpcounter_zero;
/* "Counter is equal to '1' condition" output
is used as "byte complete" condition*/
wire dpcounter_one;
/* counter output */
wire [6:0] count;
/* datapath si input*/
wire mosi_to_dp;
/* non-connected wires, used for connection convenience */
wire nc1, nc2, nc3, nc4;
/* TX and RX FIFO status outputs */
wire dpMISO_fifo_not_empty;
wire dpMISO_fifo_not_full;
wire dpMISO_fifo_empty;
wire dpMOSI_fifo_not_empty;
wire dpMOSI_fifo_full;
wire dpMOSI_fifo_empty;
/* "clear on read" status input sources */
wire mosi_buf_overrun;
/* load RX FIFO (from counter) */
wire load;
/* Datapath and Counter7 clock */
wire dp_clock;
/* conditional 'shift out' wires for 16-bit datapath */
wire mosi_from_dpL;
wire mosi_from_dpR;
wire cnt_reset = reset | ss;
wire inv_ss = ~ss;
/*registered MOSI value*/
reg mosi_tmp;
reg dpcounter_one_reg;
reg mosi_buf_overrun_fin;
wire clock_fin;
wire dpcounter_one_fin;
wire miso_tx_empty_reg_fin;
wire mosi_buf_overrun_reg;
wire dpMOSI_fifo_full_reg;
wire tx_load = (ModeCPHA == 1'b0) ? load : dpcounter_zero;
wire byte_complete = dpcounter_one_fin & (~dpcounter_one_reg);
wire rx_buf_overrun = mosi_buf_overrun_reg & (~mosi_buf_overrun_fin);
wire prc_clk_src = (((ModeCPHA == 0) && (ModePOL == 0)) || ((ModeCPHA == 1) && (ModePOL == 1))) ? sclk : ~sclk;
wire dp_clk_src = (((ModeCPHA == 0) && (ModePOL == 1)) || ((ModeCPHA == 1) && (ModePOL == 0))) ? sclk : ~sclk;
wire prc_clk;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE))
ClkEn (
.clock_in(clock),
.enable(1'b1),
.clock_out(clock_fin)
);
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE))
PrcClkEn (
.clock_in(prc_clk_src),
.enable(1'b1),
.clock_out(prc_clk)
);
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE))
DpClkEn (
.clock_in(dp_clk_src),
.enable(1'b1),
.clock_out(dp_clock)
);
cy_psoc3_sync sync_1(
.sc_out(dpcounter_one_fin),
.sc_in(dpcounter_one),
.clock(clock_fin)
);
cy_psoc3_sync sync_2(
.sc_out(miso_tx_empty_reg_fin),
.sc_in(dpMISO_fifo_empty),
.clock(clock_fin)
);
cy_psoc3_sync sync_3(
.sc_out(mosi_buf_overrun_reg),
.sc_in(mosi_buf_overrun),
.clock(clock_fin)
);
cy_psoc3_sync sync_4(
.sc_out(dpMOSI_fifo_full_reg),
.sc_in(dpMOSI_fifo_full),
.clock(clock_fin)
);
assign miso = (ss == 1'b0) ? miso_from_dp : 1'b0;
assign dpMISO_fifo_not_empty = ~dpMISO_fifo_empty;
assign mosi_buf_overrun = load & dpMOSI_fifo_full;
/* status register connections */
assign tx_status[SPIS_STS_SPI_DONE_BIT] = (byte_complete & miso_tx_empty_reg_fin);
assign tx_status[SPIS_STS_TX_BUFFER_EMPTY_BIT] = miso_tx_empty_reg_fin;
assign tx_status[SPIS_STS_TX_BUFFER_NOT_FULL_BIT] = dpMISO_fifo_not_full;
assign tx_status[SPIS_STS_BYTE_COMPLETE_BIT] = byte_complete;
assign rx_status[SPIS_STS_RX_BUFFER_EMPTY_BIT] = dpMISO_fifo_empty;
assign rx_status[SPIS_STS_RX_BUFFER_NOT_EMPTY_BIT] = dpMOSI_fifo_not_empty;
assign rx_status[SPIS_STS_RX_FIFO_OVERRUN_BIT] = rx_buf_overrun;
assign rx_status[SPIS_STS_RX_FIFO_FULL_BIT] = dpMOSI_fifo_full_reg;
assign tx_status[5:3] = 3'h0;
assign rx_status[2:0] = 3'h0;
assign tx_drq = dpMISO_fifo_not_full;
assign rx_drq = dpMOSI_fifo_not_empty;
/* Determination of 'sclk_fin' polarity
according to the ModePOL parameter value.
If 'SS' is 'high' SCLK should be blocked */
cy_psoc3_count7 #(.cy_period(NumberOfDataBits - 7'h1), .cy_route_ld(0), .cy_route_en(1))
BitCounter(
/* input */ .clock(dp_clock),
/* input */ .reset(cnt_reset),
/* input */ .load(1'b0),
/* input */ .enable(inv_ss),
/* output [06:00] */ .count(count),
/* output */ .tc()
);
assign dpcounter_zero = (count[3:0] == 4'h0);
assign dpcounter_one = (count[3:0] == 4'h1);
assign load = (ModeCPHA == 1'b0) ? dpcounter_one : dpcounter_zero;
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h41), .cy_int_mask(7'h7F))
TxStsReg(
/* input */ .clock(clock_fin),
/* input [06:00] */ .status(tx_status),
/* output */ .interrupt(tx_interpt)
);
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h20), .cy_int_mask(7'h7F))
RxStsReg(
/* input */ .clock(clock_fin),
/* input [06:00] */ .status(rx_status),
/* output */ .interrupt(rx_interpt)
);
always @(posedge clock_fin) begin
dpcounter_one_reg <= dpcounter_one_fin;
mosi_buf_overrun_fin <= mosi_buf_overrun_reg;
end
always @(posedge prc_clk) begin
mosi_tmp <= mosi;
end
always @(posedge dp_clock) begin
if (inv_ss == 1'b1 && tx_load == 1'b1) begin
tde <= dpMISO_fifo_empty;
end
else if (dpMISO_fifo_not_full == 1'b1) begin
tde <= 1'b0;
end
else begin
tde <= tde;
end
end
/* Bypass input flip-flop on last received bit */
assign mosi_to_dp = (load == 1'b1) ? mosi : mosi_tmp;
wire load_rx;
assign load_rx = (rde == 1'b0) ? load : 1'b0;
generate
if (NumberOfDataBits <= SR8) begin: sR8
cy_psoc3_dp8 #(.cy_dpconfig_a(dp8_config))
Dp(
/* input */ .clk(dp_clock),
/* input */ .reset(reset),
/* input [02:00] */ .cs_addr({inv_ss, 1'b0, tx_load}),
/* input */ .route_si(mosi_to_dp),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(load_rx),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(miso_from_dp),
/* output */ .f0_bus_stat(dpMISO_fifo_not_full),
/* output */ .f0_blk_stat(dpMISO_fifo_empty),
/* output */ .f1_bus_stat(dpMOSI_fifo_not_empty),
/* output */ .f1_blk_stat(dpMOSI_fifo_full)
);
end /* NumberOfDataBits <= 8 */
else if (NumberOfDataBits <= SR16) begin : sR16 /* NumberOfDataBits > 8 */
cy_psoc3_dp16 #(.cy_dpconfig_a(dp16_config_lsb), .cy_dpconfig_b(dp16_config_msb))
Dp(
/* input */ .clk(dp_clock),
/* input */ .reset(reset),
/* input [02:00] */ .cs_addr({inv_ss, 1'b0, tx_load}),
/* input */ .route_si(mosi_to_dp),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(load_rx),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so({mosi_from_dpL, mosi_from_dpR}),
/* output */ .f0_bus_stat({dpMISO_fifo_not_full, nc1}),
/* output */ .f0_blk_stat({dpMISO_fifo_empty, nc2}),
/* output */ .f1_bus_stat({dpMOSI_fifo_not_empty, nc3}),
/* output */ .f1_blk_stat({dpMOSI_fifo_full, nc4})
);
assign miso_from_dp = (ShiftDir == SPIS_MSB_FIRST) ? mosi_from_dpL : mosi_from_dpR;
end /* sR16 */
endgenerate
endmodule
|
module fifo_122x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [121:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [121:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [121:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [121:0] q = sub_wire2[121:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 122,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
|
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module tb_dac;
reg [7:0] dac_in;
reg clk;
reg conv;
reg rst;
reg [7:0] counter;
wire dac_out;
dac uut (
.dac_in(dac_in),
.clk(clk),
.rst(rst),
.conv(conv),
.dac_out(dac_out)
);
defparam uut.RES = 7;
initial
begin
$dumpfile("dump.lxt");
$dumpvars();
// $display ( "time \tclk \trst \tdac_in \tdac_out ");
#1981284252
$finish;
end
initial begin
dac_in = 8'h00;
clk = 0;
conv = 0;
rst = 0;
#20
rst <= 1;
#20
rst <= 0;
#20
dac_in = 8'he6;
conv = 1;
#100
$stop;
end
always begin
#`clkperiodby2 clk <= ~clk;
// #((`clkperiodby2)*2*256) dac_in <= dac_in + 1;
end
/* always@(posedge clk)
counter <= counter + 1;
always@(posedge clk)
begin
if(counter == 8'hff) begin
dac_in <= dac_in + 1;
counter <= 8'b0; end
else begin
dac_in <= dac_in;
counter <= counter + 1; end
end
*/
endmodule
|
module cpu(CLK, RESET, EN_L, Iin, Din, PC, NextPC, DataA, DataB, DataC, DataD, MW);
input CLK;
input RESET;
input EN_L;
input [15:0] Iin;
input [7:0] Din;
output [7:0] PC;
output [7:0] NextPC;
output [7:0] DataA;
output [7:0] DataB;
output [7:0] DataC;
output [7:0] DataD;
output MW;
// comment the two lines out below if you use a submodule to generate PC/NextPC
reg [7:0] PC;
reg [7:0] NextPC;
wire MW;
// ADD YOUR CODE BELOW THIS LINE
wire [2:0] SA;
wire [2:0] SB;
wire [2:0] DR;
wire LD;
wire [7:0] DataA;
wire [7:0] DataB;
wire [7:0] DataC;
wire [7:0] DataD;
wire [7:0] ALUB;
wire [7:0] IMM_EXT;
wire [5:0] IMM;
wire MB;
wire [2:0] FS;
wire MD;
wire HALT;
wire H;
wire [5:0] OFF;
wire MP;
wire [2:0] BS;
wire N;
wire Z;
wire [7:0] OFF_EXT;
registerFile regfile(
.SA(SA),
.SB(SB),
.DR(DR),
.D_IN(DataC),
.LD(LD),
.RESET(RESET),
.DataA(DataA),
.DataB(DataB),
.CLK(CLK)
);
decoder hyperwave(
.INST(Iin),
.DR(DR),
.SA(SA),
.SB(SB),
.IMM(IMM),
.MB(MB),
.FS(FS),
.MD(MD),
.LD(LD),
.MW(MW),
.BS(BS),
.OFF(OFF),
.HALT(HALT)
);
alu aluminum(
.A(DataA),
.B(ALUB),
.OP(FS),
.N(N),
.Z(Z),
.Y(DataD),
.C(),
.V(),
.HEX0(),
.HEX1(),
.HEX2(),
.HEX3(),
.HEX4(),
.HEX5(),
.HEX6(),
.HEX7()
);
signExtend theExtendables(
.IN(IMM),
.OUT(IMM_EXT)
);
eight_to_one_mux #(.WIDTH(1)) brancher(
.A(Z),
.B(~Z),
.C(~N),
.D(N),
.E(1'b0),
.F(1'b0),
.G(1'b0),
.H(1'b0),
.SEL(BS),
.Y(MP)
);
halt_logic halting_problem(
.CLK(CLK),
.HALT(HALT),
.EN_L(EN_L),
.H(H)
);
assign OFF_EXT[7] = OFF[5];
assign OFF_EXT[6:1] = OFF;
assign OFF_EXT[0] = 1'b0;
assign ALUB = MB ? IMM_EXT : DataB;
assign DataC = MD ? Din : DataD;
always @(posedge CLK) begin
if (RESET) begin
PC = 8'b0;
end else begin
PC = NextPC;
end
end
always @(*) begin
if (H) begin
NextPC = PC;
end else if (MP) begin
NextPC = PC + 8'd2 + OFF_EXT;
end else begin
NextPC = PC + 8'd2;
end
end
// ADD YOUR CODE ABOVE THIS LINE
endmodule
|
module crc_tb;
// Inputs
reg [0:0] data_in;
reg crc_en;
reg rst;
reg clk;
// Outputs
wire [15:0] crc_out;
// Instantiate the Unit Under Test (UUT)
crc uut (
.data_in(data_in),
.crc_en(crc_en),
.crc_out(crc_out),
.rst(rst),
.clk(clk)
);
initial begin
// Initialize Inputs
data_in = 0;
crc_en = 0;
rst = 1;
clk = 0;
toggle_clk;
rst = 0;
toggle_clk;
zero;
zero;
one;
one;
zero;
zero;
zero;
one;
zero;
one;
zero;
zero;
zero;
one;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
toggle_clk;
end
task one;
begin
data_in = 1;
crc_en = 1;
#10 clk = ~clk;
#10 clk = ~clk;
crc_en = 0;
end
endtask
task zero;
begin
data_in = 0;
crc_en = 1;
#10 clk = ~clk;
#10 clk = ~clk;
crc_en = 0;
end
endtask
task toggle_clk;
begin
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
end
endtask
endmodule
|
module axis_eth_fcs_check_64
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [63:0] s_axis_tdata,
input wire [7:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* AXI output
*/
output wire [63:0] m_axis_tdata,
output wire [7:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Status
*/
output wire busy,
output wire error_bad_fcs
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1,
STATE_LAST = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg shift_in;
reg shift_reset;
reg [7:0] last_cycle_tkeep_reg = 8'd0, last_cycle_tkeep_next;
reg last_cycle_tuser_reg = 1'b0, last_cycle_tuser_next;
reg [63:0] s_axis_tdata_d0 = 64'd0;
reg [7:0] s_axis_tkeep_d0 = 8'd0;
reg s_axis_tvalid_d0 = 1'b0;
reg s_axis_tuser_d0 = 1'b0;
reg busy_reg = 1'b0;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
reg [31:0] crc_state3 = 32'hFFFFFFFF;
wire [31:0] crc_next0;
wire [31:0] crc_next1;
wire [31:0] crc_next2;
wire [31:0] crc_next3;
wire [31:0] crc_next7;
wire crc_valid0 = crc_next0 == ~32'h2144df1c;
wire crc_valid1 = crc_next1 == ~32'h2144df1c;
wire crc_valid2 = crc_next2 == ~32'h2144df1c;
wire crc_valid3 = crc_next3 == ~32'h2144df1c;
// internal datapath
reg [63:0] m_axis_tdata_int;
reg [7:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign busy = busy_reg;
assign error_bad_fcs = error_bad_fcs_reg;
wire last_cycle = state_reg == STATE_LAST;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(last_cycle ? s_axis_tdata_d0[39:32] : s_axis_tdata[7:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next0)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(16),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(last_cycle ? s_axis_tdata_d0[47:32] : s_axis_tdata[15:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next1)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(24),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(last_cycle ? s_axis_tdata_d0[55:32] : s_axis_tdata[23:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next2)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(last_cycle ? s_axis_tdata_d0[63:32] : s_axis_tdata[31:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next3)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(s_axis_tdata[63:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next7)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
shift_in = 1'b0;
shift_reset = 1'b0;
last_cycle_tkeep_next = last_cycle_tkeep_reg;
last_cycle_tuser_next = last_cycle_tuser_reg;
s_axis_tready_next = 1'b0;
m_axis_tdata_int = 64'd0;
m_axis_tkeep_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
error_bad_fcs_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
s_axis_tready_next = m_axis_tready_int_early;
reset_crc = 1'b1;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = s_axis_tkeep_d0;
m_axis_tvalid_int = s_axis_tvalid_d0 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
reset_crc = 1'b0;
update_crc = 1'b1;
if (s_axis_tlast) begin
if (s_axis_tkeep[7:4] == 0) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
m_axis_tkeep_int = {s_axis_tkeep[3:0], 4'b1111};
if ((s_axis_tkeep[3:0] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep[3:0] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep[3:0] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep[3:0] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
last_cycle_tkeep_next = {4'b0000, s_axis_tkeep[7:4]};
last_cycle_tuser_next = s_axis_tuser;
s_axis_tready_next = 1'b0;
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = s_axis_tkeep_d0;
m_axis_tvalid_int = s_axis_tvalid_d0 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
update_crc = 1'b1;
if (s_axis_tlast) begin
if (s_axis_tkeep[7:4] == 0) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
m_axis_tkeep_int = {s_axis_tkeep[3:0], 4'b1111};
if ((s_axis_tkeep[3:0] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep[3:0] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep[3:0] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep[3:0] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
last_cycle_tkeep_next = {4'b0000, s_axis_tkeep[7:4]};
last_cycle_tuser_next = s_axis_tuser;
s_axis_tready_next = 1'b0;
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_LAST: begin
// last cycle
s_axis_tready_next = 1'b0;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = last_cycle_tkeep_reg;
m_axis_tvalid_int = s_axis_tvalid_d0;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = last_cycle_tuser_reg;
if ((s_axis_tkeep_d0[7:4] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep_d0[7:4] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep_d0[7:4] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep_d0[7:4] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
if (m_axis_tready_int_reg) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_axis_tready_reg <= 1'b0;
busy_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
s_axis_tvalid_d0 <= 1'b0;
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
s_axis_tready_reg <= s_axis_tready_next;
busy_reg <= state_next != STATE_IDLE;
error_bad_fcs_reg <= error_bad_fcs_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next7;
crc_state3 <= crc_next3;
end
if (shift_reset) begin
s_axis_tvalid_d0 <= 1'b0;
end else if (shift_in) begin
s_axis_tvalid_d0 <= s_axis_tvalid;
end
end
last_cycle_tkeep_reg <= last_cycle_tkeep_next;
last_cycle_tuser_reg <= last_cycle_tuser_next;
if (shift_in) begin
s_axis_tdata_d0 <= s_axis_tdata;
s_axis_tkeep_d0 <= s_axis_tkeep;
s_axis_tuser_d0 <= s_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_axis_tdata_reg = 64'd0;
reg [7:0] m_axis_tkeep_reg = 8'd0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_axis_tkeep_reg = 8'd0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = m_axis_tkeep_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
module scdata_ctr_io(/*AUTOARG*/
// Outputs
so, scdata_sctag_decc_c6_ctr, scdata_decc_out_c6,
cache_decc_in_c3, cache_col_offset_c3, cache_word_en_c3,
cache_way_sel_c3_0, cache_set_c3_0, cache_wr_en_c3_0,
cache_way_sel_c3_1, cache_set_c3_1, cache_wr_en_c3_1,
cache_way_sel_c3_2, cache_set_c3_2, cache_wr_en_c3_2,
cache_way_sel_c3_3, cache_set_c3_3, cache_wr_en_c3_3,
// Inputs
sctag_scdata_way_sel_c2_buf, sctag_scdata_rd_wr_c2_buf,
sctag_scdata_set_c2_buf, sctag_scdata_col_offset_c2_buf,
sctag_scdata_word_en_c2_buf, sctag_scdata_fbrd_c3_buf,
scbuf_scdata_fbdecc_c5, sctag_scdata_fb_hit_c3_buf,
sctag_scdata_stdecc_c2_buf, cache_decc_out_c5, rclk, se, si
);
input [11:0] sctag_scdata_way_sel_c2_buf; // way select
input sctag_scdata_rd_wr_c2_buf; // Rd/WRbar
input [9:0] sctag_scdata_set_c2_buf; // index
input [3:0] sctag_scdata_col_offset_c2_buf; // 16B column that is accessed
input [15:0] sctag_scdata_word_en_c2_buf; // word enables for stores
input sctag_scdata_fbrd_c3_buf; // if fill 1 else 0
input [623:0] scbuf_scdata_fbdecc_c5;
input sctag_scdata_fb_hit_c3_buf; // use bypass data from the Fill Buffer.
input [77:0] sctag_scdata_stdecc_c2_buf; // store data from sctag
input [623:0] cache_decc_out_c5; // data output from memory array
input rclk, se, si;
output so;
output [155:0] scdata_sctag_decc_c6_ctr;
output [623:0] scdata_decc_out_c6;
output [623:0] cache_decc_in_c3;
output [3:0] cache_col_offset_c3;
output [15:0] cache_word_en_c3;
output [11:0] cache_way_sel_c3_0;
output [9:0] cache_set_c3_0;
output cache_wr_en_c3_0;
output [11:0] cache_way_sel_c3_1;
output [9:0] cache_set_c3_1;
output cache_wr_en_c3_1;
output [11:0] cache_way_sel_c3_2;
output [9:0] cache_set_c3_2;
output cache_wr_en_c3_2;
output [11:0] cache_way_sel_c3_3;
output [9:0] cache_set_c3_3;
output cache_wr_en_c3_3;
wire [11:0] cache_way_sel_c3;
wire [9:0] cache_set_c3;
wire cache_wr_en_c3;
wire [77:0] st_decc_out_c3;
wire [155:0] scdata_sctag_decc_c5;
wire sel_decc_c5_23;
wire [155:0] decc_c5_01;
wire [155:0] decc_c5_23;
wire [3:0] cache_col_offset_c4, cache_col_offset_c5 ;
wire cache_sel_fbdecc_c4, cache_sel_fbdecc_c5 ;
wire cache_fb_hit_c4, cache_fb_hit_c5 ;
wire [155:0] scdata_sctag_decc_c6_ctr ;
wire [623:0] rd_decc_out_c5;
wire [623:0] scdata_decc_out_c5;
wire [623:0] scdata_decc_out_c6;
// way selects
dff_s #(12) ff_cache_way_sel_c3 (.q(cache_way_sel_c3[11:0]),
.din(sctag_scdata_way_sel_c2_buf[11:0]),
.clk(rclk), .se(se), .si(), .so());
assign cache_way_sel_c3_0 = cache_way_sel_c3;
assign cache_way_sel_c3_1 = cache_way_sel_c3;
assign cache_way_sel_c3_2 = cache_way_sel_c3;
assign cache_way_sel_c3_3 = cache_way_sel_c3;
// set
dff_s #(10) ff_cache_set_c3 (.q(cache_set_c3[9:0]),
.din(sctag_scdata_set_c2_buf[9:0]),
.clk(rclk), .se(se), .si(), .so());
assign cache_set_c3_0 = cache_set_c3;
assign cache_set_c3_1 = cache_set_c3;
assign cache_set_c3_2 = cache_set_c3;
assign cache_set_c3_3 = cache_set_c3;
// col offset
dff_s #(4) ff_cache_col_offset_c3 (.q(cache_col_offset_c3[3:0]),
.din(sctag_scdata_col_offset_c2_buf[3:0]),
.clk(rclk), .se(se), .si(), .so());
dff_s #(4) ff_cache_col_offset_c4 (.q(cache_col_offset_c4[3:0]),
.din(cache_col_offset_c3[3:0]),
.clk(rclk), .se(se), .si(), .so());
dff_s #(4) ff_cache_col_offset_c5 (.q(cache_col_offset_c5[3:0]),
.din(cache_col_offset_c4[3:0]),
.clk(rclk), .se(se), .si(), .so());
// word enables for writes
dff_s #(16) ff_cache_word_en_c3 (.q(cache_word_en_c3[15:0]),
.din(sctag_scdata_word_en_c2_buf[15:0]),
.clk(rclk), .se(se), .si(), .so());
// write enable into cache
dff_s #(1) ff_cache_wr_en_c3 (.q(cache_wr_en_c3),
.din(~sctag_scdata_rd_wr_c2_buf),
.clk(rclk), .se(se), .si(), .so());
assign cache_wr_en_c3_0 = cache_wr_en_c3;
assign cache_wr_en_c3_1 = cache_wr_en_c3;
assign cache_wr_en_c3_2 = cache_wr_en_c3;
assign cache_wr_en_c3_3 = cache_wr_en_c3;
// sel fill data instead of store data.
dff_s #(1) ff_cache_sel_fbdecc_c4 (.q(cache_sel_fbdecc_c4),
.din(sctag_scdata_fbrd_c3_buf),
.clk(rclk), .se(se), .si(), .so());
dff_s #(1) ff_cache_sel_fbdecc_c5 (.q(cache_sel_fbdecc_c5),
.din(cache_sel_fbdecc_c4),
.clk(rclk), .se(se), .si(), .so());
// sel fill buffer data over l2$ data.
dff_s #(1) ff_cache_fb_hit_c4 (.q(cache_fb_hit_c4),
.din(sctag_scdata_fb_hit_c3_buf),
.clk(rclk), .se(se), .si(), .so());
dff_s #(1) ff_cache_fb_hit_c5 (.q(cache_fb_hit_c5),
.din(cache_fb_hit_c4),
.clk(rclk), .se(se), .si(), .so());
// store data
dff_s #(78) ff_st_decc_out_c3 (.q(st_decc_out_c3[77:0]),
.din(sctag_scdata_stdecc_c2_buf[77:0]),
.clk(rclk), .se(se), .si(), .so());
mux2ds #(624) mux_cache_decc_in_c3 (.dout(cache_decc_in_c3[623:0]),
.in0({8{st_decc_out_c3[77:0]}}),
.in1(scbuf_scdata_fbdecc_c5[623:0]),
.sel0(~cache_sel_fbdecc_c5),
.sel1(cache_sel_fbdecc_c5));
dff_s #(156) ff_scdata_sctag_decc_c6 (.q(scdata_sctag_decc_c6_ctr[155:0]),
.din(scdata_sctag_decc_c5[155:0]),
.clk(rclk), .se(se), .si(), .so());
mux2ds #(624) mux_rd_decc_out_c5 (.dout(rd_decc_out_c5[623:0]),
.in0(cache_decc_out_c5[623:0]),
.in1(scbuf_scdata_fbdecc_c5[623:0]),
.sel0(~cache_fb_hit_c5),
.sel1(cache_fb_hit_c5));
assign scdata_decc_out_c5[623:0] = rd_decc_out_c5[623:0];
dff_s #(624) ff_scdata_decc_out_c6 (.q(scdata_decc_out_c6[623:0]),
.din(scdata_decc_out_c5[623:0]),
.clk(rclk), .se(se), .si(), .so());
////////////////////////////////////////////////////////////////////////
// The 64B-16B mux will be performed in the full custom data array.
// if the col offsets are non one hot, sctag will cause the hold signal
// to be high causing the output mux to hold its old value.
////////////////////////////////////////////////////////////////////////
assign sel_decc_c5_23 = cache_col_offset_c5[3] || cache_col_offset_c5[2];
mux2ds #(156) mux_decc_c5_01 (.dout(decc_c5_01[155:0]),
.in0(rd_decc_out_c5[155:0]),
.in1(rd_decc_out_c5[311:156]),
.sel0(cache_col_offset_c5[0]),
.sel1(~cache_col_offset_c5[0]));
mux2ds #(156) mux_decc_c5_23 (.dout(decc_c5_23[155:0]),
.in0(rd_decc_out_c5[467:312]),
.in1(rd_decc_out_c5[623:468]),
.sel0(cache_col_offset_c5[2]),
.sel1(~cache_col_offset_c5[2]));
mux2ds #(156) mux_scdata_sctag_decc_c5 (.dout(scdata_sctag_decc_c5[155:0]),
.in0(decc_c5_01[155:0]),
.in1(decc_c5_23[155:0]),
.sel0(~sel_decc_c5_23),
.sel1(sel_decc_c5_23));
endmodule
|
module sky130_fd_sc_ms__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module ff_jbi_sc1_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
module router #(
parameter X_LOCAL = 2,
parameter Y_LOCAL = 2,
parameter X_WIDTH = 2,
parameter Y_WIDTH = 2
)
(
input wire clk,
input wire reset,
// -- puertos de entrada ------------------------------------- >>>>>
output wire credit_out_xpos_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_xpos_din,
output wire credit_out_ypos_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_ypos_din,
output wire credit_out_xneg_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_xneg_din,
output wire credit_out_yneg_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_yneg_din,
output wire credit_out_pe_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_pe_din,
// -- puertos de salida -------------------------------------- >>>>>
input wire credit_in_xpos_din,
output wire [`CHANNEL_WIDTH-1:0] channel_xpos_dout,
input wire credit_in_ypos_din,
output wire [`CHANNEL_WIDTH-1:0] channel_ypos_dout,
input wire credit_in_xneg_din,
output wire [`CHANNEL_WIDTH-1:0] channel_xneg_dout,
input wire credit_in_yneg_din,
output wire [`CHANNEL_WIDTH-1:0] channel_yneg_dout,
input wire credit_in_pe_din,
output wire [`CHANNEL_WIDTH-1:0] channel_pe_dout
);
/*
-- Instancia :: Camino de Control
-- Descripcion: Top level para logica de control. En este modulo
contiene instancias para los modulos:
-- control de enlace (link controller)
-- selector
-- planificador de salida (outport scheduler)
Todas las salidas del modulo se conectan al camino de
datos con excepcion de las terminales para la recepcion/
transmicion de creditos.
La señales IO se agrupan en arreglos para facilitar la
interconexion.
Los puertos buffer_xxxx son el puente de comunicacion
con el camino de datos. Se utilizan para la transmision
del campo 'destino' para el calculo de ruta.
*/
// -- Desglose de Señales ------------------------------------ >>>>>
// -- Entrada :: Dupla (x,y) desde buffer ---------------- >>>>>
wire [29:24] buffer_xpos;
wire [29:24] buffer_ypos;
wire [29:24] buffer_xneg;
wire [29:24] buffer_yneg;
wire [29:24] buffer_pe;
// -- Entrada :: Campo 'done' desde buffer---------------- >>>>>
wire buffer_done_xpos;
wire buffer_done_ypos;
wire buffer_done_xneg;
wire buffer_done_yneg;
wire buffer_done_pe;
// -- Salida :: Señales de Escritura/Lectura a Buffer ---- >>>>>
wire [4:0] write_strobe;
wire [4:0] read_strobe;
// -- Salida :: Señales de Configuracion de XBAR --------- >>>>>
wire [3:0] xbar_conf_vector_xpos;
wire [3:0] xbar_conf_vector_ypos;
wire [3:0] xbar_conf_vector_xneg;
wire [3:0] xbar_conf_vector_yneg;
wire [3:0] xbar_conf_vector_pe;
// -- Instancia :: Camino de Control ------------------------- >>>>>
control_path
#(
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL),
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH)
)
camino_de_control
(
.clk (clk),
.reset (reset),
// -- segmentos de puertos de entrada -------------------- >>>>>
.credit_out_xpos_dout (credit_out_xpos_dout),
.input_channel_xpos_din (channel_xpos_din[31:24]),
.credit_out_ypos_dout (credit_out_ypos_dout),
.input_channel_ypos_din (channel_ypos_din[31:24]),
.credit_out_xneg_dout (credit_out_xneg_dout),
.input_channel_xneg_din (channel_xneg_din[31:24]),
.credit_out_yneg_dout (credit_out_yneg_dout),
.input_channel_yneg_din (channel_yneg_din[31:24]),
.credit_out_pe_dout (credit_out_pe_dout),
.input_channel_pe_din (channel_pe_din[31:24]),
// -- puertos de recepcion de creditos ------------------- >>>>>
.credit_in_xpos_din (credit_in_xpos_din),
.credit_in_ypos_din (credit_in_ypos_din),
.credit_in_xneg_din (credit_in_xneg_din),
.credit_in_yneg_din (credit_in_yneg_din),
.credit_in_pe_din (credit_in_pe_din),
// -- señales de entrada desde el camino de datos -------- >>>>>
.buffer_xpos_din (buffer_xpos),
.done_buffer_xpos_din (buffer_done_xpos),
.buffer_ypos_din (buffer_ypos),
.done_buffer_ypos_din (buffer_done_ypos),
.buffer_xneg_din (buffer_xneg),
.done_buffer_xneg_din (buffer_done_xneg),
.buffer_yneg_din (buffer_yneg),
.done_buffer_yneg_din (buffer_done_yneg),
.buffer_pe_din (buffer_pe),
.done_buffer_pe_din (buffer_done_pe),
// -- señales de salida a camino de datos ---------------- >>>>>
.write_strobe_dout (write_strobe),
.read_strobe_dout (read_strobe),
.xbar_conf_vector_xpos_dout (xbar_conf_vector_xpos),
.xbar_conf_vector_ypos_dout (xbar_conf_vector_ypos),
.xbar_conf_vector_xneg_dout (xbar_conf_vector_xneg),
.xbar_conf_vector_yneg_dout (xbar_conf_vector_yneg),
.xbar_conf_vector_pe_dout (xbar_conf_vector_pe)
);
/*
-- Instancia :: Camino de Datos
-- Descripcion: Top level para la infraestructura de manejo de datos a
traves del router. El modulo incluye las instancias de:
-- Colas de almacenamiento (Input Queue)
-- Crossbar (switch_fabric)
El modulo proporciona los puertos de entrada y salida
del router. Todas las señales de control son
proporcionadas por el modulo 'control_path'.
Los puertos buffer_xxxx son el puente de comunicacion
con el camino de datos. Se utilizan para la transmision
del campo 'destino' para el calculo de ruta.
*/
data_path camino_de_datos
(
.clk (clk),
.reset (reset),
// -- input -------------------------------------------------- >>>>>
.channel_xpos_din (channel_xpos_din),
.channel_ypos_din (channel_ypos_din),
.channel_xneg_din (channel_xneg_din),
.channel_yneg_din (channel_yneg_din),
.channel_pe_din (channel_pe_din),
.write_strobe_din (write_strobe),
.read_strobe_din (read_strobe),
.xbar_conf_vector_xpos_din (xbar_conf_vector_xpos),
.xbar_conf_vector_ypos_din (xbar_conf_vector_ypos),
.xbar_conf_vector_xneg_din (xbar_conf_vector_xneg),
.xbar_conf_vector_yneg_din (xbar_conf_vector_yneg),
.xbar_conf_vector_pe_din (xbar_conf_vector_pe),
// -- output ------------------------------------------------- >>>>>
.buffer_xpos_dout (buffer_xpos),
.buffer_ypos_dout (buffer_ypos),
.buffer_xneg_dout (buffer_xneg),
.buffer_yneg_dout (buffer_yneg),
.buffer_pe_dout (buffer_pe),
.done_buffer_xpos_dout (buffer_done_xpos),
.done_buffer_ypos_dout (buffer_done_ypos),
.done_buffer_xneg_dout (buffer_done_xneg),
.done_buffer_yneg_dout (buffer_done_yneg),
.done_buffer_pe_dout (buffer_done_pe),
.channel_xpos_dout (channel_xpos_dout),
.channel_ypos_dout (channel_ypos_dout),
.channel_xneg_dout (channel_xneg_dout),
.channel_yneg_dout (channel_yneg_dout),
.channel_pe_dout (channel_pe_dout)
);
endmodule
|
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 D = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 D = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 D = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__dlxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
|
module framing_encoding_test;
wire framing_encoding_out;
wire framing_encoding_out_valid;
reg [7:0] phr_psdu_in;
reg phr_psdu_in_valid;
reg clk;
reg reset_n;
initial begin
$monitor($time, " indicator: %b, framing_out: %h, whiting_out: %h, serializing_out: %h",
framing_encoding_out_valid,
u0framing_encoding.framing_crc_out,
u0framing_encoding.whiting_out,
framing_encoding_out);
end
framing_encoding u0framing_encoding(
.framing_encoding_out (framing_encoding_out),
.framing_encoding_out_valid (framing_encoding_out_valid),
.phr_psdu_in (phr_psdu_in),
.phr_psdu_in_valid (phr_psdu_in_valid),
.clk (clk),
.reset_n (reset_n)
);
// stop simulation after 20000us
initial
begin
#20000 $finish;
end
// generate data input signal
initial
begin
phr_psdu_in=8'h00;
#500 phr_psdu_in=8'h07;
#100 phr_psdu_in=8'h03;
#100 phr_psdu_in=8'h01;
#100 phr_psdu_in=8'h05;
#100 phr_psdu_in=8'h21;
#100 phr_psdu_in=8'h43;
#100 phr_psdu_in=8'h65;
#100 phr_psdu_in=8'h87;
end
// generate phr_psdu_in_valid signal
initial
begin
phr_psdu_in_valid =1'b0;
#500 phr_psdu_in_valid =1'b1;
#800 phr_psdu_in_valid =1'b0;
end
// generate clk signal
initial
begin
clk=1'b0;
end
always #50 clk=~clk;
// generate resrt_n signal
initial
begin
reset_n=1'b1;
# 520 reset_n=1'b0;
# 20 reset_n=1'b1;
end
endmodule
|
module AUDIO_IF(
avs_s1_clk,
avs_s1_reset,
avs_s1_address,
avs_s1_read,
avs_s1_readdata,
avs_s1_write,
avs_s1_writedata,
//
avs_s1_export_BCLK,
avs_s1_export_DACLRC,
avs_s1_export_DACDAT,
avs_s1_export_ADCLRC,
avs_s1_export_ADCDAT
);
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
`define DAC_LFIFO_ADDR 0
`define DAC_RFIFO_ADDR 1
`define ADC_LFIFO_ADDR 2
`define ADC_RFIFO_ADDR 3
`define CMD_ADDR 4
`define STATUS_ADDR 5
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input avs_s1_clk;
input avs_s1_reset;
input [2:0] avs_s1_address;
input avs_s1_read;
output [15:0] avs_s1_readdata;
input avs_s1_write;
input [15:0] avs_s1_writedata;
//
input avs_s1_export_BCLK;
input avs_s1_export_DACLRC;
output avs_s1_export_DACDAT;
input avs_s1_export_ADCLRC;
input avs_s1_export_ADCDAT;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// host
reg [15:0] reg_readdata;
reg fifo_clear;
// dac
wire dacfifo_full;
reg dacfifo_write;
reg [31:0] dacfifo_writedata;
// adc
wire adcfifo_empty;
reg adcfifo_read;
wire [31:0] adcfifo_readdata;
reg [31:0] data32_from_adcfifo;
reg [31:0] data32_from_adcfifo_2;
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
////////// fifo clear
always @ (posedge avs_s1_clk)
begin
if (avs_s1_reset)
fifo_clear <= 1'b0;
else if (avs_s1_write && (avs_s1_address == `CMD_ADDR))
fifo_clear <= avs_s1_writedata[0];
else if (fifo_clear)
fifo_clear <= 1'b0;
end
////////// write audio data(left&right) to dac-fifo
always @ (posedge avs_s1_clk)
begin
if (avs_s1_reset || fifo_clear)
begin
dacfifo_write <= 1'b0;
end
else if (avs_s1_write && (avs_s1_address == `DAC_LFIFO_ADDR))
begin
dacfifo_writedata[31:16] <= avs_s1_writedata;
dacfifo_write <= 1'b0;
end
else if (avs_s1_write && (avs_s1_address == `DAC_RFIFO_ADDR))
begin
dacfifo_writedata[15:0] <= avs_s1_writedata;
dacfifo_write <= 1'b1;
end
else
dacfifo_write <= 1'b0;
end
////////// response data to avalon-mm
always @ (negedge avs_s1_clk)
begin
if (avs_s1_reset || fifo_clear)
data32_from_adcfifo = 0;
else if (avs_s1_read && (avs_s1_address == `STATUS_ADDR))
reg_readdata <= {adcfifo_empty, dacfifo_full};
else if (avs_s1_read && (avs_s1_address == `ADC_LFIFO_ADDR))
reg_readdata <= data32_from_adcfifo[31:16];
else if (avs_s1_read && (avs_s1_address == `ADC_RFIFO_ADDR))
begin
reg_readdata <= data32_from_adcfifo[15:0];
data32_from_adcfifo <= data32_from_adcfifo_2;
end
end
////////// read audio data from adc fifo
always @ (negedge avs_s1_clk)
begin
if (avs_s1_reset)
begin
adcfifo_read <= 1'b0;
data32_from_adcfifo_2 <= 0;
end
else if ((avs_s1_address == `ADC_LFIFO_ADDR) & avs_s1_read & ~adcfifo_empty)
begin
adcfifo_read <= 1'b1;
end
else if (adcfifo_read)
begin
data32_from_adcfifo_2 = adcfifo_readdata;
adcfifo_read <= 1'b0;
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign avs_s1_readdata = reg_readdata;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
AUDIO_DAC DAC_Instance(
// host
.clk(avs_s1_clk),
.reset(avs_s1_reset),
.write(dacfifo_write),
.writedata(dacfifo_writedata),
.full(dacfifo_full),
.clear(fifo_clear),
// dac
.bclk(avs_s1_export_BCLK),
.daclrc(avs_s1_export_DACLRC),
.dacdat(avs_s1_export_DACDAT)
);
AUDIO_ADC ADC_Instance(
// host
.clk(avs_s1_clk),
.reset(avs_s1_reset),
.read(adcfifo_read),
.readdata(adcfifo_readdata),
.empty(adcfifo_empty),
.clear(fifo_clear),
// adc
.bclk(avs_s1_export_BCLK),
.adclrc(avs_s1_export_ADCLRC),
.adcdat(avs_s1_export_ADCDAT)
);
defparam
DAC_Instance.DATA_WIDTH = 32;
defparam
ADC_Instance.DATA_WIDTH = 32;
endmodule
|
module VGA_Audio_PLL (
areset,
inclk0,
c0,
c1,
c2);
input areset;
input inclk0;
output c0;
output c1;
output c2;
wire [5:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.areset (areset),
.clk (sub_wire0)
// synopsys translate_off
,
.scanclk (),
.pllena (),
.sclkout1 (),
.sclkout0 (),
.fbin (),
.scandone (),
.clkloss (),
.extclk (),
.clkswitch (),
.pfdena (),
.scanaclr (),
.clkena (),
.clkbad (),
.scandata (),
.enable1 (),
.scandataout (),
.extclkena (),
.enable0 (),
.scanwrite (),
.locked (),
.activeclock (),
.scanread ()
// synopsys translate_on
);
defparam
altpll_component.clk0_divide_by = 15,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 14,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 3,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 15,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 14,
altpll_component.clk2_phase_shift = "-9921",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "FAST";
endmodule
|
module or1200_except
(
// Clock and reset
clk, rst,
// Internal i/f
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss,
sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault,
sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze,
if_stall, if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,
extend_flush, except_flushpipe, except_type, except_start, except_started,
except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,
spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,
abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee,
dsx
);
//
// I/O
//
input clk;
input rst;
input sig_ibuserr;
input sig_dbuserr;
input sig_illegal;
input sig_align;
input sig_range;
input sig_dtlbmiss;
input sig_dmmufault;
input sig_int;
input sig_syscall;
input sig_trap;
input sig_itlbmiss;
input sig_immufault;
input sig_tick;
input sig_fp;
input fpcsr_fpee;
input ex_branch_taken;
input genpc_freeze;
input id_freeze;
input ex_freeze;
input wb_freeze;
input if_stall;
input [31:0] if_pc;
output [31:0] id_pc;
output [31:0] ex_pc;
output [31:0] wb_pc;
input [31:0] datain;
input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
input [24:0] du_dmr1;
input du_hwbkpt;
input du_hwbkpt_ls_r;
input epcr_we;
input eear_we;
input esr_we;
input pc_we;
output [31:0] epcr;
output [31:0] eear;
output [`OR1200_SR_WIDTH-1:0] esr;
input [`OR1200_SR_WIDTH-1:0] to_sr;
input sr_we;
input [`OR1200_SR_WIDTH-1:0] sr;
input [31:0] lsu_addr;
input id_flushpipe;
input ex_flushpipe;
output except_flushpipe;
output extend_flush;
output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
output except_start;
output except_started;
output [13:0] except_stop;
output [13:0] except_trig;
input ex_void;
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
output [31:0] spr_dat_ppc;
output [31:0] spr_dat_npc;
output abort_ex;
output abort_mvspr;
input icpu_ack_i;
input icpu_err_i;
input dcpu_ack_i;
input dcpu_err_i;
output dsx;
//
// Internal regs and wires
//
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type /* verilator public */;
reg [31:0] id_pc /* verilator public */;
reg id_pc_val;
reg [31:0] ex_pc /* verilator public */;
reg ex_pc_val;
reg [31:0] wb_pc /* verilator public */;
reg [31:0] dl_pc;
reg [31:0] epcr;
reg [31:0] eear;
reg [`OR1200_SR_WIDTH-1:0] esr;
reg [2:0] id_exceptflags;
reg [2:0] ex_exceptflags;
reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
reg extend_flush;
reg extend_flush_last;
reg ex_dslot /* verilator public */;
reg delayed1_ex_dslot;
reg delayed2_ex_dslot;
wire except_started;
wire except_flushpipe /* verilator public */;
reg [2:0] delayed_iee;
reg [2:0] delayed_tee;
wire int_pending;
wire tick_pending;
wire fp_pending;
wire range_pending;
reg dsx;
reg trace_trap ;
reg ex_freeze_prev;
reg sr_ted_prev;
reg dsr_te_prev;
reg dmr1_st_prev ;
reg dmr1_bt_prev ;
wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
//
// Simple combinatorial logic
//
assign except_started = extend_flush & except_start;
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] |
(sr_we & to_sr[`OR1200_SR_IEE]))
& id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken
& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] |
(sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val
& delayed_tee[2] & ~ex_freeze & ~ex_branch_taken
& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken
& ~ex_dslot;
`ifdef OR1200_IMPL_OVE
assign range_pending = sig_range & sr[`OR1200_SR_OVE] & ~ex_freeze &
~ex_branch_taken & ~ex_dslot;
`else
assign range_pending = 0;
`endif
// Abort write into RF by load & other instructions
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align |
sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
& !sr_ted & !dsr_te);
// abort spr read/writes
assign abort_mvspr = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
& !sr_ted & !dsr_te) ;
assign spr_dat_ppc = wb_pc;
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
//
// Order defines exception detection priority
//
assign except_trig = {
ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
range_pending & ~du_dsr[`OR1200_DU_DSR_RE],
fp_pending & ~du_dsr[`OR1200_DU_DSR_FPE],
int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE]
};
wire trace_cond = !ex_freeze && !ex_void && (1'b0
`ifdef OR1200_DU_DMR1_ST
|| dmr1_st
`endif
`ifdef OR1200_DU_DMR1_BT
|| ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
`endif
);
assign except_stop = {
tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
int_pending & du_dsr[`OR1200_DU_DSR_IE],
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
sig_align & du_dsr[`OR1200_DU_DSR_AE],
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
range_pending & du_dsr[`OR1200_DU_DSR_RE],
sig_trap & du_dsr[`OR1200_DU_DSR_TE],
fp_pending & du_dsr[`OR1200_DU_DSR_FPE],
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
};
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
trace_trap <= 1'b0 ;
end
else if (!(trace_trap && !ex_pc_val)) begin
trace_trap <= trace_cond & !dsr_te & !sr_ted ;
end
end
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
ex_freeze_prev <= 1'b0 ;
sr_ted_prev <= 1'b0 ;
dsr_te_prev <= 1'b0 ;
dmr1_st_prev <= 1'b0 ;
dmr1_bt_prev <= 1'b0 ;
end
else begin
ex_freeze_prev <= ex_freeze ;
if (!ex_freeze_prev || ex_void) begin
sr_ted_prev <= sr [`OR1200_SR_TED ] ;
dsr_te_prev <= du_dsr [`OR1200_DU_DSR_TE ] ;
dmr1_st_prev <= du_dmr1[`OR1200_DU_DMR1_ST] ;
dmr1_bt_prev <= du_dmr1[`OR1200_DU_DMR1_BT] ;
end
end
end
`ifdef verilator
// Function to access wb_pc (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_wb_pc;
// verilator public
get_wb_pc = wb_pc;
endfunction // get_wb_pc
// Function to access id_pc (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_id_pc;
// verilator public
get_id_pc = id_pc;
endfunction // get_id_pc
// Function to access ex_pc (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_ex_pc;
// verilator public
get_ex_pc = ex_pc;
endfunction // get_ex_pc
// Function to access except_type[3:0] (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [3:0] get_except_type;
// verilator public
get_except_type = except_type;
endfunction // get_except_type
`endif
//
// PC and Exception flags pipelines
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
id_pc <= 32'd0;
id_pc_val <= 1'b0 ;
id_exceptflags <= 3'b000;
end
else if (id_flushpipe) begin
id_pc_val <= 1'b0 ;
id_exceptflags <= 3'b000;
end
else if (!id_freeze) begin
id_pc <= if_pc;
id_pc_val <= 1'b1 ;
id_exceptflags <= { sig_ibuserr, sig_itlbmiss, sig_immufault };
end
end
//
// delayed_iee
//
// SR[IEE] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_iee
// together with SR[IEE] enables interrupts once
// pipeline is again ready.
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
delayed_iee <= 3'b000;
else if (!sr[`OR1200_SR_IEE])
delayed_iee <= 3'b000;
else
delayed_iee <= {delayed_iee[1:0], 1'b1};
//
// delayed_tee
//
// SR[TEE] should not enable tick exceptions right away
// when it is restored with l.rfe. Instead delayed_tee
// together with SR[TEE] enables tick exceptions once
// pipeline is again ready.
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
delayed_tee <= 3'b000;
else if (!sr[`OR1200_SR_TEE])
delayed_tee <= 3'b000;
else
delayed_tee <= {delayed_tee[1:0], 1'b1};
//
// PC and Exception flags pipelines
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
ex_dslot <= 1'b0;
ex_pc <= 32'd0;
ex_pc_val <= 1'b0 ;
ex_exceptflags <= 3'b000;
delayed1_ex_dslot <= 1'b0;
delayed2_ex_dslot <= 1'b0;
end
else if (ex_flushpipe) begin
ex_dslot <= 1'b0;
ex_pc_val <= 1'b0 ;
ex_exceptflags <= 3'b000;
delayed1_ex_dslot <= 1'b0;
delayed2_ex_dslot <= 1'b0;
end
else if (!ex_freeze & id_freeze) begin
ex_dslot <= 1'b0;
ex_pc <= id_pc;
ex_pc_val <= id_pc_val ;
ex_exceptflags <= 3'b000;
delayed1_ex_dslot <= ex_dslot;
delayed2_ex_dslot <= delayed1_ex_dslot;
end
else if (!ex_freeze) begin
ex_dslot <= ex_branch_taken;
ex_pc <= id_pc;
ex_pc_val <= id_pc_val ;
ex_exceptflags <= id_exceptflags;
delayed1_ex_dslot <= ex_dslot;
delayed2_ex_dslot <= delayed1_ex_dslot;
end
end
//
// PC and Exception flags pipelines
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
wb_pc <= 32'd0;
dl_pc <= 32'd0;
end
else if (!wb_freeze) begin
wb_pc <= ex_pc;
dl_pc <= wb_pc;
end
end
//
// We have started execution of exception handler:
// 1. Asserted for 3 clock cycles
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
//
assign except_flushpipe = |except_trig & ~|state;
//
// Exception FSM that sequences execution of exception handler
//
// except_type signals which exception handler we start fetching in:
// 1. Asserted in next clock cycle after exception is recognized
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
state <= `OR1200_EXCEPTFSM_IDLE;
except_type <= `OR1200_EXCEPT_NONE;
extend_flush <= 1'b0;
epcr <= 32'b0;
eear <= 32'b0;
esr <= {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
extend_flush_last <= 1'b0;
dsx <= 1'b0;
end
else begin
`ifdef OR1200_CASE_DEFAULT
case (state) // synopsys parallel_case
`else
case (state) // synopsys full_case parallel_case
`endif
`OR1200_EXCEPTFSM_IDLE:
if (except_flushpipe) begin
state <= `OR1200_EXCEPTFSM_FLU1;
extend_flush <= 1'b1;
esr <= sr_we ? to_sr : sr;
casez (except_trig)
`ifdef OR1200_EXCEPT_ITLBMISS
14'b1?_????_????_????: begin
except_type <= `OR1200_EXCEPT_ITLBMISS;
eear <= ex_dslot ?
ex_pc : ex_pc;
epcr <= ex_dslot ?
wb_pc : ex_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_IPF
14'b01_????_????_????: begin
except_type <= `OR1200_EXCEPT_IPF;
eear <= ex_dslot ?
ex_pc : delayed1_ex_dslot ?
id_pc : delayed2_ex_dslot ?
id_pc : id_pc;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
id_pc : delayed2_ex_dslot ?
id_pc : id_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
14'b00_1???_????_????: begin // Insn. Bus Error
except_type <= `OR1200_EXCEPT_BUSERR;
eear <= ex_dslot ?
wb_pc : ex_pc;
epcr <= ex_dslot ?
wb_pc : ex_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_ILLEGAL
14'b00_01??_????_????: begin
except_type <= `OR1200_EXCEPT_ILLEGAL;
eear <= ex_pc;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
dl_pc : delayed2_ex_dslot ?
id_pc : ex_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_ALIGN
14'b00_001?_????_????: begin
except_type <= `OR1200_EXCEPT_ALIGN;
eear <= lsu_addr;
epcr <= ex_dslot ?
wb_pc : ex_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_DTLBMISS
14'b00_0001_????_????: begin
except_type <= `OR1200_EXCEPT_DTLBMISS;
eear <= lsu_addr;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
dl_pc : ex_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_TRAP
14'b00_0000_1???_????: begin
except_type <= `OR1200_EXCEPT_TRAP;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
id_pc : ex_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_SYSCALL
14'b00_0000_01??_????: begin
except_type <= `OR1200_EXCEPT_SYSCALL;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
id_pc : delayed2_ex_dslot ?
id_pc : id_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_DPF
14'b00_0000_001?_????: begin
except_type <= `OR1200_EXCEPT_DPF;
eear <= lsu_addr;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
dl_pc : ex_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
14'b00_0000_0001_????: begin // Data Bus Error
except_type <= `OR1200_EXCEPT_BUSERR;
eear <= lsu_addr;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
dl_pc : ex_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_RANGE
14'b00_0000_0000_1???: begin
except_type <= `OR1200_EXCEPT_RANGE;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
dl_pc : delayed2_ex_dslot ?
id_pc : ex_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_FLOAT
14'b00_0000_0000_01??: begin
except_type <= `OR1200_EXCEPT_FLOAT;
epcr <= id_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_INT
14'b00_0000_0000_001?: begin
except_type <= `OR1200_EXCEPT_INT;
epcr <= id_pc;
dsx <= ex_dslot;
end
`endif
`ifdef OR1200_EXCEPT_TICK
14'b00_0000_0000_0001: begin
except_type <= `OR1200_EXCEPT_TICK;
epcr <= id_pc;
dsx <= ex_dslot;
end
`endif
default:
except_type <= `OR1200_EXCEPT_NONE;
endcase
end
else if (pc_we) begin
state <= `OR1200_EXCEPTFSM_FLU1;
extend_flush <= 1'b1;
end
else begin
if (epcr_we)
epcr <= datain;
if (eear_we)
eear <= datain;
if (esr_we)
esr <= {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
end
`OR1200_EXCEPTFSM_FLU1:
if (icpu_ack_i | icpu_err_i | genpc_freeze)
state <= `OR1200_EXCEPTFSM_FLU2;
`OR1200_EXCEPTFSM_FLU2:
`ifdef OR1200_EXCEPT_TRAP
if (except_type == `OR1200_EXCEPT_TRAP) begin
state <= `OR1200_EXCEPTFSM_IDLE;
extend_flush <= 1'b0;
extend_flush_last <= 1'b0;
except_type <= `OR1200_EXCEPT_NONE;
end
else
`endif
state <= `OR1200_EXCEPTFSM_FLU3;
`OR1200_EXCEPTFSM_FLU3:
begin
state <= `OR1200_EXCEPTFSM_FLU4;
end
`OR1200_EXCEPTFSM_FLU4: begin
state <= `OR1200_EXCEPTFSM_FLU5;
extend_flush <= 1'b0;
extend_flush_last <= 1'b0; // damjan
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_EXCEPTFSM_FLU5: begin
`endif
if (!if_stall && !id_freeze) begin
state <= `OR1200_EXCEPTFSM_IDLE;
except_type <= `OR1200_EXCEPT_NONE;
extend_flush_last <= 1'b0;
end
end
endcase
end
end
endmodule
|
module SmallBpf_tb ();
parameter K0_SHIFT = 5; ///< K0 filter term = 2^-K0_SHIFT
parameter K1_SHIFT = 5; ///< K1 filter term = 2^-K1_SHIFT
parameter WIDTH = 16; ///< Width of data path
parameter CLAMP = 1; ///< Set to 1 to clamp the accumulators
parameter FREQ_RATE = 512000;
reg clk;
reg rst;
reg en;
reg signed [WIDTH-1:0] dataIn;
wire signed [WIDTH-1:0] dataOut;
integer i;
initial begin
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
dataIn = 'd0;
#2 rst = 1'b0;
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) dataIn = $rtoi($sin($itor(i)**2*3.14159/FREQ_RATE)*(2**(WIDTH-2)-1));
end
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) dataIn = $random();
end
$stop();
end
always #1 clk = ~clk;
SmallBpf #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uut (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataIn), ///< [WIDTH-1:0] Filter input
.dataOut(dataOut) ///< [WIDTH-1:0] Filter output
);
endmodule
|
module ClockManager(
(* buffer_type = "ibufg" *) input CLK_IN,
input RESET_IN,
output CLK_MAIN,
output reg RESET
);
parameter DELAY = 4;
reg [DELAY - 1:0] CNT_SLOW;
reg CLK_SLOW;
always @ (posedge CLK_IN)
if(RESET_IN)
CNT_SLOW <= 0;
else
CNT_SLOW <= CNT_SLOW + 1;
always @ (posedge CLK_IN)
if(RESET_IN)
begin
RESET <= 1'b1;
CLK_SLOW <= 1'b0;
end
else if(CNT_SLOW == (1 << DELAY) - 1)
begin
RESET <= 1'b0;
CLK_SLOW <= ~CLK_SLOW;
end
assign CLK_MAIN = CLK_IN;
endmodule
|
module PLLE4_BASE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer CLKFBOUT_MULT = 5,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN_PERIOD = 0.000,
parameter integer CLKOUT0_DIVIDE = 1,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter CLKOUTPHY_MODE = "VCO_2X",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUTPHY,
output LOCKED,
input CLKFBIN,
input CLKIN,
input CLKOUTPHYEN,
input PWRDWN,
input RST
);
// define constants
localparam MODULE_NAME = "PLLE4_BASE";
initial begin
#1;
if ($realtime == 0) begin
$display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME);
$display ("The simulator resolution must be set to 1ps or smaller. Instance %m");
#1 $finish;
end
end
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
PLLE4_ADV #(
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN_PERIOD(CLKIN_PERIOD),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUTPHY_MODE(CLKOUTPHY_MODE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.IS_CLKFBIN_INVERTED(IS_CLKFBIN_INVERTED),
.IS_CLKIN_INVERTED(IS_CLKIN_INVERTED),
.IS_PWRDWN_INVERTED(IS_PWRDWN_INVERTED),
.IS_RST_INVERTED(IS_RST_INVERTED),
.REF_JITTER(REF_JITTER),
.STARTUP_WAIT(STARTUP_WAIT)
) pll_adv_1 (
.CLKFBOUT (CLKFBOUT),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUTPHY (CLKOUTPHY),
.CLKOUTPHYEN (CLKOUTPHYEN),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.LOCKED (LOCKED),
.CLKFBIN (CLKFBIN),
.CLKIN (CLKIN),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PWRDWN(PWRDWN),
.RST (RST)
);
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKIN, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUTPHY, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKIN, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUTPHY, 0:0:0, notifier);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
|
module sky130_fd_sc_ms__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module hps_design (
input wire clk_clk, // clk.clk
output wire [14:0] hps_0_ddr_mem_a, // hps_0_ddr.mem_a
output wire [2:0] hps_0_ddr_mem_ba, // .mem_ba
output wire hps_0_ddr_mem_ck, // .mem_ck
output wire hps_0_ddr_mem_ck_n, // .mem_ck_n
output wire hps_0_ddr_mem_cke, // .mem_cke
output wire hps_0_ddr_mem_cs_n, // .mem_cs_n
output wire hps_0_ddr_mem_ras_n, // .mem_ras_n
output wire hps_0_ddr_mem_cas_n, // .mem_cas_n
output wire hps_0_ddr_mem_we_n, // .mem_we_n
output wire hps_0_ddr_mem_reset_n, // .mem_reset_n
inout wire [31:0] hps_0_ddr_mem_dq, // .mem_dq
inout wire [3:0] hps_0_ddr_mem_dqs, // .mem_dqs
inout wire [3:0] hps_0_ddr_mem_dqs_n, // .mem_dqs_n
output wire hps_0_ddr_mem_odt, // .mem_odt
output wire [3:0] hps_0_ddr_mem_dm, // .mem_dm
input wire hps_0_ddr_oct_rzqin, // .oct_rzqin
output wire hps_0_io_hps_io_emac1_inst_TX_CLK, // hps_0_io.hps_io_emac1_inst_TX_CLK
output wire hps_0_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_0_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_0_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_0_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_0_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_0_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_0_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_0_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_0_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_0_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_0_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_0_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_0_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_0_io_hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_0_io_hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_0_io_hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_0_io_hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_0_io_hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_0_io_hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_0_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_0_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_0_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_0_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_0_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_0_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_0_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_0_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_0_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_0_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_0_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_0_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_0_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_0_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_0_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_0_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_0_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_0_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_0_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_0_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_0_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_0_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_0_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_0_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_0_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_0_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_0_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_0_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_0_io_hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_0_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_0_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_0_io_hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_0_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_0_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_0_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire ledr_export, // ledr.export
output wire pll_0_sdram_clk, // pll_0_sdram.clk
input wire reset_reset_n // reset.reset_n
);
wire pll_0_outclk0_clk; // pll_0:outclk_0 -> [hps_0:h2f_lw_axi_clk, mm_interconnect_0:pll_0_outclk0_clk, pio_0:clk, rst_controller:clk, rst_controller_001:clk]
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awburst
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlen
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_rready
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlen
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wid
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arcache
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wvalid
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_araddr
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arprot
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awprot
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arvalid
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awcache
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arid
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlock
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlock
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awaddr
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arburst
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arsize
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_bready
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wlast
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awid
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awsize
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awvalid
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:pio_0_reset_reset_bridge_in_reset_reset, pio_0:reset_n]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
wire hps_0_h2f_reset_reset; // hps_0:h2f_rst_n -> rst_controller_001:reset_in0
hps_design_hps_0 #(
.F2S_Width (0),
.S2F_Width (0)
) hps_0 (
.mem_a (hps_0_ddr_mem_a), // memory.mem_a
.mem_ba (hps_0_ddr_mem_ba), // .mem_ba
.mem_ck (hps_0_ddr_mem_ck), // .mem_ck
.mem_ck_n (hps_0_ddr_mem_ck_n), // .mem_ck_n
.mem_cke (hps_0_ddr_mem_cke), // .mem_cke
.mem_cs_n (hps_0_ddr_mem_cs_n), // .mem_cs_n
.mem_ras_n (hps_0_ddr_mem_ras_n), // .mem_ras_n
.mem_cas_n (hps_0_ddr_mem_cas_n), // .mem_cas_n
.mem_we_n (hps_0_ddr_mem_we_n), // .mem_we_n
.mem_reset_n (hps_0_ddr_mem_reset_n), // .mem_reset_n
.mem_dq (hps_0_ddr_mem_dq), // .mem_dq
.mem_dqs (hps_0_ddr_mem_dqs), // .mem_dqs
.mem_dqs_n (hps_0_ddr_mem_dqs_n), // .mem_dqs_n
.mem_odt (hps_0_ddr_mem_odt), // .mem_odt
.mem_dm (hps_0_ddr_mem_dm), // .mem_dm
.oct_rzqin (hps_0_ddr_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_0_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_0_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_0_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_0_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_0_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_0_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_0_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_0_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_0_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_0_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_0_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_0_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_0_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_0_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_0_io_hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_0_io_hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_0_io_hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_0_io_hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_0_io_hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_0_io_hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_0_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_0_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_0_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_0_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_0_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_0_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_0_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_0_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_0_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_0_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_0_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_0_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_0_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_0_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_0_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_0_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_0_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_0_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_0_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_0_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_0_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_0_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_0_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_0_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_0_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_0_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_0_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_0_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_0_io_hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_0_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_0_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_0_io_hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_0_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_0_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_0_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (hps_0_h2f_reset_reset), // h2f_reset.reset_n
.h2f_lw_axi_clk (pll_0_outclk0_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready) // .rready
);
hps_design_pio_0 pio_0 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.out_port (ledr_export) // external_connection.export
);
hps_design_pll_0 pll_0 (
.refclk (clk_clk), // refclk.clk
.rst (~reset_reset_n), // reset.reset
.outclk_0 (pll_0_outclk0_clk), // outclk0.clk
.outclk_1 (), // outclk1.clk
.outclk_2 (pll_0_sdram_clk), // outclk2.clk
.locked () // (terminated)
);
hps_design_mm_interconnect_0 mm_interconnect_0 (
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.pll_0_outclk0_clk (pll_0_outclk0_clk), // pll_0_outclk0.clk
.hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.pio_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // pio_0_reset_reset_bridge_in_reset.reset
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect) // .chipselect
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~hps_0_h2f_reset_reset), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
|
module test;
genvar i;
localparam nodes_p=7;
wire [nodes_p:0] wi_nets, ei_nets;
logic [nodes_p-1:0] pi_nets, po_nets;
logic clk_li, reset_li;
// program the barrier network
//
// WEP
localparam [nodes_p-1:0][2:0] ins_p = { 3'b001 /* east end node */
, 3'b011 /* east middle node */
, 3'b111 /* center node */
, 3'b101 /* west middle node */
, 3'b101 /* west middle node */
, 3'b101 /* west middle node */
, 3'b001 /* west end node */ };
localparam [nodes_p-1:0][1:0] outs_p = { 2'd2 /*node 6 W */
,2'd2 /*node 5 W */
,2'd3 /*node 4 X */
,2'd1 /*nodes 3 E */
,2'd1 /*nodes 2 E */
,2'd1 /*nodes 1 E */
,2'd1 /*nodes 0 E */
};
// 0 1 2 3 4
// ---> ---> ---> Wi ---> ---> Wi ---> --> Wi
// <--- node 0 <---- node 1 <--- Ei <---- node 2 <--- Ei <---- node 3 <--- Ei
//
// wire up the topology
for (i=0; i < nodes_p; i++)
begin: rof
bsg_barrier #(.dirs_p(3)) one
(.clk_i(clk_li)
,.reset_i(reset_li)
,.data_i({wi_nets[i+0],ei_nets[i+1], pi_nets[i]})
,.data_o({ei_nets[i+0],wi_nets[i+1], po_nets[i]})
,.src_r_i(ins_p[i])
,.dest_r_i(outs_p[i])
);
end
initial
begin
clk_li = 0;
while (1)
begin
#5 clk_li = ~clk_li;
end
end
// we set it up so we enter the next barrier immediately after the first
bsg_dff_reset #(.width_p(nodes_p)) dff
(.clk_i(clk_li)
,.reset_i(reset_li)
,.data_i(~po_nets)
,.data_o(pi_nets)
);
always @(negedge clk_li)
begin
$display("%d Pi=%b, Wi=%b Ei=%b Po=%b",$time, pi_nets, wi_nets, ei_nets, po_nets);
// when pi==po, we know the barrier is completed
// so we can xor the pi bit to enter the barrier
for (integer i = 0; i < nodes_p; i++)
if (pi_nets[i] == po_nets[i])
$display("%t %d: barrier completed",$time,i);
end
initial
begin
reset_li = 0;
#10
reset_li = 1;
#10
reset_li = 0;
#200
#200
$finish();
end
endmodule
|
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