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module tcp_ip_wrapper #(
parameter MAC_ADDRESS = 48'hE59D02350A00, // LSB first, 00:0A:35:02:9D:E5
parameter IP_ADDRESS = 32'h00000000,
parameter IP_SUBNET_MASK = 32'h00FFFFFF,
parameter IP_DEFAULT_GATEWAY = 32'h00000000,
parameter DHCP_EN = 0
)(
input aclk,
//input reset,
input aresetn,
// network interface streams
output AXI_M_Stream_TVALID,
input AXI_M_Stream_TREADY,
output[63:0] AXI_M_Stream_TDATA,
output[7:0] AXI_M_Stream_TKEEP,
output AXI_M_Stream_TLAST,
input AXI_S_Stream_TVALID,
output AXI_S_Stream_TREADY,
input[63:0] AXI_S_Stream_TDATA,
input[7:0] AXI_S_Stream_TKEEP,
input AXI_S_Stream_TLAST,
// memory rx cmd streams
output m_axis_rxread_cmd_TVALID,
input m_axis_rxread_cmd_TREADY,
output[71:0] m_axis_rxread_cmd_TDATA,
output m_axis_rxwrite_cmd_TVALID,
input m_axis_rxwrite_cmd_TREADY,
output[71:0] m_axis_rxwrite_cmd_TDATA,
// memory rx sts streams
input s_axis_rxread_sts_TVALID,
output s_axis_rxread_sts_TREADY,
input[7:0] s_axis_rxread_sts_TDATA,
input s_axis_rxwrite_sts_TVALID,
output s_axis_rxwrite_sts_TREADY,
input[31:0] s_axis_rxwrite_sts_TDATA,
// memory rx data streams
input s_axis_rxread_data_TVALID,
output s_axis_rxread_data_TREADY,
input[63:0] s_axis_rxread_data_TDATA,
input[7:0] s_axis_rxread_data_TKEEP,
input s_axis_rxread_data_TLAST,
output m_axis_rxwrite_data_TVALID,
input m_axis_rxwrite_data_TREADY,
output[63:0] m_axis_rxwrite_data_TDATA,
output[7:0] m_axis_rxwrite_data_TKEEP,
output m_axis_rxwrite_data_TLAST,
// memory tx cmd streams
output m_axis_txread_cmd_TVALID,
input m_axis_txread_cmd_TREADY,
output[71:0] m_axis_txread_cmd_TDATA,
output m_axis_txwrite_cmd_TVALID,
input m_axis_txwrite_cmd_TREADY,
output[71:0] m_axis_txwrite_cmd_TDATA,
// memory tx sts streams
input s_axis_txread_sts_TVALID,
output s_axis_txread_sts_TREADY,
input[7:0] s_axis_txread_sts_TDATA,
input s_axis_txwrite_sts_TVALID,
output s_axis_txwrite_sts_TREADY,
input[63:0] s_axis_txwrite_sts_TDATA,
// memory tx data streams
input s_axis_txread_data_TVALID,
output s_axis_txread_data_TREADY,
input[63:0] s_axis_txread_data_TDATA,
input[7:0] s_axis_txread_data_TKEEP,
input s_axis_txread_data_TLAST,
output m_axis_txwrite_data_TVALID,
input m_axis_txwrite_data_TREADY,
output[63:0] m_axis_txwrite_data_TDATA,
output[7:0] m_axis_txwrite_data_TKEEP,
output m_axis_txwrite_data_TLAST,
//application interface streams
output m_axis_listen_port_status_TVALID,
input m_axis_listen_port_status_TREADY,
output[7:0] m_axis_listen_port_status_TDATA,
output m_axis_notifications_TVALID,
input m_axis_notifications_TREADY,
output[87:0] m_axis_notifications_TDATA,
output m_axis_open_status_TVALID,
input m_axis_open_status_TREADY,
output[23:0] m_axis_open_status_TDATA,
output m_axis_rx_data_TVALID,
input m_axis_rx_data_TREADY,
output[63:0] m_axis_rx_data_TDATA,
output[7:0] m_axis_rx_data_TKEEP,
output m_axis_rx_data_TLAST,
output m_axis_rx_metadata_TVALID,
input m_axis_rx_metadata_TREADY,
output[15:0] m_axis_rx_metadata_TDATA,
output m_axis_tx_status_TVALID,
input m_axis_tx_status_TREADY,
output[63:0] m_axis_tx_status_TDATA,
input s_axis_listen_port_TVALID,
output s_axis_listen_port_TREADY,
input[15:0] s_axis_listen_port_TDATA,
//input s_axis_close_port_TVALID,
//output s_axis_close_port_TREADY,
//input[15:0] s_axis_close_port_TDATA,
input s_axis_close_connection_TVALID,
output s_axis_close_connection_TREADY,
input[15:0] s_axis_close_connection_TDATA,
input s_axis_open_connection_TVALID,
output s_axis_open_connection_TREADY,
input[47:0] s_axis_open_connection_TDATA,
input s_axis_read_package_TVALID,
output s_axis_read_package_TREADY,
input[31:0] s_axis_read_package_TDATA,
input s_axis_tx_data_TVALID,
output s_axis_tx_data_TREADY,
input[63:0] s_axis_tx_data_TDATA,
input[7:0] s_axis_tx_data_TKEEP,
input s_axis_tx_data_TLAST,
input s_axis_tx_metadata_TVALID,
output s_axis_tx_metadata_TREADY,
input[31:0] s_axis_tx_metadata_TDATA, //change to 15?
//debug
output debug_axi_intercon_to_mie_tready,
output debug_axi_intercon_to_mie_tvalid,
output debug_axi_slice_toe_mie_tvalid,
output debug_axi_slice_toe_mie_tready,
output [161:0] debug_out,
output[31:0] ip_address_out,
output[15:0] regSessionCount_V,
output regSessionCount_V_ap_vld,
input[3:0] board_number,
input[1:0] subnet_number
);
// cmd streams
wire axis_rxread_cmd_TVALID;
wire axis_rxread_cmd_TREADY;
wire[71:0] axis_rxread_cmd_TDATA;
wire axis_rxwrite_cmd_TVALID;
wire axis_rxwrite_cmd_TREADY;
wire[71:0] axis_rxwrite_cmd_TDATA;
wire axis_txread_cmd_TVALID;
wire axis_txread_cmd_TREADY;
wire[71:0] axis_txread_cmd_TDATA;
wire axis_txwrite_cmd_TVALID;
wire axis_txwrite_cmd_TREADY;
wire[71:0] axis_txwrite_cmd_TDATA;
// sts streams
wire axis_rxread_sts_TVALID;
wire axis_rxread_sts_TREADY;
wire[7:0] axis_rxread_sts_TDATA;
wire axis_rxwrite_sts_TVALID;
wire axis_rxwrite_sts_TREADY;
wire[7:0] axis_rxwrite_sts_TDATA;
wire axis_txread_sts_TVALID;
wire axis_txread_sts_TREADY;
wire[7:0] axis_txread_sts_TDATA;
wire axis_txwrite_sts_TVALID;
wire axis_txwrite_sts_TREADY;
wire[63:0] axis_txwrite_sts_TDATA;
//data streams
wire axis_rxbuffer2app_TVALID;
wire axis_rxbuffer2app_TREADY;
wire[63:0] axis_rxbuffer2app_TDATA;
wire[7:0] axis_rxbuffer2app_TKEEP;
wire axis_rxbuffer2app_TLAST;
wire axis_tcp2rxbuffer_TVALID;
wire axis_tcp2rxbuffer_TREADY;
wire[63:0] axis_tcp2rxbuffer_TDATA;
wire[7:0] axis_tcp2rxbuffer_TKEEP;
wire axis_tcp2rxbuffer_TLAST;
wire axis_txbuffer2tcp_TVALID;
wire axis_txbuffer2tcp_TREADY;
wire[63:0] axis_txbuffer2tcp_TDATA;
wire[7:0] axis_txbuffer2tcp_TKEEP;
wire axis_txbuffer2tcp_TLAST;
wire axis_app2txbuffer_TVALID;
wire axis_app2txbuffer_TREADY;
wire[63:0] axis_app2txbuffer_TDATA;
wire[7:0] axis_app2txbuffer_TKEEP;
wire axis_app2txbuffer_TLAST;
wire upd_req_TVALID;
wire upd_req_TREADY;
wire[111:0] upd_req_TDATA; //(1 + 1 + 14 + 96) - 1 = 111
wire upd_rsp_TVALID;
wire upd_rsp_TREADY;
wire[15:0] upd_rsp_TDATA;
wire ins_req_TVALID;
wire ins_req_TREADY;
wire[111:0] ins_req_TDATA;
wire del_req_TVALID;
wire del_req_TREADY;
wire[111:0] del_req_TDATA;
wire lup_req_TVALID;
wire lup_req_TREADY;
wire[97:0] lup_req_TDATA; //should be 96, also wrong in SmartCam
wire lup_rsp_TVALID;
wire lup_rsp_TREADY;
wire[15:0] lup_rsp_TDATA;
//wire[14:0] free_list_data_count;
// IP Handler Outputs
wire axi_iph_to_arp_slice_tvalid;
wire axi_iph_to_arp_slice_tready;
wire[63:0] axi_iph_to_arp_slice_tdata;
wire[7:0] axi_iph_to_arp_slice_tkeep;
wire axi_iph_to_arp_slice_tlast;
wire axi_iph_to_icmp_slice_tvalid;
wire axi_iph_to_icmp_slice_tready;
wire[63:0] axi_iph_to_icmp_slice_tdata;
wire[7:0] axi_iph_to_icmp_slice_tkeep;
wire axi_iph_to_icmp_slice_tlast;
wire axi_iph_to_udp_slice_tvalid;
wire axi_iph_to_udp_slice_tready;
wire[63:0] axi_iph_to_udp_slice_tdata;
wire[7:0] axi_iph_to_udp_slice_tkeep;
wire axi_iph_to_udp_slice_tlast;
wire axi_iph_to_toe_slice_tvalid;
wire axi_iph_to_toe_slice_tready;
wire[63:0] axi_iph_to_toe_slice_tdata;
wire[7:0] axi_iph_to_toe_slice_tkeep;
wire axi_iph_to_toe_slice_tlast;
//Slice connections on RX path
wire axi_arp_slice_to_arp_tvalid;
wire axi_arp_slice_to_arp_tready;
wire[63:0] axi_arp_slice_to_arp_tdata;
wire[7:0] axi_arp_slice_to_arp_tkeep;
wire axi_arp_slice_to_arp_tlast;
wire axi_icmp_slice_to_icmp_tvalid;
wire axi_icmp_slice_to_icmp_tready;
wire[63:0] axi_icmp_slice_to_icmp_tdata;
wire[7:0] axi_icmp_slice_to_icmp_tkeep;
wire axi_icmp_slice_to_icmp_tlast;
wire axi_udp_slice_to_udp_tvalid;
wire axi_udp_slice_to_udp_tready;
wire[63:0] axi_udp_slice_to_udp_tdata;
wire[7:0] axi_udp_slice_to_udp_tkeep;
wire axi_udp_slice_to_udp_tlast;
wire axi_toe_slice_to_toe_tvalid;
wire axi_toe_slice_to_toe_tready;
wire[63:0] axi_toe_slice_to_toe_tdata;
wire[7:0] axi_toe_slice_to_toe_tkeep;
wire axi_toe_slice_to_toe_tlast;
// MAC-IP Encode Inputs
wire axi_intercon_to_mie_tvalid;
wire axi_intercon_to_mie_tready;
wire[63:0] axi_intercon_to_mie_tdata;
wire[7:0] axi_intercon_to_mie_tkeep;
wire axi_intercon_to_mie_tlast;
wire axi_mie_to_intercon_tvalid;
wire axi_mie_to_intercon_tready;
wire[63:0] axi_mie_to_intercon_tdata;
wire[7:0] axi_mie_to_intercon_tkeep;
wire axi_mie_to_intercon_tlast;
/*wire axi_arp_slice_to_mie_tvalid;
wire axi_arp_slice_to_mie_tready;
wire[63:0] axi_arp_slice_to_mie_tdata;
wire[7:0] axi_arp_slice_to_mie_tkeep;
wire axi_arp_slice_to_mie_tlast;
wire axi_icmp_slice_to_mie_tvalid;
wire axi_icmp_slice_to_mie_tready;
wire[63:0] axi_icmp_slice_to_mie_tdata;
wire[7:0] axi_icmp_slice_to_mie_tkeep;
wire axi_icmp_slice_to_mie_tlast;
wire axi_toe_slice_to_mie_tvalid;
wire axi_toe_slice_to_mie_tready;
wire[63:0] axi_toe_slice_to_mie_tdata;
wire[7:0] axi_toe_slice_to_mie_tkeep;
wire axi_toe_slice_to_mie_tlast;*/
//Slice connections on RX path
wire axi_arp_to_arp_slice_tvalid;
wire axi_arp_to_arp_slice_tready;
wire[63:0] axi_arp_to_arp_slice_tdata;
wire[7:0] axi_arp_to_arp_slice_tkeep;
wire axi_arp_to_arp_slice_tlast;
wire axi_icmp_to_icmp_slice_tvalid;
wire axi_icmp_to_icmp_slice_tready;
wire[63:0] axi_icmp_to_icmp_slice_tdata;
wire[7:0] axi_icmp_to_icmp_slice_tkeep;
wire axi_icmp_to_icmp_slice_tlast;
wire axi_toe_to_toe_slice_tvalid;
wire axi_toe_to_toe_slice_tready;
wire[63:0] axi_toe_to_toe_slice_tdata;
wire[7:0] axi_toe_to_toe_slice_tkeep;
wire axi_toe_to_toe_slice_tlast;
wire axi_udp_to_merge_tvalid;
wire axi_udp_to_merge_tready;
wire[63:0] axi_udp_to_merge_tdata;
wire[7:0] axi_udp_to_merge_tkeep;
wire axi_udp_to_merge_tlast;
wire cam_ready;
wire sc_led0;
wire sc_led1;
wire[255:0] sc_debug;
wire [157:0] debug_out_ips;
assign debug_axi_intercon_to_mie_tready = axi_intercon_to_mie_tready;
assign debug_axi_intercon_to_mie_tvalid = axi_intercon_to_mie_tvalid;
assign debug_axi_slice_toe_mie_tvalid = axi_mie_to_intercon_tvalid;
assign debug_axi_slice_toe_mie_tready = axi_mie_to_intercon_tready;
// RX assignments
assign m_axis_rxread_cmd_TVALID = axis_rxread_cmd_TVALID;
assign axis_rxread_cmd_TREADY = m_axis_rxread_cmd_TREADY;
assign m_axis_rxread_cmd_TDATA = axis_rxread_cmd_TDATA;
assign m_axis_rxwrite_cmd_TVALID = axis_rxwrite_cmd_TVALID;
assign axis_rxwrite_cmd_TREADY = m_axis_rxwrite_cmd_TREADY;
assign m_axis_rxwrite_cmd_TDATA = axis_rxwrite_cmd_TDATA;
assign axis_rxread_sts_TVALID = s_axis_rxread_sts_TVALID;
assign s_axis_rxread_sts_TREADY = axis_rxread_sts_TREADY;
assign axis_rxread_sts_TDATA = s_axis_rxread_sts_TDATA;
assign axis_rxwrite_sts_TVALID = s_axis_rxwrite_sts_TVALID;
assign s_axis_rxwrite_sts_TREADY = axis_rxwrite_sts_TREADY;
assign axis_rxwrite_sts_TDATA = s_axis_rxwrite_sts_TDATA;
// read
/*assign axis_rxbuffer2app_TVALID = s_axis_rxread_data_TVALID;
assign s_axis_rxread_data_TREADY = axis_rxbuffer2app_TREADY;
assign axis_rxbuffer2app_TDATA = s_axis_rxread_data_TDATA;
assign axis_rxbuffer2app_TKEEP = s_axis_rxread_data_TKEEP;
assign axis_rxbuffer2app_TLAST = s_axis_rxread_data_TLAST;
// write
assign m_axis_rxwrite_data_TVALID = axis_tcp2rxbuffer_TVALID;
assign axis_tcp2rxbuffer_TREADY = m_axis_rxwrite_data_TREADY;
assign m_axis_rxwrite_data_TDATA = axis_tcp2rxbuffer_TDATA;
assign m_axis_rxwrite_data_TKEEP = axis_tcp2rxbuffer_TKEEP;
assign m_axis_rxwrite_data_TLAST = axis_tcp2rxbuffer_TLAST;*/
// TX assignments
assign m_axis_txread_cmd_TVALID = axis_txread_cmd_TVALID;
assign axis_txread_cmd_TREADY = m_axis_txread_cmd_TREADY;
assign m_axis_txread_cmd_TDATA = axis_txread_cmd_TDATA;
assign m_axis_txwrite_cmd_TVALID = axis_txwrite_cmd_TVALID;
assign axis_txwrite_cmd_TREADY = m_axis_txwrite_cmd_TREADY;
assign m_axis_txwrite_cmd_TDATA = axis_txwrite_cmd_TDATA;
assign axis_txread_sts_TVALID = s_axis_txread_sts_TVALID;
assign s_axis_txread_sts_TREADY = axis_txread_sts_TREADY;
assign axis_txread_sts_TDATA = s_axis_txread_sts_TDATA;
assign axis_txwrite_sts_TVALID = s_axis_txwrite_sts_TVALID;
assign s_axis_txwrite_sts_TREADY = axis_txwrite_sts_TREADY;
assign axis_txwrite_sts_TDATA = s_axis_txwrite_sts_TDATA;
// read
assign axis_txbuffer2tcp_TVALID = s_axis_txread_data_TVALID;
assign s_axis_txread_data_TREADY = axis_txbuffer2tcp_TREADY;
assign axis_txbuffer2tcp_TDATA = s_axis_txread_data_TDATA;
assign axis_txbuffer2tcp_TKEEP = s_axis_txread_data_TKEEP;
assign axis_txbuffer2tcp_TLAST = s_axis_txread_data_TLAST;
// write
assign m_axis_txwrite_data_TVALID = axis_app2txbuffer_TVALID;
assign axis_app2txbuffer_TREADY = m_axis_txwrite_data_TREADY;
assign m_axis_txwrite_data_TDATA = axis_app2txbuffer_TDATA;
assign m_axis_txwrite_data_TKEEP = axis_app2txbuffer_TKEEP;
assign m_axis_txwrite_data_TLAST = axis_app2txbuffer_TLAST;
// because read status is not used
assign axis_rxread_sts_TREADY = 1'b1;
assign axis_txread_sts_TREADY = 1'b1;
// Register and distribute ip address
wire[31:0] dhcp_ip_address;
wire dhcp_ip_address_en;
reg[47:0] mie_mac_address;
reg[47:0] arp_mac_address;
reg[31:0] iph_ip_address;
reg[31:0] arp_ip_address;
reg[31:0] toe_ip_address;
reg[31:0] ip_subnet_mask;
reg[31:0] ip_default_gateway;
//assign dhcp_ip_address_en = 1'b1;
//assign dhcp_ip_address = 32'hD1D4010A;
always @(posedge aclk)
begin
if (aresetn == 0) begin
mie_mac_address <= 48'h000000000000;
arp_mac_address <= 48'h000000000000;
iph_ip_address <= 32'h00000000;
arp_ip_address <= 32'h00000000;
toe_ip_address <= 32'h00000000;
ip_subnet_mask <= 32'h00000000;
ip_default_gateway <= 32'h00000000;
end
else begin
mie_mac_address <= {MAC_ADDRESS[47:44], (MAC_ADDRESS[43:40]+board_number), MAC_ADDRESS[39:0]};
arp_mac_address <= {MAC_ADDRESS[47:44], (MAC_ADDRESS[43:40]+board_number), MAC_ADDRESS[39:0]};
if (DHCP_EN == 1) begin
if (dhcp_ip_address_en == 1'b1) begin
iph_ip_address <= dhcp_ip_address;
arp_ip_address <= dhcp_ip_address;
toe_ip_address <= dhcp_ip_address;
end
end
else begin
iph_ip_address <= {IP_ADDRESS[31:28], IP_ADDRESS[27:24]+board_number, IP_ADDRESS[23:4], IP_ADDRESS[3:0]+subnet_number};
arp_ip_address <= {IP_ADDRESS[31:28], IP_ADDRESS[27:24]+board_number, IP_ADDRESS[23:4], IP_ADDRESS[3:0]+subnet_number};
toe_ip_address <= {IP_ADDRESS[31:28], IP_ADDRESS[27:24]+board_number, IP_ADDRESS[23:4], IP_ADDRESS[3:0]+subnet_number};
ip_subnet_mask <= IP_SUBNET_MASK;
ip_default_gateway <= {IP_DEFAULT_GATEWAY[31:4], IP_DEFAULT_GATEWAY[3:0]+subnet_number};
end
end
end
// ip address output
assign ip_address_out = iph_ip_address;
wire [157:0] debug_out_tcp;
wire [7:0] aux;
// for shortcut_toe
assign axis_rxread_cmd_TVALID = 1'b0;
assign axis_rxwrite_cmd_TVALID = 1'b0;
assign axis_rxwrite_sts_TREADY = 1'b1;
/*assign axis_rxbuffer2app_TREADY = 1'b1;
assign axis_tcp2rxbuffer_TVALID = 1'b0;*/
wire[31:0] rx_buffer_data_count;
shortcut_toe_NODELAY_ip toe_inst (
// Data output
.m_axis_tcp_data_TVALID(axi_toe_to_toe_slice_tvalid), // output AXI_M_Stream_TVALID
.m_axis_tcp_data_TREADY(axi_toe_to_toe_slice_tready), // input AXI_M_Stream_TREADY
.m_axis_tcp_data_TDATA(axi_toe_to_toe_slice_tdata), // output [63 : 0] AXI_M_Stream_TDATA
.m_axis_tcp_data_TKEEP(axi_toe_to_toe_slice_tkeep), // output [7 : 0] AXI_M_Stream_TSTRB
.m_axis_tcp_data_TLAST(axi_toe_to_toe_slice_tlast), // output [0 : 0] AXI_M_Stream_TLAST
// Data input
.s_axis_tcp_data_TVALID(axi_toe_slice_to_toe_tvalid), // input AXI_S_Stream_TVALID
.s_axis_tcp_data_TREADY(axi_toe_slice_to_toe_tready), // output AXI_S_Stream_TREADY
.s_axis_tcp_data_TDATA(axi_toe_slice_to_toe_tdata), // input [63 : 0] AXI_S_Stream_TDATA
.s_axis_tcp_data_TKEEP(axi_toe_slice_to_toe_tkeep), // input [7 : 0] AXI_S_Stream_TKEEP
.s_axis_tcp_data_TLAST(axi_toe_slice_to_toe_tlast), // input [0 : 0] AXI_S_Stream_TLAST
// rx read commands
/*.m_axis_rxread_cmd_TVALID(axis_rxread_cmd_TVALID),
.m_axis_rxread_cmd_TREADY(axis_rxread_cmd_TREADY),
.m_axis_rxread_cmd_TDATA(axis_rxread_cmd_TDATA),
// rx write commands
.m_axis_rxwrite_cmd_TVALID(axis_rxwrite_cmd_TVALID),
.m_axis_rxwrite_cmd_TREADY(axis_rxwrite_cmd_TREADY),
.m_axis_rxwrite_cmd_TDATA(axis_rxwrite_cmd_TDATA),
// rx write status
.s_axis_rxwrite_sts_TVALID(axis_rxwrite_sts_TVALID),
.s_axis_rxwrite_sts_TREADY(axis_rxwrite_sts_TREADY),
.s_axis_rxwrite_sts_TDATA(axis_rxwrite_sts_TDATA),*/
// rx buffer read path
.s_axis_rxread_data_TVALID(axis_rxbuffer2app_TVALID),
.s_axis_rxread_data_TREADY(axis_rxbuffer2app_TREADY),
.s_axis_rxread_data_TDATA(axis_rxbuffer2app_TDATA),
.s_axis_rxread_data_TKEEP(axis_rxbuffer2app_TKEEP),
.s_axis_rxread_data_TLAST(axis_rxbuffer2app_TLAST),
// rx buffer write path
.m_axis_rxwrite_data_TVALID(axis_tcp2rxbuffer_TVALID),
.m_axis_rxwrite_data_TREADY(axis_tcp2rxbuffer_TREADY),
.m_axis_rxwrite_data_TDATA(axis_tcp2rxbuffer_TDATA),
.m_axis_rxwrite_data_TKEEP(axis_tcp2rxbuffer_TKEEP),
.m_axis_rxwrite_data_TLAST(axis_tcp2rxbuffer_TLAST),
// tx read commands
.m_axis_txread_cmd_TVALID(axis_txread_cmd_TVALID),
.m_axis_txread_cmd_TREADY(axis_txread_cmd_TREADY),
.m_axis_txread_cmd_TDATA(axis_txread_cmd_TDATA),
//tx write commands
.m_axis_txwrite_cmd_TVALID(axis_txwrite_cmd_TVALID),
.m_axis_txwrite_cmd_TREADY(axis_txwrite_cmd_TREADY),
.m_axis_txwrite_cmd_TDATA(axis_txwrite_cmd_TDATA),
// tx write status
.s_axis_txwrite_sts_TVALID(axis_txwrite_sts_TVALID),
.s_axis_txwrite_sts_TREADY(axis_txwrite_sts_TREADY),
.s_axis_txwrite_sts_TDATA(axis_txwrite_sts_TDATA),
// tx read path
.s_axis_txread_data_TVALID(axis_txbuffer2tcp_TVALID),
.s_axis_txread_data_TREADY(axis_txbuffer2tcp_TREADY),
.s_axis_txread_data_TDATA(axis_txbuffer2tcp_TDATA),
.s_axis_txread_data_TKEEP(axis_txbuffer2tcp_TKEEP),
.s_axis_txread_data_TLAST(axis_txbuffer2tcp_TLAST),
// tx write path
.m_axis_txwrite_data_TVALID(axis_app2txbuffer_TVALID),
.m_axis_txwrite_data_TREADY(axis_app2txbuffer_TREADY),
.m_axis_txwrite_data_TDATA(axis_app2txbuffer_TDATA),
.m_axis_txwrite_data_TKEEP(axis_app2txbuffer_TKEEP),
.m_axis_txwrite_data_TLAST(axis_app2txbuffer_TLAST),
/// SmartCAM I/F ///
.m_axis_session_upd_req_TVALID(upd_req_TVALID),
.m_axis_session_upd_req_TREADY(upd_req_TREADY),
.m_axis_session_upd_req_TDATA(upd_req_TDATA),
.s_axis_session_upd_rsp_TVALID(upd_rsp_TVALID),
.s_axis_session_upd_rsp_TREADY(upd_rsp_TREADY),
.s_axis_session_upd_rsp_TDATA(upd_rsp_TDATA),
.m_axis_session_lup_req_TVALID(lup_req_TVALID),
.m_axis_session_lup_req_TREADY(lup_req_TREADY),
.m_axis_session_lup_req_TDATA(lup_req_TDATA),
.s_axis_session_lup_rsp_TVALID(lup_rsp_TVALID),
.s_axis_session_lup_rsp_TREADY(lup_rsp_TREADY),
.s_axis_session_lup_rsp_TDATA(lup_rsp_TDATA),
/* Application Interface */
// listen&close port
.s_axis_listen_port_req_TVALID(s_axis_listen_port_TVALID),
.s_axis_listen_port_req_TREADY(s_axis_listen_port_TREADY),
.s_axis_listen_port_req_TDATA(s_axis_listen_port_TDATA),
.m_axis_listen_port_rsp_TVALID(m_axis_listen_port_status_TVALID),
.m_axis_listen_port_rsp_TREADY(m_axis_listen_port_status_TREADY),
.m_axis_listen_port_rsp_TDATA(m_axis_listen_port_status_TDATA),
// notification & read request
.m_axis_notification_TVALID(m_axis_notifications_TVALID),
.m_axis_notification_TREADY(m_axis_notifications_TREADY),
.m_axis_notification_TDATA(m_axis_notifications_TDATA),
.s_axis_rx_data_req_TVALID(s_axis_read_package_TVALID),
.s_axis_rx_data_req_TREADY(s_axis_read_package_TREADY),
.s_axis_rx_data_req_TDATA(s_axis_read_package_TDATA),
// open&close connection
.s_axis_open_conn_req_TVALID(s_axis_open_connection_TVALID),
.s_axis_open_conn_req_TREADY(s_axis_open_connection_TREADY),
.s_axis_open_conn_req_TDATA(s_axis_open_connection_TDATA),
.m_axis_open_conn_rsp_TVALID(m_axis_open_status_TVALID),
.m_axis_open_conn_rsp_TREADY(m_axis_open_status_TREADY),
.m_axis_open_conn_rsp_TDATA(m_axis_open_status_TDATA),
.s_axis_close_conn_req_TVALID(s_axis_close_connection_TVALID),//axis_close_connection_TVALID
.s_axis_close_conn_req_TREADY(s_axis_close_connection_TREADY),
.s_axis_close_conn_req_TDATA(s_axis_close_connection_TDATA),
// rx data
.m_axis_rx_data_rsp_metadata_TVALID(m_axis_rx_metadata_TVALID),
.m_axis_rx_data_rsp_metadata_TREADY(m_axis_rx_metadata_TREADY),
.m_axis_rx_data_rsp_metadata_TDATA(m_axis_rx_metadata_TDATA),
.m_axis_rx_data_rsp_TVALID(m_axis_rx_data_TVALID),
.m_axis_rx_data_rsp_TREADY(m_axis_rx_data_TREADY),
.m_axis_rx_data_rsp_TDATA(m_axis_rx_data_TDATA),
.m_axis_rx_data_rsp_TKEEP(m_axis_rx_data_TKEEP),
.m_axis_rx_data_rsp_TLAST(m_axis_rx_data_TLAST),
// tx data
.s_axis_tx_data_req_metadata_TVALID(s_axis_tx_metadata_TVALID),
.s_axis_tx_data_req_metadata_TREADY(s_axis_tx_metadata_TREADY),
.s_axis_tx_data_req_metadata_TDATA(s_axis_tx_metadata_TDATA),
.s_axis_tx_data_req_TVALID(s_axis_tx_data_TVALID),
.s_axis_tx_data_req_TREADY(s_axis_tx_data_TREADY),
.s_axis_tx_data_req_TDATA(s_axis_tx_data_TDATA),
.s_axis_tx_data_req_TKEEP(s_axis_tx_data_TKEEP),
.s_axis_tx_data_req_TLAST(s_axis_tx_data_TLAST),
.m_axis_tx_data_rsp_TVALID(m_axis_tx_status_TVALID),
.m_axis_tx_data_rsp_TREADY(m_axis_tx_status_TREADY),
.m_axis_tx_data_rsp_TDATA(m_axis_tx_status_TDATA[63:0]),
.regIpAddress_V(toe_ip_address),
.regSessionCount_V(regSessionCount_V),
.regSessionCount_V_ap_vld(regSessionCount_V_ap_vld),
//for external RX Buffer
.axis_data_count_V(rx_buffer_data_count),
.axis_max_data_count_V(32'd2048),
//.debug_out(debug_out_tcp[157:0]),
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
assign debug_out = {debug_out_tcp[137:0], debug_out_ips[19:0]};
//assign m_axis_tx_status_TDATA[7:0] = debug_out;
//RX BUFFER FIFO
fifo_generator_0 rx_buffer_fifo (
.s_aresetn(aresetn), // input wire s_axis_aresetn
.s_aclk(aclk), // input wire s_axis_aclk
.s_axis_tvalid(axis_tcp2rxbuffer_TVALID), // inp wire s_axis_tvalid
.s_axis_tready(axis_tcp2rxbuffer_TREADY), // output wire s_axis_tready
.s_axis_tdata(axis_tcp2rxbuffer_TDATA), // input wire [63 : 0] s_axis_tdata
.s_axis_tkeep(axis_tcp2rxbuffer_TKEEP), // input wire [7 : 0] s_axis_tkeep
.s_axis_tlast(axis_tcp2rxbuffer_TLAST), // input wire s_axis_tlast
.m_axis_tvalid(axis_rxbuffer2app_TVALID), // output wire m_axis_tvalid
.m_axis_tready(axis_rxbuffer2app_TREADY), // input wire m_axis_tready
.m_axis_tdata(axis_rxbuffer2app_TDATA), // output wire [63 : 0] m_axis_tdata
.m_axis_tkeep(axis_rxbuffer2app_TKEEP), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast(axis_rxbuffer2app_TLAST), // output wire m_axis_tlast
.axis_data_count(rx_buffer_data_count[11:0])
);
assign rx_buffer_data_count[31:12] = 20'h0;
SmartCamCtl SmartCamCtl_inst
(
.clk(aclk),
.rst(~aresetn),
.led0(sc_led0),
.led1(sc_led1),
.cam_ready(cam_ready),
.lup_req_valid(lup_req_TVALID),
.lup_req_ready(lup_req_TREADY),
.lup_req_din(lup_req_TDATA),
.lup_rsp_valid(lup_rsp_TVALID),
.lup_rsp_ready(lup_rsp_TREADY),
.lup_rsp_dout(lup_rsp_TDATA),
.upd_req_valid(upd_req_TVALID),
.upd_req_ready(upd_req_TREADY),
.upd_req_din(upd_req_TDATA),
.upd_rsp_valid(upd_rsp_TVALID),
.upd_rsp_ready(upd_rsp_TREADY),
.upd_rsp_dout(upd_rsp_TDATA),
.debug(sc_debug)
);
// DHCP port
wire axis_dhcp_open_port_tvalid;
wire axis_dhcp_open_port_tready;
wire[15:0] axis_dhcp_open_port_tdata;
wire axis_dhcp_open_port_status_tvalid;
wire axis_dhcp_open_port_status_tready;
wire[7:0] axis_dhcp_open_port_status_tdata; //actually only [0:0]
// DHCP RX
wire axis_dhcp_rx_data_tvalid;
wire axis_dhcp_rx_data_tready;
wire[63:0] axis_dhcp_rx_data_tdata;
wire[7:0] axis_dhcp_rx_data_tkeep;
wire axis_dhcp_rx_data_tlast;
wire axis_dhcp_rx_metadata_tvalid;
wire axis_dhcp_rx_metadata_tready;
wire[95:0] axis_dhcp_rx_metadata_tdata;
// DHCP TX
wire axis_dhcp_tx_data_tvalid;
wire axis_dhcp_tx_data_tready;
wire[63:0] axis_dhcp_tx_data_tdata;
wire[7:0] axis_dhcp_tx_data_tkeep;
wire axis_dhcp_tx_data_tlast;
wire axis_dhcp_tx_metadata_tvalid;
wire axis_dhcp_tx_metadata_tready;
wire[95:0] axis_dhcp_tx_metadata_tdata;
wire axis_dhcp_tx_length_tvalid;
wire axis_dhcp_tx_length_tready;
wire[15:0] axis_dhcp_tx_length_tdata;
assign axi_udp_slice_to_udp_tready = 1'b1;
assign axi_udp_to_merge_tvalid = 1'b0;
assign axi_udp_to_merge_tdata = 0;
assign axi_udp_to_merge_tkeep = 0;
assign axi_udp_to_merge_tlast = 0;
// UDP Engine
/*udp_ip udp_inst (
.inputPathInData_TVALID(axi_udp_slice_to_udp_tvalid), // input wire inputPathInData_TVALID
.inputPathInData_TREADY(axi_udp_slice_to_udp_tready), // output wire inputPathInData_TREADY
.inputPathInData_TDATA(axi_udp_slice_to_udp_tdata), // input wire [63 : 0] inputPathInData_TDATA
.inputPathInData_TKEEP(axi_udp_slice_to_udp_tkeep), // input wire [7 : 0] inputPathInData_TKEEP
.inputPathInData_TLAST(axi_udp_slice_to_udp_tlast), // input wire [0 : 0] inputPathInData_TLAST
.inputpathOutData_TVALID(axis_dhcp_rx_data_tvalid), // output wire inputpathOutData_V_TVALID
.inputpathOutData_TREADY(axis_dhcp_rx_data_tready), // input wire inputpathOutData_V_TREADY
.inputpathOutData_TDATA(axis_dhcp_rx_data_tdata), // output wire [71 : 0] inputpathOutData_V_TDATA
.inputpathOutData_TKEEP(axis_dhcp_rx_data_tkeep), // output wire [7:0]
.inputpathOutData_TLAST(axis_dhcp_rx_data_tlast), // output wire
.openPort_TVALID(axis_dhcp_open_port_tvalid), // input wire openPort_V_TVALID
.openPort_TREADY(axis_dhcp_open_port_tready), // output wire openPort_V_TREADY
.openPort_TDATA(axis_dhcp_open_port_tdata), // input wire [7 : 0] openPort_V_TDATA
.confirmPortStatus_TVALID(axis_dhcp_open_port_status_tvalid), // output wire confirmPortStatus_V_V_TVALID
.confirmPortStatus_TREADY(axis_dhcp_open_port_status_tready), // input wire confirmPortStatus_V_V_TREADY
.confirmPortStatus_TDATA(axis_dhcp_open_port_status_tdata), // output wire [15 : 0] confirmPortStatus_V_V_TDATA
.inputPathOutputMetadata_TVALID(axis_dhcp_rx_metadata_tvalid), // output wire inputPathOutputMetadata_V_TVALID
.inputPathOutputMetadata_TREADY(axis_dhcp_rx_metadata_tready), // input wire inputPathOutputMetadata_V_TREADY
.inputPathOutputMetadata_TDATA(axis_dhcp_rx_metadata_tdata), // output wire [95 : 0] inputPathOutputMetadata_V_TDATA
.portRelease_TVALID(1'b0), // input wire portRelease_V_V_TVALID
.portRelease_TREADY(), // output wire portRelease_V_V_TREADY
.portRelease_TDATA(15'b0), // input wire [15 : 0] portRelease_V_V_TDATA
.outputPathInData_TVALID(axis_dhcp_tx_data_tvalid), // input wire outputPathInData_V_TVALID
.outputPathInData_TREADY(axis_dhcp_tx_data_tready), // output wire outputPathInData_V_TREADY
.outputPathInData_TDATA(axis_dhcp_tx_data_tdata), // input wire [71 : 0] outputPathInData_V_TDATA
.outputPathInData_TKEEP(axis_dhcp_tx_data_tkeep), // input wire [7 : 0] outputPathInData_TKEEP
.outputPathInData_TLAST(axis_dhcp_tx_data_tlast), // input wire [0 : 0] outputPathInData_TLAST
.outputPathOutData_TVALID(axi_udp_to_merge_tvalid), // output wire outputPathOutData_TVALID
.outputPathOutData_TREADY(axi_udp_to_merge_tready), // input wire outputPathOutData_TREADY
.outputPathOutData_TDATA(axi_udp_to_merge_tdata), // output wire [63 : 0] outputPathOutData_TDATA
.outputPathOutData_TKEEP(axi_udp_to_merge_tkeep), // output wire [7 : 0] outputPathOutData_TKEEP
.outputPathOutData_TLAST(axi_udp_to_merge_tlast), // output wire [0 : 0] outputPathOutData_TLAST
.outputPathInMetadata_TVALID(axis_dhcp_tx_metadata_tvalid), // input wire outputPathInMetadata_V_TVALID
.outputPathInMetadata_TREADY(axis_dhcp_tx_metadata_tready), // output wire outputPathInMetadata_V_TREADY
.outputPathInMetadata_TDATA(axis_dhcp_tx_metadata_tdata), // input wire [95 : 0] outputPathInMetadata_V_TDATA
.outputpathInLength_TVALID(axis_dhcp_tx_length_tvalid), // input wire outputpathInLength_V_V_TVALID
.outputpathInLength_TREADY(axis_dhcp_tx_length_tready), // output wire outputpathInLength_V_V_TREADY
.outputpathInLength_TDATA(axis_dhcp_tx_length_tdata), // input wire [15 : 0] outputpathInLength_V_V_TDATA
.inputPathPortUnreachable_TVALID(), // output wire inputPathPortUnreachable_TVALID
.inputPathPortUnreachable_TREADY(1'b1), // input wire inputPathPortUnreachable_TREADY
.inputPathPortUnreachable_TDATA(), // output wire [63 : 0] inputPathPortUnreachable_TDATA
.inputPathPortUnreachable_TKEEP(), // output wire [7 : 0] inputPathPortUnreachable_TKEEP
.inputPathPortUnreachable_TLAST(), // output wire [0 : 0] inputPathPortUnreachable_TLAST
.aclk(aclk), // input wire ap_clk
.aresetn(aresetn) // input wire ap_rst_n
);
dhcp_client_ip dhcp_client_inst (
.m_axis_open_port_TVALID(axis_dhcp_open_port_tvalid), // output wire m_axis_open_port_TVALID
.m_axis_open_port_TREADY(axis_dhcp_open_port_tready), // input wire m_axis_open_port_TREADY
.m_axis_open_port_TDATA(axis_dhcp_open_port_tdata), // output wire [15 : 0] m_axis_open_port_TDATA
.m_axis_tx_data_TVALID(axis_dhcp_tx_data_tvalid), // output wire m_axis_tx_data_TVALID
.m_axis_tx_data_TREADY(axis_dhcp_tx_data_tready), // input wire m_axis_tx_data_TREADY
.m_axis_tx_data_TDATA(axis_dhcp_tx_data_tdata), // output wire [63 : 0] m_axis_tx_data_TDATA
.m_axis_tx_data_TKEEP(axis_dhcp_tx_data_tkeep), // output wire [7 : 0] m_axis_tx_data_TKEEP
.m_axis_tx_data_TLAST(axis_dhcp_tx_data_tlast), // output wire [0 : 0] m_axis_tx_data_TLAST
.m_axis_tx_length_TVALID(axis_dhcp_tx_length_tvalid), // output wire m_axis_tx_length_TVALID
.m_axis_tx_length_TREADY(axis_dhcp_tx_length_tready), // input wire m_axis_tx_length_TREADY
.m_axis_tx_length_TDATA(axis_dhcp_tx_length_tdata), // output wire [15 : 0] m_axis_tx_length_TDATA
.m_axis_tx_metadata_TVALID(axis_dhcp_tx_metadata_tvalid), // output wire m_axis_tx_metadata_TVALID
.m_axis_tx_metadata_TREADY(axis_dhcp_tx_metadata_tready), // input wire m_axis_tx_metadata_TREADY
.m_axis_tx_metadata_TDATA(axis_dhcp_tx_metadata_tdata), // output wire [95 : 0] m_axis_tx_metadata_TDATA
.s_axis_open_port_status_TVALID(axis_dhcp_open_port_status_tvalid), // input wire s_axis_open_port_status_TVALID
.s_axis_open_port_status_TREADY(axis_dhcp_open_port_status_tready), // output wire s_axis_open_port_status_TREADY
.s_axis_open_port_status_TDATA(axis_dhcp_open_port_status_tdata), // input wire [7 : 0] s_axis_open_port_status_TDATA
.s_axis_rx_data_TVALID(axis_dhcp_rx_data_tvalid), // input wire s_axis_rx_data_TVALID
.s_axis_rx_data_TREADY(axis_dhcp_rx_data_tready), // output wire s_axis_rx_data_TREADY
.s_axis_rx_data_TDATA(axis_dhcp_rx_data_tdata), // input wire [63 : 0] s_axis_rx_data_TDATA
.s_axis_rx_data_TKEEP(axis_dhcp_rx_data_tkeep), // input wire [7 : 0] s_axis_rx_data_TKEEP
.s_axis_rx_data_TLAST(axis_dhcp_rx_data_tlast), // input wire [0 : 0] s_axis_rx_data_TLAST
.s_axis_rx_metadata_TVALID(axis_dhcp_rx_metadata_tvalid), // input wire s_axis_rx_metadata_TVALID
.s_axis_rx_metadata_TREADY(axis_dhcp_rx_metadata_tready), // output wire s_axis_rx_metadata_TREADY
.s_axis_rx_metadata_TDATA(axis_dhcp_rx_metadata_tdata), // input wire [95 : 0] s_axis_rx_metadata_TDATA
.dhcpIpAddressOut_V(dhcp_ip_address), // output wire [31 : 0] dhcpIpAddressOut_V
.dhcpIpAddressOut_V_ap_vld(dhcp_ip_address_en),
.aclk(aclk), // input wire aclk
.aresetn(aresetn) // input wire aresetn
);*/
ip_handler_ip ip_handler_inst (
.m_axis_ARP_TVALID(axi_iph_to_arp_slice_tvalid), // output AXI4Stream_M_TVALID
.m_axis_ARP_TREADY(axi_iph_to_arp_slice_tready), // input AXI4Stream_M_TREADY
.m_axis_ARP_TDATA(axi_iph_to_arp_slice_tdata), // output [63 : 0] AXI4Stream_M_TDATA
.m_axis_ARP_TKEEP(axi_iph_to_arp_slice_tkeep), // output [7 : 0] AXI4Stream_M_TSTRB
.m_axis_ARP_TLAST(axi_iph_to_arp_slice_tlast), // output [0 : 0] AXI4Stream_M_TLAST
.m_axis_ICMP_TVALID(axi_iph_to_icmp_slice_tvalid), // output AXI4Stream_M_TVALID
.m_axis_ICMP_TREADY(axi_iph_to_icmp_slice_tready), // input AXI4Stream_M_TREADY
.m_axis_ICMP_TDATA(axi_iph_to_icmp_slice_tdata), // output [63 : 0] AXI4Stream_M_TDATA
.m_axis_ICMP_TKEEP(axi_iph_to_icmp_slice_tkeep), // output [7 : 0] AXI4Stream_M_TSTRB
.m_axis_ICMP_TLAST(axi_iph_to_icmp_slice_tlast), // output [0 : 0] AXI4Stream_M_TLAST
.m_axis_UDP_TVALID(axi_iph_to_udp_slice_tvalid), // output AXI4Stream_M_TVALID
.m_axis_UDP_TREADY(axi_iph_to_udp_slice_tready), // input AXI4Stream_M_TREADY
.m_axis_UDP_TDATA(axi_iph_to_udp_slice_tdata), // output [63 : 0] AXI4Stream_M_TDATA
.m_axis_UDP_TKEEP(axi_iph_to_udp_slice_tkeep), // output [7 : 0] AXI4Stream_M_TSTRB
.m_axis_UDP_TLAST(axi_iph_to_udp_slice_tlast), // output [0 : 0]
.m_axis_TCP_TVALID(axi_iph_to_toe_slice_tvalid), // output AXI4Stream_M_TVALID
.m_axis_TCP_TREADY(axi_iph_to_toe_slice_tready), // input AXI4Stream_M_TREADY
.m_axis_TCP_TDATA(axi_iph_to_toe_slice_tdata), // output [63 : 0] AXI4Stream_M_TDATA
.m_axis_TCP_TKEEP(axi_iph_to_toe_slice_tkeep), // output [7 : 0] AXI4Stream_M_TSTRB
.m_axis_TCP_TLAST(axi_iph_to_toe_slice_tlast), // output [0 : 0] AXI4Stream_M_TLAST
.s_axis_raw_TVALID(AXI_S_Stream_TVALID), // input AXI4Stream_S_TVALID
.s_axis_raw_TREADY(AXI_S_Stream_TREADY), // output AXI4Stream_S_TREADY
.s_axis_raw_TDATA(AXI_S_Stream_TDATA), // input [63 : 0] AXI4Stream_S_TDATA
.s_axis_raw_TKEEP(AXI_S_Stream_TKEEP), // input [7 : 0] AXI4Stream_S_TSTRB
.s_axis_raw_TLAST(AXI_S_Stream_TLAST), // input [0 : 0] AXI4Stream_S_TLAST
.regIpAddress_V(iph_ip_address),
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
assign debug_out_ips[0] = axi_iph_to_arp_slice_tvalid;
assign debug_out_ips[1] = axi_iph_to_arp_slice_tready;
assign debug_out_ips[2] = axi_iph_to_arp_slice_tlast;
assign debug_out_ips[3] = axi_iph_to_icmp_slice_tvalid;
assign debug_out_ips[4] = axi_iph_to_icmp_slice_tready;
assign debug_out_ips[5] = axi_iph_to_icmp_slice_tlast;
assign debug_out_ips[6] = axi_iph_to_toe_slice_tvalid;
assign debug_out_ips[7] = axi_iph_to_toe_slice_tready;
assign debug_out_ips[8] = axi_iph_to_toe_slice_tlast;
assign debug_out_ips[9] = AXI_S_Stream_TVALID;
assign debug_out_ips[10] = AXI_S_Stream_TREADY;
assign debug_out_ips[11] = AXI_S_Stream_TLAST;
// ARP lookup
wire axis_arp_lookup_request_TVALID;
wire axis_arp_lookup_request_TREADY;
wire[31:0] axis_arp_lookup_request_TDATA;
wire axis_arp_lookup_reply_TVALID;
wire axis_arp_lookup_reply_TREADY;
wire[55:0] axis_arp_lookup_reply_TDATA;
mac_ip_encode_ip mac_ip_encode_inst (
.m_axis_ip_TVALID(axi_mie_to_intercon_tvalid),
.m_axis_ip_TREADY(axi_mie_to_intercon_tready),
.m_axis_ip_TDATA(axi_mie_to_intercon_tdata),
.m_axis_ip_TKEEP(axi_mie_to_intercon_tkeep),
.m_axis_ip_TLAST(axi_mie_to_intercon_tlast),
.m_axis_arp_lookup_request_TVALID(axis_arp_lookup_request_TVALID),
.m_axis_arp_lookup_request_TREADY(axis_arp_lookup_request_TREADY),
.m_axis_arp_lookup_request_TDATA(axis_arp_lookup_request_TDATA),
.s_axis_ip_TVALID(axi_intercon_to_mie_tvalid),
.s_axis_ip_TREADY(axi_intercon_to_mie_tready),
.s_axis_ip_TDATA(axi_intercon_to_mie_tdata),
.s_axis_ip_TKEEP(axi_intercon_to_mie_tkeep),
.s_axis_ip_TLAST(axi_intercon_to_mie_tlast),
.s_axis_arp_lookup_reply_TVALID(axis_arp_lookup_reply_TVALID),
.s_axis_arp_lookup_reply_TREADY(axis_arp_lookup_reply_TREADY),
.s_axis_arp_lookup_reply_TDATA(axis_arp_lookup_reply_TDATA),
.myMacAddress_V(mie_mac_address), // input wire [47 : 0] regMacAddress_V
.regSubNetMask_V(ip_subnet_mask), // input wire [31 : 0] regSubNetMask_V
.regDefaultGateway_V(ip_default_gateway), // input wire [31 : 0] regDefaultGateway_V
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
// merges icmp, udp and tcp
axis_interconnect_3to1 ip_merger (
.ACLK(aclk), // input ACLK
.ARESETN(aresetn), // input ARESETN
// ICMP
.S00_AXIS_ACLK(aclk), // input S00_AXIS_ACLK
.S00_AXIS_ARESETN(aresetn), // input S00_AXIS_ARESETN
.S00_AXIS_TVALID(axi_icmp_to_icmp_slice_tvalid), // input S00_AXIS_TVALID
.S00_AXIS_TREADY(axi_icmp_to_icmp_slice_tready), // output S00_AXIS_TREADY
.S00_AXIS_TDATA(axi_icmp_to_icmp_slice_tdata), // input [63 : 0] S00_AXIS_TDATA
.S00_AXIS_TKEEP(axi_icmp_to_icmp_slice_tkeep), // input [7 : 0] S00_AXIS_TKEEP
.S00_AXIS_TLAST(axi_icmp_to_icmp_slice_tlast), // input S00_AXIS_TLAST
//UDP
.S01_AXIS_ACLK(aclk), // input S01_AXIS_ACLK
.S01_AXIS_ARESETN(aresetn), // input S01_AXIS_ARESETN
.S01_AXIS_TVALID(axi_udp_to_merge_tvalid), // input S01_AXIS_TVALID
.S01_AXIS_TREADY(axi_udp_to_merge_tready), // output S01_AXIS_TREADY
.S01_AXIS_TDATA(axi_udp_to_merge_tdata), // input [63 : 0] S01_AXIS_TDATA
.S01_AXIS_TKEEP(axi_udp_to_merge_tkeep), // input [7 : 0] S01_AXIS_TKEEP
.S01_AXIS_TLAST(axi_udp_to_merge_tlast), // input S01_AXIS_TLAST
//TCP
.S02_AXIS_ACLK(aclk), // input S01_AXIS_ACLK
.S02_AXIS_ARESETN(aresetn), // input S01_AXIS_ARESETN
.S02_AXIS_TVALID(axi_toe_to_toe_slice_tvalid), // input S01_AXIS_TVALID
.S02_AXIS_TREADY(axi_toe_to_toe_slice_tready), // output S01_AXIS_TREADY
.S02_AXIS_TDATA(axi_toe_to_toe_slice_tdata), // input [63 : 0] S01_AXIS_TDATA
.S02_AXIS_TKEEP(axi_toe_to_toe_slice_tkeep), // input [7 : 0] S01_AXIS_TKEEP
.S02_AXIS_TLAST(axi_toe_to_toe_slice_tlast), // input S01_AXIS_TLAST
.M00_AXIS_ACLK(aclk), // input M00_AXIS_ACLK
.M00_AXIS_ARESETN(aresetn), // input M00_AXIS_ARESETN
.M00_AXIS_TVALID(axi_intercon_to_mie_tvalid), // output M00_AXIS_TVALID
.M00_AXIS_TREADY(axi_intercon_to_mie_tready), // input M00_AXIS_TREADY
.M00_AXIS_TDATA(axi_intercon_to_mie_tdata), // output [63 : 0] M00_AXIS_TDATA
.M00_AXIS_TKEEP(axi_intercon_to_mie_tkeep), // output [7 : 0] M00_AXIS_TKEEP
.M00_AXIS_TLAST(axi_intercon_to_mie_tlast), // output M00_AXIS_TLAST
.S00_ARB_REQ_SUPPRESS(1'b0), // input S00_ARB_REQ_SUPPRESS
.S01_ARB_REQ_SUPPRESS(1'b0), // input S01_ARB_REQ_SUPPRESS
.S02_ARB_REQ_SUPPRESS(1'b0) // input S02_ARB_REQ_SUPPRESS
);
// merges ip and arp
axis_interconnect_2to1 mac_merger (
.ACLK(aclk), // input ACLK
.ARESETN(aresetn), // input ARESETN
.S00_AXIS_ACLK(aclk), // input S00_AXIS_ACLK
.S01_AXIS_ACLK(aclk), // input S01_AXIS_ACLK
.S00_AXIS_ARESETN(aresetn), // input S00_AXIS_ARESETN
.S01_AXIS_ARESETN(aresetn), // input S01_AXIS_ARESETN
.S00_AXIS_TVALID(axi_arp_to_arp_slice_tvalid), // input S00_AXIS_TVALID
.S01_AXIS_TVALID(axi_mie_to_intercon_tvalid), // input S01_AXIS_TVALID
.S00_AXIS_TREADY(axi_arp_to_arp_slice_tready), // output S00_AXIS_TREADY
.S01_AXIS_TREADY(axi_mie_to_intercon_tready), // output S01_AXIS_TREADY
.S00_AXIS_TDATA(axi_arp_to_arp_slice_tdata), // input [63 : 0] S00_AXIS_TDATA
.S01_AXIS_TDATA(axi_mie_to_intercon_tdata), // input [63 : 0] S01_AXIS_TDATA
.S00_AXIS_TKEEP(axi_arp_to_arp_slice_tkeep), // input [7 : 0] S00_AXIS_TKEEP
.S01_AXIS_TKEEP(axi_mie_to_intercon_tkeep), // input [7 : 0] S01_AXIS_TKEEP
.S00_AXIS_TLAST(axi_arp_to_arp_slice_tlast), // input S00_AXIS_TLAST
.S01_AXIS_TLAST(axi_mie_to_intercon_tlast), // input S01_AXIS_TLAST
.M00_AXIS_ACLK(aclk), // input M00_AXIS_ACLK
.M00_AXIS_ARESETN(aresetn), // input M00_AXIS_ARESETN
.M00_AXIS_TVALID(AXI_M_Stream_TVALID), // output M00_AXIS_TVALID
.M00_AXIS_TREADY(AXI_M_Stream_TREADY), // input M00_AXIS_TREADY
.M00_AXIS_TDATA(AXI_M_Stream_TDATA), // output [63 : 0] M00_AXIS_TDATA
.M00_AXIS_TKEEP(AXI_M_Stream_TKEEP), // output [7 : 0] M00_AXIS_TKEEP
.M00_AXIS_TLAST(AXI_M_Stream_TLAST), // output M00_AXIS_TLAST
.S00_ARB_REQ_SUPPRESS(1'b0), // input S00_ARB_REQ_SUPPRESS
.S01_ARB_REQ_SUPPRESS(1'b0) // input S01_ARB_REQ_SUPPRESS
);
assign debug_out_ips[12] = axi_arp_to_arp_slice_tvalid;
assign debug_out_ips[13] = axi_arp_to_arp_slice_tready;
assign debug_out_ips[14] = axi_mie_to_intercon_tvalid;
assign debug_out_ips[15] = axi_mie_to_intercon_tready;
assign debug_out_ips[16] = AXI_M_Stream_TVALID;
assign debug_out_ips[17] = AXI_M_Stream_TREADY;
assign debug_out_ips[18] = AXI_M_Stream_TLAST;
// ARP Server
/*arpServerWrapper arpServerInst (
.axi_arp_to_arp_slice_tvalid(axi_arp_to_arp_slice_tvalid),
.axi_arp_to_arp_slice_tready(axi_arp_to_arp_slice_tready),
.axi_arp_to_arp_slice_tdata(axi_arp_to_arp_slice_tdata),
.axi_arp_to_arp_slice_tkeep(axi_arp_to_arp_slice_tkeep),
.axi_arp_to_arp_slice_tlast(axi_arp_to_arp_slice_tlast),
.axis_arp_lookup_reply_TVALID(axis_arp_lookup_reply_TVALID),
.axis_arp_lookup_reply_TREADY(axis_arp_lookup_reply_TREADY),
.axis_arp_lookup_reply_TDATA(axis_arp_lookup_reply_TDATA),
.axi_arp_slice_to_arp_tvalid(axi_arp_slice_to_arp_tvalid),
.axi_arp_slice_to_arp_tready(axi_arp_slice_to_arp_tready),
.axi_arp_slice_to_arp_tdata(axi_arp_slice_to_arp_tdata),
.axi_arp_slice_to_arp_tkeep(axi_arp_slice_to_arp_tkeep),
.axi_arp_slice_to_arp_tlast(axi_arp_slice_to_arp_tlast),
.axis_arp_lookup_request_TVALID(axis_arp_lookup_request_TVALID),
.axis_arp_lookup_request_TREADY(axis_arp_lookup_request_TREADY),
.axis_arp_lookup_request_TDATA(axis_arp_lookup_request_TDATA),
//.ip_address(arp_ip_address),
.aclk(aclk), // input aclk
.aresetn(aresetn)); // input aresetn*/
arp_server_subnet_ip arp_server_inst(
.m_axis_TVALID(axi_arp_to_arp_slice_tvalid),
.m_axis_TREADY(axi_arp_to_arp_slice_tready),
.m_axis_TDATA(axi_arp_to_arp_slice_tdata),
.m_axis_TKEEP(axi_arp_to_arp_slice_tkeep),
.m_axis_TLAST(axi_arp_to_arp_slice_tlast),
.m_axis_arp_lookup_reply_TVALID(axis_arp_lookup_reply_TVALID),
.m_axis_arp_lookup_reply_TREADY(axis_arp_lookup_reply_TREADY),
.m_axis_arp_lookup_reply_TDATA(axis_arp_lookup_reply_TDATA),
.s_axis_TVALID(axi_arp_slice_to_arp_tvalid),
.s_axis_TREADY(axi_arp_slice_to_arp_tready),
.s_axis_TDATA(axi_arp_slice_to_arp_tdata),
.s_axis_TKEEP(axi_arp_slice_to_arp_tkeep),
.s_axis_TLAST(axi_arp_slice_to_arp_tlast),
.s_axis_arp_lookup_request_TVALID(axis_arp_lookup_request_TVALID),
.s_axis_arp_lookup_request_TREADY(axis_arp_lookup_request_TREADY),
.s_axis_arp_lookup_request_TDATA(axis_arp_lookup_request_TDATA),
.regMacAddress_V(arp_mac_address),
.regIpAddress_V(arp_ip_address),
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
icmp_server_ip icmp_server_inst (
.m_axis_TVALID(axi_icmp_to_icmp_slice_tvalid),
.m_axis_TREADY(axi_icmp_to_icmp_slice_tready),
.m_axis_TDATA(axi_icmp_to_icmp_slice_tdata),
.m_axis_TKEEP(axi_icmp_to_icmp_slice_tkeep),
.m_axis_TLAST(axi_icmp_to_icmp_slice_tlast),
.s_axis_TVALID(axi_icmp_slice_to_icmp_tvalid),
.s_axis_TREADY(axi_icmp_slice_to_icmp_tready),
.s_axis_TDATA(axi_icmp_slice_to_icmp_tdata),
.s_axis_TKEEP(axi_icmp_slice_to_icmp_tkeep),
.s_axis_TLAST(axi_icmp_slice_to_icmp_tlast),
.ttlIn_TVALID(1'b0), // input wire ttlIn_TVALID
.ttlIn_TREADY(), // output wire ttlIn_TREADY
.ttlIn_TDATA(64'h0000000000000000), // input wire [63 : 0] ttlIn_TDATA
.ttlIn_TKEEP(8'h00), // input wire [7 : 0] ttlIn_TKEEP
.ttlIn_TLAST(1'b0), // input wire [0 : 0] ttlIn_TLAST
.udpIn_TVALID(1'b0), // input wire udpIn_TVALID
.udpIn_TREADY(), // output wire udpIn_TREADY
.udpIn_TDATA(64'h0000000000000000), // input wire [63 : 0] udpIn_TDATA
.udpIn_TKEEP(8'h00), // input wire [7 : 0] udpIn_TKEEP
.udpIn_TLAST(1'b0), // input wire [0 : 0] udpIn_TLAST
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
/*
* Slices
*/
// ARP Input Slice
axis_register_slice_64 axis_register_arp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_arp_slice_tvalid),
.s_axis_tready(axi_iph_to_arp_slice_tready),
.s_axis_tdata(axi_iph_to_arp_slice_tdata),
.s_axis_tkeep(axi_iph_to_arp_slice_tkeep),
.s_axis_tlast(axi_iph_to_arp_slice_tlast),
.m_axis_tvalid(axi_arp_slice_to_arp_tvalid),
.m_axis_tready(axi_arp_slice_to_arp_tready),
.m_axis_tdata(axi_arp_slice_to_arp_tdata),
.m_axis_tkeep(axi_arp_slice_to_arp_tkeep),
.m_axis_tlast(axi_arp_slice_to_arp_tlast)
);
// ARP Output Slice
/*axis_register_slice_64 axis_register_arp_out_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_arp_to_arp_slice_tvalid),
.s_axis_tready(axi_arp_to_arp_slice_tready),
.s_axis_tdata(axi_arp_to_arp_slice_tdata),
.s_axis_tkeep(axi_arp_to_arp_slice_tkeep),
.s_axis_tlast(axi_arp_to_arp_slice_tlast),
.m_axis_tvalid(axi_arp_slice_to_mie_tvalid),
.m_axis_tready(axi_arp_slice_to_mie_tready),
.m_axis_tdata(axi_arp_slice_to_mie_tdata),
.m_axis_tkeep(axi_arp_slice_to_mie_tkeep),
.m_axis_tlast(axi_arp_slice_to_mie_tlast)
);*/
// ICMP Input Slice
axis_register_slice_64 axis_register_icmp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_icmp_slice_tvalid),
.s_axis_tready(axi_iph_to_icmp_slice_tready),
.s_axis_tdata(axi_iph_to_icmp_slice_tdata),
.s_axis_tkeep(axi_iph_to_icmp_slice_tkeep),
.s_axis_tlast(axi_iph_to_icmp_slice_tlast),
.m_axis_tvalid(axi_icmp_slice_to_icmp_tvalid),
.m_axis_tready(axi_icmp_slice_to_icmp_tready),
.m_axis_tdata(axi_icmp_slice_to_icmp_tdata),
.m_axis_tkeep(axi_icmp_slice_to_icmp_tkeep),
.m_axis_tlast(axi_icmp_slice_to_icmp_tlast)
);
// ICMP Output Slice
/*axis_register_slice_64 axis_register_icmp_out_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_icmp_to_icmp_slice_tvalid),
.s_axis_tready(axi_icmp_to_icmp_slice_tready),
.s_axis_tdata(axi_icmp_to_icmp_slice_tdata),
.s_axis_tkeep(axi_icmp_to_icmp_slice_tkeep),
.s_axis_tlast(axi_icmp_to_icmp_slice_tlast),
.m_axis_tvalid(axi_icmp_slice_to_mie_tvalid),
.m_axis_tready(axi_icmp_slice_to_mie_tready),
.m_axis_tdata(axi_icmp_slice_to_mie_tdata),
.m_axis_tkeep(axi_icmp_slice_to_mie_tkeep),
.m_axis_tlast(axi_icmp_slice_to_mie_tlast)
);*/
// UDP Input Slice
axis_register_slice_64 axis_register_udp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_udp_slice_tvalid),
.s_axis_tready(axi_iph_to_udp_slice_tready),
.s_axis_tdata(axi_iph_to_udp_slice_tdata),
.s_axis_tkeep(axi_iph_to_udp_slice_tkeep),
.s_axis_tlast(axi_iph_to_udp_slice_tlast),
.m_axis_tvalid(axi_udp_slice_to_udp_tvalid),
.m_axis_tready(axi_udp_slice_to_udp_tready),
.m_axis_tdata(axi_udp_slice_to_udp_tdata),
.m_axis_tkeep(axi_udp_slice_to_udp_tkeep),
.m_axis_tlast(axi_udp_slice_to_udp_tlast)
);
// TOE Input Slice
axis_register_slice_64 axis_register_toe_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_toe_slice_tvalid),
.s_axis_tready(axi_iph_to_toe_slice_tready),
.s_axis_tdata(axi_iph_to_toe_slice_tdata),
.s_axis_tkeep(axi_iph_to_toe_slice_tkeep),
.s_axis_tlast(axi_iph_to_toe_slice_tlast),
.m_axis_tvalid(axi_toe_slice_to_toe_tvalid),
.m_axis_tready(axi_toe_slice_to_toe_tready),
.m_axis_tdata(axi_toe_slice_to_toe_tdata),
.m_axis_tkeep(axi_toe_slice_to_toe_tkeep),
.m_axis_tlast(axi_toe_slice_to_toe_tlast)
);
// TOE Output Slice
/*axis_register_slice_64 axis_register_toe_out_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_toe_to_toe_slice_tvalid),
.s_axis_tready(axi_toe_to_toe_slice_tready),
.s_axis_tdata(axi_toe_to_toe_slice_tdata),
.s_axis_tkeep(axi_toe_to_toe_slice_tkeep),
.s_axis_tlast(axi_toe_to_toe_slice_tlast),
.m_axis_tvalid(axi_toe_slice_to_mie_tvalid),
.m_axis_tready(axi_toe_slice_to_mie_tready),
.m_axis_tdata(axi_toe_slice_to_mie_tdata),
.m_axis_tkeep(axi_toe_slice_to_mie_tkeep),
.m_axis_tlast(axi_toe_slice_to_mie_tlast)
);*/
//debug
/*reg[3:0] pkg_count;
reg[3:0] port_count;
always @(posedge aclk)
begin
if (aresetn == 0) begin
pkg_count <= 0;
port_count <= 0;
end
else begin
if ((axis_dhcp_tx_data_tvalid == 1'b1) && (axis_dhcp_tx_data_tready == 1'b1)) begin// && (axi_toe_to_toe_slice_tlast == 1'b1)) begin
pkg_count <= pkg_count + 1;
end
if ((axis_dhcp_open_port_status_tvalid == 1'b1) && (axis_dhcp_open_port_status_tready == 1'b1)) begin
port_count <= port_count + 1;
end
end
end
reg[255:0] debug_r;
reg[255:0] debug_r2;
always @(posedge aclk)
begin
debug_r[0] <= axis_dhcp_rx_data_tvalid;
debug_r[1] <= axis_dhcp_rx_data_tready;
debug_r[65:2] <= axis_dhcp_rx_data_tdata;
debug_r[73:66] <= axis_dhcp_rx_data_tkeep;
debug_r[74] <= axis_dhcp_rx_data_tlast;
debug_r[75] <= axi_udp_to_merge_tvalid;
debug_r[76] <= axi_udp_to_merge_tready;
debug_r[140:77] <= axi_udp_to_merge_tdata;
debug_r[148:141] <= axi_udp_to_merge_tkeep;
debug_r[149] <= axi_udp_to_merge_tlast;
debug_r[181:150] <= dhcp_ip_address;
debug_r[182] <= dhcp_ip_address_en;
debug_r[214:183] <= arp_ip_address;
/*debug_r[150] <= axi_iph_to_udp_tvalid;
debug_r[151] <= axi_iph_to_udp_tready;
debug_r[215:152] <= axi_iph_to_udp_tdata;
debug_r[223:216] <= axi_iph_to_udp_tkeep;
debug_r[224] <= axi_iph_to_udp_tlast;
debug_r[225] <= axis_dhcp_tx_data_tvalid;
debug_r[226] <= axis_dhcp_tx_data_tready;
debug_r[242:227] <= axis_dhcp_tx_data_tdata[15:0];
debug_r[243] <= axis_dhcp_tx_data_tlast;
debug_r[244] <= axis_dhcp_open_port_tvalid;
debug_r[245] <= axis_dhcp_open_port_tready;
//debug_r[243] <= axis_arp_lookup_request_TDATA),
debug_r[246] <= axis_dhcp_open_port_status_tvalid;
debug_r[247] <= axis_dhcp_open_port_status_tready;
//debug_r[248] <= axis_dhcp_open_port_status_tdata[0];
//debug_r[248] <= axis_txbuffer2tcp_TVALID;
//debug_r[249] <= axis_txbuffer2tcp_TREADY;
//debug_r[247] <= axis_txbuffer2tcp_TDATA;
//debug_r[247] <= axis_txbuffer2tcp_TKEEP;
//debug_r[250] <= axis_txbuffer2tcp_TLAST;*/
/*debug_r[251:248] <= port_count;
debug_r[255:252] <= pkg_count;
debug_r2 <= debug_r;
end
wire [35:0] control0;
wire [35:0] control1;
wire [63:0] vio_signals;
wire [255:0] debug_signal;
assign debug_signal = debug_r2;
icon icon_isnt
(
.CONTROL0 (control0),
.CONTROL1 (control1)
);
ila_256 ila_inst
(
.CLK (aclk),
.CONTROL (control0),
.TRIG0 (debug_signal)
);
vio vio_inst
(
.CLK (aclk),
.CONTROL (control1),
.SYNC_OUT (vio_signals)
);*/
endmodule
|
module system_clk_wiz_1_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_system_clk_wiz_1_0;
wire clk_in2_system_clk_wiz_1_0;
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_1_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_system_clk_wiz_1_0;
wire clk_out2_system_clk_wiz_1_0;
wire clk_out3_system_clk_wiz_1_0;
wire clk_out4_system_clk_wiz_1_0;
wire clk_out5_system_clk_wiz_1_0;
wire clk_out6_system_clk_wiz_1_0;
wire clk_out7_system_clk_wiz_1_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_1_0;
wire clkfbout_buf_system_clk_wiz_1_0;
wire clkfboutb_unused;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (10),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.0))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_1_0),
.CLKOUT0 (clk_out1_system_clk_wiz_1_0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_1_0),
.CLKIN1 (clk_in1_system_clk_wiz_1_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (1'b0));
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_1_0),
.I (clkfbout_system_clk_wiz_1_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_1_0));
endmodule
|
module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b);
parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL";
parameter clock_enable_output_a = "NORMAL";
parameter wrcontrol_aclr_a = "NONE";
parameter indata_aclr_a = "NONE";
parameter address_aclr_a = "NONE";
parameter outdata_aclr_a = "NONE";
parameter outdata_reg_a = "UNREGISTERED";
parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_b = "UNREGISTERED";
parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter power_up_uninitialized = "FALSE";
parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
parameter width_byteena_a = 1;
parameter numwords_b = 0;
parameter numwords_a = 0;
parameter widthad_b = 1;
parameter width_b = 1;
parameter widthad_a = 1;
parameter width_a = 1;
// Port A declarations
output [35:0] q_a;
input [35:0] data_a;
input [7:0] address_a;
input wren_a;
input rden_a;
// Port B declarations
output [35:0] q_b;
input [35:0] data_b;
input [7:0] address_b;
input wren_b;
input rden_b;
// Control signals
input clock0, clock1;
input clocken0, clocken1, clocken2, clocken3;
input aclr0, aclr1;
input addressstall_a;
input addressstall_b;
// TODO: Implement the correct simulation model
endmodule
|
module <module_name> (
);
//----------------------- Global parameters Declarations ------------------
//----------------------- Input Declarations ------------------------------
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
//----------------------- Internal Wire Declarations ----------------------
//----------------------- FSM Parameters --------------------------------------
//only for FSM state vector representation
parameter [?:0] // synopsys enum fsm_pstate
IDLE = ,
//----------------------- FSM Register Declarations ------------------
reg [?:0] // synopsys enum fsm_pstate
fsm_pstate, next_state;
//----------------------- FSM String Declarations ------------------
//synthesis translate_off
reg [8*?:0] state_name;//"state name" is user defined
//synthesis translate_on
//----------------------- FSM Debugging Logic Declarations ------------------
//synthesis translate_off
always @ (fsm_pstate)
begin
case (fsm_pstate)
<IDLE> : state_name = "IDLE";
<state2> : state_name = "state2";
.
.
.
<default> : state_name = "default";
endcase
end
//synthesis translate_on
//----------------------- Input/Output Registers --------------------------
//----------------------- Start of Code -----------------------------------
//code should be <=200 lines
/* comments for assign statements
*/
//assign statements
/* comments for combinatory logic
Asynchronous part of FSM
*/
/* comments for sequential logic
*/
//<sequential logic>;
endmodule
|
module tb (
input wire FCLK_IN,
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
output wire CLK_BX,
input wire [64*64-1:0] HIT,
input wire TRIGGER,
output wire [1:0] RESET
);
wire [19:0] SRAM_A;
wire [15:0] SRAM_IO;
wire SRAM_BHE_B;
wire SRAM_BLE_B;
wire SRAM_CE1_B;
wire SRAM_OE_B;
wire SRAM_WE_B;
//wire [1:0] RESET;
//wire CLK_BX;
wire TRIGGER_DUT;
wire CLK_CNFG;
wire EN_PIX_SR_CNFG;
wire LD_CNFG;
wire SI_CNFG;
wire SO_CNFG;
wire PIX_D_CONF;
wire CLK_DATA;
wire OUT_DATA;
wire HIT_OR;
wire INJ;
fe65p2_mio fpga (
.FCLK_IN(FCLK_IN),
.BUS_DATA(BUS_DATA),
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.FDATA(FD),
.FREAD(FREAD),
.FSTROBE(FSTROBE),
.FMODE(FMODE),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.DUT_RESET(RESET) ,
.DUT_CLK_BX(CLK_BX),
.DUT_TRIGGER(TRIGGER_DUT),
.DUT_INJ(INJ),
.DUT_CLK_CNFG(CLK_CNFG),
.DUT_EN_PIX_SR_CNFG(EN_PIX_SR_CNFG),
.DUT_LD_CNFG(LD_CNFG),
.DUT_SI_CNFG(SI_CNFG),
.DUT_SO_CNFG(SO_CNFG),
.DUT_PIX_D_CONF(PIX_D_CONF),
.DUT_CLK_DATA(CLK_DATA),
.DUT_OUT_DATA(OUT_DATA),
.DUT_HIT_OR(HIT_OR)
);
wire [64*64-1:0] ANA_HIT;
wire TRIGGER_FE;
assign TRIGGER_FE = TRIGGER_DUT | TRIGGER;
wire PrmpVbp, vthin1, vthin2, vff, VctrCF0, VctrCF1, PrmpVbnFol, vbnLcc, compVbn, preCompVbn, RefVbn;
wire [31:0] test_out1L, test_out1R, test_out2L, test_out2R, test_out2bL, test_out2bR;
wire [63:0] outDiscInvR;
wire HIT_OR_N, OUT_DATA_N;
wire OUT_DATA_P;
fe65p2 dut(
ANA_HIT,
RESET ,
CLK_BX,
TRIGGER_FE,
HIT_OR,
HIT_OR_N,
CLK_CNFG,
EN_PIX_SR_CNFG,
LD_CNFG,
SI_CNFG,
SO_CNFG,
PIX_D_CONF,
CLK_DATA,
OUT_DATA_P,
OUT_DATA_N,
~INJ,
PrmpVbp, vthin1, vthin2, vff, VctrCF0, VctrCF1, PrmpVbnFol, vbnLcc, compVbn, preCompVbn, RefVbn,
test_out1L, test_out1R, test_out2L, test_out2R, test_out2bL, test_out2bR, outDiscInvR
);
assign #5500 OUT_DATA = OUT_DATA_P;
//SRAM Model
reg [15:0] sram [1048576-1:0];
assign SRAM_IO = !SRAM_OE_B ? sram[SRAM_A] : 16'hzzzz;
always@(negedge SRAM_WE_B)
sram[SRAM_A] <= SRAM_IO;
assign ANA_HIT = HIT;
initial begin
$dumpfile("fe65p2.vcd");
$dumpvars(0);
//force dut.i_output_data.iser_div.cnt = 4'b0;
//#10 force CLK_DATA = 4'b0;
//#100000 force CLK_DATA = 4'b1;
//#10000 release CLK_DATA;
//#50000 release dut.i_output_data.iser_div.cnt;
end
endmodule
|
module SHIFT (
data,
direction,
distance,
result);
input [15:0] data;
input direction;
input [3:0] distance;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_clshift LPM_CLSHIFT_component (
.data (data),
.direction (direction),
.distance (distance),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.overflow (),
.underflow ()
// synopsys translate_on
);
defparam
LPM_CLSHIFT_component.lpm_shifttype = "LOGICAL",
LPM_CLSHIFT_component.lpm_type = "LPM_CLSHIFT",
LPM_CLSHIFT_component.lpm_width = 16,
LPM_CLSHIFT_component.lpm_widthdist = 4;
endmodule
|
module sky130_fd_sc_ms__dlymetal6s6s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
|
module seg_disp(
input clk,
input[7:0] d1,
input[7:0] d2,
input[7:0] d3,
input[7:0] d4,
input dp,
output reg[6:0] seg,
output reg[3:0] an,
output dp_pin
);
wire[6:0] seg1;
wire[6:0] seg2;
wire[6:0] seg3;
wire[6:0] seg4;
reg[2:0] state = 0;
assign dp_pin = 1;
number_to_seg dd1(d1, seg1);
number_to_seg dd2(d2, seg2);
number_to_seg dd3(d3, seg3);
number_to_seg dd4(d4, seg4);
wire nd1 = (d1 == 0);
wire nd2 = (d2 == 0);
wire nd3 = (d3 == 0);
always @(posedge clk) begin
case (state)
default: state <= 0;
0: begin
seg <= seg1;
an <= nd1 ? 4'b1111 : 4'b0111;
state <= state + 1;
end
1: begin
seg <= seg2;
an <= nd1 && nd2 ? 4'b1111 : 4'b1011;
state <= state + 1;
end
2: begin
seg <= seg3;
an <= nd1 && nd2 && nd3 ? 4'b1111 : 4'b1101;
state <= state + 1;
end
3: begin
seg <= seg4;
an <= 4'b1110;
state <= 0;
end
endcase
end
endmodule
|
module number_to_seg(input[7:0] d, output[6:0] seg);
assign seg = (d == 0) ? 7'b1000000 :
(d == 1) ? 7'b1111001 :
(d == 2) ? 7'b0100100 :
(d == 3) ? 7'b0110000 :
(d == 4) ? 7'b0011001 :
(d == 5) ? 7'b0010010 :
(d == 6) ? 7'b0000010 :
(d == 7) ? 7'b1111000 :
(d == 8) ? 7'b0000000 :
(d == 9) ? 7'b0010000 : 7'b1000000;
endmodule
|
module num_to_digits(input[11:0] _num, output[3:0] _thousands, output [3:0] _hundreds, output [3:0] _tens, output [3:0] _ones);
assign _thousands = (_num % 10000) / 1000;
assign _hundreds = (_num % 1000) / 100;
assign _tens = (_num % 100) / 10;
assign _ones = _num % 10;
endmodule
|
module num_to_digits1(input[17:0] _num, output[3:0] _thousands, output [3:0] _hundreds, output [3:0] _tens, output [3:0] _ones);
assign _thousands = (_num % 10000) / 1000;
assign _hundreds = (_num % 1000) / 100;
assign _tens = (_num % 100) / 10;
assign _ones = _num % 10;
endmodule
|
module sky130_fd_sc_hdll__clkinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module CLKPLL (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [5:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 7,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 50000000,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 41176471,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=CLKPLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
|
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ls__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
|
module Fifo #(
parameter WIDTH = 8, ///< Width of data word
parameter LOG2_DEPTH = 4 ///< log2(depth of FIFO). Must be an integer
)
(
// Inputs
input clk, ///< System clock
input rst, ///< Reset FIFO pointer
input write, ///< Write strobe (1 clk)
input read, ///< Read strobe (1 clk)
input [WIDTH-1:0] dataIn, ///< Data to write
// Outputs
output wire [WIDTH-1:0] dataOut, ///< Data from FIFO
output reg dataPresent, ///< Data is present in FIFO
output wire halfFull, ///< FIFO is half full
output wire full ///< FIFO is full
);
reg [WIDTH-1:0] memory[2**LOG2_DEPTH-1:0];
reg [LOG2_DEPTH-1:0] pointer;
wire zero;
integer i;
// Zero out internal memory
initial begin
pointer = 'd0;
dataPresent = 1'b0;
for (i=0; i<(2**LOG2_DEPTH); i=i+1) begin
memory[i] = 'd0;
end
end
// Shift register for FIFO
always @(posedge clk) begin
if (write) begin
memory[0] <= dataIn;
for (i=1; i<(2**LOG2_DEPTH); i=i+1) begin
memory[i] <= memory[i-1];
end
end
end
assign dataOut = memory[pointer];
// Pointer for FIFO
always @(posedge clk) begin
if (rst) begin
pointer <= 'd0;
dataPresent <= 1'b0;
end
else begin
dataPresent <= write
| (dataPresent & ~zero)
| (dataPresent & zero & ~read);
case ({read, write})
2'b00 : pointer <= pointer;
2'b01 : pointer <= (!full && dataPresent) ? pointer + 2'd1 : pointer;
2'b10 : pointer <= (!zero) ? pointer - 2'd1 : pointer;
2'b11 : pointer <= pointer;
endcase
end
end
assign zero = ~|pointer;
assign halfFull = pointer[LOG2_DEPTH-1];
assign full = &pointer;
endmodule
|
module or2(output Z, input A, B);
wire i;
not(Z, i);
nor(i, A, B);
endmodule
|
module or4(output Z, input A, B, C, D);
wire [1:0]i;
or2 o0(i[0], A, B),
o1(i[1], C, D),
o2(Z, i[0], i[1]);
endmodule
|
module and2(output Z, input A, B);
nand(nz, A, B);
not(Z, nz);
endmodule
|
module and3(output Z, input A, B, C);
wire i;
and2 a0(i, A, B),
a1(Z, i, C);
endmodule
|
module xnor2(output Z, input A, B);
wire [1:0]i;
not(na, A);
not(nb, B);
and2 a0(i[0], A, B),
a1(i[1], na, nb);
or2 o0(Z, i[0], i[1]);
endmodule
|
module xor2(output Z, input A, B);
wire [1:0]i;
not (na, A);
not (nb, B);
and2 a0(i[0], A, nb),
a1(i[1], na, B);
or2 o0(Z, i[0], i[1]);
endmodule
|
module op_00(output Z, input A, B);
or2 o(Z, A, B);
endmodule
|
module op_01(output Z, input A, B);
xor2 x(Z, A, B);
endmodule
|
module op_10(output Z, input A, B, C);
wire i;
xnor2 x(i, B, C);
and2 a(Z, i, A);
endmodule
|
module op_11(output Z, input A, B, C);
wire i;
xor2 x(i, A, B);
nand n(Z, i, C);
endmodule
|
module mux_4_1(output Z, input [1:0] sel, input [3:0] i);
wire [1:0]n_s;
wire [3:0]a;
not(n_s[0], sel[0]);
not(n_s[1], sel[1]);
and3 a0(a[0], n_s[1], n_s[0], i[0]),
a1(a[1], n_s[1], sel[0], i[1]),
a2(a[2], sel[1], n_s[0], i[2]),
a3(a[3], sel[1], sel[0], i[3]);
or4 o0(Z, a[0], a[1], a[2], a[3]);
endmodule
|
module alu_01(output Z, input [1:0]op, input A, B, C);
wire [3:0]op_z;
op_00 op00(op_z[0], A, B);
op_01 op01(op_z[1], A, B);
op_10 op10(op_z[2], A, B, C);
op_11 op11(op_z[3], A, B, C);
mux_4_1 mux(Z, op, op_z);
endmodule
|
module alu_02(output [1:0]Z, input [1:0]op, input [1:0] A, B, C);
alu_01 a0(Z[0], op, A[0], B[0], C[0]),
a1(Z[1], op, A[1], B[1], C[1]);
endmodule
|
module alu_04(output [3:0]Z, input [1:0]op, input [3:0] A, B, C);
alu_02 a0(Z[1:0], op, A[1:0], B[1:0], C[1:0]),
a1(Z[3:2], op, A[3:2], B[3:2], C[3:2]);
endmodule
|
module alu_08(output [7:0]Z, input [1:0]op, input [7:0] A, B, C);
alu_04 a0(Z[3:0], op, A[3:0], B[3:0], C[3:0]),
a1(Z[7:4], op, A[7:4], B[7:4], C[7:4]);
endmodule
|
module alu_16(output [15:0]Z, input [1:0]op, input [15:0] A, B, C);
alu_08 a0(Z[7:0], op, A[7:0], B[7:0], C[7:0]),
a1(Z[15:8], op, A[15:8], B[15:8], C[15:8]);
endmodule
|
module alu_32(output [31:0]Z, input [1:0]op, input [31:0] A, B, C);
alu_16 a0(Z[15:0], op, A[15:0], B[15:0], C[15:0]),
a1(Z[31:16], op, A[31:16], B[31:16], C[31:16]);
endmodule
|
module p2_tb();
reg [31:0]A, B, C;
reg [1:0]op;
wire [31:0] Z;
alu_32 device(Z, op, A, B, C);
integer op_i, val_i;
initial begin
$dumpfile("p2.vcd");
$dumpvars(0, device);
$monitor("op(%b) A=%b B=%b C=%b => %b", op, A, B, C, Z);
for( op_i = 0; op_i <= 'b11; op_i = op_i + 1) begin
op = op_i[1:0];
for(val_i = 0; val_i <= 'b111; val_i = val_i + 1) begin
A = {32{val_i[2]}};
B = {32{val_i[1]}};
C = {32{val_i[0]}};
#10;
end
end
end
endmodule
|
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n3505, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM,
ZERO_FLAG_NRM, SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1473, n1474, n1476, n1477, n1479, n1480, n1482, n1483, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796,
n1797, n1798, n1799, n1800, n1801, n1802, n1803,
DP_OP_15J9_123_7955_n11, DP_OP_15J9_123_7955_n10,
DP_OP_15J9_123_7955_n9, DP_OP_15J9_123_7955_n8,
DP_OP_15J9_123_7955_n7, DP_OP_15J9_123_7955_n6, n1804, n1805, n1806,
n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816,
n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826,
n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836,
n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846,
n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856,
n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866,
n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876,
n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886,
n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896,
n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906,
n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916,
n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926,
n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936,
n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946,
n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956,
n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966,
n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976,
n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986,
n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996,
n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006,
n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016,
n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026,
n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036,
n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046,
n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056,
n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066,
n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076,
n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086,
n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096,
n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106,
n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116,
n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126,
n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136,
n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146,
n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156,
n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166,
n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176,
n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186,
n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196,
n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206,
n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216,
n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226,
n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236,
n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246,
n2247, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2594, n2595, n2596, n2597, n2598,
n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608,
n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618,
n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628,
n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638,
n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648,
n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658,
n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668,
n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678,
n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688,
n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698,
n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708,
n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718,
n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728,
n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738,
n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748,
n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758,
n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768,
n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778,
n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788,
n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798,
n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808,
n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818,
n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828,
n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838,
n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848,
n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858,
n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868,
n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878,
n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888,
n2889, n2890, n2891, n2892, n2893, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141,
n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151,
n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161,
n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171,
n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181,
n3182, n3183, n3184, n3185, n3186, n3187, n3189, n3190, n3191, n3192,
n3194, n3195, n3196, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3210, n3211, n3212, n3213, n3214, n3215,
n3217, n3218, n3219, n3220, n3221, n3223, n3224, n3225, n3226, n3227,
n3228, n3229, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238,
n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248,
n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258,
n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268,
n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278,
n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288,
n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298,
n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308,
n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318,
n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328,
n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338,
n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348,
n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358,
n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368,
n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378,
n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388,
n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398,
n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408,
n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418,
n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428,
n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438,
n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448,
n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458,
n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468,
n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478,
n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488,
n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498,
n3499, n3500, n3501, n3503, n3504;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [50:0] DmP_mant_SHT1_SW;
wire [5:1] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [44:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [5:1] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [54:2] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n1798), .CK(clk), .RN(n3495), .Q(
Shift_reg_FLAGS_7[3]), .QN(n1886) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1730), .CK(clk), .RN(n3447), .Q(
intAS) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n3448),
.Q(intDY_EWSW[0]), .QN(n1820) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1626), .CK(clk), .RN(n3450), .QN(
n1819) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1616), .CK(clk), .RN(n3448), .QN(
n1828) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1614), .CK(clk), .RN(n3451), .QN(
n1827) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1613), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1604), .CK(clk), .RN(n3441),
.QN(n1822) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1603), .CK(clk), .RN(n3452),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n3501),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1601), .CK(clk), .RN(n3441),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1600), .CK(clk), .RN(n3452),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1599), .CK(clk), .RN(n3470),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1587), .CK(clk), .RN(n3460), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1586), .CK(clk), .RN(n3501), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1585), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1584), .CK(clk), .RN(n3462), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1583), .CK(clk), .RN(n3441), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1582), .CK(clk), .RN(n3457), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1581), .CK(clk), .RN(n3499), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1580), .CK(clk), .RN(n3452), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1579), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1578), .CK(clk), .RN(n3460), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1577), .CK(clk), .RN(n3501), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1576), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1575), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1574), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1573), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1572), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1571), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1570), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1569), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1568), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1567), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1566), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1565), .CK(clk), .RN(n3453), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1564), .CK(clk), .RN(n3500), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1563), .CK(clk), .RN(n3500), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1562), .CK(clk), .RN(n3476), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1561), .CK(clk), .RN(n3477), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1560), .CK(clk), .RN(n3478), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1559), .CK(clk), .RN(n3462), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1558), .CK(clk), .RN(n3499), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1557), .CK(clk), .RN(n3460), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1556), .CK(clk), .RN(n3441), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1555), .CK(clk), .RN(n3468), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1554), .CK(clk), .RN(n3442), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1553), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1552), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1551), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1550), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1549), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1548), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1547), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1546), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1545), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1544), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1543), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1542), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1541), .CK(clk), .RN(n3454), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1540), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1539), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1538), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1537), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1536), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1530), .CK(clk), .RN(n3455), .QN(
n1837) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1529), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1528), .CK(clk), .RN(n3456), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1527), .CK(clk), .RN(n3456), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1526), .CK(clk), .RN(n3456), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1525), .CK(clk), .RN(n3456), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1524), .CK(clk), .RN(n3456), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1523), .CK(clk), .RN(n3456), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1522), .CK(clk), .RN(n3456), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1521), .CK(clk), .RN(n3456), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1520), .CK(clk), .RN(n3456), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1519), .CK(clk), .RN(n3456), .Q(
DMP_SFG[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1518), .CK(clk), .RN(n3456), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1517), .CK(clk), .RN(n3456), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1516), .CK(clk), .RN(n3444), .Q(
DMP_SFG[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1515), .CK(clk), .RN(n3498), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1514), .CK(clk), .RN(n3500), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1513), .CK(clk), .RN(n3460), .Q(
DMP_SFG[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1512), .CK(clk), .RN(n3476), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1511), .CK(clk), .RN(n3500), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1510), .CK(clk), .RN(n3470), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1509), .CK(clk), .RN(n3477), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1508), .CK(clk), .RN(n3500), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1507), .CK(clk), .RN(n3448), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1506), .CK(clk), .RN(n3478), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1505), .CK(clk), .RN(n3500), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1504), .CK(clk), .RN(n3492), .Q(
DMP_SFG[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1503), .CK(clk), .RN(n3457), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1502), .CK(clk), .RN(n3470), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1501), .CK(clk), .RN(n3468), .Q(
DMP_SFG[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1500), .CK(clk), .RN(n3494), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1499), .CK(clk), .RN(n3481), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1498), .CK(clk), .RN(n3469), .Q(
DMP_SFG[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1497), .CK(clk), .RN(n3492), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1496), .CK(clk), .RN(n3457), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1495), .CK(clk), .RN(n3470), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1494), .CK(clk), .RN(n3468), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1493), .CK(clk), .RN(n3481), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1492), .CK(clk), .RN(n3496), .Q(
DMP_SFG[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1491), .CK(clk), .RN(n3497), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1490), .CK(clk), .RN(n3493), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1489), .CK(clk), .RN(n3458), .Q(
DMP_SFG[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1488), .CK(clk), .RN(n3474), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1487), .CK(clk), .RN(n3496), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1486), .CK(clk), .RN(n3497), .Q(
DMP_SFG[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1485), .CK(clk), .RN(n3493), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n3439), .CK(clk), .RN(n3481), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1482), .CK(clk), .RN(n3458), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n3438), .CK(clk), .RN(n3470), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1479), .CK(clk), .RN(n3474), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n3437), .CK(clk), .RN(n3488), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1476), .CK(clk), .RN(n3496), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n3436), .CK(clk), .RN(n3488), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1473), .CK(clk), .RN(n3493), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n3435), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1470), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1469), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1467), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1466), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1464), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1463), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1461), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1460), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1458), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1457), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1455), .CK(clk), .RN(n3459), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1454), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1452), .CK(clk), .RN(n3462), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1451), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1449), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1448), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n3499), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1440), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1437), .CK(clk), .RN(n3499), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1436), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1434), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1433), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1431), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1430), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1428), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1427), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1425), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1424), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1422), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1421), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1419), .CK(clk), .RN(n3461), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1418), .CK(clk), .RN(n3461), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1416), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1415), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1413), .CK(clk), .RN(n3499), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1412), .CK(clk), .RN(n3460), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1410), .CK(clk), .RN(n3462), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1409), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1407), .CK(clk), .RN(n3460), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1406), .CK(clk), .RN(n3462), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1404), .CK(clk), .RN(n3499), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1403), .CK(clk), .RN(n3460), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1401), .CK(clk), .RN(n3462), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1400), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1398), .CK(clk), .RN(n3459), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1397), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1395), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1394), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1392), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1391), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1389), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1388), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1386), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1385), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1383), .CK(clk), .RN(n3463), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1382), .CK(clk), .RN(n3463), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1380), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1379), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1377), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1376), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1374), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1373), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1371), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1370), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1368), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1367), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1365), .CK(clk), .RN(n3464), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1364), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1363), .CK(clk), .RN(n3465), .Q(
DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1362), .CK(clk), .RN(n3465), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1361), .CK(clk), .RN(n3468), .Q(
DMP_exp_NRM2_EW[0]), .QN(n3351) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1360), .CK(clk), .RN(n3465), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1359), .CK(clk), .RN(n3465), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1358), .CK(clk), .RN(n3465), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n3465), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1355), .CK(clk), .RN(n3465), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1354), .CK(clk), .RN(n3465), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1353), .CK(clk), .RN(n3465), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(n3465), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1350), .CK(clk), .RN(n3465), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1349), .CK(clk), .RN(n3465), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1348), .CK(clk), .RN(n3490), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1347), .CK(clk), .RN(n3490), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1345), .CK(clk), .RN(n3466), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1344), .CK(clk), .RN(n3466), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1343), .CK(clk), .RN(n3466), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1342), .CK(clk), .RN(n3466), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1340), .CK(clk), .RN(n3466), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1339), .CK(clk), .RN(n3466), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1338), .CK(clk), .RN(n3466), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1337), .CK(clk), .RN(n3466), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1335), .CK(clk), .RN(n3466), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1334), .CK(clk), .RN(n3466), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1333), .CK(clk), .RN(n3467), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1332), .CK(clk), .RN(n3459), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1330), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1329), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1328), .CK(clk), .RN(n3467), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1327), .CK(clk), .RN(n3459), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1325), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1324), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1323), .CK(clk), .RN(n3467), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1322), .CK(clk), .RN(n3459), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1320), .CK(clk), .RN(n3467), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1319), .CK(clk), .RN(n3459), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1318), .CK(clk), .RN(n3495), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1317), .CK(clk), .RN(n3496), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1315), .CK(clk), .RN(n3500), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1314), .CK(clk), .RN(n3458), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1313), .CK(clk), .RN(n3497), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1312), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1310), .CK(clk), .RN(n3504), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1308), .CK(clk), .RN(n3484), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1306), .CK(clk), .RN(n3493), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1304), .CK(clk), .RN(n3481), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1302), .CK(clk), .RN(n3469), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1300), .CK(clk), .RN(n3492), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1298), .CK(clk), .RN(n3457), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1296), .CK(clk), .RN(n3470), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1294), .CK(clk), .RN(n3468), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1292), .CK(clk), .RN(n3457), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1290), .CK(clk), .RN(n3470), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1288), .CK(clk), .RN(n3468), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1286), .CK(clk), .RN(n3492), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1284), .CK(clk), .RN(n3469), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1282), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1280), .CK(clk), .RN(n3481), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1278), .CK(clk), .RN(n3469), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1277), .CK(clk), .RN(n3492),
.QN(n1838) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1276), .CK(clk), .RN(n3457), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1274), .CK(clk), .RN(n3470), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1272), .CK(clk), .RN(n3468), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1270), .CK(clk), .RN(n3481), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1269), .CK(clk), .RN(n3469),
.QN(n1834) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1268), .CK(clk), .RN(n3456), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1266), .CK(clk), .RN(n3465), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1264), .CK(clk), .RN(n3461), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1262), .CK(clk), .RN(n3454), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1261), .CK(clk), .RN(n3490),
.QN(n1812) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1260), .CK(clk), .RN(n3478), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1258), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1256), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1254), .CK(clk), .RN(n3444), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1252), .CK(clk), .RN(n3462), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1251), .CK(clk), .RN(n3454),
.QN(n1813) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1250), .CK(clk), .RN(n3441), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1248), .CK(clk), .RN(n3441), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1246), .CK(clk), .RN(n3454), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1244), .CK(clk), .RN(n3449), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1242), .CK(clk), .RN(n3468), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1240), .CK(clk), .RN(n3443), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1238), .CK(clk), .RN(n3465), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1237), .CK(clk), .RN(n3457),
.QN(n1814) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1236), .CK(clk), .RN(n3443), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1234), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1232), .CK(clk), .RN(n2009), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1231), .CK(clk), .RN(n3471),
.QN(n1830) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1230), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1229), .CK(clk), .RN(n3471),
.QN(n1832) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1228), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1227), .CK(clk), .RN(n3471),
.QN(n1811) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1226), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1224), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1223), .CK(clk), .RN(n3471),
.QN(n1831) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1222), .CK(clk), .RN(n3471), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1220), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1219), .CK(clk), .RN(n3472),
.QN(n1829) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1218), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1217), .CK(clk), .RN(n3472),
.QN(n1835) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1216), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1214), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1213), .CK(clk), .RN(n3472),
.QN(n1836) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1212), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1210), .CK(clk), .RN(n3472), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1208), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1207), .CK(clk), .RN(n3473),
.QN(n1833) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1205), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[53]), .QN(n3318) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1202), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[56]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1198), .CK(clk), .RN(n3473), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1197), .CK(clk), .RN(n3473), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1196), .CK(clk), .RN(n3458), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1195), .CK(clk), .RN(n3474), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1194), .CK(clk), .RN(n3496),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1192), .CK(clk), .RN(n3493), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n3434), .CK(clk), .RN(n3457), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1189), .CK(clk), .RN(n3458), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1188), .CK(clk), .RN(n3474), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1187), .CK(clk), .RN(n3496), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1186), .CK(clk), .RN(n3493), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1185), .CK(clk), .RN(n3458),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1155), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[43]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1151), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[47]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1149), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[49]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1141), .CK(clk), .RN(n3494),
.Q(LZD_output_NRM2_EW[5]), .QN(n3364) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1140), .CK(clk), .RN(n3474), .QN(
n1840) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1138), .CK(clk), .RN(n3469),
.Q(LZD_output_NRM2_EW[0]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1137), .CK(clk), .RN(n3493), .QN(
n1839) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1135), .CK(clk), .RN(n3468),
.Q(LZD_output_NRM2_EW[4]), .QN(n3365) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1130), .CK(clk), .RN(n3492),
.Q(LZD_output_NRM2_EW[1]), .QN(n3353) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1129), .CK(clk), .RN(n3475), .QN(
n1841) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1125), .CK(clk), .RN(n3470),
.Q(LZD_output_NRM2_EW[3]), .QN(n3361) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1122), .CK(clk), .RN(n3457),
.Q(LZD_output_NRM2_EW[2]), .QN(n3352) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1121), .CK(clk), .RN(n3475), .QN(
n1842) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1113), .CK(clk), .RN(n3500), .Q(
DmP_mant_SFG_SWR[12]), .QN(n3432) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1111), .CK(clk), .RN(n3498), .Q(
DmP_mant_SFG_SWR[13]), .QN(n3433) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1053), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1047), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1046), .CK(clk), .RN(n3473), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1045), .CK(clk), .RN(n3472), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1044), .CK(clk), .RN(n3473), .Q(
DmP_mant_SFG_SWR[26]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1043), .CK(clk), .RN(n3472), .Q(
DmP_mant_SFG_SWR[27]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1042), .CK(clk), .RN(n2008), .Q(
DmP_mant_SFG_SWR[28]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1041), .CK(clk), .RN(n3479), .Q(
DmP_mant_SFG_SWR[29]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1027), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[43]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1026), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[44]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1025), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[45]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1024), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[46]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1023), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[47]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1018), .CK(clk), .RN(n3489), .Q(
DmP_mant_SFG_SWR[52]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1017), .CK(clk), .RN(n3489), .Q(
DmP_mant_SFG_SWR[53]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1016), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[54]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1311), .CK(clk), .RN(n3480),
.Q(DMP_exp_NRM2_EW[10]), .QN(n3425) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1316), .CK(clk), .RN(n3484), .Q(
DMP_exp_NRM2_EW[9]), .QN(n3420) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1676), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[52]), .QN(n3415) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1745), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[49]), .QN(n3414) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n3504),
.Q(intDY_EWSW[30]), .QN(n3412) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n3483),
.Q(intDY_EWSW[22]), .QN(n3411) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[14]), .QN(n3410) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1679), .CK(clk), .RN(n3487),
.Q(intDY_EWSW[49]), .QN(n3409) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1664), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[44]), .QN(n3408) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1663), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[43]), .QN(n3407) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1677), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[51]), .QN(n3406) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1682), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[46]), .QN(n3405) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1686), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[42]), .QN(n3403) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1688), .CK(clk), .RN(n3465),
.Q(intDY_EWSW[40]), .QN(n3402) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1692), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[36]), .QN(n3401) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1694), .CK(clk), .RN(n3460),
.Q(intDY_EWSW[34]), .QN(n3400) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1695), .CK(clk), .RN(n3478),
.Q(intDY_EWSW[33]), .QN(n3399) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1683), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[45]), .QN(n3398) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1689), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[39]), .QN(n3397) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1321), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM2_EW[8]), .QN(n3394) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1733), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[61]), .QN(n3391) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1802), .CK(clk), .RN(
n3458), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n3390) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1671), .CK(clk), .RN(n3450),
.Q(intDY_EWSW[57]), .QN(n3389) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1678), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[50]), .QN(n3388) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1326), .CK(clk), .RN(n3485), .Q(
DMP_exp_NRM2_EW[7]), .QN(n3385) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1331), .CK(clk), .RN(n3483), .Q(
DMP_exp_NRM2_EW[6]), .QN(n3384) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1696), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[32]), .QN(n3380) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n3472),
.Q(intDY_EWSW[28]), .QN(n3379) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n3473),
.Q(intDY_EWSW[26]), .QN(n3378) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n3484),
.Q(intDY_EWSW[24]), .QN(n3377) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n3504),
.Q(intDY_EWSW[20]), .QN(n3376) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[18]), .QN(n3375) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[12]), .QN(n3374) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[8]), .QN(n3373) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[2]), .QN(n3372) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n3504),
.Q(intDY_EWSW[21]), .QN(n3371) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[13]), .QN(n3370) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[9]), .QN(n3368) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1608), .CK(clk), .RN(n3451),
.Q(shift_value_SHT2_EWR[3]), .QN(n3345) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1136), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[0]), .QN(n3329) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1667), .CK(clk), .RN(n3448),
.Q(intDY_EWSW[61]), .QN(n3325) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1531), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[56]), .QN(n3321) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1740), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[54]), .QN(n3320) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1532), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[55]), .QN(n3319) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1533), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[54]), .QN(n3317) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1534), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[53]), .QN(n3316) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[6]), .QN(n3315) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n3463),
.Q(intDY_EWSW[31]), .QN(n3314) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n3482),
.Q(intDY_EWSW[23]), .QN(n3313) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[15]), .QN(n3312) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1685), .CK(clk), .RN(n3456),
.Q(intDY_EWSW[43]), .QN(n3311) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1687), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[41]), .QN(n3310) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1693), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[35]), .QN(n3309) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1681), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[47]), .QN(n3308) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1735), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[59]), .QN(n3307) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[11]), .QN(n3305) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n3485),
.Q(intDY_EWSW[29]), .QN(n3302) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[3]), .QN(n3301) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[27]), .QN(n3300) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[25]), .QN(n3299) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[19]), .QN(n3298) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[17]), .QN(n3297) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1771), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[23]), .QN(n3291) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1763), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[31]), .QN(n3290) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1779), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[15]), .QN(n3287) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1116), .CK(clk), .RN(n3495), .Q(
Raw_mant_NRM_SWR[11]), .QN(n3286) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1675), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[53]), .QN(n3284) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1673), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[55]), .QN(n3283) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1674), .CK(clk), .RN(n3455),
.Q(intDY_EWSW[54]), .QN(n3282) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1672), .CK(clk), .RN(n3442),
.Q(intDY_EWSW[56]), .QN(n3281) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n3446),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1200), .CK(clk), .RN(n3473), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1184), .CK(clk), .RN(n3496), .Q(
final_result_ieee[63]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1193), .CK(clk), .RN(n3493), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1115), .CK(clk), .RN(n3474), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1114), .CK(clk), .RN(n3474), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1109), .CK(clk), .RN(n3490), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1106), .CK(clk), .RN(n3477), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1101), .CK(clk), .RN(n3498), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1100), .CK(clk), .RN(n3476), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1093), .CK(clk), .RN(n3498), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1092), .CK(clk), .RN(n3476), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1088), .CK(clk), .RN(n3477), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1087), .CK(clk), .RN(n3478), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1084), .CK(clk), .RN(n3478), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1081), .CK(clk), .RN(n3498), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1074), .CK(clk), .RN(n3476), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1073), .CK(clk), .RN(n3477), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1072), .CK(clk), .RN(n2008), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1071), .CK(clk), .RN(n3491), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1070), .CK(clk), .RN(n3479), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1069), .CK(clk), .RN(n2008), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1064), .CK(clk), .RN(n3491), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1063), .CK(clk), .RN(n3479), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1062), .CK(clk), .RN(n2008), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1061), .CK(clk), .RN(n3491), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1199), .CK(clk), .RN(n3473), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1588), .CK(clk), .RN(n3482), .Q(
final_result_ieee[62]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1108), .CK(clk), .RN(n3477), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1107), .CK(clk), .RN(n3478), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1103), .CK(clk), .RN(n3498), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1102), .CK(clk), .RN(n3477), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1099), .CK(clk), .RN(n3478), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1098), .CK(clk), .RN(n3476), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1095), .CK(clk), .RN(n3498), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1094), .CK(clk), .RN(n3476), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1091), .CK(clk), .RN(n3477), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1090), .CK(clk), .RN(n3478), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1089), .CK(clk), .RN(n3498), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1086), .CK(clk), .RN(n3476), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1085), .CK(clk), .RN(n3477), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1083), .CK(clk), .RN(n3478), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1082), .CK(clk), .RN(n3498), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1080), .CK(clk), .RN(n3476), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1079), .CK(clk), .RN(n3477), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1078), .CK(clk), .RN(n3478), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1077), .CK(clk), .RN(n3498), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1076), .CK(clk), .RN(n3477), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1075), .CK(clk), .RN(n3478), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1068), .CK(clk), .RN(n3479), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1067), .CK(clk), .RN(n2008), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1066), .CK(clk), .RN(n3491), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1065), .CK(clk), .RN(n3479), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1060), .CK(clk), .RN(n3484), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1059), .CK(clk), .RN(n3480), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1058), .CK(clk), .RN(n3483), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1057), .CK(clk), .RN(n3443), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1056), .CK(clk), .RN(n3485), .Q(
final_result_ieee[51]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1598), .CK(clk), .RN(n3469), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1597), .CK(clk), .RN(n3492), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1596), .CK(clk), .RN(n3457), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1595), .CK(clk), .RN(n3470), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1594), .CK(clk), .RN(n3484), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1593), .CK(clk), .RN(n3482), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1592), .CK(clk), .RN(n3480), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1591), .CK(clk), .RN(n3483), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1590), .CK(clk), .RN(n3485), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1589), .CK(clk), .RN(n3442), .Q(
final_result_ieee[61]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n3481), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n3304) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1096), .CK(clk), .RN(n3477), .Q(
Raw_mant_NRM_SWR[10]), .QN(n3423) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1118), .CK(clk), .RN(n3469), .Q(
Raw_mant_NRM_SWR[8]), .QN(n3292) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1126), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[4]), .QN(n3344) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1133), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[2]), .QN(n3362) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n1795), .CK(clk), .RN(n3494), .Q(
Shift_reg_FLAGS_7[0]), .QN(n3426) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1180), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[18]), .QN(n3356) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1179), .CK(clk), .RN(n3447), .Q(
Raw_mant_NRM_SWR[19]), .QN(n3355) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1772), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[22]), .QN(n3339) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1773), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[21]), .QN(n3357) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1774), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[20]), .QN(n3337) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1775), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[19]), .QN(n3295) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1776), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[18]), .QN(n3360) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1777), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[17]), .QN(n3348) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1780), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[14]), .QN(n3328) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[4]), .QN(n3303) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1764), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[30]), .QN(n3338) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1765), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[29]), .QN(n3342) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1766), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[28]), .QN(n3336) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1767), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[27]), .QN(n3294) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1768), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[26]), .QN(n3359) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1769), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[25]), .QN(n3347) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1786), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[8]), .QN(n3349) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1748), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[46]), .QN(n3326) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1791), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[3]), .QN(n3331) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1758), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[36]), .QN(n3340) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1759), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[35]), .QN(n3289) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1761), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[33]), .QN(n3333) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1783), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[11]), .QN(n3330) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1737), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[57]), .QN(n3350) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1743), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[51]), .QN(n3354) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1744), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[50]), .QN(n3293) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1760), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[34]), .QN(n3335) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1684), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[44]), .QN(n3404) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1680), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[48]), .QN(n3381) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1734), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[60]), .QN(n3393) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[10]), .QN(n3369) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1752), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[42]), .QN(n3334) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1782), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[12]), .QN(n3327) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1749), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[45]), .QN(n3346) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1751), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[43]), .QN(n3288) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1753), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[41]), .QN(n3341) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1781), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[13]), .QN(n3343) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1739), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[55]), .QN(n3429) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1741), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[53]), .QN(n3428) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[16]), .QN(n3382) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n3462),
.Q(intDY_EWSW[1]), .QN(n3421) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1736), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[58]), .QN(n3392) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1690), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[38]), .QN(n3422) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1691), .CK(clk), .RN(n3449),
.Q(intDY_EWSW[37]), .QN(n3396) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1738), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[56]), .QN(n3285) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1163), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[35]), .QN(n3383) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1160), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[38]), .QN(n3296) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1156), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[42]), .QN(n3366) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1154), .CK(clk), .RN(n3486), .Q(
Raw_mant_NRM_SWR[44]) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1607), .CK(clk), .RN(n3440),
.Q(shift_value_SHT2_EWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1178), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1789), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1120), .CK(clk), .RN(n3460), .Q(
Raw_mant_NRM_SWR[7]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1169), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[29]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n1799), .CK(clk), .RN(n3496), .Q(
n3505), .QN(n3503) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1128), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[3]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1139), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1175), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1631), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1636), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1634), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1756), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[38]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1757), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[37]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1742), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[52]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1637), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1639), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1750), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[44]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1747), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[47]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1746), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1778), .CK(clk), .RN(n3441),
.Q(intDX_EWSW[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1754), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[40]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1784), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1793), .CK(clk), .RN(n3490),
.Q(intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1762), .CK(clk), .RN(n3442),
.Q(intDX_EWSW[32]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1787), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1770), .CK(clk), .RN(n3452),
.Q(intDX_EWSW[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1182), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1792), .CK(clk), .RN(n3458),
.Q(intDX_EWSW[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1164), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[34]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1110), .CK(clk), .RN(n3490), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1183), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1633), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1649), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[32]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1628), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[14]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1181), .CK(clk), .RN(n3447), .Q(
Raw_mant_NRM_SWR[17]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1668), .CK(clk), .RN(n3440),
.Q(intDY_EWSW[60]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1670), .CK(clk), .RN(n3445),
.Q(intDY_EWSW[58]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1666), .CK(clk), .RN(n3455),
.Q(intDY_EWSW[62]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1803), .CK(clk), .RN(
n3474), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1173), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1177), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1657), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[37]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1622), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[10]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1647), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[30]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1168), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[30]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1652), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[34]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1650), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[33]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1609), .CK(clk), .RN(n3451),
.Q(shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1659), .CK(clk), .RN(n3456), .Q(
Data_array_SWR[39]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1166), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[32]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1620), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1618), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1281), .CK(clk), .RN(n3481),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1289), .CK(clk), .RN(n3457),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1245), .CK(clk), .RN(n3487),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1263), .CK(clk), .RN(n3468),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1253), .CK(clk), .RN(n3461),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1257), .CK(clk), .RN(n3460),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1275), .CK(clk), .RN(n3470),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1162), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[36]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1731), .CK(clk), .RN(n3445),
.Q(intDX_EWSW[63]) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1190), .CK(clk), .RN(n3470), .Q(
OP_FLAG_SFG) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1471), .CK(clk), .RN(n3488), .Q(
DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1477), .CK(clk), .RN(n3488), .Q(
DMP_SFG[14]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1468), .CK(clk), .RN(n3464), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1474), .CK(clk), .RN(n3488), .Q(
DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1465), .CK(clk), .RN(n3489), .Q(
DMP_SFG[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1112), .CK(clk), .RN(n3493), .Q(
Raw_mant_NRM_SWR[12]), .QN(n3358) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1297), .CK(clk), .RN(n3492), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1233), .CK(clk), .RN(n3461),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1243), .CK(clk), .RN(n3453),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1247), .CK(clk), .RN(n3470),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1255), .CK(clk), .RN(n3447),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1265), .CK(clk), .RN(n3462),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1273), .CK(clk), .RN(n3468),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1279), .CK(clk), .RN(n3481),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1287), .CK(clk), .RN(n3470),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1206), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1283), .CK(clk), .RN(n3468),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1285), .CK(clk), .RN(n3492),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1241), .CK(clk), .RN(n3446),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1259), .CK(clk), .RN(n3455),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1291), .CK(clk), .RN(n3469), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1303), .CK(clk), .RN(n3494), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1617), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1293), .CK(clk), .RN(n3481), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1301), .CK(clk), .RN(n3469), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1615), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1295), .CK(clk), .RN(n3492), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1299), .CK(clk), .RN(n3457), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1305), .CK(clk), .RN(n3466), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1307), .CK(clk), .RN(n3504), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1309), .CK(clk), .RN(n3474), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1483), .CK(clk), .RN(n3468), .Q(
DMP_SFG[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1117), .CK(clk), .RN(n3496), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1124), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1127), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[4]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1132), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[5]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1134), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1097), .CK(clk), .RN(n3498), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1105), .CK(clk), .RN(n3476), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1119), .CK(clk), .RN(n3501), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1161), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[37]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1638), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[23]), .QN(n1823) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1366), .CK(clk), .RN(n3491), .Q(
DMP_SFG[51]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1369), .CK(clk), .RN(n3479), .Q(
DMP_SFG[50]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1372), .CK(clk), .RN(n3491), .Q(
DMP_SFG[49]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1204), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[54]), .QN(n1821) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1480), .CK(clk), .RN(n3492), .Q(
DMP_SFG[13]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1378), .CK(clk), .RN(n3479), .Q(
DMP_SFG[47]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1384), .CK(clk), .RN(n3491), .Q(
DMP_SFG[45]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1390), .CK(clk), .RN(n3479), .Q(
DMP_SFG[43]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1396), .CK(clk), .RN(n3491), .Q(
DMP_SFG[41]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1402), .CK(clk), .RN(n3495), .Q(
DMP_SFG[39]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1408), .CK(clk), .RN(n3490), .Q(
DMP_SFG[37]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1414), .CK(clk), .RN(n3490), .Q(
DMP_SFG[35]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1420), .CK(clk), .RN(n3495), .Q(
DMP_SFG[33]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1426), .CK(clk), .RN(n3495), .Q(
DMP_SFG[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1432), .CK(clk), .RN(n3490), .Q(
DMP_SFG[29]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n3464), .Q(
DMP_SFG[27]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1444), .CK(clk), .RN(n3489), .Q(
DMP_SFG[25]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1450), .CK(clk), .RN(n3464), .Q(
DMP_SFG[23]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1456), .CK(clk), .RN(n3489), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1462), .CK(clk), .RN(n3464), .Q(
DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1375), .CK(clk), .RN(n3479), .Q(
DMP_SFG[48]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1381), .CK(clk), .RN(n3491), .Q(
DMP_SFG[46]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1387), .CK(clk), .RN(n3479), .Q(
DMP_SFG[44]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1393), .CK(clk), .RN(n2008), .Q(
DMP_SFG[42]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1399), .CK(clk), .RN(n2008), .Q(
DMP_SFG[40]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1405), .CK(clk), .RN(n3495), .Q(
DMP_SFG[38]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1411), .CK(clk), .RN(n3490), .Q(
DMP_SFG[36]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1417), .CK(clk), .RN(n3490), .Q(
DMP_SFG[34]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1423), .CK(clk), .RN(n3495), .Q(
DMP_SFG[32]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1429), .CK(clk), .RN(n3490), .Q(
DMP_SFG[30]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1435), .CK(clk), .RN(n3495), .Q(
DMP_SFG[28]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n3489), .Q(
DMP_SFG[26]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1447), .CK(clk), .RN(n3464), .Q(
DMP_SFG[24]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1453), .CK(clk), .RN(n3489), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1459), .CK(clk), .RN(n3489), .Q(
DMP_SFG[20]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1611), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1612), .CK(clk), .RN(n3441), .Q(
Data_array_SWR[2]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1201), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[57]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1049), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1050), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n3446),
.Q(intDY_EWSW[7]), .QN(n3413) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n3447),
.Q(intDY_EWSW[5]), .QN(n3387) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1665), .CK(clk), .RN(n3444),
.Q(intDY_EWSW[63]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1019), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[51]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1020), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[50]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1021), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[49]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1022), .CK(clk), .RN(n3488), .Q(
DmP_mant_SFG_SWR[48]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1028), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[42]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1029), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[41]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1030), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[40]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1031), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[39]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1036), .CK(clk), .RN(n2008), .Q(
DmP_mant_SFG_SWR[34]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1037), .CK(clk), .RN(n3491), .Q(
DmP_mant_SFG_SWR[33]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1038), .CK(clk), .RN(n3479), .Q(
DmP_mant_SFG_SWR[32]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1048), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1605), .CK(clk), .RN(n3478),
.Q(shift_value_SHT2_EWR[5]), .QN(n3332) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1174), .CK(clk), .RN(n3477), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1104), .CK(clk), .RN(n3478), .Q(
Raw_mant_NRM_SWR[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1170), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[28]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1790), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1785), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1755), .CK(clk), .RN(n3443),
.Q(intDX_EWSW[39]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1176), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1165), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[33]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1643), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1629), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1788), .CK(clk), .RN(n3440),
.Q(intDX_EWSW[6]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1794), .CK(clk), .RN(n3490),
.Q(intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1669), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[59]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1662), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[42]), .QN(n1826) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1624), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[12]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1654), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[35]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1625), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[13]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1159), .CK(clk), .RN(n3484),
.QN(n1807) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1645), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[28]), .QN(n3416) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1619), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1267), .CK(clk), .RN(n3499),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1249), .CK(clk), .RN(n3490),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1211), .CK(clk), .RN(n3472),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1271), .CK(clk), .RN(n3457),
.Q(DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1239), .CK(clk), .RN(n3499),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1235), .CK(clk), .RN(n3457),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1167), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1215), .CK(clk), .RN(n3472),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1131), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1123), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[6]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1644), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[27]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1627), .CK(clk), .RN(n3448), .QN(
n1809) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1646), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[29]), .QN(n3417) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1648), .CK(clk), .RN(n3501), .Q(
Data_array_SWR[31]), .QN(n3418) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1225), .CK(clk), .RN(n3471),
.Q(DmP_mant_SHT1_SW[42]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1732), .CK(clk), .RN(n3444),
.Q(intDX_EWSW[62]), .QN(n3306) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1209), .CK(clk), .RN(n3472),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1221), .CK(clk), .RN(n3471),
.Q(DmP_mant_SHT1_SW[44]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1157), .CK(clk), .RN(n3482),
.QN(n1816) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1147), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[51]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1158), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[40]), .QN(n3363) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1144), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[54]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1661), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[41]), .QN(n3395) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1142), .CK(clk), .RN(n3485), .Q(
Raw_mant_NRM_SWR[14]), .QN(n3427) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1535), .CK(clk), .RN(n3455), .Q(
DMP_EXP_EWSW[52]), .QN(n3424) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1040), .CK(clk), .RN(n3504), .Q(
DmP_mant_SFG_SWR[30]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1039), .CK(clk), .RN(n3491), .Q(
DmP_mant_SFG_SWR[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1035), .CK(clk), .RN(n3491), .Q(
DmP_mant_SFG_SWR[35]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n3481), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n3480), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(n3483), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1341), .CK(clk), .RN(n3485), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1336), .CK(clk), .RN(n3483), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1610), .CK(clk), .RN(n3446), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1203), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[55]), .QN(n3322) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1143), .CK(clk), .RN(n3494), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1055), .CK(clk), .RN(n3469), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1054), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1052), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1051), .CK(clk), .RN(n3486), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1034), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[36]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1033), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[37]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1032), .CK(clk), .RN(n3487), .Q(
DmP_mant_SFG_SWR[38]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1635), .CK(clk), .RN(n3449), .QN(
n1825) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1653), .CK(clk), .RN(n3451), .QN(
n1824) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1640), .CK(clk), .RN(n3450), .QN(
n1818) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1642), .CK(clk), .RN(n3448), .QN(
n1817) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1655), .CK(clk), .RN(n3451), .QN(
n1810) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1651), .CK(clk), .RN(n3452), .QN(
n1806) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1153), .CK(clk), .RN(n3486), .Q(
Raw_mant_NRM_SWR[45]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1152), .CK(clk), .RN(n3486), .Q(
Raw_mant_NRM_SWR[46]), .QN(n3386) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1150), .CK(clk), .RN(n3500), .Q(
Raw_mant_NRM_SWR[48]), .QN(n3323) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1146), .CK(clk), .RN(n3491), .Q(
Raw_mant_NRM_SWR[52]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1145), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[53]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1172), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[26]), .QN(n3419) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1171), .CK(clk), .RN(n3484), .Q(
Raw_mant_NRM_SWR[27]), .QN(n3324) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1641), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1632), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1630), .CK(clk), .RN(n3449), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1660), .CK(clk), .RN(n3441), .Q(
Data_array_SWR[40]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1623), .CK(clk), .RN(n3450), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1656), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[36]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1658), .CK(clk), .RN(n3451), .Q(
Data_array_SWR[38]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1621), .CK(clk), .RN(n3448), .Q(
Data_array_SWR[9]) );
ADDFX1TS DP_OP_15J9_123_7955_U10 ( .A(n3352), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J9_123_7955_n10), .CO(DP_OP_15J9_123_7955_n9), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J9_123_7955_U9 ( .A(n3361), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J9_123_7955_n9), .CO(DP_OP_15J9_123_7955_n8), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J9_123_7955_U8 ( .A(n3365), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J9_123_7955_n8), .CO(DP_OP_15J9_123_7955_n7), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1148), .CK(clk), .RN(n3483), .Q(
Raw_mant_NRM_SWR[50]), .QN(n3367) );
CMPR32X2TS DP_OP_15J9_123_7955_U11 ( .A(n3353), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J9_123_7955_n11), .CO(DP_OP_15J9_123_7955_n10), .S(
exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J9_123_7955_U7 ( .A(n3364), .B(DMP_exp_NRM2_EW[5]), .C(
DP_OP_15J9_123_7955_n7), .CO(DP_OP_15J9_123_7955_n6), .S(
exp_rslt_NRM2_EW1[5]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n1796), .CK(clk), .RN(n3490), .Q(
Shift_reg_FLAGS_7[1]), .QN(n1884) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1729), .CK(clk), .RN(n3447),
.Q(left_right_SHT2), .QN(n1804) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n1801), .CK(clk), .RN(n2009), .Q(
Shift_reg_FLAGS_7_6), .QN(n1887) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1797), .CK(clk), .RN(n3468), .Q(
Shift_reg_FLAGS_7[2]), .QN(n3431) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n1800), .CK(clk), .RN(n2009), .Q(
Shift_reg_FLAGS_7_5), .QN(n3430) );
CMPR32X2TS U1842 ( .A(n2985), .B(DMP_SFG[51]), .C(n2984), .CO(n2988), .S(
n2851) );
CLKINVX6TS U1843 ( .A(n1815), .Y(n1846) );
CMPR32X2TS U1844 ( .A(n2979), .B(DMP_SFG[50]), .C(n2978), .CO(n2984), .S(
n2980) );
OR2X4TS U1845 ( .A(n2482), .B(n2629), .Y(n2560) );
BUFX3TS U1846 ( .A(n2753), .Y(n2829) );
CMPR32X2TS U1847 ( .A(n2982), .B(DMP_SFG[49]), .C(n2981), .CO(n2978), .S(
n2983) );
INVX2TS U1848 ( .A(n3128), .Y(n2002) );
BUFX8TS U1849 ( .A(n2753), .Y(n2816) );
CLKINVX6TS U1850 ( .A(n2653), .Y(n2753) );
NAND2X2TS U1851 ( .A(n2003), .B(Shift_reg_FLAGS_7[1]), .Y(n3128) );
OAI221XLTS U1852 ( .A0(n2477), .A1(n2476), .B0(n2475), .B1(n2474), .C0(n2473), .Y(n2478) );
NAND4X1TS U1853 ( .A(n3123), .B(n2001), .C(n2000), .D(n1999), .Y(n2003) );
NOR2X4TS U1854 ( .A(Shift_reg_FLAGS_7[1]), .B(n3223), .Y(n2659) );
OAI211X1TS U1855 ( .A0(n1895), .A1(n1954), .B0(n1894), .C0(n1893), .Y(n1975)
);
NAND2X1TS U1856 ( .A(Raw_mant_NRM_SWR[15]), .B(n1890), .Y(n1994) );
CMPR32X2TS U1857 ( .A(n3105), .B(DMP_SFG[13]), .C(n3104), .CO(n3102), .S(
n3107) );
NOR2X1TS U1858 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .Y(
n1916) );
INVX2TS U1859 ( .A(n1987), .Y(n1992) );
NOR2XLTS U1860 ( .A(n2459), .B(n2458), .Y(n2472) );
INVX2TS U1861 ( .A(n1943), .Y(n1935) );
INVX1TS U1862 ( .A(LZD_output_NRM2_EW[0]), .Y(n2835) );
NOR2XLTS U1863 ( .A(n2144), .B(n3241), .Y(n2145) );
INVX2TS U1864 ( .A(n2828), .Y(n1843) );
NAND2X1TS U1865 ( .A(beg_OP), .B(n3133), .Y(n3151) );
OAI211XLTS U1866 ( .A0(n2785), .A1(n2649), .B0(n2784), .C0(n2783), .Y(n1651)
);
OAI211XLTS U1867 ( .A0(n2695), .A1(n2753), .B0(n2694), .C0(n2693), .Y(n1648)
);
OAI211XLTS U1868 ( .A0(n2678), .A1(n2826), .B0(n2648), .C0(n2647), .Y(n1619)
);
OAI211XLTS U1869 ( .A0(n2823), .A1(n2826), .B0(n2791), .C0(n2790), .Y(n1629)
);
OAI211XLTS U1870 ( .A0(n2665), .A1(n2649), .B0(n2652), .C0(n2651), .Y(n1612)
);
OAI211XLTS U1871 ( .A0(n2657), .A1(n2822), .B0(n2656), .C0(n2655), .Y(n1611)
);
OAI211XLTS U1872 ( .A0(n2817), .A1(n2649), .B0(n2814), .C0(n2813), .Y(n1638)
);
OAI211XLTS U1873 ( .A0(n2666), .A1(n2822), .B0(n2661), .C0(n2660), .Y(n1617)
);
OAI211XLTS U1874 ( .A0(n2760), .A1(n2826), .B0(n2759), .C0(n2758), .Y(n1620)
);
OAI211XLTS U1875 ( .A0(n2834), .A1(n2833), .B0(n2832), .C0(n2831), .Y(n1659)
);
OAI211XLTS U1876 ( .A0(n2799), .A1(n2649), .B0(n2798), .C0(n2797), .Y(n1649)
);
OAI211XLTS U1877 ( .A0(n2719), .A1(n2753), .B0(n2718), .C0(n2717), .Y(n1639)
);
OAI211XLTS U1878 ( .A0(n2767), .A1(n2826), .B0(n2766), .C0(n2765), .Y(n1626)
);
CLKINVX6TS U1879 ( .A(n1815), .Y(n1845) );
AOI2BB2X1TS U1880 ( .B0(Raw_mant_NRM_SWR[26]), .B1(n2720), .A0N(n2719),
.A1N(n2833), .Y(n2679) );
OR2X2TS U1881 ( .A(n2736), .B(n2816), .Y(n2828) );
AOI2BB2X1TS U1882 ( .B0(Raw_mant_NRM_SWR[29]), .B1(n2720), .A0N(n2741),
.A1N(n2833), .Y(n2721) );
AOI2BB2X1TS U1883 ( .B0(Raw_mant_NRM_SWR[20]), .B1(n2756), .A0N(n2744),
.A1N(n2833), .Y(n2726) );
AOI2BB2X1TS U1884 ( .B0(Raw_mant_NRM_SWR[24]), .B1(n2720), .A0N(n2716),
.A1N(n2833), .Y(n2717) );
AOI2BB2X1TS U1885 ( .B0(Raw_mant_NRM_SWR[22]), .B1(n2720), .A0N(n2728),
.A1N(n2833), .Y(n2702) );
INVX6TS U1886 ( .A(n2807), .Y(n2649) );
NOR3X4TS U1887 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .C(n1954),
.Y(n1900) );
CLKMX2X2TS U1888 ( .A(Raw_mant_NRM_SWR[49]), .B(n2854), .S0(n3016), .Y(n1149) );
CLKINVX1TS U1889 ( .A(n1953), .Y(n1896) );
NOR3X6TS U1890 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .C(n3115),
.Y(n1953) );
AOI32X1TS U1891 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1981), .A2(n3292), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1981), .Y(n1984) );
NOR2X6TS U1892 ( .A(Raw_mant_NRM_SWR[10]), .B(n3114), .Y(n1981) );
INVX1TS U1893 ( .A(n1974), .Y(n1977) );
NOR2X4TS U1894 ( .A(Raw_mant_NRM_SWR[16]), .B(n1974), .Y(n1890) );
NAND2X4TS U1895 ( .A(n1901), .B(n1998), .Y(n1974) );
NAND2BX4TS U1896 ( .AN(Raw_mant_NRM_SWR[21]), .B(n1923), .Y(n1945) );
NAND2XLTS U1897 ( .A(n1986), .B(Raw_mant_NRM_SWR[22]), .Y(n1937) );
CLKINVX2TS U1898 ( .A(n1942), .Y(n1917) );
NOR3X4TS U1899 ( .A(Raw_mant_NRM_SWR[28]), .B(Raw_mant_NRM_SWR[29]), .C(
n1942), .Y(n1909) );
NOR2BX2TS U1900 ( .AN(n2125), .B(n3129), .Y(n2126) );
INVX2TS U1901 ( .A(n2127), .Y(n2128) );
NOR3X4TS U1902 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .C(
n1943), .Y(n1907) );
NAND2X1TS U1903 ( .A(n3394), .B(n2121), .Y(n2123) );
NAND2X1TS U1904 ( .A(n3385), .B(n2115), .Y(n2120) );
INVX1TS U1905 ( .A(n1911), .Y(n1912) );
NAND2X1TS U1906 ( .A(n3384), .B(n2114), .Y(n2118) );
INVX1TS U1907 ( .A(n1961), .Y(n1973) );
AOI21X1TS U1908 ( .A0(n3102), .A1(n2843), .B0(n2842), .Y(n3045) );
INVX4TS U1909 ( .A(n2734), .Y(n2704) );
NOR2X1TS U1910 ( .A(n3049), .B(n3051), .Y(n2843) );
INVX3TS U1911 ( .A(n2907), .Y(n2103) );
NOR2X4TS U1912 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n1965) );
CLKBUFX2TS U1913 ( .A(Raw_mant_NRM_SWR[14]), .Y(n1848) );
NAND2BXLTS U1914 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2342) );
NAND2BXLTS U1915 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2343) );
OAI211X1TS U1916 ( .A0(n2827), .A1(n2826), .B0(n2825), .C0(n2824), .Y(n1631)
);
OAI211X1TS U1917 ( .A0(n2786), .A1(n2649), .B0(n2776), .C0(n2775), .Y(n1655)
);
OAI211X1TS U1918 ( .A0(n2796), .A1(n2649), .B0(n2779), .C0(n2778), .Y(n1647)
);
OAI211X1TS U1919 ( .A0(n2830), .A1(n2649), .B0(n2788), .C0(n2787), .Y(n1657)
);
OAI211X1TS U1920 ( .A0(n2802), .A1(n2826), .B0(n2801), .C0(n2800), .Y(n1633)
);
OAI211X1TS U1921 ( .A0(n2763), .A1(n2826), .B0(n2762), .C0(n2761), .Y(n1622)
);
OAI211X1TS U1922 ( .A0(n2794), .A1(n2649), .B0(n2793), .C0(n2792), .Y(n1642)
);
OAI211X1TS U1923 ( .A0(n2782), .A1(n2711), .B0(n2781), .C0(n2780), .Y(n1653)
);
OAI211X1TS U1924 ( .A0(n2820), .A1(n2649), .B0(n2819), .C0(n2818), .Y(n1640)
);
OAI21X1TS U1925 ( .A0(n2816), .A1(n2740), .B0(n2735), .Y(n1664) );
OAI211X1TS U1926 ( .A0(n2826), .A1(n2740), .B0(n2739), .C0(n2738), .Y(n1662)
);
OAI211X1TS U1927 ( .A0(n2812), .A1(n2649), .B0(n2743), .C0(n2742), .Y(n1636)
);
OAI211X1TS U1928 ( .A0(n2764), .A1(n2826), .B0(n2755), .C0(n2754), .Y(n1624)
);
AOI22X1TS U1929 ( .A0(n2795), .A1(Data_array_SWR[15]), .B0(n1844), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2791) );
AOI22X1TS U1930 ( .A0(n2815), .A1(Data_array_SWR[19]), .B0(n1844), .B1(
DmP_mant_SHT1_SW[21]), .Y(n2801) );
AOI22X1TS U1931 ( .A0(n2795), .A1(Data_array_SWR[30]), .B0(n1844), .B1(
DmP_mant_SHT1_SW[35]), .Y(n2779) );
OAI211X1TS U1932 ( .A0(n2777), .A1(n2649), .B0(n2746), .C0(n2745), .Y(n1645)
);
AOI2BB2X1TS U1933 ( .B0(n1846), .B1(n1872), .A0N(n2782), .A1N(n2816), .Y(
n2775) );
OAI211X1TS U1934 ( .A0(n2708), .A1(n2753), .B0(n2707), .C0(n2706), .Y(n1660)
);
OAI211X1TS U1935 ( .A0(n2712), .A1(n2753), .B0(n2689), .C0(n2688), .Y(n1658)
);
AOI2BB2X1TS U1936 ( .B0(n1846), .B1(n1874), .A0N(n2799), .A1N(n2816), .Y(
n2783) );
OAI211X1TS U1937 ( .A0(n2715), .A1(n2753), .B0(n2714), .C0(n2713), .Y(n1656)
);
AOI2BB1X1TS U1938 ( .A0N(n2737), .A1N(n2816), .B0(n1846), .Y(n2738) );
AOI2BB2X1TS U1939 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2820),
.A1N(n2816), .Y(n2792) );
OAI211X1TS U1940 ( .A0(n2675), .A1(n2822), .B0(n2671), .C0(n2670), .Y(n1623)
);
OAI211X1TS U1941 ( .A0(n2698), .A1(n2822), .B0(n2687), .C0(n2686), .Y(n1632)
);
AOI2BB2X1TS U1942 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n2756), .A0N(n2737), .A1N(
n2711), .Y(n2706) );
OAI211X1TS U1943 ( .A0(n2723), .A1(n2822), .B0(n2722), .C0(n2721), .Y(n1634)
);
AOI2BB2X1TS U1944 ( .B0(Raw_mant_NRM_SWR[40]), .B1(n2720), .A0N(n2683),
.A1N(n2711), .Y(n2670) );
OAI211X1TS U1945 ( .A0(n2701), .A1(n2822), .B0(n2700), .C0(n2699), .Y(n1630)
);
OAI211X1TS U1946 ( .A0(n2729), .A1(n2753), .B0(n2710), .C0(n2709), .Y(n1654)
);
AOI2BB2X1TS U1947 ( .B0(Raw_mant_NRM_SWR[45]), .B1(n2720), .A0N(n2757),
.A1N(n2711), .Y(n2672) );
OAI211X1TS U1948 ( .A0(n2728), .A1(n2753), .B0(n2727), .C0(n2726), .Y(n1643)
);
OAI211X1TS U1949 ( .A0(n2692), .A1(n2753), .B0(n2691), .C0(n2690), .Y(n1650)
);
OAI211X1TS U1950 ( .A0(n2683), .A1(n2822), .B0(n2682), .C0(n2681), .Y(n1625)
);
OAI211X1TS U1951 ( .A0(n2774), .A1(n2753), .B0(n2697), .C0(n2696), .Y(n1646)
);
OAI211X1TS U1952 ( .A0(n2716), .A1(n2753), .B0(n2703), .C0(n2702), .Y(n1641)
);
AOI2BB2X1TS U1953 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n2756), .A0N(n2708), .A1N(
n2711), .Y(n2688) );
AOI2BB2X1TS U1954 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n2756), .A0N(n2712), .A1N(
n2711), .Y(n2713) );
OAI211X1TS U1955 ( .A0(n2733), .A1(n2753), .B0(n2732), .C0(n2731), .Y(n1652)
);
AOI2BB2X1TS U1956 ( .B0(Raw_mant_NRM_SWR[42]), .B1(n2720), .A0N(n2675),
.A1N(n2711), .Y(n2676) );
AOI2BB2X1TS U1957 ( .B0(Raw_mant_NRM_SWR[35]), .B1(n2720), .A0N(n2701),
.A1N(n2833), .Y(n2684) );
AOI2BB2X1TS U1958 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n2756), .A0N(n2692),
.A1N(n2833), .Y(n2693) );
AOI2BB2X1TS U1959 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n2756), .A0N(n2715), .A1N(
n2833), .Y(n2709) );
AOI2BB2X1TS U1960 ( .B0(Raw_mant_NRM_SWR[17]), .B1(n2756), .A0N(n2695),
.A1N(n2833), .Y(n2696) );
AOI2BB2X1TS U1961 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n2756), .A0N(n2733),
.A1N(n2833), .Y(n2690) );
AOI2BB2X1TS U1962 ( .B0(Raw_mant_NRM_SWR[38]), .B1(n2720), .A0N(n2747),
.A1N(n2833), .Y(n2681) );
AOI2BB2X1TS U1963 ( .B0(Raw_mant_NRM_SWR[33]), .B1(n2720), .A0N(n2698),
.A1N(n2833), .Y(n2699) );
AOI2BB2X1TS U1964 ( .B0(Raw_mant_NRM_SWR[48]), .B1(n2720), .A0N(n2826),
.A1N(n2666), .Y(n2667) );
OAI211X1TS U1965 ( .A0(n2669), .A1(n2826), .B0(n2638), .C0(n2637), .Y(n1613)
);
AOI2BB2X1TS U1966 ( .B0(Raw_mant_NRM_SWR[31]), .B1(n2720), .A0N(n2723),
.A1N(n2833), .Y(n2686) );
OAI211X1TS U1967 ( .A0(n2674), .A1(n2826), .B0(n2644), .C0(n2643), .Y(n1616)
);
OAI21X1TS U1968 ( .A0(n3329), .A1(n2730), .B0(n2633), .Y(n1663) );
NOR2X4TS U1969 ( .A(n2631), .B(n2795), .Y(n2653) );
AND2X2TS U1970 ( .A(n2636), .B(n2002), .Y(n2642) );
AOI222X1TS U1971 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[49]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[3]), .C0(n2725), .C1(DmP_mant_SHT1_SW[4]), .Y(n2669)
);
AOI222X1TS U1972 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2804), .B0(
Raw_mant_NRM_SWR[2]), .B1(n2810), .C0(DmP_mant_SHT1_SW[50]), .C1(n2751), .Y(n2834) );
AOI222X1TS U1973 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2811), .B0(
Raw_mant_NRM_SWR[23]), .B1(n2810), .C0(n2725), .C1(n1853), .Y(n2817)
);
AOI222X1TS U1974 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[26]), .C0(n2724), .C1(DmP_mant_SHT1_SW[25]), .Y(n2770) );
AOI222X1TS U1975 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2811), .B0(
Raw_mant_NRM_SWR[34]), .B1(n2810), .C0(n2751), .C1(
DmP_mant_SHT1_SW[18]), .Y(n2789) );
AOI222X1TS U1976 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[17]), .C0(n2750), .C1(n1856), .Y(n2767) );
NOR2X6TS U1977 ( .A(n3137), .B(n2003), .Y(n2639) );
CLKMX2X2TS U1978 ( .A(Raw_mant_NRM_SWR[53]), .B(n2851), .S0(n3016), .Y(n1145) );
OAI211XLTS U1979 ( .A0(n3358), .A1(n1956), .B0(n2001), .C0(n3122), .Y(n1957)
);
CLKMX2X2TS U1980 ( .A(Raw_mant_NRM_SWR[52]), .B(n2980), .S0(n3016), .Y(n1146) );
CLKMX2X2TS U1981 ( .A(Raw_mant_NRM_SWR[50]), .B(n2992), .S0(n3016), .Y(n1148) );
OAI21X1TS U1982 ( .A0(Raw_mant_NRM_SWR[8]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1892), .Y(n1893) );
NAND3X1TS U1983 ( .A(n1984), .B(n1983), .C(n1982), .Y(n1985) );
NAND2X4TS U1984 ( .A(n3286), .B(n1952), .Y(n3114) );
OAI211X1TS U1985 ( .A0(n3324), .A1(n1950), .B0(n1949), .C0(n1948), .Y(n1951)
);
AOI31X1TS U1986 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1998), .A2(n3356), .B0(
n1997), .Y(n2000) );
OAI211X1TS U1987 ( .A0(n1996), .A1(n3383), .B0(n1995), .C0(n1994), .Y(n1997)
);
INVX1TS U1988 ( .A(n3247), .Y(n3249) );
OR2X4TS U1989 ( .A(n2126), .B(n3215), .Y(n3247) );
NAND3X1TS U1990 ( .A(n2136), .B(n3129), .C(n2135), .Y(n3226) );
NOR2X1TS U1991 ( .A(n2122), .B(n2129), .Y(n2125) );
NAND4BX1TS U1992 ( .AN(n2130), .B(n2119), .C(n2302), .D(n2306), .Y(n2122) );
NOR2X4TS U1993 ( .A(n1996), .B(Raw_mant_NRM_SWR[35]), .Y(n1934) );
INVX3TS U1994 ( .A(n2590), .Y(n3210) );
INVX3TS U1995 ( .A(n2590), .Y(n2627) );
INVX3TS U1996 ( .A(n2555), .Y(n2589) );
INVX3TS U1997 ( .A(n2555), .Y(n2585) );
INVX3TS U1998 ( .A(n2555), .Y(n2579) );
INVX4TS U1999 ( .A(n1922), .Y(n1996) );
NOR2X4TS U2000 ( .A(Raw_mant_NRM_SWR[36]), .B(n1911), .Y(n1922) );
NAND2X2TS U2001 ( .A(n1889), .B(n1916), .Y(n1911) );
AOI31X1TS U2002 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n3111), .A2(n3386), .B0(
n1993), .Y(n1995) );
NOR3X2TS U2003 ( .A(Raw_mant_NRM_SWR[40]), .B(n1875), .C(n1961), .Y(n1889)
);
NOR2X1TS U2004 ( .A(n2117), .B(exp_rslt_NRM2_EW1[5]), .Y(n2119) );
NAND3X1TS U2005 ( .A(n2216), .B(n2215), .C(n2214), .Y(n2229) );
NAND3X1TS U2006 ( .A(n2209), .B(n2208), .C(n2207), .Y(n2212) );
NAND3X1TS U2007 ( .A(n2151), .B(n2150), .C(n2149), .Y(n2159) );
NAND3BX1TS U2008 ( .AN(n2397), .B(n2390), .C(n2389), .Y(n2410) );
NAND2BX2TS U2009 ( .AN(n1849), .B(n1938), .Y(n1961) );
NOR2BX2TS U2010 ( .AN(n1962), .B(Raw_mant_NRM_SWR[43]), .Y(n1987) );
BUFX3TS U2011 ( .A(n3140), .Y(n3146) );
OAI21X1TS U2012 ( .A0(n2436), .A1(n2435), .B0(n2434), .Y(n2438) );
NOR2X2TS U2013 ( .A(Raw_mant_NRM_SWR[47]), .B(n1888), .Y(n1962) );
MX2X1TS U2014 ( .A(DMP_SFG[37]), .B(DMP_SHT2_EWSW[37]), .S0(n2858), .Y(n1408) );
MX2X1TS U2015 ( .A(DMP_SFG[39]), .B(DMP_SHT2_EWSW[39]), .S0(n3198), .Y(n1402) );
MX2X1TS U2016 ( .A(DMP_SFG[41]), .B(DMP_SHT2_EWSW[41]), .S0(n3258), .Y(n1396) );
MX2X1TS U2017 ( .A(DMP_SFG[43]), .B(DMP_SHT2_EWSW[43]), .S0(n2858), .Y(n1390) );
MX2X1TS U2018 ( .A(DMP_SFG[45]), .B(DMP_SHT2_EWSW[45]), .S0(n3258), .Y(n1384) );
MX2X1TS U2019 ( .A(DMP_SFG[47]), .B(DMP_SHT2_EWSW[47]), .S0(n3246), .Y(n1378) );
INVX4TS U2020 ( .A(n3151), .Y(n3140) );
NAND2X2TS U2021 ( .A(n3110), .B(n3111), .Y(n1888) );
OAI211XLTS U2022 ( .A0(intDY_EWSW[8]), .A1(n3349), .B0(n2374), .C0(n2377),
.Y(n2386) );
NOR2X1TS U2023 ( .A(n1804), .B(n2144), .Y(n2113) );
OAI211X1TS U2024 ( .A0(intDX_EWSW[61]), .A1(n3325), .B0(n2420), .C0(n2419),
.Y(n2421) );
NOR2XLTS U2025 ( .A(n1804), .B(n2111), .Y(n2112) );
NOR2X4TS U2026 ( .A(n1931), .B(n1933), .Y(n3111) );
OAI211X2TS U2027 ( .A0(intDY_EWSW[12]), .A1(n3327), .B0(n2384), .C0(n2358),
.Y(n2388) );
OAI211X2TS U2028 ( .A0(intDY_EWSW[28]), .A1(n3336), .B0(n2356), .C0(n2347),
.Y(n2406) );
NAND3X1TS U2029 ( .A(n3393), .B(n2418), .C(intDY_EWSW[60]), .Y(n2419) );
NAND2X1TS U2030 ( .A(n1965), .B(n3323), .Y(n1933) );
CLKINVX3TS U2031 ( .A(n2086), .Y(n2897) );
INVX1TS U2032 ( .A(n1901), .Y(n1902) );
OAI211X2TS U2033 ( .A0(intDY_EWSW[20]), .A1(n3337), .B0(n2403), .C0(n2357),
.Y(n2397) );
INVX4TS U2034 ( .A(n2258), .Y(n1805) );
INVX3TS U2035 ( .A(n2010), .Y(n3211) );
AOI211X1TS U2036 ( .A0(intDX_EWSW[52]), .A1(n3415), .B0(n2339), .C0(n2458),
.Y(n2460) );
NOR2X4TS U2037 ( .A(n2086), .B(n2144), .Y(n2106) );
NAND2BX1TS U2038 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2349) );
NAND2X4TS U2039 ( .A(shift_value_SHT2_EWR[4]), .B(n3332), .Y(n2111) );
NAND2BX1TS U2040 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2425) );
OR2X2TS U2041 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2220) );
NAND2BX1TS U2042 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2414) );
NAND2BX1TS U2043 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2422) );
NAND2BX1TS U2044 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2420) );
NAND2BX1TS U2045 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2463) );
NOR4X6TS U2046 ( .A(Raw_mant_NRM_SWR[1]), .B(Raw_mant_NRM_SWR[2]), .C(n1925),
.D(n3329), .Y(n1910) );
NAND2BX4TS U2047 ( .AN(Raw_mant_NRM_SWR[15]), .B(n1890), .Y(n1930) );
NOR2X4TS U2048 ( .A(n1848), .B(n1930), .Y(n1899) );
AOI21X1TS U2049 ( .A0(n3091), .A1(n3095), .B0(n2848), .Y(n2849) );
XOR2X1TS U2050 ( .A(n2844), .B(DmP_mant_SFG_SWR[20]), .Y(n2847) );
INVX2TS U2051 ( .A(n1900), .Y(n1925) );
NOR2XLTS U2052 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n1895)
);
NAND3XLTS U2053 ( .A(n1900), .B(Raw_mant_NRM_SWR[1]), .C(n3362), .Y(n1999)
);
AOI222X1TS U2054 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2639), .C0(n2803), .C1(
DmP_mant_SHT1_SW[31]), .Y(n2820) );
AOI222X1TS U2055 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2639), .C0(n2704), .C1(
DmP_mant_SHT1_SW[42]), .Y(n2785) );
AOI222X1TS U2056 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n2804), .B0(n2803), .B1(
DmP_mant_SHT1_SW[37]), .C0(n2724), .C1(n1852), .Y(n2695) );
AOI222X1TS U2057 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2804), .C0(n2803), .C1(
DmP_mant_SHT1_SW[33]), .Y(n2794) );
AOI222X1TS U2058 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2804), .B0(n2803), .B1(
DmP_mant_SHT1_SW[35]), .C0(n2724), .C1(DmP_mant_SHT1_SW[34]), .Y(n2774) );
AOI222X1TS U2059 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n2752), .B0(n2725), .B1(
DmP_mant_SHT1_SW[10]), .C0(n2750), .C1(DmP_mant_SHT1_SW[9]), .Y(n2678)
);
AOI222X1TS U2060 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2811), .B0(n2725), .B1(
n1856), .C0(n2750), .C1(DmP_mant_SHT1_SW[15]), .Y(n2747) );
AOI222X1TS U2061 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2804), .B0(n2725), .B1(
n1872), .C0(n2724), .C1(DmP_mant_SHT1_SW[44]), .Y(n2715) );
AOI222X1TS U2062 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2804), .B0(n2803), .B1(
DmP_mant_SHT1_SW[47]), .C0(n2705), .C1(n1851), .Y(n2712) );
AOI222X1TS U2063 ( .A0(n1849), .A1(n2752), .B0(n2725), .B1(
DmP_mant_SHT1_SW[12]), .C0(n2750), .C1(DmP_mant_SHT1_SW[11]), .Y(n2675) );
AOI222X1TS U2064 ( .A0(n1875), .A1(n2811), .B0(n2803), .B1(
DmP_mant_SHT1_SW[14]), .C0(n2750), .C1(DmP_mant_SHT1_SW[13]), .Y(n2683) );
AOI222X1TS U2065 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n2804), .B0(n2751), .B1(
DmP_mant_SHT1_SW[49]), .C0(n2705), .C1(n1850), .Y(n2708) );
AOI222X1TS U2066 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n2752), .B0(
DmP_mant_SHT1_SW[50]), .B1(n2705), .C0(n2751), .C1(n1862), .Y(n2737)
);
AOI222X1TS U2067 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[34]), .C0(n2724), .C1(DmP_mant_SHT1_SW[33]), .Y(n2744) );
AOI222X1TS U2068 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[21]), .C0(n2724), .C1(n1855), .Y(n2698) );
AOI222X1TS U2069 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[32]), .C0(n2724), .C1(DmP_mant_SHT1_SW[31]), .Y(n2728) );
AOI222X1TS U2070 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[47]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[5]), .C0(n2803), .C1(DmP_mant_SHT1_SW[6]), .Y(n2666)
);
AOI222X1TS U2071 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2752), .B0(n2803), .B1(
DmP_mant_SHT1_SW[9]), .C0(n2750), .C1(DmP_mant_SHT1_SW[8]), .Y(n2757)
);
AOI222X1TS U2072 ( .A0(n1848), .A1(n2804), .B0(n2751), .B1(n1870), .C0(n2724), .C1(DmP_mant_SHT1_SW[38]), .Y(n2692) );
AOI222X1TS U2073 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2804), .B0(n2704), .B1(
n1873), .C0(n2724), .C1(DmP_mant_SHT1_SW[42]), .Y(n2729) );
AOI222X1TS U2074 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2804), .B0(
Raw_mant_NRM_SWR[4]), .B1(n2810), .C0(n2751), .C1(n1850), .Y(n2830) );
AOI222X1TS U2075 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2804), .B0(
Raw_mant_NRM_SWR[6]), .B1(n2810), .C0(n2725), .C1(n1851), .Y(n2786) );
AOI222X1TS U2076 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[19]), .C0(n2750), .C1(DmP_mant_SHT1_SW[18]), .Y(n2701) );
AOI222X1TS U2077 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2639), .C0(n2725), .C1(n1863), .Y(n2799)
);
AOI222X1TS U2078 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[30]), .C0(n2724), .C1(n1853), .Y(n2716) );
AOI222X1TS U2079 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[28]), .C0(n2724), .C1(DmP_mant_SHT1_SW[27]), .Y(n2719) );
AOI222X1TS U2080 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[23]), .C0(n2724), .C1(DmP_mant_SHT1_SW[22]), .Y(n2723) );
AOI222X1TS U2081 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2811), .B0(n2725), .B1(
DmP_mant_SHT1_SW[25]), .C0(n2724), .C1(n1854), .Y(n2741) );
AOI222X1TS U2082 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2002), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2639), .C0(n2704), .C1(
DmP_mant_SHT1_SW[22]), .Y(n2827) );
AOI222X1TS U2083 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2002), .B0(
Raw_mant_NRM_SWR[33]), .B1(n2639), .C0(n2751), .C1(n1855), .Y(n2823)
);
NAND3XLTS U2084 ( .A(Raw_mant_NRM_SWR[0]), .B(n3128), .C(n2734), .Y(n2740)
);
AOI222X1TS U2085 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n2811), .B0(n2751), .B1(
DmP_mant_SHT1_SW[7]), .C0(n2724), .C1(DmP_mant_SHT1_SW[6]), .Y(n2674)
);
INVX4TS U2086 ( .A(n2828), .Y(n1844) );
OAI211XLTS U2087 ( .A0(n3331), .A1(intDY_EWSW[3]), .B0(n2363), .C0(n2362),
.Y(n2366) );
NAND2BXLTS U2088 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2375) );
NAND3XLTS U2089 ( .A(n3349), .B(n2374), .C(intDY_EWSW[8]), .Y(n2376) );
OAI21XLTS U2090 ( .A0(intDY_EWSW[15]), .A1(n3287), .B0(intDY_EWSW[14]), .Y(
n2380) );
OAI21XLTS U2091 ( .A0(intDY_EWSW[41]), .A1(n3341), .B0(intDY_EWSW[40]), .Y(
n2428) );
NAND2BXLTS U2092 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2394) );
NAND2BXLTS U2093 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2374) );
NAND2BXLTS U2094 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2358) );
NAND2BXLTS U2095 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2357) );
NOR2X4TS U2096 ( .A(Raw_mant_NRM_SWR[26]), .B(n3113), .Y(n1919) );
NAND3XLTS U2097 ( .A(n3340), .B(n2440), .C(intDY_EWSW[36]), .Y(n2441) );
OAI21XLTS U2098 ( .A0(intDY_EWSW[43]), .A1(n3288), .B0(intDY_EWSW[42]), .Y(
n2429) );
AOI2BB2XLTS U2099 ( .B0(intDY_EWSW[53]), .B1(n3428), .A0N(intDX_EWSW[52]),
.A1N(n2457), .Y(n2459) );
OAI21XLTS U2100 ( .A0(intDY_EWSW[53]), .A1(n3428), .B0(intDY_EWSW[52]), .Y(
n2457) );
OAI21XLTS U2101 ( .A0(intDY_EWSW[55]), .A1(n3429), .B0(intDY_EWSW[54]), .Y(
n2468) );
OAI21XLTS U2102 ( .A0(intDY_EWSW[31]), .A1(n3290), .B0(intDY_EWSW[30]), .Y(
n2352) );
NAND2BXLTS U2103 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2347) );
OAI21XLTS U2104 ( .A0(n3417), .A1(n2220), .B0(n2210), .Y(n2211) );
OAI21XLTS U2105 ( .A0(n3416), .A1(n2220), .B0(n2219), .Y(n2221) );
OAI21XLTS U2106 ( .A0(n3418), .A1(n2220), .B0(n2104), .Y(n2105) );
INVX2TS U2107 ( .A(n1965), .Y(n1967) );
INVX2TS U2108 ( .A(n1963), .Y(n1969) );
AOI2BB1XLTS U2109 ( .A0N(n1989), .A1N(Raw_mant_NRM_SWR[52]), .B0(
Raw_mant_NRM_SWR[53]), .Y(n1990) );
NAND4XLTS U2110 ( .A(n3296), .B(n3366), .C(Raw_mant_NRM_SWR[37]), .D(n1988),
.Y(n1991) );
OAI211XLTS U2111 ( .A0(n3333), .A1(intDY_EWSW[33]), .B0(n2344), .C0(n2446),
.Y(n2345) );
NAND2BXLTS U2112 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2344) );
NOR2XLTS U2113 ( .A(n2412), .B(intDX_EWSW[56]), .Y(n2413) );
NAND4XLTS U2114 ( .A(n2133), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n2132), .Y(n2134) );
NAND4BXLTS U2115 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n2116), .C(n2314), .D(n2319), .Y(n2117) );
OAI211XLTS U2116 ( .A0(n2952), .A1(n2939), .B0(n2183), .C0(n2182), .Y(n2184)
);
OAI211XLTS U2117 ( .A0(n2967), .A1(n2111), .B0(n2912), .C0(n2911), .Y(n2913)
);
INVX2TS U2118 ( .A(n1931), .Y(n1932) );
AOI211X1TS U2119 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2875), .B0(n2874),
.C0(n2873), .Y(n3233) );
AO22XLTS U2120 ( .A0(Data_array_SWR[5]), .A1(n2106), .B0(Data_array_SWR[3]),
.B1(n2910), .Y(n2874) );
BUFX4TS U2121 ( .A(left_right_SHT2), .Y(n3241) );
AOI222X1TS U2122 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2804), .B0(
Raw_mant_NRM_SWR[16]), .B1(n2810), .C0(n2704), .C1(n1852), .Y(n2777)
);
AOI222X1TS U2123 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2752), .B0(n2751), .B1(
DmP_mant_SHT1_SW[13]), .C0(n2750), .C1(DmP_mant_SHT1_SW[12]), .Y(n2763) );
AOI222X1TS U2124 ( .A0(n1849), .A1(n2002), .B0(Raw_mant_NRM_SWR[42]), .B1(
n2639), .C0(n2725), .C1(DmP_mant_SHT1_SW[11]), .Y(n2760) );
XOR2X1TS U2125 ( .A(n2844), .B(DmP_mant_SFG_SWR[21]), .Y(n3080) );
OAI21X1TS U2126 ( .A0(n3045), .A1(n2850), .B0(n2849), .Y(n3079) );
NAND2X1TS U2127 ( .A(n3092), .B(n3095), .Y(n2850) );
INVX2TS U2128 ( .A(n3099), .Y(n3050) );
INVX2TS U2129 ( .A(n3051), .Y(n3053) );
AOI222X1TS U2130 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n2804), .B0(n1848), .B1(
n2810), .C0(n2803), .C1(DmP_mant_SHT1_SW[38]), .Y(n2796) );
AOI222X1TS U2131 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[29]), .B1(n2804), .C0(n2751), .C1(n1854), .Y(n2802)
);
CLKAND2X2TS U2132 ( .A(n2839), .B(DMP_SFG[12]), .Y(n3104) );
INVX2TS U2133 ( .A(n3049), .Y(n3100) );
AOI222X1TS U2134 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2002), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2639), .C0(n2803), .C1(
DmP_mant_SHT1_SW[27]), .Y(n2812) );
OAI21X1TS U2135 ( .A0(n3085), .A1(n3082), .B0(n3086), .Y(n3091) );
NOR2X1TS U2136 ( .A(n3046), .B(n3085), .Y(n3092) );
INVX2TS U2137 ( .A(n3082), .Y(n3083) );
INVX2TS U2138 ( .A(n3045), .Y(n3093) );
INVX2TS U2139 ( .A(n3046), .Y(n3084) );
OAI211X1TS U2140 ( .A0(n2958), .A1(n3238), .B0(n2925), .C0(n2924), .Y(n3254)
);
AO22XLTS U2141 ( .A0(n2143), .A1(n2961), .B0(n2963), .B1(n2962), .Y(n2204)
);
AO22XLTS U2142 ( .A0(n2954), .A1(n2143), .B0(n2955), .B1(n2962), .Y(n2160)
);
CLKAND2X2TS U2143 ( .A(n3425), .B(n2128), .Y(n2136) );
CLKINVX3TS U2144 ( .A(n3218), .Y(n2274) );
OAI211X1TS U2145 ( .A0(n2946), .A1(n2966), .B0(n2945), .C0(n2944), .Y(n3255)
);
OAI211X1TS U2146 ( .A0(n2958), .A1(n2966), .B0(n2957), .C0(n2956), .Y(n3253)
);
NAND4XLTS U2147 ( .A(n3123), .B(n3122), .C(n3121), .D(n3120), .Y(n3125) );
OAI211XLTS U2148 ( .A0(n3236), .A1(n2866), .B0(n2099), .C0(n2098), .Y(n2100)
);
OAI211XLTS U2149 ( .A0(n3231), .A1(n2866), .B0(n2088), .C0(n2087), .Y(n2089)
);
NAND4BXLTS U2150 ( .AN(n1904), .B(n1948), .C(n1999), .D(n1903), .Y(n1905) );
OAI31X1TS U2151 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1848), .A2(n1902), .B0(
n1998), .Y(n1903) );
INVX4TS U2152 ( .A(n3218), .Y(n3016) );
BUFX4TS U2153 ( .A(n2010), .Y(n2549) );
AOI222X1TS U2154 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[50]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[2]), .C0(n2751), .C1(DmP_mant_SHT1_SW[3]), .Y(n2665)
);
AOI222X1TS U2155 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[38]), .B1(n2639), .C0(n2803), .C1(
DmP_mant_SHT1_SW[15]), .Y(n2764) );
BUFX3TS U2156 ( .A(n3430), .Y(n3208) );
OAI21XLTS U2157 ( .A0(n2298), .A1(n2919), .B0(n2297), .Y(n1035) );
OAI211XLTS U2158 ( .A0(n2834), .A1(n2816), .B0(n2809), .C0(n2808), .Y(n1661)
);
MX2X1TS U2159 ( .A(Raw_mant_NRM_SWR[54]), .B(n2989), .S0(n3016), .Y(n1144)
);
MX2X1TS U2160 ( .A(Raw_mant_NRM_SWR[40]), .B(n3010), .S0(n3016), .Y(n1158)
);
MX2X1TS U2161 ( .A(Raw_mant_NRM_SWR[51]), .B(n2983), .S0(n3016), .Y(n1147)
);
MX2X1TS U2162 ( .A(n1849), .B(n3007), .S0(n3016), .Y(n1157) );
AO22XLTS U2163 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[44]), .B0(n3207),
.B1(DmP_mant_SHT1_SW[44]), .Y(n1221) );
AO22XLTS U2164 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[50]), .B0(n3208),
.B1(DmP_mant_SHT1_SW[50]), .Y(n1209) );
AO22XLTS U2165 ( .A0(n3144), .A1(intDX_EWSW[62]), .B0(n3145), .B1(Data_X[62]), .Y(n1732) );
AO22XLTS U2166 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[42]), .B0(n3207),
.B1(DmP_mant_SHT1_SW[42]), .Y(n1225) );
AO22XLTS U2167 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[47]), .B0(n3207),
.B1(DmP_mant_SHT1_SW[47]), .Y(n1215) );
MX2X1TS U2168 ( .A(Raw_mant_NRM_SWR[31]), .B(n3038), .S0(n3065), .Y(n1167)
);
AO22XLTS U2169 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[37]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[37]), .Y(n1235) );
AO22XLTS U2170 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[35]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[35]), .Y(n1239) );
AO22XLTS U2171 ( .A0(n3200), .A1(DmP_EXP_EWSW[19]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1271) );
AO22XLTS U2172 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[49]), .B0(n3207),
.B1(DmP_mant_SHT1_SW[49]), .Y(n1211) );
AO22XLTS U2173 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[30]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[30]), .Y(n1249) );
AO22XLTS U2174 ( .A0(n3204), .A1(DmP_EXP_EWSW[21]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1267) );
OAI211XLTS U2175 ( .A0(n2678), .A1(n2753), .B0(n2677), .C0(n2676), .Y(n1621)
);
MX2X1TS U2176 ( .A(n1875), .B(n3013), .S0(n3016), .Y(n1159) );
AO22XLTS U2177 ( .A0(n3158), .A1(Data_Y[59]), .B0(n3159), .B1(intDY_EWSW[59]), .Y(n1669) );
AO22XLTS U2178 ( .A0(n3143), .A1(Data_X[0]), .B0(n3157), .B1(intDX_EWSW[0]),
.Y(n1794) );
AO22XLTS U2179 ( .A0(n3146), .A1(Data_X[6]), .B0(n3142), .B1(intDX_EWSW[6]),
.Y(n1788) );
MX2X1TS U2180 ( .A(Raw_mant_NRM_SWR[33]), .B(n3032), .S0(n3065), .Y(n1165)
);
AO22XLTS U2181 ( .A0(n3140), .A1(Data_X[39]), .B0(n3147), .B1(intDX_EWSW[39]), .Y(n1755) );
AO22XLTS U2182 ( .A0(n3146), .A1(Data_X[9]), .B0(n3142), .B1(intDX_EWSW[9]),
.Y(n1785) );
AO22XLTS U2183 ( .A0(n3143), .A1(Data_X[4]), .B0(n3150), .B1(intDX_EWSW[4]),
.Y(n1790) );
MX2X1TS U2184 ( .A(n3268), .B(DmP_mant_SFG_SWR[48]), .S0(n2968), .Y(n1022)
);
MX2X1TS U2185 ( .A(n3274), .B(DmP_mant_SFG_SWR[49]), .S0(n2968), .Y(n1021)
);
MX2X1TS U2186 ( .A(n3270), .B(DmP_mant_SFG_SWR[50]), .S0(n2968), .Y(n1020)
);
MX2X1TS U2187 ( .A(n3276), .B(DmP_mant_SFG_SWR[51]), .S0(n3259), .Y(n1019)
);
AO22XLTS U2188 ( .A0(n3160), .A1(Data_Y[63]), .B0(n3159), .B1(intDY_EWSW[63]), .Y(n1665) );
AO22XLTS U2189 ( .A0(n3159), .A1(intDY_EWSW[5]), .B0(n3146), .B1(Data_Y[5]),
.Y(n1723) );
AO22XLTS U2190 ( .A0(n3159), .A1(intDY_EWSW[7]), .B0(n3146), .B1(Data_Y[7]),
.Y(n1721) );
MX2X1TS U2191 ( .A(Raw_mant_NRM_SWR[37]), .B(n3017), .S0(n3016), .Y(n1161)
);
AO22XLTS U2192 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[2]), .B0(n3258), .B1(n3275), .Y(n1134) );
AO22XLTS U2193 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[5]), .B0(n3185), .B1(n3273), .Y(n1132) );
AO22XLTS U2194 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[4]), .B0(n3185), .B1(n3269), .Y(n1127) );
AO22XLTS U2195 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[6]), .B0(n3217), .B1(n3267), .Y(n1124) );
AO22XLTS U2196 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[11]), .B0(n3217), .B1(
n3243), .Y(n1117) );
AO22XLTS U2197 ( .A0(n3204), .A1(DmP_EXP_EWSW[0]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1309) );
AO22XLTS U2198 ( .A0(n3200), .A1(DmP_EXP_EWSW[1]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1307) );
AO22XLTS U2199 ( .A0(n3204), .A1(DmP_EXP_EWSW[2]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1305) );
AO22XLTS U2200 ( .A0(n3200), .A1(DmP_EXP_EWSW[5]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1299) );
AO22XLTS U2201 ( .A0(n3204), .A1(DmP_EXP_EWSW[4]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1301) );
AO22XLTS U2202 ( .A0(n3200), .A1(DmP_EXP_EWSW[3]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1303) );
AO22XLTS U2203 ( .A0(n3204), .A1(DmP_EXP_EWSW[9]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1291) );
AO22XLTS U2204 ( .A0(n3200), .A1(DmP_EXP_EWSW[25]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1259) );
AO22XLTS U2205 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[34]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[34]), .Y(n1241) );
AOI222X1TS U2206 ( .A0(n2567), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n2629), .C0(intDY_EWSW[52]), .C1(n2555), .Y(n2630) );
AO22XLTS U2207 ( .A0(n3200), .A1(DmP_EXP_EWSW[11]), .B0(n3201), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1287) );
AO22XLTS U2208 ( .A0(n3200), .A1(DmP_EXP_EWSW[15]), .B0(n3220), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1279) );
AO22XLTS U2209 ( .A0(n3204), .A1(DmP_EXP_EWSW[18]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1273) );
AO22XLTS U2210 ( .A0(n3200), .A1(DmP_EXP_EWSW[22]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1265) );
AO22XLTS U2211 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[27]), .B0(n3205),
.B1(DmP_mant_SHT1_SW[27]), .Y(n1255) );
AO22XLTS U2212 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[31]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[31]), .Y(n1247) );
AO22XLTS U2213 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[33]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[33]), .Y(n1243) );
AO22XLTS U2214 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[38]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[38]), .Y(n1233) );
AO22XLTS U2215 ( .A0(n3156), .A1(Data_X[63]), .B0(n3157), .B1(intDX_EWSW[63]), .Y(n1731) );
MX2X1TS U2216 ( .A(Raw_mant_NRM_SWR[36]), .B(n3023), .S0(n3065), .Y(n1162)
);
AO22XLTS U2217 ( .A0(n3200), .A1(DmP_EXP_EWSW[17]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1275) );
AO22XLTS U2218 ( .A0(n3204), .A1(DmP_EXP_EWSW[26]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1257) );
AO22XLTS U2219 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[28]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[28]), .Y(n1253) );
AO22XLTS U2220 ( .A0(n3204), .A1(DmP_EXP_EWSW[23]), .B0(n3205), .B1(
DmP_mant_SHT1_SW[23]), .Y(n1263) );
AO22XLTS U2221 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[32]), .B0(n3206),
.B1(DmP_mant_SHT1_SW[32]), .Y(n1245) );
MX2X1TS U2222 ( .A(Raw_mant_NRM_SWR[32]), .B(n3035), .S0(n3065), .Y(n1166)
);
AO22XLTS U2223 ( .A0(n3158), .A1(Data_Y[62]), .B0(n3157), .B1(intDY_EWSW[62]), .Y(n1666) );
AO22XLTS U2224 ( .A0(n3156), .A1(Data_Y[58]), .B0(n3159), .B1(intDY_EWSW[58]), .Y(n1670) );
AO22XLTS U2225 ( .A0(n3158), .A1(Data_Y[60]), .B0(n3159), .B1(intDY_EWSW[60]), .Y(n1668) );
MX2X1TS U2226 ( .A(Raw_mant_NRM_SWR[34]), .B(n3029), .S0(n3065), .Y(n1164)
);
AO22XLTS U2227 ( .A0(n3140), .A1(Data_X[2]), .B0(n3150), .B1(intDX_EWSW[2]),
.Y(n1792) );
AO22XLTS U2228 ( .A0(n3152), .A1(Data_X[24]), .B0(n3141), .B1(intDX_EWSW[24]), .Y(n1770) );
AO22XLTS U2229 ( .A0(n3140), .A1(Data_X[7]), .B0(n3142), .B1(intDX_EWSW[7]),
.Y(n1787) );
AO22XLTS U2230 ( .A0(n3143), .A1(Data_X[32]), .B0(n3148), .B1(intDX_EWSW[32]), .Y(n1762) );
AO22XLTS U2231 ( .A0(n3156), .A1(Data_X[1]), .B0(n3150), .B1(intDX_EWSW[1]),
.Y(n1793) );
AO22XLTS U2232 ( .A0(n3156), .A1(Data_X[10]), .B0(n3142), .B1(intDX_EWSW[10]), .Y(n1784) );
AO22XLTS U2233 ( .A0(n3140), .A1(Data_X[40]), .B0(n3144), .B1(intDX_EWSW[40]), .Y(n1754) );
AO22XLTS U2234 ( .A0(n3152), .A1(Data_X[16]), .B0(n3142), .B1(intDX_EWSW[16]), .Y(n1778) );
AO22XLTS U2235 ( .A0(n3143), .A1(Data_X[48]), .B0(n3157), .B1(intDX_EWSW[48]), .Y(n1746) );
AO22XLTS U2236 ( .A0(n3143), .A1(Data_X[47]), .B0(n3157), .B1(intDX_EWSW[47]), .Y(n1747) );
AO22XLTS U2237 ( .A0(n3145), .A1(Data_X[44]), .B0(n3157), .B1(intDX_EWSW[44]), .Y(n1750) );
OAI211XLTS U2238 ( .A0(n2770), .A1(n2822), .B0(n2680), .C0(n2679), .Y(n1637)
);
AO22XLTS U2239 ( .A0(n3156), .A1(Data_X[52]), .B0(n3157), .B1(intDX_EWSW[52]), .Y(n1742) );
AO22XLTS U2240 ( .A0(n3140), .A1(Data_X[37]), .B0(n3148), .B1(intDX_EWSW[37]), .Y(n1757) );
AO22XLTS U2241 ( .A0(n3140), .A1(Data_X[38]), .B0(n3147), .B1(intDX_EWSW[38]), .Y(n1756) );
AOI22X1TS U2242 ( .A0(n2795), .A1(Data_array_SWR[17]), .B0(n1844), .B1(
DmP_mant_SHT1_SW[19]), .Y(n2825) );
AO22XLTS U2243 ( .A0(n3143), .A1(Data_X[5]), .B0(n3142), .B1(intDX_EWSW[5]),
.Y(n1789) );
MX2X1TS U2244 ( .A(Raw_mant_NRM_SWR[44]), .B(n2971), .S0(n3065), .Y(n1154)
);
MX2X1TS U2245 ( .A(Raw_mant_NRM_SWR[42]), .B(n3004), .S0(n3016), .Y(n1156)
);
MX2X1TS U2246 ( .A(Raw_mant_NRM_SWR[38]), .B(n3020), .S0(n3065), .Y(n1160)
);
MX2X1TS U2247 ( .A(Raw_mant_NRM_SWR[35]), .B(n3026), .S0(n3065), .Y(n1163)
);
AO22XLTS U2248 ( .A0(n3144), .A1(intDX_EWSW[56]), .B0(n3149), .B1(Data_X[56]), .Y(n1738) );
AO22XLTS U2249 ( .A0(n3155), .A1(intDY_EWSW[37]), .B0(n3149), .B1(Data_Y[37]), .Y(n1691) );
AO22XLTS U2250 ( .A0(n3155), .A1(intDY_EWSW[38]), .B0(n3149), .B1(Data_Y[38]), .Y(n1690) );
AO22XLTS U2251 ( .A0(n3144), .A1(intDX_EWSW[58]), .B0(n3145), .B1(Data_X[58]), .Y(n1736) );
AO22XLTS U2252 ( .A0(n3159), .A1(intDY_EWSW[1]), .B0(n3145), .B1(Data_Y[1]),
.Y(n1727) );
AO22XLTS U2253 ( .A0(n3147), .A1(intDY_EWSW[16]), .B0(n3145), .B1(Data_Y[16]), .Y(n1712) );
AO22XLTS U2254 ( .A0(n3147), .A1(intDX_EWSW[53]), .B0(n3145), .B1(Data_X[53]), .Y(n1741) );
AO22XLTS U2255 ( .A0(n3147), .A1(intDX_EWSW[55]), .B0(n3145), .B1(Data_X[55]), .Y(n1739) );
AO22XLTS U2256 ( .A0(n3149), .A1(Data_X[13]), .B0(n3142), .B1(intDX_EWSW[13]), .Y(n1781) );
AO22XLTS U2257 ( .A0(n3149), .A1(Data_X[41]), .B0(n3147), .B1(intDX_EWSW[41]), .Y(n1753) );
AO22XLTS U2258 ( .A0(n3149), .A1(Data_X[43]), .B0(n3142), .B1(intDX_EWSW[43]), .Y(n1751) );
AO22XLTS U2259 ( .A0(n3149), .A1(Data_X[45]), .B0(n3157), .B1(intDX_EWSW[45]), .Y(n1749) );
AO22XLTS U2260 ( .A0(n3145), .A1(Data_X[12]), .B0(n3142), .B1(intDX_EWSW[12]), .Y(n1782) );
AO22XLTS U2261 ( .A0(n3145), .A1(Data_X[42]), .B0(n3148), .B1(intDX_EWSW[42]), .Y(n1752) );
AO22XLTS U2262 ( .A0(n3144), .A1(intDY_EWSW[10]), .B0(n3139), .B1(Data_Y[10]), .Y(n1718) );
OAI211XLTS U2263 ( .A0(n2316), .A1(n3136), .B0(n3214), .C0(n2315), .Y(n1590)
);
OAI211XLTS U2264 ( .A0(n2306), .A1(n2318), .B0(n3214), .C0(n2305), .Y(n1592)
);
OAI211XLTS U2265 ( .A0(n2310), .A1(n3278), .B0(n3214), .C0(n2309), .Y(n1593)
);
OAI211XLTS U2266 ( .A0(n2319), .A1(n3272), .B0(n3214), .C0(n2317), .Y(n1596)
);
AO22XLTS U2267 ( .A0(n3280), .A1(n3279), .B0(final_result_ieee[51]), .B1(
n3272), .Y(n1056) );
AO22XLTS U2268 ( .A0(n3280), .A1(n3277), .B0(final_result_ieee[50]), .B1(
n3136), .Y(n1057) );
AO22XLTS U2269 ( .A0(n3280), .A1(n3276), .B0(final_result_ieee[49]), .B1(
n3278), .Y(n1058) );
AO22XLTS U2270 ( .A0(n3280), .A1(n3275), .B0(final_result_ieee[0]), .B1(
n2318), .Y(n1059) );
AO22XLTS U2271 ( .A0(n3280), .A1(n3274), .B0(final_result_ieee[47]), .B1(
n3219), .Y(n1060) );
AO22XLTS U2272 ( .A0(n3280), .A1(n3273), .B0(final_result_ieee[3]), .B1(
n3272), .Y(n1065) );
AO22XLTS U2273 ( .A0(n3280), .A1(n3271), .B0(final_result_ieee[1]), .B1(
n3136), .Y(n1066) );
AO22XLTS U2274 ( .A0(n3280), .A1(n3270), .B0(final_result_ieee[48]), .B1(
n3278), .Y(n1067) );
AO22XLTS U2275 ( .A0(n3280), .A1(n3269), .B0(final_result_ieee[2]), .B1(
n2318), .Y(n1068) );
AO22XLTS U2276 ( .A0(n3280), .A1(n3268), .B0(final_result_ieee[46]), .B1(
n3272), .Y(n1075) );
AO22XLTS U2277 ( .A0(n3280), .A1(n3267), .B0(final_result_ieee[4]), .B1(
n3219), .Y(n1076) );
AO22XLTS U2278 ( .A0(n3280), .A1(n3266), .B0(final_result_ieee[45]), .B1(
n3272), .Y(n1077) );
AO22XLTS U2279 ( .A0(n3280), .A1(n3265), .B0(final_result_ieee[5]), .B1(
n3278), .Y(n1078) );
AO22XLTS U2280 ( .A0(n3280), .A1(n3264), .B0(final_result_ieee[44]), .B1(
n3136), .Y(n1079) );
AO22XLTS U2281 ( .A0(n3263), .A1(n3242), .B0(final_result_ieee[6]), .B1(
n2318), .Y(n1080) );
AO22XLTS U2282 ( .A0(n3263), .A1(n3262), .B0(final_result_ieee[29]), .B1(
n2318), .Y(n1082) );
AO22XLTS U2283 ( .A0(n3263), .A1(n3261), .B0(final_result_ieee[21]), .B1(
n3219), .Y(n1083) );
AO22XLTS U2284 ( .A0(n3263), .A1(n2920), .B0(final_result_ieee[41]), .B1(
n3278), .Y(n1085) );
AO22XLTS U2285 ( .A0(n3263), .A1(n3243), .B0(final_result_ieee[9]), .B1(
n3219), .Y(n1086) );
AO22XLTS U2286 ( .A0(n3263), .A1(n3260), .B0(final_result_ieee[25]), .B1(
n3272), .Y(n1089) );
AO22XLTS U2287 ( .A0(n3263), .A1(n2917), .B0(final_result_ieee[43]), .B1(
n3219), .Y(n1090) );
AO22XLTS U2288 ( .A0(n3263), .A1(n3251), .B0(final_result_ieee[7]), .B1(
n3136), .Y(n1091) );
AO22XLTS U2289 ( .A0(n3263), .A1(n2918), .B0(final_result_ieee[42]), .B1(
n3278), .Y(n1094) );
AO22XLTS U2290 ( .A0(n3263), .A1(n3257), .B0(final_result_ieee[8]), .B1(
n2318), .Y(n1095) );
AO22XLTS U2291 ( .A0(n3263), .A1(n3256), .B0(final_result_ieee[26]), .B1(
n3136), .Y(n1098) );
AO22XLTS U2292 ( .A0(n3263), .A1(n3255), .B0(final_result_ieee[24]), .B1(
n3278), .Y(n1099) );
AO22XLTS U2293 ( .A0(n3263), .A1(n3254), .B0(final_result_ieee[28]), .B1(
n2318), .Y(n1102) );
AO22XLTS U2294 ( .A0(n3263), .A1(n3253), .B0(final_result_ieee[22]), .B1(
n3219), .Y(n1103) );
AO22XLTS U2295 ( .A0(n3263), .A1(n3250), .B0(final_result_ieee[27]), .B1(
n3272), .Y(n1107) );
AO22XLTS U2296 ( .A0(n3249), .A1(n3248), .B0(final_result_ieee[23]), .B1(
n3136), .Y(n1108) );
AO22XLTS U2297 ( .A0(n3280), .A1(n3129), .B0(final_result_ieee[62]), .B1(
n3272), .Y(n1588) );
AO22XLTS U2298 ( .A0(n3148), .A1(intDY_EWSW[27]), .B0(n3149), .B1(Data_Y[27]), .Y(n1701) );
AO22XLTS U2299 ( .A0(n3159), .A1(intDY_EWSW[3]), .B0(n3140), .B1(Data_Y[3]),
.Y(n1725) );
AO22XLTS U2300 ( .A0(n3144), .A1(intDX_EWSW[59]), .B0(n3145), .B1(Data_X[59]), .Y(n1735) );
AO22XLTS U2301 ( .A0(n3148), .A1(intDY_EWSW[31]), .B0(n3149), .B1(Data_Y[31]), .Y(n1697) );
AO22XLTS U2302 ( .A0(n3159), .A1(intDY_EWSW[6]), .B0(n3146), .B1(Data_Y[6]),
.Y(n1722) );
OAI222X1TS U2303 ( .A0(n3210), .A1(n3428), .B0(n3316), .B1(n3211), .C0(n3284), .C1(n3213), .Y(n1534) );
AO22XLTS U2304 ( .A0(n3144), .A1(intDX_EWSW[54]), .B0(n3145), .B1(Data_X[54]), .Y(n1740) );
AO22XLTS U2305 ( .A0(n3159), .A1(intDY_EWSW[9]), .B0(n3146), .B1(Data_Y[9]),
.Y(n1719) );
AO22XLTS U2306 ( .A0(n3147), .A1(intDY_EWSW[13]), .B0(n3146), .B1(Data_Y[13]), .Y(n1715) );
AO22XLTS U2307 ( .A0(n3144), .A1(intDY_EWSW[2]), .B0(n3149), .B1(Data_Y[2]),
.Y(n1726) );
AO22XLTS U2308 ( .A0(n3159), .A1(intDY_EWSW[8]), .B0(n3146), .B1(Data_Y[8]),
.Y(n1720) );
AO22XLTS U2309 ( .A0(n3144), .A1(intDY_EWSW[12]), .B0(n3146), .B1(Data_Y[12]), .Y(n1716) );
AO22XLTS U2310 ( .A0(n3150), .A1(intDY_EWSW[32]), .B0(n3149), .B1(Data_Y[32]), .Y(n1696) );
AO22XLTS U2311 ( .A0(n3144), .A1(intDX_EWSW[61]), .B0(n3145), .B1(Data_X[61]), .Y(n1733) );
AO22XLTS U2312 ( .A0(n3148), .A1(intDY_EWSW[33]), .B0(n3149), .B1(Data_Y[33]), .Y(n1695) );
AO22XLTS U2313 ( .A0(n3155), .A1(intDY_EWSW[34]), .B0(n3149), .B1(Data_Y[34]), .Y(n1694) );
AO22XLTS U2314 ( .A0(n3150), .A1(intDY_EWSW[36]), .B0(n3149), .B1(Data_Y[36]), .Y(n1692) );
AO22XLTS U2315 ( .A0(n3148), .A1(intDY_EWSW[30]), .B0(n3149), .B1(Data_Y[30]), .Y(n1698) );
AO22XLTS U2316 ( .A0(n3147), .A1(intDX_EWSW[49]), .B0(n3145), .B1(Data_X[49]), .Y(n1745) );
AO22XLTS U2317 ( .A0(n3259), .A1(n1858), .B0(n2858), .B1(n3271), .Y(n1129)
);
MX2X1TS U2318 ( .A(Raw_mant_NRM_SWR[48]), .B(n2995), .S0(n3016), .Y(n1150)
);
MX2X1TS U2319 ( .A(Raw_mant_NRM_SWR[47]), .B(n2998), .S0(n3016), .Y(n1151)
);
MX2X1TS U2320 ( .A(Raw_mant_NRM_SWR[46]), .B(n2974), .S0(n3225), .Y(n1152)
);
MX2X1TS U2321 ( .A(Raw_mant_NRM_SWR[45]), .B(n2977), .S0(n3016), .Y(n1153)
);
MX2X1TS U2322 ( .A(Raw_mant_NRM_SWR[43]), .B(n3001), .S0(n3016), .Y(n1155)
);
OAI222X1TS U2323 ( .A0(n3213), .A1(n3285), .B0(n3212), .B1(n3211), .C0(n3281), .C1(n3210), .Y(n1202) );
AO22XLTS U2324 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[51]), .B0(n3208),
.B1(n1862), .Y(n1207) );
OAI21XLTS U2325 ( .A0(n3406), .A1(n3210), .B0(n2603), .Y(n1208) );
OAI21XLTS U2326 ( .A0(n3388), .A1(n3210), .B0(n2601), .Y(n1210) );
OAI21XLTS U2327 ( .A0(n3409), .A1(n3210), .B0(n2599), .Y(n1212) );
AO22XLTS U2328 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[48]), .B0(n3207),
.B1(n1850), .Y(n1213) );
OAI21XLTS U2329 ( .A0(n3381), .A1(n3210), .B0(n2598), .Y(n1214) );
OAI21XLTS U2330 ( .A0(n3308), .A1(n2579), .B0(n2566), .Y(n1216) );
AO22XLTS U2331 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[46]), .B0(n3207),
.B1(n1851), .Y(n1217) );
OAI21XLTS U2332 ( .A0(n3405), .A1(n2579), .B0(n2519), .Y(n1218) );
AO22XLTS U2333 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[45]), .B0(n3207),
.B1(n1872), .Y(n1219) );
OAI21XLTS U2334 ( .A0(n3398), .A1(n2579), .B0(n2524), .Y(n1220) );
OAI21XLTS U2335 ( .A0(n3404), .A1(n2579), .B0(n2570), .Y(n1222) );
AO22XLTS U2336 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[43]), .B0(n3207),
.B1(n1873), .Y(n1223) );
OAI21XLTS U2337 ( .A0(n3311), .A1(n2579), .B0(n2520), .Y(n1224) );
OAI21XLTS U2338 ( .A0(n3403), .A1(n2579), .B0(n2523), .Y(n1226) );
AO22XLTS U2339 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[41]), .B0(n3207),
.B1(n1874), .Y(n1227) );
OAI21XLTS U2340 ( .A0(n3310), .A1(n2579), .B0(n2527), .Y(n1228) );
AO22XLTS U2341 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[40]), .B0(n3207),
.B1(n1863), .Y(n1229) );
OAI21XLTS U2342 ( .A0(n3402), .A1(n2579), .B0(n2565), .Y(n1230) );
AO22XLTS U2343 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[39]), .B0(n3207),
.B1(n1870), .Y(n1231) );
OAI21XLTS U2344 ( .A0(n3397), .A1(n2579), .B0(n2578), .Y(n1232) );
OAI21XLTS U2345 ( .A0(n3422), .A1(n2579), .B0(n2569), .Y(n1234) );
OAI21XLTS U2346 ( .A0(n3396), .A1(n2579), .B0(n2568), .Y(n1236) );
AO22XLTS U2347 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[36]), .B0(n3206),
.B1(n1852), .Y(n1237) );
OAI21XLTS U2348 ( .A0(n3401), .A1(n2579), .B0(n2525), .Y(n1238) );
OAI21XLTS U2349 ( .A0(n3309), .A1(n2579), .B0(n2526), .Y(n1240) );
OAI21XLTS U2350 ( .A0(n3400), .A1(n2585), .B0(n2521), .Y(n1242) );
OAI21XLTS U2351 ( .A0(n3399), .A1(n2585), .B0(n2522), .Y(n1244) );
OAI21XLTS U2352 ( .A0(n3380), .A1(n2585), .B0(n2564), .Y(n1246) );
OAI21XLTS U2353 ( .A0(n3314), .A1(n2585), .B0(n2512), .Y(n1248) );
OAI21XLTS U2354 ( .A0(n3412), .A1(n2585), .B0(n2513), .Y(n1250) );
AO22XLTS U2355 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[29]), .B0(n3206),
.B1(n1853), .Y(n1251) );
OAI21XLTS U2356 ( .A0(n3302), .A1(n2585), .B0(n2515), .Y(n1252) );
OAI21XLTS U2357 ( .A0(n3379), .A1(n2585), .B0(n2518), .Y(n1254) );
OAI21XLTS U2358 ( .A0(n3300), .A1(n2585), .B0(n2514), .Y(n1256) );
OAI21XLTS U2359 ( .A0(n3378), .A1(n2585), .B0(n2517), .Y(n1258) );
OAI21XLTS U2360 ( .A0(n3299), .A1(n2585), .B0(n2516), .Y(n1260) );
AO22XLTS U2361 ( .A0(n3200), .A1(DmP_EXP_EWSW[24]), .B0(n3205), .B1(n1854),
.Y(n1261) );
OAI21XLTS U2362 ( .A0(n3377), .A1(n2585), .B0(n2574), .Y(n1262) );
OAI21XLTS U2363 ( .A0(n3313), .A1(n2585), .B0(n2561), .Y(n1264) );
OAI21XLTS U2364 ( .A0(n3411), .A1(n2627), .B0(n2615), .Y(n1266) );
OAI21XLTS U2365 ( .A0(n3371), .A1(n2627), .B0(n2612), .Y(n1268) );
AO22XLTS U2366 ( .A0(n3204), .A1(DmP_EXP_EWSW[20]), .B0(n3205), .B1(n1855),
.Y(n1269) );
OAI21XLTS U2367 ( .A0(n3376), .A1(n2627), .B0(n2611), .Y(n1270) );
OAI21XLTS U2368 ( .A0(n3298), .A1(n2627), .B0(n2610), .Y(n1272) );
OAI21XLTS U2369 ( .A0(n3375), .A1(n2627), .B0(n2621), .Y(n1274) );
OAI21XLTS U2370 ( .A0(n3297), .A1(n2627), .B0(n2609), .Y(n1276) );
OAI21XLTS U2371 ( .A0(n3382), .A1(n2627), .B0(n2624), .Y(n1278) );
OAI21XLTS U2372 ( .A0(n3312), .A1(n2627), .B0(n2614), .Y(n1280) );
OAI21XLTS U2373 ( .A0(n3410), .A1(n2627), .B0(n2608), .Y(n1282) );
OAI21XLTS U2374 ( .A0(n3370), .A1(n2627), .B0(n2613), .Y(n1284) );
OAI21XLTS U2375 ( .A0(n3374), .A1(n2627), .B0(n2616), .Y(n1286) );
OAI21XLTS U2376 ( .A0(n3305), .A1(n2627), .B0(n2617), .Y(n1288) );
OAI21XLTS U2377 ( .A0(n3369), .A1(n2627), .B0(n2620), .Y(n1290) );
OAI21XLTS U2378 ( .A0(n3368), .A1(n2589), .B0(n2575), .Y(n1292) );
OAI21XLTS U2379 ( .A0(n3373), .A1(n2589), .B0(n2562), .Y(n1294) );
OAI21XLTS U2380 ( .A0(n2582), .A1(n2589), .B0(n2581), .Y(n1296) );
OAI21XLTS U2381 ( .A0(n3315), .A1(n2589), .B0(n2573), .Y(n1298) );
OAI21XLTS U2382 ( .A0(n2606), .A1(n2589), .B0(n2586), .Y(n1300) );
OAI21XLTS U2383 ( .A0(n3303), .A1(n2589), .B0(n2580), .Y(n1302) );
OAI21XLTS U2384 ( .A0(n3372), .A1(n2589), .B0(n2576), .Y(n1306) );
OAI21XLTS U2385 ( .A0(n3421), .A1(n2589), .B0(n2583), .Y(n1308) );
OAI21XLTS U2386 ( .A0(n1867), .A1(n2589), .B0(n2588), .Y(n1310) );
OAI21XLTS U2387 ( .A0(n3391), .A1(n2589), .B0(n2572), .Y(n1526) );
OAI21XLTS U2388 ( .A0(n3393), .A1(n2627), .B0(n2626), .Y(n1527) );
OAI21XLTS U2389 ( .A0(n3307), .A1(n2589), .B0(n2587), .Y(n1528) );
OAI21XLTS U2390 ( .A0(n3392), .A1(n3210), .B0(n2600), .Y(n1529) );
OAI21XLTS U2391 ( .A0(n3389), .A1(n3213), .B0(n2607), .Y(n1530) );
OAI21XLTS U2392 ( .A0(n3406), .A1(n3213), .B0(n2510), .Y(n1536) );
OAI21XLTS U2393 ( .A0(n3388), .A1(n3213), .B0(n2509), .Y(n1537) );
OAI21XLTS U2394 ( .A0(n3409), .A1(n2503), .B0(n2490), .Y(n1538) );
OAI21XLTS U2395 ( .A0(n3381), .A1(n2503), .B0(n2488), .Y(n1539) );
OAI21XLTS U2396 ( .A0(n3308), .A1(n2503), .B0(n2496), .Y(n1540) );
OAI21XLTS U2397 ( .A0(n3405), .A1(n2503), .B0(n2501), .Y(n1541) );
OAI21XLTS U2398 ( .A0(n3404), .A1(n2503), .B0(n2491), .Y(n1543) );
OAI21XLTS U2399 ( .A0(n3311), .A1(n2503), .B0(n2497), .Y(n1544) );
OAI21XLTS U2400 ( .A0(n3403), .A1(n2503), .B0(n2502), .Y(n1545) );
OAI21XLTS U2401 ( .A0(n3310), .A1(n2503), .B0(n2500), .Y(n1546) );
OAI21XLTS U2402 ( .A0(n3402), .A1(n2503), .B0(n2498), .Y(n1547) );
OAI21XLTS U2403 ( .A0(n3397), .A1(n2552), .B0(n2545), .Y(n1548) );
OAI21XLTS U2404 ( .A0(n3422), .A1(n2552), .B0(n2529), .Y(n1549) );
OAI21XLTS U2405 ( .A0(n3396), .A1(n2552), .B0(n2533), .Y(n1550) );
OAI21XLTS U2406 ( .A0(n3401), .A1(n2552), .B0(n2544), .Y(n1551) );
OAI21XLTS U2407 ( .A0(n3309), .A1(n2552), .B0(n2546), .Y(n1552) );
OAI21XLTS U2408 ( .A0(n3400), .A1(n2552), .B0(n2551), .Y(n1553) );
OAI21XLTS U2409 ( .A0(n3399), .A1(n2552), .B0(n2548), .Y(n1554) );
OAI21XLTS U2410 ( .A0(n3380), .A1(n2552), .B0(n2543), .Y(n1555) );
OAI21XLTS U2411 ( .A0(n3412), .A1(n2605), .B0(n2532), .Y(n1557) );
OAI21XLTS U2412 ( .A0(n3302), .A1(n2552), .B0(n2542), .Y(n1558) );
OAI21XLTS U2413 ( .A0(n3379), .A1(n3213), .B0(n2507), .Y(n1559) );
OAI21XLTS U2414 ( .A0(n3300), .A1(n2503), .B0(n2495), .Y(n1560) );
OAI21XLTS U2415 ( .A0(n3378), .A1(n2552), .B0(n2535), .Y(n1561) );
OAI21XLTS U2416 ( .A0(n3299), .A1(n3213), .B0(n2508), .Y(n1562) );
OAI21XLTS U2417 ( .A0(n3377), .A1(n2503), .B0(n2493), .Y(n1563) );
OAI21XLTS U2418 ( .A0(n3313), .A1(n2503), .B0(n2489), .Y(n1564) );
OAI21XLTS U2419 ( .A0(n3411), .A1(n2552), .B0(n2528), .Y(n1565) );
OAI21XLTS U2420 ( .A0(n3371), .A1(n2503), .B0(n2492), .Y(n1566) );
OAI21XLTS U2421 ( .A0(n3376), .A1(n3213), .B0(n2506), .Y(n1567) );
OAI21XLTS U2422 ( .A0(n3298), .A1(n3213), .B0(n2505), .Y(n1568) );
OAI21XLTS U2423 ( .A0(n3375), .A1(n2605), .B0(n2538), .Y(n1569) );
OAI21XLTS U2424 ( .A0(n3382), .A1(n2560), .B0(n2487), .Y(n1571) );
OAI21XLTS U2425 ( .A0(n3312), .A1(n2605), .B0(n2531), .Y(n1572) );
OAI21XLTS U2426 ( .A0(n3410), .A1(n2560), .B0(n2483), .Y(n1573) );
OAI21XLTS U2427 ( .A0(n3370), .A1(n2605), .B0(n2536), .Y(n1574) );
OAI21XLTS U2428 ( .A0(n3374), .A1(n3213), .B0(n2504), .Y(n1575) );
OAI21XLTS U2429 ( .A0(n3305), .A1(n2552), .B0(n2539), .Y(n1576) );
OAI21XLTS U2430 ( .A0(n3369), .A1(n2560), .B0(n2594), .Y(n1577) );
OAI21XLTS U2431 ( .A0(n3368), .A1(n2605), .B0(n2592), .Y(n1578) );
OAI21XLTS U2432 ( .A0(n3373), .A1(n2605), .B0(n2537), .Y(n1579) );
OAI21XLTS U2433 ( .A0(n2582), .A1(n2605), .B0(n2553), .Y(n1580) );
OAI21XLTS U2434 ( .A0(n3315), .A1(n2605), .B0(n2591), .Y(n1581) );
OAI21XLTS U2435 ( .A0(n2606), .A1(n2605), .B0(n2604), .Y(n1582) );
OAI21XLTS U2436 ( .A0(n3303), .A1(n2605), .B0(n2596), .Y(n1583) );
OAI21XLTS U2437 ( .A0(n3372), .A1(n2605), .B0(n2595), .Y(n1585) );
OAI21XLTS U2438 ( .A0(n3421), .A1(n2605), .B0(n2597), .Y(n1586) );
OAI21XLTS U2439 ( .A0(n1867), .A1(n3213), .B0(n2511), .Y(n1587) );
AO22XLTS U2440 ( .A0(n3186), .A1(n3165), .B0(n3430), .B1(n1859), .Y(n1604)
);
AO22XLTS U2441 ( .A0(n3144), .A1(n1868), .B0(n3145), .B1(Data_Y[0]), .Y(
n1728) );
OA21XLTS U2442 ( .A0(n3417), .A1(n2907), .B0(n2185), .Y(n1808) );
BUFX3TS U2443 ( .A(n2826), .Y(n2711) );
OR2X2TS U2444 ( .A(n2826), .B(n2736), .Y(n1815) );
NOR2X6TS U2445 ( .A(n3241), .B(n2111), .Y(n2143) );
OAI221X1TS U2446 ( .A0(n3300), .A1(intDX_EWSW[27]), .B0(n3378), .B1(
intDX_EWSW[26]), .C0(n2045), .Y(n2048) );
OAI21XLTS U2447 ( .A0(n2292), .A1(n2919), .B0(n2291), .Y(n1032) );
OAI21XLTS U2448 ( .A0(n2290), .A1(n2919), .B0(n2289), .Y(n1033) );
OAI21XLTS U2449 ( .A0(n2288), .A1(n2919), .B0(n2287), .Y(n1034) );
OAI21XLTS U2450 ( .A0(n2294), .A1(n2919), .B0(n2293), .Y(n1051) );
OAI21XLTS U2451 ( .A0(n2280), .A1(n2919), .B0(n2279), .Y(n1052) );
OAI21XLTS U2452 ( .A0(n2286), .A1(n2919), .B0(n2285), .Y(n1054) );
OAI21XLTS U2453 ( .A0(n2282), .A1(n2919), .B0(n2281), .Y(n1055) );
OAI21XLTS U2454 ( .A0(n2296), .A1(n2919), .B0(n2295), .Y(n1143) );
OAI21X1TS U2455 ( .A0(n3416), .A1(n2907), .B0(n2906), .Y(n2908) );
CLKINVX3TS U2456 ( .A(rst), .Y(n3504) );
NOR4X2TS U2457 ( .A(n2340), .B(n2412), .C(n2424), .D(n2416), .Y(n2469) );
BUFX4TS U2458 ( .A(n3494), .Y(n3461) );
BUFX4TS U2459 ( .A(n3496), .Y(n3462) );
BUFX4TS U2460 ( .A(n3494), .Y(n3499) );
BUFX4TS U2461 ( .A(n3496), .Y(n3460) );
BUFX4TS U2462 ( .A(n3477), .Y(n3456) );
BUFX4TS U2463 ( .A(n3485), .Y(n3453) );
BUFX4TS U2464 ( .A(n3483), .Y(n3454) );
BUFX3TS U2465 ( .A(n2008), .Y(n2009) );
BUFX4TS U2466 ( .A(n3491), .Y(n3473) );
BUFX4TS U2467 ( .A(n3491), .Y(n3472) );
AOI222X1TS U2468 ( .A0(n1935), .A1(Raw_mant_NRM_SWR[32]), .B0(
Raw_mant_NRM_SWR[34]), .B1(n1934), .C0(n1933), .C1(n1932), .Y(n1936)
);
BUFX4TS U2469 ( .A(n3474), .Y(n3487) );
BUFX4TS U2470 ( .A(n3474), .Y(n3465) );
BUFX4TS U2471 ( .A(n3498), .Y(n3455) );
BUFX4TS U2472 ( .A(n2009), .Y(n3468) );
BUFX4TS U2473 ( .A(n2009), .Y(n3470) );
BUFX3TS U2474 ( .A(n2009), .Y(n3494) );
BUFX4TS U2475 ( .A(n2009), .Y(n3457) );
BUFX4TS U2476 ( .A(n3208), .Y(n3191) );
BUFX4TS U2477 ( .A(n3140), .Y(n3153) );
BUFX4TS U2478 ( .A(n3201), .Y(n3203) );
INVX4TS U2479 ( .A(n3505), .Y(n1847) );
AOI21X2TS U2480 ( .A0(n1881), .A1(n2909), .B0(n2190), .Y(n2946) );
OAI21X1TS U2481 ( .A0(n3418), .A1(n2907), .B0(n2189), .Y(n2190) );
BUFX4TS U2482 ( .A(n3207), .Y(n3206) );
BUFX4TS U2483 ( .A(n3478), .Y(n3445) );
BUFX4TS U2484 ( .A(n3140), .Y(n3152) );
BUFX4TS U2485 ( .A(n3452), .Y(n3444) );
BUFX4TS U2486 ( .A(n2649), .Y(n2833) );
BUFX4TS U2487 ( .A(n3441), .Y(n3443) );
BUFX4TS U2488 ( .A(n3501), .Y(n3442) );
BUFX4TS U2489 ( .A(n3500), .Y(n3446) );
BUFX4TS U2490 ( .A(n3500), .Y(n3447) );
BUFX4TS U2491 ( .A(n3450), .Y(n3440) );
BUFX4TS U2492 ( .A(n3445), .Y(n3498) );
BUFX4TS U2493 ( .A(n3495), .Y(n3477) );
BUFX4TS U2494 ( .A(n3495), .Y(n3478) );
BUFX4TS U2495 ( .A(n3160), .Y(n3156) );
BUFX4TS U2496 ( .A(n3139), .Y(n3143) );
BUFX3TS U2497 ( .A(n3504), .Y(n2008) );
BUFX4TS U2498 ( .A(n3504), .Y(n3491) );
AOI211X1TS U2499 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2882), .B0(n2881),
.C0(n2880), .Y(n3235) );
OAI22X2TS U2500 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2235), .B0(n1826), .B1(
n2225), .Y(n2882) );
AOI211X1TS U2501 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2903), .B0(n2902),
.C0(n2901), .Y(n3237) );
OAI22X2TS U2502 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2152), .B0(n3408), .B1(
n2225), .Y(n2903) );
BUFX4TS U2503 ( .A(n3426), .Y(n3219) );
BUFX4TS U2504 ( .A(n3499), .Y(n3441) );
BUFX3TS U2505 ( .A(n3462), .Y(n3501) );
BUFX4TS U2506 ( .A(n3474), .Y(n3449) );
BUFX4TS U2507 ( .A(n3501), .Y(n3450) );
BUFX4TS U2508 ( .A(n3458), .Y(n3448) );
BUFX4TS U2509 ( .A(n2009), .Y(n3483) );
OAI22X2TS U2510 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2226), .B0(n3395), .B1(
n2225), .Y(n2875) );
BUFX4TS U2511 ( .A(n2008), .Y(n3485) );
INVX2TS U2512 ( .A(n1816), .Y(n1849) );
OAI222X1TS U2513 ( .A0(n2560), .A1(n3320), .B0(n1821), .B1(n3211), .C0(n3282), .C1(n3210), .Y(n1204) );
OAI222X1TS U2514 ( .A0(n3210), .A1(n3285), .B0(n3321), .B1(n3211), .C0(n3281), .C1(n3213), .Y(n1531) );
OAI222X1TS U2515 ( .A0(n3210), .A1(n3429), .B0(n3319), .B1(n3211), .C0(n3283), .C1(n3213), .Y(n1532) );
OAI222X1TS U2516 ( .A0(n3210), .A1(n3320), .B0(n3317), .B1(n3211), .C0(n3282), .C1(n3213), .Y(n1533) );
INVX2TS U2517 ( .A(n1836), .Y(n1850) );
INVX2TS U2518 ( .A(n1835), .Y(n1851) );
INVX2TS U2519 ( .A(n1814), .Y(n1852) );
INVX2TS U2520 ( .A(n1813), .Y(n1853) );
INVX2TS U2521 ( .A(n1812), .Y(n1854) );
INVX2TS U2522 ( .A(n1834), .Y(n1855) );
INVX2TS U2523 ( .A(n1838), .Y(n1856) );
INVX2TS U2524 ( .A(n1842), .Y(n1857) );
INVX2TS U2525 ( .A(n1841), .Y(n1858) );
INVX2TS U2526 ( .A(n1822), .Y(n1859) );
INVX2TS U2527 ( .A(n1839), .Y(n1860) );
INVX2TS U2528 ( .A(n1840), .Y(n1861) );
INVX2TS U2529 ( .A(n1833), .Y(n1862) );
BUFX4TS U2530 ( .A(n3426), .Y(n3272) );
BUFX4TS U2531 ( .A(n3426), .Y(n3278) );
BUFX4TS U2532 ( .A(n3426), .Y(n3136) );
BUFX4TS U2533 ( .A(n3426), .Y(n2318) );
AOI222X1TS U2534 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2810), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2639), .C0(n2704), .C1(DmP_mant_SHT1_SW[44]), .Y(n2782) );
INVX2TS U2535 ( .A(n1832), .Y(n1863) );
INVX2TS U2536 ( .A(n1837), .Y(n1864) );
INVX2TS U2537 ( .A(n1827), .Y(n1865) );
INVX2TS U2538 ( .A(n1828), .Y(n1866) );
INVX2TS U2539 ( .A(intDY_EWSW[0]), .Y(n1867) );
INVX2TS U2540 ( .A(n1867), .Y(n1868) );
BUFX4TS U2541 ( .A(n2704), .Y(n2751) );
BUFX4TS U2542 ( .A(n2704), .Y(n2725) );
BUFX3TS U2543 ( .A(n2704), .Y(n2803) );
OAI21XLTS U2544 ( .A0(n2558), .A1(n2629), .B0(n2589), .Y(n2556) );
BUFX4TS U2545 ( .A(n2010), .Y(n2629) );
OAI221X1TS U2546 ( .A0(n3306), .A1(intDY_EWSW[62]), .B0(n3391), .B1(
intDY_EWSW[61]), .C0(n2018), .Y(n2021) );
OAI21XLTS U2547 ( .A0(n3306), .A1(n2589), .B0(n2571), .Y(n1525) );
AOI222X1TS U2548 ( .A0(n2169), .A1(n1804), .B0(n2943), .B1(n2962), .C0(n2942), .C1(n2143), .Y(n3244) );
AOI222X1TS U2549 ( .A0(n2170), .A1(n1804), .B0(n2949), .B1(n2962), .C0(n2948), .C1(n2143), .Y(n3245) );
AOI222X4TS U2550 ( .A0(n2243), .A1(left_right_SHT2), .B0(n2242), .B1(n2143),
.C0(n2241), .C1(n2929), .Y(n2325) );
BUFX4TS U2551 ( .A(n2560), .Y(n2503) );
CLKINVX3TS U2552 ( .A(n3208), .Y(n3187) );
CLKINVX3TS U2553 ( .A(n3208), .Y(n3186) );
BUFX4TS U2554 ( .A(n1887), .Y(n2577) );
BUFX4TS U2555 ( .A(n2549), .Y(n2622) );
AOI222X4TS U2556 ( .A0(n2170), .A1(left_right_SHT2), .B0(n2949), .B1(n2929),
.C0(n2948), .C1(n2960), .Y(n2335) );
AOI222X4TS U2557 ( .A0(n2169), .A1(left_right_SHT2), .B0(n2943), .B1(n2929),
.C0(n2942), .C1(n2960), .Y(n2338) );
AOI222X1TS U2558 ( .A0(n2161), .A1(left_right_SHT2), .B0(n2955), .B1(n2929),
.C0(n2954), .C1(n2960), .Y(n2486) );
AOI222X1TS U2559 ( .A0(n2231), .A1(n3241), .B0(n2963), .B1(n2929), .C0(n2961), .C1(n2960), .Y(n2300) );
BUFX4TS U2560 ( .A(n2112), .Y(n2960) );
NAND2X1TS U2561 ( .A(n3241), .B(n2910), .Y(n3232) );
AOI222X4TS U2562 ( .A0(n2146), .A1(n3241), .B0(n2147), .B1(n2143), .C0(n2148), .C1(n2929), .Y(n2327) );
AOI222X4TS U2563 ( .A0(n2245), .A1(n3241), .B0(n2244), .B1(n2143), .C0(n2869), .C1(n2929), .Y(n2333) );
BUFX3TS U2564 ( .A(n2856), .Y(n2858) );
CLKBUFX3TS U2565 ( .A(n2856), .Y(n2883) );
AOI2BB2X1TS U2566 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[21]), .A0N(n2823),
.A1N(n2822), .Y(n2824) );
OAI211XLTS U2567 ( .A0(n2774), .A1(n2649), .B0(n2773), .C0(n2772), .Y(n1644)
);
BUFX4TS U2568 ( .A(n2815), .Y(n3162) );
BUFX4TS U2569 ( .A(n2815), .Y(n2795) );
INVX2TS U2570 ( .A(n1809), .Y(n1869) );
INVX3TS U2571 ( .A(n3258), .Y(n2336) );
INVX3TS U2572 ( .A(n2962), .Y(n3238) );
INVX3TS U2573 ( .A(n2929), .Y(n2966) );
AOI22X1TS U2574 ( .A0(n2815), .A1(Data_array_SWR[27]), .B0(
Raw_mant_NRM_SWR[17]), .B1(n2771), .Y(n2773) );
INVX3TS U2575 ( .A(n3221), .Y(n3202) );
INVX3TS U2576 ( .A(n3221), .Y(n3200) );
INVX3TS U2577 ( .A(n3221), .Y(n3204) );
OAI2BB2XLTS U2578 ( .B0(n1954), .B1(n3344), .A0N(n1953), .A1N(
Raw_mant_NRM_SWR[6]), .Y(n1955) );
INVX2TS U2579 ( .A(n1830), .Y(n1870) );
INVX2TS U2580 ( .A(n1819), .Y(n1871) );
INVX2TS U2581 ( .A(n1829), .Y(n1872) );
INVX2TS U2582 ( .A(n1831), .Y(n1873) );
INVX2TS U2583 ( .A(n1811), .Y(n1874) );
INVX2TS U2584 ( .A(n1807), .Y(n1875) );
AOI22X2TS U2585 ( .A0(Data_array_SWR[42]), .A1(n2887), .B0(
Data_array_SWR[38]), .B1(n2896), .Y(n3236) );
INVX2TS U2586 ( .A(n1810), .Y(n1876) );
INVX2TS U2587 ( .A(n1806), .Y(n1877) );
INVX2TS U2588 ( .A(n1824), .Y(n1878) );
AOI32X1TS U2589 ( .A0(n3392), .A1(n2414), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n3307), .Y(n2415) );
OAI221XLTS U2590 ( .A0(n3393), .A1(intDY_EWSW[60]), .B0(n3307), .B1(
intDY_EWSW[59]), .C0(n2019), .Y(n2020) );
OAI221XLTS U2591 ( .A0(n1867), .A1(intDX_EWSW[0]), .B0(n3373), .B1(
intDX_EWSW[8]), .C0(n2067), .Y(n2068) );
OAI221X1TS U2592 ( .A0(n3413), .A1(intDX_EWSW[7]), .B0(n3315), .B1(
intDX_EWSW[6]), .C0(n2367), .Y(n2071) );
OAI211X1TS U2593 ( .A0(n2789), .A1(n2826), .B0(n2749), .C0(n2748), .Y(n1627)
);
INVX2TS U2594 ( .A(n1817), .Y(n1879) );
AOI221X1TS U2595 ( .A0(n3422), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n3397), .C0(n2038), .Y(n2041) );
OAI221XLTS U2596 ( .A0(n3368), .A1(intDX_EWSW[9]), .B0(n3382), .B1(
intDX_EWSW[16]), .C0(n2060), .Y(n2061) );
AOI222X1TS U2597 ( .A0(intDX_EWSW[4]), .A1(n3303), .B0(intDX_EWSW[5]), .B1(
n2606), .C0(n2366), .C1(n2365), .Y(n2368) );
OAI221X1TS U2598 ( .A0(n3370), .A1(intDX_EWSW[13]), .B0(n3303), .B1(
intDX_EWSW[4]), .C0(n2058), .Y(n2063) );
INVX2TS U2599 ( .A(n1825), .Y(n1880) );
INVX2TS U2600 ( .A(n1818), .Y(n1881) );
OAI21XLTS U2601 ( .A0(n2484), .A1(n2329), .B0(n2328), .Y(n1048) );
OAI21XLTS U2602 ( .A0(n2484), .A1(n2327), .B0(n2326), .Y(n1038) );
OAI21XLTS U2603 ( .A0(n2484), .A1(n2325), .B0(n2324), .Y(n1037) );
OAI21XLTS U2604 ( .A0(n2484), .A1(n2333), .B0(n2332), .Y(n1036) );
OAI21XLTS U2605 ( .A0(n2919), .A1(n2300), .B0(n2299), .Y(n1031) );
OAI21XLTS U2606 ( .A0(n2919), .A1(n2486), .B0(n2485), .Y(n1030) );
OAI21XLTS U2607 ( .A0(n2919), .A1(n2335), .B0(n2334), .Y(n1029) );
OAI21XLTS U2608 ( .A0(n2919), .A1(n2338), .B0(n2337), .Y(n1028) );
XOR2X1TS U2609 ( .A(n2844), .B(DmP_mant_SFG_SWR[16]), .Y(n2840) );
XOR2X1TS U2610 ( .A(n2844), .B(DmP_mant_SFG_SWR[17]), .Y(n2841) );
XOR2X1TS U2611 ( .A(n2844), .B(DmP_mant_SFG_SWR[18]), .Y(n2845) );
OAI21XLTS U2612 ( .A0(n2484), .A1(n2323), .B0(n2322), .Y(n1050) );
OAI21XLTS U2613 ( .A0(n2484), .A1(n2331), .B0(n2330), .Y(n1049) );
OAI21XLTS U2614 ( .A0(n3389), .A1(n2585), .B0(n2584), .Y(n1201) );
OAI31XLTS U2615 ( .A0(n2559), .A1(n2558), .A2(n2560), .B0(n2557), .Y(n1522)
);
CLKINVX1TS U2616 ( .A(DmP_EXP_EWSW[56]), .Y(n3212) );
BUFX4TS U2617 ( .A(n3146), .Y(n3149) );
NAND2X1TS U2618 ( .A(n1882), .B(n1883), .Y(n2958) );
NAND2X1TS U2619 ( .A(n1808), .B(n2086), .Y(n1882) );
NAND2X1TS U2620 ( .A(n1808), .B(n1823), .Y(n1883) );
OAI211XLTS U2621 ( .A0(n2958), .A1(n2111), .B0(n2187), .C0(n2186), .Y(n2188)
);
XNOR2X2TS U2622 ( .A(DMP_exp_NRM2_EW[10]), .B(n2127), .Y(n3129) );
OAI211XLTS U2623 ( .A0(n2669), .A1(n2822), .B0(n2668), .C0(n2667), .Y(n1615)
);
BUFX4TS U2624 ( .A(n3497), .Y(n3490) );
BUFX4TS U2625 ( .A(n3493), .Y(n3459) );
BUFX4TS U2626 ( .A(n3458), .Y(n3489) );
BUFX3TS U2627 ( .A(n3494), .Y(n3493) );
NAND2X1TS U2628 ( .A(n2847), .B(DMP_SFG[18]), .Y(n3094) );
OAI222X4TS U2629 ( .A0(n3213), .A1(n3428), .B0(n3318), .B1(n3211), .C0(n3284), .C1(n3210), .Y(n1205) );
BUFX4TS U2630 ( .A(n2560), .Y(n3213) );
NOR2X1TS U2631 ( .A(n2840), .B(DMP_SFG[14]), .Y(n3049) );
NAND2X1TS U2632 ( .A(n2840), .B(DMP_SFG[14]), .Y(n3099) );
NOR2X1TS U2633 ( .A(n2845), .B(DMP_SFG[16]), .Y(n3046) );
NAND2X1TS U2634 ( .A(n2845), .B(DMP_SFG[16]), .Y(n3082) );
OAI211XLTS U2635 ( .A0(n2308), .A1(n3219), .B0(n3214), .C0(n2307), .Y(n1598)
);
OAI211XLTS U2636 ( .A0(n2314), .A1(n2318), .B0(n3214), .C0(n2313), .Y(n1595)
);
OAI211XLTS U2637 ( .A0(n2321), .A1(n3278), .B0(n3214), .C0(n2320), .Y(n1597)
);
OAI211XLTS U2638 ( .A0(n2302), .A1(n3219), .B0(n3214), .C0(n2301), .Y(n1591)
);
OAI211XLTS U2639 ( .A0(n2304), .A1(n3136), .B0(n3214), .C0(n2303), .Y(n1594)
);
NAND2X4TS U2640 ( .A(n2126), .B(Shift_reg_FLAGS_7[0]), .Y(n3214) );
OAI211XLTS U2641 ( .A0(n3234), .A1(n2866), .B0(n2865), .C0(n2864), .Y(n2867)
);
AOI22X2TS U2642 ( .A0(Data_array_SWR[44]), .A1(n2887), .B0(
Data_array_SWR[40]), .B1(n2896), .Y(n3234) );
INVX3TS U2643 ( .A(n2220), .Y(n2896) );
BUFX4TS U2644 ( .A(n2897), .Y(n2887) );
BUFX4TS U2645 ( .A(OP_FLAG_SFG), .Y(n2844) );
OAI211XLTS U2646 ( .A0(n2674), .A1(n2822), .B0(n2673), .C0(n2672), .Y(n1618)
);
INVX3TS U2647 ( .A(n2858), .Y(n3224) );
BUFX3TS U2648 ( .A(n2856), .Y(n3185) );
INVX3TS U2649 ( .A(n3218), .Y(n3225) );
AOI22X2TS U2650 ( .A0(Data_array_SWR[39]), .A1(n2905), .B0(
Data_array_SWR[43]), .B1(n2887), .Y(n3231) );
NAND2X2TS U2651 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2907) );
INVX2TS U2652 ( .A(n1884), .Y(n1885) );
NAND2X4TS U2653 ( .A(Shift_reg_FLAGS_7[1]), .B(n2636), .Y(n2837) );
AOI22X2TS U2654 ( .A0(Data_array_SWR[37]), .A1(n2905), .B0(
Data_array_SWR[41]), .B1(n2887), .Y(n3239) );
NOR2X2TS U2655 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3390), .Y(n3130) );
OAI221X1TS U2656 ( .A0(n3392), .A1(intDY_EWSW[58]), .B0(n3389), .B1(
intDX_EWSW[57]), .C0(n2016), .Y(n2023) );
NOR2X2TS U2657 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .Y(
n1901) );
OAI211XLTS U2658 ( .A0(n2767), .A1(n2822), .B0(n2685), .C0(n2684), .Y(n1628)
);
OAI221X1TS U2659 ( .A0(n3301), .A1(intDX_EWSW[3]), .B0(n3372), .B1(
intDX_EWSW[2]), .C0(n2066), .Y(n2069) );
NOR2XLTS U2660 ( .A(n2404), .B(intDX_EWSW[24]), .Y(n2348) );
OAI221X1TS U2661 ( .A0(n3297), .A1(intDX_EWSW[17]), .B0(n3377), .B1(
intDX_EWSW[24]), .C0(n2053), .Y(n2054) );
OAI221X1TS U2662 ( .A0(n3299), .A1(intDX_EWSW[25]), .B0(n3380), .B1(
intDX_EWSW[32]), .C0(n2046), .Y(n2047) );
NOR2XLTS U2663 ( .A(n2372), .B(intDX_EWSW[10]), .Y(n2373) );
OAI221X1TS U2664 ( .A0(n3369), .A1(intDX_EWSW[10]), .B0(n3374), .B1(
intDX_EWSW[12]), .C0(n2059), .Y(n2062) );
NOR2XLTS U2665 ( .A(n2392), .B(intDX_EWSW[16]), .Y(n2393) );
NOR2XLTS U2666 ( .A(n2461), .B(intDX_EWSW[48]), .Y(n2462) );
OAI221X1TS U2667 ( .A0(n3371), .A1(intDX_EWSW[21]), .B0(n3381), .B1(
intDX_EWSW[48]), .C0(n2051), .Y(n2056) );
AOI211X2TS U2668 ( .A0(intDX_EWSW[44]), .A1(n3404), .B0(n2426), .C0(n2435),
.Y(n2433) );
AOI21X2TS U2669 ( .A0(Data_array_SWR[24]), .A1(n2909), .B0(n2181), .Y(n2952)
);
AOI21X2TS U2670 ( .A0(Data_array_SWR[22]), .A1(n2909), .B0(n2908), .Y(n2967)
);
AOI222X1TS U2671 ( .A0(n2555), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n2629), .C0(intDY_EWSW[52]), .C1(n2567), .Y(n2628) );
OAI21XLTS U2672 ( .A0(intDX_EWSW[37]), .A1(n3396), .B0(n2441), .Y(n2450) );
OAI221XLTS U2673 ( .A0(n2606), .A1(intDX_EWSW[5]), .B0(n3379), .B1(
intDX_EWSW[28]), .C0(n2065), .Y(n2070) );
NOR3X6TS U2674 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
n1945), .Y(n1998) );
NAND2X2TS U2675 ( .A(shift_value_SHT2_EWR[4]), .B(n2180), .Y(n2225) );
OAI22X2TS U2676 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2240), .B0(n3407), .B1(
n2225), .Y(n2893) );
INVX2TS U2677 ( .A(Shift_reg_FLAGS_7_6), .Y(n2010) );
OAI21XLTS U2678 ( .A0(intDX_EWSW[1]), .A1(n3421), .B0(intDX_EWSW[0]), .Y(
n2361) );
NOR2XLTS U2679 ( .A(n2131), .B(exp_rslt_NRM2_EW1[1]), .Y(n2116) );
NOR2XLTS U2680 ( .A(n2426), .B(intDX_EWSW[44]), .Y(n2427) );
NOR2XLTS U2681 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n1964) );
OAI21XLTS U2682 ( .A0(intDY_EWSW[29]), .A1(n3342), .B0(intDY_EWSW[28]), .Y(
n2346) );
XOR2X1TS U2683 ( .A(n2844), .B(DmP_mant_SFG_SWR[19]), .Y(n2846) );
INVX2TS U2684 ( .A(n3085), .Y(n3087) );
OAI211XLTS U2685 ( .A0(n2946), .A1(n2939), .B0(n2192), .C0(n2191), .Y(n2193)
);
OR2X1TS U2686 ( .A(n3431), .B(n2844), .Y(n2258) );
OR2X1TS U2687 ( .A(n2847), .B(DMP_SFG[18]), .Y(n3095) );
OAI21XLTS U2688 ( .A0(DmP_EXP_EWSW[53]), .A1(n3316), .B0(n3168), .Y(n3166)
);
OAI211XLTS U2689 ( .A0(n2312), .A1(n2318), .B0(n3214), .C0(n2311), .Y(n1589)
);
OAI211XLTS U2690 ( .A0(DmP_mant_SFG_SWR[11]), .A1(n2277), .B0(n2250), .C0(
n2249), .Y(n1116) );
OAI211XLTS U2691 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n2277), .B0(n2268), .C0(
n2267), .Y(n1112) );
OAI21XLTS U2692 ( .A0(n2284), .A1(n2919), .B0(n2283), .Y(n1053) );
OAI211XLTS U2693 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n2277), .B0(n2264), .C0(
n2263), .Y(n1123) );
OAI21XLTS U2694 ( .A0(n3301), .A1(n2589), .B0(n2563), .Y(n1304) );
OAI21XLTS U2695 ( .A0(n3398), .A1(n2503), .B0(n2499), .Y(n1542) );
OAI21XLTS U2696 ( .A0(n3314), .A1(n2552), .B0(n2534), .Y(n1556) );
OAI21XLTS U2697 ( .A0(n3297), .A1(n2503), .B0(n2494), .Y(n1570) );
OAI21XLTS U2698 ( .A0(n3301), .A1(n2605), .B0(n2540), .Y(n1584) );
OAI211XLTS U2699 ( .A0(n2665), .A1(n2822), .B0(n2664), .C0(n2663), .Y(n1614)
);
INVX2TS U2700 ( .A(n3505), .Y(n3189) );
BUFX3TS U2701 ( .A(n3189), .Y(n3194) );
INVX4TS U2702 ( .A(n3194), .Y(n3223) );
BUFX3TS U2703 ( .A(n2659), .Y(n2815) );
NOR2X2TS U2704 ( .A(Shift_reg_FLAGS_7[1]), .B(n3189), .Y(n3161) );
AOI22X1TS U2705 ( .A0(n2659), .A1(shift_value_SHT2_EWR[5]), .B0(n3161), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1906) );
NOR3X2TS U2706 ( .A(Raw_mant_NRM_SWR[44]), .B(Raw_mant_NRM_SWR[46]), .C(
Raw_mant_NRM_SWR[45]), .Y(n3110) );
NOR2X2TS U2707 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(
n1963) );
NOR2X2TS U2708 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n1966) );
NAND2X2TS U2709 ( .A(n1963), .B(n1966), .Y(n1931) );
NOR2BX4TS U2710 ( .AN(n1987), .B(Raw_mant_NRM_SWR[42]), .Y(n1938) );
NOR2BX4TS U2711 ( .AN(n1934), .B(Raw_mant_NRM_SWR[34]), .Y(n1918) );
NAND2BX4TS U2712 ( .AN(Raw_mant_NRM_SWR[33]), .B(n1918), .Y(n1943) );
NAND2BX4TS U2713 ( .AN(Raw_mant_NRM_SWR[30]), .B(n1907), .Y(n1942) );
NAND2X4TS U2714 ( .A(n1909), .B(n3324), .Y(n3113) );
NOR2BX4TS U2715 ( .AN(n1919), .B(Raw_mant_NRM_SWR[25]), .Y(n3112) );
NOR2BX4TS U2716 ( .AN(n3112), .B(Raw_mant_NRM_SWR[24]), .Y(n1986) );
NOR3BX4TS U2717 ( .AN(n1986), .B(Raw_mant_NRM_SWR[23]), .C(
Raw_mant_NRM_SWR[22]), .Y(n1923) );
NAND2BX4TS U2718 ( .AN(Raw_mant_NRM_SWR[13]), .B(n1899), .Y(n1956) );
NOR2X6TS U2719 ( .A(Raw_mant_NRM_SWR[12]), .B(n1956), .Y(n1952) );
NAND2BX4TS U2720 ( .AN(Raw_mant_NRM_SWR[9]), .B(n1981), .Y(n3115) );
NOR2X1TS U2721 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n1898)
);
NAND2X4TS U2722 ( .A(n1953), .B(n1898), .Y(n1954) );
AOI32X1TS U2723 ( .A0(n1994), .A1(n3286), .A2(n3358), .B0(n1956), .B1(n1994),
.Y(n1891) );
INVX2TS U2724 ( .A(n1891), .Y(n1894) );
INVX2TS U2725 ( .A(n3115), .Y(n1892) );
AOI22X1TS U2726 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1981), .B0(
Raw_mant_NRM_SWR[10]), .B1(n1952), .Y(n1897) );
AOI32X1TS U2727 ( .A0(n1898), .A1(n1897), .A2(n3362), .B0(n1896), .B1(n1897),
.Y(n1904) );
NAND2X1TS U2728 ( .A(Raw_mant_NRM_SWR[13]), .B(n1899), .Y(n1948) );
OAI31X1TS U2729 ( .A0(n1910), .A1(n1975), .A2(n1905), .B0(
Shift_reg_FLAGS_7[1]), .Y(n3108) );
NAND2X1TS U2730 ( .A(n1906), .B(n3108), .Y(n1605) );
BUFX3TS U2731 ( .A(n2815), .Y(n2821) );
AOI22X1TS U2732 ( .A0(n2821), .A1(shift_value_SHT2_EWR[4]), .B0(n3161), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1928) );
OAI2BB1X1TS U2733 ( .A0N(n1907), .A1N(Raw_mant_NRM_SWR[30]), .B0(n1937), .Y(
n3118) );
OR2X1TS U2734 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .Y(n1908) );
AOI22X1TS U2735 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n1909), .B0(n1935), .B1(
n1908), .Y(n1915) );
OAI31X1TS U2736 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1910), .A2(
Raw_mant_NRM_SWR[24]), .B0(n3112), .Y(n1914) );
INVX2TS U2737 ( .A(n1945), .Y(n1929) );
OAI21X1TS U2738 ( .A0(Raw_mant_NRM_SWR[19]), .A1(Raw_mant_NRM_SWR[20]), .B0(
n1929), .Y(n3120) );
OAI21X1TS U2739 ( .A0(Raw_mant_NRM_SWR[35]), .A1(Raw_mant_NRM_SWR[36]), .B0(
n1912), .Y(n1913) );
NAND4X2TS U2740 ( .A(n1915), .B(n1914), .C(n3120), .D(n1913), .Y(n1976) );
NOR2XLTS U2741 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[1]), .Y(n1926)
);
NOR2X1TS U2742 ( .A(Raw_mant_NRM_SWR[40]), .B(n1875), .Y(n1988) );
INVX2TS U2743 ( .A(n1988), .Y(n1972) );
NAND2X1TS U2744 ( .A(n1917), .B(Raw_mant_NRM_SWR[28]), .Y(n1980) );
OAI31X1TS U2745 ( .A0(n1916), .A1(n1961), .A2(n1972), .B0(n1980), .Y(n1921)
);
AOI22X1TS U2746 ( .A0(Raw_mant_NRM_SWR[33]), .A1(n1918), .B0(n1917), .B1(
Raw_mant_NRM_SWR[29]), .Y(n1944) );
NAND2X1TS U2747 ( .A(Raw_mant_NRM_SWR[25]), .B(n1919), .Y(n1982) );
OAI211XLTS U2748 ( .A0(n3419), .A1(n1942), .B0(n1944), .C0(n1982), .Y(n1920)
);
AOI211X1TS U2749 ( .A0(n1922), .A1(Raw_mant_NRM_SWR[34]), .B0(n1921), .C0(
n1920), .Y(n1924) );
NAND2X1TS U2750 ( .A(Raw_mant_NRM_SWR[21]), .B(n1923), .Y(n1940) );
OAI211X1TS U2751 ( .A0(n1926), .A1(n1925), .B0(n1924), .C0(n1940), .Y(n1927)
);
OAI31X1TS U2752 ( .A0(n3118), .A1(n1976), .A2(n1927), .B0(
Shift_reg_FLAGS_7[1]), .Y(n3109) );
NAND2X1TS U2753 ( .A(n1928), .B(n3109), .Y(n1607) );
AOI22X1TS U2754 ( .A0(n2821), .A1(shift_value_SHT2_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n3161), .Y(n1960) );
OAI2BB2XLTS U2755 ( .B0(n1930), .B1(n3427), .A0N(Raw_mant_NRM_SWR[20]),
.A1N(n1929), .Y(n1959) );
OAI211XLTS U2756 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1937), .B0(n1936), .C0(
n1980), .Y(n1958) );
AOI32X1TS U2757 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1953), .A2(n3344), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1953), .Y(n1941) );
AOI32X1TS U2758 ( .A0(n1875), .A1(n1938), .A2(n3363), .B0(n1849), .B1(n1938),
.Y(n1939) );
OAI211X1TS U2759 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1941), .B0(n1940), .C0(
n1939), .Y(n3126) );
OR2X1TS U2760 ( .A(Raw_mant_NRM_SWR[28]), .B(n1942), .Y(n1950) );
NOR3BX1TS U2761 ( .AN(Raw_mant_NRM_SWR[31]), .B(Raw_mant_NRM_SWR[32]), .C(
n1943), .Y(n1947) );
OAI31X1TS U2762 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n3355), .A2(n1945), .B0(
n1944), .Y(n1946) );
AOI211X1TS U2763 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n3111), .B0(n1947), .C0(
n1946), .Y(n1949) );
AOI211X4TS U2764 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1952), .B0(n3126), .C0(
n1951), .Y(n2001) );
OAI31X1TS U2765 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n1955), .A2(
Raw_mant_NRM_SWR[40]), .B0(n1987), .Y(n3122) );
OAI31X1TS U2766 ( .A0(n1959), .A1(n1958), .A2(n1957), .B0(
Shift_reg_FLAGS_7[1]), .Y(n3127) );
NAND2X1TS U2767 ( .A(n1960), .B(n3127), .Y(n1609) );
INVX4TS U2768 ( .A(Shift_reg_FLAGS_7[1]), .Y(n3137) );
NAND2X1TS U2769 ( .A(Raw_mant_NRM_SWR[43]), .B(n1962), .Y(n1983) );
INVX2TS U2770 ( .A(n1983), .Y(n1971) );
AOI211X1TS U2771 ( .A0(n1964), .A1(Raw_mant_NRM_SWR[44]), .B0(
Raw_mant_NRM_SWR[47]), .C0(Raw_mant_NRM_SWR[48]), .Y(n1968) );
OAI32X1TS U2772 ( .A0(n1969), .A1(n1968), .A2(n1967), .B0(n1966), .B1(n1969),
.Y(n1970) );
AOI211X1TS U2773 ( .A0(n1973), .A1(n1972), .B0(n1971), .C0(n1970), .Y(n1979)
);
AOI211X2TS U2774 ( .A0(n1977), .A1(Raw_mant_NRM_SWR[16]), .B0(n1976), .C0(
n1975), .Y(n1978) );
OAI211X4TS U2775 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n1980), .B0(n1979), .C0(
n1978), .Y(n2636) );
OAI2BB1X4TS U2776 ( .A0N(Shift_amount_SHT1_EWR[1]), .A1N(n3137), .B0(n2837),
.Y(n2631) );
NOR2BX4TS U2777 ( .AN(n2631), .B(n2795), .Y(n2807) );
AOI21X1TS U2778 ( .A0(n1986), .A1(Raw_mant_NRM_SWR[23]), .B0(n1985), .Y(
n3123) );
AOI21X1TS U2779 ( .A0(n3367), .A1(Raw_mant_NRM_SWR[49]), .B0(
Raw_mant_NRM_SWR[51]), .Y(n1989) );
OAI22X1TS U2780 ( .A0(n1992), .A1(n1991), .B0(Raw_mant_NRM_SWR[54]), .B1(
n1990), .Y(n1993) );
NAND2X1TS U2781 ( .A(n1859), .B(n3137), .Y(n2734) );
AOI22X1TS U2782 ( .A0(n2810), .A1(Raw_mant_NRM_SWR[51]), .B0(n2704), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2005) );
BUFX4TS U2783 ( .A(n2639), .Y(n2752) );
OR2X2TS U2784 ( .A(Shift_reg_FLAGS_7[1]), .B(n1859), .Y(n2736) );
INVX4TS U2785 ( .A(n2736), .Y(n2750) );
AOI22X1TS U2786 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[52]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2004) );
NAND2X1TS U2787 ( .A(n2005), .B(n2004), .Y(n2650) );
AOI22X1TS U2788 ( .A0(n3162), .A1(Data_array_SWR[0]), .B0(n2807), .B1(n2650),
.Y(n2007) );
OR2X2TS U2789 ( .A(n2636), .B(n3128), .Y(n2730) );
INVX4TS U2790 ( .A(n2730), .Y(n2720) );
AOI22X1TS U2791 ( .A0(n2720), .A1(Raw_mant_NRM_SWR[53]), .B0(n2752), .B1(
Raw_mant_NRM_SWR[54]), .Y(n2006) );
NAND2X1TS U2792 ( .A(n2007), .B(n2006), .Y(n1610) );
BUFX3TS U2793 ( .A(n3494), .Y(n3496) );
BUFX3TS U2794 ( .A(n3493), .Y(n3467) );
BUFX3TS U2795 ( .A(n3497), .Y(n3466) );
CLKBUFX2TS U2796 ( .A(n3457), .Y(n3497) );
BUFX3TS U2797 ( .A(n3458), .Y(n3464) );
BUFX3TS U2798 ( .A(n3493), .Y(n3463) );
BUFX3TS U2799 ( .A(n2008), .Y(n3471) );
BUFX3TS U2800 ( .A(n3497), .Y(n3495) );
BUFX3TS U2801 ( .A(n2009), .Y(n3469) );
BUFX3TS U2802 ( .A(n3460), .Y(n3452) );
BUFX3TS U2803 ( .A(n3494), .Y(n3458) );
BUFX3TS U2804 ( .A(n3458), .Y(n3488) );
BUFX3TS U2805 ( .A(n3477), .Y(n3500) );
BUFX3TS U2806 ( .A(n2009), .Y(n3482) );
BUFX3TS U2807 ( .A(n2009), .Y(n3481) );
BUFX3TS U2808 ( .A(n3494), .Y(n3480) );
BUFX3TS U2809 ( .A(n3468), .Y(n3475) );
BUFX3TS U2810 ( .A(n3470), .Y(n3474) );
BUFX3TS U2811 ( .A(n3504), .Y(n3486) );
BUFX3TS U2812 ( .A(n3499), .Y(n3451) );
BUFX3TS U2813 ( .A(n2009), .Y(n3492) );
BUFX3TS U2814 ( .A(n2008), .Y(n3484) );
BUFX3TS U2815 ( .A(n3495), .Y(n3476) );
BUFX3TS U2816 ( .A(n3504), .Y(n3479) );
AO22XLTS U2817 ( .A0(n1885), .A1(SIGN_FLAG_NRM), .B0(n3137), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1185) );
AO22XLTS U2818 ( .A0(n1885), .A1(ZERO_FLAG_NRM), .B0(n3137), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1194) );
CLKXOR2X2TS U2819 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n2554) );
OAI21XLTS U2820 ( .A0(n2554), .A1(intDX_EWSW[63]), .B0(n3211), .Y(n2011) );
AOI21X1TS U2821 ( .A0(n2554), .A1(intDX_EWSW[63]), .B0(n2011), .Y(n2080) );
AO21XLTS U2822 ( .A0(OP_FLAG_EXP), .A1(n2629), .B0(n2080), .Y(n1524) );
INVX4TS U2823 ( .A(n3194), .Y(busy) );
AOI22X1TS U2824 ( .A0(n3305), .A1(intDX_EWSW[11]), .B0(n3388), .B1(
intDX_EWSW[50]), .Y(n2012) );
OAI221XLTS U2825 ( .A0(n3305), .A1(intDX_EWSW[11]), .B0(n3388), .B1(
intDX_EWSW[50]), .C0(n2012), .Y(n2013) );
AOI221X1TS U2826 ( .A0(intDY_EWSW[49]), .A1(n3414), .B0(n3409), .B1(
intDX_EWSW[49]), .C0(n2013), .Y(n2027) );
OAI22X1TS U2827 ( .A0(n3284), .A1(intDX_EWSW[53]), .B0(n3282), .B1(
intDX_EWSW[54]), .Y(n2014) );
AOI221X1TS U2828 ( .A0(n3284), .A1(intDX_EWSW[53]), .B0(intDX_EWSW[54]),
.B1(n3282), .C0(n2014), .Y(n2026) );
OAI22X1TS U2829 ( .A0(n3406), .A1(intDX_EWSW[51]), .B0(n3415), .B1(
intDX_EWSW[52]), .Y(n2015) );
AOI221X1TS U2830 ( .A0(n3406), .A1(intDX_EWSW[51]), .B0(intDX_EWSW[52]),
.B1(n3415), .C0(n2015), .Y(n2025) );
AOI22X1TS U2831 ( .A0(n3392), .A1(intDY_EWSW[58]), .B0(n3389), .B1(
intDX_EWSW[57]), .Y(n2016) );
AOI22X1TS U2832 ( .A0(n3281), .A1(intDX_EWSW[56]), .B0(n3283), .B1(
intDX_EWSW[55]), .Y(n2017) );
OAI221XLTS U2833 ( .A0(n3281), .A1(intDX_EWSW[56]), .B0(n3283), .B1(
intDX_EWSW[55]), .C0(n2017), .Y(n2022) );
AOI22X1TS U2834 ( .A0(n3306), .A1(intDY_EWSW[62]), .B0(n3391), .B1(
intDY_EWSW[61]), .Y(n2018) );
AOI22X1TS U2835 ( .A0(n3393), .A1(intDY_EWSW[60]), .B0(n3307), .B1(
intDY_EWSW[59]), .Y(n2019) );
NOR4X1TS U2836 ( .A(n2023), .B(n2022), .C(n2021), .D(n2020), .Y(n2024) );
NAND4XLTS U2837 ( .A(n2027), .B(n2026), .C(n2025), .D(n2024), .Y(n2079) );
OAI22X1TS U2838 ( .A0(n3403), .A1(intDX_EWSW[42]), .B0(n3311), .B1(
intDX_EWSW[43]), .Y(n2028) );
AOI221X1TS U2839 ( .A0(n3403), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n3311), .C0(n2028), .Y(n2035) );
OAI22X1TS U2840 ( .A0(n3402), .A1(intDX_EWSW[40]), .B0(n3310), .B1(
intDX_EWSW[41]), .Y(n2029) );
AOI221X1TS U2841 ( .A0(n3402), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n3310), .C0(n2029), .Y(n2034) );
OAI22X1TS U2842 ( .A0(n3405), .A1(intDX_EWSW[46]), .B0(n3308), .B1(
intDX_EWSW[47]), .Y(n2030) );
AOI221X1TS U2843 ( .A0(n3405), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n3308), .C0(n2030), .Y(n2033) );
OAI22X1TS U2844 ( .A0(n3404), .A1(intDX_EWSW[44]), .B0(n3398), .B1(
intDX_EWSW[45]), .Y(n2031) );
AOI221X1TS U2845 ( .A0(n3404), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n3398), .C0(n2031), .Y(n2032) );
NAND4XLTS U2846 ( .A(n2035), .B(n2034), .C(n2033), .D(n2032), .Y(n2078) );
OAI22X1TS U2847 ( .A0(n3400), .A1(intDX_EWSW[34]), .B0(n3309), .B1(
intDX_EWSW[35]), .Y(n2036) );
AOI221X1TS U2848 ( .A0(n3400), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n3309), .C0(n2036), .Y(n2043) );
OAI22X1TS U2849 ( .A0(n3421), .A1(intDX_EWSW[1]), .B0(n3399), .B1(
intDX_EWSW[33]), .Y(n2037) );
AOI221X1TS U2850 ( .A0(n3421), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[33]), .B1(
n3399), .C0(n2037), .Y(n2042) );
OAI22X1TS U2851 ( .A0(n3422), .A1(intDX_EWSW[38]), .B0(n3397), .B1(
intDX_EWSW[39]), .Y(n2038) );
OAI22X1TS U2852 ( .A0(n3401), .A1(intDX_EWSW[36]), .B0(n3396), .B1(
intDX_EWSW[37]), .Y(n2039) );
AOI221X1TS U2853 ( .A0(n3401), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n3396), .C0(n2039), .Y(n2040) );
NAND4XLTS U2854 ( .A(n2043), .B(n2042), .C(n2041), .D(n2040), .Y(n2077) );
OA22X1TS U2855 ( .A0(n3338), .A1(intDY_EWSW[30]), .B0(n3290), .B1(
intDY_EWSW[31]), .Y(n2356) );
OAI221XLTS U2856 ( .A0(n3314), .A1(intDX_EWSW[31]), .B0(n3412), .B1(
intDX_EWSW[30]), .C0(n2356), .Y(n2050) );
AOI22X1TS U2857 ( .A0(n3302), .A1(intDX_EWSW[29]), .B0(n3376), .B1(
intDX_EWSW[20]), .Y(n2044) );
OAI221XLTS U2858 ( .A0(n3302), .A1(intDX_EWSW[29]), .B0(n3376), .B1(
intDX_EWSW[20]), .C0(n2044), .Y(n2049) );
AOI22X1TS U2859 ( .A0(n3300), .A1(intDX_EWSW[27]), .B0(n3378), .B1(
intDX_EWSW[26]), .Y(n2045) );
AOI22X1TS U2860 ( .A0(n3299), .A1(intDX_EWSW[25]), .B0(n3380), .B1(
intDX_EWSW[32]), .Y(n2046) );
NOR4X1TS U2861 ( .A(n2047), .B(n2049), .C(n2048), .D(n2050), .Y(n2075) );
OA22X1TS U2862 ( .A0(n3339), .A1(intDY_EWSW[22]), .B0(n3291), .B1(
intDY_EWSW[23]), .Y(n2403) );
OAI221XLTS U2863 ( .A0(n3313), .A1(intDX_EWSW[23]), .B0(n3411), .B1(
intDX_EWSW[22]), .C0(n2403), .Y(n2057) );
AOI22X1TS U2864 ( .A0(n3371), .A1(intDX_EWSW[21]), .B0(n3381), .B1(
intDX_EWSW[48]), .Y(n2051) );
AOI22X1TS U2865 ( .A0(n3298), .A1(intDX_EWSW[19]), .B0(n3375), .B1(
intDX_EWSW[18]), .Y(n2052) );
OAI221XLTS U2866 ( .A0(n3298), .A1(intDX_EWSW[19]), .B0(n3375), .B1(
intDX_EWSW[18]), .C0(n2052), .Y(n2055) );
AOI22X1TS U2867 ( .A0(n3297), .A1(intDX_EWSW[17]), .B0(n3377), .B1(
intDX_EWSW[24]), .Y(n2053) );
NOR4X1TS U2868 ( .A(n2056), .B(n2057), .C(n2054), .D(n2055), .Y(n2074) );
OA22X1TS U2869 ( .A0(n3328), .A1(intDY_EWSW[14]), .B0(n3287), .B1(
intDY_EWSW[15]), .Y(n2384) );
OAI221XLTS U2870 ( .A0(n3312), .A1(intDX_EWSW[15]), .B0(n3410), .B1(
intDX_EWSW[14]), .C0(n2384), .Y(n2064) );
AOI22X1TS U2871 ( .A0(n3370), .A1(intDX_EWSW[13]), .B0(n3303), .B1(
intDX_EWSW[4]), .Y(n2058) );
AOI22X1TS U2872 ( .A0(n3369), .A1(intDX_EWSW[10]), .B0(n3374), .B1(
intDX_EWSW[12]), .Y(n2059) );
AOI22X1TS U2873 ( .A0(n3368), .A1(intDX_EWSW[9]), .B0(n3382), .B1(
intDX_EWSW[16]), .Y(n2060) );
NOR4X1TS U2874 ( .A(n2063), .B(n2064), .C(n2062), .D(n2061), .Y(n2073) );
INVX2TS U2875 ( .A(intDY_EWSW[7]), .Y(n2582) );
AOI22X1TS U2876 ( .A0(intDX_EWSW[7]), .A1(n2582), .B0(intDX_EWSW[6]), .B1(
n3315), .Y(n2367) );
INVX2TS U2877 ( .A(intDY_EWSW[5]), .Y(n2606) );
AOI22X1TS U2878 ( .A0(n3387), .A1(intDX_EWSW[5]), .B0(n3379), .B1(
intDX_EWSW[28]), .Y(n2065) );
AOI22X1TS U2879 ( .A0(n3301), .A1(intDX_EWSW[3]), .B0(n3372), .B1(
intDX_EWSW[2]), .Y(n2066) );
AOI22X1TS U2880 ( .A0(n1820), .A1(intDX_EWSW[0]), .B0(n3373), .B1(
intDX_EWSW[8]), .Y(n2067) );
NOR4X1TS U2881 ( .A(n2071), .B(n2070), .C(n2069), .D(n2068), .Y(n2072) );
NAND4XLTS U2882 ( .A(n2075), .B(n2074), .C(n2073), .D(n2072), .Y(n2076) );
NOR4X1TS U2883 ( .A(n2079), .B(n2078), .C(n2077), .D(n2076), .Y(n2559) );
AO22XLTS U2884 ( .A0(n2559), .A1(n2080), .B0(ZERO_FLAG_EXP), .B1(n2629), .Y(
n1523) );
AOI22X1TS U2885 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n3130), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n3304), .Y(n3133) );
CLKBUFX2TS U2886 ( .A(n3140), .Y(n3139) );
INVX4TS U2887 ( .A(n3139), .Y(n3141) );
AO22XLTS U2888 ( .A0(n3152), .A1(Data_X[23]), .B0(n3141), .B1(intDX_EWSW[23]), .Y(n1771) );
INVX4TS U2889 ( .A(n3139), .Y(n3142) );
AO22XLTS U2890 ( .A0(n3152), .A1(Data_X[15]), .B0(n3142), .B1(intDX_EWSW[15]), .Y(n1779) );
AO22XLTS U2891 ( .A0(n3152), .A1(Data_X[19]), .B0(n3141), .B1(intDX_EWSW[19]), .Y(n1775) );
AO22XLTS U2892 ( .A0(n3152), .A1(Data_X[17]), .B0(n3142), .B1(intDX_EWSW[17]), .Y(n1777) );
AO22XLTS U2893 ( .A0(n3152), .A1(Data_X[18]), .B0(n3141), .B1(intDX_EWSW[18]), .Y(n1776) );
AO22XLTS U2894 ( .A0(n3152), .A1(Data_X[22]), .B0(n3141), .B1(intDX_EWSW[22]), .Y(n1772) );
AO22XLTS U2895 ( .A0(n3152), .A1(Data_X[20]), .B0(n3141), .B1(intDX_EWSW[20]), .Y(n1774) );
AO22XLTS U2896 ( .A0(n3139), .A1(Data_X[14]), .B0(n3142), .B1(intDX_EWSW[14]), .Y(n1780) );
AO22XLTS U2897 ( .A0(n3152), .A1(Data_X[21]), .B0(n3141), .B1(intDX_EWSW[21]), .Y(n1773) );
INVX4TS U2898 ( .A(n3140), .Y(n3157) );
AO22XLTS U2899 ( .A0(n3157), .A1(intDY_EWSW[41]), .B0(n3153), .B1(Data_Y[41]), .Y(n1687) );
CLKBUFX2TS U2900 ( .A(n3140), .Y(n3158) );
INVX4TS U2901 ( .A(n3158), .Y(n3159) );
AO22XLTS U2902 ( .A0(n3158), .A1(Data_Y[61]), .B0(n3159), .B1(intDY_EWSW[61]), .Y(n1667) );
NOR2X1TS U2903 ( .A(n1886), .B(Shift_reg_FLAGS_7[0]), .Y(n2857) );
BUFX3TS U2904 ( .A(n2857), .Y(n2856) );
NOR2XLTS U2905 ( .A(shift_value_SHT2_EWR[4]), .B(n3332), .Y(n2081) );
BUFX3TS U2906 ( .A(n2081), .Y(n2914) );
NOR2X1TS U2907 ( .A(shift_value_SHT2_EWR[2]), .B(n3345), .Y(n2162) );
INVX2TS U2908 ( .A(n2162), .Y(n2172) );
INVX4TS U2909 ( .A(n2172), .Y(n2884) );
AOI22X1TS U2910 ( .A0(n1876), .A1(n2103), .B0(n1877), .B1(n2884), .Y(n2083)
);
NAND2X1TS U2911 ( .A(n3345), .B(shift_value_SHT2_EWR[2]), .Y(n2086) );
INVX2TS U2912 ( .A(n2220), .Y(n2180) );
AOI22X1TS U2913 ( .A0(Data_array_SWR[30]), .A1(n2887), .B0(
Data_array_SWR[26]), .B1(n2180), .Y(n2082) );
NAND2X1TS U2914 ( .A(n2083), .B(n2082), .Y(n2241) );
INVX4TS U2915 ( .A(n2172), .Y(n2904) );
AOI22X1TS U2916 ( .A0(n1880), .A1(n2904), .B0(Data_array_SWR[24]), .B1(n2103), .Y(n2085) );
AOI22X1TS U2917 ( .A0(Data_array_SWR[17]), .A1(n2887), .B0(n1869), .B1(n2896), .Y(n2084) );
BUFX3TS U2918 ( .A(n2111), .Y(n2939) );
AOI21X1TS U2919 ( .A0(n2085), .A1(n2084), .B0(n2939), .Y(n2090) );
INVX4TS U2920 ( .A(n2220), .Y(n2905) );
NAND2X1TS U2921 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n2866) );
NAND2BX2TS U2922 ( .AN(shift_value_SHT2_EWR[4]), .B(n3332), .Y(n2144) );
NOR2X1TS U2923 ( .A(n2907), .B(n2144), .Y(n2097) );
BUFX3TS U2924 ( .A(n2097), .Y(n2895) );
NOR2X1TS U2925 ( .A(n2220), .B(n2144), .Y(n2091) );
BUFX3TS U2926 ( .A(n2091), .Y(n2933) );
AOI22X1TS U2927 ( .A0(Data_array_SWR[11]), .A1(n2895), .B0(Data_array_SWR[1]), .B1(n2933), .Y(n2088) );
NOR2X1TS U2928 ( .A(n2172), .B(n2144), .Y(n2107) );
BUFX3TS U2929 ( .A(n2107), .Y(n2934) );
AOI22X1TS U2930 ( .A0(Data_array_SWR[7]), .A1(n2934), .B0(Data_array_SWR[4]),
.B1(n2106), .Y(n2087) );
AOI211X1TS U2931 ( .A0(n2914), .A1(n2241), .B0(n2090), .C0(n2089), .Y(n2861)
);
BUFX3TS U2932 ( .A(n2091), .Y(n2910) );
OAI22X1TS U2933 ( .A0(left_right_SHT2), .A1(n2861), .B0(n3407), .B1(n3232),
.Y(n2092) );
AO22XLTS U2934 ( .A0(n3198), .A1(n2092), .B0(n3224), .B1(n1861), .Y(n1140)
);
BUFX3TS U2935 ( .A(n2856), .Y(n3198) );
AOI22X1TS U2936 ( .A0(Data_array_SWR[35]), .A1(n2103), .B0(
Data_array_SWR[33]), .B1(n2884), .Y(n2094) );
AOI22X1TS U2937 ( .A0(n1879), .A1(n2905), .B0(Data_array_SWR[29]), .B1(n2887), .Y(n2093) );
NAND2X1TS U2938 ( .A(n2094), .B(n2093), .Y(n2148) );
AOI22X1TS U2939 ( .A0(Data_array_SWR[23]), .A1(n2103), .B0(
Data_array_SWR[20]), .B1(n2884), .Y(n2096) );
AOI22X1TS U2940 ( .A0(n1871), .A1(n2905), .B0(Data_array_SWR[16]), .B1(n2887), .Y(n2095) );
AOI21X1TS U2941 ( .A0(n2096), .A1(n2095), .B0(n2939), .Y(n2101) );
BUFX3TS U2942 ( .A(n2097), .Y(n2936) );
AOI22X1TS U2943 ( .A0(Data_array_SWR[10]), .A1(n2936), .B0(Data_array_SWR[0]), .B1(n2910), .Y(n2099) );
AOI22X1TS U2944 ( .A0(Data_array_SWR[6]), .A1(n2934), .B0(n1865), .B1(n2106),
.Y(n2098) );
AOI211X1TS U2945 ( .A0(n2914), .A1(n2148), .B0(n2101), .C0(n2100), .Y(n2859)
);
OAI22X1TS U2946 ( .A0(left_right_SHT2), .A1(n2859), .B0(n3408), .B1(n3232),
.Y(n2102) );
AO22XLTS U2947 ( .A0(n3258), .A1(n2102), .B0(n3224), .B1(n1860), .Y(n1137)
);
BUFX3TS U2948 ( .A(n2897), .Y(n2909) );
BUFX3TS U2949 ( .A(n2103), .Y(n2885) );
AOI22X1TS U2950 ( .A0(Data_array_SWR[40]), .A1(n2885), .B0(
Data_array_SWR[36]), .B1(n2884), .Y(n2104) );
AOI21X1TS U2951 ( .A0(Data_array_SWR[34]), .A1(n2909), .B0(n2105), .Y(n2152)
);
BUFX3TS U2952 ( .A(n2106), .Y(n2935) );
AOI22X1TS U2953 ( .A0(Data_array_SWR[21]), .A1(n2935), .B0(
Data_array_SWR[18]), .B1(n2933), .Y(n2110) );
NAND2X1TS U2954 ( .A(n2180), .B(n2914), .Y(n2236) );
CLKBUFX3TS U2955 ( .A(n2107), .Y(n2886) );
OAI2BB2XLTS U2956 ( .B0(n3408), .B1(n2236), .A0N(n1881), .A1N(n2886), .Y(
n2108) );
AOI21X1TS U2957 ( .A0(Data_array_SWR[27]), .A1(n2895), .B0(n2108), .Y(n2109)
);
OAI211X1TS U2958 ( .A0(n2152), .A1(n2939), .B0(n2110), .C0(n2109), .Y(n2146)
);
INVX2TS U2959 ( .A(n3236), .Y(n2147) );
BUFX3TS U2960 ( .A(n2113), .Y(n2962) );
AOI222X1TS U2961 ( .A0(n2146), .A1(n1804), .B0(n2147), .B1(n2960), .C0(n2148), .C1(n2962), .Y(n2329) );
INVX2TS U2962 ( .A(DP_OP_15J9_123_7955_n6), .Y(n2114) );
INVX2TS U2963 ( .A(n2118), .Y(n2115) );
XNOR2X1TS U2964 ( .A(DMP_exp_NRM2_EW[8]), .B(n2120), .Y(n2130) );
XNOR2X1TS U2965 ( .A(DMP_exp_NRM2_EW[0]), .B(n2835), .Y(n2131) );
INVX2TS U2966 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n2314) );
INVX2TS U2967 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n2319) );
CLKXOR2X2TS U2968 ( .A(DMP_exp_NRM2_EW[7]), .B(n2118), .Y(n2302) );
XNOR2X1TS U2969 ( .A(DMP_exp_NRM2_EW[6]), .B(DP_OP_15J9_123_7955_n6), .Y(
n2133) );
INVX2TS U2970 ( .A(n2133), .Y(n2306) );
INVX2TS U2971 ( .A(n2120), .Y(n2121) );
XNOR2X1TS U2972 ( .A(DMP_exp_NRM2_EW[9]), .B(n2123), .Y(n2129) );
INVX2TS U2973 ( .A(n2123), .Y(n2124) );
NAND2X1TS U2974 ( .A(n3420), .B(n2124), .Y(n2127) );
INVX2TS U2975 ( .A(n2129), .Y(n2312) );
INVX2TS U2976 ( .A(n2130), .Y(n2316) );
INVX2TS U2977 ( .A(n2131), .Y(n2308) );
INVX2TS U2978 ( .A(exp_rslt_NRM2_EW1[1]), .Y(n2321) );
NOR4X1TS U2979 ( .A(n2314), .B(n2319), .C(n2308), .D(n2321), .Y(n2132) );
NOR4X1TS U2980 ( .A(n2312), .B(n2316), .C(n2302), .D(n2134), .Y(n2135) );
NAND2X1TS U2981 ( .A(Shift_reg_FLAGS_7[0]), .B(n3226), .Y(n3215) );
OAI2BB2XLTS U2982 ( .B0(n2329), .B1(n3247), .A0N(final_result_ieee[20]),
.A1N(n3278), .Y(n1093) );
AOI222X4TS U2983 ( .A0(Data_array_SWR[42]), .A1(n2904), .B0(
Data_array_SWR[38]), .B1(n2909), .C0(Data_array_SWR[35]), .C1(n2180),
.Y(n2930) );
INVX2TS U2984 ( .A(n2914), .Y(n2199) );
AOI22X1TS U2985 ( .A0(Data_array_SWR[10]), .A1(n2933), .B0(
Data_array_SWR[16]), .B1(n2886), .Y(n2138) );
AOI22X1TS U2986 ( .A0(n1871), .A1(n2935), .B0(Data_array_SWR[20]), .B1(n2895), .Y(n2137) );
OAI211X1TS U2987 ( .A0(n2930), .A1(n2199), .B0(n2138), .C0(n2137), .Y(n2169)
);
AOI22X1TS U2988 ( .A0(Data_array_SWR[44]), .A1(n2885), .B0(
Data_array_SWR[40]), .B1(n2904), .Y(n2140) );
AOI22X1TS U2989 ( .A0(Data_array_SWR[36]), .A1(n2909), .B0(
Data_array_SWR[34]), .B1(n2905), .Y(n2139) );
NAND2X2TS U2990 ( .A(n2140), .B(n2139), .Y(n2943) );
AOI22X1TS U2991 ( .A0(Data_array_SWR[33]), .A1(n2885), .B0(
Data_array_SWR[29]), .B1(n2904), .Y(n2142) );
AOI22X1TS U2992 ( .A0(n1879), .A1(n2897), .B0(Data_array_SWR[23]), .B1(n2905), .Y(n2141) );
NAND2X1TS U2993 ( .A(n2142), .B(n2141), .Y(n2942) );
OAI2BB2XLTS U2994 ( .B0(n3244), .B1(n3247), .A0N(final_result_ieee[10]),
.A1N(n3219), .Y(n1088) );
BUFX3TS U2995 ( .A(n2145), .Y(n2929) );
OAI2BB2XLTS U2996 ( .B0(n2327), .B1(n3247), .A0N(final_result_ieee[30]),
.A1N(n3278), .Y(n1092) );
AOI22X1TS U2997 ( .A0(Data_array_SWR[20]), .A1(n2934), .B0(
Data_array_SWR[16]), .B1(n2106), .Y(n2151) );
AOI22X1TS U2998 ( .A0(Data_array_SWR[23]), .A1(n2936), .B0(n1871), .B1(n2910), .Y(n2150) );
INVX2TS U2999 ( .A(n2939), .Y(n2213) );
AOI22X1TS U3000 ( .A0(n2213), .A1(n2148), .B0(n2914), .B1(n2147), .Y(n2149)
);
NOR2X2TS U3001 ( .A(shift_value_SHT2_EWR[5]), .B(n3241), .Y(n2227) );
AOI22X1TS U3002 ( .A0(left_right_SHT2), .A1(n2159), .B0(n2227), .B1(n2903),
.Y(n2292) );
OAI2BB2XLTS U3003 ( .B0(n2292), .B1(n3247), .A0N(final_result_ieee[36]),
.A1N(n3136), .Y(n1114) );
AOI222X4TS U3004 ( .A0(Data_array_SWR[44]), .A1(n2884), .B0(
Data_array_SWR[40]), .B1(n2909), .C0(Data_array_SWR[36]), .C1(n2180),
.Y(n2923) );
AOI22X1TS U3005 ( .A0(Data_array_SWR[21]), .A1(n2936), .B0(
Data_array_SWR[18]), .B1(n2934), .Y(n2154) );
AOI22X1TS U3006 ( .A0(Data_array_SWR[12]), .A1(n2933), .B0(
Data_array_SWR[14]), .B1(n2935), .Y(n2153) );
OAI211X1TS U3007 ( .A0(n2923), .A1(n2199), .B0(n2154), .C0(n2153), .Y(n2161)
);
AOI22X1TS U3008 ( .A0(Data_array_SWR[42]), .A1(n2885), .B0(
Data_array_SWR[38]), .B1(n2904), .Y(n2156) );
AOI22X1TS U3009 ( .A0(Data_array_SWR[35]), .A1(n2887), .B0(
Data_array_SWR[33]), .B1(n2180), .Y(n2155) );
NAND2X2TS U3010 ( .A(n2156), .B(n2155), .Y(n2955) );
AOI22X1TS U3011 ( .A0(Data_array_SWR[34]), .A1(n2103), .B0(
Data_array_SWR[31]), .B1(n2884), .Y(n2158) );
AOI22X1TS U3012 ( .A0(n1881), .A1(n2905), .B0(Data_array_SWR[27]), .B1(n2887), .Y(n2157) );
NAND2X1TS U3013 ( .A(n2158), .B(n2157), .Y(n2954) );
OAI2BB2XLTS U3014 ( .B0(n2486), .B1(n3247), .A0N(final_result_ieee[38]),
.A1N(n3272), .Y(n1100) );
NOR2X2TS U3015 ( .A(shift_value_SHT2_EWR[5]), .B(n1804), .Y(n2230) );
INVX4TS U3016 ( .A(left_right_SHT2), .Y(n2915) );
AOI22X1TS U3017 ( .A0(n2903), .A1(n2230), .B0(n2159), .B1(n2915), .Y(n2286)
);
OAI2BB2XLTS U3018 ( .B0(n2286), .B1(n3247), .A0N(final_result_ieee[14]),
.A1N(n3219), .Y(n1115) );
AOI21X1TS U3019 ( .A0(n2161), .A1(n2915), .B0(n2160), .Y(n2296) );
OAI2BB2XLTS U3020 ( .B0(n2296), .B1(n3247), .A0N(final_result_ieee[12]),
.A1N(n3278), .Y(n1101) );
AOI222X4TS U3021 ( .A0(Data_array_SWR[39]), .A1(n2909), .B0(n1876), .B1(
n2180), .C0(Data_array_SWR[43]), .C1(n2162), .Y(n2926) );
AOI22X1TS U3022 ( .A0(Data_array_SWR[17]), .A1(n2934), .B0(
Data_array_SWR[11]), .B1(n2933), .Y(n2164) );
AOI22X1TS U3023 ( .A0(n1880), .A1(n2936), .B0(n1869), .B1(n2935), .Y(n2163)
);
OAI211X1TS U3024 ( .A0(n2926), .A1(n2199), .B0(n2164), .C0(n2163), .Y(n2170)
);
AOI22X1TS U3025 ( .A0(Data_array_SWR[39]), .A1(n2904), .B0(
Data_array_SWR[43]), .B1(n2103), .Y(n2166) );
AOI22X1TS U3026 ( .A0(n1876), .A1(n2887), .B0(n1877), .B1(n2905), .Y(n2165)
);
NAND2X2TS U3027 ( .A(n2166), .B(n2165), .Y(n2949) );
AOI22X1TS U3028 ( .A0(n1877), .A1(n2885), .B0(Data_array_SWR[30]), .B1(n2904), .Y(n2168) );
AOI22X1TS U3029 ( .A0(Data_array_SWR[26]), .A1(n2897), .B0(
Data_array_SWR[24]), .B1(n2905), .Y(n2167) );
NAND2X1TS U3030 ( .A(n2168), .B(n2167), .Y(n2948) );
OAI2BB2XLTS U3031 ( .B0(n2335), .B1(n3247), .A0N(final_result_ieee[39]),
.A1N(n3136), .Y(n1106) );
OAI2BB2XLTS U3032 ( .B0(n2338), .B1(n3247), .A0N(final_result_ieee[40]),
.A1N(n3136), .Y(n1087) );
OAI2BB2XLTS U3033 ( .B0(n3245), .B1(n3247), .A0N(final_result_ieee[11]),
.A1N(n2318), .Y(n1109) );
INVX4TS U3034 ( .A(n3247), .Y(n3263) );
AOI22X1TS U3035 ( .A0(Data_array_SWR[37]), .A1(n2897), .B0(n1878), .B1(n2896), .Y(n2171) );
OAI21X1TS U3036 ( .A0(n3395), .A1(n2172), .B0(n2171), .Y(n2178) );
AO22XLTS U3037 ( .A0(Data_array_SWR[15]), .A1(n2886), .B0(Data_array_SWR[13]), .B1(n2106), .Y(n2177) );
AOI22X1TS U3038 ( .A0(Data_array_SWR[32]), .A1(n2885), .B0(
Data_array_SWR[28]), .B1(n2904), .Y(n2175) );
AOI22X1TS U3039 ( .A0(Data_array_SWR[19]), .A1(n2936), .B0(Data_array_SWR[9]), .B1(n2910), .Y(n2174) );
AOI22X1TS U3040 ( .A0(Data_array_SWR[25]), .A1(n2897), .B0(
Data_array_SWR[22]), .B1(n2896), .Y(n2173) );
AOI32X1TS U3041 ( .A0(n2175), .A1(n2174), .A2(n2173), .B0(n2111), .B1(n2174),
.Y(n2176) );
AOI211X1TS U3042 ( .A0(n2914), .A1(n2178), .B0(n2177), .C0(n2176), .Y(n2196)
);
INVX2TS U3043 ( .A(n2178), .Y(n2940) );
OAI22X1TS U3044 ( .A0(n3241), .A1(n2196), .B0(n2940), .B1(n3238), .Y(n3243)
);
AOI22X1TS U3045 ( .A0(Data_array_SWR[30]), .A1(n2885), .B0(
Data_array_SWR[26]), .B1(n2904), .Y(n2179) );
OAI2BB1X1TS U3046 ( .A0N(n1880), .A1N(n2180), .B0(n2179), .Y(n2181) );
AOI22X1TS U3047 ( .A0(n1869), .A1(n2934), .B0(Data_array_SWR[11]), .B1(n2935), .Y(n2183) );
AOI22X1TS U3048 ( .A0(Data_array_SWR[17]), .A1(n2936), .B0(Data_array_SWR[7]), .B1(n2933), .Y(n2182) );
AOI21X1TS U3049 ( .A0(n2914), .A1(n2949), .B0(n2184), .Y(n2195) );
OAI22X1TS U3050 ( .A0(n2195), .A1(n2915), .B0(n2926), .B1(n2966), .Y(n2917)
);
AOI22X1TS U3051 ( .A0(n1879), .A1(n2904), .B0(Data_array_SWR[20]), .B1(n2896), .Y(n2185) );
AOI22X1TS U3052 ( .A0(n1871), .A1(n2934), .B0(Data_array_SWR[10]), .B1(n2106), .Y(n2187) );
AOI22X1TS U3053 ( .A0(Data_array_SWR[16]), .A1(n2936), .B0(Data_array_SWR[6]), .B1(n2910), .Y(n2186) );
AOI21X1TS U3054 ( .A0(n2914), .A1(n2955), .B0(n2188), .Y(n2916) );
OAI22X1TS U3055 ( .A0(n3241), .A1(n2916), .B0(n2923), .B1(n3238), .Y(n3242)
);
AOI22X1TS U3056 ( .A0(Data_array_SWR[27]), .A1(n2904), .B0(
Data_array_SWR[21]), .B1(n2905), .Y(n2189) );
AOI22X1TS U3057 ( .A0(Data_array_SWR[12]), .A1(n2935), .B0(
Data_array_SWR[14]), .B1(n2886), .Y(n2192) );
AOI22X1TS U3058 ( .A0(Data_array_SWR[8]), .A1(n2933), .B0(Data_array_SWR[18]), .B1(n2895), .Y(n2191) );
AOI21X1TS U3059 ( .A0(n2914), .A1(n2943), .B0(n2193), .Y(n2194) );
OAI22X1TS U3060 ( .A0(n3241), .A1(n2194), .B0(n2930), .B1(n3238), .Y(n3257)
);
OAI22X1TS U3061 ( .A0(n2194), .A1(n2915), .B0(n2930), .B1(n2966), .Y(n2918)
);
OAI22X1TS U3062 ( .A0(n3241), .A1(n2195), .B0(n2926), .B1(n3238), .Y(n3251)
);
OAI22X1TS U3063 ( .A0(n2940), .A1(n2966), .B0(n2196), .B1(n1804), .Y(n2920)
);
AOI22X1TS U3064 ( .A0(Data_array_SWR[19]), .A1(n2934), .B0(
Data_array_SWR[13]), .B1(n2910), .Y(n2198) );
AOI22X1TS U3065 ( .A0(Data_array_SWR[15]), .A1(n2935), .B0(
Data_array_SWR[22]), .B1(n2895), .Y(n2197) );
OAI211X1TS U3066 ( .A0(n3239), .A1(n2199), .B0(n2198), .C0(n2197), .Y(n2231)
);
AOI22X1TS U3067 ( .A0(n1878), .A1(n2885), .B0(Data_array_SWR[32]), .B1(n2884), .Y(n2201) );
AOI22X1TS U3068 ( .A0(Data_array_SWR[28]), .A1(n2897), .B0(
Data_array_SWR[25]), .B1(n2896), .Y(n2200) );
NAND2X1TS U3069 ( .A(n2201), .B(n2200), .Y(n2961) );
AOI22X1TS U3070 ( .A0(Data_array_SWR[37]), .A1(n2904), .B0(
Data_array_SWR[41]), .B1(n2103), .Y(n2203) );
AOI22X1TS U3071 ( .A0(n1878), .A1(n2909), .B0(Data_array_SWR[32]), .B1(n2896), .Y(n2202) );
NAND2X2TS U3072 ( .A(n2203), .B(n2202), .Y(n2963) );
AOI21X1TS U3073 ( .A0(n2231), .A1(n2915), .B0(n2204), .Y(n2282) );
BUFX3TS U3074 ( .A(n3247), .Y(n2246) );
OAI2BB2XLTS U3075 ( .B0(n2282), .B1(n2246), .A0N(final_result_ieee[13]),
.A1N(n3272), .Y(n1084) );
AOI22X1TS U3076 ( .A0(Data_array_SWR[21]), .A1(n2934), .B0(
Data_array_SWR[18]), .B1(n2935), .Y(n2209) );
AOI22X1TS U3077 ( .A0(n1881), .A1(n2936), .B0(Data_array_SWR[14]), .B1(n2933), .Y(n2208) );
AOI22X1TS U3078 ( .A0(Data_array_SWR[36]), .A1(n2103), .B0(
Data_array_SWR[34]), .B1(n2884), .Y(n2206) );
AOI22X1TS U3079 ( .A0(Data_array_SWR[27]), .A1(n2905), .B0(
Data_array_SWR[31]), .B1(n2887), .Y(n2205) );
NAND2X1TS U3080 ( .A(n2206), .B(n2205), .Y(n2869) );
INVX2TS U3081 ( .A(n3234), .Y(n2244) );
AOI22X1TS U3082 ( .A0(n2213), .A1(n2869), .B0(n2914), .B1(n2244), .Y(n2207)
);
AOI22X1TS U3083 ( .A0(Data_array_SWR[38]), .A1(n2885), .B0(
Data_array_SWR[35]), .B1(n2884), .Y(n2210) );
AOI21X1TS U3084 ( .A0(Data_array_SWR[33]), .A1(n2887), .B0(n2211), .Y(n2235)
);
AOI22X1TS U3085 ( .A0(left_right_SHT2), .A1(n2212), .B0(n2227), .B1(n2882),
.Y(n2288) );
OAI2BB2XLTS U3086 ( .B0(n2288), .B1(n2246), .A0N(final_result_ieee[34]),
.A1N(n3219), .Y(n1069) );
AOI22X1TS U3087 ( .A0(n2882), .A1(n2230), .B0(n2212), .B1(n2915), .Y(n2280)
);
OAI2BB2XLTS U3088 ( .B0(n2280), .B1(n2246), .A0N(final_result_ieee[16]),
.A1N(n3278), .Y(n1070) );
AOI22X1TS U3089 ( .A0(Data_array_SWR[17]), .A1(n2935), .B0(n1880), .B1(n2886), .Y(n2216) );
AOI22X1TS U3090 ( .A0(n1869), .A1(n2933), .B0(Data_array_SWR[24]), .B1(n2895), .Y(n2215) );
INVX2TS U3091 ( .A(n3231), .Y(n2242) );
AOI22X1TS U3092 ( .A0(n2213), .A1(n2241), .B0(n2914), .B1(n2242), .Y(n2214)
);
AOI22X1TS U3093 ( .A0(n1876), .A1(n2904), .B0(Data_array_SWR[30]), .B1(n2896), .Y(n2217) );
OAI2BB1X1TS U3094 ( .A0N(Data_array_SWR[39]), .A1N(n2103), .B0(n2217), .Y(
n2218) );
AOI21X1TS U3095 ( .A0(n1877), .A1(n2887), .B0(n2218), .Y(n2240) );
AOI22X1TS U3096 ( .A0(left_right_SHT2), .A1(n2229), .B0(n2227), .B1(n2893),
.Y(n2290) );
OAI2BB2XLTS U3097 ( .B0(n2290), .B1(n2246), .A0N(final_result_ieee[35]),
.A1N(n3136), .Y(n1061) );
AOI22X1TS U3098 ( .A0(Data_array_SWR[37]), .A1(n2885), .B0(n1878), .B1(n2884), .Y(n2219) );
AOI21X1TS U3099 ( .A0(Data_array_SWR[32]), .A1(n2909), .B0(n2221), .Y(n2226)
);
AOI22X1TS U3100 ( .A0(Data_array_SWR[19]), .A1(n2935), .B0(
Data_array_SWR[15]), .B1(n2933), .Y(n2224) );
OAI2BB2XLTS U3101 ( .B0(n3395), .B1(n2236), .A0N(Data_array_SWR[22]), .A1N(
n2886), .Y(n2222) );
AOI21X1TS U3102 ( .A0(Data_array_SWR[25]), .A1(n2895), .B0(n2222), .Y(n2223)
);
OAI211X1TS U3103 ( .A0(n2226), .A1(n2939), .B0(n2224), .C0(n2223), .Y(n2228)
);
AOI22X1TS U3104 ( .A0(left_right_SHT2), .A1(n2228), .B0(n2227), .B1(n2875),
.Y(n2298) );
OAI2BB2XLTS U3105 ( .B0(n2298), .B1(n2246), .A0N(final_result_ieee[33]),
.A1N(n2318), .Y(n1073) );
AOI22X1TS U3106 ( .A0(n2228), .A1(n2915), .B0(n2230), .B1(n2875), .Y(n2294)
);
OAI2BB2XLTS U3107 ( .B0(n2294), .B1(n2246), .A0N(final_result_ieee[17]),
.A1N(n3272), .Y(n1074) );
AOI22X1TS U3108 ( .A0(n2230), .A1(n2893), .B0(n2229), .B1(n2915), .Y(n2284)
);
OAI2BB2XLTS U3109 ( .B0(n2284), .B1(n2246), .A0N(final_result_ieee[15]),
.A1N(n3219), .Y(n1062) );
OAI2BB2XLTS U3110 ( .B0(n2300), .B1(n2246), .A0N(final_result_ieee[37]),
.A1N(n3278), .Y(n1081) );
AOI22X1TS U3111 ( .A0(Data_array_SWR[20]), .A1(n2935), .B0(
Data_array_SWR[16]), .B1(n2933), .Y(n2234) );
OAI2BB2XLTS U3112 ( .B0(n1826), .B1(n2236), .A0N(Data_array_SWR[23]), .A1N(
n2886), .Y(n2232) );
AOI21X1TS U3113 ( .A0(n1879), .A1(n2895), .B0(n2232), .Y(n2233) );
OAI211X1TS U3114 ( .A0(n2235), .A1(n2939), .B0(n2234), .C0(n2233), .Y(n2245)
);
OAI2BB2XLTS U3115 ( .B0(n2333), .B1(n2246), .A0N(final_result_ieee[32]),
.A1N(n3136), .Y(n1071) );
AOI22X1TS U3116 ( .A0(Data_array_SWR[17]), .A1(n2933), .B0(n1880), .B1(n2935), .Y(n2239) );
OAI2BB2XLTS U3117 ( .B0(n3407), .B1(n2236), .A0N(Data_array_SWR[24]), .A1N(
n2886), .Y(n2237) );
AOI21X1TS U3118 ( .A0(Data_array_SWR[26]), .A1(n2895), .B0(n2237), .Y(n2238)
);
OAI211X1TS U3119 ( .A0(n2240), .A1(n2939), .B0(n2239), .C0(n2238), .Y(n2243)
);
OAI2BB2XLTS U3120 ( .B0(n2325), .B1(n2246), .A0N(final_result_ieee[31]),
.A1N(n2318), .Y(n1063) );
AOI222X1TS U3121 ( .A0(n2243), .A1(n1804), .B0(n2242), .B1(n2960), .C0(n2241), .C1(n2962), .Y(n2331) );
OAI2BB2XLTS U3122 ( .B0(n2331), .B1(n2246), .A0N(final_result_ieee[19]),
.A1N(n3272), .Y(n1064) );
AOI222X1TS U3123 ( .A0(n2245), .A1(n1804), .B0(n2244), .B1(n2960), .C0(n2869), .C1(n2962), .Y(n2323) );
OAI2BB2XLTS U3124 ( .B0(n2323), .B1(n2246), .A0N(final_result_ieee[18]),
.A1N(n3219), .Y(n1072) );
BUFX4TS U3125 ( .A(OP_FLAG_SFG), .Y(n2986) );
XOR2X1TS U3126 ( .A(n2986), .B(DmP_mant_SFG_SWR[14]), .Y(n2839) );
OAI21XLTS U3127 ( .A0(n2839), .A1(DMP_SFG[12]), .B0(Shift_reg_FLAGS_7[2]),
.Y(n2247) );
OAI21XLTS U3128 ( .A0(Shift_reg_FLAGS_7[2]), .A1(n3427), .B0(n2247), .Y(
n1142) );
OAI21XLTS U3129 ( .A0(n3223), .A1(n1804), .B0(n3137), .Y(n1729) );
BUFX3TS U3130 ( .A(n3431), .Y(n3218) );
NAND2X4TS U3131 ( .A(n2844), .B(n2274), .Y(n2277) );
MXI2X1TS U3132 ( .A(Raw_mant_NRM_SWR[11]), .B(DMP_SFG[9]), .S0(n2274), .Y(
n2250) );
NAND2X1TS U3133 ( .A(n1805), .B(DmP_mant_SFG_SWR[11]), .Y(n2249) );
MXI2X1TS U3134 ( .A(Raw_mant_NRM_SWR[8]), .B(DMP_SFG[6]), .S0(n2274), .Y(
n2252) );
NAND2X1TS U3135 ( .A(n1805), .B(DmP_mant_SFG_SWR[8]), .Y(n2251) );
OAI211XLTS U3136 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n2277), .B0(n2252), .C0(
n2251), .Y(n1118) );
MXI2X1TS U3137 ( .A(Raw_mant_NRM_SWR[10]), .B(DMP_SFG[8]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n2254) );
NAND2X1TS U3138 ( .A(n1805), .B(DmP_mant_SFG_SWR[10]), .Y(n2253) );
OAI211XLTS U3139 ( .A0(DmP_mant_SFG_SWR[10]), .A1(n2277), .B0(n2254), .C0(
n2253), .Y(n1096) );
AOI22X1TS U3140 ( .A0(n1805), .A1(n1860), .B0(Raw_mant_NRM_SWR[0]), .B1(
n3218), .Y(n2255) );
OAI21XLTS U3141 ( .A0(n1860), .A1(n2277), .B0(n2255), .Y(n1136) );
MXI2X1TS U3142 ( .A(Raw_mant_NRM_SWR[9]), .B(DMP_SFG[7]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n2257) );
NAND2X1TS U3143 ( .A(n1805), .B(DmP_mant_SFG_SWR[9]), .Y(n2256) );
OAI211XLTS U3144 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n2277), .B0(n2257), .C0(
n2256), .Y(n1104) );
MXI2X1TS U3145 ( .A(Raw_mant_NRM_SWR[5]), .B(DMP_SFG[3]), .S0(n2274), .Y(
n2260) );
NAND2X1TS U3146 ( .A(n1805), .B(DmP_mant_SFG_SWR[5]), .Y(n2259) );
OAI211XLTS U3147 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n2277), .B0(n2260), .C0(
n2259), .Y(n1131) );
MXI2X1TS U3148 ( .A(Raw_mant_NRM_SWR[3]), .B(DMP_SFG[1]), .S0(n2274), .Y(
n2262) );
NAND2X1TS U3149 ( .A(n1805), .B(n1858), .Y(n2261) );
OAI211XLTS U3150 ( .A0(n1858), .A1(n2277), .B0(n2262), .C0(n2261), .Y(n1128)
);
MXI2X1TS U3151 ( .A(Raw_mant_NRM_SWR[6]), .B(DMP_SFG[4]), .S0(n2274), .Y(
n2264) );
NAND2X1TS U3152 ( .A(n1805), .B(DmP_mant_SFG_SWR[6]), .Y(n2263) );
MXI2X1TS U3153 ( .A(Raw_mant_NRM_SWR[13]), .B(DMP_SFG[11]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n2266) );
NAND2BXLTS U3154 ( .AN(n3433), .B(n1805), .Y(n2265) );
OAI211XLTS U3155 ( .A0(DmP_mant_SFG_SWR[13]), .A1(n2277), .B0(n2266), .C0(
n2265), .Y(n1110) );
MXI2X1TS U3156 ( .A(Raw_mant_NRM_SWR[12]), .B(DMP_SFG[10]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n2268) );
NAND2BXLTS U3157 ( .AN(n3432), .B(n1805), .Y(n2267) );
MXI2X1TS U3158 ( .A(Raw_mant_NRM_SWR[2]), .B(DMP_SFG[0]), .S0(n2274), .Y(
n2270) );
NAND2X1TS U3159 ( .A(n1805), .B(DmP_mant_SFG_SWR[2]), .Y(n2269) );
OAI211XLTS U3160 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n2277), .B0(n2270), .C0(
n2269), .Y(n1133) );
MXI2X1TS U3161 ( .A(Raw_mant_NRM_SWR[4]), .B(DMP_SFG[2]), .S0(n2274), .Y(
n2272) );
NAND2X1TS U3162 ( .A(n1805), .B(DmP_mant_SFG_SWR[4]), .Y(n2271) );
OAI211XLTS U3163 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n2277), .B0(n2272), .C0(
n2271), .Y(n1126) );
AOI22X1TS U3164 ( .A0(n1805), .A1(n1861), .B0(Raw_mant_NRM_SWR[1]), .B1(
n3431), .Y(n2273) );
OAI21XLTS U3165 ( .A0(n1861), .A1(n2277), .B0(n2273), .Y(n1139) );
MXI2X1TS U3166 ( .A(Raw_mant_NRM_SWR[7]), .B(DMP_SFG[5]), .S0(n2274), .Y(
n2276) );
NAND2X1TS U3167 ( .A(n1805), .B(n1857), .Y(n2275) );
OAI211XLTS U3168 ( .A0(n1857), .A1(n2277), .B0(n2276), .C0(n2275), .Y(n1120)
);
AOI2BB2XLTS U3169 ( .B0(beg_OP), .B1(n3304), .A0N(n3304), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2278) );
NAND3XLTS U3170 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3304), .C(
n3390), .Y(n3131) );
OAI21XLTS U3171 ( .A0(n3130), .A1(n2278), .B0(n3131), .Y(n1802) );
INVX4TS U3172 ( .A(n3217), .Y(n2919) );
NAND2X1TS U3173 ( .A(n2336), .B(DmP_mant_SFG_SWR[18]), .Y(n2279) );
NAND2X1TS U3174 ( .A(n2336), .B(DmP_mant_SFG_SWR[15]), .Y(n2281) );
NAND2X1TS U3175 ( .A(DmP_mant_SFG_SWR[17]), .B(n2336), .Y(n2283) );
NAND2X1TS U3176 ( .A(n2336), .B(DmP_mant_SFG_SWR[16]), .Y(n2285) );
INVX4TS U3177 ( .A(n3185), .Y(n2484) );
NAND2X1TS U3178 ( .A(n2484), .B(DmP_mant_SFG_SWR[36]), .Y(n2287) );
NAND2X1TS U3179 ( .A(n2484), .B(DmP_mant_SFG_SWR[37]), .Y(n2289) );
NAND2X1TS U3180 ( .A(n2484), .B(DmP_mant_SFG_SWR[38]), .Y(n2291) );
NAND2X1TS U3181 ( .A(n2336), .B(DmP_mant_SFG_SWR[19]), .Y(n2293) );
NAND2X1TS U3182 ( .A(n2336), .B(DmP_mant_SFG_SWR[14]), .Y(n2295) );
NAND2X1TS U3183 ( .A(n2484), .B(DmP_mant_SFG_SWR[35]), .Y(n2297) );
NAND2X1TS U3184 ( .A(n2484), .B(DmP_mant_SFG_SWR[39]), .Y(n2299) );
NAND2X1TS U3185 ( .A(n3272), .B(final_result_ieee[59]), .Y(n2301) );
INVX2TS U3186 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n2304) );
NAND2X1TS U3187 ( .A(n3278), .B(final_result_ieee[56]), .Y(n2303) );
NAND2X1TS U3188 ( .A(n3278), .B(final_result_ieee[58]), .Y(n2305) );
NAND2X1TS U3189 ( .A(n2318), .B(final_result_ieee[52]), .Y(n2307) );
INVX2TS U3190 ( .A(exp_rslt_NRM2_EW1[5]), .Y(n2310) );
NAND2X1TS U3191 ( .A(n3136), .B(final_result_ieee[57]), .Y(n2309) );
NAND2X1TS U3192 ( .A(n3136), .B(final_result_ieee[61]), .Y(n2311) );
NAND2X1TS U3193 ( .A(n3219), .B(final_result_ieee[55]), .Y(n2313) );
NAND2X1TS U3194 ( .A(n3272), .B(final_result_ieee[60]), .Y(n2315) );
NAND2X1TS U3195 ( .A(n2318), .B(final_result_ieee[54]), .Y(n2317) );
NAND2X1TS U3196 ( .A(n3272), .B(final_result_ieee[53]), .Y(n2320) );
NAND2X1TS U3197 ( .A(n2336), .B(DmP_mant_SFG_SWR[20]), .Y(n2322) );
NAND2X1TS U3198 ( .A(n2336), .B(DmP_mant_SFG_SWR[33]), .Y(n2324) );
NAND2X1TS U3199 ( .A(n2336), .B(DmP_mant_SFG_SWR[32]), .Y(n2326) );
NAND2X1TS U3200 ( .A(n2336), .B(DmP_mant_SFG_SWR[22]), .Y(n2328) );
NAND2X1TS U3201 ( .A(n2336), .B(DmP_mant_SFG_SWR[21]), .Y(n2330) );
NAND2X1TS U3202 ( .A(n2484), .B(DmP_mant_SFG_SWR[34]), .Y(n2332) );
NAND2X1TS U3203 ( .A(n2484), .B(DmP_mant_SFG_SWR[41]), .Y(n2334) );
NAND2X1TS U3204 ( .A(n2336), .B(DmP_mant_SFG_SWR[42]), .Y(n2337) );
NOR2X1TS U3205 ( .A(n3428), .B(intDY_EWSW[53]), .Y(n2339) );
OAI22X1TS U3206 ( .A0(n3429), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n3320), .Y(n2458) );
NOR2BX1TS U3207 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2340) );
NOR2X1TS U3208 ( .A(n3350), .B(intDY_EWSW[57]), .Y(n2412) );
NAND2X1TS U3209 ( .A(n3325), .B(intDX_EWSW[61]), .Y(n2418) );
OAI211X1TS U3210 ( .A0(intDY_EWSW[60]), .A1(n3393), .B0(n2422), .C0(n2418),
.Y(n2424) );
OAI21X1TS U3211 ( .A0(intDY_EWSW[58]), .A1(n3392), .B0(n2414), .Y(n2416) );
NOR2X1TS U3212 ( .A(n3414), .B(intDY_EWSW[49]), .Y(n2461) );
OAI21X1TS U3213 ( .A0(intDY_EWSW[50]), .A1(n3293), .B0(n2463), .Y(n2467) );
AOI211X1TS U3214 ( .A0(intDX_EWSW[48]), .A1(n3381), .B0(n2461), .C0(n2467),
.Y(n2341) );
NAND3X1TS U3215 ( .A(n2460), .B(n2469), .C(n2341), .Y(n2477) );
NOR2BX1TS U3216 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2452) );
AOI21X1TS U3217 ( .A0(intDX_EWSW[38]), .A1(n3422), .B0(n2452), .Y(n2451) );
NAND2X1TS U3218 ( .A(n3396), .B(intDX_EWSW[37]), .Y(n2440) );
OAI211X1TS U3219 ( .A0(intDY_EWSW[36]), .A1(n3340), .B0(n2451), .C0(n2440),
.Y(n2442) );
NOR2X1TS U3220 ( .A(n3346), .B(intDY_EWSW[45]), .Y(n2426) );
OAI21X1TS U3221 ( .A0(intDY_EWSW[46]), .A1(n3326), .B0(n2425), .Y(n2435) );
OA22X1TS U3222 ( .A0(n3334), .A1(intDY_EWSW[42]), .B0(n3288), .B1(
intDY_EWSW[43]), .Y(n2431) );
NAND4X1TS U3223 ( .A(n2433), .B(n2431), .C(n2343), .D(n2342), .Y(n2475) );
OA22X1TS U3224 ( .A0(n3335), .A1(intDY_EWSW[34]), .B0(n3289), .B1(
intDY_EWSW[35]), .Y(n2446) );
NOR4X1TS U3225 ( .A(n2477), .B(n2442), .C(n2475), .D(n2345), .Y(n2481) );
OAI2BB2XLTS U3226 ( .B0(intDX_EWSW[28]), .B1(n2346), .A0N(intDY_EWSW[29]),
.A1N(n3342), .Y(n2355) );
OAI21X1TS U3227 ( .A0(intDY_EWSW[26]), .A1(n3359), .B0(n2349), .Y(n2407) );
NOR2X1TS U3228 ( .A(n3347), .B(intDY_EWSW[25]), .Y(n2404) );
AOI22X1TS U3229 ( .A0(n2348), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n3347), .Y(n2351) );
AOI32X1TS U3230 ( .A0(n3359), .A1(n2349), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n3294), .Y(n2350) );
OAI32X1TS U3231 ( .A0(n2407), .A1(n2406), .A2(n2351), .B0(n2350), .B1(n2406),
.Y(n2354) );
OAI2BB2XLTS U3232 ( .B0(intDX_EWSW[30]), .B1(n2352), .A0N(intDY_EWSW[31]),
.A1N(n3290), .Y(n2353) );
AOI211X1TS U3233 ( .A0(n2356), .A1(n2355), .B0(n2354), .C0(n2353), .Y(n2411)
);
OAI2BB1X1TS U3234 ( .A0N(n2606), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2359) );
OAI22X1TS U3235 ( .A0(intDX_EWSW[4]), .A1(n2359), .B0(n2606), .B1(
intDX_EWSW[5]), .Y(n2370) );
OAI2BB1X1TS U3236 ( .A0N(n2582), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2360) );
OAI22X1TS U3237 ( .A0(intDX_EWSW[6]), .A1(n2360), .B0(n2582), .B1(
intDX_EWSW[7]), .Y(n2369) );
NAND2BXLTS U3238 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2363) );
AOI2BB2XLTS U3239 ( .B0(intDX_EWSW[1]), .B1(n3421), .A0N(n1868), .A1N(n2361),
.Y(n2362) );
OAI21XLTS U3240 ( .A0(intDY_EWSW[3]), .A1(n3331), .B0(intDY_EWSW[2]), .Y(
n2364) );
AOI2BB2XLTS U3241 ( .B0(intDY_EWSW[3]), .B1(n3331), .A0N(intDX_EWSW[2]),
.A1N(n2364), .Y(n2365) );
OAI32X1TS U3242 ( .A0(n2370), .A1(n2369), .A2(n2368), .B0(n2367), .B1(n2369),
.Y(n2387) );
NOR2X1TS U3243 ( .A(n3330), .B(intDY_EWSW[11]), .Y(n2372) );
AOI21X1TS U3244 ( .A0(intDX_EWSW[10]), .A1(n3369), .B0(n2372), .Y(n2377) );
OAI21XLTS U3245 ( .A0(intDY_EWSW[13]), .A1(n3343), .B0(intDY_EWSW[12]), .Y(
n2371) );
OAI2BB2XLTS U3246 ( .B0(intDX_EWSW[12]), .B1(n2371), .A0N(intDY_EWSW[13]),
.A1N(n3343), .Y(n2383) );
AOI22X1TS U3247 ( .A0(intDY_EWSW[11]), .A1(n3330), .B0(intDY_EWSW[10]), .B1(
n2373), .Y(n2379) );
AOI21X1TS U3248 ( .A0(n2376), .A1(n2375), .B0(n2388), .Y(n2378) );
OAI2BB2XLTS U3249 ( .B0(n2379), .B1(n2388), .A0N(n2378), .A1N(n2377), .Y(
n2382) );
OAI2BB2XLTS U3250 ( .B0(intDX_EWSW[14]), .B1(n2380), .A0N(intDY_EWSW[15]),
.A1N(n3287), .Y(n2381) );
AOI211X1TS U3251 ( .A0(n2384), .A1(n2383), .B0(n2382), .C0(n2381), .Y(n2385)
);
OAI31X1TS U3252 ( .A0(n2388), .A1(n2387), .A2(n2386), .B0(n2385), .Y(n2390)
);
NOR2X1TS U3253 ( .A(n3348), .B(intDY_EWSW[17]), .Y(n2392) );
OAI21X1TS U3254 ( .A0(intDY_EWSW[18]), .A1(n3360), .B0(n2394), .Y(n2398) );
AOI211X1TS U3255 ( .A0(intDX_EWSW[16]), .A1(n3382), .B0(n2392), .C0(n2398),
.Y(n2389) );
OAI21XLTS U3256 ( .A0(intDY_EWSW[21]), .A1(n3357), .B0(intDY_EWSW[20]), .Y(
n2391) );
OAI2BB2XLTS U3257 ( .B0(intDX_EWSW[20]), .B1(n2391), .A0N(intDY_EWSW[21]),
.A1N(n3357), .Y(n2402) );
AOI22X1TS U3258 ( .A0(n2393), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n3348), .Y(n2396) );
AOI32X1TS U3259 ( .A0(n3360), .A1(n2394), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n3295), .Y(n2395) );
OAI32X1TS U3260 ( .A0(n2398), .A1(n2397), .A2(n2396), .B0(n2395), .B1(n2397),
.Y(n2401) );
OAI21XLTS U3261 ( .A0(intDY_EWSW[23]), .A1(n3291), .B0(intDY_EWSW[22]), .Y(
n2399) );
OAI2BB2XLTS U3262 ( .B0(intDX_EWSW[22]), .B1(n2399), .A0N(intDY_EWSW[23]),
.A1N(n3291), .Y(n2400) );
AOI211X1TS U3263 ( .A0(n2403), .A1(n2402), .B0(n2401), .C0(n2400), .Y(n2409)
);
NOR2BX1TS U3264 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2405) );
OR4X2TS U3265 ( .A(n2407), .B(n2406), .C(n2405), .D(n2404), .Y(n2408) );
AOI32X1TS U3266 ( .A0(n2411), .A1(n2410), .A2(n2409), .B0(n2408), .B1(n2411),
.Y(n2480) );
AOI22X1TS U3267 ( .A0(intDY_EWSW[57]), .A1(n3350), .B0(intDY_EWSW[56]), .B1(
n2413), .Y(n2417) );
OA21XLTS U3268 ( .A0(n2417), .A1(n2416), .B0(n2415), .Y(n2423) );
OAI2BB2XLTS U3269 ( .B0(n2424), .B1(n2423), .A0N(n2422), .A1N(n2421), .Y(
n2479) );
NOR2BX1TS U3270 ( .AN(n2425), .B(intDX_EWSW[46]), .Y(n2439) );
AOI22X1TS U3271 ( .A0(intDY_EWSW[45]), .A1(n3346), .B0(intDY_EWSW[44]), .B1(
n2427), .Y(n2436) );
OAI2BB2XLTS U3272 ( .B0(intDX_EWSW[40]), .B1(n2428), .A0N(intDY_EWSW[41]),
.A1N(n3341), .Y(n2432) );
OAI2BB2XLTS U3273 ( .B0(intDX_EWSW[42]), .B1(n2429), .A0N(intDY_EWSW[43]),
.A1N(n3288), .Y(n2430) );
AOI32X1TS U3274 ( .A0(n2433), .A1(n2432), .A2(n2431), .B0(n2430), .B1(n2433),
.Y(n2434) );
NOR2BX1TS U3275 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2437) );
AOI211X1TS U3276 ( .A0(intDY_EWSW[46]), .A1(n2439), .B0(n2438), .C0(n2437),
.Y(n2476) );
INVX2TS U3277 ( .A(n2442), .Y(n2448) );
OAI21XLTS U3278 ( .A0(intDY_EWSW[33]), .A1(n3333), .B0(intDY_EWSW[32]), .Y(
n2443) );
OAI2BB2XLTS U3279 ( .B0(intDX_EWSW[32]), .B1(n2443), .A0N(intDY_EWSW[33]),
.A1N(n3333), .Y(n2447) );
OAI21XLTS U3280 ( .A0(intDY_EWSW[35]), .A1(n3289), .B0(intDY_EWSW[34]), .Y(
n2444) );
OAI2BB2XLTS U3281 ( .B0(intDX_EWSW[34]), .B1(n2444), .A0N(intDY_EWSW[35]),
.A1N(n3289), .Y(n2445) );
AOI32X1TS U3282 ( .A0(n2448), .A1(n2447), .A2(n2446), .B0(n2445), .B1(n2448),
.Y(n2449) );
OAI2BB1X1TS U3283 ( .A0N(n2451), .A1N(n2450), .B0(n2449), .Y(n2456) );
NOR2BX1TS U3284 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2455) );
NOR3X1TS U3285 ( .A(n3422), .B(n2452), .C(intDX_EWSW[38]), .Y(n2454) );
INVX2TS U3286 ( .A(n2477), .Y(n2453) );
OAI31X1TS U3287 ( .A0(n2456), .A1(n2455), .A2(n2454), .B0(n2453), .Y(n2474)
);
INVX2TS U3288 ( .A(n2460), .Y(n2466) );
AOI22X1TS U3289 ( .A0(intDY_EWSW[49]), .A1(n3414), .B0(intDY_EWSW[48]), .B1(
n2462), .Y(n2465) );
AOI32X1TS U3290 ( .A0(n3293), .A1(n2463), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n3354), .Y(n2464) );
OAI32X1TS U3291 ( .A0(n2467), .A1(n2466), .A2(n2465), .B0(n2464), .B1(n2466),
.Y(n2471) );
OAI2BB2XLTS U3292 ( .B0(intDX_EWSW[54]), .B1(n2468), .A0N(intDY_EWSW[55]),
.A1N(n3429), .Y(n2470) );
OAI31X1TS U3293 ( .A0(n2472), .A1(n2471), .A2(n2470), .B0(n2469), .Y(n2473)
);
AOI211X1TS U3294 ( .A0(n2481), .A1(n2480), .B0(n2479), .C0(n2478), .Y(n2482)
);
AND2X4TS U3295 ( .A(n3211), .B(n2482), .Y(n2555) );
BUFX3TS U3296 ( .A(n2555), .Y(n2550) );
AOI22X1TS U3297 ( .A0(intDX_EWSW[14]), .A1(n2550), .B0(DMP_EXP_EWSW[14]),
.B1(n1887), .Y(n2483) );
NAND2X1TS U3298 ( .A(n2484), .B(DmP_mant_SFG_SWR[40]), .Y(n2485) );
BUFX4TS U3299 ( .A(n2555), .Y(n2541) );
AOI22X1TS U3300 ( .A0(intDX_EWSW[16]), .A1(n2541), .B0(DMP_EXP_EWSW[16]),
.B1(n1887), .Y(n2487) );
BUFX3TS U3301 ( .A(n2555), .Y(n2530) );
BUFX3TS U3302 ( .A(n2577), .Y(n2625) );
AOI22X1TS U3303 ( .A0(intDX_EWSW[48]), .A1(n2530), .B0(DMP_EXP_EWSW[48]),
.B1(n2625), .Y(n2488) );
AOI22X1TS U3304 ( .A0(intDX_EWSW[23]), .A1(n2541), .B0(DMP_EXP_EWSW[23]),
.B1(n2549), .Y(n2489) );
BUFX3TS U3305 ( .A(n2577), .Y(n2547) );
AOI22X1TS U3306 ( .A0(intDX_EWSW[49]), .A1(n2530), .B0(DMP_EXP_EWSW[49]),
.B1(n2547), .Y(n2490) );
AOI22X1TS U3307 ( .A0(intDX_EWSW[44]), .A1(n2530), .B0(DMP_EXP_EWSW[44]),
.B1(n2547), .Y(n2491) );
AOI22X1TS U3308 ( .A0(intDX_EWSW[21]), .A1(n2541), .B0(DMP_EXP_EWSW[21]),
.B1(n1887), .Y(n2492) );
AOI22X1TS U3309 ( .A0(intDX_EWSW[24]), .A1(n2541), .B0(DMP_EXP_EWSW[24]),
.B1(n2549), .Y(n2493) );
AOI22X1TS U3310 ( .A0(intDX_EWSW[17]), .A1(n2541), .B0(DMP_EXP_EWSW[17]),
.B1(n1887), .Y(n2494) );
AOI22X1TS U3311 ( .A0(intDX_EWSW[27]), .A1(n2541), .B0(DMP_EXP_EWSW[27]),
.B1(n2549), .Y(n2495) );
AOI22X1TS U3312 ( .A0(intDX_EWSW[47]), .A1(n2530), .B0(DMP_EXP_EWSW[47]),
.B1(n2547), .Y(n2496) );
AOI22X1TS U3313 ( .A0(intDX_EWSW[43]), .A1(n2530), .B0(DMP_EXP_EWSW[43]),
.B1(n2547), .Y(n2497) );
AOI22X1TS U3314 ( .A0(intDX_EWSW[40]), .A1(n2541), .B0(DMP_EXP_EWSW[40]),
.B1(n2547), .Y(n2498) );
AOI22X1TS U3315 ( .A0(intDX_EWSW[45]), .A1(n2530), .B0(DMP_EXP_EWSW[45]),
.B1(n2547), .Y(n2499) );
AOI22X1TS U3316 ( .A0(intDX_EWSW[41]), .A1(n2550), .B0(DMP_EXP_EWSW[41]),
.B1(n2547), .Y(n2500) );
AOI22X1TS U3317 ( .A0(intDX_EWSW[46]), .A1(n2530), .B0(DMP_EXP_EWSW[46]),
.B1(n2547), .Y(n2501) );
AOI22X1TS U3318 ( .A0(intDX_EWSW[42]), .A1(n2550), .B0(DMP_EXP_EWSW[42]),
.B1(n2547), .Y(n2502) );
BUFX3TS U3319 ( .A(n2555), .Y(n2590) );
AOI22X1TS U3320 ( .A0(intDX_EWSW[12]), .A1(n2590), .B0(DMP_EXP_EWSW[12]),
.B1(n1887), .Y(n2504) );
AOI22X1TS U3321 ( .A0(intDX_EWSW[19]), .A1(n2541), .B0(DMP_EXP_EWSW[19]),
.B1(n1887), .Y(n2505) );
AOI22X1TS U3322 ( .A0(intDX_EWSW[20]), .A1(n2530), .B0(DMP_EXP_EWSW[20]),
.B1(n1887), .Y(n2506) );
AOI22X1TS U3323 ( .A0(intDX_EWSW[28]), .A1(n2541), .B0(DMP_EXP_EWSW[28]),
.B1(n2549), .Y(n2507) );
AOI22X1TS U3324 ( .A0(intDX_EWSW[25]), .A1(n2541), .B0(DMP_EXP_EWSW[25]),
.B1(n2625), .Y(n2508) );
AOI22X1TS U3325 ( .A0(intDX_EWSW[50]), .A1(n2530), .B0(DMP_EXP_EWSW[50]),
.B1(n2625), .Y(n2509) );
AOI22X1TS U3326 ( .A0(intDX_EWSW[51]), .A1(n2530), .B0(DMP_EXP_EWSW[51]),
.B1(n2625), .Y(n2510) );
AOI22X1TS U3327 ( .A0(intDX_EWSW[0]), .A1(n2530), .B0(DMP_EXP_EWSW[0]), .B1(
n2629), .Y(n2511) );
INVX4TS U3328 ( .A(n2560), .Y(n2567) );
AOI22X1TS U3329 ( .A0(intDX_EWSW[31]), .A1(n2567), .B0(DmP_EXP_EWSW[31]),
.B1(n2577), .Y(n2512) );
AOI22X1TS U3330 ( .A0(intDX_EWSW[30]), .A1(n2567), .B0(DmP_EXP_EWSW[30]),
.B1(n2622), .Y(n2513) );
AOI22X1TS U3331 ( .A0(intDX_EWSW[27]), .A1(n2567), .B0(DmP_EXP_EWSW[27]),
.B1(n2622), .Y(n2514) );
AOI22X1TS U3332 ( .A0(intDX_EWSW[29]), .A1(n2567), .B0(DmP_EXP_EWSW[29]),
.B1(n2577), .Y(n2515) );
AOI22X1TS U3333 ( .A0(intDX_EWSW[25]), .A1(n2567), .B0(DmP_EXP_EWSW[25]),
.B1(n2625), .Y(n2516) );
AOI22X1TS U3334 ( .A0(intDX_EWSW[26]), .A1(n2567), .B0(DmP_EXP_EWSW[26]),
.B1(n2622), .Y(n2517) );
AOI22X1TS U3335 ( .A0(intDX_EWSW[28]), .A1(n2567), .B0(DmP_EXP_EWSW[28]),
.B1(n2577), .Y(n2518) );
INVX4TS U3336 ( .A(n2560), .Y(n2602) );
BUFX3TS U3337 ( .A(n2622), .Y(n3134) );
AOI22X1TS U3338 ( .A0(intDX_EWSW[46]), .A1(n2602), .B0(DmP_EXP_EWSW[46]),
.B1(n3134), .Y(n2519) );
AOI22X1TS U3339 ( .A0(intDX_EWSW[43]), .A1(n2602), .B0(DmP_EXP_EWSW[43]),
.B1(n3134), .Y(n2520) );
AOI22X1TS U3340 ( .A0(intDX_EWSW[34]), .A1(n2567), .B0(DmP_EXP_EWSW[34]),
.B1(n2577), .Y(n2521) );
AOI22X1TS U3341 ( .A0(intDX_EWSW[33]), .A1(n2567), .B0(DmP_EXP_EWSW[33]),
.B1(n2577), .Y(n2522) );
AOI22X1TS U3342 ( .A0(intDX_EWSW[42]), .A1(n2602), .B0(DmP_EXP_EWSW[42]),
.B1(n3134), .Y(n2523) );
AOI22X1TS U3343 ( .A0(intDX_EWSW[45]), .A1(n2602), .B0(DmP_EXP_EWSW[45]),
.B1(n3134), .Y(n2524) );
AOI22X1TS U3344 ( .A0(intDX_EWSW[36]), .A1(n2567), .B0(DmP_EXP_EWSW[36]),
.B1(n2577), .Y(n2525) );
AOI22X1TS U3345 ( .A0(intDX_EWSW[35]), .A1(n2567), .B0(DmP_EXP_EWSW[35]),
.B1(n2577), .Y(n2526) );
AOI22X1TS U3346 ( .A0(intDX_EWSW[41]), .A1(n2602), .B0(DmP_EXP_EWSW[41]),
.B1(n2577), .Y(n2527) );
BUFX3TS U3347 ( .A(n2560), .Y(n2552) );
AOI22X1TS U3348 ( .A0(intDX_EWSW[22]), .A1(n2550), .B0(DMP_EXP_EWSW[22]),
.B1(n2549), .Y(n2528) );
AOI22X1TS U3349 ( .A0(intDX_EWSW[38]), .A1(n2550), .B0(DMP_EXP_EWSW[38]),
.B1(n2547), .Y(n2529) );
BUFX3TS U3350 ( .A(n2560), .Y(n2605) );
AOI22X1TS U3351 ( .A0(intDX_EWSW[15]), .A1(n2530), .B0(DMP_EXP_EWSW[15]),
.B1(n1887), .Y(n2531) );
AOI22X1TS U3352 ( .A0(intDX_EWSW[30]), .A1(n2541), .B0(DMP_EXP_EWSW[30]),
.B1(n2549), .Y(n2532) );
AOI22X1TS U3353 ( .A0(intDX_EWSW[37]), .A1(n2550), .B0(DMP_EXP_EWSW[37]),
.B1(n2549), .Y(n2533) );
AOI22X1TS U3354 ( .A0(intDX_EWSW[31]), .A1(n2541), .B0(DMP_EXP_EWSW[31]),
.B1(n2549), .Y(n2534) );
AOI22X1TS U3355 ( .A0(intDX_EWSW[26]), .A1(n2541), .B0(DMP_EXP_EWSW[26]),
.B1(n2549), .Y(n2535) );
AOI22X1TS U3356 ( .A0(intDX_EWSW[13]), .A1(n2541), .B0(DMP_EXP_EWSW[13]),
.B1(n1887), .Y(n2536) );
AOI22X1TS U3357 ( .A0(intDX_EWSW[8]), .A1(n2590), .B0(DMP_EXP_EWSW[8]), .B1(
n1887), .Y(n2537) );
AOI22X1TS U3358 ( .A0(intDX_EWSW[18]), .A1(n2550), .B0(DMP_EXP_EWSW[18]),
.B1(n1887), .Y(n2538) );
AOI22X1TS U3359 ( .A0(intDX_EWSW[11]), .A1(n2590), .B0(DMP_EXP_EWSW[11]),
.B1(n1887), .Y(n2539) );
AOI22X1TS U3360 ( .A0(intDX_EWSW[3]), .A1(n2590), .B0(DMP_EXP_EWSW[3]), .B1(
n2629), .Y(n2540) );
AOI22X1TS U3361 ( .A0(intDX_EWSW[29]), .A1(n2541), .B0(DMP_EXP_EWSW[29]),
.B1(n2549), .Y(n2542) );
AOI22X1TS U3362 ( .A0(intDX_EWSW[32]), .A1(n2550), .B0(DMP_EXP_EWSW[32]),
.B1(n2549), .Y(n2543) );
AOI22X1TS U3363 ( .A0(intDX_EWSW[36]), .A1(n2550), .B0(DMP_EXP_EWSW[36]),
.B1(n2547), .Y(n2544) );
AOI22X1TS U3364 ( .A0(intDX_EWSW[39]), .A1(n2550), .B0(DMP_EXP_EWSW[39]),
.B1(n2547), .Y(n2545) );
AOI22X1TS U3365 ( .A0(intDX_EWSW[35]), .A1(n2550), .B0(DMP_EXP_EWSW[35]),
.B1(n2549), .Y(n2546) );
AOI22X1TS U3366 ( .A0(intDX_EWSW[33]), .A1(n2550), .B0(DMP_EXP_EWSW[33]),
.B1(n2547), .Y(n2548) );
AOI22X1TS U3367 ( .A0(intDX_EWSW[34]), .A1(n2550), .B0(DMP_EXP_EWSW[34]),
.B1(n2549), .Y(n2551) );
AOI22X1TS U3368 ( .A0(intDX_EWSW[7]), .A1(n2590), .B0(DMP_EXP_EWSW[7]), .B1(
n2629), .Y(n2553) );
INVX2TS U3369 ( .A(n2554), .Y(n2558) );
AOI22X1TS U3370 ( .A0(intDX_EWSW[63]), .A1(n2556), .B0(SIGN_FLAG_EXP), .B1(
n2625), .Y(n2557) );
INVX4TS U3371 ( .A(n2560), .Y(n2623) );
AOI22X1TS U3372 ( .A0(intDX_EWSW[23]), .A1(n2623), .B0(DmP_EXP_EWSW[23]),
.B1(n2622), .Y(n2561) );
INVX4TS U3373 ( .A(n2560), .Y(n2619) );
BUFX3TS U3374 ( .A(n2622), .Y(n2618) );
AOI22X1TS U3375 ( .A0(intDX_EWSW[8]), .A1(n2619), .B0(DmP_EXP_EWSW[8]), .B1(
n2618), .Y(n2562) );
AOI22X1TS U3376 ( .A0(intDX_EWSW[3]), .A1(n2619), .B0(DmP_EXP_EWSW[3]), .B1(
n2618), .Y(n2563) );
AOI22X1TS U3377 ( .A0(intDX_EWSW[32]), .A1(n2567), .B0(DmP_EXP_EWSW[32]),
.B1(n2577), .Y(n2564) );
AOI22X1TS U3378 ( .A0(intDX_EWSW[40]), .A1(n2602), .B0(DmP_EXP_EWSW[40]),
.B1(n2577), .Y(n2565) );
AOI22X1TS U3379 ( .A0(intDX_EWSW[47]), .A1(n2602), .B0(DmP_EXP_EWSW[47]),
.B1(n3134), .Y(n2566) );
AOI22X1TS U3380 ( .A0(intDX_EWSW[37]), .A1(n2567), .B0(DmP_EXP_EWSW[37]),
.B1(n2577), .Y(n2568) );
AOI22X1TS U3381 ( .A0(intDX_EWSW[38]), .A1(n2602), .B0(DmP_EXP_EWSW[38]),
.B1(n2577), .Y(n2569) );
AOI22X1TS U3382 ( .A0(intDX_EWSW[44]), .A1(n2602), .B0(DmP_EXP_EWSW[44]),
.B1(n3134), .Y(n2570) );
AOI22X1TS U3383 ( .A0(intDY_EWSW[62]), .A1(n2619), .B0(DMP_EXP_EWSW[62]),
.B1(n2625), .Y(n2571) );
AOI22X1TS U3384 ( .A0(intDY_EWSW[61]), .A1(n2602), .B0(DMP_EXP_EWSW[61]),
.B1(n2625), .Y(n2572) );
AOI22X1TS U3385 ( .A0(intDX_EWSW[6]), .A1(n2619), .B0(DmP_EXP_EWSW[6]), .B1(
n2618), .Y(n2573) );
AOI22X1TS U3386 ( .A0(intDX_EWSW[24]), .A1(n2623), .B0(DmP_EXP_EWSW[24]),
.B1(n2622), .Y(n2574) );
AOI22X1TS U3387 ( .A0(intDX_EWSW[9]), .A1(n2619), .B0(DmP_EXP_EWSW[9]), .B1(
n2618), .Y(n2575) );
AOI22X1TS U3388 ( .A0(intDX_EWSW[2]), .A1(n2619), .B0(DmP_EXP_EWSW[2]), .B1(
n2618), .Y(n2576) );
AOI22X1TS U3389 ( .A0(intDX_EWSW[39]), .A1(n2623), .B0(DmP_EXP_EWSW[39]),
.B1(n2577), .Y(n2578) );
AOI22X1TS U3390 ( .A0(intDX_EWSW[4]), .A1(n2619), .B0(DmP_EXP_EWSW[4]), .B1(
n2618), .Y(n2580) );
AOI22X1TS U3391 ( .A0(intDX_EWSW[7]), .A1(n2619), .B0(DmP_EXP_EWSW[7]), .B1(
n2618), .Y(n2581) );
AOI22X1TS U3392 ( .A0(intDX_EWSW[1]), .A1(n2619), .B0(DmP_EXP_EWSW[1]), .B1(
n2625), .Y(n2583) );
AOI22X1TS U3393 ( .A0(DmP_EXP_EWSW[57]), .A1(n3134), .B0(intDX_EWSW[57]),
.B1(n2619), .Y(n2584) );
AOI22X1TS U3394 ( .A0(intDX_EWSW[5]), .A1(n2619), .B0(DmP_EXP_EWSW[5]), .B1(
n2618), .Y(n2586) );
AOI22X1TS U3395 ( .A0(intDY_EWSW[59]), .A1(n2602), .B0(DMP_EXP_EWSW[59]),
.B1(n2625), .Y(n2587) );
AOI22X1TS U3396 ( .A0(intDX_EWSW[0]), .A1(n2619), .B0(DmP_EXP_EWSW[0]), .B1(
n2625), .Y(n2588) );
AOI22X1TS U3397 ( .A0(intDX_EWSW[6]), .A1(n2590), .B0(DMP_EXP_EWSW[6]), .B1(
n2629), .Y(n2591) );
AOI22X1TS U3398 ( .A0(intDX_EWSW[9]), .A1(n2590), .B0(DMP_EXP_EWSW[9]), .B1(
n2629), .Y(n2592) );
AOI22X1TS U3399 ( .A0(intDX_EWSW[10]), .A1(n2555), .B0(DMP_EXP_EWSW[10]),
.B1(n1887), .Y(n2594) );
AOI22X1TS U3400 ( .A0(intDX_EWSW[2]), .A1(n2555), .B0(DMP_EXP_EWSW[2]), .B1(
n2629), .Y(n2595) );
AOI22X1TS U3401 ( .A0(intDX_EWSW[4]), .A1(n2590), .B0(DMP_EXP_EWSW[4]), .B1(
n2629), .Y(n2596) );
AOI22X1TS U3402 ( .A0(intDX_EWSW[1]), .A1(n2555), .B0(DMP_EXP_EWSW[1]), .B1(
n2629), .Y(n2597) );
AOI22X1TS U3403 ( .A0(intDX_EWSW[48]), .A1(n2602), .B0(DmP_EXP_EWSW[48]),
.B1(n3134), .Y(n2598) );
AOI22X1TS U3404 ( .A0(intDX_EWSW[49]), .A1(n2602), .B0(DmP_EXP_EWSW[49]),
.B1(n3134), .Y(n2599) );
AOI22X1TS U3405 ( .A0(intDY_EWSW[58]), .A1(n2623), .B0(DMP_EXP_EWSW[58]),
.B1(n2625), .Y(n2600) );
AOI22X1TS U3406 ( .A0(intDX_EWSW[50]), .A1(n2602), .B0(DmP_EXP_EWSW[50]),
.B1(n3134), .Y(n2601) );
AOI22X1TS U3407 ( .A0(intDX_EWSW[51]), .A1(n2602), .B0(DmP_EXP_EWSW[51]),
.B1(n3134), .Y(n2603) );
AOI22X1TS U3408 ( .A0(intDX_EWSW[5]), .A1(n2530), .B0(DMP_EXP_EWSW[5]), .B1(
n2629), .Y(n2604) );
AOI22X1TS U3409 ( .A0(n1864), .A1(n3134), .B0(intDX_EWSW[57]), .B1(n2555),
.Y(n2607) );
AOI22X1TS U3410 ( .A0(intDX_EWSW[14]), .A1(n2623), .B0(DmP_EXP_EWSW[14]),
.B1(n2622), .Y(n2608) );
AOI22X1TS U3411 ( .A0(intDX_EWSW[17]), .A1(n2623), .B0(DmP_EXP_EWSW[17]),
.B1(n2622), .Y(n2609) );
AOI22X1TS U3412 ( .A0(intDX_EWSW[19]), .A1(n2623), .B0(DmP_EXP_EWSW[19]),
.B1(n2622), .Y(n2610) );
AOI22X1TS U3413 ( .A0(intDX_EWSW[20]), .A1(n2623), .B0(DmP_EXP_EWSW[20]),
.B1(n2622), .Y(n2611) );
AOI22X1TS U3414 ( .A0(intDX_EWSW[21]), .A1(n2623), .B0(DmP_EXP_EWSW[21]),
.B1(n2622), .Y(n2612) );
AOI22X1TS U3415 ( .A0(intDX_EWSW[13]), .A1(n2623), .B0(DmP_EXP_EWSW[13]),
.B1(n2618), .Y(n2613) );
AOI22X1TS U3416 ( .A0(intDX_EWSW[15]), .A1(n2623), .B0(DmP_EXP_EWSW[15]),
.B1(n2618), .Y(n2614) );
AOI22X1TS U3417 ( .A0(intDX_EWSW[22]), .A1(n2623), .B0(DmP_EXP_EWSW[22]),
.B1(n2622), .Y(n2615) );
AOI22X1TS U3418 ( .A0(intDX_EWSW[12]), .A1(n2619), .B0(DmP_EXP_EWSW[12]),
.B1(n2618), .Y(n2616) );
AOI22X1TS U3419 ( .A0(intDX_EWSW[11]), .A1(n2619), .B0(DmP_EXP_EWSW[11]),
.B1(n2618), .Y(n2617) );
AOI22X1TS U3420 ( .A0(intDX_EWSW[10]), .A1(n2619), .B0(DmP_EXP_EWSW[10]),
.B1(n2618), .Y(n2620) );
AOI22X1TS U3421 ( .A0(intDX_EWSW[18]), .A1(n2623), .B0(DmP_EXP_EWSW[18]),
.B1(n2622), .Y(n2621) );
AOI22X1TS U3422 ( .A0(intDX_EWSW[16]), .A1(n2623), .B0(DmP_EXP_EWSW[16]),
.B1(n2622), .Y(n2624) );
AOI22X1TS U3423 ( .A0(intDY_EWSW[60]), .A1(n2623), .B0(DMP_EXP_EWSW[60]),
.B1(n2625), .Y(n2626) );
INVX2TS U3424 ( .A(n2628), .Y(n1535) );
INVX2TS U3425 ( .A(n2630), .Y(n1206) );
AOI22X1TS U3426 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[1]), .B0(n1862), .B1(
n3137), .Y(n2632) );
NAND2X1TS U3427 ( .A(n2632), .B(n2734), .Y(n2806) );
AOI22X1TS U3428 ( .A0(n3162), .A1(Data_array_SWR[43]), .B0(n2653), .B1(n2806), .Y(n2633) );
BUFX8TS U3429 ( .A(n2649), .Y(n2826) );
AOI22X1TS U3430 ( .A0(n2002), .A1(Raw_mant_NRM_SWR[50]), .B0(n2704), .B1(
DmP_mant_SHT1_SW[2]), .Y(n2635) );
AOI22X1TS U3431 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[51]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2634) );
NAND2X1TS U3432 ( .A(n2635), .B(n2634), .Y(n2654) );
AOI22X1TS U3433 ( .A0(n2821), .A1(Data_array_SWR[3]), .B0(n2653), .B1(n2654),
.Y(n2638) );
BUFX4TS U3434 ( .A(n2642), .Y(n2805) );
NAND2X1TS U3435 ( .A(n2805), .B(Raw_mant_NRM_SWR[48]), .Y(n2637) );
BUFX4TS U3436 ( .A(n2639), .Y(n2811) );
INVX4TS U3437 ( .A(n2736), .Y(n2724) );
AOI22X1TS U3438 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2002), .B0(n2704), .B1(
DmP_mant_SHT1_SW[5]), .Y(n2641) );
AOI22X1TS U3439 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[48]), .B0(n2750), .B1(
DmP_mant_SHT1_SW[4]), .Y(n2640) );
NAND2X1TS U3440 ( .A(n2641), .B(n2640), .Y(n2662) );
AOI22X1TS U3441 ( .A0(n3162), .A1(n1866), .B0(n2653), .B1(n2662), .Y(n2644)
);
BUFX4TS U3442 ( .A(n2642), .Y(n2771) );
NAND2X1TS U3443 ( .A(Raw_mant_NRM_SWR[45]), .B(n2771), .Y(n2643) );
AOI22X1TS U3444 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2002), .B0(n2704), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2646) );
AOI22X1TS U3445 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2752), .B0(n2750), .B1(
DmP_mant_SHT1_SW[7]), .Y(n2645) );
NAND2X1TS U3446 ( .A(n2646), .B(n2645), .Y(n2658) );
AOI22X1TS U3447 ( .A0(n2795), .A1(Data_array_SWR[7]), .B0(n2653), .B1(n2658),
.Y(n2648) );
NAND2X1TS U3448 ( .A(Raw_mant_NRM_SWR[42]), .B(n2771), .Y(n2647) );
AOI22X1TS U3449 ( .A0(n2815), .A1(Data_array_SWR[2]), .B0(n2653), .B1(n2650),
.Y(n2652) );
NAND2X1TS U3450 ( .A(n2805), .B(Raw_mant_NRM_SWR[49]), .Y(n2651) );
AOI22X1TS U3451 ( .A0(n2752), .A1(Raw_mant_NRM_SWR[53]), .B0(n2803), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2657) );
BUFX4TS U3452 ( .A(n2829), .Y(n2822) );
AOI22X1TS U3453 ( .A0(n2659), .A1(Data_array_SWR[1]), .B0(n2807), .B1(n2654),
.Y(n2656) );
NAND2X1TS U3454 ( .A(n2720), .B(Raw_mant_NRM_SWR[52]), .Y(n2655) );
AOI22X1TS U3455 ( .A0(n2659), .A1(Data_array_SWR[5]), .B0(n2807), .B1(n2658),
.Y(n2661) );
INVX4TS U3456 ( .A(n2730), .Y(n2756) );
NAND2X1TS U3457 ( .A(Raw_mant_NRM_SWR[46]), .B(n2756), .Y(n2660) );
AOI22X1TS U3458 ( .A0(n2659), .A1(n1865), .B0(n2807), .B1(n2662), .Y(n2664)
);
NAND2X1TS U3459 ( .A(n2720), .B(Raw_mant_NRM_SWR[49]), .Y(n2663) );
AOI22X1TS U3460 ( .A0(n2659), .A1(Data_array_SWR[4]), .B0(
Raw_mant_NRM_SWR[46]), .B1(n2771), .Y(n2668) );
AOI22X1TS U3461 ( .A0(n2821), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[38]), .B1(n2805), .Y(n2671) );
AOI22X1TS U3462 ( .A0(n2815), .A1(Data_array_SWR[6]), .B0(
Raw_mant_NRM_SWR[43]), .B1(n2805), .Y(n2673) );
AOI22X1TS U3463 ( .A0(n2821), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[40]), .B1(n2805), .Y(n2677) );
AOI22X1TS U3464 ( .A0(n2659), .A1(Data_array_SWR[22]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n2805), .Y(n2680) );
AOI22X1TS U3465 ( .A0(n3162), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[36]), .B1(n2805), .Y(n2682) );
AOI22X1TS U3466 ( .A0(n2795), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[33]), .B1(n2805), .Y(n2685) );
AOI22X1TS U3467 ( .A0(n2821), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[29]), .B1(n2805), .Y(n2687) );
BUFX4TS U3468 ( .A(n2639), .Y(n2804) );
INVX2TS U3469 ( .A(n2736), .Y(n2705) );
AOI22X1TS U3470 ( .A0(n3162), .A1(Data_array_SWR[38]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n2771), .Y(n2689) );
AOI22X1TS U3471 ( .A0(n2795), .A1(Data_array_SWR[33]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2771), .Y(n2691) );
AOI222X1TS U3472 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2804), .B0(n2704), .B1(
n1874), .C0(n2724), .C1(n1863), .Y(n2733) );
AOI22X1TS U3473 ( .A0(n2795), .A1(Data_array_SWR[31]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2771), .Y(n2694) );
AOI22X1TS U3474 ( .A0(n2795), .A1(Data_array_SWR[29]), .B0(
Raw_mant_NRM_SWR[15]), .B1(n2771), .Y(n2697) );
AOI22X1TS U3475 ( .A0(n3162), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2805), .Y(n2700) );
AOI22X1TS U3476 ( .A0(n2815), .A1(Data_array_SWR[25]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2771), .Y(n2703) );
AOI22X1TS U3477 ( .A0(n3162), .A1(Data_array_SWR[40]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2771), .Y(n2707) );
AOI22X1TS U3478 ( .A0(n2821), .A1(Data_array_SWR[35]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n2771), .Y(n2710) );
AOI22X1TS U3479 ( .A0(n2821), .A1(Data_array_SWR[36]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2771), .Y(n2714) );
AOI22X1TS U3480 ( .A0(n2815), .A1(Data_array_SWR[24]), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2771), .Y(n2718) );
AOI22X1TS U3481 ( .A0(n2815), .A1(Data_array_SWR[20]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2805), .Y(n2722) );
AOI22X1TS U3482 ( .A0(n2815), .A1(Data_array_SWR[26]), .B0(
Raw_mant_NRM_SWR[18]), .B1(n2771), .Y(n2727) );
AOI22X1TS U3483 ( .A0(n2795), .A1(Data_array_SWR[34]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2771), .Y(n2732) );
OA22X1TS U3484 ( .A0(n3286), .A1(n2730), .B0(n2729), .B1(n2833), .Y(n2731)
);
AOI21X1TS U3485 ( .A0(n3162), .A1(Data_array_SWR[44]), .B0(n1844), .Y(n2735)
);
AOI22X1TS U3486 ( .A0(n3162), .A1(Data_array_SWR[42]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2756), .Y(n2739) );
AOI22X1TS U3487 ( .A0(n2815), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2756), .Y(n2743) );
AOI2BB2X1TS U3488 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[26]), .A0N(n2741),
.A1N(n2816), .Y(n2742) );
INVX4TS U3489 ( .A(n3128), .Y(n2810) );
AOI22X1TS U3490 ( .A0(n2821), .A1(Data_array_SWR[28]), .B0(
Raw_mant_NRM_SWR[18]), .B1(n2756), .Y(n2746) );
AOI2BB2X1TS U3491 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[35]), .A0N(n2744),
.A1N(n2829), .Y(n2745) );
AOI22X1TS U3492 ( .A0(n3162), .A1(n1869), .B0(Raw_mant_NRM_SWR[36]), .B1(
n2756), .Y(n2749) );
AOI2BB2X1TS U3493 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[17]), .A0N(n2747),
.A1N(n2822), .Y(n2748) );
AOI22X1TS U3494 ( .A0(n2821), .A1(Data_array_SWR[12]), .B0(n1875), .B1(n2756), .Y(n2755) );
AOI2BB2X1TS U3495 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2763),
.A1N(n2753), .Y(n2754) );
AOI22X1TS U3496 ( .A0(n2795), .A1(Data_array_SWR[8]), .B0(
Raw_mant_NRM_SWR[43]), .B1(n2756), .Y(n2759) );
AOI2BB2X1TS U3497 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2757),
.A1N(n2829), .Y(n2758) );
AOI22X1TS U3498 ( .A0(n2795), .A1(Data_array_SWR[10]), .B0(n1875), .B1(n2805), .Y(n2762) );
AOI2BB2X1TS U3499 ( .B0(n1844), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2760),
.A1N(n2829), .Y(n2761) );
AOI22X1TS U3500 ( .A0(n3162), .A1(n1871), .B0(Raw_mant_NRM_SWR[35]), .B1(
n2805), .Y(n2766) );
AOI2BB2X1TS U3501 ( .B0(n1844), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2764),
.A1N(n2829), .Y(n2765) );
AOI22X1TS U3502 ( .A0(n2659), .A1(n1880), .B0(Raw_mant_NRM_SWR[26]), .B1(
n2805), .Y(n2769) );
AOI2BB2X1TS U3503 ( .B0(n1844), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2802),
.A1N(n2829), .Y(n2768) );
OAI211X1TS U3504 ( .A0(n2770), .A1(n2649), .B0(n2769), .C0(n2768), .Y(n1635)
);
AOI2BB2X1TS U3505 ( .B0(n1843), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2794),
.A1N(n2816), .Y(n2772) );
AOI22X1TS U3506 ( .A0(n3162), .A1(n1876), .B0(n1844), .B1(n1873), .Y(n2776)
);
AOI2BB2X1TS U3507 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[37]), .A0N(n2777),
.A1N(n2816), .Y(n2778) );
AOI22X1TS U3508 ( .A0(n2795), .A1(n1878), .B0(n1843), .B1(n1874), .Y(n2781)
);
AOI2BB2X1TS U3509 ( .B0(n1846), .B1(n1873), .A0N(n2785), .A1N(n2816), .Y(
n2780) );
AOI22X1TS U3510 ( .A0(n3162), .A1(n1877), .B0(n1844), .B1(n1870), .Y(n2784)
);
AOI22X1TS U3511 ( .A0(n3162), .A1(Data_array_SWR[37]), .B0(n1843), .B1(n1872), .Y(n2788) );
AOI2BB2X1TS U3512 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[47]), .A0N(n2786),
.A1N(n2822), .Y(n2787) );
AOI2BB2X1TS U3513 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[19]), .A0N(n2789),
.A1N(n2829), .Y(n2790) );
AOI22X1TS U3514 ( .A0(n2659), .A1(n1879), .B0(n1843), .B1(
DmP_mant_SHT1_SW[30]), .Y(n2793) );
AOI22X1TS U3515 ( .A0(n2795), .A1(Data_array_SWR[32]), .B0(n1843), .B1(
DmP_mant_SHT1_SW[37]), .Y(n2798) );
AOI2BB2X1TS U3516 ( .B0(n1845), .B1(n1870), .A0N(n2796), .A1N(n2816), .Y(
n2797) );
AOI2BB2X1TS U3517 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2827),
.A1N(n2816), .Y(n2800) );
AOI22X1TS U3518 ( .A0(n2821), .A1(Data_array_SWR[41]), .B0(
Raw_mant_NRM_SWR[0]), .B1(n2805), .Y(n2809) );
AOI22X1TS U3519 ( .A0(n2807), .A1(n2806), .B0(DmP_mant_SHT1_SW[49]), .B1(
n1843), .Y(n2808) );
AOI22X1TS U3520 ( .A0(n2659), .A1(Data_array_SWR[23]), .B0(n1843), .B1(
DmP_mant_SHT1_SW[26]), .Y(n2814) );
AOI2BB2X1TS U3521 ( .B0(n1846), .B1(DmP_mant_SHT1_SW[28]), .A0N(n2812),
.A1N(n2816), .Y(n2813) );
AOI22X1TS U3522 ( .A0(n2659), .A1(n1881), .B0(n1843), .B1(
DmP_mant_SHT1_SW[28]), .Y(n2819) );
AOI2BB2X1TS U3523 ( .B0(n1845), .B1(DmP_mant_SHT1_SW[30]), .A0N(n2817),
.A1N(n2816), .Y(n2818) );
AOI22X1TS U3524 ( .A0(n2821), .A1(Data_array_SWR[39]), .B0(
DmP_mant_SHT1_SW[47]), .B1(n1843), .Y(n2832) );
AOI2BB2X1TS U3525 ( .B0(DmP_mant_SHT1_SW[49]), .B1(n1845), .A0N(n2830),
.A1N(n2829), .Y(n2831) );
AO22XLTS U3526 ( .A0(n3223), .A1(OP_FLAG_SHT1), .B0(OP_FLAG_SHT2), .B1(n3194), .Y(n3434) );
AO22XLTS U3527 ( .A0(n3223), .A1(DMP_SHT1_EWSW[16]), .B0(DMP_SHT2_EWSW[16]),
.B1(n3194), .Y(n3435) );
AO22XLTS U3528 ( .A0(n3223), .A1(DMP_SHT1_EWSW[15]), .B0(DMP_SHT2_EWSW[15]),
.B1(n3194), .Y(n3436) );
AO22XLTS U3529 ( .A0(n3223), .A1(DMP_SHT1_EWSW[14]), .B0(DMP_SHT2_EWSW[14]),
.B1(n3194), .Y(n3437) );
AO22XLTS U3530 ( .A0(n3223), .A1(DMP_SHT1_EWSW[13]), .B0(DMP_SHT2_EWSW[13]),
.B1(n3194), .Y(n3438) );
AO22XLTS U3531 ( .A0(n3223), .A1(DMP_SHT1_EWSW[12]), .B0(DMP_SHT2_EWSW[12]),
.B1(n3194), .Y(n3439) );
INVX2TS U3532 ( .A(n2835), .Y(n2836) );
NAND2X1TS U3533 ( .A(n3351), .B(n2836), .Y(DP_OP_15J9_123_7955_n11) );
OAI2BB1X1TS U3534 ( .A0N(LZD_output_NRM2_EW[1]), .A1N(n3137), .B0(n2837),
.Y(n1130) );
XOR2X1TS U3535 ( .A(n2986), .B(DmP_mant_SFG_SWR[53]), .Y(n2985) );
XOR2X1TS U3536 ( .A(n2986), .B(DmP_mant_SFG_SWR[52]), .Y(n2979) );
XOR2X1TS U3537 ( .A(n2986), .B(DmP_mant_SFG_SWR[51]), .Y(n2982) );
XOR2X1TS U3538 ( .A(n2986), .B(DmP_mant_SFG_SWR[50]), .Y(n2991) );
XOR2X1TS U3539 ( .A(n2986), .B(DmP_mant_SFG_SWR[49]), .Y(n2853) );
XOR2X1TS U3540 ( .A(n2986), .B(DmP_mant_SFG_SWR[48]), .Y(n2994) );
XOR2X1TS U3541 ( .A(n2986), .B(DmP_mant_SFG_SWR[47]), .Y(n2997) );
XOR2X1TS U3542 ( .A(n2986), .B(DmP_mant_SFG_SWR[46]), .Y(n2973) );
XOR2X1TS U3543 ( .A(n2986), .B(DmP_mant_SFG_SWR[45]), .Y(n2976) );
XOR2X1TS U3544 ( .A(n2986), .B(DmP_mant_SFG_SWR[44]), .Y(n2970) );
BUFX4TS U3545 ( .A(OP_FLAG_SFG), .Y(n2838) );
XOR2X1TS U3546 ( .A(n2838), .B(DmP_mant_SFG_SWR[43]), .Y(n3000) );
XOR2X1TS U3547 ( .A(n2838), .B(DmP_mant_SFG_SWR[42]), .Y(n3003) );
XOR2X1TS U3548 ( .A(n2838), .B(DmP_mant_SFG_SWR[41]), .Y(n3006) );
XOR2X1TS U3549 ( .A(n2838), .B(DmP_mant_SFG_SWR[40]), .Y(n3009) );
XOR2X1TS U3550 ( .A(n2838), .B(DmP_mant_SFG_SWR[39]), .Y(n3012) );
XOR2X1TS U3551 ( .A(n2838), .B(DmP_mant_SFG_SWR[38]), .Y(n3019) );
XOR2X1TS U3552 ( .A(n2838), .B(DmP_mant_SFG_SWR[37]), .Y(n3015) );
XOR2X1TS U3553 ( .A(n2838), .B(DmP_mant_SFG_SWR[36]), .Y(n3022) );
XOR2X1TS U3554 ( .A(n2838), .B(DmP_mant_SFG_SWR[35]), .Y(n3025) );
XOR2X1TS U3555 ( .A(n2838), .B(DmP_mant_SFG_SWR[34]), .Y(n3028) );
XOR2X1TS U3556 ( .A(n2838), .B(DmP_mant_SFG_SWR[33]), .Y(n3031) );
XOR2X1TS U3557 ( .A(n2838), .B(DmP_mant_SFG_SWR[32]), .Y(n3034) );
XOR2X1TS U3558 ( .A(n2838), .B(DmP_mant_SFG_SWR[31]), .Y(n3037) );
XOR2X1TS U3559 ( .A(n2838), .B(DmP_mant_SFG_SWR[30]), .Y(n3040) );
XOR2X1TS U3560 ( .A(n2844), .B(DmP_mant_SFG_SWR[29]), .Y(n3058) );
XOR2X1TS U3561 ( .A(n2844), .B(DmP_mant_SFG_SWR[28]), .Y(n3043) );
XOR2X1TS U3562 ( .A(n2844), .B(DmP_mant_SFG_SWR[27]), .Y(n3061) );
XOR2X1TS U3563 ( .A(n2844), .B(DmP_mant_SFG_SWR[26]), .Y(n3064) );
XOR2X1TS U3564 ( .A(n2844), .B(DmP_mant_SFG_SWR[25]), .Y(n3068) );
XOR2X1TS U3565 ( .A(n2838), .B(DmP_mant_SFG_SWR[24]), .Y(n3071) );
XOR2X1TS U3566 ( .A(n2844), .B(DmP_mant_SFG_SWR[23]), .Y(n3074) );
XOR2X1TS U3567 ( .A(n2844), .B(DmP_mant_SFG_SWR[22]), .Y(n3077) );
XOR2X1TS U3568 ( .A(n2986), .B(DmP_mant_SFG_SWR[15]), .Y(n3105) );
NOR2X2TS U3569 ( .A(n2841), .B(DMP_SFG[15]), .Y(n3051) );
NAND2X1TS U3570 ( .A(n2841), .B(DMP_SFG[15]), .Y(n3052) );
OAI21X1TS U3571 ( .A0(n3051), .A1(n3099), .B0(n3052), .Y(n2842) );
NOR2X2TS U3572 ( .A(n2846), .B(DMP_SFG[17]), .Y(n3085) );
NAND2X1TS U3573 ( .A(n2846), .B(DMP_SFG[17]), .Y(n3086) );
INVX2TS U3574 ( .A(n3094), .Y(n2848) );
AFHCONX2TS U3575 ( .A(DMP_SFG[47]), .B(n2853), .CI(n2852), .CON(n2990), .S(
n2854) );
NOR2XLTS U3576 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2855) );
AOI32X4TS U3577 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n2855), .B1(n3390), .Y(n3138)
);
MXI2X1TS U3578 ( .A(n3218), .B(n1886), .S0(n3138), .Y(n1797) );
MX2X1TS U3579 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n3185), .Y(n1480) );
BUFX3TS U3580 ( .A(n2856), .Y(n3246) );
MX2X1TS U3581 ( .A(n2986), .B(OP_FLAG_SHT2), .S0(n3246), .Y(n1190) );
MX2X1TS U3582 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n3246), .Y(n1483) );
MX2X1TS U3583 ( .A(DMP_SFG[51]), .B(DMP_SHT2_EWSW[51]), .S0(n3258), .Y(n1366) );
MX2X1TS U3584 ( .A(DMP_SFG[50]), .B(DMP_SHT2_EWSW[50]), .S0(n2858), .Y(n1369) );
MX2X1TS U3585 ( .A(DMP_SFG[49]), .B(DMP_SHT2_EWSW[49]), .S0(n2883), .Y(n1372) );
BUFX3TS U3586 ( .A(n2856), .Y(n3217) );
MX2X1TS U3587 ( .A(DMP_SFG[48]), .B(DMP_SHT2_EWSW[48]), .S0(n2858), .Y(n1375) );
MX2X1TS U3588 ( .A(DMP_SFG[46]), .B(DMP_SHT2_EWSW[46]), .S0(n3246), .Y(n1381) );
MX2X1TS U3589 ( .A(DMP_SFG[44]), .B(DMP_SHT2_EWSW[44]), .S0(n2883), .Y(n1387) );
MX2X1TS U3590 ( .A(DMP_SFG[42]), .B(DMP_SHT2_EWSW[42]), .S0(n2858), .Y(n1393) );
BUFX3TS U3591 ( .A(n2856), .Y(n3258) );
MX2X1TS U3592 ( .A(DMP_SFG[40]), .B(DMP_SHT2_EWSW[40]), .S0(n3246), .Y(n1399) );
MX2X1TS U3593 ( .A(DMP_SFG[38]), .B(DMP_SHT2_EWSW[38]), .S0(n3198), .Y(n1405) );
MX2X1TS U3594 ( .A(DMP_SFG[36]), .B(DMP_SHT2_EWSW[36]), .S0(n2858), .Y(n1411) );
MX2X1TS U3595 ( .A(DMP_SFG[35]), .B(DMP_SHT2_EWSW[35]), .S0(n3258), .Y(n1414) );
MX2X1TS U3596 ( .A(DMP_SFG[34]), .B(DMP_SHT2_EWSW[34]), .S0(n2883), .Y(n1417) );
MX2X1TS U3597 ( .A(DMP_SFG[33]), .B(DMP_SHT2_EWSW[33]), .S0(n2856), .Y(n1420) );
MX2X1TS U3598 ( .A(DMP_SFG[32]), .B(DMP_SHT2_EWSW[32]), .S0(n3246), .Y(n1423) );
MX2X1TS U3599 ( .A(DMP_SFG[31]), .B(DMP_SHT2_EWSW[31]), .S0(n3198), .Y(n1426) );
MX2X1TS U3600 ( .A(DMP_SFG[30]), .B(DMP_SHT2_EWSW[30]), .S0(n3217), .Y(n1429) );
MX2X1TS U3601 ( .A(DMP_SFG[29]), .B(DMP_SHT2_EWSW[29]), .S0(n3217), .Y(n1432) );
MX2X1TS U3602 ( .A(DMP_SFG[28]), .B(DMP_SHT2_EWSW[28]), .S0(n3185), .Y(n1435) );
MX2X1TS U3603 ( .A(DMP_SFG[27]), .B(DMP_SHT2_EWSW[27]), .S0(n3217), .Y(n1438) );
MX2X1TS U3604 ( .A(DMP_SFG[26]), .B(DMP_SHT2_EWSW[26]), .S0(n3185), .Y(n1441) );
MX2X1TS U3605 ( .A(DMP_SFG[25]), .B(DMP_SHT2_EWSW[25]), .S0(n2856), .Y(n1444) );
MX2X1TS U3606 ( .A(DMP_SFG[24]), .B(DMP_SHT2_EWSW[24]), .S0(n2856), .Y(n1447) );
MX2X1TS U3607 ( .A(DMP_SFG[23]), .B(DMP_SHT2_EWSW[23]), .S0(n2856), .Y(n1450) );
MX2X1TS U3608 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n2856), .Y(n1453) );
MX2X1TS U3609 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n2857), .Y(n1456) );
MX2X1TS U3610 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n3217), .Y(n1459) );
MX2X1TS U3611 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n3198), .Y(n1462) );
MX2X1TS U3612 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n3246), .Y(n1465) );
MX2X1TS U3613 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n3185), .Y(n1468) );
MX2X1TS U3614 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n3217), .Y(n1471) );
MX2X1TS U3615 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n3185), .Y(n1474) );
MX2X1TS U3616 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n3185), .Y(n1477) );
NAND2X1TS U3617 ( .A(n2910), .B(n1804), .Y(n2876) );
OAI22X1TS U3618 ( .A0(n2859), .A1(n2915), .B0(n3408), .B1(n2876), .Y(n2860)
);
INVX4TS U3619 ( .A(n3246), .Y(n3259) );
MX2X1TS U3620 ( .A(n2860), .B(DmP_mant_SFG_SWR[54]), .S0(n3259), .Y(n1016)
);
OAI22X1TS U3621 ( .A0(n2861), .A1(n1804), .B0(n3407), .B1(n2876), .Y(n3279)
);
MX2X1TS U3622 ( .A(n3279), .B(DmP_mant_SFG_SWR[53]), .S0(n3259), .Y(n1017)
);
AOI22X1TS U3623 ( .A0(n1881), .A1(n2103), .B0(Data_array_SWR[21]), .B1(n2884), .Y(n2863) );
AOI22X1TS U3624 ( .A0(Data_array_SWR[18]), .A1(n2909), .B0(
Data_array_SWR[14]), .B1(n2896), .Y(n2862) );
AOI21X1TS U3625 ( .A0(n2863), .A1(n2862), .B0(n2939), .Y(n2868) );
AOI22X1TS U3626 ( .A0(Data_array_SWR[12]), .A1(n2895), .B0(Data_array_SWR[2]), .B1(n2910), .Y(n2865) );
AOI22X1TS U3627 ( .A0(Data_array_SWR[8]), .A1(n2934), .B0(n1866), .B1(n2106),
.Y(n2864) );
AOI211X1TS U3628 ( .A0(n2914), .A1(n2869), .B0(n2868), .C0(n2867), .Y(n3228)
);
OAI22X1TS U3629 ( .A0(n3228), .A1(n2915), .B0(n1826), .B1(n2876), .Y(n3277)
);
MX2X1TS U3630 ( .A(n3277), .B(DmP_mant_SFG_SWR[52]), .S0(n3259), .Y(n1018)
);
AOI22X1TS U3631 ( .A0(Data_array_SWR[25]), .A1(n2885), .B0(
Data_array_SWR[22]), .B1(n2884), .Y(n2872) );
AOI22X1TS U3632 ( .A0(Data_array_SWR[13]), .A1(n2936), .B0(Data_array_SWR[9]), .B1(n2886), .Y(n2871) );
AOI22X1TS U3633 ( .A0(Data_array_SWR[19]), .A1(n2897), .B0(
Data_array_SWR[15]), .B1(n2896), .Y(n2870) );
AOI32X1TS U3634 ( .A0(n2872), .A1(n2871), .A2(n2870), .B0(n2111), .B1(n2871),
.Y(n2873) );
OAI22X1TS U3635 ( .A0(n3233), .A1(n2915), .B0(n3395), .B1(n2876), .Y(n3276)
);
AO22XLTS U3636 ( .A0(Data_array_SWR[6]), .A1(n2106), .B0(n1865), .B1(n2910),
.Y(n2881) );
AOI22X1TS U3637 ( .A0(n1879), .A1(n2885), .B0(Data_array_SWR[23]), .B1(n2884), .Y(n2879) );
AOI22X1TS U3638 ( .A0(n1871), .A1(n2936), .B0(Data_array_SWR[10]), .B1(n2886), .Y(n2878) );
AOI22X1TS U3639 ( .A0(Data_array_SWR[20]), .A1(n2897), .B0(
Data_array_SWR[16]), .B1(n2896), .Y(n2877) );
AOI32X1TS U3640 ( .A0(n2879), .A1(n2878), .A2(n2877), .B0(n2111), .B1(n2878),
.Y(n2880) );
OAI22X1TS U3641 ( .A0(n3235), .A1(n2915), .B0(n3234), .B1(n2966), .Y(n3270)
);
INVX4TS U3642 ( .A(n3198), .Y(n2968) );
AO22XLTS U3643 ( .A0(Data_array_SWR[7]), .A1(n2106), .B0(Data_array_SWR[4]),
.B1(n2910), .Y(n2892) );
AOI22X1TS U3644 ( .A0(Data_array_SWR[26]), .A1(n2885), .B0(
Data_array_SWR[24]), .B1(n2884), .Y(n2890) );
AOI22X1TS U3645 ( .A0(n1869), .A1(n2936), .B0(Data_array_SWR[11]), .B1(n2886), .Y(n2889) );
AOI22X1TS U3646 ( .A0(Data_array_SWR[17]), .A1(n2905), .B0(n1880), .B1(n2887), .Y(n2888) );
AOI32X1TS U3647 ( .A0(n2890), .A1(n2889), .A2(n2888), .B0(n2111), .B1(n2889),
.Y(n2891) );
AOI211X1TS U3648 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2893), .B0(n2892),
.C0(n2891), .Y(n3229) );
OAI22X1TS U3649 ( .A0(n3229), .A1(n1804), .B0(n3231), .B1(n2966), .Y(n3274)
);
AO22XLTS U3650 ( .A0(Data_array_SWR[8]), .A1(n2106), .B0(n1866), .B1(n2910),
.Y(n2902) );
AOI22X1TS U3651 ( .A0(n1881), .A1(n2904), .B0(Data_array_SWR[27]), .B1(n2103), .Y(n2900) );
AOI22X1TS U3652 ( .A0(Data_array_SWR[12]), .A1(n2934), .B0(
Data_array_SWR[14]), .B1(n2895), .Y(n2899) );
AOI22X1TS U3653 ( .A0(Data_array_SWR[21]), .A1(n2897), .B0(
Data_array_SWR[18]), .B1(n2896), .Y(n2898) );
AOI32X1TS U3654 ( .A0(n2900), .A1(n2899), .A2(n2898), .B0(n2111), .B1(n2899),
.Y(n2901) );
OAI22X1TS U3655 ( .A0(n3237), .A1(n2915), .B0(n3236), .B1(n2966), .Y(n3268)
);
AOI22X1TS U3656 ( .A0(Data_array_SWR[19]), .A1(n2905), .B0(
Data_array_SWR[25]), .B1(n2904), .Y(n2906) );
AOI22X1TS U3657 ( .A0(Data_array_SWR[13]), .A1(n2934), .B0(Data_array_SWR[9]), .B1(n2106), .Y(n2912) );
AOI22X1TS U3658 ( .A0(Data_array_SWR[15]), .A1(n2936), .B0(Data_array_SWR[5]), .B1(n2910), .Y(n2911) );
AOI21X1TS U3659 ( .A0(n2914), .A1(n2963), .B0(n2913), .Y(n3240) );
OAI22X1TS U3660 ( .A0(n3240), .A1(n2915), .B0(n3239), .B1(n2966), .Y(n3266)
);
MX2X1TS U3661 ( .A(n3266), .B(DmP_mant_SFG_SWR[47]), .S0(n2968), .Y(n1023)
);
OAI22X1TS U3662 ( .A0(n2916), .A1(n2915), .B0(n2923), .B1(n2966), .Y(n3264)
);
MX2X1TS U3663 ( .A(n3264), .B(DmP_mant_SFG_SWR[46]), .S0(n2968), .Y(n1024)
);
MX2X1TS U3664 ( .A(n2917), .B(DmP_mant_SFG_SWR[45]), .S0(n2968), .Y(n1025)
);
MX2X1TS U3665 ( .A(n2918), .B(DmP_mant_SFG_SWR[44]), .S0(n2968), .Y(n1026)
);
MX2X1TS U3666 ( .A(n2920), .B(DmP_mant_SFG_SWR[43]), .S0(n2919), .Y(n1027)
);
AOI22X1TS U3667 ( .A0(n2929), .A1(n2961), .B0(n2960), .B1(n2963), .Y(n2922)
);
INVX2TS U3668 ( .A(n3239), .Y(n2959) );
NAND2X1TS U3669 ( .A(n2143), .B(n2959), .Y(n2921) );
OAI211X1TS U3670 ( .A0(n2967), .A1(n3238), .B0(n2922), .C0(n2921), .Y(n3262)
);
MX2X1TS U3671 ( .A(n3262), .B(DmP_mant_SFG_SWR[31]), .S0(n2968), .Y(n1039)
);
AOI22X1TS U3672 ( .A0(n2929), .A1(n2954), .B0(n2960), .B1(n2955), .Y(n2925)
);
INVX2TS U3673 ( .A(n2923), .Y(n2953) );
NAND2X1TS U3674 ( .A(n2143), .B(n2953), .Y(n2924) );
MX2X1TS U3675 ( .A(n3254), .B(DmP_mant_SFG_SWR[30]), .S0(n3259), .Y(n1040)
);
AOI22X1TS U3676 ( .A0(n2929), .A1(n2948), .B0(n2960), .B1(n2949), .Y(n2928)
);
INVX2TS U3677 ( .A(n2926), .Y(n2947) );
NAND2X1TS U3678 ( .A(n2143), .B(n2947), .Y(n2927) );
OAI211X1TS U3679 ( .A0(n2952), .A1(n3238), .B0(n2928), .C0(n2927), .Y(n3250)
);
MX2X1TS U3680 ( .A(n3250), .B(DmP_mant_SFG_SWR[29]), .S0(n2968), .Y(n1041)
);
AOI22X1TS U3681 ( .A0(n2929), .A1(n2942), .B0(n2960), .B1(n2943), .Y(n2932)
);
INVX2TS U3682 ( .A(n2930), .Y(n2941) );
NAND2X1TS U3683 ( .A(n2143), .B(n2941), .Y(n2931) );
OAI211X1TS U3684 ( .A0(n2946), .A1(n3238), .B0(n2932), .C0(n2931), .Y(n3256)
);
MX2X1TS U3685 ( .A(n3256), .B(DmP_mant_SFG_SWR[28]), .S0(n2968), .Y(n1042)
);
AOI22X1TS U3686 ( .A0(Data_array_SWR[28]), .A1(n2934), .B0(
Data_array_SWR[22]), .B1(n2933), .Y(n2938) );
AOI22X1TS U3687 ( .A0(Data_array_SWR[32]), .A1(n2936), .B0(
Data_array_SWR[25]), .B1(n2935), .Y(n2937) );
OAI211X1TS U3688 ( .A0(n2940), .A1(n2939), .B0(n2938), .C0(n2937), .Y(n3260)
);
MX2X1TS U3689 ( .A(n3260), .B(DmP_mant_SFG_SWR[27]), .S0(n2968), .Y(n1043)
);
AOI22X1TS U3690 ( .A0(n2962), .A1(n2942), .B0(n2960), .B1(n2941), .Y(n2945)
);
NAND2X1TS U3691 ( .A(n2143), .B(n2943), .Y(n2944) );
MX2X1TS U3692 ( .A(n3255), .B(DmP_mant_SFG_SWR[26]), .S0(n2968), .Y(n1044)
);
AOI22X1TS U3693 ( .A0(n2962), .A1(n2948), .B0(n2960), .B1(n2947), .Y(n2951)
);
NAND2X1TS U3694 ( .A(n2143), .B(n2949), .Y(n2950) );
OAI211X1TS U3695 ( .A0(n2952), .A1(n2966), .B0(n2951), .C0(n2950), .Y(n3248)
);
MX2X1TS U3696 ( .A(n3248), .B(DmP_mant_SFG_SWR[25]), .S0(n2968), .Y(n1045)
);
AOI22X1TS U3697 ( .A0(n2962), .A1(n2954), .B0(n2960), .B1(n2953), .Y(n2957)
);
NAND2X1TS U3698 ( .A(n2143), .B(n2955), .Y(n2956) );
MX2X1TS U3699 ( .A(n3253), .B(DmP_mant_SFG_SWR[24]), .S0(n2968), .Y(n1046)
);
AOI22X1TS U3700 ( .A0(n2962), .A1(n2961), .B0(n2960), .B1(n2959), .Y(n2965)
);
NAND2X1TS U3701 ( .A(n2143), .B(n2963), .Y(n2964) );
OAI211X1TS U3702 ( .A0(n2967), .A1(n2966), .B0(n2965), .C0(n2964), .Y(n3261)
);
MX2X1TS U3703 ( .A(n3261), .B(DmP_mant_SFG_SWR[23]), .S0(n2968), .Y(n1047)
);
AFHCINX2TS U3704 ( .CIN(n2969), .B(n2970), .A(DMP_SFG[42]), .S(n2971), .CO(
n2975) );
INVX4TS U3705 ( .A(n3218), .Y(n3065) );
AFHCINX2TS U3706 ( .CIN(n2972), .B(n2973), .A(DMP_SFG[44]), .S(n2974), .CO(
n2996) );
AFHCONX2TS U3707 ( .A(DMP_SFG[43]), .B(n2976), .CI(n2975), .CON(n2972), .S(
n2977) );
XOR2X1TS U3708 ( .A(n2986), .B(DmP_mant_SFG_SWR[54]), .Y(n2987) );
XNOR2X1TS U3709 ( .A(n2988), .B(n2987), .Y(n2989) );
AFHCINX2TS U3710 ( .CIN(n2990), .B(n2991), .A(DMP_SFG[48]), .S(n2992), .CO(
n2981) );
AFHCINX2TS U3711 ( .CIN(n2993), .B(n2994), .A(DMP_SFG[46]), .S(n2995), .CO(
n2852) );
AFHCONX2TS U3712 ( .A(DMP_SFG[45]), .B(n2997), .CI(n2996), .CON(n2993), .S(
n2998) );
AFHCONX2TS U3713 ( .A(DMP_SFG[41]), .B(n3000), .CI(n2999), .CON(n2969), .S(
n3001) );
AFHCINX2TS U3714 ( .CIN(n3002), .B(n3003), .A(DMP_SFG[40]), .S(n3004), .CO(
n2999) );
AFHCONX2TS U3715 ( .A(DMP_SFG[39]), .B(n3006), .CI(n3005), .CON(n3002), .S(
n3007) );
AFHCINX2TS U3716 ( .CIN(n3008), .B(n3009), .A(DMP_SFG[38]), .S(n3010), .CO(
n3005) );
AFHCONX2TS U3717 ( .A(DMP_SFG[37]), .B(n3012), .CI(n3011), .CON(n3008), .S(
n3013) );
AFHCONX2TS U3718 ( .A(DMP_SFG[35]), .B(n3015), .CI(n3014), .CON(n3018), .S(
n3017) );
AFHCINX2TS U3719 ( .CIN(n3018), .B(n3019), .A(DMP_SFG[36]), .S(n3020), .CO(
n3011) );
AFHCINX2TS U3720 ( .CIN(n3021), .B(n3022), .A(DMP_SFG[34]), .S(n3023), .CO(
n3014) );
AFHCONX2TS U3721 ( .A(DMP_SFG[33]), .B(n3025), .CI(n3024), .CON(n3021), .S(
n3026) );
AFHCINX2TS U3722 ( .CIN(n3027), .B(n3028), .A(DMP_SFG[32]), .S(n3029), .CO(
n3024) );
AFHCONX2TS U3723 ( .A(DMP_SFG[31]), .B(n3031), .CI(n3030), .CON(n3027), .S(
n3032) );
AFHCINX2TS U3724 ( .CIN(n3033), .B(n3034), .A(DMP_SFG[30]), .S(n3035), .CO(
n3030) );
AFHCONX2TS U3725 ( .A(DMP_SFG[29]), .B(n3037), .CI(n3036), .CON(n3033), .S(
n3038) );
AFHCINX2TS U3726 ( .CIN(n3039), .B(n3040), .A(DMP_SFG[28]), .S(n3041), .CO(
n3036) );
MX2X1TS U3727 ( .A(Raw_mant_NRM_SWR[30]), .B(n3041), .S0(n3065), .Y(n1168)
);
AFHCINX2TS U3728 ( .CIN(n3042), .B(n3043), .A(DMP_SFG[26]), .S(n3044), .CO(
n3057) );
MX2X1TS U3729 ( .A(Raw_mant_NRM_SWR[28]), .B(n3044), .S0(n3065), .Y(n1170)
);
NAND2X1TS U3730 ( .A(n3084), .B(n3082), .Y(n3047) );
XNOR2X1TS U3731 ( .A(n3093), .B(n3047), .Y(n3048) );
MX2X1TS U3732 ( .A(Raw_mant_NRM_SWR[18]), .B(n3048), .S0(n3065), .Y(n1180)
);
AOI21X1TS U3733 ( .A0(n3102), .A1(n3100), .B0(n3050), .Y(n3055) );
NAND2X1TS U3734 ( .A(n3053), .B(n3052), .Y(n3054) );
XOR2XLTS U3735 ( .A(n3055), .B(n3054), .Y(n3056) );
MX2X1TS U3736 ( .A(Raw_mant_NRM_SWR[17]), .B(n3056), .S0(n3065), .Y(n1181)
);
AFHCONX2TS U3737 ( .A(DMP_SFG[27]), .B(n3058), .CI(n3057), .CON(n3039), .S(
n3059) );
MX2X1TS U3738 ( .A(Raw_mant_NRM_SWR[29]), .B(n3059), .S0(n3065), .Y(n1169)
);
AFHCONX2TS U3739 ( .A(DMP_SFG[25]), .B(n3061), .CI(n3060), .CON(n3042), .S(
n3062) );
MX2X1TS U3740 ( .A(Raw_mant_NRM_SWR[27]), .B(n3062), .S0(n3065), .Y(n1171)
);
AFHCINX2TS U3741 ( .CIN(n3063), .B(n3064), .A(DMP_SFG[24]), .S(n3066), .CO(
n3060) );
MX2X1TS U3742 ( .A(Raw_mant_NRM_SWR[26]), .B(n3066), .S0(n3065), .Y(n1172)
);
AFHCONX2TS U3743 ( .A(DMP_SFG[23]), .B(n3068), .CI(n3067), .CON(n3063), .S(
n3069) );
MX2X1TS U3744 ( .A(Raw_mant_NRM_SWR[25]), .B(n3069), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1173) );
AFHCINX2TS U3745 ( .CIN(n3070), .B(n3071), .A(DMP_SFG[22]), .S(n3072), .CO(
n3067) );
MX2X1TS U3746 ( .A(Raw_mant_NRM_SWR[24]), .B(n3072), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1174) );
AFHCONX2TS U3747 ( .A(DMP_SFG[21]), .B(n3074), .CI(n3073), .CON(n3070), .S(
n3075) );
MX2X1TS U3748 ( .A(Raw_mant_NRM_SWR[23]), .B(n3075), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1175) );
AFHCINX2TS U3749 ( .CIN(n3076), .B(n3077), .A(DMP_SFG[20]), .S(n3078), .CO(
n3073) );
MX2X1TS U3750 ( .A(Raw_mant_NRM_SWR[22]), .B(n3078), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1176) );
AFHCONX2TS U3751 ( .A(DMP_SFG[19]), .B(n3080), .CI(n3079), .CON(n3076), .S(
n3081) );
MX2X1TS U3752 ( .A(Raw_mant_NRM_SWR[21]), .B(n3081), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1177) );
AOI21X1TS U3753 ( .A0(n3093), .A1(n3084), .B0(n3083), .Y(n3089) );
NAND2X1TS U3754 ( .A(n3087), .B(n3086), .Y(n3088) );
XOR2XLTS U3755 ( .A(n3089), .B(n3088), .Y(n3090) );
MX2X1TS U3756 ( .A(Raw_mant_NRM_SWR[19]), .B(n3090), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1179) );
AOI21X1TS U3757 ( .A0(n3093), .A1(n3092), .B0(n3091), .Y(n3097) );
NAND2X1TS U3758 ( .A(n3095), .B(n3094), .Y(n3096) );
XOR2XLTS U3759 ( .A(n3097), .B(n3096), .Y(n3098) );
MX2X1TS U3760 ( .A(Raw_mant_NRM_SWR[20]), .B(n3098), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1178) );
NAND2X1TS U3761 ( .A(n3100), .B(n3099), .Y(n3101) );
XNOR2X1TS U3762 ( .A(n3102), .B(n3101), .Y(n3103) );
MX2X1TS U3763 ( .A(Raw_mant_NRM_SWR[16]), .B(n3103), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1182) );
MX2X1TS U3764 ( .A(Raw_mant_NRM_SWR[15]), .B(n3107), .S0(
Shift_reg_FLAGS_7[2]), .Y(n1183) );
MX2X1TS U3765 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1311) );
MX2X1TS U3766 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1316) );
MX2X1TS U3767 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1321) );
MX2X1TS U3768 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1326) );
MX2X1TS U3769 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1331) );
MX2X1TS U3770 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n1885),
.Y(n1336) );
MX2X1TS U3771 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1885),
.Y(n1341) );
MX2X1TS U3772 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1885),
.Y(n1346) );
MX2X1TS U3773 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1885),
.Y(n1351) );
MX2X1TS U3774 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1885),
.Y(n1356) );
MX2X1TS U3775 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1885),
.Y(n1361) );
OAI2BB1X1TS U3776 ( .A0N(LZD_output_NRM2_EW[5]), .A1N(n3137), .B0(n3108),
.Y(n1141) );
OAI2BB1X1TS U3777 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n3137), .B0(n3109),
.Y(n1135) );
NOR3BX1TS U3778 ( .AN(n3111), .B(n3110), .C(Raw_mant_NRM_SWR[47]), .Y(n3119)
);
OAI2BB2XLTS U3779 ( .B0(n3419), .B1(n3113), .A0N(Raw_mant_NRM_SWR[24]),
.A1N(n3112), .Y(n3117) );
OAI22X1TS U3780 ( .A0(n3292), .A1(n3115), .B0(n3423), .B1(n3114), .Y(n3116)
);
NOR4X1TS U3781 ( .A(n3119), .B(n3118), .C(n3117), .D(n3116), .Y(n3121) );
OAI21X1TS U3782 ( .A0(n3126), .A1(n3125), .B0(Shift_reg_FLAGS_7[1]), .Y(
n3163) );
OAI2BB1X1TS U3783 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n3137), .B0(n3163),
.Y(n1125) );
OAI2BB1X1TS U3784 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n3137), .B0(n3127),
.Y(n1122) );
OAI2BB1X1TS U3785 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n3137), .B0(n3128),
.Y(n1138) );
INVX4TS U3786 ( .A(n3247), .Y(n3280) );
INVX2TS U3787 ( .A(n3130), .Y(n3132) );
AOI22X1TS U3788 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n3132), .B1(n3304), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U3789 ( .A(n3132), .B(n3131), .Y(n1803) );
INVX2TS U3790 ( .A(n3138), .Y(n3135) );
AO22XLTS U3791 ( .A0(n3135), .A1(n3211), .B0(n3138), .B1(n3133), .Y(n1801)
);
AOI22X1TS U3792 ( .A0(n3138), .A1(n3134), .B0(n3208), .B1(n3135), .Y(n1800)
);
AOI22X1TS U3793 ( .A0(n3138), .A1(n3208), .B0(n3189), .B1(n3135), .Y(n1799)
);
AO22XLTS U3794 ( .A0(n3138), .A1(busy), .B0(n3135), .B1(Shift_reg_FLAGS_7[3]), .Y(n1798) );
AOI22X1TS U3795 ( .A0(n3138), .A1(n3218), .B0(n3137), .B1(n3135), .Y(n1796)
);
AOI22X1TS U3796 ( .A0(n3138), .A1(n3137), .B0(n3219), .B1(n3135), .Y(n1795)
);
CLKBUFX2TS U3797 ( .A(n3140), .Y(n3160) );
INVX2TS U3798 ( .A(n3139), .Y(n3150) );
AO22XLTS U3799 ( .A0(n3156), .A1(Data_X[3]), .B0(n3150), .B1(intDX_EWSW[3]),
.Y(n1791) );
AO22XLTS U3800 ( .A0(n3143), .A1(Data_X[8]), .B0(n3142), .B1(intDX_EWSW[8]),
.Y(n1786) );
AO22XLTS U3801 ( .A0(n3156), .A1(Data_X[11]), .B0(n3142), .B1(intDX_EWSW[11]), .Y(n1783) );
BUFX3TS U3802 ( .A(n3146), .Y(n3145) );
AO22XLTS U3803 ( .A0(n3143), .A1(Data_X[25]), .B0(n3141), .B1(intDX_EWSW[25]), .Y(n1769) );
AO22XLTS U3804 ( .A0(n3143), .A1(Data_X[26]), .B0(n3141), .B1(intDX_EWSW[26]), .Y(n1768) );
AO22XLTS U3805 ( .A0(n3143), .A1(Data_X[27]), .B0(n3141), .B1(intDX_EWSW[27]), .Y(n1767) );
AO22XLTS U3806 ( .A0(n3143), .A1(Data_X[28]), .B0(n3141), .B1(intDX_EWSW[28]), .Y(n1766) );
AO22XLTS U3807 ( .A0(n3143), .A1(Data_X[29]), .B0(n3141), .B1(intDX_EWSW[29]), .Y(n1765) );
AO22XLTS U3808 ( .A0(n3143), .A1(Data_X[30]), .B0(n3141), .B1(intDX_EWSW[30]), .Y(n1764) );
INVX4TS U3809 ( .A(n3160), .Y(n3144) );
AO22XLTS U3810 ( .A0(n3143), .A1(Data_X[31]), .B0(n3144), .B1(intDX_EWSW[31]), .Y(n1763) );
INVX4TS U3811 ( .A(n3160), .Y(n3148) );
AO22XLTS U3812 ( .A0(n3156), .A1(Data_X[33]), .B0(n3141), .B1(intDX_EWSW[33]), .Y(n1761) );
AO22XLTS U3813 ( .A0(n3156), .A1(Data_X[34]), .B0(n3144), .B1(intDX_EWSW[34]), .Y(n1760) );
AO22XLTS U3814 ( .A0(n3156), .A1(Data_X[35]), .B0(n3142), .B1(intDX_EWSW[35]), .Y(n1759) );
AO22XLTS U3815 ( .A0(n3156), .A1(Data_X[36]), .B0(n3141), .B1(intDX_EWSW[36]), .Y(n1758) );
INVX4TS U3816 ( .A(n3160), .Y(n3147) );
AO22XLTS U3817 ( .A0(n3143), .A1(Data_X[46]), .B0(n3157), .B1(intDX_EWSW[46]), .Y(n1748) );
AO22XLTS U3818 ( .A0(n3156), .A1(Data_X[50]), .B0(n3157), .B1(intDX_EWSW[50]), .Y(n1744) );
AO22XLTS U3819 ( .A0(n3156), .A1(Data_X[51]), .B0(n3157), .B1(intDX_EWSW[51]), .Y(n1743) );
AO22XLTS U3820 ( .A0(n3156), .A1(Data_X[57]), .B0(n3157), .B1(intDX_EWSW[57]), .Y(n1737) );
AO22XLTS U3821 ( .A0(n3144), .A1(intDX_EWSW[60]), .B0(n3146), .B1(Data_X[60]), .Y(n1734) );
AO22XLTS U3822 ( .A0(n3156), .A1(add_subt), .B0(n3157), .B1(intAS), .Y(n1730) );
AO22XLTS U3823 ( .A0(n3159), .A1(intDY_EWSW[4]), .B0(n3152), .B1(Data_Y[4]),
.Y(n1724) );
AO22XLTS U3824 ( .A0(n3144), .A1(intDY_EWSW[11]), .B0(n3153), .B1(Data_Y[11]), .Y(n1717) );
AO22XLTS U3825 ( .A0(n3147), .A1(intDY_EWSW[14]), .B0(n3146), .B1(Data_Y[14]), .Y(n1714) );
AO22XLTS U3826 ( .A0(n3147), .A1(intDY_EWSW[15]), .B0(n3153), .B1(Data_Y[15]), .Y(n1713) );
AO22XLTS U3827 ( .A0(n3147), .A1(intDY_EWSW[17]), .B0(n3153), .B1(Data_Y[17]), .Y(n1711) );
AO22XLTS U3828 ( .A0(n3147), .A1(intDY_EWSW[18]), .B0(n3153), .B1(Data_Y[18]), .Y(n1710) );
BUFX3TS U3829 ( .A(n3140), .Y(n3154) );
AO22XLTS U3830 ( .A0(n3147), .A1(intDY_EWSW[19]), .B0(n3154), .B1(Data_Y[19]), .Y(n1709) );
AO22XLTS U3831 ( .A0(n3148), .A1(intDY_EWSW[20]), .B0(n3153), .B1(Data_Y[20]), .Y(n1708) );
AO22XLTS U3832 ( .A0(n3147), .A1(intDY_EWSW[21]), .B0(n3153), .B1(Data_Y[21]), .Y(n1707) );
AO22XLTS U3833 ( .A0(n3148), .A1(intDY_EWSW[22]), .B0(n3146), .B1(Data_Y[22]), .Y(n1706) );
AO22XLTS U3834 ( .A0(n3147), .A1(intDY_EWSW[23]), .B0(n3154), .B1(Data_Y[23]), .Y(n1705) );
AO22XLTS U3835 ( .A0(n3148), .A1(intDY_EWSW[24]), .B0(n3154), .B1(Data_Y[24]), .Y(n1704) );
AO22XLTS U3836 ( .A0(n3148), .A1(intDY_EWSW[25]), .B0(n3154), .B1(Data_Y[25]), .Y(n1703) );
AO22XLTS U3837 ( .A0(n3148), .A1(intDY_EWSW[26]), .B0(n3153), .B1(Data_Y[26]), .Y(n1702) );
AO22XLTS U3838 ( .A0(n3148), .A1(intDY_EWSW[28]), .B0(n3154), .B1(Data_Y[28]), .Y(n1700) );
AO22XLTS U3839 ( .A0(n3148), .A1(intDY_EWSW[29]), .B0(n3154), .B1(Data_Y[29]), .Y(n1699) );
INVX4TS U3840 ( .A(n3158), .Y(n3155) );
AO22XLTS U3841 ( .A0(n3148), .A1(intDY_EWSW[35]), .B0(n3153), .B1(Data_Y[35]), .Y(n1693) );
AO22XLTS U3842 ( .A0(n3150), .A1(intDY_EWSW[39]), .B0(n3154), .B1(Data_Y[39]), .Y(n1689) );
AO22XLTS U3843 ( .A0(n3159), .A1(intDY_EWSW[40]), .B0(n3153), .B1(Data_Y[40]), .Y(n1688) );
AO22XLTS U3844 ( .A0(n3151), .A1(intDY_EWSW[42]), .B0(n3153), .B1(Data_Y[42]), .Y(n1686) );
AO22XLTS U3845 ( .A0(n3159), .A1(intDY_EWSW[43]), .B0(n3154), .B1(Data_Y[43]), .Y(n1685) );
AO22XLTS U3846 ( .A0(n3155), .A1(intDY_EWSW[44]), .B0(n3154), .B1(Data_Y[44]), .Y(n1684) );
AO22XLTS U3847 ( .A0(n3157), .A1(intDY_EWSW[45]), .B0(n3152), .B1(Data_Y[45]), .Y(n1683) );
AO22XLTS U3848 ( .A0(n3155), .A1(intDY_EWSW[46]), .B0(n3152), .B1(Data_Y[46]), .Y(n1682) );
AO22XLTS U3849 ( .A0(n3151), .A1(intDY_EWSW[47]), .B0(n3154), .B1(Data_Y[47]), .Y(n1681) );
AO22XLTS U3850 ( .A0(n3155), .A1(intDY_EWSW[48]), .B0(n3153), .B1(Data_Y[48]), .Y(n1680) );
AO22XLTS U3851 ( .A0(n3155), .A1(intDY_EWSW[49]), .B0(n3152), .B1(Data_Y[49]), .Y(n1679) );
AO22XLTS U3852 ( .A0(n3155), .A1(intDY_EWSW[50]), .B0(n3153), .B1(Data_Y[50]), .Y(n1678) );
AO22XLTS U3853 ( .A0(n3155), .A1(intDY_EWSW[51]), .B0(n3154), .B1(Data_Y[51]), .Y(n1677) );
AO22XLTS U3854 ( .A0(n3155), .A1(intDY_EWSW[52]), .B0(n3153), .B1(Data_Y[52]), .Y(n1676) );
AO22XLTS U3855 ( .A0(n3155), .A1(intDY_EWSW[53]), .B0(n3152), .B1(Data_Y[53]), .Y(n1675) );
AO22XLTS U3856 ( .A0(n3155), .A1(intDY_EWSW[54]), .B0(n3153), .B1(Data_Y[54]), .Y(n1674) );
AO22XLTS U3857 ( .A0(n3155), .A1(intDY_EWSW[55]), .B0(n3154), .B1(Data_Y[55]), .Y(n1673) );
AO22XLTS U3858 ( .A0(n3155), .A1(intDY_EWSW[56]), .B0(n3154), .B1(Data_Y[56]), .Y(n1672) );
AO22XLTS U3859 ( .A0(n3155), .A1(intDY_EWSW[57]), .B0(n3154), .B1(Data_Y[57]), .Y(n1671) );
AOI22X1TS U3860 ( .A0(n3162), .A1(shift_value_SHT2_EWR[3]), .B0(n3161), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n3164) );
NAND2X1TS U3861 ( .A(n3164), .B(n3163), .Y(n1608) );
NAND2X1TS U3862 ( .A(DmP_EXP_EWSW[52]), .B(n3424), .Y(n3169) );
OAI21XLTS U3863 ( .A0(DmP_EXP_EWSW[52]), .A1(n3424), .B0(n3169), .Y(n3165)
);
NAND2X1TS U3864 ( .A(DmP_EXP_EWSW[53]), .B(n3316), .Y(n3168) );
XNOR2X1TS U3865 ( .A(n3169), .B(n3166), .Y(n3167) );
BUFX3TS U3866 ( .A(n3430), .Y(n3192) );
AO22XLTS U3867 ( .A0(n3186), .A1(n3167), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n1603) );
AOI22X1TS U3868 ( .A0(DMP_EXP_EWSW[53]), .A1(n3318), .B0(n3169), .B1(n3168),
.Y(n3172) );
NOR2X1TS U3869 ( .A(n1821), .B(DMP_EXP_EWSW[54]), .Y(n3173) );
AOI21X1TS U3870 ( .A0(DMP_EXP_EWSW[54]), .A1(n1821), .B0(n3173), .Y(n3170)
);
XNOR2X1TS U3871 ( .A(n3172), .B(n3170), .Y(n3171) );
AO22XLTS U3872 ( .A0(n3186), .A1(n3171), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1602) );
OAI22X1TS U3873 ( .A0(n3173), .A1(n3172), .B0(DmP_EXP_EWSW[54]), .B1(n3317),
.Y(n3176) );
NAND2X1TS U3874 ( .A(DmP_EXP_EWSW[55]), .B(n3319), .Y(n3177) );
OAI21XLTS U3875 ( .A0(DmP_EXP_EWSW[55]), .A1(n3319), .B0(n3177), .Y(n3174)
);
XNOR2X1TS U3876 ( .A(n3176), .B(n3174), .Y(n3175) );
AO22XLTS U3877 ( .A0(n3186), .A1(n3175), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1601) );
AOI22X1TS U3878 ( .A0(DMP_EXP_EWSW[55]), .A1(n3322), .B0(n3177), .B1(n3176),
.Y(n3180) );
NOR2X1TS U3879 ( .A(n3212), .B(DMP_EXP_EWSW[56]), .Y(n3181) );
AOI21X1TS U3880 ( .A0(DMP_EXP_EWSW[56]), .A1(n3212), .B0(n3181), .Y(n3178)
);
XNOR2X1TS U3881 ( .A(n3180), .B(n3178), .Y(n3179) );
AO22XLTS U3882 ( .A0(n3186), .A1(n3179), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1600) );
OAI22X1TS U3883 ( .A0(n3181), .A1(n3180), .B0(DmP_EXP_EWSW[56]), .B1(n3321),
.Y(n3183) );
XNOR2X1TS U3884 ( .A(DmP_EXP_EWSW[57]), .B(n1864), .Y(n3182) );
XOR2XLTS U3885 ( .A(n3183), .B(n3182), .Y(n3184) );
AO22XLTS U3886 ( .A0(n3186), .A1(n3184), .B0(n3192), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1599) );
AO22XLTS U3887 ( .A0(n3186), .A1(DMP_EXP_EWSW[0]), .B0(n3192), .B1(
DMP_SHT1_EWSW[0]), .Y(n1521) );
AO22XLTS U3888 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n3189), .B1(
DMP_SHT2_EWSW[0]), .Y(n1520) );
INVX4TS U3889 ( .A(n2883), .Y(n3252) );
AO22XLTS U3890 ( .A0(n2883), .A1(DMP_SHT2_EWSW[0]), .B0(n3252), .B1(
DMP_SFG[0]), .Y(n1519) );
AO22XLTS U3891 ( .A0(n3186), .A1(DMP_EXP_EWSW[1]), .B0(n3192), .B1(
DMP_SHT1_EWSW[1]), .Y(n1518) );
AO22XLTS U3892 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n3189), .B1(
DMP_SHT2_EWSW[1]), .Y(n1517) );
AO22XLTS U3893 ( .A0(n3185), .A1(DMP_SHT2_EWSW[1]), .B0(n3252), .B1(
DMP_SFG[1]), .Y(n1516) );
AO22XLTS U3894 ( .A0(n3186), .A1(DMP_EXP_EWSW[2]), .B0(n3192), .B1(
DMP_SHT1_EWSW[2]), .Y(n1515) );
AO22XLTS U3895 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n3189), .B1(
DMP_SHT2_EWSW[2]), .Y(n1514) );
AO22XLTS U3896 ( .A0(n3258), .A1(DMP_SHT2_EWSW[2]), .B0(n3252), .B1(
DMP_SFG[2]), .Y(n1513) );
AO22XLTS U3897 ( .A0(n3186), .A1(DMP_EXP_EWSW[3]), .B0(n3192), .B1(
DMP_SHT1_EWSW[3]), .Y(n1512) );
BUFX3TS U3898 ( .A(n3503), .Y(n3190) );
AO22XLTS U3899 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n3190), .B1(
DMP_SHT2_EWSW[3]), .Y(n1511) );
AO22XLTS U3900 ( .A0(n3198), .A1(DMP_SHT2_EWSW[3]), .B0(n3252), .B1(
DMP_SFG[3]), .Y(n1510) );
AO22XLTS U3901 ( .A0(n3186), .A1(DMP_EXP_EWSW[4]), .B0(n3191), .B1(
DMP_SHT1_EWSW[4]), .Y(n1509) );
AO22XLTS U3902 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n3190), .B1(
DMP_SHT2_EWSW[4]), .Y(n1508) );
AO22XLTS U3903 ( .A0(n3217), .A1(DMP_SHT2_EWSW[4]), .B0(n3252), .B1(
DMP_SFG[4]), .Y(n1507) );
AO22XLTS U3904 ( .A0(n3186), .A1(DMP_EXP_EWSW[5]), .B0(n3191), .B1(
DMP_SHT1_EWSW[5]), .Y(n1506) );
AO22XLTS U3905 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n3190), .B1(
DMP_SHT2_EWSW[5]), .Y(n1505) );
AO22XLTS U3906 ( .A0(n3198), .A1(DMP_SHT2_EWSW[5]), .B0(n3224), .B1(
DMP_SFG[5]), .Y(n1504) );
AO22XLTS U3907 ( .A0(n3187), .A1(DMP_EXP_EWSW[6]), .B0(n3191), .B1(
DMP_SHT1_EWSW[6]), .Y(n1503) );
AO22XLTS U3908 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n3190), .B1(
DMP_SHT2_EWSW[6]), .Y(n1502) );
AO22XLTS U3909 ( .A0(n3185), .A1(DMP_SHT2_EWSW[6]), .B0(n3252), .B1(
DMP_SFG[6]), .Y(n1501) );
AO22XLTS U3910 ( .A0(n3187), .A1(DMP_EXP_EWSW[7]), .B0(n3191), .B1(
DMP_SHT1_EWSW[7]), .Y(n1500) );
AO22XLTS U3911 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n3190), .B1(
DMP_SHT2_EWSW[7]), .Y(n1499) );
AO22XLTS U3912 ( .A0(n3258), .A1(DMP_SHT2_EWSW[7]), .B0(n3252), .B1(
DMP_SFG[7]), .Y(n1498) );
AO22XLTS U3913 ( .A0(n3187), .A1(DMP_EXP_EWSW[8]), .B0(n3191), .B1(
DMP_SHT1_EWSW[8]), .Y(n1497) );
AO22XLTS U3914 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n3190), .B1(
DMP_SHT2_EWSW[8]), .Y(n1496) );
AO22XLTS U3915 ( .A0(n3217), .A1(DMP_SHT2_EWSW[8]), .B0(n3224), .B1(
DMP_SFG[8]), .Y(n1495) );
AO22XLTS U3916 ( .A0(n3187), .A1(DMP_EXP_EWSW[9]), .B0(n3191), .B1(
DMP_SHT1_EWSW[9]), .Y(n1494) );
AO22XLTS U3917 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n3190), .B1(
DMP_SHT2_EWSW[9]), .Y(n1493) );
AO22XLTS U3918 ( .A0(n3246), .A1(DMP_SHT2_EWSW[9]), .B0(n3252), .B1(
DMP_SFG[9]), .Y(n1492) );
AO22XLTS U3919 ( .A0(n3187), .A1(DMP_EXP_EWSW[10]), .B0(n3191), .B1(
DMP_SHT1_EWSW[10]), .Y(n1491) );
AO22XLTS U3920 ( .A0(busy), .A1(DMP_SHT1_EWSW[10]), .B0(n3190), .B1(
DMP_SHT2_EWSW[10]), .Y(n1490) );
AO22XLTS U3921 ( .A0(n3198), .A1(DMP_SHT2_EWSW[10]), .B0(n3252), .B1(
DMP_SFG[10]), .Y(n1489) );
AO22XLTS U3922 ( .A0(n3187), .A1(DMP_EXP_EWSW[11]), .B0(n3191), .B1(
DMP_SHT1_EWSW[11]), .Y(n1488) );
AO22XLTS U3923 ( .A0(busy), .A1(DMP_SHT1_EWSW[11]), .B0(n3190), .B1(
DMP_SHT2_EWSW[11]), .Y(n1487) );
AO22XLTS U3924 ( .A0(n2883), .A1(DMP_SHT2_EWSW[11]), .B0(n3252), .B1(
DMP_SFG[11]), .Y(n1486) );
AO22XLTS U3925 ( .A0(n3187), .A1(DMP_EXP_EWSW[12]), .B0(n3191), .B1(
DMP_SHT1_EWSW[12]), .Y(n1485) );
AO22XLTS U3926 ( .A0(n3187), .A1(DMP_EXP_EWSW[13]), .B0(n3191), .B1(
DMP_SHT1_EWSW[13]), .Y(n1482) );
AO22XLTS U3927 ( .A0(n3187), .A1(DMP_EXP_EWSW[14]), .B0(n3191), .B1(
DMP_SHT1_EWSW[14]), .Y(n1479) );
AO22XLTS U3928 ( .A0(n3187), .A1(DMP_EXP_EWSW[15]), .B0(n3430), .B1(
DMP_SHT1_EWSW[15]), .Y(n1476) );
AO22XLTS U3929 ( .A0(n3187), .A1(DMP_EXP_EWSW[16]), .B0(n3208), .B1(
DMP_SHT1_EWSW[16]), .Y(n1473) );
AO22XLTS U3930 ( .A0(n3187), .A1(DMP_EXP_EWSW[17]), .B0(n3208), .B1(
DMP_SHT1_EWSW[17]), .Y(n1470) );
AO22XLTS U3931 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n3190), .B1(
DMP_SHT2_EWSW[17]), .Y(n1469) );
BUFX3TS U3932 ( .A(n3430), .Y(n3207) );
AO22XLTS U3933 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[18]), .B0(n3206),
.B1(DMP_SHT1_EWSW[18]), .Y(n1467) );
AO22XLTS U3934 ( .A0(n3505), .A1(DMP_SHT1_EWSW[18]), .B0(n3190), .B1(
DMP_SHT2_EWSW[18]), .Y(n1466) );
BUFX3TS U3935 ( .A(n3207), .Y(n3205) );
AO22XLTS U3936 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[19]), .B0(n3205),
.B1(DMP_SHT1_EWSW[19]), .Y(n1464) );
AO22XLTS U3937 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1847), .B1(
DMP_SHT2_EWSW[19]), .Y(n1463) );
AO22XLTS U3938 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[20]), .B0(n3208),
.B1(DMP_SHT1_EWSW[20]), .Y(n1461) );
AO22XLTS U3939 ( .A0(n3505), .A1(DMP_SHT1_EWSW[20]), .B0(n3190), .B1(
DMP_SHT2_EWSW[20]), .Y(n1460) );
AO22XLTS U3940 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[21]), .B0(n3206),
.B1(DMP_SHT1_EWSW[21]), .Y(n1458) );
AO22XLTS U3941 ( .A0(n3505), .A1(DMP_SHT1_EWSW[21]), .B0(n1847), .B1(
DMP_SHT2_EWSW[21]), .Y(n1457) );
AO22XLTS U3942 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[22]), .B0(n3205),
.B1(DMP_SHT1_EWSW[22]), .Y(n1455) );
AO22XLTS U3943 ( .A0(n3505), .A1(DMP_SHT1_EWSW[22]), .B0(n3190), .B1(
DMP_SHT2_EWSW[22]), .Y(n1454) );
AO22XLTS U3944 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[23]), .B0(n3206),
.B1(DMP_SHT1_EWSW[23]), .Y(n1452) );
AO22XLTS U3945 ( .A0(n3505), .A1(DMP_SHT1_EWSW[23]), .B0(n1847), .B1(
DMP_SHT2_EWSW[23]), .Y(n1451) );
AO22XLTS U3946 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[24]), .B0(n3205),
.B1(DMP_SHT1_EWSW[24]), .Y(n1449) );
AO22XLTS U3947 ( .A0(n3505), .A1(DMP_SHT1_EWSW[24]), .B0(n3194), .B1(
DMP_SHT2_EWSW[24]), .Y(n1448) );
AO22XLTS U3948 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[25]), .B0(n3206),
.B1(DMP_SHT1_EWSW[25]), .Y(n1446) );
AO22XLTS U3949 ( .A0(n3505), .A1(DMP_SHT1_EWSW[25]), .B0(n3189), .B1(
DMP_SHT2_EWSW[25]), .Y(n1445) );
AO22XLTS U3950 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[26]), .B0(n3191),
.B1(DMP_SHT1_EWSW[26]), .Y(n1443) );
AO22XLTS U3951 ( .A0(n3505), .A1(DMP_SHT1_EWSW[26]), .B0(n3189), .B1(
DMP_SHT2_EWSW[26]), .Y(n1442) );
AO22XLTS U3952 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[27]), .B0(n3191),
.B1(DMP_SHT1_EWSW[27]), .Y(n1440) );
AO22XLTS U3953 ( .A0(n3505), .A1(DMP_SHT1_EWSW[27]), .B0(n3194), .B1(
DMP_SHT2_EWSW[27]), .Y(n1439) );
AO22XLTS U3954 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[28]), .B0(n3191),
.B1(DMP_SHT1_EWSW[28]), .Y(n1437) );
INVX4TS U3955 ( .A(n3189), .Y(n3195) );
AO22XLTS U3956 ( .A0(n3195), .A1(DMP_SHT1_EWSW[28]), .B0(n3190), .B1(
DMP_SHT2_EWSW[28]), .Y(n1436) );
AO22XLTS U3957 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[29]), .B0(n3208),
.B1(DMP_SHT1_EWSW[29]), .Y(n1434) );
AO22XLTS U3958 ( .A0(n3195), .A1(DMP_SHT1_EWSW[29]), .B0(n1847), .B1(
DMP_SHT2_EWSW[29]), .Y(n1433) );
CLKBUFX2TS U3959 ( .A(n3430), .Y(n3220) );
AO22XLTS U3960 ( .A0(n3202), .A1(DMP_EXP_EWSW[30]), .B0(n3208), .B1(
DMP_SHT1_EWSW[30]), .Y(n1431) );
AO22XLTS U3961 ( .A0(n3195), .A1(DMP_SHT1_EWSW[30]), .B0(n1847), .B1(
DMP_SHT2_EWSW[30]), .Y(n1430) );
AO22XLTS U3962 ( .A0(n3202), .A1(DMP_EXP_EWSW[31]), .B0(n3191), .B1(
DMP_SHT1_EWSW[31]), .Y(n1428) );
AO22XLTS U3963 ( .A0(n3195), .A1(DMP_SHT1_EWSW[31]), .B0(n1847), .B1(
DMP_SHT2_EWSW[31]), .Y(n1427) );
AO22XLTS U3964 ( .A0(n3204), .A1(DMP_EXP_EWSW[32]), .B0(n3192), .B1(
DMP_SHT1_EWSW[32]), .Y(n1425) );
AO22XLTS U3965 ( .A0(n3195), .A1(DMP_SHT1_EWSW[32]), .B0(n1847), .B1(
DMP_SHT2_EWSW[32]), .Y(n1424) );
AO22XLTS U3966 ( .A0(n3202), .A1(DMP_EXP_EWSW[33]), .B0(n3192), .B1(
DMP_SHT1_EWSW[33]), .Y(n1422) );
AO22XLTS U3967 ( .A0(n3195), .A1(DMP_SHT1_EWSW[33]), .B0(n1847), .B1(
DMP_SHT2_EWSW[33]), .Y(n1421) );
AO22XLTS U3968 ( .A0(n3200), .A1(DMP_EXP_EWSW[34]), .B0(n3192), .B1(
DMP_SHT1_EWSW[34]), .Y(n1419) );
AO22XLTS U3969 ( .A0(n3195), .A1(DMP_SHT1_EWSW[34]), .B0(n1847), .B1(
DMP_SHT2_EWSW[34]), .Y(n1418) );
AO22XLTS U3970 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[35]), .B0(n3192),
.B1(DMP_SHT1_EWSW[35]), .Y(n1416) );
AO22XLTS U3971 ( .A0(n3195), .A1(DMP_SHT1_EWSW[35]), .B0(n1847), .B1(
DMP_SHT2_EWSW[35]), .Y(n1415) );
AO22XLTS U3972 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[36]), .B0(n3192),
.B1(DMP_SHT1_EWSW[36]), .Y(n1413) );
AO22XLTS U3973 ( .A0(n3195), .A1(DMP_SHT1_EWSW[36]), .B0(n1847), .B1(
DMP_SHT2_EWSW[36]), .Y(n1412) );
BUFX3TS U3974 ( .A(n3430), .Y(n3201) );
AO22XLTS U3975 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[37]), .B0(n3203),
.B1(DMP_SHT1_EWSW[37]), .Y(n1410) );
AO22XLTS U3976 ( .A0(n3195), .A1(DMP_SHT1_EWSW[37]), .B0(n1847), .B1(
DMP_SHT2_EWSW[37]), .Y(n1409) );
AO22XLTS U3977 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[38]), .B0(n3203),
.B1(DMP_SHT1_EWSW[38]), .Y(n1407) );
AO22XLTS U3978 ( .A0(n3195), .A1(DMP_SHT1_EWSW[38]), .B0(n1847), .B1(
DMP_SHT2_EWSW[38]), .Y(n1406) );
AO22XLTS U3979 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[39]), .B0(n3203),
.B1(DMP_SHT1_EWSW[39]), .Y(n1404) );
AO22XLTS U3980 ( .A0(n3195), .A1(DMP_SHT1_EWSW[39]), .B0(n1847), .B1(
DMP_SHT2_EWSW[39]), .Y(n1403) );
AO22XLTS U3981 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[40]), .B0(n3203),
.B1(DMP_SHT1_EWSW[40]), .Y(n1401) );
AO22XLTS U3982 ( .A0(n3195), .A1(DMP_SHT1_EWSW[40]), .B0(n1847), .B1(
DMP_SHT2_EWSW[40]), .Y(n1400) );
AO22XLTS U3983 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[41]), .B0(n3203),
.B1(DMP_SHT1_EWSW[41]), .Y(n1398) );
INVX2TS U3984 ( .A(n3505), .Y(n3196) );
AO22XLTS U3985 ( .A0(n3195), .A1(DMP_SHT1_EWSW[41]), .B0(n3196), .B1(
DMP_SHT2_EWSW[41]), .Y(n1397) );
AO22XLTS U3986 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[42]), .B0(n3203),
.B1(DMP_SHT1_EWSW[42]), .Y(n1395) );
INVX4TS U3987 ( .A(n3194), .Y(n3199) );
AO22XLTS U3988 ( .A0(n3199), .A1(DMP_SHT1_EWSW[42]), .B0(n3196), .B1(
DMP_SHT2_EWSW[42]), .Y(n1394) );
AO22XLTS U3989 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[43]), .B0(n3203),
.B1(DMP_SHT1_EWSW[43]), .Y(n1392) );
AO22XLTS U3990 ( .A0(n3199), .A1(DMP_SHT1_EWSW[43]), .B0(n3194), .B1(
DMP_SHT2_EWSW[43]), .Y(n1391) );
AO22XLTS U3991 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[44]), .B0(n3203),
.B1(DMP_SHT1_EWSW[44]), .Y(n1389) );
AO22XLTS U3992 ( .A0(n3199), .A1(DMP_SHT1_EWSW[44]), .B0(n3196), .B1(
DMP_SHT2_EWSW[44]), .Y(n1388) );
AO22XLTS U3993 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[45]), .B0(n3203),
.B1(DMP_SHT1_EWSW[45]), .Y(n1386) );
AO22XLTS U3994 ( .A0(n3199), .A1(DMP_SHT1_EWSW[45]), .B0(n3503), .B1(
DMP_SHT2_EWSW[45]), .Y(n1385) );
AO22XLTS U3995 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[46]), .B0(n3203),
.B1(DMP_SHT1_EWSW[46]), .Y(n1383) );
AO22XLTS U3996 ( .A0(n3199), .A1(DMP_SHT1_EWSW[46]), .B0(n3196), .B1(
DMP_SHT2_EWSW[46]), .Y(n1382) );
AO22XLTS U3997 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[47]), .B0(n3203),
.B1(DMP_SHT1_EWSW[47]), .Y(n1380) );
AO22XLTS U3998 ( .A0(n3199), .A1(DMP_SHT1_EWSW[47]), .B0(n3196), .B1(
DMP_SHT2_EWSW[47]), .Y(n1379) );
BUFX3TS U3999 ( .A(n3430), .Y(n3221) );
AO22XLTS U4000 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[48]), .B0(n3221),
.B1(DMP_SHT1_EWSW[48]), .Y(n1377) );
AO22XLTS U4001 ( .A0(n3199), .A1(DMP_SHT1_EWSW[48]), .B0(n3196), .B1(
DMP_SHT2_EWSW[48]), .Y(n1376) );
AO22XLTS U4002 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[49]), .B0(n3221),
.B1(DMP_SHT1_EWSW[49]), .Y(n1374) );
AO22XLTS U4003 ( .A0(n3195), .A1(DMP_SHT1_EWSW[49]), .B0(n3196), .B1(
DMP_SHT2_EWSW[49]), .Y(n1373) );
AO22XLTS U4004 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[50]), .B0(n3221),
.B1(DMP_SHT1_EWSW[50]), .Y(n1371) );
AO22XLTS U4005 ( .A0(n3199), .A1(DMP_SHT1_EWSW[50]), .B0(n3196), .B1(
DMP_SHT2_EWSW[50]), .Y(n1370) );
AO22XLTS U4006 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[51]), .B0(n3221),
.B1(DMP_SHT1_EWSW[51]), .Y(n1368) );
AO22XLTS U4007 ( .A0(n3199), .A1(DMP_SHT1_EWSW[51]), .B0(n3196), .B1(
DMP_SHT2_EWSW[51]), .Y(n1367) );
AO22XLTS U4008 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[52]), .B0(n3221),
.B1(DMP_SHT1_EWSW[52]), .Y(n1365) );
AO22XLTS U4009 ( .A0(n3199), .A1(DMP_SHT1_EWSW[52]), .B0(n3503), .B1(
DMP_SHT2_EWSW[52]), .Y(n1364) );
AO22XLTS U4010 ( .A0(n3258), .A1(DMP_SHT2_EWSW[52]), .B0(n3224), .B1(
DMP_SFG[52]), .Y(n1363) );
AO22XLTS U4011 ( .A0(n3225), .A1(DMP_SFG[52]), .B0(n3431), .B1(
DMP_exp_NRM_EW[0]), .Y(n1362) );
AO22XLTS U4012 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[53]), .B0(n3221),
.B1(DMP_SHT1_EWSW[53]), .Y(n1360) );
AO22XLTS U4013 ( .A0(n3199), .A1(DMP_SHT1_EWSW[53]), .B0(n3503), .B1(
DMP_SHT2_EWSW[53]), .Y(n1359) );
AO22XLTS U4014 ( .A0(n3185), .A1(DMP_SHT2_EWSW[53]), .B0(n3252), .B1(
DMP_SFG[53]), .Y(n1358) );
AO22XLTS U4015 ( .A0(n3225), .A1(DMP_SFG[53]), .B0(n3431), .B1(
DMP_exp_NRM_EW[1]), .Y(n1357) );
AO22XLTS U4016 ( .A0(n3202), .A1(DMP_EXP_EWSW[54]), .B0(n3220), .B1(
DMP_SHT1_EWSW[54]), .Y(n1355) );
AO22XLTS U4017 ( .A0(n3199), .A1(DMP_SHT1_EWSW[54]), .B0(n3503), .B1(
DMP_SHT2_EWSW[54]), .Y(n1354) );
AO22XLTS U4018 ( .A0(n2883), .A1(DMP_SHT2_EWSW[54]), .B0(n3224), .B1(
DMP_SFG[54]), .Y(n1353) );
AO22XLTS U4019 ( .A0(n3225), .A1(DMP_SFG[54]), .B0(n3431), .B1(
DMP_exp_NRM_EW[2]), .Y(n1352) );
AO22XLTS U4020 ( .A0(n3202), .A1(DMP_EXP_EWSW[55]), .B0(n3220), .B1(
DMP_SHT1_EWSW[55]), .Y(n1350) );
AO22XLTS U4021 ( .A0(n3199), .A1(DMP_SHT1_EWSW[55]), .B0(n3503), .B1(
DMP_SHT2_EWSW[55]), .Y(n1349) );
AO22XLTS U4022 ( .A0(n3246), .A1(DMP_SHT2_EWSW[55]), .B0(n3252), .B1(
DMP_SFG[55]), .Y(n1348) );
AO22XLTS U4023 ( .A0(n3225), .A1(DMP_SFG[55]), .B0(n3431), .B1(
DMP_exp_NRM_EW[3]), .Y(n1347) );
AO22XLTS U4024 ( .A0(n3202), .A1(DMP_EXP_EWSW[56]), .B0(n3220), .B1(
DMP_SHT1_EWSW[56]), .Y(n1345) );
AO22XLTS U4025 ( .A0(n3199), .A1(DMP_SHT1_EWSW[56]), .B0(n3503), .B1(
DMP_SHT2_EWSW[56]), .Y(n1344) );
AO22XLTS U4026 ( .A0(n3217), .A1(DMP_SHT2_EWSW[56]), .B0(n3224), .B1(
DMP_SFG[56]), .Y(n1343) );
AO22XLTS U4027 ( .A0(n3225), .A1(DMP_SFG[56]), .B0(n3218), .B1(
DMP_exp_NRM_EW[4]), .Y(n1342) );
AO22XLTS U4028 ( .A0(n3200), .A1(n1864), .B0(n3220), .B1(DMP_SHT1_EWSW[57]),
.Y(n1340) );
AO22XLTS U4029 ( .A0(n3199), .A1(DMP_SHT1_EWSW[57]), .B0(n3503), .B1(
DMP_SHT2_EWSW[57]), .Y(n1339) );
AO22XLTS U4030 ( .A0(n3198), .A1(DMP_SHT2_EWSW[57]), .B0(n3252), .B1(
DMP_SFG[57]), .Y(n1338) );
AO22XLTS U4031 ( .A0(n3225), .A1(DMP_SFG[57]), .B0(n3218), .B1(
DMP_exp_NRM_EW[5]), .Y(n1337) );
AO22XLTS U4032 ( .A0(n3204), .A1(DMP_EXP_EWSW[58]), .B0(n3201), .B1(
DMP_SHT1_EWSW[58]), .Y(n1335) );
AO22XLTS U4033 ( .A0(n3223), .A1(DMP_SHT1_EWSW[58]), .B0(n3503), .B1(
DMP_SHT2_EWSW[58]), .Y(n1334) );
AO22XLTS U4034 ( .A0(n3198), .A1(DMP_SHT2_EWSW[58]), .B0(n3224), .B1(
DMP_SFG[58]), .Y(n1333) );
AO22XLTS U4035 ( .A0(n3225), .A1(DMP_SFG[58]), .B0(n3431), .B1(
DMP_exp_NRM_EW[6]), .Y(n1332) );
AO22XLTS U4036 ( .A0(n3200), .A1(DMP_EXP_EWSW[59]), .B0(n3201), .B1(
DMP_SHT1_EWSW[59]), .Y(n1330) );
AO22XLTS U4037 ( .A0(n3223), .A1(DMP_SHT1_EWSW[59]), .B0(n3503), .B1(
DMP_SHT2_EWSW[59]), .Y(n1329) );
AO22XLTS U4038 ( .A0(n2858), .A1(DMP_SHT2_EWSW[59]), .B0(n3224), .B1(
DMP_SFG[59]), .Y(n1328) );
AO22XLTS U4039 ( .A0(n3225), .A1(DMP_SFG[59]), .B0(n3431), .B1(
DMP_exp_NRM_EW[7]), .Y(n1327) );
AO22XLTS U4040 ( .A0(n3204), .A1(DMP_EXP_EWSW[60]), .B0(n3201), .B1(
DMP_SHT1_EWSW[60]), .Y(n1325) );
AO22XLTS U4041 ( .A0(n3223), .A1(DMP_SHT1_EWSW[60]), .B0(n3503), .B1(
DMP_SHT2_EWSW[60]), .Y(n1324) );
AO22XLTS U4042 ( .A0(n3246), .A1(DMP_SHT2_EWSW[60]), .B0(n3224), .B1(
DMP_SFG[60]), .Y(n1323) );
AO22XLTS U4043 ( .A0(n3225), .A1(DMP_SFG[60]), .B0(n3431), .B1(
DMP_exp_NRM_EW[8]), .Y(n1322) );
AO22XLTS U4044 ( .A0(n3200), .A1(DMP_EXP_EWSW[61]), .B0(n3201), .B1(
DMP_SHT1_EWSW[61]), .Y(n1320) );
AO22XLTS U4045 ( .A0(n3223), .A1(DMP_SHT1_EWSW[61]), .B0(n3503), .B1(
DMP_SHT2_EWSW[61]), .Y(n1319) );
AO22XLTS U4046 ( .A0(n3258), .A1(DMP_SHT2_EWSW[61]), .B0(n3224), .B1(
DMP_SFG[61]), .Y(n1318) );
AO22XLTS U4047 ( .A0(n3225), .A1(DMP_SFG[61]), .B0(n3431), .B1(
DMP_exp_NRM_EW[9]), .Y(n1317) );
AO22XLTS U4048 ( .A0(n3204), .A1(DMP_EXP_EWSW[62]), .B0(n3201), .B1(
DMP_SHT1_EWSW[62]), .Y(n1315) );
AO22XLTS U4049 ( .A0(n3223), .A1(DMP_SHT1_EWSW[62]), .B0(n3503), .B1(
DMP_SHT2_EWSW[62]), .Y(n1314) );
AO22XLTS U4050 ( .A0(n3198), .A1(DMP_SHT2_EWSW[62]), .B0(n3224), .B1(
DMP_SFG[62]), .Y(n1313) );
AO22XLTS U4051 ( .A0(n3225), .A1(DMP_SFG[62]), .B0(n3431), .B1(
DMP_exp_NRM_EW[10]), .Y(n1312) );
AO22XLTS U4052 ( .A0(n3202), .A1(DmP_EXP_EWSW[6]), .B0(n3203), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1297) );
AO22XLTS U4053 ( .A0(n3202), .A1(DmP_EXP_EWSW[7]), .B0(n3221), .B1(
DmP_mant_SHT1_SW[7]), .Y(n1295) );
AO22XLTS U4054 ( .A0(n3202), .A1(DmP_EXP_EWSW[8]), .B0(n3221), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1293) );
AO22XLTS U4055 ( .A0(n3202), .A1(DmP_EXP_EWSW[10]), .B0(n3221), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1289) );
AO22XLTS U4056 ( .A0(n3202), .A1(DmP_EXP_EWSW[12]), .B0(n3203), .B1(
DmP_mant_SHT1_SW[12]), .Y(n1285) );
AO22XLTS U4057 ( .A0(n3202), .A1(DmP_EXP_EWSW[13]), .B0(n3203), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1283) );
AO22XLTS U4058 ( .A0(n3202), .A1(DmP_EXP_EWSW[14]), .B0(n3221), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1281) );
AO22XLTS U4059 ( .A0(n3204), .A1(DmP_EXP_EWSW[16]), .B0(n3203), .B1(n1856),
.Y(n1277) );
OAI222X1TS U4060 ( .A0(n2560), .A1(n3429), .B0(n3322), .B1(n3211), .C0(n3283), .C1(n3210), .Y(n1203) );
OAI2BB1X1TS U4061 ( .A0N(underflow_flag), .A1N(n3426), .B0(n3214), .Y(n1200)
);
OA21XLTS U4062 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n3215),
.Y(n1199) );
AO22XLTS U4063 ( .A0(Shift_reg_FLAGS_7_5), .A1(ZERO_FLAG_EXP), .B0(n3430),
.B1(ZERO_FLAG_SHT1), .Y(n1198) );
AO22XLTS U4064 ( .A0(n3223), .A1(ZERO_FLAG_SHT1), .B0(n3503), .B1(
ZERO_FLAG_SHT2), .Y(n1197) );
AO22XLTS U4065 ( .A0(n3198), .A1(ZERO_FLAG_SHT2), .B0(n3224), .B1(
ZERO_FLAG_SFG), .Y(n1196) );
AO22XLTS U4066 ( .A0(n3225), .A1(ZERO_FLAG_SFG), .B0(n3218), .B1(
ZERO_FLAG_NRM), .Y(n1195) );
AO22XLTS U4067 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n2318), .B1(zero_flag), .Y(n1193) );
AO22XLTS U4068 ( .A0(Shift_reg_FLAGS_7_5), .A1(OP_FLAG_EXP), .B0(n3220),
.B1(OP_FLAG_SHT1), .Y(n1192) );
AO22XLTS U4069 ( .A0(Shift_reg_FLAGS_7_5), .A1(SIGN_FLAG_EXP), .B0(n3220),
.B1(SIGN_FLAG_SHT1), .Y(n1189) );
AO22XLTS U4070 ( .A0(n3223), .A1(SIGN_FLAG_SHT1), .B0(n3196), .B1(
SIGN_FLAG_SHT2), .Y(n1188) );
AO22XLTS U4071 ( .A0(n3258), .A1(SIGN_FLAG_SHT2), .B0(n3224), .B1(
SIGN_FLAG_SFG), .Y(n1187) );
AO22XLTS U4072 ( .A0(n3225), .A1(SIGN_FLAG_SFG), .B0(n3431), .B1(
SIGN_FLAG_NRM), .Y(n1186) );
OAI211XLTS U4073 ( .A0(n2126), .A1(SIGN_FLAG_SHT1SHT2), .B0(
Shift_reg_FLAGS_7[0]), .C0(n3226), .Y(n3227) );
OAI2BB1X1TS U4074 ( .A0N(final_result_ieee[63]), .A1N(n3426), .B0(n3227),
.Y(n1184) );
OAI22X1TS U4075 ( .A0(n3241), .A1(n3228), .B0(n1826), .B1(n3232), .Y(n3275)
);
OAI22X1TS U4076 ( .A0(n3231), .A1(n3238), .B0(left_right_SHT2), .B1(n3229),
.Y(n3273) );
OAI22X1TS U4077 ( .A0(left_right_SHT2), .A1(n3233), .B0(n3395), .B1(n3232),
.Y(n3271) );
OAI22X1TS U4078 ( .A0(n3241), .A1(n3235), .B0(n3234), .B1(n3238), .Y(n3269)
);
OAI22X1TS U4079 ( .A0(n3241), .A1(n3237), .B0(n3236), .B1(n3238), .Y(n3267)
);
OAI22X1TS U4080 ( .A0(n3241), .A1(n3240), .B0(n3239), .B1(n3238), .Y(n3265)
);
AO22XLTS U4081 ( .A0(n3259), .A1(n1857), .B0(n3258), .B1(n3265), .Y(n1121)
);
AO22XLTS U4082 ( .A0(n3252), .A1(DmP_mant_SFG_SWR[8]), .B0(n3217), .B1(n3242), .Y(n1119) );
AOI22X1TS U4083 ( .A0(n2858), .A1(n3244), .B0(n3432), .B1(n3259), .Y(n1113)
);
AOI22X1TS U4084 ( .A0(n2858), .A1(n3245), .B0(n3433), .B1(n3259), .Y(n1111)
);
AO22XLTS U4085 ( .A0(n3252), .A1(DmP_mant_SFG_SWR[9]), .B0(n2858), .B1(n3251), .Y(n1105) );
AO22XLTS U4086 ( .A0(n3259), .A1(DmP_mant_SFG_SWR[10]), .B0(n3246), .B1(
n3257), .Y(n1097) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk20.tcl_LOA_syn.sdf");
endmodule
|
module sky130_fd_sc_hs__clkbuf (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule
|
module sky130_fd_sc_lp__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module outputs)
wire MT_so_0; // From u_test_stub of test_stub_scan.v
wire cmp_rclk; // From u_cmp_header of bw_clk_cl_jbi_cmp.v
wire cmp_rst_l; // From u_cmp_header of bw_clk_cl_jbi_cmp.v
wire [4:0] csr_16x65array_margin; // From u_csr of jbi_csr.v
wire [4:0] csr_16x81array_margin; // From u_csr of jbi_csr.v
wire [`JBI_CSR_WIDTH-1:0]csr_csr_read_data; // From u_csr of jbi_csr.v
wire csr_dok_on; // From u_csr of jbi_csr.v
wire csr_int_req; // From u_csr of jbi_csr.v
wire [31:0] csr_jbi_arb_timeout_timeval;// From u_csr of jbi_csr.v
wire [3:0] csr_jbi_config2_iq_high;// From u_csr of jbi_csr.v
wire [3:0] csr_jbi_config2_iq_low; // From u_csr of jbi_csr.v
wire [3:0] csr_jbi_config2_max_pio;// From u_csr of jbi_csr.v
wire [1:0] csr_jbi_config2_max_rd; // From u_csr of jbi_csr.v
wire [3:0] csr_jbi_config2_max_wr; // From u_csr of jbi_csr.v
wire [1:0] csr_jbi_config2_max_wris;// From u_csr of jbi_csr.v
wire csr_jbi_config2_ord_int;// From u_csr of jbi_csr.v
wire csr_jbi_config2_ord_pio;// From u_csr of jbi_csr.v
wire csr_jbi_config2_ord_rd; // From u_csr of jbi_csr.v
wire csr_jbi_config2_ord_wr; // From u_csr of jbi_csr.v
wire [1:0] csr_jbi_config_arb_mode;// From u_csr of jbi_csr.v
wire [6:0] csr_jbi_config_port_pres;// From u_csr of jbi_csr.v
wire csr_jbi_debug_arb_aggr_arb;// From u_csr of jbi_csr.v
wire csr_jbi_debug_arb_alternate;// From u_csr of jbi_csr.v
wire csr_jbi_debug_arb_alternate_set_l;// From u_csr of jbi_csr.v
wire csr_jbi_debug_arb_data_arb;// From u_csr of jbi_csr.v
wire [4:0] csr_jbi_debug_arb_hi_water;// From u_csr of jbi_csr.v
wire [4:0] csr_jbi_debug_arb_lo_water;// From u_csr of jbi_csr.v
wire [9:0] csr_jbi_debug_arb_max_wait;// From u_csr of jbi_csr.v
wire [6:0] csr_jbi_debug_arb_tstamp_wrap;// From u_csr of jbi_csr.v
wire csr_jbi_debug_info_enb; // From u_csr of jbi_csr.v
wire [23:0] csr_jbi_err_inject_count;// From u_csr of jbi_csr.v
wire csr_jbi_err_inject_errtype;// From u_csr of jbi_csr.v
wire csr_jbi_err_inject_input;// From u_csr of jbi_csr.v
wire csr_jbi_err_inject_output;// From u_csr of jbi_csr.v
wire [3:0] csr_jbi_err_inject_xormask;// From u_csr of jbi_csr.v
wire csr_jbi_error_config_erren;// From u_csr of jbi_csr.v
wire csr_jbi_error_config_fe_enb;// From u_csr of jbi_csr.v
wire csr_jbi_error_config_sigen;// From u_csr of jbi_csr.v
wire csr_jbi_intr_timeout_rst_l;// From u_csr of jbi_csr.v
wire [31:0] csr_jbi_intr_timeout_timeval;// From u_csr of jbi_csr.v
wire [31:0] csr_jbi_l2_timeout_timeval;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_apar; // From u_csr of jbi_csr.v
wire csr_jbi_log_enb_dpar_o; // From u_csr of jbi_csr.v
wire csr_jbi_log_enb_dpar_rd;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_dpar_wr;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_err_cycle;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_nonex_rd;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_read_to;// From u_csr of jbi_csr.v
wire csr_jbi_log_enb_rep_ue; // From u_csr of jbi_csr.v
wire csr_jbi_log_enb_unexp_dr;// From u_csr of jbi_csr.v
wire [37:30] csr_jbi_memsize_size; // From u_csr of jbi_csr.v
wire [31:0] csr_jbi_trans_timeout_timeval;// From u_csr of jbi_csr.v
wire [127:0] dbg_data; // From u_dbg of jbi_dbg.v
wire dbg_req_arbitrate; // From u_dbg of jbi_dbg.v
wire dbg_req_priority; // From u_dbg of jbi_dbg.v
wire dbg_req_transparent; // From u_dbg of jbi_dbg.v
wire [6:0] jbi_log_arb_aok; // From u_mout of jbi_mout.v
wire [6:0] jbi_log_arb_dok; // From u_mout of jbi_mout.v
wire [6:0] jbi_log_arb_jreq; // From u_mout of jbi_mout.v
wire [2:0] jbi_log_arb_myreq; // From u_mout of jbi_mout.v
wire [2:0] jbi_log_arb_reqtype; // From u_mout of jbi_mout.v
wire jbus_rclk; // From u_jbus_header of bw_clk_cl_jbi_jbus.v
wire jbus_rst_l; // From u_jbus_header of bw_clk_cl_jbi_jbus.v
wire min_aok_off; // From u_min of jbi_min.v
wire min_aok_on; // From u_min of jbi_min.v
wire min_csr_err_adtype; // From u_min of jbi_min.v
wire min_csr_err_apar; // From u_min of jbi_min.v
wire min_csr_err_dpar_o; // From u_min of jbi_min.v
wire min_csr_err_dpar_rd; // From u_min of jbi_min.v
wire min_csr_err_dpar_wr; // From u_min of jbi_min.v
wire min_csr_err_err_cycle; // From u_min of jbi_min.v
wire min_csr_err_illegal; // From u_min of jbi_min.v
wire min_csr_err_l2_to0; // From u_min of jbi_min.v
wire min_csr_err_l2_to1; // From u_min of jbi_min.v
wire min_csr_err_l2_to2; // From u_min of jbi_min.v
wire min_csr_err_l2_to3; // From u_min of jbi_min.v
wire min_csr_err_nonex_rd; // From u_min of jbi_min.v
wire min_csr_err_nonex_wr; // From u_min of jbi_min.v
wire min_csr_err_rep_ue; // From u_min of jbi_min.v
wire min_csr_err_unexp_dr; // From u_min of jbi_min.v
wire min_csr_err_unmap_wr; // From u_min of jbi_min.v
wire min_csr_err_unsupp; // From u_min of jbi_min.v
wire min_csr_inject_input_done;// From u_min of jbi_min.v
wire [42:0] min_csr_log_addr_addr; // From u_min of jbi_min.v
wire [7:0] min_csr_log_addr_adtype;// From u_min of jbi_min.v
wire [2:0] min_csr_log_addr_owner; // From u_min of jbi_min.v
wire [4:0] min_csr_log_addr_ttype; // From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype0;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype1;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype2;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype3;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype4;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype5;// From u_min of jbi_min.v
wire [7:0] min_csr_log_ctl_adtype6;// From u_min of jbi_min.v
wire [2:0] min_csr_log_ctl_owner; // From u_min of jbi_min.v
wire [3:0] min_csr_log_ctl_parity; // From u_min of jbi_min.v
wire [63:0] min_csr_log_data0; // From u_min of jbi_min.v
wire [63:0] min_csr_log_data1; // From u_min of jbi_min.v
wire [3:0] min_csr_perf_blk_q0; // From u_min of jbi_min.v
wire [3:0] min_csr_perf_blk_q1; // From u_min of jbi_min.v
wire [3:0] min_csr_perf_blk_q2; // From u_min of jbi_min.v
wire [3:0] min_csr_perf_blk_q3; // From u_min of jbi_min.v
wire min_csr_perf_dma_rd_in; // From u_min of jbi_min.v
wire [4:0] min_csr_perf_dma_rd_latency;// From u_min of jbi_min.v
wire min_csr_perf_dma_wr; // From u_min of jbi_min.v
wire min_csr_perf_dma_wr8; // From u_min of jbi_min.v
wire min_csr_write_log_addr; // From u_min of jbi_min.v
wire min_free; // From u_min of jbi_min.v
wire [`JBI_JID_WIDTH-1:0]min_free_jid; // From u_min of jbi_min.v
wire [127:0] min_j_ad_ff; // From u_min of jbi_min.v
wire min_mondo_data_err; // From u_min of jbi_min.v
wire min_mondo_data_push; // From u_min of jbi_min.v
wire min_mondo_hdr_push; // From u_min of jbi_min.v
wire min_mout_inject_err; // From u_min of jbi_min.v
wire [`JBI_WRI_TAG_WIDTH-1:0]min_oldest_wri_tag;// From u_min of jbi_min.v
wire min_pio_data_err; // From u_min of jbi_min.v
wire min_pio_rtrn_push; // From u_min of jbi_min.v
wire [`JBI_WRI_TAG_WIDTH-1:0]min_pre_wri_tag; // From u_min of jbi_min.v
wire min_snp_launch; // From u_min of jbi_min.v
wire [`JBI_JID_WIDTH-1:0]min_trans_jid; // From u_min of jbi_min.v
wire mout_csr_err_arb_to; // From u_mout of jbi_mout.v
wire mout_csr_err_cpar; // From u_mout of jbi_mout.v
wire [5:4] mout_csr_err_fatal; // From u_mout of jbi_mout.v
wire mout_csr_err_read_to; // From u_mout of jbi_mout.v
wire mout_csr_inject_output_done;// From u_mout of jbi_mout.v
wire [2:0] mout_csr_jbi_log_par_jpack0;// From u_mout of jbi_mout.v
wire [2:0] mout_csr_jbi_log_par_jpack1;// From u_mout of jbi_mout.v
wire [2:0] mout_csr_jbi_log_par_jpack4;// From u_mout of jbi_mout.v
wire [2:0] mout_csr_jbi_log_par_jpack5;// From u_mout of jbi_mout.v
wire mout_csr_jbi_log_par_jpar;// From u_mout of jbi_mout.v
wire [6:0] mout_csr_jbi_log_par_jreq;// From u_mout of jbi_mout.v
wire mout_dbg_pop; // From u_mout of jbi_mout.v
wire mout_dsbl_sampling; // From u_mout of jbi_mout.v
wire mout_min_inject_err_done;// From u_mout of jbi_mout.v
wire [5:0] mout_min_jbus_owner; // From u_mout of jbi_mout.v
wire mout_mondo_pop; // From u_mout of jbi_mout.v
wire mout_nack; // From u_mout of jbi_mout.v
wire [1:0] mout_nack_buf_id; // From u_mout of jbi_mout.v
wire [5:0] mout_nack_thr_id; // From u_mout of jbi_mout.v
wire mout_perf_aok_off; // From u_mout of jbi_mout.v
wire mout_perf_dok_off; // From u_mout of jbi_mout.v
wire mout_pio_pop; // From u_mout of jbi_mout.v
wire mout_pio_req_adv; // From u_mout of jbi_mout.v
wire mout_port_4_present; // From u_mout of jbi_mout.v
wire mout_port_5_present; // From u_mout of jbi_mout.v
wire mout_scb0_jbus_rd_ack; // From u_mout of jbi_mout.v
wire mout_scb0_jbus_wr_ack; // From u_mout of jbi_mout.v
wire mout_scb1_jbus_rd_ack; // From u_mout of jbi_mout.v
wire mout_scb1_jbus_wr_ack; // From u_mout of jbi_mout.v
wire mout_scb2_jbus_rd_ack; // From u_mout of jbi_mout.v
wire mout_scb2_jbus_wr_ack; // From u_mout of jbi_mout.v
wire mout_scb3_jbus_rd_ack; // From u_mout of jbi_mout.v
wire mout_scb3_jbus_wr_ack; // From u_mout of jbi_mout.v
wire mout_trans_valid; // From u_mout of jbi_mout.v
wire [`JBI_YID_WIDTH-1:0]mout_trans_yid; // From u_mout of jbi_mout.v
wire [31:0] ncio_csr_err_intr_to; // From u_ncio of jbi_ncio.v
wire [4:0] ncio_csr_perf_pio_rd_latency;// From u_ncio of jbi_ncio.v
wire ncio_csr_perf_pio_rd_out;// From u_ncio of jbi_ncio.v
wire ncio_csr_perf_pio_wr; // From u_ncio of jbi_ncio.v
wire [`JBI_CSR_ADDR_WIDTH-1:0]ncio_csr_read_addr;// From u_ncio of jbi_ncio.v
wire ncio_csr_write; // From u_ncio of jbi_ncio.v
wire [`JBI_CSR_ADDR_WIDTH-1:0]ncio_csr_write_addr;// From u_ncio of jbi_ncio.v
wire [`JBI_CSR_WIDTH-1:0]ncio_csr_write_data; // From u_ncio of jbi_ncio.v
wire [`JBI_MAKQ_ADDR_WIDTH:0]ncio_makq_level; // From u_ncio of jbi_ncio.v
wire ncio_mondo_ack; // From u_ncio of jbi_ncio.v
wire [`JBI_AD_INT_AGTID_WIDTH-1:0]ncio_mondo_agnt_id;// From u_ncio of jbi_ncio.v
wire [`JBI_AD_INT_CPUID_WIDTH-1:0]ncio_mondo_cpu_id;// From u_ncio of jbi_ncio.v
wire ncio_mondo_req; // From u_ncio of jbi_ncio.v
wire ncio_mout_nack_pop; // From u_ncio of jbi_ncio.v
wire [63:0] ncio_pio_ad; // From u_ncio of jbi_ncio.v
wire [15:0] ncio_pio_be; // From u_ncio of jbi_ncio.v
wire ncio_pio_req; // From u_ncio of jbi_ncio.v
wire [1:0] ncio_pio_req_dest; // From u_ncio of jbi_ncio.v
wire ncio_pio_req_rw; // From u_ncio of jbi_ncio.v
wire ncio_pio_ue; // From u_ncio of jbi_ncio.v
wire [`JBI_PRQQ_ADDR_WIDTH:0]ncio_prqq_level; // From u_ncio of jbi_ncio.v
wire [`JBI_YID_WIDTH-1:0]ncio_yid; // From u_ncio of jbi_ncio.v
wire rst_tri_en; // From u_test_stub of test_stub_scan.v
wire rx_en_local; // From u_sync_header of cluster_header_sync.v
wire se; // From u_test_stub of test_stub_scan.v
wire sehold; // From u_test_stub of test_stub_scan.v
wire testmux_sel; // From u_test_stub of test_stub_scan.v
wire tx_en_local; // From u_sync_header of cluster_header_sync.v
// End of automatics
wire MT_long_chain_so_0;
wire MT_short_chain_so_0;
//*******************************************************************************
// CLUSTER HEADERS
//*******************************************************************************
/* bw_clk_cl_jbi_jbus AUTO_TEMPLATE (
.dbginit_l (),
.cluster_grst_l (jbus_rst_l),
.rclk (jbus_rclk),
.so (),
.gclk (jbus_gclk),
.cluster_cken (clk_jbi_jbus_cken),
.arst_l (jbus_arst_l),
.grst_l (jbus_grst_l),
.adbginit_l (1'b1),
.gdbginit_l (1'b1),
.si (),
); */
bw_clk_cl_jbi_jbus u_jbus_header (/*AUTOINST*/
// Outputs
.so (), // Templated
.dbginit_l(), // Templated
.cluster_grst_l(jbus_rst_l), // Templated
.rclk (jbus_rclk), // Templated
// Inputs
.si (), // Templated
.se (se),
.adbginit_l(1'b1), // Templated
.gdbginit_l(1'b1), // Templated
.arst_l(jbus_arst_l), // Templated
.grst_l(jbus_grst_l), // Templated
.cluster_cken(clk_jbi_jbus_cken), // Templated
.gclk (jbus_gclk)); // Templated
/* bw_clk_cl_jbi_cmp AUTO_TEMPLATE (
.dbginit_l (),
.cluster_grst_l (cmp_rst_l),
.rclk (cmp_rclk),
.so (),
.gclk (cmp_gclk),
.cluster_cken (clk_jbi_cmp_cken),
.arst_l (cmp_arst_l),
.grst_l (cmp_grst_l),
.adbginit_l (1'b1),
.gdbginit_l (1'b1),
.si (),
); */
bw_clk_cl_jbi_cmp u_cmp_header (/*AUTOINST*/
// Outputs
.so (), // Templated
.dbginit_l(), // Templated
.cluster_grst_l(cmp_rst_l), // Templated
.rclk (cmp_rclk), // Templated
// Inputs
.si (), // Templated
.se (se),
.adbginit_l(1'b1), // Templated
.gdbginit_l(1'b1), // Templated
.arst_l (cmp_arst_l), // Templated
.grst_l (cmp_grst_l), // Templated
.cluster_cken(clk_jbi_cmp_cken), // Templated
.gclk (cmp_gclk)); // Templated
/* cluster_header_sync AUTO_TEMPLATE (
// outputs
.dram_rx_sync_local (),
.dram_tx_sync_local (),
.jbus_rx_sync_local (rx_en_local),
.jbus_tx_sync_local (tx_en_local),
.so (),
// inputs
.dram_rx_sync_global (1'b0),
.dram_tx_sync_global (1'b0),
.jbus_rx_sync_global (ctu_jbi_rx_en),
.jbus_tx_sync_global (ctu_jbi_tx_en),
.si (),
); */
cluster_header_sync u_sync_header (/*AUTOINST*/
// Outputs
.dram_rx_sync_local(), // Templated
.dram_tx_sync_local(), // Templated
.jbus_rx_sync_local(rx_en_local), // Templated
.jbus_tx_sync_local(tx_en_local), // Templated
.so (), // Templated
// Inputs
.dram_rx_sync_global(1'b0), // Templated
.dram_tx_sync_global(1'b0), // Templated
.jbus_rx_sync_global(ctu_jbi_rx_en), // Templated
.jbus_tx_sync_global(ctu_jbi_tx_en), // Templated
.cmp_gclk(cmp_gclk),
.cmp_rclk(cmp_rclk),
.si (), // Templated
.se (se));
//*******************************************************************************
// CMP Reset Flop
//*******************************************************************************
dffrl_async_ns u_dffrl_async_cmp_rst_l_ff0
( .din (cmp_rst_l),
.clk (cmp_rclk),
.rst_l (cmp_arst_l),
.q (cmp_rst_l_ff0)
);
dffrl_async_ns u_dffrl_async_cmp_rst_l_ff1
( .din (cmp_rst_l),
.clk (cmp_rclk),
.rst_l (cmp_arst_l),
.q (cmp_rst_l_ff1)
);
//*******************************************************************************
// Test Stub
//*******************************************************************************
/*test_stub_scan AUTO_TEMPLATE (
.testmode_l (),
.tst_ctu_data_out (test_csr_data_out[2:0]),
.mem_bypass (testmux_sel),
.arst_l (jbus_arst_l),
.mux_drive_disable (), //replaces rst_tri_en for logic
.mem_write_disable (rst_tri_en), //replaces rst_tri_en for memory
// macrotest
.so_0 (MT_so_0),
.long_chain_so_0 (MT_long_chain_so_0),
.short_chain_so_0 (MT_short_chain_so_0),
.so_1 (),
.long_chain_so_1 (1'b0),
.short_chain_so_1 (1'b0),
.so_2 (),
.long_chain_so_2 (1'b0),
.short_chain_so_2 (1'b0),
);*/
test_stub_scan u_test_stub (/*AUTOINST*/
// Outputs
.mux_drive_disable(), // Templated
.mem_write_disable(rst_tri_en), // Templated
.sehold (sehold),
.se (se),
.testmode_l (), // Templated
.mem_bypass (testmux_sel), // Templated
.so_0 (MT_so_0), // Templated
.so_1 (), // Templated
.so_2 (), // Templated
// Inputs
.ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
.arst_l (jbus_arst_l), // Templated
.global_shift_enable(global_shift_enable),
.ctu_tst_scan_disable(ctu_tst_scan_disable),
.ctu_tst_scanmode(ctu_tst_scanmode),
.ctu_tst_macrotest(ctu_tst_macrotest),
.ctu_tst_short_chain(ctu_tst_short_chain),
.long_chain_so_0(MT_long_chain_so_0), // Templated
.short_chain_so_0(MT_short_chain_so_0), // Templated
.long_chain_so_1(1'b0), // Templated
.short_chain_so_1(1'b0), // Templated
.long_chain_so_2(1'b0), // Templated
.short_chain_so_2(1'b0)); // Templated
//*******************************************************************************
// Memory Inbound Block
//*******************************************************************************
/* jbi_min AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.arst_l (jbus_arst_l),
.cpu_clk (cmp_rclk),
.cpu_rst_l (cmp_rst_l),
.hold (sehold),
.cpu_tx_en (tx_en_local),
.cpu_rx_en (rx_en_local),
); */
jbi_min u_min (/*AUTOINST*/
// Outputs
.min_csr_inject_input_done(min_csr_inject_input_done),
.min_csr_err_apar (min_csr_err_apar),
.min_csr_err_adtype (min_csr_err_adtype),
.min_csr_err_dpar_wr (min_csr_err_dpar_wr),
.min_csr_err_dpar_rd (min_csr_err_dpar_rd),
.min_csr_err_dpar_o (min_csr_err_dpar_o),
.min_csr_err_rep_ue (min_csr_err_rep_ue),
.min_csr_err_illegal (min_csr_err_illegal),
.min_csr_err_unsupp (min_csr_err_unsupp),
.min_csr_err_nonex_wr (min_csr_err_nonex_wr),
.min_csr_err_nonex_rd (min_csr_err_nonex_rd),
.min_csr_err_unmap_wr (min_csr_err_unmap_wr),
.min_csr_err_err_cycle (min_csr_err_err_cycle),
.min_csr_err_unexp_dr (min_csr_err_unexp_dr),
.min_csr_err_l2_to0 (min_csr_err_l2_to0),
.min_csr_err_l2_to1 (min_csr_err_l2_to1),
.min_csr_err_l2_to2 (min_csr_err_l2_to2),
.min_csr_err_l2_to3 (min_csr_err_l2_to3),
.min_csr_write_log_addr (min_csr_write_log_addr),
.min_csr_log_addr_owner (min_csr_log_addr_owner[2:0]),
.min_csr_log_addr_adtype (min_csr_log_addr_adtype[7:0]),
.min_csr_log_addr_ttype (min_csr_log_addr_ttype[4:0]),
.min_csr_log_addr_addr (min_csr_log_addr_addr[42:0]),
.min_csr_log_data0 (min_csr_log_data0[63:0]),
.min_csr_log_data1 (min_csr_log_data1[63:0]),
.min_csr_log_ctl_owner (min_csr_log_ctl_owner[2:0]),
.min_csr_log_ctl_parity (min_csr_log_ctl_parity[3:0]),
.min_csr_log_ctl_adtype0 (min_csr_log_ctl_adtype0[7:0]),
.min_csr_log_ctl_adtype1 (min_csr_log_ctl_adtype1[7:0]),
.min_csr_log_ctl_adtype2 (min_csr_log_ctl_adtype2[7:0]),
.min_csr_log_ctl_adtype3 (min_csr_log_ctl_adtype3[7:0]),
.min_csr_log_ctl_adtype4 (min_csr_log_ctl_adtype4[7:0]),
.min_csr_log_ctl_adtype5 (min_csr_log_ctl_adtype5[7:0]),
.min_csr_log_ctl_adtype6 (min_csr_log_ctl_adtype6[7:0]),
.min_csr_perf_dma_rd_in (min_csr_perf_dma_rd_in),
.min_csr_perf_dma_wr (min_csr_perf_dma_wr),
.min_csr_perf_dma_rd_latency(min_csr_perf_dma_rd_latency[4:0]),
.min_csr_perf_dma_wr8 (min_csr_perf_dma_wr8),
.min_csr_perf_blk_q0 (min_csr_perf_blk_q0[3:0]),
.min_csr_perf_blk_q1 (min_csr_perf_blk_q1[3:0]),
.min_csr_perf_blk_q2 (min_csr_perf_blk_q2[3:0]),
.min_csr_perf_blk_q3 (min_csr_perf_blk_q3[3:0]),
.jbi_sctag0_req (jbi_sctag0_req[31:0]),
.jbi_scbuf0_ecc (jbi_scbuf0_ecc[6:0]),
.jbi_sctag0_req_vld (jbi_sctag0_req_vld),
.jbi_sctag1_req (jbi_sctag1_req[31:0]),
.jbi_scbuf1_ecc (jbi_scbuf1_ecc[6:0]),
.jbi_sctag1_req_vld (jbi_sctag1_req_vld),
.jbi_sctag2_req (jbi_sctag2_req[31:0]),
.jbi_scbuf2_ecc (jbi_scbuf2_ecc[6:0]),
.jbi_sctag2_req_vld (jbi_sctag2_req_vld),
.jbi_sctag3_req (jbi_sctag3_req[31:0]),
.jbi_scbuf3_ecc (jbi_scbuf3_ecc[6:0]),
.jbi_sctag3_req_vld (jbi_sctag3_req_vld),
.min_mout_inject_err (min_mout_inject_err),
.min_trans_jid (min_trans_jid[`JBI_JID_WIDTH-1:0]),
.min_snp_launch (min_snp_launch),
.min_free (min_free),
.min_free_jid (min_free_jid[`JBI_JID_WIDTH-1:0]),
.min_aok_on (min_aok_on),
.min_aok_off (min_aok_off),
.min_j_ad_ff (min_j_ad_ff[127:0]),
.min_pio_rtrn_push (min_pio_rtrn_push),
.min_pio_data_err (min_pio_data_err),
.min_mondo_hdr_push (min_mondo_hdr_push),
.min_mondo_data_push (min_mondo_data_push),
.min_mondo_data_err (min_mondo_data_err),
.min_oldest_wri_tag (min_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.min_pre_wri_tag (min_pre_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
// Inputs
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.arst_l (jbus_arst_l), // Templated
.testmux_sel (testmux_sel),
.rst_tri_en (rst_tri_en),
.cpu_clk (cmp_rclk), // Templated
.cpu_rst_l (cmp_rst_l), // Templated
.cpu_tx_en (tx_en_local), // Templated
.cpu_rx_en (rx_en_local), // Templated
.hold (sehold), // Templated
.csr_16x65array_margin (csr_16x65array_margin[4:0]),
.csr_jbi_config_port_pres(csr_jbi_config_port_pres[6:0]),
.csr_jbi_error_config_erren(csr_jbi_error_config_erren),
.csr_jbi_log_enb_apar (csr_jbi_log_enb_apar),
.csr_jbi_log_enb_dpar_wr (csr_jbi_log_enb_dpar_wr),
.csr_jbi_log_enb_dpar_rd (csr_jbi_log_enb_dpar_rd),
.csr_jbi_log_enb_rep_ue (csr_jbi_log_enb_rep_ue),
.csr_jbi_log_enb_nonex_rd(csr_jbi_log_enb_nonex_rd),
.csr_jbi_log_enb_err_cycle(csr_jbi_log_enb_err_cycle),
.csr_jbi_log_enb_dpar_o (csr_jbi_log_enb_dpar_o),
.csr_jbi_log_enb_unexp_dr(csr_jbi_log_enb_unexp_dr),
.csr_jbi_config2_iq_high (csr_jbi_config2_iq_high[3:0]),
.csr_jbi_config2_iq_low (csr_jbi_config2_iq_low[3:0]),
.csr_jbi_config2_max_rd (csr_jbi_config2_max_rd[1:0]),
.csr_jbi_config2_max_wr (csr_jbi_config2_max_wr[3:0]),
.csr_jbi_config2_ord_rd (csr_jbi_config2_ord_rd),
.csr_jbi_config2_ord_wr (csr_jbi_config2_ord_wr),
.csr_jbi_memsize_size (csr_jbi_memsize_size[37:30]),
.csr_jbi_config2_max_wris(csr_jbi_config2_max_wris[1:0]),
.csr_jbi_l2_timeout_timeval(csr_jbi_l2_timeout_timeval[31:0]),
.csr_jbi_err_inject_input(csr_jbi_err_inject_input),
.csr_jbi_err_inject_output(csr_jbi_err_inject_output),
.csr_jbi_err_inject_errtype(csr_jbi_err_inject_errtype),
.csr_jbi_err_inject_xormask(csr_jbi_err_inject_xormask[3:0]),
.csr_jbi_err_inject_count(csr_jbi_err_inject_count[23:0]),
.sctag0_jbi_iq_dequeue (sctag0_jbi_iq_dequeue),
.sctag0_jbi_wib_dequeue (sctag0_jbi_wib_dequeue),
.sctag1_jbi_iq_dequeue (sctag1_jbi_iq_dequeue),
.sctag1_jbi_wib_dequeue (sctag1_jbi_wib_dequeue),
.sctag2_jbi_iq_dequeue (sctag2_jbi_iq_dequeue),
.sctag2_jbi_wib_dequeue (sctag2_jbi_wib_dequeue),
.sctag3_jbi_iq_dequeue (sctag3_jbi_iq_dequeue),
.sctag3_jbi_wib_dequeue (sctag3_jbi_wib_dequeue),
.io_jbi_j_adtype (io_jbi_j_adtype[7:0]),
.io_jbi_j_ad (io_jbi_j_ad[127:0]),
.io_jbi_j_adp (io_jbi_j_adp[3:0]),
.mout_dsbl_sampling (mout_dsbl_sampling),
.mout_scb0_jbus_wr_ack (mout_scb0_jbus_wr_ack),
.mout_scb1_jbus_wr_ack (mout_scb1_jbus_wr_ack),
.mout_scb2_jbus_wr_ack (mout_scb2_jbus_wr_ack),
.mout_scb3_jbus_wr_ack (mout_scb3_jbus_wr_ack),
.mout_scb0_jbus_rd_ack (mout_scb0_jbus_rd_ack),
.mout_scb1_jbus_rd_ack (mout_scb1_jbus_rd_ack),
.mout_scb2_jbus_rd_ack (mout_scb2_jbus_rd_ack),
.mout_scb3_jbus_rd_ack (mout_scb3_jbus_rd_ack),
.mout_trans_valid (mout_trans_valid),
.mout_min_inject_err_done(mout_min_inject_err_done),
.mout_min_jbus_owner (mout_min_jbus_owner[5:0]));
//*******************************************************************************
// Memory Outbound Block
//*******************************************************************************
/* jbi_mout AUTO_TEMPLATE (
.cclk (cmp_rclk),
.crst_l (cmp_rst_l_ff0),
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.tx_en_local_m1 (tx_en_local),
.hold (sehold),
.arst_l (cmp_arst_l),
); */
jbi_mout u_mout(/*AUTOINST*/
// Outputs
.mout_pio_req_adv (mout_pio_req_adv),
.mout_pio_pop (mout_pio_pop),
.mout_mondo_pop (mout_mondo_pop),
.jbi_io_j_adtype (jbi_io_j_adtype[7:0]),
.jbi_io_j_adtype_en (jbi_io_j_adtype_en),
.jbi_io_j_ad (jbi_io_j_ad[127:0]),
.jbi_io_j_ad_en (jbi_io_j_ad_en[3:0]),
.jbi_io_j_adp (jbi_io_j_adp[3:0]),
.jbi_io_j_adp_en (jbi_io_j_adp_en),
.jbi_io_j_req0_out_l (jbi_io_j_req0_out_l),
.jbi_io_j_req0_out_en (jbi_io_j_req0_out_en),
.jbi_io_j_pack0 (jbi_io_j_pack0[2:0]),
.jbi_io_j_pack0_en (jbi_io_j_pack0_en),
.jbi_io_j_pack1 (jbi_io_j_pack1[2:0]),
.jbi_io_j_pack1_en (jbi_io_j_pack1_en),
.mout_dsbl_sampling (mout_dsbl_sampling),
.mout_trans_yid (mout_trans_yid[`JBI_YID_WIDTH-1:0]),
.mout_trans_valid (mout_trans_valid),
.mout_scb0_jbus_wr_ack (mout_scb0_jbus_wr_ack),
.mout_scb1_jbus_wr_ack (mout_scb1_jbus_wr_ack),
.mout_scb2_jbus_wr_ack (mout_scb2_jbus_wr_ack),
.mout_scb3_jbus_wr_ack (mout_scb3_jbus_wr_ack),
.mout_scb0_jbus_rd_ack (mout_scb0_jbus_rd_ack),
.mout_scb1_jbus_rd_ack (mout_scb1_jbus_rd_ack),
.mout_scb2_jbus_rd_ack (mout_scb2_jbus_rd_ack),
.mout_scb3_jbus_rd_ack (mout_scb3_jbus_rd_ack),
.mout_nack (mout_nack),
.mout_nack_buf_id (mout_nack_buf_id[1:0]),
.mout_nack_thr_id (mout_nack_thr_id[5:0]),
.mout_min_inject_err_done(mout_min_inject_err_done),
.mout_csr_inject_output_done(mout_csr_inject_output_done),
.mout_min_jbus_owner (mout_min_jbus_owner[5:0]),
.mout_port_4_present (mout_port_4_present),
.mout_port_5_present (mout_port_5_present),
.mout_csr_err_cpar (mout_csr_err_cpar),
.mout_csr_jbi_log_par_jpar(mout_csr_jbi_log_par_jpar),
.mout_csr_jbi_log_par_jpack0(mout_csr_jbi_log_par_jpack0[2:0]),
.mout_csr_jbi_log_par_jpack1(mout_csr_jbi_log_par_jpack1[2:0]),
.mout_csr_jbi_log_par_jpack4(mout_csr_jbi_log_par_jpack4[2:0]),
.mout_csr_jbi_log_par_jpack5(mout_csr_jbi_log_par_jpack5[2:0]),
.mout_csr_jbi_log_par_jreq(mout_csr_jbi_log_par_jreq[6:0]),
.mout_csr_err_arb_to (mout_csr_err_arb_to),
.jbi_log_arb_myreq (jbi_log_arb_myreq[2:0]),
.jbi_log_arb_reqtype (jbi_log_arb_reqtype[2:0]),
.jbi_log_arb_aok (jbi_log_arb_aok[6:0]),
.jbi_log_arb_dok (jbi_log_arb_dok[6:0]),
.jbi_log_arb_jreq (jbi_log_arb_jreq[6:0]),
.mout_csr_err_fatal (mout_csr_err_fatal[5:4]),
.mout_csr_err_read_to (mout_csr_err_read_to),
.mout_perf_aok_off (mout_perf_aok_off),
.mout_perf_dok_off (mout_perf_dok_off),
.mout_dbg_pop (mout_dbg_pop),
// Inputs
.scbuf0_jbi_data (scbuf0_jbi_data[31:0]),
.scbuf0_jbi_ctag_vld (scbuf0_jbi_ctag_vld),
.scbuf0_jbi_ue_err (scbuf0_jbi_ue_err),
.sctag0_jbi_por_req_buf (sctag0_jbi_por_req_buf),
.scbuf1_jbi_data (scbuf1_jbi_data[31:0]),
.scbuf1_jbi_ctag_vld (scbuf1_jbi_ctag_vld),
.scbuf1_jbi_ue_err (scbuf1_jbi_ue_err),
.sctag1_jbi_por_req_buf (sctag1_jbi_por_req_buf),
.scbuf2_jbi_data (scbuf2_jbi_data[31:0]),
.scbuf2_jbi_ctag_vld (scbuf2_jbi_ctag_vld),
.scbuf2_jbi_ue_err (scbuf2_jbi_ue_err),
.sctag2_jbi_por_req_buf (sctag2_jbi_por_req_buf),
.scbuf3_jbi_data (scbuf3_jbi_data[31:0]),
.scbuf3_jbi_ctag_vld (scbuf3_jbi_ctag_vld),
.scbuf3_jbi_ue_err (scbuf3_jbi_ue_err),
.sctag3_jbi_por_req_buf (sctag3_jbi_por_req_buf),
.ncio_pio_req (ncio_pio_req),
.ncio_pio_req_rw (ncio_pio_req_rw),
.ncio_pio_req_dest (ncio_pio_req_dest[1:0]),
.ncio_pio_ad (ncio_pio_ad[63:0]),
.ncio_pio_ue (ncio_pio_ue),
.ncio_pio_be (ncio_pio_be[15:0]),
.ncio_yid (ncio_yid[`JBI_YID_WIDTH-1:0]),
.ncio_mondo_req (ncio_mondo_req),
.ncio_mondo_ack (ncio_mondo_ack),
.ncio_mondo_agnt_id (ncio_mondo_agnt_id[`JBI_AD_INT_AGTID_WIDTH-1:0]),
.ncio_mondo_cpu_id (ncio_mondo_cpu_id[`JBI_AD_INT_CPUID_WIDTH-1:0]),
.ncio_prqq_level (ncio_prqq_level[`JBI_PRQQ_ADDR_WIDTH:0]),
.ncio_makq_level (ncio_makq_level[`JBI_MAKQ_ADDR_WIDTH:0]),
.io_jbi_j_pack4 (io_jbi_j_pack4[2:0]),
.io_jbi_j_pack5 (io_jbi_j_pack5[2:0]),
.io_jbi_j_req4_in_l (io_jbi_j_req4_in_l),
.io_jbi_j_req5_in_l (io_jbi_j_req5_in_l),
.io_jbi_j_par (io_jbi_j_par),
.min_free (min_free),
.min_free_jid (min_free_jid[3:0]),
.min_trans_jid (min_trans_jid[`JBI_JID_WIDTH-1:0]),
.min_aok_on (min_aok_on),
.min_aok_off (min_aok_off),
.min_snp_launch (min_snp_launch),
.ncio_mout_nack_pop (ncio_mout_nack_pop),
.min_mout_inject_err (min_mout_inject_err),
.csr_jbi_config_arb_mode(csr_jbi_config_arb_mode[1:0]),
.csr_jbi_arb_timeout_timeval(csr_jbi_arb_timeout_timeval[31:0]),
.csr_jbi_trans_timeout_timeval(csr_jbi_trans_timeout_timeval[31:0]),
.csr_jbi_err_inject_errtype(csr_jbi_err_inject_errtype),
.csr_jbi_err_inject_xormask(csr_jbi_err_inject_xormask[3:0]),
.csr_jbi_debug_info_enb (csr_jbi_debug_info_enb),
.csr_dok_on (csr_dok_on),
.csr_jbi_debug_arb_aggr_arb(csr_jbi_debug_arb_aggr_arb),
.csr_jbi_error_config_fe_enb(csr_jbi_error_config_fe_enb),
.csr_jbi_log_enb_read_to(csr_jbi_log_enb_read_to),
.dbg_req_transparent (dbg_req_transparent),
.dbg_req_arbitrate (dbg_req_arbitrate),
.dbg_req_priority (dbg_req_priority),
.dbg_data (dbg_data[127:0]),
.testmux_sel (testmux_sel),
.hold (sehold), // Templated
.rst_tri_en (rst_tri_en),
.cclk (cmp_rclk), // Templated
.crst_l (cmp_rst_l_ff0), // Templated
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.tx_en_local_m1 (tx_en_local), // Templated
.arst_l (cmp_arst_l)); // Templated
//*******************************************************************************
// NCIO Block (Non-Cached IO)
//*******************************************************************************
/* jbi_ncio AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.arst_l (jbus_arst_l),
.cpu_clk (cmp_rclk),
.cpu_rst_l (cmp_rst_l_ff1),
.hold (sehold),
.scan_en (se),
.io_jbi_j_ad_ff (min_j_ad_ff),
.cpu_tx_en (tx_en_local),
.cpu_rx_en (rx_en_local),
); */
jbi_ncio u_ncio (/*AUTOINST*/
// Outputs
.ncio_csr_err_intr_to (ncio_csr_err_intr_to[31:0]),
.ncio_csr_perf_pio_rd_out(ncio_csr_perf_pio_rd_out),
.ncio_csr_perf_pio_wr (ncio_csr_perf_pio_wr),
.ncio_csr_perf_pio_rd_latency(ncio_csr_perf_pio_rd_latency[4:0]),
.ncio_csr_read_addr (ncio_csr_read_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_write (ncio_csr_write),
.ncio_csr_write_addr (ncio_csr_write_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_write_data (ncio_csr_write_data[`JBI_CSR_WIDTH-1:0]),
.jbi_iob_pio_vld (jbi_iob_pio_vld),
.jbi_iob_pio_data (jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
.jbi_iob_pio_stall (jbi_iob_pio_stall),
.jbi_iob_mondo_vld (jbi_iob_mondo_vld),
.jbi_iob_mondo_data (jbi_iob_mondo_data[`JBI_IOB_MONDO_BUS_WIDTH-1:0]),
.ncio_pio_req (ncio_pio_req),
.ncio_pio_req_rw (ncio_pio_req_rw),
.ncio_pio_req_dest (ncio_pio_req_dest[1:0]),
.ncio_pio_ue (ncio_pio_ue),
.ncio_pio_be (ncio_pio_be[15:0]),
.ncio_pio_ad (ncio_pio_ad[63:0]),
.ncio_yid (ncio_yid[`JBI_YID_WIDTH-1:0]),
.ncio_prqq_level (ncio_prqq_level[`JBI_PRQQ_ADDR_WIDTH:0]),
.ncio_mondo_req (ncio_mondo_req),
.ncio_mondo_ack (ncio_mondo_ack),
.ncio_mondo_agnt_id (ncio_mondo_agnt_id[`JBI_AD_INT_AGTID_WIDTH-1:0]),
.ncio_mondo_cpu_id (ncio_mondo_cpu_id[`JBI_AD_INT_CPUID_WIDTH-1:0]),
.ncio_makq_level (ncio_makq_level[`JBI_MAKQ_ADDR_WIDTH:0]),
.ncio_mout_nack_pop (ncio_mout_nack_pop),
// Inputs
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.arst_l (jbus_arst_l), // Templated
.cpu_clk (cmp_rclk), // Templated
.cpu_rst_l (cmp_rst_l_ff1), // Templated
.cpu_rx_en (rx_en_local), // Templated
.cpu_tx_en (tx_en_local), // Templated
.hold (sehold), // Templated
.testmux_sel (testmux_sel),
.scan_en (se), // Templated
.rst_tri_en (rst_tri_en),
.csr_16x65array_margin (csr_16x65array_margin[4:0]),
.csr_16x81array_margin (csr_16x81array_margin[4:0]),
.csr_jbi_config2_max_pio(csr_jbi_config2_max_pio[3:0]),
.csr_jbi_config2_ord_int(csr_jbi_config2_ord_int),
.csr_jbi_config2_ord_pio(csr_jbi_config2_ord_pio),
.csr_jbi_intr_timeout_timeval(csr_jbi_intr_timeout_timeval[31:0]),
.csr_jbi_intr_timeout_rst_l(csr_jbi_intr_timeout_rst_l),
.csr_int_req (csr_int_req),
.csr_csr_read_data (csr_csr_read_data[`JBI_CSR_WIDTH-1:0]),
.iob_jbi_pio_stall (iob_jbi_pio_stall),
.iob_jbi_pio_vld (iob_jbi_pio_vld),
.iob_jbi_pio_data (iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),
.iob_jbi_mondo_ack (iob_jbi_mondo_ack),
.iob_jbi_mondo_nack (iob_jbi_mondo_nack),
.io_jbi_j_ad_ff (min_j_ad_ff), // Templated
.min_pio_rtrn_push (min_pio_rtrn_push),
.min_pio_data_err (min_pio_data_err),
.min_mondo_hdr_push (min_mondo_hdr_push),
.min_mondo_data_push (min_mondo_data_push),
.min_mondo_data_err (min_mondo_data_err),
.min_oldest_wri_tag (min_oldest_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.min_pre_wri_tag (min_pre_wri_tag[`JBI_WRI_TAG_WIDTH-1:0]),
.mout_trans_yid (mout_trans_yid[`JBI_YID_WIDTH-1:0]),
.mout_pio_pop (mout_pio_pop),
.mout_pio_req_adv (mout_pio_req_adv),
.mout_mondo_pop (mout_mondo_pop),
.mout_nack (mout_nack),
.mout_nack_buf_id (mout_nack_buf_id[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.mout_nack_thr_id (mout_nack_thr_id[`UCB_THR_HI-`UCB_THR_LO:0]));
//*******************************************************************************
// SSI (System Serial Interface)
//*******************************************************************************
/* jbi_ssi AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.arst_l (jbus_arst_l),
); */
jbi_ssi u_ssi (/*AUTOINST*/
// Outputs
.jbi_io_ssi_mosi (jbi_io_ssi_mosi),
.jbi_io_ssi_sck (jbi_io_ssi_sck),
.jbi_iob_spi_vld (jbi_iob_spi_vld),
.jbi_iob_spi_data (jbi_iob_spi_data[3:0]),
.jbi_iob_spi_stall (jbi_iob_spi_stall),
// Inputs
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.arst_l (jbus_arst_l), // Templated
.ctu_jbi_ssiclk (ctu_jbi_ssiclk),
.io_jbi_ssi_miso (io_jbi_ssi_miso),
.io_jbi_ext_int_l (io_jbi_ext_int_l),
.iob_jbi_spi_vld (iob_jbi_spi_vld),
.iob_jbi_spi_data (iob_jbi_spi_data[3:0]),
.iob_jbi_spi_stall (iob_jbi_spi_stall));
//*******************************************************************************
// Debug Port
//*******************************************************************************
/* jbi_dbg AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
.dbg_rst_l (jbus_rst_l),
.hold (sehold),
.scan_en (se),
); */
jbi_dbg u_dbg (/*AUTOINST*/
// Outputs
.dbg_req_transparent (dbg_req_transparent),
.dbg_req_arbitrate (dbg_req_arbitrate),
.dbg_req_priority (dbg_req_priority),
.dbg_data (dbg_data[127:0]),
// Inputs
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.dbg_rst_l (jbus_rst_l), // Templated
.hold (sehold), // Templated
.testmux_sel (testmux_sel),
.scan_en (se), // Templated
.csr_16x65array_margin (csr_16x65array_margin[4:0]),
.csr_jbi_debug_arb_max_wait(csr_jbi_debug_arb_max_wait[`JBI_CSR_DBG_MAX_WAIT_WIDTH-1:0]),
.csr_jbi_debug_arb_hi_water(csr_jbi_debug_arb_hi_water[`JBI_CSR_DBG_HI_WATER_WIDTH-1:0]),
.csr_jbi_debug_arb_lo_water(csr_jbi_debug_arb_lo_water[`JBI_CSR_DBG_LO_WATER_WIDTH-1:0]),
.csr_jbi_debug_arb_data_arb(csr_jbi_debug_arb_data_arb),
.csr_jbi_debug_arb_tstamp_wrap(csr_jbi_debug_arb_tstamp_wrap[`JBI_CSR_DBG_TSWRAP_WIDTH-1:0]),
.csr_jbi_debug_arb_alternate(csr_jbi_debug_arb_alternate),
.csr_jbi_debug_arb_alternate_set_l(csr_jbi_debug_arb_alternate_set_l),
.iob_jbi_dbg_hi_data (iob_jbi_dbg_hi_data[47:0]),
.iob_jbi_dbg_hi_vld (iob_jbi_dbg_hi_vld),
.iob_jbi_dbg_lo_data (iob_jbi_dbg_lo_data[47:0]),
.iob_jbi_dbg_lo_vld (iob_jbi_dbg_lo_vld),
.mout_dbg_pop (mout_dbg_pop));
//*******************************************************************************
// CSR
//*******************************************************************************
/* jbi_csr AUTO_TEMPLATE (
.clk (jbus_rclk),
.rst_l (jbus_rst_l),
); */
jbi_csr u_csr (/*AUTOINST*/
// Outputs
.csr_csr_read_data (csr_csr_read_data[`JBI_CSR_WIDTH-1:0]),
.csr_jbi_config_port_pres(csr_jbi_config_port_pres[6:0]),
.jbi_io_config_dtl (jbi_io_config_dtl[1:0]),
.csr_jbi_config_arb_mode (csr_jbi_config_arb_mode[1:0]),
.csr_jbi_config2_iq_high (csr_jbi_config2_iq_high[3:0]),
.csr_jbi_config2_iq_low (csr_jbi_config2_iq_low[3:0]),
.csr_jbi_config2_max_rd (csr_jbi_config2_max_rd[1:0]),
.csr_jbi_config2_max_wris(csr_jbi_config2_max_wris[1:0]),
.csr_jbi_config2_max_wr (csr_jbi_config2_max_wr[3:0]),
.csr_jbi_config2_ord_wr (csr_jbi_config2_ord_wr),
.csr_jbi_config2_ord_int (csr_jbi_config2_ord_int),
.csr_jbi_config2_ord_pio (csr_jbi_config2_ord_pio),
.csr_jbi_config2_ord_rd (csr_jbi_config2_ord_rd),
.csr_jbi_config2_max_pio (csr_jbi_config2_max_pio[3:0]),
.csr_16x65array_margin (csr_16x65array_margin[4:0]),
.csr_16x81array_margin (csr_16x81array_margin[4:0]),
.csr_jbi_debug_info_enb (csr_jbi_debug_info_enb),
.csr_jbi_debug_arb_tstamp_wrap(csr_jbi_debug_arb_tstamp_wrap[6:0]),
.csr_jbi_debug_arb_alternate(csr_jbi_debug_arb_alternate),
.csr_jbi_debug_arb_hi_water(csr_jbi_debug_arb_hi_water[4:0]),
.csr_jbi_debug_arb_lo_water(csr_jbi_debug_arb_lo_water[4:0]),
.csr_jbi_debug_arb_data_arb(csr_jbi_debug_arb_data_arb),
.csr_jbi_debug_arb_aggr_arb(csr_jbi_debug_arb_aggr_arb),
.csr_jbi_debug_arb_max_wait(csr_jbi_debug_arb_max_wait[9:0]),
.csr_jbi_debug_arb_alternate_set_l(csr_jbi_debug_arb_alternate_set_l),
.csr_jbi_err_inject_output(csr_jbi_err_inject_output),
.csr_jbi_err_inject_input(csr_jbi_err_inject_input),
.csr_jbi_err_inject_errtype(csr_jbi_err_inject_errtype),
.csr_jbi_err_inject_xormask(csr_jbi_err_inject_xormask[3:0]),
.csr_jbi_err_inject_count(csr_jbi_err_inject_count[23:0]),
.csr_jbi_error_config_fe_enb(csr_jbi_error_config_fe_enb),
.csr_jbi_error_config_erren(csr_jbi_error_config_erren),
.csr_jbi_error_config_sigen(csr_jbi_error_config_sigen),
.csr_jbi_log_enb_apar (csr_jbi_log_enb_apar),
.csr_jbi_log_enb_dpar_wr (csr_jbi_log_enb_dpar_wr),
.csr_jbi_log_enb_dpar_rd (csr_jbi_log_enb_dpar_rd),
.csr_jbi_log_enb_dpar_o (csr_jbi_log_enb_dpar_o),
.csr_jbi_log_enb_rep_ue (csr_jbi_log_enb_rep_ue),
.csr_jbi_log_enb_nonex_rd(csr_jbi_log_enb_nonex_rd),
.csr_jbi_log_enb_read_to (csr_jbi_log_enb_read_to),
.csr_jbi_log_enb_err_cycle(csr_jbi_log_enb_err_cycle),
.csr_jbi_log_enb_unexp_dr(csr_jbi_log_enb_unexp_dr),
.csr_int_req (csr_int_req),
.csr_dok_on (csr_dok_on),
.csr_jbi_l2_timeout_timeval(csr_jbi_l2_timeout_timeval[31:0]),
.csr_jbi_arb_timeout_timeval(csr_jbi_arb_timeout_timeval[31:0]),
.csr_jbi_trans_timeout_timeval(csr_jbi_trans_timeout_timeval[31:0]),
.csr_jbi_intr_timeout_timeval(csr_jbi_intr_timeout_timeval[31:0]),
.csr_jbi_intr_timeout_rst_l(csr_jbi_intr_timeout_rst_l),
.csr_jbi_memsize_size (csr_jbi_memsize_size[37:30]),
.jbi_clk_tr (jbi_clk_tr),
// Inputs
.ncio_csr_read_addr (ncio_csr_read_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_write (ncio_csr_write),
.ncio_csr_write_addr (ncio_csr_write_addr[`JBI_CSR_ADDR_WIDTH-1:0]),
.ncio_csr_write_data (ncio_csr_write_data[`JBI_CSR_WIDTH-1:0]),
.mout_port_4_present (mout_port_4_present),
.mout_port_5_present (mout_port_5_present),
.min_csr_inject_input_done(min_csr_inject_input_done),
.mout_csr_inject_output_done(mout_csr_inject_output_done),
.min_csr_err_apar (min_csr_err_apar),
.min_csr_err_adtype (min_csr_err_adtype),
.min_csr_err_dpar_wr (min_csr_err_dpar_wr),
.min_csr_err_dpar_rd (min_csr_err_dpar_rd),
.min_csr_err_dpar_o (min_csr_err_dpar_o),
.min_csr_err_rep_ue (min_csr_err_rep_ue),
.min_csr_err_illegal (min_csr_err_illegal),
.min_csr_err_unsupp (min_csr_err_unsupp),
.min_csr_err_nonex_wr (min_csr_err_nonex_wr),
.min_csr_err_nonex_rd (min_csr_err_nonex_rd),
.min_csr_err_err_cycle (min_csr_err_err_cycle),
.min_csr_err_unexp_dr (min_csr_err_unexp_dr),
.min_csr_err_unmap_wr (min_csr_err_unmap_wr),
.ncio_csr_err_intr_to (ncio_csr_err_intr_to[31:0]),
.min_csr_err_l2_to0 (min_csr_err_l2_to0),
.min_csr_err_l2_to1 (min_csr_err_l2_to1),
.min_csr_err_l2_to2 (min_csr_err_l2_to2),
.min_csr_err_l2_to3 (min_csr_err_l2_to3),
.mout_csr_err_cpar (mout_csr_err_cpar),
.mout_csr_err_arb_to (mout_csr_err_arb_to),
.mout_csr_err_fatal (mout_csr_err_fatal[5:4]),
.mout_csr_err_read_to (mout_csr_err_read_to),
.min_csr_write_log_addr (min_csr_write_log_addr),
.min_csr_log_addr_owner (min_csr_log_addr_owner[2:0]),
.min_csr_log_addr_adtype (min_csr_log_addr_adtype[7:0]),
.min_csr_log_addr_ttype (min_csr_log_addr_ttype[4:0]),
.min_csr_log_addr_addr (min_csr_log_addr_addr[42:0]),
.min_csr_log_ctl_owner (min_csr_log_ctl_owner[2:0]),
.min_csr_log_ctl_parity (min_csr_log_ctl_parity[3:0]),
.min_csr_log_ctl_adtype0 (min_csr_log_ctl_adtype0[7:0]),
.min_csr_log_ctl_adtype1 (min_csr_log_ctl_adtype1[7:0]),
.min_csr_log_ctl_adtype2 (min_csr_log_ctl_adtype2[7:0]),
.min_csr_log_ctl_adtype3 (min_csr_log_ctl_adtype3[7:0]),
.min_csr_log_ctl_adtype4 (min_csr_log_ctl_adtype4[7:0]),
.min_csr_log_ctl_adtype5 (min_csr_log_ctl_adtype5[7:0]),
.min_csr_log_ctl_adtype6 (min_csr_log_ctl_adtype6[7:0]),
.min_csr_log_data0 (min_csr_log_data0[63:0]),
.min_csr_log_data1 (min_csr_log_data1[63:0]),
.mout_csr_jbi_log_par_jpar(mout_csr_jbi_log_par_jpar),
.mout_csr_jbi_log_par_jpack5(mout_csr_jbi_log_par_jpack5[2:0]),
.mout_csr_jbi_log_par_jpack4(mout_csr_jbi_log_par_jpack4[2:0]),
.mout_csr_jbi_log_par_jpack1(mout_csr_jbi_log_par_jpack1[2:0]),
.mout_csr_jbi_log_par_jpack0(mout_csr_jbi_log_par_jpack0[2:0]),
.mout_csr_jbi_log_par_jreq(mout_csr_jbi_log_par_jreq[6:0]),
.jbi_log_arb_myreq (jbi_log_arb_myreq[2:0]),
.jbi_log_arb_reqtype (jbi_log_arb_reqtype[2:0]),
.jbi_log_arb_aok (jbi_log_arb_aok[6:0]),
.jbi_log_arb_dok (jbi_log_arb_dok[6:0]),
.jbi_log_arb_jreq (jbi_log_arb_jreq[6:0]),
.min_csr_perf_dma_rd_in (min_csr_perf_dma_rd_in),
.min_csr_perf_dma_rd_latency(min_csr_perf_dma_rd_latency[4:0]),
.min_csr_perf_dma_wr (min_csr_perf_dma_wr),
.min_csr_perf_dma_wr8 (min_csr_perf_dma_wr8),
.min_csr_perf_blk_q0 (min_csr_perf_blk_q0[3:0]),
.min_csr_perf_blk_q1 (min_csr_perf_blk_q1[3:0]),
.min_csr_perf_blk_q2 (min_csr_perf_blk_q2[3:0]),
.min_csr_perf_blk_q3 (min_csr_perf_blk_q3[3:0]),
.ncio_csr_perf_pio_rd_out(ncio_csr_perf_pio_rd_out),
.ncio_csr_perf_pio_wr (ncio_csr_perf_pio_wr),
.ncio_csr_perf_pio_rd_latency(ncio_csr_perf_pio_rd_latency[4:0]),
.mout_perf_aok_off (mout_perf_aok_off),
.mout_perf_dok_off (mout_perf_dok_off),
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.ctu_jbi_fst_rst_l (ctu_jbi_fst_rst_l),
.sehold (sehold));
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
parameter CNT = 5;
wire [31:0] w [CNT:0];
generate
for (genvar g=0; g<CNT; g++)
sub sub (.clk(clk), .i(w[g]), .z(w[g+1]));
endgenerate
reg [31:0] w0;
assign w[0] = w0;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
w0 = 32'h1234;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
`define EXPECTED_SUM 32'h1239
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d sum=%x\n",$time, cyc, w[CNT]);
`endif
if (w[CNT] !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module sub (input clk, input [31:0] i, output [31:0] z);
logic [31:0] z_tmp /* verilator public */;
always @(posedge clk)
z_tmp <= i+1+$c("0"); // $c so doesn't optimize away
assign z = z_tmp;
endmodule
|
module modmult #( parameter n_words = 4
, parameter w_width = 27
, parameter b_offset = 1 // bit offset of MSB for modulo reduction (see note below)
, parameter last_factor = 0 // how many factors are in the modulo reduction? (see note below)
, parameter factor_1 = 0 // factors range from 0 to 15 (represented as 4 bits internally)
, parameter factor_2 = 0
, parameter factor_3 = 0
////////////// BELOW THIS LINE SHOULD BE LOCALAPARAMS - see note ---------------vv
, parameter wbits = $clog2(n_words) // the rest of these should be localparams
, parameter o_width = 2*w_width + wbits + b_offset + 1 // but Quartus follows V2001 strictly and
, parameter m_width = 2*w_width + wbits // does not allow localparams within the
, parameter nres = 2*n_words - 1 // ANSI style parameter list.
, parameter rbits = $clog2(nres) // Do not override these values!!!
)
( output [8:0] m_addr
, output m_rden
, output m_wren
, output [w_width-1:0] m_datao
, input [w_width-1:0] m_datai
, input [w_width-1:0] t_datai
, input aclr
, input clk
, input [2:0] command
, output command_ack
);
/*
*** b_offset explanation ***
We are reducing the product mod a number of bits equal to n_words *
w_width - b_offset. The assumption is that we are reducing a Mersenne or
Crandall prime, which means that we are going to add the MSBs with some
shifts to the LSBs. So that we know where those MSBs start, we
parameterize over b_offset.
After finishing the multiplies, when we read the values out of the
multipliers, we offset the values into the higher-order registers.
When we resolve the carry bits, we simultaneously take the (w_width-
b_offset)th bit from result_reg[n_words-1] and add it into the LSB
of the result_reg[n_words] register, which makes the value stored in
result_reg[n_words-1:0] a (n_words*w_width - b_offset) bit value.
*/
/*
*** last_factor explanation ***
This block assumes that we are reducing the multiplication result mod a
Mersenne or Crandall number, that is, one of the form
2^k - n
for n small and of low Hamming weight. For example, 2^107-1 (Mersenne)
and 2^104 - 17 (Crandall) are both primes.
To reduce mod 2^107-1, note that a product of two 107-bit numbers will
be, at most 214 bits, and further that the result can be viewed as
having two words, w0 and w1, of 107 bits. In other words, the product is
w0 + 2^107*w1. But 2^107 mod 2^107-1 is 1, so the modular reduction
of 2^107*w1 is just w1, and thus the modular reduction of w0 + 2^107*w1
is just w0 + w1.
A similar argument applies to 2^104-17. Now the product is
w0 + 2^104*w1, and 2^104 mod 2^104-17 = 17, so the reduction is
w0 + 17*w1, or w0 + w1 + w1 << 4. (This is why we want n to be of low
Hamming weight.)
factor_0 is always 0. If we are reducing mod a Crandall number, then we
need to add other factors, e.g., 4 in the case above. In this case, also
be sure to change the last_factor parameter.
*/
// last_factor can't be higher than 3; we don't have the support for it
localparam last_factor_int = (last_factor > 3) ? 3 : last_factor;
// '$max' not supported for synthesis even though this is all static data. BOOO.
// add 2 bits for margin in case I've misapprehended the widest possible post-reduction carry.
// TODO: REVISIT if there are problems with synthesis speed.
localparam maxfact_tmp = 2 + ( (factor_3 > factor_2) ?
(factor_3 > factor_1 ?
(factor_3 > 0 ? factor_3 : 0) :
(factor_1 > 0 ? factor_1 : 0)) :
(factor_2 > factor_1 ?
(factor_2 > 0 ? factor_2 : 0) :
(factor_1 > 0 ? factor_1 : 0)) );
localparam maxfactor = (maxfact_tmp < w_width) ? maxfact_tmp : w_width;
localparam r_width = w_width + b_offset + maxfactor;
localparam d_width = w_width + maxfactor;
localparam h_width = w_width + wbits + b_offset + 1;
reg [w_width-1:0] result_reg[n_words-1:0], result_next[n_words-1:0];
reg [w_width-1:0] rshifto_reg[n_words-1:0], rshifto_next[n_words-1:0];
reg [w_width-1:0] mac_y_reg[n_words-1:0], mac_y_next[n_words-1:0];
wire [m_width-1:0] mult_out[n_words-1:0];
reg [w_width-1:0] mac_x, mac_x_reg[n_words-1:0], mac_x_next[n_words-1:0];
wire [n_words-1:0] en_accum;
wire en_mac;
reg [o_width-1:0] mult_o0_reg[n_words-1:0], mult_o0_next[n_words-1:0];
reg [h_width:0] mult_o1h_reg[nres-2:n_words], mult_o1h_next[nres-2:n_words];
reg [o_width-1:0] mult_o1h_n_reg, mult_o1h_n_next;
reg [w_width-1:0] mult_o1l_reg[n_words-1:0], mult_o1l_next[n_words-1:0];
reg [w_width:0] mult_o2_reg[nres-2:n_words], mult_o2_next[nres-2:n_words];
reg [o_width-1:0] mult_o2_n_reg, mult_o2_n_next;
reg [d_width:0] redc_reg[0:last_factor][n_words-2:0], redc_next[0:last_factor][n_words-2:0];
reg [o_width-1:0] redc_n_reg[0:last_factor], redc_n_next[0:last_factor];
reg [w_width:0] carry_o0_reg[n_words-2:0], carry_o0_next[n_words-2:0];
reg [r_width:0] carry_o0_n_reg, carry_o0_n_next;
reg [w_width:0] carry_o1_reg[n_words-2:0], carry_o1_next[n_words-2:0];
reg [r_width:0] carry_o1_n_reg, carry_o1_n_next;
/* *** MULTIPLIERS *** */
genvar MacIter;
generate for(MacIter=0; MacIter<n_words; MacIter++) begin: MacInst
mac_element #( .o_width (m_width)
) mInst ( .data_y (mac_y_reg[MacIter])
, .data_x (mac_x)
, .result (mult_out[MacIter])
, .clk (clk)
, .clken_y (en_mac)
, .clken_x (en_mac)
, .clken_o (en_mac)
, .accumulate (en_accum[MacIter])
, .aclr (aclr)
);
end
endgenerate
/* *** CARRY TREE *** */
wire [n_words-1:2] carry_gen;
wire [n_words-1:2] carry_prop;
wire [n_words-1:2] carry_out;
reg [n_words-1:2] carry_t_reg, carry_t_next;
generate for(MacIter=2; MacIter<n_words; MacIter++) begin: CTreeWires
assign carry_gen[MacIter] = carry_o0_reg[MacIter-1][w_width];
assign carry_prop[MacIter] = &(carry_o0_reg[MacIter-1][w_width-1:0]);
end
endgenerate
carry_tree #( .n_words (n_words-2)
) ctree_inst
( .g (carry_gen[n_words-1:2])
, .p (carry_prop[n_words-1:2])
, .c (carry_out[n_words-1:2])
);
// How many bits could the result after carry tree extend above the "top" of result_reg[n_words-1]?
//
// At maximum, the value in result_reg[2*n_words-2] after multiplication and shifting
// is 2*w_width+b_offset bits wide (because the maximum possible size of the result
// of a multiply is 2*n_words*w_width for n_words*w_width inputs, and we shift that
// up by b_offset). We added that to the low-order words with up to maxfactor shift.
// So we could have as many as maxfactor+b_offset bits above w_width-1, and recall
// that result_reg[n_words-1] is only supposed to be w_width-b_offset bits wide.
wire [2*b_offset+maxfactor:0] reduce_detect = carry_o1_n_reg[w_width+b_offset+maxfactor:w_width-b_offset];
wire continue_reducing = |(reduce_detect);
// In short, if any of these bits are nonzero, we have more reduction to do.
/* *** STATE MACHINE PARAMS *** */
reg [2:0] state_reg, state_next;
reg [wbits-1:0] count_reg, count_next;
reg square_reg, square_next, rammult_reg, rammult_next;
wire last_count = count_reg == (n_words - 1);
`include "mult_commands.vh"
localparam ST_IDLE = 3'b000;
localparam ST_PRELOAD = 3'b001;
localparam ST_STORE = 3'b010;
localparam ST_BEGINMULT = 3'b100;
localparam ST_SHUFFLE = 3'b101;
localparam ST_REDUCE = 3'b110;
localparam ST_CARRY = 3'b111;
wire inST_IDLE = state_reg == ST_IDLE;
wire inST_PRELOAD = state_reg == ST_PRELOAD;
wire inST_STORE = state_reg == ST_STORE;
wire inST_BEGINMULT = state_reg == ST_BEGINMULT;
wire inST_SHUFFLE = state_reg == ST_SHUFFLE;
wire inST_REDUCE = state_reg == ST_REDUCE;
wire inST_CARRY = state_reg == ST_CARRY;
wire nextST_BEGINRAMMULT = inST_IDLE & (command == CMD_BEGINRAMMULT);
wire nextST_BEGINMULT = inST_IDLE & (command == CMD_BEGINMULT);
wire nextST_BEGINSQUARE = inST_IDLE & (command == CMD_BEGINSQUARE);
wire nextST_PRELOAD = inST_IDLE & (command == CMD_PRELOAD);
wire nextST_STORE = inST_IDLE & (command == CMD_STORE);
wire nextST_SHUFFLE = inST_BEGINMULT & last_count;
wire nextST_REDUCE = inST_SHUFFLE & (count_reg == {'0,2'b10});
wire nextST_CARRY = inST_REDUCE & (count_reg == last_factor_int);
/* *** COMBINATIONAL CONTROL SIGNALS *** */
assign command_ack = inST_IDLE;
// address to read/write is determined by state_next and count_next
// such that we are ready to go with our reads/writes immediately
// upon entering a state
assign m_rden = nextST_PRELOAD | inST_PRELOAD | nextST_BEGINRAMMULT | rammult_reg;
assign m_wren = inST_STORE;
assign m_addr = m_wren ? {'0,2'b10,count_reg} : {'0,state_next[1:0],count_next};
assign m_datao = m_wren ? rshifto_reg[0] : '0;
assign en_mac = nextST_BEGINMULT | inST_BEGINMULT | inST_SHUFFLE;
/* Timing sequence for BEGINMULT state
cnt_next cnt_reg inX inY accum output[0] comment
0 X 0 X '0 X ST_IDLE transitioning to ST_BEGINMULT
1 0 d[0] res '1 X ST_BEGINMULT, cnt_reg == 0
2 1 d[1] res<< 'b1110 0
3 2 d[2] res<< 'b1101 d[0]*res
0 3 d[3] res<< 'b1011 d[1]*res<< cnt_next = 0, state_next = ST_SHUFFLE
0 0 0 X '0 d[2]*res<< ST_SHUFFLE
0 1 0 X '0 d[3]*res<<
*/
assign en_accum[n_words-1] = inST_BEGINMULT;
generate for(MacIter=0; MacIter<n_words-1; MacIter++) begin: EnAccInst
assign en_accum[MacIter] = inST_BEGINMULT & (count_reg != MacIter + 1);
end
endgenerate
// as we enter ST_BEGINMULT, mac_x = 0 so that we clear the output registers
// once in ST_BEGINMULT, choose source for X based on multiplication mode
always_comb begin
if (inST_BEGINMULT) begin
if (square_reg) begin
mac_x = mac_x_reg[0];
end else if (rammult_reg) begin
mac_x = m_datai;
end else begin
mac_x = t_datai;
end
end else begin
mac_x = '0;
end
end
// sadly, while Altera's synthesis could handle modmult_v_reduce_step with a task, ModelSim cannot, so we use a `define instead.
`ifndef modmult_v_reduce_step
`define modmult_v_reduce_step(j,k) \
generate if (last_factor_int > (``j``-1)) begin \
always_comb begin \
for (int i=0; i<n_words-1; i++) begin \
redc_next[``j``][i] = redc_reg[``j``][i]; \
end \
redc_n_next[``j``] = redc_n_reg[``j``]; \
if ((state_reg == ST_REDUCE) & (count_reg == ``j``)) begin \
for(int i=0; i<n_words-2; i++) begin \
redc_next[``j``][i] = redc_reg[``j``-1][i] + {mult_o2_reg[n_words+i],{``k``{1'b0}}}; \
end \
redc_next[``j``][n_words-2] = redc_reg[``j``-1][n_words-2] + {'0,mult_o2_n_reg[w_width-1:0],{``k``{1'b0}}}; \
redc_n_next[``j``] = redc_n_reg[``j``-1] + {'0,mult_o2_n_reg[o_width-1:w_width],{``k``{1'b0}}}; \
end \
end \
end \
endgenerate
`else //modmult_v_reduce_step
`error_multmult_v_reduce_step_macro_already_defined
`endif
`modmult_v_reduce_step(1, factor_1)
`modmult_v_reduce_step(2, factor_2)
`modmult_v_reduce_step(3, factor_3)
// careful to undef things once we're done with them
`ifdef modmult_v_reduce_step
`undef modmult_v_reduce_step
`endif //modmult_v_reduce_step
/* *** STATE TRANSITION LOGIC *** */
always_comb begin
result_next = result_reg;
rshifto_next = rshifto_reg;
mac_y_next = mac_y_reg;
mac_x_next = mac_x_reg;
mult_o0_next = mult_o0_reg;
mult_o1l_next = mult_o1l_reg;
mult_o1h_next = mult_o1h_reg;
mult_o1h_n_next = mult_o1h_n_reg;
mult_o2_next = mult_o2_reg;
mult_o2_n_next = mult_o2_n_reg;
carry_o0_next = carry_o0_reg;
carry_o0_n_next = carry_o0_n_reg;
carry_o1_next = carry_o1_reg;
carry_o1_n_next = carry_o1_n_reg;
carry_t_next = carry_t_reg;
state_next = state_reg;
count_next = count_reg;
square_next = square_reg;
rammult_next = rammult_reg;
for (int i=0; i<n_words-1; i++) begin
redc_next[0][i] = redc_reg[0][i];
end
redc_n_next[0] = redc_n_reg[0];
case (state_reg)
ST_IDLE: begin
count_next = '0;
case (command)
CMD_BEGINRAMMULT, CMD_BEGINMULT, CMD_BEGINSQUARE: begin
for (int i=0; i<n_words; i++) begin
mac_y_next[i] = result_reg[i][w_width-1:0];
end
if (command == CMD_BEGINSQUARE) begin
square_next = '1;
rammult_next = '0;
for (int i=0; i<n_words; i++) begin
mac_x_next[i] = result_reg[i][w_width-1:0];
end
end else if (command == CMD_BEGINRAMMULT) begin
square_next = '0;
rammult_next = '1;
end else begin
square_next = '0;
rammult_next = '0;
end
state_next = ST_BEGINMULT;
end
CMD_RESETRESULT: begin
// reset result register to {'0,1'b1}
result_next[0] = {'0,1'b1};
for (int i=1; i<n_words; i++) begin
result_next[i] = '0;
end
//TODO: optimization: remember that result=1, and next time we're
//asked to multiply or square, we can do so quickly by copying
//the input to the result register or no-op, respectively.
end
CMD_STORE: begin
for (int i=0; i<n_words; i++) begin
rshifto_next[i] = result_reg[i];
end
state_next = ST_STORE;
end
CMD_PRELOAD: state_next = ST_PRELOAD;
default: state_next = ST_IDLE;
endcase
end
ST_PRELOAD: begin
for (int i=0; i<n_words; i++) begin
if (count_reg == i) begin
result_next[i][w_width-1:0] = m_datai[w_width-1:0];
end
end
if (last_count) begin // on the last word; we're done
state_next = ST_IDLE;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
end
ST_STORE: begin
for (int i=0; i<n_words-1; i++) begin
rshifto_next[i] = rshifto_reg[i+1];
end
if (last_count) begin
state_next = ST_IDLE;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
end
ST_BEGINMULT: begin
// read out intermediate results as they're available, rippling carries up the chain
if (count_reg == 2) begin
mult_o0_next[0] = mult_out[0];
end
for (int i=3; i<n_words; i++) begin
if (count_reg == i) begin
mult_o0_next[i-2] = mult_out[i-2] + {'0,mult_o0_reg[i-3][o_width-1:w_width]};
mult_o1l_next[i-3] = mult_o0_reg[i-3][w_width-1:0];
end
end
// cyclic shift of y input to multipliers
for (int i=0; i<n_words; i++) begin
automatic int j = i-1 + (i-1 < 0 ? n_words : 0);
mac_y_next[i] = mac_y_reg[j];
end
// if we're squaring, shift the next word of the X operand into mac_x_reg[0]
if (square_reg) begin
for (int i=0; i<n_words-1; i++) begin
mac_x_next[i] = mac_x_reg[i+1];
end
end
if (last_count) begin
state_next = ST_SHUFFLE;
square_next = '0;
rammult_next = '0;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
end
/*
NOTE: in principle, we could save some registers by delaying the offset one cycle,
at the cost of an additional cycle of latency.
TODO: REVISIT if we're having trouble fitting.
*/
ST_SHUFFLE: begin
count_next = count_reg + 1'b1;
case (count_reg)
{'0}: begin
// read out intermediate result, as above, doing ripples
mult_o0_next[n_words-2] = mult_out[n_words-2] + {'0,mult_o0_reg[n_words-3][o_width-1:w_width]};
mult_o1l_next[n_words-3] = mult_o0_reg[n_words-3][w_width-1:0];
end
{'0,1'b1}: begin
// here we finally introduce the offset implied by b_offset
// ripple into nwords-1 register
mult_o0_next[n_words-1] = {'0,mult_out[n_words-1][w_width-b_offset-1:0]} + {'0,mult_o0_reg[n_words-2][o_width-1:w_width]};
mult_o1l_next[n_words-2] = mult_o0_reg[n_words-2][w_width-1:0];
// copy from multout into high registers, resolving one round of saved carries
for(int i=0; i<n_words-1; i++) begin
automatic int j = i-1 + (i-1 < 0 ? n_words : 0);
if (i < n_words - 2) begin
// offset the mult_out into the high registers
mult_o1h_next[i+n_words] = {'0,mult_out[i][w_width-b_offset-1:0],{(b_offset){1'b0}}} + {'0,mult_out[j][m_width-1:w_width-b_offset]};
end else begin
// highest mult_out is a doubleword, so we don't mask its high bits
mult_o1h_n_next = {'0,mult_out[i],{(b_offset){1'b0}}} + {'0,mult_out[j][m_width-1:w_width-b_offset]};
end
end
end
{'0,2'b10}: begin
// mult_o2_reg[n_words-1] is only w_width-b_offset large. We carry everything else up
mult_o1l_next[n_words-1] = {'0,mult_o0_reg[n_words-1][w_width-b_offset-1:0]};
mult_o2_next[n_words] = {'0,mult_o1h_reg[n_words][w_width-1:0]} + {'0,mult_o0_reg[n_words-1][h_width:w_width-b_offset]};
for(int i=n_words+1; i<nres-1; i++) begin
// TODO: REVISIT this optimization; can we add in fewer bits?
// In the previous step, we added numbers of w_width-b_offset and (m_width-(w_width-b_offset)) bits.
// m_width = 2*w_width + wbits, so we have a sum of (w_width - b_offset) + (w_width + wbits + b_offset)
// Max width is thus w_width + wbits + b_offset + 1.
// here we are adding one more bit than this, which should certainly be sufficient
mult_o2_next[i] = {'0,mult_o1h_reg[i][w_width-1:0]} + {'0,mult_o1h_reg[i-1][h_width:w_width]};
end
// the most significant word is actually a double word, so do not mask it
mult_o2_n_next = mult_o1h_n_reg + {'0,mult_o1h_reg[nres-2][h_width:w_width]};
// now we just have to resolve the possible carry-outs with a carry tree (after reducing)
// (carry propagate is result[w_width-1:0]=='1, carry generate is result[w_width]==1'b1
// at this point, the carries have been completely propagated to the higher-order words
// this means we are safe to start the modulo reduction (though be careful because the
// high words can still have carries in the (w_width+1)th bit position. That's OK---
// we'll resolve those during the modular reduction
// NOTE that this approach means that we don't have to bother with the carry tree until
// the very very end. This is pretty sweet.
state_next = ST_REDUCE;
count_next = '0;
end
default: begin
// something wrong here; give up
state_next = ST_IDLE;
count_next = '0;
end
endcase
end
ST_REDUCE: begin
if (count_reg == last_factor_int) begin
state_next = ST_CARRY;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
/* there is danger of overflow here fi result[n_words+i] has excess carry bits or factor is too big */
if (count_reg == 0) begin
for(int i=0; i<n_words-2; i++) begin
redc_next[0][i] = mult_o1l_reg[i] + mult_o2_reg[n_words+i];
end
/* special cases: split lower and upper half of the nres'th register */
redc_next[0][n_words-2] = mult_o1l_reg[n_words-2] + {'0,mult_o2_n_reg[w_width-1:0]};
redc_n_next[0] = mult_o1l_reg[n_words-1] + {'0,mult_o2_n_reg[o_width-1:w_width]};
end
end
ST_CARRY: begin
count_next = count_reg + 1'b1;
case (count_reg)
{'0,2'b00}: begin
// carry width in redc is maxfactor (already includes 2-bit safety margin, see above)
carry_o0_next[0] = {'0,redc_reg[last_factor_int][0][w_width-1:0]};
for(int i=1; i<n_words-1; i++) begin
carry_o0_next[i] = {'0,redc_reg[last_factor_int][i][w_width-1:0]} + {'0,redc_reg[last_factor_int][i-1][d_width:w_width]};
end
carry_o0_n_next = redc_n_reg[last_factor_int] + {'0,redc_reg[last_factor_int][n_words-2][d_width:w_width]};
end
{'0,2'b01}: begin
carry_t_next = carry_out;
end
{'0,2'b10}: begin
// since maxfactor <= w_width (enforced above)
// we know that at this point we have at most 1 bit of carry
// so it's time for the carry tree!
carry_o1_next[0] = carry_o0_reg[0];
carry_o1_next[1] = carry_o0_reg[1] & {w_width{1'b1}};
for(int i=2; i<n_words-1; i++) begin
carry_o1_next[i] = (carry_o0_reg[i] + {'0,carry_t_reg[i]}) & {w_width{1'b1}};
end
carry_o1_n_next = carry_o0_n_reg + {'0,carry_t_reg[n_words-1]};
end
{'0,2'b11}: begin
// clear out high-order result registers
for(int i=n_words+1; i<nres-1; i++) begin
mult_o2_next[i] = '0;
end
mult_o2_n_next = '0;
// any remaining carry coming out of the top of the register gets moved to mult_o2_reg[n_words]
mult_o2_next[n_words] = {'0,reduce_detect};
mult_o1l_next[n_words-1] = {'0,carry_o1_n_reg[w_width-b_offset-1:0]};
// write result registers in case we're done
result_next[n_words-1] = {'0,carry_o1_n_reg[w_width-b_offset-1:0]};
for(int i=0; i<n_words-1; i++) begin
result_next[i] = carry_o1_reg[i][w_width-1:0];
mult_o1l_next[i] = carry_o1_reg[i][w_width-1:0];
end
// Now we detect whether to do another reduction step or not.
if (continue_reducing) begin
state_next = ST_REDUCE;
end else begin
state_next = ST_IDLE;
end
count_next = '0;
end
default: begin
// something wrong here; give up
state_next = ST_IDLE;
count_next = '0;
end
endcase
end
default: begin
// something wrong here; give up
state_next = ST_IDLE;
end
endcase
end
/* *** FLIP-FLOPS *** */
always_ff @(posedge clk or posedge aclr) begin
if (aclr) begin
state_reg <= '0;
count_reg <= '0;
rammult_reg <= '0;
result_reg <= '{default:0};
rshifto_reg <= '{default:0};
square_reg <= '0;
mac_y_reg <= '{default:0};
mac_x_reg <= '{default:0};
mult_o0_reg <= '{default:0};
mult_o1l_reg <= '{default:0};
mult_o1h_reg <= '{default:0};
mult_o1h_n_reg <= '0;
mult_o2_reg <= '{default:0};
mult_o2_n_reg <= '0;
redc_reg <= '{default:0};
redc_n_reg <= '{default:0};
carry_o0_reg <= '{default:0};
carry_o0_n_reg <= '0;
carry_o1_reg <= '{default:0};
carry_o1_n_reg <= '0;
carry_t_reg <= '0;
end else begin
state_reg <= state_next;
count_reg <= count_next;
rammult_reg <= rammult_next;
result_reg <= result_next;
rshifto_reg <= rshifto_next;
square_reg <= square_next;
mac_y_reg <= mac_y_next;
mac_x_reg <= mac_x_next;
mult_o0_reg <= mult_o0_next;
mult_o1l_reg <= mult_o1l_next;
mult_o1h_reg <= mult_o1h_next;
mult_o1h_n_reg <= mult_o1h_n_next;
mult_o2_reg <= mult_o2_next;
mult_o2_n_reg <= mult_o2_n_next;
redc_reg <= redc_next;
redc_n_reg <= redc_n_next;
carry_o0_reg <= carry_o0_next;
carry_o0_n_reg <= carry_o0_n_next;
carry_o1_reg <= carry_o1_next;
carry_o1_n_reg <= carry_o1_n_next;
carry_t_reg <= carry_t_next;
end
end
endmodule
|
module sky130_fd_sc_ms__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module axi_hdmi_rx_tpm (
hdmi_clk,
hdmi_sof,
hdmi_de,
hdmi_data,
hdmi_tpm_oos);
input hdmi_clk;
input hdmi_sof;
input hdmi_de;
input [15:0] hdmi_data;
output hdmi_tpm_oos;
wire [15:0] hdmi_tpm_lr_data_s;
wire hdmi_tpm_lr_mismatch_s;
wire [15:0] hdmi_tpm_fr_data_s;
wire hdmi_tpm_fr_mismatch_s;
reg [15:0] hdmi_tpm_data = 'd0;
reg hdmi_tpm_lr_mismatch = 'd0;
reg hdmi_tpm_fr_mismatch = 'd0;
reg hdmi_tpm_oos = 'd0;
// Limited range
assign hdmi_tpm_lr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h10) ? 8'h10 :
((hdmi_tpm_data[15:8] > 8'heb) ? 8'heb : hdmi_tpm_data[15:8]);
assign hdmi_tpm_lr_data_s[ 7:0] = (hdmi_tpm_data[ 7:0] < 8'h10) ? 8'h10 :
((hdmi_tpm_data[ 7:0] > 8'heb) ? 8'heb : hdmi_tpm_data[ 7:0]);
assign hdmi_tpm_lr_mismatch_s = (hdmi_tpm_lr_data_s == hdmi_data) ? 1'b0 : 1'b1;
// Full range
assign hdmi_tpm_fr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h01) ? 8'h01 :
((hdmi_tpm_data[15:8] > 8'hfe) ? 8'hfe : hdmi_tpm_data[15:8]);
assign hdmi_tpm_fr_data_s[ 7:0] = (hdmi_tpm_data[ 7:0] < 8'h01) ? 8'h01 :
((hdmi_tpm_data[ 7:0] > 8'hfe) ? 8'hfe : hdmi_tpm_data[ 7:0]);
assign hdmi_tpm_fr_mismatch_s = (hdmi_tpm_fr_data_s == hdmi_data) ? 1'b0 : 1'b1;
always @(posedge hdmi_clk) begin
if (hdmi_sof == 1'b1) begin
hdmi_tpm_data <= 16'd0;
hdmi_tpm_lr_mismatch <= 1'd0;
hdmi_tpm_fr_mismatch <= 1'd0;
hdmi_tpm_oos <= hdmi_tpm_lr_mismatch & hdmi_tpm_fr_mismatch;
end else if (hdmi_de == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
hdmi_tpm_lr_mismatch <= hdmi_tpm_lr_mismatch | hdmi_tpm_lr_mismatch_s;
hdmi_tpm_fr_mismatch <= hdmi_tpm_fr_mismatch | hdmi_tpm_fr_mismatch_s;
end
end
endmodule
|
module dist_mem_gen_1 (
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input wire [11 : 0] a;
input wire [5 : 0] d;
input wire [11 : 0] dpra;
input wire clk;
input wire we;
output wire [5 : 0] spo;
output wire [5 : 0] dpo;
dist_mem_gen_v8_0_10 #(
.C_FAMILY("artix7"),
.C_ADDR_WIDTH(12),
.C_DEFAULT_DATA("0"),
.C_DEPTH(2160),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(1),
.C_HAS_DPRA(1),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("dist_mem_gen_1.mif"),
.C_ELABORATION_DIR("./"),
.C_MEM_TYPE(2),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(6),
.C_PARSER_TYPE(1)
) inst (
.a(a),
.d(d),
.dpra(dpra),
.clk(clk),
.we(we),
.i_ce(1'D1),
.qspo_ce(1'D1),
.qdpo_ce(1'D1),
.qdpo_clk(1'D0),
.qspo_rst(1'D0),
.qdpo_rst(1'D0),
.qspo_srst(1'D0),
.qdpo_srst(1'D0),
.spo(spo),
.dpo(dpo),
.qspo(),
.qdpo()
);
endmodule
|
module ssio_sdr_in_diff #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire input_clk_p,
input wire input_clk_n,
input wire [WIDTH-1:0] input_d_p,
input wire [WIDTH-1:0] input_d_n,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
wire input_clk;
wire [WIDTH-1:0] input_d;
genvar n;
generate
if (TARGET == "XILINX") begin
IBUFDS
clk_ibufds_inst (
.I(input_clk_p),
.IB(input_clk_n),
.O(input_clk)
);
for (n = 0; n < WIDTH; n = n + 1) begin
IBUFDS
data_ibufds_inst (
.I(input_d_p[n]),
.IB(input_d_n[n]),
.O(input_d[n])
);
end
end else if (TARGET == "ALTERA") begin
ALT_INBUF_DIFF
clk_inbuf_diff_inst (
.i(input_clk_p),
.ibar(input_clk_n),
.o(input_clk)
);
for (n = 0; n < WIDTH; n = n + 1) begin
ALT_INBUF_DIFF
data_inbuf_diff_inst (
.i(input_d_p[n]),
.ibar(input_d_n[n]),
.o(input_d[n])
);
end
end else begin
assign input_clk = input_clk_p;
assign input_d = input_d_p;
end
endgenerate
ssio_sdr_in #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.WIDTH(WIDTH)
)
ssio_ddr_in_inst(
.input_clk(input_clk),
.input_d(input_d),
.output_clk(output_clk),
.output_q(output_q)
);
endmodule
|
module ppu_vga
(
input clk_in, // 100MHz system clock signal
input rst_in, // reset signal
//Generated Signals to Drive VGA
output hsync_out, // vga hsync signal
output vsync_out, // vga vsync signal
output [2:0] r_out, // vga red signal
output [2:0] g_out, // vga green signal
output [1:0] b_out, // vga blue signal
//From the below control signal, the PPU returns this value
input [5:0] sys_palette_idx_in, // system palette index (selects output color)
//X, Y, Y Next, pixel clock and a vblank
output [9:0] nes_x_out, // nes x coordinate
output [9:0] nes_y_out, // nes y coordinate
output [9:0] nes_y_next_out, // next line's nes y coordinate
output pix_pulse_out, // 1 clk pulse prior to nes_x update
output vblank_out // indicates a vblank is occuring (no PPU vram access)
);
// Display dimensions (640x480).
localparam [9:0] DISPLAY_W = 10'h280,
DISPLAY_H = 10'h1E0;
// NES screen dimensions (256x240).
localparam [9:0] NES_W = 10'h100,
NES_H = 10'h0F0;
// Border color (surrounding NES screen).
localparam [7:0] BORDER_COLOR = 8'h49;
//
// VGA_SYNC: VGA synchronization control block.
//
wire sync_en; // vga enable signal
wire [9:0] sync_x; // current vga x coordinate
wire [9:0] sync_y; // current vga y coordinate
wire [9:0] sync_x_next; // vga x coordinate for next clock
wire [9:0] sync_y_next; // vga y coordinate for next line
vga_sync vga_sync_blk(
.clk (clk_in ),
.rst (rst_in ),
.hsync (hsync_out ),
.vsync (vsync_out ),
.en (sync_en ),
.x (sync_x ),
.y (sync_y ),
.x_next (sync_x_next ),
.y_next (sync_y_next )
);
//
// Registers.
//
reg [7:0] q_rgb; // output color latch (1 clk delay required by vga_sync)
reg [7:0] d_rgb;
reg q_vblank; // current vblank state
wire d_vblank;
always @(posedge clk_in) begin
if (rst_in)
begin
q_rgb <= 8'h00;
q_vblank <= 1'h0;
end
else
begin
q_rgb <= d_rgb;
q_vblank <= d_vblank;
end
end
//
// Coord and timing signals.
//
wire [9:0] nes_x_next; // nes x coordinate for next clock
wire border; // indicates we are displaying a vga pixel outside the nes extents
/* Why subtract 64 and divide by two
* because each pixel takes up to blocks on a VGA because thye are doubling the pixels then
* we add an offset of 32 to the pixel values (64 / 2) so the image coming out on the VGA
* screen is really 32 pixels shifted to the right, so there is 32 x double pixels before the
* x image (64 real pixels) and 32 after, so this make the 256 bit wide image right in the
* center of the 320 image, or completely expanded out:
* |--------------------| = Image = (320 *2) = 640 pixels wide
* |32|-----256------|32| = 320
* |64|-----512------|64| = 640
*/
assign nes_x_out = (sync_x - 10'h040) >> 1;
assign nes_y_out = sync_y >> 1;
assign nes_x_next = (sync_x_next - 10'h040) >> 1;
assign nes_y_next_out = sync_y_next >> 1;
assign border = (nes_x_out >= NES_W) || (nes_y_out < 8) || (nes_y_out >= (NES_H - 8));
//
// Lookup RGB values based on sys_palette_idx.
//
always @*
begin
if (!sync_en)
begin
d_rgb = 8'h00;
end
else if (border)
begin
d_rgb = BORDER_COLOR;
end
else
begin
// Lookup RGB values based on sys_palette_idx. Table is an approximation of the NES
// system palette. Taken from http://nesdev.parodius.com/NESTechFAQ.htm#nessnescompat.
case (sys_palette_idx_in)
6'h00: d_rgb = { 3'h3, 3'h3, 2'h1 };
6'h01: d_rgb = { 3'h1, 3'h0, 2'h2 };
6'h02: d_rgb = { 3'h0, 3'h0, 2'h2 };
6'h03: d_rgb = { 3'h2, 3'h0, 2'h2 };
6'h04: d_rgb = { 3'h4, 3'h0, 2'h1 };
6'h05: d_rgb = { 3'h5, 3'h0, 2'h0 };
6'h06: d_rgb = { 3'h5, 3'h0, 2'h0 };
6'h07: d_rgb = { 3'h3, 3'h0, 2'h0 };
6'h08: d_rgb = { 3'h2, 3'h1, 2'h0 };
6'h09: d_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0a: d_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0b: d_rgb = { 3'h0, 3'h1, 2'h0 };
6'h0c: d_rgb = { 3'h0, 3'h1, 2'h1 };
6'h0d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0f: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h10: d_rgb = { 3'h5, 3'h5, 2'h2 };
6'h11: d_rgb = { 3'h0, 3'h3, 2'h3 };
6'h12: d_rgb = { 3'h1, 3'h1, 2'h3 };
6'h13: d_rgb = { 3'h4, 3'h0, 2'h3 };
6'h14: d_rgb = { 3'h5, 3'h0, 2'h2 };
6'h15: d_rgb = { 3'h7, 3'h0, 2'h1 };
6'h16: d_rgb = { 3'h6, 3'h1, 2'h0 };
6'h17: d_rgb = { 3'h6, 3'h2, 2'h0 };
6'h18: d_rgb = { 3'h4, 3'h3, 2'h0 };
6'h19: d_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1a: d_rgb = { 3'h0, 3'h5, 2'h0 };
6'h1b: d_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1c: d_rgb = { 3'h0, 3'h4, 2'h2 };
6'h1d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1f: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h20: d_rgb = { 3'h7, 3'h7, 2'h3 };
6'h21: d_rgb = { 3'h1, 3'h5, 2'h3 };
6'h22: d_rgb = { 3'h2, 3'h4, 2'h3 };
6'h23: d_rgb = { 3'h5, 3'h4, 2'h3 };
6'h24: d_rgb = { 3'h7, 3'h3, 2'h3 };
6'h25: d_rgb = { 3'h7, 3'h3, 2'h2 };
6'h26: d_rgb = { 3'h7, 3'h3, 2'h1 };
6'h27: d_rgb = { 3'h7, 3'h4, 2'h0 };
6'h28: d_rgb = { 3'h7, 3'h5, 2'h0 };
6'h29: d_rgb = { 3'h4, 3'h6, 2'h0 };
6'h2a: d_rgb = { 3'h2, 3'h6, 2'h1 };
6'h2b: d_rgb = { 3'h2, 3'h7, 2'h2 };
6'h2c: d_rgb = { 3'h0, 3'h7, 2'h3 };
6'h2d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2f: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h30: d_rgb = { 3'h7, 3'h7, 2'h3 };
6'h31: d_rgb = { 3'h5, 3'h7, 2'h3 };
6'h32: d_rgb = { 3'h6, 3'h6, 2'h3 };
6'h33: d_rgb = { 3'h6, 3'h6, 2'h3 };
6'h34: d_rgb = { 3'h7, 3'h6, 2'h3 };
6'h35: d_rgb = { 3'h7, 3'h6, 2'h3 };
6'h36: d_rgb = { 3'h7, 3'h5, 2'h2 };
6'h37: d_rgb = { 3'h7, 3'h6, 2'h2 };
6'h38: d_rgb = { 3'h7, 3'h7, 2'h2 };
6'h39: d_rgb = { 3'h7, 3'h7, 2'h2 };
6'h3a: d_rgb = { 3'h5, 3'h7, 2'h2 };
6'h3b: d_rgb = { 3'h5, 3'h7, 2'h3 };
6'h3c: d_rgb = { 3'h4, 3'h7, 2'h3 };
6'h3d: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3e: d_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3f: d_rgb = { 3'h0, 3'h0, 2'h0 };
endcase
end
end
assign { r_out, g_out, b_out } = q_rgb;
assign pix_pulse_out = nes_x_next != nes_x_out;
// Clear the VBLANK signal immediately before starting processing of the pre-0 garbage line. From
// here. Set the vblank approximately 2270 CPU cycles before it will be cleared. This is done
// in order to pass vbl_clear_time.nes. It eats into the visible portion of the playfield, but we
// currently hide that portion of the screen anyway.
assign d_vblank = ((sync_x == 730) && (sync_y == 477)) ? 1'b1 :
((sync_x == 64) && (sync_y == 519)) ? 1'b0 : q_vblank;
assign vblank_out = q_vblank;
endmodule
|
module vga_scandoubler (
input wire clkvideo,
input wire clkvga,
input wire enable_scandoubling,
input wire disable_scaneffect, // 1 to disable scanlines
input wire [2:0] ri,
input wire [2:0] gi,
input wire [2:0] bi,
input wire hsync_ext_n,
input wire vsync_ext_n,
input wire csync_ext_n,
output reg [2:0] ro,
output reg [2:0] go,
output reg [2:0] bo,
output reg hsync,
output reg vsync
);
parameter [31:0] CLKVIDEO = 12000;
// http://www.epanorama.net/faq/vga2rgb/calc.html
// SVGA 800x600
// HSYNC = 3.36us VSYNC = 114.32us
parameter [63:0] HSYNC_COUNT = (CLKVIDEO * 3360 * 2)/1000000;
parameter [63:0] VSYNC_COUNT = (CLKVIDEO * 114320 * 2)/1000000;
reg [10:0] addrvideo = 11'd0, addrvga = 11'b00000000000;
reg [9:0] totalhor = 10'd0;
wire [2:0] rout, gout, bout;
// Memoria de doble puerto que guarda la información de dos scans
// Cada scan puede ser de hasta 1024 puntos, incluidos aquí los
// puntos en negro que se pintan durante el HBlank
vgascanline_dport memscan (
.clk(clkvga),
.addrwrite(addrvideo),
.addrread(addrvga),
.we(1'b1),
.din({ri,gi,bi}),
.dout({rout,gout,bout})
);
// Para generar scanlines:
reg scaneffect = 1'b0;
wire [2:0] rout_dimmed, gout_dimmed, bout_dimmed;
color_dimmed apply_to_red (rout, rout_dimmed);
color_dimmed apply_to_green (gout, gout_dimmed);
color_dimmed apply_to_blue (bout, bout_dimmed);
wire [2:0] ro_vga = (scaneffect | disable_scaneffect)? rout : rout_dimmed;
wire [2:0] go_vga = (scaneffect | disable_scaneffect)? gout : gout_dimmed;
wire [2:0] bo_vga = (scaneffect | disable_scaneffect)? bout : bout_dimmed;
// Voy alternativamente escribiendo en una mitad o en otra del scan buffer
// Cambio de mitad cada vez que encuentro un pulso de sincronismo horizontal
// En "totalhor" mido el número de ciclos de reloj que hay en un scan
always @(posedge clkvideo) begin
// if (vsync_ext_n == 1'b0) begin
// addrvideo <= 11'd0;
// end
if (hsync_ext_n == 1'b0 && addrvideo[9:7] != 3'b000) begin
totalhor <= addrvideo[9:0];
addrvideo <= {~addrvideo[10],10'b0000000000};
end
else
addrvideo <= addrvideo + 11'd1;
end
// Recorro el scanbuffer al doble de velocidad, generando direcciones para
// el scan buffer. Cada vez que el video original ha terminado una linea,
// cambio de mitad de buffer. Cuando termino de recorrerlo pero aún no
// estoy en un retrazo horizontal, simplemente vuelvo a recorrer el scan buffer
// desde el mismo origen
// Cada vez que termino de recorrer el scan buffer basculo "scaneffect" que
// uso después para mostrar los píxeles a su brillo nominal, o con su brillo
// reducido para un efecto chachi de scanlines en la VGA
always @(posedge clkvga) begin
// if (vsync_ext_n == 1'b0) begin
// addrvga <= 11'b10000000000;
// scaneffect <= 1'b0;
// end
if (addrvga[9:0] == totalhor && hsync_ext_n == 1'b1) begin
addrvga <= {addrvga[10], 10'b000000000};
scaneffect <= ~scaneffect;
end
else if (hsync_ext_n == 1'b0 && addrvga[9:7] != 3'b000) begin
addrvga <= {~addrvga[10],10'b000000000};
scaneffect <= ~scaneffect;
end
else
addrvga <= addrvga + 11'd1;
end
// El HSYNC de la VGA está bajo sólo durante HSYNC_COUNT ciclos a partir del comienzo
// del barrido de un scanline
reg hsync_vga, vsync_vga;
always @* begin
if (addrvga[9:0] < HSYNC_COUNT[9:0])
hsync_vga = 1'b0;
else
hsync_vga = 1'b1;
end
// El VSYNC de la VGA está bajo sólo durante VSYNC_COUNT ciclos a partir del flanco de
// bajada de la señal de sincronismo vertical original
reg [15:0] cntvsync = 16'hFFFF;
initial vsync_vga = 1'b1;
always @(posedge clkvga) begin
if (vsync_ext_n == 1'b0) begin
if (cntvsync == 16'hFFFF) begin
cntvsync <= 16'd0;
vsync_vga <= 1'b0;
end
else if (cntvsync != 16'hFFFE) begin
if (cntvsync == VSYNC_COUNT[15:0]) begin
vsync_vga <= 1'b1;
cntvsync <= 16'hFFFE;
end
else
cntvsync <= cntvsync + 16'd1;
end
end
else if (vsync_ext_n == 1'b1)
cntvsync <= 16'hFFFF;
end
always @* begin
if (enable_scandoubling == 1'b0) begin // 15kHz output
ro = ri;
go = gi;
bo = bi;
hsync = csync_ext_n;
vsync = 1'b1;
end
else begin // VGA output
ro = ro_vga;
go = go_vga;
bo = bo_vga;
hsync = hsync_vga;
vsync = vsync_vga;
end
end
endmodule
|
module vgascanline_dport (
input wire clk,
input wire [10:0] addrwrite,
input wire [10:0] addrread,
input wire we,
input wire [8:0] din,
output reg [8:0] dout
);
reg [8:0] scan[0:2047]; // two scanlines
always @(posedge clk) begin
dout <= scan[addrread];
if (we == 1'b1)
scan[addrwrite] <= din;
end
endmodule
|
module color_dimmed (
input wire [2:0] in,
output reg [2:0] out // out is scaled to roughly 70% of in
);
always @* begin // a LUT
case (in)
3'd0 : out = 3'd0;
3'd1 : out = 3'd1;
3'd2 : out = 3'd1;
3'd3 : out = 3'd2;
3'd4 : out = 3'd3;
3'd5 : out = 3'd3;
3'd6 : out = 3'd4;
3'd7 : out = 3'd5;
default: out = 3'd0;
endcase
end
endmodule
|
module LiftControl(sw0,sw1,sw2,sw3,sw4,sw5,reset,k0,k1,k2,k3,CLK
,Up1Dis,Up2Dis,Up3Dis,Dn2Dis,Dn3Dis,Dn4Dis,Stop1Dis,Stop2Dis
,Stop3Dis,Stop4Dis,PosDis/*,choice*/,seg);//核心控制模块,The Top Level
output Up1Dis,Up2Dis,Up3Dis,Dn2Dis,Dn3Dis,Dn4Dis,Stop1Dis,Stop2Dis,Stop3Dis,Stop4Dis;//向上、向下与停靠的请求显示
output[3:0] PosDis;//楼层显示
output[6:0] seg;
//input choice;
input sw0,sw1,sw2,sw3,sw4,sw5,reset,k0,k1,k2,k3,CLK;//向上、向下与停靠的按键输入
wire clk,reset;
reg DoorFlag=1'b0,blink;
reg Up1Dis,Up2Dis,Up3Dis,Dn2Dis,Dn3Dis,Dn4Dis,Stop1Dis,Stop2Dis,Stop3Dis,Stop4Dis;
reg[1:0] UpDnFlag=2'b00;
reg[2:0] count;//门开后要持续4个时钟周期,用count
reg[3:0] pos,PosDis;
wire[6:0] seg;
//reg speedup=1'b0;
reg[3:0] UpReq,DownReq,StopReq;//分别用来合并向上请求的各信号，向下请求的各信号和停靠请求的各信号
reg[6:0] LiftState=7'b0000001,NextState=7'b0000001;//分别表示电梯的当前状态和下一状态
parameter WAIT=7'b0000001, UP=7'b0000010, DOWN=7'b0000100, UPSTOP=7'b0001000
, DOWNSTOP=7'b0010000, OPENDOOR=7'b0100000, CLOSEDOOR=7'b1000000;
parameter IDLE=4'b0000,FLOOR1=4'b0001, FLOOR2=4'b0010, FLOOR3=4'b0100, FLOOR4=4'b1000;
parameter TRUE=1'b1, FALSE=1'b0;
parameter OPEN=1'b1, CLOSED=1'b0;
parameter UPFLAG=2'b01,DNFLAG=2'b10,STATIC=2'b00;
FrequenceDevide fd(.CLK(CLK),.reset(reset),.clk(clk));//降频模块
LEDDisplay led(.pos(pos), .seg(seg));
/*
always @(posedge clk or posedge choice)
if(choice)
FrequenceDevide fd(.CLK(CLK),.reset(reset),.clk(clk));//降频模块
else
FrequenceDevide2 fd(.speedup(speedup),.CLK(CLK),.reset(reset),.clk(clk));//降频模块*/
always @(posedge sw0 or posedge reset or posedge DoorFlag)//一层上升请求
begin
if(reset)
Up1Dis<=1'b0;
if(sw0)
Up1Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0001)
begin
Up1Dis<=1'b0;
end
end
end
always @(posedge sw1 or posedge reset or posedge DoorFlag)//二层上升请求
begin
if(reset)
Up2Dis<=1'b0;
if(sw1)
Up2Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0010)
begin
Up2Dis<=1'b0;
end
end
end
always @(posedge sw2 or posedge reset or posedge DoorFlag)//三层上升请求
begin
if(reset)
Up3Dis<=1'b0;
if(sw2)
Up3Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0100)
begin
Up3Dis<=1'b0;
end
end
end
always @(posedge sw3 or posedge reset or posedge DoorFlag)//二层下降请求
begin
if(reset)
Dn2Dis<=1'b0;
if(sw3)
Dn2Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0010)
begin
Dn2Dis<=1'b0;
end
end
end
always @(posedge sw4 or posedge reset or posedge DoorFlag)//三层下降请求
begin
if(reset)
Dn3Dis<=1'b0;
if(sw4)
Dn3Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0100)
begin
Dn3Dis<=1'b0;
end
end
end
always @(posedge sw5 or posedge reset or posedge DoorFlag)//四层下降请求
begin
if(reset)
Dn4Dis<=1'b0;
if(sw5)
Dn4Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b1000)
begin
Dn4Dis<=1'b0;
end
end
end
always @(posedge k0 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop1Dis<=1'b0;
if(k0)
Stop1Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0001)
begin
Stop1Dis<=1'b0;
end
end
end
always @(posedge k1 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop2Dis<=1'b0;
if(k1)
Stop2Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0010)
begin
Stop2Dis<=1'b0;
end
end
end
always @(posedge k2 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop3Dis<=1'b0;
if(k2)
Stop3Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0100)
begin
Stop3Dis<=1'b0;
end
end
end
always @(posedge k3 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop4Dis<=1'b0;
if(k3)
Stop4Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b1000)
begin
Stop4Dis<=1'b0;
end
end
end
always @(pos or blink or reset or clk)
begin
if(reset)
PosDis=4'b0001;
else if(blink)//开门LED闪烁
PosDis=IDLE;
else
case(pos)
FLOOR1:
PosDis=FLOOR1;
FLOOR2:
PosDis=FLOOR2;
FLOOR3:
PosDis=FLOOR3;
FLOOR4:
PosDis=FLOOR4;
default:
PosDis=FLOOR1;
endcase
//若使用如下方法，电梯不能正常运行
//同时赋值时钟脉冲紊乱，故单独使用LEDDisplay模块处理楼层LED显示
/*case(pos)
FLOOR1:
begin
PosDis<=FLOOR1;
seg<=7'b1111001;
end
FLOOR2:
begin
PosDis<=FLOOR2;
seg<=7'b0100100;
end
FLOOR3:
begin
PosDis<=FLOOR3;
seg<=7'b0110000;
end
FLOOR4:
begin
PosDis<=FLOOR4;
seg<=7'b0011001;
end
default:
begin
PosDis<=FLOOR1;
seg<=7'b1111001;
end
endcase */
end
always @(Up1Dis or Up2Dis or Up3Dis )
UpReq={1'b0,Up3Dis,Up2Dis,Up1Dis};
always @(Dn2Dis or Dn3Dis or Dn4Dis)
DownReq={Dn4Dis, Dn3Dis, Dn2Dis,1'b0};
always @(Stop1Dis or Stop2Dis or Stop3Dis or Stop4Dis)
StopReq={Stop4Dis,Stop3Dis,Stop2Dis,Stop1Dis};
always @(posedge clk or posedge reset)
if(reset)
begin
LiftState<=WAIT;
end
else
begin
LiftState<=NextState;
end
always @(clk)
begin
if((DoorFlag==OPEN)&&(~clk))//门打开并且时钟信号处于低电平
blink<=1'b1;//开门LED闪烁信号
else
blink<=1'b0;
end
always @(LiftState or UpReq or DownReq or StopReq or pos or count or UpDnFlag or reset)
begin
if(reset)
NextState=WAIT;
else
case(LiftState)
WAIT:
begin
if(StopReq>0)//有停靠请求否
begin
if((StopReq&pos)>0)//停靠请求中有当前楼层停靠请求否
NextState=OPENDOOR;//有当前楼层请求，则下一状态转开门
else if(StopReq>pos)//有当前楼层之上的停靠请求否
NextState=UP;
else
NextState=DOWN;
end
else if((UpReq&pos)||(DownReq&pos))//上下请求中有当前楼层请求否
begin
NextState=OPENDOOR;
end
else if((UpReq>pos)||(DownReq>pos))//上下请求中有当前楼层之上的请求否
NextState=UP;
else if(UpReq||DownReq)//上下请求中有当前楼层之下的请求否
NextState=DOWN;
else
NextState=WAIT;//无任何请求，继续处于WAIT模式
end
UP:
begin
if((StopReq&pos)||(UpReq&pos))//停靠或上升请求中有当前楼层的请求否
NextState=UPSTOP;//有，下一状态转为UPSTOP(停靠后要1s才开门,UPSTOP即为这1s的过渡期)
else if((StopReq>pos)||(UpReq>pos))//停靠或上升请求中有当前楼层之上的请求否
NextState=UP;
else if(DownReq>0)//有下降请求否
begin
if((DownReq>pos)&&((DownReq^pos)>pos))//下降请求中有当前楼层之上的请求否
NextState=UP;
else if((DownReq&pos)&&(pos<FLOOR4))
NextState=DOWNSTOP;
else if((DownReq&pos)&&(pos==FLOOR4))
NextState=DOWNSTOP;
else//下降请求中只有当前楼层之下的请求
NextState=DOWN;
end
else if(StopReq||UpReq)//只有当前楼层之上的停靠或上升请求否
NextState=DOWN;
else
NextState=WAIT;//无任何请求，转为WAIT模式
end
DOWN:
begin
if((StopReq&pos)||(DownReq&pos))
NextState=DOWNSTOP;
else if(((StopReq&FLOOR1)<pos&&(StopReq&FLOOR1))||((StopReq&FLOOR2)<pos&&(StopReq&FLOOR2))||((StopReq&FLOOR3)<pos&&(StopReq&FLOOR3))||((StopReq&FLOOR4)<pos&&(StopReq&FLOOR4)))
NextState=DOWN;
else if(((DownReq&FLOOR1)<pos&&(DownReq&FLOOR1))||((DownReq&FLOOR2)<pos&&(DownReq&FLOOR2))||((DownReq&FLOOR3)<pos&&(DownReq&FLOOR3))||((DownReq&FLOOR4)<pos&&(DownReq&FLOOR4)))
NextState=DOWN;
else if(UpReq>0)
begin
if(((UpReq&FLOOR1)<pos&&(UpReq&FLOOR1))||((UpReq&FLOOR2)<pos&&(UpReq&FLOOR2))||((UpReq&FLOOR3)<pos&&(UpReq&FLOOR3))||((UpReq&FLOOR4)<pos&&(UpReq&FLOOR4)))
NextState=DOWN;
else if((UpReq&pos)&&(pos>FLOOR1))
NextState=UPSTOP;
else if((UpReq&pos)&&(pos==FLOOR1))
NextState=UPSTOP;
else
NextState=UP;
end
else if(StopReq||DownReq)
NextState=UP;
else
NextState=WAIT;
end
UPSTOP:
begin
NextState=OPENDOOR;
end
DOWNSTOP:
begin
NextState=OPENDOOR;
end
OPENDOOR:
begin
if(count<4)//开门不足4周期，则继续转移到开门状态
NextState=OPENDOOR;
else
NextState=CLOSEDOOR;
end
CLOSEDOOR:
begin
if(UpDnFlag==UPFLAG)//开门关门前电梯是处于上升状态
begin
if((StopReq&pos)||(UpReq&pos))//上升或停靠请求中有当前楼层的请求否，有可能关门的瞬间又有新的请求
NextState=OPENDOOR;
else if((StopReq>pos)||(UpReq>pos))//上升或停靠请求中有当前楼层之上的请求否
NextState=UP;
else if(DownReq>0)//有下降请求否
begin
if((DownReq>pos)&&((DownReq^pos)>pos))//有当前楼层之上的下降请求，则下一状态转移上升
NextState=UP;
else if((DownReq&pos)>0)//有当前楼层的下降请求信号，且更上层无下降请求
NextState=OPENDOOR;
else//只有低于当前层的下降请求
NextState=DOWN;
end
else if(StopReq||UpReq)//上升和停靠请求中只有当前层下的请求
NextState=DOWN;
else
NextState=WAIT;//无任何请求，转为WAIT模式
end
else if(UpDnFlag==DNFLAG)
begin
if((StopReq&pos)||(DownReq&pos))
NextState=OPENDOOR;
else if(((StopReq&FLOOR1)<pos&&(StopReq&FLOOR1))||((StopReq&FLOOR2)<pos&&(StopReq&FLOOR2))||((StopReq&FLOOR3)<pos&&(StopReq&FLOOR3))||((StopReq&FLOOR4)<pos&&(StopReq&FLOOR4)))
NextState=DOWN;
else if(((DownReq&FLOOR1)<pos&&(DownReq&FLOOR1))||((DownReq&FLOOR2)<pos&&(DownReq&FLOOR2))||((DownReq&FLOOR3)<pos&&(DownReq&FLOOR3))||((DownReq&FLOOR4)<pos&&(DownReq&FLOOR4)))
NextState=DOWN;
else if(UpReq>0)
begin
if(((UpReq&FLOOR1)<pos&&(UpReq&FLOOR1))||((UpReq&FLOOR2)<pos&&(UpReq&FLOOR2))||((UpReq&FLOOR3)<pos&&(UpReq&FLOOR3))||((UpReq&FLOOR4)<pos&&(UpReq&FLOOR4)))
NextState=DOWN;
else if((UpReq&pos)>0)
NextState=OPENDOOR;
else
NextState=UP;
end
else if(StopReq||DownReq)
NextState=UP;
else
NextState=WAIT;
end
else
begin
if(StopReq>0)
begin
if((StopReq&pos)>0)
NextState=OPENDOOR;
else if(StopReq>pos)
NextState=UP;
else
NextState=DOWN;
end
else if((UpReq&pos)||(DownReq&pos))
begin
NextState=OPENDOOR;
end
else if((UpReq>pos)||(DownReq>pos))
NextState=UP;
else if(UpReq||DownReq)
NextState=DOWN;
else
begin
NextState=WAIT;
end
end
end
default:
NextState=WAIT;
endcase
end
always @(posedge clk or posedge reset)
if(reset)
begin
pos<=FLOOR1;
DoorFlag<=CLOSED;
UpDnFlag<=STATIC;
end
else
begin
case(NextState)
WAIT:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=STATIC;
end
UP:
begin
pos<=pos<<1;
DoorFlag<=CLOSED;
UpDnFlag<=UPFLAG;
end
DOWN:
begin
pos<=pos>>1;
DoorFlag<=CLOSED;
UpDnFlag<=DNFLAG;
end
UPSTOP:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=UPFLAG;
end
DOWNSTOP:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=DNFLAG;
end
OPENDOOR:
begin
pos<=pos;
DoorFlag<=OPEN;
UpDnFlag<=UpDnFlag;
end
CLOSEDOOR:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=UpDnFlag;
end
default:
begin
pos<=FLOOR1;
DoorFlag<=CLOSED;
UpDnFlag<=STATIC;
end
endcase
end
always @(posedge clk or posedge reset)
if(reset)
count<=0;
else if((NextState==OPENDOOR)&&(count<4))
count<=count+1;
else
count<=0;
endmodule
|
module sky130_fd_sc_ms__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
|
module GC_fifo(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count
);
input clk;
input rst;
input [31 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
output [12 : 0] data_count;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(13),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(1),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("4kx9"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(4095),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(4094),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(13),
.C_RD_DEPTH(4096),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(12),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(13),
.C_WR_DEPTH(4096),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(12),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.DATA_COUNT(data_count),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
module asmi_asmi_parallel_0
(
addr,
busy,
clkin,
data_valid,
dataout,
rden,
read,
reset) /* synthesis synthesis_clearbox=1 */;
input [23:0] addr;
output busy;
input clkin;
output data_valid;
output [7:0] dataout;
input rden;
input read;
input reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 read;
tri0 reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2:0] wire_addbyte_cntr_q;
wire [2:0] wire_gen_cntr_q;
wire [1:0] wire_stage_cntr_q;
wire wire_sd2_data1in;
reg add_msb_reg;
wire wire_add_msb_reg_ena;
wire [23:0] wire_addr_reg_d;
reg [23:0] addr_reg;
wire [23:0] wire_addr_reg_ena;
wire [7:0] wire_asmi_opcode_reg_d;
reg [7:0] asmi_opcode_reg;
wire [7:0] wire_asmi_opcode_reg_ena;
reg busy_det_reg;
reg clr_read_reg;
reg clr_read_reg2;
reg dffe3;
reg dvalid_reg;
wire wire_dvalid_reg_ena;
wire wire_dvalid_reg_sclr;
reg dvalid_reg2;
reg end1_cyc_reg;
reg end1_cyc_reg2;
reg end_op_hdlyreg;
reg end_op_reg;
reg end_rbyte_reg;
wire wire_end_rbyte_reg_ena;
wire wire_end_rbyte_reg_sclr;
reg end_read_reg;
reg ncs_reg;
wire wire_ncs_reg_sclr;
wire [7:0] wire_read_data_reg_d;
reg [7:0] read_data_reg;
wire [7:0] wire_read_data_reg_ena;
wire [7:0] wire_read_dout_reg_d;
reg [7:0] read_dout_reg;
wire [7:0] wire_read_dout_reg_ena;
reg read_reg;
wire wire_read_reg_ena;
reg shift_op_reg;
reg stage2_reg;
reg stage3_reg;
reg stage4_reg;
wire wire_mux211_dataout;
wire addr_overdie;
wire addr_overdie_pos;
wire [23:0] addr_reg_overdie;
wire [7:0] b4addr_opcode;
wire [7:0] berase_opcode;
wire busy_wire;
wire clkin_wire;
wire clr_addmsb_wire;
wire clr_endrbyte_wire;
wire clr_read_wire;
wire clr_read_wire2;
wire clr_rstat_wire;
wire clr_sid_wire;
wire clr_write_wire2;
wire data0out_wire;
wire data_valid_wire;
wire [3:0] dataoe_wire;
wire [3:0] dataout_wire;
wire [7:0] derase_opcode;
wire do_4baddr;
wire do_bulk_erase;
wire do_die_erase;
wire do_ex4baddr;
wire do_fast_read;
wire do_fread_epcq;
wire do_freadwrv_polling;
wire do_memadd;
wire do_polling;
wire do_read;
wire do_read_nonvolatile;
wire do_read_rdid;
wire do_read_sid;
wire do_read_stat;
wire do_read_volatile;
wire do_sec_erase;
wire do_sec_prot;
wire do_sprot_polling;
wire do_wait_dummyclk;
wire do_wren;
wire do_write;
wire do_write_polling;
wire do_write_volatile;
wire end1_cyc_gen_cntr_wire;
wire end1_cyc_normal_in_wire;
wire end1_cyc_reg_in_wire;
wire end_add_cycle;
wire end_add_cycle_mux_datab_wire;
wire end_fast_read;
wire end_one_cyc_pos;
wire end_one_cycle;
wire end_op_wire;
wire end_operation;
wire end_ophdly;
wire end_pgwr_data;
wire end_read;
wire end_read_byte;
wire [7:0] exb4addr_opcode;
wire [7:0] fast_read_opcode;
wire freadwrv_sdoin;
wire in_operation;
wire load_opcode;
wire memadd_sdoin;
wire ncs_reg_ena_wire;
wire not_busy;
wire oe_wire;
wire [0:0] pagewr_buf_not_empty;
wire rden_wire;
wire [7:0] rdid_opcode;
wire [7:0] rdummyclk_opcode;
wire [7:0] read_data_reg_in_wire;
wire [7:0] read_opcode;
wire read_rdid_wire;
wire read_sid_wire;
wire read_wire;
wire [7:0] rflagstat_opcode;
wire [7:0] rnvdummyclk_opcode;
wire [7:0] rsid_opcode;
wire rsid_sdoin;
wire [7:0] rstat_opcode;
wire scein_wire;
wire sdoin_wire;
wire sec_protect_wire;
wire [7:0] secprot_opcode;
wire secprot_sdoin;
wire [7:0] serase_opcode;
wire shift_opcode;
wire shift_opdata;
wire shift_pgwr_data;
wire st_busy_wire;
wire stage2_wire;
wire stage3_wire;
wire stage4_wire;
wire start_frpoll;
wire start_poll;
wire start_sppoll;
wire start_wrpoll;
wire to_sdoin_wire;
wire [7:0] wren_opcode;
wire wren_wire;
wire [7:0] write_opcode;
wire write_prot_true;
wire write_sdoin;
wire [7:0] wrvolatile_opcode;
a_graycounter addbyte_cntr
(
.aclr(reset),
.clk_en((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & end_one_cyc_pos) & (((((((do_read_sid | do_write) | do_sec_erase) | do_die_erase) | do_read_rdid) | do_read) | do_fast_read) | do_read_nonvolatile)) | addr_overdie) | end_operation)),
.clock((~ clkin_wire)),
.q(wire_addbyte_cntr_q),
.qbin(),
.sclr((end_operation | addr_overdie))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addbyte_cntr.width = 3,
addbyte_cntr.lpm_type = "a_graycounter";
a_graycounter gen_cntr
(
.aclr(reset),
.clk_en((((((in_operation & (~ end_ophdly)) & (~ clr_rstat_wire)) & (~ clr_sid_wire)) | do_wait_dummyclk) | addr_overdie)),
.clock(clkin_wire),
.q(wire_gen_cntr_q),
.qbin(),
.sclr(((end1_cyc_reg_in_wire | addr_overdie) | do_wait_dummyclk))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
gen_cntr.width = 3,
gen_cntr.lpm_type = "a_graycounter";
a_graycounter stage_cntr
(
.aclr(reset),
.clk_en(((((((((((((((in_operation & end_one_cycle) & (~ (stage3_wire & (~ end_add_cycle)))) & (~ (stage4_wire & (~ end_read)))) & (~ (stage4_wire & (~ end_fast_read)))) & (~ ((((do_write | do_sec_erase) | do_die_erase) | do_bulk_erase) & write_prot_true))) & (~ (do_write & (~ pagewr_buf_not_empty[0])))) & (~ (stage3_wire & st_busy_wire))) & (~ ((do_write & shift_pgwr_data) & (~ end_pgwr_data)))) & (~ (stage2_wire & do_wren))) & (~ ((((stage3_wire & (do_sec_erase | do_die_erase)) & (~ do_wren)) & (~ do_read_stat)) & (~ do_read_rdid)))) & (~ (stage3_wire & ((do_write_volatile | do_read_volatile) | do_read_nonvolatile)))) | ((stage3_wire & do_fast_read) & do_wait_dummyclk)) | addr_overdie) | end_ophdly)),
.clock(clkin_wire),
.q(wire_stage_cntr_q),
.qbin(),
.sclr((end_operation | addr_overdie))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
stage_cntr.width = 2,
stage_cntr.lpm_type = "a_graycounter";
cyclonev_asmiblock sd2
(
.data0in(),
.data0oe(dataoe_wire[0]),
.data0out(sdoin_wire),
.data1in(wire_sd2_data1in),
.data1oe(dataoe_wire[1]),
.data2in(),
.data2oe(dataoe_wire[2]),
.data2out(1'b1),
.data3in(),
.data3oe(dataoe_wire[3]),
.data3out(1'b1),
.dclk(clkin_wire),
.oe(oe_wire),
.sce(scein_wire)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.data1out(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
sd2.enable_sim = "false",
sd2.lpm_type = "cyclonev_asmiblock";
// synopsys translate_off
initial
add_msb_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) add_msb_reg <= 1'b0;
else if (wire_add_msb_reg_ena == 1'b1)
if (clr_addmsb_wire == 1'b1) add_msb_reg <= 1'b0;
else add_msb_reg <= addr_reg[23];
assign
wire_add_msb_reg_ena = ((((((((do_read | do_fast_read) | do_write) | do_sec_erase) | do_die_erase) & (~ (((do_write | do_sec_erase) | do_die_erase) & (~ do_memadd)))) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) | clr_addmsb_wire);
// synopsys translate_off
initial
addr_reg[0:0] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[0:0] <= 1'b0;
else if (wire_addr_reg_ena[0:0] == 1'b1) addr_reg[0:0] <= wire_addr_reg_d[0:0];
// synopsys translate_off
initial
addr_reg[1:1] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[1:1] <= 1'b0;
else if (wire_addr_reg_ena[1:1] == 1'b1) addr_reg[1:1] <= wire_addr_reg_d[1:1];
// synopsys translate_off
initial
addr_reg[2:2] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[2:2] <= 1'b0;
else if (wire_addr_reg_ena[2:2] == 1'b1) addr_reg[2:2] <= wire_addr_reg_d[2:2];
// synopsys translate_off
initial
addr_reg[3:3] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[3:3] <= 1'b0;
else if (wire_addr_reg_ena[3:3] == 1'b1) addr_reg[3:3] <= wire_addr_reg_d[3:3];
// synopsys translate_off
initial
addr_reg[4:4] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[4:4] <= 1'b0;
else if (wire_addr_reg_ena[4:4] == 1'b1) addr_reg[4:4] <= wire_addr_reg_d[4:4];
// synopsys translate_off
initial
addr_reg[5:5] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[5:5] <= 1'b0;
else if (wire_addr_reg_ena[5:5] == 1'b1) addr_reg[5:5] <= wire_addr_reg_d[5:5];
// synopsys translate_off
initial
addr_reg[6:6] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[6:6] <= 1'b0;
else if (wire_addr_reg_ena[6:6] == 1'b1) addr_reg[6:6] <= wire_addr_reg_d[6:6];
// synopsys translate_off
initial
addr_reg[7:7] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[7:7] <= 1'b0;
else if (wire_addr_reg_ena[7:7] == 1'b1) addr_reg[7:7] <= wire_addr_reg_d[7:7];
// synopsys translate_off
initial
addr_reg[8:8] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[8:8] <= 1'b0;
else if (wire_addr_reg_ena[8:8] == 1'b1) addr_reg[8:8] <= wire_addr_reg_d[8:8];
// synopsys translate_off
initial
addr_reg[9:9] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[9:9] <= 1'b0;
else if (wire_addr_reg_ena[9:9] == 1'b1) addr_reg[9:9] <= wire_addr_reg_d[9:9];
// synopsys translate_off
initial
addr_reg[10:10] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[10:10] <= 1'b0;
else if (wire_addr_reg_ena[10:10] == 1'b1) addr_reg[10:10] <= wire_addr_reg_d[10:10];
// synopsys translate_off
initial
addr_reg[11:11] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[11:11] <= 1'b0;
else if (wire_addr_reg_ena[11:11] == 1'b1) addr_reg[11:11] <= wire_addr_reg_d[11:11];
// synopsys translate_off
initial
addr_reg[12:12] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[12:12] <= 1'b0;
else if (wire_addr_reg_ena[12:12] == 1'b1) addr_reg[12:12] <= wire_addr_reg_d[12:12];
// synopsys translate_off
initial
addr_reg[13:13] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[13:13] <= 1'b0;
else if (wire_addr_reg_ena[13:13] == 1'b1) addr_reg[13:13] <= wire_addr_reg_d[13:13];
// synopsys translate_off
initial
addr_reg[14:14] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[14:14] <= 1'b0;
else if (wire_addr_reg_ena[14:14] == 1'b1) addr_reg[14:14] <= wire_addr_reg_d[14:14];
// synopsys translate_off
initial
addr_reg[15:15] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[15:15] <= 1'b0;
else if (wire_addr_reg_ena[15:15] == 1'b1) addr_reg[15:15] <= wire_addr_reg_d[15:15];
// synopsys translate_off
initial
addr_reg[16:16] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[16:16] <= 1'b0;
else if (wire_addr_reg_ena[16:16] == 1'b1) addr_reg[16:16] <= wire_addr_reg_d[16:16];
// synopsys translate_off
initial
addr_reg[17:17] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[17:17] <= 1'b0;
else if (wire_addr_reg_ena[17:17] == 1'b1) addr_reg[17:17] <= wire_addr_reg_d[17:17];
// synopsys translate_off
initial
addr_reg[18:18] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[18:18] <= 1'b0;
else if (wire_addr_reg_ena[18:18] == 1'b1) addr_reg[18:18] <= wire_addr_reg_d[18:18];
// synopsys translate_off
initial
addr_reg[19:19] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[19:19] <= 1'b0;
else if (wire_addr_reg_ena[19:19] == 1'b1) addr_reg[19:19] <= wire_addr_reg_d[19:19];
// synopsys translate_off
initial
addr_reg[20:20] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[20:20] <= 1'b0;
else if (wire_addr_reg_ena[20:20] == 1'b1) addr_reg[20:20] <= wire_addr_reg_d[20:20];
// synopsys translate_off
initial
addr_reg[21:21] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[21:21] <= 1'b0;
else if (wire_addr_reg_ena[21:21] == 1'b1) addr_reg[21:21] <= wire_addr_reg_d[21:21];
// synopsys translate_off
initial
addr_reg[22:22] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[22:22] <= 1'b0;
else if (wire_addr_reg_ena[22:22] == 1'b1) addr_reg[22:22] <= wire_addr_reg_d[22:22];
// synopsys translate_off
initial
addr_reg[23:23] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[23:23] <= 1'b0;
else if (wire_addr_reg_ena[23:23] == 1'b1) addr_reg[23:23] <= wire_addr_reg_d[23:23];
assign
wire_addr_reg_d = {((({23{not_busy}} & addr[23:1]) | ({23{stage3_wire}} & addr_reg[22:0])) | ({23{addr_overdie}} & addr_reg_overdie[23:1])), ((not_busy & addr[0]) | (addr_overdie & addr_reg_overdie[0]))};
assign
wire_addr_reg_ena = {24{((((rden_wire | wren_wire) & not_busy) | (stage4_wire & addr_overdie)) | (stage3_wire & ((((do_write | do_sec_erase) | do_die_erase) & do_memadd) | (do_read | do_fast_read))))}};
// synopsys translate_off
initial
asmi_opcode_reg[0:0] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[0:0] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[0:0] == 1'b1) asmi_opcode_reg[0:0] <= wire_asmi_opcode_reg_d[0:0];
// synopsys translate_off
initial
asmi_opcode_reg[1:1] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[1:1] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[1:1] == 1'b1) asmi_opcode_reg[1:1] <= wire_asmi_opcode_reg_d[1:1];
// synopsys translate_off
initial
asmi_opcode_reg[2:2] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[2:2] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[2:2] == 1'b1) asmi_opcode_reg[2:2] <= wire_asmi_opcode_reg_d[2:2];
// synopsys translate_off
initial
asmi_opcode_reg[3:3] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[3:3] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[3:3] == 1'b1) asmi_opcode_reg[3:3] <= wire_asmi_opcode_reg_d[3:3];
// synopsys translate_off
initial
asmi_opcode_reg[4:4] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[4:4] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[4:4] == 1'b1) asmi_opcode_reg[4:4] <= wire_asmi_opcode_reg_d[4:4];
// synopsys translate_off
initial
asmi_opcode_reg[5:5] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[5:5] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[5:5] == 1'b1) asmi_opcode_reg[5:5] <= wire_asmi_opcode_reg_d[5:5];
// synopsys translate_off
initial
asmi_opcode_reg[6:6] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[6:6] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[6:6] == 1'b1) asmi_opcode_reg[6:6] <= wire_asmi_opcode_reg_d[6:6];
// synopsys translate_off
initial
asmi_opcode_reg[7:7] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[7:7] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[7:7] == 1'b1) asmi_opcode_reg[7:7] <= wire_asmi_opcode_reg_d[7:7];
assign
wire_asmi_opcode_reg_d = {(((((((((((((((((({7{(load_opcode & do_read_sid)}} & rsid_opcode[7:1]) | ({7{(load_opcode & do_read_rdid)}} & rdid_opcode[7:1])) | ({7{(((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat))}} & secprot_opcode[7:1])) | ({7{(load_opcode & do_read)}} & read_opcode[7:1])) | ({7{(load_opcode & do_fast_read)}} & fast_read_opcode[7:1])) | ({7{((((load_opcode & do_read_volatile) & (~ do_write_volatile)) & (~ do_wren)) & (~ do_read_stat))}} & rdummyclk_opcode[7:1])) | ({7{((((load_opcode & do_write_volatile) & (~ do_read_volatile)) & (~ do_wren)) & (~ do_read_stat))}} & wrvolatile_opcode[7:1])) | ({7{(load_opcode & do_read_nonvolatile)}} & rnvdummyclk_opcode[7:1])) | ({7{(load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren)))}} & write_opcode[7:1])) | ({7{((load_opcode & do_read_stat) & (~ do_polling))}} & rstat_opcode[7:1])) | ({7{((load_opcode & do_read_stat) & do_polling)}} & rflagstat_opcode[7:1])) | ({7{(((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat))}} & serase_opcode[7:1])) | ({7{(((load_opcode & do_die_erase) & (~ do_wren)) & (~ do_read_stat))}} & derase_opcode[7:1])) | ({7{(((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat))}} & berase_opcode[7:1])) | ({7{(load_opcode & do_wren)}} & wren_opcode[7:1])) | ({7{(load_opcode & ((do_4baddr & (~ do_read_stat)) & (~ do_wren)))}} & b4addr_opcode[7:1])) | ({7{(load_opcode & ((do_ex4baddr & (~ do_read_stat)) & (~ do_wren)))}} & exb4addr_opcode[7:1])) | ({7{shift_opcode}} & asmi_opcode_reg[6:0])), ((((((((((((((((((load_opcode & do_read_sid) & rsid_opcode[0]) | ((load_opcode & do_read_rdid) & rdid_opcode[0])) | ((((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & secprot_opcode[0])) | ((load_opcode & do_read) & read_opcode[0])) | ((load_opcode & do_fast_read) & fast_read_opcode[0])) | (((((load_opcode & do_read_volatile) & (~ do_write_volatile)) & (~ do_wren)) & (~ do_read_stat)) & rdummyclk_opcode[0])) | (((((load_opcode & do_write_volatile) & (~ do_read_volatile)) & (~ do_wren)) & (~ do_read_stat
)) & wrvolatile_opcode[0])) | ((load_opcode & do_read_nonvolatile) & rnvdummyclk_opcode[0])) | ((load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren))) & write_opcode[0])) | (((load_opcode & do_read_stat) & (~ do_polling)) & rstat_opcode[0])) | (((load_opcode & do_read_stat) & do_polling) & rflagstat_opcode[0])) | ((((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat)) & serase_opcode[0])) | ((((load_opcode & do_die_erase) & (~ do_wren)) & (~ do_read_stat)) & derase_opcode[0])) | ((((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat)) & berase_opcode[0])) | ((load_opcode & do_wren) & wren_opcode[0])) | ((load_opcode & ((do_4baddr & (~ do_read_stat)) & (~ do_wren))) & b4addr_opcode[0])) | ((load_opcode & ((do_ex4baddr & (~ do_read_stat)) & (~ do_wren))) & exb4addr_opcode[0]))};
assign
wire_asmi_opcode_reg_ena = {8{(load_opcode | shift_opcode)}};
// synopsys translate_off
initial
busy_det_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) busy_det_reg <= 1'b0;
else busy_det_reg <= (~ busy_wire);
// synopsys translate_off
initial
clr_read_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_read_reg <= 1'b0;
else clr_read_reg <= ((do_read_sid | do_sec_prot) | end_operation);
// synopsys translate_off
initial
clr_read_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_read_reg2 <= 1'b0;
else clr_read_reg2 <= clr_read_reg;
// synopsys translate_off
initial
dffe3 = 0;
// synopsys translate_on
// synopsys translate_off
initial
dvalid_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) dvalid_reg <= 1'b0;
else if (wire_dvalid_reg_ena == 1'b1)
if (wire_dvalid_reg_sclr == 1'b1) dvalid_reg <= 1'b0;
else dvalid_reg <= (end_read_byte & end_one_cyc_pos);
assign
wire_dvalid_reg_ena = (do_read | do_fast_read),
wire_dvalid_reg_sclr = (end_op_wire | end_operation);
// synopsys translate_off
initial
dvalid_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) dvalid_reg2 <= 1'b0;
else dvalid_reg2 <= dvalid_reg;
// synopsys translate_off
initial
end1_cyc_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) end1_cyc_reg <= 1'b0;
else end1_cyc_reg <= end1_cyc_reg_in_wire;
// synopsys translate_off
initial
end1_cyc_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end1_cyc_reg2 <= 1'b0;
else end1_cyc_reg2 <= end_one_cycle;
// synopsys translate_off
initial
end_op_hdlyreg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) end_op_hdlyreg <= 1'b0;
else end_op_hdlyreg <= end_operation;
// synopsys translate_off
initial
end_op_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end_op_reg <= 1'b0;
else end_op_reg <= end_op_wire;
// synopsys translate_off
initial
end_rbyte_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end_rbyte_reg <= 1'b0;
else if (wire_end_rbyte_reg_ena == 1'b1)
if (wire_end_rbyte_reg_sclr == 1'b1) end_rbyte_reg <= 1'b0;
else end_rbyte_reg <= (((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0]));
assign
wire_end_rbyte_reg_ena = (((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]) | clr_endrbyte_wire),
wire_end_rbyte_reg_sclr = (clr_endrbyte_wire | addr_overdie);
// synopsys translate_off
initial
end_read_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) end_read_reg <= 1'b0;
else end_read_reg <= ((((~ rden_wire) & (do_read | do_fast_read)) & data_valid_wire) & end_read_byte);
// synopsys translate_off
initial
ncs_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) ncs_reg <= 1'b0;
else if (ncs_reg_ena_wire == 1'b1)
if (wire_ncs_reg_sclr == 1'b1) ncs_reg <= 1'b0;
else ncs_reg <= 1'b1;
assign
wire_ncs_reg_sclr = (end_operation | addr_overdie_pos);
// synopsys translate_off
initial
read_data_reg[0:0] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[0:0] <= 1'b0;
else if (wire_read_data_reg_ena[0:0] == 1'b1) read_data_reg[0:0] <= wire_read_data_reg_d[0:0];
// synopsys translate_off
initial
read_data_reg[1:1] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[1:1] <= 1'b0;
else if (wire_read_data_reg_ena[1:1] == 1'b1) read_data_reg[1:1] <= wire_read_data_reg_d[1:1];
// synopsys translate_off
initial
read_data_reg[2:2] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[2:2] <= 1'b0;
else if (wire_read_data_reg_ena[2:2] == 1'b1) read_data_reg[2:2] <= wire_read_data_reg_d[2:2];
// synopsys translate_off
initial
read_data_reg[3:3] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[3:3] <= 1'b0;
else if (wire_read_data_reg_ena[3:3] == 1'b1) read_data_reg[3:3] <= wire_read_data_reg_d[3:3];
// synopsys translate_off
initial
read_data_reg[4:4] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[4:4] <= 1'b0;
else if (wire_read_data_reg_ena[4:4] == 1'b1) read_data_reg[4:4] <= wire_read_data_reg_d[4:4];
// synopsys translate_off
initial
read_data_reg[5:5] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[5:5] <= 1'b0;
else if (wire_read_data_reg_ena[5:5] == 1'b1) read_data_reg[5:5] <= wire_read_data_reg_d[5:5];
// synopsys translate_off
initial
read_data_reg[6:6] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[6:6] <= 1'b0;
else if (wire_read_data_reg_ena[6:6] == 1'b1) read_data_reg[6:6] <= wire_read_data_reg_d[6:6];
// synopsys translate_off
initial
read_data_reg[7:7] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[7:7] <= 1'b0;
else if (wire_read_data_reg_ena[7:7] == 1'b1) read_data_reg[7:7] <= wire_read_data_reg_d[7:7];
assign
wire_read_data_reg_d = {read_data_reg_in_wire[7:0]};
assign
wire_read_data_reg_ena = {8{(((((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & end_one_cyc_pos) & end_read_byte)}};
// synopsys translate_off
initial
read_dout_reg[0:0] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[0:0] <= 1'b0;
else if (wire_read_dout_reg_ena[0:0] == 1'b1) read_dout_reg[0:0] <= wire_read_dout_reg_d[0:0];
// synopsys translate_off
initial
read_dout_reg[1:1] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[1:1] <= 1'b0;
else if (wire_read_dout_reg_ena[1:1] == 1'b1) read_dout_reg[1:1] <= wire_read_dout_reg_d[1:1];
// synopsys translate_off
initial
read_dout_reg[2:2] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[2:2] <= 1'b0;
else if (wire_read_dout_reg_ena[2:2] == 1'b1) read_dout_reg[2:2] <= wire_read_dout_reg_d[2:2];
// synopsys translate_off
initial
read_dout_reg[3:3] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[3:3] <= 1'b0;
else if (wire_read_dout_reg_ena[3:3] == 1'b1) read_dout_reg[3:3] <= wire_read_dout_reg_d[3:3];
// synopsys translate_off
initial
read_dout_reg[4:4] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[4:4] <= 1'b0;
else if (wire_read_dout_reg_ena[4:4] == 1'b1) read_dout_reg[4:4] <= wire_read_dout_reg_d[4:4];
// synopsys translate_off
initial
read_dout_reg[5:5] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[5:5] <= 1'b0;
else if (wire_read_dout_reg_ena[5:5] == 1'b1) read_dout_reg[5:5] <= wire_read_dout_reg_d[5:5];
// synopsys translate_off
initial
read_dout_reg[6:6] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[6:6] <= 1'b0;
else if (wire_read_dout_reg_ena[6:6] == 1'b1) read_dout_reg[6:6] <= wire_read_dout_reg_d[6:6];
// synopsys translate_off
initial
read_dout_reg[7:7] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[7:7] <= 1'b0;
else if (wire_read_dout_reg_ena[7:7] == 1'b1) read_dout_reg[7:7] <= wire_read_dout_reg_d[7:7];
assign
wire_read_dout_reg_d = {read_dout_reg[6:0], (data0out_wire | dataout_wire[1])};
assign
wire_read_dout_reg_ena = {8{((stage4_wire & ((do_read | do_fast_read) | do_read_sid)) | (stage3_wire & (((do_read_stat | do_read_rdid) | do_read_volatile) | do_read_nonvolatile)))}};
// synopsys translate_off
initial
read_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_reg <= 1'b0;
else if (wire_read_reg_ena == 1'b1)
if (clr_read_wire == 1'b1) read_reg <= 1'b0;
else read_reg <= read;
assign
wire_read_reg_ena = (((~ busy_wire) & rden_wire) | clr_read_wire);
// synopsys translate_off
initial
shift_op_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) shift_op_reg <= 1'b0;
else shift_op_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
stage2_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) stage2_reg <= 1'b0;
else stage2_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
stage3_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) stage3_reg <= 1'b0;
else stage3_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
stage4_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) stage4_reg <= 1'b0;
else stage4_reg <= (wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0]));
assign wire_mux211_dataout = (do_fast_read === 1'b1) ? end_add_cycle_mux_datab_wire : (wire_addbyte_cntr_q[1] & (~ wire_addbyte_cntr_q[0]));
assign
addr_overdie = 1'b0,
addr_overdie_pos = 1'b0,
addr_reg_overdie = {24{1'b0}},
b4addr_opcode = {8{1'b0}},
berase_opcode = {8{1'b0}},
busy = busy_wire,
busy_wire = ((((((((((((((do_read_rdid | do_read_sid) | do_read) | do_fast_read) | do_write) | do_sec_prot) | do_read_stat) | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_read_volatile) | do_fread_epcq) | do_read_nonvolatile) | do_ex4baddr),
clkin_wire = clkin,
clr_addmsb_wire = (((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & end_add_cycle) & end_one_cyc_pos) | (((~ do_read) & (~ do_fast_read)) & clr_write_wire2)) | ((((do_sec_erase | do_die_erase) & (~ do_wren)) & (~ do_read_stat)) & end_operation)),
clr_endrbyte_wire = (((((do_read | do_fast_read) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | clr_read_wire2),
clr_read_wire = clr_read_reg,
clr_read_wire2 = clr_read_reg2,
clr_rstat_wire = 1'b0,
clr_sid_wire = 1'b0,
clr_write_wire2 = 1'b0,
data0out_wire = wire_sd2_data1in,
data_valid = data_valid_wire,
data_valid_wire = dvalid_reg2,
dataoe_wire = {{2{1'b1}}, 1'b0, 1'b1},
dataout = {read_data_reg[7:0]},
dataout_wire = {{4{1'b0}}},
derase_opcode = {8{1'b0}},
do_4baddr = 1'b0,
do_bulk_erase = 1'b0,
do_die_erase = 1'b0,
do_ex4baddr = 1'b0,
do_fast_read = 1'b0,
do_fread_epcq = 1'b0,
do_freadwrv_polling = 1'b0,
do_memadd = 1'b0,
do_polling = ((do_write_polling | do_sprot_polling) | do_freadwrv_polling),
do_read = ((((~ read_rdid_wire) & (~ read_sid_wire)) & (~ sec_protect_wire)) & read_wire),
do_read_nonvolatile = 1'b0,
do_read_rdid = 1'b0,
do_read_sid = 1'b0,
do_read_stat = 1'b0,
do_read_volatile = 1'b0,
do_sec_erase = 1'b0,
do_sec_prot = 1'b0,
do_sprot_polling = 1'b0,
do_wait_dummyclk = 1'b0,
do_wren = 1'b0,
do_write = 1'b0,
do_write_polling = 1'b0,
do_write_volatile = 1'b0,
end1_cyc_gen_cntr_wire = ((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & (~ wire_gen_cntr_q[0])),
end1_cyc_normal_in_wire = ((((((((((((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1])) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | ((~ ((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1]))) & end1_cyc_gen_cntr_wire)) | (do_read & end_read)) | (do_fast_read & end_fast_read)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | (do_write & (~ pagewr_buf_not_empty[0]))) | ((do_read_stat & start_poll) & (~ st_busy_wire))) | (do_read_rdid & end_op_wire)),
end1_cyc_reg_in_wire = end1_cyc_normal_in_wire,
end_add_cycle = wire_mux211_dataout,
end_add_cycle_mux_datab_wire = (wire_addbyte_cntr_q[2] & wire_addbyte_cntr_q[1]),
end_fast_read = end_read_reg,
end_one_cyc_pos = end1_cyc_reg2,
end_one_cycle = end1_cyc_reg,
end_op_wire = ((((((((((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & ((((((~ do_read) & (~ do_fast_read)) & (~ (do_write & shift_pgwr_data))) & end_one_cycle) | (do_read & end_read)) | (do_fast_read & end_fast_read))) | ((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_read_stat) & end_one_cycle) & (~ do_polling))) | ((((((do_read_rdid & end_one_cyc_pos) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & wire_addbyte_cntr_q[2]) & wire_addbyte_cntr_q[1]) & (~ wire_addbyte_cntr_q[0]))) | (((start_poll & do_read_stat) & do_polling) & (~ st_busy_wire))) | ((((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & (do_wren | (do_4baddr | (do_ex4baddr | (do_bulk_erase & (~ do_read_stat)))))) & end_one_cycle)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | ((do_write & shift_pgwr_data) & end_pgwr_data)) | (do_write & (~ pagewr_buf_not_empty[0]))) | (((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & end_one_cycle)) | ((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & (do_sec_erase | do_die_erase)) & (~ do_wren)) & (~ do_read_stat)) & end_add_cycle) & end_one_cycle)) | (((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & end_one_cycle) & ((do_write_volatile | do_read_volatile) | (do_read_nonvolatile & wire_addbyte_cntr_q[1])))),
end_operation = end_op_reg,
end_ophdly = end_op_hdlyreg,
end_pgwr_data = 1'b0,
end_read = end_read_reg,
end_read_byte = (end_rbyte_reg & (~ addr_overdie)),
exb4addr_opcode = {8{1'b0}},
fast_read_opcode = {8{1'b0}},
freadwrv_sdoin = 1'b0,
in_operation = busy_wire,
load_opcode = (((((~ wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & (~ wire_gen_cntr_q[2])) & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]),
memadd_sdoin = add_msb_reg,
ncs_reg_ena_wire = (((((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & end_one_cyc_pos) | addr_overdie_pos) | end_operation),
not_busy = busy_det_reg,
oe_wire = 1'b0,
pagewr_buf_not_empty = {1'b1},
rden_wire = rden,
rdid_opcode = {8{1'b0}},
rdummyclk_opcode = {8{1'b0}},
read_data_reg_in_wire = {read_dout_reg[7:0]},
read_opcode = 8'b00000011,
read_rdid_wire = 1'b0,
read_sid_wire = 1'b0,
read_wire = read_reg,
rflagstat_opcode = {8{1'b0}},
rnvdummyclk_opcode = {8{1'b0}},
rsid_opcode = {8{1'b0}},
rsid_sdoin = 1'b0,
rstat_opcode = {8{1'b0}},
scein_wire = (~ ncs_reg),
sdoin_wire = to_sdoin_wire,
sec_protect_wire = 1'b0,
secprot_opcode = {8{1'b0}},
secprot_sdoin = 1'b0,
serase_opcode = {8{1'b0}},
shift_opcode = shift_op_reg,
shift_opdata = stage2_wire,
shift_pgwr_data = 1'b0,
st_busy_wire = 1'b0,
stage2_wire = stage2_reg,
stage3_wire = stage3_reg,
stage4_wire = stage4_reg,
start_frpoll = 1'b0,
start_poll = ((start_wrpoll | start_sppoll) | start_frpoll),
start_sppoll = 1'b0,
start_wrpoll = 1'b0,
to_sdoin_wire = ((((((shift_opdata & asmi_opcode_reg[7]) | rsid_sdoin) | memadd_sdoin) | write_sdoin) | secprot_sdoin) | freadwrv_sdoin),
wren_opcode = {8{1'b0}},
wren_wire = 1'b1,
write_opcode = {8{1'b0}},
write_prot_true = 1'b0,
write_sdoin = 1'b0,
wrvolatile_opcode = {8{1'b0}};
endmodule
|
module ym09(
input wire clk50,
input wire ext_rst,
// UART pins
input wire uart_rx,
output wire uart_tx,
// YM2151 pins
inout wire [7:0] ym_d,
output wire ym_a0,
output wire ym_wr_n,
output wire ym_rd_n,
output wire ym_cs_n,
output wire ym_ic_n,
input wire ym_irq_n,
input wire ym_ct1,
input wire ym_ct2,
input wire ym_so,
input wire ym_sh1,
input wire ym_sh2,
output wire ym_pm, // system clock
input wire ym_p1, // DAC clock
// level shifters
output wire DIR, // 0 means FPGA writes on YM, 1 means FPGA reads from YM
// LED control
output reg [7:0] led,
input wire [2:0] ledcfg,
input wire uart_speed,
input wire dump_memory
);
/* historial de versiones
6 Separado el estado de la UART de rx y tx en dos posiciones de memoria distintos
9 RAM ampliada a 32 kB. Esta version no sintetizaba a 50MHz.
10 Volcado de memoria por la UART. Esta version no sintetizaba a 50MHz.
11 Control de la velocidad del YM2151 para poder bajarla durante el volcado directo.
12 La velocidad lenta del YM es aun mas lenta.
13 Añade la lectura del audio en formato exponencial directamente por la CPU
14 Añade lectura de datos YM sincronizados con ym_p1
15 Añade el JT51
16 Actualiza el JT51 y trata de medir el OP31
*/
parameter version_number = 8'd16;
wire [15:0] cpu_addr;
wire [ 7:0] cpu_data_i, cpu_data_o, memory_data_o;
wire cpu_rw, cpu_vma;
wire ram_cs;
wire [7:0] uart_rx_byte, uart_tx_byte, uart_error_count;
wire uart_transmit, uart_received;
wire uart_irq, uart_irq_clear;
wire [2:0] uart_status;
wire [ 7:0] led09, led09_alt, fsm_led;
wire [11:0] fsm_addr;
wire fsm_wr;
wire cpu_rst;
wire [15:0] jt51_left, jt51_right;
wire [7:0] jt51_do;
wire jt51_ct1, jt51_ct2, jt51_irq_n, jt51_sh1, jt51_sh2;
wire rst;
always @(*) begin
case( ledcfg )
default: led <= cpu_rst ? fsm_led : led09;
3'b000: led <= { ym_ic_n, 3'd0, ym_cs_n, ym_wr_n, ym_rd_n, ym_a0 };
3'b001: led <= { ym_irq_n, ym_ct2, ym_ct1, ym_pm,
ym_p1, ym_sh2, ym_sh1, ym_so };
3'b010: led <= fsm_addr[ 7:0];
3'b011: led <= { 4'h0, fsm_addr[11:8] };
3'b100: led <= cpu_rst ? fsm_led : led09;
3'b101: led <= cpu_rst ? fsm_led : led09_alt;
3'b110: led <= { uart_irq, 3'b0, 1'b0, uart_status };
3'b111: led <= version_number;
endcase
end
pll u_pll (
.CLKIN_IN(clk50),
.CLKFX_OUT(clk) // 16.67 MHz
//.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
//.CLK0_OUT(CLK0_OUT),
//.LOCKED_OUT(LOCKED_OUT)
);
fpga_reset u_rst(
.clk ( clk ),
.ext_rst( ext_rst ),
.rst ( rst )
);
wire dump_memory_sync;
debouncer u_debouncer(
.clk ( clk ),
.rst ( rst ),
.PB ( dump_memory ), // "PB" is the glitchy, asynchronous to clk, active low push-button signal
.PB_up ( dump_memory_sync ) // 1 for one clock cycle when the push-button goes up (i.e. just released)
);
system_bus #(version_number) u_bus(
.clk ( clk ),
.rst ( rst ),
.cpu_data_i ( cpu_data_i ),
.cpu_data_o ( cpu_data_o ),
.cpu_rw ( cpu_rw ),
.cpu_vma ( cpu_vma ),
.memory_data_o ( memory_data_o ),
.address ( cpu_addr ),
.ram_cs ( ram_cs ),
// UART
.uart_rx_byte ( uart_rx_byte ),
.uart_transmit ( uart_transmit ),
.uart_tx_byte ( uart_tx_byte ),
.rx_status ( rx_status ), // IRQ handling
.tx_status ( tx_status ),
.rx_status_clear( rx_status_clear),
.tx_status_clear( tx_status_clear),
.uart_speed ( uart_speed ),
// YM2151 pins
.ym_d ( ym_d ),
.ym_a0 ( ym_a0 ),
.ym_wr_n ( ym_wr_n ),
.ym_rd_n ( ym_rd_n ),
.ym_cs_n ( ym_cs_n ),
.ym_ic_n ( ym_ic_n ),
.ym_irq_n ( ym_irq_n ),
.ym_ct1 ( ym_ct1 ),
.ym_ct2 ( ym_ct2 ),
.ym_so ( ym_so ),
.ym_sh1 ( ym_sh1 ),
.ym_sh2 ( ym_sh2 ),
.ym_pm ( ym_pm ),
.ym_p1 ( ym_p1 ),
// JT51 pins
.jt51_cs_n ( jt51_cs_n ),
.jt51_left ( jt51_left ),
.jt51_right ( jt51_right ),
.jt51_do ( jt51_do ),
.jt51_ct1 ( jt51_ct1 ),
.jt51_ct2 ( jt51_ct2 ),
.jt51_irq_n ( jt51_irq_n ),
.jt51_sh1 ( jt51_sh1 ),
.jt51_sh2 ( jt51_sh2 ),
// level shifters
.dir ( DIR ), // 0 means FPGA writes on YM, 1 means FPGA reads from YM
// LED
.led ( led09 ),
.led_alt ( led09_alt )
);
memory #(15)u_memory(
.datain ( fsm_wr ? uart_rx_byte : cpu_data_o ),
.dataout( memory_data_o ),
.clk ( clk ),
.addr ( cpu_rst ? {3'b111, fsm_addr} : cpu_addr[14:0] ),
.en ( cpu_rst | ram_cs ),
.we ( cpu_rst ? fsm_wr : ~cpu_rw ) // high for write, low for read
);
uart09 #(12)u_uart(
.clk ( clk ),
.rst ( rst ),
.uart_rx ( uart_rx ),
.uart_tx ( uart_tx ),
.uart_rx_byte ( uart_rx_byte ),
.uart_transmit ( uart_transmit ),
.uart_tx_byte ( uart_tx_byte ),
.mem_data_o ( memory_data_o ),
.uart_error_count( uart_error_count ),
.uart_received ( uart_received ),
.uart_speed ( uart_speed ),
// IRQ handling
.rx_status ( rx_status ),
.tx_status ( tx_status ),
.rx_status_clear( rx_status_clear ),
.tx_status_clear( tx_status_clear ),
// control RAM load
.fsm_addr ( fsm_addr ),
.fsm_wr ( fsm_wr ),
.cpu_rst ( cpu_rst ),
.led ( fsm_led ),
.dump_memory ( dump_memory_sync )
);
//wire [15:0] pc_out;
cpu09 cpu(
.clk ( clk ),
.rst ( cpu_rst ),
.rw ( cpu_rw ),
.vma ( cpu_vma ),
.address ( cpu_addr ),
.data_in ( cpu_data_i ),
.data_out( cpu_data_o ),
.halt ( 1'b0 ),
.hold ( 1'b0 ),
.irq ( rx_status ),
.firq ( 1'b0 ),
.nmi ( 1'b0 ),
.pc_out ( )
);
jt51 u_jt51(
.clk ( ~clk ), // main clock
.rst ( cpu_rst ), // reset
.cs_n ( jt51_cs_n ), // chip select
.wr_n ( ~cpu_rw ), // write
.a0 ( cpu_addr[0] ),
.d_in ( cpu_data_o), // data in
.d_out ( jt51_do ), // data out
.ct1 ( jt51_ct1 ),
.ct2 ( jt51_ct2 ),
.irq_n ( jt51_irq_n),
.left ( jt51_left ),
.right ( jt51_right)
);
endmodule
|
module
parameter LPT_LOW = 2'b00; //low precision timestamp low register
parameter LPT_HIGH = 2'b01; //low precision timestamp high register
parameter HPT_LOW = 2'b10; //high precision timestamp low register
parameter HPT_HIGH = 2'b11; //high precision timestamp high register
wire select;
// Address decoder generates the select sinal out of the upper part of the peripheral address.
pselect iCSL (
.addr ( addr_peri[9:2] ),
.activ_peri ( access_peri ),
.select ( select )
);
defparam iCSL.ADDR_WIDTH = 8;
defparam iCSL.BASE_WIDTH = 8;
defparam iCSL.BASE_ADDR = BASE_ADR >> 2; //BASE_ADR has to be divisible by 4
//counter write register
reg [35:0] lpt_counter_write;
reg [35:0] hpt_counter_write;
reg counter_write_req;
//SpartanMC peripheral interface read logic -> no read
assign di_peri = 18'b0;
//SpartanMC peripheral interface write logic
always @(posedge clk_peri) begin
if (reset) begin
counter_write_req <= 1'b0;
end else begin
if (select & wr_peri) begin
case (addr_peri[1:0])
LPT_LOW: lpt_counter_write[17:0] = do_peri[17:0];
LPT_HIGH: lpt_counter_write[35:18] = do_peri[17:0];
HPT_LOW: hpt_counter_write[17:0] = do_peri[17:0];
HPT_HIGH: begin
hpt_counter_write[35:18] = do_peri[17:0];
counter_write_req <= 1'b1;
end
endcase
end else begin
counter_write_req <= 1'b0;
end
end
end
//counter logic
always @(posedge clk_peri) begin
if (reset) begin
hpt_counter <= 18'd0; //reset counters to 0
lpt_counter <= 18'd0;
end else begin
if (counter_write_req == 1'b1)begin
hpt_counter <= hpt_counter_write;
lpt_counter <= lpt_counter_write;
end else begin
if (hpt_counter == CLOCK_FREQUENCY-1) begin
hpt_counter <= 18'd0; //reset high precision counter if max value reached
lpt_counter <= lpt_counter + 1; //increment low precision counter
end else
hpt_counter <= hpt_counter + 1; //otherwise increment high precision counter
end
end
end
endmodule
|
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
module system_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
input wire TTC0_CLK0_IN;
input wire TTC0_CLK1_IN;
input wire TTC0_CLK2_IN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_3_processing_system7 #(
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("false"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TD_I(1'B0),
.PJTAG_TD_T(),
.PJTAG_TD_O(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B0),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(TTC0_CLK0_IN),
.TTC0_CLK1_IN(TTC0_CLK1_IN),
.TTC0_CLK2_IN(TTC0_CLK2_IN),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(),
.USB0_VBUS_PWRSELECT(),
.USB0_VBUS_PWRFAULT(1'B0),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(),
.M_AXI_GP0_AWVALID(),
.M_AXI_GP0_BREADY(),
.M_AXI_GP0_RREADY(),
.M_AXI_GP0_WLAST(),
.M_AXI_GP0_WVALID(),
.M_AXI_GP0_ARID(),
.M_AXI_GP0_AWID(),
.M_AXI_GP0_WID(),
.M_AXI_GP0_ARBURST(),
.M_AXI_GP0_ARLOCK(),
.M_AXI_GP0_ARSIZE(),
.M_AXI_GP0_AWBURST(),
.M_AXI_GP0_AWLOCK(),
.M_AXI_GP0_AWSIZE(),
.M_AXI_GP0_ARPROT(),
.M_AXI_GP0_AWPROT(),
.M_AXI_GP0_ARADDR(),
.M_AXI_GP0_AWADDR(),
.M_AXI_GP0_WDATA(),
.M_AXI_GP0_ARCACHE(),
.M_AXI_GP0_ARLEN(),
.M_AXI_GP0_ARQOS(),
.M_AXI_GP0_AWCACHE(),
.M_AXI_GP0_AWLEN(),
.M_AXI_GP0_AWQOS(),
.M_AXI_GP0_WSTRB(),
.M_AXI_GP0_ACLK(1'B0),
.M_AXI_GP0_ARREADY(1'B0),
.M_AXI_GP0_AWREADY(1'B0),
.M_AXI_GP0_BVALID(1'B0),
.M_AXI_GP0_RLAST(1'B0),
.M_AXI_GP0_RVALID(1'B0),
.M_AXI_GP0_WREADY(1'B0),
.M_AXI_GP0_BID(12'B0),
.M_AXI_GP0_RID(12'B0),
.M_AXI_GP0_BRESP(2'B0),
.M_AXI_GP0_RRESP(2'B0),
.M_AXI_GP0_RDATA(32'B0),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG(4'B0),
.FTMT_F2P_TRIGACK(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK(4'B0),
.FTMT_P2F_TRIG(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ms__dlrbp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
|
module ALU(A, B, ALUOp , ALUOut, Zero);
output reg [31:0] ALUOut;
output reg [0:0] Zero;
input [31:0] A, B;
input [4:0] ALUOp;
parameter ADD = 5'd0;
parameter SUB = 5'd1;
parameter ADDI = 5'd2;
parameter SUBI = 5'd3;
parameter MLT = 5'd4;
parameter MLTI = 5'd5;
parameter AND = 5'd6;
parameter OR = 5'd7;
parameter ANDI = 5'd8;
parameter ORI = 5'd9;
parameter SLR = 5'd10;
parameter SLL = 5'd11;
parameter LDR = 5'd12;
parameter STR = 5'd13;
parameter BNE = 5'd14;
parameter BEQ = 5'd15;
parameter J = 5'd16;
parameter CMP = 5'd17;
parameter NOP = 5'b11111;
parameter on = 1'd1;
parameter off = 1'd0;
initial begin
ALUOut=32'd0;
Zero=1'd0;
end
always @ (A or B or ALUOp) begin
case (ALUOp)
ADD:
begin
ALUOut = A+B;
Zero=off;
end
SUB:
begin
ALUOut = A-B;
Zero=off;
end
ADDI:
begin
ALUOut = A+B;
Zero=off;
end
SUBI:
begin
ALUOut = A-B;
Zero=off;
end
MLT:
begin
ALUOut = A*B;
Zero=off;
end
MLTI:
begin
ALUOut = A*B;
Zero=off;
end
AND:
begin
ALUOut = A&B;
Zero=off;
end
OR:
begin
ALUOut = A|B;
Zero=off;
end
ANDI:
begin
ALUOut = A&B;
Zero=off;
end
ORI:
begin
ALUOut = A|B;
Zero=off;
end
SLR:
begin
ALUOut = A>>B;
Zero=off;
end
SLL:
begin
ALUOut = A<<B;
Zero=off;
end
LDR:
begin
ALUOut = A+B;
Zero=off;
end
STR:
begin
ALUOut = A+B;
Zero=off;
end
BNE:
begin
ALUOut = 32'd0;
if(A==B) Zero=on;
else Zero=off;
end
BEQ:
begin
ALUOut = 32'd0;
if (A==B) Zero=on;
else Zero=off;
end
CMP:
begin
if (A>B) ALUOut=2'd1;
else if(A==B) ALUOut=2'd0;
else ALUOut=2'd2;
Zero=off;
end
default:
begin
ALUOut = 32'd0;
Zero=off;
end
endcase
end
endmodule
|
module outputs)
wire [15:0] ecfg_clk_settings; // From ecfg of ecfg.v
wire [11:0] ecfg_coreid; // From ecfg of ecfg.v
wire [10:0] ecfg_dataout; // From ecfg of ecfg.v
wire [8:0] ecfg_rx_datain; // From erx of erx.v
wire [15:0] ecfg_rx_debug; // From erx of erx.v
wire ecfg_rx_enable; // From ecfg of ecfg.v
wire ecfg_rx_gpio_enable; // From ecfg of ecfg.v
wire ecfg_rx_mmu_enable; // From ecfg of ecfg.v
wire ecfg_timeout_enable; // From ecfg of ecfg.v
wire [3:0] ecfg_tx_ctrlmode; // From ecfg of ecfg.v
wire [1:0] ecfg_tx_datain; // From etx of etx.v
wire [15:0] ecfg_tx_debug; // From etx of etx.v
wire ecfg_tx_enable; // From ecfg of ecfg.v
wire ecfg_tx_gpio_enable; // From ecfg of ecfg.v
wire ecfg_tx_mmu_enable; // From ecfg of ecfg.v
wire emaxi_emrq_access; // From erx of erx.v
wire [3:0] emaxi_emrq_ctrlmode; // From erx of erx.v
wire [31:0] emaxi_emrq_data; // From erx of erx.v
wire [1:0] emaxi_emrq_datamode; // From erx of erx.v
wire [31:0] emaxi_emrq_dstaddr; // From erx of erx.v
wire emaxi_emrq_rd_en; // From emaxi of emaxi.v
wire [31:0] emaxi_emrq_srcaddr; // From erx of erx.v
wire emaxi_emrq_write; // From erx of erx.v
wire emaxi_emrr_access; // From emaxi of emaxi.v
wire [3:0] emaxi_emrr_ctrlmode; // From emaxi of emaxi.v
wire [31:0] emaxi_emrr_data; // From emaxi of emaxi.v
wire [1:0] emaxi_emrr_datamode; // From emaxi of emaxi.v
wire [31:0] emaxi_emrr_dstaddr; // From emaxi of emaxi.v
wire emaxi_emrr_progfull; // From etx of etx.v
wire [31:0] emaxi_emrr_srcaddr; // From emaxi of emaxi.v
wire emaxi_emrr_write; // From emaxi of emaxi.v
wire emaxi_emwr_access; // From erx of erx.v
wire [3:0] emaxi_emwr_ctrlmode; // From erx of erx.v
wire [31:0] emaxi_emwr_data; // From erx of erx.v
wire [1:0] emaxi_emwr_datamode; // From erx of erx.v
wire [31:0] emaxi_emwr_dstaddr; // From erx of erx.v
wire emaxi_emwr_rd_en; // From emaxi of emaxi.v
wire [31:0] emaxi_emwr_srcaddr; // From erx of erx.v
wire emaxi_emwr_write; // From erx of erx.v
wire esaxi_emrq_access; // From esaxi of esaxi.v
wire [3:0] esaxi_emrq_ctrlmode; // From esaxi of esaxi.v
wire [31:0] esaxi_emrq_data; // From esaxi of esaxi.v
wire [1:0] esaxi_emrq_datamode; // From esaxi of esaxi.v
wire [31:0] esaxi_emrq_dstaddr; // From esaxi of esaxi.v
wire esaxi_emrq_progfull; // From etx of etx.v
wire [31:0] esaxi_emrq_srcaddr; // From esaxi of esaxi.v
wire esaxi_emrq_write; // From esaxi of esaxi.v
wire esaxi_emrr_access; // From erx of erx.v
wire [31:0] esaxi_emrr_data; // From erx of erx.v
wire esaxi_emrr_rd_en; // From esaxi of esaxi.v
wire esaxi_emwr_access; // From esaxi of esaxi.v
wire [3:0] esaxi_emwr_ctrlmode; // From esaxi of esaxi.v
wire [31:0] esaxi_emwr_data; // From esaxi of esaxi.v
wire [1:0] esaxi_emwr_datamode; // From esaxi of esaxi.v
wire [31:0] esaxi_emwr_dstaddr; // From esaxi of esaxi.v
wire esaxi_emwr_progfull; // From etx of etx.v
wire [31:0] esaxi_emwr_srcaddr; // From esaxi of esaxi.v
wire esaxi_emwr_write; // From esaxi of esaxi.v
wire [19:0] mi_addr; // From esaxi of esaxi.v
wire mi_clk; // From esaxi of esaxi.v
wire [31:0] mi_din; // From esaxi of esaxi.v
wire [31:0] mi_ecfg_dout; // From ecfg of ecfg.v
wire mi_ecfg_sel; // From esaxi of esaxi.v
wire [DW-1:0] mi_embox_dout; // From embox of embox.v
wire mi_embox_sel; // From esaxi of esaxi.v
wire [31:0] mi_rx_emmu_dout; // From erx of erx.v
wire mi_rx_emmu_sel; // From esaxi of esaxi.v
wire [31:0] mi_tx_emmu_dout; // From etx of etx.v
wire mi_tx_emmu_sel; // From esaxi of esaxi.v
wire mi_we; // From esaxi of esaxi.v
wire reset; // From ereset of ereset.v
wire soft_reset; // From ecfg of ecfg.v
wire tx_lclk; // From eclocks of eclocks.v
wire tx_lclk_out; // From eclocks of eclocks.v
wire tx_lclk_par; // From eclocks of eclocks.v
// End of automatics
/***********************************************************/
/*AXI MASTER */
/***********************************************************/
/*emaxi AUTO_TEMPLATE (
// Outputs
.m00_\(.*\) (m_\1[]),
.em\(.*\) (emaxi_em\1[]),
);
*/
defparam emaxi.IDW =IDW; //ID width from instantiation
emaxi emaxi(
/*AUTOINST*/
// Outputs
.emwr_rd_en (emaxi_emwr_rd_en), // Templated
.emrq_rd_en (emaxi_emrq_rd_en), // Templated
.emrr_access (emaxi_emrr_access), // Templated
.emrr_write (emaxi_emrr_write), // Templated
.emrr_datamode (emaxi_emrr_datamode[1:0]), // Templated
.emrr_ctrlmode (emaxi_emrr_ctrlmode[3:0]), // Templated
.emrr_dstaddr (emaxi_emrr_dstaddr[31:0]), // Templated
.emrr_data (emaxi_emrr_data[31:0]), // Templated
.emrr_srcaddr (emaxi_emrr_srcaddr[31:0]), // Templated
.m_axi_awid (m_axi_awid[IDW-1:0]),
.m_axi_awaddr (m_axi_awaddr[31:0]),
.m_axi_awlen (m_axi_awlen[7:0]),
.m_axi_awsize (m_axi_awsize[2:0]),
.m_axi_awburst (m_axi_awburst[1:0]),
.m_axi_awlock (m_axi_awlock[1:0]),
.m_axi_awcache (m_axi_awcache[3:0]),
.m_axi_awprot (m_axi_awprot[2:0]),
.m_axi_awqos (m_axi_awqos[3:0]),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_wid (m_axi_wid[IDW-1:0]),
.m_axi_wdata (m_axi_wdata[63:0]),
.m_axi_wstrb (m_axi_wstrb[7:0]),
.m_axi_wlast (m_axi_wlast),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_bready (m_axi_bready),
.m_axi_arid (m_axi_arid[IDW-1:0]),
.m_axi_araddr (m_axi_araddr[31:0]),
.m_axi_arlen (m_axi_arlen[7:0]),
.m_axi_arsize (m_axi_arsize[2:0]),
.m_axi_arburst (m_axi_arburst[1:0]),
.m_axi_arlock (m_axi_arlock[1:0]),
.m_axi_arcache (m_axi_arcache[3:0]),
.m_axi_arprot (m_axi_arprot[2:0]),
.m_axi_arqos (m_axi_arqos[3:0]),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_rready (m_axi_rready),
// Inputs
.emwr_access (emaxi_emwr_access), // Templated
.emwr_write (emaxi_emwr_write), // Templated
.emwr_datamode (emaxi_emwr_datamode[1:0]), // Templated
.emwr_ctrlmode (emaxi_emwr_ctrlmode[3:0]), // Templated
.emwr_dstaddr (emaxi_emwr_dstaddr[31:0]), // Templated
.emwr_data (emaxi_emwr_data[31:0]), // Templated
.emwr_srcaddr (emaxi_emwr_srcaddr[31:0]), // Templated
.emrq_access (emaxi_emrq_access), // Templated
.emrq_write (emaxi_emrq_write), // Templated
.emrq_datamode (emaxi_emrq_datamode[1:0]), // Templated
.emrq_ctrlmode (emaxi_emrq_ctrlmode[3:0]), // Templated
.emrq_dstaddr (emaxi_emrq_dstaddr[31:0]), // Templated
.emrq_data (emaxi_emrq_data[31:0]), // Templated
.emrq_srcaddr (emaxi_emrq_srcaddr[31:0]), // Templated
.emrr_progfull (emaxi_emrr_progfull), // Templated
.m_axi_aclk (m_axi_aclk),
.m_axi_aresetn (m_axi_aresetn),
.m_axi_awready (m_axi_awready),
.m_axi_wready (m_axi_wready),
.m_axi_bid (m_axi_bid[IDW-1:0]),
.m_axi_bresp (m_axi_bresp[1:0]),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rid (m_axi_rid[IDW-1:0]),
.m_axi_rdata (m_axi_rdata[63:0]),
.m_axi_rresp (m_axi_rresp[1:0]),
.m_axi_rlast (m_axi_rlast),
.m_axi_rvalid (m_axi_rvalid));
/***********************************************************/
/*AXI SLAVE */
/***********************************************************/
/*esaxi AUTO_TEMPLATE (
// Outputs
.s00_\(.*\) (s_\1[]),
.emwr_\(.*\) (esaxi_emwr_\1[]),
.emrq_\(.*\) (esaxi_emrq_\1[]),
.emrr_\(.*\) (esaxi_emrr_\1[]),
);
*/
defparam esaxi.ELINKID=ELINKID; //passing along ID from top level
defparam esaxi.IDW =IDW; //ID width from instantiation
esaxi esaxi(
/*AUTOINST*/
// Outputs
.emwr_access (esaxi_emwr_access), // Templated
.emwr_write (esaxi_emwr_write), // Templated
.emwr_datamode (esaxi_emwr_datamode[1:0]), // Templated
.emwr_ctrlmode (esaxi_emwr_ctrlmode[3:0]), // Templated
.emwr_dstaddr (esaxi_emwr_dstaddr[31:0]), // Templated
.emwr_data (esaxi_emwr_data[31:0]), // Templated
.emwr_srcaddr (esaxi_emwr_srcaddr[31:0]), // Templated
.emrq_access (esaxi_emrq_access), // Templated
.emrq_write (esaxi_emrq_write), // Templated
.emrq_datamode (esaxi_emrq_datamode[1:0]), // Templated
.emrq_ctrlmode (esaxi_emrq_ctrlmode[3:0]), // Templated
.emrq_dstaddr (esaxi_emrq_dstaddr[31:0]), // Templated
.emrq_data (esaxi_emrq_data[31:0]), // Templated
.emrq_srcaddr (esaxi_emrq_srcaddr[31:0]), // Templated
.emrr_rd_en (esaxi_emrr_rd_en), // Templated
.mi_clk (mi_clk),
.mi_rx_emmu_sel (mi_rx_emmu_sel),
.mi_tx_emmu_sel (mi_tx_emmu_sel),
.mi_ecfg_sel (mi_ecfg_sel),
.mi_embox_sel (mi_embox_sel),
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[31:0]),
.s_axi_arready (s_axi_arready),
.s_axi_awready (s_axi_awready),
.s_axi_bid (s_axi_bid[IDW-1:0]),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_rid (s_axi_rid[IDW-1:0]),
.s_axi_rdata (s_axi_rdata[31:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_wready (s_axi_wready),
// Inputs
.emwr_progfull (esaxi_emwr_progfull), // Templated
.emrq_progfull (esaxi_emrq_progfull), // Templated
.emrr_data (esaxi_emrr_data[31:0]), // Templated
.emrr_access (esaxi_emrr_access), // Templated
.mi_ecfg_dout (mi_ecfg_dout[31:0]),
.mi_tx_emmu_dout (mi_tx_emmu_dout[31:0]),
.mi_rx_emmu_dout (mi_rx_emmu_dout[31:0]),
.mi_embox_dout (mi_embox_dout[31:0]),
.ecfg_tx_ctrlmode (ecfg_tx_ctrlmode[3:0]),
.ecfg_coreid (ecfg_coreid[11:0]),
.ecfg_timeout_enable (ecfg_timeout_enable),
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_arid (s_axi_arid[IDW-1:0]),
.s_axi_araddr (s_axi_araddr[31:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_arlock (s_axi_arlock[1:0]),
.s_axi_arlen (s_axi_arlen[7:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arqos (s_axi_arqos[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_awid (s_axi_awid[IDW-1:0]),
.s_axi_awaddr (s_axi_awaddr[31:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awlock (s_axi_awlock[1:0]),
.s_axi_awlen (s_axi_awlen[7:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awqos (s_axi_awqos[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_bready (s_axi_bready),
.s_axi_rready (s_axi_rready),
.s_axi_wid (s_axi_wid[IDW-1:0]),
.s_axi_wdata (s_axi_wdata[31:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wstrb (s_axi_wstrb[3:0]),
.s_axi_wvalid (s_axi_wvalid));
/***********************************************************/
/*RECEIVER */
/***********************************************************/
/*erx AUTO_TEMPLATE (
.mi_dout (mi_rx_emmu_dout[]),
.mi_en (mi_rx_emmu_sel),
.emwr_\(.*\) (emaxi_emwr_\1[]),
.emrq_\(.*\) (emaxi_emrq_\1[]),
.emrr_\(.*\) (esaxi_emrr_\1[]),
);
*/
erx erx(
/*AUTOINST*/
// Outputs
.ecfg_rx_debug (ecfg_rx_debug[15:0]),
.ecfg_rx_datain (ecfg_rx_datain[8:0]),
.mi_dout (mi_rx_emmu_dout[31:0]), // Templated
.emwr_access (emaxi_emwr_access), // Templated
.emwr_write (emaxi_emwr_write), // Templated
.emwr_datamode (emaxi_emwr_datamode[1:0]), // Templated
.emwr_ctrlmode (emaxi_emwr_ctrlmode[3:0]), // Templated
.emwr_dstaddr (emaxi_emwr_dstaddr[31:0]), // Templated
.emwr_data (emaxi_emwr_data[31:0]), // Templated
.emwr_srcaddr (emaxi_emwr_srcaddr[31:0]), // Templated
.emrq_access (emaxi_emrq_access), // Templated
.emrq_write (emaxi_emrq_write), // Templated
.emrq_datamode (emaxi_emrq_datamode[1:0]), // Templated
.emrq_ctrlmode (emaxi_emrq_ctrlmode[3:0]), // Templated
.emrq_dstaddr (emaxi_emrq_dstaddr[31:0]), // Templated
.emrq_data (emaxi_emrq_data[31:0]), // Templated
.emrq_srcaddr (emaxi_emrq_srcaddr[31:0]), // Templated
.emrr_access (esaxi_emrr_access), // Templated
.emrr_data (esaxi_emrr_data[31:0]), // Templated
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
// Inputs
.reset (reset),
.s_axi_aclk (s_axi_aclk),
.m_axi_aclk (m_axi_aclk),
.ecfg_rx_enable (ecfg_rx_enable),
.ecfg_rx_mmu_enable (ecfg_rx_mmu_enable),
.ecfg_rx_gpio_enable (ecfg_rx_gpio_enable),
.ecfg_dataout (ecfg_dataout[1:0]),
.mi_clk (mi_clk),
.mi_en (mi_rx_emmu_sel), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[15:0]),
.mi_din (mi_din[31:0]),
.emwr_rd_en (emaxi_emwr_rd_en), // Templated
.emrq_rd_en (emaxi_emrq_rd_en), // Templated
.emrr_rd_en (esaxi_emrr_rd_en), // Templated
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]));
/***********************************************************/
/*TRANSMITTER */
/***********************************************************/
/*etx AUTO_TEMPLATE (
.mi_dout (mi_tx_emmu_dout[]),
.mi_en (mi_tx_emmu_sel),
.emwr_\(.*\) (esaxi_emwr_\1[]),
.emrq_\(.*\) (esaxi_emrq_\1[]),
.emrr_\(.*\) (emaxi_emrr_\1[]),
);
*/
etx etx(
/*AUTOINST*/
// Outputs
.ecfg_tx_datain (ecfg_tx_datain[1:0]),
.ecfg_tx_debug (ecfg_tx_debug[15:0]),
.emrq_progfull (esaxi_emrq_progfull), // Templated
.emwr_progfull (esaxi_emwr_progfull), // Templated
.emrr_progfull (emaxi_emrr_progfull), // Templated
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.mi_dout (mi_tx_emmu_dout[31:0]), // Templated
// Inputs
.reset (reset),
.tx_lclk (tx_lclk),
.tx_lclk_out (tx_lclk_out),
.tx_lclk_par (tx_lclk_par),
.s_axi_aclk (s_axi_aclk),
.m_axi_aclk (m_axi_aclk),
.ecfg_tx_enable (ecfg_tx_enable),
.ecfg_tx_gpio_enable (ecfg_tx_gpio_enable),
.ecfg_tx_mmu_enable (ecfg_tx_mmu_enable),
.ecfg_dataout (ecfg_dataout[8:0]),
.emrq_access (esaxi_emrq_access), // Templated
.emrq_write (esaxi_emrq_write), // Templated
.emrq_datamode (esaxi_emrq_datamode[1:0]), // Templated
.emrq_ctrlmode (esaxi_emrq_ctrlmode[3:0]), // Templated
.emrq_dstaddr (esaxi_emrq_dstaddr[31:0]), // Templated
.emrq_data (esaxi_emrq_data[31:0]), // Templated
.emrq_srcaddr (esaxi_emrq_srcaddr[31:0]), // Templated
.emwr_access (esaxi_emwr_access), // Templated
.emwr_write (esaxi_emwr_write), // Templated
.emwr_datamode (esaxi_emwr_datamode[1:0]), // Templated
.emwr_ctrlmode (esaxi_emwr_ctrlmode[3:0]), // Templated
.emwr_dstaddr (esaxi_emwr_dstaddr[31:0]), // Templated
.emwr_data (esaxi_emwr_data[31:0]), // Templated
.emwr_srcaddr (esaxi_emwr_srcaddr[31:0]), // Templated
.emrr_access (emaxi_emrr_access), // Templated
.emrr_write (emaxi_emrr_write), // Templated
.emrr_datamode (emaxi_emrr_datamode[1:0]), // Templated
.emrr_ctrlmode (emaxi_emrr_ctrlmode[3:0]), // Templated
.emrr_dstaddr (emaxi_emrr_dstaddr[31:0]), // Templated
.emrr_data (emaxi_emrr_data[31:0]), // Templated
.emrr_srcaddr (emaxi_emrr_srcaddr[31:0]), // Templated
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.mi_clk (mi_clk),
.mi_en (mi_tx_emmu_sel), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[15:0]),
.mi_din (mi_din[31:0]));
/***********************************************************/
/*ELINK CONFIGURATION REGISTERES */
/***********************************************************/
/*ecfg AUTO_TEMPLATE (
.mi_dout (mi_ecfg_dout[]),
.mi_en (mi_ecfg_sel),
.ecfg_reset (reset),
.clk (mi_clk),
);
*/
ecfg ecfg(
/*AUTOINST*/
// Outputs
.soft_reset (soft_reset),
.mi_dout (mi_ecfg_dout[31:0]), // Templated
.ecfg_tx_enable (ecfg_tx_enable),
.ecfg_tx_mmu_enable (ecfg_tx_mmu_enable),
.ecfg_tx_gpio_enable (ecfg_tx_gpio_enable),
.ecfg_tx_ctrlmode (ecfg_tx_ctrlmode[3:0]),
.ecfg_timeout_enable (ecfg_timeout_enable),
.ecfg_rx_enable (ecfg_rx_enable),
.ecfg_rx_mmu_enable (ecfg_rx_mmu_enable),
.ecfg_rx_gpio_enable (ecfg_rx_gpio_enable),
.ecfg_clk_settings (ecfg_clk_settings[15:0]),
.ecfg_coreid (ecfg_coreid[11:0]),
.ecfg_dataout (ecfg_dataout[10:0]),
// Inputs
.hard_reset (hard_reset),
.mi_clk (mi_clk),
.mi_en (mi_ecfg_sel), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[31:0]),
.ecfg_rx_datain (ecfg_rx_datain[8:0]),
.ecfg_tx_datain (ecfg_tx_datain[1:0]),
.embox_not_empty (embox_not_empty),
.embox_full (embox_full),
.ecfg_tx_debug (ecfg_tx_debug[15:0]),
.ecfg_rx_debug (ecfg_rx_debug[15:0]));
/***********************************************************/
/*GENERAL PURPOSE MAILBOX */
/***********************************************************/
/*embox AUTO_TEMPLATE (
.mi_dout (mi_embox_dout[]),
.mi_en (mi_embox_sel),
);
*/
embox embox(.clk (s_axi_aclk),
/*AUTOINST*/
// Outputs
.mi_dout (mi_embox_dout[DW-1:0]), // Templated
.embox_full (embox_full),
.embox_not_empty (embox_not_empty),
// Inputs
.reset (reset),
.mi_en (mi_embox_sel), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[DW-1:0]));
/***********************************************************/
/*RESET CIRCUITRY */
/***********************************************************/
ereset ereset (/*AUTOINST*/
// Outputs
.reset (reset),
.chip_resetb (chip_resetb),
// Inputs
.hard_reset (hard_reset),
.soft_reset (soft_reset));
/***********************************************************/
/*CLOCKS */
/***********************************************************/
eclocks eclocks (
/*AUTOINST*/
// Outputs
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.tx_lclk (tx_lclk),
.tx_lclk_out (tx_lclk_out),
.tx_lclk_par (tx_lclk_par),
// Inputs
.clkin (clkin),
.hard_reset (hard_reset),
.ecfg_clk_settings (ecfg_clk_settings[15:0]),
.clkbypass (clkbypass[2:0]));
endmodule
|
module data_sampler_fifo_tb
#(
parameter DIN_WIDTH = 512,
parameter DOUT_WIDTH = 32
)
();
reg reset;
reg clk;
reg trig;
reg [DIN_WIDTH-1:0] din;
reg din_valid, din_clk;
wire [DOUT_WIDTH-1:0] dout;
wire dout_empty;
reg dout_rden;
data_sampler_fifo
#(
.DIN_WIDTH(DIN_WIDTH),
.DOUT_WIDTH(DOUT_WIDTH)
)
data_sampler_fifo_tb_inst
(
.RESET(reset),
.CLK(clk),
.TRIG(trig),
.DIN(din),
.DIN_VALID(din_valid),
.DIN_CLK(din_clk),
.DOUT(dout),
.DOUT_EMPTY(dout_empty),
.DOUT_RDEN(dout_rden)
);
//initial begin
//$dumpfile("a.vcd");
//$dumpvars(0, x);
//end
initial begin
clk = 0;
din_clk = 0;
reset = 0;
#16 reset = 1;
#36 reset = 0;
end
always #10 clk = ~clk;
always #5 din_clk = ~din_clk;
initial begin
din_valid = 0;
dout_rden = 0;
end
initial begin
trig = 0;
#180 trig <= 1;
#20 trig <= 0;
#212 trig <= 1;
#100 trig <= 0;
#212 trig <= 1;
#100 trig <= 0;
end
endmodule
|
module sky130_fd_sc_ms__fill_diode_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__fill_diode_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fill_diode base ();
endmodule
|
module can receive pkt
exe_dfifo_rd <= 1'b1;
rule_fifo_rd <= 1'b1;
exe_state <= METADATA_S;
end
else begin
exe_dfifo_rd <= 1'b0;
rule_fifo_rd <= 1'b0;
exe_state <= IDLE_S;
end
end
METADATA_S: begin
rule_fifo_rd <= 1'b0;
case(rule_fifo_rdata[31:28])
4'd1: begin//1 trans to CPU with thread id assignd by user
exe2disp_data_wr <= 1'b1;
exe2disp_data[133:56] <= exe_dfifo_rdata[133:56];
exe2disp_data[55:47] <= {1'b0,rule_fifo_rdata[7:0]};
exe2disp_data[46:0] <= exe_dfifo_rdata[46:0];
exe_state <= TRANS_S;
end
4'd2: begin//2 trans to CPU with polling thread id
exe2disp_data_wr <= 1'b1;
exe2disp_data[133:56] <= exe_dfifo_rdata[133:56];
exe2disp_data[55:47] <= {3'b0,polling_cpuid};
exe2disp_data[46:0] <= exe_dfifo_rdata[46:0];
if((polling_cpuid+6'b1) < sys_max_cpuid) begin
//if use sys_max_cpuid -1,maybe underflow
polling_cpuid <= polling_cpuid + 6'd1;
end
else begin
polling_cpuid <= 6'b0;
end
exe_state <= TRANS_S;
end
4'd3: begin//3 trans to port
exe2disp_data_wr <= 1'b1;
//modify by lxj 20161011 start
exe2disp_data[133:113] <= exe_dfifo_rdata[133:113];
exe2disp_data[109:74] <= exe_dfifo_rdata[109:74];
if(rule_fifo_rdata[7:4] == 4'b0) begin//slot0
exe2disp_data[112:110] <= 3'b0;
exe2disp_data[73:64] <= {6'b0,rule_fifo_rdata[3:0]};
end
else begin//slot1
exe2disp_data[112:110] <= 3'b1;
exe2disp_data[73:64] <= {6'b0,rule_fifo_rdata[7:4]};
end
//modify by lxj 20161011 end
//exe2disp_data[73:64] <= {2'b0,rule_fifo_rdata[7:0]};
exe2disp_data[63:0] <= exe_dfifo_rdata[63:0];
exe_state <= TRANS_S;
end
default: begin//discard
exe2disp_data_wr <= 1'b0;
exe_state <= DISCARD_S;
end
endcase
end
TRANS_S: begin
exe2disp_data_wr <= 1'b1;
exe2disp_data <= exe_dfifo_rdata;
if(exe_dfifo_rdata[133:132] == 2'b10) begin//end of pkt
exe_dfifo_rd <= 1'b0;
exe2disp_valid_wr <= 1'b1;
exe_state <= IDLE_S;
end
else begin
exe_dfifo_rd <= 1'b1;
exe2disp_valid_wr <= 1'b0;
exe_state <= TRANS_S;
end
end
DISCARD_S: begin
rule_fifo_rd <= 1'b0;
exe2disp_data_wr <= 1'b0;
if(exe_dfifo_rdata[133:132] == 2'b10) begin//end of pkt
exe_dfifo_rd <= 1'b0;
exe_state <= IDLE_S;
end
else begin
exe_dfifo_rd <= 1'b1;
exe_state <= DISCARD_S;
end
end
default: begin
exe_dfifo_rd <= 1'b0;
rule_fifo_rd <= 1'b0;
exe2disp_data_wr <= 1'b0;
exe2disp_valid_wr <= 1'b0;
polling_cpuid <= 6'b0;
exe_state <= IDLE_S;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
rule_fifo_rd_dly <= 1'b0;
end
else begin
rule_fifo_rd_dly <= rule_fifo_rd;
end
end
//***************************************************
// Other IP Instance
//***************************************************
//likely fifo/ram/async block....
//should be instantiated below here
fifo_256_134 exe_dfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(parser2exe_data_wr),
.data(parser2exe_data),
.rdreq(exe_dfifo_rd),
.q(exe_dfifo_rdata),
.usedw(exe_dfifo_usedw)
);
rulefifo_64_32 rule_fifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(lookup2exe_rule_wr),
.data(lookup2exe_rule),
.rdreq(rule_fifo_rd_dly),
.q(rule_fifo_rdata),
.empty(rule_fifo_empty)
);
endmodule
|
module sky130_fd_sc_hd__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module Debouncer_tb;
reg CLK;
reg IN;
wire OUT;
Debouncer db_tb(
.CLK(CLK),
.IN(IN),
.OUT(OUT)
);
always begin
#50 CLK = ~CLK;
end
initial begin
CLK=0;
IN = 1;
$display("==================================//\\\\==================================");
$display("| Testbench Modulo Debouncer: Clock = 100ns |");
$display("==================================\\\\//==================================");
$display("\tTEMPO: %0t // IN estavel sem pressionamento\n", $time);
#400 $display("\tTEMPO: %0t // IN pressionado, gerando bouncing por 100ns\n", $time);
#5 IN = ~IN;
#15 IN = ~IN;
#2 IN = ~IN;
#1 IN = ~IN;
#8 IN = ~IN;
#9 IN = ~IN;
#5 IN = ~IN;
#5 IN = ~IN;
#10 IN = ~IN;
#5 IN = ~IN;
#4 IN = ~IN;
#8 IN = ~IN;
#1 IN = ~IN;
#7 IN = ~IN;
#4 IN = ~IN;
#2 IN = ~IN;
#4 IN = ~IN;
#5 $display("\tTEMPO: %0t // IN estabilizou enquanto pressionado\n", $time);
#500
$display("==================================//\\\\==================================");
$display("| Fim do Testbench |");
$display("==================================\\\\//==================================");
$stop;
end
endmodule
|
module m6502_alu(
input wire [7 : 0] operation,
input wire [7 : 0] op_a,
input wire [7 : 0] op_b,
input wire carry_in,
output wire [7 : 0] result,
output wire carry,
output wire zero,
output wire overflow
);
//----------------------------------------------------------------
// Defines.
//----------------------------------------------------------------
localparam OP_AND = 8'h01;
localparam OP_OR = 8'h02;
localparam OP_XOR = 8'h03;
localparam OP_NOT = 8'h04;
localparam OP_ASL = 8'h11;
localparam OP_ROL = 8'h12;
localparam OP_ASR = 8'h13;
localparam OP_ROR = 8'h14;
localparam OP_ADD = 8'h21;
localparam OP_INC = 8'h22;
localparam OP_SUB = 8'h23;
localparam OP_DEC = 8'h24;
localparam OP_CMP = 8'h31;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [7 : 0] tmp_result;
reg tmp_carry;
reg tmp_zero;
reg tmp_overflow;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign result = tmp_result;
assign carry = tmp_carry;
assign zero = tmp_zero;
assign overflow = tmp_overflow;
//----------------------------------------------------------------
// alu
//
// The actual logic to implement the ALU functions.
//----------------------------------------------------------------
always @*
begin : alu
reg [8 : 0] tmp_add;
tmp_result = 8'h0;
tmp_carry = 0;
tmp_zero = 0;
tmp_overflow = 0;
case (operation)
OP_AND:
begin
tmp_result = op_a & op_b;
end
OP_OR:
begin
tmp_result = op_a | op_b;
end
OP_XOR:
begin
tmp_result = op_a ^ op_b;
end
OP_NOT:
begin
tmp_result = ~op_a;
end
OP_ASL:
begin
tmp_result = {op_a[6 : 0], carry_in};
tmp_carry = op_a[7];
end
OP_ROL:
begin
tmp_result = {op_a[6 : 0], op_a[7]};
end
OP_ASR:
begin
tmp_result = {carry_in, op_a[7 : 1]};
tmp_carry = op_a[0];
end
OP_ROR:
begin
tmp_result = {op_a[0], op_a[7 : 1]};
end
OP_ADD:
begin
tmp_add = op_a + op_b + carry_in;
tmp_result = tmp_add[7 : 0];
tmp_carry = tmp_add[8];
end
OP_INC:
begin
tmp_add = op_a + 1'b1;
tmp_result = tmp_add[7 : 0];
tmp_carry = tmp_add[8];
end
OP_SUB:
begin
tmp_result = op_a - op_b;
if (tmp_result == 8'h00)
tmp_zero = 1;
end
OP_DEC:
begin
tmp_result = op_a - 1'b1;
end
OP_CMP:
begin
if (op_a == op_b)
tmp_zero = 1;
end
default:
begin
end
endcase // case (operation)
end // alu
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
|
module sky130_fd_sc_hd__dlymetal6s4s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
module uart_tx #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
/*
* UART interface
*/
output wire txd,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [15:0] prescale
);
reg input_axis_tready_reg = 0;
reg txd_reg = 1;
reg busy_reg = 0;
reg [DATA_WIDTH:0] data_reg = 0;
reg [18:0] prescale_reg = 0;
reg [3:0] bit_cnt = 0;
assign input_axis_tready = input_axis_tready_reg;
assign txd = txd_reg;
assign busy = busy_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
input_axis_tready_reg <= 0;
txd_reg <= 1;
prescale_reg <= 0;
bit_cnt <= 0;
busy_reg <= 0;
end else begin
if (prescale_reg > 0) begin
input_axis_tready_reg <= 0;
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt == 0) begin
input_axis_tready_reg <= 1;
busy_reg <= 0;
if (input_axis_tvalid) begin
input_axis_tready_reg <= ~input_axis_tready_reg;
prescale_reg <= (prescale << 3)-1;
bit_cnt <= DATA_WIDTH+1;
data_reg <= {1'b1, input_axis_tdata};
txd_reg <= 0;
busy_reg <= 1;
end
end else begin
if (bit_cnt > 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
{data_reg, txd_reg} <= {1'b0, data_reg};
end else if (bit_cnt == 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3);
txd_reg <= 1;
end
end
end
end
endmodule
|
module sky130_fd_sc_hs__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
|
module counter_16bit_tb;
reg clk, reset, enable;
wire [15:0] count;
reg status;
reg [15:0] count_compare;
top DUT (.clk(clk), .reset(reset), .enable(enable), .count(count));
event terminate_sim;
initial begin
@ (terminate_sim);
$display("FAIL");
#5 $fatal;
end
always @ (posedge clk)
if (reset == 1'b1) begin
count_compare <= 0;
end else if ( enable == 1'b1) begin
count_compare <= count_compare + 1;
end
initial begin
clk = 0;
reset = 1;
enable = 0;
#50 reset = 0;
#50 enable = 1;
#10 status = 0;
end
always
#15 clk = !clk;
always @ (posedge clk)
if (count_compare != count) begin
$display ("DUT Error at time %d", $time);
$display (" Expected value %d, Got Value %d", count_compare, count);
status =1;
#5 -> terminate_sim;
end
initial begin
$dumpfile("counter_16bit_tb.vcd");
$dumpvars(0,counter_16bit_tb);
$display("\t\ttime,\tclk,\treset,\tenable,\tcount");
$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,enable,count);
if(status == 1'b0)
$display("PASS");
end
initial
#3000 $finish;
endmodule
|
module system_acl_iface_acl_kernel_clk (
output wire kernel_clk2x_clk, // kernel_clk2x.clk
input wire pll_refclk_clk, // pll_refclk.clk
output wire ctrl_waitrequest, // ctrl.waitrequest
output wire [31:0] ctrl_readdata, // .readdata
output wire ctrl_readdatavalid, // .readdatavalid
input wire [0:0] ctrl_burstcount, // .burstcount
input wire [31:0] ctrl_writedata, // .writedata
input wire [10:0] ctrl_address, // .address
input wire ctrl_write, // .write
input wire ctrl_read, // .read
input wire [3:0] ctrl_byteenable, // .byteenable
input wire ctrl_debugaccess, // .debugaccess
output wire kernel_clk_clk, // kernel_clk.clk
output wire kernel_pll_locked_export, // kernel_pll_locked.export
input wire clk_clk, // clk.clk
input wire reset_reset_n // reset.reset_n
);
wire [63:0] pll_reconfig_0_reconfig_to_pll_reconfig_to_pll; // pll_reconfig_0:reconfig_to_pll -> kernel_pll:reconfig_to_pll
wire [63:0] kernel_pll_reconfig_from_pll_reconfig_from_pll; // kernel_pll:reconfig_from_pll -> pll_reconfig_0:reconfig_from_pll
wire kernel_pll_outclk0_clk; // kernel_pll:outclk_0 -> global_routing_kernel_clk:s
wire kernel_pll_outclk1_clk; // kernel_pll:outclk_1 -> [counter:clk2x, global_routing_kernel_clk2x:s]
wire kernel_pll_locked_export_signal; // kernel_pll:locked -> pll_lock_avs_0:lock
wire [0:0] ctrl_m0_burstcount; // ctrl:m0_burstcount -> mm_interconnect_0:ctrl_m0_burstcount
wire ctrl_m0_waitrequest; // mm_interconnect_0:ctrl_m0_waitrequest -> ctrl:m0_waitrequest
wire [10:0] ctrl_m0_address; // ctrl:m0_address -> mm_interconnect_0:ctrl_m0_address
wire [31:0] ctrl_m0_writedata; // ctrl:m0_writedata -> mm_interconnect_0:ctrl_m0_writedata
wire ctrl_m0_write; // ctrl:m0_write -> mm_interconnect_0:ctrl_m0_write
wire ctrl_m0_read; // ctrl:m0_read -> mm_interconnect_0:ctrl_m0_read
wire [31:0] ctrl_m0_readdata; // mm_interconnect_0:ctrl_m0_readdata -> ctrl:m0_readdata
wire ctrl_m0_debugaccess; // ctrl:m0_debugaccess -> mm_interconnect_0:ctrl_m0_debugaccess
wire [3:0] ctrl_m0_byteenable; // ctrl:m0_byteenable -> mm_interconnect_0:ctrl_m0_byteenable
wire ctrl_m0_readdatavalid; // mm_interconnect_0:ctrl_m0_readdatavalid -> ctrl:m0_readdatavalid
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest; // pll_reconfig_0:mgmt_waitrequest -> mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_waitrequest
wire [31:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_writedata -> pll_reconfig_0:mgmt_writedata
wire [5:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_address -> pll_reconfig_0:mgmt_address
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_write -> pll_reconfig_0:mgmt_write
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_read -> pll_reconfig_0:mgmt_read
wire [31:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata; // pll_reconfig_0:mgmt_readdata -> mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_readdata
wire [31:0] mm_interconnect_0_pll_rom_s1_writedata; // mm_interconnect_0:pll_rom_s1_writedata -> pll_rom:writedata
wire [7:0] mm_interconnect_0_pll_rom_s1_address; // mm_interconnect_0:pll_rom_s1_address -> pll_rom:address
wire mm_interconnect_0_pll_rom_s1_chipselect; // mm_interconnect_0:pll_rom_s1_chipselect -> pll_rom:chipselect
wire mm_interconnect_0_pll_rom_s1_clken; // mm_interconnect_0:pll_rom_s1_clken -> pll_rom:clken
wire mm_interconnect_0_pll_rom_s1_write; // mm_interconnect_0:pll_rom_s1_write -> pll_rom:write
wire [31:0] mm_interconnect_0_pll_rom_s1_readdata; // pll_rom:readdata -> mm_interconnect_0:pll_rom_s1_readdata
wire mm_interconnect_0_pll_rom_s1_debugaccess; // mm_interconnect_0:pll_rom_s1_debugaccess -> pll_rom:debugaccess
wire [3:0] mm_interconnect_0_pll_rom_s1_byteenable; // mm_interconnect_0:pll_rom_s1_byteenable -> pll_rom:byteenable
wire mm_interconnect_0_counter_s_waitrequest; // counter:slave_waitrequest -> mm_interconnect_0:counter_s_waitrequest
wire [31:0] mm_interconnect_0_counter_s_writedata; // mm_interconnect_0:counter_s_writedata -> counter:slave_writedata
wire [1:0] mm_interconnect_0_counter_s_address; // mm_interconnect_0:counter_s_address -> counter:slave_address
wire mm_interconnect_0_counter_s_write; // mm_interconnect_0:counter_s_write -> counter:slave_write
wire mm_interconnect_0_counter_s_read; // mm_interconnect_0:counter_s_read -> counter:slave_read
wire [31:0] mm_interconnect_0_counter_s_readdata; // counter:slave_readdata -> mm_interconnect_0:counter_s_readdata
wire mm_interconnect_0_counter_s_readdatavalid; // counter:slave_readdatavalid -> mm_interconnect_0:counter_s_readdatavalid
wire [3:0] mm_interconnect_0_counter_s_byteenable; // mm_interconnect_0:counter_s_byteenable -> counter:slave_byteenable
wire mm_interconnect_0_pll_sw_reset_s_waitrequest; // pll_sw_reset:slave_waitrequest -> mm_interconnect_0:pll_sw_reset_s_waitrequest
wire [31:0] mm_interconnect_0_pll_sw_reset_s_writedata; // mm_interconnect_0:pll_sw_reset_s_writedata -> pll_sw_reset:slave_writedata
wire mm_interconnect_0_pll_sw_reset_s_write; // mm_interconnect_0:pll_sw_reset_s_write -> pll_sw_reset:slave_write
wire mm_interconnect_0_pll_sw_reset_s_read; // mm_interconnect_0:pll_sw_reset_s_read -> pll_sw_reset:slave_read
wire [31:0] mm_interconnect_0_pll_sw_reset_s_readdata; // pll_sw_reset:slave_readdata -> mm_interconnect_0:pll_sw_reset_s_readdata
wire [3:0] mm_interconnect_0_pll_sw_reset_s_byteenable; // mm_interconnect_0:pll_sw_reset_s_byteenable -> pll_sw_reset:slave_byteenable
wire mm_interconnect_0_pll_lock_avs_0_s_read; // mm_interconnect_0:pll_lock_avs_0_s_read -> pll_lock_avs_0:slave_read
wire [31:0] mm_interconnect_0_pll_lock_avs_0_s_readdata; // pll_lock_avs_0:slave_readdata -> mm_interconnect_0:pll_lock_avs_0_s_readdata
wire mm_interconnect_0_version_id_0_s_read; // mm_interconnect_0:version_id_0_s_read -> version_id_0:slave_read
wire [31:0] mm_interconnect_0_version_id_0_s_readdata; // version_id_0:slave_readdata -> mm_interconnect_0:version_id_0_s_readdata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> kernel_pll:rst
wire pll_sw_reset_sw_reset_reset; // pll_sw_reset:sw_reset_n_out -> rst_controller:reset_in0
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [ctrl:reset, mm_interconnect_0:ctrl_reset_reset_bridge_in_reset_reset, pll_lock_avs_0:resetn, pll_reconfig_0:mgmt_reset, pll_rom:reset, pll_sw_reset:resetn, rst_translator:in_reset, version_id_0:resetn]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [pll_rom:reset_req, rst_translator:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [counter:resetn, mm_interconnect_0:counter_clk_reset_reset_bridge_in_reset_reset]
system_acl_iface_acl_kernel_clk_kernel_pll kernel_pll (
.refclk (pll_refclk_clk), // refclk.clk
.rst (rst_controller_reset_out_reset), // reset.reset
.outclk_0 (kernel_pll_outclk0_clk), // outclk0.clk
.outclk_1 (kernel_pll_outclk1_clk), // outclk1.clk
.locked (kernel_pll_locked_export_signal), // locked.export
.reconfig_to_pll (pll_reconfig_0_reconfig_to_pll_reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (kernel_pll_reconfig_from_pll_reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll
);
altera_pll_reconfig_top #(
.device_family ("Cyclone V"),
.reconf_width (64),
.ENABLE_MIF (0),
.MIF_FILE_NAME ("")
) pll_reconfig_0 (
.mgmt_clk (clk_clk), // mgmt_clk.clk
.mgmt_reset (rst_controller_001_reset_out_reset), // mgmt_reset.reset
.mgmt_readdata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata), // mgmt_avalon_slave.readdata
.mgmt_waitrequest (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.mgmt_read (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read), // .read
.mgmt_write (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write), // .write
.mgmt_address (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address), // .address
.mgmt_writedata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.reconfig_to_pll (pll_reconfig_0_reconfig_to_pll_reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (kernel_pll_reconfig_from_pll_reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll
);
system_acl_iface_acl_kernel_clk_pll_rom pll_rom (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_pll_rom_s1_address), // s1.address
.debugaccess (mm_interconnect_0_pll_rom_s1_debugaccess), // .debugaccess
.clken (mm_interconnect_0_pll_rom_s1_clken), // .clken
.chipselect (mm_interconnect_0_pll_rom_s1_chipselect), // .chipselect
.write (mm_interconnect_0_pll_rom_s1_write), // .write
.readdata (mm_interconnect_0_pll_rom_s1_readdata), // .readdata
.writedata (mm_interconnect_0_pll_rom_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_pll_rom_s1_byteenable), // .byteenable
.reset (rst_controller_001_reset_out_reset), // reset1.reset
.reset_req (rst_controller_001_reset_out_reset_req) // .reset_req
);
timer #(
.WIDTH (32),
.S_WIDTH_A (2)
) counter (
.clk (kernel_clk_clk), // clk.clk
.clk2x (kernel_pll_outclk1_clk), // clk2x.clk
.resetn (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
.slave_address (mm_interconnect_0_counter_s_address), // s.address
.slave_writedata (mm_interconnect_0_counter_s_writedata), // .writedata
.slave_read (mm_interconnect_0_counter_s_read), // .read
.slave_write (mm_interconnect_0_counter_s_write), // .write
.slave_byteenable (mm_interconnect_0_counter_s_byteenable), // .byteenable
.slave_waitrequest (mm_interconnect_0_counter_s_waitrequest), // .waitrequest
.slave_readdata (mm_interconnect_0_counter_s_readdata), // .readdata
.slave_readdatavalid (mm_interconnect_0_counter_s_readdatavalid) // .readdatavalid
);
global_routing global_routing_kernel_clk (
.s (kernel_pll_outclk0_clk), // clk.clk
.g (kernel_clk_clk) // global_clk.clk
);
global_routing global_routing_kernel_clk2x (
.s (kernel_pll_outclk1_clk), // clk.clk
.g (kernel_clk2x_clk) // global_clk.clk
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (11),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (0),
.PIPELINE_RESPONSE (0)
) ctrl (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.s0_waitrequest (ctrl_waitrequest), // s0.waitrequest
.s0_readdata (ctrl_readdata), // .readdata
.s0_readdatavalid (ctrl_readdatavalid), // .readdatavalid
.s0_burstcount (ctrl_burstcount), // .burstcount
.s0_writedata (ctrl_writedata), // .writedata
.s0_address (ctrl_address), // .address
.s0_write (ctrl_write), // .write
.s0_read (ctrl_read), // .read
.s0_byteenable (ctrl_byteenable), // .byteenable
.s0_debugaccess (ctrl_debugaccess), // .debugaccess
.m0_waitrequest (ctrl_m0_waitrequest), // m0.waitrequest
.m0_readdata (ctrl_m0_readdata), // .readdata
.m0_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.m0_burstcount (ctrl_m0_burstcount), // .burstcount
.m0_writedata (ctrl_m0_writedata), // .writedata
.m0_address (ctrl_m0_address), // .address
.m0_write (ctrl_m0_write), // .write
.m0_read (ctrl_m0_read), // .read
.m0_byteenable (ctrl_m0_byteenable), // .byteenable
.m0_debugaccess (ctrl_m0_debugaccess) // .debugaccess
);
sw_reset #(
.WIDTH (32),
.LOG2_RESET_CYCLES (10)
) pll_sw_reset (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_0_pll_sw_reset_s_write), // s.write
.slave_writedata (mm_interconnect_0_pll_sw_reset_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_0_pll_sw_reset_s_byteenable), // .byteenable
.slave_read (mm_interconnect_0_pll_sw_reset_s_read), // .read
.slave_readdata (mm_interconnect_0_pll_sw_reset_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_0_pll_sw_reset_s_waitrequest), // .waitrequest
.sw_reset_n_out (pll_sw_reset_sw_reset_reset) // sw_reset.reset_n
);
pll_lock_avs #(
.WIDTH (32)
) pll_lock_avs_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.lock (kernel_pll_locked_export_signal), // lock.export
.lock_export (kernel_pll_locked_export), // lock_export.export
.slave_read (mm_interconnect_0_pll_lock_avs_0_s_read), // s.read
.slave_readdata (mm_interconnect_0_pll_lock_avs_0_s_readdata) // .readdata
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1598029823)
) version_id_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_0_version_id_0_s_read), // s.read
.slave_readdata (mm_interconnect_0_version_id_0_s_readdata) // .readdata
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.global_routing_kernel_clk_global_clk_clk (kernel_clk_clk), // global_routing_kernel_clk_global_clk.clk
.counter_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // counter_clk_reset_reset_bridge_in_reset.reset
.ctrl_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // ctrl_reset_reset_bridge_in_reset.reset
.ctrl_m0_address (ctrl_m0_address), // ctrl_m0.address
.ctrl_m0_waitrequest (ctrl_m0_waitrequest), // .waitrequest
.ctrl_m0_burstcount (ctrl_m0_burstcount), // .burstcount
.ctrl_m0_byteenable (ctrl_m0_byteenable), // .byteenable
.ctrl_m0_read (ctrl_m0_read), // .read
.ctrl_m0_readdata (ctrl_m0_readdata), // .readdata
.ctrl_m0_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.ctrl_m0_write (ctrl_m0_write), // .write
.ctrl_m0_writedata (ctrl_m0_writedata), // .writedata
.ctrl_m0_debugaccess (ctrl_m0_debugaccess), // .debugaccess
.counter_s_address (mm_interconnect_0_counter_s_address), // counter_s.address
.counter_s_write (mm_interconnect_0_counter_s_write), // .write
.counter_s_read (mm_interconnect_0_counter_s_read), // .read
.counter_s_readdata (mm_interconnect_0_counter_s_readdata), // .readdata
.counter_s_writedata (mm_interconnect_0_counter_s_writedata), // .writedata
.counter_s_byteenable (mm_interconnect_0_counter_s_byteenable), // .byteenable
.counter_s_readdatavalid (mm_interconnect_0_counter_s_readdatavalid), // .readdatavalid
.counter_s_waitrequest (mm_interconnect_0_counter_s_waitrequest), // .waitrequest
.pll_lock_avs_0_s_read (mm_interconnect_0_pll_lock_avs_0_s_read), // pll_lock_avs_0_s.read
.pll_lock_avs_0_s_readdata (mm_interconnect_0_pll_lock_avs_0_s_readdata), // .readdata
.pll_reconfig_0_mgmt_avalon_slave_address (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address), // pll_reconfig_0_mgmt_avalon_slave.address
.pll_reconfig_0_mgmt_avalon_slave_write (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write), // .write
.pll_reconfig_0_mgmt_avalon_slave_read (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read), // .read
.pll_reconfig_0_mgmt_avalon_slave_readdata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata), // .readdata
.pll_reconfig_0_mgmt_avalon_slave_writedata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.pll_reconfig_0_mgmt_avalon_slave_waitrequest (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.pll_rom_s1_address (mm_interconnect_0_pll_rom_s1_address), // pll_rom_s1.address
.pll_rom_s1_write (mm_interconnect_0_pll_rom_s1_write), // .write
.pll_rom_s1_readdata (mm_interconnect_0_pll_rom_s1_readdata), // .readdata
.pll_rom_s1_writedata (mm_interconnect_0_pll_rom_s1_writedata), // .writedata
.pll_rom_s1_byteenable (mm_interconnect_0_pll_rom_s1_byteenable), // .byteenable
.pll_rom_s1_chipselect (mm_interconnect_0_pll_rom_s1_chipselect), // .chipselect
.pll_rom_s1_clken (mm_interconnect_0_pll_rom_s1_clken), // .clken
.pll_rom_s1_debugaccess (mm_interconnect_0_pll_rom_s1_debugaccess), // .debugaccess
.pll_sw_reset_s_write (mm_interconnect_0_pll_sw_reset_s_write), // pll_sw_reset_s.write
.pll_sw_reset_s_read (mm_interconnect_0_pll_sw_reset_s_read), // .read
.pll_sw_reset_s_readdata (mm_interconnect_0_pll_sw_reset_s_readdata), // .readdata
.pll_sw_reset_s_writedata (mm_interconnect_0_pll_sw_reset_s_writedata), // .writedata
.pll_sw_reset_s_byteenable (mm_interconnect_0_pll_sw_reset_s_byteenable), // .byteenable
.pll_sw_reset_s_waitrequest (mm_interconnect_0_pll_sw_reset_s_waitrequest), // .waitrequest
.version_id_0_s_read (mm_interconnect_0_version_id_0_s_read), // version_id_0_s.read
.version_id_0_s_readdata (mm_interconnect_0_version_id_0_s_readdata) // .readdata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~pll_sw_reset_sw_reset_reset), // reset_in0.reset
.reset_in1 (~reset_reset_n), // reset_in1.reset
.clk (pll_refclk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module sky130_fd_sc_ms__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module RegBankP2Sim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] out_0;
wire [7:0] out_1;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`RegBankP2_LD0,8'hBA};
inst_en = 1;
#4 inst = {`RegBankP2_LD1,8'hFE};
inst_en = 1;
#4 inst = {`RegBankP2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`RegBankP2_LD1,8'h87};
inst_en = 0;
#4 inst = {`RegBankP2_LD0,8'hAE};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'hAB};
inst_en = 1;
#4 inst = {`RegBankP2_LD1,8'h27};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`RegBankP2_LD0,8'h1A};
inst_en = 1;
#4 inst = {`RegBankP2_NOP,8'bxxxxxxxx};
inst_en = 1;
end
RegBankP2
rbp2 (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.out_0(out_0),
.out_1(out_1));
endmodule
|
module sky130_fd_sc_hvl__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hvl__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hvl__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
|
module sky130_fd_sc_hs__or4b_2 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__or4b_2 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
|
module ad_ss_422to444 (
// 422 inputs
clk,
s422_de,
s422_sync,
s422_data,
// 444 outputs
s444_sync,
s444_data);
// parameters
parameter Cr_Cb_N = 0;
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// 422 inputs
input clk;
input s422_de;
input [DW:0] s422_sync;
input [15:0] s422_data;
// 444 inputs
output [DW:0] s444_sync;
output [23:0] s444_data;
// internal registers
reg cr_cb_sel = 'd0;
reg s422_de_d = 'd0;
reg [DW:0] s422_sync_d = 'd0;
reg s422_de_2d = 'd0;
reg [7:0] s422_Y_d;
reg [7:0] s422_CbCr_d;
reg [7:0] s422_CbCr_2d;
reg [DW:0] s444_sync = 'd0;
reg [23:0] s444_data = 'd0;
reg [ 8:0] s422_CbCr_avg;
// internal wires
wire [ 7:0] s422_Y;
wire [ 7:0] s422_CbCr;
// Input format is
// [15:8] Cb/Cr
// [ 7:0] Y
//
// Output format is
// [23:15] Cr
// [16: 8] Y
// [ 7: 0] Cb
assign s422_Y = s422_data[7:0];
assign s422_CbCr = s422_data[15:8];
// first data on de assertion is cb (0x0), then cr (0x1).
// previous data is held when not current
always @(posedge clk) begin
if (s422_de_d == 1'b1) begin
cr_cb_sel <= ~cr_cb_sel;
end else begin
cr_cb_sel <= Cr_Cb_N;
end
end
// pipe line stages
always @(posedge clk) begin
s422_de_d <= s422_de;
s422_sync_d <= s422_sync;
s422_de_2d <= s422_de_d;
s422_Y_d <= s422_Y;
s422_CbCr_d <= s422_CbCr;
s422_CbCr_2d <= s422_CbCr_d;
end
// If both the left and the right sample are valid do the average, otherwise
// use the only valid.
always @(s422_de_2d, s422_de, s422_CbCr, s422_CbCr_2d)
begin
if (s422_de == 1'b1 && s422_de_2d)
s422_CbCr_avg <= s422_CbCr + s422_CbCr_2d;
else if (s422_de == 1'b1)
s422_CbCr_avg <= {s422_CbCr, 1'b0};
else
s422_CbCr_avg <= {s422_CbCr_2d, 1'b0};
end
// 444 outputs
always @(posedge clk) begin
s444_sync <= s422_sync_d;
s444_data[15:8] <= s422_Y_d;
if (cr_cb_sel) begin
s444_data[23:16] <= s422_CbCr_d;
s444_data[ 7: 0] <= s422_CbCr_avg[8:1];
end else begin
s444_data[23:16] <= s422_CbCr_avg[8:1];
s444_data[ 7: 0] <= s422_CbCr_d;
end
end
endmodule
|
module sky130_fd_sc_ls__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_lp__or3_lp (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__or3_lp (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
|
module net2pci_dma_512x32 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [31:0] data;
input rdreq;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [31:0] q;
output [8:0] usedw;
endmodule
|
module meganode_tb();
wire clk_20;
sim_clk #(20) sim_clk_20_inst(.clk(clk_20));
wire clk_25;
sim_clk #(25) sim_clk_25_inst(.clk(clk_25));
wire clk_50;
sim_clk #(50) sim_clk_50_inst(.clk(clk_50));
wire clk_48;
sim_clk #(48) sim_clk_48_inst(.clk(clk_48));
wire clk_100;
sim_clk #(100) sim_clk_100_inst(.clk(clk_100));
wire enet_rst, enet_mdc, enet_mdio;
wire [3:0] enet_leds;
wire [1:0] enet_txclk, enet_txen, enet_rxclk, enet_rxdv;
wire [3:0] enet_txd, enet_rxd;
wire [4:0] usb_oe, usb_rcv, usb_pwr, usb_vp, usb_vm;
wire [15:0] outb;
wire [2:0] mosfet_hi, mosfet_lo, mclk;
reg [2:0] mdata;
wire mosfet_en;
wire mcu_io;
wire mcu_spim_cs, mcu_spim_sclk, mcu_spim_mosi, mcu_spim_miso;
wire mcu_spis_cs, mcu_spis_sclk, mcu_spis_mosi, mcu_spis_miso;
wire led;
localparam W = 8;
reg [W-1:0] master_txd;
wire [W-1:0] master_rxd;
reg master_txdv;
wire master_rxdv;
wire master_done, master_busy;
spi_master #(.SCLK_DIV(50), .W(8)) spi_master_inst
(.c(clk_100), .busy(master_busy), .done(master_done),
.txd(master_txd), .txdv(master_txdv),
.rxd(master_rxd), .rxdv(master_rxdv),
.cs(mcu_spis_cs), .sclk(mcu_spis_sclk),
.mosi(mcu_spis_mosi), .miso(mcu_spis_miso));
initial begin
master_txd = 8'ha5;
master_txdv = 0;
#100
@(posedge clk_100);
#1 master_txdv = 1;
@(posedge clk_100);
#1 master_txd = 8'h7;
@(posedge clk_100);
#1 master_txd = 8'h51;
@(posedge clk_100);
#1 master_txdv = 0;
#50000
@(posedge clk_100);
#1 master_txdv = 1;
@(posedge clk_100);
#1 master_txd = 8'h8;
@(posedge clk_100);
#1 master_txd = 8'h52;
@(posedge clk_100);
#1 master_txdv = 0;
end
meganode meganode_inst(.*);
initial begin
$dumpfile("meganode.lxt");
$dumpvars();
#1_000_000 $finish();
//#150000 $finish();
end
fake_rmii_phy #(.INPUT_FILE_NAME("tb_packets.dat")) sim_rmii_phy_0
(.refclk(clk_50), .mdc(enet_mdc), .mdio(enet_mdio),
.txd(enet_txd[1:0]), .txen(enet_txen[0]),
.rxd(enet_rxd[1:0]), .rxdv(enet_rxdv[0]),
.rst(1'b1));
fake_rmii_phy #(.INPUT_FILE_NAME("tb_packets.dat")) sim_rmii_phy_1
(.refclk(clk_50), .mdc(enet_mdc), .mdio(enet_mdio),
.txd(enet_txd[3:2]), .txen(enet_txen[1]),
.rxd(enet_rxd[3:2]), .rxdv(enet_rxdv[1]),
.rst(1'b1));
wire [4:0] usb_dp, usb_dm;
sim_fsusb_phy sim_usb_phy[4:0]
(.vp(usb_vp), .vm(usb_vm), .oe_n(usb_oe), .pwr(usb_pwr),
.dp(usb_dp), .dm(usb_dm));
sim_fsusb_encoder sim_enc[2:0]
(.dp(usb_dp[2:0]), .dm(usb_dm[2:0]));
sim_fsusb_foot sim_foot
(.dp(usb_dp[3]), .dm(usb_dm[3]));
integer i;
reg [2:0] all_bits [999:0];
initial begin
$readmemh("sigma_delta_test_data.txt", all_bits, 0, 999);
mdata = 3'b0;
for (i = 0; i < 1000; i = i + 1) begin
wait(mclk[0]);
wait(~mclk[0]);
mdata = all_bits[i]; //{3{all_bits[i][0]}};
end
end
endmodule
|
module sky130_fd_sc_ls__a211oi (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module ctrl_reg_readback #(parameter CR_WIDTH=6, N_CTRL_REGS=64) (
input clk,
input rst,
input tx_en,
input tx_data_loaded,
output reg tx_data_ready,
output reg tx_complete,
output reg [CR_WIDTH-1:0] tx_cnt
);
// Readback logic. This works as the DAQ RAM readback. Each ctrl reg is
// stepped trhough in turn, with its data presented until transmitted by the uart
always @(posedge clk) begin
if (rst) begin
tx_cnt <= 0;
tx_data_ready <= 0;
tx_complete <= 0;
end else begin
//tx_data_loaded is asserted by the UART once it has loaded the current
//data word. Since the UART operates on the baud clock domain, synchronise
if (!tx_complete && tx_en) begin //Transmission of RAM contents enabled
if (tx_data_ready && tx_data_loaded) begin //Data word has been loaded to the uart. tx_data_loaded will stay high until the UART transmission has finished
tx_data_ready <= 0;
if (tx_cnt == N_CTRL_REGS-1) begin //We have transmitted the data from the last address
tx_complete <= 1;
tx_cnt <= tx_cnt;
end
else begin
tx_complete <= tx_complete;
tx_cnt <= tx_cnt + 1;
end
end
else begin
tx_complete <= tx_complete;
tx_cnt <= tx_cnt;
tx_data_ready <= (!tx_data_ready && !tx_data_loaded) ? 1 : tx_data_ready; //Load the data from RAM address currently specified by tx_cnt
end
end else if (tx_complete && !tx_en) begin //Transmission is complete. Wait for enable to go low, then reset tx logic
tx_cnt <= 0;
tx_data_ready <= 0;
tx_complete <= 0;
end else begin
tx_data_ready <= tx_data_ready;
tx_complete <= tx_complete;
tx_cnt <= tx_cnt;
end
end // if (~rst)
end //always
endmodule
|
module sky130_fd_sc_ms__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
|
module wb_test_dma_mem #(
parameter ADDR_WIDTH = 10,
parameter READ_FIFO_SIZE = 8,
parameter WRITE_FIFO_SIZE = 8,
parameter ENABLE_ERROR_CHECK = 1,
parameter INITIALIZE_MEM = 1
)(
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
//Write Side
input i_write_enable,
input [63:0] i_write_addr,
input i_write_addr_inc,
input i_write_addr_dec,
output o_write_finished,
input [23:0] i_write_count,
input i_write_flush,
output [1:0] o_write_ready,
input [1:0] i_write_activate,
output [23:0] o_write_size,
input i_write_strobe,
input [31:0] i_write_data,
//Read Side
input i_read_enable,
input [63:0] i_read_addr,
input i_read_addr_inc,
input i_read_addr_dec,
output o_read_busy,
output o_read_error,
input [23:0] i_read_count,
input i_read_flush,
output o_read_ready,
input i_read_activate,
output [23:0] o_read_size,
output [31:0] o_read_data,
input i_read_strobe
);
localparam SLEEP_COUNT = 4;
//Registers/Wires
reg [3:0] ram_sleep;
reg bram_en;
reg [ADDR_WIDTH - 1:0] bram_addr;
reg [31:0] bram_write_data;
wire [31:0] bram_read_data;
//Sub Modules
test_mem_dev #(
.READ_FIFO_SIZE (READ_FIFO_SIZE ),
.WRITE_FIFO_SIZE (WRITE_FIFO_SIZE ),
.ADDRESS_WIDTH (ADDR_WIDTH ),
.ENABLE_ERROR_CHECK (ENABLE_ERROR_CHECK ),
.INITIALIZE_MEM (INITIALIZE_MEM )
)tmd(
.clk (clk ),
.rst (rst ),
//BRAM
.bram_en (bram_en ),
.bram_we (i_wbs_we ),
.bram_address (bram_addr ),
.bram_data_in (bram_write_data ),
.bram_data_out (bram_read_data ),
.write_enable (i_write_enable ),
.write_addr (i_write_addr ),
.write_addr_inc (i_write_addr_inc ),
.write_addr_dec (i_write_addr_dec ),
.write_finished (o_write_finished ),
.write_count (i_write_count ),
.write_flush (i_write_flush ),
.write_ready (o_write_ready ),
.write_activate (i_write_activate ),
.write_size (o_write_size ),
.write_strobe (i_write_strobe ),
.write_data (i_write_data ),
.read_enable (i_read_enable ),
.read_addr (i_read_addr ),
.read_addr_inc (i_read_addr_inc ),
.read_addr_dec (i_read_addr_dec ),
.read_busy (o_read_busy ),
.read_error (o_read_error ),
.read_count (i_read_count ),
.read_flush (i_read_flush ),
.read_ready (o_read_ready ),
.read_activate (i_read_activate ),
.read_size (o_read_size ),
.read_data (o_read_data ),
.read_strobe (i_read_strobe )
);
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
ram_sleep <= SLEEP_COUNT;
bram_en <= 0;
bram_addr <= 0;
bram_write_data <= 0;
end
else begin
bram_en <= 0;
if (o_wbs_ack & ~i_wbs_stb)begin
//when the master acks our ack, then put our ack down
o_wbs_ack <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
bram_en <= 1;
bram_addr <= i_wbs_adr[ADDR_WIDTH - 1:0];
if (i_wbs_we) begin
//write request
bram_write_data <= i_wbs_dat;
end
else begin
//read request
o_wbs_dat <= bram_read_data;
end
if (ram_sleep > 0) begin
ram_sleep <= ram_sleep - 1;
end
else begin
o_wbs_ack <= 1;
ram_sleep <= SLEEP_COUNT;
end
end
end
end
endmodule
|
module system_rgb888_to_rgb565_0_0(rgb_888, rgb_565)
/* synthesis syn_black_box black_box_pad_pin="rgb_888[23:0],rgb_565[15:0]" */;
input [23:0]rgb_888;
output [15:0]rgb_565;
endmodule
|
module assert_unchange_assert (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on_new_start, error_on_new_start, xzcheck_enable);
parameter width = 8;
parameter num_cks = 2;
input clk, reset_n, start_event, window, ignore_new_start, reset_on_new_start, error_on_new_start;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
|
module assert_unchange_assume (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on_new_start, error_on_new_start, xzcheck_enable);
parameter width = 8;
parameter num_cks = 2;
input clk, reset_n, start_event, window, ignore_new_start, reset_on_new_start, error_on_new_start;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
|
module assert_unchange_cover (clk, reset_n, start_event, window, reset_on_new_start, window_close);
parameter OVL_COVER_BASIC_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n, start_event, window, reset_on_new_start, window_close;
endmodule
|
module system_axi_uartlite_0_0
(s_axi_aclk,
s_axi_aresetn,
interrupt,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
rx,
tx);
(* x_interface_info = "xilinx.com:signal:clock:1.0 ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT" *) output interrupt;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [3:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [3:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:uart:1.0 UART RxD" *) input rx;
(* x_interface_info = "xilinx.com:interface:uart:1.0 UART TxD" *) output tx;
wire interrupt;
wire rx;
wire s_axi_aclk;
wire [3:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [3:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire tx;
(* C_BAUDRATE = "9600" *)
(* C_DATA_BITS = "8" *)
(* C_FAMILY = "artix7" *)
(* C_ODD_PARITY = "0" *)
(* C_S_AXI_ACLK_FREQ_HZ = "100000000" *)
(* C_S_AXI_ADDR_WIDTH = "4" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_USE_PARITY = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
system_axi_uartlite_0_0_axi_uartlite U0
(.interrupt(interrupt),
.rx(rx),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.tx(tx));
endmodule
|
module system_axi_uartlite_0_0_address_decoder
(tx_Buffer_Empty_Pre_reg,
\s_axi_rresp_i_reg[1] ,
enable_interrupts_reg,
ip2bus_error,
fifo_wr,
\INFERRED_GEN.cnt_i_reg[2] ,
D,
\INFERRED_GEN.cnt_i_reg[2]_0 ,
\state_reg[1] ,
s_axi_arready,
FIFO_Full_reg,
reset_TX_FIFO,
reset_RX_FIFO,
s_axi_awready,
bus2ip_rdce,
enable_interrupts_reg_0,
tx_Buffer_Empty_Pre_reg_0,
s_axi_rvalid_i_reg,
s_axi_bvalid_i_reg,
\s_axi_bresp_i_reg[1] ,
rx_Data_Present_Pre_reg,
start2,
s_axi_aclk,
tx_Buffer_Full,
Q,
out,
rx_Buffer_Full,
\INFERRED_GEN.cnt_i_reg[4] ,
enable_interrupts,
status_reg,
\state_reg[1]_0 ,
\state_reg[1]_1 ,
s_axi_wvalid,
s_axi_arvalid,
s_axi_wdata,
\state_reg[0] ,
s_axi_aresetn,
s_axi_rready,
s_axi_rvalid_i_reg_0,
s_axi_bready,
s_axi_bvalid_i_reg_0,
s_axi_bresp,
bus2ip_rnw_i,
\bus2ip_addr_i_reg[3] ,
\bus2ip_addr_i_reg[2] );
output tx_Buffer_Empty_Pre_reg;
output \s_axi_rresp_i_reg[1] ;
output enable_interrupts_reg;
output ip2bus_error;
output fifo_wr;
output \INFERRED_GEN.cnt_i_reg[2] ;
output [7:0]D;
output \INFERRED_GEN.cnt_i_reg[2]_0 ;
output [1:0]\state_reg[1] ;
output s_axi_arready;
output FIFO_Full_reg;
output reset_TX_FIFO;
output reset_RX_FIFO;
output s_axi_awready;
output [0:0]bus2ip_rdce;
output enable_interrupts_reg_0;
output tx_Buffer_Empty_Pre_reg_0;
output s_axi_rvalid_i_reg;
output s_axi_bvalid_i_reg;
output \s_axi_bresp_i_reg[1] ;
output rx_Data_Present_Pre_reg;
input start2;
input s_axi_aclk;
input tx_Buffer_Full;
input [0:0]Q;
input [7:0]out;
input rx_Buffer_Full;
input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
input enable_interrupts;
input [1:0]status_reg;
input \state_reg[1]_0 ;
input [1:0]\state_reg[1]_1 ;
input s_axi_wvalid;
input s_axi_arvalid;
input [2:0]s_axi_wdata;
input \state_reg[0] ;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_rvalid_i_reg_0;
input s_axi_bready;
input s_axi_bvalid_i_reg_0;
input [0:0]s_axi_bresp;
input bus2ip_rnw_i;
input \bus2ip_addr_i_reg[3] ;
input \bus2ip_addr_i_reg[2] ;
wire Bus_RNW_reg_i_1_n_0;
wire [7:0]D;
wire FIFO_Full_reg;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \INFERRED_GEN.cnt_i_reg[2] ;
wire \INFERRED_GEN.cnt_i_reg[2]_0 ;
wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
wire [0:0]Q;
wire \bus2ip_addr_i_reg[2] ;
wire \bus2ip_addr_i_reg[3] ;
wire [0:0]bus2ip_rdce;
wire bus2ip_rnw_i;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire cs_ce_clr;
wire enable_interrupts;
wire enable_interrupts_reg;
wire enable_interrupts_reg_0;
wire fifo_wr;
wire ip2bus_error;
wire [7:0]out;
wire reset_RX_FIFO;
wire reset_TX_FIFO;
wire rx_Buffer_Full;
wire rx_Data_Present_Pre_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire s_axi_awready;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire \s_axi_bresp_i_reg[1] ;
wire s_axi_bvalid_i_reg;
wire s_axi_bvalid_i_reg_0;
wire s_axi_rready;
wire \s_axi_rresp_i_reg[1] ;
wire s_axi_rvalid_i_reg;
wire s_axi_rvalid_i_reg_0;
wire [2:0]s_axi_wdata;
wire s_axi_wvalid;
wire start2;
wire \state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_0 ;
wire [1:0]\state_reg[1]_1 ;
wire [1:0]status_reg;
wire tx_Buffer_Empty_Pre_reg;
wire tx_Buffer_Empty_Pre_reg_0;
wire tx_Buffer_Full;
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i),
.I1(start2),
.I2(enable_interrupts_reg),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(enable_interrupts_reg),
.R(1'b0));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(start2),
.D(ce_expnd_i_3),
.Q(\s_axi_rresp_i_reg[1] ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h08))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(start2),
.I1(\bus2ip_addr_i_reg[2] ),
.I2(\bus2ip_addr_i_reg[3] ),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(start2),
.D(ce_expnd_i_2),
.Q(tx_Buffer_Empty_Pre_reg),
.R(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(start2),
.D(ce_expnd_i_1),
.Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'hFFFEFFFF))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I1(tx_Buffer_Empty_Pre_reg),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(\s_axi_rresp_i_reg[1] ),
.I4(s_axi_aresetn),
.O(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h80))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(\bus2ip_addr_i_reg[3] ),
.I1(start2),
.I2(\bus2ip_addr_i_reg[2] ),
.O(ce_expnd_i_0));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi_aclk),
.CE(start2),
.D(ce_expnd_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF7))
\INFERRED_GEN.cnt_i[3]_i_2
(.I0(enable_interrupts_reg),
.I1(\s_axi_rresp_i_reg[1] ),
.I2(Q),
.O(\INFERRED_GEN.cnt_i_reg[2]_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h7))
\INFERRED_GEN.cnt_i[4]_i_3
(.I0(\s_axi_rresp_i_reg[1] ),
.I1(enable_interrupts_reg),
.O(FIFO_Full_reg));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hFD))
\INFERRED_GEN.cnt_i[4]_i_5
(.I0(tx_Buffer_Empty_Pre_reg),
.I1(enable_interrupts_reg),
.I2(tx_Buffer_Full),
.O(\INFERRED_GEN.cnt_i_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h10))
\INFERRED_GEN.data_reg[15][0]_srl16_i_1
(.I0(tx_Buffer_Full),
.I1(enable_interrupts_reg),
.I2(tx_Buffer_Empty_Pre_reg),
.O(fifo_wr));
system_axi_uartlite_0_0_pselect_f \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.\bus2ip_addr_i_reg[2] (\bus2ip_addr_i_reg[2] ),
.\bus2ip_addr_i_reg[3] (\bus2ip_addr_i_reg[3] ),
.ce_expnd_i_3(ce_expnd_i_3),
.start2(start2));
system_axi_uartlite_0_0_pselect_f__parameterized1 \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.\bus2ip_addr_i_reg[2] (\bus2ip_addr_i_reg[2] ),
.\bus2ip_addr_i_reg[3] (\bus2ip_addr_i_reg[3] ),
.ce_expnd_i_1(ce_expnd_i_1),
.start2(start2));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h8))
clr_Status_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I1(enable_interrupts_reg),
.O(bus2ip_rdce));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hFB08))
enable_interrupts_i_1
(.I0(s_axi_wdata[2]),
.I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I2(enable_interrupts_reg),
.I3(enable_interrupts),
.O(enable_interrupts_reg_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h40))
reset_RX_FIFO_i_1
(.I0(enable_interrupts_reg),
.I1(s_axi_wdata[1]),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.O(reset_RX_FIFO));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h40))
reset_TX_FIFO_i_1
(.I0(enable_interrupts_reg),
.I1(s_axi_wdata[0]),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.O(reset_TX_FIFO));
LUT4 #(
.INIT(16'h002A))
rx_Data_Present_Pre_i_1
(.I0(s_axi_aresetn),
.I1(\s_axi_rresp_i_reg[1] ),
.I2(enable_interrupts_reg),
.I3(Q),
.O(rx_Data_Present_Pre_reg));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hF0F0F0E0))
s_axi_arready_INST_0
(.I0(\s_axi_rresp_i_reg[1] ),
.I1(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I2(enable_interrupts_reg),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I4(tx_Buffer_Empty_Pre_reg),
.O(s_axi_arready));
LUT4 #(
.INIT(16'hFB08))
\s_axi_bresp_i[1]_i_1
(.I0(ip2bus_error),
.I1(\state_reg[1]_1 [1]),
.I2(\state_reg[1]_1 [0]),
.I3(s_axi_bresp),
.O(\s_axi_bresp_i_reg[1] ));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_awready),
.I1(\state_reg[1]_1 [1]),
.I2(\state_reg[1]_1 [0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid_i_reg_0),
.O(s_axi_bvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h5C005000))
\s_axi_rdata_i[0]_i_1
(.I0(Q),
.I1(out[0]),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(enable_interrupts_reg),
.I4(\s_axi_rresp_i_reg[1] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hAC00A000))
\s_axi_rdata_i[1]_i_1
(.I0(rx_Buffer_Full),
.I1(out[1]),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(enable_interrupts_reg),
.I4(\s_axi_rresp_i_reg[1] ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hAC00A000))
\s_axi_rdata_i[2]_i_1
(.I0(\INFERRED_GEN.cnt_i_reg[4] ),
.I1(out[2]),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(enable_interrupts_reg),
.I4(\s_axi_rresp_i_reg[1] ),
.O(D[2]));
LUT5 #(
.INIT(32'hAC00A000))
\s_axi_rdata_i[3]_i_1
(.I0(tx_Buffer_Full),
.I1(out[3]),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(enable_interrupts_reg),
.I4(\s_axi_rresp_i_reg[1] ),
.O(D[3]));
LUT5 #(
.INIT(32'hAC00A000))
\s_axi_rdata_i[4]_i_1
(.I0(enable_interrupts),
.I1(out[4]),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(enable_interrupts_reg),
.I4(\s_axi_rresp_i_reg[1] ),
.O(D[4]));
LUT5 #(
.INIT(32'hAC00A000))
\s_axi_rdata_i[5]_i_1
(.I0(status_reg[0]),
.I1(out[5]),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(enable_interrupts_reg),
.I4(\s_axi_rresp_i_reg[1] ),
.O(D[5]));
LUT5 #(
.INIT(32'hAC00A000))
\s_axi_rdata_i[6]_i_1
(.I0(status_reg[1]),
.I1(out[6]),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(enable_interrupts_reg),
.I4(\s_axi_rresp_i_reg[1] ),
.O(D[6]));
LUT4 #(
.INIT(16'h0800))
\s_axi_rdata_i[7]_i_2
(.I0(\s_axi_rresp_i_reg[1] ),
.I1(enable_interrupts_reg),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(out[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hF0880088))
\s_axi_rresp_i[1]_i_1
(.I0(tx_Buffer_Empty_Pre_reg),
.I1(tx_Buffer_Full),
.I2(\s_axi_rresp_i_reg[1] ),
.I3(enable_interrupts_reg),
.I4(Q),
.O(ip2bus_error));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(\state_reg[1]_1 [0]),
.I2(\state_reg[1]_1 [1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid_i_reg_0),
.O(s_axi_rvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h0000FFFE))
s_axi_wready_INST_0
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I1(tx_Buffer_Empty_Pre_reg),
.I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I3(\s_axi_rresp_i_reg[1] ),
.I4(enable_interrupts_reg),
.O(s_axi_awready));
LUT5 #(
.INIT(32'hCEFFCEFC))
\state[0]_i_1
(.I0(s_axi_awready),
.I1(\state_reg[0] ),
.I2(\state_reg[1]_1 [0]),
.I3(\state_reg[1]_1 [1]),
.I4(s_axi_arvalid),
.O(\state_reg[1] [0]));
LUT6 #(
.INIT(64'hCEFCCEFCCEFFCEFC))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(\state_reg[1]_0 ),
.I2(\state_reg[1]_1 [1]),
.I3(\state_reg[1]_1 [0]),
.I4(s_axi_wvalid),
.I5(s_axi_arvalid),
.O(\state_reg[1] [1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h8088))
tx_Buffer_Empty_Pre_i_1
(.I0(\INFERRED_GEN.cnt_i_reg[4] ),
.I1(s_axi_aresetn),
.I2(enable_interrupts_reg),
.I3(tx_Buffer_Empty_Pre_reg),
.O(tx_Buffer_Empty_Pre_reg_0));
endmodule
|
module system_axi_uartlite_0_0_axi_lite_ipif
(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
s_axi_rresp,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
fifo_wr,
\INFERRED_GEN.cnt_i_reg[2] ,
\INFERRED_GEN.cnt_i_reg[2]_0 ,
s_axi_arready,
FIFO_Full_reg,
reset_TX_FIFO,
reset_RX_FIFO,
s_axi_awready,
bus2ip_rdce,
enable_interrupts_reg,
tx_Buffer_Empty_Pre_reg,
rx_Data_Present_Pre_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
tx_Buffer_Full,
Q,
out,
rx_Buffer_Full,
\INFERRED_GEN.cnt_i_reg[4] ,
enable_interrupts,
status_reg,
s_axi_arvalid,
s_axi_wdata,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
s_axi_awaddr,
s_axi_araddr);
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
output [0:0]s_axi_rresp;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output fifo_wr;
output \INFERRED_GEN.cnt_i_reg[2] ;
output \INFERRED_GEN.cnt_i_reg[2]_0 ;
output s_axi_arready;
output FIFO_Full_reg;
output reset_TX_FIFO;
output reset_RX_FIFO;
output s_axi_awready;
output [0:0]bus2ip_rdce;
output enable_interrupts_reg;
output tx_Buffer_Empty_Pre_reg;
output rx_Data_Present_Pre_reg;
output [7:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input tx_Buffer_Full;
input [0:0]Q;
input [7:0]out;
input rx_Buffer_Full;
input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
input enable_interrupts;
input [1:0]status_reg;
input s_axi_arvalid;
input [2:0]s_axi_wdata;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awaddr;
input [1:0]s_axi_araddr;
wire Bus_RNW_reg;
wire FIFO_Full_reg;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \INFERRED_GEN.cnt_i_reg[2] ;
wire \INFERRED_GEN.cnt_i_reg[2]_0 ;
wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
wire [0:0]Q;
wire [0:0]bus2ip_rdce;
wire bus2ip_reset;
wire enable_interrupts;
wire enable_interrupts_reg;
wire fifo_wr;
wire [7:0]out;
wire reset_RX_FIFO;
wire reset_TX_FIFO;
wire rx_Buffer_Full;
wire rx_Data_Present_Pre_reg;
wire s_axi_aclk;
wire [1:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [1:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire s_axi_bvalid;
wire [7:0]s_axi_rdata;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire [2:0]s_axi_wdata;
wire s_axi_wvalid;
wire [1:0]status_reg;
wire tx_Buffer_Empty_Pre_reg;
wire tx_Buffer_Full;
system_axi_uartlite_0_0_slave_attachment I_SLAVE_ATTACHMENT
(.FIFO_Full_reg(FIFO_Full_reg),
.\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
.\INFERRED_GEN.cnt_i_reg[2]_0 (\INFERRED_GEN.cnt_i_reg[2]_0 ),
.\INFERRED_GEN.cnt_i_reg[4] (\INFERRED_GEN.cnt_i_reg[4] ),
.Q(Q),
.bus2ip_rdce(bus2ip_rdce),
.bus2ip_reset(bus2ip_reset),
.enable_interrupts(enable_interrupts),
.enable_interrupts_reg(Bus_RNW_reg),
.enable_interrupts_reg_0(enable_interrupts_reg),
.fifo_wr(fifo_wr),
.out(out),
.reset_RX_FIFO(reset_RX_FIFO),
.reset_TX_FIFO(reset_TX_FIFO),
.rx_Buffer_Full(rx_Buffer_Full),
.rx_Data_Present_Pre_reg(rx_Data_Present_Pre_reg),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.\s_axi_rresp_i_reg[1]_0 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wvalid(s_axi_wvalid),
.status_reg(status_reg),
.tx_Buffer_Empty_Pre_reg(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.tx_Buffer_Empty_Pre_reg_0(tx_Buffer_Empty_Pre_reg),
.tx_Buffer_Full(tx_Buffer_Full));
endmodule
|
module system_axi_uartlite_0_0_axi_uartlite
(s_axi_aclk,
s_axi_aresetn,
interrupt,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
rx,
tx);
(* max_fanout = "10000" *) input s_axi_aclk;
(* max_fanout = "10000" *) input s_axi_aresetn;
output interrupt;
input [3:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input rx;
output tx;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_16;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_18;
wire AXI_LITE_IPIF_I_n_8;
wire AXI_LITE_IPIF_I_n_9;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \UARTLITE_RX_I/rx_Data_Empty ;
wire \UARTLITE_TX_I/fifo_wr ;
wire [1:1]bus2ip_rdce;
wire bus2ip_reset;
wire enable_interrupts;
wire interrupt;
wire reset_RX_FIFO;
wire reset_TX_FIFO;
wire rx;
wire rx_Buffer_Full;
wire [0:7]rx_Data;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) wire s_axi_aclk;
wire [3:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [3:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:1]\^s_axi_bresp ;
wire s_axi_bvalid;
wire [7:0]\^s_axi_rdata ;
wire s_axi_rready;
wire [1:1]\^s_axi_rresp ;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wvalid;
wire [1:2]status_reg;
wire tx;
wire tx_Buffer_Empty;
wire tx_Buffer_Full;
assign s_axi_bresp[1] = \^s_axi_bresp [1];
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \^s_axi_rresp [1];
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_wready = s_axi_awready;
system_axi_uartlite_0_0_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.FIFO_Full_reg(AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\INFERRED_GEN.cnt_i_reg[2] (AXI_LITE_IPIF_I_n_8),
.\INFERRED_GEN.cnt_i_reg[2]_0 (AXI_LITE_IPIF_I_n_9),
.\INFERRED_GEN.cnt_i_reg[4] (tx_Buffer_Empty),
.Q(\UARTLITE_RX_I/rx_Data_Empty ),
.bus2ip_rdce(bus2ip_rdce),
.bus2ip_reset(bus2ip_reset),
.enable_interrupts(enable_interrupts),
.enable_interrupts_reg(AXI_LITE_IPIF_I_n_16),
.fifo_wr(\UARTLITE_TX_I/fifo_wr ),
.out({rx_Data[0],rx_Data[1],rx_Data[2],rx_Data[3],rx_Data[4],rx_Data[5],rx_Data[6],rx_Data[7]}),
.reset_RX_FIFO(reset_RX_FIFO),
.reset_TX_FIFO(reset_TX_FIFO),
.rx_Buffer_Full(rx_Buffer_Full),
.rx_Data_Present_Pre_reg(AXI_LITE_IPIF_I_n_18),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[3:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[3:2]),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(\^s_axi_bresp ),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(\^s_axi_rresp ),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[4],s_axi_wdata[1:0]}),
.s_axi_wvalid(s_axi_wvalid),
.status_reg({status_reg[1],status_reg[2]}),
.tx_Buffer_Empty_Pre_reg(AXI_LITE_IPIF_I_n_17),
.tx_Buffer_Full(tx_Buffer_Full));
GND GND
(.G(\<const0> ));
system_axi_uartlite_0_0_uartlite_core UARTLITE_CORE_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.Bus_RNW_reg_reg(AXI_LITE_IPIF_I_n_9),
.FIFO_Full_reg(\UARTLITE_RX_I/rx_Data_Empty ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (AXI_LITE_IPIF_I_n_18),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 (AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (AXI_LITE_IPIF_I_n_8),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] (AXI_LITE_IPIF_I_n_16),
.\INFERRED_GEN.cnt_i_reg[4] (AXI_LITE_IPIF_I_n_17),
.Q(tx_Buffer_Empty),
.bus2ip_rdce(bus2ip_rdce),
.bus2ip_reset(bus2ip_reset),
.enable_interrupts(enable_interrupts),
.fifo_wr(\UARTLITE_TX_I/fifo_wr ),
.interrupt(interrupt),
.out({rx_Data[0],rx_Data[1],rx_Data[2],rx_Data[3],rx_Data[4],rx_Data[5],rx_Data[6],rx_Data[7]}),
.reset_RX_FIFO(reset_RX_FIFO),
.reset_TX_FIFO(reset_TX_FIFO),
.rx(rx),
.rx_Buffer_Full(rx_Buffer_Full),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata[7:0]),
.status_reg({status_reg[1],status_reg[2]}),
.tx(tx),
.tx_Buffer_Full(tx_Buffer_Full));
endmodule
|
module system_axi_uartlite_0_0_baudrate
(en_16x_Baud,
SR,
s_axi_aclk);
output en_16x_Baud;
input [0:0]SR;
input s_axi_aclk;
wire EN_16x_Baud;
wire [0:0]SR;
wire [9:0]count;
wire \count[2]_i_2_n_0 ;
wire \count[4]_i_2_n_0 ;
wire \count[4]_i_3_n_0 ;
wire \count[9]_i_2_n_0 ;
wire [9:0]count_0;
wire en_16x_Baud;
wire s_axi_aclk;
LUT6 #(
.INIT(64'h0000000000000001))
EN_16x_Baud_i_1
(.I0(\count[9]_i_2_n_0 ),
.I1(count[5]),
.I2(count[6]),
.I3(count[9]),
.I4(count[7]),
.I5(count[8]),
.O(EN_16x_Baud));
FDRE EN_16x_Baud_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(EN_16x_Baud),
.Q(en_16x_Baud),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFF0000FFFE))
\count[0]_i_1
(.I0(count[3]),
.I1(count[4]),
.I2(\count[2]_i_2_n_0 ),
.I3(count[2]),
.I4(count[0]),
.I5(count[1]),
.O(count_0[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h9))
\count[1]_i_1
(.I0(count[1]),
.I1(count[0]),
.O(count_0[1]));
LUT6 #(
.INIT(64'hE1E1E1E1E1E1E1E0))
\count[2]_i_1
(.I0(count[1]),
.I1(count[0]),
.I2(count[2]),
.I3(\count[2]_i_2_n_0 ),
.I4(count[4]),
.I5(count[3]),
.O(count_0[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\count[2]_i_2
(.I0(count[9]),
.I1(count[7]),
.I2(count[8]),
.I3(count[6]),
.I4(count[5]),
.O(\count[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hAAA9))
\count[3]_i_1
(.I0(count[3]),
.I1(count[1]),
.I2(count[0]),
.I3(count[2]),
.O(count_0[3]));
LUT6 #(
.INIT(64'hA9A9A9A9A9A9A9A8))
\count[4]_i_1
(.I0(count[4]),
.I1(count[3]),
.I2(\count[4]_i_2_n_0 ),
.I3(\count[4]_i_3_n_0 ),
.I4(count[6]),
.I5(count[5]),
.O(count_0[4]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hFE))
\count[4]_i_2
(.I0(count[1]),
.I1(count[0]),
.I2(count[2]),
.O(\count[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hFE))
\count[4]_i_3
(.I0(count[8]),
.I1(count[7]),
.I2(count[9]),
.O(\count[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFF00000000FFFE))
\count[5]_i_1
(.I0(count[9]),
.I1(count[7]),
.I2(count[8]),
.I3(count[6]),
.I4(count[5]),
.I5(\count[9]_i_2_n_0 ),
.O(count_0[5]));
LUT6 #(
.INIT(64'hA9A9A9A9A9A9A9A8))
\count[6]_i_1
(.I0(count[6]),
.I1(count[5]),
.I2(\count[9]_i_2_n_0 ),
.I3(count[8]),
.I4(count[7]),
.I5(count[9]),
.O(count_0[6]));
LUT4 #(
.INIT(16'hAAA9))
\count[7]_i_1
(.I0(count[7]),
.I1(count[6]),
.I2(count[5]),
.I3(\count[9]_i_2_n_0 ),
.O(count_0[7]));
LUT6 #(
.INIT(64'hFF00FE01FF00FE00))
\count[8]_i_1
(.I0(\count[9]_i_2_n_0 ),
.I1(count[5]),
.I2(count[6]),
.I3(count[8]),
.I4(count[7]),
.I5(count[9]),
.O(count_0[8]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F0E1))
\count[9]_i_1
(.I0(count[8]),
.I1(count[7]),
.I2(count[9]),
.I3(count[6]),
.I4(count[5]),
.I5(\count[9]_i_2_n_0 ),
.O(count_0[9]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\count[9]_i_2
(.I0(count[4]),
.I1(count[3]),
.I2(count[2]),
.I3(count[0]),
.I4(count[1]),
.O(\count[9]_i_2_n_0 ));
FDRE \count_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[0]),
.Q(count[0]),
.R(SR));
FDRE \count_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[1]),
.Q(count[1]),
.R(SR));
FDRE \count_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[2]),
.Q(count[2]),
.R(SR));
FDRE \count_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[3]),
.Q(count[3]),
.R(SR));
FDRE \count_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[4]),
.Q(count[4]),
.R(SR));
FDRE \count_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[5]),
.Q(count[5]),
.R(SR));
FDRE \count_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[6]),
.Q(count[6]),
.R(SR));
FDRE \count_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[7]),
.Q(count[7]),
.R(SR));
FDRE \count_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[8]),
.Q(count[8]),
.R(SR));
FDRE \count_reg[9]
(.C(s_axi_aclk),
.CE(1'b1),
.D(count_0[9]),
.Q(count[9]),
.R(SR));
endmodule
|
module system_axi_uartlite_0_0_cdc_sync
(p_26_out,
scndry_out,
start_Edge_Detected,
EN_16x_Baud_reg,
s_axi_aresetn,
in,
rx,
s_axi_aclk);
output p_26_out;
output scndry_out;
input start_Edge_Detected;
input EN_16x_Baud_reg;
input s_axi_aresetn;
input [0:0]in;
input rx;
input s_axi_aclk;
wire EN_16x_Baud_reg;
wire [0:0]in;
wire p_26_out;
wire rx;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire start_Edge_Detected;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(rx),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hFE00CE00))
\SERIAL_TO_PARALLEL[1].fifo_din[1]_i_1
(.I0(scndry_out),
.I1(start_Edge_Detected),
.I2(EN_16x_Baud_reg),
.I3(s_axi_aresetn),
.I4(in),
.O(p_26_out));
endmodule
|
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