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module sky130_fd_sc_hs__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule |
module rcn_ram
(
input clk,
input rst,
input [68:0] rcn_in,
output [68:0] rcn_out
);
parameter ADDR_BASE = 0;
wire cs;
wire wr;
wire [3:0] mask;
wire [23:0] addr;
wire [31:0] wdata;
wire [31:0] rdata;
rcn_slave #(.ADDR_MASK(24'hFF0000), .ADDR_BASE(ADDR_BASE)) rcn_slave
(
.rst(rst),
.clk(clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(cs),
.wr(wr),
.mask(mask),
.addr(addr),
.wdata(wdata),
.rdata(rdata)
);
reg [7:0] byte_0[(1024 * 16)-1:0];
reg [7:0] byte_1[(1024 * 16)-1:0];
reg [7:0] byte_2[(1024 * 16)-1:0];
reg [7:0] byte_3[(1024 * 16)-1:0];
reg [31:0] data_out;
always @ (posedge clk)
if (cs && wr)
begin
if (mask[0])
byte_0[addr[15:2]] <= wdata[7:0];
if (mask[1])
byte_1[addr[15:2]] <= wdata[15:8];
if (mask[2])
byte_2[addr[15:2]] <= wdata[23:16];
if (mask[3])
byte_3[addr[15:2]] <= wdata[31:24];
end
always @ (posedge clk)
if (cs)
data_out <= {byte_3[addr[15:2]], byte_2[addr[15:2]],
byte_1[addr[15:2]], byte_0[addr[15:2]]};
assign rdata = data_out;
endmodule |
module DataMemory(
output reg [31:0] ReadData,
output reg [31:0] DATO1,
output reg [31:0] DATO2,
output reg [31:0] RESULTADO,
input [31:0] Address,
input [31:0] WriteData,
input [31:0] MouseData,
input MouseEnable,
input WriteEnable,
input CLK
);
reg [31:0] block [0:9];
always @ (*) begin
DATO1 = block[4];
DATO2 = block[5];
RESULTADO = block[7];
if (CLK) begin
case (Address)
32'h00000000: ReadData = block[0];
32'h00000004: ReadData = block[1];
32'h00000008: ReadData = block[2];
32'h0000000c: ReadData = block[3];
32'h00000010: ReadData = block[4];
32'h00000014: ReadData = block[5];
32'h00000018: ReadData = block[6];
32'h0000001c: ReadData = block[7];
32'h00000020: ReadData = block[8];
32'h00000024: ReadData = block[9];
default: ReadData = 32'b0;
endcase
end
else begin
if (MouseEnable) begin
block[1] = MouseData;
end
if (WriteEnable)
case (Address)
32'h00000000: block[0] = WriteData;
32'h00000004: block[1] = WriteData;
32'h00000008: block[2] = WriteData;
32'h0000000c: block[3] = WriteData;
32'h00000010: block[4] = WriteData;
32'h00000014: block[5] = WriteData;
32'h00000018: block[6] = WriteData;
32'h0000001c: block[7] = WriteData;
32'h00000020: block[8] = WriteData;
32'h00000024: block[9] = WriteData;
endcase
end
end
integer i = 0;
initial begin
for (i=0;i<10;i=i+1)
block[i] = 32'b0;
block[1] = 2;
block[4] = 2;
end
endmodule |
module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000100000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000001000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000100000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule |
module URAM288 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer AUTO_SLEEP_LATENCY = 8,
parameter integer AVG_CONS_INACTIVE_CYCLES = 10,
parameter BWE_MODE_A = "PARITY_INTERLEAVED",
parameter BWE_MODE_B = "PARITY_INTERLEAVED",
parameter CASCADE_ORDER_A = "NONE",
parameter CASCADE_ORDER_B = "NONE",
parameter EN_AUTO_SLEEP_MODE = "FALSE",
parameter EN_ECC_RD_A = "FALSE",
parameter EN_ECC_RD_B = "FALSE",
parameter EN_ECC_WR_A = "FALSE",
parameter EN_ECC_WR_B = "FALSE",
parameter IREG_PRE_A = "FALSE",
parameter IREG_PRE_B = "FALSE",
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_EN_A_INVERTED = 1'b0,
parameter [0:0] IS_EN_B_INVERTED = 1'b0,
parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0,
parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0,
parameter [0:0] IS_RST_A_INVERTED = 1'b0,
parameter [0:0] IS_RST_B_INVERTED = 1'b0,
parameter MATRIX_ID = "NONE",
parameter integer NUM_UNIQUE_SELF_ADDR_A = 1,
parameter integer NUM_UNIQUE_SELF_ADDR_B = 1,
parameter integer NUM_URAM_IN_MATRIX = 1,
parameter OREG_A = "FALSE",
parameter OREG_B = "FALSE",
parameter OREG_ECC_A = "FALSE",
parameter OREG_ECC_B = "FALSE",
parameter REG_CAS_A = "FALSE",
parameter REG_CAS_B = "FALSE",
parameter RST_MODE_A = "SYNC",
parameter RST_MODE_B = "SYNC",
parameter [10:0] SELF_ADDR_A = 11'h000,
parameter [10:0] SELF_ADDR_B = 11'h000,
parameter [10:0] SELF_MASK_A = 11'h7FF,
parameter [10:0] SELF_MASK_B = 11'h7FF,
parameter USE_EXT_CE_A = "FALSE",
parameter USE_EXT_CE_B = "FALSE"
)(
output [22:0] CAS_OUT_ADDR_A,
output [22:0] CAS_OUT_ADDR_B,
output [8:0] CAS_OUT_BWE_A,
output [8:0] CAS_OUT_BWE_B,
output CAS_OUT_DBITERR_A,
output CAS_OUT_DBITERR_B,
output [71:0] CAS_OUT_DIN_A,
output [71:0] CAS_OUT_DIN_B,
output [71:0] CAS_OUT_DOUT_A,
output [71:0] CAS_OUT_DOUT_B,
output CAS_OUT_EN_A,
output CAS_OUT_EN_B,
output CAS_OUT_RDACCESS_A,
output CAS_OUT_RDACCESS_B,
output CAS_OUT_RDB_WR_A,
output CAS_OUT_RDB_WR_B,
output CAS_OUT_SBITERR_A,
output CAS_OUT_SBITERR_B,
output DBITERR_A,
output DBITERR_B,
output [71:0] DOUT_A,
output [71:0] DOUT_B,
output RDACCESS_A,
output RDACCESS_B,
output SBITERR_A,
output SBITERR_B,
input [22:0] ADDR_A,
input [22:0] ADDR_B,
input [8:0] BWE_A,
input [8:0] BWE_B,
input [22:0] CAS_IN_ADDR_A,
input [22:0] CAS_IN_ADDR_B,
input [8:0] CAS_IN_BWE_A,
input [8:0] CAS_IN_BWE_B,
input CAS_IN_DBITERR_A,
input CAS_IN_DBITERR_B,
input [71:0] CAS_IN_DIN_A,
input [71:0] CAS_IN_DIN_B,
input [71:0] CAS_IN_DOUT_A,
input [71:0] CAS_IN_DOUT_B,
input CAS_IN_EN_A,
input CAS_IN_EN_B,
input CAS_IN_RDACCESS_A,
input CAS_IN_RDACCESS_B,
input CAS_IN_RDB_WR_A,
input CAS_IN_RDB_WR_B,
input CAS_IN_SBITERR_A,
input CAS_IN_SBITERR_B,
input CLK,
input [71:0] DIN_A,
input [71:0] DIN_B,
input EN_A,
input EN_B,
input INJECT_DBITERR_A,
input INJECT_DBITERR_B,
input INJECT_SBITERR_A,
input INJECT_SBITERR_B,
input OREG_CE_A,
input OREG_CE_B,
input OREG_ECC_CE_A,
input OREG_ECC_CE_B,
input RDB_WR_A,
input RDB_WR_B,
input RST_A,
input RST_B,
input SLEEP
);
// define constants
localparam MODULE_NAME = "URAM288";
// Parameter encodings and registers
localparam BWE_MODE_A_PARITY_INDEPENDENT = 1;
localparam BWE_MODE_A_PARITY_INTERLEAVED = 0;
localparam BWE_MODE_B_PARITY_INDEPENDENT = 1;
localparam BWE_MODE_B_PARITY_INTERLEAVED = 0;
localparam CASCADE_ORDER_A_FIRST = 1;
localparam CASCADE_ORDER_A_LAST = 2;
localparam CASCADE_ORDER_A_MIDDLE = 3;
localparam CASCADE_ORDER_A_NONE = 0;
localparam CASCADE_ORDER_B_FIRST = 1;
localparam CASCADE_ORDER_B_LAST = 2;
localparam CASCADE_ORDER_B_MIDDLE = 3;
localparam CASCADE_ORDER_B_NONE = 0;
localparam EN_AUTO_SLEEP_MODE_FALSE = 0;
localparam EN_AUTO_SLEEP_MODE_TRUE = 1;
localparam EN_ECC_RD_A_FALSE = 0;
localparam EN_ECC_RD_A_TRUE = 1;
localparam EN_ECC_RD_B_FALSE = 0;
localparam EN_ECC_RD_B_TRUE = 1;
localparam EN_ECC_WR_A_FALSE = 0;
localparam EN_ECC_WR_A_TRUE = 1;
localparam EN_ECC_WR_B_FALSE = 0;
localparam EN_ECC_WR_B_TRUE = 1;
localparam IREG_PRE_A_FALSE = 0;
localparam IREG_PRE_A_TRUE = 1;
localparam IREG_PRE_B_FALSE = 0;
localparam IREG_PRE_B_TRUE = 1;
localparam OREG_A_FALSE = 0;
localparam OREG_A_TRUE = 1;
localparam OREG_B_FALSE = 0;
localparam OREG_B_TRUE = 1;
localparam OREG_ECC_A_FALSE = 0;
localparam OREG_ECC_A_TRUE = 1;
localparam OREG_ECC_B_FALSE = 0;
localparam OREG_ECC_B_TRUE = 1;
localparam REG_CAS_A_FALSE = 0;
localparam REG_CAS_A_TRUE = 1;
localparam REG_CAS_B_FALSE = 0;
localparam REG_CAS_B_TRUE = 1;
localparam RST_MODE_A_ASYNC = 1;
localparam RST_MODE_A_SYNC = 0;
localparam RST_MODE_B_ASYNC = 1;
localparam RST_MODE_B_SYNC = 0;
localparam USE_EXT_CE_A_FALSE = 0;
localparam USE_EXT_CE_A_TRUE = 1;
localparam USE_EXT_CE_B_FALSE = 0;
localparam USE_EXT_CE_B_TRUE = 1;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "URAM288_dr.v"
`else
reg [31:0] AUTO_SLEEP_LATENCY_REG = AUTO_SLEEP_LATENCY;
reg [31:0] AVG_CONS_INACTIVE_CYCLES_REG = AVG_CONS_INACTIVE_CYCLES;
reg [144:1] BWE_MODE_A_REG = BWE_MODE_A;
reg [144:1] BWE_MODE_B_REG = BWE_MODE_B;
reg [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A;
reg [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B;
reg [40:1] EN_AUTO_SLEEP_MODE_REG = EN_AUTO_SLEEP_MODE;
reg [40:1] EN_ECC_RD_A_REG = EN_ECC_RD_A;
reg [40:1] EN_ECC_RD_B_REG = EN_ECC_RD_B;
reg [40:1] EN_ECC_WR_A_REG = EN_ECC_WR_A;
reg [40:1] EN_ECC_WR_B_REG = EN_ECC_WR_B;
reg [40:1] IREG_PRE_A_REG = IREG_PRE_A;
reg [40:1] IREG_PRE_B_REG = IREG_PRE_B;
reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
reg [0:0] IS_EN_A_INVERTED_REG = IS_EN_A_INVERTED;
reg [0:0] IS_EN_B_INVERTED_REG = IS_EN_B_INVERTED;
reg [0:0] IS_RDB_WR_A_INVERTED_REG = IS_RDB_WR_A_INVERTED;
reg [0:0] IS_RDB_WR_B_INVERTED_REG = IS_RDB_WR_B_INVERTED;
reg [0:0] IS_RST_A_INVERTED_REG = IS_RST_A_INVERTED;
reg [0:0] IS_RST_B_INVERTED_REG = IS_RST_B_INVERTED;
reg [32:1] MATRIX_ID_REG = MATRIX_ID;
reg [31:0] NUM_UNIQUE_SELF_ADDR_A_REG = NUM_UNIQUE_SELF_ADDR_A;
reg [31:0] NUM_UNIQUE_SELF_ADDR_B_REG = NUM_UNIQUE_SELF_ADDR_B;
reg [31:0] NUM_URAM_IN_MATRIX_REG = NUM_URAM_IN_MATRIX;
reg [40:1] OREG_A_REG = OREG_A;
reg [40:1] OREG_B_REG = OREG_B;
reg [40:1] OREG_ECC_A_REG = OREG_ECC_A;
reg [40:1] OREG_ECC_B_REG = OREG_ECC_B;
reg [40:1] REG_CAS_A_REG = REG_CAS_A;
reg [40:1] REG_CAS_B_REG = REG_CAS_B;
reg [40:1] RST_MODE_A_REG = RST_MODE_A;
reg [40:1] RST_MODE_B_REG = RST_MODE_B;
reg [10:0] SELF_ADDR_A_REG = SELF_ADDR_A;
reg [10:0] SELF_ADDR_B_REG = SELF_ADDR_B;
reg [10:0] SELF_MASK_A_REG = SELF_MASK_A;
reg [10:0] SELF_MASK_B_REG = SELF_MASK_B;
reg [40:1] USE_EXT_CE_A_REG = USE_EXT_CE_A;
reg [40:1] USE_EXT_CE_B_REG = USE_EXT_CE_B;
`endif
`ifdef XIL_XECLIB
wire [3:0] AUTO_SLEEP_LATENCY_BIN;
wire [16:0] AVG_CONS_INACTIVE_CYCLES_BIN;
wire BWE_MODE_A_BIN;
wire BWE_MODE_B_BIN;
wire [1:0] CASCADE_ORDER_A_BIN;
wire [1:0] CASCADE_ORDER_B_BIN;
wire EN_AUTO_SLEEP_MODE_BIN;
wire EN_ECC_RD_A_BIN;
wire EN_ECC_RD_B_BIN;
wire EN_ECC_WR_A_BIN;
wire EN_ECC_WR_B_BIN;
wire IREG_PRE_A_BIN;
wire IREG_PRE_B_BIN;
wire [11:0] NUM_UNIQUE_SELF_ADDR_A_BIN;
wire [11:0] NUM_UNIQUE_SELF_ADDR_B_BIN;
wire [11:0] NUM_URAM_IN_MATRIX_BIN;
wire OREG_A_BIN;
wire OREG_B_BIN;
wire OREG_ECC_A_BIN;
wire OREG_ECC_B_BIN;
wire REG_CAS_A_BIN;
wire REG_CAS_B_BIN;
wire RST_MODE_A_BIN;
wire RST_MODE_B_BIN;
wire USE_EXT_CE_A_BIN;
wire USE_EXT_CE_B_BIN;
`else
reg [3:0] AUTO_SLEEP_LATENCY_BIN;
reg [16:0] AVG_CONS_INACTIVE_CYCLES_BIN;
reg BWE_MODE_A_BIN;
reg BWE_MODE_B_BIN;
reg [1:0] CASCADE_ORDER_A_BIN;
reg [1:0] CASCADE_ORDER_B_BIN;
reg EN_AUTO_SLEEP_MODE_BIN;
reg EN_ECC_RD_A_BIN;
reg EN_ECC_RD_B_BIN;
reg EN_ECC_WR_A_BIN;
reg EN_ECC_WR_B_BIN;
reg IREG_PRE_A_BIN;
reg IREG_PRE_B_BIN;
reg [11:0] NUM_UNIQUE_SELF_ADDR_A_BIN;
reg [11:0] NUM_UNIQUE_SELF_ADDR_B_BIN;
reg [11:0] NUM_URAM_IN_MATRIX_BIN;
reg OREG_A_BIN;
reg OREG_B_BIN;
reg OREG_ECC_A_BIN;
reg OREG_ECC_B_BIN;
reg REG_CAS_A_BIN;
reg REG_CAS_B_BIN;
reg RST_MODE_A_BIN;
reg RST_MODE_B_BIN;
reg USE_EXT_CE_A_BIN;
reg USE_EXT_CE_B_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CAS_IN_DBITERR_A_in;
wire CAS_IN_DBITERR_B_in;
wire CAS_IN_EN_A_in;
wire CAS_IN_EN_B_in;
wire CAS_IN_RDACCESS_A_in;
wire CAS_IN_RDACCESS_B_in;
wire CAS_IN_RDB_WR_A_in;
wire CAS_IN_RDB_WR_B_in;
wire CAS_IN_SBITERR_A_in;
wire CAS_IN_SBITERR_B_in;
wire CLK_in;
wire EN_A_in;
wire EN_B_in;
wire INJECT_DBITERR_A_in;
wire INJECT_DBITERR_B_in;
wire INJECT_SBITERR_A_in;
wire INJECT_SBITERR_B_in;
wire OREG_CE_A_in;
wire OREG_CE_B_in;
wire OREG_ECC_CE_A_in;
wire OREG_ECC_CE_B_in;
wire RDB_WR_A_in;
wire RDB_WR_B_in;
wire RST_A_in;
wire RST_B_in;
wire SLEEP_in;
wire [22:0] ADDR_A_in;
wire [22:0] ADDR_B_in;
wire [22:0] CAS_IN_ADDR_A_in;
wire [22:0] CAS_IN_ADDR_B_in;
wire [71:0] CAS_IN_DIN_A_in;
wire [71:0] CAS_IN_DIN_B_in;
wire [71:0] CAS_IN_DOUT_A_in;
wire [71:0] CAS_IN_DOUT_B_in;
wire [71:0] DIN_A_in;
wire [71:0] DIN_B_in;
wire [8:0] BWE_A_in;
wire [8:0] BWE_B_in;
wire [8:0] CAS_IN_BWE_A_in;
wire [8:0] CAS_IN_BWE_B_in;
`ifdef XIL_TIMING
wire CAS_IN_DBITERR_A_delay;
wire CAS_IN_DBITERR_B_delay;
wire CAS_IN_EN_A_delay;
wire CAS_IN_EN_B_delay;
wire CAS_IN_RDACCESS_A_delay;
wire CAS_IN_RDACCESS_B_delay;
wire CAS_IN_RDB_WR_A_delay;
wire CAS_IN_RDB_WR_B_delay;
wire CAS_IN_SBITERR_A_delay;
wire CAS_IN_SBITERR_B_delay;
wire CLK_delay;
wire EN_A_delay;
wire EN_B_delay;
wire INJECT_DBITERR_A_delay;
wire INJECT_DBITERR_B_delay;
wire INJECT_SBITERR_A_delay;
wire INJECT_SBITERR_B_delay;
wire OREG_CE_A_delay;
wire OREG_CE_B_delay;
wire OREG_ECC_CE_A_delay;
wire OREG_ECC_CE_B_delay;
wire RDB_WR_A_delay;
wire RDB_WR_B_delay;
wire RST_A_delay;
wire RST_B_delay;
wire SLEEP_delay;
wire [22:0] ADDR_A_delay;
wire [22:0] ADDR_B_delay;
wire [22:0] CAS_IN_ADDR_A_delay;
wire [22:0] CAS_IN_ADDR_B_delay;
wire [71:0] CAS_IN_DIN_A_delay;
wire [71:0] CAS_IN_DIN_B_delay;
wire [71:0] CAS_IN_DOUT_A_delay;
wire [71:0] CAS_IN_DOUT_B_delay;
wire [71:0] DIN_A_delay;
wire [71:0] DIN_B_delay;
wire [8:0] BWE_A_delay;
wire [8:0] BWE_B_delay;
wire [8:0] CAS_IN_BWE_A_delay;
wire [8:0] CAS_IN_BWE_B_delay;
`endif
`ifdef XIL_TIMING
assign ADDR_A_in = ADDR_A_delay;
assign ADDR_B_in = ADDR_B_delay;
assign BWE_A_in = BWE_A_delay;
assign BWE_B_in = BWE_B_delay;
assign CAS_IN_ADDR_A_in[0] = (CAS_IN_ADDR_A[0] !== 1'bz) && CAS_IN_ADDR_A_delay[0]; // rv 0
assign CAS_IN_ADDR_A_in[10] = (CAS_IN_ADDR_A[10] !== 1'bz) && CAS_IN_ADDR_A_delay[10]; // rv 0
assign CAS_IN_ADDR_A_in[11] = (CAS_IN_ADDR_A[11] !== 1'bz) && CAS_IN_ADDR_A_delay[11]; // rv 0
assign CAS_IN_ADDR_A_in[12] = (CAS_IN_ADDR_A[12] !== 1'bz) && CAS_IN_ADDR_A_delay[12]; // rv 0
assign CAS_IN_ADDR_A_in[13] = (CAS_IN_ADDR_A[13] !== 1'bz) && CAS_IN_ADDR_A_delay[13]; // rv 0
assign CAS_IN_ADDR_A_in[14] = (CAS_IN_ADDR_A[14] !== 1'bz) && CAS_IN_ADDR_A_delay[14]; // rv 0
assign CAS_IN_ADDR_A_in[15] = (CAS_IN_ADDR_A[15] !== 1'bz) && CAS_IN_ADDR_A_delay[15]; // rv 0
assign CAS_IN_ADDR_A_in[16] = (CAS_IN_ADDR_A[16] !== 1'bz) && CAS_IN_ADDR_A_delay[16]; // rv 0
assign CAS_IN_ADDR_A_in[17] = (CAS_IN_ADDR_A[17] !== 1'bz) && CAS_IN_ADDR_A_delay[17]; // rv 0
assign CAS_IN_ADDR_A_in[18] = (CAS_IN_ADDR_A[18] !== 1'bz) && CAS_IN_ADDR_A_delay[18]; // rv 0
assign CAS_IN_ADDR_A_in[19] = (CAS_IN_ADDR_A[19] !== 1'bz) && CAS_IN_ADDR_A_delay[19]; // rv 0
assign CAS_IN_ADDR_A_in[1] = (CAS_IN_ADDR_A[1] !== 1'bz) && CAS_IN_ADDR_A_delay[1]; // rv 0
assign CAS_IN_ADDR_A_in[20] = (CAS_IN_ADDR_A[20] !== 1'bz) && CAS_IN_ADDR_A_delay[20]; // rv 0
assign CAS_IN_ADDR_A_in[21] = (CAS_IN_ADDR_A[21] !== 1'bz) && CAS_IN_ADDR_A_delay[21]; // rv 0
assign CAS_IN_ADDR_A_in[22] = (CAS_IN_ADDR_A[22] !== 1'bz) && CAS_IN_ADDR_A_delay[22]; // rv 0
assign CAS_IN_ADDR_A_in[2] = (CAS_IN_ADDR_A[2] !== 1'bz) && CAS_IN_ADDR_A_delay[2]; // rv 0
assign CAS_IN_ADDR_A_in[3] = (CAS_IN_ADDR_A[3] !== 1'bz) && CAS_IN_ADDR_A_delay[3]; // rv 0
assign CAS_IN_ADDR_A_in[4] = (CAS_IN_ADDR_A[4] !== 1'bz) && CAS_IN_ADDR_A_delay[4]; // rv 0
assign CAS_IN_ADDR_A_in[5] = (CAS_IN_ADDR_A[5] !== 1'bz) && CAS_IN_ADDR_A_delay[5]; // rv 0
assign CAS_IN_ADDR_A_in[6] = (CAS_IN_ADDR_A[6] !== 1'bz) && CAS_IN_ADDR_A_delay[6]; // rv 0
assign CAS_IN_ADDR_A_in[7] = (CAS_IN_ADDR_A[7] !== 1'bz) && CAS_IN_ADDR_A_delay[7]; // rv 0
assign CAS_IN_ADDR_A_in[8] = (CAS_IN_ADDR_A[8] !== 1'bz) && CAS_IN_ADDR_A_delay[8]; // rv 0
assign CAS_IN_ADDR_A_in[9] = (CAS_IN_ADDR_A[9] !== 1'bz) && CAS_IN_ADDR_A_delay[9]; // rv 0
assign CAS_IN_ADDR_B_in[0] = (CAS_IN_ADDR_B[0] !== 1'bz) && CAS_IN_ADDR_B_delay[0]; // rv 0
assign CAS_IN_ADDR_B_in[10] = (CAS_IN_ADDR_B[10] !== 1'bz) && CAS_IN_ADDR_B_delay[10]; // rv 0
assign CAS_IN_ADDR_B_in[11] = (CAS_IN_ADDR_B[11] !== 1'bz) && CAS_IN_ADDR_B_delay[11]; // rv 0
assign CAS_IN_ADDR_B_in[12] = (CAS_IN_ADDR_B[12] !== 1'bz) && CAS_IN_ADDR_B_delay[12]; // rv 0
assign CAS_IN_ADDR_B_in[13] = (CAS_IN_ADDR_B[13] !== 1'bz) && CAS_IN_ADDR_B_delay[13]; // rv 0
assign CAS_IN_ADDR_B_in[14] = (CAS_IN_ADDR_B[14] !== 1'bz) && CAS_IN_ADDR_B_delay[14]; // rv 0
assign CAS_IN_ADDR_B_in[15] = (CAS_IN_ADDR_B[15] !== 1'bz) && CAS_IN_ADDR_B_delay[15]; // rv 0
assign CAS_IN_ADDR_B_in[16] = (CAS_IN_ADDR_B[16] !== 1'bz) && CAS_IN_ADDR_B_delay[16]; // rv 0
assign CAS_IN_ADDR_B_in[17] = (CAS_IN_ADDR_B[17] !== 1'bz) && CAS_IN_ADDR_B_delay[17]; // rv 0
assign CAS_IN_ADDR_B_in[18] = (CAS_IN_ADDR_B[18] !== 1'bz) && CAS_IN_ADDR_B_delay[18]; // rv 0
assign CAS_IN_ADDR_B_in[19] = (CAS_IN_ADDR_B[19] !== 1'bz) && CAS_IN_ADDR_B_delay[19]; // rv 0
assign CAS_IN_ADDR_B_in[1] = (CAS_IN_ADDR_B[1] !== 1'bz) && CAS_IN_ADDR_B_delay[1]; // rv 0
assign CAS_IN_ADDR_B_in[20] = (CAS_IN_ADDR_B[20] !== 1'bz) && CAS_IN_ADDR_B_delay[20]; // rv 0
assign CAS_IN_ADDR_B_in[21] = (CAS_IN_ADDR_B[21] !== 1'bz) && CAS_IN_ADDR_B_delay[21]; // rv 0
assign CAS_IN_ADDR_B_in[22] = (CAS_IN_ADDR_B[22] !== 1'bz) && CAS_IN_ADDR_B_delay[22]; // rv 0
assign CAS_IN_ADDR_B_in[2] = (CAS_IN_ADDR_B[2] !== 1'bz) && CAS_IN_ADDR_B_delay[2]; // rv 0
assign CAS_IN_ADDR_B_in[3] = (CAS_IN_ADDR_B[3] !== 1'bz) && CAS_IN_ADDR_B_delay[3]; // rv 0
assign CAS_IN_ADDR_B_in[4] = (CAS_IN_ADDR_B[4] !== 1'bz) && CAS_IN_ADDR_B_delay[4]; // rv 0
assign CAS_IN_ADDR_B_in[5] = (CAS_IN_ADDR_B[5] !== 1'bz) && CAS_IN_ADDR_B_delay[5]; // rv 0
assign CAS_IN_ADDR_B_in[6] = (CAS_IN_ADDR_B[6] !== 1'bz) && CAS_IN_ADDR_B_delay[6]; // rv 0
assign CAS_IN_ADDR_B_in[7] = (CAS_IN_ADDR_B[7] !== 1'bz) && CAS_IN_ADDR_B_delay[7]; // rv 0
assign CAS_IN_ADDR_B_in[8] = (CAS_IN_ADDR_B[8] !== 1'bz) && CAS_IN_ADDR_B_delay[8]; // rv 0
assign CAS_IN_ADDR_B_in[9] = (CAS_IN_ADDR_B[9] !== 1'bz) && CAS_IN_ADDR_B_delay[9]; // rv 0
assign CAS_IN_BWE_A_in[0] = (CAS_IN_BWE_A[0] !== 1'bz) && CAS_IN_BWE_A_delay[0]; // rv 0
assign CAS_IN_BWE_A_in[1] = (CAS_IN_BWE_A[1] !== 1'bz) && CAS_IN_BWE_A_delay[1]; // rv 0
assign CAS_IN_BWE_A_in[2] = (CAS_IN_BWE_A[2] !== 1'bz) && CAS_IN_BWE_A_delay[2]; // rv 0
assign CAS_IN_BWE_A_in[3] = (CAS_IN_BWE_A[3] !== 1'bz) && CAS_IN_BWE_A_delay[3]; // rv 0
assign CAS_IN_BWE_A_in[4] = (CAS_IN_BWE_A[4] !== 1'bz) && CAS_IN_BWE_A_delay[4]; // rv 0
assign CAS_IN_BWE_A_in[5] = (CAS_IN_BWE_A[5] !== 1'bz) && CAS_IN_BWE_A_delay[5]; // rv 0
assign CAS_IN_BWE_A_in[6] = (CAS_IN_BWE_A[6] !== 1'bz) && CAS_IN_BWE_A_delay[6]; // rv 0
assign CAS_IN_BWE_A_in[7] = (CAS_IN_BWE_A[7] !== 1'bz) && CAS_IN_BWE_A_delay[7]; // rv 0
assign CAS_IN_BWE_A_in[8] = (CAS_IN_BWE_A[8] !== 1'bz) && CAS_IN_BWE_A_delay[8]; // rv 0
assign CAS_IN_BWE_B_in[0] = (CAS_IN_BWE_B[0] !== 1'bz) && CAS_IN_BWE_B_delay[0]; // rv 0
assign CAS_IN_BWE_B_in[1] = (CAS_IN_BWE_B[1] !== 1'bz) && CAS_IN_BWE_B_delay[1]; // rv 0
assign CAS_IN_BWE_B_in[2] = (CAS_IN_BWE_B[2] !== 1'bz) && CAS_IN_BWE_B_delay[2]; // rv 0
assign CAS_IN_BWE_B_in[3] = (CAS_IN_BWE_B[3] !== 1'bz) && CAS_IN_BWE_B_delay[3]; // rv 0
assign CAS_IN_BWE_B_in[4] = (CAS_IN_BWE_B[4] !== 1'bz) && CAS_IN_BWE_B_delay[4]; // rv 0
assign CAS_IN_BWE_B_in[5] = (CAS_IN_BWE_B[5] !== 1'bz) && CAS_IN_BWE_B_delay[5]; // rv 0
assign CAS_IN_BWE_B_in[6] = (CAS_IN_BWE_B[6] !== 1'bz) && CAS_IN_BWE_B_delay[6]; // rv 0
assign CAS_IN_BWE_B_in[7] = (CAS_IN_BWE_B[7] !== 1'bz) && CAS_IN_BWE_B_delay[7]; // rv 0
assign CAS_IN_BWE_B_in[8] = (CAS_IN_BWE_B[8] !== 1'bz) && CAS_IN_BWE_B_delay[8]; // rv 0
assign CAS_IN_DBITERR_A_in = (CAS_IN_DBITERR_A !== 1'bz) && CAS_IN_DBITERR_A_delay; // rv 0
assign CAS_IN_DBITERR_B_in = (CAS_IN_DBITERR_B !== 1'bz) && CAS_IN_DBITERR_B_delay; // rv 0
assign CAS_IN_DIN_A_in[0] = (CAS_IN_DIN_A[0] !== 1'bz) && CAS_IN_DIN_A_delay[0]; // rv 0
assign CAS_IN_DIN_A_in[10] = (CAS_IN_DIN_A[10] !== 1'bz) && CAS_IN_DIN_A_delay[10]; // rv 0
assign CAS_IN_DIN_A_in[11] = (CAS_IN_DIN_A[11] !== 1'bz) && CAS_IN_DIN_A_delay[11]; // rv 0
assign CAS_IN_DIN_A_in[12] = (CAS_IN_DIN_A[12] !== 1'bz) && CAS_IN_DIN_A_delay[12]; // rv 0
assign CAS_IN_DIN_A_in[13] = (CAS_IN_DIN_A[13] !== 1'bz) && CAS_IN_DIN_A_delay[13]; // rv 0
assign CAS_IN_DIN_A_in[14] = (CAS_IN_DIN_A[14] !== 1'bz) && CAS_IN_DIN_A_delay[14]; // rv 0
assign CAS_IN_DIN_A_in[15] = (CAS_IN_DIN_A[15] !== 1'bz) && CAS_IN_DIN_A_delay[15]; // rv 0
assign CAS_IN_DIN_A_in[16] = (CAS_IN_DIN_A[16] !== 1'bz) && CAS_IN_DIN_A_delay[16]; // rv 0
assign CAS_IN_DIN_A_in[17] = (CAS_IN_DIN_A[17] !== 1'bz) && CAS_IN_DIN_A_delay[17]; // rv 0
assign CAS_IN_DIN_A_in[18] = (CAS_IN_DIN_A[18] !== 1'bz) && CAS_IN_DIN_A_delay[18]; // rv 0
assign CAS_IN_DIN_A_in[19] = (CAS_IN_DIN_A[19] !== 1'bz) && CAS_IN_DIN_A_delay[19]; // rv 0
assign CAS_IN_DIN_A_in[1] = (CAS_IN_DIN_A[1] !== 1'bz) && CAS_IN_DIN_A_delay[1]; // rv 0
assign CAS_IN_DIN_A_in[20] = (CAS_IN_DIN_A[20] !== 1'bz) && CAS_IN_DIN_A_delay[20]; // rv 0
assign CAS_IN_DIN_A_in[21] = (CAS_IN_DIN_A[21] !== 1'bz) && CAS_IN_DIN_A_delay[21]; // rv 0
assign CAS_IN_DIN_A_in[22] = (CAS_IN_DIN_A[22] !== 1'bz) && CAS_IN_DIN_A_delay[22]; // rv 0
assign CAS_IN_DIN_A_in[23] = (CAS_IN_DIN_A[23] !== 1'bz) && CAS_IN_DIN_A_delay[23]; // rv 0
assign CAS_IN_DIN_A_in[24] = (CAS_IN_DIN_A[24] !== 1'bz) && CAS_IN_DIN_A_delay[24]; // rv 0
assign CAS_IN_DIN_A_in[25] = (CAS_IN_DIN_A[25] !== 1'bz) && CAS_IN_DIN_A_delay[25]; // rv 0
assign CAS_IN_DIN_A_in[26] = (CAS_IN_DIN_A[26] !== 1'bz) && CAS_IN_DIN_A_delay[26]; // rv 0
assign CAS_IN_DIN_A_in[27] = (CAS_IN_DIN_A[27] !== 1'bz) && CAS_IN_DIN_A_delay[27]; // rv 0
assign CAS_IN_DIN_A_in[28] = (CAS_IN_DIN_A[28] !== 1'bz) && CAS_IN_DIN_A_delay[28]; // rv 0
assign CAS_IN_DIN_A_in[29] = (CAS_IN_DIN_A[29] !== 1'bz) && CAS_IN_DIN_A_delay[29]; // rv 0
assign CAS_IN_DIN_A_in[2] = (CAS_IN_DIN_A[2] !== 1'bz) && CAS_IN_DIN_A_delay[2]; // rv 0
assign CAS_IN_DIN_A_in[30] = (CAS_IN_DIN_A[30] !== 1'bz) && CAS_IN_DIN_A_delay[30]; // rv 0
assign CAS_IN_DIN_A_in[31] = (CAS_IN_DIN_A[31] !== 1'bz) && CAS_IN_DIN_A_delay[31]; // rv 0
assign CAS_IN_DIN_A_in[32] = (CAS_IN_DIN_A[32] !== 1'bz) && CAS_IN_DIN_A_delay[32]; // rv 0
assign CAS_IN_DIN_A_in[33] = (CAS_IN_DIN_A[33] !== 1'bz) && CAS_IN_DIN_A_delay[33]; // rv 0
assign CAS_IN_DIN_A_in[34] = (CAS_IN_DIN_A[34] !== 1'bz) && CAS_IN_DIN_A_delay[34]; // rv 0
assign CAS_IN_DIN_A_in[35] = (CAS_IN_DIN_A[35] !== 1'bz) && CAS_IN_DIN_A_delay[35]; // rv 0
assign CAS_IN_DIN_A_in[36] = (CAS_IN_DIN_A[36] !== 1'bz) && CAS_IN_DIN_A_delay[36]; // rv 0
assign CAS_IN_DIN_A_in[37] = (CAS_IN_DIN_A[37] !== 1'bz) && CAS_IN_DIN_A_delay[37]; // rv 0
assign CAS_IN_DIN_A_in[38] = (CAS_IN_DIN_A[38] !== 1'bz) && CAS_IN_DIN_A_delay[38]; // rv 0
assign CAS_IN_DIN_A_in[39] = (CAS_IN_DIN_A[39] !== 1'bz) && CAS_IN_DIN_A_delay[39]; // rv 0
assign CAS_IN_DIN_A_in[3] = (CAS_IN_DIN_A[3] !== 1'bz) && CAS_IN_DIN_A_delay[3]; // rv 0
assign CAS_IN_DIN_A_in[40] = (CAS_IN_DIN_A[40] !== 1'bz) && CAS_IN_DIN_A_delay[40]; // rv 0
assign CAS_IN_DIN_A_in[41] = (CAS_IN_DIN_A[41] !== 1'bz) && CAS_IN_DIN_A_delay[41]; // rv 0
assign CAS_IN_DIN_A_in[42] = (CAS_IN_DIN_A[42] !== 1'bz) && CAS_IN_DIN_A_delay[42]; // rv 0
assign CAS_IN_DIN_A_in[43] = (CAS_IN_DIN_A[43] !== 1'bz) && CAS_IN_DIN_A_delay[43]; // rv 0
assign CAS_IN_DIN_A_in[44] = (CAS_IN_DIN_A[44] !== 1'bz) && CAS_IN_DIN_A_delay[44]; // rv 0
assign CAS_IN_DIN_A_in[45] = (CAS_IN_DIN_A[45] !== 1'bz) && CAS_IN_DIN_A_delay[45]; // rv 0
assign CAS_IN_DIN_A_in[46] = (CAS_IN_DIN_A[46] !== 1'bz) && CAS_IN_DIN_A_delay[46]; // rv 0
assign CAS_IN_DIN_A_in[47] = (CAS_IN_DIN_A[47] !== 1'bz) && CAS_IN_DIN_A_delay[47]; // rv 0
assign CAS_IN_DIN_A_in[48] = (CAS_IN_DIN_A[48] !== 1'bz) && CAS_IN_DIN_A_delay[48]; // rv 0
assign CAS_IN_DIN_A_in[49] = (CAS_IN_DIN_A[49] !== 1'bz) && CAS_IN_DIN_A_delay[49]; // rv 0
assign CAS_IN_DIN_A_in[4] = (CAS_IN_DIN_A[4] !== 1'bz) && CAS_IN_DIN_A_delay[4]; // rv 0
assign CAS_IN_DIN_A_in[50] = (CAS_IN_DIN_A[50] !== 1'bz) && CAS_IN_DIN_A_delay[50]; // rv 0
assign CAS_IN_DIN_A_in[51] = (CAS_IN_DIN_A[51] !== 1'bz) && CAS_IN_DIN_A_delay[51]; // rv 0
assign CAS_IN_DIN_A_in[52] = (CAS_IN_DIN_A[52] !== 1'bz) && CAS_IN_DIN_A_delay[52]; // rv 0
assign CAS_IN_DIN_A_in[53] = (CAS_IN_DIN_A[53] !== 1'bz) && CAS_IN_DIN_A_delay[53]; // rv 0
assign CAS_IN_DIN_A_in[54] = (CAS_IN_DIN_A[54] !== 1'bz) && CAS_IN_DIN_A_delay[54]; // rv 0
assign CAS_IN_DIN_A_in[55] = (CAS_IN_DIN_A[55] !== 1'bz) && CAS_IN_DIN_A_delay[55]; // rv 0
assign CAS_IN_DIN_A_in[56] = (CAS_IN_DIN_A[56] !== 1'bz) && CAS_IN_DIN_A_delay[56]; // rv 0
assign CAS_IN_DIN_A_in[57] = (CAS_IN_DIN_A[57] !== 1'bz) && CAS_IN_DIN_A_delay[57]; // rv 0
assign CAS_IN_DIN_A_in[58] = (CAS_IN_DIN_A[58] !== 1'bz) && CAS_IN_DIN_A_delay[58]; // rv 0
assign CAS_IN_DIN_A_in[59] = (CAS_IN_DIN_A[59] !== 1'bz) && CAS_IN_DIN_A_delay[59]; // rv 0
assign CAS_IN_DIN_A_in[5] = (CAS_IN_DIN_A[5] !== 1'bz) && CAS_IN_DIN_A_delay[5]; // rv 0
assign CAS_IN_DIN_A_in[60] = (CAS_IN_DIN_A[60] !== 1'bz) && CAS_IN_DIN_A_delay[60]; // rv 0
assign CAS_IN_DIN_A_in[61] = (CAS_IN_DIN_A[61] !== 1'bz) && CAS_IN_DIN_A_delay[61]; // rv 0
assign CAS_IN_DIN_A_in[62] = (CAS_IN_DIN_A[62] !== 1'bz) && CAS_IN_DIN_A_delay[62]; // rv 0
assign CAS_IN_DIN_A_in[63] = (CAS_IN_DIN_A[63] !== 1'bz) && CAS_IN_DIN_A_delay[63]; // rv 0
assign CAS_IN_DIN_A_in[64] = (CAS_IN_DIN_A[64] !== 1'bz) && CAS_IN_DIN_A_delay[64]; // rv 0
assign CAS_IN_DIN_A_in[65] = (CAS_IN_DIN_A[65] !== 1'bz) && CAS_IN_DIN_A_delay[65]; // rv 0
assign CAS_IN_DIN_A_in[66] = (CAS_IN_DIN_A[66] !== 1'bz) && CAS_IN_DIN_A_delay[66]; // rv 0
assign CAS_IN_DIN_A_in[67] = (CAS_IN_DIN_A[67] !== 1'bz) && CAS_IN_DIN_A_delay[67]; // rv 0
assign CAS_IN_DIN_A_in[68] = (CAS_IN_DIN_A[68] !== 1'bz) && CAS_IN_DIN_A_delay[68]; // rv 0
assign CAS_IN_DIN_A_in[69] = (CAS_IN_DIN_A[69] !== 1'bz) && CAS_IN_DIN_A_delay[69]; // rv 0
assign CAS_IN_DIN_A_in[6] = (CAS_IN_DIN_A[6] !== 1'bz) && CAS_IN_DIN_A_delay[6]; // rv 0
assign CAS_IN_DIN_A_in[70] = (CAS_IN_DIN_A[70] !== 1'bz) && CAS_IN_DIN_A_delay[70]; // rv 0
assign CAS_IN_DIN_A_in[71] = (CAS_IN_DIN_A[71] !== 1'bz) && CAS_IN_DIN_A_delay[71]; // rv 0
assign CAS_IN_DIN_A_in[7] = (CAS_IN_DIN_A[7] !== 1'bz) && CAS_IN_DIN_A_delay[7]; // rv 0
assign CAS_IN_DIN_A_in[8] = (CAS_IN_DIN_A[8] !== 1'bz) && CAS_IN_DIN_A_delay[8]; // rv 0
assign CAS_IN_DIN_A_in[9] = (CAS_IN_DIN_A[9] !== 1'bz) && CAS_IN_DIN_A_delay[9]; // rv 0
assign CAS_IN_DIN_B_in[0] = (CAS_IN_DIN_B[0] !== 1'bz) && CAS_IN_DIN_B_delay[0]; // rv 0
assign CAS_IN_DIN_B_in[10] = (CAS_IN_DIN_B[10] !== 1'bz) && CAS_IN_DIN_B_delay[10]; // rv 0
assign CAS_IN_DIN_B_in[11] = (CAS_IN_DIN_B[11] !== 1'bz) && CAS_IN_DIN_B_delay[11]; // rv 0
assign CAS_IN_DIN_B_in[12] = (CAS_IN_DIN_B[12] !== 1'bz) && CAS_IN_DIN_B_delay[12]; // rv 0
assign CAS_IN_DIN_B_in[13] = (CAS_IN_DIN_B[13] !== 1'bz) && CAS_IN_DIN_B_delay[13]; // rv 0
assign CAS_IN_DIN_B_in[14] = (CAS_IN_DIN_B[14] !== 1'bz) && CAS_IN_DIN_B_delay[14]; // rv 0
assign CAS_IN_DIN_B_in[15] = (CAS_IN_DIN_B[15] !== 1'bz) && CAS_IN_DIN_B_delay[15]; // rv 0
assign CAS_IN_DIN_B_in[16] = (CAS_IN_DIN_B[16] !== 1'bz) && CAS_IN_DIN_B_delay[16]; // rv 0
assign CAS_IN_DIN_B_in[17] = (CAS_IN_DIN_B[17] !== 1'bz) && CAS_IN_DIN_B_delay[17]; // rv 0
assign CAS_IN_DIN_B_in[18] = (CAS_IN_DIN_B[18] !== 1'bz) && CAS_IN_DIN_B_delay[18]; // rv 0
assign CAS_IN_DIN_B_in[19] = (CAS_IN_DIN_B[19] !== 1'bz) && CAS_IN_DIN_B_delay[19]; // rv 0
assign CAS_IN_DIN_B_in[1] = (CAS_IN_DIN_B[1] !== 1'bz) && CAS_IN_DIN_B_delay[1]; // rv 0
assign CAS_IN_DIN_B_in[20] = (CAS_IN_DIN_B[20] !== 1'bz) && CAS_IN_DIN_B_delay[20]; // rv 0
assign CAS_IN_DIN_B_in[21] = (CAS_IN_DIN_B[21] !== 1'bz) && CAS_IN_DIN_B_delay[21]; // rv 0
assign CAS_IN_DIN_B_in[22] = (CAS_IN_DIN_B[22] !== 1'bz) && CAS_IN_DIN_B_delay[22]; // rv 0
assign CAS_IN_DIN_B_in[23] = (CAS_IN_DIN_B[23] !== 1'bz) && CAS_IN_DIN_B_delay[23]; // rv 0
assign CAS_IN_DIN_B_in[24] = (CAS_IN_DIN_B[24] !== 1'bz) && CAS_IN_DIN_B_delay[24]; // rv 0
assign CAS_IN_DIN_B_in[25] = (CAS_IN_DIN_B[25] !== 1'bz) && CAS_IN_DIN_B_delay[25]; // rv 0
assign CAS_IN_DIN_B_in[26] = (CAS_IN_DIN_B[26] !== 1'bz) && CAS_IN_DIN_B_delay[26]; // rv 0
assign CAS_IN_DIN_B_in[27] = (CAS_IN_DIN_B[27] !== 1'bz) && CAS_IN_DIN_B_delay[27]; // rv 0
assign CAS_IN_DIN_B_in[28] = (CAS_IN_DIN_B[28] !== 1'bz) && CAS_IN_DIN_B_delay[28]; // rv 0
assign CAS_IN_DIN_B_in[29] = (CAS_IN_DIN_B[29] !== 1'bz) && CAS_IN_DIN_B_delay[29]; // rv 0
assign CAS_IN_DIN_B_in[2] = (CAS_IN_DIN_B[2] !== 1'bz) && CAS_IN_DIN_B_delay[2]; // rv 0
assign CAS_IN_DIN_B_in[30] = (CAS_IN_DIN_B[30] !== 1'bz) && CAS_IN_DIN_B_delay[30]; // rv 0
assign CAS_IN_DIN_B_in[31] = (CAS_IN_DIN_B[31] !== 1'bz) && CAS_IN_DIN_B_delay[31]; // rv 0
assign CAS_IN_DIN_B_in[32] = (CAS_IN_DIN_B[32] !== 1'bz) && CAS_IN_DIN_B_delay[32]; // rv 0
assign CAS_IN_DIN_B_in[33] = (CAS_IN_DIN_B[33] !== 1'bz) && CAS_IN_DIN_B_delay[33]; // rv 0
assign CAS_IN_DIN_B_in[34] = (CAS_IN_DIN_B[34] !== 1'bz) && CAS_IN_DIN_B_delay[34]; // rv 0
assign CAS_IN_DIN_B_in[35] = (CAS_IN_DIN_B[35] !== 1'bz) && CAS_IN_DIN_B_delay[35]; // rv 0
assign CAS_IN_DIN_B_in[36] = (CAS_IN_DIN_B[36] !== 1'bz) && CAS_IN_DIN_B_delay[36]; // rv 0
assign CAS_IN_DIN_B_in[37] = (CAS_IN_DIN_B[37] !== 1'bz) && CAS_IN_DIN_B_delay[37]; // rv 0
assign CAS_IN_DIN_B_in[38] = (CAS_IN_DIN_B[38] !== 1'bz) && CAS_IN_DIN_B_delay[38]; // rv 0
assign CAS_IN_DIN_B_in[39] = (CAS_IN_DIN_B[39] !== 1'bz) && CAS_IN_DIN_B_delay[39]; // rv 0
assign CAS_IN_DIN_B_in[3] = (CAS_IN_DIN_B[3] !== 1'bz) && CAS_IN_DIN_B_delay[3]; // rv 0
assign CAS_IN_DIN_B_in[40] = (CAS_IN_DIN_B[40] !== 1'bz) && CAS_IN_DIN_B_delay[40]; // rv 0
assign CAS_IN_DIN_B_in[41] = (CAS_IN_DIN_B[41] !== 1'bz) && CAS_IN_DIN_B_delay[41]; // rv 0
assign CAS_IN_DIN_B_in[42] = (CAS_IN_DIN_B[42] !== 1'bz) && CAS_IN_DIN_B_delay[42]; // rv 0
assign CAS_IN_DIN_B_in[43] = (CAS_IN_DIN_B[43] !== 1'bz) && CAS_IN_DIN_B_delay[43]; // rv 0
assign CAS_IN_DIN_B_in[44] = (CAS_IN_DIN_B[44] !== 1'bz) && CAS_IN_DIN_B_delay[44]; // rv 0
assign CAS_IN_DIN_B_in[45] = (CAS_IN_DIN_B[45] !== 1'bz) && CAS_IN_DIN_B_delay[45]; // rv 0
assign CAS_IN_DIN_B_in[46] = (CAS_IN_DIN_B[46] !== 1'bz) && CAS_IN_DIN_B_delay[46]; // rv 0
assign CAS_IN_DIN_B_in[47] = (CAS_IN_DIN_B[47] !== 1'bz) && CAS_IN_DIN_B_delay[47]; // rv 0
assign CAS_IN_DIN_B_in[48] = (CAS_IN_DIN_B[48] !== 1'bz) && CAS_IN_DIN_B_delay[48]; // rv 0
assign CAS_IN_DIN_B_in[49] = (CAS_IN_DIN_B[49] !== 1'bz) && CAS_IN_DIN_B_delay[49]; // rv 0
assign CAS_IN_DIN_B_in[4] = (CAS_IN_DIN_B[4] !== 1'bz) && CAS_IN_DIN_B_delay[4]; // rv 0
assign CAS_IN_DIN_B_in[50] = (CAS_IN_DIN_B[50] !== 1'bz) && CAS_IN_DIN_B_delay[50]; // rv 0
assign CAS_IN_DIN_B_in[51] = (CAS_IN_DIN_B[51] !== 1'bz) && CAS_IN_DIN_B_delay[51]; // rv 0
assign CAS_IN_DIN_B_in[52] = (CAS_IN_DIN_B[52] !== 1'bz) && CAS_IN_DIN_B_delay[52]; // rv 0
assign CAS_IN_DIN_B_in[53] = (CAS_IN_DIN_B[53] !== 1'bz) && CAS_IN_DIN_B_delay[53]; // rv 0
assign CAS_IN_DIN_B_in[54] = (CAS_IN_DIN_B[54] !== 1'bz) && CAS_IN_DIN_B_delay[54]; // rv 0
assign CAS_IN_DIN_B_in[55] = (CAS_IN_DIN_B[55] !== 1'bz) && CAS_IN_DIN_B_delay[55]; // rv 0
assign CAS_IN_DIN_B_in[56] = (CAS_IN_DIN_B[56] !== 1'bz) && CAS_IN_DIN_B_delay[56]; // rv 0
assign CAS_IN_DIN_B_in[57] = (CAS_IN_DIN_B[57] !== 1'bz) && CAS_IN_DIN_B_delay[57]; // rv 0
assign CAS_IN_DIN_B_in[58] = (CAS_IN_DIN_B[58] !== 1'bz) && CAS_IN_DIN_B_delay[58]; // rv 0
assign CAS_IN_DIN_B_in[59] = (CAS_IN_DIN_B[59] !== 1'bz) && CAS_IN_DIN_B_delay[59]; // rv 0
assign CAS_IN_DIN_B_in[5] = (CAS_IN_DIN_B[5] !== 1'bz) && CAS_IN_DIN_B_delay[5]; // rv 0
assign CAS_IN_DIN_B_in[60] = (CAS_IN_DIN_B[60] !== 1'bz) && CAS_IN_DIN_B_delay[60]; // rv 0
assign CAS_IN_DIN_B_in[61] = (CAS_IN_DIN_B[61] !== 1'bz) && CAS_IN_DIN_B_delay[61]; // rv 0
assign CAS_IN_DIN_B_in[62] = (CAS_IN_DIN_B[62] !== 1'bz) && CAS_IN_DIN_B_delay[62]; // rv 0
assign CAS_IN_DIN_B_in[63] = (CAS_IN_DIN_B[63] !== 1'bz) && CAS_IN_DIN_B_delay[63]; // rv 0
assign CAS_IN_DIN_B_in[64] = (CAS_IN_DIN_B[64] !== 1'bz) && CAS_IN_DIN_B_delay[64]; // rv 0
assign CAS_IN_DIN_B_in[65] = (CAS_IN_DIN_B[65] !== 1'bz) && CAS_IN_DIN_B_delay[65]; // rv 0
assign CAS_IN_DIN_B_in[66] = (CAS_IN_DIN_B[66] !== 1'bz) && CAS_IN_DIN_B_delay[66]; // rv 0
assign CAS_IN_DIN_B_in[67] = (CAS_IN_DIN_B[67] !== 1'bz) && CAS_IN_DIN_B_delay[67]; // rv 0
assign CAS_IN_DIN_B_in[68] = (CAS_IN_DIN_B[68] !== 1'bz) && CAS_IN_DIN_B_delay[68]; // rv 0
assign CAS_IN_DIN_B_in[69] = (CAS_IN_DIN_B[69] !== 1'bz) && CAS_IN_DIN_B_delay[69]; // rv 0
assign CAS_IN_DIN_B_in[6] = (CAS_IN_DIN_B[6] !== 1'bz) && CAS_IN_DIN_B_delay[6]; // rv 0
assign CAS_IN_DIN_B_in[70] = (CAS_IN_DIN_B[70] !== 1'bz) && CAS_IN_DIN_B_delay[70]; // rv 0
assign CAS_IN_DIN_B_in[71] = (CAS_IN_DIN_B[71] !== 1'bz) && CAS_IN_DIN_B_delay[71]; // rv 0
assign CAS_IN_DIN_B_in[7] = (CAS_IN_DIN_B[7] !== 1'bz) && CAS_IN_DIN_B_delay[7]; // rv 0
assign CAS_IN_DIN_B_in[8] = (CAS_IN_DIN_B[8] !== 1'bz) && CAS_IN_DIN_B_delay[8]; // rv 0
assign CAS_IN_DIN_B_in[9] = (CAS_IN_DIN_B[9] !== 1'bz) && CAS_IN_DIN_B_delay[9]; // rv 0
assign CAS_IN_DOUT_A_in[0] = (CAS_IN_DOUT_A[0] !== 1'bz) && CAS_IN_DOUT_A_delay[0]; // rv 0
assign CAS_IN_DOUT_A_in[10] = (CAS_IN_DOUT_A[10] !== 1'bz) && CAS_IN_DOUT_A_delay[10]; // rv 0
assign CAS_IN_DOUT_A_in[11] = (CAS_IN_DOUT_A[11] !== 1'bz) && CAS_IN_DOUT_A_delay[11]; // rv 0
assign CAS_IN_DOUT_A_in[12] = (CAS_IN_DOUT_A[12] !== 1'bz) && CAS_IN_DOUT_A_delay[12]; // rv 0
assign CAS_IN_DOUT_A_in[13] = (CAS_IN_DOUT_A[13] !== 1'bz) && CAS_IN_DOUT_A_delay[13]; // rv 0
assign CAS_IN_DOUT_A_in[14] = (CAS_IN_DOUT_A[14] !== 1'bz) && CAS_IN_DOUT_A_delay[14]; // rv 0
assign CAS_IN_DOUT_A_in[15] = (CAS_IN_DOUT_A[15] !== 1'bz) && CAS_IN_DOUT_A_delay[15]; // rv 0
assign CAS_IN_DOUT_A_in[16] = (CAS_IN_DOUT_A[16] !== 1'bz) && CAS_IN_DOUT_A_delay[16]; // rv 0
assign CAS_IN_DOUT_A_in[17] = (CAS_IN_DOUT_A[17] !== 1'bz) && CAS_IN_DOUT_A_delay[17]; // rv 0
assign CAS_IN_DOUT_A_in[18] = (CAS_IN_DOUT_A[18] !== 1'bz) && CAS_IN_DOUT_A_delay[18]; // rv 0
assign CAS_IN_DOUT_A_in[19] = (CAS_IN_DOUT_A[19] !== 1'bz) && CAS_IN_DOUT_A_delay[19]; // rv 0
assign CAS_IN_DOUT_A_in[1] = (CAS_IN_DOUT_A[1] !== 1'bz) && CAS_IN_DOUT_A_delay[1]; // rv 0
assign CAS_IN_DOUT_A_in[20] = (CAS_IN_DOUT_A[20] !== 1'bz) && CAS_IN_DOUT_A_delay[20]; // rv 0
assign CAS_IN_DOUT_A_in[21] = (CAS_IN_DOUT_A[21] !== 1'bz) && CAS_IN_DOUT_A_delay[21]; // rv 0
assign CAS_IN_DOUT_A_in[22] = (CAS_IN_DOUT_A[22] !== 1'bz) && CAS_IN_DOUT_A_delay[22]; // rv 0
assign CAS_IN_DOUT_A_in[23] = (CAS_IN_DOUT_A[23] !== 1'bz) && CAS_IN_DOUT_A_delay[23]; // rv 0
assign CAS_IN_DOUT_A_in[24] = (CAS_IN_DOUT_A[24] !== 1'bz) && CAS_IN_DOUT_A_delay[24]; // rv 0
assign CAS_IN_DOUT_A_in[25] = (CAS_IN_DOUT_A[25] !== 1'bz) && CAS_IN_DOUT_A_delay[25]; // rv 0
assign CAS_IN_DOUT_A_in[26] = (CAS_IN_DOUT_A[26] !== 1'bz) && CAS_IN_DOUT_A_delay[26]; // rv 0
assign CAS_IN_DOUT_A_in[27] = (CAS_IN_DOUT_A[27] !== 1'bz) && CAS_IN_DOUT_A_delay[27]; // rv 0
assign CAS_IN_DOUT_A_in[28] = (CAS_IN_DOUT_A[28] !== 1'bz) && CAS_IN_DOUT_A_delay[28]; // rv 0
assign CAS_IN_DOUT_A_in[29] = (CAS_IN_DOUT_A[29] !== 1'bz) && CAS_IN_DOUT_A_delay[29]; // rv 0
assign CAS_IN_DOUT_A_in[2] = (CAS_IN_DOUT_A[2] !== 1'bz) && CAS_IN_DOUT_A_delay[2]; // rv 0
assign CAS_IN_DOUT_A_in[30] = (CAS_IN_DOUT_A[30] !== 1'bz) && CAS_IN_DOUT_A_delay[30]; // rv 0
assign CAS_IN_DOUT_A_in[31] = (CAS_IN_DOUT_A[31] !== 1'bz) && CAS_IN_DOUT_A_delay[31]; // rv 0
assign CAS_IN_DOUT_A_in[32] = (CAS_IN_DOUT_A[32] !== 1'bz) && CAS_IN_DOUT_A_delay[32]; // rv 0
assign CAS_IN_DOUT_A_in[33] = (CAS_IN_DOUT_A[33] !== 1'bz) && CAS_IN_DOUT_A_delay[33]; // rv 0
assign CAS_IN_DOUT_A_in[34] = (CAS_IN_DOUT_A[34] !== 1'bz) && CAS_IN_DOUT_A_delay[34]; // rv 0
assign CAS_IN_DOUT_A_in[35] = (CAS_IN_DOUT_A[35] !== 1'bz) && CAS_IN_DOUT_A_delay[35]; // rv 0
assign CAS_IN_DOUT_A_in[36] = (CAS_IN_DOUT_A[36] !== 1'bz) && CAS_IN_DOUT_A_delay[36]; // rv 0
assign CAS_IN_DOUT_A_in[37] = (CAS_IN_DOUT_A[37] !== 1'bz) && CAS_IN_DOUT_A_delay[37]; // rv 0
assign CAS_IN_DOUT_A_in[38] = (CAS_IN_DOUT_A[38] !== 1'bz) && CAS_IN_DOUT_A_delay[38]; // rv 0
assign CAS_IN_DOUT_A_in[39] = (CAS_IN_DOUT_A[39] !== 1'bz) && CAS_IN_DOUT_A_delay[39]; // rv 0
assign CAS_IN_DOUT_A_in[3] = (CAS_IN_DOUT_A[3] !== 1'bz) && CAS_IN_DOUT_A_delay[3]; // rv 0
assign CAS_IN_DOUT_A_in[40] = (CAS_IN_DOUT_A[40] !== 1'bz) && CAS_IN_DOUT_A_delay[40]; // rv 0
assign CAS_IN_DOUT_A_in[41] = (CAS_IN_DOUT_A[41] !== 1'bz) && CAS_IN_DOUT_A_delay[41]; // rv 0
assign CAS_IN_DOUT_A_in[42] = (CAS_IN_DOUT_A[42] !== 1'bz) && CAS_IN_DOUT_A_delay[42]; // rv 0
assign CAS_IN_DOUT_A_in[43] = (CAS_IN_DOUT_A[43] !== 1'bz) && CAS_IN_DOUT_A_delay[43]; // rv 0
assign CAS_IN_DOUT_A_in[44] = (CAS_IN_DOUT_A[44] !== 1'bz) && CAS_IN_DOUT_A_delay[44]; // rv 0
assign CAS_IN_DOUT_A_in[45] = (CAS_IN_DOUT_A[45] !== 1'bz) && CAS_IN_DOUT_A_delay[45]; // rv 0
assign CAS_IN_DOUT_A_in[46] = (CAS_IN_DOUT_A[46] !== 1'bz) && CAS_IN_DOUT_A_delay[46]; // rv 0
assign CAS_IN_DOUT_A_in[47] = (CAS_IN_DOUT_A[47] !== 1'bz) && CAS_IN_DOUT_A_delay[47]; // rv 0
assign CAS_IN_DOUT_A_in[48] = (CAS_IN_DOUT_A[48] !== 1'bz) && CAS_IN_DOUT_A_delay[48]; // rv 0
assign CAS_IN_DOUT_A_in[49] = (CAS_IN_DOUT_A[49] !== 1'bz) && CAS_IN_DOUT_A_delay[49]; // rv 0
assign CAS_IN_DOUT_A_in[4] = (CAS_IN_DOUT_A[4] !== 1'bz) && CAS_IN_DOUT_A_delay[4]; // rv 0
assign CAS_IN_DOUT_A_in[50] = (CAS_IN_DOUT_A[50] !== 1'bz) && CAS_IN_DOUT_A_delay[50]; // rv 0
assign CAS_IN_DOUT_A_in[51] = (CAS_IN_DOUT_A[51] !== 1'bz) && CAS_IN_DOUT_A_delay[51]; // rv 0
assign CAS_IN_DOUT_A_in[52] = (CAS_IN_DOUT_A[52] !== 1'bz) && CAS_IN_DOUT_A_delay[52]; // rv 0
assign CAS_IN_DOUT_A_in[53] = (CAS_IN_DOUT_A[53] !== 1'bz) && CAS_IN_DOUT_A_delay[53]; // rv 0
assign CAS_IN_DOUT_A_in[54] = (CAS_IN_DOUT_A[54] !== 1'bz) && CAS_IN_DOUT_A_delay[54]; // rv 0
assign CAS_IN_DOUT_A_in[55] = (CAS_IN_DOUT_A[55] !== 1'bz) && CAS_IN_DOUT_A_delay[55]; // rv 0
assign CAS_IN_DOUT_A_in[56] = (CAS_IN_DOUT_A[56] !== 1'bz) && CAS_IN_DOUT_A_delay[56]; // rv 0
assign CAS_IN_DOUT_A_in[57] = (CAS_IN_DOUT_A[57] !== 1'bz) && CAS_IN_DOUT_A_delay[57]; // rv 0
assign CAS_IN_DOUT_A_in[58] = (CAS_IN_DOUT_A[58] !== 1'bz) && CAS_IN_DOUT_A_delay[58]; // rv 0
assign CAS_IN_DOUT_A_in[59] = (CAS_IN_DOUT_A[59] !== 1'bz) && CAS_IN_DOUT_A_delay[59]; // rv 0
assign CAS_IN_DOUT_A_in[5] = (CAS_IN_DOUT_A[5] !== 1'bz) && CAS_IN_DOUT_A_delay[5]; // rv 0
assign CAS_IN_DOUT_A_in[60] = (CAS_IN_DOUT_A[60] !== 1'bz) && CAS_IN_DOUT_A_delay[60]; // rv 0
assign CAS_IN_DOUT_A_in[61] = (CAS_IN_DOUT_A[61] !== 1'bz) && CAS_IN_DOUT_A_delay[61]; // rv 0
assign CAS_IN_DOUT_A_in[62] = (CAS_IN_DOUT_A[62] !== 1'bz) && CAS_IN_DOUT_A_delay[62]; // rv 0
assign CAS_IN_DOUT_A_in[63] = (CAS_IN_DOUT_A[63] !== 1'bz) && CAS_IN_DOUT_A_delay[63]; // rv 0
assign CAS_IN_DOUT_A_in[64] = (CAS_IN_DOUT_A[64] !== 1'bz) && CAS_IN_DOUT_A_delay[64]; // rv 0
assign CAS_IN_DOUT_A_in[65] = (CAS_IN_DOUT_A[65] !== 1'bz) && CAS_IN_DOUT_A_delay[65]; // rv 0
assign CAS_IN_DOUT_A_in[66] = (CAS_IN_DOUT_A[66] !== 1'bz) && CAS_IN_DOUT_A_delay[66]; // rv 0
assign CAS_IN_DOUT_A_in[67] = (CAS_IN_DOUT_A[67] !== 1'bz) && CAS_IN_DOUT_A_delay[67]; // rv 0
assign CAS_IN_DOUT_A_in[68] = (CAS_IN_DOUT_A[68] !== 1'bz) && CAS_IN_DOUT_A_delay[68]; // rv 0
assign CAS_IN_DOUT_A_in[69] = (CAS_IN_DOUT_A[69] !== 1'bz) && CAS_IN_DOUT_A_delay[69]; // rv 0
assign CAS_IN_DOUT_A_in[6] = (CAS_IN_DOUT_A[6] !== 1'bz) && CAS_IN_DOUT_A_delay[6]; // rv 0
assign CAS_IN_DOUT_A_in[70] = (CAS_IN_DOUT_A[70] !== 1'bz) && CAS_IN_DOUT_A_delay[70]; // rv 0
assign CAS_IN_DOUT_A_in[71] = (CAS_IN_DOUT_A[71] !== 1'bz) && CAS_IN_DOUT_A_delay[71]; // rv 0
assign CAS_IN_DOUT_A_in[7] = (CAS_IN_DOUT_A[7] !== 1'bz) && CAS_IN_DOUT_A_delay[7]; // rv 0
assign CAS_IN_DOUT_A_in[8] = (CAS_IN_DOUT_A[8] !== 1'bz) && CAS_IN_DOUT_A_delay[8]; // rv 0
assign CAS_IN_DOUT_A_in[9] = (CAS_IN_DOUT_A[9] !== 1'bz) && CAS_IN_DOUT_A_delay[9]; // rv 0
assign CAS_IN_DOUT_B_in[0] = (CAS_IN_DOUT_B[0] !== 1'bz) && CAS_IN_DOUT_B_delay[0]; // rv 0
assign CAS_IN_DOUT_B_in[10] = (CAS_IN_DOUT_B[10] !== 1'bz) && CAS_IN_DOUT_B_delay[10]; // rv 0
assign CAS_IN_DOUT_B_in[11] = (CAS_IN_DOUT_B[11] !== 1'bz) && CAS_IN_DOUT_B_delay[11]; // rv 0
assign CAS_IN_DOUT_B_in[12] = (CAS_IN_DOUT_B[12] !== 1'bz) && CAS_IN_DOUT_B_delay[12]; // rv 0
assign CAS_IN_DOUT_B_in[13] = (CAS_IN_DOUT_B[13] !== 1'bz) && CAS_IN_DOUT_B_delay[13]; // rv 0
assign CAS_IN_DOUT_B_in[14] = (CAS_IN_DOUT_B[14] !== 1'bz) && CAS_IN_DOUT_B_delay[14]; // rv 0
assign CAS_IN_DOUT_B_in[15] = (CAS_IN_DOUT_B[15] !== 1'bz) && CAS_IN_DOUT_B_delay[15]; // rv 0
assign CAS_IN_DOUT_B_in[16] = (CAS_IN_DOUT_B[16] !== 1'bz) && CAS_IN_DOUT_B_delay[16]; // rv 0
assign CAS_IN_DOUT_B_in[17] = (CAS_IN_DOUT_B[17] !== 1'bz) && CAS_IN_DOUT_B_delay[17]; // rv 0
assign CAS_IN_DOUT_B_in[18] = (CAS_IN_DOUT_B[18] !== 1'bz) && CAS_IN_DOUT_B_delay[18]; // rv 0
assign CAS_IN_DOUT_B_in[19] = (CAS_IN_DOUT_B[19] !== 1'bz) && CAS_IN_DOUT_B_delay[19]; // rv 0
assign CAS_IN_DOUT_B_in[1] = (CAS_IN_DOUT_B[1] !== 1'bz) && CAS_IN_DOUT_B_delay[1]; // rv 0
assign CAS_IN_DOUT_B_in[20] = (CAS_IN_DOUT_B[20] !== 1'bz) && CAS_IN_DOUT_B_delay[20]; // rv 0
assign CAS_IN_DOUT_B_in[21] = (CAS_IN_DOUT_B[21] !== 1'bz) && CAS_IN_DOUT_B_delay[21]; // rv 0
assign CAS_IN_DOUT_B_in[22] = (CAS_IN_DOUT_B[22] !== 1'bz) && CAS_IN_DOUT_B_delay[22]; // rv 0
assign CAS_IN_DOUT_B_in[23] = (CAS_IN_DOUT_B[23] !== 1'bz) && CAS_IN_DOUT_B_delay[23]; // rv 0
assign CAS_IN_DOUT_B_in[24] = (CAS_IN_DOUT_B[24] !== 1'bz) && CAS_IN_DOUT_B_delay[24]; // rv 0
assign CAS_IN_DOUT_B_in[25] = (CAS_IN_DOUT_B[25] !== 1'bz) && CAS_IN_DOUT_B_delay[25]; // rv 0
assign CAS_IN_DOUT_B_in[26] = (CAS_IN_DOUT_B[26] !== 1'bz) && CAS_IN_DOUT_B_delay[26]; // rv 0
assign CAS_IN_DOUT_B_in[27] = (CAS_IN_DOUT_B[27] !== 1'bz) && CAS_IN_DOUT_B_delay[27]; // rv 0
assign CAS_IN_DOUT_B_in[28] = (CAS_IN_DOUT_B[28] !== 1'bz) && CAS_IN_DOUT_B_delay[28]; // rv 0
assign CAS_IN_DOUT_B_in[29] = (CAS_IN_DOUT_B[29] !== 1'bz) && CAS_IN_DOUT_B_delay[29]; // rv 0
assign CAS_IN_DOUT_B_in[2] = (CAS_IN_DOUT_B[2] !== 1'bz) && CAS_IN_DOUT_B_delay[2]; // rv 0
assign CAS_IN_DOUT_B_in[30] = (CAS_IN_DOUT_B[30] !== 1'bz) && CAS_IN_DOUT_B_delay[30]; // rv 0
assign CAS_IN_DOUT_B_in[31] = (CAS_IN_DOUT_B[31] !== 1'bz) && CAS_IN_DOUT_B_delay[31]; // rv 0
assign CAS_IN_DOUT_B_in[32] = (CAS_IN_DOUT_B[32] !== 1'bz) && CAS_IN_DOUT_B_delay[32]; // rv 0
assign CAS_IN_DOUT_B_in[33] = (CAS_IN_DOUT_B[33] !== 1'bz) && CAS_IN_DOUT_B_delay[33]; // rv 0
assign CAS_IN_DOUT_B_in[34] = (CAS_IN_DOUT_B[34] !== 1'bz) && CAS_IN_DOUT_B_delay[34]; // rv 0
assign CAS_IN_DOUT_B_in[35] = (CAS_IN_DOUT_B[35] !== 1'bz) && CAS_IN_DOUT_B_delay[35]; // rv 0
assign CAS_IN_DOUT_B_in[36] = (CAS_IN_DOUT_B[36] !== 1'bz) && CAS_IN_DOUT_B_delay[36]; // rv 0
assign CAS_IN_DOUT_B_in[37] = (CAS_IN_DOUT_B[37] !== 1'bz) && CAS_IN_DOUT_B_delay[37]; // rv 0
assign CAS_IN_DOUT_B_in[38] = (CAS_IN_DOUT_B[38] !== 1'bz) && CAS_IN_DOUT_B_delay[38]; // rv 0
assign CAS_IN_DOUT_B_in[39] = (CAS_IN_DOUT_B[39] !== 1'bz) && CAS_IN_DOUT_B_delay[39]; // rv 0
assign CAS_IN_DOUT_B_in[3] = (CAS_IN_DOUT_B[3] !== 1'bz) && CAS_IN_DOUT_B_delay[3]; // rv 0
assign CAS_IN_DOUT_B_in[40] = (CAS_IN_DOUT_B[40] !== 1'bz) && CAS_IN_DOUT_B_delay[40]; // rv 0
assign CAS_IN_DOUT_B_in[41] = (CAS_IN_DOUT_B[41] !== 1'bz) && CAS_IN_DOUT_B_delay[41]; // rv 0
assign CAS_IN_DOUT_B_in[42] = (CAS_IN_DOUT_B[42] !== 1'bz) && CAS_IN_DOUT_B_delay[42]; // rv 0
assign CAS_IN_DOUT_B_in[43] = (CAS_IN_DOUT_B[43] !== 1'bz) && CAS_IN_DOUT_B_delay[43]; // rv 0
assign CAS_IN_DOUT_B_in[44] = (CAS_IN_DOUT_B[44] !== 1'bz) && CAS_IN_DOUT_B_delay[44]; // rv 0
assign CAS_IN_DOUT_B_in[45] = (CAS_IN_DOUT_B[45] !== 1'bz) && CAS_IN_DOUT_B_delay[45]; // rv 0
assign CAS_IN_DOUT_B_in[46] = (CAS_IN_DOUT_B[46] !== 1'bz) && CAS_IN_DOUT_B_delay[46]; // rv 0
assign CAS_IN_DOUT_B_in[47] = (CAS_IN_DOUT_B[47] !== 1'bz) && CAS_IN_DOUT_B_delay[47]; // rv 0
assign CAS_IN_DOUT_B_in[48] = (CAS_IN_DOUT_B[48] !== 1'bz) && CAS_IN_DOUT_B_delay[48]; // rv 0
assign CAS_IN_DOUT_B_in[49] = (CAS_IN_DOUT_B[49] !== 1'bz) && CAS_IN_DOUT_B_delay[49]; // rv 0
assign CAS_IN_DOUT_B_in[4] = (CAS_IN_DOUT_B[4] !== 1'bz) && CAS_IN_DOUT_B_delay[4]; // rv 0
assign CAS_IN_DOUT_B_in[50] = (CAS_IN_DOUT_B[50] !== 1'bz) && CAS_IN_DOUT_B_delay[50]; // rv 0
assign CAS_IN_DOUT_B_in[51] = (CAS_IN_DOUT_B[51] !== 1'bz) && CAS_IN_DOUT_B_delay[51]; // rv 0
assign CAS_IN_DOUT_B_in[52] = (CAS_IN_DOUT_B[52] !== 1'bz) && CAS_IN_DOUT_B_delay[52]; // rv 0
assign CAS_IN_DOUT_B_in[53] = (CAS_IN_DOUT_B[53] !== 1'bz) && CAS_IN_DOUT_B_delay[53]; // rv 0
assign CAS_IN_DOUT_B_in[54] = (CAS_IN_DOUT_B[54] !== 1'bz) && CAS_IN_DOUT_B_delay[54]; // rv 0
assign CAS_IN_DOUT_B_in[55] = (CAS_IN_DOUT_B[55] !== 1'bz) && CAS_IN_DOUT_B_delay[55]; // rv 0
assign CAS_IN_DOUT_B_in[56] = (CAS_IN_DOUT_B[56] !== 1'bz) && CAS_IN_DOUT_B_delay[56]; // rv 0
assign CAS_IN_DOUT_B_in[57] = (CAS_IN_DOUT_B[57] !== 1'bz) && CAS_IN_DOUT_B_delay[57]; // rv 0
assign CAS_IN_DOUT_B_in[58] = (CAS_IN_DOUT_B[58] !== 1'bz) && CAS_IN_DOUT_B_delay[58]; // rv 0
assign CAS_IN_DOUT_B_in[59] = (CAS_IN_DOUT_B[59] !== 1'bz) && CAS_IN_DOUT_B_delay[59]; // rv 0
assign CAS_IN_DOUT_B_in[5] = (CAS_IN_DOUT_B[5] !== 1'bz) && CAS_IN_DOUT_B_delay[5]; // rv 0
assign CAS_IN_DOUT_B_in[60] = (CAS_IN_DOUT_B[60] !== 1'bz) && CAS_IN_DOUT_B_delay[60]; // rv 0
assign CAS_IN_DOUT_B_in[61] = (CAS_IN_DOUT_B[61] !== 1'bz) && CAS_IN_DOUT_B_delay[61]; // rv 0
assign CAS_IN_DOUT_B_in[62] = (CAS_IN_DOUT_B[62] !== 1'bz) && CAS_IN_DOUT_B_delay[62]; // rv 0
assign CAS_IN_DOUT_B_in[63] = (CAS_IN_DOUT_B[63] !== 1'bz) && CAS_IN_DOUT_B_delay[63]; // rv 0
assign CAS_IN_DOUT_B_in[64] = (CAS_IN_DOUT_B[64] !== 1'bz) && CAS_IN_DOUT_B_delay[64]; // rv 0
assign CAS_IN_DOUT_B_in[65] = (CAS_IN_DOUT_B[65] !== 1'bz) && CAS_IN_DOUT_B_delay[65]; // rv 0
assign CAS_IN_DOUT_B_in[66] = (CAS_IN_DOUT_B[66] !== 1'bz) && CAS_IN_DOUT_B_delay[66]; // rv 0
assign CAS_IN_DOUT_B_in[67] = (CAS_IN_DOUT_B[67] !== 1'bz) && CAS_IN_DOUT_B_delay[67]; // rv 0
assign CAS_IN_DOUT_B_in[68] = (CAS_IN_DOUT_B[68] !== 1'bz) && CAS_IN_DOUT_B_delay[68]; // rv 0
assign CAS_IN_DOUT_B_in[69] = (CAS_IN_DOUT_B[69] !== 1'bz) && CAS_IN_DOUT_B_delay[69]; // rv 0
assign CAS_IN_DOUT_B_in[6] = (CAS_IN_DOUT_B[6] !== 1'bz) && CAS_IN_DOUT_B_delay[6]; // rv 0
assign CAS_IN_DOUT_B_in[70] = (CAS_IN_DOUT_B[70] !== 1'bz) && CAS_IN_DOUT_B_delay[70]; // rv 0
assign CAS_IN_DOUT_B_in[71] = (CAS_IN_DOUT_B[71] !== 1'bz) && CAS_IN_DOUT_B_delay[71]; // rv 0
assign CAS_IN_DOUT_B_in[7] = (CAS_IN_DOUT_B[7] !== 1'bz) && CAS_IN_DOUT_B_delay[7]; // rv 0
assign CAS_IN_DOUT_B_in[8] = (CAS_IN_DOUT_B[8] !== 1'bz) && CAS_IN_DOUT_B_delay[8]; // rv 0
assign CAS_IN_DOUT_B_in[9] = (CAS_IN_DOUT_B[9] !== 1'bz) && CAS_IN_DOUT_B_delay[9]; // rv 0
assign CAS_IN_EN_A_in = (CAS_IN_EN_A !== 1'bz) && CAS_IN_EN_A_delay; // rv 0
assign CAS_IN_EN_B_in = (CAS_IN_EN_B !== 1'bz) && CAS_IN_EN_B_delay; // rv 0
assign CAS_IN_RDACCESS_A_in = (CAS_IN_RDACCESS_A !== 1'bz) && CAS_IN_RDACCESS_A_delay; // rv 0
assign CAS_IN_RDACCESS_B_in = (CAS_IN_RDACCESS_B !== 1'bz) && CAS_IN_RDACCESS_B_delay; // rv 0
assign CAS_IN_RDB_WR_A_in = (CAS_IN_RDB_WR_A !== 1'bz) && CAS_IN_RDB_WR_A_delay; // rv 0
assign CAS_IN_RDB_WR_B_in = (CAS_IN_RDB_WR_B !== 1'bz) && CAS_IN_RDB_WR_B_delay; // rv 0
assign CAS_IN_SBITERR_A_in = (CAS_IN_SBITERR_A !== 1'bz) && CAS_IN_SBITERR_A_delay; // rv 0
assign CAS_IN_SBITERR_B_in = (CAS_IN_SBITERR_B !== 1'bz) && CAS_IN_SBITERR_B_delay; // rv 0
assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0
assign DIN_A_in = DIN_A_delay;
assign DIN_B_in = DIN_B_delay;
assign EN_A_in = (EN_A !== 1'bz) && (EN_A_delay ^ IS_EN_A_INVERTED_REG); // rv 0
assign EN_B_in = (EN_B !== 1'bz) && (EN_B_delay ^ IS_EN_B_INVERTED_REG); // rv 0
assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A_delay; // rv 0
assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B_delay; // rv 0
assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A_delay; // rv 0
assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B_delay; // rv 0
assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A_delay; // rv 1
assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B_delay; // rv 1
assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A_delay; // rv 1
assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B_delay; // rv 1
assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A_delay ^ IS_RDB_WR_A_INVERTED_REG); // rv 0
assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B_delay ^ IS_RDB_WR_B_INVERTED_REG); // rv 0
assign RST_A_in = (RST_A !== 1'bz) && (RST_A_delay ^ IS_RST_A_INVERTED_REG); // rv 0
assign RST_B_in = (RST_B !== 1'bz) && (RST_B_delay ^ IS_RST_B_INVERTED_REG); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0
`else
assign ADDR_A_in = ADDR_A;
assign ADDR_B_in = ADDR_B;
assign BWE_A_in[0] = (BWE_A[0] === 1'bz) || BWE_A[0]; // rv 1
assign BWE_A_in[1] = (BWE_A[1] === 1'bz) || BWE_A[1]; // rv 1
assign BWE_A_in[2] = (BWE_A[2] === 1'bz) || BWE_A[2]; // rv 1
assign BWE_A_in[3] = (BWE_A[3] === 1'bz) || BWE_A[3]; // rv 1
assign BWE_A_in[4] = (BWE_A[4] === 1'bz) || BWE_A[4]; // rv 1
assign BWE_A_in[5] = (BWE_A[5] === 1'bz) || BWE_A[5]; // rv 1
assign BWE_A_in[6] = (BWE_A[6] === 1'bz) || BWE_A[6]; // rv 1
assign BWE_A_in[7] = (BWE_A[7] === 1'bz) || BWE_A[7]; // rv 1
assign BWE_A_in[8] = (BWE_A[8] === 1'bz) || BWE_A[8]; // rv 1
assign BWE_B_in[0] = (BWE_B[0] === 1'bz) || BWE_B[0]; // rv 1
assign BWE_B_in[1] = (BWE_B[1] === 1'bz) || BWE_B[1]; // rv 1
assign BWE_B_in[2] = (BWE_B[2] === 1'bz) || BWE_B[2]; // rv 1
assign BWE_B_in[3] = (BWE_B[3] === 1'bz) || BWE_B[3]; // rv 1
assign BWE_B_in[4] = (BWE_B[4] === 1'bz) || BWE_B[4]; // rv 1
assign BWE_B_in[5] = (BWE_B[5] === 1'bz) || BWE_B[5]; // rv 1
assign BWE_B_in[6] = (BWE_B[6] === 1'bz) || BWE_B[6]; // rv 1
assign BWE_B_in[7] = (BWE_B[7] === 1'bz) || BWE_B[7]; // rv 1
assign BWE_B_in[8] = (BWE_B[8] === 1'bz) || BWE_B[8]; // rv 1
assign CAS_IN_ADDR_A_in[0] = (CAS_IN_ADDR_A[0] !== 1'bz) && CAS_IN_ADDR_A[0]; // rv 0
assign CAS_IN_ADDR_A_in[10] = (CAS_IN_ADDR_A[10] !== 1'bz) && CAS_IN_ADDR_A[10]; // rv 0
assign CAS_IN_ADDR_A_in[11] = (CAS_IN_ADDR_A[11] !== 1'bz) && CAS_IN_ADDR_A[11]; // rv 0
assign CAS_IN_ADDR_A_in[12] = (CAS_IN_ADDR_A[12] !== 1'bz) && CAS_IN_ADDR_A[12]; // rv 0
assign CAS_IN_ADDR_A_in[13] = (CAS_IN_ADDR_A[13] !== 1'bz) && CAS_IN_ADDR_A[13]; // rv 0
assign CAS_IN_ADDR_A_in[14] = (CAS_IN_ADDR_A[14] !== 1'bz) && CAS_IN_ADDR_A[14]; // rv 0
assign CAS_IN_ADDR_A_in[15] = (CAS_IN_ADDR_A[15] !== 1'bz) && CAS_IN_ADDR_A[15]; // rv 0
assign CAS_IN_ADDR_A_in[16] = (CAS_IN_ADDR_A[16] !== 1'bz) && CAS_IN_ADDR_A[16]; // rv 0
assign CAS_IN_ADDR_A_in[17] = (CAS_IN_ADDR_A[17] !== 1'bz) && CAS_IN_ADDR_A[17]; // rv 0
assign CAS_IN_ADDR_A_in[18] = (CAS_IN_ADDR_A[18] !== 1'bz) && CAS_IN_ADDR_A[18]; // rv 0
assign CAS_IN_ADDR_A_in[19] = (CAS_IN_ADDR_A[19] !== 1'bz) && CAS_IN_ADDR_A[19]; // rv 0
assign CAS_IN_ADDR_A_in[1] = (CAS_IN_ADDR_A[1] !== 1'bz) && CAS_IN_ADDR_A[1]; // rv 0
assign CAS_IN_ADDR_A_in[20] = (CAS_IN_ADDR_A[20] !== 1'bz) && CAS_IN_ADDR_A[20]; // rv 0
assign CAS_IN_ADDR_A_in[21] = (CAS_IN_ADDR_A[21] !== 1'bz) && CAS_IN_ADDR_A[21]; // rv 0
assign CAS_IN_ADDR_A_in[22] = (CAS_IN_ADDR_A[22] !== 1'bz) && CAS_IN_ADDR_A[22]; // rv 0
assign CAS_IN_ADDR_A_in[2] = (CAS_IN_ADDR_A[2] !== 1'bz) && CAS_IN_ADDR_A[2]; // rv 0
assign CAS_IN_ADDR_A_in[3] = (CAS_IN_ADDR_A[3] !== 1'bz) && CAS_IN_ADDR_A[3]; // rv 0
assign CAS_IN_ADDR_A_in[4] = (CAS_IN_ADDR_A[4] !== 1'bz) && CAS_IN_ADDR_A[4]; // rv 0
assign CAS_IN_ADDR_A_in[5] = (CAS_IN_ADDR_A[5] !== 1'bz) && CAS_IN_ADDR_A[5]; // rv 0
assign CAS_IN_ADDR_A_in[6] = (CAS_IN_ADDR_A[6] !== 1'bz) && CAS_IN_ADDR_A[6]; // rv 0
assign CAS_IN_ADDR_A_in[7] = (CAS_IN_ADDR_A[7] !== 1'bz) && CAS_IN_ADDR_A[7]; // rv 0
assign CAS_IN_ADDR_A_in[8] = (CAS_IN_ADDR_A[8] !== 1'bz) && CAS_IN_ADDR_A[8]; // rv 0
assign CAS_IN_ADDR_A_in[9] = (CAS_IN_ADDR_A[9] !== 1'bz) && CAS_IN_ADDR_A[9]; // rv 0
assign CAS_IN_ADDR_B_in[0] = (CAS_IN_ADDR_B[0] !== 1'bz) && CAS_IN_ADDR_B[0]; // rv 0
assign CAS_IN_ADDR_B_in[10] = (CAS_IN_ADDR_B[10] !== 1'bz) && CAS_IN_ADDR_B[10]; // rv 0
assign CAS_IN_ADDR_B_in[11] = (CAS_IN_ADDR_B[11] !== 1'bz) && CAS_IN_ADDR_B[11]; // rv 0
assign CAS_IN_ADDR_B_in[12] = (CAS_IN_ADDR_B[12] !== 1'bz) && CAS_IN_ADDR_B[12]; // rv 0
assign CAS_IN_ADDR_B_in[13] = (CAS_IN_ADDR_B[13] !== 1'bz) && CAS_IN_ADDR_B[13]; // rv 0
assign CAS_IN_ADDR_B_in[14] = (CAS_IN_ADDR_B[14] !== 1'bz) && CAS_IN_ADDR_B[14]; // rv 0
assign CAS_IN_ADDR_B_in[15] = (CAS_IN_ADDR_B[15] !== 1'bz) && CAS_IN_ADDR_B[15]; // rv 0
assign CAS_IN_ADDR_B_in[16] = (CAS_IN_ADDR_B[16] !== 1'bz) && CAS_IN_ADDR_B[16]; // rv 0
assign CAS_IN_ADDR_B_in[17] = (CAS_IN_ADDR_B[17] !== 1'bz) && CAS_IN_ADDR_B[17]; // rv 0
assign CAS_IN_ADDR_B_in[18] = (CAS_IN_ADDR_B[18] !== 1'bz) && CAS_IN_ADDR_B[18]; // rv 0
assign CAS_IN_ADDR_B_in[19] = (CAS_IN_ADDR_B[19] !== 1'bz) && CAS_IN_ADDR_B[19]; // rv 0
assign CAS_IN_ADDR_B_in[1] = (CAS_IN_ADDR_B[1] !== 1'bz) && CAS_IN_ADDR_B[1]; // rv 0
assign CAS_IN_ADDR_B_in[20] = (CAS_IN_ADDR_B[20] !== 1'bz) && CAS_IN_ADDR_B[20]; // rv 0
assign CAS_IN_ADDR_B_in[21] = (CAS_IN_ADDR_B[21] !== 1'bz) && CAS_IN_ADDR_B[21]; // rv 0
assign CAS_IN_ADDR_B_in[22] = (CAS_IN_ADDR_B[22] !== 1'bz) && CAS_IN_ADDR_B[22]; // rv 0
assign CAS_IN_ADDR_B_in[2] = (CAS_IN_ADDR_B[2] !== 1'bz) && CAS_IN_ADDR_B[2]; // rv 0
assign CAS_IN_ADDR_B_in[3] = (CAS_IN_ADDR_B[3] !== 1'bz) && CAS_IN_ADDR_B[3]; // rv 0
assign CAS_IN_ADDR_B_in[4] = (CAS_IN_ADDR_B[4] !== 1'bz) && CAS_IN_ADDR_B[4]; // rv 0
assign CAS_IN_ADDR_B_in[5] = (CAS_IN_ADDR_B[5] !== 1'bz) && CAS_IN_ADDR_B[5]; // rv 0
assign CAS_IN_ADDR_B_in[6] = (CAS_IN_ADDR_B[6] !== 1'bz) && CAS_IN_ADDR_B[6]; // rv 0
assign CAS_IN_ADDR_B_in[7] = (CAS_IN_ADDR_B[7] !== 1'bz) && CAS_IN_ADDR_B[7]; // rv 0
assign CAS_IN_ADDR_B_in[8] = (CAS_IN_ADDR_B[8] !== 1'bz) && CAS_IN_ADDR_B[8]; // rv 0
assign CAS_IN_ADDR_B_in[9] = (CAS_IN_ADDR_B[9] !== 1'bz) && CAS_IN_ADDR_B[9]; // rv 0
assign CAS_IN_BWE_A_in[0] = (CAS_IN_BWE_A[0] !== 1'bz) && CAS_IN_BWE_A[0]; // rv 0
assign CAS_IN_BWE_A_in[1] = (CAS_IN_BWE_A[1] !== 1'bz) && CAS_IN_BWE_A[1]; // rv 0
assign CAS_IN_BWE_A_in[2] = (CAS_IN_BWE_A[2] !== 1'bz) && CAS_IN_BWE_A[2]; // rv 0
assign CAS_IN_BWE_A_in[3] = (CAS_IN_BWE_A[3] !== 1'bz) && CAS_IN_BWE_A[3]; // rv 0
assign CAS_IN_BWE_A_in[4] = (CAS_IN_BWE_A[4] !== 1'bz) && CAS_IN_BWE_A[4]; // rv 0
assign CAS_IN_BWE_A_in[5] = (CAS_IN_BWE_A[5] !== 1'bz) && CAS_IN_BWE_A[5]; // rv 0
assign CAS_IN_BWE_A_in[6] = (CAS_IN_BWE_A[6] !== 1'bz) && CAS_IN_BWE_A[6]; // rv 0
assign CAS_IN_BWE_A_in[7] = (CAS_IN_BWE_A[7] !== 1'bz) && CAS_IN_BWE_A[7]; // rv 0
assign CAS_IN_BWE_A_in[8] = (CAS_IN_BWE_A[8] !== 1'bz) && CAS_IN_BWE_A[8]; // rv 0
assign CAS_IN_BWE_B_in[0] = (CAS_IN_BWE_B[0] !== 1'bz) && CAS_IN_BWE_B[0]; // rv 0
assign CAS_IN_BWE_B_in[1] = (CAS_IN_BWE_B[1] !== 1'bz) && CAS_IN_BWE_B[1]; // rv 0
assign CAS_IN_BWE_B_in[2] = (CAS_IN_BWE_B[2] !== 1'bz) && CAS_IN_BWE_B[2]; // rv 0
assign CAS_IN_BWE_B_in[3] = (CAS_IN_BWE_B[3] !== 1'bz) && CAS_IN_BWE_B[3]; // rv 0
assign CAS_IN_BWE_B_in[4] = (CAS_IN_BWE_B[4] !== 1'bz) && CAS_IN_BWE_B[4]; // rv 0
assign CAS_IN_BWE_B_in[5] = (CAS_IN_BWE_B[5] !== 1'bz) && CAS_IN_BWE_B[5]; // rv 0
assign CAS_IN_BWE_B_in[6] = (CAS_IN_BWE_B[6] !== 1'bz) && CAS_IN_BWE_B[6]; // rv 0
assign CAS_IN_BWE_B_in[7] = (CAS_IN_BWE_B[7] !== 1'bz) && CAS_IN_BWE_B[7]; // rv 0
assign CAS_IN_BWE_B_in[8] = (CAS_IN_BWE_B[8] !== 1'bz) && CAS_IN_BWE_B[8]; // rv 0
assign CAS_IN_DBITERR_A_in = (CAS_IN_DBITERR_A !== 1'bz) && CAS_IN_DBITERR_A; // rv 0
assign CAS_IN_DBITERR_B_in = (CAS_IN_DBITERR_B !== 1'bz) && CAS_IN_DBITERR_B; // rv 0
assign CAS_IN_DIN_A_in[0] = (CAS_IN_DIN_A[0] !== 1'bz) && CAS_IN_DIN_A[0]; // rv 0
assign CAS_IN_DIN_A_in[10] = (CAS_IN_DIN_A[10] !== 1'bz) && CAS_IN_DIN_A[10]; // rv 0
assign CAS_IN_DIN_A_in[11] = (CAS_IN_DIN_A[11] !== 1'bz) && CAS_IN_DIN_A[11]; // rv 0
assign CAS_IN_DIN_A_in[12] = (CAS_IN_DIN_A[12] !== 1'bz) && CAS_IN_DIN_A[12]; // rv 0
assign CAS_IN_DIN_A_in[13] = (CAS_IN_DIN_A[13] !== 1'bz) && CAS_IN_DIN_A[13]; // rv 0
assign CAS_IN_DIN_A_in[14] = (CAS_IN_DIN_A[14] !== 1'bz) && CAS_IN_DIN_A[14]; // rv 0
assign CAS_IN_DIN_A_in[15] = (CAS_IN_DIN_A[15] !== 1'bz) && CAS_IN_DIN_A[15]; // rv 0
assign CAS_IN_DIN_A_in[16] = (CAS_IN_DIN_A[16] !== 1'bz) && CAS_IN_DIN_A[16]; // rv 0
assign CAS_IN_DIN_A_in[17] = (CAS_IN_DIN_A[17] !== 1'bz) && CAS_IN_DIN_A[17]; // rv 0
assign CAS_IN_DIN_A_in[18] = (CAS_IN_DIN_A[18] !== 1'bz) && CAS_IN_DIN_A[18]; // rv 0
assign CAS_IN_DIN_A_in[19] = (CAS_IN_DIN_A[19] !== 1'bz) && CAS_IN_DIN_A[19]; // rv 0
assign CAS_IN_DIN_A_in[1] = (CAS_IN_DIN_A[1] !== 1'bz) && CAS_IN_DIN_A[1]; // rv 0
assign CAS_IN_DIN_A_in[20] = (CAS_IN_DIN_A[20] !== 1'bz) && CAS_IN_DIN_A[20]; // rv 0
assign CAS_IN_DIN_A_in[21] = (CAS_IN_DIN_A[21] !== 1'bz) && CAS_IN_DIN_A[21]; // rv 0
assign CAS_IN_DIN_A_in[22] = (CAS_IN_DIN_A[22] !== 1'bz) && CAS_IN_DIN_A[22]; // rv 0
assign CAS_IN_DIN_A_in[23] = (CAS_IN_DIN_A[23] !== 1'bz) && CAS_IN_DIN_A[23]; // rv 0
assign CAS_IN_DIN_A_in[24] = (CAS_IN_DIN_A[24] !== 1'bz) && CAS_IN_DIN_A[24]; // rv 0
assign CAS_IN_DIN_A_in[25] = (CAS_IN_DIN_A[25] !== 1'bz) && CAS_IN_DIN_A[25]; // rv 0
assign CAS_IN_DIN_A_in[26] = (CAS_IN_DIN_A[26] !== 1'bz) && CAS_IN_DIN_A[26]; // rv 0
assign CAS_IN_DIN_A_in[27] = (CAS_IN_DIN_A[27] !== 1'bz) && CAS_IN_DIN_A[27]; // rv 0
assign CAS_IN_DIN_A_in[28] = (CAS_IN_DIN_A[28] !== 1'bz) && CAS_IN_DIN_A[28]; // rv 0
assign CAS_IN_DIN_A_in[29] = (CAS_IN_DIN_A[29] !== 1'bz) && CAS_IN_DIN_A[29]; // rv 0
assign CAS_IN_DIN_A_in[2] = (CAS_IN_DIN_A[2] !== 1'bz) && CAS_IN_DIN_A[2]; // rv 0
assign CAS_IN_DIN_A_in[30] = (CAS_IN_DIN_A[30] !== 1'bz) && CAS_IN_DIN_A[30]; // rv 0
assign CAS_IN_DIN_A_in[31] = (CAS_IN_DIN_A[31] !== 1'bz) && CAS_IN_DIN_A[31]; // rv 0
assign CAS_IN_DIN_A_in[32] = (CAS_IN_DIN_A[32] !== 1'bz) && CAS_IN_DIN_A[32]; // rv 0
assign CAS_IN_DIN_A_in[33] = (CAS_IN_DIN_A[33] !== 1'bz) && CAS_IN_DIN_A[33]; // rv 0
assign CAS_IN_DIN_A_in[34] = (CAS_IN_DIN_A[34] !== 1'bz) && CAS_IN_DIN_A[34]; // rv 0
assign CAS_IN_DIN_A_in[35] = (CAS_IN_DIN_A[35] !== 1'bz) && CAS_IN_DIN_A[35]; // rv 0
assign CAS_IN_DIN_A_in[36] = (CAS_IN_DIN_A[36] !== 1'bz) && CAS_IN_DIN_A[36]; // rv 0
assign CAS_IN_DIN_A_in[37] = (CAS_IN_DIN_A[37] !== 1'bz) && CAS_IN_DIN_A[37]; // rv 0
assign CAS_IN_DIN_A_in[38] = (CAS_IN_DIN_A[38] !== 1'bz) && CAS_IN_DIN_A[38]; // rv 0
assign CAS_IN_DIN_A_in[39] = (CAS_IN_DIN_A[39] !== 1'bz) && CAS_IN_DIN_A[39]; // rv 0
assign CAS_IN_DIN_A_in[3] = (CAS_IN_DIN_A[3] !== 1'bz) && CAS_IN_DIN_A[3]; // rv 0
assign CAS_IN_DIN_A_in[40] = (CAS_IN_DIN_A[40] !== 1'bz) && CAS_IN_DIN_A[40]; // rv 0
assign CAS_IN_DIN_A_in[41] = (CAS_IN_DIN_A[41] !== 1'bz) && CAS_IN_DIN_A[41]; // rv 0
assign CAS_IN_DIN_A_in[42] = (CAS_IN_DIN_A[42] !== 1'bz) && CAS_IN_DIN_A[42]; // rv 0
assign CAS_IN_DIN_A_in[43] = (CAS_IN_DIN_A[43] !== 1'bz) && CAS_IN_DIN_A[43]; // rv 0
assign CAS_IN_DIN_A_in[44] = (CAS_IN_DIN_A[44] !== 1'bz) && CAS_IN_DIN_A[44]; // rv 0
assign CAS_IN_DIN_A_in[45] = (CAS_IN_DIN_A[45] !== 1'bz) && CAS_IN_DIN_A[45]; // rv 0
assign CAS_IN_DIN_A_in[46] = (CAS_IN_DIN_A[46] !== 1'bz) && CAS_IN_DIN_A[46]; // rv 0
assign CAS_IN_DIN_A_in[47] = (CAS_IN_DIN_A[47] !== 1'bz) && CAS_IN_DIN_A[47]; // rv 0
assign CAS_IN_DIN_A_in[48] = (CAS_IN_DIN_A[48] !== 1'bz) && CAS_IN_DIN_A[48]; // rv 0
assign CAS_IN_DIN_A_in[49] = (CAS_IN_DIN_A[49] !== 1'bz) && CAS_IN_DIN_A[49]; // rv 0
assign CAS_IN_DIN_A_in[4] = (CAS_IN_DIN_A[4] !== 1'bz) && CAS_IN_DIN_A[4]; // rv 0
assign CAS_IN_DIN_A_in[50] = (CAS_IN_DIN_A[50] !== 1'bz) && CAS_IN_DIN_A[50]; // rv 0
assign CAS_IN_DIN_A_in[51] = (CAS_IN_DIN_A[51] !== 1'bz) && CAS_IN_DIN_A[51]; // rv 0
assign CAS_IN_DIN_A_in[52] = (CAS_IN_DIN_A[52] !== 1'bz) && CAS_IN_DIN_A[52]; // rv 0
assign CAS_IN_DIN_A_in[53] = (CAS_IN_DIN_A[53] !== 1'bz) && CAS_IN_DIN_A[53]; // rv 0
assign CAS_IN_DIN_A_in[54] = (CAS_IN_DIN_A[54] !== 1'bz) && CAS_IN_DIN_A[54]; // rv 0
assign CAS_IN_DIN_A_in[55] = (CAS_IN_DIN_A[55] !== 1'bz) && CAS_IN_DIN_A[55]; // rv 0
assign CAS_IN_DIN_A_in[56] = (CAS_IN_DIN_A[56] !== 1'bz) && CAS_IN_DIN_A[56]; // rv 0
assign CAS_IN_DIN_A_in[57] = (CAS_IN_DIN_A[57] !== 1'bz) && CAS_IN_DIN_A[57]; // rv 0
assign CAS_IN_DIN_A_in[58] = (CAS_IN_DIN_A[58] !== 1'bz) && CAS_IN_DIN_A[58]; // rv 0
assign CAS_IN_DIN_A_in[59] = (CAS_IN_DIN_A[59] !== 1'bz) && CAS_IN_DIN_A[59]; // rv 0
assign CAS_IN_DIN_A_in[5] = (CAS_IN_DIN_A[5] !== 1'bz) && CAS_IN_DIN_A[5]; // rv 0
assign CAS_IN_DIN_A_in[60] = (CAS_IN_DIN_A[60] !== 1'bz) && CAS_IN_DIN_A[60]; // rv 0
assign CAS_IN_DIN_A_in[61] = (CAS_IN_DIN_A[61] !== 1'bz) && CAS_IN_DIN_A[61]; // rv 0
assign CAS_IN_DIN_A_in[62] = (CAS_IN_DIN_A[62] !== 1'bz) && CAS_IN_DIN_A[62]; // rv 0
assign CAS_IN_DIN_A_in[63] = (CAS_IN_DIN_A[63] !== 1'bz) && CAS_IN_DIN_A[63]; // rv 0
assign CAS_IN_DIN_A_in[64] = (CAS_IN_DIN_A[64] !== 1'bz) && CAS_IN_DIN_A[64]; // rv 0
assign CAS_IN_DIN_A_in[65] = (CAS_IN_DIN_A[65] !== 1'bz) && CAS_IN_DIN_A[65]; // rv 0
assign CAS_IN_DIN_A_in[66] = (CAS_IN_DIN_A[66] !== 1'bz) && CAS_IN_DIN_A[66]; // rv 0
assign CAS_IN_DIN_A_in[67] = (CAS_IN_DIN_A[67] !== 1'bz) && CAS_IN_DIN_A[67]; // rv 0
assign CAS_IN_DIN_A_in[68] = (CAS_IN_DIN_A[68] !== 1'bz) && CAS_IN_DIN_A[68]; // rv 0
assign CAS_IN_DIN_A_in[69] = (CAS_IN_DIN_A[69] !== 1'bz) && CAS_IN_DIN_A[69]; // rv 0
assign CAS_IN_DIN_A_in[6] = (CAS_IN_DIN_A[6] !== 1'bz) && CAS_IN_DIN_A[6]; // rv 0
assign CAS_IN_DIN_A_in[70] = (CAS_IN_DIN_A[70] !== 1'bz) && CAS_IN_DIN_A[70]; // rv 0
assign CAS_IN_DIN_A_in[71] = (CAS_IN_DIN_A[71] !== 1'bz) && CAS_IN_DIN_A[71]; // rv 0
assign CAS_IN_DIN_A_in[7] = (CAS_IN_DIN_A[7] !== 1'bz) && CAS_IN_DIN_A[7]; // rv 0
assign CAS_IN_DIN_A_in[8] = (CAS_IN_DIN_A[8] !== 1'bz) && CAS_IN_DIN_A[8]; // rv 0
assign CAS_IN_DIN_A_in[9] = (CAS_IN_DIN_A[9] !== 1'bz) && CAS_IN_DIN_A[9]; // rv 0
assign CAS_IN_DIN_B_in[0] = (CAS_IN_DIN_B[0] !== 1'bz) && CAS_IN_DIN_B[0]; // rv 0
assign CAS_IN_DIN_B_in[10] = (CAS_IN_DIN_B[10] !== 1'bz) && CAS_IN_DIN_B[10]; // rv 0
assign CAS_IN_DIN_B_in[11] = (CAS_IN_DIN_B[11] !== 1'bz) && CAS_IN_DIN_B[11]; // rv 0
assign CAS_IN_DIN_B_in[12] = (CAS_IN_DIN_B[12] !== 1'bz) && CAS_IN_DIN_B[12]; // rv 0
assign CAS_IN_DIN_B_in[13] = (CAS_IN_DIN_B[13] !== 1'bz) && CAS_IN_DIN_B[13]; // rv 0
assign CAS_IN_DIN_B_in[14] = (CAS_IN_DIN_B[14] !== 1'bz) && CAS_IN_DIN_B[14]; // rv 0
assign CAS_IN_DIN_B_in[15] = (CAS_IN_DIN_B[15] !== 1'bz) && CAS_IN_DIN_B[15]; // rv 0
assign CAS_IN_DIN_B_in[16] = (CAS_IN_DIN_B[16] !== 1'bz) && CAS_IN_DIN_B[16]; // rv 0
assign CAS_IN_DIN_B_in[17] = (CAS_IN_DIN_B[17] !== 1'bz) && CAS_IN_DIN_B[17]; // rv 0
assign CAS_IN_DIN_B_in[18] = (CAS_IN_DIN_B[18] !== 1'bz) && CAS_IN_DIN_B[18]; // rv 0
assign CAS_IN_DIN_B_in[19] = (CAS_IN_DIN_B[19] !== 1'bz) && CAS_IN_DIN_B[19]; // rv 0
assign CAS_IN_DIN_B_in[1] = (CAS_IN_DIN_B[1] !== 1'bz) && CAS_IN_DIN_B[1]; // rv 0
assign CAS_IN_DIN_B_in[20] = (CAS_IN_DIN_B[20] !== 1'bz) && CAS_IN_DIN_B[20]; // rv 0
assign CAS_IN_DIN_B_in[21] = (CAS_IN_DIN_B[21] !== 1'bz) && CAS_IN_DIN_B[21]; // rv 0
assign CAS_IN_DIN_B_in[22] = (CAS_IN_DIN_B[22] !== 1'bz) && CAS_IN_DIN_B[22]; // rv 0
assign CAS_IN_DIN_B_in[23] = (CAS_IN_DIN_B[23] !== 1'bz) && CAS_IN_DIN_B[23]; // rv 0
assign CAS_IN_DIN_B_in[24] = (CAS_IN_DIN_B[24] !== 1'bz) && CAS_IN_DIN_B[24]; // rv 0
assign CAS_IN_DIN_B_in[25] = (CAS_IN_DIN_B[25] !== 1'bz) && CAS_IN_DIN_B[25]; // rv 0
assign CAS_IN_DIN_B_in[26] = (CAS_IN_DIN_B[26] !== 1'bz) && CAS_IN_DIN_B[26]; // rv 0
assign CAS_IN_DIN_B_in[27] = (CAS_IN_DIN_B[27] !== 1'bz) && CAS_IN_DIN_B[27]; // rv 0
assign CAS_IN_DIN_B_in[28] = (CAS_IN_DIN_B[28] !== 1'bz) && CAS_IN_DIN_B[28]; // rv 0
assign CAS_IN_DIN_B_in[29] = (CAS_IN_DIN_B[29] !== 1'bz) && CAS_IN_DIN_B[29]; // rv 0
assign CAS_IN_DIN_B_in[2] = (CAS_IN_DIN_B[2] !== 1'bz) && CAS_IN_DIN_B[2]; // rv 0
assign CAS_IN_DIN_B_in[30] = (CAS_IN_DIN_B[30] !== 1'bz) && CAS_IN_DIN_B[30]; // rv 0
assign CAS_IN_DIN_B_in[31] = (CAS_IN_DIN_B[31] !== 1'bz) && CAS_IN_DIN_B[31]; // rv 0
assign CAS_IN_DIN_B_in[32] = (CAS_IN_DIN_B[32] !== 1'bz) && CAS_IN_DIN_B[32]; // rv 0
assign CAS_IN_DIN_B_in[33] = (CAS_IN_DIN_B[33] !== 1'bz) && CAS_IN_DIN_B[33]; // rv 0
assign CAS_IN_DIN_B_in[34] = (CAS_IN_DIN_B[34] !== 1'bz) && CAS_IN_DIN_B[34]; // rv 0
assign CAS_IN_DIN_B_in[35] = (CAS_IN_DIN_B[35] !== 1'bz) && CAS_IN_DIN_B[35]; // rv 0
assign CAS_IN_DIN_B_in[36] = (CAS_IN_DIN_B[36] !== 1'bz) && CAS_IN_DIN_B[36]; // rv 0
assign CAS_IN_DIN_B_in[37] = (CAS_IN_DIN_B[37] !== 1'bz) && CAS_IN_DIN_B[37]; // rv 0
assign CAS_IN_DIN_B_in[38] = (CAS_IN_DIN_B[38] !== 1'bz) && CAS_IN_DIN_B[38]; // rv 0
assign CAS_IN_DIN_B_in[39] = (CAS_IN_DIN_B[39] !== 1'bz) && CAS_IN_DIN_B[39]; // rv 0
assign CAS_IN_DIN_B_in[3] = (CAS_IN_DIN_B[3] !== 1'bz) && CAS_IN_DIN_B[3]; // rv 0
assign CAS_IN_DIN_B_in[40] = (CAS_IN_DIN_B[40] !== 1'bz) && CAS_IN_DIN_B[40]; // rv 0
assign CAS_IN_DIN_B_in[41] = (CAS_IN_DIN_B[41] !== 1'bz) && CAS_IN_DIN_B[41]; // rv 0
assign CAS_IN_DIN_B_in[42] = (CAS_IN_DIN_B[42] !== 1'bz) && CAS_IN_DIN_B[42]; // rv 0
assign CAS_IN_DIN_B_in[43] = (CAS_IN_DIN_B[43] !== 1'bz) && CAS_IN_DIN_B[43]; // rv 0
assign CAS_IN_DIN_B_in[44] = (CAS_IN_DIN_B[44] !== 1'bz) && CAS_IN_DIN_B[44]; // rv 0
assign CAS_IN_DIN_B_in[45] = (CAS_IN_DIN_B[45] !== 1'bz) && CAS_IN_DIN_B[45]; // rv 0
assign CAS_IN_DIN_B_in[46] = (CAS_IN_DIN_B[46] !== 1'bz) && CAS_IN_DIN_B[46]; // rv 0
assign CAS_IN_DIN_B_in[47] = (CAS_IN_DIN_B[47] !== 1'bz) && CAS_IN_DIN_B[47]; // rv 0
assign CAS_IN_DIN_B_in[48] = (CAS_IN_DIN_B[48] !== 1'bz) && CAS_IN_DIN_B[48]; // rv 0
assign CAS_IN_DIN_B_in[49] = (CAS_IN_DIN_B[49] !== 1'bz) && CAS_IN_DIN_B[49]; // rv 0
assign CAS_IN_DIN_B_in[4] = (CAS_IN_DIN_B[4] !== 1'bz) && CAS_IN_DIN_B[4]; // rv 0
assign CAS_IN_DIN_B_in[50] = (CAS_IN_DIN_B[50] !== 1'bz) && CAS_IN_DIN_B[50]; // rv 0
assign CAS_IN_DIN_B_in[51] = (CAS_IN_DIN_B[51] !== 1'bz) && CAS_IN_DIN_B[51]; // rv 0
assign CAS_IN_DIN_B_in[52] = (CAS_IN_DIN_B[52] !== 1'bz) && CAS_IN_DIN_B[52]; // rv 0
assign CAS_IN_DIN_B_in[53] = (CAS_IN_DIN_B[53] !== 1'bz) && CAS_IN_DIN_B[53]; // rv 0
assign CAS_IN_DIN_B_in[54] = (CAS_IN_DIN_B[54] !== 1'bz) && CAS_IN_DIN_B[54]; // rv 0
assign CAS_IN_DIN_B_in[55] = (CAS_IN_DIN_B[55] !== 1'bz) && CAS_IN_DIN_B[55]; // rv 0
assign CAS_IN_DIN_B_in[56] = (CAS_IN_DIN_B[56] !== 1'bz) && CAS_IN_DIN_B[56]; // rv 0
assign CAS_IN_DIN_B_in[57] = (CAS_IN_DIN_B[57] !== 1'bz) && CAS_IN_DIN_B[57]; // rv 0
assign CAS_IN_DIN_B_in[58] = (CAS_IN_DIN_B[58] !== 1'bz) && CAS_IN_DIN_B[58]; // rv 0
assign CAS_IN_DIN_B_in[59] = (CAS_IN_DIN_B[59] !== 1'bz) && CAS_IN_DIN_B[59]; // rv 0
assign CAS_IN_DIN_B_in[5] = (CAS_IN_DIN_B[5] !== 1'bz) && CAS_IN_DIN_B[5]; // rv 0
assign CAS_IN_DIN_B_in[60] = (CAS_IN_DIN_B[60] !== 1'bz) && CAS_IN_DIN_B[60]; // rv 0
assign CAS_IN_DIN_B_in[61] = (CAS_IN_DIN_B[61] !== 1'bz) && CAS_IN_DIN_B[61]; // rv 0
assign CAS_IN_DIN_B_in[62] = (CAS_IN_DIN_B[62] !== 1'bz) && CAS_IN_DIN_B[62]; // rv 0
assign CAS_IN_DIN_B_in[63] = (CAS_IN_DIN_B[63] !== 1'bz) && CAS_IN_DIN_B[63]; // rv 0
assign CAS_IN_DIN_B_in[64] = (CAS_IN_DIN_B[64] !== 1'bz) && CAS_IN_DIN_B[64]; // rv 0
assign CAS_IN_DIN_B_in[65] = (CAS_IN_DIN_B[65] !== 1'bz) && CAS_IN_DIN_B[65]; // rv 0
assign CAS_IN_DIN_B_in[66] = (CAS_IN_DIN_B[66] !== 1'bz) && CAS_IN_DIN_B[66]; // rv 0
assign CAS_IN_DIN_B_in[67] = (CAS_IN_DIN_B[67] !== 1'bz) && CAS_IN_DIN_B[67]; // rv 0
assign CAS_IN_DIN_B_in[68] = (CAS_IN_DIN_B[68] !== 1'bz) && CAS_IN_DIN_B[68]; // rv 0
assign CAS_IN_DIN_B_in[69] = (CAS_IN_DIN_B[69] !== 1'bz) && CAS_IN_DIN_B[69]; // rv 0
assign CAS_IN_DIN_B_in[6] = (CAS_IN_DIN_B[6] !== 1'bz) && CAS_IN_DIN_B[6]; // rv 0
assign CAS_IN_DIN_B_in[70] = (CAS_IN_DIN_B[70] !== 1'bz) && CAS_IN_DIN_B[70]; // rv 0
assign CAS_IN_DIN_B_in[71] = (CAS_IN_DIN_B[71] !== 1'bz) && CAS_IN_DIN_B[71]; // rv 0
assign CAS_IN_DIN_B_in[7] = (CAS_IN_DIN_B[7] !== 1'bz) && CAS_IN_DIN_B[7]; // rv 0
assign CAS_IN_DIN_B_in[8] = (CAS_IN_DIN_B[8] !== 1'bz) && CAS_IN_DIN_B[8]; // rv 0
assign CAS_IN_DIN_B_in[9] = (CAS_IN_DIN_B[9] !== 1'bz) && CAS_IN_DIN_B[9]; // rv 0
assign CAS_IN_DOUT_A_in[0] = (CAS_IN_DOUT_A[0] !== 1'bz) && CAS_IN_DOUT_A[0]; // rv 0
assign CAS_IN_DOUT_A_in[10] = (CAS_IN_DOUT_A[10] !== 1'bz) && CAS_IN_DOUT_A[10]; // rv 0
assign CAS_IN_DOUT_A_in[11] = (CAS_IN_DOUT_A[11] !== 1'bz) && CAS_IN_DOUT_A[11]; // rv 0
assign CAS_IN_DOUT_A_in[12] = (CAS_IN_DOUT_A[12] !== 1'bz) && CAS_IN_DOUT_A[12]; // rv 0
assign CAS_IN_DOUT_A_in[13] = (CAS_IN_DOUT_A[13] !== 1'bz) && CAS_IN_DOUT_A[13]; // rv 0
assign CAS_IN_DOUT_A_in[14] = (CAS_IN_DOUT_A[14] !== 1'bz) && CAS_IN_DOUT_A[14]; // rv 0
assign CAS_IN_DOUT_A_in[15] = (CAS_IN_DOUT_A[15] !== 1'bz) && CAS_IN_DOUT_A[15]; // rv 0
assign CAS_IN_DOUT_A_in[16] = (CAS_IN_DOUT_A[16] !== 1'bz) && CAS_IN_DOUT_A[16]; // rv 0
assign CAS_IN_DOUT_A_in[17] = (CAS_IN_DOUT_A[17] !== 1'bz) && CAS_IN_DOUT_A[17]; // rv 0
assign CAS_IN_DOUT_A_in[18] = (CAS_IN_DOUT_A[18] !== 1'bz) && CAS_IN_DOUT_A[18]; // rv 0
assign CAS_IN_DOUT_A_in[19] = (CAS_IN_DOUT_A[19] !== 1'bz) && CAS_IN_DOUT_A[19]; // rv 0
assign CAS_IN_DOUT_A_in[1] = (CAS_IN_DOUT_A[1] !== 1'bz) && CAS_IN_DOUT_A[1]; // rv 0
assign CAS_IN_DOUT_A_in[20] = (CAS_IN_DOUT_A[20] !== 1'bz) && CAS_IN_DOUT_A[20]; // rv 0
assign CAS_IN_DOUT_A_in[21] = (CAS_IN_DOUT_A[21] !== 1'bz) && CAS_IN_DOUT_A[21]; // rv 0
assign CAS_IN_DOUT_A_in[22] = (CAS_IN_DOUT_A[22] !== 1'bz) && CAS_IN_DOUT_A[22]; // rv 0
assign CAS_IN_DOUT_A_in[23] = (CAS_IN_DOUT_A[23] !== 1'bz) && CAS_IN_DOUT_A[23]; // rv 0
assign CAS_IN_DOUT_A_in[24] = (CAS_IN_DOUT_A[24] !== 1'bz) && CAS_IN_DOUT_A[24]; // rv 0
assign CAS_IN_DOUT_A_in[25] = (CAS_IN_DOUT_A[25] !== 1'bz) && CAS_IN_DOUT_A[25]; // rv 0
assign CAS_IN_DOUT_A_in[26] = (CAS_IN_DOUT_A[26] !== 1'bz) && CAS_IN_DOUT_A[26]; // rv 0
assign CAS_IN_DOUT_A_in[27] = (CAS_IN_DOUT_A[27] !== 1'bz) && CAS_IN_DOUT_A[27]; // rv 0
assign CAS_IN_DOUT_A_in[28] = (CAS_IN_DOUT_A[28] !== 1'bz) && CAS_IN_DOUT_A[28]; // rv 0
assign CAS_IN_DOUT_A_in[29] = (CAS_IN_DOUT_A[29] !== 1'bz) && CAS_IN_DOUT_A[29]; // rv 0
assign CAS_IN_DOUT_A_in[2] = (CAS_IN_DOUT_A[2] !== 1'bz) && CAS_IN_DOUT_A[2]; // rv 0
assign CAS_IN_DOUT_A_in[30] = (CAS_IN_DOUT_A[30] !== 1'bz) && CAS_IN_DOUT_A[30]; // rv 0
assign CAS_IN_DOUT_A_in[31] = (CAS_IN_DOUT_A[31] !== 1'bz) && CAS_IN_DOUT_A[31]; // rv 0
assign CAS_IN_DOUT_A_in[32] = (CAS_IN_DOUT_A[32] !== 1'bz) && CAS_IN_DOUT_A[32]; // rv 0
assign CAS_IN_DOUT_A_in[33] = (CAS_IN_DOUT_A[33] !== 1'bz) && CAS_IN_DOUT_A[33]; // rv 0
assign CAS_IN_DOUT_A_in[34] = (CAS_IN_DOUT_A[34] !== 1'bz) && CAS_IN_DOUT_A[34]; // rv 0
assign CAS_IN_DOUT_A_in[35] = (CAS_IN_DOUT_A[35] !== 1'bz) && CAS_IN_DOUT_A[35]; // rv 0
assign CAS_IN_DOUT_A_in[36] = (CAS_IN_DOUT_A[36] !== 1'bz) && CAS_IN_DOUT_A[36]; // rv 0
assign CAS_IN_DOUT_A_in[37] = (CAS_IN_DOUT_A[37] !== 1'bz) && CAS_IN_DOUT_A[37]; // rv 0
assign CAS_IN_DOUT_A_in[38] = (CAS_IN_DOUT_A[38] !== 1'bz) && CAS_IN_DOUT_A[38]; // rv 0
assign CAS_IN_DOUT_A_in[39] = (CAS_IN_DOUT_A[39] !== 1'bz) && CAS_IN_DOUT_A[39]; // rv 0
assign CAS_IN_DOUT_A_in[3] = (CAS_IN_DOUT_A[3] !== 1'bz) && CAS_IN_DOUT_A[3]; // rv 0
assign CAS_IN_DOUT_A_in[40] = (CAS_IN_DOUT_A[40] !== 1'bz) && CAS_IN_DOUT_A[40]; // rv 0
assign CAS_IN_DOUT_A_in[41] = (CAS_IN_DOUT_A[41] !== 1'bz) && CAS_IN_DOUT_A[41]; // rv 0
assign CAS_IN_DOUT_A_in[42] = (CAS_IN_DOUT_A[42] !== 1'bz) && CAS_IN_DOUT_A[42]; // rv 0
assign CAS_IN_DOUT_A_in[43] = (CAS_IN_DOUT_A[43] !== 1'bz) && CAS_IN_DOUT_A[43]; // rv 0
assign CAS_IN_DOUT_A_in[44] = (CAS_IN_DOUT_A[44] !== 1'bz) && CAS_IN_DOUT_A[44]; // rv 0
assign CAS_IN_DOUT_A_in[45] = (CAS_IN_DOUT_A[45] !== 1'bz) && CAS_IN_DOUT_A[45]; // rv 0
assign CAS_IN_DOUT_A_in[46] = (CAS_IN_DOUT_A[46] !== 1'bz) && CAS_IN_DOUT_A[46]; // rv 0
assign CAS_IN_DOUT_A_in[47] = (CAS_IN_DOUT_A[47] !== 1'bz) && CAS_IN_DOUT_A[47]; // rv 0
assign CAS_IN_DOUT_A_in[48] = (CAS_IN_DOUT_A[48] !== 1'bz) && CAS_IN_DOUT_A[48]; // rv 0
assign CAS_IN_DOUT_A_in[49] = (CAS_IN_DOUT_A[49] !== 1'bz) && CAS_IN_DOUT_A[49]; // rv 0
assign CAS_IN_DOUT_A_in[4] = (CAS_IN_DOUT_A[4] !== 1'bz) && CAS_IN_DOUT_A[4]; // rv 0
assign CAS_IN_DOUT_A_in[50] = (CAS_IN_DOUT_A[50] !== 1'bz) && CAS_IN_DOUT_A[50]; // rv 0
assign CAS_IN_DOUT_A_in[51] = (CAS_IN_DOUT_A[51] !== 1'bz) && CAS_IN_DOUT_A[51]; // rv 0
assign CAS_IN_DOUT_A_in[52] = (CAS_IN_DOUT_A[52] !== 1'bz) && CAS_IN_DOUT_A[52]; // rv 0
assign CAS_IN_DOUT_A_in[53] = (CAS_IN_DOUT_A[53] !== 1'bz) && CAS_IN_DOUT_A[53]; // rv 0
assign CAS_IN_DOUT_A_in[54] = (CAS_IN_DOUT_A[54] !== 1'bz) && CAS_IN_DOUT_A[54]; // rv 0
assign CAS_IN_DOUT_A_in[55] = (CAS_IN_DOUT_A[55] !== 1'bz) && CAS_IN_DOUT_A[55]; // rv 0
assign CAS_IN_DOUT_A_in[56] = (CAS_IN_DOUT_A[56] !== 1'bz) && CAS_IN_DOUT_A[56]; // rv 0
assign CAS_IN_DOUT_A_in[57] = (CAS_IN_DOUT_A[57] !== 1'bz) && CAS_IN_DOUT_A[57]; // rv 0
assign CAS_IN_DOUT_A_in[58] = (CAS_IN_DOUT_A[58] !== 1'bz) && CAS_IN_DOUT_A[58]; // rv 0
assign CAS_IN_DOUT_A_in[59] = (CAS_IN_DOUT_A[59] !== 1'bz) && CAS_IN_DOUT_A[59]; // rv 0
assign CAS_IN_DOUT_A_in[5] = (CAS_IN_DOUT_A[5] !== 1'bz) && CAS_IN_DOUT_A[5]; // rv 0
assign CAS_IN_DOUT_A_in[60] = (CAS_IN_DOUT_A[60] !== 1'bz) && CAS_IN_DOUT_A[60]; // rv 0
assign CAS_IN_DOUT_A_in[61] = (CAS_IN_DOUT_A[61] !== 1'bz) && CAS_IN_DOUT_A[61]; // rv 0
assign CAS_IN_DOUT_A_in[62] = (CAS_IN_DOUT_A[62] !== 1'bz) && CAS_IN_DOUT_A[62]; // rv 0
assign CAS_IN_DOUT_A_in[63] = (CAS_IN_DOUT_A[63] !== 1'bz) && CAS_IN_DOUT_A[63]; // rv 0
assign CAS_IN_DOUT_A_in[64] = (CAS_IN_DOUT_A[64] !== 1'bz) && CAS_IN_DOUT_A[64]; // rv 0
assign CAS_IN_DOUT_A_in[65] = (CAS_IN_DOUT_A[65] !== 1'bz) && CAS_IN_DOUT_A[65]; // rv 0
assign CAS_IN_DOUT_A_in[66] = (CAS_IN_DOUT_A[66] !== 1'bz) && CAS_IN_DOUT_A[66]; // rv 0
assign CAS_IN_DOUT_A_in[67] = (CAS_IN_DOUT_A[67] !== 1'bz) && CAS_IN_DOUT_A[67]; // rv 0
assign CAS_IN_DOUT_A_in[68] = (CAS_IN_DOUT_A[68] !== 1'bz) && CAS_IN_DOUT_A[68]; // rv 0
assign CAS_IN_DOUT_A_in[69] = (CAS_IN_DOUT_A[69] !== 1'bz) && CAS_IN_DOUT_A[69]; // rv 0
assign CAS_IN_DOUT_A_in[6] = (CAS_IN_DOUT_A[6] !== 1'bz) && CAS_IN_DOUT_A[6]; // rv 0
assign CAS_IN_DOUT_A_in[70] = (CAS_IN_DOUT_A[70] !== 1'bz) && CAS_IN_DOUT_A[70]; // rv 0
assign CAS_IN_DOUT_A_in[71] = (CAS_IN_DOUT_A[71] !== 1'bz) && CAS_IN_DOUT_A[71]; // rv 0
assign CAS_IN_DOUT_A_in[7] = (CAS_IN_DOUT_A[7] !== 1'bz) && CAS_IN_DOUT_A[7]; // rv 0
assign CAS_IN_DOUT_A_in[8] = (CAS_IN_DOUT_A[8] !== 1'bz) && CAS_IN_DOUT_A[8]; // rv 0
assign CAS_IN_DOUT_A_in[9] = (CAS_IN_DOUT_A[9] !== 1'bz) && CAS_IN_DOUT_A[9]; // rv 0
assign CAS_IN_DOUT_B_in[0] = (CAS_IN_DOUT_B[0] !== 1'bz) && CAS_IN_DOUT_B[0]; // rv 0
assign CAS_IN_DOUT_B_in[10] = (CAS_IN_DOUT_B[10] !== 1'bz) && CAS_IN_DOUT_B[10]; // rv 0
assign CAS_IN_DOUT_B_in[11] = (CAS_IN_DOUT_B[11] !== 1'bz) && CAS_IN_DOUT_B[11]; // rv 0
assign CAS_IN_DOUT_B_in[12] = (CAS_IN_DOUT_B[12] !== 1'bz) && CAS_IN_DOUT_B[12]; // rv 0
assign CAS_IN_DOUT_B_in[13] = (CAS_IN_DOUT_B[13] !== 1'bz) && CAS_IN_DOUT_B[13]; // rv 0
assign CAS_IN_DOUT_B_in[14] = (CAS_IN_DOUT_B[14] !== 1'bz) && CAS_IN_DOUT_B[14]; // rv 0
assign CAS_IN_DOUT_B_in[15] = (CAS_IN_DOUT_B[15] !== 1'bz) && CAS_IN_DOUT_B[15]; // rv 0
assign CAS_IN_DOUT_B_in[16] = (CAS_IN_DOUT_B[16] !== 1'bz) && CAS_IN_DOUT_B[16]; // rv 0
assign CAS_IN_DOUT_B_in[17] = (CAS_IN_DOUT_B[17] !== 1'bz) && CAS_IN_DOUT_B[17]; // rv 0
assign CAS_IN_DOUT_B_in[18] = (CAS_IN_DOUT_B[18] !== 1'bz) && CAS_IN_DOUT_B[18]; // rv 0
assign CAS_IN_DOUT_B_in[19] = (CAS_IN_DOUT_B[19] !== 1'bz) && CAS_IN_DOUT_B[19]; // rv 0
assign CAS_IN_DOUT_B_in[1] = (CAS_IN_DOUT_B[1] !== 1'bz) && CAS_IN_DOUT_B[1]; // rv 0
assign CAS_IN_DOUT_B_in[20] = (CAS_IN_DOUT_B[20] !== 1'bz) && CAS_IN_DOUT_B[20]; // rv 0
assign CAS_IN_DOUT_B_in[21] = (CAS_IN_DOUT_B[21] !== 1'bz) && CAS_IN_DOUT_B[21]; // rv 0
assign CAS_IN_DOUT_B_in[22] = (CAS_IN_DOUT_B[22] !== 1'bz) && CAS_IN_DOUT_B[22]; // rv 0
assign CAS_IN_DOUT_B_in[23] = (CAS_IN_DOUT_B[23] !== 1'bz) && CAS_IN_DOUT_B[23]; // rv 0
assign CAS_IN_DOUT_B_in[24] = (CAS_IN_DOUT_B[24] !== 1'bz) && CAS_IN_DOUT_B[24]; // rv 0
assign CAS_IN_DOUT_B_in[25] = (CAS_IN_DOUT_B[25] !== 1'bz) && CAS_IN_DOUT_B[25]; // rv 0
assign CAS_IN_DOUT_B_in[26] = (CAS_IN_DOUT_B[26] !== 1'bz) && CAS_IN_DOUT_B[26]; // rv 0
assign CAS_IN_DOUT_B_in[27] = (CAS_IN_DOUT_B[27] !== 1'bz) && CAS_IN_DOUT_B[27]; // rv 0
assign CAS_IN_DOUT_B_in[28] = (CAS_IN_DOUT_B[28] !== 1'bz) && CAS_IN_DOUT_B[28]; // rv 0
assign CAS_IN_DOUT_B_in[29] = (CAS_IN_DOUT_B[29] !== 1'bz) && CAS_IN_DOUT_B[29]; // rv 0
assign CAS_IN_DOUT_B_in[2] = (CAS_IN_DOUT_B[2] !== 1'bz) && CAS_IN_DOUT_B[2]; // rv 0
assign CAS_IN_DOUT_B_in[30] = (CAS_IN_DOUT_B[30] !== 1'bz) && CAS_IN_DOUT_B[30]; // rv 0
assign CAS_IN_DOUT_B_in[31] = (CAS_IN_DOUT_B[31] !== 1'bz) && CAS_IN_DOUT_B[31]; // rv 0
assign CAS_IN_DOUT_B_in[32] = (CAS_IN_DOUT_B[32] !== 1'bz) && CAS_IN_DOUT_B[32]; // rv 0
assign CAS_IN_DOUT_B_in[33] = (CAS_IN_DOUT_B[33] !== 1'bz) && CAS_IN_DOUT_B[33]; // rv 0
assign CAS_IN_DOUT_B_in[34] = (CAS_IN_DOUT_B[34] !== 1'bz) && CAS_IN_DOUT_B[34]; // rv 0
assign CAS_IN_DOUT_B_in[35] = (CAS_IN_DOUT_B[35] !== 1'bz) && CAS_IN_DOUT_B[35]; // rv 0
assign CAS_IN_DOUT_B_in[36] = (CAS_IN_DOUT_B[36] !== 1'bz) && CAS_IN_DOUT_B[36]; // rv 0
assign CAS_IN_DOUT_B_in[37] = (CAS_IN_DOUT_B[37] !== 1'bz) && CAS_IN_DOUT_B[37]; // rv 0
assign CAS_IN_DOUT_B_in[38] = (CAS_IN_DOUT_B[38] !== 1'bz) && CAS_IN_DOUT_B[38]; // rv 0
assign CAS_IN_DOUT_B_in[39] = (CAS_IN_DOUT_B[39] !== 1'bz) && CAS_IN_DOUT_B[39]; // rv 0
assign CAS_IN_DOUT_B_in[3] = (CAS_IN_DOUT_B[3] !== 1'bz) && CAS_IN_DOUT_B[3]; // rv 0
assign CAS_IN_DOUT_B_in[40] = (CAS_IN_DOUT_B[40] !== 1'bz) && CAS_IN_DOUT_B[40]; // rv 0
assign CAS_IN_DOUT_B_in[41] = (CAS_IN_DOUT_B[41] !== 1'bz) && CAS_IN_DOUT_B[41]; // rv 0
assign CAS_IN_DOUT_B_in[42] = (CAS_IN_DOUT_B[42] !== 1'bz) && CAS_IN_DOUT_B[42]; // rv 0
assign CAS_IN_DOUT_B_in[43] = (CAS_IN_DOUT_B[43] !== 1'bz) && CAS_IN_DOUT_B[43]; // rv 0
assign CAS_IN_DOUT_B_in[44] = (CAS_IN_DOUT_B[44] !== 1'bz) && CAS_IN_DOUT_B[44]; // rv 0
assign CAS_IN_DOUT_B_in[45] = (CAS_IN_DOUT_B[45] !== 1'bz) && CAS_IN_DOUT_B[45]; // rv 0
assign CAS_IN_DOUT_B_in[46] = (CAS_IN_DOUT_B[46] !== 1'bz) && CAS_IN_DOUT_B[46]; // rv 0
assign CAS_IN_DOUT_B_in[47] = (CAS_IN_DOUT_B[47] !== 1'bz) && CAS_IN_DOUT_B[47]; // rv 0
assign CAS_IN_DOUT_B_in[48] = (CAS_IN_DOUT_B[48] !== 1'bz) && CAS_IN_DOUT_B[48]; // rv 0
assign CAS_IN_DOUT_B_in[49] = (CAS_IN_DOUT_B[49] !== 1'bz) && CAS_IN_DOUT_B[49]; // rv 0
assign CAS_IN_DOUT_B_in[4] = (CAS_IN_DOUT_B[4] !== 1'bz) && CAS_IN_DOUT_B[4]; // rv 0
assign CAS_IN_DOUT_B_in[50] = (CAS_IN_DOUT_B[50] !== 1'bz) && CAS_IN_DOUT_B[50]; // rv 0
assign CAS_IN_DOUT_B_in[51] = (CAS_IN_DOUT_B[51] !== 1'bz) && CAS_IN_DOUT_B[51]; // rv 0
assign CAS_IN_DOUT_B_in[52] = (CAS_IN_DOUT_B[52] !== 1'bz) && CAS_IN_DOUT_B[52]; // rv 0
assign CAS_IN_DOUT_B_in[53] = (CAS_IN_DOUT_B[53] !== 1'bz) && CAS_IN_DOUT_B[53]; // rv 0
assign CAS_IN_DOUT_B_in[54] = (CAS_IN_DOUT_B[54] !== 1'bz) && CAS_IN_DOUT_B[54]; // rv 0
assign CAS_IN_DOUT_B_in[55] = (CAS_IN_DOUT_B[55] !== 1'bz) && CAS_IN_DOUT_B[55]; // rv 0
assign CAS_IN_DOUT_B_in[56] = (CAS_IN_DOUT_B[56] !== 1'bz) && CAS_IN_DOUT_B[56]; // rv 0
assign CAS_IN_DOUT_B_in[57] = (CAS_IN_DOUT_B[57] !== 1'bz) && CAS_IN_DOUT_B[57]; // rv 0
assign CAS_IN_DOUT_B_in[58] = (CAS_IN_DOUT_B[58] !== 1'bz) && CAS_IN_DOUT_B[58]; // rv 0
assign CAS_IN_DOUT_B_in[59] = (CAS_IN_DOUT_B[59] !== 1'bz) && CAS_IN_DOUT_B[59]; // rv 0
assign CAS_IN_DOUT_B_in[5] = (CAS_IN_DOUT_B[5] !== 1'bz) && CAS_IN_DOUT_B[5]; // rv 0
assign CAS_IN_DOUT_B_in[60] = (CAS_IN_DOUT_B[60] !== 1'bz) && CAS_IN_DOUT_B[60]; // rv 0
assign CAS_IN_DOUT_B_in[61] = (CAS_IN_DOUT_B[61] !== 1'bz) && CAS_IN_DOUT_B[61]; // rv 0
assign CAS_IN_DOUT_B_in[62] = (CAS_IN_DOUT_B[62] !== 1'bz) && CAS_IN_DOUT_B[62]; // rv 0
assign CAS_IN_DOUT_B_in[63] = (CAS_IN_DOUT_B[63] !== 1'bz) && CAS_IN_DOUT_B[63]; // rv 0
assign CAS_IN_DOUT_B_in[64] = (CAS_IN_DOUT_B[64] !== 1'bz) && CAS_IN_DOUT_B[64]; // rv 0
assign CAS_IN_DOUT_B_in[65] = (CAS_IN_DOUT_B[65] !== 1'bz) && CAS_IN_DOUT_B[65]; // rv 0
assign CAS_IN_DOUT_B_in[66] = (CAS_IN_DOUT_B[66] !== 1'bz) && CAS_IN_DOUT_B[66]; // rv 0
assign CAS_IN_DOUT_B_in[67] = (CAS_IN_DOUT_B[67] !== 1'bz) && CAS_IN_DOUT_B[67]; // rv 0
assign CAS_IN_DOUT_B_in[68] = (CAS_IN_DOUT_B[68] !== 1'bz) && CAS_IN_DOUT_B[68]; // rv 0
assign CAS_IN_DOUT_B_in[69] = (CAS_IN_DOUT_B[69] !== 1'bz) && CAS_IN_DOUT_B[69]; // rv 0
assign CAS_IN_DOUT_B_in[6] = (CAS_IN_DOUT_B[6] !== 1'bz) && CAS_IN_DOUT_B[6]; // rv 0
assign CAS_IN_DOUT_B_in[70] = (CAS_IN_DOUT_B[70] !== 1'bz) && CAS_IN_DOUT_B[70]; // rv 0
assign CAS_IN_DOUT_B_in[71] = (CAS_IN_DOUT_B[71] !== 1'bz) && CAS_IN_DOUT_B[71]; // rv 0
assign CAS_IN_DOUT_B_in[7] = (CAS_IN_DOUT_B[7] !== 1'bz) && CAS_IN_DOUT_B[7]; // rv 0
assign CAS_IN_DOUT_B_in[8] = (CAS_IN_DOUT_B[8] !== 1'bz) && CAS_IN_DOUT_B[8]; // rv 0
assign CAS_IN_DOUT_B_in[9] = (CAS_IN_DOUT_B[9] !== 1'bz) && CAS_IN_DOUT_B[9]; // rv 0
assign CAS_IN_EN_A_in = (CAS_IN_EN_A !== 1'bz) && CAS_IN_EN_A; // rv 0
assign CAS_IN_EN_B_in = (CAS_IN_EN_B !== 1'bz) && CAS_IN_EN_B; // rv 0
assign CAS_IN_RDACCESS_A_in = (CAS_IN_RDACCESS_A !== 1'bz) && CAS_IN_RDACCESS_A; // rv 0
assign CAS_IN_RDACCESS_B_in = (CAS_IN_RDACCESS_B !== 1'bz) && CAS_IN_RDACCESS_B; // rv 0
assign CAS_IN_RDB_WR_A_in = (CAS_IN_RDB_WR_A !== 1'bz) && CAS_IN_RDB_WR_A; // rv 0
assign CAS_IN_RDB_WR_B_in = (CAS_IN_RDB_WR_B !== 1'bz) && CAS_IN_RDB_WR_B; // rv 0
assign CAS_IN_SBITERR_A_in = (CAS_IN_SBITERR_A !== 1'bz) && CAS_IN_SBITERR_A; // rv 0
assign CAS_IN_SBITERR_B_in = (CAS_IN_SBITERR_B !== 1'bz) && CAS_IN_SBITERR_B; // rv 0
assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0
assign DIN_A_in = DIN_A;
assign DIN_B_in = DIN_B;
assign EN_A_in = (EN_A !== 1'bz) && (EN_A ^ IS_EN_A_INVERTED_REG); // rv 0
assign EN_B_in = (EN_B !== 1'bz) && (EN_B ^ IS_EN_B_INVERTED_REG); // rv 0
assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A; // rv 0
assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B; // rv 0
assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A; // rv 0
assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B; // rv 0
assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A; // rv 1
assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B; // rv 1
assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A; // rv 1
assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B; // rv 1
assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A ^ IS_RDB_WR_A_INVERTED_REG); // rv 0
assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B ^ IS_RDB_WR_B_INVERTED_REG); // rv 0
assign RST_A_in = (RST_A !== 1'bz) && (RST_A ^ IS_RST_A_INVERTED_REG); // rv 0
assign RST_B_in = (RST_B !== 1'bz) && (RST_B ^ IS_RST_B_INVERTED_REG); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0];
assign AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0];
assign BWE_MODE_A_BIN =
(BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED :
(BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT :
BWE_MODE_A_PARITY_INTERLEAVED;
assign BWE_MODE_B_BIN =
(BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED :
(BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT :
BWE_MODE_B_PARITY_INTERLEAVED;
assign CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE :
(CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST :
(CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST :
(CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE :
CASCADE_ORDER_A_NONE;
assign CASCADE_ORDER_B_BIN =
(CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE :
(CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST :
(CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST :
(CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE :
CASCADE_ORDER_B_NONE;
assign EN_AUTO_SLEEP_MODE_BIN =
(EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE :
(EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE :
EN_AUTO_SLEEP_MODE_FALSE;
assign EN_ECC_RD_A_BIN =
(EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE :
(EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE :
EN_ECC_RD_A_FALSE;
assign EN_ECC_RD_B_BIN =
(EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE :
(EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE :
EN_ECC_RD_B_FALSE;
assign EN_ECC_WR_A_BIN =
(EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE :
(EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE :
EN_ECC_WR_A_FALSE;
assign EN_ECC_WR_B_BIN =
(EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE :
(EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE :
EN_ECC_WR_B_FALSE;
assign IREG_PRE_A_BIN =
(IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE :
(IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE :
IREG_PRE_A_FALSE;
assign IREG_PRE_B_BIN =
(IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE :
(IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE :
IREG_PRE_B_FALSE;
assign NUM_UNIQUE_SELF_ADDR_A_BIN = NUM_UNIQUE_SELF_ADDR_A_REG[11:0];
assign NUM_UNIQUE_SELF_ADDR_B_BIN = NUM_UNIQUE_SELF_ADDR_B_REG[11:0];
assign NUM_URAM_IN_MATRIX_BIN = NUM_URAM_IN_MATRIX_REG[11:0];
assign OREG_A_BIN =
(OREG_A_REG == "FALSE") ? OREG_A_FALSE :
(OREG_A_REG == "TRUE") ? OREG_A_TRUE :
OREG_A_FALSE;
assign OREG_B_BIN =
(OREG_B_REG == "FALSE") ? OREG_B_FALSE :
(OREG_B_REG == "TRUE") ? OREG_B_TRUE :
OREG_B_FALSE;
assign OREG_ECC_A_BIN =
(OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE :
(OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE :
OREG_ECC_A_FALSE;
assign OREG_ECC_B_BIN =
(OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE :
(OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE :
OREG_ECC_B_FALSE;
assign REG_CAS_A_BIN =
(REG_CAS_A_REG == "FALSE") ? REG_CAS_A_FALSE :
(REG_CAS_A_REG == "TRUE") ? REG_CAS_A_TRUE :
REG_CAS_A_FALSE;
assign REG_CAS_B_BIN =
(REG_CAS_B_REG == "FALSE") ? REG_CAS_B_FALSE :
(REG_CAS_B_REG == "TRUE") ? REG_CAS_B_TRUE :
REG_CAS_B_FALSE;
assign RST_MODE_A_BIN =
(RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC :
(RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC :
RST_MODE_A_SYNC;
assign RST_MODE_B_BIN =
(RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC :
(RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC :
RST_MODE_B_SYNC;
assign USE_EXT_CE_A_BIN =
(USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE :
(USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE :
USE_EXT_CE_A_FALSE;
assign USE_EXT_CE_B_BIN =
(USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE :
(USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE :
USE_EXT_CE_B_FALSE;
`else
always @ (trig_attr) begin
#1;
AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0];
AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0];
BWE_MODE_A_BIN =
(BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED :
(BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT :
BWE_MODE_A_PARITY_INTERLEAVED;
BWE_MODE_B_BIN =
(BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED :
(BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT :
BWE_MODE_B_PARITY_INTERLEAVED;
CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE :
(CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST :
(CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST :
(CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE :
CASCADE_ORDER_A_NONE;
CASCADE_ORDER_B_BIN =
(CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE :
(CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST :
(CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST :
(CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE :
CASCADE_ORDER_B_NONE;
EN_AUTO_SLEEP_MODE_BIN =
(EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE :
(EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE :
EN_AUTO_SLEEP_MODE_FALSE;
EN_ECC_RD_A_BIN =
(EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE :
(EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE :
EN_ECC_RD_A_FALSE;
EN_ECC_RD_B_BIN =
(EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE :
(EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE :
EN_ECC_RD_B_FALSE;
EN_ECC_WR_A_BIN =
(EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE :
(EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE :
EN_ECC_WR_A_FALSE;
EN_ECC_WR_B_BIN =
(EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE :
(EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE :
EN_ECC_WR_B_FALSE;
IREG_PRE_A_BIN =
(IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE :
(IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE :
IREG_PRE_A_FALSE;
IREG_PRE_B_BIN =
(IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE :
(IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE :
IREG_PRE_B_FALSE;
NUM_UNIQUE_SELF_ADDR_A_BIN = NUM_UNIQUE_SELF_ADDR_A_REG[11:0];
NUM_UNIQUE_SELF_ADDR_B_BIN = NUM_UNIQUE_SELF_ADDR_B_REG[11:0];
NUM_URAM_IN_MATRIX_BIN = NUM_URAM_IN_MATRIX_REG[11:0];
OREG_A_BIN =
(OREG_A_REG == "FALSE") ? OREG_A_FALSE :
(OREG_A_REG == "TRUE") ? OREG_A_TRUE :
OREG_A_FALSE;
OREG_B_BIN =
(OREG_B_REG == "FALSE") ? OREG_B_FALSE :
(OREG_B_REG == "TRUE") ? OREG_B_TRUE :
OREG_B_FALSE;
OREG_ECC_A_BIN =
(OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE :
(OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE :
OREG_ECC_A_FALSE;
OREG_ECC_B_BIN =
(OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE :
(OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE :
OREG_ECC_B_FALSE;
REG_CAS_A_BIN =
(REG_CAS_A_REG == "FALSE") ? REG_CAS_A_FALSE :
(REG_CAS_A_REG == "TRUE") ? REG_CAS_A_TRUE :
REG_CAS_A_FALSE;
REG_CAS_B_BIN =
(REG_CAS_B_REG == "FALSE") ? REG_CAS_B_FALSE :
(REG_CAS_B_REG == "TRUE") ? REG_CAS_B_TRUE :
REG_CAS_B_FALSE;
RST_MODE_A_BIN =
(RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC :
(RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC :
RST_MODE_A_SYNC;
RST_MODE_B_BIN =
(RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC :
(RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC :
RST_MODE_B_SYNC;
USE_EXT_CE_A_BIN =
(USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE :
(USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE :
USE_EXT_CE_A_FALSE;
USE_EXT_CE_B_BIN =
(USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE :
(USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE :
USE_EXT_CE_B_FALSE;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((AUTO_SLEEP_LATENCY_REG != 8) &&
(AUTO_SLEEP_LATENCY_REG != 3) &&
(AUTO_SLEEP_LATENCY_REG != 4) &&
(AUTO_SLEEP_LATENCY_REG != 5) &&
(AUTO_SLEEP_LATENCY_REG != 6) &&
(AUTO_SLEEP_LATENCY_REG != 7) &&
(AUTO_SLEEP_LATENCY_REG != 9) &&
(AUTO_SLEEP_LATENCY_REG != 10) &&
(AUTO_SLEEP_LATENCY_REG != 11) &&
(AUTO_SLEEP_LATENCY_REG != 12) &&
(AUTO_SLEEP_LATENCY_REG != 13) &&
(AUTO_SLEEP_LATENCY_REG != 14) &&
(AUTO_SLEEP_LATENCY_REG != 15))) begin
$display("Error: [Unisim %s-101] AUTO_SLEEP_LATENCY attribute is set to %d. Legal values for this attribute are 8, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, AUTO_SLEEP_LATENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((AVG_CONS_INACTIVE_CYCLES_REG < 10) || (AVG_CONS_INACTIVE_CYCLES_REG > 100000))) begin
$display("Error: [Unisim %s-102] AVG_CONS_INACTIVE_CYCLES attribute is set to %d. Legal values for this attribute are 10 to 100000. Instance: %m", MODULE_NAME, AVG_CONS_INACTIVE_CYCLES_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BWE_MODE_A_REG != "PARITY_INTERLEAVED") &&
(BWE_MODE_A_REG != "PARITY_INDEPENDENT"))) begin
$display("Error: [Unisim %s-103] BWE_MODE_A attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BWE_MODE_B_REG != "PARITY_INTERLEAVED") &&
(BWE_MODE_B_REG != "PARITY_INDEPENDENT"))) begin
$display("Error: [Unisim %s-104] BWE_MODE_B attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_A_REG != "NONE") &&
(CASCADE_ORDER_A_REG != "FIRST") &&
(CASCADE_ORDER_A_REG != "LAST") &&
(CASCADE_ORDER_A_REG != "MIDDLE"))) begin
$display("Error: [Unisim %s-105] CASCADE_ORDER_A attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_B_REG != "NONE") &&
(CASCADE_ORDER_B_REG != "FIRST") &&
(CASCADE_ORDER_B_REG != "LAST") &&
(CASCADE_ORDER_B_REG != "MIDDLE"))) begin
$display("Error: [Unisim %s-106] CASCADE_ORDER_B attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_AUTO_SLEEP_MODE_REG != "FALSE") &&
(EN_AUTO_SLEEP_MODE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-107] EN_AUTO_SLEEP_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_RD_A_REG != "FALSE") &&
(EN_ECC_RD_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-108] EN_ECC_RD_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_RD_B_REG != "FALSE") &&
(EN_ECC_RD_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-109] EN_ECC_RD_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_WR_A_REG != "FALSE") &&
(EN_ECC_WR_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-110] EN_ECC_WR_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_WR_B_REG != "FALSE") &&
(EN_ECC_WR_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-111] EN_ECC_WR_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IREG_PRE_A_REG != "FALSE") &&
(IREG_PRE_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-112] IREG_PRE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IREG_PRE_B_REG != "FALSE") &&
(IREG_PRE_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-113] IREG_PRE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((NUM_UNIQUE_SELF_ADDR_A_REG < 1) || (NUM_UNIQUE_SELF_ADDR_A_REG > 2048))) begin
$display("Error: [Unisim %s-122] NUM_UNIQUE_SELF_ADDR_A attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_UNIQUE_SELF_ADDR_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((NUM_UNIQUE_SELF_ADDR_B_REG < 1) || (NUM_UNIQUE_SELF_ADDR_B_REG > 2048))) begin
$display("Error: [Unisim %s-123] NUM_UNIQUE_SELF_ADDR_B attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_UNIQUE_SELF_ADDR_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((NUM_URAM_IN_MATRIX_REG < 1) || (NUM_URAM_IN_MATRIX_REG > 2048))) begin
$display("Error: [Unisim %s-124] NUM_URAM_IN_MATRIX attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_URAM_IN_MATRIX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_A_REG != "FALSE") &&
(OREG_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-125] OREG_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_B_REG != "FALSE") &&
(OREG_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-126] OREG_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_ECC_A_REG != "FALSE") &&
(OREG_ECC_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-127] OREG_ECC_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_ECC_B_REG != "FALSE") &&
(OREG_ECC_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-128] OREG_ECC_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REG_CAS_A_REG != "FALSE") &&
(REG_CAS_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-129] REG_CAS_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, REG_CAS_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REG_CAS_B_REG != "FALSE") &&
(REG_CAS_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-130] REG_CAS_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, REG_CAS_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RST_MODE_A_REG != "SYNC") &&
(RST_MODE_A_REG != "ASYNC"))) begin
$display("Error: [Unisim %s-131] RST_MODE_A attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RST_MODE_B_REG != "SYNC") &&
(RST_MODE_B_REG != "ASYNC"))) begin
$display("Error: [Unisim %s-132] RST_MODE_B attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_EXT_CE_A_REG != "FALSE") &&
(USE_EXT_CE_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-137] USE_EXT_CE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_EXT_CE_B_REG != "FALSE") &&
(USE_EXT_CE_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-138] USE_EXT_CE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_B_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
// define tasks, functions
reg cas_a_warning = 1'b0;
reg cas_b_warning = 1'b0;
task is_cas_a_zero;
integer i;
begin
cas_a_warning = 1'b0;
for (i=0;i<=22;i=i+1) begin
if (CAS_IN_ADDR_A[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_ADDR_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
for (i=0;i<=8;i=i+1) begin
if (CAS_IN_BWE_A[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_BWE_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
if (CAS_IN_DBITERR_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_DBITERR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DIN_A[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_DIN_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DOUT_A[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_DOUT_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
if (CAS_IN_EN_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_EN_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_RDACCESS_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_RDACCESS_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_RDB_WR_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_RDB_WR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_SBITERR_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_SBITERR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
end
endtask // is_cas_a_zero
task is_cas_a_floating;
integer i;
begin
cas_a_warning = 1'b0;
for (i=0;i<=22;i=i+1) begin
if (CAS_IN_ADDR_A[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_ADDR_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
for (i=0;i<=8;i=i+1) begin
if (CAS_IN_BWE_A[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_BWE_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
if (CAS_IN_DBITERR_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_DBITERR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DIN_A[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_DIN_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DOUT_A[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_DOUT_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
if (CAS_IN_EN_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_EN_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_RDACCESS_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_RDACCESS_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_RDB_WR_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_RDB_WR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_SBITERR_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_SBITERR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
end
endtask // is_cas_a_floating
task is_cas_b_zero;
integer i;
begin
cas_b_warning = 1'b0;
for (i=0;i<=22;i=i+1) begin
if (CAS_IN_ADDR_B[i] !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_ADDR_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG);
end
end
for (i=0;i<=8;i=i+1) begin
if (CAS_IN_BWE_B[i] !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_BWE_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG);
end
end
if (CAS_IN_DBITERR_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_DBITERR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DIN_B[i] !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_DIN_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG);
end
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DOUT_B[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_DOUT_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG);
end
end
if (CAS_IN_EN_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_EN_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if (CAS_IN_RDACCESS_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_RDACCESS_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if (CAS_IN_RDB_WR_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_RDB_WR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if (CAS_IN_SBITERR_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_SBITERR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
end
endtask // is_cas_b_zero
task is_cas_b_floating;
integer i;
begin
cas_b_warning = 1'b0;
for (i=0;i<=22;i=i+1) begin
if (CAS_IN_ADDR_B[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_ADDR_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
for (i=0;i<=8;i=i+1) begin
if (CAS_IN_BWE_B[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_BWE_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
if (CAS_IN_DBITERR_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_DBITERR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DIN_B[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_DIN_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DOUT_B[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_DOUT_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
if (CAS_IN_EN_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_EN_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CAS_IN_RDACCESS_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_RDACCESS_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CAS_IN_RDB_WR_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_RDB_WR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CAS_IN_SBITERR_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_SBITERR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
end
endtask // is_cas_b_floating
function [7:0] fn_ecc (
input encode,
input [63:0] d_i,
input [7:0] dp_i
);
reg ecc_7;
begin
fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^
d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^
d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^
d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^
d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^
d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^
d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63];
fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^
d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^
d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^
d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^
d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^
d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^
d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63];
fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^
d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^
d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^
d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^
d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^
d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^
d_i[62] ^ d_i[63];
ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^
d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^
d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^
d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^
d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^
d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^
d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^
d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^
d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^
d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^
d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^
d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^
d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
if (encode) begin
fn_ecc[7] = ecc_7 ^
fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^
fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6];
end
else begin
fn_ecc[7] = ecc_7 ^
dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^
dp_i[4] ^ dp_i[5] ^ dp_i[6];
end
end
endfunction // fn_ecc
function [71:0] fn_cor_bit (
input [6:0] error_bit,
input [63:0] d_i,
input [7:0] dp_i
);
reg [71:0] cor_int;
begin
cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4],
d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0],
dp_i[7]};
cor_int[error_bit] = ~cor_int[error_bit];
fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16],
cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65],
cor_int[63:33], cor_int[31:17], cor_int[15:9],
cor_int[7:5], cor_int[3]};
end
endfunction // fn_cor_bit
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_A_REG != "NONE") &&
(USE_EXT_CE_A_REG == "TRUE"))) begin
$display("Error: [Unisim %s-1] CASCADE_ORDER_A attribute is set to %s and USE_EXT_CE_A attribute is set to %s. EXT_CE_A can not be used in cascaded URAM applications. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG, USE_EXT_CE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_B_REG != "NONE") &&
(USE_EXT_CE_B_REG == "TRUE"))) begin
$display("Error: [Unisim %s-2] CASCADE_ORDER_B attribute is set to %s and USE_EXT_CE_B attribute is set to %s. EXT_CE_B can not be used in cascaded URAM applications. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG, USE_EXT_CE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CASCADE_ORDER_A_REG == "NONE") ||
(CASCADE_ORDER_A_REG == "FIRST")) begin
is_cas_a_zero;
if (cas_a_warning) $display("Warning: [Unisim %s-13] CASCADE_ORDER_A attribute is set to %s and some or all of the CASCADE signals are not tied low. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly tied off. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if ((attr_test == 1'b1) ||
(CASCADE_ORDER_A_REG == "LAST") ||
(CASCADE_ORDER_A_REG == "MIDDLE")) begin
is_cas_a_floating;
if (cas_a_warning) $display("Warning: [Unisim %s-13] CASCADE_ORDER_A attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if ((attr_test == 1'b1) ||
(CASCADE_ORDER_B_REG == "NONE") ||
(CASCADE_ORDER_B_REG == "FIRST")) begin
is_cas_b_zero;
if (cas_b_warning) $display("Warning: [Unisim %s-14] CASCADE_ORDER_B attribute is set to %s and some or all of the CASCADE signals are not tied low. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly tied off. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if ((attr_test == 1'b1) ||
(CASCADE_ORDER_B_REG == "LAST") ||
(CASCADE_ORDER_B_REG == "MIDDLE")) begin
is_cas_b_floating;
if (cas_b_warning) $display("Warning: [Unisim %s-14] CASCADE_ORDER_B attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if ((attr_test == 1'b1) ||
((EN_AUTO_SLEEP_MODE_REG == "TRUE") &&
(USE_EXT_CE_A_REG == "TRUE"))) begin
$display("Error: [Unisim %s-19] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_A is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_AUTO_SLEEP_MODE_REG == "TRUE") &&
(USE_EXT_CE_B_REG == "TRUE"))) begin
$display("Error: [Unisim %s-20] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_B is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_B_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
localparam mem_width = 72;
localparam mem_depth = 4 * 1024;
localparam encode = 1'b1;
localparam decode = 1'b0;
localparam [22:0] ADDR_INIT = 23'b0;
localparam [8:0] BWE_INIT = 9'b0;
localparam [mem_width-1:0] D_INIT = {mem_width{1'b0}};
localparam [mem_width-1:0] D_UNDEF = {mem_width{1'bx}};
reg [mem_width-1 : 0 ] mem [0 : mem_depth-1];
integer wa;
reg [11:0] ram_addr_a;
reg [11:0] ram_addr_b;
reg ram_ce_a;
reg ram_ce_b;
reg DEEPSLEEP_in = 1'b0;
reg SHUTDOWN_in = 1'b0;
reg ram_ce_a_int=0;
reg ram_ce_b_int=0;
reg ram_ce_a_pre=0;
reg ram_ce_b_pre=0;
reg [15:1] ram_ce_a_fifo;
reg [15:1] ram_ce_b_fifo;
reg [71:0] ram_bwe_a;
reg [71:0] ram_bwe_b;
reg ram_we_a;
reg ram_we_b;
reg ram_we_a_event = 1'b0;
reg ram_we_b_event = 1'b0;
reg [71:0] ram_data_a;
reg [71:0] ram_data_b;
// input register stages
// decisions simulate faster than assignments - wider muxes, less busses
reg [22:0] ADDR_A_reg;
reg [22:0] ADDR_B_reg;
reg [8:0] BWE_A_reg;
reg [8:0] BWE_B_reg;
reg [71:0] DIN_A_reg;
reg [71:0] DIN_B_reg;
reg EN_A_reg;
reg EN_B_reg;
reg INJECT_DBITERR_A_reg;
reg INJECT_DBITERR_B_reg;
reg INJECT_SBITERR_A_reg;
reg INJECT_SBITERR_B_reg;
reg RDB_WR_A_reg;
reg RDB_WR_B_reg;
reg [22:0] ADDR_A_int;
reg [22:0] ADDR_B_int;
reg [8:0] BWE_A_int;
reg [8:0] BWE_B_int;
reg [71:0] DIN_A_int;
reg [71:0] DIN_B_int;
reg EN_A_int;
reg EN_B_int;
reg INJECT_DBITERR_A_int;
reg INJECT_DBITERR_B_int;
reg INJECT_SBITERR_A_int;
reg INJECT_SBITERR_B_int;
reg RDB_WR_A_int;
reg RDB_WR_B_int;
reg RST_A_async = 1'b0;
reg RST_B_async = 1'b0;
reg RST_A_sync = 1'b0;
reg RST_B_sync = 1'b0;
integer wake_count;
wire auto_sleep;
reg shut_down;
reg a_sleep;
reg auto_sleep_A;
reg auto_sleep_B;
wire auto_wake_up_A;
wire auto_wake_up_B;
reg CAS_OUT_DBITERR_A_out;
reg CAS_OUT_DBITERR_B_out;
reg CAS_OUT_EN_A_out;
reg CAS_OUT_EN_B_out;
reg CAS_OUT_RDACCESS_A_out;
reg CAS_OUT_RDACCESS_B_out;
reg CAS_OUT_RDB_WR_A_out;
reg CAS_OUT_RDB_WR_B_out;
reg CAS_OUT_SBITERR_A_out;
reg CAS_OUT_SBITERR_B_out;
reg DBITERR_A_out;
reg DBITERR_B_out;
reg RDACCESS_A_out;
reg RDACCESS_B_out;
reg SBITERR_A_out;
reg SBITERR_B_out;
reg [22:0] CAS_OUT_ADDR_A_out;
reg [22:0] CAS_OUT_ADDR_B_out;
reg [71:0] CAS_OUT_DIN_A_out;
reg [71:0] CAS_OUT_DIN_B_out;
reg [71:0] CAS_OUT_DOUT_A_out;
reg [71:0] CAS_OUT_DOUT_B_out;
reg [71:0] DOUT_A_out;
reg [71:0] DOUT_B_out;
reg [8:0] CAS_OUT_BWE_A_out;
reg [8:0] CAS_OUT_BWE_B_out;
assign CAS_OUT_ADDR_A = CAS_OUT_ADDR_A_out;
assign CAS_OUT_ADDR_B = CAS_OUT_ADDR_B_out;
assign CAS_OUT_BWE_A = CAS_OUT_BWE_A_out;
assign CAS_OUT_BWE_B = CAS_OUT_BWE_B_out;
assign CAS_OUT_DBITERR_A = DBITERR_A_out;
assign CAS_OUT_DBITERR_B = DBITERR_B_out;
assign CAS_OUT_DIN_A = CAS_OUT_DIN_A_out;
assign CAS_OUT_DIN_B = CAS_OUT_DIN_B_out;
assign CAS_OUT_DOUT_A = DOUT_A_out;
assign CAS_OUT_DOUT_B = DOUT_B_out;
assign CAS_OUT_EN_A = CAS_OUT_EN_A_out;
assign CAS_OUT_EN_B = CAS_OUT_EN_B_out;
assign CAS_OUT_RDACCESS_A = RDACCESS_A_out;
assign CAS_OUT_RDACCESS_B = RDACCESS_B_out;
assign CAS_OUT_RDB_WR_A = CAS_OUT_RDB_WR_A_out;
assign CAS_OUT_RDB_WR_B = CAS_OUT_RDB_WR_B_out;
assign CAS_OUT_SBITERR_A = SBITERR_A_out;
assign CAS_OUT_SBITERR_B = SBITERR_B_out;
assign DBITERR_A = DBITERR_A_out;
assign DBITERR_B = DBITERR_B_out;
assign DOUT_A = DOUT_A_out;
assign DOUT_B = DOUT_B_out;
assign RDACCESS_A = RDACCESS_A_out;
assign RDACCESS_B = RDACCESS_B_out;
assign SBITERR_A = SBITERR_A_out;
assign SBITERR_B = SBITERR_B_out;
`ifndef XIL_XECLIB
reg INIT_RAM = 1'b0;
initial begin
#100; INIT_RAM = 1'b1;
end
`endif
`ifndef XIL_XECLIB
reg rst_a_warn_once = 1'b0;
reg rst_b_warn_once = 1'b0;
always @(posedge CLK_in) begin
if ((attr_test == 1'b1) ||
((EN_A_int == 1'b1) && (RDB_WR_A_int == 1'b0) &&
((RST_A_sync == 1'b1) || (RST_A_async == 1'b1)) &&
(CASCADE_ORDER_A_BIN != CASCADE_ORDER_A_NONE) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
if (rst_a_warn_once == 1'b0) begin
$display("Warning: [Unisim %s-11] At time (%.3f) ns: CASCADE_ORDER_A attribute is set to %s and REG_CAS_A attribute is set to %s with RST_A and a READ command both active. In certain circumstances the implementation tools optimize the uram pipeline to achieve optimal timing. This is achieved by manipulating the REG_CAS_A attributes. This will not alter the latency of the pipeline but may result in different reset behavior pre and post implementation under these conditions. To avoid this, deassert EN_A when RST_A is active. Instance: %m", MODULE_NAME, $time/1000.0, CASCADE_ORDER_A_REG, REG_CAS_A_REG);
rst_a_warn_once = 1'b1;
end
end else begin
rst_a_warn_once = 1'b0;
end
end
always @(posedge CLK_in) begin
if ((attr_test == 1'b1) ||
((EN_B_int == 1'b1) && (RDB_WR_B_int == 1'b0) &&
((RST_B_sync == 1'b1) || (RST_B_async == 1'b1)) &&
(CASCADE_ORDER_B_BIN != CASCADE_ORDER_B_NONE) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
if (rst_b_warn_once == 1'b0) begin
$display("Warning: [Unisim %s-12] At time (%.3f) ns: CASCADE_ORDER_B attribute is set to %s and REG_CAS_B attribute is set to %s with RST_B and a READ command both active. In certain circumstances the implementation tools optimize the uram pipeline to achieve optimal timing. This is achieved by manipulating the REG_CAS_B attributes. This will not alter the latency of the pipeline but may result in different reset behavior pre and post implementation under these conditions. To avoid this, deassert EN_B when RST_B is active. Instance: %m", MODULE_NAME, $time/1000.0, CASCADE_ORDER_B_REG, REG_CAS_B_REG);
rst_b_warn_once = 1'b1;
end
end else begin
rst_b_warn_once = 1'b0;
end
end
`endif
always @ (*) begin
if (RST_MODE_A_BIN == RST_MODE_A_ASYNC) begin
RST_A_async = RST_A_in;
end
end
always @ (*) begin
if (RST_MODE_B_BIN == RST_MODE_B_ASYNC) begin
RST_B_async = RST_B_in;
end
end
always @ (posedge CLK_in) begin
if ((RST_MODE_A_BIN == RST_MODE_A_SYNC) && (RST_A_sync !== RST_A_in))
RST_A_sync <= RST_A_in;
if ((RST_MODE_B_BIN == RST_MODE_B_SYNC) && (RST_B_sync !== RST_B_in))
RST_B_sync <= RST_B_in;
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR ||
(((CASCADE_ORDER_A_BIN != CASCADE_ORDER_A_NONE) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) &&
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_FALSE)))) begin
ADDR_A_reg <= ADDR_INIT;
EN_A_reg <= 1'b0;
RDB_WR_A_reg <= 1'b0;
BWE_A_reg <= BWE_INIT;
DIN_A_reg <= D_INIT;
INJECT_DBITERR_A_reg <= 1'b0;
INJECT_SBITERR_A_reg <= 1'b0;
end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE)) begin
EN_A_reg <= CAS_IN_EN_A_in;
if (CAS_IN_EN_A_in) begin
ADDR_A_reg[22:12] <= CAS_IN_ADDR_A_in[22:12];
end
if (CAS_IN_EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_A_reg[11:0] <= CAS_IN_ADDR_A_in[11:0];
BWE_A_reg <= CAS_IN_BWE_A_in;
DIN_A_reg <= CAS_IN_DIN_A_in;
RDB_WR_A_reg <= CAS_IN_RDB_WR_A_in;
end
end else begin
EN_A_reg <= EN_A_in;
if (EN_A_in) begin
ADDR_A_reg[22:12] <= ADDR_A_in[22:12];
end
if (EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_A_reg[11:0] <= ADDR_A_in[11:0];
BWE_A_reg <= BWE_A_in;
DIN_A_reg <= DIN_A_in;
INJECT_DBITERR_A_reg <= INJECT_DBITERR_A_in;
INJECT_SBITERR_A_reg <= INJECT_SBITERR_A_in;
RDB_WR_A_reg <= RDB_WR_A_in;
end
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
ADDR_A_int = CAS_IN_ADDR_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
ADDR_A_int = ADDR_A_reg;
end else begin
ADDR_A_int = ADDR_A_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
BWE_A_int = CAS_IN_BWE_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
BWE_A_int = BWE_A_reg;
end else begin
BWE_A_int = BWE_A_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
DIN_A_int = CAS_IN_DIN_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
DIN_A_int = DIN_A_reg;
end else begin
DIN_A_int = DIN_A_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
EN_A_int = CAS_IN_EN_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
EN_A_int = EN_A_reg;
end else begin
EN_A_int = EN_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
INJECT_DBITERR_A_int = INJECT_DBITERR_A_reg;
end else begin
INJECT_DBITERR_A_int = INJECT_DBITERR_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
INJECT_SBITERR_A_int = INJECT_SBITERR_A_reg;
end else begin
INJECT_SBITERR_A_int = INJECT_SBITERR_A_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
RDB_WR_A_int = CAS_IN_RDB_WR_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
RDB_WR_A_int = RDB_WR_A_reg;
end else begin
RDB_WR_A_int = RDB_WR_A_in;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR ||
(((CASCADE_ORDER_B_BIN != CASCADE_ORDER_B_NONE) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) &&
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_FALSE)))) begin
ADDR_B_reg <= ADDR_INIT;
EN_B_reg <= 1'b0;
RDB_WR_B_reg <= 1'b0;
BWE_B_reg <= BWE_INIT;
DIN_B_reg <= D_INIT;
INJECT_DBITERR_B_reg <= 1'b0;
INJECT_SBITERR_B_reg <= 1'b0;
end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE)) begin
EN_B_reg <= CAS_IN_EN_B_in;
if (CAS_IN_EN_B_in) begin
ADDR_B_reg[22:12] <= CAS_IN_ADDR_B_in[22:12];
end
if (CAS_IN_EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_B_reg[11:0] <= CAS_IN_ADDR_B_in[11:0];
BWE_B_reg <= CAS_IN_BWE_B_in;
DIN_B_reg <= CAS_IN_DIN_B_in;
RDB_WR_B_reg <= CAS_IN_RDB_WR_B_in;
end
end else begin
EN_B_reg <= EN_B_in;
if (EN_B_in) begin
ADDR_B_reg[22:12] <= ADDR_B_in[22:12];
end
if (EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_B_reg[11:0] <= ADDR_B_in[11:0];
BWE_B_reg <= BWE_B_in;
DIN_B_reg <= DIN_B_in;
INJECT_DBITERR_B_reg <= INJECT_DBITERR_B_in;
INJECT_SBITERR_B_reg <= INJECT_SBITERR_B_in;
RDB_WR_B_reg <= RDB_WR_B_in;
end
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
ADDR_B_int = CAS_IN_ADDR_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
ADDR_B_int = ADDR_B_reg;
end else begin
ADDR_B_int = ADDR_B_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
BWE_B_int = CAS_IN_BWE_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
BWE_B_int = BWE_B_reg;
end else begin
BWE_B_int = BWE_B_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
DIN_B_int = CAS_IN_DIN_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
DIN_B_int = DIN_B_reg;
end else begin
DIN_B_int = DIN_B_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
EN_B_int = CAS_IN_EN_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
EN_B_int = EN_B_reg;
end else begin
EN_B_int = EN_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
INJECT_DBITERR_B_int = INJECT_DBITERR_B_reg;
end else begin
INJECT_DBITERR_B_int = INJECT_DBITERR_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
INJECT_SBITERR_B_int = INJECT_SBITERR_B_reg;
end else begin
INJECT_SBITERR_B_int = INJECT_SBITERR_B_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
RDB_WR_B_int = CAS_IN_RDB_WR_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
RDB_WR_B_int = RDB_WR_B_reg;
end else begin
RDB_WR_B_int = RDB_WR_B_in;
end
end
// cascade out - input controls
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_ADDR_A_out = ADDR_INIT;
end else begin
CAS_OUT_ADDR_A_out = ADDR_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_BWE_A_out = BWE_INIT;
end else begin
CAS_OUT_BWE_A_out = BWE_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_DIN_A_out = D_INIT;
end else begin
CAS_OUT_DIN_A_out = DIN_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_EN_A_out = 1'b0;
end else begin
CAS_OUT_EN_A_out = EN_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_RDB_WR_A_out = 1'b0;
end else begin
CAS_OUT_RDB_WR_A_out = RDB_WR_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_ADDR_B_out = ADDR_INIT;
end else begin
CAS_OUT_ADDR_B_out = ADDR_B_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_BWE_B_out = BWE_INIT;
end else begin
CAS_OUT_BWE_B_out = BWE_B_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_DIN_B_out = D_INIT;
end else begin
CAS_OUT_DIN_B_out = DIN_B_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_EN_B_out = 1'b0;
end else begin
CAS_OUT_EN_B_out = EN_B_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_RDB_WR_B_out = 1'b0;
end else begin
CAS_OUT_RDB_WR_B_out = RDB_WR_B_int;
end
end
// cascade=data out - outputs
reg [71:0] ram_data_a_lat;
reg [71:0] ram_data_a_out;
// reg [71:0] ram_data_a_hold=D_INIT;
reg [71:0] ram_data_a_reg;
reg [71:0] ram_data_a_ecc=72'h000000000000000000;
reg [71:0] ram_data_b_lat;
reg [71:0] ram_data_b_out;
reg [71:0] ram_data_b_reg;
reg [71:0] ram_data_b_ecc=72'h000000000000000000;
reg RDACCESS_A_lat;
// reg RDACCESS_A_hold;
reg RDACCESS_B_lat;
reg RDACCESS_A_int;
reg RDACCESS_B_int;
reg SBITERR_A_ecc=1'b0;
reg DBITERR_A_ecc=1'b0;
reg SBITERR_B_ecc=1'b0;
reg DBITERR_B_ecc=1'b0;
reg DBITERR_A_reg;
reg DBITERR_B_reg;
reg [71:0] DOUT_A_reg;
reg [71:0] DOUT_B_reg;
reg RDACCESS_A_reg;
reg RDACCESS_B_reg;
reg SBITERR_A_reg;
reg SBITERR_B_reg;
reg RDACCESS_A_ecc_reg;
reg RDACCESS_B_ecc_reg;
reg CAS_IN_DBITERR_A_reg;
reg CAS_IN_DBITERR_B_reg;
reg [71:0] CAS_IN_DOUT_A_reg;
reg [71:0] CAS_IN_DOUT_B_reg;
reg CAS_IN_RDACCESS_A_reg;
reg CAS_IN_RDACCESS_B_reg;
reg CAS_IN_SBITERR_A_reg;
reg CAS_IN_SBITERR_B_reg;
reg data_A_enable = 1'b0;
reg data_B_enable = 1'b0;
// data/cas reg
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
`endif
CAS_IN_DBITERR_A_reg <= 1'b0;
CAS_IN_DOUT_A_reg <= D_INIT;
CAS_IN_RDACCESS_A_reg <= 1'b0;
CAS_IN_SBITERR_A_reg <= 1'b0;
end else begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) begin
CAS_IN_RDACCESS_A_reg <= CAS_IN_RDACCESS_A_in;
if (CAS_IN_RDACCESS_A_in) begin
CAS_IN_DBITERR_A_reg <= CAS_IN_DBITERR_A_in;
CAS_IN_DOUT_A_reg <= CAS_IN_DOUT_A_in;
CAS_IN_SBITERR_A_reg <= CAS_IN_SBITERR_A_in;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
`endif
CAS_IN_DBITERR_B_reg <= 1'b0;
CAS_IN_DOUT_B_reg <= D_INIT;
CAS_IN_RDACCESS_B_reg <= 1'b0;
CAS_IN_SBITERR_B_reg <= 1'b0;
end else begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) begin
CAS_IN_RDACCESS_B_reg <= CAS_IN_RDACCESS_B_in;
if (CAS_IN_RDACCESS_B_in) begin
CAS_IN_DBITERR_B_reg <= CAS_IN_DBITERR_B_in;
CAS_IN_DOUT_B_reg <= CAS_IN_DOUT_B_in;
CAS_IN_SBITERR_B_reg <= CAS_IN_SBITERR_B_in;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR ||
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR ||
`endif
shut_down || SHUTDOWN_in) begin
RDACCESS_A_int = 1'b0;
end else begin
if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin
RDACCESS_A_int = RDACCESS_A_ecc_reg;
end else begin
RDACCESS_A_int = 1'b0;
end
end else if (OREG_A_BIN == OREG_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin
RDACCESS_A_int = RDACCESS_A_reg;
end else begin
RDACCESS_A_int = 1'b0;
end
end else begin
RDACCESS_A_int = RDACCESS_A_lat;
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR ||
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR ||
`endif
shut_down || SHUTDOWN_in) begin
RDACCESS_B_int = 1'b0;
end else begin
if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin
RDACCESS_B_int = RDACCESS_B_ecc_reg;
end else begin
RDACCESS_B_int = 1'b0;
end
end else if (OREG_B_BIN == OREG_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin
RDACCESS_B_int = RDACCESS_B_reg;
end else begin
RDACCESS_B_int = 1'b0;
end
end else begin
RDACCESS_B_int = RDACCESS_B_lat;
end
end
end
reg cas_out_mux_sel_a;
reg cas_out_mux_sel_b;
reg cas_out_mux_sel_a_reg;
reg cas_out_mux_sel_b_reg;
always @ (*) begin
if ((CAS_IN_RDACCESS_A_in && REG_CAS_A_BIN == REG_CAS_A_FALSE) ||
(CAS_IN_RDACCESS_A_reg && REG_CAS_A_BIN == REG_CAS_A_TRUE) ||
RDACCESS_A_int) begin
cas_out_mux_sel_a = ~RDACCESS_A_int;
end else begin
cas_out_mux_sel_a = ~cas_out_mux_sel_a_reg;
end
end
always @ (*) begin
if ((CAS_IN_RDACCESS_B_in && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) ||
(CAS_IN_RDACCESS_B_reg && (REG_CAS_B_BIN == REG_CAS_B_TRUE)) ||
RDACCESS_B_int) begin
cas_out_mux_sel_b = ~RDACCESS_B_int;
end else begin
cas_out_mux_sel_b = ~cas_out_mux_sel_b_reg;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR) begin
`endif
cas_out_mux_sel_a_reg <= 1'b0;
end else begin
cas_out_mux_sel_a_reg <= ~cas_out_mux_sel_a;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR) begin
`endif
cas_out_mux_sel_b_reg <= 1'b0;
end else begin
cas_out_mux_sel_b_reg <= ~cas_out_mux_sel_b;
end
end
// data out mux
always @ (*) begin
if (RST_A_async || RST_A_sync || glblGSR) begin
RDACCESS_A_out = 1'b0;
end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
cas_out_mux_sel_a) begin
if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin
RDACCESS_A_out = CAS_IN_RDACCESS_A_reg;
end else begin
RDACCESS_A_out = CAS_IN_RDACCESS_A_in;
end
end else begin
RDACCESS_A_out = RDACCESS_A_int;
end
end
always @ (*) begin
if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin
DBITERR_A_out = 1'b0;
SBITERR_A_out = 1'b0;
end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
cas_out_mux_sel_a) begin
if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin
DBITERR_A_out = CAS_IN_DBITERR_A_reg;
SBITERR_A_out = CAS_IN_SBITERR_A_reg;
end else begin
DBITERR_A_out = CAS_IN_DBITERR_A_in;
SBITERR_A_out = CAS_IN_SBITERR_A_in;
end
end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin
DBITERR_A_out = DBITERR_A_reg;
SBITERR_A_out = SBITERR_A_reg;
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DBITERR_A_out = DBITERR_A_ecc;
SBITERR_A_out = SBITERR_A_ecc;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`endif
data_A_enable <= 1'b0;
end else if ((OREG_A_BIN == OREG_A_TRUE) && ram_ce_a && ~ram_we_a) begin
data_A_enable <= 1'b1;
end else if ((OREG_A_BIN == OREG_A_FALSE) && ram_ce_a_int && ~RDB_WR_A_int) begin
data_A_enable <= 1'b1;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`endif
data_B_enable <= 1'b0;
end else if ((OREG_B_BIN == OREG_B_TRUE) && ram_ce_b && ~ram_we_b) begin
data_B_enable <= 1'b1;
end else if ((OREG_B_BIN == OREG_B_FALSE) && ram_ce_b_int && ~RDB_WR_B_int) begin
data_B_enable <= 1'b1;
end
end
always @ (posedge CLK_in) begin
if (ram_ce_a && ~ram_we_a && SLEEP_in && ~a_sleep && (OREG_A_BIN == OREG_A_TRUE)) begin
$display("Warning: [Unisim %s-3] At time (%.3f) ns: Port A READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_A attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a, OREG_A_REG);
end else if (ram_ce_a && ram_we_a && SLEEP_in && ~a_sleep) begin
$display("Warning: [Unisim %s-4] At time (%.3f) ns: Port A WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a);
end else if (ram_ce_a_pre && a_sleep && SLEEP_in) begin
$display("Warning: [Unisim %s-5] At time (%.3f) ns: Port A access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a);
end else if (ram_ce_a_pre && a_sleep && ~SLEEP_in) begin
$display("Warning: [Unisim %s-6] At time (%.3f) ns: Port A access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a);
end
end
always @ (posedge CLK_in) begin
if (ram_ce_b && ~ram_we_b && SLEEP_in && ~a_sleep && (OREG_B_BIN == OREG_B_TRUE)) begin
$display("Warning: [Unisim %s-7] At time (%.3f) ns: Port B READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_B attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b, OREG_B_REG);
end else if (ram_ce_b && ram_we_b && SLEEP_in && ~a_sleep) begin
$display("Warning: [Unisim %s-8] At time (%.3f) ns: Port B WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b);
end else if (ram_ce_b_pre && a_sleep && SLEEP_in) begin
$display("Warning: [Unisim %s-9] At time (%.3f) ns: Port B access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b);
end else if (ram_ce_b_pre && a_sleep && ~SLEEP_in) begin
$display("Warning: [Unisim %s-10] At time (%.3f) ns: Port B access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b);
end
end
always @ (*) begin
if (RST_A_async || RST_A_sync || glblGSR) begin
DOUT_A_out = D_INIT;
end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
cas_out_mux_sel_a) begin
if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin
DOUT_A_out = CAS_IN_DOUT_A_reg;
end else begin
DOUT_A_out = CAS_IN_DOUT_A_in;
end
end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin
DOUT_A_out = DOUT_A_reg;
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DOUT_A_out = ram_data_a_ecc;
end else if (data_A_enable) begin
if (OREG_A_BIN == OREG_A_TRUE) begin
DOUT_A_out = ram_data_a_reg;
end else begin
DOUT_A_out = ram_data_a_lat;
end
end else begin
DOUT_A_out = D_INIT;
end
end
always @ (*) begin
if (RST_B_async || RST_B_sync || glblGSR) begin
RDACCESS_B_out = 1'b0;
end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
cas_out_mux_sel_b) begin
if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin
RDACCESS_B_out = CAS_IN_RDACCESS_B_reg;
end else begin
RDACCESS_B_out = CAS_IN_RDACCESS_B_in;
end
end else begin
RDACCESS_B_out = RDACCESS_B_int;
end
end
always @ (*) begin
if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin
DBITERR_B_out = 1'b0;
SBITERR_B_out = 1'b0;
end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
cas_out_mux_sel_b) begin
if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin
DBITERR_B_out = CAS_IN_DBITERR_B_reg;
SBITERR_B_out = CAS_IN_SBITERR_B_reg;
end else begin
DBITERR_B_out = CAS_IN_DBITERR_B_in;
SBITERR_B_out = CAS_IN_SBITERR_B_in;
end
end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin
DBITERR_B_out = DBITERR_B_reg;
SBITERR_B_out = SBITERR_B_reg;
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DBITERR_B_out = DBITERR_B_ecc;
SBITERR_B_out = SBITERR_B_ecc;
end
end
always @ (*) begin
if (RST_B_async || RST_B_sync || glblGSR) begin
DOUT_B_out = D_INIT;
end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
cas_out_mux_sel_b) begin
if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin
DOUT_B_out = CAS_IN_DOUT_B_reg;
end else begin
DOUT_B_out = CAS_IN_DOUT_B_in;
end
end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin
DOUT_B_out = DOUT_B_reg;
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DOUT_B_out = ram_data_b_ecc;
end else if (data_B_enable) begin
if (OREG_B_BIN == OREG_B_TRUE) begin
DOUT_B_out = ram_data_b_reg;
end else begin
DOUT_B_out = ram_data_b_lat;
end
end else begin
DOUT_B_out = D_INIT;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`endif
DBITERR_A_reg <= 1'b0;
SBITERR_A_reg <= 1'b0;
end else if ((~a_sleep && ~shut_down && data_A_enable) &&
(((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) ||
((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg)))) begin
if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin
DBITERR_A_reg <= DBITERR_A_ecc;
SBITERR_A_reg <= SBITERR_A_ecc;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`endif
DOUT_A_reg <= D_INIT;
end else if (~shut_down && data_A_enable) begin
if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin
if (OREG_ECC_CE_A_in) begin
if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DOUT_A_reg <= ram_data_a_ecc;
end else if (OREG_A_BIN == OREG_A_TRUE) begin
DOUT_A_reg <= ram_data_a_reg;
end else begin
DOUT_A_reg <= ram_data_a_lat;
end
end
end else if (((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) ||
((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg))) begin
if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DOUT_A_reg <= ram_data_a_ecc;
end else if (OREG_A_BIN == OREG_A_TRUE) begin
DOUT_A_reg <= ram_data_a_reg;
end else begin
DOUT_A_reg <= ram_data_a_lat;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`endif
RDACCESS_A_ecc_reg <= 1'b0;
end else begin
if (OREG_A_BIN == OREG_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin
RDACCESS_A_ecc_reg <= RDACCESS_A_reg;
end
end else begin
RDACCESS_A_ecc_reg <= RDACCESS_A_lat;
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`endif
DBITERR_B_reg <= 1'b0;
SBITERR_B_reg <= 1'b0;
end else if ((~a_sleep && ~shut_down && data_B_enable) &&
(((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) ||
((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg)))) begin
if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin
DBITERR_B_reg <= DBITERR_B_ecc;
SBITERR_B_reg <= SBITERR_B_ecc;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`endif
DOUT_B_reg <= D_INIT;
end else if (~shut_down && data_B_enable) begin
if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin
if (OREG_ECC_CE_B_in) begin
if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DOUT_B_reg <= ram_data_b_ecc;
end else if (OREG_B_BIN == OREG_B_TRUE) begin
DOUT_B_reg <= ram_data_b_reg;
end else begin
DOUT_B_reg <= ram_data_b_lat;
end
end
end else if (((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) ||
((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg))) begin
if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DOUT_B_reg <= ram_data_b_ecc;
end else if (OREG_B_BIN == OREG_B_TRUE) begin
DOUT_B_reg <= ram_data_b_reg;
end else begin
DOUT_B_reg <= ram_data_b_lat;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`endif
RDACCESS_B_ecc_reg <= 1'b0;
end else begin
if (OREG_B_BIN == OREG_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin
RDACCESS_B_ecc_reg <= RDACCESS_B_reg;
end
end else begin
RDACCESS_B_ecc_reg <= RDACCESS_B_lat;
end
end
end
// ram oreg
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || shut_down || a_sleep || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin
if (RST_A_in || shut_down || a_sleep || glblGSR) begin
`endif
RDACCESS_A_reg <= 1'b0;
end else begin
RDACCESS_A_reg <= RDACCESS_A_lat;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin
if (RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin
`endif
ram_data_a_reg <= D_INIT;
end else if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin
if (OREG_CE_A_in) begin
ram_data_a_reg = ram_data_a_lat;
end
end else if (ram_ce_a_int || RDACCESS_A_reg) begin
ram_data_a_reg = ram_data_a_lat;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || shut_down || a_sleep || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin
if (RST_B_in || shut_down || a_sleep || glblGSR) begin
`endif
RDACCESS_B_reg <= 1'b0;
end else begin
RDACCESS_B_reg <= RDACCESS_B_lat;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin
if (RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin
`endif
ram_data_b_reg <= D_INIT;
end else if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin
if (OREG_CE_B_in) begin
ram_data_b_reg = ram_data_b_lat;
end
end else if (ram_ce_b_int || RDACCESS_B_reg) begin
ram_data_b_reg = ram_data_b_lat;
end
end
reg [15:1] ram_ce_a_fifo_in = 15'b0;
always @ (*) begin
ram_ce_a_fifo_in = 15'b0;
ram_ce_a_fifo_in[AUTO_SLEEP_LATENCY_BIN] = &(~(ADDR_A_int[22:12] ^ SELF_ADDR_A_REG) | SELF_MASK_A_REG) && EN_A_int;
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
ram_ce_a_fifo <= 15'b0;
end else begin
ram_ce_a_fifo <= {1'b0, ram_ce_a_fifo[15:2]} | ram_ce_a_fifo_in;
end
end
always @ (*) begin
if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin
ram_ce_a_pre = &(~(ADDR_A_int[22:12] ^ SELF_ADDR_A_REG) | SELF_MASK_A_REG) && EN_A_int;
end else begin
ram_ce_a_pre = ram_ce_a_fifo[1];
end
end
always @ (*) begin
if (a_sleep || SLEEP_in || auto_sleep) begin
ram_ce_a_int = 1'b0;
end else begin
ram_ce_a_int = ram_ce_a_pre;
end
end
reg [15:1] ram_ce_b_fifo_in = 15'b0;
always @ (*) begin
ram_ce_b_fifo_in = 15'b0;
ram_ce_b_fifo_in[AUTO_SLEEP_LATENCY_BIN] = &(~(ADDR_B_int[22:12] ^ SELF_ADDR_B_REG) | SELF_MASK_B_REG) && EN_B_int;
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
ram_ce_b_fifo <= 15'b0;
end else begin
ram_ce_b_fifo <= {1'b0, ram_ce_b_fifo[15:2]} | ram_ce_b_fifo_in;
end
end
always @ (*) begin
if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin
ram_ce_b_pre = &(~(ADDR_B_int[22:12] ^ SELF_ADDR_B_REG) | SELF_MASK_B_REG) && EN_B_int;
end else begin
ram_ce_b_pre = ram_ce_b_fifo[1];
end
end
always @ (*) begin
if (a_sleep || SLEEP_in || auto_sleep) begin
ram_ce_b_int = 1'b0;
end else begin
ram_ce_b_int = ram_ce_b_pre;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || ~RDB_WR_A_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_bwe_a <= 72'h00;
end else if (ram_ce_a_int) begin
if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin
ram_bwe_a <= 72'hFFFFFFFFFFFFFFFFFF;
end else if (BWE_MODE_A_BIN == BWE_MODE_A_PARITY_INTERLEAVED) begin
ram_bwe_a <= {BWE_A_int[7:0],
{8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}},
{8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}};
end else begin
ram_bwe_a <= {{8{BWE_A_int[8]}},
{8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}},
{8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}};
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || ~RDB_WR_B_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_bwe_b <= 72'b0;
end else if (ram_ce_b_int) begin
if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin
ram_bwe_b <= 72'hFFFFFFFFFFFFFFFFFF;
end else if (BWE_MODE_B_BIN == BWE_MODE_B_PARITY_INTERLEAVED) begin
ram_bwe_b <= {BWE_B_int[7:0],
{8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}},
{8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}};
end else begin
ram_bwe_b <= {{8{BWE_B_int[8]}},
{8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}},
{8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}};
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_addr_a <= 12'b0;
end else if (ram_ce_a_int) begin
ram_addr_a <= ADDR_A_int[11:0];
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_addr_b <= 12'b0;
end else if (ram_ce_b_int) begin
ram_addr_b <= ADDR_B_int[11:0];
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (glblGSR || (RST_A_async || RST_A_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (glblGSR || RST_A_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`endif
ram_ce_a <= 1'b0;
end else begin
ram_ce_a <= ram_ce_a_int;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (glblGSR || (RST_B_async || RST_B_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (glblGSR || RST_B_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`endif
ram_ce_b <= 1'b0;
end else begin
ram_ce_b <= ram_ce_b_int;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_a_int) begin
ram_we_a <= 1'b0;
end else begin
ram_we_a <= RDB_WR_A_int;
if (RDB_WR_A_int) ram_we_a_event <= ~ram_we_a_event;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_b_int) begin
ram_we_b <= 1'b0;
end else begin
ram_we_b <= RDB_WR_B_int;
if (RDB_WR_B_int) ram_we_b_event <= ~ram_we_b_event;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_data_a <= D_INIT;
end else if (RDB_WR_A_int && ram_ce_a_int) begin
if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin
ram_data_a[63:0] <= {DIN_A_int[63],
DIN_A_int[62] ^ (INJECT_DBITERR_A_int),
DIN_A_int[61:31],
DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int),
DIN_A_int[29:0]};
ram_data_a[71:64] <= fn_ecc(encode, DIN_A_int[63:0], DIN_A_int[71:64]);
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
ram_data_a[63:0] <= {DIN_A_int[63],
DIN_A_int[62] ^ (INJECT_DBITERR_A_int),
DIN_A_int[61:31],
DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int),
DIN_A_int[29:0]};
ram_data_a[71:64] <= DIN_A_int[71:64];
end else begin
ram_data_a <= DIN_A_int;
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_data_b <= D_INIT;
end else if (RDB_WR_B_int && ram_ce_b_int) begin
if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin
ram_data_b[63:0] <= {DIN_B_int[63],
DIN_B_int[62] ^ (INJECT_DBITERR_B_int),
DIN_B_int[61:31],
DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int),
DIN_B_int[29:0]};
ram_data_b[71:64] <= fn_ecc(encode, DIN_B_int[63:0], DIN_B_int[71:64]);
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
ram_data_b[63:0] <= {DIN_B_int[63],
DIN_B_int[62] ^ (INJECT_DBITERR_B_int),
DIN_B_int[61:31],
DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int),
DIN_B_int[29:0]};
ram_data_b[71:64] <= DIN_B_int[71:64];
end else begin
ram_data_b <= DIN_B_int;
end
end
end
// ram
always @ (*) begin
if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) ||
(((OREG_A_BIN == OREG_A_TRUE) || (OREG_ECC_A_BIN == OREG_ECC_A_TRUE )) &&
(a_sleep || shut_down)))begin
RDACCESS_A_lat <= 1'b0;
end else if ((ram_ce_a_int === 1'b1) && (RDB_WR_A_int === 1'b0)) begin
RDACCESS_A_lat <= 1'b1;
end else begin
RDACCESS_A_lat <= 1'b0;
end
end
always @ (*) begin
if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) ||
(((OREG_B_BIN == OREG_B_TRUE) || (OREG_ECC_B_BIN == OREG_ECC_B_TRUE )) &&
(a_sleep || shut_down)))begin
RDACCESS_B_lat <= 1'b0;
end else if ((ram_ce_b_int === 1'b1) && (RDB_WR_B_int === 1'b0)) begin
RDACCESS_B_lat <= 1'b1;
end else begin
RDACCESS_B_lat <= 1'b0;
end
end
`ifndef XIL_XECLIB
// always @ (posedge INIT_RAM or posedge glblGSR) begin
always @ (posedge INIT_RAM) begin
for (wa=0;wa<mem_depth;wa=wa+1) begin
mem[wa] <= D_INIT;
end
end
always @ (posedge shut_down) begin
for (wa=0;wa<mem_depth;wa=wa+1) begin
mem[wa] <= D_UNDEF;
end
end
`endif
always @ (*) begin
if (RST_A_sync || RST_A_async || glblGSR || a_sleep || shut_down) begin
ram_data_a_lat = D_INIT;
end else if (ram_ce_a && ~ram_we_a) begin
ram_data_a_lat = ram_data_a_out;
end
end
always @ (*) begin
if (RST_B_sync || RST_B_async || glblGSR || a_sleep || shut_down) begin
ram_data_b_lat = D_INIT;
end else if (ram_ce_b && ~ram_we_b) begin
ram_data_b_lat = ram_data_b_out;
end
end
`ifdef XIL_XECLIB
always @ (posedge RST_A_async or posedge RST_B_async or posedge CLK_in) begin
`else
always @ (ram_we_a or ram_we_b or ram_ce_a or ram_ce_b or a_sleep or shut_down or ram_addr_a or ram_addr_b or ram_data_a or ram_data_b or ram_bwe_a or ram_bwe_b or ram_we_a_event or ram_we_b_event or posedge RST_A_async or posedge RST_B_async or posedge RST_A_sync or posedge RST_B_sync or glblGSR) begin
`endif
if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin
ram_data_a_out = D_INIT;
end
if (ram_we_a && ~shut_down && ~a_sleep && ~glblGSR) begin
mem [ram_addr_a] = (ram_data_a & ram_bwe_a) | (mem [ram_addr_a] & ~ram_bwe_a);
end
if (ram_ce_a && ~ram_we_a && ~RST_A_in && ~shut_down && ~a_sleep && ~glblGSR) begin
ram_data_a_out = mem[ram_addr_a];
end
if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin
ram_data_b_out = D_INIT;
end
if (ram_we_b && ~shut_down && ~a_sleep && ~glblGSR) begin
mem [ram_addr_b] = (ram_data_b & ram_bwe_b) | (mem [ram_addr_b] & ~ram_bwe_b);
end
if (ram_ce_b && ~ram_we_b && ~RST_B_in && ~shut_down && ~a_sleep && ~glblGSR) begin
ram_data_b_out = mem[ram_addr_b];
end
end
// ecc correction
task ecc_cor;
output [71:0] data_cor; output sbiterr; output dbiterr;
input [71:0] data;
reg [7:0] synd_rd; reg [7:0] synd_ecc; reg decode;
begin
decode = 1'b0;
synd_rd = fn_ecc(decode, data[63:0], data[71:64]);
synd_ecc = synd_rd ^ data[71:64];
sbiterr = (|synd_ecc && synd_ecc[7]);
dbiterr = (|synd_ecc && ~synd_ecc[7]);
if (sbiterr) begin
data_cor = fn_cor_bit(synd_ecc[6:0],data[63:0],data[71:64]);
end else begin
data_cor = data;
end
end
endtask
always @ (*) begin
if (a_sleep || shut_down || glblGSR || (EN_ECC_RD_A_BIN == EN_ECC_RD_A_FALSE)) begin
ram_data_a_ecc <= D_INIT;
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
if (OREG_A_BIN == OREG_A_TRUE) begin
ecc_cor(ram_data_a_ecc, SBITERR_A_ecc, DBITERR_A_ecc, ram_data_a_reg);
end else begin
ecc_cor(ram_data_a_ecc, SBITERR_A_ecc, DBITERR_A_ecc, ram_data_a_lat);
end
end
end
always @ (*) begin
if (a_sleep || shut_down || glblGSR || (EN_ECC_RD_B_BIN == EN_ECC_RD_B_FALSE)) begin
ram_data_b_ecc <= D_INIT;
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
if (OREG_B_BIN == OREG_B_TRUE) begin
ecc_cor(ram_data_b_ecc, SBITERR_B_ecc, DBITERR_B_ecc, ram_data_b_reg);
end else begin
ecc_cor(ram_data_b_ecc, SBITERR_B_ecc, DBITERR_B_ecc, ram_data_b_lat);
end
end
end
// sleep, deepsleep, shutdown
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR) begin
wake_count <= 0;
end else if (((wake_count > 0) &&
(~(auto_sleep || SLEEP_in || DEEPSLEEP_in || SHUTDOWN_in))) ||
(~(SHUTDOWN_in || DEEPSLEEP_in) && (wake_count > 2)) ||
(~SHUTDOWN_in && (wake_count > 3))) begin
wake_count <= wake_count - 1;
end else if (SHUTDOWN_in) begin
wake_count <= 9;
end else if (DEEPSLEEP_in && (wake_count <= 3)) begin
wake_count <= 3;
end else if (SLEEP_in && (wake_count <= 2)) begin
wake_count <= 2;
end else if (auto_sleep && (wake_count <= 1)) begin
wake_count <= 1;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (~auto_sleep && wake_count == 1)) begin
a_sleep <= 1'b0;
end else if (DEEPSLEEP_in || SLEEP_in || auto_sleep) begin
a_sleep <= 1'b1;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (wake_count == 1)) begin
shut_down <= 1'b0;
end else if (SHUTDOWN_in) begin
shut_down <= 1'b1;
end
end
assign auto_sleep = auto_sleep_A && auto_sleep_B && ~auto_wake_up_A && ~auto_wake_up_B;
assign auto_wake_up_A = ram_ce_a_fifo[3];
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
auto_sleep_A <= 1'b0;
end else if (auto_wake_up_A && auto_sleep_A) begin
auto_sleep_A <= 1'b0;
end else if (~|ram_ce_a_fifo && ~auto_sleep_A) begin
auto_sleep_A <= 1'b1;
end
end
assign auto_wake_up_B = ram_ce_b_fifo[3];
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
auto_sleep_B <= 1'b0;
end else if (auto_wake_up_B && auto_sleep_B) begin
auto_sleep_B <= 1'b0;
end else if (~|ram_ce_b_fifo && ~auto_sleep_B) begin
auto_sleep_B <= 1'b1;
end
end
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
wire clk_en_n;
wire clk_en_p;
assign clk_en_n = IS_CLK_INVERTED_REG;
assign clk_en_p = ~IS_CLK_INVERTED_REG;
`endif
specify
(ADDR_A *> CAS_OUT_ADDR_A) = (0:0:0, 0:0:0);
(ADDR_B *> CAS_OUT_ADDR_B) = (0:0:0, 0:0:0);
(BWE_A *> CAS_OUT_BWE_A) = (0:0:0, 0:0:0);
(BWE_B *> CAS_OUT_BWE_B) = (0:0:0, 0:0:0);
(CAS_IN_ADDR_A *> CAS_OUT_ADDR_A) = (0:0:0, 0:0:0);
(CAS_IN_ADDR_B *> CAS_OUT_ADDR_B) = (0:0:0, 0:0:0);
(CAS_IN_BWE_A *> CAS_OUT_BWE_A) = (0:0:0, 0:0:0);
(CAS_IN_BWE_B *> CAS_OUT_BWE_B) = (0:0:0, 0:0:0);
(CAS_IN_DBITERR_A => CAS_OUT_DBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_DBITERR_A => DBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_DBITERR_B => CAS_OUT_DBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_DBITERR_B => DBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_DIN_A *> CAS_OUT_DIN_A) = (0:0:0, 0:0:0);
(CAS_IN_DIN_B *> CAS_OUT_DIN_B) = (0:0:0, 0:0:0);
(CAS_IN_DOUT_A *> CAS_OUT_DOUT_A) = (0:0:0, 0:0:0);
(CAS_IN_DOUT_A *> DOUT_A) = (0:0:0, 0:0:0);
(CAS_IN_DOUT_B *> CAS_OUT_DOUT_B) = (0:0:0, 0:0:0);
(CAS_IN_DOUT_B *> DOUT_B) = (0:0:0, 0:0:0);
(CAS_IN_EN_A => CAS_OUT_EN_A) = (0:0:0, 0:0:0);
(CAS_IN_EN_B => CAS_OUT_EN_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A *> CAS_OUT_DOUT_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A *> DOUT_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => CAS_OUT_DBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => CAS_OUT_RDACCESS_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => CAS_OUT_SBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => DBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => RDACCESS_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => SBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B *> CAS_OUT_DOUT_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B *> DOUT_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => CAS_OUT_DBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => CAS_OUT_RDACCESS_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => CAS_OUT_SBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => DBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => RDACCESS_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => SBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_RDB_WR_A => CAS_OUT_RDB_WR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDB_WR_B => CAS_OUT_RDB_WR_B) = (0:0:0, 0:0:0);
(CAS_IN_SBITERR_A => CAS_OUT_SBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_SBITERR_A => SBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_SBITERR_B => CAS_OUT_SBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_SBITERR_B => SBITERR_B) = (0:0:0, 0:0:0);
(CLK *> CAS_OUT_ADDR_A) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_ADDR_B) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_BWE_A) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_BWE_B) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_DIN_A) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_DIN_B) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_DOUT_A) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_DOUT_B) = (100:100:100, 100:100:100);
(CLK *> DOUT_A) = (100:100:100, 100:100:100);
(CLK *> DOUT_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_DBITERR_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_DBITERR_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_EN_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_EN_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_RDACCESS_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_RDACCESS_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_RDB_WR_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_RDB_WR_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_SBITERR_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_SBITERR_B) = (100:100:100, 100:100:100);
(CLK => DBITERR_A) = (100:100:100, 100:100:100);
(CLK => DBITERR_B) = (100:100:100, 100:100:100);
(CLK => RDACCESS_A) = (100:100:100, 100:100:100);
(CLK => RDACCESS_B) = (100:100:100, 100:100:100);
(CLK => SBITERR_A) = (100:100:100, 100:100:100);
(CLK => SBITERR_B) = (100:100:100, 100:100:100);
(DIN_A *> CAS_OUT_DIN_A) = (0:0:0, 0:0:0);
(DIN_B *> CAS_OUT_DIN_B) = (0:0:0, 0:0:0);
(EN_A => CAS_OUT_EN_A) = (0:0:0, 0:0:0);
(EN_B => CAS_OUT_EN_B) = (0:0:0, 0:0:0);
(RDB_WR_A => CAS_OUT_RDB_WR_A) = (0:0:0, 0:0:0);
(RDB_WR_B => CAS_OUT_RDB_WR_B) = (0:0:0, 0:0:0);
(negedge RST_A *> (CAS_OUT_DOUT_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (CAS_OUT_DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (CAS_OUT_RDACCESS_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (CAS_OUT_SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (RDACCESS_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B *> (CAS_OUT_DOUT_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (CAS_OUT_DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (CAS_OUT_RDACCESS_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (CAS_OUT_SBITERR_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (RDACCESS_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A *> (CAS_OUT_DOUT_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (CAS_OUT_DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (CAS_OUT_RDACCESS_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (CAS_OUT_SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (RDACCESS_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B *> (CAS_OUT_DOUT_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (CAS_OUT_DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (CAS_OUT_RDACCESS_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (CAS_OUT_SBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (RDACCESS_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$recrem (negedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay);
$recrem (negedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay);
$recrem (negedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay);
$recrem (negedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay);
$recrem (posedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay);
$recrem (posedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay);
$recrem (posedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay);
$recrem (posedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay);
$setuphold (negedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay);
$setuphold (negedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay);
$setuphold (negedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay);
$setuphold (negedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_B_delay);
$setuphold (negedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay);
$setuphold (negedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay);
$setuphold (negedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay);
$setuphold (negedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay);
$setuphold (negedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (negedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (negedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (negedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (negedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay);
$setuphold (negedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay);
$setuphold (negedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (negedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (negedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay);
$setuphold (negedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay);
$setuphold (negedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay);
$setuphold (negedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay);
$setuphold (negedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay);
$setuphold (negedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay);
$setuphold (negedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay);
$setuphold (negedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay);
$setuphold (negedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_B_delay);
$setuphold (negedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay);
$setuphold (negedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay);
$setuphold (negedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay);
$setuphold (negedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay);
$setuphold (negedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (negedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (negedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (negedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (negedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay);
$setuphold (negedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay);
$setuphold (negedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (negedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (negedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay);
$setuphold (negedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay);
$setuphold (negedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay);
$setuphold (negedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay);
$setuphold (negedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay);
$setuphold (posedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay);
$setuphold (posedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay);
$setuphold (posedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay);
$setuphold (posedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_B_delay);
$setuphold (posedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay);
$setuphold (posedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay);
$setuphold (posedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay);
$setuphold (posedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay);
$setuphold (posedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (posedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (posedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (posedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (posedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay);
$setuphold (posedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay);
$setuphold (posedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (posedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (posedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay);
$setuphold (posedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay);
$setuphold (posedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay);
$setuphold (posedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay);
$setuphold (posedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay);
$setuphold (posedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay);
$setuphold (posedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay);
$setuphold (posedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay);
$setuphold (posedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_B_delay);
$setuphold (posedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay);
$setuphold (posedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay);
$setuphold (posedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay);
$setuphold (posedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay);
$setuphold (posedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (posedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (posedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (posedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (posedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay);
$setuphold (posedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay);
$setuphold (posedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (posedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (posedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay);
$setuphold (posedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay);
$setuphold (posedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay);
$setuphold (posedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay);
$setuphold (posedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge RST_A, 0:0:0, 0, notifier);
$width (negedge RST_B, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge RST_A, 0:0:0, 0, notifier);
$width (posedge RST_B, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule |
module pcx_buf_pm_even(/*AUTOARG*/
// Outputs
arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l,
arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l,
arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa,
arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px,
// Inputs
arbpc0_pcxdp_grant_arbbf_pa, arbpc0_pcxdp_q0_hold_arbbf_pa_l,
arbpc0_pcxdp_qsel0_arbbf_pa, arbpc0_pcxdp_qsel1_arbbf_pa_l,
arbpc0_pcxdp_shift_arbbf_px, arbpc2_pcxdp_grant_arbbf_pa,
arbpc2_pcxdp_q0_hold_arbbf_pa_l, arbpc2_pcxdp_qsel0_arbbf_pa,
arbpc2_pcxdp_qsel1_arbbf_pa_l, arbpc2_pcxdp_shift_arbbf_px
);
output arbpc0_pcxdp_grant_pa ;
output arbpc0_pcxdp_q0_hold_pa_l ;
output arbpc0_pcxdp_qsel0_pa ;
output arbpc0_pcxdp_qsel1_pa_l ;
output arbpc0_pcxdp_shift_px ;
output arbpc2_pcxdp_grant_pa ;
output arbpc2_pcxdp_q0_hold_pa_l ;
output arbpc2_pcxdp_qsel0_pa ;
output arbpc2_pcxdp_qsel1_pa_l ;
output arbpc2_pcxdp_shift_px ;
input arbpc0_pcxdp_grant_arbbf_pa;
input arbpc0_pcxdp_q0_hold_arbbf_pa_l;
input arbpc0_pcxdp_qsel0_arbbf_pa;
input arbpc0_pcxdp_qsel1_arbbf_pa_l;
input arbpc0_pcxdp_shift_arbbf_px;
input arbpc2_pcxdp_grant_arbbf_pa;
input arbpc2_pcxdp_q0_hold_arbbf_pa_l;
input arbpc2_pcxdp_qsel0_arbbf_pa;
input arbpc2_pcxdp_qsel1_arbbf_pa_l;
input arbpc2_pcxdp_shift_arbbf_px;
assign arbpc0_pcxdp_grant_pa = arbpc0_pcxdp_grant_arbbf_pa;
assign arbpc0_pcxdp_q0_hold_pa_l = arbpc0_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc0_pcxdp_qsel0_pa = arbpc0_pcxdp_qsel0_arbbf_pa;
assign arbpc0_pcxdp_qsel1_pa_l = arbpc0_pcxdp_qsel1_arbbf_pa_l;
assign arbpc0_pcxdp_shift_px = arbpc0_pcxdp_shift_arbbf_px;
assign arbpc2_pcxdp_grant_pa = arbpc2_pcxdp_grant_arbbf_pa;
assign arbpc2_pcxdp_q0_hold_pa_l = arbpc2_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc2_pcxdp_qsel0_pa = arbpc2_pcxdp_qsel0_arbbf_pa;
assign arbpc2_pcxdp_qsel1_pa_l = arbpc2_pcxdp_qsel1_arbbf_pa_l;
assign arbpc2_pcxdp_shift_px = arbpc2_pcxdp_shift_arbbf_px;
endmodule |
module sky130_fd_sc_hd__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module fifo
#(
parameter adr_width = 4,
parameter dat_width = 8
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(posedge reset, posedge wr, posedge rd)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule |
module regfile_tb;
reg clk;
wire [`N-1:0] a,b;
reg [`N-1:0] x;
reg [`K-1:0] sa, sb, d;
reg ld;
regfile #(.n(`N), .k(`K)) r1 (clk, x, ld, d, sa, sb, a, b);
initial begin
clk = 0;
end
initial begin
$monitor("time:%t\tld: %b\tsa: %d\tsb: %d\td %d\tx: %d\ta: %d\tb: %d", $time, ld, sa, sb, d, x, a, b);
end
initial begin
// Load 10 into register 2
#0 begin
$display("\nStarting test 1");
ld = 1;
x = 16'd10;
d = 3;
sa = 3;
sb = 3;
end
// Retrieve 10 from register 2
#2 begin
$display("Reading register");
ld = 0;
x = 0;
d = 3;
sa = 3;//4'b0010;
sb = 3;//4'b0010;
end
#2 begin
$display("Writing + Reading");
ld = 1;
x = 16'd15;
d = 1;
sa = 3;
sb = 3;
end
#2 begin
$display("Reading both registers");
ld = 0;
x = 0;
d = 0;
sa = 1;
sb = 3;
end
#2 begin
$display("Read again");
ld = 0;
x = 0;
d = 0;
sa = 1;
sb = 3;
end
#4 $finish;
end
//Simulate Clock
always begin
#1 clk = !clk;
end
endmodule |
module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_from_masters_1_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_from_masters_1_bid,
v_from_masters_1_rid,
v_to_slaves_0_arcache,
v_to_slaves_0_arid,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awid,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arid,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awid,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arid,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awid,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_from_masters_1_bresp,
v_from_masters_1_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_from_masters_1_arready,
v_from_masters_1_awready,
v_from_masters_1_bvalid,
v_from_masters_1_rlast,
v_from_masters_1_rvalid,
v_from_masters_1_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_r_err_beat_count_1
reg [7 : 0] fabric_v_rg_r_err_beat_count_1;
wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN;
wire fabric_v_rg_r_err_beat_count_1$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_1
reg [7 : 0] fabric_v_rg_wd_beat_count_1;
wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN;
wire fabric_v_rg_wd_beat_count_1$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ;
// ports of submodule fabric_v_f_rd_err_info_1
wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT;
wire fabric_v_f_rd_err_info_1$CLR,
fabric_v_f_rd_err_info_1$DEQ,
fabric_v_f_rd_err_info_1$EMPTY_N,
fabric_v_f_rd_err_info_1$ENQ;
// ports of submodule fabric_v_f_rd_mis_0
wire [9 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [9 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [9 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_1
reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT;
wire fabric_v_f_rd_sjs_1$CLR,
fabric_v_f_rd_sjs_1$DEQ,
fabric_v_f_rd_sjs_1$EMPTY_N,
fabric_v_f_rd_sjs_1$ENQ,
fabric_v_f_rd_sjs_1$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_1
reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT;
wire fabric_v_f_wd_tasks_1$CLR,
fabric_v_f_wd_tasks_1$DEQ,
fabric_v_f_wd_tasks_1$EMPTY_N,
fabric_v_f_wd_tasks_1$ENQ,
fabric_v_f_wd_tasks_1$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ;
// ports of submodule fabric_v_f_wr_err_info_1
wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT;
wire fabric_v_f_wr_err_info_1$CLR,
fabric_v_f_wr_err_info_1$DEQ,
fabric_v_f_wr_err_info_1$EMPTY_N,
fabric_v_f_wr_err_info_1$ENQ;
// ports of submodule fabric_v_f_wr_mis_0
wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT;
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT;
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT;
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_1
reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT;
wire fabric_v_f_wr_sjs_1$CLR,
fabric_v_f_wr_sjs_1$DEQ,
fabric_v_f_wr_sjs_1$EMPTY_N,
fabric_v_f_wr_sjs_1$ENQ,
fabric_v_f_wr_sjs_1$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN,
fabric_xactors_from_masters_1_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_addr$CLR,
fabric_xactors_from_masters_1_f_rd_addr$DEQ,
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_addr$ENQ,
fabric_xactors_from_masters_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_data$CLR,
fabric_xactors_from_masters_1_f_rd_data$DEQ,
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_data$ENQ,
fabric_xactors_from_masters_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN,
fabric_xactors_from_masters_1_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_addr$CLR,
fabric_xactors_from_masters_1_f_wr_addr$DEQ,
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_addr$ENQ,
fabric_xactors_from_masters_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN,
fabric_xactors_from_masters_1_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_data$CLR,
fabric_xactors_from_masters_1_f_wr_data$DEQ,
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_data$ENQ,
fabric_xactors_from_masters_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_resp$CLR,
fabric_xactors_from_masters_1_f_wr_resp$DEQ,
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_resp$ENQ,
fabric_xactors_from_masters_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_from_masters_1_m_arvalid,
CAN_FIRE_v_from_masters_1_m_awvalid,
CAN_FIRE_v_from_masters_1_m_bready,
CAN_FIRE_v_from_masters_1_m_rready,
CAN_FIRE_v_from_masters_1_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_from_masters_1_m_arvalid,
WILL_FIRE_v_from_masters_1_m_awvalid,
WILL_FIRE_v_from_masters_1_m_bready,
WILL_FIRE_v_from_masters_1_m_rready,
WILL_FIRE_v_from_masters_1_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1,
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2;
wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h8466;
reg [31 : 0] v__h8813;
reg [31 : 0] v__h9160;
reg [31 : 0] v__h9570;
reg [31 : 0] v__h9911;
reg [31 : 0] v__h10252;
reg [31 : 0] v__h11228;
reg [31 : 0] v__h11475;
reg [31 : 0] v__h11829;
reg [31 : 0] v__h12076;
reg [31 : 0] v__h12433;
reg [31 : 0] v__h12703;
reg [31 : 0] v__h12973;
reg [31 : 0] v__h13247;
reg [31 : 0] v__h13491;
reg [31 : 0] v__h13735;
reg [31 : 0] v__h13969;
reg [31 : 0] v__h14179;
reg [31 : 0] v__h14579;
reg [31 : 0] v__h14913;
reg [31 : 0] v__h15247;
reg [31 : 0] v__h15635;
reg [31 : 0] v__h15945;
reg [31 : 0] v__h16255;
reg [31 : 0] v__h17211;
reg [31 : 0] v__h17492;
reg [31 : 0] v__h17860;
reg [31 : 0] v__h18131;
reg [31 : 0] v__h18499;
reg [31 : 0] v__h18770;
reg [31 : 0] v__h19118;
reg [31 : 0] v__h19399;
reg [31 : 0] v__h19722;
reg [31 : 0] v__h19993;
reg [31 : 0] v__h20316;
reg [31 : 0] v__h20587;
reg [31 : 0] v__h21067;
reg [31 : 0] v__h21449;
reg [31 : 0] v__h5786;
reg [31 : 0] v__h5780;
reg [31 : 0] v__h8460;
reg [31 : 0] v__h8807;
reg [31 : 0] v__h9154;
reg [31 : 0] v__h9564;
reg [31 : 0] v__h9905;
reg [31 : 0] v__h10246;
reg [31 : 0] v__h11222;
reg [31 : 0] v__h11469;
reg [31 : 0] v__h11823;
reg [31 : 0] v__h12070;
reg [31 : 0] v__h12427;
reg [31 : 0] v__h12697;
reg [31 : 0] v__h12967;
reg [31 : 0] v__h13241;
reg [31 : 0] v__h13485;
reg [31 : 0] v__h13729;
reg [31 : 0] v__h13963;
reg [31 : 0] v__h14173;
reg [31 : 0] v__h14573;
reg [31 : 0] v__h14907;
reg [31 : 0] v__h15241;
reg [31 : 0] v__h15629;
reg [31 : 0] v__h15939;
reg [31 : 0] v__h16249;
reg [31 : 0] v__h17205;
reg [31 : 0] v__h17486;
reg [31 : 0] v__h17854;
reg [31 : 0] v__h18125;
reg [31 : 0] v__h18493;
reg [31 : 0] v__h18764;
reg [31 : 0] v__h19112;
reg [31 : 0] v__h19393;
reg [31 : 0] v__h19716;
reg [31 : 0] v__h19987;
reg [31 : 0] v__h20310;
reg [31 : 0] v__h20581;
reg [31 : 0] v__h21061;
reg [31 : 0] v__h21443;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1,
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2;
wire [7 : 0] x__h11377,
x__h11978,
x__h17375,
x__h18024,
x__h18663,
x__h21004,
x__h21386;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403,
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438,
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473,
x1_avValue_rresp__h17353,
x1_avValue_rresp__h18002,
x1_avValue_rresp__h18641;
wire _dor1fabric_v_f_rd_mis_0$EN_deq,
_dor1fabric_v_f_rd_mis_1$EN_deq,
_dor1fabric_v_f_rd_mis_2$EN_deq,
fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130,
fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159,
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387,
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422,
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457,
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522,
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540,
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146,
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// action method v_from_masters_1_m_awvalid
assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
// value method v_from_masters_1_m_awready
assign v_from_masters_1_awready =
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
// action method v_from_masters_1_m_wvalid
assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
// value method v_from_masters_1_m_wready
assign v_from_masters_1_wready =
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
// value method v_from_masters_1_m_bvalid
assign v_from_masters_1_bvalid =
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
// value method v_from_masters_1_m_bid
assign v_from_masters_1_bid =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_1_m_bresp
assign v_from_masters_1_bresp =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_1_m_bready
assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ;
// action method v_from_masters_1_m_arvalid
assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
// value method v_from_masters_1_m_arready
assign v_from_masters_1_arready =
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
// value method v_from_masters_1_m_rvalid
assign v_from_masters_1_rvalid =
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
// value method v_from_masters_1_m_rid
assign v_from_masters_1_rid =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_1_m_rdata
assign v_from_masters_1_rdata =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_1_m_rresp
assign v_from_masters_1_rresp =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_1_m_rlast
assign v_from_masters_1_rlast =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ;
// action method v_from_masters_1_m_rready
assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_err_info_1
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_1$D_IN),
.ENQ(fabric_v_f_rd_err_info_1$ENQ),
.DEQ(fabric_v_f_rd_err_info_1$DEQ),
.CLR(fabric_v_f_rd_err_info_1$CLR),
.D_OUT(fabric_v_f_rd_err_info_1$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_rd_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_1$D_IN),
.ENQ(fabric_v_f_rd_sjs_1$ENQ),
.DEQ(fabric_v_f_rd_sjs_1$DEQ),
.CLR(fabric_v_f_rd_sjs_1$CLR),
.D_OUT(fabric_v_f_rd_sjs_1$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_1
FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_1$D_IN),
.ENQ(fabric_v_f_wd_tasks_1$ENQ),
.DEQ(fabric_v_f_wd_tasks_1$DEQ),
.CLR(fabric_v_f_wd_tasks_1$CLR),
.D_OUT(fabric_v_f_wd_tasks_1$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_1$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_1
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_1$D_IN),
.ENQ(fabric_v_f_wr_err_info_1$ENQ),
.DEQ(fabric_v_f_wr_err_info_1$DEQ),
.CLR(fabric_v_f_wr_err_info_1$CLR),
.D_OUT(fabric_v_f_wr_err_info_1$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_v_f_wr_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_1$D_IN),
.ENQ(fabric_v_f_wr_sjs_1$ENQ),
.DEQ(fabric_v_f_wr_sjs_1$DEQ),
.CLR(fabric_v_f_wr_sjs_1$CLR),
.D_OUT(fabric_v_f_wr_sjs_1$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
fabric_v_f_wr_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_wr_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_1$EMPTY_N &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_rd_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_1$EMPTY_N &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ?
8'd0 :
x__h17375 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ?
8'd0 :
x__h18024 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ?
8'd0 :
x__h18663 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 ?
8'd0 :
x__h11377 ;
assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 ?
8'd0 :
x__h11978 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_1$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ;
assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_0$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_1$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_2$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ?
8'd0 :
x__h21004 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_r_err_beat_count_1
assign fabric_v_rg_r_err_beat_count_1$D_IN =
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ?
8'd0 :
x__h21386 ;
assign fabric_v_rg_r_err_beat_count_1$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// register fabric_v_rg_wd_beat_count_1
assign fabric_v_rg_wd_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ;
assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_1
assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ;
assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ;
assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_v_f_rd_mis_0$DEQ =
_dor1fabric_v_f_rd_mis_0$EN_deq &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_v_f_rd_mis_1$DEQ =
_dor1fabric_v_f_rd_mis_1$EN_deq &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_mis_2$DEQ =
_dor1fabric_v_f_rd_mis_2$EN_deq &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_1
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3:
fabric_v_f_rd_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4:
fabric_v_f_rd_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5:
fabric_v_f_rd_sjs_1$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ;
assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_1$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wd_tasks_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 ;
assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ;
assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_1
assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ;
assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ;
assign fabric_v_f_wr_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_v_f_wr_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_v_f_wr_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wr_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wr_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wr_sjs_1$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_addr
assign fabric_xactors_from_masters_1_f_rd_addr$D_IN =
{ v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion } ;
assign fabric_xactors_from_masters_1_f_rd_addr$ENQ =
v_from_masters_1_arvalid &&
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_rd_data$DEQ =
v_from_masters_1_rready &&
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_addr
assign fabric_xactors_from_masters_1_f_wr_addr$D_IN =
{ v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion } ;
assign fabric_xactors_from_masters_1_f_wr_addr$ENQ =
v_from_masters_1_awvalid &&
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_data
assign fabric_xactors_from_masters_1_f_wr_data$D_IN =
{ v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast } ;
assign fabric_xactors_from_masters_1_f_wr_data$ENQ =
v_from_masters_1_wvalid &&
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_data$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ;
assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_wr_resp$DEQ =
v_from_masters_1_bready &&
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403 =
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ?
x1_avValue_rresp__h17353 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438 =
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ?
x1_avValue_rresp__h18002 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473 =
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ?
x1_avValue_rresp__h18641 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign _dor1fabric_v_f_rd_mis_0$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign _dor1fabric_v_f_rd_mis_1$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign _dor1fabric_v_f_rd_mis_2$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159 =
fabric_v_f_wd_tasks_1$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ;
assign fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[11:4] ;
assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 =
fabric_v_rg_r_err_beat_count_1 ==
fabric_v_f_rd_err_info_1$D_OUT[11:4] ;
assign fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 =
fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign x1_avValue_rresp__h17353 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h18002 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h18641 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h11377 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
assign x__h11978 = fabric_v_rg_wd_beat_count_1 + 8'd1 ;
assign x__h17375 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h18024 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h18663 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h21004 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h21386 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
always@(fabric_v_f_wd_tasks_1$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_1$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_r_err_beat_count_1$EN)
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_1$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_1$EN)
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_r_err_beat_count_1 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_1 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8466 = $stime;
#0;
end
v__h8460 = v__h8466 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8460,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8813 = $stime;
#0;
end
v__h8807 = v__h8813 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8807,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9160 = $stime;
#0;
end
v__h9154 = v__h9160 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9154,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9570 = $stime;
#0;
end
v__h9564 = v__h9570 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9564,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9911 = $stime;
#0;
end
v__h9905 = v__h9911 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9905,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10252 = $stime;
#0;
end
v__h10246 = v__h10252 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10246,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11228 = $stime;
#0;
end
v__h11222 = v__h11228 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h11222,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8],
fabric_v_rg_wd_beat_count_0,
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h11475 = $stime;
#0;
end
v__h11469 = v__h11475 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h11469,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11829 = $stime;
#0;
end
v__h11823 = v__h11829 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h11823,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8],
fabric_v_rg_wd_beat_count_1,
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
begin
v__h12076 = $stime;
#0;
end
v__h12070 = v__h12076 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h12070,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12433 = $stime;
#0;
end
v__h12427 = v__h12433 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12427,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12703 = $stime;
#0;
end
v__h12697 = v__h12703 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12697,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12973 = $stime;
#0;
end
v__h12967 = v__h12973 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12967,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13247 = $stime;
#0;
end
v__h13241 = v__h13247 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13241,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13491 = $stime;
#0;
end
v__h13485 = v__h13491 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13485,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13735 = $stime;
#0;
end
v__h13729 = v__h13735 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13729,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13969 = $stime;
#0;
end
v__h13963 = v__h13969 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h13963,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14179 = $stime;
#0;
end
v__h14173 = v__h14179 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14173,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_1$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14579 = $stime;
#0;
end
v__h14573 = v__h14579 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h14573,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14913 = $stime;
#0;
end
v__h14907 = v__h14913 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h14907,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15247 = $stime;
#0;
end
v__h15241 = v__h15247 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15241,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15635 = $stime;
#0;
end
v__h15629 = v__h15635 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15629,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15945 = $stime;
#0;
end
v__h15939 = v__h15945 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15939,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16255 = $stime;
#0;
end
v__h16249 = v__h16255 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16249,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h17211 = $stime;
#0;
end
v__h17205 = v__h17211 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h17205,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17492 = $stime;
#0;
end
v__h17486 = v__h17492 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h17486,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h17860 = $stime;
#0;
end
v__h17854 = v__h17860 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h17854,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18131 = $stime;
#0;
end
v__h18125 = v__h18131 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18125,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h18499 = $stime;
#0;
end
v__h18493 = v__h18499 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18493,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18770 = $stime;
#0;
end
v__h18764 = v__h18770 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18764,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h19118 = $stime;
#0;
end
v__h19112 = v__h19118 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19112,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19399 = $stime;
#0;
end
v__h19393 = v__h19399 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19393,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h19722 = $stime;
#0;
end
v__h19716 = v__h19722 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19716,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19993 = $stime;
#0;
end
v__h19987 = v__h19993 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19987,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h20316 = $stime;
#0;
end
v__h20310 = v__h20316 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20310,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20587 = $stime;
#0;
end
v__h20581 = v__h20587 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20581,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21067 = $stime;
#0;
end
v__h21061 = v__h21067 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21061,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21449 = $stime;
#0;
end
v__h21443 = v__h21449 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21443,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h5786 = $stime;
#0;
end
v__h5780 = v__h5786 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h5780);
end
// synopsys translate_on
endmodule |
module sky130_fd_sc_ms__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule |
module mor1kx_branch_prediction
#(
parameter FEATURE_BRANCH_PREDICTOR = "NONE"
)
(
input clk,
input rst,
// Signals belonging to the stage where the branch is predicted.
input op_bf_i, // from decode stage, brn is bf
input op_bnf_i, // from decode stage, brn is bnf
input [9:0] immjbr_upper_i, // from decode stage, imm
output predicted_flag_o, // to decode-execute stage, flag we predict to be
// Signals belonging to the stage where the branch is resolved.
input prev_op_brcond_i, // from decode-execute stage, prev brn was cond
input prev_predicted_flag_i, // from decode-execute, prev predicted flag
input flag_i, // from execute-ctrl stage, real flag we got
input padv_decode_i, // is decode stage stalled
input execute_bf_i, // prev insn was bf
input execute_bnf_i, // prev insn was bnf
// Branch misprediction indicator
output branch_mispredict_o // to decode-execute stage, was brn mispredicted or not
);
// Compare the real flag with the previously predicted flag and signal a
// misprediction in case of a mismatch.
assign branch_mispredict_o = prev_op_brcond_i & (flag_i != prev_predicted_flag_i);
generate
if (FEATURE_BRANCH_PREDICTOR=="SAT_COUNTER") begin : branch_predictor_saturation_counter
mor1kx_branch_predictor_saturation_counter
mor1kx_branch_predictor_saturation_counter
(
// Outputs
.predicted_flag_o (predicted_flag_o),
// Inputs
.clk (clk),
.rst (rst),
.flag_i (flag_i),
.execute_op_bf_i (execute_bf_i),
.execute_op_bnf_i (execute_bnf_i),
.op_bf_i (op_bf_i),
.op_bnf_i (op_bnf_i),
.prev_op_brcond_i (prev_op_brcond_i),
.branch_mispredict_i (branch_mispredict_o));
end else if (FEATURE_BRANCH_PREDICTOR=="SIMPLE") begin : branch_predictor_simple
mor1kx_branch_predictor_simple
mor1kx_branch_predictor_simple
(
// Outputs
.predicted_flag_o (predicted_flag_o),
// Inputs
.op_bf_i (op_bf_i),
.op_bnf_i (op_bnf_i),
.immjbr_upper_i (immjbr_upper_i));
end else begin
initial begin
$display("Error: FEATURE_PREDICTOR_TYPE, %s, not valid", FEATURE_BRANCH_PREDICTOR);
$finish();
end
end
endgenerate
endmodule |
module fir_inj (x_in,clk,y,p_desc0_p_O_FD,p_desc1_p_O_FD,p_desc2_p_O_FD,p_desc3_p_O_FD,p_desc4_p_O_FD,p_desc5_p_O_FD,p_desc6_p_O_FD,p_desc7_p_O_FD,p_desc8_p_O_FD,p_desc9_p_O_FD,p_desc10_p_O_FD,p_desc11_p_O_FD,p_desc12_p_O_FD,p_desc13_p_O_FD,p_desc14_p_O_FD,p_desc15_p_O_FD,p_desc16_p_O_FD,p_desc17_p_O_FD,p_desc18_p_O_FD,p_desc19_p_O_FD,p_desc20_p_O_FD,p_desc21_p_O_FD,p_desc22_p_O_FD,p_desc23_p_O_FD,p_desc24_p_O_FD,p_desc25_p_O_FD,p_desc26_p_O_FD,p_desc27_p_O_FD,p_desc28_p_O_FD,p_desc29_p_O_FD,p_desc30_p_O_FD,p_desc31_p_O_FD,p_desc32_p_O_FD,p_x_14_pipe_0_Z_p_O_FD,p_x_14_pipe_9_Z_p_O_FD,p_x_14_pipe_10_Z_p_O_FD,p_x_14_pipe_11_Z_p_O_FD,p_x_14_pipe_12_Z_p_O_FD,p_x_14_pipe_13_Z_p_O_FD,p_x_14_pipe_14_Z_p_O_FD,p_x_14_pipe_15_Z_p_O_FD,p_x_14_pipe_16_Z_p_O_FD,p_x_14_pipe_17_Z_p_O_FD,p_x_9_pipe_1_Z_p_O_FD,p_x_9_pipe_2_Z_p_O_FD,p_x_9_pipe_3_Z_p_O_FD,p_x_9_pipe_4_Z_p_O_FD,p_x_9_pipe_5_Z_p_O_FD,p_x_9_pipe_6_Z_p_O_FD,p_x_9_pipe_7_Z_p_O_FD,p_x_9_pipe_8_Z_p_O_FD,p_x_15_pipe_0_0_15_Z_p_O_FD,p_x_15_pipe_0_0_16_Z_p_O_FD,p_x_15_pipe_0_0_17_Z_p_O_FD,p_x_15_pipe_0_0_18_Z_p_O_FD,p_x_15_pipe_0_0_19_Z_p_O_FD,p_x_15_pipe_0_0_20_Z_p_O_FD,p_x_15_pipe_0_0_21_Z_p_O_FD,p_x_15_pipe_0_0_22_Z_p_O_FD,p_x_15_pipe_0_0_23_Z_p_O_FD,p_x_15_pipe_0_0_24_Z_p_O_FD,p_x_15_pipe_0_0_25_Z_p_O_FD,p_x_15_pipe_0_0_26_Z_p_O_FD,p_x_15_pipe_0_0_27_Z_p_O_FD,p_x_15_pipe_0_0_28_Z_p_O_FD,p_x_15_pipe_0_0_29_Z_p_O_FD,p_x_16_pipe_0_0_0_Z_p_O_FD,p_x_16_pipe_0_0_1_Z_p_O_FD,p_x_16_pipe_0_0_2_Z_p_O_FD,p_x_16_pipe_0_0_3_Z_p_O_FD,p_x_16_pipe_0_0_4_Z_p_O_FD,p_x_16_pipe_0_0_5_Z_p_O_FD,p_x_16_pipe_0_0_6_Z_p_O_FD,p_x_16_pipe_0_0_7_Z_p_O_FD,p_x_16_pipe_0_0_8_Z_p_O_FD,p_x_16_pipe_0_0_9_Z_p_O_FD,p_x_16_pipe_0_0_10_Z_p_O_FD,p_x_16_pipe_0_0_11_Z_p_O_FD,p_x_16_pipe_0_0_12_Z_p_O_FD,p_x_16_pipe_0_0_13_Z_p_O_FD,p_x_16_pipe_0_0_14_Z_p_O_FD,p_desc33_p_O_FD,p_desc34_p_O_FD,p_desc35_p_O_FD,p_desc36_p_O_FD,p_desc37_p_O_FD,p_desc38_p_O_FD,p_desc39_p_O_FD,p_desc40_p_O_FD,p_desc41_p_O_FD,p_desc42_p_O_FD,p_desc43_p_O_FD,p_desc44_p_O_FD,p_desc45_p_O_FD,p_desc46_p_O_FD,p_desc47_p_O_FD,p_desc48_p_O_FD,p_desc49_p_O_FD,p_desc50_p_O_FD,p_desc51_p_O_FD,p_desc52_p_O_FD,p_desc53_p_O_FD,p_desc54_p_O_FD,p_desc55_p_O_FD,p_desc56_p_O_FD);
input [7:0] x_in ;
input clk ;
output [7:0] y ;
wire clk ;
wire [7:0] x_0 ;
wire [15:4] un1_x_1 ;
wire [15:5] un1_x_2 ;
wire [15:4] un1_x_3 ;
wire [7:0] x_4 ;
wire [15:2] un1_x_4 ;
wire [14:0] un84_sop_0_0_0_0_5 ;
wire [7:0] x_7 ;
wire [7:0] x_8 ;
wire x_9 ;
wire [7:0] x_12 ;
wire [7:0] x_13 ;
wire [9:0] un84_sop_0_0_0_0_0 ;
wire [9:0] un84_sop_0_0_0_0_1 ;
wire [15:4] un1_x_14_0_0 ;
wire [15:5] un1_x_13_0_0 ;
wire [15:4] un1_x_12_0_0 ;
wire [14:7] un1_x_11_0_0 ;
wire [14:0] un84_sop_0_0_0_10_0 ;
wire [15:8] un1_x_10_0_0 ;
wire [15:5] un1_x_9_0 ;
wire [15:4] un1_x_8_0 ;
wire [15:2] un1_x_7_0 ;
wire [15:1] un1_x_6_0 ;
wire [14:0] un84_sop_0_0_0_5_0 ;
wire [47:11] P_uc ;
wire [29:0] ACOUT ;
wire [3:0] CARRYOUT ;
wire [47:0] PCOUT ;
wire [47:11] P_uc_0 ;
wire [29:0] ACOUT_0 ;
wire [3:0] CARRYOUT_0 ;
wire [47:0] PCOUT_0 ;
wire [47:11] P_uc_1 ;
wire [29:0] ACOUT_1 ;
wire [17:0] BCOUT_1 ;
wire [3:0] CARRYOUT_1 ;
wire [47:0] PCOUT_1 ;
wire [47:12] P_uc_2 ;
wire [29:0] ACOUT_2 ;
wire [3:0] CARRYOUT_2 ;
wire [47:0] PCOUT_2 ;
wire [47:12] P_uc_3 ;
wire [29:0] ACOUT_3 ;
wire [3:0] CARRYOUT_3 ;
wire [47:0] PCOUT_3 ;
wire [47:12] P_uc_4 ;
wire [29:0] ACOUT_4 ;
wire [3:0] CARRYOUT_4 ;
wire [47:0] PCOUT_4 ;
wire [47:12] P_uc_5 ;
wire [29:0] ACOUT_5 ;
wire [3:0] CARRYOUT_5 ;
wire [47:0] PCOUT_5 ;
wire [47:12] P_uc_6 ;
wire [29:0] ACOUT_6 ;
wire [3:0] CARRYOUT_6 ;
wire [47:0] PCOUT_6 ;
wire [47:14] P_uc_7 ;
wire [29:0] ACOUT_7 ;
wire [3:0] CARRYOUT_7 ;
wire [47:0] PCOUT_7 ;
wire [47:14] P_uc_8 ;
wire [29:0] ACOUT_8 ;
wire [3:0] CARRYOUT_8 ;
wire [47:0] PCOUT_8 ;
wire [47:15] P_uc_9 ;
wire [29:0] ACOUT_9 ;
wire [17:0] BCOUT_9 ;
wire [3:0] CARRYOUT_9 ;
wire [47:0] PCOUT_9 ;
wire [7:0] x_10_0 ;
wire [7:7] x_10_1 ;
wire [7:7] x_10_2 ;
wire [7:7] x_10_3 ;
wire [7:7] x_10_4 ;
wire [7:7] x_10_5 ;
wire [7:7] x_10_6 ;
wire [7:7] x_10_7 ;
wire [7:7] x_10_8 ;
wire [7:7] x_10_9 ;
wire [7:7] x_10_10 ;
wire [7:0] x_9_0 ;
wire [7:7] x_9_1 ;
wire [7:7] x_9_2 ;
wire [7:7] x_9_3 ;
wire [7:7] x_9_4 ;
wire [7:7] x_9_5 ;
wire [7:7] x_9_6 ;
wire [7:7] x_9_7 ;
wire [7:7] x_9_8 ;
wire [7:7] x_9_9 ;
wire [7:7] x_9_10 ;
wire [7:0] x_6_0 ;
wire [7:7] x_6_1 ;
wire [7:7] x_6_2 ;
wire [7:7] x_6_3 ;
wire [7:7] x_6_4 ;
wire [7:7] x_6_5 ;
wire [7:7] x_6_6 ;
wire [7:7] x_6_7 ;
wire [7:7] x_6_8 ;
wire [7:7] x_6_9 ;
wire [7:7] x_6_10 ;
wire [7:0] x_5_0 ;
wire [7:7] x_5_1 ;
wire [7:7] x_5_2 ;
wire [7:7] x_5_3 ;
wire [7:7] x_5_4 ;
wire [7:7] x_5_5 ;
wire [7:7] x_5_6 ;
wire [7:7] x_5_7 ;
wire [7:7] x_5_8 ;
wire [7:7] x_5_9 ;
wire [7:7] x_5_10 ;
wire [7:0] x_4_0 ;
wire [7:7] x_4_1 ;
wire [7:7] x_4_2 ;
wire [7:7] x_4_3 ;
wire [7:7] x_4_4 ;
wire [7:7] x_4_5 ;
wire [7:7] x_4_6 ;
wire [7:7] x_4_7 ;
wire [7:7] x_4_8 ;
wire [7:7] x_4_9 ;
wire [7:7] x_4_10 ;
wire [7:0] x_3_0 ;
wire [7:7] x_3_1 ;
wire [7:7] x_3_2 ;
wire [7:7] x_3_3 ;
wire [7:7] x_3_4 ;
wire [7:7] x_3_5 ;
wire [7:7] x_3_6 ;
wire [7:7] x_3_7 ;
wire [7:7] x_3_8 ;
wire [7:7] x_3_9 ;
wire [7:7] x_3_10 ;
wire [7:0] x_2_0 ;
wire [7:7] x_2_1 ;
wire [7:7] x_2_2 ;
wire [7:7] x_2_3 ;
wire [7:7] x_2_4 ;
wire [7:7] x_2_5 ;
wire [7:7] x_2_6 ;
wire [7:7] x_2_7 ;
wire [7:7] x_2_8 ;
wire [7:7] x_2_9 ;
wire [7:7] x_2_10 ;
wire [7:0] x_1_0 ;
wire [7:7] x_1_1 ;
wire [7:7] x_1_2 ;
wire [7:7] x_1_3 ;
wire [7:7] x_1_4 ;
wire [7:7] x_1_5 ;
wire [7:7] x_1_6 ;
wire [7:7] x_1_7 ;
wire [7:7] x_1_8 ;
wire [7:7] x_1_9 ;
wire [7:7] x_1_10 ;
wire [7:0] x_0_0 ;
wire [7:7] x_0_1 ;
wire [7:7] x_0_2 ;
wire [7:7] x_0_3 ;
wire [7:7] x_0_4 ;
wire [7:7] x_0_5 ;
wire [7:7] x_0_6 ;
wire [7:7] x_0_7 ;
wire [7:7] x_0_8 ;
wire [7:7] x_0_9 ;
wire [7:7] x_0_10 ;
wire [14:3] un84_sop_0_0_0_1_6_8 ;
wire [14:0] un84_sop_1_7 ;
wire [14:0] un84_sop_0_0_0_0_11_7 ;
wire [14:0] un84_sop_1_4 ;
wire [10:2] un1_x_10_4 ;
wire [14:0] un84_sop_0_0_0_1_6_4 ;
wire [14:0] un84_sop_0_0_0_0_11_6 ;
wire [14:0] un84_sop_0_0_0_0_8 ;
wire [14:0] un84_sop_0_0_0_1_6_6 ;
wire [14:0] un84_sop_1_6 ;
wire [14:7] un1_x_15_0_0_0 ;
wire [14:7] un1_x_11_0_0_0 ;
wire [14:7] un1_x_16_0_0_0 ;
wire x_12_6_tmp_d_array_0 ;
wire x_12_5_tmp_d_array_0 ;
wire x_12_4_tmp_d_array_0 ;
wire x_12_3_tmp_d_array_0 ;
wire x_12_2_tmp_d_array_0 ;
wire x_12_1_tmp_d_array_0 ;
wire x_12_0_tmp_d_array_0 ;
wire x_12_tmp_d_array_0 ;
wire x_7_6_tmp_d_array_0 ;
wire x_7_5_tmp_d_array_0 ;
wire x_7_4_tmp_d_array_0 ;
wire x_7_3_tmp_d_array_0 ;
wire x_7_2_tmp_d_array_0 ;
wire x_7_1_tmp_d_array_0 ;
wire x_7_0_tmp_d_array_0 ;
wire x_7_tmp_d_array_0 ;
wire x_4_6_tmp_d_array_0 ;
wire x_4_5_tmp_d_array_0 ;
wire x_4_4_tmp_d_array_0 ;
wire x_4_3_tmp_d_array_0 ;
wire x_4_2_tmp_d_array_0 ;
wire x_4_1_tmp_d_array_0 ;
wire x_4_0_tmp_d_array_0 ;
wire x_4_tmp_d_array_0 ;
wire [4:4] un1_x_14_0_0_0 ;
wire [5:5] un1_x_9_0_0 ;
wire [4:4] un1_x_3_0 ;
wire VCC ;
wire GND ;
wire un84_sop_1_s_7 ;
wire un84_sop_1_s_8 ;
wire un84_sop_1_s_9 ;
wire un84_sop_1_s_10 ;
wire un84_sop_1_s_11 ;
wire un84_sop_1_s_12 ;
wire un84_sop_1_s_13 ;
wire un84_sop_1_s_14 ;
wire un1_x_10_s_2_sf ;
wire un1_x_10_axb_3 ;
wire CARRYCASCOUT ;
wire OVERFLOW ;
wire MULTSIGNOUT ;
wire PATTERNBDETECT ;
wire PATTERNDETECT ;
wire UNDERFLOW ;
wire CARRYCASCOUT_0 ;
wire OVERFLOW_0 ;
wire MULTSIGNOUT_0 ;
wire PATTERNBDETECT_0 ;
wire PATTERNDETECT_0 ;
wire UNDERFLOW_0 ;
wire CARRYCASCOUT_1 ;
wire OVERFLOW_1 ;
wire MULTSIGNOUT_1 ;
wire PATTERNBDETECT_1 ;
wire PATTERNDETECT_1 ;
wire UNDERFLOW_1 ;
wire CARRYCASCOUT_2 ;
wire OVERFLOW_2 ;
wire MULTSIGNOUT_2 ;
wire PATTERNBDETECT_2 ;
wire PATTERNDETECT_2 ;
wire UNDERFLOW_2 ;
wire CARRYCASCOUT_3 ;
wire OVERFLOW_3 ;
wire MULTSIGNOUT_3 ;
wire PATTERNBDETECT_3 ;
wire PATTERNDETECT_3 ;
wire UNDERFLOW_3 ;
wire CARRYCASCOUT_4 ;
wire OVERFLOW_4 ;
wire MULTSIGNOUT_4 ;
wire PATTERNBDETECT_4 ;
wire PATTERNDETECT_4 ;
wire UNDERFLOW_4 ;
wire CARRYCASCOUT_5 ;
wire OVERFLOW_5 ;
wire MULTSIGNOUT_5 ;
wire PATTERNBDETECT_5 ;
wire PATTERNDETECT_5 ;
wire UNDERFLOW_5 ;
wire CARRYCASCOUT_6 ;
wire OVERFLOW_6 ;
wire MULTSIGNOUT_6 ;
wire PATTERNBDETECT_6 ;
wire PATTERNDETECT_6 ;
wire UNDERFLOW_6 ;
wire CARRYCASCOUT_7 ;
wire OVERFLOW_7 ;
wire MULTSIGNOUT_7 ;
wire PATTERNBDETECT_7 ;
wire PATTERNDETECT_7 ;
wire UNDERFLOW_7 ;
wire CARRYCASCOUT_8 ;
wire OVERFLOW_8 ;
wire MULTSIGNOUT_8 ;
wire PATTERNBDETECT_8 ;
wire PATTERNDETECT_8 ;
wire UNDERFLOW_8 ;
wire CARRYCASCOUT_9 ;
wire OVERFLOW_9 ;
wire MULTSIGNOUT_9 ;
wire PATTERNBDETECT_9 ;
wire PATTERNDETECT_9 ;
wire UNDERFLOW_9 ;
wire un84_sop_1_6_0_axb_1_lut6_2_O5 ;
wire un84_sop_1_6_0_o5_2 ;
wire un84_sop_1_6_0_o5_3 ;
wire un84_sop_1_6_0_o5_4 ;
wire un84_sop_1_6_0_o5_5 ;
wire un84_sop_1_6_0_o5_6 ;
wire un84_sop_1_6_0_o5_7 ;
wire un84_sop_1_6_0_o5_8 ;
wire un84_sop_1_6_0_o5_9 ;
wire un84_sop_1_6_0_o5_10 ;
wire un84_sop_1_6_0_o5_11 ;
wire un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5 ;
wire un84_sop_0_0_0_1_6_8_o5_3 ;
wire un84_sop_0_0_0_1_6_8_o5_4 ;
wire un84_sop_0_0_0_1_6_8_o5_5 ;
wire un84_sop_0_0_0_1_6_8_o5_6 ;
wire un84_sop_0_0_0_1_6_8_o5_7 ;
wire un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5 ;
wire un84_sop_0_0_0_6_6_0_o5_2 ;
wire un84_sop_0_0_0_6_6_0_o5_3 ;
wire un84_sop_0_0_0_6_6_0_o5_4 ;
wire un84_sop_0_0_0_6_6_0_o5_5 ;
wire un84_sop_0_0_0_6_6_0_o5_6 ;
wire un84_sop_0_0_0_6_6_0_o5_7 ;
wire un84_sop_0_0_0_6_6_0_o5_8 ;
wire un84_sop_0_0_0_6_6_0_o5_9 ;
wire un84_sop_0_0_0_6_6_0_o5_10 ;
wire un84_sop_0_0_0_6_6_0_o5_11 ;
wire un84_sop_0_0_0_6_6_0_o5_12 ;
wire un84_sop_0_0_0_11_0_o5_2 ;
wire un84_sop_0_0_0_11_0_o5_3 ;
wire un84_sop_0_0_0_11_0_o5_4 ;
wire un84_sop_0_0_0_11_0_o5_5 ;
wire un84_sop_0_0_0_11_0_o5_6 ;
wire un84_sop_0_0_0_11_0_o5_7 ;
wire un84_sop_0_0_0_11_0_o5_8 ;
wire un84_sop_0_0_0_11_0_o5_9 ;
wire un84_sop_0_0_0_11_0_o5_10 ;
wire un84_sop_0_0_0_11_0_o5_11 ;
wire un84_sop_0_0_0_11_0_o5_12 ;
wire un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5 ;
wire un84_sop_0_0_0_11_6_0_o5_2 ;
wire un84_sop_0_0_0_11_6_0_o5_3 ;
wire un84_sop_0_0_0_11_6_0_o5_4 ;
wire un84_sop_0_0_0_11_6_0_o5_5 ;
wire un84_sop_0_0_0_11_6_0_o5_6 ;
wire un84_sop_0_0_0_11_6_0_o5_7 ;
wire un84_sop_0_0_0_11_6_0_o5_8 ;
wire un84_sop_0_0_0_11_6_0_o5_9 ;
wire un84_sop_0_0_0_11_6_0_o5_10 ;
wire un84_sop_0_0_0_11_6_0_o5_11 ;
wire un84_sop_0_0_0_11_6_0_cry_0 ;
wire un84_sop_0_0_0_11_6_0_axb_1 ;
wire un84_sop_0_0_0_11_6_0_cry_1 ;
wire un84_sop_0_0_0_11_6_0_axb_2 ;
wire un84_sop_0_0_0_11_6_0_cry_2 ;
wire un84_sop_0_0_0_11_6_0_axb_3 ;
wire un84_sop_0_0_0_11_6_0_cry_3 ;
wire un84_sop_0_0_0_11_6_0_axb_4 ;
wire un84_sop_0_0_0_11_6_0_cry_4 ;
wire un84_sop_0_0_0_11_6_0_axb_5 ;
wire un84_sop_0_0_0_11_6_0_cry_5 ;
wire un84_sop_0_0_0_11_6_0_axb_6 ;
wire un84_sop_0_0_0_11_6_0_cry_6 ;
wire un84_sop_0_0_0_11_6_0_axb_7 ;
wire un84_sop_0_0_0_11_6_0_cry_7 ;
wire un84_sop_0_0_0_11_6_0_axb_8 ;
wire un84_sop_0_0_0_11_6_0_cry_8 ;
wire un84_sop_0_0_0_11_6_0_axb_9 ;
wire un84_sop_0_0_0_11_6_0_cry_9 ;
wire un84_sop_0_0_0_11_6_0_axb_10 ;
wire un84_sop_0_0_0_11_6_0_cry_10 ;
wire un84_sop_0_0_0_11_6_0_axb_11 ;
wire un84_sop_0_0_0_11_6_0_cry_11 ;
wire un84_sop_0_0_0_11_6_0_axb_12 ;
wire un84_sop_0_0_0_11_6_0_cry_12 ;
wire un84_sop_0_0_0_11_6_0_axb_13 ;
wire un84_sop_0_0_0_11_0_axb_0 ;
wire un84_sop_0_0_0_11_0_cry_0 ;
wire un84_sop_0_0_0_11_0_axb_1 ;
wire un84_sop_0_0_0_11_0_cry_1 ;
wire un84_sop_0_0_0_11_0_cry_2_RNO ;
wire un84_sop_0_0_0_11_0_axb_2 ;
wire un84_sop_0_0_0_11_0_cry_2 ;
wire un84_sop_0_0_0_11_0_axb_3 ;
wire un84_sop_0_0_0_11_0_cry_3 ;
wire un84_sop_0_0_0_11_0_axb_4 ;
wire un84_sop_0_0_0_11_0_cry_4 ;
wire un84_sop_0_0_0_11_0_axb_5 ;
wire un84_sop_0_0_0_11_0_cry_5 ;
wire un84_sop_0_0_0_11_0_axb_6 ;
wire un84_sop_0_0_0_11_0_cry_6 ;
wire un84_sop_0_0_0_11_0_axb_7 ;
wire un84_sop_0_0_0_11_0_cry_7 ;
wire un84_sop_0_0_0_11_0_axb_8 ;
wire un84_sop_0_0_0_11_0_cry_8 ;
wire un84_sop_0_0_0_11_0_axb_9 ;
wire un84_sop_0_0_0_11_0_cry_9 ;
wire un84_sop_0_0_0_11_0_axb_10 ;
wire un84_sop_0_0_0_11_0_cry_10 ;
wire un84_sop_0_0_0_11_0_axb_11 ;
wire un84_sop_0_0_0_11_0_cry_11 ;
wire un84_sop_0_0_0_11_0_axb_12 ;
wire un84_sop_0_0_0_11_0_cry_12 ;
wire un84_sop_0_0_0_11_0_axb_13 ;
wire un84_sop_0_0_0_11_0_cry_13 ;
wire un84_sop_0_0_0_11_0_axb_14 ;
wire un84_sop_0_0_0_6_6_0_cry_0 ;
wire un84_sop_0_0_0_6_6_0_axb_1 ;
wire un84_sop_0_0_0_6_6_0_cry_1 ;
wire un84_sop_0_0_0_6_6_0_axb_2 ;
wire un84_sop_0_0_0_6_6_0_cry_2 ;
wire un84_sop_0_0_0_6_6_0_axb_3 ;
wire un84_sop_0_0_0_6_6_0_cry_3 ;
wire un84_sop_0_0_0_6_6_0_axb_4 ;
wire un84_sop_0_0_0_6_6_0_cry_4 ;
wire un84_sop_0_0_0_6_6_0_axb_5 ;
wire un84_sop_0_0_0_6_6_0_cry_5 ;
wire un84_sop_0_0_0_6_6_0_axb_6 ;
wire un84_sop_0_0_0_6_6_0_cry_6 ;
wire un84_sop_0_0_0_6_6_0_axb_7 ;
wire un84_sop_0_0_0_6_6_0_cry_7 ;
wire un84_sop_0_0_0_6_6_0_axb_8 ;
wire un84_sop_0_0_0_6_6_0_cry_8 ;
wire un84_sop_0_0_0_6_6_0_axb_9 ;
wire un84_sop_0_0_0_6_6_0_cry_9 ;
wire un84_sop_0_0_0_6_6_0_axb_10 ;
wire un84_sop_0_0_0_6_6_0_cry_10 ;
wire un84_sop_0_0_0_6_6_0_axb_11 ;
wire un84_sop_0_0_0_6_6_0_cry_11 ;
wire un84_sop_0_0_0_6_6_0_axb_12 ;
wire un84_sop_0_0_0_6_6_0_cry_12 ;
wire un84_sop_0_0_0_6_6_0_axb_13 ;
wire un84_sop_0_0_0_6_6_0_cry_13 ;
wire un84_sop_0_0_0_6_6_0_axb_14 ;
wire un84_sop_0_0_0_1_6_8_cry_0 ;
wire un84_sop_0_0_0_1_6_8_axb_1 ;
wire un84_sop_0_0_0_1_6_8_cry_1 ;
wire un84_sop_0_0_0_1_6_8_axb_2 ;
wire un84_sop_0_0_0_1_6_8_cry_2 ;
wire un84_sop_0_0_0_1_6_8_axb_3 ;
wire un84_sop_0_0_0_1_6_8_cry_3 ;
wire un84_sop_0_0_0_1_6_8_axb_4 ;
wire un84_sop_0_0_0_1_6_8_cry_4 ;
wire un84_sop_0_0_0_1_6_8_axb_5 ;
wire un84_sop_0_0_0_1_6_8_cry_5 ;
wire un84_sop_0_0_0_1_6_8_axb_6 ;
wire un84_sop_0_0_0_1_6_8_cry_6 ;
wire un84_sop_0_0_0_1_6_8_axb_7 ;
wire un84_sop_0_0_0_1_6_8_cry_7 ;
wire un84_sop_0_0_0_1_6_8_axb_8 ;
wire un84_sop_0_0_0_1_6_8_cry_8 ;
wire un84_sop_0_0_0_1_6_8_axb_9 ;
wire un84_sop_0_0_0_1_6_8_cry_9 ;
wire un84_sop_0_0_0_1_6_8_axb_10 ;
wire un84_sop_0_0_0_1_6_8_cry_10 ;
wire un84_sop_0_0_0_1_6_8_axb_11 ;
wire un84_sop_1_6_0_cry_0 ;
wire un84_sop_1_6_0_axb_1 ;
wire un84_sop_1_6_0_cry_1 ;
wire un84_sop_1_6_0_axb_2 ;
wire un84_sop_1_6_0_cry_2 ;
wire un84_sop_1_6_0_axb_3 ;
wire un84_sop_1_6_0_cry_3 ;
wire un84_sop_1_6_0_axb_4 ;
wire un84_sop_1_6_0_cry_4 ;
wire un84_sop_1_6_0_axb_5 ;
wire un84_sop_1_6_0_cry_5 ;
wire un84_sop_1_6_0_axb_6 ;
wire un84_sop_1_6_0_cry_6 ;
wire un84_sop_1_6_0_axb_7 ;
wire un84_sop_1_6_0_cry_7 ;
wire un84_sop_1_6_0_axb_8 ;
wire un84_sop_1_6_0_cry_8 ;
wire un84_sop_1_6_0_axb_9 ;
wire un84_sop_1_6_0_cry_9 ;
wire un84_sop_1_6_0_axb_10 ;
wire un84_sop_1_6_0_cry_10 ;
wire un84_sop_1_6_0_axb_11 ;
wire un84_sop_1_6_0_cry_11 ;
wire un84_sop_1_6_0_axb_12 ;
wire un84_sop_1_6_0_cry_12 ;
wire un84_sop_1_6_0_axb_13 ;
wire un1_x_10_cry_3 ;
wire un1_x_10_axb_4 ;
wire un1_x_10_cry_4 ;
wire un1_x_10_axb_5 ;
wire un1_x_10_cry_5 ;
wire un1_x_10_axb_6 ;
wire un1_x_10_cry_6 ;
wire un1_x_10_axb_7 ;
wire un1_x_10_cry_7 ;
wire un1_x_10_axb_8 ;
wire un1_x_10_cry_8 ;
wire un1_x_10_axb_9 ;
wire un1_x_10_cry_9 ;
wire un1_x_10_axb_10 ;
wire un1_x_10_cry_10 ;
wire un1_x_10_axb_11 ;
wire un84_sop_0_0_0_1_6_4_cry_0 ;
wire un84_sop_0_0_0_1_6_4_axb_1 ;
wire un84_sop_0_0_0_1_6_4_cry_1 ;
wire un84_sop_0_0_0_1_6_4_axb_2 ;
wire un84_sop_0_0_0_1_6_4_cry_2 ;
wire un84_sop_0_0_0_1_6_4_axb_3 ;
wire un84_sop_0_0_0_1_6_4_cry_3 ;
wire un84_sop_0_0_0_1_6_4_axb_4 ;
wire un84_sop_0_0_0_1_6_4_cry_4 ;
wire un84_sop_0_0_0_1_6_4_axb_5 ;
wire un84_sop_0_0_0_1_6_4_cry_5 ;
wire un84_sop_0_0_0_1_6_4_axb_6 ;
wire un84_sop_0_0_0_1_6_4_cry_6 ;
wire un84_sop_0_0_0_1_6_4_axb_7 ;
wire un84_sop_0_0_0_1_6_4_cry_7 ;
wire un84_sop_0_0_0_1_6_4_axb_8 ;
wire un84_sop_0_0_0_1_6_4_cry_8 ;
wire un84_sop_0_0_0_1_6_4_axb_9 ;
wire un84_sop_0_0_0_1_6_4_cry_9 ;
wire un84_sop_0_0_0_1_6_4_axb_10 ;
wire un84_sop_0_0_0_1_6_4_cry_10 ;
wire un84_sop_0_0_0_1_6_4_axb_11 ;
wire un84_sop_0_0_0_1_6_4_cry_11 ;
wire un84_sop_0_0_0_1_6_4_axb_12 ;
wire un84_sop_0_0_0_1_6_4_cry_12 ;
wire un84_sop_0_0_0_1_6_4_axb_13 ;
wire un84_sop_0_0_0_1_6_4_cry_13 ;
wire un84_sop_0_0_0_1_6_4_axb_14 ;
wire un84_sop_0_0_0_1_6_cry_0 ;
wire un84_sop_0_0_0_1_6_axb_1 ;
wire un84_sop_0_0_0_1_6_cry_1 ;
wire un84_sop_0_0_0_1_6_axb_2 ;
wire un84_sop_0_0_0_1_6_cry_2 ;
wire un84_sop_0_0_0_1_6_axb_3 ;
wire un84_sop_0_0_0_1_6_cry_3 ;
wire un84_sop_0_0_0_1_6_axb_4 ;
wire un84_sop_0_0_0_1_6_cry_4 ;
wire un84_sop_0_0_0_1_6_axb_5 ;
wire un84_sop_0_0_0_1_6_cry_5 ;
wire un84_sop_0_0_0_1_6_axb_6 ;
wire un84_sop_0_0_0_1_6_cry_6 ;
wire un84_sop_0_0_0_1_6_axb_7 ;
wire un84_sop_0_0_0_1_6_cry_7 ;
wire un84_sop_0_0_0_1_6_axb_8 ;
wire un84_sop_0_0_0_1_6_cry_8 ;
wire un84_sop_0_0_0_1_6_axb_9 ;
wire un84_sop_0_0_0_1_6_cry_9 ;
wire un84_sop_0_0_0_1_6_axb_10 ;
wire un84_sop_0_0_0_1_6_cry_10 ;
wire un84_sop_0_0_0_1_6_axb_11 ;
wire un84_sop_0_0_0_1_6_cry_11 ;
wire un84_sop_0_0_0_1_6_axb_12 ;
wire un84_sop_0_0_0_1_6_cry_12 ;
wire un84_sop_0_0_0_1_6_axb_13 ;
wire un84_sop_0_0_0_1_6_cry_13 ;
wire un84_sop_0_0_0_1_6_axb_14 ;
wire un1_x_0_0_c4 ;
wire un1_x_10_5_c5 ;
wire un84_sop_1_7_cry_0 ;
wire un84_sop_1_7_axb_1 ;
wire un84_sop_1_7_cry_1 ;
wire un84_sop_1_7_axb_2 ;
wire un84_sop_1_7_cry_2 ;
wire un84_sop_1_7_axb_3 ;
wire un84_sop_1_7_cry_3 ;
wire un84_sop_1_7_axb_4 ;
wire un84_sop_1_7_cry_4 ;
wire un84_sop_1_7_axb_5 ;
wire un84_sop_1_7_cry_5 ;
wire un84_sop_1_7_axb_6 ;
wire un84_sop_1_7_cry_6 ;
wire un84_sop_1_7_axb_7 ;
wire un84_sop_1_7_cry_7 ;
wire un84_sop_1_7_axb_8 ;
wire un84_sop_1_7_cry_8 ;
wire un84_sop_1_7_axb_9 ;
wire un84_sop_1_7_cry_9 ;
wire un84_sop_1_7_axb_10 ;
wire un84_sop_1_7_cry_10 ;
wire un84_sop_1_7_axb_11 ;
wire un84_sop_1_7_cry_11 ;
wire un84_sop_1_7_axb_12 ;
wire un84_sop_1_7_cry_12 ;
wire un84_sop_1_7_axb_13 ;
wire un84_sop_1_7_cry_13 ;
wire un84_sop_1_7_axb_14 ;
wire un84_sop_0_0_0_0_11_7_cry_0 ;
wire un84_sop_0_0_0_0_11_7_axb_1 ;
wire un84_sop_0_0_0_0_11_7_cry_1 ;
wire un84_sop_0_0_0_0_11_7_axb_2 ;
wire un84_sop_0_0_0_0_11_7_cry_2 ;
wire un84_sop_0_0_0_0_11_7_axb_3 ;
wire un84_sop_0_0_0_0_11_7_cry_3 ;
wire un84_sop_0_0_0_0_11_7_axb_4 ;
wire un84_sop_0_0_0_0_11_7_cry_4 ;
wire un84_sop_0_0_0_0_11_7_axb_5 ;
wire un84_sop_0_0_0_0_11_7_cry_5 ;
wire un84_sop_0_0_0_0_11_7_axb_6 ;
wire un84_sop_0_0_0_0_11_7_cry_6 ;
wire un84_sop_0_0_0_0_11_7_axb_7 ;
wire un84_sop_0_0_0_0_11_7_cry_7 ;
wire un84_sop_0_0_0_0_11_7_axb_8 ;
wire un84_sop_0_0_0_0_11_7_cry_8 ;
wire un84_sop_0_0_0_0_11_7_axb_9 ;
wire un84_sop_0_0_0_0_11_7_cry_9 ;
wire un84_sop_0_0_0_0_11_7_axb_10 ;
wire un84_sop_1_4_cry_0 ;
wire un84_sop_1_4_axb_1 ;
wire un84_sop_1_4_cry_1 ;
wire un84_sop_1_4_axb_2 ;
wire un84_sop_1_4_cry_2 ;
wire un84_sop_1_4_axb_3 ;
wire un84_sop_1_4_cry_3 ;
wire un84_sop_1_4_axb_4 ;
wire un84_sop_1_4_cry_4 ;
wire un84_sop_1_4_axb_5 ;
wire un84_sop_1_4_cry_5 ;
wire un84_sop_1_4_axb_6 ;
wire un84_sop_1_4_cry_6 ;
wire un84_sop_1_4_axb_7 ;
wire un84_sop_1_4_cry_7 ;
wire un84_sop_1_4_axb_8 ;
wire un84_sop_1_4_cry_8 ;
wire un84_sop_1_4_axb_9 ;
wire un84_sop_1_4_cry_9 ;
wire un84_sop_1_4_axb_10 ;
wire un84_sop_1_4_cry_10 ;
wire un84_sop_1_4_axb_11 ;
wire un84_sop_1_4_cry_11 ;
wire un84_sop_1_4_axb_12 ;
wire un84_sop_1_4_cry_12 ;
wire un84_sop_1_4_axb_13 ;
wire un84_sop_1_4_cry_13 ;
wire un84_sop_1_4_axb_14 ;
wire un84_sop_1_axb_0 ;
wire un84_sop_1_cry_0 ;
wire un84_sop_1_axb_1 ;
wire un84_sop_1_cry_1 ;
wire un84_sop_1_axb_2 ;
wire un84_sop_1_cry_2 ;
wire un84_sop_1_axb_3 ;
wire un84_sop_1_cry_3 ;
wire un84_sop_1_axb_4 ;
wire un84_sop_1_cry_4 ;
wire un84_sop_1_axb_5 ;
wire un84_sop_1_cry_5 ;
wire un84_sop_1_axb_6 ;
wire un84_sop_1_cry_6 ;
wire un84_sop_1_axb_7 ;
wire un84_sop_1_cry_7 ;
wire un84_sop_1_axb_8 ;
wire un84_sop_1_cry_8 ;
wire un84_sop_1_axb_9 ;
wire un84_sop_1_cry_9 ;
wire un84_sop_1_axb_10 ;
wire un84_sop_1_cry_10 ;
wire un84_sop_1_axb_11 ;
wire un84_sop_1_cry_11 ;
wire un84_sop_1_axb_12 ;
wire un84_sop_1_cry_12 ;
wire un84_sop_1_axb_13 ;
wire un84_sop_1_cry_13 ;
wire un84_sop_1_axb_14 ;
wire un1_x_10_4_cry_1 ;
wire un1_x_10_4_axb_2 ;
wire un1_x_10_4_cry_2 ;
wire un1_x_10_4_axb_3 ;
wire un1_x_10_4_cry_3 ;
wire un1_x_10_4_axb_4 ;
wire un1_x_10_4_cry_4 ;
wire un1_x_10_4_axb_5 ;
wire un1_x_10_4_cry_5 ;
wire un1_x_10_4_axb_6 ;
wire un1_x_10_4_cry_6 ;
wire un1_x_10_4_axb_7 ;
wire un1_x_10_4_cry_7 ;
wire un1_x_15_0_axb_0 ;
wire un1_x_15_0_cry_0 ;
wire un1_x_15_0_axb_1 ;
wire un1_x_15_0_cry_1 ;
wire un1_x_15_0_axb_2 ;
wire un1_x_15_0_cry_2 ;
wire un1_x_15_0_axb_3 ;
wire un1_x_15_0_cry_3 ;
wire un1_x_15_0_axb_4 ;
wire un1_x_15_0_cry_4 ;
wire un1_x_15_0_axb_5 ;
wire un1_x_15_0_cry_5 ;
wire un1_x_15_0_axb_6 ;
wire un1_x_15_0_cry_6 ;
wire un1_x_15_0_axb_7 ;
wire un1_x_15_0_cry_7 ;
wire un1_x_15_0_axb_8 ;
wire un1_x_11_0_axb_0 ;
wire un1_x_11_0_cry_0 ;
wire un1_x_11_0_axb_1 ;
wire un1_x_11_0_cry_1 ;
wire un1_x_11_0_axb_2 ;
wire un1_x_11_0_cry_2 ;
wire un1_x_11_0_axb_3 ;
wire un1_x_11_0_cry_3 ;
wire un1_x_11_0_axb_4 ;
wire un1_x_11_0_cry_4 ;
wire un1_x_11_0_axb_5 ;
wire un1_x_11_0_cry_5 ;
wire un1_x_11_0_axb_6 ;
wire un1_x_11_0_cry_6 ;
wire un1_x_11_0_axb_7 ;
wire un1_x_11_0_cry_7 ;
wire un1_x_11_0_axb_8 ;
wire un1_x_16_0_axb_0 ;
wire un1_x_16_0_cry_0 ;
wire un1_x_16_0_axb_1 ;
wire un1_x_16_0_cry_1 ;
wire un1_x_16_0_axb_2 ;
wire un1_x_16_0_cry_2 ;
wire un1_x_16_0_axb_3 ;
wire un1_x_16_0_cry_3 ;
wire un1_x_16_0_axb_4 ;
wire un1_x_16_0_cry_4 ;
wire un1_x_16_0_axb_5 ;
wire un1_x_16_0_cry_5 ;
wire un1_x_16_0_axb_6 ;
wire un1_x_16_0_cry_6 ;
wire un1_x_16_0_axb_7 ;
wire un1_x_16_0_cry_7 ;
wire un1_x_16_0_axb_8 ;
wire un84_sop_0_0_0_1_cry_0 ;
wire un84_sop_0_0_0_1_axb_1 ;
wire un84_sop_0_0_0_1_cry_1 ;
wire un84_sop_0_0_0_1_axb_2 ;
wire un84_sop_0_0_0_1_cry_2 ;
wire un84_sop_0_0_0_1_axb_3 ;
wire un84_sop_0_0_0_1_cry_3 ;
wire un84_sop_0_0_0_1_axb_4 ;
wire un84_sop_0_0_0_1_cry_4 ;
wire un84_sop_0_0_0_1_axb_5 ;
wire un84_sop_0_0_0_1_cry_5 ;
wire un84_sop_0_0_0_1_axb_6 ;
wire un84_sop_0_0_0_1_cry_6 ;
wire un84_sop_0_0_0_1_axb_7 ;
wire un84_sop_0_0_0_1_cry_7 ;
wire un84_sop_0_0_0_1_axb_8 ;
wire un84_sop_0_0_0_1_cry_8 ;
wire un84_sop_0_0_0_1_axb_9 ;
wire un1_x_10_4_cry_1_sf ;
wire un84_sop_0_0_0_0_11_7_axb_0_ci ;
wire un84_sop_0_0_0_11_0_cry_0_cy ;
wire un84_sop_0_0_0_11_6_0_cry_0_cy ;
wire un84_sop_0_0_0_6_6_0_cry_0_cy ;
wire un84_sop_1_6_0_cry_0_cy ;
wire un84_sop_0_0_0_6_0_axb_0_0 ;
wire un84_sop_0_0_0_6_0_axb_0_1 ;
wire un84_sop_1_6_0_axb_0_0 ;
wire un1_x_10_4_s_8_false ;
wire x_4_x_4_1Q_Q31 ;
wire x_4_0_x_4_1Q_Q31 ;
wire x_4_1_x_4_1Q_Q31 ;
wire x_4_2_x_4_1Q_Q31 ;
wire x_4_3_x_4_1Q_Q31 ;
wire x_4_4_x_4_1Q_Q31 ;
wire x_4_5_x_4_1Q_Q31 ;
wire x_4_6_x_4_1Q_Q31 ;
wire x_7_x_7_1Q_Q31 ;
wire x_7_0_x_7_1Q_Q31 ;
wire x_7_1_x_7_1Q_Q31 ;
wire x_7_2_x_7_1Q_Q31 ;
wire x_7_3_x_7_1Q_Q31 ;
wire x_7_4_x_7_1Q_Q31 ;
wire x_7_5_x_7_1Q_Q31 ;
wire x_7_6_x_7_1Q_Q31 ;
wire x_12_x_4_1Q_Q31 ;
wire x_12_0_x_4_1Q_Q31 ;
wire x_12_1_x_4_1Q_Q31 ;
wire x_12_2_x_4_1Q_Q31 ;
wire x_12_3_x_4_1Q_Q31 ;
wire x_12_4_x_4_1Q_Q31 ;
wire x_12_5_x_4_1Q_Q31 ;
wire x_12_6_x_7_1Q_Q31 ;
input p_desc0_p_O_FD ;
input p_desc1_p_O_FD ;
input p_desc2_p_O_FD ;
input p_desc3_p_O_FD ;
input p_desc4_p_O_FD ;
input p_desc5_p_O_FD ;
input p_desc6_p_O_FD ;
input p_desc7_p_O_FD ;
input p_desc8_p_O_FD ;
input p_desc9_p_O_FD ;
input p_desc10_p_O_FD ;
input p_desc11_p_O_FD ;
input p_desc12_p_O_FD ;
input p_desc13_p_O_FD ;
input p_desc14_p_O_FD ;
input p_desc15_p_O_FD ;
input p_desc16_p_O_FD ;
input p_desc17_p_O_FD ;
input p_desc18_p_O_FD ;
input p_desc19_p_O_FD ;
input p_desc20_p_O_FD ;
input p_desc21_p_O_FD ;
input p_desc22_p_O_FD ;
input p_desc23_p_O_FD ;
input p_desc24_p_O_FD ;
input p_desc25_p_O_FD ;
input p_desc26_p_O_FD ;
input p_desc27_p_O_FD ;
input p_desc28_p_O_FD ;
input p_desc29_p_O_FD ;
input p_desc30_p_O_FD ;
input p_desc31_p_O_FD ;
input p_desc32_p_O_FD ;
input p_x_14_pipe_0_Z_p_O_FD ;
input p_x_14_pipe_9_Z_p_O_FD ;
input p_x_14_pipe_10_Z_p_O_FD ;
input p_x_14_pipe_11_Z_p_O_FD ;
input p_x_14_pipe_12_Z_p_O_FD ;
input p_x_14_pipe_13_Z_p_O_FD ;
input p_x_14_pipe_14_Z_p_O_FD ;
input p_x_14_pipe_15_Z_p_O_FD ;
input p_x_14_pipe_16_Z_p_O_FD ;
input p_x_14_pipe_17_Z_p_O_FD ;
input p_x_9_pipe_1_Z_p_O_FD ;
input p_x_9_pipe_2_Z_p_O_FD ;
input p_x_9_pipe_3_Z_p_O_FD ;
input p_x_9_pipe_4_Z_p_O_FD ;
input p_x_9_pipe_5_Z_p_O_FD ;
input p_x_9_pipe_6_Z_p_O_FD ;
input p_x_9_pipe_7_Z_p_O_FD ;
input p_x_9_pipe_8_Z_p_O_FD ;
input p_x_15_pipe_0_0_15_Z_p_O_FD ;
input p_x_15_pipe_0_0_16_Z_p_O_FD ;
input p_x_15_pipe_0_0_17_Z_p_O_FD ;
input p_x_15_pipe_0_0_18_Z_p_O_FD ;
input p_x_15_pipe_0_0_19_Z_p_O_FD ;
input p_x_15_pipe_0_0_20_Z_p_O_FD ;
input p_x_15_pipe_0_0_21_Z_p_O_FD ;
input p_x_15_pipe_0_0_22_Z_p_O_FD ;
input p_x_15_pipe_0_0_23_Z_p_O_FD ;
input p_x_15_pipe_0_0_24_Z_p_O_FD ;
input p_x_15_pipe_0_0_25_Z_p_O_FD ;
input p_x_15_pipe_0_0_26_Z_p_O_FD ;
input p_x_15_pipe_0_0_27_Z_p_O_FD ;
input p_x_15_pipe_0_0_28_Z_p_O_FD ;
input p_x_15_pipe_0_0_29_Z_p_O_FD ;
input p_x_16_pipe_0_0_0_Z_p_O_FD ;
input p_x_16_pipe_0_0_1_Z_p_O_FD ;
input p_x_16_pipe_0_0_2_Z_p_O_FD ;
input p_x_16_pipe_0_0_3_Z_p_O_FD ;
input p_x_16_pipe_0_0_4_Z_p_O_FD ;
input p_x_16_pipe_0_0_5_Z_p_O_FD ;
input p_x_16_pipe_0_0_6_Z_p_O_FD ;
input p_x_16_pipe_0_0_7_Z_p_O_FD ;
input p_x_16_pipe_0_0_8_Z_p_O_FD ;
input p_x_16_pipe_0_0_9_Z_p_O_FD ;
input p_x_16_pipe_0_0_10_Z_p_O_FD ;
input p_x_16_pipe_0_0_11_Z_p_O_FD ;
input p_x_16_pipe_0_0_12_Z_p_O_FD ;
input p_x_16_pipe_0_0_13_Z_p_O_FD ;
input p_x_16_pipe_0_0_14_Z_p_O_FD ;
input p_desc33_p_O_FD ;
input p_desc34_p_O_FD ;
input p_desc35_p_O_FD ;
input p_desc36_p_O_FD ;
input p_desc37_p_O_FD ;
input p_desc38_p_O_FD ;
input p_desc39_p_O_FD ;
input p_desc40_p_O_FD ;
input p_desc41_p_O_FD ;
input p_desc42_p_O_FD ;
input p_desc43_p_O_FD ;
input p_desc44_p_O_FD ;
input p_desc45_p_O_FD ;
input p_desc46_p_O_FD ;
input p_desc47_p_O_FD ;
input p_desc48_p_O_FD ;
input p_desc49_p_O_FD ;
input p_desc50_p_O_FD ;
input p_desc51_p_O_FD ;
input p_desc52_p_O_FD ;
input p_desc53_p_O_FD ;
input p_desc54_p_O_FD ;
input p_desc55_p_O_FD ;
input p_desc56_p_O_FD ;
// instances
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
SRLC32E x_12_6_x_7_1Q(.Q(x_12_6_tmp_d_array_0),.Q31(x_12_6_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_9),.CLK(clk),.CE(VCC));
SRLC32E x_12_5_x_4_1Q(.Q(x_12_5_tmp_d_array_0),.Q31(x_12_5_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[1:1]),.CLK(clk),.CE(VCC));
SRLC32E x_12_4_x_4_1Q(.Q(x_12_4_tmp_d_array_0),.Q31(x_12_4_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[2:2]),.CLK(clk),.CE(VCC));
SRLC32E x_12_3_x_4_1Q(.Q(x_12_3_tmp_d_array_0),.Q31(x_12_3_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[3:3]),.CLK(clk),.CE(VCC));
SRLC32E x_12_2_x_4_1Q(.Q(x_12_2_tmp_d_array_0),.Q31(x_12_2_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[4:4]),.CLK(clk),.CE(VCC));
SRLC32E x_12_1_x_4_1Q(.Q(x_12_1_tmp_d_array_0),.Q31(x_12_1_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[5:5]),.CLK(clk),.CE(VCC));
SRLC32E x_12_0_x_4_1Q(.Q(x_12_0_tmp_d_array_0),.Q31(x_12_0_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[6:6]),.CLK(clk),.CE(VCC));
SRLC32E x_12_x_4_1Q(.Q(x_12_tmp_d_array_0),.Q31(x_12_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[7:7]),.CLK(clk),.CE(VCC));
SRLC32E x_7_6_x_7_1Q(.Q(x_7_6_tmp_d_array_0),.Q31(x_7_6_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[0:0]),.CLK(clk),.CE(VCC));
SRLC32E x_7_5_x_7_1Q(.Q(x_7_5_tmp_d_array_0),.Q31(x_7_5_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[1:1]),.CLK(clk),.CE(VCC));
SRLC32E x_7_4_x_7_1Q(.Q(x_7_4_tmp_d_array_0),.Q31(x_7_4_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[2:2]),.CLK(clk),.CE(VCC));
SRLC32E x_7_3_x_7_1Q(.Q(x_7_3_tmp_d_array_0),.Q31(x_7_3_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[3:3]),.CLK(clk),.CE(VCC));
SRLC32E x_7_2_x_7_1Q(.Q(x_7_2_tmp_d_array_0),.Q31(x_7_2_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[4:4]),.CLK(clk),.CE(VCC));
SRLC32E x_7_1_x_7_1Q(.Q(x_7_1_tmp_d_array_0),.Q31(x_7_1_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[5:5]),.CLK(clk),.CE(VCC));
SRLC32E x_7_0_x_7_1Q(.Q(x_7_0_tmp_d_array_0),.Q31(x_7_0_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[6:6]),.CLK(clk),.CE(VCC));
SRLC32E x_7_x_7_1Q(.Q(x_7_tmp_d_array_0),.Q31(x_7_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[7:7]),.CLK(clk),.CE(VCC));
SRLC32E x_4_6_x_4_1Q(.Q(x_4_6_tmp_d_array_0),.Q31(x_4_6_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[0:0]),.CLK(clk),.CE(VCC));
SRLC32E x_4_5_x_4_1Q(.Q(x_4_5_tmp_d_array_0),.Q31(x_4_5_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[1:1]),.CLK(clk),.CE(VCC));
SRLC32E x_4_4_x_4_1Q(.Q(x_4_4_tmp_d_array_0),.Q31(x_4_4_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[2:2]),.CLK(clk),.CE(VCC));
SRLC32E x_4_3_x_4_1Q(.Q(x_4_3_tmp_d_array_0),.Q31(x_4_3_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[3:3]),.CLK(clk),.CE(VCC));
SRLC32E x_4_2_x_4_1Q(.Q(x_4_2_tmp_d_array_0),.Q31(x_4_2_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[4:4]),.CLK(clk),.CE(VCC));
SRLC32E x_4_1_x_4_1Q(.Q(x_4_1_tmp_d_array_0),.Q31(x_4_1_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[5:5]),.CLK(clk),.CE(VCC));
SRLC32E x_4_0_x_4_1Q(.Q(x_4_0_tmp_d_array_0),.Q31(x_4_0_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[6:6]),.CLK(clk),.CE(VCC));
SRLC32E x_4_x_4_1Q(.Q(x_4_tmp_d_array_0),.Q31(x_4_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[7:7]),.CLK(clk),.CE(VCC));
LUT1 un1_x_10_4_s_8_false_cZ(.I0(GND),.O(un1_x_10_4_s_8_false));
defparam un1_x_10_4_s_8_false_cZ.INIT=2'h0;
LUT3 un84_sop_1_6_0_s_0_lut(.I0(un1_x_1[4:4]),.I1(un1_x_2[5:5]),.I2(un1_x_3[4:4]),.O(un84_sop_1_6[0:0]));
defparam un84_sop_1_6_0_s_0_lut.INIT=8'h96;
LUT3 un84_sop_0_0_0_11_6_0_s_0_lut(.I0(un1_x_12_0_0[4:4]),.I1(un1_x_13_0_0[5:5]),.I2(un1_x_14_0_0[4:4]),.O(un84_sop_0_0_0_0_11_6[0:0]));
defparam un84_sop_0_0_0_11_6_0_s_0_lut.INIT=8'h96;
LUT3 un84_sop_0_0_0_6_6_0_s_0_lut(.I0(un1_x_7_0[2:2]),.I1(un1_x_8_0[4:4]),.I2(un1_x_9_0[5:5]),.O(un84_sop_0_0_0_1_6_6[0:0]));
defparam un84_sop_0_0_0_6_6_0_s_0_lut.INIT=8'h96;
LUT2 un84_sop_0_0_0_6_0_axb_0_0_cZ(.I0(un1_x_12_0_0[4:4]),.I1(un1_x_13_0_0[5:5]),.O(un84_sop_0_0_0_6_0_axb_0_0));
defparam un84_sop_0_0_0_6_0_axb_0_0_cZ.INIT=4'h6;
LUT3 un84_sop_0_0_0_11_6_0_axb_12_cZ(.I0(un1_x_12_0_0[15:15]),.I1(un1_x_13_0_0[15:15]),.I2(un1_x_14_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_12));
defparam un84_sop_0_0_0_11_6_0_axb_12_cZ.INIT=8'h7E;
LUT2 un84_sop_0_0_0_6_0_axb_0_1_cZ(.I0(un1_x_7_0[2:2]),.I1(un1_x_8_0[4:4]),.O(un84_sop_0_0_0_6_0_axb_0_1));
defparam un84_sop_0_0_0_6_0_axb_0_1_cZ.INIT=4'h6;
LUT4 un84_sop_0_0_0_6_6_0_axb_12_cZ(.I0(un1_x_7_0[13:13]),.I1(un1_x_7_0[14:14]),.I2(un1_x_8_0[15:15]),.I3(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_12));
defparam un84_sop_0_0_0_6_6_0_axb_12_cZ.INIT=16'h399C;
LUT4 un84_sop_0_0_0_6_6_0_axb_13_cZ(.I0(un1_x_7_0[14:14]),.I1(un1_x_7_0[15:15]),.I2(un1_x_8_0[15:15]),.I3(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_13));
defparam un84_sop_0_0_0_6_6_0_axb_13_cZ.INIT=16'h399C;
LUT2 un84_sop_0_0_0_1_6_8_axb_0(.I0(un84_sop_0_0_0_10_0[3:3]),.I1(x_4[0:0]),.O(un84_sop_0_0_0_1_6_8[3:3]));
defparam un84_sop_0_0_0_1_6_8_axb_0.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_8_axb_1_cZ(.I0(un84_sop_0_0_0_10_0[4:4]),.I1(x_4[1:1]),.O(un84_sop_0_0_0_1_6_8_axb_1));
defparam un84_sop_0_0_0_1_6_8_axb_1_cZ.INIT=4'h6;
LUT4 un84_sop_0_0_0_1_6_8_axb_9_cZ(.I0(un84_sop_0_0_0_10_0[11:11]),.I1(un84_sop_0_0_0_10_0[12:12]),.I2(x_4[6:6]),.I3(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_9));
defparam un84_sop_0_0_0_1_6_8_axb_9_cZ.INIT=16'h366C;
LUT2 un84_sop_0_0_0_1_6_8_axb_10_cZ(.I0(un84_sop_0_0_0_10_0[13:13]),.I1(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_10));
defparam un84_sop_0_0_0_1_6_8_axb_10_cZ.INIT=4'h6;
LUT2 un84_sop_1_6_0_axb_0_0_cZ(.I0(un1_x_1[4:4]),.I1(un1_x_2[5:5]),.O(un84_sop_1_6_0_axb_0_0));
defparam un84_sop_1_6_0_axb_0_0_cZ.INIT=4'h6;
LUT3 un84_sop_1_6_0_axb_12_cZ(.I0(un1_x_1[15:15]),.I1(un1_x_2[15:15]),.I2(un1_x_3[15:15]),.O(un84_sop_1_6_0_axb_12));
defparam un84_sop_1_6_0_axb_12_cZ.INIT=8'h7E;
LUT3 un1_x_10_axb_4_cZ(.I0(un1_x_10_4[4:4]),.I1(x_8[0:0]),.I2(x_8[1:1]),.O(un1_x_10_axb_4));
defparam un1_x_10_axb_4_cZ.INIT=8'h96;
LUT4 un1_x_10_axb_5_cZ(.I0(un1_x_10_4[5:5]),.I1(x_8[0:0]),.I2(x_8[1:1]),.I3(x_8[2:2]),.O(un1_x_10_axb_5));
defparam un1_x_10_axb_5_cZ.INIT=16'hA956;
LUT3 un1_x_10_axb_8_cZ(.I0(un1_x_10_4[8:8]),.I1(un1_x_10_5_c5),.I2(x_8[5:5]),.O(un1_x_10_axb_8));
defparam un1_x_10_axb_8_cZ.INIT=8'h69;
LUT4 un1_x_10_axb_9_cZ(.I0(un1_x_10_5_c5),.I1(x_8[5:5]),.I2(x_8[6:6]),.I3(x_8[7:7]),.O(un1_x_10_axb_9));
defparam un1_x_10_axb_9_cZ.INIT=16'hD22D;
LUT3 un1_x_10_axb_10_cZ(.I0(un1_x_10_5_c5),.I1(x_8[5:5]),.I2(x_8[6:6]),.O(un1_x_10_axb_10));
defparam un1_x_10_axb_10_cZ.INIT=8'hFD;
LUT2 un84_sop_0_0_0_1_6_4_axb_0(.I0(un1_x_6_0[1:1]),.I1(un84_sop_0_0_0_10_0[0:0]),.O(un84_sop_0_0_0_1_6_4[0:0]));
defparam un84_sop_0_0_0_1_6_4_axb_0.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_1_cZ(.I0(un1_x_6_0[2:2]),.I1(un84_sop_0_0_0_10_0[1:1]),.O(un84_sop_0_0_0_1_6_4_axb_1));
defparam un84_sop_0_0_0_1_6_4_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_2_cZ(.I0(un1_x_6_0[3:3]),.I1(un84_sop_0_0_0_10_0[2:2]),.O(un84_sop_0_0_0_1_6_4_axb_2));
defparam un84_sop_0_0_0_1_6_4_axb_2_cZ.INIT=4'h6;
LUT3 un84_sop_0_0_0_1_6_4_axb_3_cZ(.I0(un1_x_6_0[4:4]),.I1(un84_sop_0_0_0_10_0[3:3]),.I2(x_4[0:0]),.O(un84_sop_0_0_0_1_6_4_axb_3));
defparam un84_sop_0_0_0_1_6_4_axb_3_cZ.INIT=8'h96;
LUT2 un84_sop_0_0_0_1_6_4_axb_4_cZ(.I0(un1_x_6_0[5:5]),.I1(un84_sop_0_0_0_1_6_8[4:4]),.O(un84_sop_0_0_0_1_6_4_axb_4));
defparam un84_sop_0_0_0_1_6_4_axb_4_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_5_cZ(.I0(un1_x_6_0[6:6]),.I1(un84_sop_0_0_0_1_6_8[5:5]),.O(un84_sop_0_0_0_1_6_4_axb_5));
defparam un84_sop_0_0_0_1_6_4_axb_5_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_6_cZ(.I0(un1_x_6_0[7:7]),.I1(un84_sop_0_0_0_1_6_8[6:6]),.O(un84_sop_0_0_0_1_6_4_axb_6));
defparam un84_sop_0_0_0_1_6_4_axb_6_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_7_cZ(.I0(un1_x_6_0[8:8]),.I1(un84_sop_0_0_0_1_6_8[7:7]),.O(un84_sop_0_0_0_1_6_4_axb_7));
defparam un84_sop_0_0_0_1_6_4_axb_7_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_8_cZ(.I0(un1_x_6_0[9:9]),.I1(un84_sop_0_0_0_1_6_8[8:8]),.O(un84_sop_0_0_0_1_6_4_axb_8));
defparam un84_sop_0_0_0_1_6_4_axb_8_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_9_cZ(.I0(un1_x_6_0[10:10]),.I1(un84_sop_0_0_0_1_6_8[9:9]),.O(un84_sop_0_0_0_1_6_4_axb_9));
defparam un84_sop_0_0_0_1_6_4_axb_9_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_10_cZ(.I0(un1_x_6_0[11:11]),.I1(un84_sop_0_0_0_1_6_8[10:10]),.O(un84_sop_0_0_0_1_6_4_axb_10));
defparam un84_sop_0_0_0_1_6_4_axb_10_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_11_cZ(.I0(un1_x_6_0[12:12]),.I1(un84_sop_0_0_0_1_6_8[11:11]),.O(un84_sop_0_0_0_1_6_4_axb_11));
defparam un84_sop_0_0_0_1_6_4_axb_11_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_12_cZ(.I0(un1_x_6_0[13:13]),.I1(un84_sop_0_0_0_1_6_8[12:12]),.O(un84_sop_0_0_0_1_6_4_axb_12));
defparam un84_sop_0_0_0_1_6_4_axb_12_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_13_cZ(.I0(un1_x_6_0[14:14]),.I1(un84_sop_0_0_0_1_6_8[13:13]),.O(un84_sop_0_0_0_1_6_4_axb_13));
defparam un84_sop_0_0_0_1_6_4_axb_13_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_1_cZ(.I0(un1_x_4[3:3]),.I1(un84_sop_0_0_0_0_5[1:1]),.O(un84_sop_1_7_axb_1));
defparam un84_sop_1_7_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_2_cZ(.I0(un1_x_4[4:4]),.I1(un84_sop_0_0_0_0_5[2:2]),.O(un84_sop_1_7_axb_2));
defparam un84_sop_1_7_axb_2_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_3_cZ(.I0(un1_x_4[5:5]),.I1(un84_sop_0_0_0_0_5[3:3]),.O(un84_sop_1_7_axb_3));
defparam un84_sop_1_7_axb_3_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_4_cZ(.I0(un1_x_4[6:6]),.I1(un84_sop_0_0_0_0_5[4:4]),.O(un84_sop_1_7_axb_4));
defparam un84_sop_1_7_axb_4_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_5_cZ(.I0(un1_x_4[7:7]),.I1(un84_sop_0_0_0_0_5[5:5]),.O(un84_sop_1_7_axb_5));
defparam un84_sop_1_7_axb_5_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_6_cZ(.I0(un1_x_4[8:8]),.I1(un84_sop_0_0_0_0_5[6:6]),.O(un84_sop_1_7_axb_6));
defparam un84_sop_1_7_axb_6_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_7_cZ(.I0(un1_x_4[9:9]),.I1(un84_sop_0_0_0_0_5[7:7]),.O(un84_sop_1_7_axb_7));
defparam un84_sop_1_7_axb_7_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_8_cZ(.I0(un1_x_4[10:10]),.I1(un84_sop_0_0_0_0_5[8:8]),.O(un84_sop_1_7_axb_8));
defparam un84_sop_1_7_axb_8_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_9_cZ(.I0(un1_x_4[11:11]),.I1(un84_sop_0_0_0_0_5[9:9]),.O(un84_sop_1_7_axb_9));
defparam un84_sop_1_7_axb_9_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_10_cZ(.I0(un1_x_4[12:12]),.I1(un84_sop_0_0_0_0_5[10:10]),.O(un84_sop_1_7_axb_10));
defparam un84_sop_1_7_axb_10_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_11_cZ(.I0(un1_x_4[13:13]),.I1(un84_sop_0_0_0_0_5[11:11]),.O(un84_sop_1_7_axb_11));
defparam un84_sop_1_7_axb_11_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_12_cZ(.I0(un1_x_4[14:14]),.I1(un84_sop_0_0_0_0_5[12:12]),.O(un84_sop_1_7_axb_12));
defparam un84_sop_1_7_axb_12_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_13_cZ(.I0(un1_x_4[15:15]),.I1(un84_sop_0_0_0_0_5[13:13]),.O(un84_sop_1_7_axb_13));
defparam un84_sop_1_7_axb_13_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_0(.I0(un84_sop_0_0_0_0_0[0:0]),.I1(x_9),.O(un84_sop_0_0_0_0_11_7[0:0]));
defparam un84_sop_0_0_0_0_11_7_axb_0.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_1_cZ(.I0(un1_x_11_0_0[7:7]),.I1(un84_sop_0_0_0_0_0[1:1]),.O(un84_sop_0_0_0_0_11_7_axb_1));
defparam un84_sop_0_0_0_0_11_7_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_2_cZ(.I0(un1_x_11_0_0[8:8]),.I1(un84_sop_0_0_0_0_0[2:2]),.O(un84_sop_0_0_0_0_11_7_axb_2));
defparam un84_sop_0_0_0_0_11_7_axb_2_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_3_cZ(.I0(un1_x_11_0_0[9:9]),.I1(un84_sop_0_0_0_0_0[3:3]),.O(un84_sop_0_0_0_0_11_7_axb_3));
defparam un84_sop_0_0_0_0_11_7_axb_3_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_4_cZ(.I0(un1_x_11_0_0[10:10]),.I1(un84_sop_0_0_0_0_0[4:4]),.O(un84_sop_0_0_0_0_11_7_axb_4));
defparam un84_sop_0_0_0_0_11_7_axb_4_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_5_cZ(.I0(un1_x_11_0_0[11:11]),.I1(un84_sop_0_0_0_0_0[5:5]),.O(un84_sop_0_0_0_0_11_7_axb_5));
defparam un84_sop_0_0_0_0_11_7_axb_5_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_6_cZ(.I0(un1_x_11_0_0[12:12]),.I1(un84_sop_0_0_0_0_0[6:6]),.O(un84_sop_0_0_0_0_11_7_axb_6));
defparam un84_sop_0_0_0_0_11_7_axb_6_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_7_cZ(.I0(un1_x_11_0_0[13:13]),.I1(un84_sop_0_0_0_0_0[7:7]),.O(un84_sop_0_0_0_0_11_7_axb_7));
defparam un84_sop_0_0_0_0_11_7_axb_7_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_8_cZ(.I0(un1_x_11_0_0[14:14]),.I1(un84_sop_0_0_0_0_0[8:8]),.O(un84_sop_0_0_0_0_11_7_axb_8));
defparam un84_sop_0_0_0_0_11_7_axb_8_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_9_cZ(.I0(un1_x_11_0_0[14:14]),.I1(un84_sop_0_0_0_0_0[9:9]),.O(un84_sop_0_0_0_0_11_7_axb_9));
defparam un84_sop_0_0_0_0_11_7_axb_9_cZ.INIT=4'h6;
LUT3 un84_sop_1_4_cry_0_RNO(.I0(un1_x_4[2:2]),.I1(un84_sop_0_0_0_0_5[0:0]),.I2(x_0[0:0]),.O(un84_sop_1_4[0:0]));
defparam un84_sop_1_4_cry_0_RNO.INIT=8'h96;
LUT3 un84_sop_1_4_axb_1_cZ(.I0(un84_sop_1_7[1:1]),.I1(x_0[0:0]),.I2(x_0[1:1]),.O(un84_sop_1_4_axb_1));
defparam un84_sop_1_4_axb_1_cZ.INIT=8'h96;
LUT4 un84_sop_1_4_axb_2_cZ(.I0(un84_sop_1_7[2:2]),.I1(x_0[0:0]),.I2(x_0[1:1]),.I3(x_0[2:2]),.O(un84_sop_1_4_axb_2));
defparam un84_sop_1_4_axb_2_cZ.INIT=16'hA956;
LUT4 un84_sop_1_4_axb_5_cZ(.I0(un1_x_0_0_c4),.I1(un84_sop_1_7[5:5]),.I2(x_0[4:4]),.I3(x_0[5:5]),.O(un84_sop_1_4_axb_5));
defparam un84_sop_1_4_axb_5_cZ.INIT=16'hC639;
LUT4 un84_sop_1_axb_0_cZ(.I0(un1_x_4[2:2]),.I1(un84_sop_0_0_0_0_5[0:0]),.I2(un84_sop_1_6[0:0]),.I3(x_0[0:0]),.O(un84_sop_1_axb_0));
defparam un84_sop_1_axb_0_cZ.INIT=16'h6996;
LUT2 un84_sop_1_axb_1_cZ(.I0(un84_sop_1_4[1:1]),.I1(un84_sop_1_6[1:1]),.O(un84_sop_1_axb_1));
defparam un84_sop_1_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_2_cZ(.I0(un84_sop_1_4[2:2]),.I1(un84_sop_1_6[2:2]),.O(un84_sop_1_axb_2));
defparam un84_sop_1_axb_2_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_3_cZ(.I0(un84_sop_1_4[3:3]),.I1(un84_sop_1_6[3:3]),.O(un84_sop_1_axb_3));
defparam un84_sop_1_axb_3_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_4_cZ(.I0(un84_sop_1_4[4:4]),.I1(un84_sop_1_6[4:4]),.O(un84_sop_1_axb_4));
defparam un84_sop_1_axb_4_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_5_cZ(.I0(un84_sop_1_4[5:5]),.I1(un84_sop_1_6[5:5]),.O(un84_sop_1_axb_5));
defparam un84_sop_1_axb_5_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_6_cZ(.I0(un84_sop_1_4[6:6]),.I1(un84_sop_1_6[6:6]),.O(un84_sop_1_axb_6));
defparam un84_sop_1_axb_6_cZ.INIT=4'h6;
LUT2 un1_x_10_4_cry_1_RNO(.I0(x_8[0:0]),.I1(x_8[1:1]),.O(un1_x_10_4_cry_1_sf));
defparam un1_x_10_4_cry_1_RNO.INIT=4'h6;
LUT2 un1_x_10_4_axb_2_cZ(.I0(x_8[1:1]),.I1(x_8[2:2]),.O(un1_x_10_4_axb_2));
defparam un1_x_10_4_axb_2_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_3_cZ(.I0(x_8[2:2]),.I1(x_8[3:3]),.O(un1_x_10_4_axb_3));
defparam un1_x_10_4_axb_3_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_4_cZ(.I0(x_8[3:3]),.I1(x_8[4:4]),.O(un1_x_10_4_axb_4));
defparam un1_x_10_4_axb_4_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_5_cZ(.I0(x_8[4:4]),.I1(x_8[5:5]),.O(un1_x_10_4_axb_5));
defparam un1_x_10_4_axb_5_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_6_cZ(.I0(x_8[5:5]),.I1(x_8[6:6]),.O(un1_x_10_4_axb_6));
defparam un1_x_10_4_axb_6_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_7_cZ(.I0(x_8[6:6]),.I1(x_8[7:7]),.O(un1_x_10_4_axb_7));
defparam un1_x_10_4_axb_7_cZ.INIT=4'h6;
LUT1 un1_x_15_0_axb_0_cZ(.I0(x_12[0:0]),.O(un1_x_15_0_axb_0));
defparam un1_x_15_0_axb_0_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_1_cZ(.I0(x_12[1:1]),.O(un1_x_15_0_axb_1));
defparam un1_x_15_0_axb_1_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_2_cZ(.I0(x_12[2:2]),.O(un1_x_15_0_axb_2));
defparam un1_x_15_0_axb_2_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_3_cZ(.I0(x_12[3:3]),.O(un1_x_15_0_axb_3));
defparam un1_x_15_0_axb_3_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_4_cZ(.I0(x_12[4:4]),.O(un1_x_15_0_axb_4));
defparam un1_x_15_0_axb_4_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_5_cZ(.I0(x_12[5:5]),.O(un1_x_15_0_axb_5));
defparam un1_x_15_0_axb_5_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_6_cZ(.I0(x_12[6:6]),.O(un1_x_15_0_axb_6));
defparam un1_x_15_0_axb_6_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_7_cZ(.I0(x_12[7:7]),.O(un1_x_15_0_axb_7));
defparam un1_x_15_0_axb_7_cZ.INIT=2'h1;
LUT1 un1_x_11_0_axb_0_cZ(.I0(x_8[0:0]),.O(un1_x_11_0_axb_0));
defparam un1_x_11_0_axb_0_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_0_cZ(.I0(x_13[0:0]),.O(un1_x_16_0_axb_0));
defparam un1_x_16_0_axb_0_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_1_cZ(.I0(x_13[1:1]),.O(un1_x_16_0_axb_1));
defparam un1_x_16_0_axb_1_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_2_cZ(.I0(x_13[2:2]),.O(un1_x_16_0_axb_2));
defparam un1_x_16_0_axb_2_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_3_cZ(.I0(x_13[3:3]),.O(un1_x_16_0_axb_3));
defparam un1_x_16_0_axb_3_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_4_cZ(.I0(x_13[4:4]),.O(un1_x_16_0_axb_4));
defparam un1_x_16_0_axb_4_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_5_cZ(.I0(x_13[5:5]),.O(un1_x_16_0_axb_5));
defparam un1_x_16_0_axb_5_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_6_cZ(.I0(x_13[6:6]),.O(un1_x_16_0_axb_6));
defparam un1_x_16_0_axb_6_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_7_cZ(.I0(x_13[7:7]),.O(un1_x_16_0_axb_7));
defparam un1_x_16_0_axb_7_cZ.INIT=2'h1;
LUT2 un84_sop_0_0_0_0_11_7_axb_0_ci_cZ(.I0(un84_sop_0_0_0_0_0[0:0]),.I1(x_9),.O(un84_sop_0_0_0_0_11_7_axb_0_ci));
defparam un84_sop_0_0_0_0_11_7_axb_0_ci_cZ.INIT=4'h6;
LUT1 un84_sop_0_0_0_11_6_0_cry_0_thru(.I0(un1_x_14_0_0[4:4]),.O(un1_x_14_0_0_0[4:4]));
defparam un84_sop_0_0_0_11_6_0_cry_0_thru.INIT=2'h2;
LUT1 un84_sop_0_0_0_6_6_0_cry_0_thru(.I0(un1_x_9_0[5:5]),.O(un1_x_9_0_0[5:5]));
defparam un84_sop_0_0_0_6_6_0_cry_0_thru.INIT=2'h2;
LUT1 un84_sop_1_6_0_cry_0_thru(.I0(un1_x_3[4:4]),.O(un1_x_3_0[4:4]));
defparam un84_sop_1_6_0_cry_0_thru.INIT=2'h2;
p_O_FD desc0(.Q(x_0[0:0]),.D(x_in[0:0]),.C(clk),.E(p_desc0_p_O_FD));
p_O_FD desc1(.Q(x_0[1:1]),.D(x_in[1:1]),.C(clk),.E(p_desc1_p_O_FD));
p_O_FD desc2(.Q(x_0[2:2]),.D(x_in[2:2]),.C(clk),.E(p_desc2_p_O_FD));
p_O_FD desc3(.Q(x_0[3:3]),.D(x_in[3:3]),.C(clk),.E(p_desc3_p_O_FD));
p_O_FD desc4(.Q(x_0[4:4]),.D(x_in[4:4]),.C(clk),.E(p_desc4_p_O_FD));
p_O_FD desc5(.Q(x_0[5:5]),.D(x_in[5:5]),.C(clk),.E(p_desc5_p_O_FD));
p_O_FD desc6(.Q(x_0[6:6]),.D(x_in[6:6]),.C(clk),.E(p_desc6_p_O_FD));
p_O_FD desc7(.Q(x_0[7:7]),.D(x_in[7:7]),.C(clk),.E(p_desc7_p_O_FD));
p_O_FD desc8(.Q(y[7:7]),.D(un84_sop_1_s_14),.C(clk),.E(p_desc8_p_O_FD));
p_O_FD desc9(.Q(y[0:0]),.D(un84_sop_1_s_7),.C(clk),.E(p_desc9_p_O_FD));
p_O_FD desc10(.Q(y[1:1]),.D(un84_sop_1_s_8),.C(clk),.E(p_desc10_p_O_FD));
p_O_FD desc11(.Q(y[2:2]),.D(un84_sop_1_s_9),.C(clk),.E(p_desc11_p_O_FD));
p_O_FD desc12(.Q(y[3:3]),.D(un84_sop_1_s_10),.C(clk),.E(p_desc12_p_O_FD));
p_O_FD desc13(.Q(y[4:4]),.D(un84_sop_1_s_11),.C(clk),.E(p_desc13_p_O_FD));
p_O_FD desc14(.Q(y[5:5]),.D(un84_sop_1_s_12),.C(clk),.E(p_desc14_p_O_FD));
p_O_FD desc15(.Q(y[6:6]),.D(un84_sop_1_s_13),.C(clk),.E(p_desc15_p_O_FD));
p_O_FD desc16(.Q(x_8[7:7]),.D(x_7[7:7]),.C(clk),.E(p_desc16_p_O_FD));
p_O_FD desc17(.Q(x_8[6:6]),.D(x_7[6:6]),.C(clk),.E(p_desc17_p_O_FD));
p_O_FD desc18(.Q(x_8[5:5]),.D(x_7[5:5]),.C(clk),.E(p_desc18_p_O_FD));
p_O_FD desc19(.Q(x_8[4:4]),.D(x_7[4:4]),.C(clk),.E(p_desc19_p_O_FD));
p_O_FD desc20(.Q(x_8[3:3]),.D(x_7[3:3]),.C(clk),.E(p_desc20_p_O_FD));
p_O_FD desc21(.Q(x_8[2:2]),.D(x_7[2:2]),.C(clk),.E(p_desc21_p_O_FD));
p_O_FD desc22(.Q(x_8[1:1]),.D(x_7[1:1]),.C(clk),.E(p_desc22_p_O_FD));
p_O_FD desc23(.Q(x_8[0:0]),.D(x_7[0:0]),.C(clk),.E(p_desc23_p_O_FD));
p_O_FD desc24(.Q(x_9),.D(x_8[0:0]),.C(clk),.E(p_desc24_p_O_FD));
p_O_FD desc25(.Q(x_13[7:7]),.D(x_12[7:7]),.C(clk),.E(p_desc25_p_O_FD));
p_O_FD desc26(.Q(x_13[6:6]),.D(x_12[6:6]),.C(clk),.E(p_desc26_p_O_FD));
p_O_FD desc27(.Q(x_13[5:5]),.D(x_12[5:5]),.C(clk),.E(p_desc27_p_O_FD));
p_O_FD desc28(.Q(x_13[4:4]),.D(x_12[4:4]),.C(clk),.E(p_desc28_p_O_FD));
p_O_FD desc29(.Q(x_13[3:3]),.D(x_12[3:3]),.C(clk),.E(p_desc29_p_O_FD));
p_O_FD desc30(.Q(x_13[2:2]),.D(x_12[2:2]),.C(clk),.E(p_desc30_p_O_FD));
p_O_FD desc31(.Q(x_13[1:1]),.D(x_12[1:1]),.C(clk),.E(p_desc31_p_O_FD));
p_O_FD desc32(.Q(x_13[0:0]),.D(x_12[0:0]),.C(clk),.E(p_desc32_p_O_FD));
p_O_FD x_14_pipe_0_Z(.Q(un84_sop_0_0_0_0_0[0:0]),.D(un84_sop_0_0_0_0_1[0:0]),.C(clk),.E(p_x_14_pipe_0_Z_p_O_FD));
p_O_FD x_14_pipe_9_Z(.Q(un84_sop_0_0_0_0_0[1:1]),.D(un84_sop_0_0_0_0_1[1:1]),.C(clk),.E(p_x_14_pipe_9_Z_p_O_FD));
p_O_FD x_14_pipe_10_Z(.Q(un84_sop_0_0_0_0_0[2:2]),.D(un84_sop_0_0_0_0_1[2:2]),.C(clk),.E(p_x_14_pipe_10_Z_p_O_FD));
p_O_FD x_14_pipe_11_Z(.Q(un84_sop_0_0_0_0_0[3:3]),.D(un84_sop_0_0_0_0_1[3:3]),.C(clk),.E(p_x_14_pipe_11_Z_p_O_FD));
p_O_FD x_14_pipe_12_Z(.Q(un84_sop_0_0_0_0_0[4:4]),.D(un84_sop_0_0_0_0_1[4:4]),.C(clk),.E(p_x_14_pipe_12_Z_p_O_FD));
p_O_FD x_14_pipe_13_Z(.Q(un84_sop_0_0_0_0_0[5:5]),.D(un84_sop_0_0_0_0_1[5:5]),.C(clk),.E(p_x_14_pipe_13_Z_p_O_FD));
p_O_FD x_14_pipe_14_Z(.Q(un84_sop_0_0_0_0_0[6:6]),.D(un84_sop_0_0_0_0_1[6:6]),.C(clk),.E(p_x_14_pipe_14_Z_p_O_FD));
p_O_FD x_14_pipe_15_Z(.Q(un84_sop_0_0_0_0_0[7:7]),.D(un84_sop_0_0_0_0_1[7:7]),.C(clk),.E(p_x_14_pipe_15_Z_p_O_FD));
p_O_FD x_14_pipe_16_Z(.Q(un84_sop_0_0_0_0_0[8:8]),.D(un84_sop_0_0_0_0_1[8:8]),.C(clk),.E(p_x_14_pipe_16_Z_p_O_FD));
p_O_FD x_14_pipe_17_Z(.Q(un84_sop_0_0_0_0_0[9:9]),.D(un84_sop_0_0_0_0_1[9:9]),.C(clk),.E(p_x_14_pipe_17_Z_p_O_FD));
p_O_FD x_9_pipe_1_Z(.Q(un1_x_11_0_0[7:7]),.D(un1_x_11_0_0_0[7:7]),.C(clk),.E(p_x_9_pipe_1_Z_p_O_FD));
p_O_FD x_9_pipe_2_Z(.Q(un1_x_11_0_0[8:8]),.D(un1_x_11_0_0_0[8:8]),.C(clk),.E(p_x_9_pipe_2_Z_p_O_FD));
p_O_FD x_9_pipe_3_Z(.Q(un1_x_11_0_0[9:9]),.D(un1_x_11_0_0_0[9:9]),.C(clk),.E(p_x_9_pipe_3_Z_p_O_FD));
p_O_FD x_9_pipe_4_Z(.Q(un1_x_11_0_0[10:10]),.D(un1_x_11_0_0_0[10:10]),.C(clk),.E(p_x_9_pipe_4_Z_p_O_FD));
p_O_FD x_9_pipe_5_Z(.Q(un1_x_11_0_0[11:11]),.D(un1_x_11_0_0_0[11:11]),.C(clk),.E(p_x_9_pipe_5_Z_p_O_FD));
p_O_FD x_9_pipe_6_Z(.Q(un1_x_11_0_0[12:12]),.D(un1_x_11_0_0_0[12:12]),.C(clk),.E(p_x_9_pipe_6_Z_p_O_FD));
p_O_FD x_9_pipe_7_Z(.Q(un1_x_11_0_0[13:13]),.D(un1_x_11_0_0_0[13:13]),.C(clk),.E(p_x_9_pipe_7_Z_p_O_FD));
p_O_FD x_9_pipe_8_Z(.Q(un1_x_11_0_0[14:14]),.D(un1_x_11_0_0_0[14:14]),.C(clk),.E(p_x_9_pipe_8_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_15_Z(.Q(un84_sop_0_0_0_10_0[0:0]),.D(un84_sop_0_0_0_0_8[0:0]),.C(clk),.E(p_x_15_pipe_0_0_15_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_16_Z(.Q(un84_sop_0_0_0_10_0[1:1]),.D(un84_sop_0_0_0_0_8[1:1]),.C(clk),.E(p_x_15_pipe_0_0_16_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_17_Z(.Q(un84_sop_0_0_0_10_0[2:2]),.D(un84_sop_0_0_0_0_8[2:2]),.C(clk),.E(p_x_15_pipe_0_0_17_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_18_Z(.Q(un84_sop_0_0_0_10_0[3:3]),.D(un84_sop_0_0_0_0_8[3:3]),.C(clk),.E(p_x_15_pipe_0_0_18_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_19_Z(.Q(un84_sop_0_0_0_10_0[4:4]),.D(un84_sop_0_0_0_0_8[4:4]),.C(clk),.E(p_x_15_pipe_0_0_19_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_20_Z(.Q(un84_sop_0_0_0_10_0[5:5]),.D(un84_sop_0_0_0_0_8[5:5]),.C(clk),.E(p_x_15_pipe_0_0_20_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_21_Z(.Q(un84_sop_0_0_0_10_0[6:6]),.D(un84_sop_0_0_0_0_8[6:6]),.C(clk),.E(p_x_15_pipe_0_0_21_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_22_Z(.Q(un84_sop_0_0_0_10_0[7:7]),.D(un84_sop_0_0_0_0_8[7:7]),.C(clk),.E(p_x_15_pipe_0_0_22_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_23_Z(.Q(un84_sop_0_0_0_10_0[8:8]),.D(un84_sop_0_0_0_0_8[8:8]),.C(clk),.E(p_x_15_pipe_0_0_23_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_24_Z(.Q(un84_sop_0_0_0_10_0[9:9]),.D(un84_sop_0_0_0_0_8[9:9]),.C(clk),.E(p_x_15_pipe_0_0_24_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_25_Z(.Q(un84_sop_0_0_0_10_0[10:10]),.D(un84_sop_0_0_0_0_8[10:10]),.C(clk),.E(p_x_15_pipe_0_0_25_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_26_Z(.Q(un84_sop_0_0_0_10_0[11:11]),.D(un84_sop_0_0_0_0_8[11:11]),.C(clk),.E(p_x_15_pipe_0_0_26_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_27_Z(.Q(un84_sop_0_0_0_10_0[12:12]),.D(un84_sop_0_0_0_0_8[12:12]),.C(clk),.E(p_x_15_pipe_0_0_27_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_28_Z(.Q(un84_sop_0_0_0_10_0[13:13]),.D(un84_sop_0_0_0_0_8[13:13]),.C(clk),.E(p_x_15_pipe_0_0_28_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_29_Z(.Q(un84_sop_0_0_0_10_0[14:14]),.D(un84_sop_0_0_0_0_8[14:14]),.C(clk),.E(p_x_15_pipe_0_0_29_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_0_Z(.Q(un84_sop_0_0_0_0_5[0:0]),.D(un84_sop_0_0_0_5_0[0:0]),.C(clk),.E(p_x_16_pipe_0_0_0_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_1_Z(.Q(un84_sop_0_0_0_0_5[1:1]),.D(un84_sop_0_0_0_5_0[1:1]),.C(clk),.E(p_x_16_pipe_0_0_1_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_2_Z(.Q(un84_sop_0_0_0_0_5[2:2]),.D(un84_sop_0_0_0_5_0[2:2]),.C(clk),.E(p_x_16_pipe_0_0_2_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_3_Z(.Q(un84_sop_0_0_0_0_5[3:3]),.D(un84_sop_0_0_0_5_0[3:3]),.C(clk),.E(p_x_16_pipe_0_0_3_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_4_Z(.Q(un84_sop_0_0_0_0_5[4:4]),.D(un84_sop_0_0_0_5_0[4:4]),.C(clk),.E(p_x_16_pipe_0_0_4_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_5_Z(.Q(un84_sop_0_0_0_0_5[5:5]),.D(un84_sop_0_0_0_5_0[5:5]),.C(clk),.E(p_x_16_pipe_0_0_5_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_6_Z(.Q(un84_sop_0_0_0_0_5[6:6]),.D(un84_sop_0_0_0_5_0[6:6]),.C(clk),.E(p_x_16_pipe_0_0_6_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_7_Z(.Q(un84_sop_0_0_0_0_5[7:7]),.D(un84_sop_0_0_0_5_0[7:7]),.C(clk),.E(p_x_16_pipe_0_0_7_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_8_Z(.Q(un84_sop_0_0_0_0_5[8:8]),.D(un84_sop_0_0_0_5_0[8:8]),.C(clk),.E(p_x_16_pipe_0_0_8_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_9_Z(.Q(un84_sop_0_0_0_0_5[9:9]),.D(un84_sop_0_0_0_5_0[9:9]),.C(clk),.E(p_x_16_pipe_0_0_9_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_10_Z(.Q(un84_sop_0_0_0_0_5[10:10]),.D(un84_sop_0_0_0_5_0[10:10]),.C(clk),.E(p_x_16_pipe_0_0_10_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_11_Z(.Q(un84_sop_0_0_0_0_5[11:11]),.D(un84_sop_0_0_0_5_0[11:11]),.C(clk),.E(p_x_16_pipe_0_0_11_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_12_Z(.Q(un84_sop_0_0_0_0_5[12:12]),.D(un84_sop_0_0_0_5_0[12:12]),.C(clk),.E(p_x_16_pipe_0_0_12_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_13_Z(.Q(un84_sop_0_0_0_0_5[13:13]),.D(un84_sop_0_0_0_5_0[13:13]),.C(clk),.E(p_x_16_pipe_0_0_13_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_14_Z(.Q(un84_sop_0_0_0_0_5[14:14]),.D(un84_sop_0_0_0_5_0[14:14]),.C(clk),.E(p_x_16_pipe_0_0_14_Z_p_O_FD));
p_O_FD desc33(.Q(x_4[7:7]),.D(x_4_tmp_d_array_0),.C(clk),.E(p_desc33_p_O_FD));
p_O_FD desc34(.Q(x_4[6:6]),.D(x_4_0_tmp_d_array_0),.C(clk),.E(p_desc34_p_O_FD));
p_O_FD desc35(.Q(x_4[5:5]),.D(x_4_1_tmp_d_array_0),.C(clk),.E(p_desc35_p_O_FD));
p_O_FD desc36(.Q(x_4[4:4]),.D(x_4_2_tmp_d_array_0),.C(clk),.E(p_desc36_p_O_FD));
p_O_FD desc37(.Q(x_4[3:3]),.D(x_4_3_tmp_d_array_0),.C(clk),.E(p_desc37_p_O_FD));
p_O_FD desc38(.Q(x_4[2:2]),.D(x_4_4_tmp_d_array_0),.C(clk),.E(p_desc38_p_O_FD));
p_O_FD desc39(.Q(x_4[1:1]),.D(x_4_5_tmp_d_array_0),.C(clk),.E(p_desc39_p_O_FD));
p_O_FD desc40(.Q(x_4[0:0]),.D(x_4_6_tmp_d_array_0),.C(clk),.E(p_desc40_p_O_FD));
p_O_FD desc41(.Q(x_7[7:7]),.D(x_7_tmp_d_array_0),.C(clk),.E(p_desc41_p_O_FD));
p_O_FD desc42(.Q(x_7[6:6]),.D(x_7_0_tmp_d_array_0),.C(clk),.E(p_desc42_p_O_FD));
p_O_FD desc43(.Q(x_7[5:5]),.D(x_7_1_tmp_d_array_0),.C(clk),.E(p_desc43_p_O_FD));
p_O_FD desc44(.Q(x_7[4:4]),.D(x_7_2_tmp_d_array_0),.C(clk),.E(p_desc44_p_O_FD));
p_O_FD desc45(.Q(x_7[3:3]),.D(x_7_3_tmp_d_array_0),.C(clk),.E(p_desc45_p_O_FD));
p_O_FD desc46(.Q(x_7[2:2]),.D(x_7_4_tmp_d_array_0),.C(clk),.E(p_desc46_p_O_FD));
p_O_FD desc47(.Q(x_7[1:1]),.D(x_7_5_tmp_d_array_0),.C(clk),.E(p_desc47_p_O_FD));
p_O_FD desc48(.Q(x_7[0:0]),.D(x_7_6_tmp_d_array_0),.C(clk),.E(p_desc48_p_O_FD));
p_O_FD desc49(.Q(x_12[7:7]),.D(x_12_tmp_d_array_0),.C(clk),.E(p_desc49_p_O_FD));
p_O_FD desc50(.Q(x_12[6:6]),.D(x_12_0_tmp_d_array_0),.C(clk),.E(p_desc50_p_O_FD));
p_O_FD desc51(.Q(x_12[5:5]),.D(x_12_1_tmp_d_array_0),.C(clk),.E(p_desc51_p_O_FD));
p_O_FD desc52(.Q(x_12[4:4]),.D(x_12_2_tmp_d_array_0),.C(clk),.E(p_desc52_p_O_FD));
p_O_FD desc53(.Q(x_12[3:3]),.D(x_12_3_tmp_d_array_0),.C(clk),.E(p_desc53_p_O_FD));
p_O_FD desc54(.Q(x_12[2:2]),.D(x_12_4_tmp_d_array_0),.C(clk),.E(p_desc54_p_O_FD));
p_O_FD desc55(.Q(x_12[1:1]),.D(x_12_5_tmp_d_array_0),.C(clk),.E(p_desc55_p_O_FD));
p_O_FD desc56(.Q(x_12[0:0]),.D(x_12_6_tmp_d_array_0),.C(clk),.E(p_desc56_p_O_FD));
MUXCY_L un84_sop_1_6_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_x_3_0[4:4]),.LO(un84_sop_1_6_0_cry_0_cy));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_x_9_0_0[5:5]),.LO(un84_sop_0_0_0_6_6_0_cry_0_cy));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_x_14_0_0_0[4:4]),.LO(un84_sop_0_0_0_11_6_0_cry_0_cy));
LUT3 un84_sop_0_0_0_11_0_cry_2_RNO_cZ(.I0(x_8[1:1]),.I1(x_8[0:0]),.I2(un84_sop_0_0_0_0_11_7[1:1]),.O(un84_sop_0_0_0_11_0_cry_2_RNO));
defparam un84_sop_0_0_0_11_0_cry_2_RNO_cZ.INIT=8'h60;
LUT6 un84_sop_0_0_0_11_6_0_axb_8_cZ(.I0(un1_x_12_0_0[11:11]),.I1(un1_x_12_0_0[12:12]),.I2(un1_x_13_0_0[12:12]),.I3(un1_x_13_0_0[13:13]),.I4(un1_x_14_0_0[11:11]),.I5(un1_x_14_0_0[12:12]),.O(un84_sop_0_0_0_11_6_0_axb_8));
defparam un84_sop_0_0_0_11_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_3_cZ(.I0(un1_x_12_0_0[6:6]),.I1(un1_x_12_0_0[7:7]),.I2(un1_x_13_0_0[7:7]),.I3(un1_x_13_0_0[8:8]),.I4(un1_x_14_0_0[6:6]),.I5(un1_x_14_0_0[7:7]),.O(un84_sop_0_0_0_11_6_0_axb_3));
defparam un84_sop_0_0_0_11_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_4_cZ(.I0(un1_x_12_0_0[7:7]),.I1(un1_x_12_0_0[8:8]),.I2(un1_x_13_0_0[8:8]),.I3(un1_x_13_0_0[9:9]),.I4(un1_x_14_0_0[7:7]),.I5(un1_x_14_0_0[8:8]),.O(un84_sop_0_0_0_11_6_0_axb_4));
defparam un84_sop_0_0_0_11_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_9_cZ(.I0(un1_x_12_0_0[12:12]),.I1(un1_x_12_0_0[13:13]),.I2(un1_x_13_0_0[13:13]),.I3(un1_x_13_0_0[14:14]),.I4(un1_x_14_0_0[12:12]),.I5(un1_x_14_0_0[13:13]),.O(un84_sop_0_0_0_11_6_0_axb_9));
defparam un84_sop_0_0_0_11_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
LUT5 un84_sop_0_0_0_11_6_0_axb_11_cZ(.I0(un1_x_12_0_0[14:14]),.I1(un1_x_14_0_0[14:14]),.I2(un1_x_12_0_0[15:15]),.I3(un1_x_14_0_0[15:15]),.I4(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_11));
defparam un84_sop_0_0_0_11_6_0_axb_11_cZ.INIT=32'h1EE18778;
LUT6 un84_sop_1_6_0_axb_4_cZ(.I0(un1_x_1[7:7]),.I1(un1_x_1[8:8]),.I2(un1_x_2[8:8]),.I3(un1_x_2[9:9]),.I4(un1_x_3[7:7]),.I5(un1_x_3[8:8]),.O(un84_sop_1_6_0_axb_4));
defparam un84_sop_1_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_10_cZ(.I0(un1_x_12_0_0[13:13]),.I1(un1_x_12_0_0[14:14]),.I2(un1_x_13_0_0[14:14]),.I3(un1_x_14_0_0[13:13]),.I4(un1_x_14_0_0[14:14]),.I5(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_10));
defparam un84_sop_0_0_0_11_6_0_axb_10_cZ.INIT=64'h366CC993C993366C;
LUT6 un84_sop_0_0_0_11_6_0_axb_2_cZ(.I0(un1_x_12_0_0[5:5]),.I1(un1_x_12_0_0[6:6]),.I2(un1_x_13_0_0[6:6]),.I3(un1_x_13_0_0[7:7]),.I4(un1_x_14_0_0[5:5]),.I5(un1_x_14_0_0[6:6]),.O(un84_sop_0_0_0_11_6_0_axb_2));
defparam un84_sop_0_0_0_11_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_5_cZ(.I0(un84_sop_0_0_0_0_11_7[4:4]),.I1(un84_sop_0_0_0_0_11_7[5:5]),.I2(un84_sop_0_0_0_0_11_6[4:4]),.I3(un84_sop_0_0_0_0_11_6[5:5]),.I4(un1_x_10_0_0[8:8]),.I5(un1_x_10_0_0[9:9]),.LO(un84_sop_0_0_0_11_0_axb_5));
defparam un84_sop_0_0_0_11_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_6_cZ(.I0(un84_sop_0_0_0_0_11_7[5:5]),.I1(un84_sop_0_0_0_0_11_7[6:6]),.I2(un84_sop_0_0_0_0_11_6[5:5]),.I3(un84_sop_0_0_0_0_11_6[6:6]),.I4(un1_x_10_0_0[9:9]),.I5(un1_x_10_0_0[10:10]),.LO(un84_sop_0_0_0_11_0_axb_6));
defparam un84_sop_0_0_0_11_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_6_cZ(.I0(un1_x_12_0_0[9:9]),.I1(un1_x_12_0_0[10:10]),.I2(un1_x_13_0_0[10:10]),.I3(un1_x_13_0_0[11:11]),.I4(un1_x_14_0_0[9:9]),.I5(un1_x_14_0_0[10:10]),.O(un84_sop_0_0_0_11_6_0_axb_6));
defparam un84_sop_0_0_0_11_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_7_cZ(.I0(un1_x_12_0_0[10:10]),.I1(un1_x_12_0_0[11:11]),.I2(un1_x_13_0_0[11:11]),.I3(un1_x_13_0_0[12:12]),.I4(un1_x_14_0_0[10:10]),.I5(un1_x_14_0_0[11:11]),.O(un84_sop_0_0_0_11_6_0_axb_7));
defparam un84_sop_0_0_0_11_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_10_cZ(.I0(un84_sop_0_0_0_0_11_7[9:9]),.I1(un84_sop_0_0_0_0_11_7[14:14]),.I2(un84_sop_0_0_0_0_11_6[9:9]),.I3(un84_sop_0_0_0_0_11_6[10:10]),.I4(un1_x_10_0_0[13:13]),.I5(un1_x_10_0_0[14:14]),.LO(un84_sop_0_0_0_11_0_axb_10));
defparam un84_sop_0_0_0_11_0_axb_10_cZ.INIT=64'h36C96C93C936936C;
LUT4_L un84_sop_0_0_0_11_0_axb_12_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[11:11]),.I2(un84_sop_0_0_0_0_11_6[12:12]),.I3(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_12));
defparam un84_sop_0_0_0_11_0_axb_12_cZ.INIT=16'h4BD2;
LUT4_L un84_sop_0_0_0_11_0_axb_13_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[14:14]),.I2(un84_sop_0_0_0_0_11_6[12:12]),.I3(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_13));
defparam un84_sop_0_0_0_11_0_axb_13_cZ.INIT=16'h63C6;
LUT3 un84_sop_0_0_0_11_6_0_axb_13_cZ(.I0(un1_x_12_0_0[15:15]),.I1(un1_x_14_0_0[15:15]),.I2(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_13));
defparam un84_sop_0_0_0_11_6_0_axb_13_cZ.INIT=8'h7E;
LUT6_L un84_sop_0_0_0_11_0_axb_3_cZ(.I0(un84_sop_0_0_0_0_11_7[2:2]),.I1(un84_sop_0_0_0_0_11_7[3:3]),.I2(un84_sop_0_0_0_0_11_6[2:2]),.I3(un1_x_10_s_2_sf),.I4(un1_x_10_axb_3),.I5(un84_sop_0_0_0_0_11_6[3:3]),.LO(un84_sop_0_0_0_11_0_axb_3));
defparam un84_sop_0_0_0_11_0_axb_3_cZ.INIT=64'h366CC993C993366C;
LUT6_L un84_sop_0_0_0_11_0_axb_4_cZ(.I0(un84_sop_0_0_0_0_11_7[3:3]),.I1(un84_sop_0_0_0_0_11_7[4:4]),.I2(un1_x_10_axb_3),.I3(un84_sop_0_0_0_0_11_6[3:3]),.I4(un84_sop_0_0_0_0_11_6[4:4]),.I5(un1_x_10_0_0[8:8]),.LO(un84_sop_0_0_0_11_0_axb_4));
defparam un84_sop_0_0_0_11_0_axb_4_cZ.INIT=64'h366CC993C993366C;
LUT6 un84_sop_0_0_0_6_6_0_axb_5_cZ(.I0(un1_x_7_0[6:6]),.I1(un1_x_7_0[7:7]),.I2(un1_x_8_0[8:8]),.I3(un1_x_8_0[9:9]),.I4(un1_x_9_0[9:9]),.I5(un1_x_9_0[10:10]),.O(un84_sop_0_0_0_6_6_0_axb_5));
defparam un84_sop_0_0_0_6_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_6_cZ(.I0(un1_x_7_0[7:7]),.I1(un1_x_7_0[8:8]),.I2(un1_x_8_0[9:9]),.I3(un1_x_8_0[10:10]),.I4(un1_x_9_0[10:10]),.I5(un1_x_9_0[11:11]),.O(un84_sop_0_0_0_6_6_0_axb_6));
defparam un84_sop_0_0_0_6_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_10_cZ(.I0(un1_x_7_0[11:11]),.I1(un1_x_7_0[12:12]),.I2(un1_x_8_0[13:13]),.I3(un1_x_8_0[14:14]),.I4(un1_x_9_0[14:14]),.I5(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_10));
defparam un84_sop_0_0_0_6_6_0_axb_10_cZ.INIT=64'h36C96C93C936936C;
LUT5 un84_sop_0_0_0_6_6_0_axb_11_cZ(.I0(un1_x_7_0[12:12]),.I1(un1_x_7_0[13:13]),.I2(un1_x_8_0[14:14]),.I3(un1_x_8_0[15:15]),.I4(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_11));
defparam un84_sop_0_0_0_6_6_0_axb_11_cZ.INIT=32'h36C9936C;
LUT6 un84_sop_0_0_0_1_6_8_axb_3_cZ(.I0(un84_sop_0_0_0_10_0[5:5]),.I1(un84_sop_0_0_0_10_0[6:6]),.I2(x_4[1:1]),.I3(x_4[0:0]),.I4(x_4[2:2]),.I5(x_4[3:3]),.O(un84_sop_0_0_0_1_6_8_axb_3));
defparam un84_sop_0_0_0_1_6_8_axb_3_cZ.INIT=64'h3C6969C3C396963C;
LUT6 un84_sop_0_0_0_1_6_8_axb_4_cZ(.I0(un84_sop_0_0_0_10_0[6:6]),.I1(un84_sop_0_0_0_10_0[7:7]),.I2(x_4[1:1]),.I3(x_4[2:2]),.I4(x_4[3:3]),.I5(x_4[4:4]),.O(un84_sop_0_0_0_1_6_8_axb_4));
defparam un84_sop_0_0_0_1_6_8_axb_4_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_1_6_8_axb_5_cZ(.I0(un84_sop_0_0_0_10_0[7:7]),.I1(un84_sop_0_0_0_10_0[8:8]),.I2(x_4[2:2]),.I3(x_4[3:3]),.I4(x_4[4:4]),.I5(x_4[5:5]),.O(un84_sop_0_0_0_1_6_8_axb_5));
defparam un84_sop_0_0_0_1_6_8_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_1_6_8_axb_6_cZ(.I0(un84_sop_0_0_0_10_0[8:8]),.I1(un84_sop_0_0_0_10_0[9:9]),.I2(x_4[6:6]),.I3(x_4[3:3]),.I4(x_4[4:4]),.I5(x_4[5:5]),.O(un84_sop_0_0_0_1_6_8_axb_6));
defparam un84_sop_0_0_0_1_6_8_axb_6_cZ.INIT=64'h3C69C39669C3963C;
LUT6 un84_sop_0_0_0_1_6_8_axb_7_cZ(.I0(un84_sop_0_0_0_10_0[9:9]),.I1(un84_sop_0_0_0_10_0[10:10]),.I2(x_4[6:6]),.I3(x_4[4:4]),.I4(x_4[5:5]),.I5(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_7));
defparam un84_sop_0_0_0_1_6_8_axb_7_cZ.INIT=64'h366CC993C993366C;
LUT5 un84_sop_0_0_0_1_6_8_axb_8_cZ(.I0(un84_sop_0_0_0_10_0[11:11]),.I1(un84_sop_0_0_0_10_0[10:10]),.I2(x_4[6:6]),.I3(x_4[5:5]),.I4(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_8));
defparam un84_sop_0_0_0_1_6_8_axb_8_cZ.INIT=32'h5A69965A;
LUT6 un84_sop_0_0_0_11_6_0_axb_5_cZ(.I0(un1_x_12_0_0[8:8]),.I1(un1_x_12_0_0[9:9]),.I2(un1_x_13_0_0[9:9]),.I3(un1_x_13_0_0[10:10]),.I4(un1_x_14_0_0[8:8]),.I5(un1_x_14_0_0[9:9]),.O(un84_sop_0_0_0_11_6_0_axb_5));
defparam un84_sop_0_0_0_11_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_2_cZ(.I0(un1_x_1[5:5]),.I1(un1_x_1[6:6]),.I2(un1_x_2[6:6]),.I3(un1_x_2[7:7]),.I4(un1_x_3[5:5]),.I5(un1_x_3[6:6]),.O(un84_sop_1_6_0_axb_2));
defparam un84_sop_1_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_3_cZ(.I0(un1_x_1[6:6]),.I1(un1_x_1[7:7]),.I2(un1_x_2[7:7]),.I3(un1_x_2[8:8]),.I4(un1_x_3[6:6]),.I5(un1_x_3[7:7]),.O(un84_sop_1_6_0_axb_3));
defparam un84_sop_1_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_5_cZ(.I0(un1_x_1[8:8]),.I1(un1_x_1[9:9]),.I2(un1_x_2[9:9]),.I3(un1_x_2[10:10]),.I4(un1_x_3[8:8]),.I5(un1_x_3[9:9]),.O(un84_sop_1_6_0_axb_5));
defparam un84_sop_1_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_6_cZ(.I0(un1_x_1[9:9]),.I1(un1_x_1[10:10]),.I2(un1_x_2[10:10]),.I3(un1_x_2[11:11]),.I4(un1_x_3[9:9]),.I5(un1_x_3[10:10]),.O(un84_sop_1_6_0_axb_6));
defparam un84_sop_1_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_7_cZ(.I0(un1_x_1[10:10]),.I1(un1_x_1[11:11]),.I2(un1_x_2[11:11]),.I3(un1_x_2[12:12]),.I4(un1_x_3[10:10]),.I5(un1_x_3[11:11]),.O(un84_sop_1_6_0_axb_7));
defparam un84_sop_1_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_8_cZ(.I0(un1_x_1[11:11]),.I1(un1_x_1[12:12]),.I2(un1_x_2[12:12]),.I3(un1_x_2[13:13]),.I4(un1_x_3[11:11]),.I5(un1_x_3[12:12]),.O(un84_sop_1_6_0_axb_8));
defparam un84_sop_1_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_9_cZ(.I0(un1_x_1[12:12]),.I1(un1_x_1[13:13]),.I2(un1_x_2[13:13]),.I3(un1_x_2[14:14]),.I4(un1_x_3[12:12]),.I5(un1_x_3[13:13]),.O(un84_sop_1_6_0_axb_9));
defparam un84_sop_1_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_10_cZ(.I0(un1_x_1[13:13]),.I1(un1_x_1[14:14]),.I2(un1_x_2[14:14]),.I3(un1_x_3[13:13]),.I4(un1_x_3[14:14]),.I5(un1_x_2[15:15]),.O(un84_sop_1_6_0_axb_10));
defparam un84_sop_1_6_0_axb_10_cZ.INIT=64'h366CC993C993366C;
LUT5 un84_sop_1_6_0_axb_11_cZ(.I0(un1_x_1[14:14]),.I1(un1_x_3[14:14]),.I2(un1_x_1[15:15]),.I3(un1_x_3[15:15]),.I4(un1_x_2[15:15]),.O(un84_sop_1_6_0_axb_11));
defparam un84_sop_1_6_0_axb_11_cZ.INIT=32'h1EE18778;
LUT3 un84_sop_1_6_0_axb_13_cZ(.I0(un1_x_1[15:15]),.I1(un1_x_3[15:15]),.I2(un1_x_2[15:15]),.O(un84_sop_1_6_0_axb_13));
defparam un84_sop_1_6_0_axb_13_cZ.INIT=8'h7E;
LUT6_L un84_sop_0_0_0_11_0_axb_7_cZ(.I0(un84_sop_0_0_0_0_11_7[6:6]),.I1(un84_sop_0_0_0_0_11_7[7:7]),.I2(un84_sop_0_0_0_0_11_6[6:6]),.I3(un84_sop_0_0_0_0_11_6[7:7]),.I4(un1_x_10_0_0[10:10]),.I5(un1_x_10_0_0[11:11]),.LO(un84_sop_0_0_0_11_0_axb_7));
defparam un84_sop_0_0_0_11_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_8_cZ(.I0(un84_sop_0_0_0_0_11_7[7:7]),.I1(un84_sop_0_0_0_0_11_7[8:8]),.I2(un84_sop_0_0_0_0_11_6[7:7]),.I3(un84_sop_0_0_0_0_11_6[8:8]),.I4(un1_x_10_0_0[11:11]),.I5(un1_x_10_0_0[12:12]),.LO(un84_sop_0_0_0_11_0_axb_8));
defparam un84_sop_0_0_0_11_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_9_cZ(.I0(un84_sop_0_0_0_0_11_7[8:8]),.I1(un84_sop_0_0_0_0_11_7[9:9]),.I2(un84_sop_0_0_0_0_11_6[8:8]),.I3(un84_sop_0_0_0_0_11_6[9:9]),.I4(un1_x_10_0_0[12:12]),.I5(un1_x_10_0_0[13:13]),.LO(un84_sop_0_0_0_11_0_axb_9));
defparam un84_sop_0_0_0_11_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
LUT4_L un84_sop_0_0_0_11_0_axb_1_cZ(.I0(x_8[1:1]),.I1(x_8[0:0]),.I2(un84_sop_0_0_0_0_11_7[1:1]),.I3(un84_sop_0_0_0_0_11_6[1:1]),.LO(un84_sop_0_0_0_11_0_axb_1));
defparam un84_sop_0_0_0_11_0_axb_1_cZ.INIT=16'h6996;
LUT5_L un84_sop_0_0_0_11_0_axb_11_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[10:10]),.I2(un84_sop_0_0_0_0_11_6[11:11]),.I3(un1_x_10_0_0[14:14]),.I4(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_11));
defparam un84_sop_0_0_0_11_0_axb_11_cZ.INIT=32'h4B2DB4D2;
LUT3 un84_sop_0_0_0_1_6_axb_0(.I0(un84_sop_0_0_0_10_0[0:0]),.I1(un1_x_6_0[1:1]),.I2(un84_sop_0_0_0_1_6_6[0:0]),.O(un84_sop_0_0_0_5_0[0:0]));
defparam un84_sop_0_0_0_1_6_axb_0.INIT=8'h96;
LUT6 un84_sop_1_4_axb_4_cZ(.I0(x_0[3:3]),.I1(x_0[2:2]),.I2(x_0[1:1]),.I3(x_0[0:0]),.I4(x_0[4:4]),.I5(un84_sop_1_7[4:4]),.O(un84_sop_1_4_axb_4));
defparam un84_sop_1_4_axb_4_cZ.INIT=64'hFFFE00010001FFFE;
LUT6 un84_sop_0_0_0_6_6_0_axb_2_cZ(.I0(un1_x_7_0[3:3]),.I1(un1_x_7_0[4:4]),.I2(un1_x_8_0[5:5]),.I3(un1_x_8_0[6:6]),.I4(un1_x_9_0[6:6]),.I5(un1_x_9_0[7:7]),.O(un84_sop_0_0_0_6_6_0_axb_2));
defparam un84_sop_0_0_0_6_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_3_cZ(.I0(un1_x_7_0[4:4]),.I1(un1_x_7_0[5:5]),.I2(un1_x_8_0[6:6]),.I3(un1_x_8_0[7:7]),.I4(un1_x_9_0[7:7]),.I5(un1_x_9_0[8:8]),.O(un84_sop_0_0_0_6_6_0_axb_3));
defparam un84_sop_0_0_0_6_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_4_cZ(.I0(un1_x_7_0[5:5]),.I1(un1_x_7_0[6:6]),.I2(un1_x_8_0[7:7]),.I3(un1_x_8_0[8:8]),.I4(un1_x_9_0[8:8]),.I5(un1_x_9_0[9:9]),.O(un84_sop_0_0_0_6_6_0_axb_4));
defparam un84_sop_0_0_0_6_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_6_0_s_2_RNIGK751(.I0(x_8[1:1]),.I1(x_8[0:0]),.I2(un84_sop_0_0_0_0_11_7[1:1]),.I3(un84_sop_0_0_0_0_11_7[2:2]),.I4(un84_sop_0_0_0_0_11_6[2:2]),.I5(un1_x_10_s_2_sf),.LO(un84_sop_0_0_0_11_0_axb_2));
defparam un84_sop_0_0_0_11_6_0_s_2_RNIGK751.INIT=64'h9F60609F609F9F60;
LUT6 un84_sop_0_0_0_6_6_0_axb_7_cZ(.I0(un1_x_7_0[8:8]),.I1(un1_x_7_0[9:9]),.I2(un1_x_8_0[10:10]),.I3(un1_x_8_0[11:11]),.I4(un1_x_9_0[11:11]),.I5(un1_x_9_0[12:12]),.O(un84_sop_0_0_0_6_6_0_axb_7));
defparam un84_sop_0_0_0_6_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_8_cZ(.I0(un1_x_7_0[9:9]),.I1(un1_x_7_0[10:10]),.I2(un1_x_8_0[11:11]),.I3(un1_x_8_0[12:12]),.I4(un1_x_9_0[12:12]),.I5(un1_x_9_0[13:13]),.O(un84_sop_0_0_0_6_6_0_axb_8));
defparam un84_sop_0_0_0_6_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_9_cZ(.I0(un1_x_7_0[10:10]),.I1(un1_x_7_0[11:11]),.I2(un1_x_8_0[12:12]),.I3(un1_x_8_0[13:13]),.I4(un1_x_9_0[13:13]),.I5(un1_x_9_0[14:14]),.O(un84_sop_0_0_0_6_6_0_axb_9));
defparam un84_sop_0_0_0_6_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
LUT4 un1_x_10_axb_11_cZ(.I0(x_8[6:6]),.I1(x_8[7:7]),.I2(x_8[5:5]),.I3(un1_x_10_5_c5),.O(un1_x_10_axb_11));
defparam un1_x_10_axb_11_cZ.INIT=16'hFEFF;
LUT3_L un84_sop_0_0_0_11_0_axb_14_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[14:14]),.I2(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_14));
defparam un84_sop_0_0_0_11_0_axb_14_cZ.INIT=8'h7E;
LUT3 un84_sop_0_0_0_6_6_0_axb_14_cZ(.I0(un1_x_7_0[15:15]),.I1(un1_x_8_0[15:15]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_14));
defparam un84_sop_0_0_0_6_6_0_axb_14_cZ.INIT=8'h7E;
MUXCY_L un84_sop_0_0_0_11_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un84_sop_0_0_0_0_11_7_axb_0_ci),.LO(un84_sop_0_0_0_11_0_cry_0_cy));
LUT1 un1_x_10_4_s_2_RNI13H1(.I0(un1_x_10_4[2:2]),.O(un1_x_10_s_2_sf));
defparam un1_x_10_4_s_2_RNI13H1.INIT=2'h2;
LUT2_L un84_sop_0_0_0_1_axb_9_cZ(.I0(un1_x_16_0_0_0[14:14]),.I1(un1_x_15_0_0_0[14:14]),.LO(un84_sop_0_0_0_1_axb_9));
defparam un84_sop_0_0_0_1_axb_9_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_8_cZ(.I0(un1_x_16_0_0_0[14:14]),.I1(un1_x_15_0_0_0[14:14]),.LO(un84_sop_0_0_0_1_axb_8));
defparam un84_sop_0_0_0_1_axb_8_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_7_cZ(.I0(un1_x_16_0_0_0[13:13]),.I1(un1_x_15_0_0_0[13:13]),.LO(un84_sop_0_0_0_1_axb_7));
defparam un84_sop_0_0_0_1_axb_7_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_6_cZ(.I0(un1_x_16_0_0_0[12:12]),.I1(un1_x_15_0_0_0[12:12]),.LO(un84_sop_0_0_0_1_axb_6));
defparam un84_sop_0_0_0_1_axb_6_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_5_cZ(.I0(un1_x_16_0_0_0[11:11]),.I1(un1_x_15_0_0_0[11:11]),.LO(un84_sop_0_0_0_1_axb_5));
defparam un84_sop_0_0_0_1_axb_5_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_4_cZ(.I0(un1_x_16_0_0_0[10:10]),.I1(un1_x_15_0_0_0[10:10]),.LO(un84_sop_0_0_0_1_axb_4));
defparam un84_sop_0_0_0_1_axb_4_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_3_cZ(.I0(un1_x_16_0_0_0[9:9]),.I1(un1_x_15_0_0_0[9:9]),.LO(un84_sop_0_0_0_1_axb_3));
defparam un84_sop_0_0_0_1_axb_3_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_2_cZ(.I0(un1_x_16_0_0_0[8:8]),.I1(un1_x_15_0_0_0[8:8]),.LO(un84_sop_0_0_0_1_axb_2));
defparam un84_sop_0_0_0_1_axb_2_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_1_cZ(.I0(un1_x_16_0_0_0[7:7]),.I1(un1_x_15_0_0_0[7:7]),.LO(un84_sop_0_0_0_1_axb_1));
defparam un84_sop_0_0_0_1_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_axb_0(.I0(x_12[0:0]),.I1(x_13[0:0]),.O(un84_sop_0_0_0_0_1[0:0]));
defparam un84_sop_0_0_0_1_axb_0.INIT=4'h6;
LUT1 un1_x_16_0_axb_8_cZ(.I0(x_13[7:7]),.O(un1_x_16_0_axb_8));
defparam un1_x_16_0_axb_8_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_8_cZ(.I0(x_8[7:7]),.LO(un1_x_11_0_axb_8));
defparam un1_x_11_0_axb_8_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_7_cZ(.I0(x_8[7:7]),.LO(un1_x_11_0_axb_7));
defparam un1_x_11_0_axb_7_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_6_cZ(.I0(x_8[6:6]),.LO(un1_x_11_0_axb_6));
defparam un1_x_11_0_axb_6_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_5_cZ(.I0(x_8[5:5]),.LO(un1_x_11_0_axb_5));
defparam un1_x_11_0_axb_5_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_4_cZ(.I0(x_8[4:4]),.LO(un1_x_11_0_axb_4));
defparam un1_x_11_0_axb_4_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_3_cZ(.I0(x_8[3:3]),.LO(un1_x_11_0_axb_3));
defparam un1_x_11_0_axb_3_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_2_cZ(.I0(x_8[2:2]),.LO(un1_x_11_0_axb_2));
defparam un1_x_11_0_axb_2_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_1_cZ(.I0(x_8[1:1]),.LO(un1_x_11_0_axb_1));
defparam un1_x_11_0_axb_1_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_8_cZ(.I0(x_12[7:7]),.O(un1_x_15_0_axb_8));
defparam un1_x_15_0_axb_8_cZ.INIT=2'h1;
LUT1 un1_x_10_4_axb_10(.I0(x_8[7:7]),.O(un1_x_10_4[10:10]));
defparam un1_x_10_4_axb_10.INIT=2'h2;
LUT1 un1_x_10_4_axb_9(.I0(x_8[7:7]),.O(un1_x_10_4[9:9]));
defparam un1_x_10_4_axb_9.INIT=2'h2;
LUT2_L un84_sop_1_axb_14_cZ(.I0(un84_sop_1_6[14:14]),.I1(un84_sop_1_4[14:14]),.LO(un84_sop_1_axb_14));
defparam un84_sop_1_axb_14_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_13_cZ(.I0(un84_sop_1_6[14:14]),.I1(un84_sop_1_4[13:13]),.LO(un84_sop_1_axb_13));
defparam un84_sop_1_axb_13_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_12_cZ(.I0(un84_sop_1_6[12:12]),.I1(un84_sop_1_4[12:12]),.LO(un84_sop_1_axb_12));
defparam un84_sop_1_axb_12_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_11_cZ(.I0(un84_sop_1_6[11:11]),.I1(un84_sop_1_4[11:11]),.LO(un84_sop_1_axb_11));
defparam un84_sop_1_axb_11_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_10_cZ(.I0(un84_sop_1_6[10:10]),.I1(un84_sop_1_4[10:10]),.LO(un84_sop_1_axb_10));
defparam un84_sop_1_axb_10_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_9_cZ(.I0(un84_sop_1_6[9:9]),.I1(un84_sop_1_4[9:9]),.LO(un84_sop_1_axb_9));
defparam un84_sop_1_axb_9_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_8_cZ(.I0(un84_sop_1_6[8:8]),.I1(un84_sop_1_4[8:8]),.LO(un84_sop_1_axb_8));
defparam un84_sop_1_axb_8_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_7_cZ(.I0(un84_sop_1_6[7:7]),.I1(un84_sop_1_4[7:7]),.LO(un84_sop_1_axb_7));
defparam un84_sop_1_axb_7_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_10_cZ(.I0(un1_x_11_0_0[14:14]),.I1(un84_sop_0_0_0_0_0[9:9]),.O(un84_sop_0_0_0_0_11_7_axb_10));
defparam un84_sop_0_0_0_0_11_7_axb_10_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_14_cZ(.I0(un84_sop_0_0_0_0_5[14:14]),.I1(un1_x_4[15:15]),.O(un84_sop_1_7_axb_14));
defparam un84_sop_1_7_axb_14_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_14_cZ(.I0(un84_sop_0_0_0_1_6_6[14:14]),.I1(un84_sop_0_0_0_1_6_4[14:14]),.LO(un84_sop_0_0_0_1_6_axb_14));
defparam un84_sop_0_0_0_1_6_axb_14_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_13_cZ(.I0(un84_sop_0_0_0_1_6_6[13:13]),.I1(un84_sop_0_0_0_1_6_4[13:13]),.LO(un84_sop_0_0_0_1_6_axb_13));
defparam un84_sop_0_0_0_1_6_axb_13_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_12_cZ(.I0(un84_sop_0_0_0_1_6_6[12:12]),.I1(un84_sop_0_0_0_1_6_4[12:12]),.LO(un84_sop_0_0_0_1_6_axb_12));
defparam un84_sop_0_0_0_1_6_axb_12_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_11_cZ(.I0(un84_sop_0_0_0_1_6_6[11:11]),.I1(un84_sop_0_0_0_1_6_4[11:11]),.LO(un84_sop_0_0_0_1_6_axb_11));
defparam un84_sop_0_0_0_1_6_axb_11_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_10_cZ(.I0(un84_sop_0_0_0_1_6_6[10:10]),.I1(un84_sop_0_0_0_1_6_4[10:10]),.LO(un84_sop_0_0_0_1_6_axb_10));
defparam un84_sop_0_0_0_1_6_axb_10_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_9_cZ(.I0(un84_sop_0_0_0_1_6_6[9:9]),.I1(un84_sop_0_0_0_1_6_4[9:9]),.LO(un84_sop_0_0_0_1_6_axb_9));
defparam un84_sop_0_0_0_1_6_axb_9_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_8_cZ(.I0(un84_sop_0_0_0_1_6_6[8:8]),.I1(un84_sop_0_0_0_1_6_4[8:8]),.LO(un84_sop_0_0_0_1_6_axb_8));
defparam un84_sop_0_0_0_1_6_axb_8_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_7_cZ(.I0(un84_sop_0_0_0_1_6_6[7:7]),.I1(un84_sop_0_0_0_1_6_4[7:7]),.LO(un84_sop_0_0_0_1_6_axb_7));
defparam un84_sop_0_0_0_1_6_axb_7_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_6_cZ(.I0(un84_sop_0_0_0_1_6_6[6:6]),.I1(un84_sop_0_0_0_1_6_4[6:6]),.LO(un84_sop_0_0_0_1_6_axb_6));
defparam un84_sop_0_0_0_1_6_axb_6_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_5_cZ(.I0(un84_sop_0_0_0_1_6_6[5:5]),.I1(un84_sop_0_0_0_1_6_4[5:5]),.LO(un84_sop_0_0_0_1_6_axb_5));
defparam un84_sop_0_0_0_1_6_axb_5_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_4_cZ(.I0(un84_sop_0_0_0_1_6_6[4:4]),.I1(un84_sop_0_0_0_1_6_4[4:4]),.LO(un84_sop_0_0_0_1_6_axb_4));
defparam un84_sop_0_0_0_1_6_axb_4_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_3_cZ(.I0(un84_sop_0_0_0_1_6_4[3:3]),.I1(un84_sop_0_0_0_1_6_6[3:3]),.LO(un84_sop_0_0_0_1_6_axb_3));
defparam un84_sop_0_0_0_1_6_axb_3_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_2_cZ(.I0(un84_sop_0_0_0_1_6_4[2:2]),.I1(un84_sop_0_0_0_1_6_6[2:2]),.LO(un84_sop_0_0_0_1_6_axb_2));
defparam un84_sop_0_0_0_1_6_axb_2_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_1_cZ(.I0(un84_sop_0_0_0_1_6_4[1:1]),.I1(un84_sop_0_0_0_1_6_6[1:1]),.LO(un84_sop_0_0_0_1_6_axb_1));
defparam un84_sop_0_0_0_1_6_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_14_cZ(.I0(un1_x_6_0[15:15]),.I1(un84_sop_0_0_0_1_6_8[14:14]),.O(un84_sop_0_0_0_1_6_4_axb_14));
defparam un84_sop_0_0_0_1_6_4_axb_14_cZ.INIT=4'h6;
LUT2 un1_x_10_axb_3_cZ(.I0(x_8[0:0]),.I1(un1_x_10_4[3:3]),.O(un1_x_10_axb_3));
defparam un1_x_10_axb_3_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_8_axb_11_cZ(.I0(un84_sop_0_0_0_10_0[14:14]),.I1(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_11));
defparam un84_sop_0_0_0_1_6_8_axb_11_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_11_0_axb_0_cZ(.I0(x_8[0:0]),.I1(un84_sop_0_0_0_0_11_6[0:0]),.LO(un84_sop_0_0_0_11_0_axb_0));
defparam un84_sop_0_0_0_11_0_axb_0_cZ.INIT=4'h6;
LUT4 un1_x_0_0_ac0_5(.I0(x_0[3:3]),.I1(x_0[2:2]),.I2(x_0[1:1]),.I3(x_0[0:0]),.O(un1_x_0_0_c4));
defparam un1_x_0_0_ac0_5.INIT=16'h0001;
LUT3 un84_sop_0_0_0_11_6_0_o5_11_cZ(.I0(un1_x_12_0_0[15:15]),.I1(un1_x_14_0_0[15:15]),.I2(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_o5_11));
defparam un84_sop_0_0_0_11_6_0_o5_11_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_10_cZ(.I0(un1_x_12_0_0[14:14]),.I1(un1_x_14_0_0[14:14]),.I2(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_o5_10));
defparam un84_sop_0_0_0_11_6_0_o5_10_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_9_cZ(.I0(un1_x_12_0_0[13:13]),.I1(un1_x_13_0_0[14:14]),.I2(un1_x_14_0_0[13:13]),.O(un84_sop_0_0_0_11_6_0_o5_9));
defparam un84_sop_0_0_0_11_6_0_o5_9_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_8_cZ(.I0(un1_x_12_0_0[12:12]),.I1(un1_x_13_0_0[13:13]),.I2(un1_x_14_0_0[12:12]),.O(un84_sop_0_0_0_11_6_0_o5_8));
defparam un84_sop_0_0_0_11_6_0_o5_8_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_7_cZ(.I0(un1_x_12_0_0[11:11]),.I1(un1_x_13_0_0[12:12]),.I2(un1_x_14_0_0[11:11]),.O(un84_sop_0_0_0_11_6_0_o5_7));
defparam un84_sop_0_0_0_11_6_0_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_6_cZ(.I0(un1_x_12_0_0[10:10]),.I1(un1_x_13_0_0[11:11]),.I2(un1_x_14_0_0[10:10]),.O(un84_sop_0_0_0_11_6_0_o5_6));
defparam un84_sop_0_0_0_11_6_0_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_5_cZ(.I0(un1_x_12_0_0[9:9]),.I1(un1_x_13_0_0[10:10]),.I2(un1_x_14_0_0[9:9]),.O(un84_sop_0_0_0_11_6_0_o5_5));
defparam un84_sop_0_0_0_11_6_0_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_4_cZ(.I0(un1_x_12_0_0[8:8]),.I1(un1_x_13_0_0[9:9]),.I2(un1_x_14_0_0[8:8]),.O(un84_sop_0_0_0_11_6_0_o5_4));
defparam un84_sop_0_0_0_11_6_0_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_3_cZ(.I0(un1_x_12_0_0[7:7]),.I1(un1_x_13_0_0[8:8]),.I2(un1_x_14_0_0[7:7]),.O(un84_sop_0_0_0_11_6_0_o5_3));
defparam un84_sop_0_0_0_11_6_0_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_2_cZ(.I0(un1_x_12_0_0[6:6]),.I1(un1_x_13_0_0[7:7]),.I2(un1_x_14_0_0[6:6]),.O(un84_sop_0_0_0_11_6_0_o5_2));
defparam un84_sop_0_0_0_11_6_0_o5_2_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_12_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[12:12]),.I2(un1_x_10_0_0[15:15]),.O(un84_sop_0_0_0_11_0_o5_12));
defparam un84_sop_0_0_0_11_0_o5_12_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_11_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[11:11]),.I2(un1_x_10_0_0[15:15]),.O(un84_sop_0_0_0_11_0_o5_11));
defparam un84_sop_0_0_0_11_0_o5_11_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_10_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[10:10]),.I2(un1_x_10_0_0[14:14]),.O(un84_sop_0_0_0_11_0_o5_10));
defparam un84_sop_0_0_0_11_0_o5_10_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_9_cZ(.I0(un84_sop_0_0_0_0_11_7[9:9]),.I1(un84_sop_0_0_0_0_11_6[9:9]),.I2(un1_x_10_0_0[13:13]),.O(un84_sop_0_0_0_11_0_o5_9));
defparam un84_sop_0_0_0_11_0_o5_9_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_8_cZ(.I0(un84_sop_0_0_0_0_11_7[8:8]),.I1(un84_sop_0_0_0_0_11_6[8:8]),.I2(un1_x_10_0_0[12:12]),.O(un84_sop_0_0_0_11_0_o5_8));
defparam un84_sop_0_0_0_11_0_o5_8_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_7_cZ(.I0(un84_sop_0_0_0_0_11_7[7:7]),.I1(un84_sop_0_0_0_0_11_6[7:7]),.I2(un1_x_10_0_0[11:11]),.O(un84_sop_0_0_0_11_0_o5_7));
defparam un84_sop_0_0_0_11_0_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_6_cZ(.I0(un84_sop_0_0_0_0_11_7[6:6]),.I1(un84_sop_0_0_0_0_11_6[6:6]),.I2(un1_x_10_0_0[10:10]),.O(un84_sop_0_0_0_11_0_o5_6));
defparam un84_sop_0_0_0_11_0_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_5_cZ(.I0(un84_sop_0_0_0_0_11_7[5:5]),.I1(un84_sop_0_0_0_0_11_6[5:5]),.I2(un1_x_10_0_0[9:9]),.O(un84_sop_0_0_0_11_0_o5_5));
defparam un84_sop_0_0_0_11_0_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_4_cZ(.I0(un84_sop_0_0_0_0_11_7[4:4]),.I1(un84_sop_0_0_0_0_11_6[4:4]),.I2(un1_x_10_0_0[8:8]),.O(un84_sop_0_0_0_11_0_o5_4));
defparam un84_sop_0_0_0_11_0_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_3_cZ(.I0(un84_sop_0_0_0_0_11_7[3:3]),.I1(un1_x_10_axb_3),.I2(un84_sop_0_0_0_0_11_6[3:3]),.O(un84_sop_0_0_0_11_0_o5_3));
defparam un84_sop_0_0_0_11_0_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_2_cZ(.I0(un84_sop_0_0_0_0_11_7[2:2]),.I1(un84_sop_0_0_0_0_11_6[2:2]),.I2(un1_x_10_s_2_sf),.O(un84_sop_0_0_0_11_0_o5_2));
defparam un84_sop_0_0_0_11_0_o5_2_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_12_cZ(.I0(un1_x_7_0[14:14]),.I1(un1_x_8_0[15:15]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_o5_12));
defparam un84_sop_0_0_0_6_6_0_o5_12_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_11_cZ(.I0(un1_x_7_0[13:13]),.I1(un1_x_8_0[15:15]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_o5_11));
defparam un84_sop_0_0_0_6_6_0_o5_11_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_10_cZ(.I0(un1_x_7_0[12:12]),.I1(un1_x_8_0[14:14]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_o5_10));
defparam un84_sop_0_0_0_6_6_0_o5_10_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_9_cZ(.I0(un1_x_7_0[11:11]),.I1(un1_x_8_0[13:13]),.I2(un1_x_9_0[14:14]),.O(un84_sop_0_0_0_6_6_0_o5_9));
defparam un84_sop_0_0_0_6_6_0_o5_9_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_8_cZ(.I0(un1_x_7_0[10:10]),.I1(un1_x_8_0[12:12]),.I2(un1_x_9_0[13:13]),.O(un84_sop_0_0_0_6_6_0_o5_8));
defparam un84_sop_0_0_0_6_6_0_o5_8_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_7_cZ(.I0(un1_x_7_0[9:9]),.I1(un1_x_8_0[11:11]),.I2(un1_x_9_0[12:12]),.O(un84_sop_0_0_0_6_6_0_o5_7));
defparam un84_sop_0_0_0_6_6_0_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_6_cZ(.I0(un1_x_7_0[8:8]),.I1(un1_x_8_0[10:10]),.I2(un1_x_9_0[11:11]),.O(un84_sop_0_0_0_6_6_0_o5_6));
defparam un84_sop_0_0_0_6_6_0_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_5_cZ(.I0(un1_x_7_0[7:7]),.I1(un1_x_8_0[9:9]),.I2(un1_x_9_0[10:10]),.O(un84_sop_0_0_0_6_6_0_o5_5));
defparam un84_sop_0_0_0_6_6_0_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_4_cZ(.I0(un1_x_7_0[6:6]),.I1(un1_x_8_0[8:8]),.I2(un1_x_9_0[9:9]),.O(un84_sop_0_0_0_6_6_0_o5_4));
defparam un84_sop_0_0_0_6_6_0_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_3_cZ(.I0(un1_x_7_0[5:5]),.I1(un1_x_8_0[7:7]),.I2(un1_x_9_0[8:8]),.O(un84_sop_0_0_0_6_6_0_o5_3));
defparam un84_sop_0_0_0_6_6_0_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_2_cZ(.I0(un1_x_7_0[4:4]),.I1(un1_x_8_0[6:6]),.I2(un1_x_9_0[7:7]),.O(un84_sop_0_0_0_6_6_0_o5_2));
defparam un84_sop_0_0_0_6_6_0_o5_2_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_7_cZ(.I0(un84_sop_0_0_0_10_0[10:10]),.I1(x_4[5:5]),.I2(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_o5_7));
defparam un84_sop_0_0_0_1_6_8_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_6_cZ(.I0(un84_sop_0_0_0_10_0[9:9]),.I1(x_4[6:6]),.I2(x_4[4:4]),.O(un84_sop_0_0_0_1_6_8_o5_6));
defparam un84_sop_0_0_0_1_6_8_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_5_cZ(.I0(un84_sop_0_0_0_10_0[8:8]),.I1(x_4[3:3]),.I2(x_4[5:5]),.O(un84_sop_0_0_0_1_6_8_o5_5));
defparam un84_sop_0_0_0_1_6_8_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_4_cZ(.I0(un84_sop_0_0_0_10_0[7:7]),.I1(x_4[2:2]),.I2(x_4[4:4]),.O(un84_sop_0_0_0_1_6_8_o5_4));
defparam un84_sop_0_0_0_1_6_8_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_3_cZ(.I0(un84_sop_0_0_0_10_0[6:6]),.I1(x_4[1:1]),.I2(x_4[3:3]),.O(un84_sop_0_0_0_1_6_8_o5_3));
defparam un84_sop_0_0_0_1_6_8_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_11_cZ(.I0(un1_x_1[15:15]),.I1(un1_x_3[15:15]),.I2(un1_x_2[15:15]),.O(un84_sop_1_6_0_o5_11));
defparam un84_sop_1_6_0_o5_11_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_10_cZ(.I0(un1_x_1[14:14]),.I1(un1_x_3[14:14]),.I2(un1_x_2[15:15]),.O(un84_sop_1_6_0_o5_10));
defparam un84_sop_1_6_0_o5_10_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_9_cZ(.I0(un1_x_1[13:13]),.I1(un1_x_2[14:14]),.I2(un1_x_3[13:13]),.O(un84_sop_1_6_0_o5_9));
defparam un84_sop_1_6_0_o5_9_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_8_cZ(.I0(un1_x_1[12:12]),.I1(un1_x_2[13:13]),.I2(un1_x_3[12:12]),.O(un84_sop_1_6_0_o5_8));
defparam un84_sop_1_6_0_o5_8_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_7_cZ(.I0(un1_x_1[11:11]),.I1(un1_x_2[12:12]),.I2(un1_x_3[11:11]),.O(un84_sop_1_6_0_o5_7));
defparam un84_sop_1_6_0_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_6_cZ(.I0(un1_x_1[10:10]),.I1(un1_x_2[11:11]),.I2(un1_x_3[10:10]),.O(un84_sop_1_6_0_o5_6));
defparam un84_sop_1_6_0_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_5_cZ(.I0(un1_x_1[9:9]),.I1(un1_x_2[10:10]),.I2(un1_x_3[9:9]),.O(un84_sop_1_6_0_o5_5));
defparam un84_sop_1_6_0_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_4_cZ(.I0(un1_x_1[8:8]),.I1(un1_x_2[9:9]),.I2(un1_x_3[8:8]),.O(un84_sop_1_6_0_o5_4));
defparam un84_sop_1_6_0_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_3_cZ(.I0(un1_x_1[7:7]),.I1(un1_x_2[8:8]),.I2(un1_x_3[7:7]),.O(un84_sop_1_6_0_o5_3));
defparam un84_sop_1_6_0_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_2_cZ(.I0(un1_x_1[6:6]),.I1(un1_x_2[7:7]),.I2(un1_x_3[6:6]),.O(un84_sop_1_6_0_o5_2));
defparam un84_sop_1_6_0_o5_2_cZ.INIT=8'hE8;
LUT5 un84_sop_1_4_axb_3_cZ(.I0(x_0[3:3]),.I1(x_0[2:2]),.I2(x_0[1:1]),.I3(x_0[0:0]),.I4(un84_sop_1_7[3:3]),.O(un84_sop_1_4_axb_3));
defparam un84_sop_1_4_axb_3_cZ.INIT=32'hAAA95556;
LUT5 un1_x_10_5_ac0_7(.I0(x_8[4:4]),.I1(x_8[3:3]),.I2(x_8[2:2]),.I3(x_8[1:1]),.I4(x_8[0:0]),.O(un1_x_10_5_c5));
defparam un1_x_10_5_ac0_7.INIT=32'h00000001;
LUT5 un1_x_10_axb_6_cZ(.I0(x_8[3:3]),.I1(x_8[2:2]),.I2(x_8[1:1]),.I3(x_8[0:0]),.I4(un1_x_10_4[6:6]),.O(un1_x_10_axb_6));
defparam un1_x_10_axb_6_cZ.INIT=32'hAAA95556;
LUT6 un1_x_10_axb_7_cZ(.I0(x_8[4:4]),.I1(x_8[3:3]),.I2(x_8[2:2]),.I3(x_8[1:1]),.I4(x_8[0:0]),.I5(un1_x_10_4[7:7]),.O(un1_x_10_axb_7));
defparam un1_x_10_axb_7_cZ.INIT=64'hAAAAAAA955555556;
LUT5 un84_sop_1_4_axb_6_cZ(.I0(x_0[6:6]),.I1(x_0[5:5]),.I2(x_0[4:4]),.I3(un1_x_0_0_c4),.I4(un84_sop_1_7[6:6]),.O(un84_sop_1_4_axb_6));
defparam un84_sop_1_4_axb_6_cZ.INIT=32'hA9AA5655;
LUT6 un84_sop_1_4_axb_7_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[7:7]),.O(un84_sop_1_4_axb_7));
defparam un84_sop_1_4_axb_7_cZ.INIT=64'hAAA9AAAA55565555;
LUT6 un84_sop_1_4_axb_14_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[14:14]),.O(un84_sop_1_4_axb_14));
defparam un84_sop_1_4_axb_14_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_13_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[13:13]),.O(un84_sop_1_4_axb_13));
defparam un84_sop_1_4_axb_13_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_12_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[12:12]),.O(un84_sop_1_4_axb_12));
defparam un84_sop_1_4_axb_12_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_11_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[11:11]),.O(un84_sop_1_4_axb_11));
defparam un84_sop_1_4_axb_11_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_10_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[10:10]),.O(un84_sop_1_4_axb_10));
defparam un84_sop_1_4_axb_10_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_9_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[9:9]),.O(un84_sop_1_4_axb_9));
defparam un84_sop_1_4_axb_9_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_8_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[8:8]),.O(un84_sop_1_4_axb_8));
defparam un84_sop_1_4_axb_8_cZ.INIT=64'hAAABAAAA55545555;
LUT2 x_16_pipe_0_0_0_RNI0KBH(.I0(un84_sop_0_0_0_0_5[0:0]),.I1(un1_x_4[2:2]),.O(un84_sop_1_7[0:0]));
defparam x_16_pipe_0_0_0_RNI0KBH.INIT=4'h6;
XORCY un84_sop_0_0_0_1_s_9(.LI(un84_sop_0_0_0_1_axb_9),.CI(un84_sop_0_0_0_1_cry_8),.O(un84_sop_0_0_0_0_1[9:9]));
XORCY un84_sop_0_0_0_1_s_8(.LI(un84_sop_0_0_0_1_axb_8),.CI(un84_sop_0_0_0_1_cry_7),.O(un84_sop_0_0_0_0_1[8:8]));
MUXCY_L un84_sop_0_0_0_1_cry_8_cZ(.DI(un1_x_15_0_0_0[14:14]),.CI(un84_sop_0_0_0_1_cry_7),.S(un84_sop_0_0_0_1_axb_8),.LO(un84_sop_0_0_0_1_cry_8));
XORCY un84_sop_0_0_0_1_s_7(.LI(un84_sop_0_0_0_1_axb_7),.CI(un84_sop_0_0_0_1_cry_6),.O(un84_sop_0_0_0_0_1[7:7]));
MUXCY_L un84_sop_0_0_0_1_cry_7_cZ(.DI(un1_x_15_0_0_0[13:13]),.CI(un84_sop_0_0_0_1_cry_6),.S(un84_sop_0_0_0_1_axb_7),.LO(un84_sop_0_0_0_1_cry_7));
XORCY un84_sop_0_0_0_1_s_6(.LI(un84_sop_0_0_0_1_axb_6),.CI(un84_sop_0_0_0_1_cry_5),.O(un84_sop_0_0_0_0_1[6:6]));
MUXCY_L un84_sop_0_0_0_1_cry_6_cZ(.DI(un1_x_15_0_0_0[12:12]),.CI(un84_sop_0_0_0_1_cry_5),.S(un84_sop_0_0_0_1_axb_6),.LO(un84_sop_0_0_0_1_cry_6));
XORCY un84_sop_0_0_0_1_s_5(.LI(un84_sop_0_0_0_1_axb_5),.CI(un84_sop_0_0_0_1_cry_4),.O(un84_sop_0_0_0_0_1[5:5]));
MUXCY_L un84_sop_0_0_0_1_cry_5_cZ(.DI(un1_x_15_0_0_0[11:11]),.CI(un84_sop_0_0_0_1_cry_4),.S(un84_sop_0_0_0_1_axb_5),.LO(un84_sop_0_0_0_1_cry_5));
XORCY un84_sop_0_0_0_1_s_4(.LI(un84_sop_0_0_0_1_axb_4),.CI(un84_sop_0_0_0_1_cry_3),.O(un84_sop_0_0_0_0_1[4:4]));
MUXCY_L un84_sop_0_0_0_1_cry_4_cZ(.DI(un1_x_15_0_0_0[10:10]),.CI(un84_sop_0_0_0_1_cry_3),.S(un84_sop_0_0_0_1_axb_4),.LO(un84_sop_0_0_0_1_cry_4));
XORCY un84_sop_0_0_0_1_s_3(.LI(un84_sop_0_0_0_1_axb_3),.CI(un84_sop_0_0_0_1_cry_2),.O(un84_sop_0_0_0_0_1[3:3]));
MUXCY_L un84_sop_0_0_0_1_cry_3_cZ(.DI(un1_x_15_0_0_0[9:9]),.CI(un84_sop_0_0_0_1_cry_2),.S(un84_sop_0_0_0_1_axb_3),.LO(un84_sop_0_0_0_1_cry_3));
XORCY un84_sop_0_0_0_1_s_2(.LI(un84_sop_0_0_0_1_axb_2),.CI(un84_sop_0_0_0_1_cry_1),.O(un84_sop_0_0_0_0_1[2:2]));
MUXCY_L un84_sop_0_0_0_1_cry_2_cZ(.DI(un1_x_15_0_0_0[8:8]),.CI(un84_sop_0_0_0_1_cry_1),.S(un84_sop_0_0_0_1_axb_2),.LO(un84_sop_0_0_0_1_cry_2));
XORCY un84_sop_0_0_0_1_s_1(.LI(un84_sop_0_0_0_1_axb_1),.CI(un84_sop_0_0_0_1_cry_0),.O(un84_sop_0_0_0_0_1[1:1]));
MUXCY_L un84_sop_0_0_0_1_cry_1_cZ(.DI(un1_x_15_0_0_0[7:7]),.CI(un84_sop_0_0_0_1_cry_0),.S(un84_sop_0_0_0_1_axb_1),.LO(un84_sop_0_0_0_1_cry_1));
MUXCY_L un84_sop_0_0_0_1_cry_0_cZ(.DI(x_13[0:0]),.CI(GND),.S(un84_sop_0_0_0_0_1[0:0]),.LO(un84_sop_0_0_0_1_cry_0));
XORCY un1_x_16_0_s_8(.LI(un1_x_16_0_axb_8),.CI(un1_x_16_0_cry_7),.O(un1_x_16_0_0_0[14:14]));
XORCY un1_x_16_0_s_7(.LI(un1_x_16_0_axb_7),.CI(un1_x_16_0_cry_6),.O(un1_x_16_0_0_0[13:13]));
MUXCY_L un1_x_16_0_cry_7_cZ(.DI(GND),.CI(un1_x_16_0_cry_6),.S(un1_x_16_0_axb_7),.LO(un1_x_16_0_cry_7));
XORCY un1_x_16_0_s_6(.LI(un1_x_16_0_axb_6),.CI(un1_x_16_0_cry_5),.O(un1_x_16_0_0_0[12:12]));
MUXCY_L un1_x_16_0_cry_6_cZ(.DI(GND),.CI(un1_x_16_0_cry_5),.S(un1_x_16_0_axb_6),.LO(un1_x_16_0_cry_6));
XORCY un1_x_16_0_s_5(.LI(un1_x_16_0_axb_5),.CI(un1_x_16_0_cry_4),.O(un1_x_16_0_0_0[11:11]));
MUXCY_L un1_x_16_0_cry_5_cZ(.DI(GND),.CI(un1_x_16_0_cry_4),.S(un1_x_16_0_axb_5),.LO(un1_x_16_0_cry_5));
XORCY un1_x_16_0_s_4(.LI(un1_x_16_0_axb_4),.CI(un1_x_16_0_cry_3),.O(un1_x_16_0_0_0[10:10]));
MUXCY_L un1_x_16_0_cry_4_cZ(.DI(GND),.CI(un1_x_16_0_cry_3),.S(un1_x_16_0_axb_4),.LO(un1_x_16_0_cry_4));
XORCY un1_x_16_0_s_3(.LI(un1_x_16_0_axb_3),.CI(un1_x_16_0_cry_2),.O(un1_x_16_0_0_0[9:9]));
MUXCY_L un1_x_16_0_cry_3_cZ(.DI(GND),.CI(un1_x_16_0_cry_2),.S(un1_x_16_0_axb_3),.LO(un1_x_16_0_cry_3));
XORCY un1_x_16_0_s_2(.LI(un1_x_16_0_axb_2),.CI(un1_x_16_0_cry_1),.O(un1_x_16_0_0_0[8:8]));
MUXCY_L un1_x_16_0_cry_2_cZ(.DI(GND),.CI(un1_x_16_0_cry_1),.S(un1_x_16_0_axb_2),.LO(un1_x_16_0_cry_2));
XORCY un1_x_16_0_s_1(.LI(un1_x_16_0_axb_1),.CI(un1_x_16_0_cry_0),.O(un1_x_16_0_0_0[7:7]));
MUXCY_L un1_x_16_0_cry_1_cZ(.DI(GND),.CI(un1_x_16_0_cry_0),.S(un1_x_16_0_axb_1),.LO(un1_x_16_0_cry_1));
MUXCY_L un1_x_16_0_cry_0_cZ(.DI(GND),.CI(VCC),.S(un1_x_16_0_axb_0),.LO(un1_x_16_0_cry_0));
XORCY un1_x_11_0_s_8(.LI(un1_x_11_0_axb_8),.CI(un1_x_11_0_cry_7),.O(un1_x_11_0_0_0[14:14]));
XORCY un1_x_11_0_s_7(.LI(un1_x_11_0_axb_7),.CI(un1_x_11_0_cry_6),.O(un1_x_11_0_0_0[13:13]));
MUXCY_L un1_x_11_0_cry_7_cZ(.DI(GND),.CI(un1_x_11_0_cry_6),.S(un1_x_11_0_axb_7),.LO(un1_x_11_0_cry_7));
XORCY un1_x_11_0_s_6(.LI(un1_x_11_0_axb_6),.CI(un1_x_11_0_cry_5),.O(un1_x_11_0_0_0[12:12]));
MUXCY_L un1_x_11_0_cry_6_cZ(.DI(GND),.CI(un1_x_11_0_cry_5),.S(un1_x_11_0_axb_6),.LO(un1_x_11_0_cry_6));
XORCY un1_x_11_0_s_5(.LI(un1_x_11_0_axb_5),.CI(un1_x_11_0_cry_4),.O(un1_x_11_0_0_0[11:11]));
MUXCY_L un1_x_11_0_cry_5_cZ(.DI(GND),.CI(un1_x_11_0_cry_4),.S(un1_x_11_0_axb_5),.LO(un1_x_11_0_cry_5));
XORCY un1_x_11_0_s_4(.LI(un1_x_11_0_axb_4),.CI(un1_x_11_0_cry_3),.O(un1_x_11_0_0_0[10:10]));
MUXCY_L un1_x_11_0_cry_4_cZ(.DI(GND),.CI(un1_x_11_0_cry_3),.S(un1_x_11_0_axb_4),.LO(un1_x_11_0_cry_4));
XORCY un1_x_11_0_s_3(.LI(un1_x_11_0_axb_3),.CI(un1_x_11_0_cry_2),.O(un1_x_11_0_0_0[9:9]));
MUXCY_L un1_x_11_0_cry_3_cZ(.DI(GND),.CI(un1_x_11_0_cry_2),.S(un1_x_11_0_axb_3),.LO(un1_x_11_0_cry_3));
XORCY un1_x_11_0_s_2(.LI(un1_x_11_0_axb_2),.CI(un1_x_11_0_cry_1),.O(un1_x_11_0_0_0[8:8]));
MUXCY_L un1_x_11_0_cry_2_cZ(.DI(GND),.CI(un1_x_11_0_cry_1),.S(un1_x_11_0_axb_2),.LO(un1_x_11_0_cry_2));
XORCY un1_x_11_0_s_1(.LI(un1_x_11_0_axb_1),.CI(un1_x_11_0_cry_0),.O(un1_x_11_0_0_0[7:7]));
MUXCY_L un1_x_11_0_cry_1_cZ(.DI(GND),.CI(un1_x_11_0_cry_0),.S(un1_x_11_0_axb_1),.LO(un1_x_11_0_cry_1));
MUXCY_L un1_x_11_0_cry_0_cZ(.DI(GND),.CI(VCC),.S(un1_x_11_0_axb_0),.LO(un1_x_11_0_cry_0));
XORCY un1_x_15_0_s_8(.LI(un1_x_15_0_axb_8),.CI(un1_x_15_0_cry_7),.O(un1_x_15_0_0_0[14:14]));
XORCY un1_x_15_0_s_7(.LI(un1_x_15_0_axb_7),.CI(un1_x_15_0_cry_6),.O(un1_x_15_0_0_0[13:13]));
MUXCY_L un1_x_15_0_cry_7_cZ(.DI(GND),.CI(un1_x_15_0_cry_6),.S(un1_x_15_0_axb_7),.LO(un1_x_15_0_cry_7));
XORCY un1_x_15_0_s_6(.LI(un1_x_15_0_axb_6),.CI(un1_x_15_0_cry_5),.O(un1_x_15_0_0_0[12:12]));
MUXCY_L un1_x_15_0_cry_6_cZ(.DI(GND),.CI(un1_x_15_0_cry_5),.S(un1_x_15_0_axb_6),.LO(un1_x_15_0_cry_6));
XORCY un1_x_15_0_s_5(.LI(un1_x_15_0_axb_5),.CI(un1_x_15_0_cry_4),.O(un1_x_15_0_0_0[11:11]));
MUXCY_L un1_x_15_0_cry_5_cZ(.DI(GND),.CI(un1_x_15_0_cry_4),.S(un1_x_15_0_axb_5),.LO(un1_x_15_0_cry_5));
XORCY un1_x_15_0_s_4(.LI(un1_x_15_0_axb_4),.CI(un1_x_15_0_cry_3),.O(un1_x_15_0_0_0[10:10]));
MUXCY_L un1_x_15_0_cry_4_cZ(.DI(GND),.CI(un1_x_15_0_cry_3),.S(un1_x_15_0_axb_4),.LO(un1_x_15_0_cry_4));
XORCY un1_x_15_0_s_3(.LI(un1_x_15_0_axb_3),.CI(un1_x_15_0_cry_2),.O(un1_x_15_0_0_0[9:9]));
MUXCY_L un1_x_15_0_cry_3_cZ(.DI(GND),.CI(un1_x_15_0_cry_2),.S(un1_x_15_0_axb_3),.LO(un1_x_15_0_cry_3));
XORCY un1_x_15_0_s_2(.LI(un1_x_15_0_axb_2),.CI(un1_x_15_0_cry_1),.O(un1_x_15_0_0_0[8:8]));
MUXCY_L un1_x_15_0_cry_2_cZ(.DI(GND),.CI(un1_x_15_0_cry_1),.S(un1_x_15_0_axb_2),.LO(un1_x_15_0_cry_2));
XORCY un1_x_15_0_s_1(.LI(un1_x_15_0_axb_1),.CI(un1_x_15_0_cry_0),.O(un1_x_15_0_0_0[7:7]));
MUXCY_L un1_x_15_0_cry_1_cZ(.DI(GND),.CI(un1_x_15_0_cry_0),.S(un1_x_15_0_axb_1),.LO(un1_x_15_0_cry_1));
MUXCY_L un1_x_15_0_cry_0_cZ(.DI(GND),.CI(VCC),.S(un1_x_15_0_axb_0),.LO(un1_x_15_0_cry_0));
XORCY un1_x_10_4_s_8(.LI(un1_x_10_4_s_8_false),.CI(un1_x_10_4_cry_7),.O(un1_x_10_4[8:8]));
XORCY un1_x_10_4_s_7(.LI(un1_x_10_4_axb_7),.CI(un1_x_10_4_cry_6),.O(un1_x_10_4[7:7]));
MUXCY_L un1_x_10_4_cry_7_cZ(.DI(x_8[6:6]),.CI(un1_x_10_4_cry_6),.S(un1_x_10_4_axb_7),.LO(un1_x_10_4_cry_7));
XORCY un1_x_10_4_s_6(.LI(un1_x_10_4_axb_6),.CI(un1_x_10_4_cry_5),.O(un1_x_10_4[6:6]));
MUXCY_L un1_x_10_4_cry_6_cZ(.DI(x_8[5:5]),.CI(un1_x_10_4_cry_5),.S(un1_x_10_4_axb_6),.LO(un1_x_10_4_cry_6));
XORCY un1_x_10_4_s_5(.LI(un1_x_10_4_axb_5),.CI(un1_x_10_4_cry_4),.O(un1_x_10_4[5:5]));
MUXCY_L un1_x_10_4_cry_5_cZ(.DI(x_8[4:4]),.CI(un1_x_10_4_cry_4),.S(un1_x_10_4_axb_5),.LO(un1_x_10_4_cry_5));
XORCY un1_x_10_4_s_4(.LI(un1_x_10_4_axb_4),.CI(un1_x_10_4_cry_3),.O(un1_x_10_4[4:4]));
MUXCY_L un1_x_10_4_cry_4_cZ(.DI(x_8[3:3]),.CI(un1_x_10_4_cry_3),.S(un1_x_10_4_axb_4),.LO(un1_x_10_4_cry_4));
XORCY un1_x_10_4_s_3(.LI(un1_x_10_4_axb_3),.CI(un1_x_10_4_cry_2),.O(un1_x_10_4[3:3]));
MUXCY_L un1_x_10_4_cry_3_cZ(.DI(x_8[2:2]),.CI(un1_x_10_4_cry_2),.S(un1_x_10_4_axb_3),.LO(un1_x_10_4_cry_3));
XORCY un1_x_10_4_s_2(.LI(un1_x_10_4_axb_2),.CI(un1_x_10_4_cry_1),.O(un1_x_10_4[2:2]));
MUXCY_L un1_x_10_4_cry_2_cZ(.DI(x_8[1:1]),.CI(un1_x_10_4_cry_1),.S(un1_x_10_4_axb_2),.LO(un1_x_10_4_cry_2));
MUXCY_L un1_x_10_4_cry_1_cZ(.DI(x_8[0:0]),.CI(GND),.S(un1_x_10_4_cry_1_sf),.LO(un1_x_10_4_cry_1));
XORCY un84_sop_1_s_14_cZ(.LI(un84_sop_1_axb_14),.CI(un84_sop_1_cry_13),.O(un84_sop_1_s_14));
XORCY un84_sop_1_s_13_cZ(.LI(un84_sop_1_axb_13),.CI(un84_sop_1_cry_12),.O(un84_sop_1_s_13));
MUXCY_L un84_sop_1_cry_13_cZ(.DI(un84_sop_1_4[13:13]),.CI(un84_sop_1_cry_12),.S(un84_sop_1_axb_13),.LO(un84_sop_1_cry_13));
XORCY un84_sop_1_s_12_cZ(.LI(un84_sop_1_axb_12),.CI(un84_sop_1_cry_11),.O(un84_sop_1_s_12));
MUXCY_L un84_sop_1_cry_12_cZ(.DI(un84_sop_1_4[12:12]),.CI(un84_sop_1_cry_11),.S(un84_sop_1_axb_12),.LO(un84_sop_1_cry_12));
XORCY un84_sop_1_s_11_cZ(.LI(un84_sop_1_axb_11),.CI(un84_sop_1_cry_10),.O(un84_sop_1_s_11));
MUXCY_L un84_sop_1_cry_11_cZ(.DI(un84_sop_1_4[11:11]),.CI(un84_sop_1_cry_10),.S(un84_sop_1_axb_11),.LO(un84_sop_1_cry_11));
XORCY un84_sop_1_s_10_cZ(.LI(un84_sop_1_axb_10),.CI(un84_sop_1_cry_9),.O(un84_sop_1_s_10));
MUXCY_L un84_sop_1_cry_10_cZ(.DI(un84_sop_1_4[10:10]),.CI(un84_sop_1_cry_9),.S(un84_sop_1_axb_10),.LO(un84_sop_1_cry_10));
XORCY un84_sop_1_s_9_cZ(.LI(un84_sop_1_axb_9),.CI(un84_sop_1_cry_8),.O(un84_sop_1_s_9));
MUXCY_L un84_sop_1_cry_9_cZ(.DI(un84_sop_1_4[9:9]),.CI(un84_sop_1_cry_8),.S(un84_sop_1_axb_9),.LO(un84_sop_1_cry_9));
XORCY un84_sop_1_s_8_cZ(.LI(un84_sop_1_axb_8),.CI(un84_sop_1_cry_7),.O(un84_sop_1_s_8));
MUXCY_L un84_sop_1_cry_8_cZ(.DI(un84_sop_1_4[8:8]),.CI(un84_sop_1_cry_7),.S(un84_sop_1_axb_8),.LO(un84_sop_1_cry_8));
XORCY un84_sop_1_s_7_cZ(.LI(un84_sop_1_axb_7),.CI(un84_sop_1_cry_6),.O(un84_sop_1_s_7));
MUXCY_L un84_sop_1_cry_7_cZ(.DI(un84_sop_1_4[7:7]),.CI(un84_sop_1_cry_6),.S(un84_sop_1_axb_7),.LO(un84_sop_1_cry_7));
MUXCY_L un84_sop_1_cry_6_cZ(.DI(un84_sop_1_4[6:6]),.CI(un84_sop_1_cry_5),.S(un84_sop_1_axb_6),.LO(un84_sop_1_cry_6));
MUXCY_L un84_sop_1_cry_5_cZ(.DI(un84_sop_1_4[5:5]),.CI(un84_sop_1_cry_4),.S(un84_sop_1_axb_5),.LO(un84_sop_1_cry_5));
MUXCY_L un84_sop_1_cry_4_cZ(.DI(un84_sop_1_4[4:4]),.CI(un84_sop_1_cry_3),.S(un84_sop_1_axb_4),.LO(un84_sop_1_cry_4));
MUXCY_L un84_sop_1_cry_3_cZ(.DI(un84_sop_1_4[3:3]),.CI(un84_sop_1_cry_2),.S(un84_sop_1_axb_3),.LO(un84_sop_1_cry_3));
MUXCY_L un84_sop_1_cry_2_cZ(.DI(un84_sop_1_4[2:2]),.CI(un84_sop_1_cry_1),.S(un84_sop_1_axb_2),.LO(un84_sop_1_cry_2));
MUXCY_L un84_sop_1_cry_1_cZ(.DI(un84_sop_1_4[1:1]),.CI(un84_sop_1_cry_0),.S(un84_sop_1_axb_1),.LO(un84_sop_1_cry_1));
MUXCY_L un84_sop_1_cry_0_cZ(.DI(un84_sop_1_6[0:0]),.CI(GND),.S(un84_sop_1_axb_0),.LO(un84_sop_1_cry_0));
XORCY un84_sop_1_4_s_14(.LI(un84_sop_1_4_axb_14),.CI(un84_sop_1_4_cry_13),.O(un84_sop_1_4[14:14]));
XORCY un84_sop_1_4_s_13(.LI(un84_sop_1_4_axb_13),.CI(un84_sop_1_4_cry_12),.O(un84_sop_1_4[13:13]));
MUXCY_L un84_sop_1_4_cry_13_cZ(.DI(un84_sop_1_7[13:13]),.CI(un84_sop_1_4_cry_12),.S(un84_sop_1_4_axb_13),.LO(un84_sop_1_4_cry_13));
XORCY un84_sop_1_4_s_12(.LI(un84_sop_1_4_axb_12),.CI(un84_sop_1_4_cry_11),.O(un84_sop_1_4[12:12]));
MUXCY_L un84_sop_1_4_cry_12_cZ(.DI(un84_sop_1_7[12:12]),.CI(un84_sop_1_4_cry_11),.S(un84_sop_1_4_axb_12),.LO(un84_sop_1_4_cry_12));
XORCY un84_sop_1_4_s_11(.LI(un84_sop_1_4_axb_11),.CI(un84_sop_1_4_cry_10),.O(un84_sop_1_4[11:11]));
MUXCY_L un84_sop_1_4_cry_11_cZ(.DI(un84_sop_1_7[11:11]),.CI(un84_sop_1_4_cry_10),.S(un84_sop_1_4_axb_11),.LO(un84_sop_1_4_cry_11));
XORCY un84_sop_1_4_s_10(.LI(un84_sop_1_4_axb_10),.CI(un84_sop_1_4_cry_9),.O(un84_sop_1_4[10:10]));
MUXCY_L un84_sop_1_4_cry_10_cZ(.DI(un84_sop_1_7[10:10]),.CI(un84_sop_1_4_cry_9),.S(un84_sop_1_4_axb_10),.LO(un84_sop_1_4_cry_10));
XORCY un84_sop_1_4_s_9(.LI(un84_sop_1_4_axb_9),.CI(un84_sop_1_4_cry_8),.O(un84_sop_1_4[9:9]));
MUXCY_L un84_sop_1_4_cry_9_cZ(.DI(un84_sop_1_7[9:9]),.CI(un84_sop_1_4_cry_8),.S(un84_sop_1_4_axb_9),.LO(un84_sop_1_4_cry_9));
XORCY un84_sop_1_4_s_8(.LI(un84_sop_1_4_axb_8),.CI(un84_sop_1_4_cry_7),.O(un84_sop_1_4[8:8]));
MUXCY_L un84_sop_1_4_cry_8_cZ(.DI(un84_sop_1_7[8:8]),.CI(un84_sop_1_4_cry_7),.S(un84_sop_1_4_axb_8),.LO(un84_sop_1_4_cry_8));
XORCY un84_sop_1_4_s_7(.LI(un84_sop_1_4_axb_7),.CI(un84_sop_1_4_cry_6),.O(un84_sop_1_4[7:7]));
MUXCY_L un84_sop_1_4_cry_7_cZ(.DI(un84_sop_1_7[7:7]),.CI(un84_sop_1_4_cry_6),.S(un84_sop_1_4_axb_7),.LO(un84_sop_1_4_cry_7));
XORCY un84_sop_1_4_s_6(.LI(un84_sop_1_4_axb_6),.CI(un84_sop_1_4_cry_5),.O(un84_sop_1_4[6:6]));
MUXCY_L un84_sop_1_4_cry_6_cZ(.DI(un84_sop_1_7[6:6]),.CI(un84_sop_1_4_cry_5),.S(un84_sop_1_4_axb_6),.LO(un84_sop_1_4_cry_6));
XORCY un84_sop_1_4_s_5(.LI(un84_sop_1_4_axb_5),.CI(un84_sop_1_4_cry_4),.O(un84_sop_1_4[5:5]));
MUXCY_L un84_sop_1_4_cry_5_cZ(.DI(un84_sop_1_7[5:5]),.CI(un84_sop_1_4_cry_4),.S(un84_sop_1_4_axb_5),.LO(un84_sop_1_4_cry_5));
XORCY un84_sop_1_4_s_4(.LI(un84_sop_1_4_axb_4),.CI(un84_sop_1_4_cry_3),.O(un84_sop_1_4[4:4]));
MUXCY_L un84_sop_1_4_cry_4_cZ(.DI(un84_sop_1_7[4:4]),.CI(un84_sop_1_4_cry_3),.S(un84_sop_1_4_axb_4),.LO(un84_sop_1_4_cry_4));
XORCY un84_sop_1_4_s_3(.LI(un84_sop_1_4_axb_3),.CI(un84_sop_1_4_cry_2),.O(un84_sop_1_4[3:3]));
MUXCY_L un84_sop_1_4_cry_3_cZ(.DI(un84_sop_1_7[3:3]),.CI(un84_sop_1_4_cry_2),.S(un84_sop_1_4_axb_3),.LO(un84_sop_1_4_cry_3));
XORCY un84_sop_1_4_s_2(.LI(un84_sop_1_4_axb_2),.CI(un84_sop_1_4_cry_1),.O(un84_sop_1_4[2:2]));
MUXCY_L un84_sop_1_4_cry_2_cZ(.DI(un84_sop_1_7[2:2]),.CI(un84_sop_1_4_cry_1),.S(un84_sop_1_4_axb_2),.LO(un84_sop_1_4_cry_2));
XORCY un84_sop_1_4_s_1(.LI(un84_sop_1_4_axb_1),.CI(un84_sop_1_4_cry_0),.O(un84_sop_1_4[1:1]));
MUXCY_L un84_sop_1_4_cry_1_cZ(.DI(un84_sop_1_7[1:1]),.CI(un84_sop_1_4_cry_0),.S(un84_sop_1_4_axb_1),.LO(un84_sop_1_4_cry_1));
MUXCY_L un84_sop_1_4_cry_0_cZ(.DI(un84_sop_1_7[0:0]),.CI(GND),.S(un84_sop_1_4[0:0]),.LO(un84_sop_1_4_cry_0));
XORCY un84_sop_0_0_0_0_11_7_s_10(.LI(un84_sop_0_0_0_0_11_7_axb_10),.CI(un84_sop_0_0_0_0_11_7_cry_9),.O(un84_sop_0_0_0_0_11_7[14:14]));
XORCY un84_sop_0_0_0_0_11_7_s_9(.LI(un84_sop_0_0_0_0_11_7_axb_9),.CI(un84_sop_0_0_0_0_11_7_cry_8),.O(un84_sop_0_0_0_0_11_7[9:9]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_9_cZ(.DI(un84_sop_0_0_0_0_0[9:9]),.CI(un84_sop_0_0_0_0_11_7_cry_8),.S(un84_sop_0_0_0_0_11_7_axb_9),.LO(un84_sop_0_0_0_0_11_7_cry_9));
XORCY un84_sop_0_0_0_0_11_7_s_8(.LI(un84_sop_0_0_0_0_11_7_axb_8),.CI(un84_sop_0_0_0_0_11_7_cry_7),.O(un84_sop_0_0_0_0_11_7[8:8]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_8_cZ(.DI(un84_sop_0_0_0_0_0[8:8]),.CI(un84_sop_0_0_0_0_11_7_cry_7),.S(un84_sop_0_0_0_0_11_7_axb_8),.LO(un84_sop_0_0_0_0_11_7_cry_8));
XORCY un84_sop_0_0_0_0_11_7_s_7(.LI(un84_sop_0_0_0_0_11_7_axb_7),.CI(un84_sop_0_0_0_0_11_7_cry_6),.O(un84_sop_0_0_0_0_11_7[7:7]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_7_cZ(.DI(un84_sop_0_0_0_0_0[7:7]),.CI(un84_sop_0_0_0_0_11_7_cry_6),.S(un84_sop_0_0_0_0_11_7_axb_7),.LO(un84_sop_0_0_0_0_11_7_cry_7));
XORCY un84_sop_0_0_0_0_11_7_s_6(.LI(un84_sop_0_0_0_0_11_7_axb_6),.CI(un84_sop_0_0_0_0_11_7_cry_5),.O(un84_sop_0_0_0_0_11_7[6:6]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_6_cZ(.DI(un84_sop_0_0_0_0_0[6:6]),.CI(un84_sop_0_0_0_0_11_7_cry_5),.S(un84_sop_0_0_0_0_11_7_axb_6),.LO(un84_sop_0_0_0_0_11_7_cry_6));
XORCY un84_sop_0_0_0_0_11_7_s_5(.LI(un84_sop_0_0_0_0_11_7_axb_5),.CI(un84_sop_0_0_0_0_11_7_cry_4),.O(un84_sop_0_0_0_0_11_7[5:5]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_5_cZ(.DI(un84_sop_0_0_0_0_0[5:5]),.CI(un84_sop_0_0_0_0_11_7_cry_4),.S(un84_sop_0_0_0_0_11_7_axb_5),.LO(un84_sop_0_0_0_0_11_7_cry_5));
XORCY un84_sop_0_0_0_0_11_7_s_4(.LI(un84_sop_0_0_0_0_11_7_axb_4),.CI(un84_sop_0_0_0_0_11_7_cry_3),.O(un84_sop_0_0_0_0_11_7[4:4]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_4_cZ(.DI(un84_sop_0_0_0_0_0[4:4]),.CI(un84_sop_0_0_0_0_11_7_cry_3),.S(un84_sop_0_0_0_0_11_7_axb_4),.LO(un84_sop_0_0_0_0_11_7_cry_4));
XORCY un84_sop_0_0_0_0_11_7_s_3(.LI(un84_sop_0_0_0_0_11_7_axb_3),.CI(un84_sop_0_0_0_0_11_7_cry_2),.O(un84_sop_0_0_0_0_11_7[3:3]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_3_cZ(.DI(un84_sop_0_0_0_0_0[3:3]),.CI(un84_sop_0_0_0_0_11_7_cry_2),.S(un84_sop_0_0_0_0_11_7_axb_3),.LO(un84_sop_0_0_0_0_11_7_cry_3));
XORCY un84_sop_0_0_0_0_11_7_s_2(.LI(un84_sop_0_0_0_0_11_7_axb_2),.CI(un84_sop_0_0_0_0_11_7_cry_1),.O(un84_sop_0_0_0_0_11_7[2:2]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_2_cZ(.DI(un84_sop_0_0_0_0_0[2:2]),.CI(un84_sop_0_0_0_0_11_7_cry_1),.S(un84_sop_0_0_0_0_11_7_axb_2),.LO(un84_sop_0_0_0_0_11_7_cry_2));
XORCY un84_sop_0_0_0_0_11_7_s_1(.LI(un84_sop_0_0_0_0_11_7_axb_1),.CI(un84_sop_0_0_0_0_11_7_cry_0),.O(un84_sop_0_0_0_0_11_7[1:1]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_1_cZ(.DI(un84_sop_0_0_0_0_0[1:1]),.CI(un84_sop_0_0_0_0_11_7_cry_0),.S(un84_sop_0_0_0_0_11_7_axb_1),.LO(un84_sop_0_0_0_0_11_7_cry_1));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_0_cZ(.DI(un84_sop_0_0_0_0_0[0:0]),.CI(GND),.S(un84_sop_0_0_0_0_11_7[0:0]),.LO(un84_sop_0_0_0_0_11_7_cry_0));
XORCY un84_sop_1_7_s_14(.LI(un84_sop_1_7_axb_14),.CI(un84_sop_1_7_cry_13),.O(un84_sop_1_7[14:14]));
XORCY un84_sop_1_7_s_13(.LI(un84_sop_1_7_axb_13),.CI(un84_sop_1_7_cry_12),.O(un84_sop_1_7[13:13]));
MUXCY_L un84_sop_1_7_cry_13_cZ(.DI(un84_sop_0_0_0_0_5[13:13]),.CI(un84_sop_1_7_cry_12),.S(un84_sop_1_7_axb_13),.LO(un84_sop_1_7_cry_13));
XORCY un84_sop_1_7_s_12(.LI(un84_sop_1_7_axb_12),.CI(un84_sop_1_7_cry_11),.O(un84_sop_1_7[12:12]));
MUXCY_L un84_sop_1_7_cry_12_cZ(.DI(un84_sop_0_0_0_0_5[12:12]),.CI(un84_sop_1_7_cry_11),.S(un84_sop_1_7_axb_12),.LO(un84_sop_1_7_cry_12));
XORCY un84_sop_1_7_s_11(.LI(un84_sop_1_7_axb_11),.CI(un84_sop_1_7_cry_10),.O(un84_sop_1_7[11:11]));
MUXCY_L un84_sop_1_7_cry_11_cZ(.DI(un84_sop_0_0_0_0_5[11:11]),.CI(un84_sop_1_7_cry_10),.S(un84_sop_1_7_axb_11),.LO(un84_sop_1_7_cry_11));
XORCY un84_sop_1_7_s_10(.LI(un84_sop_1_7_axb_10),.CI(un84_sop_1_7_cry_9),.O(un84_sop_1_7[10:10]));
MUXCY_L un84_sop_1_7_cry_10_cZ(.DI(un84_sop_0_0_0_0_5[10:10]),.CI(un84_sop_1_7_cry_9),.S(un84_sop_1_7_axb_10),.LO(un84_sop_1_7_cry_10));
XORCY un84_sop_1_7_s_9(.LI(un84_sop_1_7_axb_9),.CI(un84_sop_1_7_cry_8),.O(un84_sop_1_7[9:9]));
MUXCY_L un84_sop_1_7_cry_9_cZ(.DI(un84_sop_0_0_0_0_5[9:9]),.CI(un84_sop_1_7_cry_8),.S(un84_sop_1_7_axb_9),.LO(un84_sop_1_7_cry_9));
XORCY un84_sop_1_7_s_8(.LI(un84_sop_1_7_axb_8),.CI(un84_sop_1_7_cry_7),.O(un84_sop_1_7[8:8]));
MUXCY_L un84_sop_1_7_cry_8_cZ(.DI(un84_sop_0_0_0_0_5[8:8]),.CI(un84_sop_1_7_cry_7),.S(un84_sop_1_7_axb_8),.LO(un84_sop_1_7_cry_8));
XORCY un84_sop_1_7_s_7(.LI(un84_sop_1_7_axb_7),.CI(un84_sop_1_7_cry_6),.O(un84_sop_1_7[7:7]));
MUXCY_L un84_sop_1_7_cry_7_cZ(.DI(un84_sop_0_0_0_0_5[7:7]),.CI(un84_sop_1_7_cry_6),.S(un84_sop_1_7_axb_7),.LO(un84_sop_1_7_cry_7));
XORCY un84_sop_1_7_s_6(.LI(un84_sop_1_7_axb_6),.CI(un84_sop_1_7_cry_5),.O(un84_sop_1_7[6:6]));
MUXCY_L un84_sop_1_7_cry_6_cZ(.DI(un84_sop_0_0_0_0_5[6:6]),.CI(un84_sop_1_7_cry_5),.S(un84_sop_1_7_axb_6),.LO(un84_sop_1_7_cry_6));
XORCY un84_sop_1_7_s_5(.LI(un84_sop_1_7_axb_5),.CI(un84_sop_1_7_cry_4),.O(un84_sop_1_7[5:5]));
MUXCY_L un84_sop_1_7_cry_5_cZ(.DI(un84_sop_0_0_0_0_5[5:5]),.CI(un84_sop_1_7_cry_4),.S(un84_sop_1_7_axb_5),.LO(un84_sop_1_7_cry_5));
XORCY un84_sop_1_7_s_4(.LI(un84_sop_1_7_axb_4),.CI(un84_sop_1_7_cry_3),.O(un84_sop_1_7[4:4]));
MUXCY_L un84_sop_1_7_cry_4_cZ(.DI(un84_sop_0_0_0_0_5[4:4]),.CI(un84_sop_1_7_cry_3),.S(un84_sop_1_7_axb_4),.LO(un84_sop_1_7_cry_4));
XORCY un84_sop_1_7_s_3(.LI(un84_sop_1_7_axb_3),.CI(un84_sop_1_7_cry_2),.O(un84_sop_1_7[3:3]));
MUXCY_L un84_sop_1_7_cry_3_cZ(.DI(un84_sop_0_0_0_0_5[3:3]),.CI(un84_sop_1_7_cry_2),.S(un84_sop_1_7_axb_3),.LO(un84_sop_1_7_cry_3));
XORCY un84_sop_1_7_s_2(.LI(un84_sop_1_7_axb_2),.CI(un84_sop_1_7_cry_1),.O(un84_sop_1_7[2:2]));
MUXCY_L un84_sop_1_7_cry_2_cZ(.DI(un84_sop_0_0_0_0_5[2:2]),.CI(un84_sop_1_7_cry_1),.S(un84_sop_1_7_axb_2),.LO(un84_sop_1_7_cry_2));
XORCY un84_sop_1_7_s_1(.LI(un84_sop_1_7_axb_1),.CI(un84_sop_1_7_cry_0),.O(un84_sop_1_7[1:1]));
MUXCY_L un84_sop_1_7_cry_1_cZ(.DI(un84_sop_0_0_0_0_5[1:1]),.CI(un84_sop_1_7_cry_0),.S(un84_sop_1_7_axb_1),.LO(un84_sop_1_7_cry_1));
MUXCY_L un84_sop_1_7_cry_0_cZ(.DI(un84_sop_0_0_0_0_5[0:0]),.CI(GND),.S(un84_sop_1_7[0:0]),.LO(un84_sop_1_7_cry_0));
XORCY un84_sop_0_0_0_1_6_s_14(.LI(un84_sop_0_0_0_1_6_axb_14),.CI(un84_sop_0_0_0_1_6_cry_13),.O(un84_sop_0_0_0_5_0[14:14]));
XORCY un84_sop_0_0_0_1_6_s_13(.LI(un84_sop_0_0_0_1_6_axb_13),.CI(un84_sop_0_0_0_1_6_cry_12),.O(un84_sop_0_0_0_5_0[13:13]));
MUXCY_L un84_sop_0_0_0_1_6_cry_13_cZ(.DI(un84_sop_0_0_0_1_6_4[13:13]),.CI(un84_sop_0_0_0_1_6_cry_12),.S(un84_sop_0_0_0_1_6_axb_13),.LO(un84_sop_0_0_0_1_6_cry_13));
XORCY un84_sop_0_0_0_1_6_s_12(.LI(un84_sop_0_0_0_1_6_axb_12),.CI(un84_sop_0_0_0_1_6_cry_11),.O(un84_sop_0_0_0_5_0[12:12]));
MUXCY_L un84_sop_0_0_0_1_6_cry_12_cZ(.DI(un84_sop_0_0_0_1_6_4[12:12]),.CI(un84_sop_0_0_0_1_6_cry_11),.S(un84_sop_0_0_0_1_6_axb_12),.LO(un84_sop_0_0_0_1_6_cry_12));
XORCY un84_sop_0_0_0_1_6_s_11(.LI(un84_sop_0_0_0_1_6_axb_11),.CI(un84_sop_0_0_0_1_6_cry_10),.O(un84_sop_0_0_0_5_0[11:11]));
MUXCY_L un84_sop_0_0_0_1_6_cry_11_cZ(.DI(un84_sop_0_0_0_1_6_4[11:11]),.CI(un84_sop_0_0_0_1_6_cry_10),.S(un84_sop_0_0_0_1_6_axb_11),.LO(un84_sop_0_0_0_1_6_cry_11));
XORCY un84_sop_0_0_0_1_6_s_10(.LI(un84_sop_0_0_0_1_6_axb_10),.CI(un84_sop_0_0_0_1_6_cry_9),.O(un84_sop_0_0_0_5_0[10:10]));
MUXCY_L un84_sop_0_0_0_1_6_cry_10_cZ(.DI(un84_sop_0_0_0_1_6_4[10:10]),.CI(un84_sop_0_0_0_1_6_cry_9),.S(un84_sop_0_0_0_1_6_axb_10),.LO(un84_sop_0_0_0_1_6_cry_10));
XORCY un84_sop_0_0_0_1_6_s_9(.LI(un84_sop_0_0_0_1_6_axb_9),.CI(un84_sop_0_0_0_1_6_cry_8),.O(un84_sop_0_0_0_5_0[9:9]));
MUXCY_L un84_sop_0_0_0_1_6_cry_9_cZ(.DI(un84_sop_0_0_0_1_6_4[9:9]),.CI(un84_sop_0_0_0_1_6_cry_8),.S(un84_sop_0_0_0_1_6_axb_9),.LO(un84_sop_0_0_0_1_6_cry_9));
XORCY un84_sop_0_0_0_1_6_s_8(.LI(un84_sop_0_0_0_1_6_axb_8),.CI(un84_sop_0_0_0_1_6_cry_7),.O(un84_sop_0_0_0_5_0[8:8]));
MUXCY_L un84_sop_0_0_0_1_6_cry_8_cZ(.DI(un84_sop_0_0_0_1_6_4[8:8]),.CI(un84_sop_0_0_0_1_6_cry_7),.S(un84_sop_0_0_0_1_6_axb_8),.LO(un84_sop_0_0_0_1_6_cry_8));
XORCY un84_sop_0_0_0_1_6_s_7(.LI(un84_sop_0_0_0_1_6_axb_7),.CI(un84_sop_0_0_0_1_6_cry_6),.O(un84_sop_0_0_0_5_0[7:7]));
MUXCY_L un84_sop_0_0_0_1_6_cry_7_cZ(.DI(un84_sop_0_0_0_1_6_4[7:7]),.CI(un84_sop_0_0_0_1_6_cry_6),.S(un84_sop_0_0_0_1_6_axb_7),.LO(un84_sop_0_0_0_1_6_cry_7));
XORCY un84_sop_0_0_0_1_6_s_6(.LI(un84_sop_0_0_0_1_6_axb_6),.CI(un84_sop_0_0_0_1_6_cry_5),.O(un84_sop_0_0_0_5_0[6:6]));
MUXCY_L un84_sop_0_0_0_1_6_cry_6_cZ(.DI(un84_sop_0_0_0_1_6_4[6:6]),.CI(un84_sop_0_0_0_1_6_cry_5),.S(un84_sop_0_0_0_1_6_axb_6),.LO(un84_sop_0_0_0_1_6_cry_6));
XORCY un84_sop_0_0_0_1_6_s_5(.LI(un84_sop_0_0_0_1_6_axb_5),.CI(un84_sop_0_0_0_1_6_cry_4),.O(un84_sop_0_0_0_5_0[5:5]));
MUXCY_L un84_sop_0_0_0_1_6_cry_5_cZ(.DI(un84_sop_0_0_0_1_6_4[5:5]),.CI(un84_sop_0_0_0_1_6_cry_4),.S(un84_sop_0_0_0_1_6_axb_5),.LO(un84_sop_0_0_0_1_6_cry_5));
XORCY un84_sop_0_0_0_1_6_s_4(.LI(un84_sop_0_0_0_1_6_axb_4),.CI(un84_sop_0_0_0_1_6_cry_3),.O(un84_sop_0_0_0_5_0[4:4]));
MUXCY_L un84_sop_0_0_0_1_6_cry_4_cZ(.DI(un84_sop_0_0_0_1_6_4[4:4]),.CI(un84_sop_0_0_0_1_6_cry_3),.S(un84_sop_0_0_0_1_6_axb_4),.LO(un84_sop_0_0_0_1_6_cry_4));
XORCY un84_sop_0_0_0_1_6_s_3(.LI(un84_sop_0_0_0_1_6_axb_3),.CI(un84_sop_0_0_0_1_6_cry_2),.O(un84_sop_0_0_0_5_0[3:3]));
MUXCY_L un84_sop_0_0_0_1_6_cry_3_cZ(.DI(un84_sop_0_0_0_1_6_4[3:3]),.CI(un84_sop_0_0_0_1_6_cry_2),.S(un84_sop_0_0_0_1_6_axb_3),.LO(un84_sop_0_0_0_1_6_cry_3));
XORCY un84_sop_0_0_0_1_6_s_2(.LI(un84_sop_0_0_0_1_6_axb_2),.CI(un84_sop_0_0_0_1_6_cry_1),.O(un84_sop_0_0_0_5_0[2:2]));
MUXCY_L un84_sop_0_0_0_1_6_cry_2_cZ(.DI(un84_sop_0_0_0_1_6_4[2:2]),.CI(un84_sop_0_0_0_1_6_cry_1),.S(un84_sop_0_0_0_1_6_axb_2),.LO(un84_sop_0_0_0_1_6_cry_2));
XORCY un84_sop_0_0_0_1_6_s_1(.LI(un84_sop_0_0_0_1_6_axb_1),.CI(un84_sop_0_0_0_1_6_cry_0),.O(un84_sop_0_0_0_5_0[1:1]));
MUXCY_L un84_sop_0_0_0_1_6_cry_1_cZ(.DI(un84_sop_0_0_0_1_6_4[1:1]),.CI(un84_sop_0_0_0_1_6_cry_0),.S(un84_sop_0_0_0_1_6_axb_1),.LO(un84_sop_0_0_0_1_6_cry_1));
MUXCY_L un84_sop_0_0_0_1_6_cry_0_cZ(.DI(un84_sop_0_0_0_1_6_6[0:0]),.CI(GND),.S(un84_sop_0_0_0_5_0[0:0]),.LO(un84_sop_0_0_0_1_6_cry_0));
XORCY un84_sop_0_0_0_1_6_4_s_14(.LI(un84_sop_0_0_0_1_6_4_axb_14),.CI(un84_sop_0_0_0_1_6_4_cry_13),.O(un84_sop_0_0_0_1_6_4[14:14]));
XORCY un84_sop_0_0_0_1_6_4_s_13(.LI(un84_sop_0_0_0_1_6_4_axb_13),.CI(un84_sop_0_0_0_1_6_4_cry_12),.O(un84_sop_0_0_0_1_6_4[13:13]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_13_cZ(.DI(un84_sop_0_0_0_1_6_8[13:13]),.CI(un84_sop_0_0_0_1_6_4_cry_12),.S(un84_sop_0_0_0_1_6_4_axb_13),.LO(un84_sop_0_0_0_1_6_4_cry_13));
XORCY un84_sop_0_0_0_1_6_4_s_12(.LI(un84_sop_0_0_0_1_6_4_axb_12),.CI(un84_sop_0_0_0_1_6_4_cry_11),.O(un84_sop_0_0_0_1_6_4[12:12]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_12_cZ(.DI(un84_sop_0_0_0_1_6_8[12:12]),.CI(un84_sop_0_0_0_1_6_4_cry_11),.S(un84_sop_0_0_0_1_6_4_axb_12),.LO(un84_sop_0_0_0_1_6_4_cry_12));
XORCY un84_sop_0_0_0_1_6_4_s_11(.LI(un84_sop_0_0_0_1_6_4_axb_11),.CI(un84_sop_0_0_0_1_6_4_cry_10),.O(un84_sop_0_0_0_1_6_4[11:11]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_11_cZ(.DI(un84_sop_0_0_0_1_6_8[11:11]),.CI(un84_sop_0_0_0_1_6_4_cry_10),.S(un84_sop_0_0_0_1_6_4_axb_11),.LO(un84_sop_0_0_0_1_6_4_cry_11));
XORCY un84_sop_0_0_0_1_6_4_s_10(.LI(un84_sop_0_0_0_1_6_4_axb_10),.CI(un84_sop_0_0_0_1_6_4_cry_9),.O(un84_sop_0_0_0_1_6_4[10:10]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_10_cZ(.DI(un84_sop_0_0_0_1_6_8[10:10]),.CI(un84_sop_0_0_0_1_6_4_cry_9),.S(un84_sop_0_0_0_1_6_4_axb_10),.LO(un84_sop_0_0_0_1_6_4_cry_10));
XORCY un84_sop_0_0_0_1_6_4_s_9(.LI(un84_sop_0_0_0_1_6_4_axb_9),.CI(un84_sop_0_0_0_1_6_4_cry_8),.O(un84_sop_0_0_0_1_6_4[9:9]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_9_cZ(.DI(un84_sop_0_0_0_1_6_8[9:9]),.CI(un84_sop_0_0_0_1_6_4_cry_8),.S(un84_sop_0_0_0_1_6_4_axb_9),.LO(un84_sop_0_0_0_1_6_4_cry_9));
XORCY un84_sop_0_0_0_1_6_4_s_8(.LI(un84_sop_0_0_0_1_6_4_axb_8),.CI(un84_sop_0_0_0_1_6_4_cry_7),.O(un84_sop_0_0_0_1_6_4[8:8]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_8_cZ(.DI(un84_sop_0_0_0_1_6_8[8:8]),.CI(un84_sop_0_0_0_1_6_4_cry_7),.S(un84_sop_0_0_0_1_6_4_axb_8),.LO(un84_sop_0_0_0_1_6_4_cry_8));
XORCY un84_sop_0_0_0_1_6_4_s_7(.LI(un84_sop_0_0_0_1_6_4_axb_7),.CI(un84_sop_0_0_0_1_6_4_cry_6),.O(un84_sop_0_0_0_1_6_4[7:7]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_7_cZ(.DI(un84_sop_0_0_0_1_6_8[7:7]),.CI(un84_sop_0_0_0_1_6_4_cry_6),.S(un84_sop_0_0_0_1_6_4_axb_7),.LO(un84_sop_0_0_0_1_6_4_cry_7));
XORCY un84_sop_0_0_0_1_6_4_s_6(.LI(un84_sop_0_0_0_1_6_4_axb_6),.CI(un84_sop_0_0_0_1_6_4_cry_5),.O(un84_sop_0_0_0_1_6_4[6:6]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_6_cZ(.DI(un84_sop_0_0_0_1_6_8[6:6]),.CI(un84_sop_0_0_0_1_6_4_cry_5),.S(un84_sop_0_0_0_1_6_4_axb_6),.LO(un84_sop_0_0_0_1_6_4_cry_6));
XORCY un84_sop_0_0_0_1_6_4_s_5(.LI(un84_sop_0_0_0_1_6_4_axb_5),.CI(un84_sop_0_0_0_1_6_4_cry_4),.O(un84_sop_0_0_0_1_6_4[5:5]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_5_cZ(.DI(un84_sop_0_0_0_1_6_8[5:5]),.CI(un84_sop_0_0_0_1_6_4_cry_4),.S(un84_sop_0_0_0_1_6_4_axb_5),.LO(un84_sop_0_0_0_1_6_4_cry_5));
XORCY un84_sop_0_0_0_1_6_4_s_4(.LI(un84_sop_0_0_0_1_6_4_axb_4),.CI(un84_sop_0_0_0_1_6_4_cry_3),.O(un84_sop_0_0_0_1_6_4[4:4]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_4_cZ(.DI(un84_sop_0_0_0_1_6_8[4:4]),.CI(un84_sop_0_0_0_1_6_4_cry_3),.S(un84_sop_0_0_0_1_6_4_axb_4),.LO(un84_sop_0_0_0_1_6_4_cry_4));
XORCY un84_sop_0_0_0_1_6_4_s_3(.LI(un84_sop_0_0_0_1_6_4_axb_3),.CI(un84_sop_0_0_0_1_6_4_cry_2),.O(un84_sop_0_0_0_1_6_4[3:3]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_3_cZ(.DI(un1_x_6_0[4:4]),.CI(un84_sop_0_0_0_1_6_4_cry_2),.S(un84_sop_0_0_0_1_6_4_axb_3),.LO(un84_sop_0_0_0_1_6_4_cry_3));
XORCY un84_sop_0_0_0_1_6_4_s_2(.LI(un84_sop_0_0_0_1_6_4_axb_2),.CI(un84_sop_0_0_0_1_6_4_cry_1),.O(un84_sop_0_0_0_1_6_4[2:2]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_2_cZ(.DI(un1_x_6_0[3:3]),.CI(un84_sop_0_0_0_1_6_4_cry_1),.S(un84_sop_0_0_0_1_6_4_axb_2),.LO(un84_sop_0_0_0_1_6_4_cry_2));
XORCY un84_sop_0_0_0_1_6_4_s_1(.LI(un84_sop_0_0_0_1_6_4_axb_1),.CI(un84_sop_0_0_0_1_6_4_cry_0),.O(un84_sop_0_0_0_1_6_4[1:1]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_1_cZ(.DI(un1_x_6_0[2:2]),.CI(un84_sop_0_0_0_1_6_4_cry_0),.S(un84_sop_0_0_0_1_6_4_axb_1),.LO(un84_sop_0_0_0_1_6_4_cry_1));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_0_cZ(.DI(un1_x_6_0[1:1]),.CI(GND),.S(un84_sop_0_0_0_1_6_4[0:0]),.LO(un84_sop_0_0_0_1_6_4_cry_0));
XORCY un1_x_10_s_11(.LI(un1_x_10_axb_11),.CI(un1_x_10_cry_10),.O(un1_x_10_0_0[15:15]));
XORCY un1_x_10_s_10(.LI(un1_x_10_axb_10),.CI(un1_x_10_cry_9),.O(un1_x_10_0_0[14:14]));
MUXCY_L un1_x_10_cry_10_cZ(.DI(un1_x_10_4[10:10]),.CI(un1_x_10_cry_9),.S(un1_x_10_axb_10),.LO(un1_x_10_cry_10));
XORCY un1_x_10_s_9(.LI(un1_x_10_axb_9),.CI(un1_x_10_cry_8),.O(un1_x_10_0_0[13:13]));
MUXCY_L un1_x_10_cry_9_cZ(.DI(un1_x_10_4[9:9]),.CI(un1_x_10_cry_8),.S(un1_x_10_axb_9),.LO(un1_x_10_cry_9));
XORCY un1_x_10_s_8(.LI(un1_x_10_axb_8),.CI(un1_x_10_cry_7),.O(un1_x_10_0_0[12:12]));
MUXCY_L un1_x_10_cry_8_cZ(.DI(un1_x_10_4[8:8]),.CI(un1_x_10_cry_7),.S(un1_x_10_axb_8),.LO(un1_x_10_cry_8));
XORCY un1_x_10_s_7(.LI(un1_x_10_axb_7),.CI(un1_x_10_cry_6),.O(un1_x_10_0_0[11:11]));
MUXCY_L un1_x_10_cry_7_cZ(.DI(un1_x_10_4[7:7]),.CI(un1_x_10_cry_6),.S(un1_x_10_axb_7),.LO(un1_x_10_cry_7));
XORCY un1_x_10_s_6(.LI(un1_x_10_axb_6),.CI(un1_x_10_cry_5),.O(un1_x_10_0_0[10:10]));
MUXCY_L un1_x_10_cry_6_cZ(.DI(un1_x_10_4[6:6]),.CI(un1_x_10_cry_5),.S(un1_x_10_axb_6),.LO(un1_x_10_cry_6));
XORCY un1_x_10_s_5(.LI(un1_x_10_axb_5),.CI(un1_x_10_cry_4),.O(un1_x_10_0_0[9:9]));
MUXCY_L un1_x_10_cry_5_cZ(.DI(un1_x_10_4[5:5]),.CI(un1_x_10_cry_4),.S(un1_x_10_axb_5),.LO(un1_x_10_cry_5));
XORCY un1_x_10_s_4(.LI(un1_x_10_axb_4),.CI(un1_x_10_cry_3),.O(un1_x_10_0_0[8:8]));
MUXCY_L un1_x_10_cry_4_cZ(.DI(un1_x_10_4[4:4]),.CI(un1_x_10_cry_3),.S(un1_x_10_axb_4),.LO(un1_x_10_cry_4));
MUXCY_L un1_x_10_cry_3_cZ(.DI(un1_x_10_4[3:3]),.CI(GND),.S(un1_x_10_axb_3),.LO(un1_x_10_cry_3));
XORCY un84_sop_1_6_0_s_13(.LI(un84_sop_1_6_0_axb_13),.CI(un84_sop_1_6_0_cry_12),.O(un84_sop_1_6[14:14]));
XORCY un84_sop_1_6_0_s_12(.LI(un84_sop_1_6_0_axb_12),.CI(un84_sop_1_6_0_cry_11),.O(un84_sop_1_6[12:12]));
MUXCY_L un84_sop_1_6_0_cry_12_cZ(.DI(un84_sop_1_6_0_o5_11),.CI(un84_sop_1_6_0_cry_11),.S(un84_sop_1_6_0_axb_12),.LO(un84_sop_1_6_0_cry_12));
XORCY un84_sop_1_6_0_s_11(.LI(un84_sop_1_6_0_axb_11),.CI(un84_sop_1_6_0_cry_10),.O(un84_sop_1_6[11:11]));
MUXCY_L un84_sop_1_6_0_cry_11_cZ(.DI(un84_sop_1_6_0_o5_10),.CI(un84_sop_1_6_0_cry_10),.S(un84_sop_1_6_0_axb_11),.LO(un84_sop_1_6_0_cry_11));
XORCY un84_sop_1_6_0_s_10(.LI(un84_sop_1_6_0_axb_10),.CI(un84_sop_1_6_0_cry_9),.O(un84_sop_1_6[10:10]));
MUXCY_L un84_sop_1_6_0_cry_10_cZ(.DI(un84_sop_1_6_0_o5_9),.CI(un84_sop_1_6_0_cry_9),.S(un84_sop_1_6_0_axb_10),.LO(un84_sop_1_6_0_cry_10));
XORCY un84_sop_1_6_0_s_9(.LI(un84_sop_1_6_0_axb_9),.CI(un84_sop_1_6_0_cry_8),.O(un84_sop_1_6[9:9]));
MUXCY_L un84_sop_1_6_0_cry_9_cZ(.DI(un84_sop_1_6_0_o5_8),.CI(un84_sop_1_6_0_cry_8),.S(un84_sop_1_6_0_axb_9),.LO(un84_sop_1_6_0_cry_9));
XORCY un84_sop_1_6_0_s_8(.LI(un84_sop_1_6_0_axb_8),.CI(un84_sop_1_6_0_cry_7),.O(un84_sop_1_6[8:8]));
MUXCY_L un84_sop_1_6_0_cry_8_cZ(.DI(un84_sop_1_6_0_o5_7),.CI(un84_sop_1_6_0_cry_7),.S(un84_sop_1_6_0_axb_8),.LO(un84_sop_1_6_0_cry_8));
XORCY un84_sop_1_6_0_s_7(.LI(un84_sop_1_6_0_axb_7),.CI(un84_sop_1_6_0_cry_6),.O(un84_sop_1_6[7:7]));
MUXCY_L un84_sop_1_6_0_cry_7_cZ(.DI(un84_sop_1_6_0_o5_6),.CI(un84_sop_1_6_0_cry_6),.S(un84_sop_1_6_0_axb_7),.LO(un84_sop_1_6_0_cry_7));
XORCY un84_sop_1_6_0_s_6(.LI(un84_sop_1_6_0_axb_6),.CI(un84_sop_1_6_0_cry_5),.O(un84_sop_1_6[6:6]));
MUXCY_L un84_sop_1_6_0_cry_6_cZ(.DI(un84_sop_1_6_0_o5_5),.CI(un84_sop_1_6_0_cry_5),.S(un84_sop_1_6_0_axb_6),.LO(un84_sop_1_6_0_cry_6));
XORCY un84_sop_1_6_0_s_5(.LI(un84_sop_1_6_0_axb_5),.CI(un84_sop_1_6_0_cry_4),.O(un84_sop_1_6[5:5]));
MUXCY_L un84_sop_1_6_0_cry_5_cZ(.DI(un84_sop_1_6_0_o5_4),.CI(un84_sop_1_6_0_cry_4),.S(un84_sop_1_6_0_axb_5),.LO(un84_sop_1_6_0_cry_5));
XORCY un84_sop_1_6_0_s_4(.LI(un84_sop_1_6_0_axb_4),.CI(un84_sop_1_6_0_cry_3),.O(un84_sop_1_6[4:4]));
MUXCY_L un84_sop_1_6_0_cry_4_cZ(.DI(un84_sop_1_6_0_o5_3),.CI(un84_sop_1_6_0_cry_3),.S(un84_sop_1_6_0_axb_4),.LO(un84_sop_1_6_0_cry_4));
XORCY un84_sop_1_6_0_s_3(.LI(un84_sop_1_6_0_axb_3),.CI(un84_sop_1_6_0_cry_2),.O(un84_sop_1_6[3:3]));
MUXCY_L un84_sop_1_6_0_cry_3_cZ(.DI(un84_sop_1_6_0_o5_2),.CI(un84_sop_1_6_0_cry_2),.S(un84_sop_1_6_0_axb_3),.LO(un84_sop_1_6_0_cry_3));
XORCY un84_sop_1_6_0_s_2(.LI(un84_sop_1_6_0_axb_2),.CI(un84_sop_1_6_0_cry_1),.O(un84_sop_1_6[2:2]));
MUXCY_L un84_sop_1_6_0_cry_2_cZ(.DI(un84_sop_1_6_0_axb_1_lut6_2_O5),.CI(un84_sop_1_6_0_cry_1),.S(un84_sop_1_6_0_axb_2),.LO(un84_sop_1_6_0_cry_2));
XORCY un84_sop_1_6_0_s_1(.LI(un84_sop_1_6_0_axb_1),.CI(un84_sop_1_6_0_cry_0),.O(un84_sop_1_6[1:1]));
MUXCY_L un84_sop_1_6_0_cry_1_cZ(.DI(GND),.CI(un84_sop_1_6_0_cry_0),.S(un84_sop_1_6_0_axb_1),.LO(un84_sop_1_6_0_cry_1));
MUXCY_L un84_sop_1_6_0_cry_0_cZ(.DI(un1_x_2[5:5]),.CI(un84_sop_1_6_0_cry_0_cy),.S(un84_sop_1_6_0_axb_0_0),.LO(un84_sop_1_6_0_cry_0));
XORCY un84_sop_0_0_0_1_6_8_s_11(.LI(un84_sop_0_0_0_1_6_8_axb_11),.CI(un84_sop_0_0_0_1_6_8_cry_10),.O(un84_sop_0_0_0_1_6_8[14:14]));
XORCY un84_sop_0_0_0_1_6_8_s_10(.LI(un84_sop_0_0_0_1_6_8_axb_10),.CI(un84_sop_0_0_0_1_6_8_cry_9),.O(un84_sop_0_0_0_1_6_8[13:13]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_10_cZ(.DI(un84_sop_0_0_0_10_0[13:13]),.CI(un84_sop_0_0_0_1_6_8_cry_9),.S(un84_sop_0_0_0_1_6_8_axb_10),.LO(un84_sop_0_0_0_1_6_8_cry_10));
XORCY un84_sop_0_0_0_1_6_8_s_9(.LI(un84_sop_0_0_0_1_6_8_axb_9),.CI(un84_sop_0_0_0_1_6_8_cry_8),.O(un84_sop_0_0_0_1_6_8[12:12]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_9_cZ(.DI(un84_sop_0_0_0_10_0[12:12]),.CI(un84_sop_0_0_0_1_6_8_cry_8),.S(un84_sop_0_0_0_1_6_8_axb_9),.LO(un84_sop_0_0_0_1_6_8_cry_9));
XORCY un84_sop_0_0_0_1_6_8_s_8(.LI(un84_sop_0_0_0_1_6_8_axb_8),.CI(un84_sop_0_0_0_1_6_8_cry_7),.O(un84_sop_0_0_0_1_6_8[11:11]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_8_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_7),.CI(un84_sop_0_0_0_1_6_8_cry_7),.S(un84_sop_0_0_0_1_6_8_axb_8),.LO(un84_sop_0_0_0_1_6_8_cry_8));
XORCY un84_sop_0_0_0_1_6_8_s_7(.LI(un84_sop_0_0_0_1_6_8_axb_7),.CI(un84_sop_0_0_0_1_6_8_cry_6),.O(un84_sop_0_0_0_1_6_8[10:10]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_7_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_6),.CI(un84_sop_0_0_0_1_6_8_cry_6),.S(un84_sop_0_0_0_1_6_8_axb_7),.LO(un84_sop_0_0_0_1_6_8_cry_7));
XORCY un84_sop_0_0_0_1_6_8_s_6(.LI(un84_sop_0_0_0_1_6_8_axb_6),.CI(un84_sop_0_0_0_1_6_8_cry_5),.O(un84_sop_0_0_0_1_6_8[9:9]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_6_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_5),.CI(un84_sop_0_0_0_1_6_8_cry_5),.S(un84_sop_0_0_0_1_6_8_axb_6),.LO(un84_sop_0_0_0_1_6_8_cry_6));
XORCY un84_sop_0_0_0_1_6_8_s_5(.LI(un84_sop_0_0_0_1_6_8_axb_5),.CI(un84_sop_0_0_0_1_6_8_cry_4),.O(un84_sop_0_0_0_1_6_8[8:8]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_5_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_4),.CI(un84_sop_0_0_0_1_6_8_cry_4),.S(un84_sop_0_0_0_1_6_8_axb_5),.LO(un84_sop_0_0_0_1_6_8_cry_5));
XORCY un84_sop_0_0_0_1_6_8_s_4(.LI(un84_sop_0_0_0_1_6_8_axb_4),.CI(un84_sop_0_0_0_1_6_8_cry_3),.O(un84_sop_0_0_0_1_6_8[7:7]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_4_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_3),.CI(un84_sop_0_0_0_1_6_8_cry_3),.S(un84_sop_0_0_0_1_6_8_axb_4),.LO(un84_sop_0_0_0_1_6_8_cry_4));
XORCY un84_sop_0_0_0_1_6_8_s_3(.LI(un84_sop_0_0_0_1_6_8_axb_3),.CI(un84_sop_0_0_0_1_6_8_cry_2),.O(un84_sop_0_0_0_1_6_8[6:6]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_3_cZ(.DI(un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5),.CI(un84_sop_0_0_0_1_6_8_cry_2),.S(un84_sop_0_0_0_1_6_8_axb_3),.LO(un84_sop_0_0_0_1_6_8_cry_3));
XORCY un84_sop_0_0_0_1_6_8_s_2(.LI(un84_sop_0_0_0_1_6_8_axb_2),.CI(un84_sop_0_0_0_1_6_8_cry_1),.O(un84_sop_0_0_0_1_6_8[5:5]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_2_cZ(.DI(GND),.CI(un84_sop_0_0_0_1_6_8_cry_1),.S(un84_sop_0_0_0_1_6_8_axb_2),.LO(un84_sop_0_0_0_1_6_8_cry_2));
XORCY un84_sop_0_0_0_1_6_8_s_1(.LI(un84_sop_0_0_0_1_6_8_axb_1),.CI(un84_sop_0_0_0_1_6_8_cry_0),.O(un84_sop_0_0_0_1_6_8[4:4]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_1_cZ(.DI(un84_sop_0_0_0_10_0[4:4]),.CI(un84_sop_0_0_0_1_6_8_cry_0),.S(un84_sop_0_0_0_1_6_8_axb_1),.LO(un84_sop_0_0_0_1_6_8_cry_1));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_0_cZ(.DI(un84_sop_0_0_0_10_0[3:3]),.CI(GND),.S(un84_sop_0_0_0_1_6_8[3:3]),.LO(un84_sop_0_0_0_1_6_8_cry_0));
XORCY un84_sop_0_0_0_6_6_0_s_14(.LI(un84_sop_0_0_0_6_6_0_axb_14),.CI(un84_sop_0_0_0_6_6_0_cry_13),.O(un84_sop_0_0_0_1_6_6[14:14]));
XORCY un84_sop_0_0_0_6_6_0_s_13(.LI(un84_sop_0_0_0_6_6_0_axb_13),.CI(un84_sop_0_0_0_6_6_0_cry_12),.O(un84_sop_0_0_0_1_6_6[13:13]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_13_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_12),.CI(un84_sop_0_0_0_6_6_0_cry_12),.S(un84_sop_0_0_0_6_6_0_axb_13),.LO(un84_sop_0_0_0_6_6_0_cry_13));
XORCY un84_sop_0_0_0_6_6_0_s_12(.LI(un84_sop_0_0_0_6_6_0_axb_12),.CI(un84_sop_0_0_0_6_6_0_cry_11),.O(un84_sop_0_0_0_1_6_6[12:12]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_12_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_11),.CI(un84_sop_0_0_0_6_6_0_cry_11),.S(un84_sop_0_0_0_6_6_0_axb_12),.LO(un84_sop_0_0_0_6_6_0_cry_12));
XORCY un84_sop_0_0_0_6_6_0_s_11(.LI(un84_sop_0_0_0_6_6_0_axb_11),.CI(un84_sop_0_0_0_6_6_0_cry_10),.O(un84_sop_0_0_0_1_6_6[11:11]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_11_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_10),.CI(un84_sop_0_0_0_6_6_0_cry_10),.S(un84_sop_0_0_0_6_6_0_axb_11),.LO(un84_sop_0_0_0_6_6_0_cry_11));
XORCY un84_sop_0_0_0_6_6_0_s_10(.LI(un84_sop_0_0_0_6_6_0_axb_10),.CI(un84_sop_0_0_0_6_6_0_cry_9),.O(un84_sop_0_0_0_1_6_6[10:10]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_10_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_9),.CI(un84_sop_0_0_0_6_6_0_cry_9),.S(un84_sop_0_0_0_6_6_0_axb_10),.LO(un84_sop_0_0_0_6_6_0_cry_10));
XORCY un84_sop_0_0_0_6_6_0_s_9(.LI(un84_sop_0_0_0_6_6_0_axb_9),.CI(un84_sop_0_0_0_6_6_0_cry_8),.O(un84_sop_0_0_0_1_6_6[9:9]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_9_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_8),.CI(un84_sop_0_0_0_6_6_0_cry_8),.S(un84_sop_0_0_0_6_6_0_axb_9),.LO(un84_sop_0_0_0_6_6_0_cry_9));
XORCY un84_sop_0_0_0_6_6_0_s_8(.LI(un84_sop_0_0_0_6_6_0_axb_8),.CI(un84_sop_0_0_0_6_6_0_cry_7),.O(un84_sop_0_0_0_1_6_6[8:8]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_8_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_7),.CI(un84_sop_0_0_0_6_6_0_cry_7),.S(un84_sop_0_0_0_6_6_0_axb_8),.LO(un84_sop_0_0_0_6_6_0_cry_8));
XORCY un84_sop_0_0_0_6_6_0_s_7(.LI(un84_sop_0_0_0_6_6_0_axb_7),.CI(un84_sop_0_0_0_6_6_0_cry_6),.O(un84_sop_0_0_0_1_6_6[7:7]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_7_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_6),.CI(un84_sop_0_0_0_6_6_0_cry_6),.S(un84_sop_0_0_0_6_6_0_axb_7),.LO(un84_sop_0_0_0_6_6_0_cry_7));
XORCY un84_sop_0_0_0_6_6_0_s_6(.LI(un84_sop_0_0_0_6_6_0_axb_6),.CI(un84_sop_0_0_0_6_6_0_cry_5),.O(un84_sop_0_0_0_1_6_6[6:6]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_6_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_5),.CI(un84_sop_0_0_0_6_6_0_cry_5),.S(un84_sop_0_0_0_6_6_0_axb_6),.LO(un84_sop_0_0_0_6_6_0_cry_6));
XORCY un84_sop_0_0_0_6_6_0_s_5(.LI(un84_sop_0_0_0_6_6_0_axb_5),.CI(un84_sop_0_0_0_6_6_0_cry_4),.O(un84_sop_0_0_0_1_6_6[5:5]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_5_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_4),.CI(un84_sop_0_0_0_6_6_0_cry_4),.S(un84_sop_0_0_0_6_6_0_axb_5),.LO(un84_sop_0_0_0_6_6_0_cry_5));
XORCY un84_sop_0_0_0_6_6_0_s_4(.LI(un84_sop_0_0_0_6_6_0_axb_4),.CI(un84_sop_0_0_0_6_6_0_cry_3),.O(un84_sop_0_0_0_1_6_6[4:4]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_4_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_3),.CI(un84_sop_0_0_0_6_6_0_cry_3),.S(un84_sop_0_0_0_6_6_0_axb_4),.LO(un84_sop_0_0_0_6_6_0_cry_4));
XORCY un84_sop_0_0_0_6_6_0_s_3(.LI(un84_sop_0_0_0_6_6_0_axb_3),.CI(un84_sop_0_0_0_6_6_0_cry_2),.O(un84_sop_0_0_0_1_6_6[3:3]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_3_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_2),.CI(un84_sop_0_0_0_6_6_0_cry_2),.S(un84_sop_0_0_0_6_6_0_axb_3),.LO(un84_sop_0_0_0_6_6_0_cry_3));
XORCY un84_sop_0_0_0_6_6_0_s_2(.LI(un84_sop_0_0_0_6_6_0_axb_2),.CI(un84_sop_0_0_0_6_6_0_cry_1),.O(un84_sop_0_0_0_1_6_6[2:2]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_2_cZ(.DI(un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5),.CI(un84_sop_0_0_0_6_6_0_cry_1),.S(un84_sop_0_0_0_6_6_0_axb_2),.LO(un84_sop_0_0_0_6_6_0_cry_2));
XORCY un84_sop_0_0_0_6_6_0_s_1(.LI(un84_sop_0_0_0_6_6_0_axb_1),.CI(un84_sop_0_0_0_6_6_0_cry_0),.O(un84_sop_0_0_0_1_6_6[1:1]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_1_cZ(.DI(GND),.CI(un84_sop_0_0_0_6_6_0_cry_0),.S(un84_sop_0_0_0_6_6_0_axb_1),.LO(un84_sop_0_0_0_6_6_0_cry_1));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_0_cZ(.DI(un1_x_8_0[4:4]),.CI(un84_sop_0_0_0_6_6_0_cry_0_cy),.S(un84_sop_0_0_0_6_0_axb_0_1),.LO(un84_sop_0_0_0_6_6_0_cry_0));
XORCY un84_sop_0_0_0_11_0_s_14(.LI(un84_sop_0_0_0_11_0_axb_14),.CI(un84_sop_0_0_0_11_0_cry_13),.O(un84_sop_0_0_0_0_8[14:14]));
XORCY un84_sop_0_0_0_11_0_s_13(.LI(un84_sop_0_0_0_11_0_axb_13),.CI(un84_sop_0_0_0_11_0_cry_12),.O(un84_sop_0_0_0_0_8[13:13]));
MUXCY_L un84_sop_0_0_0_11_0_cry_13_cZ(.DI(un84_sop_0_0_0_11_0_o5_12),.CI(un84_sop_0_0_0_11_0_cry_12),.S(un84_sop_0_0_0_11_0_axb_13),.LO(un84_sop_0_0_0_11_0_cry_13));
XORCY un84_sop_0_0_0_11_0_s_12(.LI(un84_sop_0_0_0_11_0_axb_12),.CI(un84_sop_0_0_0_11_0_cry_11),.O(un84_sop_0_0_0_0_8[12:12]));
MUXCY_L un84_sop_0_0_0_11_0_cry_12_cZ(.DI(un84_sop_0_0_0_11_0_o5_11),.CI(un84_sop_0_0_0_11_0_cry_11),.S(un84_sop_0_0_0_11_0_axb_12),.LO(un84_sop_0_0_0_11_0_cry_12));
XORCY un84_sop_0_0_0_11_0_s_11(.LI(un84_sop_0_0_0_11_0_axb_11),.CI(un84_sop_0_0_0_11_0_cry_10),.O(un84_sop_0_0_0_0_8[11:11]));
MUXCY_L un84_sop_0_0_0_11_0_cry_11_cZ(.DI(un84_sop_0_0_0_11_0_o5_10),.CI(un84_sop_0_0_0_11_0_cry_10),.S(un84_sop_0_0_0_11_0_axb_11),.LO(un84_sop_0_0_0_11_0_cry_11));
XORCY un84_sop_0_0_0_11_0_s_10(.LI(un84_sop_0_0_0_11_0_axb_10),.CI(un84_sop_0_0_0_11_0_cry_9),.O(un84_sop_0_0_0_0_8[10:10]));
MUXCY_L un84_sop_0_0_0_11_0_cry_10_cZ(.DI(un84_sop_0_0_0_11_0_o5_9),.CI(un84_sop_0_0_0_11_0_cry_9),.S(un84_sop_0_0_0_11_0_axb_10),.LO(un84_sop_0_0_0_11_0_cry_10));
XORCY un84_sop_0_0_0_11_0_s_9(.LI(un84_sop_0_0_0_11_0_axb_9),.CI(un84_sop_0_0_0_11_0_cry_8),.O(un84_sop_0_0_0_0_8[9:9]));
MUXCY_L un84_sop_0_0_0_11_0_cry_9_cZ(.DI(un84_sop_0_0_0_11_0_o5_8),.CI(un84_sop_0_0_0_11_0_cry_8),.S(un84_sop_0_0_0_11_0_axb_9),.LO(un84_sop_0_0_0_11_0_cry_9));
XORCY un84_sop_0_0_0_11_0_s_8(.LI(un84_sop_0_0_0_11_0_axb_8),.CI(un84_sop_0_0_0_11_0_cry_7),.O(un84_sop_0_0_0_0_8[8:8]));
MUXCY_L un84_sop_0_0_0_11_0_cry_8_cZ(.DI(un84_sop_0_0_0_11_0_o5_7),.CI(un84_sop_0_0_0_11_0_cry_7),.S(un84_sop_0_0_0_11_0_axb_8),.LO(un84_sop_0_0_0_11_0_cry_8));
XORCY un84_sop_0_0_0_11_0_s_7(.LI(un84_sop_0_0_0_11_0_axb_7),.CI(un84_sop_0_0_0_11_0_cry_6),.O(un84_sop_0_0_0_0_8[7:7]));
MUXCY_L un84_sop_0_0_0_11_0_cry_7_cZ(.DI(un84_sop_0_0_0_11_0_o5_6),.CI(un84_sop_0_0_0_11_0_cry_6),.S(un84_sop_0_0_0_11_0_axb_7),.LO(un84_sop_0_0_0_11_0_cry_7));
XORCY un84_sop_0_0_0_11_0_s_6(.LI(un84_sop_0_0_0_11_0_axb_6),.CI(un84_sop_0_0_0_11_0_cry_5),.O(un84_sop_0_0_0_0_8[6:6]));
MUXCY_L un84_sop_0_0_0_11_0_cry_6_cZ(.DI(un84_sop_0_0_0_11_0_o5_5),.CI(un84_sop_0_0_0_11_0_cry_5),.S(un84_sop_0_0_0_11_0_axb_6),.LO(un84_sop_0_0_0_11_0_cry_6));
XORCY un84_sop_0_0_0_11_0_s_5(.LI(un84_sop_0_0_0_11_0_axb_5),.CI(un84_sop_0_0_0_11_0_cry_4),.O(un84_sop_0_0_0_0_8[5:5]));
MUXCY_L un84_sop_0_0_0_11_0_cry_5_cZ(.DI(un84_sop_0_0_0_11_0_o5_4),.CI(un84_sop_0_0_0_11_0_cry_4),.S(un84_sop_0_0_0_11_0_axb_5),.LO(un84_sop_0_0_0_11_0_cry_5));
XORCY un84_sop_0_0_0_11_0_s_4(.LI(un84_sop_0_0_0_11_0_axb_4),.CI(un84_sop_0_0_0_11_0_cry_3),.O(un84_sop_0_0_0_0_8[4:4]));
MUXCY_L un84_sop_0_0_0_11_0_cry_4_cZ(.DI(un84_sop_0_0_0_11_0_o5_3),.CI(un84_sop_0_0_0_11_0_cry_3),.S(un84_sop_0_0_0_11_0_axb_4),.LO(un84_sop_0_0_0_11_0_cry_4));
XORCY un84_sop_0_0_0_11_0_s_3(.LI(un84_sop_0_0_0_11_0_axb_3),.CI(un84_sop_0_0_0_11_0_cry_2),.O(un84_sop_0_0_0_0_8[3:3]));
MUXCY_L un84_sop_0_0_0_11_0_cry_3_cZ(.DI(un84_sop_0_0_0_11_0_o5_2),.CI(un84_sop_0_0_0_11_0_cry_2),.S(un84_sop_0_0_0_11_0_axb_3),.LO(un84_sop_0_0_0_11_0_cry_3));
XORCY un84_sop_0_0_0_11_0_s_2(.LI(un84_sop_0_0_0_11_0_axb_2),.CI(un84_sop_0_0_0_11_0_cry_1),.O(un84_sop_0_0_0_0_8[2:2]));
MUXCY_L un84_sop_0_0_0_11_0_cry_2_cZ(.DI(un84_sop_0_0_0_11_0_cry_2_RNO),.CI(un84_sop_0_0_0_11_0_cry_1),.S(un84_sop_0_0_0_11_0_axb_2),.LO(un84_sop_0_0_0_11_0_cry_2));
XORCY un84_sop_0_0_0_11_0_s_1(.LI(un84_sop_0_0_0_11_0_axb_1),.CI(un84_sop_0_0_0_11_0_cry_0),.O(un84_sop_0_0_0_0_8[1:1]));
MUXCY_L un84_sop_0_0_0_11_0_cry_1_cZ(.DI(un84_sop_0_0_0_0_11_6[1:1]),.CI(un84_sop_0_0_0_11_0_cry_0),.S(un84_sop_0_0_0_11_0_axb_1),.LO(un84_sop_0_0_0_11_0_cry_1));
XORCY un84_sop_0_0_0_11_0_s_0(.LI(un84_sop_0_0_0_11_0_axb_0),.CI(un84_sop_0_0_0_11_0_cry_0_cy),.O(un84_sop_0_0_0_0_8[0:0]));
MUXCY_L un84_sop_0_0_0_11_0_cry_0_cZ(.DI(un84_sop_0_0_0_0_11_6[0:0]),.CI(un84_sop_0_0_0_11_0_cry_0_cy),.S(un84_sop_0_0_0_11_0_axb_0),.LO(un84_sop_0_0_0_11_0_cry_0));
XORCY un84_sop_0_0_0_11_6_0_s_13(.LI(un84_sop_0_0_0_11_6_0_axb_13),.CI(un84_sop_0_0_0_11_6_0_cry_12),.O(un84_sop_0_0_0_0_11_6[14:14]));
XORCY un84_sop_0_0_0_11_6_0_s_12(.LI(un84_sop_0_0_0_11_6_0_axb_12),.CI(un84_sop_0_0_0_11_6_0_cry_11),.O(un84_sop_0_0_0_0_11_6[12:12]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_12_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_11),.CI(un84_sop_0_0_0_11_6_0_cry_11),.S(un84_sop_0_0_0_11_6_0_axb_12),.LO(un84_sop_0_0_0_11_6_0_cry_12));
XORCY un84_sop_0_0_0_11_6_0_s_11(.LI(un84_sop_0_0_0_11_6_0_axb_11),.CI(un84_sop_0_0_0_11_6_0_cry_10),.O(un84_sop_0_0_0_0_11_6[11:11]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_11_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_10),.CI(un84_sop_0_0_0_11_6_0_cry_10),.S(un84_sop_0_0_0_11_6_0_axb_11),.LO(un84_sop_0_0_0_11_6_0_cry_11));
XORCY un84_sop_0_0_0_11_6_0_s_10(.LI(un84_sop_0_0_0_11_6_0_axb_10),.CI(un84_sop_0_0_0_11_6_0_cry_9),.O(un84_sop_0_0_0_0_11_6[10:10]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_10_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_9),.CI(un84_sop_0_0_0_11_6_0_cry_9),.S(un84_sop_0_0_0_11_6_0_axb_10),.LO(un84_sop_0_0_0_11_6_0_cry_10));
XORCY un84_sop_0_0_0_11_6_0_s_9(.LI(un84_sop_0_0_0_11_6_0_axb_9),.CI(un84_sop_0_0_0_11_6_0_cry_8),.O(un84_sop_0_0_0_0_11_6[9:9]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_9_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_8),.CI(un84_sop_0_0_0_11_6_0_cry_8),.S(un84_sop_0_0_0_11_6_0_axb_9),.LO(un84_sop_0_0_0_11_6_0_cry_9));
XORCY un84_sop_0_0_0_11_6_0_s_8(.LI(un84_sop_0_0_0_11_6_0_axb_8),.CI(un84_sop_0_0_0_11_6_0_cry_7),.O(un84_sop_0_0_0_0_11_6[8:8]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_8_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_7),.CI(un84_sop_0_0_0_11_6_0_cry_7),.S(un84_sop_0_0_0_11_6_0_axb_8),.LO(un84_sop_0_0_0_11_6_0_cry_8));
XORCY un84_sop_0_0_0_11_6_0_s_7(.LI(un84_sop_0_0_0_11_6_0_axb_7),.CI(un84_sop_0_0_0_11_6_0_cry_6),.O(un84_sop_0_0_0_0_11_6[7:7]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_7_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_6),.CI(un84_sop_0_0_0_11_6_0_cry_6),.S(un84_sop_0_0_0_11_6_0_axb_7),.LO(un84_sop_0_0_0_11_6_0_cry_7));
XORCY un84_sop_0_0_0_11_6_0_s_6(.LI(un84_sop_0_0_0_11_6_0_axb_6),.CI(un84_sop_0_0_0_11_6_0_cry_5),.O(un84_sop_0_0_0_0_11_6[6:6]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_6_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_5),.CI(un84_sop_0_0_0_11_6_0_cry_5),.S(un84_sop_0_0_0_11_6_0_axb_6),.LO(un84_sop_0_0_0_11_6_0_cry_6));
XORCY un84_sop_0_0_0_11_6_0_s_5(.LI(un84_sop_0_0_0_11_6_0_axb_5),.CI(un84_sop_0_0_0_11_6_0_cry_4),.O(un84_sop_0_0_0_0_11_6[5:5]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_5_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_4),.CI(un84_sop_0_0_0_11_6_0_cry_4),.S(un84_sop_0_0_0_11_6_0_axb_5),.LO(un84_sop_0_0_0_11_6_0_cry_5));
XORCY un84_sop_0_0_0_11_6_0_s_4(.LI(un84_sop_0_0_0_11_6_0_axb_4),.CI(un84_sop_0_0_0_11_6_0_cry_3),.O(un84_sop_0_0_0_0_11_6[4:4]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_4_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_3),.CI(un84_sop_0_0_0_11_6_0_cry_3),.S(un84_sop_0_0_0_11_6_0_axb_4),.LO(un84_sop_0_0_0_11_6_0_cry_4));
XORCY un84_sop_0_0_0_11_6_0_s_3(.LI(un84_sop_0_0_0_11_6_0_axb_3),.CI(un84_sop_0_0_0_11_6_0_cry_2),.O(un84_sop_0_0_0_0_11_6[3:3]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_3_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_2),.CI(un84_sop_0_0_0_11_6_0_cry_2),.S(un84_sop_0_0_0_11_6_0_axb_3),.LO(un84_sop_0_0_0_11_6_0_cry_3));
XORCY un84_sop_0_0_0_11_6_0_s_2(.LI(un84_sop_0_0_0_11_6_0_axb_2),.CI(un84_sop_0_0_0_11_6_0_cry_1),.O(un84_sop_0_0_0_0_11_6[2:2]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_2_cZ(.DI(un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5),.CI(un84_sop_0_0_0_11_6_0_cry_1),.S(un84_sop_0_0_0_11_6_0_axb_2),.LO(un84_sop_0_0_0_11_6_0_cry_2));
XORCY un84_sop_0_0_0_11_6_0_s_1(.LI(un84_sop_0_0_0_11_6_0_axb_1),.CI(un84_sop_0_0_0_11_6_0_cry_0),.O(un84_sop_0_0_0_0_11_6[1:1]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_1_cZ(.DI(GND),.CI(un84_sop_0_0_0_11_6_0_cry_0),.S(un84_sop_0_0_0_11_6_0_axb_1),.LO(un84_sop_0_0_0_11_6_0_cry_1));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_0_cZ(.DI(un1_x_13_0_0[5:5]),.CI(un84_sop_0_0_0_11_6_0_cry_0_cy),.S(un84_sop_0_0_0_6_0_axb_0_0),.LO(un84_sop_0_0_0_11_6_0_cry_0));
DSP48E1 desc57(.ACOUT(ACOUT[29:0]),.BCOUT({x_0_10[7:7],x_0_9[7:7],x_0_8[7:7],x_0_7[7:7],x_0_6[7:7],x_0_5[7:7],x_0_4[7:7],x_0_3[7:7],x_0_2[7:7],x_0_1[7:7],x_0_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT),.CARRYOUT(CARRYOUT[3:0]),.MULTSIGNOUT(MULTSIGNOUT),.OVERFLOW(OVERFLOW),.P({P_uc[47:12],un1_x_1[15:4]}),.PATTERNBDETECT(PATTERNBDETECT),.PATTERNDETECT(PATTERNDETECT),.PCOUT(PCOUT[47:0]),.UNDERFLOW(UNDERFLOW),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc57.ACASCREG=0;
defparam desc57.ADREG=0;
defparam desc57.ALUMODEREG=0;
defparam desc57.AREG=0;
defparam desc57.AUTORESET_PATDET="NO_RESET";
defparam desc57.A_INPUT="DIRECT";
defparam desc57.BCASCREG=1;
defparam desc57.BREG=1;
defparam desc57.B_INPUT="DIRECT";
defparam desc57.CARRYINREG=0;
defparam desc57.CARRYINSELREG=0;
defparam desc57.CREG=1;
defparam desc57.DREG=0;
defparam desc57.INMODEREG=0;
defparam desc57.MREG=0;
defparam desc57.OPMODEREG=0;
defparam desc57.PREG=1;
defparam desc57.USE_DPORT="FALSE";
defparam desc57.USE_MULT="MULTIPLY";
defparam desc57.USE_SIMD="ONE48";
DSP48E1 desc58(.ACOUT(ACOUT_0[29:0]),.BCOUT({x_9_10[7:7],x_9_9[7:7],x_9_8[7:7],x_9_7[7:7],x_9_6[7:7],x_9_5[7:7],x_9_4[7:7],x_9_3[7:7],x_9_2[7:7],x_9_1[7:7],x_9_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_0),.CARRYOUT(CARRYOUT_0[3:0]),.MULTSIGNOUT(MULTSIGNOUT_0),.OVERFLOW(OVERFLOW_0),.P({P_uc_0[47:12],un1_x_12_0_0[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_0),.PATTERNDETECT(PATTERNDETECT_0),.PCOUT(PCOUT_0[47:0]),.UNDERFLOW(UNDERFLOW_0),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc58.ACASCREG=2;
defparam desc58.ADREG=0;
defparam desc58.ALUMODEREG=0;
defparam desc58.AREG=2;
defparam desc58.AUTORESET_PATDET="NO_RESET";
defparam desc58.A_INPUT="DIRECT";
defparam desc58.BCASCREG=2;
defparam desc58.BREG=2;
defparam desc58.B_INPUT="DIRECT";
defparam desc58.CARRYINREG=0;
defparam desc58.CARRYINSELREG=0;
defparam desc58.CREG=1;
defparam desc58.DREG=0;
defparam desc58.INMODEREG=0;
defparam desc58.MREG=0;
defparam desc58.OPMODEREG=0;
defparam desc58.PREG=1;
defparam desc58.USE_DPORT="FALSE";
defparam desc58.USE_MULT="MULTIPLY";
defparam desc58.USE_SIMD="ONE48";
DSP48E1 desc59(.ACOUT(ACOUT_1[29:0]),.BCOUT(BCOUT_1[17:0]),.CARRYCASCOUT(CARRYCASCOUT_1),.CARRYOUT(CARRYOUT_1[3:0]),.MULTSIGNOUT(MULTSIGNOUT_1),.OVERFLOW(OVERFLOW_1),.P({P_uc_1[47:12],un1_x_14_0_0[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_1),.PATTERNDETECT(PATTERNDETECT_1),.PCOUT(PCOUT_1[47:0]),.UNDERFLOW(UNDERFLOW_1),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_10_10[7:7],x_10_9[7:7],x_10_8[7:7],x_10_7[7:7],x_10_6[7:7],x_10_5[7:7],x_10_4[7:7],x_10_3[7:7],x_10_2[7:7],x_10_1[7:7],x_10_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc59.ACASCREG=0;
defparam desc59.ADREG=0;
defparam desc59.ALUMODEREG=0;
defparam desc59.AREG=0;
defparam desc59.AUTORESET_PATDET="NO_RESET";
defparam desc59.A_INPUT="DIRECT";
defparam desc59.BCASCREG=1;
defparam desc59.BREG=1;
defparam desc59.B_INPUT="CASCADE";
defparam desc59.CARRYINREG=0;
defparam desc59.CARRYINSELREG=0;
defparam desc59.CREG=1;
defparam desc59.DREG=0;
defparam desc59.INMODEREG=0;
defparam desc59.MREG=0;
defparam desc59.OPMODEREG=0;
defparam desc59.PREG=1;
defparam desc59.USE_DPORT="FALSE";
defparam desc59.USE_MULT="MULTIPLY";
defparam desc59.USE_SIMD="ONE48";
DSP48E1 desc60(.ACOUT(ACOUT_2[29:0]),.BCOUT({x_2_10[7:7],x_2_9[7:7],x_2_8[7:7],x_2_7[7:7],x_2_6[7:7],x_2_5[7:7],x_2_4[7:7],x_2_3[7:7],x_2_2[7:7],x_2_1[7:7],x_2_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_2),.CARRYOUT(CARRYOUT_2[3:0]),.MULTSIGNOUT(MULTSIGNOUT_2),.OVERFLOW(OVERFLOW_2),.P({P_uc_2[47:12],un1_x_3[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_2),.PATTERNDETECT(PATTERNDETECT_2),.PCOUT(PCOUT_2[47:0]),.UNDERFLOW(UNDERFLOW_2),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_1_10[7:7],x_1_9[7:7],x_1_8[7:7],x_1_7[7:7],x_1_6[7:7],x_1_5[7:7],x_1_4[7:7],x_1_3[7:7],x_1_2[7:7],x_1_1[7:7],x_1_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc60.ACASCREG=0;
defparam desc60.ADREG=0;
defparam desc60.ALUMODEREG=0;
defparam desc60.AREG=0;
defparam desc60.AUTORESET_PATDET="NO_RESET";
defparam desc60.A_INPUT="DIRECT";
defparam desc60.BCASCREG=1;
defparam desc60.BREG=1;
defparam desc60.B_INPUT="CASCADE";
defparam desc60.CARRYINREG=0;
defparam desc60.CARRYINSELREG=0;
defparam desc60.CREG=1;
defparam desc60.DREG=0;
defparam desc60.INMODEREG=0;
defparam desc60.MREG=0;
defparam desc60.OPMODEREG=0;
defparam desc60.PREG=1;
defparam desc60.USE_DPORT="FALSE";
defparam desc60.USE_MULT="MULTIPLY";
defparam desc60.USE_SIMD="ONE48";
DSP48E1 desc61(.ACOUT(ACOUT_3[29:0]),.BCOUT({x_6_10[7:7],x_6_9[7:7],x_6_8[7:7],x_6_7[7:7],x_6_6[7:7],x_6_5[7:7],x_6_4[7:7],x_6_3[7:7],x_6_2[7:7],x_6_1[7:7],x_6_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_3),.CARRYOUT(CARRYOUT_3[3:0]),.MULTSIGNOUT(MULTSIGNOUT_3),.OVERFLOW(OVERFLOW_3),.P({P_uc_3[47:12],un1_x_8_0[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_3),.PATTERNDETECT(PATTERNDETECT_3),.PCOUT(PCOUT_3[47:0]),.UNDERFLOW(UNDERFLOW_3),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_5_10[7:7],x_5_9[7:7],x_5_8[7:7],x_5_7[7:7],x_5_6[7:7],x_5_5[7:7],x_5_4[7:7],x_5_3[7:7],x_5_2[7:7],x_5_1[7:7],x_5_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc61.ACASCREG=0;
defparam desc61.ADREG=0;
defparam desc61.ALUMODEREG=0;
defparam desc61.AREG=0;
defparam desc61.AUTORESET_PATDET="NO_RESET";
defparam desc61.A_INPUT="DIRECT";
defparam desc61.BCASCREG=1;
defparam desc61.BREG=1;
defparam desc61.B_INPUT="CASCADE";
defparam desc61.CARRYINREG=0;
defparam desc61.CARRYINSELREG=0;
defparam desc61.CREG=1;
defparam desc61.DREG=0;
defparam desc61.INMODEREG=0;
defparam desc61.MREG=0;
defparam desc61.OPMODEREG=0;
defparam desc61.PREG=1;
defparam desc61.USE_DPORT="FALSE";
defparam desc61.USE_MULT="MULTIPLY";
defparam desc61.USE_SIMD="ONE48";
DSP48E1 desc62(.ACOUT(ACOUT_4[29:0]),.BCOUT({x_4_10[7:7],x_4_9[7:7],x_4_8[7:7],x_4_7[7:7],x_4_6[7:7],x_4_5[7:7],x_4_4[7:7],x_4_3[7:7],x_4_2[7:7],x_4_1[7:7],x_4_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_4),.CARRYOUT(CARRYOUT_4[3:0]),.MULTSIGNOUT(MULTSIGNOUT_4),.OVERFLOW(OVERFLOW_4),.P({P_uc_4[47:15],un1_x_6_0[15:1]}),.PATTERNBDETECT(PATTERNBDETECT_4),.PATTERNDETECT(PATTERNDETECT_4),.PCOUT(PCOUT_4[47:0]),.UNDERFLOW(UNDERFLOW_4),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,GND,VCC,GND,GND,GND}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_3_10[7:7],x_3_9[7:7],x_3_8[7:7],x_3_7[7:7],x_3_6[7:7],x_3_5[7:7],x_3_4[7:7],x_3_3[7:7],x_3_2[7:7],x_3_1[7:7],x_3_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc62.ACASCREG=0;
defparam desc62.ADREG=0;
defparam desc62.ALUMODEREG=0;
defparam desc62.AREG=0;
defparam desc62.AUTORESET_PATDET="NO_RESET";
defparam desc62.A_INPUT="DIRECT";
defparam desc62.BCASCREG=1;
defparam desc62.BREG=1;
defparam desc62.B_INPUT="CASCADE";
defparam desc62.CARRYINREG=0;
defparam desc62.CARRYINSELREG=0;
defparam desc62.CREG=1;
defparam desc62.DREG=0;
defparam desc62.INMODEREG=0;
defparam desc62.MREG=0;
defparam desc62.OPMODEREG=0;
defparam desc62.PREG=1;
defparam desc62.USE_DPORT="FALSE";
defparam desc62.USE_MULT="MULTIPLY";
defparam desc62.USE_SIMD="ONE48";
DSP48E1 desc63(.ACOUT(ACOUT_5[29:0]),.BCOUT({x_3_10[7:7],x_3_9[7:7],x_3_8[7:7],x_3_7[7:7],x_3_6[7:7],x_3_5[7:7],x_3_4[7:7],x_3_3[7:7],x_3_2[7:7],x_3_1[7:7],x_3_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_5),.CARRYOUT(CARRYOUT_5[3:0]),.MULTSIGNOUT(MULTSIGNOUT_5),.OVERFLOW(OVERFLOW_5),.P({P_uc_5[47:15],P_uc_4[14:14],un1_x_4[15:2]}),.PATTERNBDETECT(PATTERNBDETECT_5),.PATTERNDETECT(PATTERNDETECT_5),.PCOUT(PCOUT_5[47:0]),.UNDERFLOW(UNDERFLOW_5),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,GND,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_2_10[7:7],x_2_9[7:7],x_2_8[7:7],x_2_7[7:7],x_2_6[7:7],x_2_5[7:7],x_2_4[7:7],x_2_3[7:7],x_2_2[7:7],x_2_1[7:7],x_2_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc63.ACASCREG=0;
defparam desc63.ADREG=0;
defparam desc63.ALUMODEREG=0;
defparam desc63.AREG=0;
defparam desc63.AUTORESET_PATDET="NO_RESET";
defparam desc63.A_INPUT="DIRECT";
defparam desc63.BCASCREG=1;
defparam desc63.BREG=1;
defparam desc63.B_INPUT="CASCADE";
defparam desc63.CARRYINREG=0;
defparam desc63.CARRYINSELREG=0;
defparam desc63.CREG=1;
defparam desc63.DREG=0;
defparam desc63.INMODEREG=0;
defparam desc63.MREG=0;
defparam desc63.OPMODEREG=0;
defparam desc63.PREG=1;
defparam desc63.USE_DPORT="FALSE";
defparam desc63.USE_MULT="MULTIPLY";
defparam desc63.USE_SIMD="ONE48";
DSP48E1 desc64(.ACOUT(ACOUT_6[29:0]),.BCOUT({x_5_10[7:7],x_5_9[7:7],x_5_8[7:7],x_5_7[7:7],x_5_6[7:7],x_5_5[7:7],x_5_4[7:7],x_5_3[7:7],x_5_2[7:7],x_5_1[7:7],x_5_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_6),.CARRYOUT(CARRYOUT_6[3:0]),.MULTSIGNOUT(MULTSIGNOUT_6),.OVERFLOW(OVERFLOW_6),.P({P_uc_6[47:15],P_uc_5[14:14],un1_x_7_0[15:2]}),.PATTERNBDETECT(PATTERNBDETECT_6),.PATTERNDETECT(PATTERNDETECT_6),.PCOUT(PCOUT_6[47:0]),.UNDERFLOW(UNDERFLOW_6),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,GND,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_4_10[7:7],x_4_9[7:7],x_4_8[7:7],x_4_7[7:7],x_4_6[7:7],x_4_5[7:7],x_4_4[7:7],x_4_3[7:7],x_4_2[7:7],x_4_1[7:7],x_4_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc64.ACASCREG=0;
defparam desc64.ADREG=0;
defparam desc64.ALUMODEREG=0;
defparam desc64.AREG=0;
defparam desc64.AUTORESET_PATDET="NO_RESET";
defparam desc64.A_INPUT="DIRECT";
defparam desc64.BCASCREG=1;
defparam desc64.BREG=1;
defparam desc64.B_INPUT="CASCADE";
defparam desc64.CARRYINREG=0;
defparam desc64.CARRYINSELREG=0;
defparam desc64.CREG=1;
defparam desc64.DREG=0;
defparam desc64.INMODEREG=0;
defparam desc64.MREG=0;
defparam desc64.OPMODEREG=0;
defparam desc64.PREG=1;
defparam desc64.USE_DPORT="FALSE";
defparam desc64.USE_MULT="MULTIPLY";
defparam desc64.USE_SIMD="ONE48";
DSP48E1 desc65(.ACOUT(ACOUT_7[29:0]),.BCOUT({x_10_10[7:7],x_10_9[7:7],x_10_8[7:7],x_10_7[7:7],x_10_6[7:7],x_10_5[7:7],x_10_4[7:7],x_10_3[7:7],x_10_2[7:7],x_10_1[7:7],x_10_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_7),.CARRYOUT(CARRYOUT_7[3:0]),.MULTSIGNOUT(MULTSIGNOUT_7),.OVERFLOW(OVERFLOW_7),.P({P_uc_7[47:15],P_uc_6[14:14],P_uc_4[13:12],P_uc[11:11],un1_x_13_0_0[15:5]}),.PATTERNBDETECT(PATTERNBDETECT_7),.PATTERNDETECT(PATTERNDETECT_7),.PCOUT(PCOUT_7[47:0]),.UNDERFLOW(UNDERFLOW_7),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_9_10[7:7],x_9_9[7:7],x_9_8[7:7],x_9_7[7:7],x_9_6[7:7],x_9_5[7:7],x_9_4[7:7],x_9_3[7:7],x_9_2[7:7],x_9_1[7:7],x_9_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc65.ACASCREG=0;
defparam desc65.ADREG=0;
defparam desc65.ALUMODEREG=0;
defparam desc65.AREG=0;
defparam desc65.AUTORESET_PATDET="NO_RESET";
defparam desc65.A_INPUT="DIRECT";
defparam desc65.BCASCREG=1;
defparam desc65.BREG=1;
defparam desc65.B_INPUT="CASCADE";
defparam desc65.CARRYINREG=0;
defparam desc65.CARRYINSELREG=0;
defparam desc65.CREG=1;
defparam desc65.DREG=0;
defparam desc65.INMODEREG=0;
defparam desc65.MREG=0;
defparam desc65.OPMODEREG=0;
defparam desc65.PREG=1;
defparam desc65.USE_DPORT="FALSE";
defparam desc65.USE_MULT="MULTIPLY";
defparam desc65.USE_SIMD="ONE48";
DSP48E1 desc66(.ACOUT(ACOUT_8[29:0]),.BCOUT({x_1_10[7:7],x_1_9[7:7],x_1_8[7:7],x_1_7[7:7],x_1_6[7:7],x_1_5[7:7],x_1_4[7:7],x_1_3[7:7],x_1_2[7:7],x_1_1[7:7],x_1_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_8),.CARRYOUT(CARRYOUT_8[3:0]),.MULTSIGNOUT(MULTSIGNOUT_8),.OVERFLOW(OVERFLOW_8),.P({P_uc_8[47:15],P_uc_7[14:14],P_uc_5[13:12],P_uc_0[11:11],un1_x_2[15:5]}),.PATTERNBDETECT(PATTERNBDETECT_8),.PATTERNDETECT(PATTERNDETECT_8),.PCOUT(PCOUT_8[47:0]),.UNDERFLOW(UNDERFLOW_8),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_0_10[7:7],x_0_9[7:7],x_0_8[7:7],x_0_7[7:7],x_0_6[7:7],x_0_5[7:7],x_0_4[7:7],x_0_3[7:7],x_0_2[7:7],x_0_1[7:7],x_0_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc66.ACASCREG=0;
defparam desc66.ADREG=0;
defparam desc66.ALUMODEREG=0;
defparam desc66.AREG=0;
defparam desc66.AUTORESET_PATDET="NO_RESET";
defparam desc66.A_INPUT="DIRECT";
defparam desc66.BCASCREG=1;
defparam desc66.BREG=1;
defparam desc66.B_INPUT="CASCADE";
defparam desc66.CARRYINREG=0;
defparam desc66.CARRYINSELREG=0;
defparam desc66.CREG=1;
defparam desc66.DREG=0;
defparam desc66.INMODEREG=0;
defparam desc66.MREG=0;
defparam desc66.OPMODEREG=0;
defparam desc66.PREG=1;
defparam desc66.USE_DPORT="FALSE";
defparam desc66.USE_MULT="MULTIPLY";
defparam desc66.USE_SIMD="ONE48";
DSP48E1 desc67(.ACOUT(ACOUT_9[29:0]),.BCOUT(BCOUT_9[17:0]),.CARRYCASCOUT(CARRYCASCOUT_9),.CARRYOUT(CARRYOUT_9[3:0]),.MULTSIGNOUT(MULTSIGNOUT_9),.OVERFLOW(OVERFLOW_9),.P({P_uc_9[47:15],P_uc_8[14:14],P_uc_6[13:12],P_uc_1[11:11],un1_x_9_0[15:5]}),.PATTERNBDETECT(PATTERNBDETECT_9),.PATTERNDETECT(PATTERNDETECT_9),.PCOUT(PCOUT_9[47:0]),.UNDERFLOW(UNDERFLOW_9),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_6_10[7:7],x_6_9[7:7],x_6_8[7:7],x_6_7[7:7],x_6_6[7:7],x_6_5[7:7],x_6_4[7:7],x_6_3[7:7],x_6_2[7:7],x_6_1[7:7],x_6_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc67.ACASCREG=0;
defparam desc67.ADREG=0;
defparam desc67.ALUMODEREG=0;
defparam desc67.AREG=0;
defparam desc67.AUTORESET_PATDET="NO_RESET";
defparam desc67.A_INPUT="DIRECT";
defparam desc67.BCASCREG=1;
defparam desc67.BREG=1;
defparam desc67.B_INPUT="CASCADE";
defparam desc67.CARRYINREG=0;
defparam desc67.CARRYINSELREG=0;
defparam desc67.CREG=1;
defparam desc67.DREG=0;
defparam desc67.INMODEREG=0;
defparam desc67.MREG=0;
defparam desc67.OPMODEREG=0;
defparam desc67.PREG=1;
defparam desc67.USE_DPORT="FALSE";
defparam desc67.USE_MULT="MULTIPLY";
defparam desc67.USE_SIMD="ONE48";
LUT3 un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o6(.I0(un1_x_12_0_0[5:5]),.I1(un1_x_13_0_0[6:6]),.I2(un1_x_14_0_0[5:5]),.O(un84_sop_0_0_0_11_6_0_axb_1));
defparam un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o6.INIT=8'h96;
LUT3 un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o5(.I0(un1_x_12_0_0[5:5]),.I1(un1_x_13_0_0[6:6]),.I2(un1_x_14_0_0[5:5]),.O(un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5));
defparam un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o5.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o6(.I0(un1_x_7_0[3:3]),.I1(un1_x_8_0[5:5]),.I2(un1_x_9_0[6:6]),.O(un84_sop_0_0_0_6_6_0_axb_1));
defparam un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o6.INIT=8'h96;
LUT3 un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o5(.I0(un1_x_7_0[3:3]),.I1(un1_x_8_0[5:5]),.I2(un1_x_9_0[6:6]),.O(un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5));
defparam un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o5.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o6(.I0(un84_sop_0_0_0_10_0[5:5]),.I1(x_4[0:0]),.I2(x_4[2:2]),.O(un84_sop_0_0_0_1_6_8_axb_2));
defparam un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o6.INIT=8'h96;
LUT3 un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o5(.I0(un84_sop_0_0_0_10_0[5:5]),.I1(x_4[0:0]),.I2(x_4[2:2]),.O(un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5));
defparam un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o5.INIT=8'hE8;
LUT3 un84_sop_1_6_0_axb_1_lut6_2_o6(.I0(un1_x_1[5:5]),.I1(un1_x_2[6:6]),.I2(un1_x_3[5:5]),.O(un84_sop_1_6_0_axb_1));
defparam un84_sop_1_6_0_axb_1_lut6_2_o6.INIT=8'h96;
LUT3 un84_sop_1_6_0_axb_1_lut6_2_o5(.I0(un1_x_1[5:5]),.I1(un1_x_2[6:6]),.I2(un1_x_3[5:5]),.O(un84_sop_1_6_0_axb_1_lut6_2_O5));
defparam un84_sop_1_6_0_axb_1_lut6_2_o5.INIT=8'hE8;
endmodule |
module mig_7series_v4_0_ddr_phy_wrcal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 2500,
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps
)
(
input clk,
input rst,
// Calibration status, control signals
input wrcal_start,
input wrcal_rd_wait,
input wrcal_sanity_chk,
input dqsfound_retry_done,
input phy_rddata_en,
output dqsfound_retry,
output wrcal_read_req,
output reg wrcal_act_req,
output reg wrcal_done,
output reg wrcal_pat_err,
output reg wrcal_prech_req,
output reg temp_wrcal_done,
output reg wrcal_sanity_chk_done,
input prech_done,
// Captured data in resync clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Write level values of Phaser_Out coarse and fine
// delay taps required to load Phaser_Out register
input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
input wrlvl_byte_done,
output reg wrlvl_byte_redo,
output reg early1_data,
output reg early2_data,
// DQ IDELAY
output reg idelay_ld,
output reg wrcal_pat_resume, // to phy_init for write
output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,
output phy_if_reset,
// Debug Port
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal
);
// Length of calibration sequence (in # of words)
//localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;
// # of reads for reliable read capture
localparam NUM_READS = 2;
// # of cycles to wait after changing RDEN count value
localparam RDEN_WAIT_CNT = 12;
localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;
localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;
localparam CAL2_IDLE = 4'h0;
localparam CAL2_READ_WAIT = 4'h1;
localparam CAL2_NEXT_DQS = 4'h2;
localparam CAL2_WRLVL_WAIT = 4'h3;
localparam CAL2_IFIFO_RESET = 4'h4;
localparam CAL2_DQ_IDEL_DEC = 4'h5;
localparam CAL2_DONE = 4'h6;
localparam CAL2_SANITY_WAIT = 4'h7;
localparam CAL2_ERR = 4'h8;
integer i,j,k,l,m,p,q,d;
reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w;
reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1];
reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w;
reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;
reg [4:0] not_empty_wait_cnt;
reg [3:0] tap_inc_wait_cnt;
reg cal2_done_r;
reg cal2_done_r1;
reg cal2_prech_req_r;
reg [3:0] cal2_state_r;
reg [3:0] cal2_state_r1;
reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1];
reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1];
reg cal2_if_reset;
reg wrcal_pat_resume_r;
reg wrcal_pat_resume_r1;
reg wrcal_pat_resume_r2;
reg wrcal_pat_resume_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg pat_data_match_r;
reg pat1_data_match_r;
reg pat1_data_match_r1;
reg pat2_data_match_r;
reg pat_data_match_valid_r;
wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;
reg pat1_match_rise0_and_r;
reg pat1_match_rise1_and_r;
reg pat1_match_fall0_and_r;
reg pat1_match_fall1_and_r;
reg pat2_match_rise0_and_r;
reg pat2_match_rise1_and_r;
reg pat2_match_fall0_and_r;
reg pat2_match_fall1_and_r;
reg early1_data_match_r;
reg early1_data_match_r1;
reg [DRAM_WIDTH-1:0] early1_match_fall0_r;
reg early1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall1_r;
reg early1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall2_r;
reg early1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall3_r;
reg early1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise0_r;
reg early1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise1_r;
reg early1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise2_r;
reg early1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise3_r;
reg early1_match_rise3_and_r;
reg early2_data_match_r;
reg [DRAM_WIDTH-1:0] early2_match_fall0_r;
reg early2_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall1_r;
reg early2_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall2_r;
reg early2_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall3_r;
reg early2_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise0_r;
reg early2_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise1_r;
reg early2_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise2_r;
reg early2_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise3_r;
reg early2_match_rise3_and_r;
wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg rd_active_posedge_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg rd_active_r5;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg wrlvl_byte_done_r;
reg idelay_ld_done;
reg pat1_detect;
reg early1_detect;
reg wrcal_sanity_chk_r;
reg wrcal_sanity_chk_err;
//***************************************************************************
// Debug
//***************************************************************************
always @(*) begin
for (d = 0; d < DQS_WIDTH; d = d + 1) begin
po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d];
po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d];
end
end
assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w;
assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w;
generate
if (nCK_PER_CLK == 4) begin: match_data_4
assign dbg_phy_wrcal[0] = pat_data_match_r;
end else begin:match_data_2
assign dbg_phy_wrcal[0] = 1'b0;
end
endgenerate
assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0];
assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err;
assign dbg_phy_wrcal[6] = wrcal_start;
assign dbg_phy_wrcal[7] = wrcal_done;
assign dbg_phy_wrcal[8] = pat_data_match_valid_r;
assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;
assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt;
assign dbg_phy_wrcal[22] = early1_data;
assign dbg_phy_wrcal[23] = early2_data;
assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r;
assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r;
assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r;
assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r;
generate
if (nCK_PER_CLK == 4) begin: mux_data_4
assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r;
assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r;
assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r;
assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r;
end else begin: mux_data_2
assign dbg_phy_wrcal[56+:8] = {8{1'b0}};
assign dbg_phy_wrcal[64+:8] = {8{1'b0}};
assign dbg_phy_wrcal[72+:8] = {8{1'b0}};
assign dbg_phy_wrcal[80+:8] = {8{1'b0}};
end
endgenerate
assign dbg_phy_wrcal[88] = early1_data_match_r;
assign dbg_phy_wrcal[89] = early2_data_match_r;
assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r;
assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r;
assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done;
assign dqsfound_retry = 1'b0;
assign wrcal_read_req = 1'b0;
assign phy_if_reset = cal2_if_reset;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
always @(posedge clk) begin
po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r;
wrlvl_byte_done_r <= #TCQ wrlvl_byte_done;
wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk;
end
//***************************************************************************
// Data mux to route appropriate byte to calibration logic - i.e. calibration
// is done sequentially, one byte (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
//**************************************************************************
// Final Phaser OUT coarse and fine delay taps after write calibration
// Sum of taps used during write leveling taps and write calibration
//**************************************************************************
always @(*) begin
for (m = 0; m < DQS_WIDTH; m = m + 1) begin
wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];
wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6];
end
end
always @(posedge clk) begin
if (rst) begin
for (p = 0; p < DQS_WIDTH; p = p + 1) begin
po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}};
po_fine_tap_cnt[p] <= #TCQ {6{1'b0}};
end
end else if (cal2_done_r && ~cal2_done_r1) begin
for (q = 0; q < DQS_WIDTH; q = q + 1) begin
po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i];
po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i];
end
end
end
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end
endgenerate
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
wrcal_prech_req <= #TCQ 1'b0;
else
// Combine requests from all stages here
wrcal_prech_req <= #TCQ cal2_prech_req_r;
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
end
end
end
endgenerate
//***************************************************************************
// Write calibration:
// During write leveling DQS is aligned to the nearest CK edge that may not
// be the correct CK edge. Write calibration is required to align the DQS to
// the correct CK edge that clocks the write command.
// The Phaser_Out coarse delay line is adjusted if required to add a memory
// clock cycle of delay in order to read back the expected pattern.
//***************************************************************************
always @(posedge clk) begin
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
rd_active_r5 <= #TCQ rd_active_r4;
end
//*****************************************************************
// Expected data pattern when properly received by read capture
// logic:
// Based on pattern of ({rise,fall}) =
// 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
// Each nibble will look like:
// bit3: 1, 0, 1, 0, 0, 1, 1, 0
// bit2: 1, 0, 0, 1, 1, 0, 0, 1
// bit1: 1, 0, 1, 0, 0, 1, 0, 1
// bit0: 1, 0, 0, 1, 1, 0, 1, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// FF00AA5555AA9966
assign pat_rise0[3] = 1'b1;
assign pat_fall0[3] = 1'b0;
assign pat_rise1[3] = 1'b1;
assign pat_fall1[3] = 1'b0;
assign pat_rise2[3] = 1'b0;
assign pat_fall2[3] = 1'b1;
assign pat_rise3[3] = 1'b1;
assign pat_fall3[3] = 1'b0;
assign pat_rise0[2] = 1'b1;
assign pat_fall0[2] = 1'b0;
assign pat_rise1[2] = 1'b0;
assign pat_fall1[2] = 1'b1;
assign pat_rise2[2] = 1'b1;
assign pat_fall2[2] = 1'b0;
assign pat_rise3[2] = 1'b0;
assign pat_fall3[2] = 1'b1;
assign pat_rise0[1] = 1'b1;
assign pat_fall0[1] = 1'b0;
assign pat_rise1[1] = 1'b1;
assign pat_fall1[1] = 1'b0;
assign pat_rise2[1] = 1'b0;
assign pat_fall2[1] = 1'b1;
assign pat_rise3[1] = 1'b0;
assign pat_fall3[1] = 1'b1;
assign pat_rise0[0] = 1'b1;
assign pat_fall0[0] = 1'b0;
assign pat_rise1[0] = 1'b0;
assign pat_fall1[0] = 1'b1;
assign pat_rise2[0] = 1'b1;
assign pat_fall2[0] = 1'b0;
assign pat_rise3[0] = 1'b1;
assign pat_fall3[0] = 1'b0;
// Pattern to distinguish between early write and incorrect read
// BB11EE4444EEDD88
assign early_rise0[3] = 1'b1;
assign early_fall0[3] = 1'b0;
assign early_rise1[3] = 1'b1;
assign early_fall1[3] = 1'b0;
assign early_rise2[3] = 1'b0;
assign early_fall2[3] = 1'b1;
assign early_rise3[3] = 1'b1;
assign early_fall3[3] = 1'b1;
assign early_rise0[2] = 1'b0;
assign early_fall0[2] = 1'b0;
assign early_rise1[2] = 1'b1;
assign early_fall1[2] = 1'b1;
assign early_rise2[2] = 1'b1;
assign early_fall2[2] = 1'b1;
assign early_rise3[2] = 1'b1;
assign early_fall3[2] = 1'b0;
assign early_rise0[1] = 1'b1;
assign early_fall0[1] = 1'b0;
assign early_rise1[1] = 1'b1;
assign early_fall1[1] = 1'b0;
assign early_rise2[1] = 1'b0;
assign early_fall2[1] = 1'b1;
assign early_rise3[1] = 1'b0;
assign early_fall3[1] = 1'b0;
assign early_rise0[0] = 1'b1;
assign early_fall0[0] = 1'b1;
assign early_rise1[0] = 1'b0;
assign early_fall1[0] = 1'b0;
assign early_rise2[0] = 1'b0;
assign early_fall2[0] = 1'b0;
assign early_rise3[0] = 1'b1;
assign early_fall3[0] = 1'b0;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// First cycle pattern FF00AA55
assign pat1_rise0[3] = 1'b1;
assign pat1_fall0[3] = 1'b0;
assign pat1_rise1[3] = 1'b1;
assign pat1_fall1[3] = 1'b0;
assign pat1_rise0[2] = 1'b1;
assign pat1_fall0[2] = 1'b0;
assign pat1_rise1[2] = 1'b0;
assign pat1_fall1[2] = 1'b1;
assign pat1_rise0[1] = 1'b1;
assign pat1_fall0[1] = 1'b0;
assign pat1_rise1[1] = 1'b1;
assign pat1_fall1[1] = 1'b0;
assign pat1_rise0[0] = 1'b1;
assign pat1_fall0[0] = 1'b0;
assign pat1_rise1[0] = 1'b0;
assign pat1_fall1[0] = 1'b1;
// Second cycle pattern 55AA9966
assign pat2_rise0[3] = 1'b0;
assign pat2_fall0[3] = 1'b1;
assign pat2_rise1[3] = 1'b1;
assign pat2_fall1[3] = 1'b0;
assign pat2_rise0[2] = 1'b1;
assign pat2_fall0[2] = 1'b0;
assign pat2_rise1[2] = 1'b0;
assign pat2_fall1[2] = 1'b1;
assign pat2_rise0[1] = 1'b0;
assign pat2_fall0[1] = 1'b1;
assign pat2_rise1[1] = 1'b0;
assign pat2_fall1[1] = 1'b1;
assign pat2_rise0[0] = 1'b1;
assign pat2_fall0[0] = 1'b0;
assign pat2_rise1[0] = 1'b1;
assign pat2_fall1[0] = 1'b0;
//Pattern to distinguish between early write and incorrect read
// First cycle pattern AA5555AA
assign early1_rise0[3] = 2'b1;
assign early1_fall0[3] = 2'b0;
assign early1_rise1[3] = 2'b0;
assign early1_fall1[3] = 2'b1;
assign early1_rise0[2] = 2'b0;
assign early1_fall0[2] = 2'b1;
assign early1_rise1[2] = 2'b1;
assign early1_fall1[2] = 2'b0;
assign early1_rise0[1] = 2'b1;
assign early1_fall0[1] = 2'b0;
assign early1_rise1[1] = 2'b0;
assign early1_fall1[1] = 2'b1;
assign early1_rise0[0] = 2'b0;
assign early1_fall0[0] = 2'b1;
assign early1_rise1[0] = 2'b1;
assign early1_fall1[0] = 2'b0;
// Second cycle pattern 9966BB11
assign early2_rise0[3] = 2'b1;
assign early2_fall0[3] = 2'b0;
assign early2_rise1[3] = 2'b1;
assign early2_fall1[3] = 2'b0;
assign early2_rise0[2] = 2'b0;
assign early2_fall0[2] = 2'b1;
assign early2_rise1[2] = 2'b0;
assign early2_fall1[2] = 2'b0;
assign early2_rise0[1] = 2'b0;
assign early2_fall0[1] = 2'b1;
assign early2_rise1[1] = 2'b1;
assign early2_fall1[1] = 2'b0;
assign early2_rise0[0] = 2'b1;
assign early2_fall0[0] = 2'b0;
assign early2_rise1[0] = 2'b1;
assign early2_fall1[0] = 2'b1;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4])
pat_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4])
pat_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4])
pat_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4])
pat_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4])
pat_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4])
pat_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4])
pat_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4])
pat_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4])
early1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4])
early1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise0[pt_i%4])
early1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall0[pt_i%4])
early1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == early_rise0[pt_i%4])
early2_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == early_fall0[pt_i%4])
early2_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise1[pt_i%4])
early2_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall1[pt_i%4])
early2_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (pat_match_rise0_and_r &&
pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r3;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r;
early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r;
early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r;
early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r &&
early1_match_rise2_and_r &&
early1_match_fall2_and_r &&
early1_match_rise3_and_r &&
early1_match_fall3_and_r);
end
always @(posedge clk) begin
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r;
early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r;
early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r;
early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r;
early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r &&
early2_match_rise2_and_r &&
early2_match_fall2_and_r &&
early2_match_rise3_and_r &&
early2_match_fall3_and_r);
end
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])
pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])
pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])
pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])
pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// early2 in this case does not mean 2 cycles early but
// the second cycle of read data in 2:1 mode
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
pat1_data_match_r1 <= #TCQ pat1_data_match_r;
pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3;
pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3;
pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3;
pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3;
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r);
// For 2:1 mode, read valid is asserted for 2 clock cycles -
// here we generate a "match valid" pulse that is only 1 clock
// cycle wide that is simulatenous when the match calculation
// is complete
pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r);
early1_data_match_r1 <= #TCQ early1_data_match_r;
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r);
end
end
endgenerate
// Need to delay it by 3 cycles in order to wait for Phaser_Out
// coarse delay to take effect before issuing a write command
always @(posedge clk) begin
wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r;
wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1;
wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2;
end
always @(posedge clk) begin
if (rst)
tap_inc_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) ||
(cal2_state_r == CAL2_IFIFO_RESET) ||
(cal2_state_r == CAL2_SANITY_WAIT))
tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1;
else
tap_inc_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst)
not_empty_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait)
not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1;
else
not_empty_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk)
cal2_state_r1 <= #TCQ cal2_state_r;
//*****************************************************************
// Write Calibration state machine
//*****************************************************************
// when calibrating, check to see if the expected pattern is received.
// Otherwise delay DQS to align to correct CK edge.
// NOTES:
// 1. An error condition can occur due to two reasons:
// a. If the matching logic does not receive the expected data
// pattern. However, the error may be "recoverable" because
// the write calibration is still in progress. If an error is
// found the write calibration logic delays DQS by an additional
// clock cycle and restarts the pattern detection process.
// By design, if the write path timing is incorrect, the correct
// data pattern will never be detected.
// b. Valid data not found even after incrementing Phaser_Out
// coarse delay line.
always @(posedge clk) begin
if (rst) begin
wrcal_dqs_cnt_r <= #TCQ 'b0;
cal2_done_r <= #TCQ 1'b0;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IDLE;
wrcal_pat_err <= #TCQ 1'b0;
wrcal_pat_resume_r <= #TCQ 1'b0;
wrcal_act_req <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
temp_wrcal_done <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b0;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
idelay_ld <= #TCQ 1'b0;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
early1_detect <= #TCQ 1'b0;
wrcal_sanity_chk_done <= #TCQ 1'b0;
wrcal_sanity_chk_err <= #TCQ 1'b0;
end else begin
cal2_prech_req_r <= #TCQ 1'b0;
case (cal2_state_r)
CAL2_IDLE: begin
wrcal_pat_err <= #TCQ 1'b0;
if (wrcal_start) begin
cal2_if_reset <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip write calibration, then proceed to end.
cal2_state_r <= #TCQ CAL2_DONE;
else
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
// General wait state to wait for read data to be output by the
// IN_FIFO
CAL2_READ_WAIT: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
// Wait until read data is received, and pattern matching
// calculation is complete. NOTE: Need to add a timeout here
// in case for some reason data is never received (or rather
// the PHASER_IN and IN_FIFO think they never receives data)
if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin
if (pat_data_match_r)
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else begin
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
// If writes are one or two cycles early then redo
// write leveling for the byte
else if (early1_data_match_r) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early2_data_match_r) begin
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b1;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin
if ((pat1_data_match_r1 && pat2_data_match_r) ||
(pat1_detect && pat2_data_match_r))
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else if (pat1_data_match_r1 && ~pat2_data_match_r) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
pat1_detect <= #TCQ 1'b1;
end else begin
// If writes are one or two cycles early then redo
// write leveling for the byte
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
else if ((early1_data_match_r1 && early2_data_match_r) ||
(early1_detect && early2_data_match_r)) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early1_data_match_r1 && ~early2_data_match_r) begin
early1_detect <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (not_empty_wait_cnt == 'd31)
cal2_state_r <= #TCQ CAL2_ERR;
end
CAL2_WRLVL_WAIT: begin
early1_detect <= #TCQ 1'b0;
if (wrlvl_byte_done && ~wrlvl_byte_done_r)
wrlvl_byte_redo <= #TCQ 1'b0;
if (wrlvl_byte_done) begin
if (rd_active_r1 && ~rd_active_r) begin
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
end
end
end
CAL2_DQ_IDEL_DEC: begin
if (tap_inc_wait_cnt == 'd4) begin
idelay_ld <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b1;
end
end
CAL2_IFIFO_RESET: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_DONE;
else if (idelay_ld_done) begin
wrcal_pat_resume_r <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end else
cal2_state_r <= #TCQ CAL2_IDLE;
end
end
// Final processing for current DQS group. Move on to next group
CAL2_NEXT_DQS: begin
// At this point, we've just found the correct pattern for the
// current DQS group.
// Request bank/row precharge, and wait for its completion. Always
// precharge after each DQS group to avoid tRAS(max) violation
//verilint STARC-2.2.3.3 off
if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin
cal2_prech_req_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_SANITY_WAIT;
end else
cal2_prech_req_r <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
if (prech_done)
if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) ||
(wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin
// If either FAST_CAL is enabled and first DQS group is
// finished, or if the last DQS group was just finished,
// then end of write calibration
if (wrcal_sanity_chk_r) begin
cal2_if_reset <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
end else
cal2_state_r <= #TCQ CAL2_DONE;
end else begin
// Continue to next DQS group
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
//verilint STARC-2.2.3.3 on
CAL2_SANITY_WAIT: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
wrcal_pat_resume_r <= #TCQ 1'b1;
end
end
// Finished with read enable calibration
CAL2_DONE: begin
if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin
cal2_done_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ 'd0;
cal2_state_r <= #TCQ CAL2_IDLE;
end else
cal2_done_r <= #TCQ 1'b1;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_done <= #TCQ 1'b1;
end
// Assert error signal indicating that writes timing is incorrect
CAL2_ERR: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_err <= #TCQ 1'b1;
else
wrcal_pat_err <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_ERR;
end
endcase
end
end
// Delay assertion of wrcal_done for write calibration by a few cycles after
// we've reached CAL2_DONE
always @(posedge clk)
if (rst)
cal2_done_r1 <= #TCQ 1'b0;
else
cal2_done_r1 <= #TCQ cal2_done_r;
always @(posedge clk)
if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r))
wrcal_done <= #TCQ 1'b0;
else if (cal2_done_r)
wrcal_done <= #TCQ 1'b1;
endmodule |
module carads(
clk,
rst_n_key,
echo1,
echo2,
switch1,
switch2,
key1,
uart_rx,
to_sr,
led7,
led6,
voice,
sda,
scl,
MotorA,
MotorB,
ServoPPM,
uart_tx,
clkout,
MotorPWM,
led5,
num,
sel,
testICC
);
input wire clk;
input wire rst_n_key;
input wire echo1;
input wire echo2;
input wire switch1;
input wire switch2;
input wire key1;
input wire uart_rx;
output wire to_sr;
output wire led7;
output wire led6;
output wire voice;
inout wire sda;
output wire scl;
output wire MotorA;
output wire MotorB;
output wire ServoPPM;
output wire uart_tx;
output wire clkout;
output wire MotorPWM;
output wire led5;
output wire [6:0] num;
output wire [3:0] sel;
output wire testICC;
wire [6:0] num_ALTERA_SYNTHESIZED;
wire [3:0] sel_ALTERA_SYNTHESIZED;
wire [9:0] SYNTHESIZED_WIRE_1;
wire [15:0] SYNTHESIZED_WIRE_2;
wire [15:0] SYNTHESIZED_WIRE_3;
wire [9:0] SYNTHESIZED_WIRE_4;
wire [15:0] angle_control;
wire [13:0] distance;
reg rst_n_inside;
wire rst_n;
assign rst_n = rst_n_key && rst_n_inside;
reg[15:0]autoResetCnt;
always@(posedge clk) begin
if(autoResetCnt<10000) begin rst_n_inside <= 1; autoResetCnt = autoResetCnt + 1; end
else if(autoResetCnt>=10000 && autoResetCnt < 60000) begin autoResetCnt = autoResetCnt + 1; rst_n_inside <= 0; end
else if(autoResetCnt >= 60000) rst_n_inside = 1;
else autoResetCnt = 0;
end
transtop b2v_inst(
.clk(clk),
.rst_n(rst_n),
.echo1(echo1),
.echo2(echo2),
.clkout(to_sr),
.distance(distance),
.speed(SYNTHESIZED_WIRE_1));
mainlogic b2v_inst1(
.rst_n(rst_n),
.switch1(switch1),
.switch2(switch2),
.clk(clk),
.distance(distance),
.speed(SYNTHESIZED_WIRE_1),
.triangle(SYNTHESIZED_WIRE_2),
.led1(led7),
.led2(led6),
.voice(voice),
.out_num(SYNTHESIZED_WIRE_4),
.speed_control(SYNTHESIZED_WIRE_3),
.angle_control(angle_control));
top b2v_inst2(
.clk(clk),
.rst_n(rst_n),
.key1(key1),
.uart_rx(uart_rx),
.sda(sda),
.speed_control(SYNTHESIZED_WIRE_3),
.scl(scl),
.MotorPWM(MotorPWM),
.MotorA(MotorA),
.MotorB(MotorB),
.ServoPPM(ServoPPM),
.clkOut(clkout),
.uart_tx(uart_tx),
.newControlDataW(led5),
.accXdata(SYNTHESIZED_WIRE_2),
.angle_control(angle_control),
.testICC(testICC)
);
shumaguan b2v_inst9(
.clk(clk),
.rst_n(rst_n),
.distance(distance),
.num(num),
.sel(sel)
);
endmodule |
module ADT7310P32S16 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPreset_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPreset_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i(SPICounterPreset_i)
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i({PeriodCounterPresetH_i, PeriodCounterPresetL_i})
);
endmodule |
module escritor_lector_rtc(
input clk,reset,
input [7:0]port_id,in_dato,
input write_strobe,read_strobe,
output reg_a_d,reg_cs,reg_rd,reg_wr,
output reg[7:0]out_dato,
output flag_done,
inout [7:0]dato
);
reg en_funcion;
reg [7:0]addr_RAM,dato_escribir;
wire [7:0]dato_leido;
reg [7:0]next_out_dato;
reg [7:0]reg_addr_RAM, reg_dato_escribir,reg_dato_leido;
reg reg_escribir_leer,escribir_leer;
wire direccion_dato;
/// I/O Datos
Driver_bus_bidireccional instance_driver_bus_bidireccional (
.in_flag_escritura(~reg_wr),
.in_flag_lectura(~reg_rd),
.in_direccion_dato(direccion_dato),
.in_dato(dato_escribir),
.out_reg_dato(dato_leido),
.addr_RAM(addr_RAM),
.dato(dato)
);
//Generador de señales de control
signal_control_rtc_generator instance_signal_control_rtc_generator (
.clk(clk),
.reset(reset),
.in_escribir_leer(escribir_leer),
.en_funcion(en_funcion),
.reg_a_d(reg_a_d),
.reg_cs(reg_cs),
.reg_wr(reg_wr),
.reg_rd(reg_rd),
.out_direccion_dato(direccion_dato),
.flag_done(flag_done)
);
// logica secuencial
always@(negedge clk , posedge reset) begin
if (reset)begin
addr_RAM <= 8'h0;
dato_escribir <= 8'h0;
escribir_leer <= 1'b0;
out_dato <= 8'b0;
end
else begin
addr_RAM <= reg_addr_RAM;
dato_escribir <= reg_dato_escribir;
escribir_leer <= reg_escribir_leer;
out_dato <= next_out_dato;
end
end
// logica combinacional para port_id
always@* begin
if (~reg_rd) next_out_dato = dato_leido;
next_out_dato = out_dato;
if ( write_strobe == 1'b1 || read_strobe == 1'b1) begin
// inicio de secuencia de lectura_escritura rtc
if(port_id == 8'h0E) en_funcion = 1'b1;
else en_funcion = 1'b0;
case (port_id)
8'h00: begin //actualiza direccion
reg_addr_RAM = in_dato;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = escribir_leer;
end
8'h01: begin // actualiza dato
reg_dato_escribir = in_dato;
reg_addr_RAM = addr_RAM;
reg_escribir_leer = escribir_leer;
end
8'h0E: begin // inicia secuancia de rtc
reg_addr_RAM = addr_RAM;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = in_dato[0];
end
default: begin
reg_addr_RAM = addr_RAM;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = escribir_leer;
end
endcase
end
else begin
reg_addr_RAM = addr_RAM;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = escribir_leer;
en_funcion = 1'b0;
end
end
endmodule |
module Test (
address,
clock,
q);
input [0:0] address;
input clock;
output [15:0] q;
endmodule |
module test_axis_async_frame_fifo_64;
// Inputs
reg input_clk = 0;
reg input_rst = 0;
reg output_clk = 0;
reg output_rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
initial begin
// myhdl integration
$from_myhdl(input_clk,
input_rst,
output_clk,
output_rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast);
// dump file
$dumpfile("test_axis_async_frame_fifo_64.lxt");
$dumpvars(0, test_axis_async_frame_fifo_64);
end
axis_async_frame_fifo_64 #(
.ADDR_WIDTH(6),
.DATA_WIDTH(64),
.DROP_WHEN_FULL(0)
)
UUT (
// AXI input
.input_clk(input_clk),
.input_rst(input_rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_clk(output_clk),
.output_rst(output_rst),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast)
);
endmodule |
module CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
output [63:0] add_subt_dataA;
output [63:0] add_subt_dataB;
input [63:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_63_, cordic_FSM_state_next_1_, n564, n569, n570, n571,
n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582,
n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626,
n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648,
n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659,
n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670,
n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681,
n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857,
n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868,
n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901,
n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912,
n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489,
n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499,
n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509,
n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519,
n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559,
n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569,
n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579,
n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599,
n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649,
n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659,
n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829,
n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839,
n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849,
n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859,
n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889,
n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899,
n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909,
n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919,
n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929,
n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939,
n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949,
n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959,
n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969,
n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979,
n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989,
n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999,
n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009,
n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079,
n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089,
n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099,
n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109,
n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119,
n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129,
n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139,
n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149,
n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159,
n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169,
n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179,
n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189,
n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209,
n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219,
n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229,
n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239,
n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259,
n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269,
n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279,
n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289,
n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299,
n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309,
n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319,
n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:0] cont_iter_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [62:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
DFFRXLTS cont_iter_count_reg_3_ ( .D(n1338), .CK(clk), .RN(n2342), .Q(
cont_iter_out[3]), .QN(n1478) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1333), .CK(clk), .RN(n2341), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1332), .CK(clk), .RN(n2350), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1331), .CK(clk), .RN(n2345), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(n1488), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1329), .CK(clk), .RN(n2346), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1328), .CK(clk), .RN(n2340), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1327), .CK(clk), .RN(n2349), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1326), .CK(clk), .RN(n2346), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1325), .CK(clk), .RN(n2344), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1324), .CK(clk), .RN(n2344), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1323), .CK(clk), .RN(n2340), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(n1488), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1321), .CK(clk), .RN(n2348), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1320), .CK(clk), .RN(n2348), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1319), .CK(clk), .RN(n2348), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1318), .CK(clk), .RN(n2348), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1317), .CK(clk), .RN(n2348), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1316), .CK(clk), .RN(n2355), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n2353), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1314), .CK(clk), .RN(n2352), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1313), .CK(clk), .RN(n2351), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1312), .CK(clk), .RN(n2357), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1311), .CK(clk), .RN(n2340), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1310), .CK(clk), .RN(n2346), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1309), .CK(clk), .RN(n1489), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1308), .CK(clk), .RN(n2345), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1307), .CK(clk), .RN(n2345), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1306), .CK(clk), .RN(n2346), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1305), .CK(clk), .RN(n2349), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1304), .CK(clk), .RN(n2345), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1303), .CK(clk), .RN(n1489), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1302), .CK(clk), .RN(n1488), .Q(d_ff1_Z[31])
);
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n1301), .CK(clk), .RN(n2346), .Q(d_ff1_Z[32])
);
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n1300), .CK(clk), .RN(n2344), .Q(d_ff1_Z[33])
);
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n1299), .CK(clk), .RN(n2346), .Q(d_ff1_Z[34])
);
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n1298), .CK(clk), .RN(n2346), .Q(d_ff1_Z[35])
);
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n1297), .CK(clk), .RN(n2345), .Q(d_ff1_Z[36])
);
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n1296), .CK(clk), .RN(n2344), .Q(d_ff1_Z[37])
);
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n1295), .CK(clk), .RN(n1488), .Q(d_ff1_Z[38])
);
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n1294), .CK(clk), .RN(n2340), .Q(d_ff1_Z[39])
);
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n1293), .CK(clk), .RN(n2347), .Q(d_ff1_Z[40])
);
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n1292), .CK(clk), .RN(n2349), .Q(d_ff1_Z[41])
);
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n1291), .CK(clk), .RN(n2345), .Q(d_ff1_Z[42])
);
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n1290), .CK(clk), .RN(n2344), .Q(d_ff1_Z[43])
);
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n1289), .CK(clk), .RN(n2340), .Q(d_ff1_Z[44])
);
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n1288), .CK(clk), .RN(n2349), .Q(d_ff1_Z[45])
);
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n1287), .CK(clk), .RN(n2347), .Q(d_ff1_Z[46])
);
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n1286), .CK(clk), .RN(n1489), .Q(d_ff1_Z[47])
);
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n1285), .CK(clk), .RN(n2349), .Q(d_ff1_Z[48])
);
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n1284), .CK(clk), .RN(n2344), .Q(d_ff1_Z[49])
);
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n1283), .CK(clk), .RN(n2344), .Q(d_ff1_Z[50])
);
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n1282), .CK(clk), .RN(n2347), .Q(d_ff1_Z[51])
);
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n1281), .CK(clk), .RN(n1488), .Q(d_ff1_Z[52])
);
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n1280), .CK(clk), .RN(n2349), .Q(d_ff1_Z[53])
);
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n1279), .CK(clk), .RN(n2347), .Q(d_ff1_Z[54])
);
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n1278), .CK(clk), .RN(n2340), .Q(d_ff1_Z[55])
);
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n1277), .CK(clk), .RN(n2347), .Q(d_ff1_Z[56])
);
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n1276), .CK(clk), .RN(n1489), .Q(d_ff1_Z[57])
);
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n1275), .CK(clk), .RN(n2340), .Q(d_ff1_Z[58])
);
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n1274), .CK(clk), .RN(n2345), .Q(d_ff1_Z[59])
);
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n1273), .CK(clk), .RN(n2344), .Q(d_ff1_Z[60])
);
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n1272), .CK(clk), .RN(n2347), .Q(d_ff1_Z[61])
);
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n1271), .CK(clk), .RN(n1509), .Q(d_ff1_Z[62])
);
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n1270), .CK(clk), .RN(n1508), .Q(d_ff1_Z[63])
);
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1265), .CK(clk), .RN(n2343), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1264), .CK(clk), .RN(n2341), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1263), .CK(clk), .RN(n2342), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1262), .CK(clk), .RN(n2339), .Q(d_ff_Zn[3])
);
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1261), .CK(clk), .RN(n2339), .Q(d_ff_Zn[4])
);
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1260), .CK(clk), .RN(n1509), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1259), .CK(clk), .RN(n1508), .Q(d_ff_Zn[6])
);
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1258), .CK(clk), .RN(n2341), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1257), .CK(clk), .RN(n2350), .Q(d_ff_Zn[8])
);
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1256), .CK(clk), .RN(n2343), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1255), .CK(clk), .RN(n2342), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n2339), .Q(
d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1253), .CK(clk), .RN(n1509), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1252), .CK(clk), .RN(n1508), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1251), .CK(clk), .RN(n2350), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1250), .CK(clk), .RN(n1509), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n2357), .Q(
d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1248), .CK(clk), .RN(n1508), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1247), .CK(clk), .RN(n2343), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1246), .CK(clk), .RN(n2341), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1245), .CK(clk), .RN(n2339), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1244), .CK(clk), .RN(n2350), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1243), .CK(clk), .RN(n2343), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1242), .CK(clk), .RN(n2342), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1241), .CK(clk), .RN(n2345), .Q(
d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1240), .CK(clk), .RN(n1489), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1239), .CK(clk), .RN(n2349), .Q(
d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1238), .CK(clk), .RN(n2349), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1237), .CK(clk), .RN(n2340), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1236), .CK(clk), .RN(n2345), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1235), .CK(clk), .RN(n1488), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1234), .CK(clk), .RN(n2346), .Q(
d_ff_Zn[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n1233), .CK(clk), .RN(n2347), .Q(
d_ff_Zn[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n1232), .CK(clk), .RN(n2347), .Q(
d_ff_Zn[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n1231), .CK(clk), .RN(n1509), .Q(
d_ff_Zn[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n1230), .CK(clk), .RN(n2335), .Q(
d_ff_Zn[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n1229), .CK(clk), .RN(n1494), .Q(
d_ff_Zn[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n1228), .CK(clk), .RN(n1506), .Q(
d_ff_Zn[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n1227), .CK(clk), .RN(n1501), .Q(
d_ff_Zn[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n1226), .CK(clk), .RN(n1493), .Q(
d_ff_Zn[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n1225), .CK(clk), .RN(n2354), .Q(
d_ff_Zn[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n1224), .CK(clk), .RN(n2340), .Q(
d_ff_Zn[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n1223), .CK(clk), .RN(n2345), .Q(
d_ff_Zn[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n1222), .CK(clk), .RN(n2366), .Q(
d_ff_Zn[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n1221), .CK(clk), .RN(n2341), .Q(
d_ff_Zn[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n1220), .CK(clk), .RN(n2350), .Q(
d_ff_Zn[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n1219), .CK(clk), .RN(n2343), .Q(
d_ff_Zn[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n1218), .CK(clk), .RN(n2342), .Q(
d_ff_Zn[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n1217), .CK(clk), .RN(n2339), .Q(
d_ff_Zn[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n1216), .CK(clk), .RN(n1509), .Q(
d_ff_Zn[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n1215), .CK(clk), .RN(n1508), .Q(
d_ff_Zn[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n1214), .CK(clk), .RN(n2341), .Q(
d_ff_Zn[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n1213), .CK(clk), .RN(n2350), .Q(
d_ff_Zn[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n1212), .CK(clk), .RN(n2343), .Q(
d_ff_Zn[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n1211), .CK(clk), .RN(n2337), .Q(
d_ff_Zn[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n1210), .CK(clk), .RN(n2336), .Q(
d_ff_Zn[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n1209), .CK(clk), .RN(n2356), .Q(
d_ff_Zn[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n1208), .CK(clk), .RN(n2338), .Q(
d_ff_Zn[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n1207), .CK(clk), .RN(n2337), .Q(
d_ff_Zn[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n1206), .CK(clk), .RN(n2336), .Q(
d_ff_Zn[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n1205), .CK(clk), .RN(n2356), .Q(
d_ff_Zn[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n1204), .CK(clk), .RN(n2338), .Q(
d_ff_Zn[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n1203), .CK(clk), .RN(n2337), .Q(
d_ff_Zn[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n1202), .CK(clk), .RN(n2336), .Q(
d_ff_Zn[63]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n1201), .CK(clk), .RN(n2356), .Q(d_ff_Yn[0]),
.QN(n2239) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n1200), .CK(clk), .RN(n2338), .Q(d_ff_Yn[1]),
.QN(n2240) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n1199), .CK(clk), .RN(n2337), .Q(d_ff_Yn[2]),
.QN(n2241) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n1198), .CK(clk), .RN(n2336), .Q(d_ff_Yn[3]),
.QN(n2242) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n1197), .CK(clk), .RN(n2356), .Q(d_ff_Yn[4]),
.QN(n2243) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n1196), .CK(clk), .RN(n2338), .Q(d_ff_Yn[5]),
.QN(n2244) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n1195), .CK(clk), .RN(n2337), .Q(d_ff_Yn[6]),
.QN(n2245) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n1194), .CK(clk), .RN(n2336), .Q(d_ff_Yn[7]),
.QN(n2246) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n1193), .CK(clk), .RN(n2356), .Q(d_ff_Yn[8]),
.QN(n2247) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n1192), .CK(clk), .RN(n2338), .Q(d_ff_Yn[9]),
.QN(n2248) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n1191), .CK(clk), .RN(n2337), .Q(
d_ff_Yn[10]), .QN(n2249) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n1190), .CK(clk), .RN(n2336), .Q(
d_ff_Yn[11]), .QN(n2250) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n1189), .CK(clk), .RN(n2356), .Q(
d_ff_Yn[12]), .QN(n2251) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n1188), .CK(clk), .RN(n2338), .Q(
d_ff_Yn[13]), .QN(n2252) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n1187), .CK(clk), .RN(n2337), .Q(
d_ff_Yn[14]), .QN(n2253) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n1186), .CK(clk), .RN(n2336), .Q(
d_ff_Yn[15]), .QN(n2254) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n1185), .CK(clk), .RN(n2356), .Q(
d_ff_Yn[16]), .QN(n2255) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n1184), .CK(clk), .RN(n2338), .Q(
d_ff_Yn[17]), .QN(n2256) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n1183), .CK(clk), .RN(n2337), .Q(
d_ff_Yn[18]), .QN(n2257) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n1182), .CK(clk), .RN(n2336), .Q(
d_ff_Yn[19]), .QN(n2258) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n1181), .CK(clk), .RN(n2317), .Q(
d_ff_Yn[20]), .QN(n2259) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n1180), .CK(clk), .RN(n2314), .Q(
d_ff_Yn[21]), .QN(n2260) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n1179), .CK(clk), .RN(n2333), .Q(
d_ff_Yn[22]), .QN(n2261) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n1178), .CK(clk), .RN(n2334), .Q(
d_ff_Yn[23]), .QN(n2262) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n1177), .CK(clk), .RN(n2335), .Q(
d_ff_Yn[24]), .QN(n2263) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n1176), .CK(clk), .RN(n2315), .Q(
d_ff_Yn[25]), .QN(n2264) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n1175), .CK(clk), .RN(n2316), .Q(
d_ff_Yn[26]), .QN(n2265) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n1174), .CK(clk), .RN(n1513), .Q(
d_ff_Yn[27]), .QN(n2266) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n1173), .CK(clk), .RN(n1514), .Q(
d_ff_Yn[28]), .QN(n2267) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n1172), .CK(clk), .RN(n2317), .Q(
d_ff_Yn[29]), .QN(n2268) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n1171), .CK(clk), .RN(n2314), .Q(
d_ff_Yn[30]), .QN(n2269) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n1170), .CK(clk), .RN(n2333), .Q(
d_ff_Yn[31]), .QN(n2270) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(n1169), .CK(clk), .RN(n2334), .Q(
d_ff_Yn[32]), .QN(n2271) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(n1168), .CK(clk), .RN(n2335), .Q(
d_ff_Yn[33]), .QN(n2272) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(n1167), .CK(clk), .RN(n2315), .Q(
d_ff_Yn[34]), .QN(n2273) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(n1166), .CK(clk), .RN(n2316), .Q(
d_ff_Yn[35]), .QN(n2274) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(n1165), .CK(clk), .RN(n1513), .Q(
d_ff_Yn[36]), .QN(n2275) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(n1164), .CK(clk), .RN(n1514), .Q(
d_ff_Yn[37]), .QN(n2276) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(n1163), .CK(clk), .RN(n2317), .Q(
d_ff_Yn[38]), .QN(n2277) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(n1162), .CK(clk), .RN(n2314), .Q(
d_ff_Yn[39]), .QN(n2278) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(n1161), .CK(clk), .RN(n2333), .Q(
d_ff_Yn[40]), .QN(n2279) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(n1160), .CK(clk), .RN(n2334), .Q(
d_ff_Yn[41]), .QN(n2280) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(n1159), .CK(clk), .RN(n2335), .Q(
d_ff_Yn[42]), .QN(n2281) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(n1158), .CK(clk), .RN(n2315), .Q(
d_ff_Yn[43]), .QN(n2282) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(n1157), .CK(clk), .RN(n2316), .Q(
d_ff_Yn[44]), .QN(n2283) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(n1156), .CK(clk), .RN(n1513), .Q(
d_ff_Yn[45]), .QN(n2284) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(n1155), .CK(clk), .RN(n1514), .Q(
d_ff_Yn[46]), .QN(n2285) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(n1154), .CK(clk), .RN(n2317), .Q(
d_ff_Yn[47]), .QN(n2286) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(n1153), .CK(clk), .RN(n2314), .Q(
d_ff_Yn[48]), .QN(n2287) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(n1152), .CK(clk), .RN(n2333), .Q(
d_ff_Yn[49]), .QN(n2288) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(n1151), .CK(clk), .RN(n2304), .Q(
d_ff_Yn[50]), .QN(n2289) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(n1150), .CK(clk), .RN(n2342), .Q(
d_ff_Yn[51]), .QN(n2290) );
DFFRXLTS d_ff4_Yn_Q_reg_52_ ( .D(n1149), .CK(clk), .RN(n1507), .Q(
d_ff_Yn[52]) );
DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(n1148), .CK(clk), .RN(n2356), .Q(
d_ff_Yn[53]) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(n1147), .CK(clk), .RN(n2336), .Q(
d_ff_Yn[54]), .QN(n2291) );
DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(n1146), .CK(clk), .RN(n2357), .Q(
d_ff_Yn[55]) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(n1145), .CK(clk), .RN(n2351), .Q(
d_ff_Yn[56]) );
DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(n1144), .CK(clk), .RN(n2352), .Q(
d_ff_Yn[57]) );
DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(n1143), .CK(clk), .RN(n2353), .Q(
d_ff_Yn[58]) );
DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(n1142), .CK(clk), .RN(n2348), .Q(
d_ff_Yn[59]) );
DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(n1141), .CK(clk), .RN(n2357), .Q(
d_ff_Yn[60]) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(n1140), .CK(clk), .RN(n2351), .Q(
d_ff_Yn[61]) );
DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(n1139), .CK(clk), .RN(n2352), .Q(
d_ff_Yn[62]) );
DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(n1138), .CK(clk), .RN(n2353), .Q(
d_ff_Yn[63]), .QN(n2292) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n1073), .CK(clk), .RN(n2358), .Q(
sign_inv_out[0]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n1071), .CK(clk), .RN(n2358), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n1069), .CK(clk), .RN(n2358), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n1067), .CK(clk), .RN(n2358), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n1065), .CK(clk), .RN(n2362), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n1063), .CK(clk), .RN(n2363), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n1061), .CK(clk), .RN(n2359), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n1053), .CK(clk), .RN(n2365), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n1051), .CK(clk), .RN(n2361), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n1049), .CK(clk), .RN(n2360), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n1047), .CK(clk), .RN(n2359), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n1045), .CK(clk), .RN(n2362), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n1043), .CK(clk), .RN(n2363), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n1041), .CK(clk), .RN(n2359), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n1039), .CK(clk), .RN(n2359), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n1037), .CK(clk), .RN(n2362), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n1035), .CK(clk), .RN(n2363), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n1033), .CK(clk), .RN(n2360), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n1031), .CK(clk), .RN(n2361), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n1029), .CK(clk), .RN(n1507), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n1027), .CK(clk), .RN(n1506), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n1025), .CK(clk), .RN(n2308), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n1023), .CK(clk), .RN(n2360), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n1021), .CK(clk), .RN(n2361), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n1019), .CK(clk), .RN(n1507), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n1017), .CK(clk), .RN(n2337), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n1015), .CK(clk), .RN(n2356), .Q(
sign_inv_out[29]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n1013), .CK(clk), .RN(n1488), .Q(
sign_inv_out[30]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(n1011), .CK(clk), .RN(n2348), .Q(
sign_inv_out[31]) );
DFFRXLTS d_ff5_Q_reg_32_ ( .D(n1009), .CK(clk), .RN(n1489), .Q(
sign_inv_out[32]) );
DFFRXLTS d_ff5_Q_reg_33_ ( .D(n1007), .CK(clk), .RN(n1510), .Q(
sign_inv_out[33]) );
DFFRXLTS d_ff5_Q_reg_34_ ( .D(n1005), .CK(clk), .RN(n1510), .Q(
sign_inv_out[34]) );
DFFRXLTS d_ff5_Q_reg_35_ ( .D(n1003), .CK(clk), .RN(n2353), .Q(
sign_inv_out[35]) );
DFFRXLTS d_ff5_Q_reg_36_ ( .D(n1001), .CK(clk), .RN(n2351), .Q(
sign_inv_out[36]) );
DFFRXLTS d_ff5_Q_reg_40_ ( .D(n993), .CK(clk), .RN(n1502), .Q(
sign_inv_out[40]) );
DFFRXLTS d_ff5_Q_reg_41_ ( .D(n991), .CK(clk), .RN(n1502), .Q(
sign_inv_out[41]) );
DFFRXLTS d_ff5_Q_reg_42_ ( .D(n989), .CK(clk), .RN(n2329), .Q(
sign_inv_out[42]) );
DFFRXLTS d_ff5_Q_reg_43_ ( .D(n987), .CK(clk), .RN(n1502), .Q(
sign_inv_out[43]) );
DFFRXLTS d_ff5_Q_reg_44_ ( .D(n985), .CK(clk), .RN(n2351), .Q(
sign_inv_out[44]) );
DFFRXLTS d_ff5_Q_reg_45_ ( .D(n983), .CK(clk), .RN(n1510), .Q(
sign_inv_out[45]) );
DFFRXLTS d_ff5_Q_reg_46_ ( .D(n981), .CK(clk), .RN(n2353), .Q(
sign_inv_out[46]) );
DFFRXLTS d_ff5_Q_reg_47_ ( .D(n979), .CK(clk), .RN(n1507), .Q(
sign_inv_out[47]) );
DFFRXLTS d_ff5_Q_reg_48_ ( .D(n977), .CK(clk), .RN(n1510), .Q(
sign_inv_out[48]) );
DFFRXLTS d_ff5_Q_reg_49_ ( .D(n975), .CK(clk), .RN(n2334), .Q(
sign_inv_out[49]) );
DFFRXLTS d_ff5_Q_reg_50_ ( .D(n973), .CK(clk), .RN(n1510), .Q(
sign_inv_out[50]) );
DFFRXLTS d_ff5_Q_reg_51_ ( .D(n971), .CK(clk), .RN(n2355), .Q(
sign_inv_out[51]) );
DFFRXLTS d_ff5_Q_reg_52_ ( .D(n969), .CK(clk), .RN(n2353), .Q(
sign_inv_out[52]) );
DFFRXLTS d_ff5_Q_reg_53_ ( .D(n967), .CK(clk), .RN(n2352), .Q(
sign_inv_out[53]) );
DFFRXLTS d_ff5_Q_reg_54_ ( .D(n965), .CK(clk), .RN(n2366), .Q(
sign_inv_out[54]) );
DFFRXLTS d_ff5_Q_reg_55_ ( .D(n963), .CK(clk), .RN(n1502), .Q(
sign_inv_out[55]) );
DFFRXLTS d_ff5_Q_reg_56_ ( .D(n961), .CK(clk), .RN(n1508), .Q(
sign_inv_out[56]) );
DFFRXLTS d_ff5_Q_reg_57_ ( .D(n959), .CK(clk), .RN(n2355), .Q(
sign_inv_out[57]) );
DFFRXLTS d_ff5_Q_reg_58_ ( .D(n957), .CK(clk), .RN(n2353), .Q(
sign_inv_out[58]) );
DFFRXLTS d_ff5_Q_reg_59_ ( .D(n955), .CK(clk), .RN(n2351), .Q(
sign_inv_out[59]) );
DFFRXLTS d_ff5_Q_reg_60_ ( .D(n953), .CK(clk), .RN(n2312), .Q(
sign_inv_out[60]) );
DFFRXLTS d_ff5_Q_reg_61_ ( .D(n951), .CK(clk), .RN(n2313), .Q(
sign_inv_out[61]) );
DFFRXLTS d_ff5_Q_reg_62_ ( .D(n949), .CK(clk), .RN(n2296), .Q(
sign_inv_out[62]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n945), .CK(clk), .RN(n2294), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n944), .CK(clk), .RN(n2312), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n943), .CK(clk), .RN(n2296), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n941), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n940), .CK(clk), .RN(n2309), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n939), .CK(clk), .RN(n2329), .Q(
d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n938), .CK(clk), .RN(n2328), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n937), .CK(clk), .RN(n2310), .QN(n1517) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n936), .CK(clk), .RN(n2311), .Q(
d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n935), .CK(clk), .RN(n2309), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n934), .CK(clk), .RN(n1511), .Q(
d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n933), .CK(clk), .RN(n2330), .Q(
d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n932), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n931), .CK(clk), .RN(n2329), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n929), .CK(clk), .RN(n2311), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n928), .CK(clk), .RN(n2328), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n927), .CK(clk), .RN(n2309), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n926), .CK(clk), .RN(n2328), .QN(n1515) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n925), .CK(clk), .RN(n2310), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n924), .CK(clk), .RN(n2311), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n923), .CK(clk), .RN(n2309), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n922), .CK(clk), .RN(n1511), .Q(
d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n921), .CK(clk), .RN(n2330), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n920), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n919), .CK(clk), .RN(n2329), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n918), .CK(clk), .RN(n1511), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n917), .CK(clk), .RN(n2330), .Q(
d_ff3_LUT_out[28]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n916), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[29]) );
DFFRXLTS reg_LUT_Q_reg_30_ ( .D(n915), .CK(clk), .RN(n2329), .Q(
d_ff3_LUT_out[30]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n914), .CK(clk), .RN(n1511), .Q(
d_ff3_LUT_out[31]) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n913), .CK(clk), .RN(n2330), .Q(
d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(n912), .CK(clk), .RN(n2361), .Q(
d_ff3_LUT_out[33]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n911), .CK(clk), .RN(n2364), .Q(
d_ff3_LUT_out[34]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n910), .CK(clk), .RN(n2360), .Q(
d_ff3_LUT_out[35]) );
DFFRXLTS reg_LUT_Q_reg_36_ ( .D(n909), .CK(clk), .RN(n2365), .Q(
d_ff3_LUT_out[36]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n908), .CK(clk), .RN(n2308), .Q(
d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_38_ ( .D(n907), .CK(clk), .RN(n1507), .Q(
d_ff3_LUT_out[38]) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(n906), .CK(clk), .RN(n1506), .Q(
d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_40_ ( .D(n905), .CK(clk), .RN(n2361), .Q(
d_ff3_LUT_out[40]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n904), .CK(clk), .RN(n2364), .QN(n1516) );
DFFRXLTS reg_LUT_Q_reg_42_ ( .D(n903), .CK(clk), .RN(n2360), .Q(
d_ff3_LUT_out[42]) );
DFFRXLTS reg_LUT_Q_reg_43_ ( .D(n902), .CK(clk), .RN(n2322), .Q(
d_ff3_LUT_out[43]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n901), .CK(clk), .RN(n2306), .Q(
d_ff3_LUT_out[44]) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n900), .CK(clk), .RN(n2303), .Q(
d_ff3_LUT_out[45]) );
DFFRXLTS reg_LUT_Q_reg_46_ ( .D(n899), .CK(clk), .RN(n2307), .Q(
d_ff3_LUT_out[46]) );
DFFRXLTS reg_LUT_Q_reg_47_ ( .D(n898), .CK(clk), .RN(n2322), .Q(
d_ff3_LUT_out[47]) );
DFFRXLTS reg_LUT_Q_reg_49_ ( .D(n896), .CK(clk), .RN(n2306), .Q(
d_ff3_LUT_out[49]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n895), .CK(clk), .RN(n2303), .Q(
d_ff3_LUT_out[50]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n894), .CK(clk), .RN(n2307), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n893), .CK(clk), .RN(n2307), .Q(
d_ff3_LUT_out[53]), .QN(n2293) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(n892), .CK(clk), .RN(n2322), .Q(
d_ff3_LUT_out[54]) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(n891), .CK(clk), .RN(n2306), .Q(
d_ff3_LUT_out[55]) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n890), .CK(clk), .RN(n2303), .Q(
d_ff3_LUT_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(n709), .CK(clk), .RN(n2307), .Q(
d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n708), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n707), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n706), .CK(clk), .RN(n2303), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(n705), .CK(clk), .RN(n2307), .Q(
d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(n704), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n703), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n702), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n701), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(n700), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n699), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n581), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n580), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n579), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n578), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(n577), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[56]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n576), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n575), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(n574), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n573), .CK(clk), .RN(n2304), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n572), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n571), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n889), .CK(clk), .RN(n2304), .Q(
d_ff2_Z[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n842), .CK(clk), .RN(n2319), .Q(
d_ff2_Z[47]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n841), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[48]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n840), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[49]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n839), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[50]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n838), .CK(clk), .RN(n2319), .Q(
d_ff2_Z[51]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n837), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n836), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[53]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n835), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[54]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n834), .CK(clk), .RN(n2319), .Q(
d_ff2_Z[55]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n833), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[56]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n831), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n829), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[60]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n825), .CK(clk), .RN(n2297), .Q(
d_ff3_sign_out) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n823), .CK(clk), .RN(n2297), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n821), .CK(clk), .RN(n2297), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n819), .CK(clk), .RN(n2297), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n2297), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n2313), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n813), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n811), .CK(clk), .RN(n2296), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n809), .CK(clk), .RN(n2313), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n807), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n805), .CK(clk), .RN(n2312), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n803), .CK(clk), .RN(n2313), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n801), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n799), .CK(clk), .RN(n2296), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n797), .CK(clk), .RN(n2312), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n795), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n793), .CK(clk), .RN(n2312), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n791), .CK(clk), .RN(n2296), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n789), .CK(clk), .RN(n2313), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n787), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n785), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n783), .CK(clk), .RN(n2304), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n781), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n2304), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n777), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n775), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n773), .CK(clk), .RN(n2304), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n771), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n769), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n767), .CK(clk), .RN(n2330), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n765), .CK(clk), .RN(n2327), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n763), .CK(clk), .RN(n2329), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n761), .CK(clk), .RN(n2330), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n759), .CK(clk), .RN(n2327), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n757), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n755), .CK(clk), .RN(n2310), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n753), .CK(clk), .RN(n2311), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n751), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n749), .CK(clk), .RN(n2328), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n747), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n745), .CK(clk), .RN(n2328), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n743), .CK(clk), .RN(n2310), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n741), .CK(clk), .RN(n2311), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n739), .CK(clk), .RN(n2330), .Q(
d_ff3_sh_y_out[42]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n737), .CK(clk), .RN(n2329), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n735), .CK(clk), .RN(n2328), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n733), .CK(clk), .RN(n2310), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n731), .CK(clk), .RN(n2311), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n729), .CK(clk), .RN(n2309), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n727), .CK(clk), .RN(n1494), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n725), .CK(clk), .RN(n2302), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n723), .CK(clk), .RN(n2320), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n721), .CK(clk), .RN(n1494), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_56_ ( .D(n716), .CK(clk), .RN(n2320), .Q(
d_ff2_Y[56]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_58_ ( .D(n714), .CK(clk), .RN(n2320), .Q(
d_ff2_Y[58]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_60_ ( .D(n712), .CK(clk), .RN(n2326), .Q(
d_ff2_Y[60]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_62_ ( .D(n710), .CK(clk), .RN(n2324), .Q(
d_ff2_Y[62]), .QN(n2237) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n697), .CK(clk), .RN(n2326), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n2324), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n693), .CK(clk), .RN(n2301), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n691), .CK(clk), .RN(n1494), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n689), .CK(clk), .RN(n1494), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n687), .CK(clk), .RN(n2302), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n685), .CK(clk), .RN(n2323), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n683), .CK(clk), .RN(n2323), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n681), .CK(clk), .RN(n2323), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n679), .CK(clk), .RN(n2323), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n677), .CK(clk), .RN(n2307), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n675), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n673), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n671), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n669), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n667), .CK(clk), .RN(n2303), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n665), .CK(clk), .RN(n2307), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n663), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n661), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n659), .CK(clk), .RN(n2303), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n657), .CK(clk), .RN(n2325), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n655), .CK(clk), .RN(n2301), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n653), .CK(clk), .RN(n2325), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n2301), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n2325), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n647), .CK(clk), .RN(n2298), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n645), .CK(clk), .RN(n2319), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n643), .CK(clk), .RN(n2318), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n2299), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n639), .CK(clk), .RN(n2298), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n637), .CK(clk), .RN(n2319), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n635), .CK(clk), .RN(n2318), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n633), .CK(clk), .RN(n2299), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n631), .CK(clk), .RN(n2298), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n629), .CK(clk), .RN(n2319), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n627), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n625), .CK(clk), .RN(n2314), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n623), .CK(clk), .RN(n2334), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n621), .CK(clk), .RN(n2315), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n619), .CK(clk), .RN(n1513), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n617), .CK(clk), .RN(n2315), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n615), .CK(clk), .RN(n1513), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n613), .CK(clk), .RN(n2314), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n611), .CK(clk), .RN(n2334), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n609), .CK(clk), .RN(n2315), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n607), .CK(clk), .RN(n1513), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n605), .CK(clk), .RN(n2317), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n603), .CK(clk), .RN(n2333), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n601), .CK(clk), .RN(n2335), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n599), .CK(clk), .RN(n2316), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n597), .CK(clk), .RN(n2317), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n595), .CK(clk), .RN(n2316), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n593), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n569), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_x_out[63]) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n1337), .CK(clk), .RN(n1509), .Q(
cont_var_out[0]), .QN(n2231) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n1267), .CK(clk), .RN(n2339), .Q(
sel_mux_2_reg[0]), .QN(n2230) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n591), .CK(clk), .RN(n2314), .Q(
d_ff2_X[53]), .QN(n2228) );
DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n564), .Q(cordic_FSM_state_reg[1]), .QN(n2222) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1072), .CK(clk), .RN(n2358), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1070), .CK(clk), .RN(n2358), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1068), .CK(clk), .RN(n2358), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1066), .CK(clk), .RN(n2363), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1064), .CK(clk), .RN(n2363), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1062), .CK(clk), .RN(n2362), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1060), .CK(clk), .RN(n2359), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1058), .CK(clk), .RN(n2365), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1056), .CK(clk), .RN(n2364), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1054), .CK(clk), .RN(n2361), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1052), .CK(clk), .RN(n2365), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1050), .CK(clk), .RN(n2364), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1048), .CK(clk), .RN(n2361), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1046), .CK(clk), .RN(n2363), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1044), .CK(clk), .RN(n2362), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1042), .CK(clk), .RN(n2359), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1040), .CK(clk), .RN(n2362), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1038), .CK(clk), .RN(n2359), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1036), .CK(clk), .RN(n2363), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1034), .CK(clk), .RN(n2362), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1032), .CK(clk), .RN(n2365), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1030), .CK(clk), .RN(n2360), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1028), .CK(clk), .RN(n2308), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1026), .CK(clk), .RN(n1506), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1024), .CK(clk), .RN(n1507), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1022), .CK(clk), .RN(n2308), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1020), .CK(clk), .RN(n2360), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1018), .CK(clk), .RN(n2308), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1016), .CK(clk), .RN(n2337), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1014), .CK(clk), .RN(n2338), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1012), .CK(clk), .RN(n1488), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1010), .CK(clk), .RN(n2355), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n1008), .CK(clk), .RN(n1501), .Q(
data_output[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n1006), .CK(clk), .RN(n2351), .Q(
data_output[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n1004), .CK(clk), .RN(n2352), .Q(
data_output[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n1002), .CK(clk), .RN(n2353), .Q(
data_output[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n1000), .CK(clk), .RN(n2355), .Q(
data_output[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n998), .CK(clk), .RN(n2350), .Q(
data_output[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n996), .CK(clk), .RN(n2350), .Q(
data_output[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n994), .CK(clk), .RN(n2341), .Q(
data_output[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n992), .CK(clk), .RN(n1502), .Q(
data_output[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n990), .CK(clk), .RN(n1502), .Q(
data_output[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n988), .CK(clk), .RN(n2327), .Q(
data_output[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n986), .CK(clk), .RN(n2353), .Q(
data_output[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n984), .CK(clk), .RN(n2355), .Q(
data_output[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n982), .CK(clk), .RN(n1510), .Q(
data_output[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n980), .CK(clk), .RN(n2357), .Q(
data_output[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n978), .CK(clk), .RN(n1502), .Q(
data_output[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n976), .CK(clk), .RN(n1493), .Q(
data_output[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n974), .CK(clk), .RN(n1489), .Q(
data_output[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n972), .CK(clk), .RN(n2357), .Q(
data_output[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n970), .CK(clk), .RN(n2351), .Q(
data_output[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n968), .CK(clk), .RN(n2352), .Q(
data_output[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n966), .CK(clk), .RN(n2343), .Q(
data_output[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n964), .CK(clk), .RN(n1502), .Q(
data_output[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n962), .CK(clk), .RN(n2339), .Q(
data_output[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n960), .CK(clk), .RN(n1489), .Q(
data_output[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n958), .CK(clk), .RN(n2357), .Q(
data_output[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n956), .CK(clk), .RN(n2351), .Q(
data_output[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n954), .CK(clk), .RN(n2356), .Q(
data_output[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n952), .CK(clk), .RN(n2296), .Q(
data_output[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n950), .CK(clk), .RN(n2294), .Q(
data_output[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n948), .CK(clk), .RN(n2313), .Q(
data_output[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n946), .CK(clk), .RN(n2296), .Q(
data_output[63]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n589), .CK(clk), .RN(n2317), .Q(
d_ff2_X[55]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n585), .CK(clk), .RN(n2294), .Q(
d_ff2_X[59]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n587), .CK(clk), .RN(n2313), .Q(
d_ff2_X[57]) );
DFFRX4TS cordic_FSM_state_reg_reg_3_ ( .D(n1345), .CK(clk), .RN(n564), .Q(
cordic_FSM_state_reg[3]), .QN(n2229) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n583), .CK(clk), .RN(n2296), .Q(
d_ff2_X[61]) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n1266), .CK(clk), .RN(n2342), .Q(
sel_mux_2_reg[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n590), .CK(clk), .RN(n2334), .Q(
d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n588), .CK(clk), .RN(n2335), .Q(
d_ff2_X[56]), .QN(n1481) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n719), .CK(clk), .RN(n2301), .Q(
d_ff2_Y[53]), .QN(n1480) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n718), .CK(clk), .RN(n1493), .Q(
d_ff2_Y[54]) );
DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n1268), .CK(clk), .RN(n2343), .Q(
sel_mux_1_reg) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n826), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[63]) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1335), .CK(clk), .RN(n2350), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n2238) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n582), .CK(clk), .RN(n2323), .Q(
d_ff2_X[62]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n1269), .CK(clk), .RN(n1508), .Q(
sel_mux_3_reg) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n1342), .CK(clk), .RN(n1510), .Q(
cont_var_out[1]), .QN(n1482) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n1336), .CK(clk), .RN(n2341), .Q(
d_ff1_operation_out), .QN(n2224) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n698), .CK(clk), .RN(n2300), .Q(
d_ff2_Y[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n722), .CK(clk), .RN(n2300), .Q(
d_ff2_Y[51]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n724), .CK(clk), .RN(n2324), .Q(
d_ff2_Y[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n726), .CK(clk), .RN(n2326), .Q(
d_ff2_Y[49]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n728), .CK(clk), .RN(n2328), .Q(
d_ff2_Y[48]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n730), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[47]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n732), .CK(clk), .RN(n2311), .Q(
d_ff2_Y[46]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n734), .CK(clk), .RN(n2310), .Q(
d_ff2_Y[45]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n736), .CK(clk), .RN(n2328), .Q(
d_ff2_Y[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n738), .CK(clk), .RN(n2330), .Q(
d_ff2_Y[43]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n740), .CK(clk), .RN(n1511), .Q(
d_ff2_Y[42]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n742), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[41]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n744), .CK(clk), .RN(n2311), .Q(
d_ff2_Y[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n746), .CK(clk), .RN(n2310), .Q(
d_ff2_Y[39]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n748), .CK(clk), .RN(n2311), .Q(
d_ff2_Y[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n750), .CK(clk), .RN(n2329), .Q(
d_ff2_Y[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n752), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[36]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n754), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[35]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n756), .CK(clk), .RN(n2328), .Q(
d_ff2_Y[34]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n758), .CK(clk), .RN(n2310), .Q(
d_ff2_Y[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n760), .CK(clk), .RN(n2311), .Q(
d_ff2_Y[32]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n762), .CK(clk), .RN(n2310), .Q(
d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n764), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n766), .CK(clk), .RN(n2328), .Q(
d_ff2_Y[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n768), .CK(clk), .RN(n2332), .Q(
d_ff2_Y[28]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n770), .CK(clk), .RN(n2331), .Q(
d_ff2_Y[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n772), .CK(clk), .RN(n2304), .Q(
d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n774), .CK(clk), .RN(n2332), .Q(
d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n776), .CK(clk), .RN(n2331), .Q(
d_ff2_Y[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n2332), .Q(
d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n780), .CK(clk), .RN(n2304), .Q(
d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n782), .CK(clk), .RN(n2331), .Q(
d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n784), .CK(clk), .RN(n2304), .Q(
d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n786), .CK(clk), .RN(n2303), .Q(
d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n788), .CK(clk), .RN(n2294), .Q(
d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n790), .CK(clk), .RN(n2313), .Q(
d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n792), .CK(clk), .RN(n2296), .Q(
d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n794), .CK(clk), .RN(n2312), .Q(
d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n796), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n798), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n800), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n802), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n804), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n806), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n808), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n810), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n812), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n814), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n816), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n818), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n820), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n822), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n824), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n598), .CK(clk), .RN(n1513), .Q(
d_ff2_X[49]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n600), .CK(clk), .RN(n2315), .Q(
d_ff2_X[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n604), .CK(clk), .RN(n2314), .Q(
d_ff2_X[46]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n606), .CK(clk), .RN(n1514), .Q(
d_ff2_X[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n610), .CK(clk), .RN(n2335), .Q(
d_ff2_X[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n612), .CK(clk), .RN(n2333), .Q(
d_ff2_X[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n614), .CK(clk), .RN(n1514), .Q(
d_ff2_X[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n618), .CK(clk), .RN(n1514), .Q(
d_ff2_X[39]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n624), .CK(clk), .RN(n2333), .Q(
d_ff2_X[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n626), .CK(clk), .RN(n2317), .Q(
d_ff2_X[35]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n628), .CK(clk), .RN(n2318), .Q(
d_ff2_X[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n632), .CK(clk), .RN(n2319), .Q(
d_ff2_X[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n634), .CK(clk), .RN(n2298), .Q(
d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n638), .CK(clk), .RN(n2319), .Q(
d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n640), .CK(clk), .RN(n2298), .Q(
d_ff2_X[28]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n644), .CK(clk), .RN(n2299), .Q(
d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n648), .CK(clk), .RN(n1494), .Q(
d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n658), .CK(clk), .RN(n2321), .Q(
d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n668), .CK(clk), .RN(n2321), .Q(
d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n670), .CK(clk), .RN(n2321), .Q(
d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n674), .CK(clk), .RN(n2321), .Q(
d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n678), .CK(clk), .RN(n2323), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n680), .CK(clk), .RN(n2323), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n682), .CK(clk), .RN(n2323), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n684), .CK(clk), .RN(n2323), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n690), .CK(clk), .RN(n2302), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n696), .CK(clk), .RN(n2320), .Q(
d_ff2_X[0]) );
DFFRX1TS d_ff4_Xn_Q_reg_60_ ( .D(n1077), .CK(clk), .RN(n2312), .Q(
d_ff_Xn[60]) );
DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n1079), .CK(clk), .RN(n2357), .Q(
d_ff_Xn[58]) );
DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n1081), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[56]) );
DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n1083), .CK(clk), .RN(n2342), .Q(
d_ff_Xn[54]) );
DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n1084), .CK(clk), .RN(n2351), .Q(
d_ff_Xn[53]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n602), .CK(clk), .RN(n2334), .Q(
d_ff2_X[47]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n608), .CK(clk), .RN(n2316), .Q(
d_ff2_X[44]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n616), .CK(clk), .RN(n2316), .Q(
d_ff2_X[40]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n620), .CK(clk), .RN(n2316), .Q(
d_ff2_X[38]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n622), .CK(clk), .RN(n2335), .Q(
d_ff2_X[37]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n630), .CK(clk), .RN(n2299), .Q(
d_ff2_X[33]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n636), .CK(clk), .RN(n2318), .Q(
d_ff2_X[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n642), .CK(clk), .RN(n2318), .Q(
d_ff2_X[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n646), .CK(clk), .RN(n2319), .Q(
d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n2325), .Q(
d_ff2_X[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n2325), .Q(
d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n2302), .Q(
d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n656), .CK(clk), .RN(n2320), .Q(
d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n660), .CK(clk), .RN(n2321), .Q(
d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n662), .CK(clk), .RN(n2321), .Q(
d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n664), .CK(clk), .RN(n2321), .Q(
d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n666), .CK(clk), .RN(n2321), .Q(
d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n672), .CK(clk), .RN(n2321), .Q(
d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n676), .CK(clk), .RN(n2321), .Q(
d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n686), .CK(clk), .RN(n2323), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n688), .CK(clk), .RN(n2301), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n692), .CK(clk), .RN(n1494), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n694), .CK(clk), .RN(n2324), .Q(
d_ff2_X[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n1074), .CK(clk), .RN(n2312), .Q(
d_ff_Xn[63]) );
DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n1085), .CK(clk), .RN(n2352), .Q(
d_ff_Xn[52]) );
DFFRX1TS d_ff4_Xn_Q_reg_51_ ( .D(n1086), .CK(clk), .RN(n2353), .Q(
d_ff_Xn[51]) );
DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n1087), .CK(clk), .RN(n1494), .Q(
d_ff_Xn[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n717), .CK(clk), .RN(n2320), .Q(
d_ff2_Y[55]), .QN(n2232) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n713), .CK(clk), .RN(n2302), .Q(
d_ff2_Y[59]), .QN(n2235) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n715), .CK(clk), .RN(n2301), .Q(
d_ff2_Y[57]), .QN(n2233) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n711), .CK(clk), .RN(n2325), .Q(
d_ff2_Y[61]), .QN(n2236) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n942), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n897), .CK(clk), .RN(n2307), .Q(
d_ff3_LUT_out[48]) );
DFFRX4TS cont_iter_count_reg_2_ ( .D(n1339), .CK(clk), .RN(n2350), .Q(
cont_iter_out[2]), .QN(n2227) );
DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n1090), .CK(clk), .RN(n2366), .Q(
d_ff_Xn[47]) );
DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n1100), .CK(clk), .RN(n2354), .Q(
d_ff_Xn[37]) );
DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n1099), .CK(clk), .RN(n2354), .Q(
d_ff_Xn[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n1098), .CK(clk), .RN(n2354), .Q(
d_ff_Xn[39]) );
DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n1097), .CK(clk), .RN(n2354), .Q(
d_ff_Xn[40]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1127), .CK(clk), .RN(n2365), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1128), .CK(clk), .RN(n2361), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1129), .CK(clk), .RN(n2360), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1130), .CK(clk), .RN(n1506), .Q(d_ff_Xn[7])
);
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n1334), .CK(clk), .RN(n1508), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n2226) );
DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n1082), .CK(clk), .RN(n2366), .Q(
d_ff_Xn[55]) );
DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n1080), .CK(clk), .RN(n1510), .Q(
d_ff_Xn[57]) );
DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n1078), .CK(clk), .RN(n2352), .Q(
d_ff_Xn[59]) );
DFFRX1TS d_ff4_Xn_Q_reg_61_ ( .D(n1076), .CK(clk), .RN(n2296), .Q(
d_ff_Xn[61]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1137), .CK(clk), .RN(n2348), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1134), .CK(clk), .RN(n2358), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1131), .CK(clk), .RN(n2362), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1126), .CK(clk), .RN(n2364), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1124), .CK(clk), .RN(n2308), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1123), .CK(clk), .RN(n2363), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1118), .CK(clk), .RN(n2359), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1113), .CK(clk), .RN(n1507), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1111), .CK(clk), .RN(n2364), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1109), .CK(clk), .RN(n2338), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1108), .CK(clk), .RN(n2336), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n1106), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n1105), .CK(clk), .RN(n2320), .Q(
d_ff_Xn[32]) );
DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n1103), .CK(clk), .RN(n2357), .Q(
d_ff_Xn[34]) );
DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n1102), .CK(clk), .RN(n2355), .Q(
d_ff_Xn[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n1101), .CK(clk), .RN(n2352), .Q(
d_ff_Xn[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n1096), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[41]) );
DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n1095), .CK(clk), .RN(n2325), .Q(
d_ff_Xn[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n1094), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[43]) );
DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n1092), .CK(clk), .RN(n2357), .Q(
d_ff_Xn[45]) );
DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n1091), .CK(clk), .RN(n2355), .Q(
d_ff_Xn[46]) );
DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n1089), .CK(clk), .RN(n2301), .Q(
d_ff_Xn[48]) );
DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n1088), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1136), .CK(clk), .RN(n2358), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1135), .CK(clk), .RN(n2358), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1133), .CK(clk), .RN(n2363), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1132), .CK(clk), .RN(n2359), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1125), .CK(clk), .RN(n1506), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1122), .CK(clk), .RN(n2359), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1121), .CK(clk), .RN(n2362), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1120), .CK(clk), .RN(n2362), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1119), .CK(clk), .RN(n2363), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1117), .CK(clk), .RN(n2365), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1116), .CK(clk), .RN(n2364), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1115), .CK(clk), .RN(n1506), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1114), .CK(clk), .RN(n2308), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1112), .CK(clk), .RN(n2365), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1110), .CK(clk), .RN(n1506), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1107), .CK(clk), .RN(n2338), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n1104), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[33]) );
DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n1093), .CK(clk), .RN(n2352), .Q(
d_ff_Xn[44]) );
DFFRX1TS d_ff4_Xn_Q_reg_62_ ( .D(n1075), .CK(clk), .RN(n2312), .Q(
d_ff_Xn[62]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n596), .CK(clk), .RN(n2315), .Q(
d_ff2_X[50]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n594), .CK(clk), .RN(n1513), .Q(
d_ff2_X[51]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n570), .CK(clk), .RN(n2312), .Q(
d_ff2_X[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_52_ ( .D(n720), .CK(clk), .RN(n2300), .Q(
d_ff2_Y[52]), .QN(n2234) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(n586), .CK(clk), .RN(n2313), .Q(
d_ff2_X[58]), .QN(n1483) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(n584), .CK(clk), .RN(n2294), .Q(
d_ff2_X[60]), .QN(n1485) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n930), .CK(clk), .RN(n2310), .Q(
d_ff3_LUT_out[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n832), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[57]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n830), .CK(clk), .RN(n2319), .Q(
d_ff2_Z[59]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n828), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[61]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n827), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[62]) );
DFFRX1TS d_ff5_Q_reg_63_ ( .D(n947), .CK(clk), .RN(n2313), .Q(
data_output2_63_) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n888), .CK(clk), .RN(n2332), .Q(
d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n887), .CK(clk), .RN(n2331), .Q(
d_ff2_Z[2]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n886), .CK(clk), .RN(n2304), .Q(
d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n885), .CK(clk), .RN(n2332), .Q(
d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n884), .CK(clk), .RN(n2303), .Q(
d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n883), .CK(clk), .RN(n2307), .Q(
d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n882), .CK(clk), .RN(n2322), .Q(
d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n881), .CK(clk), .RN(n2306), .Q(
d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n880), .CK(clk), .RN(n2303), .Q(
d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n879), .CK(clk), .RN(n2307), .Q(
d_ff2_Z[10]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n878), .CK(clk), .RN(n2322), .Q(
d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n877), .CK(clk), .RN(n2306), .Q(
d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n876), .CK(clk), .RN(n2303), .Q(
d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n875), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n874), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n873), .CK(clk), .RN(n2320), .Q(
d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n872), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n871), .CK(clk), .RN(n2324), .Q(
d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n2320), .Q(
d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n869), .CK(clk), .RN(n2325), .Q(
d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n868), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n867), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n866), .CK(clk), .RN(n2302), .Q(
d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n865), .CK(clk), .RN(n2325), .Q(
d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n864), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n863), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[26]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n862), .CK(clk), .RN(n2324), .Q(
d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n861), .CK(clk), .RN(n2301), .Q(
d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n860), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n859), .CK(clk), .RN(n2302), .Q(
d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n858), .CK(clk), .RN(n2302), .Q(
d_ff2_Z[31]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n857), .CK(clk), .RN(n2325), .Q(
d_ff2_Z[32]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n856), .CK(clk), .RN(n2324), .Q(
d_ff2_Z[33]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n855), .CK(clk), .RN(n2324), .Q(
d_ff2_Z[34]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n854), .CK(clk), .RN(n2301), .Q(
d_ff2_Z[35]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n853), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[36]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n852), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[37]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n851), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[38]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n850), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[39]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n849), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[40]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n848), .CK(clk), .RN(n2320), .Q(
d_ff2_Z[41]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n847), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[42]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n846), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[43]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n845), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[44]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n844), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[45]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n843), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[46]) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n1344), .CK(clk), .RN(n564), .Q(
cordic_FSM_state_reg[2]), .QN(n2225) );
DFFRX1TS cont_iter_count_reg_1_ ( .D(n1340), .CK(clk), .RN(n1509), .Q(n1477),
.QN(n1479) );
DFFRXLTS d_ff5_Q_reg_37_ ( .D(n999), .CK(clk), .RN(n2354), .Q(
sign_inv_out[37]) );
DFFRXLTS d_ff5_Q_reg_38_ ( .D(n997), .CK(clk), .RN(n2354), .Q(
sign_inv_out[38]) );
DFFRXLTS d_ff5_Q_reg_39_ ( .D(n995), .CK(clk), .RN(n2354), .Q(
sign_inv_out[39]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n1055), .CK(clk), .RN(n2308), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n1057), .CK(clk), .RN(n2364), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n1059), .CK(clk), .RN(n1507), .Q(
sign_inv_out[7]) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n1341), .CK(clk), .RN(n2339), .Q(
cont_iter_out[0]), .QN(n1484) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_52_ ( .D(n592), .CK(clk), .RN(n2333), .Q(
d_ff2_X[52]) );
DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n1343), .CK(clk), .RN(n564), .Q(
cordic_FSM_state_reg[0]), .QN(n2223) );
AOI222X1TS U1472 ( .A0(n1844), .A1(d_ff2_Z[60]), .B0(n1736), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n1842), .Y(n1826) );
AOI222X1TS U1473 ( .A0(n1837), .A1(d_ff2_Z[56]), .B0(n1736), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n1842), .Y(n1832) );
AOI222X1TS U1474 ( .A0(n1844), .A1(d_ff2_Z[58]), .B0(n1683), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n1840), .Y(n1830) );
AOI32X1TS U1475 ( .A0(n2064), .A1(n2089), .A2(n2195), .B0(d_ff3_LUT_out[0]),
.B1(n2044), .Y(n2024) );
AOI222X1TS U1476 ( .A0(n1837), .A1(d_ff2_Z[55]), .B0(n1821), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n1840), .Y(n1838) );
AOI222X1TS U1477 ( .A0(n1837), .A1(d_ff2_Z[52]), .B0(n1719), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n1817), .Y(n1706) );
AOI222X1TS U1478 ( .A0(n1837), .A1(d_ff2_Z[53]), .B0(n1719), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n1817), .Y(n1704) );
AOI222X1TS U1479 ( .A0(d_ff2_Z[54]), .A1(n1789), .B0(d_ff2_Y[54]), .B1(n1497), .C0(d_ff2_X[54]), .C1(n1889), .Y(n1790) );
AOI222X1TS U1480 ( .A0(d_ff2_Z[51]), .A1(n1789), .B0(d_ff2_Y[51]), .B1(n1497), .C0(d_ff2_X[51]), .C1(n1889), .Y(n1788) );
AOI222X1TS U1481 ( .A0(d_ff2_Z[0]), .A1(n1789), .B0(d_ff2_Y[0]), .B1(n1887),
.C0(d_ff2_X[0]), .C1(n1889), .Y(n1785) );
AOI222X1TS U1482 ( .A0(d_ff2_Z[47]), .A1(n1789), .B0(d_ff2_Y[47]), .B1(n1782), .C0(d_ff2_X[47]), .C1(n1889), .Y(n1783) );
AOI222X1TS U1483 ( .A0(d_ff2_Z[48]), .A1(n1789), .B0(d_ff2_Y[48]), .B1(n1871), .C0(d_ff2_X[48]), .C1(n1889), .Y(n1787) );
AOI222X1TS U1484 ( .A0(d_ff2_Z[49]), .A1(n1789), .B0(d_ff2_Y[49]), .B1(n1871), .C0(d_ff2_X[49]), .C1(n1889), .Y(n1784) );
AOI222X1TS U1485 ( .A0(d_ff2_Z[50]), .A1(n1789), .B0(d_ff2_Y[50]), .B1(n1871), .C0(d_ff2_X[50]), .C1(n1889), .Y(n1786) );
AOI222X1TS U1486 ( .A0(d_ff3_LUT_out[50]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[50]), .C0(n1886), .C1(d_ff3_sh_y_out[50]), .Y(n1888) );
AOI222X1TS U1487 ( .A0(d_ff3_LUT_out[47]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[47]), .C0(n1886), .C1(d_ff3_sh_y_out[47]), .Y(n1884) );
AOI222X1TS U1488 ( .A0(d_ff3_LUT_out[43]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[43]), .C0(n1886), .C1(d_ff3_sh_y_out[43]), .Y(n1883) );
AOI222X1TS U1489 ( .A0(d_ff3_LUT_out[45]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[45]), .C0(n1886), .C1(d_ff3_sh_y_out[45]), .Y(n1882) );
AOI222X1TS U1490 ( .A0(d_ff3_LUT_out[55]), .A1(n1892), .B0(
d_ff3_sh_y_out[55]), .B1(n1889), .C0(d_ff3_sh_x_out[55]), .C1(n1806),
.Y(n1890) );
AOI222X1TS U1491 ( .A0(d_ff3_LUT_out[54]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[54]), .C0(n1889), .C1(d_ff3_sh_y_out[54]), .Y(n1885) );
AOI222X1TS U1492 ( .A0(d_ff3_LUT_out[1]), .A1(n1873), .B0(n1893), .B1(
d_ff3_sh_x_out[1]), .C0(n1894), .C1(d_ff3_sh_y_out[1]), .Y(n1864) );
AOI222X1TS U1493 ( .A0(d_ff3_LUT_out[6]), .A1(n1873), .B0(n1498), .B1(
d_ff3_sh_x_out[6]), .C0(n1894), .C1(d_ff3_sh_y_out[6]), .Y(n1869) );
AOI222X1TS U1494 ( .A0(d_ff3_LUT_out[7]), .A1(n1873), .B0(n1782), .B1(
d_ff3_sh_x_out[7]), .C0(n1894), .C1(d_ff3_sh_y_out[7]), .Y(n1872) );
AOI222X1TS U1495 ( .A0(d_ff3_LUT_out[5]), .A1(n1873), .B0(n1893), .B1(
d_ff3_sh_x_out[5]), .C0(n1894), .C1(d_ff3_sh_y_out[5]), .Y(n1870) );
AOI222X1TS U1496 ( .A0(d_ff3_LUT_out[0]), .A1(n1873), .B0(n1498), .B1(
d_ff3_sh_x_out[0]), .C0(n1894), .C1(d_ff3_sh_y_out[0]), .Y(n1862) );
AOI222X1TS U1497 ( .A0(d_ff3_LUT_out[9]), .A1(n1873), .B0(n1782), .B1(
d_ff3_sh_x_out[9]), .C0(n1867), .C1(d_ff3_sh_y_out[9]), .Y(n1868) );
AOI222X1TS U1498 ( .A0(d_ff3_LUT_out[39]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[39]), .C0(n1886), .C1(d_ff3_sh_y_out[39]), .Y(n1849) );
AOI222X1TS U1499 ( .A0(d_ff3_LUT_out[27]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[27]), .C0(n1812), .C1(d_ff3_sh_y_out[27]), .Y(n1815) );
AOI222X1TS U1500 ( .A0(d_ff3_LUT_out[25]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[25]), .C0(n1812), .C1(d_ff3_sh_y_out[25]), .Y(n1808) );
AOI222X1TS U1501 ( .A0(d_ff3_LUT_out[29]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[29]), .C0(n1851), .C1(d_ff3_sh_y_out[29]), .Y(n1767) );
AOI222X1TS U1502 ( .A0(d_ff3_LUT_out[33]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[33]), .C0(n1851), .C1(d_ff3_sh_y_out[33]), .Y(n1853) );
AOI222X1TS U1503 ( .A0(d_ff3_LUT_out[26]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[26]), .C0(n1812), .C1(d_ff3_sh_y_out[26]), .Y(n1805) );
AOI222X1TS U1504 ( .A0(d_ff2_Z[9]), .A1(n1881), .B0(d_ff2_Y[9]), .B1(n1854),
.C0(d_ff2_X[9]), .C1(n1910), .Y(n1855) );
AOI222X1TS U1505 ( .A0(d_ff3_LUT_out[14]), .A1(n1810), .B0(n1498), .B1(
d_ff3_sh_x_out[14]), .C0(n1867), .C1(d_ff3_sh_y_out[14]), .Y(n1796) );
AOI222X1TS U1506 ( .A0(d_ff3_LUT_out[11]), .A1(n1810), .B0(n1893), .B1(
d_ff3_sh_x_out[11]), .C0(n1867), .C1(d_ff3_sh_y_out[11]), .Y(n1811) );
INVX2TS U1507 ( .A(n1906), .Y(n1727) );
NAND2X1TS U1508 ( .A(n2139), .B(n2138), .Y(n2142) );
CMPR32X2TS U1509 ( .A(d_ff2_Y[54]), .B(n1491), .C(n1534), .CO(n1550), .S(
n1535) );
CMPR32X2TS U1510 ( .A(n1491), .B(d_ff2_X[54]), .C(n2193), .CO(n2197), .S(
n2194) );
INVX4TS U1511 ( .A(cont_iter_out[0]), .Y(n2188) );
NOR2X1TS U1512 ( .A(sel_mux_1_reg), .B(n2187), .Y(n1664) );
AOI31XLTS U1513 ( .A0(n1505), .A1(n1678), .A2(n2227), .B0(n1937), .Y(n1679)
);
NAND2BX1TS U1514 ( .AN(n2050), .B(n2083), .Y(n2079) );
NAND2X2TS U1515 ( .A(n2141), .B(n2127), .Y(n2144) );
AO22XLTS U1516 ( .A0(n2221), .A1(n2140), .B0(n2152), .B1(d_ff3_sh_y_out[56]),
.Y(n705) );
AO22XLTS U1517 ( .A0(n2204), .A1(n2199), .B0(n2220), .B1(d_ff3_sh_x_out[56]),
.Y(n577) );
AOI222X1TS U1518 ( .A0(n2187), .A1(d_ff2_Z[3]), .B0(n1821), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n2118), .Y(n1737) );
AOI222X1TS U1519 ( .A0(n2187), .A1(d_ff2_Z[4]), .B0(n1821), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n2118), .Y(n1741) );
AO22XLTS U1520 ( .A0(n2119), .A1(d_ff2_Y[42]), .B0(n2117), .B1(
d_ff3_sh_y_out[42]), .Y(n739) );
AO22XLTS U1521 ( .A0(n2119), .A1(d_ff2_Y[40]), .B0(n2117), .B1(
d_ff3_sh_y_out[40]), .Y(n743) );
AO22XLTS U1522 ( .A0(n2110), .A1(d_ff2_Y[18]), .B0(n2109), .B1(
d_ff3_sh_y_out[18]), .Y(n787) );
AO22XLTS U1523 ( .A0(n2110), .A1(d_ff2_Y[23]), .B0(n2109), .B1(
d_ff3_sh_y_out[23]), .Y(n777) );
AO22XLTS U1524 ( .A0(n2115), .A1(d_ff2_Y[38]), .B0(n2117), .B1(
d_ff3_sh_y_out[38]), .Y(n747) );
AO22XLTS U1525 ( .A0(n2115), .A1(d_ff2_Y[37]), .B0(n2117), .B1(
d_ff3_sh_y_out[37]), .Y(n749) );
AO22XLTS U1526 ( .A0(n2115), .A1(d_ff2_Y[36]), .B0(n2117), .B1(
d_ff3_sh_y_out[36]), .Y(n751) );
AO22XLTS U1527 ( .A0(n2115), .A1(d_ff2_Y[35]), .B0(n2117), .B1(
d_ff3_sh_y_out[35]), .Y(n753) );
AOI222X1TS U1528 ( .A0(n2187), .A1(d_ff2_Z[5]), .B0(n1736), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n2118), .Y(n1686) );
AO22XLTS U1529 ( .A0(n2104), .A1(d_ff2_Y[2]), .B0(n2103), .B1(
d_ff3_sh_y_out[2]), .Y(n819) );
AO22XLTS U1530 ( .A0(n2110), .A1(d_ff2_Y[24]), .B0(n2109), .B1(
d_ff3_sh_y_out[24]), .Y(n775) );
AO22XLTS U1531 ( .A0(n2104), .A1(d_ff2_Y[4]), .B0(n2103), .B1(
d_ff3_sh_y_out[4]), .Y(n815) );
AO22XLTS U1532 ( .A0(n2110), .A1(d_ff2_Y[22]), .B0(n2109), .B1(
d_ff3_sh_y_out[22]), .Y(n779) );
AO22XLTS U1533 ( .A0(n2110), .A1(d_ff2_Y[21]), .B0(n2109), .B1(
d_ff3_sh_y_out[21]), .Y(n781) );
AO22XLTS U1534 ( .A0(n2221), .A1(d_ff2_Y[20]), .B0(n2109), .B1(
d_ff3_sh_y_out[20]), .Y(n783) );
AO22XLTS U1535 ( .A0(n2115), .A1(d_ff2_Y[16]), .B0(n2109), .B1(
d_ff3_sh_y_out[16]), .Y(n791) );
AO22XLTS U1536 ( .A0(n2107), .A1(d_ff2_Y[17]), .B0(n2109), .B1(
d_ff3_sh_y_out[17]), .Y(n789) );
AO22XLTS U1537 ( .A0(n2206), .A1(n2080), .B0(n2103), .B1(d_ff3_LUT_out[37]),
.Y(n908) );
AO22XLTS U1538 ( .A0(n2104), .A1(n2101), .B0(n2103), .B1(d_ff3_LUT_out[56]),
.Y(n890) );
AO22XLTS U1539 ( .A0(d_ff_Yn[46]), .A1(n2186), .B0(d_ff2_Y[46]), .B1(n2218),
.Y(n732) );
AO22XLTS U1540 ( .A0(d_ff_Yn[47]), .A1(n2186), .B0(d_ff2_Y[47]), .B1(n2218),
.Y(n730) );
AO22XLTS U1541 ( .A0(n2104), .A1(n2077), .B0(n2103), .B1(d_ff3_LUT_out[24]),
.Y(n921) );
AO22XLTS U1542 ( .A0(d_ff_Yn[48]), .A1(n2186), .B0(d_ff2_Y[48]), .B1(n2218),
.Y(n728) );
AO22XLTS U1543 ( .A0(d_ff_Yn[50]), .A1(n2186), .B0(d_ff2_Y[50]), .B1(n2155),
.Y(n724) );
AO22XLTS U1544 ( .A0(d_ff_Yn[49]), .A1(n2186), .B0(d_ff2_Y[49]), .B1(n2218),
.Y(n726) );
AO22XLTS U1545 ( .A0(n2204), .A1(n2192), .B0(n2220), .B1(d_ff3_sh_x_out[53]),
.Y(n580) );
AO22XLTS U1546 ( .A0(d_ff_Yn[22]), .A1(n2114), .B0(d_ff2_Y[22]), .B1(n2111),
.Y(n780) );
AO22XLTS U1547 ( .A0(d_ff_Yn[21]), .A1(n2114), .B0(d_ff2_Y[21]), .B1(n2111),
.Y(n782) );
AO22XLTS U1548 ( .A0(d_ff_Yn[23]), .A1(n2172), .B0(d_ff2_Y[23]), .B1(n2111),
.Y(n778) );
AO22XLTS U1549 ( .A0(d_ff_Yn[24]), .A1(n2172), .B0(d_ff2_Y[24]), .B1(n2111),
.Y(n776) );
AO22XLTS U1550 ( .A0(d_ff_Yn[25]), .A1(n2172), .B0(d_ff2_Y[25]), .B1(n2111),
.Y(n774) );
AO22XLTS U1551 ( .A0(n2110), .A1(d_ff2_Y[28]), .B0(n2113), .B1(
d_ff3_sh_y_out[28]), .Y(n767) );
AO22XLTS U1552 ( .A0(n2119), .A1(d_ff2_Y[30]), .B0(n2113), .B1(
d_ff3_sh_y_out[30]), .Y(n763) );
AO22XLTS U1553 ( .A0(n2115), .A1(d_ff2_Y[31]), .B0(n2113), .B1(
d_ff3_sh_y_out[31]), .Y(n761) );
AO22XLTS U1554 ( .A0(n2115), .A1(d_ff2_Y[32]), .B0(n2113), .B1(
d_ff3_sh_y_out[32]), .Y(n759) );
AO22XLTS U1555 ( .A0(n2115), .A1(d_ff2_Y[34]), .B0(n2113), .B1(
d_ff3_sh_y_out[34]), .Y(n755) );
INVX3TS U1556 ( .A(n2185), .Y(n1739) );
INVX3TS U1557 ( .A(n2131), .Y(n1819) );
NAND3X1TS U1558 ( .A(cont_iter_out[2]), .B(n2076), .C(n1496), .Y(n2071) );
INVX3TS U1559 ( .A(n2131), .Y(n1835) );
INVX3TS U1560 ( .A(n2131), .Y(n1817) );
NOR2X1TS U1561 ( .A(n2089), .B(d_ff3_LUT_out[55]), .Y(n1700) );
AOI222X1TS U1562 ( .A0(d_ff3_LUT_out[3]), .A1(n1873), .B0(n1498), .B1(
d_ff3_sh_x_out[3]), .C0(n1894), .C1(d_ff3_sh_y_out[3]), .Y(n1865) );
AO22XLTS U1563 ( .A0(d_ff_Xn[4]), .A1(n2168), .B0(d_ff2_X[4]), .B1(n2155),
.Y(n688) );
AO22XLTS U1564 ( .A0(d_ff_Xn[10]), .A1(n2168), .B0(d_ff2_X[10]), .B1(n2155),
.Y(n676) );
AO22XLTS U1565 ( .A0(d_ff_Yn[29]), .A1(n2112), .B0(d_ff2_Y[29]), .B1(n2111),
.Y(n766) );
AO22XLTS U1566 ( .A0(d_ff_Xn[5]), .A1(n2168), .B0(d_ff2_X[5]), .B1(n2155),
.Y(n686) );
AO22XLTS U1567 ( .A0(d_ff_Xn[2]), .A1(n2168), .B0(d_ff2_X[2]), .B1(n2155),
.Y(n692) );
AO22XLTS U1568 ( .A0(d_ff_Yn[32]), .A1(n2112), .B0(d_ff2_Y[32]), .B1(n2116),
.Y(n760) );
AO22XLTS U1569 ( .A0(d_ff_Xn[44]), .A1(n2168), .B0(d_ff2_X[44]), .B1(n2218),
.Y(n608) );
AO22XLTS U1570 ( .A0(d_ff_Yn[27]), .A1(n2112), .B0(d_ff2_Y[27]), .B1(n2111),
.Y(n770) );
AO22XLTS U1571 ( .A0(d_ff_Yn[35]), .A1(n2114), .B0(d_ff2_Y[35]), .B1(n2116),
.Y(n754) );
AO22XLTS U1572 ( .A0(d_ff_Xn[12]), .A1(n2168), .B0(d_ff2_X[12]), .B1(n2155),
.Y(n672) );
AO22XLTS U1573 ( .A0(d_ff_Yn[33]), .A1(n2114), .B0(d_ff2_Y[33]), .B1(n2116),
.Y(n758) );
AO22XLTS U1574 ( .A0(d_ff_Yn[31]), .A1(n2112), .B0(d_ff2_Y[31]), .B1(n2116),
.Y(n762) );
AO22XLTS U1575 ( .A0(d_ff_Yn[30]), .A1(n2112), .B0(d_ff2_Y[30]), .B1(n2111),
.Y(n764) );
AO22XLTS U1576 ( .A0(d_ff_Yn[28]), .A1(n2112), .B0(d_ff2_Y[28]), .B1(n2111),
.Y(n768) );
AO22XLTS U1577 ( .A0(d_ff_Yn[26]), .A1(n2112), .B0(d_ff2_Y[26]), .B1(n2111),
.Y(n772) );
AO22XLTS U1578 ( .A0(d_ff_Yn[34]), .A1(n2114), .B0(d_ff2_Y[34]), .B1(n2116),
.Y(n756) );
AO22X1TS U1579 ( .A0(n2101), .A1(n2231), .B0(n1476), .B1(n1989), .Y(n1900)
);
AOI222X1TS U1580 ( .A0(d_ff3_LUT_out[15]), .A1(n1810), .B0(n1498), .B1(
d_ff3_sh_x_out[15]), .C0(n1867), .C1(d_ff3_sh_y_out[15]), .Y(n1803) );
INVX2TS U1581 ( .A(n2153), .Y(n2213) );
INVX2TS U1582 ( .A(n2153), .Y(n2076) );
INVX1TS U1583 ( .A(n2082), .Y(n2054) );
INVX3TS U1584 ( .A(n2153), .Y(n2065) );
INVX3TS U1585 ( .A(n2153), .Y(n2089) );
NAND2XLTS U1586 ( .A(sel_mux_2_reg[1]), .B(n2366), .Y(n1545) );
NAND2X1TS U1587 ( .A(n2040), .B(n2188), .Y(n2037) );
CLKBUFX3TS U1588 ( .A(n1950), .Y(n1940) );
BUFX3TS U1589 ( .A(n1560), .Y(n1475) );
INVX3TS U1590 ( .A(n2176), .Y(n2187) );
INVX3TS U1591 ( .A(n1880), .Y(n1776) );
INVX3TS U1592 ( .A(n1880), .Y(n1852) );
NOR2X4TS U1593 ( .A(sel_mux_3_reg), .B(n1605), .Y(n1555) );
OR3X2TS U1594 ( .A(n2225), .B(n2229), .C(n1929), .Y(n2008) );
CLKINVX2TS U1595 ( .A(n1519), .Y(n2211) );
NAND3X2TS U1596 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]),
.C(n1932), .Y(n1605) );
OAI211X4TS U1597 ( .A0(n2032), .A1(n1682), .B0(n1681), .C0(n1680), .Y(n934)
);
INVX2TS U1598 ( .A(n2188), .Y(n2100) );
BUFX3TS U1599 ( .A(n1792), .Y(n1881) );
BUFX3TS U1600 ( .A(n1860), .Y(n1877) );
INVX2TS U1601 ( .A(cordic_FSM_state_reg[2]), .Y(n1486) );
NAND4BXLTS U1602 ( .AN(ack_cordic), .B(n1512), .C(cordic_FSM_state_reg[2]),
.D(n2222), .Y(n1934) );
NAND2X1TS U1603 ( .A(n2208), .B(n1485), .Y(n2210) );
NAND2X1TS U1604 ( .A(n2202), .B(n1483), .Y(n2205) );
NAND2X1TS U1605 ( .A(n1481), .B(n2198), .Y(n2200) );
NAND2X1TS U1606 ( .A(n2147), .B(n2146), .Y(n2150) );
AO22XLTS U1607 ( .A0(n2006), .A1(result_add_subt[62]), .B0(n2005), .B1(
d_ff_Xn[62]), .Y(n1075) );
AO22XLTS U1608 ( .A0(n2001), .A1(result_add_subt[44]), .B0(n1999), .B1(
d_ff_Xn[44]), .Y(n1093) );
AO22XLTS U1609 ( .A0(n1998), .A1(result_add_subt[33]), .B0(n1997), .B1(
d_ff_Xn[33]), .Y(n1104) );
AO22XLTS U1610 ( .A0(n1998), .A1(result_add_subt[30]), .B0(n1997), .B1(
d_ff_Xn[30]), .Y(n1107) );
AO22XLTS U1611 ( .A0(n1996), .A1(result_add_subt[27]), .B0(n1995), .B1(
d_ff_Xn[27]), .Y(n1110) );
AO22XLTS U1612 ( .A0(n1996), .A1(result_add_subt[23]), .B0(n1995), .B1(
d_ff_Xn[23]), .Y(n1114) );
AO22XLTS U1613 ( .A0(n1996), .A1(result_add_subt[22]), .B0(n1995), .B1(
d_ff_Xn[22]), .Y(n1115) );
AO22XLTS U1614 ( .A0(n1996), .A1(result_add_subt[21]), .B0(n1995), .B1(
d_ff_Xn[21]), .Y(n1116) );
AO22XLTS U1615 ( .A0(n1996), .A1(result_add_subt[20]), .B0(n1995), .B1(
d_ff_Xn[20]), .Y(n1117) );
AO22XLTS U1616 ( .A0(n1994), .A1(result_add_subt[18]), .B0(n1993), .B1(
d_ff_Xn[18]), .Y(n1119) );
AO22XLTS U1617 ( .A0(n1994), .A1(result_add_subt[17]), .B0(n1993), .B1(
d_ff_Xn[17]), .Y(n1120) );
AO22XLTS U1618 ( .A0(n1994), .A1(result_add_subt[16]), .B0(n1993), .B1(
d_ff_Xn[16]), .Y(n1121) );
AO22XLTS U1619 ( .A0(n1994), .A1(result_add_subt[15]), .B0(n1993), .B1(
d_ff_Xn[15]), .Y(n1122) );
AO22XLTS U1620 ( .A0(n1992), .A1(result_add_subt[4]), .B0(n2000), .B1(
d_ff_Xn[4]), .Y(n1133) );
AO22XLTS U1621 ( .A0(n1992), .A1(result_add_subt[2]), .B0(n2000), .B1(
d_ff_Xn[2]), .Y(n1135) );
AO22XLTS U1622 ( .A0(n1992), .A1(result_add_subt[1]), .B0(n2004), .B1(
d_ff_Xn[1]), .Y(n1136) );
AO22XLTS U1623 ( .A0(n2001), .A1(result_add_subt[49]), .B0(n2002), .B1(
d_ff_Xn[49]), .Y(n1088) );
AO22XLTS U1624 ( .A0(n2001), .A1(result_add_subt[48]), .B0(n1999), .B1(
d_ff_Xn[48]), .Y(n1089) );
AO22XLTS U1625 ( .A0(n2001), .A1(result_add_subt[46]), .B0(n1999), .B1(
d_ff_Xn[46]), .Y(n1091) );
AO22XLTS U1626 ( .A0(n2001), .A1(result_add_subt[45]), .B0(n1999), .B1(
d_ff_Xn[45]), .Y(n1092) );
AO22XLTS U1627 ( .A0(n2001), .A1(result_add_subt[43]), .B0(n1999), .B1(
d_ff_Xn[43]), .Y(n1094) );
AO22XLTS U1628 ( .A0(n2001), .A1(result_add_subt[42]), .B0(n1999), .B1(
d_ff_Xn[42]), .Y(n1095) );
AO22XLTS U1629 ( .A0(n2001), .A1(result_add_subt[41]), .B0(n1999), .B1(
d_ff_Xn[41]), .Y(n1096) );
AO22XLTS U1630 ( .A0(n1998), .A1(result_add_subt[36]), .B0(n1997), .B1(
d_ff_Xn[36]), .Y(n1101) );
AO22XLTS U1631 ( .A0(n1998), .A1(result_add_subt[35]), .B0(n1997), .B1(
d_ff_Xn[35]), .Y(n1102) );
AO22XLTS U1632 ( .A0(n1998), .A1(result_add_subt[34]), .B0(n1997), .B1(
d_ff_Xn[34]), .Y(n1103) );
AO22XLTS U1633 ( .A0(n1998), .A1(result_add_subt[32]), .B0(n1997), .B1(
d_ff_Xn[32]), .Y(n1105) );
AO22XLTS U1634 ( .A0(n1998), .A1(result_add_subt[31]), .B0(n1997), .B1(
d_ff_Xn[31]), .Y(n1106) );
AO22XLTS U1635 ( .A0(n1996), .A1(result_add_subt[29]), .B0(n1997), .B1(
d_ff_Xn[29]), .Y(n1108) );
AO22XLTS U1636 ( .A0(n1996), .A1(result_add_subt[28]), .B0(n1995), .B1(
d_ff_Xn[28]), .Y(n1109) );
AO22XLTS U1637 ( .A0(n1996), .A1(result_add_subt[26]), .B0(n1995), .B1(
d_ff_Xn[26]), .Y(n1111) );
AO22XLTS U1638 ( .A0(n1996), .A1(result_add_subt[24]), .B0(n1995), .B1(
d_ff_Xn[24]), .Y(n1113) );
AO22XLTS U1639 ( .A0(n1994), .A1(result_add_subt[19]), .B0(n1995), .B1(
d_ff_Xn[19]), .Y(n1118) );
AO22XLTS U1640 ( .A0(n1994), .A1(result_add_subt[14]), .B0(n1993), .B1(
d_ff_Xn[14]), .Y(n1123) );
AO22XLTS U1641 ( .A0(n1994), .A1(result_add_subt[13]), .B0(n1993), .B1(
d_ff_Xn[13]), .Y(n1124) );
AO22XLTS U1642 ( .A0(n1994), .A1(result_add_subt[11]), .B0(n1993), .B1(
d_ff_Xn[11]), .Y(n1126) );
AO22XLTS U1643 ( .A0(n1992), .A1(result_add_subt[6]), .B0(n2000), .B1(
d_ff_Xn[6]), .Y(n1131) );
AO22XLTS U1644 ( .A0(n1992), .A1(result_add_subt[3]), .B0(n2000), .B1(
d_ff_Xn[3]), .Y(n1134) );
AO22XLTS U1645 ( .A0(n1992), .A1(result_add_subt[0]), .B0(n2005), .B1(
d_ff_Xn[0]), .Y(n1137) );
AO22XLTS U1646 ( .A0(n2006), .A1(result_add_subt[61]), .B0(n2005), .B1(
d_ff_Xn[61]), .Y(n1076) );
AO22XLTS U1647 ( .A0(n2003), .A1(result_add_subt[59]), .B0(n2005), .B1(
d_ff_Xn[59]), .Y(n1078) );
AO22XLTS U1648 ( .A0(n2003), .A1(result_add_subt[57]), .B0(n2002), .B1(
d_ff_Xn[57]), .Y(n1080) );
AO22XLTS U1649 ( .A0(n2003), .A1(result_add_subt[55]), .B0(n2002), .B1(
d_ff_Xn[55]), .Y(n1082) );
AO22XLTS U1650 ( .A0(n1992), .A1(result_add_subt[7]), .B0(n2000), .B1(
d_ff_Xn[7]), .Y(n1130) );
AO22XLTS U1651 ( .A0(n1992), .A1(result_add_subt[8]), .B0(n2000), .B1(
d_ff_Xn[8]), .Y(n1129) );
AO22XLTS U1652 ( .A0(n1992), .A1(result_add_subt[9]), .B0(n1993), .B1(
d_ff_Xn[9]), .Y(n1128) );
AO22XLTS U1653 ( .A0(n1994), .A1(result_add_subt[10]), .B0(n1993), .B1(
d_ff_Xn[10]), .Y(n1127) );
AO22XLTS U1654 ( .A0(n2001), .A1(result_add_subt[40]), .B0(n1999), .B1(
d_ff_Xn[40]), .Y(n1097) );
AO22XLTS U1655 ( .A0(n2001), .A1(result_add_subt[47]), .B0(n1999), .B1(
d_ff_Xn[47]), .Y(n1090) );
AO22XLTS U1656 ( .A0(n2003), .A1(result_add_subt[50]), .B0(n2002), .B1(
d_ff_Xn[50]), .Y(n1087) );
AO22XLTS U1657 ( .A0(n2003), .A1(result_add_subt[52]), .B0(n2002), .B1(
d_ff_Xn[52]), .Y(n1085) );
AO22XLTS U1658 ( .A0(n2003), .A1(result_add_subt[53]), .B0(n2002), .B1(
d_ff_Xn[53]), .Y(n1084) );
AO22XLTS U1659 ( .A0(n2003), .A1(result_add_subt[54]), .B0(n2002), .B1(
d_ff_Xn[54]), .Y(n1083) );
AO22XLTS U1660 ( .A0(n2003), .A1(result_add_subt[56]), .B0(n2002), .B1(
d_ff_Xn[56]), .Y(n1081) );
AO22XLTS U1661 ( .A0(n2006), .A1(result_add_subt[60]), .B0(n2005), .B1(
d_ff_Xn[60]), .Y(n1077) );
AO22XLTS U1662 ( .A0(d_ff2_X[62]), .A1(n2187), .B0(d_ff_Xn[62]), .B1(n2186),
.Y(n582) );
AO22XLTS U1663 ( .A0(d_ff_Xn[52]), .A1(n2175), .B0(d_ff2_X[52]), .B1(n2174),
.Y(n592) );
CLKINVX3TS U1664 ( .A(n1880), .Y(n1813) );
BUFX3TS U1665 ( .A(n1727), .Y(n1770) );
OR2X2TS U1666 ( .A(n1991), .B(n1990), .Y(n2004) );
AOI32X1TS U1667 ( .A0(n2231), .A1(n2101), .A2(n1482), .B0(n1989), .B1(n1476),
.Y(n1991) );
BUFX3TS U1668 ( .A(n2120), .Y(n2170) );
CLKAND2X2TS U1669 ( .A(n2197), .B(d_ff2_X[55]), .Y(n2196) );
INVX2TS U1670 ( .A(d_ff_Yn[62]), .Y(n2132) );
INVX2TS U1671 ( .A(d_ff_Yn[61]), .Y(n2130) );
INVX2TS U1672 ( .A(d_ff_Yn[60]), .Y(n2129) );
INVX2TS U1673 ( .A(d_ff_Yn[59]), .Y(n2128) );
INVX2TS U1674 ( .A(d_ff_Yn[58]), .Y(n2126) );
INVX2TS U1675 ( .A(d_ff_Yn[56]), .Y(n2124) );
INVX2TS U1676 ( .A(d_ff_Yn[55]), .Y(n2123) );
INVX2TS U1677 ( .A(d_ff_Yn[53]), .Y(n2122) );
INVX2TS U1678 ( .A(d_ff_Yn[52]), .Y(n2121) );
INVX2TS U1679 ( .A(n1957), .Y(n1966) );
OAI21XLTS U1680 ( .A0(n1480), .A1(n1860), .B0(n1856), .Y(add_subt_dataA[53])
);
OAI21XLTS U1681 ( .A0(n2232), .A1(n1860), .B0(n1523), .Y(add_subt_dataA[55])
);
OAI21XLTS U1682 ( .A0(n2138), .A1(n1860), .B0(n1859), .Y(add_subt_dataA[56])
);
OAI21XLTS U1683 ( .A0(n2233), .A1(n1877), .B0(n1875), .Y(add_subt_dataA[57])
);
OAI21XLTS U1684 ( .A0(n2127), .A1(n1877), .B0(n1857), .Y(add_subt_dataA[58])
);
OAI21XLTS U1685 ( .A0(n2235), .A1(n1880), .B0(n1879), .Y(add_subt_dataA[59])
);
OAI21XLTS U1686 ( .A0(n2146), .A1(n1877), .B0(n1858), .Y(add_subt_dataA[60])
);
OAI21XLTS U1687 ( .A0(n2236), .A1(n1877), .B0(n1876), .Y(add_subt_dataA[61])
);
AOI222X1TS U1688 ( .A0(d_ff2_Z[63]), .A1(n1873), .B0(d_ff2_Y[63]), .B1(n1497), .C0(d_ff2_X[63]), .C1(n1889), .Y(n1874) );
OAI21XLTS U1689 ( .A0(n1938), .A1(n2078), .B0(n1658), .Y(n1340) );
AOI32X1TS U1690 ( .A0(n1928), .A1(n1927), .A2(n1926), .B0(n2223), .B1(n1927),
.Y(n1344) );
NAND4XLTS U1691 ( .A(n1512), .B(n2225), .C(n2101), .D(n1925), .Y(n1926) );
NAND4BXLTS U1692 ( .AN(n1935), .B(n1938), .C(n1934), .D(n1933), .Y(n1343) );
OAI31X1TS U1693 ( .A0(n1932), .A1(n1931), .A2(n2229), .B0(n2223), .Y(n1933)
);
NAND3BXLTS U1694 ( .AN(n2085), .B(n2045), .C(n2072), .Y(n930) );
AOI2BB2XLTS U1695 ( .B0(n1485), .B1(n1844), .A0N(d_ff_Xn[60]), .A1N(n2185),
.Y(n584) );
AOI2BB2XLTS U1696 ( .B0(n1483), .B1(n2105), .A0N(d_ff_Xn[58]), .A1N(n2181),
.Y(n586) );
AO22XLTS U1697 ( .A0(d_ff_Xn[63]), .A1(n2219), .B0(d_ff2_X[63]), .B1(n2218),
.Y(n570) );
AO22XLTS U1698 ( .A0(d_ff_Xn[51]), .A1(n2172), .B0(d_ff2_X[51]), .B1(n2174),
.Y(n594) );
AO22XLTS U1699 ( .A0(d_ff_Xn[50]), .A1(n2172), .B0(d_ff2_X[50]), .B1(n2174),
.Y(n596) );
AO22XLTS U1700 ( .A0(n1996), .A1(result_add_subt[25]), .B0(n1995), .B1(
d_ff_Xn[25]), .Y(n1112) );
AO22XLTS U1701 ( .A0(n1994), .A1(result_add_subt[12]), .B0(n1993), .B1(
d_ff_Xn[12]), .Y(n1125) );
AO22XLTS U1702 ( .A0(n1992), .A1(result_add_subt[5]), .B0(n2000), .B1(
d_ff_Xn[5]), .Y(n1132) );
AO22XLTS U1703 ( .A0(n1952), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1955),
.B1(shift_region_flag[1]), .Y(n1334) );
OAI21XLTS U1704 ( .A0(n2246), .A1(n1645), .B0(n1638), .Y(n1059) );
OAI21XLTS U1705 ( .A0(n2247), .A1(n1645), .B0(n1644), .Y(n1057) );
OAI21XLTS U1706 ( .A0(n2248), .A1(n1645), .B0(n1636), .Y(n1055) );
OAI21XLTS U1707 ( .A0(n2278), .A1(n1604), .B0(n1586), .Y(n995) );
AO22XLTS U1708 ( .A0(n1998), .A1(result_add_subt[39]), .B0(n1999), .B1(
d_ff_Xn[39]), .Y(n1098) );
AO22XLTS U1709 ( .A0(n1998), .A1(result_add_subt[38]), .B0(n1997), .B1(
d_ff_Xn[38]), .Y(n1099) );
OAI21XLTS U1710 ( .A0(n2276), .A1(n1604), .B0(n1583), .Y(n999) );
AO22XLTS U1711 ( .A0(n1998), .A1(result_add_subt[37]), .B0(n1997), .B1(
d_ff_Xn[37]), .Y(n1100) );
NAND2BXLTS U1712 ( .AN(d_ff3_LUT_out[48]), .B(n2152), .Y(n897) );
NOR2XLTS U1713 ( .A(n2049), .B(n1571), .Y(n1572) );
AO22XLTS U1714 ( .A0(n2003), .A1(result_add_subt[51]), .B0(n2002), .B1(
d_ff_Xn[51]), .Y(n1086) );
AO22XLTS U1715 ( .A0(n2006), .A1(result_add_subt[63]), .B0(n2005), .B1(
d_ff_Xn[63]), .Y(n1074) );
AO22XLTS U1716 ( .A0(d_ff_Xn[1]), .A1(n2219), .B0(d_ff2_X[1]), .B1(n2155),
.Y(n694) );
AO22XLTS U1717 ( .A0(d_ff_Xn[15]), .A1(n2168), .B0(d_ff2_X[15]), .B1(n2160),
.Y(n666) );
AO22XLTS U1718 ( .A0(d_ff_Xn[16]), .A1(n2172), .B0(d_ff2_X[16]), .B1(n2160),
.Y(n664) );
AO22XLTS U1719 ( .A0(d_ff_Xn[17]), .A1(n2172), .B0(d_ff2_X[17]), .B1(n2160),
.Y(n662) );
AO22XLTS U1720 ( .A0(d_ff_Xn[18]), .A1(n2172), .B0(d_ff2_X[18]), .B1(n2160),
.Y(n660) );
AO22XLTS U1721 ( .A0(d_ff_Xn[20]), .A1(n2172), .B0(d_ff2_X[20]), .B1(n2160),
.Y(n656) );
AO22XLTS U1722 ( .A0(d_ff_Xn[21]), .A1(n2164), .B0(d_ff2_X[21]), .B1(n2160),
.Y(n654) );
AO22XLTS U1723 ( .A0(d_ff_Xn[22]), .A1(n2164), .B0(d_ff2_X[22]), .B1(n2160),
.Y(n652) );
AO22XLTS U1724 ( .A0(d_ff_Xn[23]), .A1(n2164), .B0(d_ff2_X[23]), .B1(n2160),
.Y(n650) );
AO22XLTS U1725 ( .A0(d_ff_Xn[25]), .A1(n2164), .B0(d_ff2_X[25]), .B1(n2160),
.Y(n646) );
AO22XLTS U1726 ( .A0(d_ff_Xn[27]), .A1(n2164), .B0(d_ff2_X[27]), .B1(n2160),
.Y(n642) );
AO22XLTS U1727 ( .A0(d_ff_Xn[30]), .A1(n2164), .B0(d_ff2_X[30]), .B1(n2174),
.Y(n636) );
AO22XLTS U1728 ( .A0(d_ff_Xn[33]), .A1(n2168), .B0(d_ff2_X[33]), .B1(n2174),
.Y(n630) );
AO22XLTS U1729 ( .A0(d_ff_Xn[37]), .A1(n2164), .B0(d_ff2_X[37]), .B1(n2174),
.Y(n622) );
AO22XLTS U1730 ( .A0(d_ff_Xn[38]), .A1(n2168), .B0(d_ff2_X[38]), .B1(n2174),
.Y(n620) );
AO22XLTS U1731 ( .A0(d_ff_Xn[40]), .A1(n2168), .B0(d_ff2_X[40]), .B1(n2174),
.Y(n616) );
AO22XLTS U1732 ( .A0(d_ff_Xn[47]), .A1(n2172), .B0(d_ff2_X[47]), .B1(n2174),
.Y(n602) );
AO22XLTS U1733 ( .A0(n2003), .A1(result_add_subt[58]), .B0(n2002), .B1(
d_ff_Xn[58]), .Y(n1079) );
AO22XLTS U1734 ( .A0(d_ff_Yn[0]), .A1(n2118), .B0(d_ff2_Y[0]), .B1(n2187),
.Y(n824) );
AO22XLTS U1735 ( .A0(d_ff_Yn[1]), .A1(n2175), .B0(d_ff2_Y[1]), .B1(n2105),
.Y(n822) );
AO22XLTS U1736 ( .A0(d_ff_Yn[2]), .A1(n2175), .B0(d_ff2_Y[2]), .B1(n1844),
.Y(n820) );
AO22XLTS U1737 ( .A0(d_ff_Yn[3]), .A1(n2112), .B0(d_ff2_Y[3]), .B1(n2183),
.Y(n818) );
AO22XLTS U1738 ( .A0(d_ff_Yn[4]), .A1(n2112), .B0(d_ff2_Y[4]), .B1(n2105),
.Y(n816) );
AO22XLTS U1739 ( .A0(d_ff_Yn[5]), .A1(n2112), .B0(d_ff2_Y[5]), .B1(n1844),
.Y(n814) );
AO22XLTS U1740 ( .A0(d_ff_Yn[6]), .A1(n2118), .B0(d_ff2_Y[6]), .B1(n2105),
.Y(n812) );
AO22XLTS U1741 ( .A0(d_ff_Yn[7]), .A1(n2118), .B0(d_ff2_Y[7]), .B1(n1844),
.Y(n810) );
AO22XLTS U1742 ( .A0(d_ff_Yn[8]), .A1(n2118), .B0(d_ff2_Y[8]), .B1(n2183),
.Y(n808) );
AO22XLTS U1743 ( .A0(d_ff_Yn[9]), .A1(n2175), .B0(d_ff2_Y[9]), .B1(n2105),
.Y(n806) );
AO22XLTS U1744 ( .A0(d_ff_Yn[10]), .A1(n2175), .B0(d_ff2_Y[10]), .B1(n1844),
.Y(n804) );
AO22XLTS U1745 ( .A0(d_ff_Yn[11]), .A1(n2175), .B0(d_ff2_Y[11]), .B1(n1717),
.Y(n802) );
AO22XLTS U1746 ( .A0(d_ff_Yn[12]), .A1(n2175), .B0(d_ff2_Y[12]), .B1(n2108),
.Y(n800) );
AO22XLTS U1747 ( .A0(d_ff_Yn[13]), .A1(n2175), .B0(d_ff2_Y[13]), .B1(n1833),
.Y(n798) );
AO22XLTS U1748 ( .A0(d_ff_Yn[14]), .A1(n2175), .B0(d_ff2_Y[14]), .B1(n1717),
.Y(n796) );
AO22XLTS U1749 ( .A0(d_ff_Yn[15]), .A1(n2175), .B0(d_ff2_Y[15]), .B1(n2108),
.Y(n794) );
AO22XLTS U1750 ( .A0(d_ff_Yn[16]), .A1(n2114), .B0(d_ff2_Y[16]), .B1(n1833),
.Y(n792) );
AO22XLTS U1751 ( .A0(d_ff_Yn[17]), .A1(n2114), .B0(d_ff2_Y[17]), .B1(n1717),
.Y(n790) );
AO22XLTS U1752 ( .A0(d_ff_Yn[18]), .A1(n2114), .B0(d_ff2_Y[18]), .B1(n2108),
.Y(n788) );
AO22XLTS U1753 ( .A0(d_ff_Yn[19]), .A1(n2114), .B0(d_ff2_Y[19]), .B1(n1833),
.Y(n786) );
AO22XLTS U1754 ( .A0(d_ff_Yn[20]), .A1(n2114), .B0(d_ff2_Y[20]), .B1(n1717),
.Y(n784) );
AO22XLTS U1755 ( .A0(d_ff_Yn[36]), .A1(n2219), .B0(d_ff2_Y[36]), .B1(n2116),
.Y(n752) );
AO22XLTS U1756 ( .A0(d_ff_Yn[37]), .A1(n2219), .B0(d_ff2_Y[37]), .B1(n2116),
.Y(n750) );
AO22XLTS U1757 ( .A0(d_ff_Yn[38]), .A1(n2219), .B0(d_ff2_Y[38]), .B1(n2116),
.Y(n748) );
AO22XLTS U1758 ( .A0(d_ff_Yn[39]), .A1(n2219), .B0(d_ff2_Y[39]), .B1(n2116),
.Y(n746) );
AO22XLTS U1759 ( .A0(d_ff_Yn[40]), .A1(n2219), .B0(d_ff2_Y[40]), .B1(n2116),
.Y(n744) );
AO22XLTS U1760 ( .A0(d_ff_Yn[41]), .A1(n2118), .B0(d_ff2_Y[41]), .B1(n2218),
.Y(n742) );
AO22XLTS U1761 ( .A0(d_ff_Yn[42]), .A1(n2164), .B0(d_ff2_Y[42]), .B1(n2218),
.Y(n740) );
AO22XLTS U1762 ( .A0(d_ff_Yn[43]), .A1(n2164), .B0(d_ff2_Y[43]), .B1(n2174),
.Y(n738) );
AO22XLTS U1763 ( .A0(d_ff_Yn[44]), .A1(n2164), .B0(d_ff2_Y[44]), .B1(n2218),
.Y(n736) );
AO22XLTS U1764 ( .A0(d_ff_Yn[45]), .A1(n2118), .B0(d_ff2_Y[45]), .B1(n2218),
.Y(n734) );
AO22XLTS U1765 ( .A0(d_ff_Yn[51]), .A1(n2219), .B0(d_ff2_Y[51]), .B1(n2155),
.Y(n722) );
AO22XLTS U1766 ( .A0(d_ff_Yn[63]), .A1(n2219), .B0(d_ff2_Y[63]), .B1(n2155),
.Y(n698) );
AO22XLTS U1767 ( .A0(n1950), .A1(d_ff1_operation_out), .B0(n1955), .B1(
operation), .Y(n1336) );
NAND3XLTS U1768 ( .A(n1544), .B(sel_mux_3_reg), .C(n2366), .Y(n1543) );
NAND3XLTS U1769 ( .A(cordic_FSM_state_reg[3]), .B(n1932), .C(n2223), .Y(
n1544) );
AO22XLTS U1770 ( .A0(n1944), .A1(d_ff1_shift_region_flag_out[0]), .B0(n1955),
.B1(shift_region_flag[0]), .Y(n1335) );
AOI222X1TS U1771 ( .A0(n2183), .A1(d_ff2_Z[63]), .B0(n1736), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n1840), .Y(n1822) );
NAND3XLTS U1772 ( .A(n1542), .B(sel_mux_1_reg), .C(n2366), .Y(n1541) );
NAND3XLTS U1773 ( .A(cordic_FSM_state_reg[0]), .B(n1932), .C(n2229), .Y(
n1542) );
AO22XLTS U1774 ( .A0(d_ff_Yn[54]), .A1(n2219), .B0(d_ff2_Y[54]), .B1(n2155),
.Y(n718) );
AOI2BB2XLTS U1775 ( .B0(n1481), .B1(n2183), .A0N(d_ff_Xn[56]), .A1N(n2185),
.Y(n588) );
OAI32X1TS U1776 ( .A0(n1899), .A1(n1476), .A2(n1482), .B0(n1902), .B1(n1545),
.Y(n1266) );
AO22XLTS U1777 ( .A0(n2022), .A1(n1537), .B0(n2021), .B1(data_output[63]),
.Y(n946) );
AO22XLTS U1778 ( .A0(n2022), .A1(sign_inv_out[62]), .B0(n2021), .B1(
data_output[62]), .Y(n948) );
AO22XLTS U1779 ( .A0(n2022), .A1(sign_inv_out[61]), .B0(n2021), .B1(
data_output[61]), .Y(n950) );
AO22XLTS U1780 ( .A0(n2022), .A1(sign_inv_out[60]), .B0(n2021), .B1(
data_output[60]), .Y(n952) );
AO22XLTS U1781 ( .A0(n2020), .A1(sign_inv_out[59]), .B0(n2021), .B1(
data_output[59]), .Y(n954) );
AO22XLTS U1782 ( .A0(n2020), .A1(sign_inv_out[58]), .B0(n2019), .B1(
data_output[58]), .Y(n956) );
AO22XLTS U1783 ( .A0(n2020), .A1(sign_inv_out[57]), .B0(n2019), .B1(
data_output[57]), .Y(n958) );
AO22XLTS U1784 ( .A0(n2020), .A1(sign_inv_out[56]), .B0(n2019), .B1(
data_output[56]), .Y(n960) );
AO22XLTS U1785 ( .A0(n2020), .A1(sign_inv_out[55]), .B0(n2019), .B1(
data_output[55]), .Y(n962) );
AO22XLTS U1786 ( .A0(n2020), .A1(sign_inv_out[54]), .B0(n2019), .B1(
data_output[54]), .Y(n964) );
AO22XLTS U1787 ( .A0(n2020), .A1(sign_inv_out[53]), .B0(n2019), .B1(
data_output[53]), .Y(n966) );
AO22XLTS U1788 ( .A0(n2020), .A1(sign_inv_out[52]), .B0(n2019), .B1(
data_output[52]), .Y(n968) );
AO22XLTS U1789 ( .A0(n2020), .A1(sign_inv_out[51]), .B0(n2019), .B1(
data_output[51]), .Y(n970) );
AO22XLTS U1790 ( .A0(n2020), .A1(sign_inv_out[50]), .B0(n2019), .B1(
data_output[50]), .Y(n972) );
AO22XLTS U1791 ( .A0(n2017), .A1(sign_inv_out[49]), .B0(n2019), .B1(
data_output[49]), .Y(n974) );
AO22XLTS U1792 ( .A0(n2017), .A1(sign_inv_out[48]), .B0(n2015), .B1(
data_output[48]), .Y(n976) );
AO22XLTS U1793 ( .A0(n2017), .A1(sign_inv_out[47]), .B0(n2015), .B1(
data_output[47]), .Y(n978) );
AO22XLTS U1794 ( .A0(n2017), .A1(sign_inv_out[46]), .B0(n2015), .B1(
data_output[46]), .Y(n980) );
AO22XLTS U1795 ( .A0(n2017), .A1(sign_inv_out[45]), .B0(n2015), .B1(
data_output[45]), .Y(n982) );
AO22XLTS U1796 ( .A0(n2017), .A1(sign_inv_out[44]), .B0(n2015), .B1(
data_output[44]), .Y(n984) );
AO22XLTS U1797 ( .A0(n2017), .A1(sign_inv_out[43]), .B0(n2015), .B1(
data_output[43]), .Y(n986) );
AO22XLTS U1798 ( .A0(n2017), .A1(sign_inv_out[42]), .B0(n2015), .B1(
data_output[42]), .Y(n988) );
AO22XLTS U1799 ( .A0(n2017), .A1(sign_inv_out[41]), .B0(n2015), .B1(
data_output[41]), .Y(n990) );
AO22XLTS U1800 ( .A0(n2017), .A1(sign_inv_out[40]), .B0(n2015), .B1(
data_output[40]), .Y(n992) );
AO22XLTS U1801 ( .A0(n2014), .A1(sign_inv_out[39]), .B0(n2015), .B1(
data_output[39]), .Y(n994) );
AO22XLTS U1802 ( .A0(n2014), .A1(sign_inv_out[38]), .B0(n2013), .B1(
data_output[38]), .Y(n996) );
AO22XLTS U1803 ( .A0(n2014), .A1(sign_inv_out[37]), .B0(n2013), .B1(
data_output[37]), .Y(n998) );
AO22XLTS U1804 ( .A0(n2014), .A1(sign_inv_out[36]), .B0(n2013), .B1(
data_output[36]), .Y(n1000) );
AO22XLTS U1805 ( .A0(n2014), .A1(sign_inv_out[35]), .B0(n2013), .B1(
data_output[35]), .Y(n1002) );
AO22XLTS U1806 ( .A0(n2014), .A1(sign_inv_out[34]), .B0(n2013), .B1(
data_output[34]), .Y(n1004) );
AO22XLTS U1807 ( .A0(n2014), .A1(sign_inv_out[33]), .B0(n2013), .B1(
data_output[33]), .Y(n1006) );
AO22XLTS U1808 ( .A0(n2014), .A1(sign_inv_out[32]), .B0(n2013), .B1(
data_output[32]), .Y(n1008) );
AO22XLTS U1809 ( .A0(n2014), .A1(sign_inv_out[31]), .B0(n2013), .B1(
data_output[31]), .Y(n1010) );
AO22XLTS U1810 ( .A0(n2014), .A1(sign_inv_out[30]), .B0(n2013), .B1(
data_output[30]), .Y(n1012) );
AO22XLTS U1811 ( .A0(n2011), .A1(sign_inv_out[29]), .B0(n2013), .B1(
data_output[29]), .Y(n1014) );
AO22XLTS U1812 ( .A0(n2011), .A1(sign_inv_out[28]), .B0(n2012), .B1(
data_output[28]), .Y(n1016) );
AO22XLTS U1813 ( .A0(n2011), .A1(sign_inv_out[27]), .B0(n2012), .B1(
data_output[27]), .Y(n1018) );
AO22XLTS U1814 ( .A0(n2011), .A1(sign_inv_out[26]), .B0(n2012), .B1(
data_output[26]), .Y(n1020) );
AO22XLTS U1815 ( .A0(n2011), .A1(sign_inv_out[25]), .B0(n2012), .B1(
data_output[25]), .Y(n1022) );
AO22XLTS U1816 ( .A0(n2011), .A1(sign_inv_out[24]), .B0(n2012), .B1(
data_output[24]), .Y(n1024) );
AO22XLTS U1817 ( .A0(n2011), .A1(sign_inv_out[23]), .B0(n2012), .B1(
data_output[23]), .Y(n1026) );
AO22XLTS U1818 ( .A0(n2011), .A1(sign_inv_out[22]), .B0(n2010), .B1(
data_output[22]), .Y(n1028) );
AO22XLTS U1819 ( .A0(n2011), .A1(sign_inv_out[21]), .B0(n2010), .B1(
data_output[21]), .Y(n1030) );
AO22XLTS U1820 ( .A0(n2011), .A1(sign_inv_out[20]), .B0(n2016), .B1(
data_output[20]), .Y(n1032) );
AO22XLTS U1821 ( .A0(n2009), .A1(sign_inv_out[19]), .B0(n2016), .B1(
data_output[19]), .Y(n1034) );
AO22XLTS U1822 ( .A0(n2009), .A1(sign_inv_out[18]), .B0(n2018), .B1(
data_output[18]), .Y(n1036) );
AO22XLTS U1823 ( .A0(n2009), .A1(sign_inv_out[17]), .B0(n2008), .B1(
data_output[17]), .Y(n1038) );
AO22XLTS U1824 ( .A0(n2009), .A1(sign_inv_out[16]), .B0(n2021), .B1(
data_output[16]), .Y(n1040) );
AO22XLTS U1825 ( .A0(n2009), .A1(sign_inv_out[15]), .B0(n2008), .B1(
data_output[15]), .Y(n1042) );
AO22XLTS U1826 ( .A0(n2009), .A1(sign_inv_out[14]), .B0(n2008), .B1(
data_output[14]), .Y(n1044) );
AO22XLTS U1827 ( .A0(n2009), .A1(sign_inv_out[13]), .B0(n2008), .B1(
data_output[13]), .Y(n1046) );
AO22XLTS U1828 ( .A0(n2009), .A1(sign_inv_out[12]), .B0(n2021), .B1(
data_output[12]), .Y(n1048) );
AO22XLTS U1829 ( .A0(n2009), .A1(sign_inv_out[11]), .B0(n2008), .B1(
data_output[11]), .Y(n1050) );
AO22XLTS U1830 ( .A0(n2009), .A1(sign_inv_out[10]), .B0(n2008), .B1(
data_output[10]), .Y(n1052) );
AO22XLTS U1831 ( .A0(n2007), .A1(sign_inv_out[9]), .B0(n2018), .B1(
data_output[9]), .Y(n1054) );
AO22XLTS U1832 ( .A0(n2007), .A1(sign_inv_out[8]), .B0(n2010), .B1(
data_output[8]), .Y(n1056) );
AO22XLTS U1833 ( .A0(n2007), .A1(sign_inv_out[7]), .B0(n2010), .B1(
data_output[7]), .Y(n1058) );
AO22XLTS U1834 ( .A0(n2007), .A1(sign_inv_out[6]), .B0(n2010), .B1(
data_output[6]), .Y(n1060) );
AO22XLTS U1835 ( .A0(n2007), .A1(sign_inv_out[5]), .B0(n2010), .B1(
data_output[5]), .Y(n1062) );
AO22XLTS U1836 ( .A0(n2007), .A1(sign_inv_out[4]), .B0(n2010), .B1(
data_output[4]), .Y(n1064) );
AO22XLTS U1837 ( .A0(n2007), .A1(sign_inv_out[3]), .B0(n2010), .B1(
data_output[3]), .Y(n1066) );
AO22XLTS U1838 ( .A0(n2007), .A1(sign_inv_out[2]), .B0(n2010), .B1(
data_output[2]), .Y(n1068) );
AO22XLTS U1839 ( .A0(n2007), .A1(sign_inv_out[1]), .B0(n2012), .B1(
data_output[1]), .Y(n1070) );
AO22XLTS U1840 ( .A0(n2007), .A1(sign_inv_out[0]), .B0(n2018), .B1(
data_output[0]), .Y(n1072) );
NAND3XLTS U1841 ( .A(n1533), .B(n2091), .C(n1575), .Y(
cordic_FSM_state_next_1_) );
NOR3XLTS U1842 ( .A(n2213), .B(n1908), .C(n1576), .Y(n1337) );
AOI31XLTS U1843 ( .A0(ack_add_subt), .A1(n2101), .A2(n1482), .B0(
cont_var_out[0]), .Y(n1576) );
AO22XLTS U1844 ( .A0(n2221), .A1(d_ff2_X[63]), .B0(n2220), .B1(
d_ff3_sh_x_out[63]), .Y(n569) );
AO22XLTS U1845 ( .A0(n2204), .A1(d_ff2_X[51]), .B0(n2173), .B1(
d_ff3_sh_x_out[51]), .Y(n593) );
AO22XLTS U1846 ( .A0(n2204), .A1(d_ff2_X[50]), .B0(n2173), .B1(
d_ff3_sh_x_out[50]), .Y(n595) );
AO22XLTS U1847 ( .A0(n2204), .A1(d_ff2_X[49]), .B0(n2173), .B1(
d_ff3_sh_x_out[49]), .Y(n597) );
AO22XLTS U1848 ( .A0(n2204), .A1(d_ff2_X[48]), .B0(n2173), .B1(
d_ff3_sh_x_out[48]), .Y(n599) );
AO22XLTS U1849 ( .A0(n2204), .A1(d_ff2_X[47]), .B0(n2173), .B1(
d_ff3_sh_x_out[47]), .Y(n601) );
AO22XLTS U1850 ( .A0(n2204), .A1(d_ff2_X[46]), .B0(n2173), .B1(
d_ff3_sh_x_out[46]), .Y(n603) );
AO22XLTS U1851 ( .A0(n2169), .A1(d_ff2_X[45]), .B0(n2173), .B1(
d_ff3_sh_x_out[45]), .Y(n605) );
AO22XLTS U1852 ( .A0(n2169), .A1(d_ff2_X[44]), .B0(n2173), .B1(
d_ff3_sh_x_out[44]), .Y(n607) );
AO22XLTS U1853 ( .A0(n2169), .A1(d_ff2_X[43]), .B0(n2173), .B1(
d_ff3_sh_x_out[43]), .Y(n609) );
AO22XLTS U1854 ( .A0(n2169), .A1(d_ff2_X[42]), .B0(n2173), .B1(
d_ff3_sh_x_out[42]), .Y(n611) );
AO22XLTS U1855 ( .A0(n2169), .A1(d_ff2_X[41]), .B0(n2165), .B1(
d_ff3_sh_x_out[41]), .Y(n613) );
AO22XLTS U1856 ( .A0(n2169), .A1(d_ff2_X[40]), .B0(n2165), .B1(
d_ff3_sh_x_out[40]), .Y(n615) );
AO22XLTS U1857 ( .A0(n2169), .A1(d_ff2_X[39]), .B0(n2165), .B1(
d_ff3_sh_x_out[39]), .Y(n617) );
AO22XLTS U1858 ( .A0(n2169), .A1(d_ff2_X[38]), .B0(n2165), .B1(
d_ff3_sh_x_out[38]), .Y(n619) );
AO22XLTS U1859 ( .A0(n2169), .A1(d_ff2_X[37]), .B0(n2165), .B1(
d_ff3_sh_x_out[37]), .Y(n621) );
AO22XLTS U1860 ( .A0(n2169), .A1(d_ff2_X[36]), .B0(n2165), .B1(
d_ff3_sh_x_out[36]), .Y(n623) );
AO22XLTS U1861 ( .A0(n2162), .A1(d_ff2_X[35]), .B0(n2165), .B1(
d_ff3_sh_x_out[35]), .Y(n625) );
AO22XLTS U1862 ( .A0(n2162), .A1(d_ff2_X[34]), .B0(n2165), .B1(
d_ff3_sh_x_out[34]), .Y(n627) );
AO22XLTS U1863 ( .A0(n2162), .A1(d_ff2_X[33]), .B0(n2165), .B1(
d_ff3_sh_x_out[33]), .Y(n629) );
AO22XLTS U1864 ( .A0(n2162), .A1(d_ff2_X[32]), .B0(n2165), .B1(
d_ff3_sh_x_out[32]), .Y(n631) );
AO22XLTS U1865 ( .A0(n2162), .A1(d_ff2_X[31]), .B0(n2161), .B1(
d_ff3_sh_x_out[31]), .Y(n633) );
AO22XLTS U1866 ( .A0(n2162), .A1(d_ff2_X[30]), .B0(n2161), .B1(
d_ff3_sh_x_out[30]), .Y(n635) );
AO22XLTS U1867 ( .A0(n2162), .A1(d_ff2_X[29]), .B0(n2161), .B1(
d_ff3_sh_x_out[29]), .Y(n637) );
AO22XLTS U1868 ( .A0(n2162), .A1(d_ff2_X[28]), .B0(n2161), .B1(
d_ff3_sh_x_out[28]), .Y(n639) );
AO22XLTS U1869 ( .A0(n2162), .A1(d_ff2_X[27]), .B0(n2161), .B1(
d_ff3_sh_x_out[27]), .Y(n641) );
AO22XLTS U1870 ( .A0(n2162), .A1(d_ff2_X[26]), .B0(n2161), .B1(
d_ff3_sh_x_out[26]), .Y(n643) );
AO22XLTS U1871 ( .A0(n2159), .A1(d_ff2_X[25]), .B0(n2161), .B1(
d_ff3_sh_x_out[25]), .Y(n645) );
AO22XLTS U1872 ( .A0(n2159), .A1(d_ff2_X[24]), .B0(n2161), .B1(
d_ff3_sh_x_out[24]), .Y(n647) );
AO22XLTS U1873 ( .A0(n2159), .A1(d_ff2_X[23]), .B0(n2161), .B1(
d_ff3_sh_x_out[23]), .Y(n649) );
AO22XLTS U1874 ( .A0(n2159), .A1(d_ff2_X[22]), .B0(n2215), .B1(
d_ff3_sh_x_out[22]), .Y(n651) );
AO22XLTS U1875 ( .A0(n2159), .A1(d_ff2_X[21]), .B0(n2215), .B1(
d_ff3_sh_x_out[21]), .Y(n653) );
AO22XLTS U1876 ( .A0(n2159), .A1(d_ff2_X[20]), .B0(n2215), .B1(
d_ff3_sh_x_out[20]), .Y(n655) );
AO22XLTS U1877 ( .A0(n2159), .A1(d_ff2_X[19]), .B0(n2158), .B1(
d_ff3_sh_x_out[19]), .Y(n657) );
AO22XLTS U1878 ( .A0(n2159), .A1(d_ff2_X[18]), .B0(n2215), .B1(
d_ff3_sh_x_out[18]), .Y(n659) );
AO22XLTS U1879 ( .A0(n2159), .A1(d_ff2_X[17]), .B0(n2215), .B1(
d_ff3_sh_x_out[17]), .Y(n661) );
AO22XLTS U1880 ( .A0(n2157), .A1(d_ff2_X[16]), .B0(n2215), .B1(
d_ff3_sh_x_out[16]), .Y(n663) );
AO22XLTS U1881 ( .A0(n2157), .A1(d_ff2_X[15]), .B0(n2171), .B1(
d_ff3_sh_x_out[15]), .Y(n665) );
AO22XLTS U1882 ( .A0(n2157), .A1(d_ff2_X[14]), .B0(n2158), .B1(
d_ff3_sh_x_out[14]), .Y(n667) );
AO22XLTS U1883 ( .A0(n2157), .A1(d_ff2_X[13]), .B0(n2158), .B1(
d_ff3_sh_x_out[13]), .Y(n669) );
AO22XLTS U1884 ( .A0(n2159), .A1(d_ff2_X[12]), .B0(n2156), .B1(
d_ff3_sh_x_out[12]), .Y(n671) );
AO22XLTS U1885 ( .A0(n2157), .A1(d_ff2_X[11]), .B0(n2154), .B1(
d_ff3_sh_x_out[11]), .Y(n673) );
AO22XLTS U1886 ( .A0(n2157), .A1(d_ff2_X[10]), .B0(n2156), .B1(
d_ff3_sh_x_out[10]), .Y(n675) );
AO22XLTS U1887 ( .A0(n2157), .A1(d_ff2_X[9]), .B0(n2154), .B1(
d_ff3_sh_x_out[9]), .Y(n677) );
AO22XLTS U1888 ( .A0(n2157), .A1(d_ff2_X[8]), .B0(n2154), .B1(
d_ff3_sh_x_out[8]), .Y(n679) );
AO22XLTS U1889 ( .A0(n2157), .A1(d_ff2_X[7]), .B0(n2153), .B1(
d_ff3_sh_x_out[7]), .Y(n681) );
AO22XLTS U1890 ( .A0(n2157), .A1(d_ff2_X[6]), .B0(n2153), .B1(
d_ff3_sh_x_out[6]), .Y(n683) );
AO22XLTS U1891 ( .A0(n2217), .A1(d_ff2_X[5]), .B0(n2152), .B1(
d_ff3_sh_x_out[5]), .Y(n685) );
AO22XLTS U1892 ( .A0(n2217), .A1(d_ff2_X[4]), .B0(n2152), .B1(
d_ff3_sh_x_out[4]), .Y(n687) );
AO22XLTS U1893 ( .A0(n2217), .A1(d_ff2_X[3]), .B0(n2154), .B1(
d_ff3_sh_x_out[3]), .Y(n689) );
AO22XLTS U1894 ( .A0(n2217), .A1(d_ff2_X[2]), .B0(n2152), .B1(
d_ff3_sh_x_out[2]), .Y(n691) );
AO22XLTS U1895 ( .A0(n2217), .A1(d_ff2_X[1]), .B0(n2152), .B1(
d_ff3_sh_x_out[1]), .Y(n693) );
AO22XLTS U1896 ( .A0(n2217), .A1(d_ff2_X[0]), .B0(n2152), .B1(
d_ff3_sh_x_out[0]), .Y(n695) );
AO22XLTS U1897 ( .A0(n2217), .A1(d_ff2_Y[63]), .B0(n2156), .B1(
d_ff3_sh_y_out[63]), .Y(n697) );
AO22XLTS U1898 ( .A0(n2221), .A1(d_ff2_Y[51]), .B0(n2171), .B1(
d_ff3_sh_y_out[51]), .Y(n721) );
AO22XLTS U1899 ( .A0(n2221), .A1(d_ff2_Y[50]), .B0(n1519), .B1(
d_ff3_sh_y_out[50]), .Y(n723) );
AO22XLTS U1900 ( .A0(n2119), .A1(d_ff2_Y[49]), .B0(n2161), .B1(
d_ff3_sh_y_out[49]), .Y(n725) );
AO22XLTS U1901 ( .A0(n2119), .A1(d_ff2_Y[48]), .B0(n2220), .B1(
d_ff3_sh_y_out[48]), .Y(n727) );
AO22XLTS U1902 ( .A0(n2119), .A1(d_ff2_Y[47]), .B0(n2220), .B1(
d_ff3_sh_y_out[47]), .Y(n729) );
AO22XLTS U1903 ( .A0(n2119), .A1(d_ff2_Y[46]), .B0(n2220), .B1(
d_ff3_sh_y_out[46]), .Y(n731) );
AO22XLTS U1904 ( .A0(n2119), .A1(d_ff2_Y[45]), .B0(n2220), .B1(
d_ff3_sh_y_out[45]), .Y(n733) );
AO22XLTS U1905 ( .A0(n2221), .A1(d_ff2_Y[44]), .B0(n2117), .B1(
d_ff3_sh_y_out[44]), .Y(n735) );
AO22XLTS U1906 ( .A0(n2119), .A1(d_ff2_Y[43]), .B0(n2117), .B1(
d_ff3_sh_y_out[43]), .Y(n737) );
AO22XLTS U1907 ( .A0(n2119), .A1(d_ff2_Y[41]), .B0(n2117), .B1(
d_ff3_sh_y_out[41]), .Y(n741) );
AO22XLTS U1908 ( .A0(n2115), .A1(d_ff2_Y[39]), .B0(n2117), .B1(
d_ff3_sh_y_out[39]), .Y(n745) );
AO22XLTS U1909 ( .A0(n2115), .A1(d_ff2_Y[33]), .B0(n2113), .B1(
d_ff3_sh_y_out[33]), .Y(n757) );
AO22XLTS U1910 ( .A0(n2110), .A1(d_ff2_Y[29]), .B0(n2113), .B1(
d_ff3_sh_y_out[29]), .Y(n765) );
AO22XLTS U1911 ( .A0(n2110), .A1(d_ff2_Y[27]), .B0(n2113), .B1(
d_ff3_sh_y_out[27]), .Y(n769) );
AO22XLTS U1912 ( .A0(n2110), .A1(d_ff2_Y[26]), .B0(n2113), .B1(
d_ff3_sh_y_out[26]), .Y(n771) );
AO22XLTS U1913 ( .A0(n2110), .A1(d_ff2_Y[25]), .B0(n2113), .B1(
d_ff3_sh_y_out[25]), .Y(n773) );
AO22XLTS U1914 ( .A0(n2107), .A1(d_ff2_Y[19]), .B0(n2109), .B1(
d_ff3_sh_y_out[19]), .Y(n785) );
AO22XLTS U1915 ( .A0(n2107), .A1(d_ff2_Y[15]), .B0(n2109), .B1(
d_ff3_sh_y_out[15]), .Y(n793) );
AO22XLTS U1916 ( .A0(n2107), .A1(d_ff2_Y[14]), .B0(n1519), .B1(
d_ff3_sh_y_out[14]), .Y(n795) );
AO22XLTS U1917 ( .A0(n2107), .A1(d_ff2_Y[13]), .B0(n1519), .B1(
d_ff3_sh_y_out[13]), .Y(n797) );
AO22XLTS U1918 ( .A0(n2107), .A1(d_ff2_Y[12]), .B0(n1519), .B1(
d_ff3_sh_y_out[12]), .Y(n799) );
AO22XLTS U1919 ( .A0(n2107), .A1(d_ff2_Y[11]), .B0(n1519), .B1(
d_ff3_sh_y_out[11]), .Y(n801) );
AO22XLTS U1920 ( .A0(n2107), .A1(d_ff2_Y[10]), .B0(n1519), .B1(
d_ff3_sh_y_out[10]), .Y(n803) );
AO22XLTS U1921 ( .A0(n2104), .A1(d_ff2_Y[9]), .B0(n2156), .B1(
d_ff3_sh_y_out[9]), .Y(n805) );
AO22XLTS U1922 ( .A0(n2107), .A1(d_ff2_Y[8]), .B0(n2044), .B1(
d_ff3_sh_y_out[8]), .Y(n807) );
AO22XLTS U1923 ( .A0(n2104), .A1(d_ff2_Y[7]), .B0(n2171), .B1(
d_ff3_sh_y_out[7]), .Y(n809) );
AO22XLTS U1924 ( .A0(n2107), .A1(d_ff2_Y[6]), .B0(n2167), .B1(
d_ff3_sh_y_out[6]), .Y(n811) );
AO22XLTS U1925 ( .A0(n2104), .A1(d_ff2_Y[5]), .B0(n2163), .B1(
d_ff3_sh_y_out[5]), .Y(n813) );
AO22XLTS U1926 ( .A0(n2104), .A1(d_ff2_Y[3]), .B0(n2103), .B1(
d_ff3_sh_y_out[3]), .Y(n817) );
AO22XLTS U1927 ( .A0(n2104), .A1(d_ff2_Y[1]), .B0(n2103), .B1(
d_ff3_sh_y_out[1]), .Y(n821) );
AO22XLTS U1928 ( .A0(n2104), .A1(d_ff2_Y[0]), .B0(n2103), .B1(
d_ff3_sh_y_out[0]), .Y(n823) );
AO22XLTS U1929 ( .A0(n1519), .A1(d_ff3_sign_out), .B0(n2206), .B1(
d_ff2_Z[63]), .Y(n825) );
AO22XLTS U1930 ( .A0(n2217), .A1(n2216), .B0(n2215), .B1(d_ff3_sh_x_out[62]),
.Y(n571) );
AOI2BB2XLTS U1931 ( .B0(n2213), .B1(n2212), .A0N(d_ff3_sh_x_out[61]), .A1N(
n2211), .Y(n572) );
AO22XLTS U1932 ( .A0(n2221), .A1(n2209), .B0(n2220), .B1(d_ff3_sh_x_out[60]),
.Y(n573) );
OAI21XLTS U1933 ( .A0(n2208), .A1(n1485), .B0(n2210), .Y(n2209) );
AOI2BB2XLTS U1934 ( .B0(n2213), .B1(n2207), .A0N(d_ff3_sh_x_out[59]), .A1N(
n2206), .Y(n574) );
AO22XLTS U1935 ( .A0(n2204), .A1(n2203), .B0(n2220), .B1(d_ff3_sh_x_out[58]),
.Y(n575) );
OAI21XLTS U1936 ( .A0(n2202), .A1(n1483), .B0(n2205), .Y(n2203) );
AOI2BB2XLTS U1937 ( .B0(n2076), .B1(n2201), .A0N(d_ff3_sh_x_out[57]), .A1N(
n2206), .Y(n576) );
AO22XLTS U1938 ( .A0(n2204), .A1(n2194), .B0(n2220), .B1(d_ff3_sh_x_out[54]),
.Y(n579) );
AOI2BB2XLTS U1939 ( .B0(n2076), .B1(n2189), .A0N(d_ff3_sh_x_out[52]), .A1N(
n2206), .Y(n581) );
AO22X1TS U1940 ( .A0(n2217), .A1(n1521), .B0(n2153), .B1(d_ff3_sh_y_out[62]),
.Y(n699) );
AOI2BB2XLTS U1941 ( .B0(n2076), .B1(n2151), .A0N(d_ff3_sh_y_out[61]), .A1N(
n2206), .Y(n700) );
AO22XLTS U1942 ( .A0(n2217), .A1(n2148), .B0(n2156), .B1(d_ff3_sh_y_out[60]),
.Y(n701) );
OAI21XLTS U1943 ( .A0(n2147), .A1(n2146), .B0(n2150), .Y(n2148) );
AOI2BB2XLTS U1944 ( .B0(n2089), .B1(n2145), .A0N(d_ff3_sh_y_out[59]), .A1N(
n2206), .Y(n702) );
AO22XLTS U1945 ( .A0(n2221), .A1(n1539), .B0(n2152), .B1(d_ff3_sh_y_out[58]),
.Y(n703) );
OAI21XLTS U1946 ( .A0(n2141), .A1(n2127), .B0(n2144), .Y(n1539) );
AOI2BB2XLTS U1947 ( .B0(n2213), .B1(n2143), .A0N(d_ff3_sh_y_out[57]), .A1N(
n2206), .Y(n704) );
OAI21XLTS U1948 ( .A0(n2139), .A1(n2138), .B0(n2142), .Y(n2140) );
OAI21XLTS U1949 ( .A0(n1682), .A1(n1552), .B0(n1551), .Y(n706) );
AO22XLTS U1950 ( .A0(n2221), .A1(n1535), .B0(n2153), .B1(d_ff3_sh_y_out[54]),
.Y(n707) );
AO22XLTS U1951 ( .A0(n2221), .A1(n2137), .B0(n1519), .B1(d_ff3_sh_y_out[53]),
.Y(n708) );
AOI2BB2XLTS U1952 ( .B0(n2089), .B1(n2134), .A0N(d_ff3_sh_y_out[52]), .A1N(
n2206), .Y(n709) );
AOI31XLTS U1953 ( .A0(n2052), .A1(n2101), .A2(n2037), .B0(n1700), .Y(n891)
);
OAI21XLTS U1954 ( .A0(n2087), .A1(n2036), .B0(n1554), .Y(n892) );
OAI32X1TS U1955 ( .A0(n2044), .A1(n2064), .A2(n1699), .B0(n2089), .B1(n2293),
.Y(n893) );
AO22XLTS U1956 ( .A0(n2206), .A1(cont_iter_out[0]), .B0(n2103), .B1(
d_ff3_LUT_out[52]), .Y(n894) );
AO21XLTS U1957 ( .A0(d_ff3_LUT_out[49]), .A1(n2103), .B0(n2096), .Y(n896) );
AO21XLTS U1958 ( .A0(d_ff3_LUT_out[47]), .A1(n2095), .B0(n2094), .Y(n898) );
AO21XLTS U1959 ( .A0(d_ff3_LUT_out[46]), .A1(n2095), .B0(n2096), .Y(n899) );
AO21XLTS U1960 ( .A0(d_ff3_LUT_out[44]), .A1(n2095), .B0(n2096), .Y(n901) );
AO21XLTS U1961 ( .A0(d_ff3_LUT_out[43]), .A1(n2095), .B0(n2092), .Y(n902) );
AO21XLTS U1962 ( .A0(d_ff3_LUT_out[42]), .A1(n2095), .B0(n2094), .Y(n903) );
NAND2BXLTS U1963 ( .AN(n2085), .B(n2084), .Y(n906) );
AO21XLTS U1964 ( .A0(d_ff3_LUT_out[34]), .A1(n2095), .B0(n2092), .Y(n911) );
AOI2BB2XLTS U1965 ( .B0(n2075), .B1(n2088), .A0N(n2097), .A1N(
d_ff3_LUT_out[31]), .Y(n914) );
AO21XLTS U1966 ( .A0(d_ff3_LUT_out[30]), .A1(n2095), .B0(n2074), .Y(n915) );
NAND4XLTS U1967 ( .A(n2073), .B(n2072), .C(n2071), .D(n2070), .Y(n916) );
NAND4XLTS U1968 ( .A(n2069), .B(n2072), .C(n2068), .D(n2067), .Y(n918) );
NAND3XLTS U1969 ( .A(n2068), .B(n2062), .C(n2061), .Y(n920) );
AOI2BB2XLTS U1970 ( .B0(n2058), .B1(n2057), .A0N(n2097), .A1N(
d_ff3_LUT_out[23]), .Y(n922) );
AOI2BB2XLTS U1971 ( .B0(n2052), .B1(n2057), .A0N(n2097), .A1N(
d_ff3_LUT_out[21]), .Y(n924) );
AOI2BB2XLTS U1972 ( .B0(n2089), .B1(n2090), .A0N(d_ff3_LUT_out[20]), .A1N(
n2211), .Y(n925) );
AO21XLTS U1973 ( .A0(d_ff3_LUT_out[16]), .A1(n2095), .B0(n2046), .Y(n929) );
OAI211XLTS U1974 ( .A0(n1682), .A1(n1496), .B0(n2071), .C0(n1562), .Y(n931)
);
AOI2BB2XLTS U1975 ( .B0(n2041), .B1(n2096), .A0N(n2097), .A1N(
d_ff3_LUT_out[13]), .Y(n932) );
AOI211XLTS U1976 ( .A0(d_ff3_LUT_out[11]), .A1(n2087), .B0(n2085), .C0(n2035), .Y(n1681) );
AOI2BB2XLTS U1977 ( .B0(n2075), .B1(n2037), .A0N(n2097), .A1N(
d_ff3_LUT_out[10]), .Y(n935) );
NAND4BXLTS U1978 ( .AN(n2035), .B(n2047), .C(n2034), .D(n2033), .Y(n936) );
NAND3XLTS U1979 ( .A(n2089), .B(n2064), .C(n2195), .Y(n2034) );
NAND3XLTS U1980 ( .A(n2073), .B(n2072), .C(n2030), .Y(n939) );
AO21XLTS U1981 ( .A0(d_ff3_LUT_out[4]), .A1(n2095), .B0(n2074), .Y(n941) );
AO21XLTS U1982 ( .A0(d_ff3_LUT_out[2]), .A1(n2095), .B0(n2026), .Y(n943) );
AOI31XLTS U1983 ( .A0(n2195), .A1(n1490), .A2(n2025), .B0(n2091), .Y(n2026)
);
OAI211XLTS U1984 ( .A0(n2073), .A1(n2078), .B0(n2047), .C0(n1570), .Y(n944)
);
NAND3XLTS U1985 ( .A(n2024), .B(n2068), .C(n2023), .Y(n945) );
OAI21XLTS U1986 ( .A0(n2132), .A1(n1475), .B0(n1561), .Y(n949) );
OAI21XLTS U1987 ( .A0(n2130), .A1(n1560), .B0(n1557), .Y(n951) );
OAI21XLTS U1988 ( .A0(n2129), .A1(n1475), .B0(n1559), .Y(n953) );
OAI21XLTS U1989 ( .A0(n2128), .A1(n1657), .B0(n1653), .Y(n955) );
OAI21XLTS U1990 ( .A0(n2125), .A1(n1657), .B0(n1649), .Y(n959) );
OAI21XLTS U1991 ( .A0(n2124), .A1(n1657), .B0(n1651), .Y(n961) );
OAI21XLTS U1992 ( .A0(n2123), .A1(n1657), .B0(n1648), .Y(n963) );
OAI21XLTS U1993 ( .A0(n2291), .A1(n1657), .B0(n1646), .Y(n965) );
OAI21XLTS U1994 ( .A0(n2122), .A1(n1657), .B0(n1656), .Y(n967) );
OAI21XLTS U1995 ( .A0(n2121), .A1(n1657), .B0(n1647), .Y(n969) );
OAI21XLTS U1996 ( .A0(n2289), .A1(n1657), .B0(n1633), .Y(n973) );
OAI21XLTS U1997 ( .A0(n2288), .A1(n1599), .B0(n1580), .Y(n975) );
OAI21XLTS U1998 ( .A0(n2287), .A1(n1599), .B0(n1590), .Y(n977) );
OAI21XLTS U1999 ( .A0(n2286), .A1(n1599), .B0(n1578), .Y(n979) );
OAI21XLTS U2000 ( .A0(n2285), .A1(n1599), .B0(n1589), .Y(n981) );
OAI21XLTS U2001 ( .A0(n2284), .A1(n1599), .B0(n1584), .Y(n983) );
OAI21XLTS U2002 ( .A0(n2283), .A1(n1599), .B0(n1581), .Y(n985) );
OAI21XLTS U2003 ( .A0(n2282), .A1(n1599), .B0(n1592), .Y(n987) );
OAI21XLTS U2004 ( .A0(n2281), .A1(n1599), .B0(n1595), .Y(n989) );
OAI21XLTS U2005 ( .A0(n2280), .A1(n1599), .B0(n1579), .Y(n991) );
OAI21XLTS U2006 ( .A0(n2279), .A1(n1599), .B0(n1598), .Y(n993) );
OAI21XLTS U2007 ( .A0(n2275), .A1(n1604), .B0(n1593), .Y(n1001) );
OAI21XLTS U2008 ( .A0(n2274), .A1(n1604), .B0(n1582), .Y(n1003) );
OAI21XLTS U2009 ( .A0(n2273), .A1(n1604), .B0(n1603), .Y(n1005) );
OAI21XLTS U2010 ( .A0(n2272), .A1(n1604), .B0(n1600), .Y(n1007) );
OAI21XLTS U2011 ( .A0(n2271), .A1(n1604), .B0(n1587), .Y(n1009) );
OAI21XLTS U2012 ( .A0(n2270), .A1(n1604), .B0(n1588), .Y(n1011) );
OAI21XLTS U2013 ( .A0(n2269), .A1(n1604), .B0(n1591), .Y(n1013) );
OAI21XLTS U2014 ( .A0(n2268), .A1(n1624), .B0(n1594), .Y(n1015) );
OAI21XLTS U2015 ( .A0(n2267), .A1(n1624), .B0(n1596), .Y(n1017) );
OAI21XLTS U2016 ( .A0(n2266), .A1(n1624), .B0(n1608), .Y(n1019) );
OAI21XLTS U2017 ( .A0(n2265), .A1(n1624), .B0(n1613), .Y(n1021) );
OAI21XLTS U2018 ( .A0(n2263), .A1(n1624), .B0(n1620), .Y(n1025) );
OAI21XLTS U2019 ( .A0(n2262), .A1(n1624), .B0(n1609), .Y(n1027) );
OAI21XLTS U2020 ( .A0(n2261), .A1(n1624), .B0(n1623), .Y(n1029) );
OAI21XLTS U2021 ( .A0(n2260), .A1(n1624), .B0(n1606), .Y(n1031) );
OAI21XLTS U2022 ( .A0(n2259), .A1(n1624), .B0(n1610), .Y(n1033) );
OAI21XLTS U2023 ( .A0(n2258), .A1(n1629), .B0(n1607), .Y(n1035) );
OAI21XLTS U2024 ( .A0(n2257), .A1(n1629), .B0(n1628), .Y(n1037) );
OAI21XLTS U2025 ( .A0(n2256), .A1(n1629), .B0(n1612), .Y(n1039) );
OAI21XLTS U2026 ( .A0(n2255), .A1(n1629), .B0(n1625), .Y(n1041) );
OAI21XLTS U2027 ( .A0(n2254), .A1(n1629), .B0(n1614), .Y(n1043) );
OAI21XLTS U2028 ( .A0(n2253), .A1(n1629), .B0(n1615), .Y(n1045) );
OAI21XLTS U2029 ( .A0(n2252), .A1(n1629), .B0(n1617), .Y(n1047) );
OAI21XLTS U2030 ( .A0(n2250), .A1(n1629), .B0(n1611), .Y(n1051) );
OAI21XLTS U2031 ( .A0(n2249), .A1(n1629), .B0(n1621), .Y(n1053) );
OAI21XLTS U2032 ( .A0(n2245), .A1(n1645), .B0(n1639), .Y(n1061) );
OAI21XLTS U2033 ( .A0(n2243), .A1(n1645), .B0(n1634), .Y(n1065) );
OAI21XLTS U2034 ( .A0(n2242), .A1(n1645), .B0(n1641), .Y(n1067) );
OAI21XLTS U2035 ( .A0(n2241), .A1(n1645), .B0(n1632), .Y(n1069) );
OAI21XLTS U2036 ( .A0(n2240), .A1(n1645), .B0(n1630), .Y(n1071) );
OAI21XLTS U2037 ( .A0(n2239), .A1(n1645), .B0(n1637), .Y(n1073) );
AO22XLTS U2038 ( .A0(n1973), .A1(result_add_subt[63]), .B0(n1972), .B1(
d_ff_Zn[63]), .Y(n1202) );
AO22XLTS U2039 ( .A0(n1973), .A1(result_add_subt[62]), .B0(n1972), .B1(
d_ff_Zn[62]), .Y(n1203) );
AO22XLTS U2040 ( .A0(n1973), .A1(result_add_subt[61]), .B0(n1972), .B1(
d_ff_Zn[61]), .Y(n1204) );
AO22XLTS U2041 ( .A0(n1973), .A1(result_add_subt[60]), .B0(n1972), .B1(
d_ff_Zn[60]), .Y(n1205) );
AO22XLTS U2042 ( .A0(n1970), .A1(result_add_subt[59]), .B0(n1972), .B1(
d_ff_Zn[59]), .Y(n1206) );
AO22XLTS U2043 ( .A0(n1970), .A1(result_add_subt[58]), .B0(n1969), .B1(
d_ff_Zn[58]), .Y(n1207) );
AO22XLTS U2044 ( .A0(n1970), .A1(result_add_subt[57]), .B0(n1969), .B1(
d_ff_Zn[57]), .Y(n1208) );
AO22XLTS U2045 ( .A0(n1970), .A1(result_add_subt[56]), .B0(n1969), .B1(
d_ff_Zn[56]), .Y(n1209) );
AO22XLTS U2046 ( .A0(n1970), .A1(result_add_subt[55]), .B0(n1969), .B1(
d_ff_Zn[55]), .Y(n1210) );
AO22XLTS U2047 ( .A0(n1970), .A1(result_add_subt[54]), .B0(n1969), .B1(
d_ff_Zn[54]), .Y(n1211) );
AO22XLTS U2048 ( .A0(n1970), .A1(result_add_subt[53]), .B0(n1969), .B1(
d_ff_Zn[53]), .Y(n1212) );
AO22XLTS U2049 ( .A0(n1970), .A1(result_add_subt[52]), .B0(n1969), .B1(
d_ff_Zn[52]), .Y(n1213) );
AO22XLTS U2050 ( .A0(n1970), .A1(result_add_subt[51]), .B0(n1969), .B1(
d_ff_Zn[51]), .Y(n1214) );
AO22XLTS U2051 ( .A0(n1970), .A1(result_add_subt[50]), .B0(n1969), .B1(
d_ff_Zn[50]), .Y(n1215) );
AO22XLTS U2052 ( .A0(n1968), .A1(result_add_subt[49]), .B0(n1969), .B1(
d_ff_Zn[49]), .Y(n1216) );
AO22XLTS U2053 ( .A0(n1968), .A1(result_add_subt[48]), .B0(n1972), .B1(
d_ff_Zn[48]), .Y(n1217) );
AO22XLTS U2054 ( .A0(n1968), .A1(result_add_subt[47]), .B0(n1967), .B1(
d_ff_Zn[47]), .Y(n1218) );
AO22XLTS U2055 ( .A0(n1968), .A1(result_add_subt[46]), .B0(n1967), .B1(
d_ff_Zn[46]), .Y(n1219) );
AO22XLTS U2056 ( .A0(n1968), .A1(result_add_subt[45]), .B0(n1967), .B1(
d_ff_Zn[45]), .Y(n1220) );
AO22XLTS U2057 ( .A0(n1968), .A1(result_add_subt[44]), .B0(n1967), .B1(
d_ff_Zn[44]), .Y(n1221) );
AO22XLTS U2058 ( .A0(n1968), .A1(result_add_subt[43]), .B0(n1966), .B1(
d_ff_Zn[43]), .Y(n1222) );
AO22XLTS U2059 ( .A0(n1968), .A1(result_add_subt[42]), .B0(n1966), .B1(
d_ff_Zn[42]), .Y(n1223) );
AO22XLTS U2060 ( .A0(n1968), .A1(result_add_subt[41]), .B0(n1966), .B1(
d_ff_Zn[41]), .Y(n1224) );
AO22XLTS U2061 ( .A0(n1968), .A1(result_add_subt[40]), .B0(n1966), .B1(
d_ff_Zn[40]), .Y(n1225) );
AO22XLTS U2062 ( .A0(n1965), .A1(result_add_subt[39]), .B0(n1966), .B1(
d_ff_Zn[39]), .Y(n1226) );
AO22XLTS U2063 ( .A0(n1965), .A1(result_add_subt[38]), .B0(n1964), .B1(
d_ff_Zn[38]), .Y(n1227) );
AO22XLTS U2064 ( .A0(n1965), .A1(result_add_subt[37]), .B0(n1964), .B1(
d_ff_Zn[37]), .Y(n1228) );
AO22XLTS U2065 ( .A0(n1965), .A1(result_add_subt[36]), .B0(n1964), .B1(
d_ff_Zn[36]), .Y(n1229) );
AO22XLTS U2066 ( .A0(n1965), .A1(result_add_subt[35]), .B0(n1964), .B1(
d_ff_Zn[35]), .Y(n1230) );
AO22XLTS U2067 ( .A0(n1965), .A1(result_add_subt[34]), .B0(n1964), .B1(
d_ff_Zn[34]), .Y(n1231) );
AO22XLTS U2068 ( .A0(n1965), .A1(result_add_subt[33]), .B0(n1964), .B1(
d_ff_Zn[33]), .Y(n1232) );
AO22XLTS U2069 ( .A0(n1965), .A1(result_add_subt[32]), .B0(n1964), .B1(
d_ff_Zn[32]), .Y(n1233) );
AO22XLTS U2070 ( .A0(n1965), .A1(result_add_subt[31]), .B0(n1964), .B1(
d_ff_Zn[31]), .Y(n1234) );
AO22XLTS U2071 ( .A0(n1965), .A1(result_add_subt[30]), .B0(n1964), .B1(
d_ff_Zn[30]), .Y(n1235) );
AO22XLTS U2072 ( .A0(n1963), .A1(result_add_subt[29]), .B0(n1964), .B1(
d_ff_Zn[29]), .Y(n1236) );
AO22XLTS U2073 ( .A0(n1963), .A1(result_add_subt[28]), .B0(n1962), .B1(
d_ff_Zn[28]), .Y(n1237) );
AO22XLTS U2074 ( .A0(n1963), .A1(result_add_subt[27]), .B0(n1962), .B1(
d_ff_Zn[27]), .Y(n1238) );
AO22XLTS U2075 ( .A0(n1963), .A1(result_add_subt[26]), .B0(n1962), .B1(
d_ff_Zn[26]), .Y(n1239) );
AO22XLTS U2076 ( .A0(n1963), .A1(result_add_subt[25]), .B0(n1962), .B1(
d_ff_Zn[25]), .Y(n1240) );
AO22XLTS U2077 ( .A0(n1963), .A1(result_add_subt[24]), .B0(n1962), .B1(
d_ff_Zn[24]), .Y(n1241) );
AO22XLTS U2078 ( .A0(n1963), .A1(result_add_subt[23]), .B0(n1962), .B1(
d_ff_Zn[23]), .Y(n1242) );
AO22XLTS U2079 ( .A0(n1963), .A1(result_add_subt[22]), .B0(n1962), .B1(
d_ff_Zn[22]), .Y(n1243) );
AO22XLTS U2080 ( .A0(n1963), .A1(result_add_subt[21]), .B0(n1962), .B1(
d_ff_Zn[21]), .Y(n1244) );
AO22XLTS U2081 ( .A0(n1963), .A1(result_add_subt[20]), .B0(n1962), .B1(
d_ff_Zn[20]), .Y(n1245) );
AO22XLTS U2082 ( .A0(n1961), .A1(result_add_subt[19]), .B0(n1962), .B1(
d_ff_Zn[19]), .Y(n1246) );
AO22XLTS U2083 ( .A0(n1961), .A1(result_add_subt[18]), .B0(n1960), .B1(
d_ff_Zn[18]), .Y(n1247) );
AO22XLTS U2084 ( .A0(n1961), .A1(result_add_subt[17]), .B0(n1960), .B1(
d_ff_Zn[17]), .Y(n1248) );
AO22XLTS U2085 ( .A0(n1961), .A1(result_add_subt[16]), .B0(n1960), .B1(
d_ff_Zn[16]), .Y(n1249) );
AO22XLTS U2086 ( .A0(n1961), .A1(result_add_subt[15]), .B0(n1960), .B1(
d_ff_Zn[15]), .Y(n1250) );
AO22XLTS U2087 ( .A0(n1961), .A1(result_add_subt[14]), .B0(n1960), .B1(
d_ff_Zn[14]), .Y(n1251) );
AO22XLTS U2088 ( .A0(n1961), .A1(result_add_subt[13]), .B0(n1960), .B1(
d_ff_Zn[13]), .Y(n1252) );
AO22XLTS U2089 ( .A0(n1961), .A1(result_add_subt[12]), .B0(n1960), .B1(
d_ff_Zn[12]), .Y(n1253) );
AO22XLTS U2090 ( .A0(n1961), .A1(result_add_subt[11]), .B0(n1960), .B1(
d_ff_Zn[11]), .Y(n1254) );
AO22XLTS U2091 ( .A0(n1961), .A1(result_add_subt[10]), .B0(n1960), .B1(
d_ff_Zn[10]), .Y(n1255) );
AO22XLTS U2092 ( .A0(n1959), .A1(result_add_subt[9]), .B0(n1960), .B1(
d_ff_Zn[9]), .Y(n1256) );
AO22XLTS U2093 ( .A0(n1959), .A1(result_add_subt[8]), .B0(n1958), .B1(
d_ff_Zn[8]), .Y(n1257) );
AO22XLTS U2094 ( .A0(n1959), .A1(result_add_subt[7]), .B0(n1958), .B1(
d_ff_Zn[7]), .Y(n1258) );
AO22XLTS U2095 ( .A0(n1959), .A1(result_add_subt[6]), .B0(n1958), .B1(
d_ff_Zn[6]), .Y(n1259) );
AO22XLTS U2096 ( .A0(n1959), .A1(result_add_subt[5]), .B0(n1958), .B1(
d_ff_Zn[5]), .Y(n1260) );
AO22XLTS U2097 ( .A0(n1959), .A1(result_add_subt[4]), .B0(n1958), .B1(
d_ff_Zn[4]), .Y(n1261) );
AO22XLTS U2098 ( .A0(n1959), .A1(result_add_subt[3]), .B0(n1958), .B1(
d_ff_Zn[3]), .Y(n1262) );
AO22XLTS U2099 ( .A0(n1959), .A1(result_add_subt[2]), .B0(n1958), .B1(
d_ff_Zn[2]), .Y(n1263) );
AO22XLTS U2100 ( .A0(n1959), .A1(result_add_subt[1]), .B0(n1971), .B1(
d_ff_Zn[1]), .Y(n1264) );
AO22XLTS U2101 ( .A0(n1959), .A1(result_add_subt[0]), .B0(n1971), .B1(
d_ff_Zn[0]), .Y(n1265) );
AO22XLTS U2102 ( .A0(n1955), .A1(data_in[63]), .B0(n1954), .B1(d_ff1_Z[63]),
.Y(n1270) );
AO22XLTS U2103 ( .A0(n1953), .A1(data_in[62]), .B0(n1952), .B1(d_ff1_Z[62]),
.Y(n1271) );
AO22XLTS U2104 ( .A0(n1953), .A1(data_in[61]), .B0(n1951), .B1(d_ff1_Z[61]),
.Y(n1272) );
AO22XLTS U2105 ( .A0(n1953), .A1(data_in[60]), .B0(n1951), .B1(d_ff1_Z[60]),
.Y(n1273) );
AO22XLTS U2106 ( .A0(n1953), .A1(data_in[59]), .B0(n1950), .B1(d_ff1_Z[59]),
.Y(n1274) );
AO22XLTS U2107 ( .A0(n1949), .A1(data_in[58]), .B0(n1950), .B1(d_ff1_Z[58]),
.Y(n1275) );
AO22XLTS U2108 ( .A0(n1949), .A1(data_in[57]), .B0(n1940), .B1(d_ff1_Z[57]),
.Y(n1276) );
AO22XLTS U2109 ( .A0(n1949), .A1(data_in[56]), .B0(n1940), .B1(d_ff1_Z[56]),
.Y(n1277) );
AO22XLTS U2110 ( .A0(n1949), .A1(data_in[55]), .B0(n1950), .B1(d_ff1_Z[55]),
.Y(n1278) );
AO22XLTS U2111 ( .A0(n1949), .A1(data_in[54]), .B0(n1952), .B1(d_ff1_Z[54]),
.Y(n1279) );
AO22XLTS U2112 ( .A0(n1948), .A1(data_in[53]), .B0(n1952), .B1(d_ff1_Z[53]),
.Y(n1280) );
AO22XLTS U2113 ( .A0(n1948), .A1(data_in[52]), .B0(n1952), .B1(d_ff1_Z[52]),
.Y(n1281) );
AO22XLTS U2114 ( .A0(n1948), .A1(data_in[51]), .B0(n1947), .B1(d_ff1_Z[51]),
.Y(n1282) );
AO22XLTS U2115 ( .A0(n1948), .A1(data_in[50]), .B0(n1947), .B1(d_ff1_Z[50]),
.Y(n1283) );
AO22XLTS U2116 ( .A0(n1946), .A1(data_in[49]), .B0(n1947), .B1(d_ff1_Z[49]),
.Y(n1284) );
AO22XLTS U2117 ( .A0(n1946), .A1(data_in[48]), .B0(n1947), .B1(d_ff1_Z[48]),
.Y(n1285) );
AO22XLTS U2118 ( .A0(n1946), .A1(data_in[47]), .B0(n1947), .B1(d_ff1_Z[47]),
.Y(n1286) );
AO22XLTS U2119 ( .A0(n1946), .A1(data_in[46]), .B0(n1947), .B1(d_ff1_Z[46]),
.Y(n1287) );
AO22XLTS U2120 ( .A0(n1946), .A1(data_in[45]), .B0(n1947), .B1(d_ff1_Z[45]),
.Y(n1288) );
AO22XLTS U2121 ( .A0(n1946), .A1(data_in[44]), .B0(n1947), .B1(d_ff1_Z[44]),
.Y(n1289) );
AO22XLTS U2122 ( .A0(n1949), .A1(data_in[43]), .B0(n1947), .B1(d_ff1_Z[43]),
.Y(n1290) );
AO22XLTS U2123 ( .A0(n1949), .A1(data_in[42]), .B0(n1947), .B1(d_ff1_Z[42]),
.Y(n1291) );
AO22XLTS U2124 ( .A0(n1949), .A1(data_in[41]), .B0(n1945), .B1(d_ff1_Z[41]),
.Y(n1292) );
AO22XLTS U2125 ( .A0(n1949), .A1(data_in[40]), .B0(n1945), .B1(d_ff1_Z[40]),
.Y(n1293) );
AO22XLTS U2126 ( .A0(n1949), .A1(data_in[39]), .B0(n1945), .B1(d_ff1_Z[39]),
.Y(n1294) );
AO22XLTS U2127 ( .A0(n1948), .A1(data_in[38]), .B0(n1945), .B1(d_ff1_Z[38]),
.Y(n1295) );
AO22XLTS U2128 ( .A0(n1948), .A1(data_in[37]), .B0(n1945), .B1(d_ff1_Z[37]),
.Y(n1296) );
AO22XLTS U2129 ( .A0(n1948), .A1(data_in[36]), .B0(n1945), .B1(d_ff1_Z[36]),
.Y(n1297) );
AO22XLTS U2130 ( .A0(n1948), .A1(data_in[35]), .B0(n1945), .B1(d_ff1_Z[35]),
.Y(n1298) );
AO22XLTS U2131 ( .A0(n1948), .A1(data_in[34]), .B0(n1945), .B1(d_ff1_Z[34]),
.Y(n1299) );
AO22XLTS U2132 ( .A0(n1943), .A1(data_in[33]), .B0(n1945), .B1(d_ff1_Z[33]),
.Y(n1300) );
AO22XLTS U2133 ( .A0(n1943), .A1(data_in[32]), .B0(n1945), .B1(d_ff1_Z[32]),
.Y(n1301) );
AO22XLTS U2134 ( .A0(n1943), .A1(data_in[31]), .B0(n1954), .B1(d_ff1_Z[31]),
.Y(n1302) );
AO22XLTS U2135 ( .A0(n1943), .A1(data_in[30]), .B0(n1954), .B1(d_ff1_Z[30]),
.Y(n1303) );
AO22XLTS U2136 ( .A0(n1955), .A1(data_in[29]), .B0(n1954), .B1(d_ff1_Z[29]),
.Y(n1304) );
AO22XLTS U2137 ( .A0(n1955), .A1(data_in[28]), .B0(n1954), .B1(d_ff1_Z[28]),
.Y(n1305) );
AO22XLTS U2138 ( .A0(n1955), .A1(data_in[27]), .B0(n1954), .B1(d_ff1_Z[27]),
.Y(n1306) );
AO22XLTS U2139 ( .A0(n1955), .A1(data_in[26]), .B0(n1954), .B1(d_ff1_Z[26]),
.Y(n1307) );
AO22XLTS U2140 ( .A0(n1942), .A1(data_in[25]), .B0(n1954), .B1(d_ff1_Z[25]),
.Y(n1308) );
AO22XLTS U2141 ( .A0(n1946), .A1(data_in[24]), .B0(n1954), .B1(d_ff1_Z[24]),
.Y(n1309) );
AO22XLTS U2142 ( .A0(n1946), .A1(data_in[23]), .B0(n1954), .B1(d_ff1_Z[23]),
.Y(n1310) );
AO22XLTS U2143 ( .A0(n1946), .A1(data_in[22]), .B0(n1941), .B1(d_ff1_Z[22]),
.Y(n1311) );
AO22XLTS U2144 ( .A0(n1946), .A1(data_in[21]), .B0(n1941), .B1(d_ff1_Z[21]),
.Y(n1312) );
AO22XLTS U2145 ( .A0(n1943), .A1(data_in[20]), .B0(n1941), .B1(d_ff1_Z[20]),
.Y(n1313) );
AO22XLTS U2146 ( .A0(n1943), .A1(data_in[19]), .B0(n1941), .B1(d_ff1_Z[19]),
.Y(n1314) );
AO22XLTS U2147 ( .A0(n1943), .A1(data_in[18]), .B0(n1941), .B1(d_ff1_Z[18]),
.Y(n1315) );
AO22XLTS U2148 ( .A0(n1943), .A1(data_in[17]), .B0(n1941), .B1(d_ff1_Z[17]),
.Y(n1316) );
AO22XLTS U2149 ( .A0(n1943), .A1(data_in[16]), .B0(n1941), .B1(d_ff1_Z[16]),
.Y(n1317) );
AO22XLTS U2150 ( .A0(n1943), .A1(data_in[15]), .B0(n1941), .B1(d_ff1_Z[15]),
.Y(n1318) );
AO22XLTS U2151 ( .A0(n1942), .A1(data_in[14]), .B0(n1941), .B1(d_ff1_Z[14]),
.Y(n1319) );
AO22XLTS U2152 ( .A0(n1942), .A1(data_in[13]), .B0(n1941), .B1(d_ff1_Z[13]),
.Y(n1320) );
AO22XLTS U2153 ( .A0(n1942), .A1(data_in[12]), .B0(n1940), .B1(d_ff1_Z[12]),
.Y(n1321) );
AO22XLTS U2154 ( .A0(n1942), .A1(data_in[11]), .B0(n1940), .B1(d_ff1_Z[11]),
.Y(n1322) );
AO22XLTS U2155 ( .A0(n1953), .A1(data_in[10]), .B0(n1940), .B1(d_ff1_Z[10]),
.Y(n1323) );
AO22XLTS U2156 ( .A0(n1953), .A1(data_in[9]), .B0(n1940), .B1(d_ff1_Z[9]),
.Y(n1324) );
AO22XLTS U2157 ( .A0(n1953), .A1(data_in[8]), .B0(n1940), .B1(d_ff1_Z[8]),
.Y(n1325) );
AO22XLTS U2158 ( .A0(n1953), .A1(data_in[7]), .B0(n1939), .B1(d_ff1_Z[7]),
.Y(n1326) );
AO22XLTS U2159 ( .A0(n1953), .A1(data_in[6]), .B0(n1939), .B1(d_ff1_Z[6]),
.Y(n1327) );
AO22XLTS U2160 ( .A0(n1953), .A1(data_in[5]), .B0(n1939), .B1(d_ff1_Z[5]),
.Y(n1328) );
AO22XLTS U2161 ( .A0(n1948), .A1(data_in[4]), .B0(n1939), .B1(d_ff1_Z[4]),
.Y(n1329) );
AO22XLTS U2162 ( .A0(n1942), .A1(data_in[3]), .B0(n1939), .B1(d_ff1_Z[3]),
.Y(n1330) );
AO22XLTS U2163 ( .A0(n1942), .A1(data_in[2]), .B0(n1939), .B1(d_ff1_Z[2]),
.Y(n1331) );
AO22XLTS U2164 ( .A0(n1942), .A1(data_in[1]), .B0(n1939), .B1(d_ff1_Z[1]),
.Y(n1332) );
AO22XLTS U2165 ( .A0(n1942), .A1(data_in[0]), .B0(n1952), .B1(d_ff1_Z[0]),
.Y(n1333) );
NOR3X6TS U2166 ( .A(n1503), .B(n1491), .C(n1676), .Y(n1476) );
INVX2TS U2167 ( .A(n1504), .Y(n2195) );
INVX2TS U2168 ( .A(n1877), .Y(n1806) );
CLKBUFX2TS U2169 ( .A(cont_iter_out[3]), .Y(n2049) );
BUFX3TS U2170 ( .A(n2120), .Y(n2176) );
CLKBUFX2TS U2171 ( .A(n1518), .Y(n1526) );
BUFX3TS U2172 ( .A(n1518), .Y(n1525) );
BUFX3TS U2173 ( .A(n1518), .Y(n1527) );
CLKINVX3TS U2174 ( .A(n1524), .Y(n2345) );
CLKINVX3TS U2175 ( .A(n1524), .Y(n2340) );
INVX2TS U2176 ( .A(n1524), .Y(n2344) );
INVX2TS U2177 ( .A(n1524), .Y(n2346) );
INVX2TS U2178 ( .A(n2340), .Y(n1487) );
INVX2TS U2179 ( .A(n1487), .Y(n1488) );
INVX2TS U2180 ( .A(n1487), .Y(n1489) );
INVX2TS U2181 ( .A(n2100), .Y(n1490) );
INVX2TS U2182 ( .A(cont_iter_out[2]), .Y(n1491) );
CLKINVX3TS U2183 ( .A(n1529), .Y(n2320) );
CLKINVX3TS U2184 ( .A(n1529), .Y(n2325) );
CLKINVX3TS U2185 ( .A(n1529), .Y(n2301) );
INVX2TS U2186 ( .A(n1529), .Y(n2300) );
INVX2TS U2187 ( .A(n2301), .Y(n1492) );
INVX2TS U2188 ( .A(n1492), .Y(n1493) );
INVX2TS U2189 ( .A(n1492), .Y(n1494) );
INVX2TS U2190 ( .A(n1477), .Y(n1495) );
CLKINVX3TS U2191 ( .A(n1499), .Y(n1496) );
INVX2TS U2192 ( .A(n1880), .Y(n1497) );
INVX2TS U2193 ( .A(n1880), .Y(n1498) );
INVX2TS U2194 ( .A(n1479), .Y(n1499) );
INVX2TS U2195 ( .A(n1479), .Y(n1500) );
INVX2TS U2196 ( .A(n1487), .Y(n1501) );
INVX2TS U2197 ( .A(n1487), .Y(n1502) );
INVX2TS U2198 ( .A(n2049), .Y(n1503) );
INVX2TS U2199 ( .A(n1503), .Y(n1504) );
INVX2TS U2200 ( .A(n1503), .Y(n1505) );
AOI211X1TS U2201 ( .A0(n1476), .A1(n1486), .B0(n1896), .C0(n1932), .Y(n1898)
);
NOR2X4TS U2202 ( .A(cordic_FSM_state_reg[2]), .B(n2222), .Y(n1932) );
OAI21XLTS U2203 ( .A0(n2237), .A1(n1877), .B0(n1861), .Y(add_subt_dataA[62])
);
AOI222X1TS U2204 ( .A0(d_ff2_Z[46]), .A1(n1792), .B0(d_ff2_Y[46]), .B1(n1497), .C0(d_ff2_X[46]), .C1(n1780), .Y(n1769) );
AOI222X1TS U2205 ( .A0(d_ff2_Z[45]), .A1(n1789), .B0(d_ff2_Y[45]), .B1(n1871), .C0(d_ff2_X[45]), .C1(n1780), .Y(n1778) );
AOI222X1TS U2206 ( .A0(d_ff2_Z[44]), .A1(n1789), .B0(d_ff2_Y[44]), .B1(n1893), .C0(d_ff2_X[44]), .C1(n1780), .Y(n1771) );
AOI222X1TS U2207 ( .A0(d_ff2_Z[43]), .A1(n1727), .B0(d_ff2_Y[43]), .B1(n1782), .C0(d_ff2_X[43]), .C1(n1780), .Y(n1779) );
AOI222X1TS U2208 ( .A0(d_ff2_Z[42]), .A1(n1792), .B0(d_ff2_Y[42]), .B1(n1871), .C0(d_ff2_X[42]), .C1(n1780), .Y(n1772) );
AOI222X1TS U2209 ( .A0(d_ff2_Z[41]), .A1(n1892), .B0(d_ff2_Y[41]), .B1(n1893), .C0(d_ff2_X[41]), .C1(n1780), .Y(n1768) );
AOI222X1TS U2210 ( .A0(d_ff2_Z[40]), .A1(n1727), .B0(d_ff2_Y[40]), .B1(n1782), .C0(d_ff2_X[40]), .C1(n1780), .Y(n1775) );
AOI222X1TS U2211 ( .A0(d_ff2_Z[39]), .A1(n1789), .B0(d_ff2_Y[39]), .B1(n1893), .C0(d_ff2_X[39]), .C1(n1780), .Y(n1781) );
AOI222X1TS U2212 ( .A0(d_ff2_Z[38]), .A1(n1773), .B0(d_ff2_Y[38]), .B1(n1782), .C0(d_ff2_X[38]), .C1(n1780), .Y(n1774) );
AOI222X1TS U2213 ( .A0(d_ff2_Z[37]), .A1(n1727), .B0(d_ff2_Y[37]), .B1(n1776), .C0(d_ff2_X[37]), .C1(n1780), .Y(n1777) );
AOI222X1TS U2214 ( .A0(d_ff2_Z[36]), .A1(n1773), .B0(d_ff2_Y[36]), .B1(n1893), .C0(d_ff2_X[36]), .C1(n1730), .Y(n1746) );
AOI222X1TS U2215 ( .A0(d_ff2_Z[35]), .A1(n1892), .B0(d_ff2_Y[35]), .B1(n1782), .C0(d_ff2_X[35]), .C1(n1730), .Y(n1749) );
AOI222X1TS U2216 ( .A0(d_ff2_Z[34]), .A1(n1727), .B0(d_ff2_Y[34]), .B1(n1776), .C0(d_ff2_X[34]), .C1(n1910), .Y(n1751) );
AOI222X1TS U2217 ( .A0(d_ff2_Z[33]), .A1(n1727), .B0(d_ff2_Y[33]), .B1(n1776), .C0(d_ff2_X[33]), .C1(n1730), .Y(n1743) );
AOI222X1TS U2218 ( .A0(d_ff2_Z[32]), .A1(n1773), .B0(d_ff2_Y[32]), .B1(n1776), .C0(d_ff2_X[32]), .C1(n1909), .Y(n1748) );
AOI222X1TS U2219 ( .A0(d_ff2_Z[31]), .A1(n1773), .B0(d_ff2_Y[31]), .B1(n1776), .C0(d_ff2_X[31]), .C1(n1730), .Y(n1755) );
AOI222X1TS U2220 ( .A0(d_ff2_Z[30]), .A1(n1773), .B0(d_ff2_Y[30]), .B1(n1776), .C0(d_ff2_X[30]), .C1(n1910), .Y(n1745) );
AOI222X1TS U2221 ( .A0(d_ff2_Z[29]), .A1(n1727), .B0(d_ff2_Y[29]), .B1(n1776), .C0(d_ff2_X[29]), .C1(n1730), .Y(n1747) );
AOI222X1TS U2222 ( .A0(d_ff2_Z[28]), .A1(n1773), .B0(d_ff2_Y[28]), .B1(n1776), .C0(d_ff2_X[28]), .C1(n1909), .Y(n1756) );
AOI222X1TS U2223 ( .A0(d_ff2_Z[27]), .A1(n1770), .B0(d_ff2_Y[27]), .B1(n1776), .C0(d_ff2_X[27]), .C1(n1910), .Y(n1731) );
AOI222X1TS U2224 ( .A0(d_ff2_Z[26]), .A1(n1773), .B0(d_ff2_Y[26]), .B1(n1920), .C0(d_ff2_X[26]), .C1(n1752), .Y(n1750) );
AOI222X1TS U2225 ( .A0(d_ff2_Z[25]), .A1(n1773), .B0(d_ff2_Y[25]), .B1(n1920), .C0(d_ff2_X[25]), .C1(n1752), .Y(n1742) );
AOI222X1TS U2226 ( .A0(d_ff2_Z[24]), .A1(n1773), .B0(d_ff2_Y[24]), .B1(n1920), .C0(d_ff2_X[24]), .C1(n1752), .Y(n1754) );
AOI222X1TS U2227 ( .A0(d_ff2_Z[23]), .A1(n1727), .B0(d_ff2_Y[23]), .B1(n1920), .C0(d_ff2_X[23]), .C1(n1752), .Y(n1728) );
AOI222X1TS U2228 ( .A0(d_ff2_Z[22]), .A1(n1792), .B0(d_ff2_Y[22]), .B1(n1920), .C0(d_ff2_X[22]), .C1(n1752), .Y(n1726) );
AOI222X1TS U2229 ( .A0(d_ff2_Z[21]), .A1(n1770), .B0(d_ff2_Y[21]), .B1(n1776), .C0(d_ff2_X[21]), .C1(n1752), .Y(n1732) );
AOI222X1TS U2230 ( .A0(d_ff2_Z[20]), .A1(n1773), .B0(d_ff2_Y[20]), .B1(n1920), .C0(d_ff2_X[20]), .C1(n1752), .Y(n1744) );
AOI222X1TS U2231 ( .A0(d_ff2_Z[19]), .A1(n1734), .B0(d_ff2_Y[19]), .B1(n1920), .C0(d_ff2_X[19]), .C1(n1752), .Y(n1735) );
AOI222X1TS U2232 ( .A0(d_ff2_Z[18]), .A1(n1770), .B0(d_ff2_Y[18]), .B1(n1920), .C0(d_ff2_X[18]), .C1(n1752), .Y(n1729) );
AOI222X1TS U2233 ( .A0(d_ff2_Z[15]), .A1(n1770), .B0(d_ff2_Y[15]), .B1(n1920), .C0(d_ff2_X[15]), .C1(n1910), .Y(n1691) );
AOI222X1TS U2234 ( .A0(d_ff2_Z[14]), .A1(n1727), .B0(d_ff2_Y[14]), .B1(n1920), .C0(d_ff2_X[14]), .C1(n1909), .Y(n1695) );
AOI222X1TS U2235 ( .A0(d_ff2_Z[5]), .A1(n1911), .B0(d_ff2_Y[5]), .B1(n1753),
.C0(d_ff2_X[5]), .C1(n1910), .Y(n1692) );
AOI222X1TS U2236 ( .A0(d_ff2_Z[4]), .A1(n1911), .B0(d_ff2_Y[4]), .B1(n1806),
.C0(d_ff2_X[4]), .C1(n1909), .Y(n1697) );
AOI222X1TS U2237 ( .A0(d_ff2_Z[3]), .A1(n1734), .B0(d_ff2_Y[3]), .B1(n1753),
.C0(d_ff2_X[3]), .C1(n1694), .Y(n1565) );
AOI222X1TS U2238 ( .A0(d_ff2_Z[2]), .A1(n1911), .B0(d_ff2_Y[2]), .B1(n1806),
.C0(d_ff2_X[2]), .C1(n1909), .Y(n1698) );
AOI222X1TS U2239 ( .A0(d_ff2_Z[1]), .A1(n1734), .B0(d_ff2_Y[1]), .B1(n1753),
.C0(d_ff2_X[1]), .C1(n1730), .Y(n1689) );
AOI222X4TS U2240 ( .A0(n2187), .A1(d_ff2_Z[0]), .B0(n1817), .B1(d_ff_Zn[0]),
.C0(n1821), .C1(d_ff1_Z[0]), .Y(n1757) );
INVX1TS U2241 ( .A(beg_add_subt), .Y(n1897) );
OAI21XLTS U2242 ( .A0(n2292), .A1(n1560), .B0(n1556), .Y(n947) );
OAI32X1TS U2243 ( .A0(n1902), .A1(n1901), .A2(n2230), .B0(n1900), .B1(n1899),
.Y(n1267) );
BUFX3TS U2244 ( .A(n1527), .Y(n1901) );
NOR4X1TS U2245 ( .A(cordic_FSM_state_reg[1]), .B(n2223), .C(n2225), .D(n2229), .Y(ready_cordic) );
OAI32X1TS U2246 ( .A0(cordic_FSM_state_reg[2]), .A1(beg_fsm_cordic), .A2(
n1930), .B0(n1929), .B1(n2225), .Y(n1935) );
OAI21X2TS U2247 ( .A0(n1571), .A1(n2080), .B0(n2065), .Y(n2060) );
NOR2X2TS U2248 ( .A(n1676), .B(n2080), .Y(n1937) );
OAI21X2TS U2249 ( .A0(n1678), .A1(n1563), .B0(n2065), .Y(n2048) );
NOR2X2TS U2250 ( .A(n2100), .B(n1499), .Y(n1678) );
OAI211XLTS U2251 ( .A0(n1569), .A1(n2087), .B0(n2023), .C0(n1564), .Y(n938)
);
OAI211XLTS U2252 ( .A0(n2076), .A1(n1515), .B0(n2062), .C0(n2023), .Y(n926)
);
OAI21X2TS U2253 ( .A0(n2051), .A1(n2039), .B0(n2089), .Y(n2023) );
CLKINVX3TS U2254 ( .A(n1860), .Y(n1920) );
NOR2X2TS U2255 ( .A(n2100), .B(n1496), .Y(n1699) );
CLKINVX3TS U2256 ( .A(n1525), .Y(n2319) );
CLKINVX3TS U2257 ( .A(n1525), .Y(n2297) );
CLKINVX3TS U2258 ( .A(n1525), .Y(n2298) );
CLKINVX3TS U2259 ( .A(n1525), .Y(n2299) );
CLKINVX3TS U2260 ( .A(n1525), .Y(n2318) );
AOI222X4TS U2261 ( .A0(n1911), .A1(d_ff3_LUT_out[44]), .B0(n1887), .B1(
d_ff3_sh_x_out[44]), .C0(n1886), .C1(d_ff3_sh_y_out[44]), .Y(n1764) );
AOI222X4TS U2262 ( .A0(n1911), .A1(d_ff3_LUT_out[52]), .B0(n1887), .B1(
d_ff3_sh_x_out[52]), .C0(n1886), .C1(d_ff3_sh_y_out[52]), .Y(n1761) );
AOI222X4TS U2263 ( .A0(n1911), .A1(d_ff3_LUT_out[49]), .B0(n1887), .B1(
d_ff3_sh_x_out[49]), .C0(n1886), .C1(d_ff3_sh_y_out[49]), .Y(n1760) );
AOI222X4TS U2264 ( .A0(n1911), .A1(d_ff3_LUT_out[46]), .B0(n1887), .B1(
d_ff3_sh_x_out[46]), .C0(n1886), .C1(d_ff3_sh_y_out[46]), .Y(n1758) );
CLKINVX3TS U2265 ( .A(n2185), .Y(n1842) );
CLKINVX3TS U2266 ( .A(n2185), .Y(n1840) );
CLKINVX3TS U2267 ( .A(n2106), .Y(n1724) );
CLKINVX3TS U2268 ( .A(n2106), .Y(n1717) );
CLKINVX3TS U2269 ( .A(n2106), .Y(n1833) );
CLKINVX3TS U2270 ( .A(n2106), .Y(n2108) );
OAI33X1TS U2271 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n2238), .B0(n2226), .B1(n2224), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n1536) );
CLKINVX3TS U2272 ( .A(n1527), .Y(n2294) );
CLKINVX3TS U2273 ( .A(n1527), .Y(n2296) );
CLKINVX3TS U2274 ( .A(n1527), .Y(n2312) );
CLKINVX3TS U2275 ( .A(n1527), .Y(n2295) );
CLKINVX3TS U2276 ( .A(n1527), .Y(n2313) );
CLKBUFX3TS U2277 ( .A(n1492), .Y(n1524) );
CLKINVX3TS U2278 ( .A(n1518), .Y(n2305) );
CLKINVX3TS U2279 ( .A(n1518), .Y(n2304) );
CLKINVX3TS U2280 ( .A(n1518), .Y(n2332) );
CLKINVX3TS U2281 ( .A(n1518), .Y(n2331) );
CLKINVX3TS U2282 ( .A(n1526), .Y(n2358) );
CLKINVX3TS U2283 ( .A(n1526), .Y(n2363) );
CLKINVX3TS U2284 ( .A(n1526), .Y(n2362) );
CLKINVX3TS U2285 ( .A(n1526), .Y(n2359) );
INVX2TS U2286 ( .A(n1901), .Y(n1506) );
INVX2TS U2287 ( .A(n1487), .Y(n1507) );
INVX2TS U2288 ( .A(n1527), .Y(n1508) );
INVX2TS U2289 ( .A(n1527), .Y(n1509) );
CLKINVX3TS U2290 ( .A(n1492), .Y(n2356) );
INVX2TS U2291 ( .A(n1525), .Y(n1510) );
CLKINVX3TS U2292 ( .A(n1492), .Y(n2357) );
CLKINVX3TS U2293 ( .A(n1487), .Y(n2351) );
CLKINVX3TS U2294 ( .A(n1492), .Y(n2352) );
CLKINVX3TS U2295 ( .A(n1487), .Y(n2353) );
BUFX3TS U2296 ( .A(n1525), .Y(n1529) );
CLKINVX3TS U2297 ( .A(n1901), .Y(n2321) );
CLKINVX3TS U2298 ( .A(n1901), .Y(n2307) );
CLKINVX3TS U2299 ( .A(n1901), .Y(n2303) );
CLKINVX3TS U2300 ( .A(n1901), .Y(n2306) );
CLKINVX3TS U2301 ( .A(n1901), .Y(n2322) );
INVX2TS U2302 ( .A(n1530), .Y(n1511) );
CLKINVX3TS U2303 ( .A(n1530), .Y(n2328) );
CLKINVX3TS U2304 ( .A(n1530), .Y(n2309) );
CLKINVX3TS U2305 ( .A(n1530), .Y(n2310) );
CLKINVX3TS U2306 ( .A(n1530), .Y(n2311) );
BUFX3TS U2307 ( .A(n1527), .Y(n1530) );
CLKINVX3TS U2308 ( .A(n1525), .Y(n2323) );
CLKINVX3TS U2309 ( .A(n1529), .Y(n2336) );
CLKINVX3TS U2310 ( .A(n1524), .Y(n2337) );
CLKINVX3TS U2311 ( .A(n1487), .Y(n2338) );
NOR2X2TS U2312 ( .A(n1504), .B(n2227), .Y(n2055) );
CLKINVX3TS U2313 ( .A(n1530), .Y(n2350) );
AOI32X4TS U2314 ( .A0(n2195), .A1(n2213), .A2(n1552), .B0(d_ff3_sh_y_out[55]), .B1(n2087), .Y(n1551) );
OAI21XLTS U2315 ( .A0(n2065), .A1(d_ff3_LUT_out[1]), .B0(n2029), .Y(n1570)
);
OAI21XLTS U2316 ( .A0(n2213), .A1(d_ff3_LUT_out[6]), .B0(n2029), .Y(n2030)
);
OAI21XLTS U2317 ( .A0(n2065), .A1(d_ff3_LUT_out[7]), .B0(n2048), .Y(n1564)
);
OAI21XLTS U2318 ( .A0(n2065), .A1(d_ff3_LUT_out[14]), .B0(n2060), .Y(n1562)
);
AOI32X4TS U2319 ( .A0(n2100), .A1(n2076), .A2(n1553), .B0(d_ff3_LUT_out[54]),
.B1(n2087), .Y(n1554) );
OAI32X4TS U2320 ( .A0(n2044), .A1(n2043), .A2(n2054), .B0(n2076), .B1(
d_ff3_LUT_out[9]), .Y(n2033) );
OAI32X4TS U2321 ( .A0(n2044), .A1(n1937), .A2(n2042), .B0(d_ff3_LUT_out[26]),
.B1(n2213), .Y(n1538) );
NOR2X2TS U2322 ( .A(n1679), .B(n2152), .Y(n2085) );
NOR2X1TS U2323 ( .A(d_ff2_Y[61]), .B(n2150), .Y(n2149) );
OAI211XLTS U2324 ( .A0(n1682), .A1(n2025), .B0(n1577), .C0(n1680), .Y(n912)
);
OAI211XLTS U2325 ( .A0(n1574), .A1(n2073), .B0(n1680), .C0(n1573), .Y(n942)
);
OAI21X2TS U2326 ( .A0(n2040), .A1(n2050), .B0(n2089), .Y(n1680) );
NOR2X2TS U2327 ( .A(d_ff2_Y[57]), .B(n2142), .Y(n2141) );
NOR2X2TS U2328 ( .A(d_ff2_Y[59]), .B(n2144), .Y(n2147) );
NOR2XLTS U2329 ( .A(n1476), .B(n2066), .Y(n2058) );
AOI222X4TS U2330 ( .A0(n1837), .A1(d_ff2_Z[54]), .B0(n1821), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n1835), .Y(n1836) );
AOI222X4TS U2331 ( .A0(n1837), .A1(d_ff2_Z[47]), .B0(n1719), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n1817), .Y(n1714) );
AOI222X4TS U2332 ( .A0(n1837), .A1(d_ff2_Z[49]), .B0(n1719), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n1817), .Y(n1712) );
AOI222X4TS U2333 ( .A0(n1837), .A1(d_ff2_Z[50]), .B0(n1719), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n1835), .Y(n1711) );
AOI222X4TS U2334 ( .A0(n1837), .A1(d_ff2_Z[51]), .B0(n1719), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n1835), .Y(n1710) );
AOI222X4TS U2335 ( .A0(n1837), .A1(d_ff2_Z[48]), .B0(n1719), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n1835), .Y(n1705) );
CLKINVX3TS U2336 ( .A(n2102), .Y(n1837) );
CLKINVX3TS U2337 ( .A(n2102), .Y(n1844) );
CLKINVX3TS U2338 ( .A(n2102), .Y(n2183) );
CLKINVX3TS U2339 ( .A(n2102), .Y(n2105) );
AOI222X4TS U2340 ( .A0(d_ff2_Z[6]), .A1(n1734), .B0(d_ff2_Y[6]), .B1(n1854),
.C0(d_ff2_X[6]), .C1(n1567), .Y(n1568) );
AOI222X4TS U2341 ( .A0(d_ff2_Z[7]), .A1(n1734), .B0(d_ff2_Y[7]), .B1(n1854),
.C0(d_ff2_X[7]), .C1(n1694), .Y(n1566) );
AOI222X4TS U2342 ( .A0(d_ff2_Z[8]), .A1(n1734), .B0(d_ff2_Y[8]), .B1(n1854),
.C0(d_ff2_X[8]), .C1(n1694), .Y(n1701) );
AOI222X4TS U2343 ( .A0(d_ff2_Z[10]), .A1(n1734), .B0(d_ff2_Y[10]), .B1(n1854), .C0(d_ff2_X[10]), .C1(n1730), .Y(n1688) );
AOI222X4TS U2344 ( .A0(d_ff2_Z[11]), .A1(n1770), .B0(d_ff2_Y[11]), .B1(n1854), .C0(d_ff2_X[11]), .C1(n1909), .Y(n1696) );
AOI222X4TS U2345 ( .A0(d_ff2_Z[12]), .A1(n1734), .B0(d_ff2_Y[12]), .B1(n1854), .C0(d_ff2_X[12]), .C1(n1910), .Y(n1693) );
AOI222X4TS U2346 ( .A0(d_ff2_Z[13]), .A1(n1734), .B0(d_ff2_Y[13]), .B1(n1854), .C0(d_ff2_X[13]), .C1(n1730), .Y(n1690) );
AOI222X4TS U2347 ( .A0(d_ff2_Z[16]), .A1(n1770), .B0(d_ff2_Y[16]), .B1(n1854), .C0(d_ff2_X[16]), .C1(n1730), .Y(n1687) );
AOI222X4TS U2348 ( .A0(d_ff2_Z[17]), .A1(n1734), .B0(d_ff2_Y[17]), .B1(n1854), .C0(d_ff2_X[17]), .C1(n1752), .Y(n1733) );
OAI21XLTS U2349 ( .A0(n1989), .A1(n1544), .B0(n1543), .Y(n1269) );
OAI21XLTS U2350 ( .A0(n2093), .A1(n1542), .B0(n1541), .Y(n1268) );
CLKBUFX2TS U2351 ( .A(cordic_FSM_state_reg[3]), .Y(n1512) );
NOR4X2TS U2352 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n2225), .D(n2222), .Y(n1902) );
OAI21X2TS U2353 ( .A0(n2049), .A1(n2032), .B0(n2065), .Y(n2086) );
INVX2TS U2354 ( .A(n1528), .Y(n1513) );
INVX2TS U2355 ( .A(n1528), .Y(n1514) );
BUFX3TS U2356 ( .A(n1527), .Y(n1528) );
NOR4X4TS U2357 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]),
.C(n2223), .D(n2229), .Y(ack_add_subt) );
BUFX3TS U2358 ( .A(n1770), .Y(n1792) );
BUFX3TS U2359 ( .A(n1694), .Y(n1916) );
BUFX3TS U2360 ( .A(n1567), .Y(n1694) );
BUFX3TS U2361 ( .A(n1683), .Y(n1736) );
BUFX3TS U2362 ( .A(n1664), .Y(n1683) );
AND3X2TS U2363 ( .A(n1896), .B(n2225), .C(n2229), .Y(n1518) );
OR4X2TS U2364 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[1]),
.C(n2223), .D(n1486), .Y(n1519) );
OR2X1TS U2365 ( .A(n1550), .B(d_ff2_Y[55]), .Y(n1549) );
OAI21XLTS U2366 ( .A0(n2065), .A1(d_ff3_LUT_out[25]), .B0(n2060), .Y(n2061)
);
INVX2TS U2367 ( .A(d_ff_Yn[57]), .Y(n2125) );
OAI211XLTS U2368 ( .A0(n2188), .A1(n1938), .B0(n1500), .C0(n1952), .Y(n1658)
);
OAI21XLTS U2369 ( .A0(n2126), .A1(n1657), .B0(n1650), .Y(n957) );
OAI21XLTS U2370 ( .A0(n2290), .A1(n1657), .B0(n1635), .Y(n971) );
OAI21XLTS U2371 ( .A0(n2277), .A1(n1604), .B0(n1585), .Y(n997) );
OAI21XLTS U2372 ( .A0(n2264), .A1(n1624), .B0(n1616), .Y(n1023) );
OAI21XLTS U2373 ( .A0(n2251), .A1(n1629), .B0(n1618), .Y(n1049) );
OAI21XLTS U2374 ( .A0(n2244), .A1(n1645), .B0(n1631), .Y(n1063) );
OAI21XLTS U2375 ( .A0(n2234), .A1(n1860), .B0(n1522), .Y(add_subt_dataA[52])
);
BUFX3TS U2376 ( .A(n2154), .Y(n2215) );
INVX2TS U2377 ( .A(n2215), .Y(n2217) );
NOR2X2TS U2378 ( .A(d_ff2_Y[52]), .B(n2188), .Y(n2136) );
NAND2X1TS U2379 ( .A(d_ff2_Y[53]), .B(n1495), .Y(n1520) );
AOI22X1TS U2380 ( .A0(n1500), .A1(n1480), .B0(n2136), .B1(n1520), .Y(n1534)
);
AOI22X1TS U2381 ( .A0(n1550), .A1(d_ff2_Y[55]), .B0(n1503), .B1(n1549), .Y(
n2139) );
INVX2TS U2382 ( .A(d_ff2_Y[56]), .Y(n2138) );
INVX2TS U2383 ( .A(d_ff2_Y[58]), .Y(n2127) );
INVX2TS U2384 ( .A(d_ff2_Y[60]), .Y(n2146) );
XOR2X1TS U2385 ( .A(d_ff2_Y[62]), .B(n2149), .Y(n1521) );
BUFX3TS U2386 ( .A(n1519), .Y(n2156) );
BUFX3TS U2387 ( .A(n2156), .Y(n2044) );
BUFX3TS U2388 ( .A(n2044), .Y(n2153) );
OR2X2TS U2389 ( .A(sel_mux_2_reg[1]), .B(n2230), .Y(n1860) );
NAND2X1TS U2390 ( .A(n2230), .B(sel_mux_2_reg[1]), .Y(n1906) );
BUFX3TS U2391 ( .A(n1881), .Y(n1878) );
NOR2X1TS U2392 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n1567) );
BUFX3TS U2393 ( .A(n1909), .Y(n1919) );
AOI22X1TS U2394 ( .A0(n1878), .A1(d_ff2_Z[52]), .B0(d_ff2_X[52]), .B1(n1919),
.Y(n1522) );
AOI22X1TS U2395 ( .A0(d_ff2_X[55]), .A1(n1916), .B0(d_ff2_Z[55]), .B1(n1878),
.Y(n1523) );
NOR2X2TS U2396 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[1]),
.Y(n1896) );
INVX2TS U2397 ( .A(n1524), .Y(n2308) );
INVX2TS U2398 ( .A(n1529), .Y(n2302) );
INVX2TS U2399 ( .A(n1901), .Y(n2339) );
INVX2TS U2400 ( .A(n1901), .Y(n2342) );
INVX2TS U2401 ( .A(n1524), .Y(n2347) );
INVX2TS U2402 ( .A(n1492), .Y(n2348) );
INVX2TS U2403 ( .A(n1524), .Y(n2349) );
INVX2TS U2404 ( .A(n1901), .Y(n2341) );
INVX2TS U2405 ( .A(n1528), .Y(n2333) );
INVX2TS U2406 ( .A(n1528), .Y(n2334) );
INVX2TS U2407 ( .A(n1528), .Y(n2335) );
INVX2TS U2408 ( .A(n1528), .Y(n2317) );
INVX2TS U2409 ( .A(n1529), .Y(n2324) );
INVX2TS U2410 ( .A(n1529), .Y(n2354) );
INVX2TS U2411 ( .A(n1492), .Y(n2355) );
INVX2TS U2412 ( .A(n1529), .Y(n2365) );
INVX2TS U2413 ( .A(n1525), .Y(n2364) );
INVX2TS U2414 ( .A(n1530), .Y(n2361) );
INVX2TS U2415 ( .A(n1528), .Y(n2360) );
INVX2TS U2416 ( .A(n1525), .Y(n2343) );
INVX2TS U2417 ( .A(n1528), .Y(n2314) );
INVX2TS U2418 ( .A(n1528), .Y(n2315) );
INVX2TS U2419 ( .A(n1528), .Y(n2316) );
INVX2TS U2420 ( .A(n1530), .Y(n2329) );
INVX2TS U2421 ( .A(n1530), .Y(n2330) );
INVX2TS U2422 ( .A(n1529), .Y(n2326) );
INVX2TS U2423 ( .A(n1530), .Y(n2327) );
INVX2TS U2424 ( .A(n1526), .Y(n2366) );
NAND2X1TS U2425 ( .A(n2229), .B(n2222), .Y(n1930) );
INVX2TS U2426 ( .A(n1930), .Y(n1532) );
AOI21X1TS U2427 ( .A0(cordic_FSM_state_reg[3]), .A1(cordic_FSM_state_reg[2]),
.B0(n2222), .Y(n1531) );
AOI32X1TS U2428 ( .A0(beg_fsm_cordic), .A1(cordic_FSM_state_reg[0]), .A2(
n1532), .B0(n2223), .B1(n1531), .Y(n1533) );
BUFX3TS U2429 ( .A(n2156), .Y(n2154) );
BUFX3TS U2430 ( .A(n2154), .Y(n2091) );
INVX2TS U2431 ( .A(ack_add_subt), .Y(n1575) );
BUFX3TS U2432 ( .A(n2154), .Y(n2171) );
INVX2TS U2433 ( .A(n2171), .Y(n2221) );
AND3X2TS U2434 ( .A(cordic_FSM_state_reg[2]), .B(n1896), .C(n2229), .Y(n2120) );
NAND2X1TS U2435 ( .A(n2170), .B(sel_mux_1_reg), .Y(n2181) );
BUFX3TS U2436 ( .A(n2182), .Y(n2166) );
OA22X1TS U2437 ( .A0(n2106), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n2166),
.Y(n658) );
BUFX3TS U2438 ( .A(n2182), .Y(n2177) );
OA22X1TS U2439 ( .A0(n2176), .A1(d_ff2_X[36]), .B0(d_ff_Xn[36]), .B1(n2177),
.Y(n624) );
CLKBUFX2TS U2440 ( .A(n2176), .Y(n2102) );
OA22X1TS U2441 ( .A0(n2102), .A1(d_ff2_X[48]), .B0(d_ff_Xn[48]), .B1(n2177),
.Y(n600) );
OA22X1TS U2442 ( .A0(n2120), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n2166),
.Y(n638) );
CLKBUFX2TS U2443 ( .A(n2176), .Y(n2106) );
OA22X1TS U2444 ( .A0(n2106), .A1(d_ff2_X[49]), .B0(d_ff_Xn[49]), .B1(n2177),
.Y(n598) );
OA22X1TS U2445 ( .A0(n2120), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n2166),
.Y(n644) );
OA22X1TS U2446 ( .A0(n2120), .A1(d_ff2_X[31]), .B0(d_ff_Xn[31]), .B1(n2166),
.Y(n634) );
OA22X1TS U2447 ( .A0(n2120), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n2166),
.Y(n640) );
OA22X1TS U2448 ( .A0(n2120), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n2166),
.Y(n648) );
BUFX3TS U2449 ( .A(n2181), .Y(n2180) );
BUFX3TS U2450 ( .A(n2180), .Y(n2185) );
OA22X1TS U2451 ( .A0(n2120), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n2185),
.Y(n668) );
OA22X1TS U2452 ( .A0(n2176), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n2185),
.Y(n670) );
CLKBUFX2TS U2453 ( .A(n2120), .Y(n2178) );
BUFX3TS U2454 ( .A(n2181), .Y(n2182) );
BUFX3TS U2455 ( .A(n2182), .Y(n2131) );
OA22X1TS U2456 ( .A0(n2178), .A1(d_ff2_X[0]), .B0(d_ff_Xn[0]), .B1(n2131),
.Y(n696) );
INVX2TS U2457 ( .A(n1896), .Y(n1929) );
CLKBUFX2TS U2458 ( .A(n2008), .Y(n2018) );
INVX2TS U2459 ( .A(n2018), .Y(n2022) );
XOR2X1TS U2460 ( .A(data_output2_63_), .B(n1536), .Y(n1537) );
CLKBUFX2TS U2461 ( .A(n2008), .Y(n2016) );
CLKBUFX2TS U2462 ( .A(n2016), .Y(n2021) );
NAND2X2TS U2463 ( .A(n2100), .B(n1499), .Y(n1676) );
INVX2TS U2464 ( .A(n2055), .Y(n2080) );
NAND3X1TS U2465 ( .A(n2055), .B(n2188), .C(n1495), .Y(n1569) );
INVX2TS U2466 ( .A(n1569), .Y(n2042) );
OAI211X4TS U2467 ( .A0(n1505), .A1(n1496), .B0(n2076), .C0(n2080), .Y(n2053)
);
NAND2X1TS U2468 ( .A(n1538), .B(n2053), .Y(n919) );
BUFX3TS U2469 ( .A(n2154), .Y(n2152) );
INVX2TS U2470 ( .A(n1476), .Y(n2101) );
XNOR2X1TS U2471 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n1540) );
CLKXOR2X2TS U2472 ( .A(d_ff1_shift_region_flag_out[0]), .B(n1540), .Y(n1989)
);
NAND4X1TS U2473 ( .A(cordic_FSM_state_reg[3]), .B(n1896), .C(ready_add_subt),
.D(n2225), .Y(n1990) );
NOR2X2TS U2474 ( .A(n1900), .B(n1990), .Y(n1974) );
BUFX3TS U2475 ( .A(n1974), .Y(n1979) );
BUFX3TS U2476 ( .A(n1979), .Y(n1987) );
OAI2BB2XLTS U2477 ( .B0(n1987), .B1(n2129), .A0N(n1979), .A1N(
result_add_subt[60]), .Y(n1141) );
OAI2BB2XLTS U2478 ( .B0(n1987), .B1(n2128), .A0N(n1976), .A1N(
result_add_subt[59]), .Y(n1142) );
OAI2BB2XLTS U2479 ( .B0(n1987), .B1(n2130), .A0N(n1976), .A1N(
result_add_subt[61]), .Y(n1140) );
OAI2BB2XLTS U2480 ( .B0(n1987), .B1(n2132), .A0N(n1976), .A1N(
result_add_subt[62]), .Y(n1139) );
INVX2TS U2481 ( .A(rst), .Y(n564) );
NOR4X1TS U2482 ( .A(cordic_FSM_state_reg[3]), .B(n2223), .C(n1486), .D(n2222), .Y(beg_add_subt) );
NOR3X2TS U2483 ( .A(n1505), .B(cont_iter_out[2]), .C(n1500), .Y(n2040) );
INVX2TS U2484 ( .A(n2037), .Y(n2093) );
INVX2TS U2485 ( .A(n1902), .Y(n1899) );
NAND2X2TS U2486 ( .A(n2100), .B(n1496), .Y(n2078) );
INVX2TS U2487 ( .A(n2078), .Y(n2064) );
NOR2X2TS U2488 ( .A(d_ff2_X[52]), .B(n2188), .Y(n2191) );
NAND2X1TS U2489 ( .A(d_ff2_X[53]), .B(n1495), .Y(n1546) );
AOI22X1TS U2490 ( .A0(n1499), .A1(n2228), .B0(n2191), .B1(n1546), .Y(n2193)
);
AOI2BB1X1TS U2491 ( .A0N(n2197), .A1N(d_ff2_X[55]), .B0(n2196), .Y(n1548) );
BUFX3TS U2492 ( .A(n2154), .Y(n2087) );
NOR2X2TS U2493 ( .A(n2087), .B(n1478), .Y(n2027) );
AOI22X1TS U2494 ( .A0(n1548), .A1(n2027), .B0(d_ff3_sh_x_out[55]), .B1(n2091), .Y(n1547) );
OAI31X1TS U2495 ( .A0(n2049), .A1(n1548), .A2(n2087), .B0(n1547), .Y(n578)
);
INVX2TS U2496 ( .A(n2027), .Y(n1682) );
OAI2BB1X1TS U2497 ( .A0N(d_ff2_Y[55]), .A1N(n1550), .B0(n1549), .Y(n1552) );
NAND2X1TS U2498 ( .A(n2227), .B(n1676), .Y(n2036) );
NOR2XLTS U2499 ( .A(n2227), .B(n1496), .Y(n1553) );
NAND2BX1TS U2500 ( .AN(n1605), .B(sel_mux_3_reg), .Y(n1560) );
CLKBUFX2TS U2501 ( .A(n1605), .Y(n1640) );
BUFX3TS U2502 ( .A(n1640), .Y(n1652) );
AOI22X1TS U2503 ( .A0(d_ff_Xn[63]), .A1(n1555), .B0(data_output2_63_), .B1(
n1652), .Y(n1556) );
AOI22X1TS U2504 ( .A0(d_ff_Xn[61]), .A1(n1555), .B0(sign_inv_out[61]), .B1(
n1652), .Y(n1557) );
INVX2TS U2505 ( .A(n2180), .Y(n2118) );
AOI222X1TS U2506 ( .A0(n2187), .A1(d_ff2_Z[6]), .B0(n1683), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n2118), .Y(n1558) );
INVX2TS U2507 ( .A(n1558), .Y(n883) );
AOI22X1TS U2508 ( .A0(d_ff_Xn[60]), .A1(n1555), .B0(sign_inv_out[60]), .B1(
n1652), .Y(n1559) );
AOI22X1TS U2509 ( .A0(d_ff_Xn[62]), .A1(n1555), .B0(sign_inv_out[62]), .B1(
n1652), .Y(n1561) );
NAND2X2TS U2510 ( .A(n1499), .B(n2227), .Y(n2025) );
NOR2X2TS U2511 ( .A(n1504), .B(n2025), .Y(n2099) );
NAND2X1TS U2512 ( .A(n2100), .B(n2099), .Y(n2082) );
OAI21X2TS U2513 ( .A0(n1500), .A1(n2080), .B0(n2082), .Y(n2038) );
NAND2X1TS U2514 ( .A(n2065), .B(n2038), .Y(n2062) );
NAND2X2TS U2515 ( .A(n2099), .B(n2188), .Y(n2088) );
INVX2TS U2516 ( .A(n2088), .Y(n2051) );
NAND2X1TS U2517 ( .A(n1505), .B(n2227), .Y(n1563) );
OAI32X4TS U2518 ( .A0(n1500), .A1(n2100), .A2(n1563), .B0(n2080), .B1(n1496),
.Y(n2039) );
INVX2TS U2519 ( .A(n1699), .Y(n1571) );
BUFX3TS U2520 ( .A(n1770), .Y(n1734) );
INVX2TS U2521 ( .A(n1565), .Y(add_subt_dataA[3]) );
INVX2TS U2522 ( .A(n1880), .Y(n1854) );
INVX2TS U2523 ( .A(n1566), .Y(add_subt_dataA[7]) );
INVX2TS U2524 ( .A(n1568), .Y(add_subt_dataA[6]) );
NAND2X2TS U2525 ( .A(cont_iter_out[2]), .B(n2027), .Y(n2073) );
NAND2X1TS U2526 ( .A(n2065), .B(n2039), .Y(n2047) );
NAND2X1TS U2527 ( .A(n2082), .B(n1569), .Y(n2050) );
NOR2X1TS U2528 ( .A(n2087), .B(n2050), .Y(n2031) );
OAI31X1TS U2529 ( .A0(n1505), .A1(cont_iter_out[2]), .A2(n2078), .B0(n2031),
.Y(n2029) );
INVX2TS U2530 ( .A(n1678), .Y(n1574) );
OAI22X1TS U2531 ( .A0(n2076), .A1(d_ff3_LUT_out[3]), .B0(n1572), .B1(n2048),
.Y(n1573) );
NOR3X2TS U2532 ( .A(n1476), .B(n2231), .C(n1575), .Y(n1908) );
INVX2TS U2533 ( .A(n2073), .Y(n2063) );
AOI21X1TS U2534 ( .A0(d_ff3_LUT_out[33]), .A1(n2091), .B0(n2063), .Y(n1577)
);
BUFX3TS U2535 ( .A(n1475), .Y(n1599) );
BUFX3TS U2536 ( .A(n1555), .Y(n1597) );
BUFX3TS U2537 ( .A(n1605), .Y(n1654) );
AOI22X1TS U2538 ( .A0(d_ff_Xn[47]), .A1(n1597), .B0(sign_inv_out[47]), .B1(
n1654), .Y(n1578) );
BUFX3TS U2539 ( .A(n1605), .Y(n1601) );
AOI22X1TS U2540 ( .A0(d_ff_Xn[41]), .A1(n1597), .B0(sign_inv_out[41]), .B1(
n1601), .Y(n1579) );
AOI22X1TS U2541 ( .A0(d_ff_Xn[49]), .A1(n1597), .B0(sign_inv_out[49]), .B1(
n1654), .Y(n1580) );
AOI22X1TS U2542 ( .A0(d_ff_Xn[44]), .A1(n1597), .B0(sign_inv_out[44]), .B1(
n1654), .Y(n1581) );
BUFX3TS U2543 ( .A(n1475), .Y(n1604) );
BUFX3TS U2544 ( .A(n1555), .Y(n1602) );
AOI22X1TS U2545 ( .A0(d_ff_Xn[35]), .A1(n1602), .B0(sign_inv_out[35]), .B1(
n1601), .Y(n1582) );
AOI22X1TS U2546 ( .A0(d_ff_Xn[37]), .A1(n1602), .B0(sign_inv_out[37]), .B1(
n1601), .Y(n1583) );
AOI22X1TS U2547 ( .A0(d_ff_Xn[45]), .A1(n1597), .B0(sign_inv_out[45]), .B1(
n1654), .Y(n1584) );
AOI22X1TS U2548 ( .A0(d_ff_Xn[38]), .A1(n1602), .B0(sign_inv_out[38]), .B1(
n1601), .Y(n1585) );
AOI22X1TS U2549 ( .A0(d_ff_Xn[39]), .A1(n1602), .B0(sign_inv_out[39]), .B1(
n1601), .Y(n1586) );
BUFX3TS U2550 ( .A(n1605), .Y(n1619) );
AOI22X1TS U2551 ( .A0(d_ff_Xn[32]), .A1(n1602), .B0(sign_inv_out[32]), .B1(
n1619), .Y(n1587) );
AOI22X1TS U2552 ( .A0(d_ff_Xn[31]), .A1(n1602), .B0(sign_inv_out[31]), .B1(
n1619), .Y(n1588) );
AOI22X1TS U2553 ( .A0(d_ff_Xn[46]), .A1(n1597), .B0(sign_inv_out[46]), .B1(
n1654), .Y(n1589) );
AOI22X1TS U2554 ( .A0(d_ff_Xn[48]), .A1(n1597), .B0(sign_inv_out[48]), .B1(
n1654), .Y(n1590) );
AOI22X1TS U2555 ( .A0(d_ff_Xn[30]), .A1(n1602), .B0(sign_inv_out[30]), .B1(
n1619), .Y(n1591) );
AOI22X1TS U2556 ( .A0(d_ff_Xn[43]), .A1(n1597), .B0(sign_inv_out[43]), .B1(
n1601), .Y(n1592) );
AOI22X1TS U2557 ( .A0(d_ff_Xn[36]), .A1(n1602), .B0(sign_inv_out[36]), .B1(
n1601), .Y(n1593) );
BUFX3TS U2558 ( .A(n1475), .Y(n1624) );
BUFX3TS U2559 ( .A(n1555), .Y(n1622) );
AOI22X1TS U2560 ( .A0(d_ff_Xn[29]), .A1(n1622), .B0(sign_inv_out[29]), .B1(
n1619), .Y(n1594) );
AOI22X1TS U2561 ( .A0(d_ff_Xn[42]), .A1(n1597), .B0(sign_inv_out[42]), .B1(
n1601), .Y(n1595) );
AOI22X1TS U2562 ( .A0(d_ff_Xn[28]), .A1(n1622), .B0(sign_inv_out[28]), .B1(
n1619), .Y(n1596) );
AOI22X1TS U2563 ( .A0(d_ff_Xn[40]), .A1(n1597), .B0(sign_inv_out[40]), .B1(
n1601), .Y(n1598) );
AOI22X1TS U2564 ( .A0(d_ff_Xn[33]), .A1(n1602), .B0(sign_inv_out[33]), .B1(
n1619), .Y(n1600) );
AOI22X1TS U2565 ( .A0(d_ff_Xn[34]), .A1(n1602), .B0(sign_inv_out[34]), .B1(
n1601), .Y(n1603) );
BUFX3TS U2566 ( .A(n1605), .Y(n1626) );
AOI22X1TS U2567 ( .A0(d_ff_Xn[21]), .A1(n1622), .B0(sign_inv_out[21]), .B1(
n1626), .Y(n1606) );
BUFX3TS U2568 ( .A(n1475), .Y(n1629) );
BUFX3TS U2569 ( .A(n1555), .Y(n1627) );
AOI22X1TS U2570 ( .A0(d_ff_Xn[19]), .A1(n1627), .B0(sign_inv_out[19]), .B1(
n1626), .Y(n1607) );
AOI22X1TS U2571 ( .A0(d_ff_Xn[27]), .A1(n1622), .B0(sign_inv_out[27]), .B1(
n1619), .Y(n1608) );
AOI22X1TS U2572 ( .A0(d_ff_Xn[23]), .A1(n1622), .B0(sign_inv_out[23]), .B1(
n1626), .Y(n1609) );
AOI22X1TS U2573 ( .A0(d_ff_Xn[20]), .A1(n1622), .B0(sign_inv_out[20]), .B1(
n1626), .Y(n1610) );
BUFX3TS U2574 ( .A(n1640), .Y(n1642) );
AOI22X1TS U2575 ( .A0(d_ff_Xn[11]), .A1(n1627), .B0(sign_inv_out[11]), .B1(
n1642), .Y(n1611) );
AOI22X1TS U2576 ( .A0(d_ff_Xn[17]), .A1(n1627), .B0(sign_inv_out[17]), .B1(
n1626), .Y(n1612) );
AOI22X1TS U2577 ( .A0(d_ff_Xn[26]), .A1(n1622), .B0(sign_inv_out[26]), .B1(
n1619), .Y(n1613) );
AOI22X1TS U2578 ( .A0(d_ff_Xn[15]), .A1(n1627), .B0(sign_inv_out[15]), .B1(
n1626), .Y(n1614) );
AOI22X1TS U2579 ( .A0(d_ff_Xn[14]), .A1(n1627), .B0(sign_inv_out[14]), .B1(
n1626), .Y(n1615) );
AOI22X1TS U2580 ( .A0(d_ff_Xn[25]), .A1(n1622), .B0(sign_inv_out[25]), .B1(
n1619), .Y(n1616) );
AOI22X1TS U2581 ( .A0(d_ff_Xn[13]), .A1(n1627), .B0(sign_inv_out[13]), .B1(
n1642), .Y(n1617) );
AOI22X1TS U2582 ( .A0(d_ff_Xn[12]), .A1(n1627), .B0(sign_inv_out[12]), .B1(
n1642), .Y(n1618) );
AOI22X1TS U2583 ( .A0(d_ff_Xn[24]), .A1(n1622), .B0(sign_inv_out[24]), .B1(
n1619), .Y(n1620) );
AOI22X1TS U2584 ( .A0(d_ff_Xn[10]), .A1(n1627), .B0(sign_inv_out[10]), .B1(
n1642), .Y(n1621) );
AOI22X1TS U2585 ( .A0(d_ff_Xn[22]), .A1(n1622), .B0(sign_inv_out[22]), .B1(
n1626), .Y(n1623) );
AOI22X1TS U2586 ( .A0(d_ff_Xn[16]), .A1(n1627), .B0(sign_inv_out[16]), .B1(
n1626), .Y(n1625) );
AOI22X1TS U2587 ( .A0(d_ff_Xn[18]), .A1(n1627), .B0(sign_inv_out[18]), .B1(
n1626), .Y(n1628) );
BUFX3TS U2588 ( .A(n1475), .Y(n1645) );
BUFX3TS U2589 ( .A(n1555), .Y(n1643) );
AOI22X1TS U2590 ( .A0(d_ff_Xn[1]), .A1(n1643), .B0(sign_inv_out[1]), .B1(
n1640), .Y(n1630) );
AOI22X1TS U2591 ( .A0(d_ff_Xn[5]), .A1(n1643), .B0(sign_inv_out[5]), .B1(
n1642), .Y(n1631) );
AOI22X1TS U2592 ( .A0(d_ff_Xn[2]), .A1(n1643), .B0(sign_inv_out[2]), .B1(
n1640), .Y(n1632) );
BUFX3TS U2593 ( .A(n1475), .Y(n1657) );
BUFX3TS U2594 ( .A(n1555), .Y(n1655) );
AOI22X1TS U2595 ( .A0(d_ff_Xn[50]), .A1(n1655), .B0(sign_inv_out[50]), .B1(
n1654), .Y(n1633) );
AOI22X1TS U2596 ( .A0(d_ff_Xn[4]), .A1(n1643), .B0(sign_inv_out[4]), .B1(
n1642), .Y(n1634) );
AOI22X1TS U2597 ( .A0(d_ff_Xn[51]), .A1(n1655), .B0(sign_inv_out[51]), .B1(
n1654), .Y(n1635) );
AOI22X1TS U2598 ( .A0(d_ff_Xn[9]), .A1(n1643), .B0(sign_inv_out[9]), .B1(
n1642), .Y(n1636) );
AOI22X1TS U2599 ( .A0(d_ff_Xn[0]), .A1(n1643), .B0(sign_inv_out[0]), .B1(
n1640), .Y(n1637) );
AOI22X1TS U2600 ( .A0(d_ff_Xn[7]), .A1(n1643), .B0(sign_inv_out[7]), .B1(
n1642), .Y(n1638) );
AOI22X1TS U2601 ( .A0(d_ff_Xn[6]), .A1(n1643), .B0(sign_inv_out[6]), .B1(
n1642), .Y(n1639) );
AOI22X1TS U2602 ( .A0(d_ff_Xn[3]), .A1(n1643), .B0(sign_inv_out[3]), .B1(
n1640), .Y(n1641) );
AOI22X1TS U2603 ( .A0(d_ff_Xn[8]), .A1(n1643), .B0(sign_inv_out[8]), .B1(
n1642), .Y(n1644) );
AOI22X1TS U2604 ( .A0(d_ff_Xn[54]), .A1(n1655), .B0(sign_inv_out[54]), .B1(
n1652), .Y(n1646) );
AOI22X1TS U2605 ( .A0(d_ff_Xn[52]), .A1(n1655), .B0(sign_inv_out[52]), .B1(
n1654), .Y(n1647) );
AOI22X1TS U2606 ( .A0(d_ff_Xn[55]), .A1(n1655), .B0(sign_inv_out[55]), .B1(
n1652), .Y(n1648) );
AOI22X1TS U2607 ( .A0(d_ff_Xn[57]), .A1(n1655), .B0(sign_inv_out[57]), .B1(
n1652), .Y(n1649) );
AOI22X1TS U2608 ( .A0(d_ff_Xn[58]), .A1(n1655), .B0(sign_inv_out[58]), .B1(
n1652), .Y(n1650) );
AOI22X1TS U2609 ( .A0(d_ff_Xn[56]), .A1(n1655), .B0(sign_inv_out[56]), .B1(
n1652), .Y(n1651) );
AOI22X1TS U2610 ( .A0(d_ff_Xn[59]), .A1(n1655), .B0(sign_inv_out[59]), .B1(
n1652), .Y(n1653) );
AOI22X1TS U2611 ( .A0(d_ff_Xn[53]), .A1(n1655), .B0(sign_inv_out[53]), .B1(
n1654), .Y(n1656) );
NAND2X1TS U2612 ( .A(cont_var_out[1]), .B(n2231), .Y(n1925) );
NOR2X1TS U2613 ( .A(n1476), .B(n1925), .Y(n1956) );
NAND2X2TS U2614 ( .A(ack_add_subt), .B(n1956), .Y(n1938) );
NAND3X1TS U2615 ( .A(n1932), .B(n2223), .C(n2229), .Y(n1951) );
BUFX3TS U2616 ( .A(n1951), .Y(n1950) );
BUFX3TS U2617 ( .A(n1950), .Y(n1952) );
AOI222X1TS U2618 ( .A0(n1833), .A1(d_ff2_Z[8]), .B0(n1683), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n1739), .Y(n1659) );
INVX2TS U2619 ( .A(n1659), .Y(n881) );
AOI222X1TS U2620 ( .A0(n1717), .A1(d_ff2_Z[10]), .B0(n1683), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n1739), .Y(n1660) );
INVX2TS U2621 ( .A(n1660), .Y(n879) );
AOI222X1TS U2622 ( .A0(n2108), .A1(d_ff2_Z[11]), .B0(n1683), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n1739), .Y(n1661) );
INVX2TS U2623 ( .A(n1661), .Y(n878) );
AOI222X1TS U2624 ( .A0(n1833), .A1(d_ff2_Z[9]), .B0(n1683), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n1739), .Y(n1662) );
INVX2TS U2625 ( .A(n1662), .Y(n880) );
AOI222X1TS U2626 ( .A0(n1717), .A1(d_ff2_Z[7]), .B0(n1683), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n1739), .Y(n1663) );
INVX2TS U2627 ( .A(n1663), .Y(n882) );
BUFX3TS U2628 ( .A(n1664), .Y(n1674) );
AOI222X1TS U2629 ( .A0(n2108), .A1(d_ff2_Z[25]), .B0(n1674), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n1817), .Y(n1665) );
INVX2TS U2630 ( .A(n1665), .Y(n864) );
AOI222X1TS U2631 ( .A0(n1724), .A1(d_ff2_Z[24]), .B0(n1674), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n1819), .Y(n1666) );
INVX2TS U2632 ( .A(n1666), .Y(n865) );
AOI222X1TS U2633 ( .A0(n1724), .A1(d_ff2_Z[27]), .B0(n1674), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n1835), .Y(n1667) );
INVX2TS U2634 ( .A(n1667), .Y(n862) );
AOI222X1TS U2635 ( .A0(n1833), .A1(d_ff2_Z[32]), .B0(n1674), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n1817), .Y(n1668) );
INVX2TS U2636 ( .A(n1668), .Y(n857) );
AOI222X1TS U2637 ( .A0(n1724), .A1(d_ff2_Z[26]), .B0(n1674), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n1835), .Y(n1669) );
INVX2TS U2638 ( .A(n1669), .Y(n863) );
AOI222X1TS U2639 ( .A0(n1717), .A1(d_ff2_Z[30]), .B0(n1674), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n1817), .Y(n1670) );
INVX2TS U2640 ( .A(n1670), .Y(n859) );
AOI222X1TS U2641 ( .A0(n2108), .A1(d_ff2_Z[33]), .B0(n1674), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n1835), .Y(n1671) );
INVX2TS U2642 ( .A(n1671), .Y(n856) );
AOI222X1TS U2643 ( .A0(n1833), .A1(d_ff2_Z[29]), .B0(n1674), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n1817), .Y(n1672) );
INVX2TS U2644 ( .A(n1672), .Y(n860) );
AOI222X1TS U2645 ( .A0(n1717), .A1(d_ff2_Z[28]), .B0(n1674), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n1835), .Y(n1673) );
INVX2TS U2646 ( .A(n1673), .Y(n861) );
AOI222X1TS U2647 ( .A0(n2108), .A1(d_ff2_Z[31]), .B0(n1674), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n1817), .Y(n1675) );
INVX2TS U2648 ( .A(n1675), .Y(n858) );
OAI211XLTS U2649 ( .A0(n1676), .A1(n1938), .B0(cont_iter_out[2]), .C0(n1952),
.Y(n1677) );
OAI31X1TS U2650 ( .A0(n1938), .A1(n1490), .A2(n2025), .B0(n1677), .Y(n1339)
);
NAND2X1TS U2651 ( .A(n2064), .B(n2227), .Y(n2032) );
NOR3X1TS U2652 ( .A(cont_iter_out[0]), .B(n2025), .C(n1682), .Y(n2035) );
AOI222X1TS U2653 ( .A0(n2108), .A1(d_ff2_Z[13]), .B0(n1736), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n1739), .Y(n1684) );
INVX2TS U2654 ( .A(n1684), .Y(n876) );
AOI222X1TS U2655 ( .A0(n1833), .A1(d_ff2_Z[12]), .B0(n1736), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n1739), .Y(n1685) );
INVX2TS U2656 ( .A(n1685), .Y(n877) );
INVX2TS U2657 ( .A(n1686), .Y(n884) );
BUFX3TS U2658 ( .A(n1694), .Y(n1730) );
INVX2TS U2659 ( .A(n1687), .Y(add_subt_dataA[16]) );
INVX2TS U2660 ( .A(n1688), .Y(add_subt_dataA[10]) );
INVX2TS U2661 ( .A(n1689), .Y(add_subt_dataA[1]) );
INVX2TS U2662 ( .A(n1690), .Y(add_subt_dataA[13]) );
INVX2TS U2663 ( .A(n1860), .Y(n1753) );
BUFX3TS U2664 ( .A(n1694), .Y(n1910) );
INVX2TS U2665 ( .A(n1691), .Y(add_subt_dataA[15]) );
BUFX3TS U2666 ( .A(n1770), .Y(n1911) );
INVX2TS U2667 ( .A(n1692), .Y(add_subt_dataA[5]) );
INVX2TS U2668 ( .A(n1693), .Y(add_subt_dataA[12]) );
BUFX3TS U2669 ( .A(n1694), .Y(n1909) );
INVX2TS U2670 ( .A(n1695), .Y(add_subt_dataA[14]) );
INVX2TS U2671 ( .A(n1696), .Y(add_subt_dataA[11]) );
INVX2TS U2672 ( .A(n1697), .Y(add_subt_dataA[4]) );
INVX2TS U2673 ( .A(n1698), .Y(add_subt_dataA[2]) );
AOI211X1TS U2674 ( .A0(n1699), .A1(n2195), .B0(n2086), .C0(n2038), .Y(n2052)
);
INVX2TS U2675 ( .A(n1701), .Y(add_subt_dataA[8]) );
BUFX3TS U2676 ( .A(n1736), .Y(n1723) );
AOI222X1TS U2677 ( .A0(n1724), .A1(d_ff2_Z[21]), .B0(n1723), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n1819), .Y(n1702) );
INVX2TS U2678 ( .A(n1702), .Y(n868) );
BUFX3TS U2679 ( .A(n1736), .Y(n1719) );
AOI222X1TS U2680 ( .A0(n2183), .A1(d_ff2_Z[44]), .B0(n1719), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n1840), .Y(n1703) );
INVX2TS U2681 ( .A(n1703), .Y(n845) );
INVX2TS U2682 ( .A(n1704), .Y(n836) );
INVX2TS U2683 ( .A(n1705), .Y(n841) );
INVX2TS U2684 ( .A(n1706), .Y(n837) );
AOI222X1TS U2685 ( .A0(n1724), .A1(d_ff2_Z[23]), .B0(n1723), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n1819), .Y(n1707) );
INVX2TS U2686 ( .A(n1707), .Y(n866) );
AOI222X1TS U2687 ( .A0(n1717), .A1(d_ff2_Z[15]), .B0(n1723), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n1739), .Y(n1708) );
INVX2TS U2688 ( .A(n1708), .Y(n874) );
AOI222X1TS U2689 ( .A0(n2105), .A1(d_ff2_Z[45]), .B0(n1719), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n1842), .Y(n1709) );
INVX2TS U2690 ( .A(n1709), .Y(n844) );
INVX2TS U2691 ( .A(n1710), .Y(n838) );
INVX2TS U2692 ( .A(n1711), .Y(n839) );
INVX2TS U2693 ( .A(n1712), .Y(n840) );
AOI222X1TS U2694 ( .A0(n1724), .A1(d_ff2_Z[19]), .B0(n1723), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n1819), .Y(n1713) );
INVX2TS U2695 ( .A(n1713), .Y(n870) );
INVX2TS U2696 ( .A(n1714), .Y(n842) );
AOI222X1TS U2697 ( .A0(n2108), .A1(d_ff2_Z[14]), .B0(n1723), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n1739), .Y(n1715) );
INVX2TS U2698 ( .A(n1715), .Y(n875) );
AOI222X1TS U2699 ( .A0(n1724), .A1(d_ff2_Z[17]), .B0(n1723), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n1819), .Y(n1716) );
INVX2TS U2700 ( .A(n1716), .Y(n872) );
AOI222X1TS U2701 ( .A0(n1833), .A1(d_ff2_Z[16]), .B0(n1723), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n1819), .Y(n1718) );
INVX2TS U2702 ( .A(n1718), .Y(n873) );
AOI222X1TS U2703 ( .A0(n1844), .A1(d_ff2_Z[46]), .B0(n1719), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n1835), .Y(n1720) );
INVX2TS U2704 ( .A(n1720), .Y(n843) );
AOI222X1TS U2705 ( .A0(n1724), .A1(d_ff2_Z[22]), .B0(n1723), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n1819), .Y(n1721) );
INVX2TS U2706 ( .A(n1721), .Y(n867) );
AOI222X1TS U2707 ( .A0(n1724), .A1(d_ff2_Z[18]), .B0(n1723), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n1819), .Y(n1722) );
INVX2TS U2708 ( .A(n1722), .Y(n871) );
AOI222X1TS U2709 ( .A0(n1724), .A1(d_ff2_Z[20]), .B0(n1723), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n1819), .Y(n1725) );
INVX2TS U2710 ( .A(n1725), .Y(n869) );
BUFX3TS U2711 ( .A(n1730), .Y(n1752) );
INVX2TS U2712 ( .A(n1726), .Y(add_subt_dataA[22]) );
INVX2TS U2713 ( .A(n1728), .Y(add_subt_dataA[23]) );
INVX2TS U2714 ( .A(n1729), .Y(add_subt_dataA[18]) );
BUFX3TS U2715 ( .A(n1877), .Y(n1880) );
INVX2TS U2716 ( .A(n1731), .Y(add_subt_dataA[27]) );
INVX2TS U2717 ( .A(n1732), .Y(add_subt_dataA[21]) );
INVX2TS U2718 ( .A(n1733), .Y(add_subt_dataA[17]) );
INVX2TS U2719 ( .A(n1735), .Y(add_subt_dataA[19]) );
BUFX3TS U2720 ( .A(n1736), .Y(n1821) );
INVX2TS U2721 ( .A(n1737), .Y(n886) );
AOI222X1TS U2722 ( .A0(n2187), .A1(d_ff2_Z[1]), .B0(n1821), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n1840), .Y(n1738) );
INVX2TS U2723 ( .A(n1738), .Y(n888) );
AOI222X1TS U2724 ( .A0(n2187), .A1(d_ff2_Z[2]), .B0(n1821), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n1739), .Y(n1740) );
INVX2TS U2725 ( .A(n1740), .Y(n887) );
INVX2TS U2726 ( .A(n1741), .Y(n885) );
BUFX3TS U2727 ( .A(n1792), .Y(n1773) );
INVX2TS U2728 ( .A(n1742), .Y(add_subt_dataA[25]) );
INVX2TS U2729 ( .A(n1743), .Y(add_subt_dataA[33]) );
INVX2TS U2730 ( .A(n1744), .Y(add_subt_dataA[20]) );
INVX2TS U2731 ( .A(n1745), .Y(add_subt_dataA[30]) );
INVX2TS U2732 ( .A(n1877), .Y(n1782) );
INVX2TS U2733 ( .A(n1746), .Y(add_subt_dataA[36]) );
INVX2TS U2734 ( .A(n1747), .Y(add_subt_dataA[29]) );
INVX2TS U2735 ( .A(n1748), .Y(add_subt_dataA[32]) );
INVX2TS U2736 ( .A(n1749), .Y(add_subt_dataA[35]) );
INVX2TS U2737 ( .A(n1750), .Y(add_subt_dataA[26]) );
INVX2TS U2738 ( .A(n1751), .Y(add_subt_dataA[34]) );
INVX2TS U2739 ( .A(n1754), .Y(add_subt_dataA[24]) );
INVX2TS U2740 ( .A(n1755), .Y(add_subt_dataA[31]) );
INVX2TS U2741 ( .A(n1756), .Y(add_subt_dataA[28]) );
INVX2TS U2742 ( .A(n1757), .Y(n889) );
INVX2TS U2743 ( .A(n1880), .Y(n1887) );
BUFX3TS U2744 ( .A(n1910), .Y(n1886) );
INVX2TS U2745 ( .A(n1758), .Y(add_subt_dataB[46]) );
BUFX3TS U2746 ( .A(n1910), .Y(n1851) );
AOI222X1TS U2747 ( .A0(d_ff3_LUT_out[36]), .A1(n1792), .B0(n1852), .B1(
d_ff3_sh_x_out[36]), .C0(n1851), .C1(d_ff3_sh_y_out[36]), .Y(n1759) );
INVX2TS U2748 ( .A(n1759), .Y(add_subt_dataB[36]) );
INVX2TS U2749 ( .A(n1760), .Y(add_subt_dataB[49]) );
INVX2TS U2750 ( .A(n1761), .Y(add_subt_dataB[52]) );
AOI222X1TS U2751 ( .A0(d_ff3_LUT_out[35]), .A1(n1792), .B0(n1813), .B1(
d_ff3_sh_x_out[35]), .C0(n1851), .C1(d_ff3_sh_y_out[35]), .Y(n1762) );
INVX2TS U2752 ( .A(n1762), .Y(add_subt_dataB[35]) );
AOI222X1TS U2753 ( .A0(n1911), .A1(d_ff3_LUT_out[37]), .B0(n1852), .B1(
d_ff3_sh_x_out[37]), .C0(n1851), .C1(d_ff3_sh_y_out[37]), .Y(n1763) );
INVX2TS U2754 ( .A(n1763), .Y(add_subt_dataB[37]) );
INVX2TS U2755 ( .A(n1764), .Y(add_subt_dataB[44]) );
AOI222X1TS U2756 ( .A0(d_ff3_LUT_out[34]), .A1(n1792), .B0(n1852), .B1(
d_ff3_sh_x_out[34]), .C0(n1851), .C1(d_ff3_sh_y_out[34]), .Y(n1765) );
INVX2TS U2757 ( .A(n1765), .Y(add_subt_dataB[34]) );
BUFX3TS U2758 ( .A(n1792), .Y(n1814) );
AOI222X1TS U2759 ( .A0(d_ff3_LUT_out[30]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[30]), .C0(n1851), .C1(d_ff3_sh_y_out[30]), .Y(n1766) );
INVX2TS U2760 ( .A(n1766), .Y(add_subt_dataB[30]) );
INVX2TS U2761 ( .A(n1767), .Y(add_subt_dataB[29]) );
BUFX3TS U2762 ( .A(n1909), .Y(n1780) );
INVX2TS U2763 ( .A(n1768), .Y(add_subt_dataA[41]) );
INVX2TS U2764 ( .A(n1769), .Y(add_subt_dataA[46]) );
BUFX3TS U2765 ( .A(n1770), .Y(n1789) );
INVX2TS U2766 ( .A(n1771), .Y(add_subt_dataA[44]) );
INVX2TS U2767 ( .A(n1877), .Y(n1893) );
INVX2TS U2768 ( .A(n1772), .Y(add_subt_dataA[42]) );
INVX2TS U2769 ( .A(n1774), .Y(add_subt_dataA[38]) );
INVX2TS U2770 ( .A(n1775), .Y(add_subt_dataA[40]) );
INVX2TS U2771 ( .A(n1777), .Y(add_subt_dataA[37]) );
INVX2TS U2772 ( .A(n1778), .Y(add_subt_dataA[45]) );
INVX2TS U2773 ( .A(n1779), .Y(add_subt_dataA[43]) );
INVX2TS U2774 ( .A(n1781), .Y(add_subt_dataA[39]) );
BUFX3TS U2775 ( .A(n1909), .Y(n1889) );
INVX2TS U2776 ( .A(n1783), .Y(add_subt_dataA[47]) );
INVX2TS U2777 ( .A(n1784), .Y(add_subt_dataA[49]) );
INVX2TS U2778 ( .A(n1785), .Y(add_subt_dataA[0]) );
INVX2TS U2779 ( .A(n1786), .Y(add_subt_dataA[50]) );
INVX2TS U2780 ( .A(n1787), .Y(add_subt_dataA[48]) );
INVX2TS U2781 ( .A(n1788), .Y(add_subt_dataA[51]) );
INVX2TS U2782 ( .A(n1790), .Y(add_subt_dataA[54]) );
BUFX3TS U2783 ( .A(n1694), .Y(n1812) );
AOI222X1TS U2784 ( .A0(n1911), .A1(d_ff3_LUT_out[20]), .B0(n1497), .B1(
d_ff3_sh_x_out[20]), .C0(n1812), .C1(d_ff3_sh_y_out[20]), .Y(n1791) );
INVX2TS U2785 ( .A(n1791), .Y(add_subt_dataB[20]) );
BUFX3TS U2786 ( .A(n1792), .Y(n1810) );
BUFX3TS U2787 ( .A(n1694), .Y(n1867) );
AOI222X1TS U2788 ( .A0(d_ff3_LUT_out[18]), .A1(n1810), .B0(n1497), .B1(
d_ff3_sh_x_out[18]), .C0(n1867), .C1(d_ff3_sh_y_out[18]), .Y(n1793) );
INVX2TS U2789 ( .A(n1793), .Y(add_subt_dataB[18]) );
AOI222X1TS U2790 ( .A0(d_ff3_LUT_out[22]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[22]), .C0(n1812), .C1(d_ff3_sh_y_out[22]), .Y(n1794) );
INVX2TS U2791 ( .A(n1794), .Y(add_subt_dataB[22]) );
AOI222X1TS U2792 ( .A0(d_ff3_LUT_out[16]), .A1(n1810), .B0(n1782), .B1(
d_ff3_sh_x_out[16]), .C0(n1867), .C1(d_ff3_sh_y_out[16]), .Y(n1795) );
INVX2TS U2793 ( .A(n1795), .Y(add_subt_dataB[16]) );
INVX2TS U2794 ( .A(n1796), .Y(add_subt_dataB[14]) );
AOI222X1TS U2795 ( .A0(d_ff3_LUT_out[21]), .A1(n1810), .B0(n1893), .B1(
d_ff3_sh_x_out[21]), .C0(n1812), .C1(d_ff3_sh_y_out[21]), .Y(n1797) );
INVX2TS U2796 ( .A(n1797), .Y(add_subt_dataB[21]) );
AOI222X1TS U2797 ( .A0(d_ff3_LUT_out[12]), .A1(n1810), .B0(n1498), .B1(
d_ff3_sh_x_out[12]), .C0(n1867), .C1(d_ff3_sh_y_out[12]), .Y(n1798) );
INVX2TS U2798 ( .A(n1798), .Y(add_subt_dataB[12]) );
AOI222X1TS U2799 ( .A0(d_ff3_LUT_out[10]), .A1(n1810), .B0(n1498), .B1(
d_ff3_sh_x_out[10]), .C0(n1867), .C1(d_ff3_sh_y_out[10]), .Y(n1799) );
INVX2TS U2800 ( .A(n1799), .Y(add_subt_dataB[10]) );
AOI222X1TS U2801 ( .A0(d_ff3_LUT_out[28]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[28]), .C0(n1812), .C1(d_ff3_sh_y_out[28]), .Y(n1800) );
INVX2TS U2802 ( .A(n1800), .Y(add_subt_dataB[28]) );
AOI222X1TS U2803 ( .A0(d_ff3_LUT_out[13]), .A1(n1810), .B0(n1782), .B1(
d_ff3_sh_x_out[13]), .C0(n1867), .C1(d_ff3_sh_y_out[13]), .Y(n1801) );
INVX2TS U2804 ( .A(n1801), .Y(add_subt_dataB[13]) );
AOI222X1TS U2805 ( .A0(d_ff3_LUT_out[24]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[24]), .C0(n1812), .C1(d_ff3_sh_y_out[24]), .Y(n1802) );
INVX2TS U2806 ( .A(n1802), .Y(add_subt_dataB[24]) );
INVX2TS U2807 ( .A(n1803), .Y(add_subt_dataB[15]) );
AOI222X1TS U2808 ( .A0(d_ff3_LUT_out[31]), .A1(n1814), .B0(n1852), .B1(
d_ff3_sh_x_out[31]), .C0(n1812), .C1(d_ff3_sh_y_out[31]), .Y(n1804) );
INVX2TS U2809 ( .A(n1804), .Y(add_subt_dataB[31]) );
INVX2TS U2810 ( .A(n1805), .Y(add_subt_dataB[26]) );
AOI222X1TS U2811 ( .A0(d_ff3_LUT_out[17]), .A1(n1810), .B0(n1893), .B1(
d_ff3_sh_x_out[17]), .C0(n1867), .C1(d_ff3_sh_y_out[17]), .Y(n1807) );
INVX2TS U2812 ( .A(n1807), .Y(add_subt_dataB[17]) );
INVX2TS U2813 ( .A(n1808), .Y(add_subt_dataB[25]) );
AOI222X1TS U2814 ( .A0(d_ff3_LUT_out[23]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[23]), .C0(n1812), .C1(d_ff3_sh_y_out[23]), .Y(n1809) );
INVX2TS U2815 ( .A(n1809), .Y(add_subt_dataB[23]) );
INVX2TS U2816 ( .A(n1877), .Y(n1871) );
INVX2TS U2817 ( .A(n1811), .Y(add_subt_dataB[11]) );
INVX2TS U2818 ( .A(n1815), .Y(add_subt_dataB[27]) );
BUFX3TS U2819 ( .A(n1821), .Y(n1843) );
AOI222X1TS U2820 ( .A0(n2183), .A1(d_ff2_Z[41]), .B0(n1843), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n1842), .Y(n1816) );
INVX2TS U2821 ( .A(n1816), .Y(n848) );
AOI222X1TS U2822 ( .A0(n1833), .A1(d_ff2_Z[34]), .B0(n1843), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n1835), .Y(n1818) );
INVX2TS U2823 ( .A(n1818), .Y(n855) );
AOI222X1TS U2824 ( .A0(n1717), .A1(d_ff2_Z[35]), .B0(n1843), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n1819), .Y(n1820) );
INVX2TS U2825 ( .A(n1820), .Y(n854) );
INVX2TS U2826 ( .A(n1822), .Y(n826) );
AOI222X1TS U2827 ( .A0(n2105), .A1(d_ff2_Z[40]), .B0(n1843), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n1840), .Y(n1823) );
INVX2TS U2828 ( .A(n1823), .Y(n849) );
AOI222X1TS U2829 ( .A0(n1844), .A1(d_ff2_Z[37]), .B0(n1843), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n1842), .Y(n1824) );
INVX2TS U2830 ( .A(n1824), .Y(n852) );
AOI222X1TS U2831 ( .A0(n2105), .A1(d_ff2_Z[61]), .B0(n1736), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n1842), .Y(n1825) );
INVX2TS U2832 ( .A(n1825), .Y(n828) );
INVX2TS U2833 ( .A(n1826), .Y(n829) );
AOI222X1TS U2834 ( .A0(n2183), .A1(d_ff2_Z[57]), .B0(n1683), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n1840), .Y(n1827) );
INVX2TS U2835 ( .A(n1827), .Y(n832) );
AOI222X1TS U2836 ( .A0(n2105), .A1(d_ff2_Z[62]), .B0(n1683), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n1842), .Y(n1828) );
INVX2TS U2837 ( .A(n1828), .Y(n827) );
AOI222X1TS U2838 ( .A0(n2183), .A1(d_ff2_Z[38]), .B0(n1843), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n1840), .Y(n1829) );
INVX2TS U2839 ( .A(n1829), .Y(n851) );
INVX2TS U2840 ( .A(n1830), .Y(n831) );
AOI222X1TS U2841 ( .A0(n2105), .A1(d_ff2_Z[43]), .B0(n1843), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n1842), .Y(n1831) );
INVX2TS U2842 ( .A(n1831), .Y(n846) );
INVX2TS U2843 ( .A(n1832), .Y(n833) );
AOI222X1TS U2844 ( .A0(n2108), .A1(d_ff2_Z[36]), .B0(n1843), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n1840), .Y(n1834) );
INVX2TS U2845 ( .A(n1834), .Y(n853) );
INVX2TS U2846 ( .A(n1836), .Y(n835) );
INVX2TS U2847 ( .A(n1838), .Y(n834) );
AOI222X1TS U2848 ( .A0(n1844), .A1(d_ff2_Z[42]), .B0(n1843), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n1842), .Y(n1839) );
INVX2TS U2849 ( .A(n1839), .Y(n847) );
AOI222X1TS U2850 ( .A0(n2183), .A1(d_ff2_Z[59]), .B0(n1821), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n1842), .Y(n1841) );
INVX2TS U2851 ( .A(n1841), .Y(n830) );
AOI222X1TS U2852 ( .A0(n2183), .A1(d_ff2_Z[39]), .B0(n1843), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n1840), .Y(n1845) );
INVX2TS U2853 ( .A(n1845), .Y(n850) );
AOI222X1TS U2854 ( .A0(d_ff3_LUT_out[38]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[38]), .C0(n1851), .C1(d_ff3_sh_y_out[38]), .Y(n1846) );
INVX2TS U2855 ( .A(n1846), .Y(add_subt_dataB[38]) );
AOI222X1TS U2856 ( .A0(d_ff3_LUT_out[42]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[42]), .C0(n1886), .C1(d_ff3_sh_y_out[42]), .Y(n1847) );
INVX2TS U2857 ( .A(n1847), .Y(add_subt_dataB[42]) );
AOI222X1TS U2858 ( .A0(d_ff3_LUT_out[32]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[32]), .C0(n1851), .C1(d_ff3_sh_y_out[32]), .Y(n1848) );
INVX2TS U2859 ( .A(n1848), .Y(add_subt_dataB[32]) );
INVX2TS U2860 ( .A(n1849), .Y(add_subt_dataB[39]) );
AOI222X1TS U2861 ( .A0(d_ff3_LUT_out[40]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[40]), .C0(n1851), .C1(d_ff3_sh_y_out[40]), .Y(n1850) );
INVX2TS U2862 ( .A(n1850), .Y(add_subt_dataB[40]) );
INVX2TS U2863 ( .A(n1853), .Y(add_subt_dataB[33]) );
INVX2TS U2864 ( .A(n1855), .Y(add_subt_dataA[9]) );
AOI22X1TS U2865 ( .A0(n1878), .A1(d_ff2_Z[53]), .B0(d_ff2_X[53]), .B1(n1919),
.Y(n1856) );
AOI22X1TS U2866 ( .A0(d_ff2_X[58]), .A1(n1916), .B0(d_ff2_Z[58]), .B1(n1878),
.Y(n1857) );
AOI22X1TS U2867 ( .A0(d_ff2_X[60]), .A1(n1919), .B0(d_ff2_Z[60]), .B1(n1878),
.Y(n1858) );
AOI22X1TS U2868 ( .A0(d_ff2_X[56]), .A1(n1916), .B0(d_ff2_Z[56]), .B1(n1878),
.Y(n1859) );
AOI22X1TS U2869 ( .A0(d_ff2_X[62]), .A1(n1919), .B0(d_ff2_Z[62]), .B1(n1878),
.Y(n1861) );
BUFX3TS U2870 ( .A(n1881), .Y(n1873) );
BUFX3TS U2871 ( .A(n1916), .Y(n1894) );
INVX2TS U2872 ( .A(n1862), .Y(add_subt_dataB[0]) );
AOI222X1TS U2873 ( .A0(d_ff3_LUT_out[4]), .A1(n1873), .B0(n1871), .B1(
d_ff3_sh_x_out[4]), .C0(n1894), .C1(d_ff3_sh_y_out[4]), .Y(n1863) );
INVX2TS U2874 ( .A(n1863), .Y(add_subt_dataB[4]) );
INVX2TS U2875 ( .A(n1864), .Y(add_subt_dataB[1]) );
INVX2TS U2876 ( .A(n1865), .Y(add_subt_dataB[3]) );
AOI222X1TS U2877 ( .A0(d_ff3_LUT_out[2]), .A1(n1873), .B0(n1871), .B1(
d_ff3_sh_x_out[2]), .C0(n1894), .C1(d_ff3_sh_y_out[2]), .Y(n1866) );
INVX2TS U2878 ( .A(n1866), .Y(add_subt_dataB[2]) );
INVX2TS U2879 ( .A(n1868), .Y(add_subt_dataB[9]) );
INVX2TS U2880 ( .A(n1869), .Y(add_subt_dataB[6]) );
INVX2TS U2881 ( .A(n1870), .Y(add_subt_dataB[5]) );
INVX2TS U2882 ( .A(n1872), .Y(add_subt_dataB[7]) );
INVX2TS U2883 ( .A(n1874), .Y(add_subt_dataA[63]) );
AOI22X1TS U2884 ( .A0(d_ff2_X[57]), .A1(n1916), .B0(d_ff2_Z[57]), .B1(n1878),
.Y(n1875) );
AOI22X1TS U2885 ( .A0(d_ff2_X[61]), .A1(n1916), .B0(d_ff2_Z[61]), .B1(n1878),
.Y(n1876) );
AOI22X1TS U2886 ( .A0(d_ff2_X[59]), .A1(n1919), .B0(d_ff2_Z[59]), .B1(n1878),
.Y(n1879) );
BUFX3TS U2887 ( .A(n1881), .Y(n1892) );
INVX2TS U2888 ( .A(n1882), .Y(add_subt_dataB[45]) );
INVX2TS U2889 ( .A(n1883), .Y(add_subt_dataB[43]) );
INVX2TS U2890 ( .A(n1884), .Y(add_subt_dataB[47]) );
INVX2TS U2891 ( .A(n1885), .Y(add_subt_dataB[54]) );
INVX2TS U2892 ( .A(n1888), .Y(add_subt_dataB[50]) );
INVX2TS U2893 ( .A(n1890), .Y(add_subt_dataB[55]) );
AOI222X1TS U2894 ( .A0(d_ff3_sh_y_out[53]), .A1(n1894), .B0(
d_ff3_sh_x_out[53]), .B1(n1871), .C0(n1892), .C1(d_ff3_LUT_out[53]),
.Y(n1891) );
INVX2TS U2895 ( .A(n1891), .Y(add_subt_dataB[53]) );
AOI222X1TS U2896 ( .A0(d_ff3_sh_y_out[56]), .A1(n1894), .B0(
d_ff3_sh_x_out[56]), .B1(n1871), .C0(n1892), .C1(d_ff3_LUT_out[56]),
.Y(n1895) );
INVX2TS U2897 ( .A(n1895), .Y(add_subt_dataB[56]) );
OAI211XLTS U2898 ( .A0(n1898), .A1(n2229), .B0(n1897), .C0(n1934), .Y(n1345)
);
AOI22X1TS U2899 ( .A0(n1806), .A1(d_ff3_sh_x_out[8]), .B0(n1919), .B1(
d_ff3_sh_y_out[8]), .Y(n1903) );
OAI21XLTS U2900 ( .A0(n1517), .A1(n1906), .B0(n1903), .Y(add_subt_dataB[8])
);
AOI22X1TS U2901 ( .A0(n1753), .A1(d_ff3_sh_x_out[19]), .B0(n1919), .B1(
d_ff3_sh_y_out[19]), .Y(n1904) );
OAI21XLTS U2902 ( .A0(n1515), .A1(n1906), .B0(n1904), .Y(add_subt_dataB[19])
);
AOI22X1TS U2903 ( .A0(n1806), .A1(d_ff3_sh_x_out[41]), .B0(n1919), .B1(
d_ff3_sh_y_out[41]), .Y(n1905) );
OAI21XLTS U2904 ( .A0(n1516), .A1(n1906), .B0(n1905), .Y(add_subt_dataB[41])
);
INVX2TS U2905 ( .A(n1908), .Y(n1907) );
AOI221XLTS U2906 ( .A0(cont_var_out[1]), .A1(n1908), .B0(n1482), .B1(n1907),
.C0(n2089), .Y(n1342) );
AO22XLTS U2907 ( .A0(n1753), .A1(d_ff3_sh_x_out[63]), .B0(n1909), .B1(
d_ff3_sh_y_out[63]), .Y(add_subt_dataB[63]) );
AO22XLTS U2908 ( .A0(d_ff3_sh_y_out[62]), .A1(n1910), .B0(d_ff3_sh_x_out[62]), .B1(n1806), .Y(add_subt_dataB[62]) );
AOI22X1TS U2909 ( .A0(d_ff3_sh_y_out[61]), .A1(n1694), .B0(
d_ff3_sh_x_out[61]), .B1(n1806), .Y(n1912) );
NAND2X2TS U2910 ( .A(d_ff3_LUT_out[48]), .B(n1911), .Y(n1921) );
NAND2X1TS U2911 ( .A(n1912), .B(n1921), .Y(add_subt_dataB[61]) );
AOI22X1TS U2912 ( .A0(d_ff3_sh_y_out[60]), .A1(n1916), .B0(
d_ff3_sh_x_out[60]), .B1(n1753), .Y(n1913) );
NAND2X1TS U2913 ( .A(n1913), .B(n1921), .Y(add_subt_dataB[60]) );
AOI22X1TS U2914 ( .A0(d_ff3_sh_y_out[59]), .A1(n1916), .B0(
d_ff3_sh_x_out[59]), .B1(n1806), .Y(n1914) );
NAND2X1TS U2915 ( .A(n1914), .B(n1921), .Y(add_subt_dataB[59]) );
AOI22X1TS U2916 ( .A0(d_ff3_sh_y_out[58]), .A1(n1916), .B0(
d_ff3_sh_x_out[58]), .B1(n1753), .Y(n1915) );
NAND2X1TS U2917 ( .A(n1915), .B(n1921), .Y(add_subt_dataB[58]) );
AOI22X1TS U2918 ( .A0(d_ff3_sh_y_out[57]), .A1(n1916), .B0(
d_ff3_sh_x_out[57]), .B1(n1753), .Y(n1917) );
NAND2X1TS U2919 ( .A(n1917), .B(n1921), .Y(add_subt_dataB[57]) );
AOI22X1TS U2920 ( .A0(n1753), .A1(d_ff3_sh_x_out[51]), .B0(n1919), .B1(
d_ff3_sh_y_out[51]), .Y(n1918) );
NAND2X1TS U2921 ( .A(n1918), .B(n1921), .Y(add_subt_dataB[51]) );
AOI22X1TS U2922 ( .A0(n1806), .A1(d_ff3_sh_x_out[48]), .B0(n1919), .B1(
d_ff3_sh_y_out[48]), .Y(n1922) );
NAND2X1TS U2923 ( .A(n1922), .B(n1921), .Y(add_subt_dataB[48]) );
AOI2BB2XLTS U2924 ( .B0(d_ff3_sign_out), .B1(n2231), .A0N(n2231), .A1N(
d_ff3_sign_out), .Y(op_add_subt) );
INVX2TS U2925 ( .A(n1932), .Y(n1928) );
NOR2XLTS U2926 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]),
.Y(n1924) );
AOI31XLTS U2927 ( .A0(cordic_FSM_state_reg[0]), .A1(cordic_FSM_state_reg[3]),
.A2(ack_cordic), .B0(cordic_FSM_state_reg[1]), .Y(n1923) );
OAI21X1TS U2928 ( .A0(n1924), .A1(n1923), .B0(cordic_FSM_state_reg[2]), .Y(
n1927) );
CLKAND2X2TS U2929 ( .A(ready_add_subt), .B(n2225), .Y(n1931) );
NAND2X1TS U2930 ( .A(n1952), .B(n1938), .Y(n1936) );
AOI22X1TS U2931 ( .A0(cont_iter_out[0]), .A1(n1936), .B0(n1938), .B1(n1490),
.Y(n1341) );
INVX2TS U2932 ( .A(n1952), .Y(n1942) );
INVX2TS U2933 ( .A(n1937), .Y(n2057) );
OAI22X1TS U2934 ( .A0(n1942), .A1(n1503), .B0(n1938), .B1(n2057), .Y(n1338)
);
INVX2TS U2935 ( .A(n1950), .Y(n1955) );
CLKBUFX2TS U2936 ( .A(n1950), .Y(n1944) );
CLKBUFX2TS U2937 ( .A(n1940), .Y(n1939) );
INVX2TS U2938 ( .A(n1944), .Y(n1948) );
INVX2TS U2939 ( .A(n1944), .Y(n1953) );
BUFX3TS U2940 ( .A(n1940), .Y(n1941) );
INVX2TS U2941 ( .A(n1944), .Y(n1943) );
INVX2TS U2942 ( .A(n1950), .Y(n1946) );
BUFX3TS U2943 ( .A(n1940), .Y(n1954) );
BUFX3TS U2944 ( .A(n1944), .Y(n1945) );
INVX2TS U2945 ( .A(n1944), .Y(n1949) );
BUFX3TS U2946 ( .A(n1950), .Y(n1947) );
NOR2BX1TS U2947 ( .AN(n1956), .B(n1990), .Y(n1957) );
BUFX3TS U2948 ( .A(n1966), .Y(n1958) );
INVX2TS U2949 ( .A(n1958), .Y(n1959) );
BUFX3TS U2950 ( .A(n1966), .Y(n1971) );
BUFX3TS U2951 ( .A(n1971), .Y(n1960) );
INVX2TS U2952 ( .A(n1971), .Y(n1961) );
BUFX3TS U2953 ( .A(n1971), .Y(n1962) );
INVX2TS U2954 ( .A(n1971), .Y(n1963) );
CLKBUFX2TS U2955 ( .A(n1966), .Y(n1967) );
BUFX3TS U2956 ( .A(n1967), .Y(n1964) );
INVX2TS U2957 ( .A(n1971), .Y(n1965) );
INVX2TS U2958 ( .A(n1966), .Y(n1968) );
CLKBUFX2TS U2959 ( .A(n1967), .Y(n1972) );
BUFX3TS U2960 ( .A(n1967), .Y(n1969) );
INVX2TS U2961 ( .A(n1971), .Y(n1970) );
INVX2TS U2962 ( .A(n1971), .Y(n1973) );
BUFX3TS U2963 ( .A(n1974), .Y(n1977) );
OAI2BB2XLTS U2964 ( .B0(n1977), .B1(n2239), .A0N(n1979), .A1N(
result_add_subt[0]), .Y(n1201) );
BUFX3TS U2965 ( .A(n1979), .Y(n1975) );
OAI2BB2XLTS U2966 ( .B0(n1975), .B1(n2240), .A0N(n1979), .A1N(
result_add_subt[1]), .Y(n1200) );
OAI2BB2XLTS U2967 ( .B0(n1977), .B1(n2241), .A0N(n1979), .A1N(
result_add_subt[2]), .Y(n1199) );
BUFX3TS U2968 ( .A(n1979), .Y(n1986) );
OAI2BB2XLTS U2969 ( .B0(n1975), .B1(n2242), .A0N(n1986), .A1N(
result_add_subt[3]), .Y(n1198) );
OAI2BB2XLTS U2970 ( .B0(n1975), .B1(n2243), .A0N(n1986), .A1N(
result_add_subt[4]), .Y(n1197) );
BUFX3TS U2971 ( .A(n1974), .Y(n1984) );
OAI2BB2XLTS U2972 ( .B0(n1977), .B1(n2244), .A0N(n1984), .A1N(
result_add_subt[5]), .Y(n1196) );
OAI2BB2XLTS U2973 ( .B0(n1977), .B1(n2245), .A0N(n1986), .A1N(
result_add_subt[6]), .Y(n1195) );
OAI2BB2XLTS U2974 ( .B0(n1975), .B1(n2246), .A0N(n1986), .A1N(
result_add_subt[7]), .Y(n1194) );
BUFX3TS U2975 ( .A(n1979), .Y(n1983) );
OAI2BB2XLTS U2976 ( .B0(n1975), .B1(n2247), .A0N(n1983), .A1N(
result_add_subt[8]), .Y(n1193) );
CLKBUFX2TS U2977 ( .A(n1979), .Y(n1976) );
BUFX3TS U2978 ( .A(n1976), .Y(n1978) );
OAI2BB2XLTS U2979 ( .B0(n1978), .B1(n2248), .A0N(n1984), .A1N(
result_add_subt[9]), .Y(n1192) );
OAI2BB2XLTS U2980 ( .B0(n1978), .B1(n2249), .A0N(n1983), .A1N(
result_add_subt[10]), .Y(n1191) );
BUFX3TS U2981 ( .A(n1974), .Y(n1981) );
OAI2BB2XLTS U2982 ( .B0(n1975), .B1(n2250), .A0N(n1981), .A1N(
result_add_subt[11]), .Y(n1190) );
OAI2BB2XLTS U2983 ( .B0(n1975), .B1(n2251), .A0N(n1983), .A1N(
result_add_subt[12]), .Y(n1189) );
OAI2BB2XLTS U2984 ( .B0(n1978), .B1(n2252), .A0N(n1981), .A1N(
result_add_subt[13]), .Y(n1188) );
OAI2BB2XLTS U2985 ( .B0(n1975), .B1(n2253), .A0N(n1983), .A1N(
result_add_subt[14]), .Y(n1187) );
OAI2BB2XLTS U2986 ( .B0(n1975), .B1(n2254), .A0N(n1981), .A1N(
result_add_subt[15]), .Y(n1186) );
BUFX3TS U2987 ( .A(n1974), .Y(n1980) );
OAI2BB2XLTS U2988 ( .B0(n1978), .B1(n2255), .A0N(n1980), .A1N(
result_add_subt[16]), .Y(n1185) );
OAI2BB2XLTS U2989 ( .B0(n1978), .B1(n2256), .A0N(n1981), .A1N(
result_add_subt[17]), .Y(n1184) );
OAI2BB2XLTS U2990 ( .B0(n1975), .B1(n2257), .A0N(n1980), .A1N(
result_add_subt[18]), .Y(n1183) );
OAI2BB2XLTS U2991 ( .B0(n1978), .B1(n2258), .A0N(n1983), .A1N(
result_add_subt[19]), .Y(n1182) );
OAI2BB2XLTS U2992 ( .B0(n1978), .B1(n2259), .A0N(n1977), .A1N(
result_add_subt[20]), .Y(n1181) );
OAI2BB2XLTS U2993 ( .B0(n1978), .B1(n2260), .A0N(n1981), .A1N(
result_add_subt[21]), .Y(n1180) );
OAI2BB2XLTS U2994 ( .B0(n1978), .B1(n2261), .A0N(n1977), .A1N(
result_add_subt[22]), .Y(n1179) );
BUFX3TS U2995 ( .A(n1976), .Y(n1988) );
OAI2BB2XLTS U2996 ( .B0(n1988), .B1(n2262), .A0N(n1980), .A1N(
result_add_subt[23]), .Y(n1178) );
OAI2BB2XLTS U2997 ( .B0(n1988), .B1(n2263), .A0N(n1977), .A1N(
result_add_subt[24]), .Y(n1177) );
OAI2BB2XLTS U2998 ( .B0(n1988), .B1(n2264), .A0N(n1980), .A1N(
result_add_subt[25]), .Y(n1176) );
OAI2BB2XLTS U2999 ( .B0(n1988), .B1(n2265), .A0N(n1980), .A1N(
result_add_subt[26]), .Y(n1175) );
OAI2BB2XLTS U3000 ( .B0(n1988), .B1(n2266), .A0N(n1977), .A1N(
result_add_subt[27]), .Y(n1174) );
OAI2BB2XLTS U3001 ( .B0(n1988), .B1(n2267), .A0N(n1977), .A1N(
result_add_subt[28]), .Y(n1173) );
OAI2BB2XLTS U3002 ( .B0(n1988), .B1(n2268), .A0N(n1980), .A1N(
result_add_subt[29]), .Y(n1172) );
OAI2BB2XLTS U3003 ( .B0(n1988), .B1(n2269), .A0N(n1977), .A1N(
result_add_subt[30]), .Y(n1171) );
OAI2BB2XLTS U3004 ( .B0(n1978), .B1(n2270), .A0N(n1980), .A1N(
result_add_subt[31]), .Y(n1170) );
OAI2BB2XLTS U3005 ( .B0(n1988), .B1(n2271), .A0N(n1981), .A1N(
result_add_subt[32]), .Y(n1169) );
BUFX3TS U3006 ( .A(n1976), .Y(n1982) );
OAI2BB2XLTS U3007 ( .B0(n1982), .B1(n2272), .A0N(n1980), .A1N(
result_add_subt[33]), .Y(n1168) );
OAI2BB2XLTS U3008 ( .B0(n1982), .B1(n2273), .A0N(n1980), .A1N(
result_add_subt[34]), .Y(n1167) );
OAI2BB2XLTS U3009 ( .B0(n1982), .B1(n2274), .A0N(n1981), .A1N(
result_add_subt[35]), .Y(n1166) );
OAI2BB2XLTS U3010 ( .B0(n1982), .B1(n2275), .A0N(n1980), .A1N(
result_add_subt[36]), .Y(n1165) );
OAI2BB2XLTS U3011 ( .B0(n1982), .B1(n2276), .A0N(n1981), .A1N(
result_add_subt[37]), .Y(n1164) );
OAI2BB2XLTS U3012 ( .B0(n1982), .B1(n2277), .A0N(n1983), .A1N(
result_add_subt[38]), .Y(n1163) );
OAI2BB2XLTS U3013 ( .B0(n1982), .B1(n2278), .A0N(n1983), .A1N(
result_add_subt[39]), .Y(n1162) );
OAI2BB2XLTS U3014 ( .B0(n1982), .B1(n2279), .A0N(n1981), .A1N(
result_add_subt[40]), .Y(n1161) );
OAI2BB2XLTS U3015 ( .B0(n1982), .B1(n2280), .A0N(n1983), .A1N(
result_add_subt[41]), .Y(n1160) );
OAI2BB2XLTS U3016 ( .B0(n1982), .B1(n2281), .A0N(n1981), .A1N(
result_add_subt[42]), .Y(n1159) );
BUFX3TS U3017 ( .A(n1976), .Y(n1985) );
OAI2BB2XLTS U3018 ( .B0(n1985), .B1(n2282), .A0N(n1983), .A1N(
result_add_subt[43]), .Y(n1158) );
OAI2BB2XLTS U3019 ( .B0(n1985), .B1(n2283), .A0N(n1984), .A1N(
result_add_subt[44]), .Y(n1157) );
OAI2BB2XLTS U3020 ( .B0(n1985), .B1(n2284), .A0N(n1983), .A1N(
result_add_subt[45]), .Y(n1156) );
OAI2BB2XLTS U3021 ( .B0(n1985), .B1(n2285), .A0N(n1984), .A1N(
result_add_subt[46]), .Y(n1155) );
OAI2BB2XLTS U3022 ( .B0(n1985), .B1(n2286), .A0N(n1984), .A1N(
result_add_subt[47]), .Y(n1154) );
OAI2BB2XLTS U3023 ( .B0(n1985), .B1(n2287), .A0N(n1984), .A1N(
result_add_subt[48]), .Y(n1153) );
OAI2BB2XLTS U3024 ( .B0(n1985), .B1(n2288), .A0N(n1984), .A1N(
result_add_subt[49]), .Y(n1152) );
OAI2BB2XLTS U3025 ( .B0(n1985), .B1(n2289), .A0N(n1984), .A1N(
result_add_subt[50]), .Y(n1151) );
OAI2BB2XLTS U3026 ( .B0(n1985), .B1(n2290), .A0N(n1984), .A1N(
result_add_subt[51]), .Y(n1150) );
OAI2BB2XLTS U3027 ( .B0(n1985), .B1(n2121), .A0N(n1984), .A1N(
result_add_subt[52]), .Y(n1149) );
OAI2BB2XLTS U3028 ( .B0(n1987), .B1(n2122), .A0N(n1986), .A1N(
result_add_subt[53]), .Y(n1148) );
OAI2BB2XLTS U3029 ( .B0(n1987), .B1(n2291), .A0N(n1986), .A1N(
result_add_subt[54]), .Y(n1147) );
OAI2BB2XLTS U3030 ( .B0(n1987), .B1(n2123), .A0N(n1986), .A1N(
result_add_subt[55]), .Y(n1146) );
OAI2BB2XLTS U3031 ( .B0(n1987), .B1(n2124), .A0N(n1986), .A1N(
result_add_subt[56]), .Y(n1145) );
OAI2BB2XLTS U3032 ( .B0(n1987), .B1(n2125), .A0N(n1986), .A1N(
result_add_subt[57]), .Y(n1144) );
OAI2BB2XLTS U3033 ( .B0(n1987), .B1(n2126), .A0N(n1986), .A1N(
result_add_subt[58]), .Y(n1143) );
OAI2BB2XLTS U3034 ( .B0(n1988), .B1(n2292), .A0N(n1979), .A1N(
result_add_subt[63]), .Y(n1138) );
BUFX3TS U3035 ( .A(n2004), .Y(n2000) );
INVX2TS U3036 ( .A(n2000), .Y(n1992) );
BUFX3TS U3037 ( .A(n2004), .Y(n2005) );
BUFX3TS U3038 ( .A(n2005), .Y(n1993) );
INVX2TS U3039 ( .A(n2004), .Y(n1994) );
BUFX3TS U3040 ( .A(n2000), .Y(n1995) );
INVX2TS U3041 ( .A(n2004), .Y(n1996) );
BUFX3TS U3042 ( .A(n2004), .Y(n1997) );
INVX2TS U3043 ( .A(n2004), .Y(n1998) );
BUFX3TS U3044 ( .A(n2005), .Y(n1999) );
INVX2TS U3045 ( .A(n2005), .Y(n2001) );
BUFX3TS U3046 ( .A(n2000), .Y(n2002) );
INVX2TS U3047 ( .A(n2005), .Y(n2003) );
INVX2TS U3048 ( .A(n2004), .Y(n2006) );
BUFX3TS U3049 ( .A(n2008), .Y(n2010) );
INVX2TS U3050 ( .A(n2010), .Y(n2007) );
BUFX3TS U3051 ( .A(n2008), .Y(n2012) );
INVX2TS U3052 ( .A(n2012), .Y(n2009) );
INVX2TS U3053 ( .A(n2012), .Y(n2011) );
BUFX3TS U3054 ( .A(n2016), .Y(n2013) );
INVX2TS U3055 ( .A(n2012), .Y(n2014) );
BUFX3TS U3056 ( .A(n2016), .Y(n2015) );
INVX2TS U3057 ( .A(n2018), .Y(n2017) );
BUFX3TS U3058 ( .A(n2016), .Y(n2019) );
INVX2TS U3059 ( .A(n2018), .Y(n2020) );
NAND3X1TS U3060 ( .A(cont_iter_out[2]), .B(n1499), .C(n2027), .Y(n2068) );
BUFX3TS U3061 ( .A(n2156), .Y(n2095) );
AOI21X2TS U3062 ( .A0(cont_iter_out[2]), .A1(n1499), .B0(n1505), .Y(n2090)
);
AOI31X1TS U3063 ( .A0(n2090), .A1(n2088), .A2(n2037), .B0(n2091), .Y(n2074)
);
AOI22X1TS U3064 ( .A0(n2027), .A1(n2227), .B0(n2091), .B1(d_ff3_LUT_out[5]),
.Y(n2028) );
NAND2X1TS U3065 ( .A(n2028), .B(n2062), .Y(n940) );
NAND2X1TS U3066 ( .A(n2065), .B(n2051), .Y(n2072) );
AOI22X1TS U3067 ( .A0(n1517), .A1(n2087), .B0(n2053), .B1(n2031), .Y(n937)
);
INVX2TS U3068 ( .A(n2032), .Y(n2043) );
AOI211X1TS U3069 ( .A0(n1505), .A1(n2036), .B0(n2153), .C0(n2038), .Y(n2075)
);
INVX2TS U3070 ( .A(n2215), .Y(n2097) );
AOI211X1TS U3071 ( .A0(n2100), .A1(n1496), .B0(n1505), .C0(cont_iter_out[2]),
.Y(n2059) );
NAND2X1TS U3072 ( .A(n2097), .B(n2059), .Y(n2098) );
OA21XLTS U3073 ( .A0(n2211), .A1(d_ff3_LUT_out[12]), .B0(n2098), .Y(n933) );
NOR3X1TS U3074 ( .A(n2043), .B(n2039), .C(n2038), .Y(n2041) );
NOR2X2TS U3075 ( .A(n2040), .B(n2152), .Y(n2096) );
OAI32X1TS U3076 ( .A0(n2044), .A1(n2043), .A2(n2042), .B0(d_ff3_LUT_out[15]),
.B1(n2213), .Y(n2045) );
AOI21X1TS U3077 ( .A0(n2090), .A1(n2078), .B0(n2091), .Y(n2046) );
BUFX3TS U3078 ( .A(n2156), .Y(n2158) );
OAI2BB1X1TS U3079 ( .A0N(d_ff3_LUT_out[17]), .A1N(n2158), .B0(n2047), .Y(
n928) );
AOI211X1TS U3080 ( .A0(cont_iter_out[2]), .A1(n2049), .B0(n2093), .C0(n2048),
.Y(n2083) );
OA22X1TS U3081 ( .A0(n2051), .A1(n2079), .B0(n2097), .B1(d_ff3_LUT_out[18]),
.Y(n927) );
OAI2BB1X1TS U3082 ( .A0N(d_ff3_LUT_out[22]), .A1N(n2158), .B0(n2053), .Y(
n923) );
AOI211X1TS U3083 ( .A0(n2055), .A1(n2064), .B0(n2060), .C0(n2054), .Y(n2056)
);
INVX2TS U3084 ( .A(n2056), .Y(n2066) );
INVX2TS U3085 ( .A(n2156), .Y(n2104) );
NAND2X1TS U3086 ( .A(n2059), .B(n2088), .Y(n2077) );
CLKBUFX2TS U3087 ( .A(n2154), .Y(n2163) );
CLKBUFX2TS U3088 ( .A(n2163), .Y(n2167) );
BUFX3TS U3089 ( .A(n2167), .Y(n2103) );
NAND2X1TS U3090 ( .A(n2064), .B(n2063), .Y(n2069) );
OAI22X1TS U3091 ( .A0(n1476), .A1(n2066), .B0(n2213), .B1(d_ff3_LUT_out[27]),
.Y(n2067) );
OAI2BB1X1TS U3092 ( .A0N(d_ff3_LUT_out[28]), .A1N(n2158), .B0(n2086), .Y(
n917) );
NAND2X1TS U3093 ( .A(d_ff3_LUT_out[29]), .B(n2091), .Y(n2070) );
OAI21X1TS U3094 ( .A0(n2093), .A1(n2077), .B0(n2213), .Y(n2081) );
OAI2BB1X1TS U3095 ( .A0N(d_ff3_LUT_out[32]), .A1N(n2158), .B0(n2081), .Y(
n913) );
AOI31X1TS U3096 ( .A0(n2090), .A1(n2078), .A2(n2088), .B0(n2091), .Y(n2092)
);
OA21XLTS U3097 ( .A0(n2211), .A1(d_ff3_LUT_out[35]), .B0(n2079), .Y(n910) );
OAI2BB1X1TS U3098 ( .A0N(d_ff3_LUT_out[36]), .A1N(n2158), .B0(n2086), .Y(
n909) );
INVX2TS U3099 ( .A(n2044), .Y(n2206) );
OAI2BB1X1TS U3100 ( .A0N(d_ff3_LUT_out[38]), .A1N(n2158), .B0(n2081), .Y(
n907) );
OAI2BB2XLTS U3101 ( .B0(n2097), .B1(d_ff3_LUT_out[39]), .A0N(n2083), .A1N(
n2082), .Y(n2084) );
OAI2BB1X1TS U3102 ( .A0N(d_ff3_LUT_out[40]), .A1N(n2158), .B0(n2086), .Y(
n905) );
AOI32X1TS U3103 ( .A0(n2090), .A1(n2076), .A2(n2088), .B0(n1516), .B1(n2087),
.Y(n904) );
AOI31X1TS U3104 ( .A0(n2195), .A1(n1484), .A2(n2227), .B0(n2091), .Y(n2094)
);
OA22X1TS U3105 ( .A0(n2093), .A1(n2098), .B0(n2097), .B1(d_ff3_LUT_out[45]),
.Y(n900) );
OA22X1TS U3106 ( .A0(n2099), .A1(n2098), .B0(n2097), .B1(d_ff3_LUT_out[50]),
.Y(n895) );
INVX2TS U3107 ( .A(n2180), .Y(n2175) );
INVX2TS U3108 ( .A(n2180), .Y(n2112) );
INVX2TS U3109 ( .A(n2171), .Y(n2107) );
BUFX3TS U3110 ( .A(n2167), .Y(n2109) );
INVX2TS U3111 ( .A(n2182), .Y(n2114) );
INVX2TS U3112 ( .A(n2171), .Y(n2115) );
INVX2TS U3113 ( .A(n2171), .Y(n2110) );
INVX2TS U3114 ( .A(n2178), .Y(n2111) );
INVX2TS U3115 ( .A(n2182), .Y(n2172) );
BUFX3TS U3116 ( .A(n2171), .Y(n2113) );
INVX2TS U3117 ( .A(n2171), .Y(n2119) );
INVX2TS U3118 ( .A(n2178), .Y(n2116) );
BUFX3TS U3119 ( .A(n2167), .Y(n2117) );
CLKBUFX2TS U3120 ( .A(n2180), .Y(n2179) );
INVX2TS U3121 ( .A(n2179), .Y(n2219) );
INVX2TS U3122 ( .A(n2178), .Y(n2218) );
INVX2TS U3123 ( .A(n2179), .Y(n2164) );
INVX2TS U3124 ( .A(n2176), .Y(n2174) );
BUFX3TS U3125 ( .A(n2167), .Y(n2220) );
INVX2TS U3126 ( .A(n2179), .Y(n2186) );
BUFX3TS U3127 ( .A(n2163), .Y(n2161) );
INVX2TS U3128 ( .A(n2178), .Y(n2155) );
BUFX3TS U3129 ( .A(n2120), .Y(n2184) );
BUFX3TS U3130 ( .A(n2184), .Y(n2133) );
OAI22X1TS U3131 ( .A0(n2133), .A1(n2234), .B0(n2121), .B1(n2180), .Y(n720)
);
OAI22X1TS U3132 ( .A0(n2133), .A1(n1480), .B0(n2122), .B1(n2185), .Y(n719)
);
OAI22X1TS U3133 ( .A0(n2133), .A1(n2232), .B0(n2123), .B1(n2185), .Y(n717)
);
OAI22X1TS U3134 ( .A0(n2133), .A1(n2138), .B0(n2124), .B1(n2182), .Y(n716)
);
OAI22X1TS U3135 ( .A0(n2133), .A1(n2233), .B0(n2125), .B1(n2131), .Y(n715)
);
OAI22X1TS U3136 ( .A0(n2133), .A1(n2127), .B0(n2126), .B1(n2131), .Y(n714)
);
OAI22X1TS U3137 ( .A0(n2133), .A1(n2235), .B0(n2128), .B1(n2131), .Y(n713)
);
OAI22X1TS U3138 ( .A0(n2133), .A1(n2146), .B0(n2129), .B1(n2131), .Y(n712)
);
OAI22X1TS U3139 ( .A0(n2133), .A1(n2236), .B0(n2130), .B1(n2131), .Y(n711)
);
OAI22X1TS U3140 ( .A0(n2133), .A1(n2237), .B0(n2132), .B1(n2131), .Y(n710)
);
AOI21X1TS U3141 ( .A0(d_ff2_Y[52]), .A1(n2188), .B0(n2136), .Y(n2134) );
AOI22X1TS U3142 ( .A0(n1477), .A1(n1480), .B0(d_ff2_Y[53]), .B1(n1496), .Y(
n2135) );
XNOR2X1TS U3143 ( .A(n2136), .B(n2135), .Y(n2137) );
AOI21X1TS U3144 ( .A0(d_ff2_Y[57]), .A1(n2142), .B0(n2141), .Y(n2143) );
AOI21X1TS U3145 ( .A0(d_ff2_Y[59]), .A1(n2144), .B0(n2147), .Y(n2145) );
AOI21X1TS U3146 ( .A0(d_ff2_Y[61]), .A1(n2150), .B0(n2149), .Y(n2151) );
INVX2TS U3147 ( .A(n2182), .Y(n2168) );
OA22X1TS U3148 ( .A0(n2184), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n2180),
.Y(n690) );
OA22X1TS U3149 ( .A0(n2184), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n2182),
.Y(n684) );
INVX2TS U3150 ( .A(n2215), .Y(n2157) );
OA22X1TS U3151 ( .A0(n2184), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n2180),
.Y(n682) );
OA22X1TS U3152 ( .A0(n2184), .A1(d_ff2_X[8]), .B0(d_ff_Xn[8]), .B1(n2182),
.Y(n680) );
OA22X1TS U3153 ( .A0(n2184), .A1(d_ff2_X[9]), .B0(d_ff_Xn[9]), .B1(n2179),
.Y(n678) );
OA22X1TS U3154 ( .A0(n2102), .A1(d_ff2_X[11]), .B0(d_ff_Xn[11]), .B1(n2179),
.Y(n674) );
INVX2TS U3155 ( .A(n2163), .Y(n2159) );
INVX2TS U3156 ( .A(n2176), .Y(n2160) );
INVX2TS U3157 ( .A(n2163), .Y(n2162) );
OA22X1TS U3158 ( .A0(n2170), .A1(d_ff2_X[32]), .B0(d_ff_Xn[32]), .B1(n2166),
.Y(n632) );
BUFX3TS U3159 ( .A(n2167), .Y(n2165) );
OA22X1TS U3160 ( .A0(n2170), .A1(d_ff2_X[34]), .B0(d_ff_Xn[34]), .B1(n2166),
.Y(n628) );
OA22X1TS U3161 ( .A0(n2170), .A1(d_ff2_X[35]), .B0(d_ff_Xn[35]), .B1(n2166),
.Y(n626) );
INVX2TS U3162 ( .A(n2163), .Y(n2169) );
OA22X1TS U3163 ( .A0(n2170), .A1(d_ff2_X[39]), .B0(d_ff_Xn[39]), .B1(n2177),
.Y(n618) );
OA22X1TS U3164 ( .A0(n2170), .A1(d_ff2_X[41]), .B0(d_ff_Xn[41]), .B1(n2177),
.Y(n614) );
OA22X1TS U3165 ( .A0(n2170), .A1(d_ff2_X[42]), .B0(d_ff_Xn[42]), .B1(n2166),
.Y(n612) );
BUFX3TS U3166 ( .A(n2167), .Y(n2173) );
OA22X1TS U3167 ( .A0(n2170), .A1(d_ff2_X[43]), .B0(d_ff_Xn[43]), .B1(n2177),
.Y(n610) );
OA22X1TS U3168 ( .A0(n2170), .A1(d_ff2_X[45]), .B0(d_ff_Xn[45]), .B1(n2177),
.Y(n606) );
OA22X1TS U3169 ( .A0(n2170), .A1(d_ff2_X[46]), .B0(d_ff_Xn[46]), .B1(n2177),
.Y(n604) );
INVX2TS U3170 ( .A(n2171), .Y(n2204) );
OA22X1TS U3171 ( .A0(n2176), .A1(d_ff2_X[53]), .B0(d_ff_Xn[53]), .B1(n2177),
.Y(n591) );
OA22X1TS U3172 ( .A0(n2178), .A1(d_ff2_X[54]), .B0(d_ff_Xn[54]), .B1(n2177),
.Y(n590) );
OA22X1TS U3173 ( .A0(d_ff_Xn[55]), .A1(n2179), .B0(d_ff2_X[55]), .B1(n2184),
.Y(n589) );
OA22X1TS U3174 ( .A0(d_ff_Xn[57]), .A1(n2180), .B0(d_ff2_X[57]), .B1(n2184),
.Y(n587) );
OA22X1TS U3175 ( .A0(d_ff_Xn[59]), .A1(n2182), .B0(d_ff2_X[59]), .B1(n2184),
.Y(n585) );
OA22X1TS U3176 ( .A0(d_ff_Xn[61]), .A1(n2185), .B0(d_ff2_X[61]), .B1(n2184),
.Y(n583) );
AOI21X1TS U3177 ( .A0(d_ff2_X[52]), .A1(n1484), .B0(n2191), .Y(n2189) );
AOI22X1TS U3178 ( .A0(n1500), .A1(n2228), .B0(d_ff2_X[53]), .B1(n1496), .Y(
n2190) );
XNOR2X1TS U3179 ( .A(n2191), .B(n2190), .Y(n2192) );
OAI22X1TS U3180 ( .A0(n2197), .A1(d_ff2_X[55]), .B0(n2196), .B1(n2195), .Y(
n2198) );
OAI21XLTS U3181 ( .A0(n2198), .A1(n1481), .B0(n2200), .Y(n2199) );
NOR2X2TS U3182 ( .A(d_ff2_X[57]), .B(n2200), .Y(n2202) );
AOI21X1TS U3183 ( .A0(d_ff2_X[57]), .A1(n2200), .B0(n2202), .Y(n2201) );
NOR2X2TS U3184 ( .A(d_ff2_X[59]), .B(n2205), .Y(n2208) );
AOI21X1TS U3185 ( .A0(d_ff2_X[59]), .A1(n2205), .B0(n2208), .Y(n2207) );
NOR2X1TS U3186 ( .A(d_ff2_X[61]), .B(n2210), .Y(n2214) );
AOI21X1TS U3187 ( .A0(d_ff2_X[61]), .A1(n2210), .B0(n2214), .Y(n2212) );
XOR2X1TS U3188 ( .A(d_ff2_X[62]), .B(n2214), .Y(n2216) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf");
endmodule |
module %m, node %2d, time = ",i, $stime);
end
// synopsys translate_on
end
endmodule |
module %m, node %2d, time = ",i, $stime);
end
// synopsys translate_on
end
endmodule |
module HeadFieldExtractor (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] dout_data,
output wire dout_last,
input wire dout_ready,
output wire dout_valid,
output wire[63:0] headers_data,
output wire headers_last,
input wire headers_ready,
output wire headers_valid
);
assign din_ready = 1'bx;
assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign dout_last = 1'bx;
assign dout_valid = 1'bx;
assign headers_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign headers_last = 1'bx;
assign headers_valid = 1'bx;
endmodule |
module PatternMatch (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] match_data,
output wire match_last,
input wire match_ready,
output wire match_valid
);
assign din_ready = 1'bx;
assign match_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign match_last = 1'bx;
assign match_valid = 1'bx;
endmodule |
module Filter (
input wire[31:0] cfg_ar_addr,
input wire[2:0] cfg_ar_prot,
output wire cfg_ar_ready,
input wire cfg_ar_valid,
input wire[31:0] cfg_aw_addr,
input wire[2:0] cfg_aw_prot,
output wire cfg_aw_ready,
input wire cfg_aw_valid,
input wire cfg_b_ready,
output wire[1:0] cfg_b_resp,
output wire cfg_b_valid,
output wire[63:0] cfg_r_data,
input wire cfg_r_ready,
output wire[1:0] cfg_r_resp,
output wire cfg_r_valid,
input wire[63:0] cfg_w_data,
output wire cfg_w_ready,
input wire[7:0] cfg_w_strb,
input wire cfg_w_valid,
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] dout_data,
output wire dout_last,
input wire dout_ready,
output wire dout_valid,
input wire[63:0] headers_data,
input wire headers_last,
output wire headers_ready,
input wire headers_valid,
input wire[63:0] patternMatch_data,
input wire patternMatch_last,
output wire patternMatch_ready,
input wire patternMatch_valid
);
assign cfg_ar_ready = 1'bx;
assign cfg_aw_ready = 1'bx;
assign cfg_b_resp = 2'bxx;
assign cfg_b_valid = 1'bx;
assign cfg_r_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign cfg_r_resp = 2'bxx;
assign cfg_r_valid = 1'bx;
assign cfg_w_ready = 1'bx;
assign din_ready = 1'bx;
assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign dout_last = 1'bx;
assign dout_valid = 1'bx;
assign headers_ready = 1'bx;
assign patternMatch_ready = 1'bx;
endmodule |
module Exporter (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] dout_data,
output wire dout_last,
input wire dout_ready,
output wire dout_valid
);
assign din_ready = 1'bx;
assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign dout_last = 1'bx;
assign dout_valid = 1'bx;
endmodule |
module AxiSSplitCopy #(
parameter DATA_WIDTH = 64,
parameter DEST_WIDTH = 0,
parameter ID_WIDTH = 0,
parameter INTF_CLS = "<class 'hwtLib.amba.axis.AxiStream'>",
parameter IS_BIGENDIAN = 0,
parameter OUTPUTS = 2,
parameter USER_WIDTH = 0,
parameter USE_KEEP = 0,
parameter USE_STRB = 0
) (
input wire[63:0] dataIn_data,
input wire dataIn_last,
output reg dataIn_ready,
input wire dataIn_valid,
output wire[63:0] dataOut_0_data,
output wire dataOut_0_last,
input wire dataOut_0_ready,
output reg dataOut_0_valid,
output wire[63:0] dataOut_1_data,
output wire dataOut_1_last,
input wire dataOut_1_ready,
output reg dataOut_1_valid
);
always @(dataOut_0_ready, dataOut_1_ready) begin: assig_process_dataIn_ready
dataIn_ready = dataOut_0_ready & dataOut_1_ready;
end
assign dataOut_0_data = dataIn_data;
assign dataOut_0_last = dataIn_last;
always @(dataIn_valid, dataOut_1_ready) begin: assig_process_dataOut_0_valid
dataOut_0_valid = dataIn_valid & dataOut_1_ready;
end
assign dataOut_1_data = dataIn_data;
assign dataOut_1_last = dataIn_last;
always @(dataIn_valid, dataOut_0_ready) begin: assig_process_dataOut_1_valid
dataOut_1_valid = dataIn_valid & dataOut_0_ready;
end
generate if (DATA_WIDTH != 64)
$error("%m Generated only for this param value");
endgenerate
generate if (DEST_WIDTH != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (ID_WIDTH != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (INTF_CLS != "<class 'hwtLib.amba.axis.AxiStream'>")
$error("%m Generated only for this param value");
endgenerate
generate if (IS_BIGENDIAN != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (OUTPUTS != 2)
$error("%m Generated only for this param value");
endgenerate
generate if (USER_WIDTH != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (USE_KEEP != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (USE_STRB != 0)
$error("%m Generated only for this param value");
endgenerate
endmodule |
module NetFilter #(
parameter DATA_WIDTH = 64
) (
input wire[31:0] cfg_ar_addr,
input wire[2:0] cfg_ar_prot,
output wire cfg_ar_ready,
input wire cfg_ar_valid,
input wire[31:0] cfg_aw_addr,
input wire[2:0] cfg_aw_prot,
output wire cfg_aw_ready,
input wire cfg_aw_valid,
input wire cfg_b_ready,
output wire[1:0] cfg_b_resp,
output wire cfg_b_valid,
output wire[63:0] cfg_r_data,
input wire cfg_r_ready,
output wire[1:0] cfg_r_resp,
output wire cfg_r_valid,
input wire[63:0] cfg_w_data,
output wire cfg_w_ready,
input wire[7:0] cfg_w_strb,
input wire cfg_w_valid,
input wire clk,
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] export_data,
output wire export_last,
input wire export_ready,
output wire export_valid,
input wire rst_n
);
wire[63:0] sig_exporter_din_data;
wire sig_exporter_din_last;
wire sig_exporter_din_ready;
wire sig_exporter_din_valid;
wire[63:0] sig_exporter_dout_data;
wire sig_exporter_dout_last;
wire sig_exporter_dout_ready;
wire sig_exporter_dout_valid;
wire[31:0] sig_filter_cfg_ar_addr;
wire[2:0] sig_filter_cfg_ar_prot;
wire sig_filter_cfg_ar_ready;
wire sig_filter_cfg_ar_valid;
wire[31:0] sig_filter_cfg_aw_addr;
wire[2:0] sig_filter_cfg_aw_prot;
wire sig_filter_cfg_aw_ready;
wire sig_filter_cfg_aw_valid;
wire sig_filter_cfg_b_ready;
wire[1:0] sig_filter_cfg_b_resp;
wire sig_filter_cfg_b_valid;
wire[63:0] sig_filter_cfg_r_data;
wire sig_filter_cfg_r_ready;
wire[1:0] sig_filter_cfg_r_resp;
wire sig_filter_cfg_r_valid;
wire[63:0] sig_filter_cfg_w_data;
wire sig_filter_cfg_w_ready;
wire[7:0] sig_filter_cfg_w_strb;
wire sig_filter_cfg_w_valid;
wire[63:0] sig_filter_din_data;
wire sig_filter_din_last;
wire sig_filter_din_ready;
wire sig_filter_din_valid;
wire[63:0] sig_filter_dout_data;
wire sig_filter_dout_last;
wire sig_filter_dout_ready;
wire sig_filter_dout_valid;
wire[63:0] sig_filter_headers_data;
wire sig_filter_headers_last;
wire sig_filter_headers_ready;
wire sig_filter_headers_valid;
wire[63:0] sig_filter_patternMatch_data;
wire sig_filter_patternMatch_last;
wire sig_filter_patternMatch_ready;
wire sig_filter_patternMatch_valid;
wire[63:0] sig_gen_dout_splitCopy_0_dataIn_data;
wire sig_gen_dout_splitCopy_0_dataIn_last;
wire sig_gen_dout_splitCopy_0_dataIn_ready;
wire sig_gen_dout_splitCopy_0_dataIn_valid;
wire[63:0] sig_gen_dout_splitCopy_0_dataOut_0_data;
wire sig_gen_dout_splitCopy_0_dataOut_0_last;
wire sig_gen_dout_splitCopy_0_dataOut_0_ready;
wire sig_gen_dout_splitCopy_0_dataOut_0_valid;
wire[63:0] sig_gen_dout_splitCopy_0_dataOut_1_data;
wire sig_gen_dout_splitCopy_0_dataOut_1_last;
wire sig_gen_dout_splitCopy_0_dataOut_1_ready;
wire sig_gen_dout_splitCopy_0_dataOut_1_valid;
wire[63:0] sig_hfe_din_data;
wire sig_hfe_din_last;
wire sig_hfe_din_ready;
wire sig_hfe_din_valid;
wire[63:0] sig_hfe_dout_data;
wire sig_hfe_dout_last;
wire sig_hfe_dout_ready;
wire sig_hfe_dout_valid;
wire[63:0] sig_hfe_headers_data;
wire sig_hfe_headers_last;
wire sig_hfe_headers_ready;
wire sig_hfe_headers_valid;
wire[63:0] sig_patternMatch_din_data;
wire sig_patternMatch_din_last;
wire sig_patternMatch_din_ready;
wire sig_patternMatch_din_valid;
wire[63:0] sig_patternMatch_match_data;
wire sig_patternMatch_match_last;
wire sig_patternMatch_match_ready;
wire sig_patternMatch_match_valid;
Exporter exporter_inst (
.din_data(sig_exporter_din_data),
.din_last(sig_exporter_din_last),
.din_ready(sig_exporter_din_ready),
.din_valid(sig_exporter_din_valid),
.dout_data(sig_exporter_dout_data),
.dout_last(sig_exporter_dout_last),
.dout_ready(sig_exporter_dout_ready),
.dout_valid(sig_exporter_dout_valid)
);
Filter filter_inst (
.cfg_ar_addr(sig_filter_cfg_ar_addr),
.cfg_ar_prot(sig_filter_cfg_ar_prot),
.cfg_ar_ready(sig_filter_cfg_ar_ready),
.cfg_ar_valid(sig_filter_cfg_ar_valid),
.cfg_aw_addr(sig_filter_cfg_aw_addr),
.cfg_aw_prot(sig_filter_cfg_aw_prot),
.cfg_aw_ready(sig_filter_cfg_aw_ready),
.cfg_aw_valid(sig_filter_cfg_aw_valid),
.cfg_b_ready(sig_filter_cfg_b_ready),
.cfg_b_resp(sig_filter_cfg_b_resp),
.cfg_b_valid(sig_filter_cfg_b_valid),
.cfg_r_data(sig_filter_cfg_r_data),
.cfg_r_ready(sig_filter_cfg_r_ready),
.cfg_r_resp(sig_filter_cfg_r_resp),
.cfg_r_valid(sig_filter_cfg_r_valid),
.cfg_w_data(sig_filter_cfg_w_data),
.cfg_w_ready(sig_filter_cfg_w_ready),
.cfg_w_strb(sig_filter_cfg_w_strb),
.cfg_w_valid(sig_filter_cfg_w_valid),
.din_data(sig_filter_din_data),
.din_last(sig_filter_din_last),
.din_ready(sig_filter_din_ready),
.din_valid(sig_filter_din_valid),
.dout_data(sig_filter_dout_data),
.dout_last(sig_filter_dout_last),
.dout_ready(sig_filter_dout_ready),
.dout_valid(sig_filter_dout_valid),
.headers_data(sig_filter_headers_data),
.headers_last(sig_filter_headers_last),
.headers_ready(sig_filter_headers_ready),
.headers_valid(sig_filter_headers_valid),
.patternMatch_data(sig_filter_patternMatch_data),
.patternMatch_last(sig_filter_patternMatch_last),
.patternMatch_ready(sig_filter_patternMatch_ready),
.patternMatch_valid(sig_filter_patternMatch_valid)
);
AxiSSplitCopy #(
.DATA_WIDTH(64),
.DEST_WIDTH(0),
.ID_WIDTH(0),
.INTF_CLS("<class 'hwtLib.amba.axis.AxiStream'>"),
.IS_BIGENDIAN(0),
.OUTPUTS(2),
.USER_WIDTH(0),
.USE_KEEP(0),
.USE_STRB(0)
) gen_dout_splitCopy_0_inst (
.dataIn_data(sig_gen_dout_splitCopy_0_dataIn_data),
.dataIn_last(sig_gen_dout_splitCopy_0_dataIn_last),
.dataIn_ready(sig_gen_dout_splitCopy_0_dataIn_ready),
.dataIn_valid(sig_gen_dout_splitCopy_0_dataIn_valid),
.dataOut_0_data(sig_gen_dout_splitCopy_0_dataOut_0_data),
.dataOut_0_last(sig_gen_dout_splitCopy_0_dataOut_0_last),
.dataOut_0_ready(sig_gen_dout_splitCopy_0_dataOut_0_ready),
.dataOut_0_valid(sig_gen_dout_splitCopy_0_dataOut_0_valid),
.dataOut_1_data(sig_gen_dout_splitCopy_0_dataOut_1_data),
.dataOut_1_last(sig_gen_dout_splitCopy_0_dataOut_1_last),
.dataOut_1_ready(sig_gen_dout_splitCopy_0_dataOut_1_ready),
.dataOut_1_valid(sig_gen_dout_splitCopy_0_dataOut_1_valid)
);
HeadFieldExtractor hfe_inst (
.din_data(sig_hfe_din_data),
.din_last(sig_hfe_din_last),
.din_ready(sig_hfe_din_ready),
.din_valid(sig_hfe_din_valid),
.dout_data(sig_hfe_dout_data),
.dout_last(sig_hfe_dout_last),
.dout_ready(sig_hfe_dout_ready),
.dout_valid(sig_hfe_dout_valid),
.headers_data(sig_hfe_headers_data),
.headers_last(sig_hfe_headers_last),
.headers_ready(sig_hfe_headers_ready),
.headers_valid(sig_hfe_headers_valid)
);
PatternMatch patternMatch_inst (
.din_data(sig_patternMatch_din_data),
.din_last(sig_patternMatch_din_last),
.din_ready(sig_patternMatch_din_ready),
.din_valid(sig_patternMatch_din_valid),
.match_data(sig_patternMatch_match_data),
.match_last(sig_patternMatch_match_last),
.match_ready(sig_patternMatch_match_ready),
.match_valid(sig_patternMatch_match_valid)
);
assign cfg_ar_ready = sig_filter_cfg_ar_ready;
assign cfg_aw_ready = sig_filter_cfg_aw_ready;
assign cfg_b_resp = sig_filter_cfg_b_resp;
assign cfg_b_valid = sig_filter_cfg_b_valid;
assign cfg_r_data = sig_filter_cfg_r_data;
assign cfg_r_resp = sig_filter_cfg_r_resp;
assign cfg_r_valid = sig_filter_cfg_r_valid;
assign cfg_w_ready = sig_filter_cfg_w_ready;
assign din_ready = sig_hfe_din_ready;
assign export_data = sig_exporter_dout_data;
assign export_last = sig_exporter_dout_last;
assign export_valid = sig_exporter_dout_valid;
assign sig_exporter_din_data = sig_filter_dout_data;
assign sig_exporter_din_last = sig_filter_dout_last;
assign sig_exporter_din_valid = sig_filter_dout_valid;
assign sig_exporter_dout_ready = export_ready;
assign sig_filter_cfg_ar_addr = cfg_ar_addr;
assign sig_filter_cfg_ar_prot = cfg_ar_prot;
assign sig_filter_cfg_ar_valid = cfg_ar_valid;
assign sig_filter_cfg_aw_addr = cfg_aw_addr;
assign sig_filter_cfg_aw_prot = cfg_aw_prot;
assign sig_filter_cfg_aw_valid = cfg_aw_valid;
assign sig_filter_cfg_b_ready = cfg_b_ready;
assign sig_filter_cfg_r_ready = cfg_r_ready;
assign sig_filter_cfg_w_data = cfg_w_data;
assign sig_filter_cfg_w_strb = cfg_w_strb;
assign sig_filter_cfg_w_valid = cfg_w_valid;
assign sig_filter_din_data = sig_gen_dout_splitCopy_0_dataOut_1_data;
assign sig_filter_din_last = sig_gen_dout_splitCopy_0_dataOut_1_last;
assign sig_filter_din_valid = sig_gen_dout_splitCopy_0_dataOut_1_valid;
assign sig_filter_dout_ready = sig_exporter_din_ready;
assign sig_filter_headers_data = sig_hfe_headers_data;
assign sig_filter_headers_last = sig_hfe_headers_last;
assign sig_filter_headers_valid = sig_hfe_headers_valid;
assign sig_filter_patternMatch_data = sig_patternMatch_match_data;
assign sig_filter_patternMatch_last = sig_patternMatch_match_last;
assign sig_filter_patternMatch_valid = sig_patternMatch_match_valid;
assign sig_gen_dout_splitCopy_0_dataIn_data = sig_hfe_dout_data;
assign sig_gen_dout_splitCopy_0_dataIn_last = sig_hfe_dout_last;
assign sig_gen_dout_splitCopy_0_dataIn_valid = sig_hfe_dout_valid;
assign sig_gen_dout_splitCopy_0_dataOut_0_ready = sig_patternMatch_din_ready;
assign sig_gen_dout_splitCopy_0_dataOut_1_ready = sig_filter_din_ready;
assign sig_hfe_din_data = din_data;
assign sig_hfe_din_last = din_last;
assign sig_hfe_din_valid = din_valid;
assign sig_hfe_dout_ready = sig_gen_dout_splitCopy_0_dataIn_ready;
assign sig_hfe_headers_ready = sig_filter_headers_ready;
assign sig_patternMatch_din_data = sig_gen_dout_splitCopy_0_dataOut_0_data;
assign sig_patternMatch_din_last = sig_gen_dout_splitCopy_0_dataOut_0_last;
assign sig_patternMatch_din_valid = sig_gen_dout_splitCopy_0_dataOut_0_valid;
assign sig_patternMatch_match_ready = sig_filter_patternMatch_ready;
generate if (DATA_WIDTH != 64)
$error("%m Generated only for this param value");
endgenerate
endmodule |
module barrel_shifter_synthesis (
rotate, sra, ain, bin, yout
);
input rotate;
input sra;
input [15 : 0] ain;
input [4 : 0] bin;
output [15 : 0] yout;
wire ain_0_IBUF_0;
wire ain_14_IBUF_1;
wire ain_1_IBUF_2;
wire ain_13_IBUF_3;
wire ain_2_IBUF_4;
wire ain_12_IBUF_5;
wire ain_3_IBUF_6;
wire ain_11_IBUF_7;
wire ain_4_IBUF_8;
wire ain_10_IBUF_9;
wire ain_5_IBUF_10;
wire ain_9_IBUF_11;
wire ain_6_IBUF_12;
wire ain_8_IBUF_13;
wire ain_7_IBUF_14;
wire ain_15_IBUF_15;
wire bin_4_IBUF_16;
wire bin_3_IBUF_17;
wire bin_2_IBUF_18;
wire bin_1_IBUF_19;
wire bin_0_IBUF_20;
wire rotate_IBUF_21;
wire sra_IBUF_22;
wire yout_15_OBUF_25;
wire yout_14_OBUF_26;
wire yout_13_OBUF_27;
wire yout_12_OBUF_28;
wire yout_11_OBUF_29;
wire yout_10_OBUF_30;
wire yout_9_OBUF_31;
wire yout_8_OBUF_32;
wire yout_7_OBUF_33;
wire yout_6_OBUF_34;
wire yout_5_OBUF_35;
wire yout_4_OBUF_36;
wire yout_3_OBUF_37;
wire yout_2_OBUF_38;
wire yout_1_OBUF_39;
wire yout_0_OBUF_40;
wire \b<3>_mmx_out29 ;
wire \b<3>_mmx_out27 ;
wire \b<3>_mmx_out25 ;
wire \b<3>_mmx_out24 ;
wire \b<3>_mmx_out23 ;
wire \b<3>_mmx_out22 ;
wire \b<2>_mmx_out15 ;
wire \b<3>_mmx_out14 ;
wire \b<2>_mmx_out14 ;
wire \b<2>_mmx_out13 ;
wire \b<3>_mmx_out12 ;
wire \b<2>_mmx_out12 ;
wire \b<3>_mmx_out11 ;
wire \b<2>_mmx_out11 ;
wire \b<2>_mmx_out10 ;
wire \b<2>_mmx_out9 ;
wire \b<3>_mmx_out7 ;
wire \b<2>_mmx_out8 ;
wire \b<3>_mmx_out5 ;
wire \b<3>_mmx_out3 ;
wire \b<2>_mmx_out ;
wire \b<2>111 ;
wire Mmux_yout201;
wire Mmux_yout141;
wire Mmux_yout121;
wire Mmux_yout111_66;
wire Mmux_yout61;
wire Mmux_yout122_68;
wire Mmux_yout191_69;
wire Mmux_yout71;
wire Mmux_yout1221;
wire Mmux_yout51;
wire Mmux_yout1811;
wire Mmux_yout1411;
wire Mmux_yout1311;
wire Mmux_yout1711;
wire Mmux_yout1222;
wire Mmux_yout52;
wire Mmux_yout1511;
wire Mmux_yout1611_80;
wire Mmux_yout114_81;
wire \b<2>151 ;
wire Mmux_yout1112;
wire Mmux_yout1224;
wire Mmux_yout911;
wire Mmux_yout14111_86;
wire Mmux_yout14112_87;
wire Mmux_yout13111_88;
wire Mmux_yout13112_89;
wire Mmux_yout15111_90;
wire Mmux_yout15112_91;
wire Mmux_yout3;
wire Mmux_yout31_93;
wire Mmux_yout32_94;
wire N2;
wire Mmux_yout1141_96;
wire Mmux_yout1211_97;
wire Mmux_yout1212_98;
wire Mmux_yout1213_99;
wire \b<2>2 ;
wire Mmux_yout17111_101;
wire Mmux_yout17112_102;
wire N4;
wire Mmux_yout18111_104;
wire Mmux_yout18112_105;
wire N6;
wire Mmux_yout11;
wire Mmux_yout112_108;
wire Mmux_yout113_109;
wire N8;
wire N10;
wire N12;
wire N14;
wire N15;
wire N16;
wire N17;
wire [3 : 2] b;
LUT2 #(
.INIT ( 4'h6 ))
\Mmux_b<3>11 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.O(b[3])
);
LUT2 #(
.INIT ( 4'h6 ))
\Mmux_b<2>11 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.O(b[2])
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout202 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout191_69),
.I2(Mmux_yout201),
.O(yout_9_OBUF_31)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout72 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout61),
.I2(Mmux_yout71),
.O(yout_13_OBUF_27)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout81 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout71),
.I2(Mmux_yout111_66),
.O(yout_14_OBUF_26)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout41 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout201),
.I2(Mmux_yout51),
.O(yout_10_OBUF_30)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout62 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout52),
.I2(Mmux_yout61),
.O(yout_12_OBUF_28)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout53 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout51),
.I2(Mmux_yout52),
.O(yout_11_OBUF_29)
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout1911 (
.I0(bin_1_IBUF_19),
.I1(\b<2>_mmx_out8 ),
.I2(bin_4_IBUF_16),
.I3(\b<2>_mmx_out9 ),
.I4(Mmux_yout1711),
.O(Mmux_yout191_69)
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout2011 (
.I0(bin_1_IBUF_19),
.I1(\b<2>_mmx_out10 ),
.I2(bin_4_IBUF_16),
.I3(\b<2>_mmx_out11 ),
.I4(Mmux_yout1811),
.O(Mmux_yout201)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout711 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out15 ),
.I3(\b<2>_mmx_out14 ),
.I4(Mmux_yout114_81),
.O(Mmux_yout71)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout611 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out13 ),
.I3(\b<2>_mmx_out12 ),
.I4(Mmux_yout1112),
.O(Mmux_yout61)
);
LUT3 #(
.INIT ( 8'h40 ))
Mmux_yout9111 (
.I0(rotate_IBUF_21),
.I1(ain_15_IBUF_15),
.I2(sra_IBUF_22),
.O(Mmux_yout911)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\b<2>311 (
.I0(b[2]),
.I1(b[3]),
.I2(ain_6_IBUF_12),
.I3(ain_14_IBUF_1),
.I4(ain_10_IBUF_9),
.I5(ain_2_IBUF_4),
.O(\b<2>_mmx_out )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout12211 (
.I0(b[3]),
.I1(bin_2_IBUF_18),
.I2(ain_1_IBUF_2),
.I3(ain_5_IBUF_10),
.I4(ain_13_IBUF_3),
.I5(ain_9_IBUF_11),
.O(Mmux_yout1221)
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout131 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout1224),
.I2(bin_1_IBUF_19),
.I3(Mmux_yout1311),
.I4(Mmux_yout121),
.O(yout_2_OBUF_38)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout142 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1311),
.I3(Mmux_yout1224),
.I4(Mmux_yout141),
.O(yout_3_OBUF_37)
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout151 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout1311),
.I2(bin_1_IBUF_19),
.I3(Mmux_yout1511),
.I4(Mmux_yout141),
.O(yout_4_OBUF_36)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout161 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1411),
.I3(Mmux_yout1611_80),
.I4(Mmux_yout1511),
.I5(Mmux_yout1311),
.O(yout_5_OBUF_35)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout171 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1511),
.I3(Mmux_yout1711),
.I4(Mmux_yout1611_80),
.I5(Mmux_yout1411),
.O(yout_6_OBUF_34)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout191 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1811),
.I3(Mmux_yout1611_80),
.I4(Mmux_yout191_69),
.O(yout_8_OBUF_32)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout181 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1611_80),
.I3(Mmux_yout1811),
.I4(Mmux_yout1711),
.I5(Mmux_yout1511),
.O(yout_7_OBUF_33)
);
LUT6 #(
.INIT ( 64'hFD5D5D5DA8080808 ))
\b<2>31 (
.I0(b[2]),
.I1(ain_4_IBUF_8),
.I2(b[3]),
.I3(ain_12_IBUF_5),
.I4(rotate_IBUF_21),
.I5(\b<3>_mmx_out11 ),
.O(\b<2>_mmx_out11 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\b<2>1511 (
.I0(b[2]),
.I1(b[3]),
.I2(ain_10_IBUF_9),
.I3(ain_2_IBUF_4),
.I4(ain_6_IBUF_12),
.I5(ain_14_IBUF_1),
.O(\b<2>151 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout511 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out12 ),
.I3(\b<2>_mmx_out13 ),
.I4(\b<2>_mmx_out9 ),
.I5(\b<2>_mmx_out8 ),
.O(Mmux_yout51)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout521 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out14 ),
.I3(\b<2>_mmx_out15 ),
.I4(\b<2>_mmx_out11 ),
.I5(\b<2>_mmx_out10 ),
.O(Mmux_yout52)
);
LUT5 #(
.INIT ( 32'hA8202020 ))
Mmux_yout31 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out ),
.I3(\b<2>151 ),
.I4(rotate_IBUF_21),
.O(Mmux_yout3)
);
LUT6 #(
.INIT ( 64'hFD5D5D5DA8080808 ))
Mmux_yout33 (
.I0(bin_2_IBUF_18),
.I1(\b<3>_mmx_out23 ),
.I2(bin_4_IBUF_16),
.I3(\b<2>111 ),
.I4(rotate_IBUF_21),
.I5(Mmux_yout31_93),
.O(Mmux_yout32_94)
);
LUT5 #(
.INIT ( 32'hEEFE4454 ))
Mmux_yout34 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout3),
.I2(Mmux_yout32_94),
.I3(bin_1_IBUF_19),
.I4(Mmux_yout122_68),
.O(yout_0_OBUF_40)
);
LUT6 #(
.INIT ( 64'hEFABABAB45010101 ))
Mmux_yout122 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(N2),
.I3(rotate_IBUF_21),
.I4(Mmux_yout1221),
.I5(Mmux_yout1224),
.O(Mmux_yout122_68)
);
LUT6 #(
.INIT ( 64'hA8AAA88820222000 ))
Mmux_yout1141 (
.I0(rotate_IBUF_21),
.I1(b[2]),
.I2(ain_8_IBUF_13),
.I3(b[3]),
.I4(ain_0_IBUF_0),
.I5(\b<3>_mmx_out23 ),
.O(Mmux_yout1141_96)
);
LUT4 #(
.INIT ( 16'hE444 ))
Mmux_yout1213 (
.I0(bin_4_IBUF_16),
.I1(\b<2>_mmx_out ),
.I2(\b<2>151 ),
.I3(rotate_IBUF_21),
.O(Mmux_yout1213_99)
);
LUT4 #(
.INIT ( 16'hFDA8 ))
Mmux_yout1214 (
.I0(bin_1_IBUF_19),
.I1(Mmux_yout1211_97),
.I2(Mmux_yout1212_98),
.I3(Mmux_yout1213_99),
.O(Mmux_yout121)
);
LUT4 #(
.INIT ( 16'hFE54 ))
Mmux_yout1413 (
.I0(bin_1_IBUF_19),
.I1(Mmux_yout1211_97),
.I2(Mmux_yout1212_98),
.I3(Mmux_yout1411),
.O(Mmux_yout141)
);
LUT6 #(
.INIT ( 64'hA8A0282088800800 ))
\b<2>21 (
.I0(rotate_IBUF_21),
.I1(b[2]),
.I2(b[3]),
.I3(ain_0_IBUF_0),
.I4(ain_8_IBUF_13),
.I5(ain_4_IBUF_8),
.O(\b<2>2 )
);
LUT6 #(
.INIT ( 64'hDDD55D5588800800 ))
Mmux_yout17112 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(b[2]),
.I3(ain_13_IBUF_3),
.I4(ain_9_IBUF_11),
.I5(Mmux_yout17111_101),
.O(Mmux_yout17112_102)
);
LUT2 #(
.INIT ( 4'h8 ))
\b<2>5_SW0 (
.I0(rotate_IBUF_21),
.I1(ain_13_IBUF_3),
.O(N4)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\b<2>5 (
.I0(b[3]),
.I1(b[2]),
.I2(ain_1_IBUF_2),
.I3(N4),
.I4(ain_5_IBUF_10),
.I5(ain_9_IBUF_11),
.O(\b<2>_mmx_out13 )
);
LUT6 #(
.INIT ( 64'hDDD55D5588800800 ))
Mmux_yout18112 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(b[2]),
.I3(ain_14_IBUF_1),
.I4(ain_10_IBUF_9),
.I5(Mmux_yout18111_104),
.O(Mmux_yout18112_105)
);
LUT6 #(
.INIT ( 64'hEFEA454045404540 ))
\b<2>29 (
.I0(b[3]),
.I1(ain_3_IBUF_6),
.I2(b[2]),
.I3(ain_7_IBUF_14),
.I4(N6),
.I5(rotate_IBUF_21),
.O(\b<2>_mmx_out9 )
);
LUT6 #(
.INIT ( 64'hFFF7DDD5AAA28880 ))
Mmux_yout115 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout112_108),
.I3(Mmux_yout113_109),
.I4(Mmux_yout114_81),
.I5(Mmux_yout111_66),
.O(yout_15_OBUF_25)
);
LUT2 #(
.INIT ( 4'h8 ))
\b<2>7_SW0 (
.I0(rotate_IBUF_21),
.I1(ain_14_IBUF_1),
.O(N8)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\b<2>7 (
.I0(b[3]),
.I1(b[2]),
.I2(ain_2_IBUF_4),
.I3(N8),
.I4(ain_6_IBUF_12),
.I5(ain_10_IBUF_9),
.O(\b<2>_mmx_out15 )
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout111 (
.I0(bin_1_IBUF_19),
.I1(N10),
.I2(bin_4_IBUF_16),
.I3(Mmux_yout1221),
.I4(Mmux_yout1112),
.O(Mmux_yout111_66)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout1611 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<3>_mmx_out24 ),
.I3(\b<3>_mmx_out22 ),
.I4(N12),
.O(Mmux_yout1611_80)
);
IBUF ain_15_IBUF (
.I(ain[15]),
.O(ain_15_IBUF_15)
);
IBUF ain_14_IBUF (
.I(ain[14]),
.O(ain_14_IBUF_1)
);
IBUF ain_13_IBUF (
.I(ain[13]),
.O(ain_13_IBUF_3)
);
IBUF ain_12_IBUF (
.I(ain[12]),
.O(ain_12_IBUF_5)
);
IBUF ain_11_IBUF (
.I(ain[11]),
.O(ain_11_IBUF_7)
);
IBUF ain_10_IBUF (
.I(ain[10]),
.O(ain_10_IBUF_9)
);
IBUF ain_9_IBUF (
.I(ain[9]),
.O(ain_9_IBUF_11)
);
IBUF ain_8_IBUF (
.I(ain[8]),
.O(ain_8_IBUF_13)
);
IBUF ain_7_IBUF (
.I(ain[7]),
.O(ain_7_IBUF_14)
);
IBUF ain_6_IBUF (
.I(ain[6]),
.O(ain_6_IBUF_12)
);
IBUF ain_5_IBUF (
.I(ain[5]),
.O(ain_5_IBUF_10)
);
IBUF ain_4_IBUF (
.I(ain[4]),
.O(ain_4_IBUF_8)
);
IBUF ain_3_IBUF (
.I(ain[3]),
.O(ain_3_IBUF_6)
);
IBUF ain_2_IBUF (
.I(ain[2]),
.O(ain_2_IBUF_4)
);
IBUF ain_1_IBUF (
.I(ain[1]),
.O(ain_1_IBUF_2)
);
IBUF ain_0_IBUF (
.I(ain[0]),
.O(ain_0_IBUF_0)
);
IBUF bin_4_IBUF (
.I(bin[4]),
.O(bin_4_IBUF_16)
);
IBUF bin_3_IBUF (
.I(bin[3]),
.O(bin_3_IBUF_17)
);
IBUF bin_2_IBUF (
.I(bin[2]),
.O(bin_2_IBUF_18)
);
IBUF bin_1_IBUF (
.I(bin[1]),
.O(bin_1_IBUF_19)
);
IBUF bin_0_IBUF (
.I(bin[0]),
.O(bin_0_IBUF_20)
);
IBUF rotate_IBUF (
.I(rotate),
.O(rotate_IBUF_21)
);
IBUF sra_IBUF (
.I(sra),
.O(sra_IBUF_22)
);
OBUF yout_15_OBUF (
.I(yout_15_OBUF_25),
.O(yout[15])
);
OBUF yout_14_OBUF (
.I(yout_14_OBUF_26),
.O(yout[14])
);
OBUF yout_13_OBUF (
.I(yout_13_OBUF_27),
.O(yout[13])
);
OBUF yout_12_OBUF (
.I(yout_12_OBUF_28),
.O(yout[12])
);
OBUF yout_11_OBUF (
.I(yout_11_OBUF_29),
.O(yout[11])
);
OBUF yout_10_OBUF (
.I(yout_10_OBUF_30),
.O(yout[10])
);
OBUF yout_9_OBUF (
.I(yout_9_OBUF_31),
.O(yout[9])
);
OBUF yout_8_OBUF (
.I(yout_8_OBUF_32),
.O(yout[8])
);
OBUF yout_7_OBUF (
.I(yout_7_OBUF_33),
.O(yout[7])
);
OBUF yout_6_OBUF (
.I(yout_6_OBUF_34),
.O(yout[6])
);
OBUF yout_5_OBUF (
.I(yout_5_OBUF_35),
.O(yout[5])
);
OBUF yout_4_OBUF (
.I(yout_4_OBUF_36),
.O(yout[4])
);
OBUF yout_3_OBUF (
.I(yout_3_OBUF_37),
.O(yout[3])
);
OBUF yout_2_OBUF (
.I(yout_2_OBUF_38),
.O(yout[2])
);
OBUF yout_1_OBUF (
.I(yout_1_OBUF_39),
.O(yout[1])
);
OBUF yout_0_OBUF (
.I(yout_0_OBUF_40),
.O(yout[0])
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>151 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_0_IBUF_0),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_8_IBUF_13),
.O(\b<3>_mmx_out22 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>181 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_1_IBUF_2),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_9_IBUF_11),
.O(\b<3>_mmx_out25 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>201 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_2_IBUF_4),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_10_IBUF_9),
.O(\b<3>_mmx_out27 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>221 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_3_IBUF_6),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_11_IBUF_7),
.O(\b<3>_mmx_out29 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>231 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_5_IBUF_10),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_13_IBUF_3),
.O(\b<3>_mmx_out3 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>251 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_6_IBUF_12),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_14_IBUF_1),
.O(\b<3>_mmx_out5 )
);
LUT6 #(
.INIT ( 64'hF7D5A280A280A280 ))
\b<3>41 (
.I0(rotate_IBUF_21),
.I1(b[3]),
.I2(ain_9_IBUF_11),
.I3(ain_1_IBUF_2),
.I4(ain_15_IBUF_15),
.I5(sra_IBUF_22),
.O(\b<3>_mmx_out12 )
);
LUT6 #(
.INIT ( 64'hF7D5A280A280A280 ))
\b<3>61 (
.I0(rotate_IBUF_21),
.I1(b[3]),
.I2(ain_10_IBUF_9),
.I3(ain_2_IBUF_4),
.I4(ain_15_IBUF_15),
.I5(sra_IBUF_22),
.O(\b<3>_mmx_out14 )
);
LUT5 #(
.INIT ( 32'hB391A280 ))
Mmux_yout14112 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_2_IBUF_4),
.I3(ain_14_IBUF_1),
.I4(ain_6_IBUF_12),
.O(Mmux_yout14112_87)
);
LUT6 #(
.INIT ( 64'hFED4D4D4BA909090 ))
Mmux_yout14113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(Mmux_yout14112_87),
.I3(rotate_IBUF_21),
.I4(Mmux_yout14111_86),
.I5(\b<3>_mmx_out27 ),
.O(Mmux_yout1411)
);
LUT5 #(
.INIT ( 32'hB391A280 ))
Mmux_yout13112 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_1_IBUF_2),
.I3(ain_13_IBUF_3),
.I4(ain_5_IBUF_10),
.O(Mmux_yout13112_89)
);
LUT6 #(
.INIT ( 64'hFED4D4D4BA909090 ))
Mmux_yout13113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(Mmux_yout13112_89),
.I3(rotate_IBUF_21),
.I4(Mmux_yout13111_88),
.I5(\b<3>_mmx_out25 ),
.O(Mmux_yout1311)
);
LUT5 #(
.INIT ( 32'hB391A280 ))
Mmux_yout15112 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_3_IBUF_6),
.I3(ain_15_IBUF_15),
.I4(ain_7_IBUF_14),
.O(Mmux_yout15112_91)
);
LUT6 #(
.INIT ( 64'hFED4D4D4BA909090 ))
Mmux_yout15113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(Mmux_yout15112_91),
.I3(rotate_IBUF_21),
.I4(Mmux_yout15111_90),
.I5(\b<3>_mmx_out29 ),
.O(Mmux_yout1511)
);
LUT6 #(
.INIT ( 64'h082A193B4C6E5D7F ))
Mmux_yout122_SW0 (
.I0(bin_2_IBUF_18),
.I1(b[3]),
.I2(ain_13_IBUF_3),
.I3(ain_5_IBUF_10),
.I4(ain_1_IBUF_2),
.I5(ain_9_IBUF_11),
.O(N2)
);
LUT6 #(
.INIT ( 64'hFD75FD75FD75A820 ))
Mmux_yout1142 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(\b<3>_mmx_out11 ),
.I3(\b<2>111 ),
.I4(Mmux_yout911),
.I5(Mmux_yout1141_96),
.O(Mmux_yout114_81)
);
LUT5 #(
.INIT ( 32'h62224000 ))
Mmux_yout1211 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<2>111 ),
.I3(rotate_IBUF_21),
.I4(\b<3>_mmx_out22 ),
.O(Mmux_yout1211_97)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout17113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(\b<3>_mmx_out3 ),
.I3(\b<3>_mmx_out25 ),
.I4(Mmux_yout17112_102),
.O(Mmux_yout1711)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout18113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(\b<3>_mmx_out5 ),
.I3(\b<3>_mmx_out27 ),
.I4(Mmux_yout18112_105),
.O(Mmux_yout1811)
);
LUT6 #(
.INIT ( 64'hAAA00A0088800800 ))
Mmux_yout112 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(bin_3_IBUF_17),
.I3(ain_6_IBUF_12),
.I4(ain_14_IBUF_1),
.I5(rotate_IBUF_21),
.O(Mmux_yout11)
);
LUT6 #(
.INIT ( 64'h5551151144400400 ))
Mmux_yout114 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(bin_3_IBUF_17),
.I3(ain_2_IBUF_4),
.I4(ain_10_IBUF_9),
.I5(\b<3>_mmx_out14 ),
.O(Mmux_yout113_109)
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
Mmux_yout111_SW0 (
.I0(bin_2_IBUF_18),
.I1(rotate_IBUF_21),
.I2(Mmux_yout1222),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(\b<3>_mmx_out12 ),
.O(N10)
);
LUT6 #(
.INIT ( 64'hDF8FDD858A8A8880 ))
Mmux_yout1611_SW0 (
.I0(bin_3_IBUF_17),
.I1(ain_4_IBUF_8),
.I2(bin_4_IBUF_16),
.I3(rotate_IBUF_21),
.I4(Mmux_yout911),
.I5(ain_12_IBUF_5),
.O(N12)
);
LUT5 #(
.INIT ( 32'hF6909090 ))
\b<3>171 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_0_IBUF_0),
.I3(rotate_IBUF_21),
.I4(ain_8_IBUF_13),
.O(\b<3>_mmx_out24 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<3>161 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_4_IBUF_8),
.I3(ain_12_IBUF_5),
.O(\b<3>_mmx_out23 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>281 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<3>_mmx_out29 ),
.I3(\b<3>_mmx_out7 ),
.O(\b<2>_mmx_out8 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>61 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<3>_mmx_out5 ),
.I3(\b<3>_mmx_out14 ),
.O(\b<2>_mmx_out14 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>41 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<3>_mmx_out3 ),
.I3(\b<3>_mmx_out12 ),
.O(\b<2>_mmx_out12 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>1111 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_12_IBUF_5),
.I3(ain_4_IBUF_8),
.O(\b<2>111 )
);
LUT6 #(
.INIT ( 64'hFFF7DDD5AAA28880 ))
Mmux_yout123 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1211_97),
.I3(Mmux_yout1212_98),
.I4(Mmux_yout1213_99),
.I5(Mmux_yout122_68),
.O(yout_1_OBUF_39)
);
LUT6 #(
.INIT ( 64'hBEAABE8282AA8282 ))
\b<3>271 (
.I0(ain_15_IBUF_15),
.I1(bin_3_IBUF_17),
.I2(bin_4_IBUF_16),
.I3(rotate_IBUF_21),
.I4(sra_IBUF_22),
.I5(ain_7_IBUF_14),
.O(\b<3>_mmx_out7 )
);
LUT4 #(
.INIT ( 16'hF690 ))
Mmux_yout17111 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(ain_5_IBUF_10),
.I3(ain_1_IBUF_2),
.O(Mmux_yout17111_101)
);
LUT4 #(
.INIT ( 16'hF690 ))
Mmux_yout18111 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(ain_6_IBUF_12),
.I3(ain_2_IBUF_4),
.O(Mmux_yout18111_104)
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>29_SW0 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(ain_15_IBUF_15),
.I3(ain_11_IBUF_7),
.O(N6)
);
LUT5 #(
.INIT ( 32'hE0EE2022 ))
Mmux_yout32 (
.I0(ain_0_IBUF_0),
.I1(bin_3_IBUF_17),
.I2(rotate_IBUF_21),
.I3(bin_4_IBUF_16),
.I4(ain_8_IBUF_13),
.O(Mmux_yout31_93)
);
LUT6 #(
.INIT ( 64'h9989988811011000 ))
Mmux_yout1212 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(bin_3_IBUF_17),
.I3(ain_12_IBUF_5),
.I4(ain_4_IBUF_8),
.I5(\b<3>_mmx_out24 ),
.O(Mmux_yout1212_98)
);
LUT6 #(
.INIT ( 64'h7E5A3C1866422400 ))
Mmux_yout14111 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(bin_2_IBUF_18),
.I3(ain_6_IBUF_12),
.I4(ain_10_IBUF_9),
.I5(ain_14_IBUF_1),
.O(Mmux_yout14111_86)
);
LUT6 #(
.INIT ( 64'h7E5A3C1866422400 ))
Mmux_yout13111 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(bin_2_IBUF_18),
.I3(ain_5_IBUF_10),
.I4(ain_9_IBUF_11),
.I5(ain_13_IBUF_3),
.O(Mmux_yout13111_88)
);
LUT6 #(
.INIT ( 64'h7E5A3C1866422400 ))
Mmux_yout15111 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(bin_2_IBUF_18),
.I3(ain_7_IBUF_14),
.I4(ain_11_IBUF_7),
.I5(ain_15_IBUF_15),
.O(Mmux_yout15111_90)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFEAAB2AA8 ))
\b<2>22 (
.I0(Mmux_yout911),
.I1(bin_2_IBUF_18),
.I2(bin_4_IBUF_16),
.I3(bin_3_IBUF_17),
.I4(ain_12_IBUF_5),
.I5(\b<2>2 ),
.O(\b<2>_mmx_out10 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<3>31 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_8_IBUF_13),
.I3(ain_0_IBUF_0),
.O(\b<3>_mmx_out11 )
);
LUT4 #(
.INIT ( 16'hF690 ))
Mmux_yout12221 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_5_IBUF_10),
.I3(ain_13_IBUF_3),
.O(Mmux_yout1222)
);
LUT6 #(
.INIT ( 64'hAABAAAAAAAAAAAAA ))
Mmux_yout113 (
.I0(Mmux_yout11),
.I1(bin_4_IBUF_16),
.I2(bin_2_IBUF_18),
.I3(rotate_IBUF_21),
.I4(ain_15_IBUF_15),
.I5(sra_IBUF_22),
.O(Mmux_yout112_108)
);
MUXF7 Mmux_yout12243 (
.I0(N14),
.I1(N15),
.S(bin_2_IBUF_18),
.O(Mmux_yout1224)
);
LUT5 #(
.INIT ( 32'hBE0E8202 ))
Mmux_yout12243_F (
.I0(ain_3_IBUF_6),
.I1(b[3]),
.I2(bin_4_IBUF_16),
.I3(rotate_IBUF_21),
.I4(ain_11_IBUF_7),
.O(N14)
);
LUT5 #(
.INIT ( 32'hBE0E8202 ))
Mmux_yout12243_G (
.I0(ain_7_IBUF_14),
.I1(b[3]),
.I2(bin_4_IBUF_16),
.I3(rotate_IBUF_21),
.I4(ain_15_IBUF_15),
.O(N15)
);
MUXF7 Mmux_yout11123 (
.I0(N16),
.I1(N17),
.S(bin_2_IBUF_18),
.O(Mmux_yout1112)
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
Mmux_yout11123_F (
.I0(bin_4_IBUF_16),
.I1(bin_3_IBUF_17),
.I2(ain_7_IBUF_14),
.I3(ain_15_IBUF_15),
.I4(rotate_IBUF_21),
.I5(\b<3>_mmx_out7 ),
.O(N16)
);
LUT6 #(
.INIT ( 64'hFD75FD75FC30A820 ))
Mmux_yout11123_G (
.I0(bin_4_IBUF_16),
.I1(bin_3_IBUF_17),
.I2(ain_3_IBUF_6),
.I3(ain_11_IBUF_7),
.I4(rotate_IBUF_21),
.I5(Mmux_yout911),
.O(N17)
);
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule |
module PeakCurrentHB(clk, cmp, DT, MaxCount, High, Low);
//Inputs and outputs
input clk, cmp;
input [7:0] DT, MaxCount;
output reg High, Low;
//Internal variables
reg [7:0] Counter = 0;
reg [7:0] DTCount = 0;
reg [7:0] MaxDuty = 0;
reg Flag;
//Wires
wire [7:0] Counter_Next, DTCount_Next, MaxDuty_Next;
wire High_Next, Low_Next, Flag_Next;
//For simulation purposes only
initial begin
High = 0;
Low = 1;
end
//Sequential Code
always @ (posedge(clk))
begin
Counter <= Counter_Next;
High <= High_Next;
Low <= Low_Next;
Flag <= Flag_Next;
MaxDuty <= MaxDuty_Next;
end
//Clock the dead time counter on the flag edge
always @ (negedge(High))
begin
DTCount <= DTCount_Next;
end
//Combinatorial Code
assign Flag_Next = (Counter == 8'b00000000)?0:(cmp || Flag);
assign Counter_Next = (Counter < MaxCount)?(Counter+1):0;
assign High_Next = (Counter >= DT) && (!Flag) && (Counter < MaxDuty);
assign Low_Next = ((Flag) && (Counter > DTCount)) || ((!High) && (Counter > MaxDuty) && (Counter >= DTCount));
assign DTCount_Next = Counter + DT;
assign MaxDuty_Next = (MaxCount >> 1) - 1;
endmodule |
module mux2to1(datain0,datain1, dataout, select);
input [31:0] datain0, datain1;
input select;
output [31:0] dataout;
*/
initial
forever #50 clock = ~clock;
initial
begin
four = 4;
yesItAlwaysTure = 1;
yesItAlwyasFalse = 0;
clock = 0;
clear = 1;
/* we may not connect clear to register file and memory because we don't want our initial data get cleared*/
#10 clear = 0;
end
initial
#10000 $stop;
endmodule |
module system_ov7670_controller_0_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
wire xclk;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_0_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod),
.xclk(xclk));
VCC VCC
(.P(\<const1> ));
endmodule |
module system_ov7670_controller_0_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule |
module system_ov7670_controller_0_0_ov7670_controller
(config_finished,
siod,
xclk,
sioc,
resend,
clk);
output config_finished;
output siod;
output xclk;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire sys_clk_i_1_n_0;
wire taken;
wire xclk;
system_ov7670_controller_0_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_0_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
LUT1 #(
.INIT(2'h1))
sys_clk_i_1
(.I0(xclk),
.O(sys_clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
sys_clk_reg
(.C(clk),
.CE(1'b1),
.D(sys_clk_i_1_n_0),
.Q(xclk),
.R(1'b0));
endmodule |
module system_ov7670_controller_0_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module/*{{{*/
FIFO F0 (
.m_aclk(m_aclk), // input m_aclk
.s_aclk(s_aclk), // input s_aclk
.s_aresetn(s_aresetn), // input s_aresetn
.s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid
.s_axis_tready(s_axis_tready), // output s_axis_tready
.s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata
.s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep
.s_axis_tlast(s_axis_tlast), // input s_axis_tlast
.m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid
.m_axis_tready(m_axis_tready), // input m_axis_tready
.m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata
.m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep
.m_axis_tlast(m_axis_tlast), // output m_axis_tlast
.axis_overflow(axis_overflow), // output axis_overflow
.axis_underflow(axis_underflow) // output axis_underflow
);
/*}}}*/
// This is to ensure we simulate our reads from the slave end of the FIFO only
// when there is valid data to be read from the queue to avoid underflows.
always @(m_axis_tvalid) begin
m_axis_tready <= m_axis_tvalid;
end
// Testbench initialization/*{{{*/
initial begin
s_aclk <= 1'b0;
m_aclk <= 1'b0;
s_aresetn <= 1'b0;
s_axis_tvalid <= 1'b0;
m_axis_tready <= 1'b0;
s_axis_tdata <= 64'b0;
s_axis_tkeep <= 8'b0;
s_axis_tlast <= 1'b0;
end
/*}}}*/
// Master domain clock
initial begin
forever begin
#10 s_aclk <= ~s_aclk;
end
end
// Slave domain clock
initial begin
forever begin
#5 m_aclk <= ~m_aclk;
end
end
// Test bench stimuli/*{{{*/
initial begin
#10 s_aresetn <= 1'b1; // Slave will be ready 3 s_aclk ticks after reset
// Test writing a single data slice to the slave specifying valid bytes with tkeep
#60 s_axis_tvalid <= 1'b1; // Wait until slave is ready to avoid overflow
s_axis_tdata <= 64'hFFFFFFFFFFFFFFFF;
s_axis_tkeep <= 8'hCF;
s_axis_tlast <= 1'b1;
#20 s_axis_tvalid <= 1'b0; // Keep the valid signal asserted for at least 1 clock
s_axis_tdata <= 64'b0;
s_axis_tkeep <= 8'b0;
s_axis_tlast <= 1'b0;
// Test writing multiple data slices to the slave specifying valid bytes with tkeep and last slice with tlast
#20 s_axis_tvalid <= 1'b1; // Wait until slave is ready to avoid overflow
s_axis_tdata <= 64'h1111111111111111;
s_axis_tkeep <= 8'hFF;
#20 s_axis_tdata <= 64'h2222222222222222;
s_axis_tkeep <= 8'hFF;
#20 s_axis_tdata <= 64'h3333333333333333;
s_axis_tkeep <= 8'hFF;
#20 s_axis_tdata <= 64'h4444444444444444;
s_axis_tkeep <= 8'hFF;
s_axis_tlast <= 1'b1;
#20 s_axis_tvalid <= 1'b0;
s_axis_tdata <= 64'b0;
s_axis_tkeep <= 8'b0;
s_axis_tlast <= 1'b0;
end
/*}}}*/
endmodule |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @ (clk) begin
if ($time % 6 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 15 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule |
module main #(
parameter v771499 = "v771499.list"
) (
input vclk,
output [3:0] v894180,
output [0:0] vinit
);
localparam p0 = v771499;
wire [0:7] w1;
wire [0:3] w2;
wire [0:7] w3;
wire w4;
assign v894180 = w2;
assign w4 = vclk;
v6809d2 #(
.v9298ae(p0)
) v60d27e (
.v6d8c97(w1),
.vc4e0ba(w3),
.v6dda25(w4)
);
vda0861 vf2b781 (
.vffb58f(w1)
);
v6bdcd9 v78e5a8 (
.v2cc41f(w2),
.vcc8c7c(w3)
);
assign vinit = 1'b0;
endmodule |
module v6809d2 #(
parameter v9298ae = "v9298ae.list"
) (
input v6dda25,
input [7:0] v6d8c97,
output [7:0] vc4e0ba
);
localparam p3 = v9298ae;
wire w0;
wire w1;
wire w2;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:7] w8;
wire [0:7] w9;
wire w10;
wire [0:31] w11;
wire [0:31] w12;
wire [0:31] w13;
wire [0:31] w14;
wire [0:31] w15;
wire [0:3] w16;
wire w17;
wire w18;
wire w19;
assign w4 = v6dda25;
assign w5 = v6dda25;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign vc4e0ba = w8;
assign w9 = v6d8c97;
assign w1 = w0;
assign w5 = w4;
assign w6 = w4;
assign w6 = w5;
assign w7 = w4;
assign w7 = w5;
assign w7 = w6;
assign w12 = w11;
vf1cffe v468719 (
.ve9ba68(w0),
.v79476f(w1),
.v6dda25(w4),
.v27dec4(w10),
.v9231ba(w11),
.vfc9252(w13),
.va0e119(w14),
.ve17e80(w16)
);
vd30ca9 v16f275 (
.v9fb85f(w0)
);
v893ac6 #(
.vba98fe(p3)
) vc59f55 (
.v6dda25(w5),
.v5d7e06(w11),
.v9a5b8a(w15)
);
ve4c3a8 v29c9ed (
.v5c832d(w12),
.v4642b6(w17),
.vd02149(w18),
.vafdfa0(w19)
);
vf68661 v66eb94 (
.v6dda25(w7),
.vfeb41a(w8),
.vf837fe(w13),
.ve9e5a1(w16),
.ve146f6(w19)
);
v145d1e v3f3e01 (
.vc74a9c(w9),
.vb76294(w14),
.vb79ed5(w15),
.v6287a6(w17),
.v19f646(w18)
);
v04e061 vb15d38 (
.v4642b6(w2),
.vd6bebe(w6)
);
v3676a0 vd1c5e9 (
.v0e28cb(w2),
.vcbab45(w10)
);
endmodule |
module vf1cffe (
input v6dda25,
input v27dec4,
input [31:0] va0e119,
input v79476f,
input ve9ba68,
output [31:0] v9231ba,
output [31:0] vfc9252,
output [3:0] ve17e80,
output v8d2eee
);
wire w0;
wire [0:31] w1;
wire w2;
wire w3;
wire [0:31] w4;
wire [0:31] w5;
wire [0:3] w6;
wire w7;
wire w8;
assign w0 = v27dec4;
assign w1 = va0e119;
assign w2 = v79476f;
assign w3 = ve9ba68;
assign v9231ba = w4;
assign vfc9252 = w5;
assign ve17e80 = w6;
assign v8d2eee = w7;
assign w8 = v6dda25;
vf1cffe_v172245 v172245 (
.reset(w0),
.mem_rdata(w1),
.mem_rbusy(w2),
.mem_wbusy(w3),
.mem_addr(w4),
.mem_wdata(w5),
.mem_wmask(w6),
.mem_rstrb(w7),
.clk(w8)
);
endmodule |
module vf1cffe_v172245 (
input clk,
input reset,
input [31:0] mem_rdata,
input mem_rbusy,
input mem_wbusy,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [3:0] mem_wmask,
output mem_rstrb
);
localparam RESET_ADDR = 0;
parameter ADDR_WIDTH = 24;
localparam ADDR_PAD = {(32-ADDR_WIDTH){1'b0}}; // 32-bits padding for addrs
/***************************************************************************/
// Instruction decoding.
/***************************************************************************/
// Extracts rd,rs1,rs2,funct3,imm and opcode from instruction.
// Reference: Table page 104 of:
// https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
// The destination register
wire [4:0] rdId = instr[11:7];
// The ALU function, decoded in 1-hot form (doing so reduces LUT count)
// It is used as follows: funct3Is[val] <=> funct3 == val
(* onehot *)
wire [7:0] funct3Is = 8'b00000001 << instr[14:12];
// The five immediate formats, see RiscV reference (link above), Fig. 2.4 p. 12
wire [31:0] Uimm = { instr[31], instr[30:12], {12{1'b0}}};
wire [31:0] Iimm = {{21{instr[31]}}, instr[30:20]};
/* verilator lint_off UNUSED */ // MSBs of SBJimms are not used by addr adder.
wire [31:0] Simm = {{21{instr[31]}}, instr[30:25],instr[11:7]};
wire [31:0] Bimm = {{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0};
wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0};
/* verilator lint_on UNUSED */
// Base RISC-V (RV32I) has only 10 different instructions !
wire isLoad = (instr[6:2] == 5'b00000); // rd <- mem[rs1+Iimm]
wire isALUimm = (instr[6:2] == 5'b00100); // rd <- rs1 OP Iimm
wire isAUIPC = (instr[6:2] == 5'b00101); // rd <- PC + Uimm
wire isStore = (instr[6:2] == 5'b01000); // mem[rs1+Simm] <- rs2
wire isALUreg = (instr[6:2] == 5'b01100); // rd <- rs1 OP rs2
wire isLUI = (instr[6:2] == 5'b01101); // rd <- Uimm
wire isBranch = (instr[6:2] == 5'b11000); // if(rs1 OP rs2) PC<-PC+Bimm
wire isJALR = (instr[6:2] == 5'b11001); // rd <- PC+4; PC<-rs1+Iimm
wire isJAL = (instr[6:2] == 5'b11011); // rd <- PC+4; PC<-PC+Jimm
wire isSYSTEM = (instr[6:2] == 5'b11100); // rd <- cycles
wire isALU = isALUimm | isALUreg;
/***************************************************************************/
// The register file.
/***************************************************************************/
reg [31:0] rs1;
reg [31:0] rs2;
reg [31:0] registerFile [31:0];
always @(posedge clk) begin
if (writeBack)
if (rdId != 0)
registerFile[rdId] <= writeBackData;
end
/***************************************************************************/
// The ALU. Does operations and tests combinatorially, except shifts.
/***************************************************************************/
// First ALU source, always rs1
wire [31:0] aluIn1 = rs1;
// Second ALU source, depends on opcode:
// ALUreg, Branch: rs2
// ALUimm, Load, JALR: Iimm
wire [31:0] aluIn2 = isALUreg | isBranch ? rs2 : Iimm;
reg [31:0] aluReg; // The internal register of the ALU, used by shift.
reg [4:0] aluShamt; // Current shift amount.
wire aluBusy = |aluShamt; // ALU is busy if shift amount is non-zero.
wire aluWr; // ALU write strobe, starts shifting.
// The adder is used by both arithmetic instructions and JALR.
wire [31:0] aluPlus = aluIn1 + aluIn2;
// Use a single 33 bits subtract to do subtraction and all comparisons
// (trick borrowed from swapforth/J1)
wire [32:0] aluMinus = {1'b1, ~aluIn2} + {1'b0,aluIn1} + 33'b1;
wire LT = (aluIn1[31] ^ aluIn2[31]) ? aluIn1[31] : aluMinus[32];
wire LTU = aluMinus[32];
wire EQ = (aluMinus[31:0] == 0);
// Notes:
// - instr[30] is 1 for SUB and 0 for ADD
// - for SUB, need to test also instr[5] to discriminate ADDI:
// (1 for ADD/SUB, 0 for ADDI, and Iimm used by ADDI overlaps bit 30 !)
// - instr[30] is 1 for SRA (do sign extension) and 0 for SRL
wire [31:0] aluOut =
(funct3Is[0] ? instr[30] & instr[5] ? aluMinus[31:0] : aluPlus : 32'b0) |
(funct3Is[2] ? {31'b0, LT} : 32'b0) |
(funct3Is[3] ? {31'b0, LTU} : 32'b0) |
(funct3Is[4] ? aluIn1 ^ aluIn2 : 32'b0) |
(funct3Is[6] ? aluIn1 | aluIn2 : 32'b0) |
(funct3Is[7] ? aluIn1 & aluIn2 : 32'b0) |
(funct3IsShift ? aluReg : 32'b0) ;
wire funct3IsShift = funct3Is[1] | funct3Is[5];
always @(posedge clk) begin
if(aluWr) begin
if (funct3IsShift) begin // SLL, SRA, SRL
aluReg <= aluIn1;
aluShamt <= aluIn2[4:0];
end
end
// Compact form of:
// funct3=001 -> SLL (aluReg <= aluReg << 1)
// funct3=101 & instr[30] -> SRA (aluReg <= {aluReg[31], aluReg[31:1]})
// funct3=101 & !instr[30] -> SRL (aluReg <= {1'b0, aluReg[31:1]})
if (|aluShamt) begin
aluShamt <= aluShamt - 1;
aluReg <= funct3Is[1] ? aluReg << 1 : // SLL
{instr[30] & aluReg[31], aluReg[31:1]}; // SRA,SRL
end
end
/***************************************************************************/
// The predicate for conditional branches.
/***************************************************************************/
wire predicate =
funct3Is[0] & EQ | // BEQ
funct3Is[1] & !EQ | // BNE
funct3Is[4] & LT | // BLT
funct3Is[5] & !LT | // BGE
funct3Is[6] & LTU | // BLTU
funct3Is[7] & !LTU ; // BGEU
/***************************************************************************/
// Program counter and branch target computation.
/***************************************************************************/
reg [ADDR_WIDTH-1:0] PC; // The program counter.
reg [31:2] instr; // Latched instruction. Note that bits 0 and 1 are
// ignored (not used in RV32I base instr set).
wire [ADDR_WIDTH-1:0] PCplus4 = PC + 4;
// An adder used to compute branch address, JAL address and AUIPC.
// branch->PC+Bimm AUIPC->PC+Uimm JAL->PC+Jimm
// Equivalent to PCplusImm = PC + (isJAL ? Jimm : isAUIPC ? Uimm : Bimm)
wire [ADDR_WIDTH-1:0] PCplusImm = PC + ( instr[3] ? Jimm[ADDR_WIDTH-1:0] :
instr[4] ? Uimm[ADDR_WIDTH-1:0] :
Bimm[ADDR_WIDTH-1:0] );
// A separate adder to compute the destination of load/store.
// testing instr[5] is equivalent to testing isStore in this context.
wire [ADDR_WIDTH-1:0] loadstore_addr = rs1[ADDR_WIDTH-1:0] +
(instr[5] ? Simm[ADDR_WIDTH-1:0] : Iimm[ADDR_WIDTH-1:0]);
assign mem_addr = {ADDR_PAD,
state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ?
PC : loadstore_addr
};
/***************************************************************************/
// The value written back to the register file.
/***************************************************************************/
wire [31:0] writeBackData =
/* verilator lint_off WIDTH */
(isSYSTEM ? cycles : 32'b0) | // SYSTEM
/* verilator lint_on WIDTH */
(isLUI ? Uimm : 32'b0) | // LUI
(isALU ? aluOut : 32'b0) | // ALUreg, ALUimm
(isAUIPC ? {ADDR_PAD,PCplusImm} : 32'b0) | // AUIPC
(isJALR | isJAL ? {ADDR_PAD,PCplus4 } : 32'b0) | // JAL, JALR
(isLoad ? LOAD_data : 32'b0); // Load
/***************************************************************************/
// LOAD/STORE
/***************************************************************************/
// All memory accesses are aligned on 32 bits boundary. For this
// reason, we need some circuitry that does unaligned halfword
// and byte load/store, based on:
// - funct3[1:0]: 00->byte 01->halfword 10->word
// - mem_addr[1:0]: indicates which byte/halfword is accessed
wire mem_byteAccess = instr[13:12] == 2'b00; // funct3[1:0] == 2'b00;
wire mem_halfwordAccess = instr[13:12] == 2'b01; // funct3[1:0] == 2'b01;
// LOAD, in addition to funct3[1:0], LOAD depends on:
// - funct3[2] (instr[14]): 0->do sign expansion 1->no sign expansion
wire LOAD_sign =
!instr[14] & (mem_byteAccess ? LOAD_byte[7] : LOAD_halfword[15]);
wire [31:0] LOAD_data =
mem_byteAccess ? {{24{LOAD_sign}}, LOAD_byte} :
mem_halfwordAccess ? {{16{LOAD_sign}}, LOAD_halfword} :
mem_rdata ;
wire [15:0] LOAD_halfword =
loadstore_addr[1] ? mem_rdata[31:16] : mem_rdata[15:0];
wire [7:0] LOAD_byte =
loadstore_addr[0] ? LOAD_halfword[15:8] : LOAD_halfword[7:0];
// STORE
assign mem_wdata[ 7: 0] = rs2[7:0];
assign mem_wdata[15: 8] = loadstore_addr[0] ? rs2[7:0] : rs2[15: 8];
assign mem_wdata[23:16] = loadstore_addr[1] ? rs2[7:0] : rs2[23:16];
assign mem_wdata[31:24] = loadstore_addr[0] ? rs2[7:0] :
loadstore_addr[1] ? rs2[15:8] : rs2[31:24];
// The memory write mask:
// 1111 if writing a word
// 0011 or 1100 if writing a halfword
// (depending on loadstore_addr[1])
// 0001, 0010, 0100 or 1000 if writing a byte
// (depending on loadstore_addr[1:0])
wire [3:0] STORE_wmask =
mem_byteAccess ?
(loadstore_addr[1] ?
(loadstore_addr[0] ? 4'b1000 : 4'b0100) :
(loadstore_addr[0] ? 4'b0010 : 4'b0001)
) :
mem_halfwordAccess ?
(loadstore_addr[1] ? 4'b1100 : 4'b0011) :
4'b1111;
/*************************************************************************/
// And, last but not least, the state machine.
/*************************************************************************/
localparam FETCH_INSTR_bit = 0;
localparam WAIT_INSTR_bit = 1;
localparam EXECUTE_bit = 2;
localparam WAIT_ALU_OR_MEM_bit = 3;
localparam NB_STATES = 4;
localparam FETCH_INSTR = 1 << FETCH_INSTR_bit;
localparam WAIT_INSTR = 1 << WAIT_INSTR_bit;
localparam EXECUTE = 1 << EXECUTE_bit;
localparam WAIT_ALU_OR_MEM = 1 << WAIT_ALU_OR_MEM_bit;
(* onehot *)
reg [NB_STATES-1:0] state;
// The signals (internal and external) that are determined
// combinatorially from state and other signals.
// register write-back enable.
wire writeBack = ~(isBranch | isStore ) &
(state[EXECUTE_bit] | state[WAIT_ALU_OR_MEM_bit]);
// The memory-read signal.
assign mem_rstrb = state[EXECUTE_bit] & isLoad | state[FETCH_INSTR_bit];
// The mask for memory-write.
assign mem_wmask = {4{state[EXECUTE_bit] & isStore}} & STORE_wmask;
// aluWr starts computation (shifts) in the ALU.
assign aluWr = state[EXECUTE_bit] & isALU;
wire jumpToPCplusImm = isJAL | (isBranch & predicate);
`ifdef NRV_IS_IO_ADDR
wire needToWait = isLoad |
isStore & `NRV_IS_IO_ADDR(mem_addr) |
isALU & funct3IsShift;
`else
wire needToWait = isLoad | isStore | isALU & funct3IsShift;
`endif
always @(posedge clk) begin
if(!reset) begin
state <= WAIT_ALU_OR_MEM; // Just waiting for !mem_wbusy
PC <= RESET_ADDR[ADDR_WIDTH-1:0];
end else
// See note [1] at the end of this file.
(* parallel_case *)
case(1'b1)
state[WAIT_INSTR_bit]: begin
if(!mem_rbusy) begin // may be high when executing from SPI flash
rs1 <= registerFile[mem_rdata[19:15]];
rs2 <= registerFile[mem_rdata[24:20]];
instr <= mem_rdata[31:2]; // Bits 0 and 1 are ignored (see
state <= EXECUTE; // also the declaration of instr).
end
end
state[EXECUTE_bit]: begin
PC <= isJALR ? {aluPlus[ADDR_WIDTH-1:1],1'b0} :
jumpToPCplusImm ? PCplusImm :
PCplus4;
state <= needToWait ? WAIT_ALU_OR_MEM : FETCH_INSTR;
end
state[WAIT_ALU_OR_MEM_bit]: begin
if(!aluBusy & !mem_rbusy & !mem_wbusy) state <= FETCH_INSTR;
end
default: begin // FETCH_INSTR
state <= WAIT_INSTR;
end
endcase
end
/***************************************************************************/
// Cycle counter
/***************************************************************************/
`ifdef NRV_COUNTER_WIDTH
reg [`NRV_COUNTER_WIDTH-1:0] cycles;
`else
reg [31:0] cycles;
`endif
always @(posedge clk) cycles <= cycles + 1;
`ifdef BENCH
initial begin
cycles = 0;
aluShamt = 0;
registerFile[0] = 0;
end
`endif
/*****************************************************************************/
// Notes:
//
// [1] About the "reverse case" statement, also used in Claire Wolf's picorv32:
// It is just a cleaner way of writing a series of cascaded if() statements,
// To understand it, think about the case statement *in general* as follows:
// case (expr)
// val_1: statement_1
// val_2: statement_2
// ... val_n: statement_n
// endcase
// The first statement_i such that expr == val_i is executed.
// Now if expr is 1'b1:
// case (1'b1)
// cond_1: statement_1
// cond_2: statement_2
// ... cond_n: statement_n
// endcase
// It is *exactly the same thing*, the first statement_i such that
// expr == cond_i is executed (that is, such that 1'b1 == cond_i,
// in other words, such that cond_i is true)
// More on this:
// https://stackoverflow.com/questions/15418636/case-statement-in-verilog
//
// [2] state uses 1-hot encoding (at any time, state has only one bit set to 1).
// It uses a larger number of bits (one bit per state), but often results in
// a both more compact (fewer LUTs) and faster state machine.
endmodule |
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule |
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule |
module v893ac6 #(
parameter vba98fe = "vba98fe.list"
) (
input v6dda25,
input [31:0] v5d7e06,
output [31:0] v9a5b8a
);
localparam p6 = vba98fe;
wire w0;
wire [0:31] w1;
wire w2;
wire [0:31] w3;
wire [0:9] w4;
wire [0:31] w5;
wire w7;
wire [0:31] w8;
wire [0:31] w9;
assign w7 = v6dda25;
assign v9a5b8a = w8;
assign w9 = v5d7e06;
vd30ca9 vc98086 (
.v9fb85f(w0)
);
vd30ca9 v30628d (
.v9fb85f(w2)
);
v2c97f6 v773b48 (
.v7c9bd8(w3)
);
v675d07 #(
.v5a4ee6(p6)
) vdbacf7 (
.v23dc54(w2),
.v6f4b70(w3),
.vb261ad(w4),
.v922e3d(w7),
.vddff9f(w8)
);
v794b6d va8ea8d (
.vef1612(w4),
.ve841af(w5)
);
vaaf5c4 ve8e400 (
.v712289(w0),
.v51eedb(w1),
.v4f6beb(w9)
);
vaaf5c4 v677471 (
.v4f6beb(w1),
.v51eedb(w5)
);
endmodule |
module v2c97f6 #(
parameter vfffc23 = 0
) (
output [31:0] v7c9bd8
);
localparam p0 = vfffc23;
wire [0:31] w1;
assign v7c9bd8 = w1;
v959751 #(
.vc5c8ea(p0)
) v9f49e7 (
.vbc97e4(w1)
);
endmodule |
module v959751 #(
parameter vc5c8ea = 0
) (
output [31:0] vbc97e4
);
localparam p0 = vc5c8ea;
wire [0:31] w1;
assign vbc97e4 = w1;
v959751_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule |
module v959751_v465065 #(
parameter VALUE = 0
) (
output [31:0] k
);
assign k = VALUE;
endmodule |
module v675d07 #(
parameter v5a4ee6 = "v5a4ee6.list"
) (
input v922e3d,
input [9:0] vb261ad,
input [31:0] v6f4b70,
input v23dc54,
output [31:0] vddff9f
);
localparam p2 = v5a4ee6;
wire w0;
wire w1;
wire [0:9] w3;
wire [0:31] w4;
wire [0:31] w5;
assign w0 = v922e3d;
assign w1 = v23dc54;
assign w3 = vb261ad;
assign vddff9f = w4;
assign w5 = v6f4b70;
v675d07_vbaa912 #(
.ROMF(p2)
) vbaa912 (
.clk(w0),
.wr(w1),
.addr(w3),
.data_out(w4),
.data_in(w5)
);
endmodule |
module v675d07_vbaa912 #(
parameter ROMF = 0
) (
input clk,
input [9:0] addr,
input [31:0] data_in,
input wr,
output [31:0] data_out
);
//-- Address with
localparam ADDR_WIDTH = 10;
//-- Data with
localparam DATA_WIDTH = 32;
//-- Size of the memory
localparam SIZE = 1 << ADDR_WIDTH;
//-- Memory itself
reg [DATA_WIDTH-1:0] mem[0:SIZE-1];
//-- The data_out is a registered output (not a wire)
reg data_out;
//-- Reading port: Synchronous
always @(posedge clk)
begin
data_out <= mem[addr];
end
//-- Writing port: Synchronous
always @(posedge clk)
begin
if (wr) mem[addr] <= data_in;
end
//-- Init the memory
initial begin
if (ROMF)
$readmemh(ROMF, mem, 0, SIZE-1);
end
endmodule |
module v794b6d (
input [31:0] ve841af,
output [21:0] v51fb1f,
output [9:0] vef1612
);
wire [0:31] w0;
wire [0:9] w1;
wire [0:21] w2;
assign w0 = ve841af;
assign vef1612 = w1;
assign v51fb1f = w2;
v794b6d_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module v794b6d_v9a2a06 (
input [31:0] i,
output [21:0] o1,
output [9:0] o0
);
assign o1 = i[31:10];
assign o0 = i[9:0];
endmodule |
module vaaf5c4 (
input v712289,
input [31:0] v4f6beb,
output [31:0] v51eedb,
output v7e4f0f
);
wire [0:31] w0;
wire w1;
wire w2;
wire [0:30] w3;
wire [0:31] w4;
assign w0 = v4f6beb;
assign v7e4f0f = w1;
assign w2 = v712289;
assign v51eedb = w4;
vecd30a vd4273f (
.ve841af(w0),
.v8d1a42(w1),
.v11ef80(w3)
);
v51b3c0 v9b7810 (
.v411a12(w2),
.vd40455(w3),
.v7d0a31(w4)
);
endmodule |
module vecd30a (
input [31:0] ve841af,
output [30:0] v11ef80,
output v8d1a42
);
wire [0:31] w0;
wire w1;
wire [0:30] w2;
assign w0 = ve841af;
assign v8d1a42 = w1;
assign v11ef80 = w2;
vecd30a_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module vecd30a_v9a2a06 (
input [31:0] i,
output [30:0] o1,
output o0
);
assign o1 = i[31:1];
assign o0 = i[0];
endmodule |
module v51b3c0 (
input v411a12,
input [30:0] vd40455,
output [31:0] v7d0a31
);
wire [0:31] w0;
wire [0:30] w1;
wire w2;
assign v7d0a31 = w0;
assign w1 = vd40455;
assign w2 = v411a12;
v51b3c0_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule |
module v51b3c0_v9a2a06 (
input i1,
input [30:0] i0,
output [31:0] o
);
assign o = {i1, i0};
endmodule |
module ve4c3a8 #(
parameter v389bd1 = 5'h1F
) (
input [31:0] v5c832d,
output v4642b6,
output vafdfa0,
output vd02149
);
localparam p8 = v389bd1;
wire w0;
wire w1;
wire w2;
wire [0:14] w3;
wire [0:4] w4;
wire [0:4] w5;
wire [0:4] w6;
wire [0:4] w7;
wire [0:2] w9;
wire [0:31] w10;
wire [0:31] w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
assign w10 = v5c832d;
assign w11 = v5c832d;
assign v4642b6 = w12;
assign vafdfa0 = w13;
assign vd02149 = w14;
assign w2 = w1;
assign w6 = w4;
assign w11 = w10;
assign w16 = w15;
v3676a0 v8f98d9 (
.vcbab45(w0),
.v0e28cb(w1)
);
vba518e v72db53 (
.v0e28cb(w0),
.vcbab45(w13),
.v3ca442(w16)
);
vba518e v97a3cf (
.v3ca442(w2),
.vcbab45(w14),
.v0e28cb(w15)
);
v9a2795 v666bdb (
.vda577d(w1),
.vdee7c7(w9)
);
va7b832 ve316c5 (
.v29a212(w3),
.ve841af(w10)
);
vef0f91 v3ffece (
.vcbe66f(w3),
.vfa86aa(w4)
);
v1cc648 v736214 (
.vfad888(w4),
.vd80e4f(w5),
.v4642b6(w12)
);
v108a6d v2a89b0 (
.v6ece80(w5)
);
v1cc648 v01ba64 (
.vd80e4f(w6),
.vfad888(w7),
.v4642b6(w15)
);
v3693fc #(
.vc5c8ea(p8)
) v006a39 (
.vc8d3b9(w7)
);
ve500df vfe8608 (
.vbb2522(w9),
.ve841af(w11)
);
endmodule |
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule |
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule |
module vba518e (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vba518e_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule |
module vba518e_vf4938a (
input a,
input b,
output c
);
//-- AND gate
//-- Verilog implementation
assign c = a & b;
endmodule |
module v9a2795 (
input [2:0] vdee7c7,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire [0:2] w2;
wire w3;
assign v3f8943 = w0;
assign v64d863 = w1;
assign w2 = vdee7c7;
assign vda577d = w3;
v9a2795_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2),
.o2(w3)
);
endmodule |
module v9a2795_v9a2a06 (
input [2:0] i,
output o2,
output o1,
output o0
);
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule |
module va7b832 (
input [31:0] ve841af,
output [16:0] v62a8c1,
output [14:0] v29a212
);
wire [0:31] w0;
wire [0:14] w1;
wire [0:16] w2;
assign w0 = ve841af;
assign v29a212 = w1;
assign v62a8c1 = w2;
va7b832_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module va7b832_v9a2a06 (
input [31:0] i,
output [16:0] o1,
output [14:0] o0
);
assign o1 = i[31:15];
assign o0 = i[14:0];
endmodule |
module vef0f91 (
input [14:0] vcbe66f,
output [4:0] vfa86aa,
output [9:0] vbdb2c8
);
wire [0:14] w0;
wire [0:9] w1;
wire [0:4] w2;
assign w0 = vcbe66f;
assign vbdb2c8 = w1;
assign vfa86aa = w2;
vef0f91_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module vef0f91_v9a2a06 (
input [14:0] i,
output [4:0] o1,
output [9:0] o0
);
assign o1 = i[14:10];
assign o0 = i[9:0];
endmodule |
module v1cc648 (
input [4:0] vd80e4f,
input [4:0] vfad888,
output v4642b6
);
wire w0;
wire [0:4] w1;
wire [0:4] w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
assign v4642b6 = w0;
assign w1 = vfad888;
assign w2 = vd80e4f;
v23b15b vc1b29d (
.v4642b6(w3),
.v27dec4(w5),
.v6848e9(w7)
);
v91f34c vf38386 (
.v427dd1(w1),
.v53baa6(w7),
.v479af4(w8)
);
v91f34c v83c3c9 (
.v427dd1(w2),
.v53baa6(w5),
.v479af4(w6)
);
v438230 v577a36 (
.v4642b6(w4),
.v693354(w6),
.v5369cd(w8)
);
vba518e v707c6e (
.vcbab45(w0),
.v0e28cb(w3),
.v3ca442(w4)
);
endmodule |
module v23b15b (
input v27dec4,
input v6848e9,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
assign w1 = v27dec4;
assign v4642b6 = w2;
assign w3 = v6848e9;
vd12401 v955b2b (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v3676a0 vf92936 (
.v0e28cb(w0),
.vcbab45(w2)
);
endmodule |
module vd12401 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vd12401_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule |
module vd12401_vf4938a (
input a,
input b,
output c
);
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;
endmodule |
module v91f34c (
input [4:0] v427dd1,
output v53baa6,
output [3:0] v479af4
);
wire [0:3] w0;
wire [0:4] w1;
wire w2;
assign v479af4 = w0;
assign w1 = v427dd1;
assign v53baa6 = w2;
v91f34c_v9a2a06 v9a2a06 (
.o0(w0),
.i(w1),
.o1(w2)
);
endmodule |
module v91f34c_v9a2a06 (
input [4:0] i,
output o1,
output [3:0] o0
);
assign o1 = i[4];
assign o0 = i[3:0];
endmodule |
module v438230 (
input [3:0] v693354,
input [3:0] v5369cd,
output v4642b6
);
wire w0;
wire [0:3] w1;
wire [0:3] w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign v4642b6 = w0;
assign w1 = v693354;
assign w2 = v5369cd;
v23b15b v09a5a5 (
.v4642b6(w3),
.v27dec4(w12),
.v6848e9(w14)
);
v23b15b vc1b29d (
.v4642b6(w4),
.v27dec4(w11),
.v6848e9(w13)
);
v23b15b vcd27ce (
.v4642b6(w5),
.v27dec4(w9),
.v6848e9(w10)
);
vc4f23a vea9c80 (
.v985fcb(w1),
.v4f1fd3(w7),
.vda577d(w9),
.v3f8943(w11),
.v64d863(w12)
);
vc4f23a va7dcdc (
.v985fcb(w2),
.v4f1fd3(w8),
.vda577d(w10),
.v3f8943(w13),
.v64d863(w14)
);
v23b15b va0849c (
.v4642b6(w6),
.v27dec4(w7),
.v6848e9(w8)
);
veffd42 v6e3e65 (
.vcbab45(w0),
.v3ca442(w3),
.v0e28cb(w4),
.v033bf6(w5),
.v9eb652(w6)
);
endmodule |
module vc4f23a (
input [3:0] v985fcb,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign w4 = v985fcb;
vc4f23a_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.i(w4)
);
endmodule |
module vc4f23a_v9a2a06 (
input [3:0] i,
output o3,
output o2,
output o1,
output o0
);
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule |
module veffd42 (
input v9eb652,
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = v3ca442;
assign w1 = v9eb652;
assign w2 = v033bf6;
assign w3 = v0e28cb;
assign vcbab45 = w4;
vba518e vf3ef0f (
.v3ca442(w0),
.v0e28cb(w3),
.vcbab45(w6)
);
vba518e vdcc53d (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w5)
);
vba518e v17ac22 (
.vcbab45(w4),
.v0e28cb(w5),
.v3ca442(w6)
);
endmodule |
module v108a6d #(
parameter vfffc23 = 0
) (
output [4:0] v6ece80
);
localparam p0 = vfffc23;
wire [0:4] w1;
assign v6ece80 = w1;
v3693fc #(
.vc5c8ea(p0)
) ve88537 (
.vc8d3b9(w1)
);
endmodule |
module v3693fc #(
parameter vc5c8ea = 0
) (
output [4:0] vc8d3b9
);
localparam p0 = vc5c8ea;
wire [0:4] w1;
assign vc8d3b9 = w1;
v3693fc_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule |
module v3693fc_v465065 #(
parameter VALUE = 0
) (
output [4:0] k
);
assign k = VALUE;
endmodule |
module ve500df (
input [31:0] ve841af,
output [28:0] vfc82fb,
output [2:0] vbb2522
);
wire [0:31] w0;
wire [0:2] w1;
wire [0:28] w2;
assign w0 = ve841af;
assign vbb2522 = w1;
assign vfc82fb = w2;
ve500df_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule |
module ve500df_v9a2a06 (
input [31:0] i,
output [28:0] o1,
output [2:0] o0
);
assign o1 = i[31:3];
assign o0 = i[2:0];
endmodule |
module vf68661 (
input v6dda25,
input [31:0] vf837fe,
input [3:0] ve9e5a1,
input ve146f6,
output [7:0] vfeb41a
);
wire w0;
wire [0:7] w1;
wire w2;
wire [0:7] w3;
wire w4;
wire [0:31] w5;
wire [0:3] w6;
wire w7;
assign vfeb41a = w3;
assign w4 = v6dda25;
assign w5 = vf837fe;
assign w6 = ve9e5a1;
assign w7 = ve146f6;
vf61fa3 v8cf02b (
.vcbab45(w0),
.vaf45b8(w6)
);
vba518e v7c2c65 (
.v0e28cb(w0),
.vcbab45(w2),
.v3ca442(w7)
);
v468a05 v4dcb81 (
.vc6471a(w1),
.ve841af(w5)
);
v857d2e v415624 (
.vec26ff(w1),
.vccca56(w2),
.v19a59f(w3),
.v6dda25(w4)
);
endmodule |
module vf61fa3 (
input [3:0] vaf45b8,
output vcbab45
);
wire w0;
wire [0:3] w1;
wire w2;
wire w3;
wire w4;
wire w5;
assign vcbab45 = w0;
assign w1 = vaf45b8;
vc4f23a v5f4674 (
.v985fcb(w1),
.v4f1fd3(w2),
.vda577d(w3),
.v3f8943(w4),
.v64d863(w5)
);
vf49321 vea932e (
.vcbab45(w0),
.ve86251(w2),
.v0e28cb(w3),
.v3ca442(w4),
.v8b2684(w5)
);
endmodule |
module vf49321 (
input ve86251,
input v0e28cb,
input v3ca442,
input v8b2684,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = ve86251;
assign w1 = v0e28cb;
assign w3 = v3ca442;
assign vcbab45 = w5;
assign w6 = v8b2684;
v873425 v1edc96 (
.v0e28cb(w0),
.v3ca442(w1),
.vcbab45(w2)
);
v873425 v5591ec (
.v0e28cb(w2),
.v3ca442(w3),
.vcbab45(w4)
);
v873425 vdba9a4 (
.v0e28cb(w4),
.vcbab45(w5),
.v3ca442(w6)
);
endmodule |
module v873425 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v873425_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule |
module v873425_vf4938a (
input a,
input b,
output c
);
//-- OR Gate
//-- Verilog implementation
assign c = a | b;
endmodule |
module v468a05 (
input [31:0] ve841af,
output [7:0] vdd0469,
output [7:0] v4ba85d,
output [7:0] vf93ecb,
output [7:0] vc6471a
);
wire [0:31] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
assign w0 = ve841af;
assign vc6471a = w1;
assign vf93ecb = w2;
assign v4ba85d = w3;
assign vdd0469 = w4;
v468a05_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2),
.o2(w3),
.o3(w4)
);
endmodule |
module v468a05_v9a2a06 (
input [31:0] i,
output [7:0] o3,
output [7:0] o2,
output [7:0] o1,
output [7:0] o0
);
assign o3 = i[32:24];
assign o2 = i[23:16];
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule |
module v857d2e (
input v6dda25,
input [7:0] vec26ff,
input vccca56,
output [7:0] v19a59f
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = vec26ff;
assign v19a59f = w1;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = vccca56;
assign w9 = vccca56;
assign w7 = w6;
assign w9 = w8;
v6bdcd9 v8e04d7 (
.vcc8c7c(w0),
.v651522(w2),
.v2cc41f(w4)
);
vafb28f vdbcc53 (
.va9ac17(w1),
.v515fe7(w3),
.v3c88fc(w5)
);
v370cd6 v732df5 (
.v2856c0(w2),
.v7891f9(w3),
.v6dda25(w6),
.vccca56(w8)
);
v370cd6 v21c6af (
.v2856c0(w4),
.v7891f9(w5),
.v6dda25(w7),
.vccca56(w9)
);
endmodule |
module v6bdcd9 (
input [7:0] vcc8c7c,
output [3:0] v651522,
output [3:0] v2cc41f
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
assign v651522 = w0;
assign v2cc41f = w1;
assign w2 = vcc8c7c;
v6bdcd9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule |
module v6bdcd9_v9a2a06 (
input [7:0] i,
output [3:0] o1,
output [3:0] o0
);
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule |
module vafb28f (
input [3:0] v515fe7,
input [3:0] v3c88fc,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:3] w1;
wire [0:3] w2;
assign va9ac17 = w0;
assign w1 = v515fe7;
assign w2 = v3c88fc;
vafb28f_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule |
module vafb28f_v9a2a06 (
input [3:0] i1,
input [3:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule |
module v370cd6 (
input v6dda25,
input [3:0] v2856c0,
input vccca56,
output [3:0] v7891f9
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v2856c0;
assign v7891f9 = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = vccca56;
assign w15 = vccca56;
assign w16 = vccca56;
assign w17 = vccca56;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
v22cb98 v1ba30c (
.v27dec4(w0),
.v4642b6(w2),
.ve4a668(w12),
.vd793aa(w16)
);
v22cb98 v38f79d (
.v27dec4(w1),
.v4642b6(w3),
.ve4a668(w13),
.vd793aa(w17)
);
v22cb98 v009467 (
.v27dec4(w4),
.v4642b6(w5),
.ve4a668(w11),
.vd793aa(w15)
);
vc4f23a vf2e2c0 (
.v3f8943(w0),
.v64d863(w1),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v947047 (
.vee8a83(w2),
.v03aaf0(w3),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v22cb98 v3a0f4c (
.v27dec4(w8),
.v4642b6(w9),
.ve4a668(w10),
.vd793aa(w14)
);
endmodule |
module v22cb98 #(
parameter v5462c0 = 0
) (
input ve4a668,
input v27dec4,
input vd793aa,
output v4642b6
);
localparam p1 = v5462c0;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w2 = ve4a668;
assign w3 = v27dec4;
assign v4642b6 = w5;
assign w6 = vd793aa;
assign w5 = w4;
va40d2f v9ff767 (
.v030ad0(w0),
.vb192d0(w3),
.v27dec4(w4),
.v2d3366(w6)
);
v053dc2 #(
.v71e305(p1)
) v89c757 (
.vf54559(w0),
.va4102a(w2),
.ve8318d(w4)
);
endmodule |