module_content
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module va40d2f (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
assign v030ad0 = w0;
assign w1 = v2d3366;
assign w2 = v27dec4;
assign w3 = vb192d0;
vd0c4e5 v0f3fef (
.v030ad0(w0),
.v2d3366(w1),
.vb192d0(w2),
.v27dec4(w3)
);
endmodule |
module vd0c4e5 (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign v030ad0 = w0;
assign w2 = v2d3366;
assign w3 = v2d3366;
assign w6 = v27dec4;
assign w7 = vb192d0;
assign w3 = w2;
v873425 vaaee1f (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w4)
);
vba518e v569873 (
.vcbab45(w1),
.v3ca442(w2),
.v0e28cb(w6)
);
v3676a0 v1f00ae (
.v0e28cb(w3),
.vcbab45(w5)
);
vba518e vc8527f (
.vcbab45(w4),
.v3ca442(w5),
.v0e28cb(w7)
);
endmodule |
module v053dc2 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v053dc2_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule |
module v053dc2_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule |
module v84f0a1 (
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [3:0] v11bca5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign w2 = vf8041d;
assign w3 = vd84a57;
assign v11bca5 = w4;
v84f0a1_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.i2(w2),
.i3(w3),
.o(w4)
);
endmodule |
module v84f0a1_v9a2a06 (
input i3,
input i2,
input i1,
input i0,
output [3:0] o
);
assign o = {i3, i2, i1, i0};
endmodule |
module v145d1e (
input [31:0] vb79ed5,
input [7:0] vc74a9c,
input v6287a6,
input v19f646,
output [31:0] vb76294
);
wire [0:31] w0;
wire [0:31] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:31] w5;
wire [0:31] w6;
wire [0:31] w7;
wire [0:7] w8;
wire w9;
wire w10;
assign w6 = vb79ed5;
assign vb76294 = w7;
assign w8 = vc74a9c;
assign w9 = v6287a6;
assign w10 = v19f646;
assign w3 = w2;
assign w4 = w2;
assign w4 = w3;
v15006c v7f618a (
.v3d79e8(w0),
.v53354a(w6),
.vd99bd0(w7),
.v2d3366(w9)
);
v15006c vf576d8 (
.vd99bd0(w0),
.v53354a(w1),
.v3d79e8(w5),
.v2d3366(w10)
);
v78e0a3 v9e8b5c (
.v7d0a31(w1),
.v6127ee(w2),
.v12d067(w3),
.vea9d11(w4),
.v29bdec(w8)
);
vda0861 vfb1ecd (
.vffb58f(w2)
);
v2c97f6 v1dbb84 (
.v7c9bd8(w5)
);
endmodule |
module v15006c (
input [31:0] v53354a,
input [31:0] v3d79e8,
input v2d3366,
output [31:0] vd99bd0
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:31] w3;
wire [0:31] w4;
wire [0:31] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire [0:7] w13;
wire [0:7] w14;
wire [0:7] w15;
wire [0:7] w16;
wire [0:7] w17;
wire [0:7] w18;
assign vd99bd0 = w3;
assign w4 = v3d79e8;
assign w5 = v53354a;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
v1bbb5b v41cfb0 (
.v9d2a6a(w0),
.v2d3366(w12),
.v2a1cbe(w17),
.v9d7ae8(w18)
);
v1bbb5b vf7893e (
.v9d2a6a(w1),
.v2d3366(w11),
.v2a1cbe(w15),
.v9d7ae8(w16)
);
v1bbb5b v40a6d4 (
.v9d2a6a(w2),
.v2d3366(w10),
.v2a1cbe(w13),
.v9d7ae8(w14)
);
v78e0a3 v2e8dfc (
.v29bdec(w0),
.vea9d11(w1),
.v6127ee(w2),
.v7d0a31(w3),
.v12d067(w6)
);
v468a05 v95e147 (
.ve841af(w5),
.vdd0469(w7),
.v4ba85d(w13),
.vf93ecb(w15),
.vc6471a(w17)
);
v468a05 v44f594 (
.ve841af(w4),
.vdd0469(w8),
.v4ba85d(w14),
.vf93ecb(w16),
.vc6471a(w18)
);
v1bbb5b v68fd67 (
.v9d2a6a(w6),
.v2a1cbe(w7),
.v9d7ae8(w8),
.v2d3366(w9)
);
endmodule |
module v1bbb5b (
input [7:0] v2a1cbe,
input [7:0] v9d7ae8,
input v2d3366,
output [7:0] v9d2a6a
);
wire [0:3] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire [0:3] w10;
assign v9d2a6a = w1;
assign w2 = v2a1cbe;
assign w3 = v9d7ae8;
assign w8 = v2d3366;
assign w9 = v2d3366;
assign w9 = w8;
v952eda v54aed2 (
.v6833fd(w0),
.v54ac99(w7),
.v2d3366(w9),
.ve2616d(w10)
);
vafb28f v117a88 (
.v3c88fc(w0),
.va9ac17(w1),
.v515fe7(w4)
);
v6bdcd9 v9f32ae (
.vcc8c7c(w2),
.v651522(w5),
.v2cc41f(w7)
);
v6bdcd9 v9881c7 (
.vcc8c7c(w3),
.v651522(w6),
.v2cc41f(w10)
);
v952eda v34a43a (
.v6833fd(w4),
.v54ac99(w5),
.ve2616d(w6),
.v2d3366(w8)
);
endmodule |
module v952eda (
input [3:0] v54ac99,
input [3:0] ve2616d,
input v2d3366,
output [3:0] v6833fd
);
wire w0;
wire w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign v6833fd = w3;
assign w5 = ve2616d;
assign w6 = v54ac99;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
vd0c4e5 v6d94c9 (
.v030ad0(w0),
.v2d3366(w11),
.v27dec4(w15),
.vb192d0(w17)
);
vd0c4e5 vebe465 (
.v030ad0(w1),
.v2d3366(w12),
.v27dec4(w16),
.vb192d0(w18)
);
vd0c4e5 ve1c21f (
.v030ad0(w2),
.v2d3366(w10),
.v27dec4(w13),
.vb192d0(w14)
);
v84f0a1 va44bdf (
.vee8a83(w0),
.v03aaf0(w1),
.vf8041d(w2),
.v11bca5(w3),
.vd84a57(w4)
);
vd0c4e5 v2ebff3 (
.v030ad0(w4),
.v27dec4(w7),
.vb192d0(w8),
.v2d3366(w9)
);
vc4f23a v3c3a57 (
.v985fcb(w5),
.v4f1fd3(w8),
.vda577d(w14),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a vd6d480 (
.v985fcb(w6),
.v4f1fd3(w7),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
endmodule |
module v78e0a3 (
input [7:0] v12d067,
input [7:0] v6127ee,
input [7:0] vea9d11,
input [7:0] v29bdec,
output [31:0] v7d0a31
);
wire [0:31] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
assign v7d0a31 = w0;
assign w1 = v29bdec;
assign w2 = vea9d11;
assign w3 = v6127ee;
assign w4 = v12d067;
v78e0a3_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2),
.i2(w3),
.i3(w4)
);
endmodule |
module v78e0a3_v9a2a06 (
input [7:0] i3,
input [7:0] i2,
input [7:0] i1,
input [7:0] i0,
output [31:0] o
);
assign o = {i3, i2, i1, i0};
endmodule |
module vda0861 #(
parameter vfffc23 = 0
) (
output [7:0] vffb58f
);
localparam p0 = vfffc23;
wire [0:7] w1;
assign vffb58f = w1;
vffc517 #(
.vc5c8ea(p0)
) v778577 (
.va0aeac(w1)
);
endmodule |
module vffc517 #(
parameter vc5c8ea = 0
) (
output [7:0] va0aeac
);
localparam p0 = vc5c8ea;
wire [0:7] w1;
assign va0aeac = w1;
vffc517_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule |
module vffc517_v465065 #(
parameter VALUE = 0
) (
output [7:0] k
);
assign k = VALUE;
endmodule |
module v04e061 #(
parameter v001ed5 = 1
) (
input vd6bebe,
output v4642b6,
output [4:0] vb385cd,
output vd9f5b6
);
localparam p1 = v001ed5;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:4] w8;
wire w9;
wire w10;
wire w11;
wire [0:4] w12;
assign v4642b6 = w2;
assign vd9f5b6 = w6;
assign vb385cd = w8;
assign w9 = vd6bebe;
assign w10 = vd6bebe;
assign w4 = w2;
assign w5 = w3;
assign w10 = w9;
assign w11 = w2;
assign w11 = w4;
v144728 #(
.v573b2a(p1)
) v04fe70 (
.v27dec4(w0),
.v4642b6(w2),
.v92a149(w3),
.v6dda25(w9)
);
vd30ca9 v8af589 (
.v9fb85f(w0)
);
vba518e ve66489 (
.v0e28cb(w5),
.vcbab45(w6),
.v3ca442(w11)
);
vaf1249 ve31e7c (
.ve37344(w3),
.ve556f1(w7),
.v6dda25(w10),
.va1c800(w12)
);
vd30ca9 va31481 (
.v9fb85f(w7)
);
v51353d vabd391 (
.v427380(w4),
.v81cd93(w8),
.v083523(w12)
);
endmodule |
module v144728 #(
parameter v573b2a = 0
) (
input v6dda25,
input v27dec4,
input v92a149,
output v4642b6
);
localparam p0 = v573b2a;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w5 = v6dda25;
assign v4642b6 = w6;
assign w8 = v27dec4;
assign w9 = v92a149;
assign w7 = w6;
v053dc2 #(
.v71e305(p0)
) v24b497 (
.vf54559(w1),
.va4102a(w5),
.ve8318d(w6)
);
vd0c4e5 vda4b54 (
.v030ad0(w1),
.v27dec4(w2),
.vb192d0(w3),
.v2d3366(w8)
);
vfebcfe v2141a0 (
.v9fb85f(w2)
);
vd0c4e5 v75d8ff (
.v030ad0(w3),
.v27dec4(w4),
.vb192d0(w7),
.v2d3366(w9)
);
vd30ca9 va595cf (
.v9fb85f(w4)
);
endmodule |
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule |
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule |
module vaf1249 (
input v6dda25,
input ve556f1,
output [4:0] va1c800,
output ve37344
);
wire w0;
wire [0:4] w1;
wire [0:4] w2;
wire w3;
wire [0:4] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign va1c800 = w4;
assign ve37344 = w5;
assign w4 = w1;
v6ed669 vad9b51 (
.v782748(w0),
.vcc30ea(w1),
.v35dd11(w2),
.v6dda25(w3)
);
vd0bb30 v1e9706 (
.vd03823(w1),
.vb4c454(w2),
.v4642b6(w5)
);
endmodule |
module v6ed669 (
input v6dda25,
input v782748,
input [4:0] v35dd11,
output [4:0] vcc30ea
);
wire [0:4] w0;
wire [0:3] w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:4] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = v35dd11;
assign vcc30ea = w5;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = v782748;
assign w9 = v782748;
assign w7 = w6;
assign w9 = w8;
v2be0f8 v8aa818 (
.vf354ee(w2),
.v4642b6(w4),
.vd53b77(w6),
.v27dec4(w8)
);
v5c75f6 vbdef88 (
.v4de61b(w1),
.v50034e(w3),
.v6dda25(w7),
.v782748(w9)
);
v91f34c v122992 (
.v427dd1(w0),
.v479af4(w1),
.v53baa6(w2)
);
vcdce79 v93fefd (
.v167ed7(w3),
.vee8a83(w4),
.v6a2e9e(w5)
);
endmodule |
module v2be0f8 #(
parameter vbd3217 = 0
) (
input vd53b77,
input v27dec4,
input vf354ee,
output v4642b6
);
localparam p5 = vbd3217;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w6;
assign w2 = v27dec4;
assign w3 = vf354ee;
assign v4642b6 = w4;
assign w6 = vd53b77;
v3676a0 v7539bf (
.vcbab45(w1),
.v0e28cb(w2)
);
vba518e vfe8158 (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v053dc2 #(
.v71e305(p5)
) vd104a4 (
.vf54559(w0),
.ve8318d(w4),
.va4102a(w6)
);
endmodule |
module v5c75f6 (
input v6dda25,
input v782748,
input [3:0] v4de61b,
output [3:0] v50034e
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v4de61b;
assign v50034e = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
vc4f23a v4b1225 (
.v3f8943(w2),
.v64d863(w3),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v6491fd (
.v03aaf0(w0),
.vee8a83(w1),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v2be0f8 v10a04f (
.v4642b6(w0),
.vf354ee(w3),
.vd53b77(w13),
.v27dec4(w17)
);
v2be0f8 v7d9648 (
.v4642b6(w1),
.vf354ee(w2),
.vd53b77(w12),
.v27dec4(w16)
);
v2be0f8 v004b14 (
.vf354ee(w4),
.v4642b6(w5),
.vd53b77(w11),
.v27dec4(w15)
);
v2be0f8 v8aa818 (
.vf354ee(w8),
.v4642b6(w9),
.vd53b77(w10),
.v27dec4(w14)
);
endmodule |
module vcdce79 (
input vee8a83,
input [3:0] v167ed7,
output [4:0] v6a2e9e
);
wire [0:4] w0;
wire w1;
wire [0:3] w2;
assign v6a2e9e = w0;
assign w1 = vee8a83;
assign w2 = v167ed7;
vcdce79_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule |
module vcdce79_v9a2a06 (
input i1,
input [3:0] i0,
output [4:0] o
);
assign o = {i1, i0};
endmodule |
module vd0bb30 #(
parameter v6c5139 = 1
) (
input [4:0] vd03823,
output v4642b6,
output [4:0] vb4c454
);
localparam p1 = v6c5139;
wire w0;
wire [0:4] w2;
wire [0:4] w3;
assign v4642b6 = w0;
assign w2 = vd03823;
assign vb4c454 = w3;
va17f79 #(
.vd73390(p1)
) vc288d0 (
.v4642b6(w0),
.va6f14e(w2),
.v919f01(w3)
);
endmodule |
module va17f79 #(
parameter vd73390 = 0
) (
input [4:0] va6f14e,
output v4642b6,
output [4:0] v919f01
);
localparam p1 = vd73390;
wire w0;
wire [0:4] w2;
wire [0:4] w3;
wire [0:4] w4;
assign v4642b6 = w0;
assign w3 = va6f14e;
assign v919f01 = w4;
v0cfc7a v530cb5 (
.v4642b6(w0),
.v225d34(w2),
.vbb6b94(w3),
.vae8b91(w4)
);
v3693fc #(
.vc5c8ea(p1)
) v809c3c (
.vc8d3b9(w2)
);
endmodule |
module v0cfc7a (
input [4:0] v225d34,
input [4:0] vbb6b94,
output v4642b6,
output [4:0] vae8b91
);
wire w0;
wire w1;
wire [0:4] w2;
wire [0:4] w3;
wire [0:4] w4;
wire w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
wire w9;
wire [0:3] w10;
assign w2 = vbb6b94;
assign w3 = v225d34;
assign vae8b91 = w4;
assign v4642b6 = w5;
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w5),
.v27dec4(w7),
.v82de4f(w9)
);
v91f34c v144430 (
.v427dd1(w2),
.v53baa6(w9),
.v479af4(w10)
);
v91f34c v09d2c7 (
.v427dd1(w3),
.v53baa6(w7),
.v479af4(w8)
);
v25966b vd35762 (
.v4642b6(w0),
.v817794(w6),
.v0550b6(w8),
.v24708e(w10)
);
vcdce79 v758283 (
.vee8a83(w1),
.v6a2e9e(w4),
.v167ed7(w6)
);
endmodule |
module vad119b (
input v27dec4,
input v82de4f,
input v0ef266,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
assign v8e8a67 = w1;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v27dec4;
assign w8 = v82de4f;
assign w9 = v82de4f;
assign w10 = v0ef266;
assign w11 = v0ef266;
assign w2 = w0;
assign w7 = w6;
assign w9 = w8;
assign w11 = w10;
vd12401 v2e3d9f (
.vcbab45(w0),
.v0e28cb(w7),
.v3ca442(w9)
);
vd12401 vb50462 (
.v0e28cb(w0),
.vcbab45(w1),
.v3ca442(w11)
);
vba518e v4882f4 (
.v3ca442(w2),
.vcbab45(w3),
.v0e28cb(w10)
);
vba518e v8fcf41 (
.vcbab45(w4),
.v0e28cb(w6),
.v3ca442(w8)
);
v873425 vc5b8b9 (
.v3ca442(w3),
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule |
module v25966b (
input [3:0] v0550b6,
input [3:0] v24708e,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
v1ea21d vdbe125 (
.v4642b6(w0),
.v8e8a67(w2),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w14),
.v82de4f(w17)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w12),
.v82de4f(w16)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w13),
.vda577d(w16),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w11),
.vda577d(w12),
.v3f8943(w14),
.v64d863(w15)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w11),
.v82de4f(w13)
);
endmodule |
module v1ea21d (
input v27dec4,
input v82de4f,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v82de4f;
assign w1 = v27dec4;
assign v4642b6 = w3;
assign v8e8a67 = w4;
vad119b vb820a1 (
.v82de4f(w0),
.v27dec4(w1),
.v0ef266(w2),
.v4642b6(w3),
.v8e8a67(w4)
);
vd30ca9 v23ebb6 (
.v9fb85f(w2)
);
endmodule |
module v51353d (
input [4:0] v083523,
input v427380,
output [4:0] v81cd93
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:4] w8;
wire w9;
wire [0:4] w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
assign w1 = v427380;
assign w2 = v427380;
assign w6 = v427380;
assign w8 = v083523;
assign v81cd93 = w10;
assign w13 = v427380;
assign w14 = v427380;
assign w2 = w1;
assign w6 = w1;
assign w6 = w2;
assign w13 = w1;
assign w13 = w2;
assign w13 = w6;
assign w14 = w1;
assign w14 = w2;
assign w14 = w6;
assign w14 = w13;
vba518e v984c00 (
.v0e28cb(w0),
.v3ca442(w2),
.vcbab45(w3)
);
vba518e v63c547 (
.v3ca442(w1),
.vcbab45(w4),
.v0e28cb(w9)
);
vba518e v017827 (
.v0e28cb(w5),
.v3ca442(w6),
.vcbab45(w7)
);
v60f5a9 v3aadcd (
.v3f8943(w0),
.vda577d(w5),
.v427dd1(w8),
.v64d863(w9),
.v53baa6(w11),
.v4f1fd3(w12)
);
v36cddd v6e87bf (
.vee8a83(w3),
.v03aaf0(w4),
.vf8041d(w7),
.v6a2e9e(w10),
.vd84a57(w15),
.v684b0d(w16)
);
vba518e vd994d2 (
.v0e28cb(w12),
.v3ca442(w13),
.vcbab45(w15)
);
vba518e v0bd924 (
.v0e28cb(w11),
.v3ca442(w14),
.vcbab45(w16)
);
endmodule |
module v60f5a9 (
input [4:0] v427dd1,
output v53baa6,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:4] w5;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign v53baa6 = w4;
assign w5 = v427dd1;
v60f5a9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.o4(w4),
.i(w5)
);
endmodule |
module v60f5a9_v9a2a06 (
input [4:0] i,
output o4,
output o3,
output o2,
output o1,
output o0
);
assign o4 = i[4];
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule |
module v36cddd (
input v684b0d,
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [4:0] v6a2e9e
);
wire w0;
wire w1;
wire [0:4] w2;
wire w3;
wire w4;
wire w5;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign v6a2e9e = w2;
assign w3 = vf8041d;
assign w4 = vd84a57;
assign w5 = v684b0d;
v36cddd_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.o(w2),
.i2(w3),
.i3(w4),
.i4(w5)
);
endmodule |
module v36cddd_v9a2a06 (
input i4,
input i3,
input i2,
input i1,
input i0,
output [4:0] o
);
assign o = {i4, i3, i2, i1, i0};
endmodule |
module altera_up_character_lcd_communication (
// Inputs
clk,
reset,
data_in,
enable,
rs,
rw,
display_on,
back_light_on,
// Bidirectionals
LCD_DATA,
// Outputs
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RS,
LCD_RW,
data_out,
transfer_complete
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for minimum wait between consecutive communications
// if using a 50MHz Clk
parameter CLOCK_CYCLES_FOR_IDLE_STATE = 7'h7F; // Minimum 2500 ns
parameter IC = 7; // Number of bits for idle counter
parameter IDLE_COUNTER_INCREMENT = 7'h01;
parameter CLOCK_CYCLES_FOR_OPERATION_STATE = 3; // Minimum 40 ns
parameter CLOCK_CYCLES_FOR_ENABLE_STATE = 15; // Minimum 230 ns
parameter CLOCK_CYCLES_FOR_HOLD_STATE = 1; // Minimum 10 ns
parameter SC = 4; // Number of bits for states counter
parameter COUNTER_INCREMENT = 4'h1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] data_in;
input rs;
input rw;
input enable;
input display_on;
input back_light_on;
// Bidirectionals
inout [ 7: 0] LCD_DATA;
// Outputs
output reg LCD_ON;
output reg LCD_BLON;
output reg LCD_EN;
output reg LCD_RS;
output reg LCD_RW;
output reg [ 7: 0] data_out; // Stores data read from the LCD
output reg transfer_complete; // Indicates the end of the transfer
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter LCD_STATE_4_IDLE = 3'h4,
LCD_STATE_0_OPERATION = 3'h0,
LCD_STATE_1_ENABLE = 3'h1,
LCD_STATE_2_HOLD = 3'h2,
LCD_STATE_3_END = 3'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [ 7: 0] data_to_lcd;
reg [IC: 1] idle_counter;
reg [SC: 1] state_0_counter;
reg [SC: 1] state_1_counter;
reg [SC: 1] state_2_counter;
// State Machine Registers
reg [ 2: 0] ns_lcd;
reg [ 2: 0] s_lcd;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd <= LCD_STATE_4_IDLE;
else
s_lcd <= ns_lcd;
end
always @(*)
begin
ns_lcd = LCD_STATE_4_IDLE;
case (s_lcd)
LCD_STATE_4_IDLE:
begin
if ((idle_counter == CLOCK_CYCLES_FOR_IDLE_STATE) & enable)
ns_lcd = LCD_STATE_0_OPERATION;
else
ns_lcd = LCD_STATE_4_IDLE;
end
LCD_STATE_0_OPERATION:
begin
if (state_0_counter == CLOCK_CYCLES_FOR_OPERATION_STATE)
ns_lcd = LCD_STATE_1_ENABLE;
else
ns_lcd = LCD_STATE_0_OPERATION;
end
LCD_STATE_1_ENABLE:
begin
if (state_1_counter == CLOCK_CYCLES_FOR_ENABLE_STATE)
ns_lcd = LCD_STATE_2_HOLD;
else
ns_lcd = LCD_STATE_1_ENABLE;
end
LCD_STATE_2_HOLD:
begin
if (state_2_counter == CLOCK_CYCLES_FOR_HOLD_STATE)
ns_lcd = LCD_STATE_3_END;
else
ns_lcd = LCD_STATE_2_HOLD;
end
LCD_STATE_3_END:
begin
if (enable == 1'b0)
ns_lcd = LCD_STATE_4_IDLE;
else
ns_lcd = LCD_STATE_3_END;
end
default:
begin
ns_lcd = LCD_STATE_4_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
begin
LCD_ON <= 1'b0;
LCD_BLON <= 1'b0;
end
else
begin
LCD_ON <= display_on;
LCD_BLON <= back_light_on;
end
end
always @(posedge clk)
begin
if (reset)
begin
LCD_EN <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
data_out <= 8'h00;
transfer_complete <= 1'b0;
end
else
begin
if (s_lcd == LCD_STATE_1_ENABLE)
LCD_EN <= 1'b1;
else
LCD_EN <= 1'b0;
if (s_lcd == LCD_STATE_4_IDLE)
begin
LCD_RS <= rs;
LCD_RW <= rw;
data_to_lcd <= data_in;
end
if (s_lcd == LCD_STATE_1_ENABLE)
data_out <= LCD_DATA;
if (s_lcd == LCD_STATE_3_END)
transfer_complete <= 1'b1;
else
transfer_complete <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
idle_counter <= {IC{1'b0}};
else if (s_lcd == LCD_STATE_4_IDLE)
idle_counter <= idle_counter + IDLE_COUNTER_INCREMENT;
else
idle_counter <= {IC{1'b0}};
end
always @(posedge clk)
begin
if (reset)
begin
state_0_counter <= {SC{1'b0}};
state_1_counter <= {SC{1'b0}};
state_2_counter <= {SC{1'b0}};
end
else
begin
if (s_lcd == LCD_STATE_0_OPERATION)
state_0_counter <= state_0_counter + COUNTER_INCREMENT;
else
state_0_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_1_ENABLE)
state_1_counter <= state_1_counter + COUNTER_INCREMENT;
else
state_1_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_2_HOLD)
state_2_counter <= state_2_counter + COUNTER_INCREMENT;
else
state_2_counter <= {SC{1'b0}};
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign LCD_DATA =
(((s_lcd == LCD_STATE_1_ENABLE) ||
(s_lcd == LCD_STATE_2_HOLD)) &&
(LCD_RW == 1'b0)) ? data_to_lcd : 8'hzz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module small_async_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 3,
parameter ALMOST_FULL_SIZE = 5,
parameter ALMOST_EMPTY_SIZE = 3
)
(
//wr interface
output wfull,
output w_almost_full,
input [DSIZE-1:0] wdata,
input winc, wclk, wrst_n,
//rd interface
output [DSIZE-1:0] rdata,
output rempty,
output r_almost_empty,
input rinc, rclk, rrst_n
);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
sync_r2w #(ASIZE) sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr),
.wclk(wclk), .wrst_n(wrst_n));
sync_w2r #(ASIZE) sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr),
.rclk(rclk), .rrst_n(rrst_n));
fifo_mem #(DSIZE, ASIZE) fifo_mem
(.rdata(rdata), .wdata(wdata),
.waddr(waddr), .raddr(raddr),
.wclken(winc), .wfull(wfull),
.wclk(wclk));
rptr_empty #(.ADDRSIZE(ASIZE), .ALMOST_EMPTY_SIZE(ALMOST_EMPTY_SIZE))
rptr_empty
(.rempty(rempty),
.r_almost_empty(r_almost_empty),
.raddr(raddr),
.rptr(rptr),
.rq2_wptr(rq2_wptr),
.rinc(rinc),
.rclk(rclk),
.rrst_n(rrst_n));
wptr_full #(.ADDRSIZE(ASIZE), .ALMOST_FULL_SIZE(ALMOST_FULL_SIZE))
wptr_full
(.wfull(wfull),
.w_almost_full(w_almost_full),
.waddr(waddr),
.wptr(wptr),
.wq2_rptr(wq2_rptr),
.winc(winc),
.wclk(wclk),
.wrst_n(wrst_n));
endmodule |
module sync_r2w #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk, wrst_n);
reg [ADDRSIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;
else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
endmodule |
module sync_w2r #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] rq2_wptr,
input [ADDRSIZE:0] wptr,
input rclk, rrst_n);
reg [ADDRSIZE:0] rq1_wptr;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;
else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
endmodule |
module rptr_empty
#(parameter ADDRSIZE = 3,
parameter ALMOST_EMPTY_SIZE=3)
(output reg rempty,
output reg r_almost_empty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input [ADDRSIZE :0] rq2_wptr,
input rinc, rclk, rrst_n);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
reg [ADDRSIZE :0] rq2_wptr_bin;
integer i;
//------------------
// GRAYSTYLE2 pointer
//------------------
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//--------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//--------------------------------------------------------------
wire rempty_val = (rgraynext == rq2_wptr);
// Gray code to Binary code conversion
always @(rq2_wptr)
for (i=0; i<(ADDRSIZE+1); i=i+1)
rq2_wptr_bin[i] = ^ (rq2_wptr >> i);
wire [ADDRSIZE:0] subtract = (rbinnext + ALMOST_EMPTY_SIZE)-rq2_wptr_bin;
wire r_almost_empty_val = ~subtract[ADDRSIZE];
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) begin
rempty <= 1'b1;
r_almost_empty <= 1'b 1;
end
else begin
rempty <= rempty_val;
r_almost_empty <= r_almost_empty_val;
end
endmodule |
module wptr_full
#(parameter ADDRSIZE = 3,
parameter ALMOST_FULL_SIZE=5
)
(output reg wfull,
output reg w_almost_full,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr,
input [ADDRSIZE :0] wq2_rptr,
input winc, wclk, wrst_n);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
reg [ADDRSIZE :0] wq2_rptr_bin;
integer i;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wbin, wptr} <= 0;
else {wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext>>1) ^ wbinnext;
//-----------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//-----------------------------------------------------------------
wire wfull_val = (wgraynext ==
{~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
// Gray code to Binary code conversion
always @(wq2_rptr)
for (i=0; i<(ADDRSIZE+1); i=i+1)
wq2_rptr_bin[i] = ^ (wq2_rptr >> i);
wire [ADDRSIZE :0] subtract = wbinnext - wq2_rptr_bin - ALMOST_FULL_SIZE;
wire w_almost_full_val = ~subtract[ADDRSIZE];
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) begin
wfull <= 1'b0;
w_almost_full <= 1'b 0;
end
else begin
wfull <= wfull_val;
w_almost_full <= w_almost_full_val;
end
endmodule |
module fifo_mem #(parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 3) // Number of mem address bits
(output [DATASIZE-1:0] rdata,
input [DATASIZE-1:0] wdata,
input [ADDRSIZE-1:0] waddr, raddr,
input wclken, wfull, wclk);
// RTL Verilog memory model
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
assign rdata = mem[raddr];
always @(posedge wclk)
if (wclken && !wfull) mem[waddr] <= wdata;
endmodule |
module block_design_m01_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_9_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H1),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module ded_top
#(parameter BYTES = 16)
(
// Global Signals
input de_clk, // Drawing Engine Clock
de_rstn, // Drawing Engine Reset
// Host/ XY Windows
input hb_clk, // host bus clock
hb_rstn, // host bus reset
input [12:2] hb_adr, // host bus lower address bits
input hb_we, // host bus write strobe
input hb_xyw_csn, // chip select for XY window
// DEX related
input dx_mem_req, // memory request
dx_mem_rd, // memory read
dx_line_actv_2, // line command active signal
dx_blt_actv_2, // bit blt active signal
input dx_pc_ld, // load pixel cache
input [31:0] dx_clpx_bus_2, // clipping X values
input dx_rstn_wad, // load cache write address
input dx_ld_rad, // load cache read address
input dx_ld_rad_e, // load cache read address
input dx_sol_2, // start of line flag
dx_eol_2, // end of line flag
input dx_ld_msk, // load mask.{ld_start,ld_end,
// ld_lftclp,ld_rhtclp}
input [9:0] dx_xalu, // lower four bits of the X alu.
input [15:0] srcx, // lower five bits from the destination X
input [15:0] srcy, // lower five bits from the destination X
input [15:0] dsty, // lower five bits from the destination Y
input [15:0] dx_dstx, // Current X for blts and xfers.
input dx_fg_bgn, // fore/back ground bit for line pat.
input clip, // Clip indicator. PIPED SIGNAL
input [4:0] xpat_ofs, // X off set for patterns.
input [4:0] ypat_ofs, // Y off set for patterns.
input [15:0] real_dstx, // X destination.
input [15:0] real_dsty, // Y destination.
input ld_initial, // load the initial color value.
input pc_msk_last, // Mask the last pixel for nolast
input last_pixel, // Last Pixel from Jim (Not Clean)
input ld_wcnt,
input [3:0] fx_1,
input rmw,
// Memory Controller Inputs
input mclock, // memory controller clock
input mc_popen, // memory controller pop enable
input mc_push, // push data into fifo from MC.
mc_eop, // end of page cycle pulse, from MC
mc_eop4, // end of page cycle pulse, from MC
input de_pc_pop, // Pop from PC
// Level 2 Registers
input [3:0] de_pln_msk_2, // Plane mask bits
input dr_solid_2, // solid mode bit
dr_trnsp_2, // transparent mode bit
input [1:0] stpl_2, // stipple mode bit 01 = planar, 10 = packed
input [1:0] dr_apat_2, // area mode bits 01 = 8x8, 10 = 32x32
input [1:0] dr_clp_2, // lower two bits of the clipping register
input [31:0] fore_2, // foreground register output
input [31:0] back_2, // background register output
input dr_sen_2, // Source enable bits
input y_clip_2, // Inside the Y clipping boundries
input ps8_2, // pixel size equals eight
ps16_2, // pixel size equals sixteen
ps32_2, // pixel size equals thirty-two
input [1:0] bc_lvl_2, // Y page request limit
input hb_write,
input [27:0] dorg_2, // Destination origin.
input [27:0] sorg_2, // Source origin.
input [27:0] z_org, // Z origin
input [11:0] dptch_2, // destination pitch.
input [11:0] sptch_2, // source pitch.
input [11:0] z_ptch, // Z pitch
input [1:0] ps_2, // Pixel size to MC
input [3:0] bsrcr_2, // Source blending function.
input [2:0] bdstr_2, // Destination blending function.
input blend_en_2, // Blending enable.
input [1:0] blend_reg_en_2,// Select blending registers or alpha from FB
input [7:0] bsrc_alpha_2, // Source alpha data.
input [7:0] bdst_alpha_2, // Destination alpha data.
input [3:0] rop_2, // Raster operation.
input [31:0] kcol_2, // Key Color.
input [2:0] key_ctrl_2, // Key control.
input [2:0] frst8_2, // used to be in dex
// Memory Controller Outputs
output [BYTES-1:0] mc_pixel_msk, // pixel mask data output
output [(BYTES<<3)-1:0] mc_fb_out, // frame buffer data output
output [(BYTES<<2)-1:0] mc_fb_a, // frame buffer data output
output pc_mc_busy, // gated MC busy for Jim
output [31:0] de_mc_address, // Line/ Blt linear address
output de_mc_read,
output de_mc_rmw,
output [3:0] de_mc_wcnt,
output de_pc_empty,
output pc_empty,
// Host Bus
output [31:0] hb_dout, // Host read back data.
// ded_ca_top memory interface
`ifdef BYTE16 output [3:0] ca_enable,
`elsif BYTE8 output [1:0] ca_enable,
`else output ca_enable, `endif
output [4:0] hb_ram_addr,
output [4:0] ca_ram_addr0,
output [4:0] ca_ram_addr1,
input [(BYTES*8)-1:0] hb_dout_ram,
input [(BYTES<<3)-1:0] ca_dout0,
input [(BYTES<<3)-1:0] ca_dout1,
// Drawing Engine
output pc_dirty, // data is left in the pixel cache
output clip_ind, // Clipping indicator.
output stpl_pk_4, // packed stipple bit, level four
output pc_mc_rdy, // Ready signal from PC to DX
output pipe_pending, // There is something in the PC or pipe
output line_actv_4,
output [1:0] ps_4,
output [3:0] bsrcr_4, // Source blending function.
output [2:0] bdstr_4, // Destination blending function.
output blend_en_4, // Blending enable.
output [1:0] blend_reg_en_4, // Blending register enables
output [7:0] bsrc_alpha_4, // Source alpha data.
output [7:0] bdst_alpha_4, // Destination alpha data.
output [3:0] rop_4, // Raster operation.
output [31:0] kcol_4, // Key Color.
output [2:0] key_ctrl_4, // Key control.
////////////////////////////////////////////////////////
// 3D Interface.
output pc_busy_3d,
input valid_3d,
input fg_bgn_3d,
input msk_last_3d,
input [15:0] x_out_3d,
input [15:0] y_out_3d,
input last_3d,
input [31:0] pixel_3d,
input [31:0] z_3d,
input [4:0] z_ctrl,
input active_3d_2,
input [7:0] alpha_3d,
output pc_last,
output [4:0] z_ctrl_4,
output [31:0] z_address_4,
output [(BYTES*8)-1:0] z_out
);
wire [(BYTES<<3)-1:0] de_pc_data;
wire [(BYTES<<2)-1:0] de_pc_a;
wire [BYTES-1:0] de_pc_mask;
wire [1:0] clp_4;
wire [31:0] fore_4; // foreground register output
wire [31:0] back_4; // foreground register output
/************************************************************************/
/* CREATE INTERNAL WIRE BUSSES */
/************************************************************************/
wire [(BYTES<<3)-1:0] ca_din; /* Data into cache. */
wire [BYTES-1:0] cx_sel; /* color expand selector. */
wire [BYTES-1:0] trns_msk; /* transparentcy mask. */
wire [9:0] ca_rad; /* Cache read address. */
wire [7:0] ca_wr_en; /* Cache write enables. */
wire [1:0] apat_4;
wire [2:0] psize_4;
wire [1:0] stpl_4;
wire [8:0] x_bitmask; /* muxed input bitmask to texel cache */
wire [8:0] y_bitmask; /* muxed input bitmask to texel cache */
wire ca_src_2 = dr_sen_2;
reg xyw_csn_d;
`ifdef BYTE16 wire [2:0] ca_mc_addr;
`elsif BYTE8 wire [3:0] ca_mc_addr;
`else wire [4:0] ca_mc_addr;
`endif
wire sol_3;
wire ps32_4;
wire ps16_4;
wire ps8_4;
wire solid_4;
wire blt_actv_4;
wire trnsp_4;
wire eol_4;
wire pc_busy;
wire [3:0] mask_4;
wire rad_flg_2, rad_flg_3;
wire [2:0] strt_wrd_2;
wire [3:0] strt_byt_2;
wire [2:0] strt_bit_2;
wire [2:0] strt_wrd_3;
wire [3:0] strt_byt_3;
wire [2:0] strt_bit_3;
wire [2:0] strt_wrd_4;
wire [3:0] strt_byt_4;
wire [2:0] strt_bit_4;
wire [6:0] lft_enc_2;
wire [6:0] rht_enc_2;
wire [11:0] clp_min_2; // left clipping pointer
wire [11:0] clp_max_2; // right clipping pointer
wire [3:0] cmin_enc_2;
wire [3:0] cmax_enc_2;
wire [6:0] lft_enc_4;
wire [6:0] rht_enc_4;
wire [11:0] clp_min_4; // left clipping pointer
wire [11:0] clp_max_4; // right clipping pointer
wire [3:0] cmin_enc_4;
wire [3:0] cmax_enc_4;
wire y_clip_4;
wire sol_4;
wire [13:0] x_bus_4;
wire mc_read_3;
wire rst_wad_flg_2, rst_wad_flg_3;
wire [2:0] frst8_4;
wire mc_acken;
assign stpl_pk_4 = stpl_4[1];
assign pc_mc_rdy = ~pc_busy;
/****************************************************************/
/* DATAPATH CACHE CONTROLLER */
/****************************************************************/
ded_cactrl
#(.BYTES (BYTES)) U_CACTRL
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.mc_read_4 (mc_read_3),
.mc_push (mc_push),
.mclock (mclock),
//.mc_popen (mc_popen & blt_actv_4 & ~solid_4),
.mc_popen (mc_popen),
.mc_acken (mc_acken),
.irst_wad (dx_rstn_wad),
.ld_rad (dx_ld_rad),
.ld_rad_e (dx_ld_rad_e),
.x_adr (dx_xalu),
.srcx (srcx[8:0]),
.dsty (dsty[4:0]),
.dstx (dx_dstx[6:0]),
.lt_actv_4 (line_actv_4),
.stpl_2 (stpl_2),
.stpl_4 (stpl_4),
.apat_2 (dr_apat_2),
.apat_4 (apat_4),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.psize_4 (psize_4),
//.mc_eop (mc_eop & blt_actv_4 & ~solid_4),
.mc_eop (mc_eop),
.eol_4 (eol_4),
.ofset (srcx[2:0]),
.frst8_4 (frst8_4),
.sol_3 (sol_3),
//.mem_req (dx_mem_req & dx_blt_actv_2),
.mem_req (dx_mem_req),
.mem_rd (dx_mem_rd),
.xpat_ofs (xpat_ofs),
.ypat_ofs (ypat_ofs),
.ca_src_2 (ca_src_2),
.rad_flg_2 (rad_flg_2),
.strt_wrd_3 (strt_wrd_3),
.strt_byt_3 (strt_byt_3),
.strt_bit_3 (strt_bit_3),
.strt_wrd_4 (strt_wrd_4),
.strt_byt_4 (strt_byt_4),
.strt_bit_4 (strt_bit_4),
.rst_wad_flg_3 (rst_wad_flg_3),
.rad_flg_3 (rad_flg_3),
.strt_wrd_2 (strt_wrd_2),
.strt_byt_2 (strt_byt_2),
.strt_bit_2 (strt_bit_2),
.rst_wad_flg_2 (rst_wad_flg_2),
.ca_rad (ca_rad),
.ca_mc_addr (ca_mc_addr)
);
/****************************************************************/
/* DATAPATH DATA CACHE */
/****************************************************************/
ded_ca_top
#(.BYTES (BYTES)) U_CA_TOP
(
.mclock (mclock),
.mc_push (mc_push),
.mc_addr (ca_mc_addr),
.hclock (hb_clk),
.hb_we (hb_we & ~hb_xyw_csn), // fixme??? is this needed
.hb_addr (hb_adr[6:2]),
.hb_dout_ram (hb_dout_ram),
`ifdef BYTE16 .rad (ca_rad[9:7]),
`elsif BYTE8 .rad (ca_rad[9:6]),
`else .rad (ca_rad[9:5]), `endif
.ca_enable (ca_enable),
.hb_dout (hb_dout),
.hb_ram_addr (hb_ram_addr),
.ca_ram_addr0 (ca_ram_addr0),
.ca_ram_addr1 (ca_ram_addr1)
);
// always @ (posedge hb_clk) xyw_csn_d <= hb_xyw_csn;
/****************************************************************/
/* DATAPATH FUNNEL SHIFTER */
/* DATAPATH COLOR SELECTOR */
/* (grouped for synthesis) */
/****************************************************************/
ded_funcol
#(.BYTES (BYTES)) U_FUNCOL
(
.mclock (mclock),
.stpl_4 (stpl_4),
.apat_4 (apat_4),
.ps32_4 (ps32_4),
.ps16_4 (ps16_4),
.ps8_4 (ps8_4),
.lt_actv_4 (line_actv_4),
.fore_4 (fore_4),
.back_4 (back_4),
.solid_4 (solid_4),
.pc_col (de_pc_data),
`ifdef BYTE16 .rad (ca_rad[6:0]),
`elsif BYTE8 .rad (ca_rad[5:0]),
`else .rad (ca_rad[4:0]), `endif
.bsd0 (ca_dout0),
.bsd1 (ca_dout1),
.col_dat (mc_fb_out),
.trns_msk (trns_msk),
.cx_sel (cx_sel)
);
/****************************************************************/
/* MASK GENERATOR */
/****************************************************************/
ded_mskgen
#(.BYTES (BYTES)) U_MSKGEN
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.mclock (mclock),
.mc_acken (mc_acken),
.mc_popen (mc_popen),
.ld_msk (dx_ld_msk),
.line_actv_4 (line_actv_4),
.blt_actv_4 (blt_actv_4),
.clp_4 (clp_4),
.mem_req (dx_mem_req),
.mem_rd (dx_mem_rd),
.pc_msk_in (de_pc_mask),
.clpx_bus_2 (dx_clpx_bus_2),
.x_bus (dx_dstx),
.xalu_bus (dx_xalu[6:0]),
.trnsp_4 (trnsp_4),
.trns_msk_in (trns_msk),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.mc_eop (mc_eop),
.mask_4 (mask_4),
.lft_enc_4 (lft_enc_4),
.rht_enc_4 (rht_enc_4),
.clp_min_4 (clp_min_4),
.clp_max_4 (clp_max_4),
.cmin_enc_4 (cmin_enc_4),
.cmax_enc_4 (cmax_enc_4),
.y_clip_4 (y_clip_4),
.sol_4 (sol_4),
.eol_4 (eol_4),
.x_count_4 (x_bus_4),
.mc_eop4 (mc_eop4),
.pixel_msk (mc_pixel_msk),
.clip_ind (clip_ind),
.lft_enc_2 (lft_enc_2),
.rht_enc_2 (rht_enc_2),
.clp_min_2 (clp_min_2),
.clp_max_2 (clp_max_2),
.cmin_enc_2 (cmin_enc_2),
.cmax_enc_2 (cmax_enc_2)
);
/****************************************************************/
/* LINE PIXEL CACHE */
/****************************************************************/
ded_pix_cache
#(.BYTES (BYTES)) U_PIX
(
.de_clk (de_clk),
.mc_clk (mclock),
// .de_rstn (de_rstn),
.de_rstn (hb_rstn),
.dorg_2 (dorg_2),
.sorg_2 (sorg_2),
.dptch_2 (dptch_2),
.sptch_2 (sptch_2),
.ld_wcnt (ld_wcnt),
.fx_1 (fx_1),
.rmw (rmw),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.fore_2 (fore_2),
.back_2 (back_2),
.solid_2 (dr_solid_2),
.dr_trnsp_2 (dr_trnsp_2),
// 2D Interface.
.dx_pc_ld (dx_pc_ld),
.dx_clip (clip),
.dx_real_dstx (real_dstx),
.dx_real_dsty (real_dsty),
.dx_pc_msk_last (pc_msk_last),
.dx_fg_bgn (dx_fg_bgn),
.dx_last_pixel (last_pixel),
// 3D Interface.
`ifdef CORE_3D
.valid_3d (valid_3d),
.fg_bgn_3d (fg_bgn_3d),
.x_out_3d (x_out_3d),
.y_out_3d (y_out_3d),
.pc_msk_last_3d (msk_last_3d),
.pc_last_3d (last_3d),
.pixel_3d (pixel_3d),
.z_3d (z_3d),
.alpha_3d (alpha_3d),
.z_op (z_ctrl[2:0]),
.z_en (z_ctrl[3]),
.z_ro (z_ctrl[4]),
.zorg_2 (z_org),
.zptch_2 (z_ptch),
.active_3d_2 (active_3d_2),
`else
.valid_3d (1'b0),
.fg_bgn_3d (1'b0),
.x_out_3d (16'h0),
.y_out_3d (16'h0),
.pc_msk_last_3d (1'b0),
.pc_last_3d (1'b0),
.pixel_3d (32'h0),
.alpha_3d (8'h0),
.z_op (3'b0),
.z_en (1'b0),
.z_ro (1'b0),
.zorg_2 (28'b0),
.zptch_2 (12'b0),
.active_3d_2 (1'b0),
`endif
//
.de_pc_pop (de_pc_pop),
.mc_popen (mc_popen),
.srcx (srcx),
.srcy (srcy),
.dstx (dx_dstx),
.dsty (dsty),
.imem_rd (dx_mem_rd),
.dx_mem_req (dx_mem_req),
.mask_2 (de_pln_msk_2),
.stpl_2 (stpl_2),
.dr_apat_2 (dr_apat_2),
.dr_clp_2 (dr_clp_2),
.rad_flg_2 (rad_flg_2),
.strt_wrd_2 (strt_wrd_2),
.strt_byt_2 (strt_byt_2),
.strt_bit_2 (strt_bit_2),
.ps_2 (ps_2),
.bsrcr_2 (bsrcr_2),
.bdstr_2 (bdstr_2),
.blend_en_2 (blend_en_2),
.blend_reg_en_2 (blend_reg_en_2),
.bsrc_alpha_2 (bsrc_alpha_2),
.bdst_alpha_2 (bdst_alpha_2),
.rop_2 (rop_2),
.kcol_2 (kcol_2),
.key_ctrl_2 (key_ctrl_2),
.lft_enc_2 (lft_enc_2),
.rht_enc_2 (rht_enc_2),
.clp_min_2 (clp_min_2),
.clp_max_2 (clp_max_2),
.cmin_enc_2 (cmin_enc_2),
.cmax_enc_2 (cmax_enc_2),
.y_clip_2 (y_clip_2),
.sol_2 (dx_sol_2),
.eol_2 (dx_eol_2),
.rst_wad_flg_2 (rst_wad_flg_2),
.frst8_2 (frst8_2),
.rad_flg_3 (rad_flg_3),
.strt_wrd_3 (strt_wrd_3),
.strt_byt_3 (strt_byt_3),
.strt_bit_3 (strt_bit_3),
.strt_wrd_4 (strt_wrd_4),
.strt_byt_4 (strt_byt_4),
.strt_bit_4 (strt_bit_4),
.px_a (mc_fb_a),
.px_col (de_pc_data),
.px_msk_color (de_pc_mask),
.de_mc_address (de_mc_address),
.de_mc_read (de_mc_read),
.de_mc_rmw (de_mc_rmw),
.de_mc_wcnt (de_mc_wcnt),
.pc_dirty (pc_dirty),
.de_pc_empty (de_pc_empty),
.pc_pending (pipe_pending),
.pc_busy (pc_busy),
.pc_busy_3d (pc_busy_3d),
.fore_4 (fore_4),
.back_4 (back_4),
.blt_actv_4 (blt_actv_4),
.stpl_4 (stpl_4),
.ps8_4 (ps8_4),
.ps16_4 (ps16_4),
.ps32_4 (ps32_4),
.trnsp_4 (trnsp_4),
.solid_4 (solid_4),
.clp_4 (clp_4),
.line_actv_4 (line_actv_4),
.apat_4 (apat_4),
.mask_4 (mask_4),
.ps_4 (ps_4),
.bsrcr_4 (bsrcr_4),
.bdstr_4 (bdstr_4),
.blend_en_4 (blend_en_4),
.blend_reg_en_4 (blend_reg_en_4),
.bsrc_alpha_4 (bsrc_alpha_4),
.bdst_alpha_4 (bdst_alpha_4),
.rop_4 (rop_4),
.kcol_4 (kcol_4),
.key_ctrl_4 (key_ctrl_4),
.lft_enc_4 (lft_enc_4),
.rht_enc_4 (rht_enc_4),
.clp_min_4 (clp_min_4),
.clp_max_4 (clp_max_4),
.cmin_enc_4 (cmin_enc_4),
.cmax_enc_4 (cmax_enc_4),
.y_clip_4 (y_clip_4),
.sol_4 (sol_4),
.eol_4 (eol_4),
.x_bus_4 (x_bus_4),
.rst_wad_flg_3 (rst_wad_flg_3),
.mc_read_3 (mc_read_3),
.sol_3 (sol_3),
.mc_acken (mc_acken),
.frst8_4 (frst8_4),
.pc_empty (pc_empty),
.pc_last (pc_last),
.z_en_4 (z_ctrl_4[3]),
.z_ro_4 (z_ctrl_4[4]),
.z_op_4 (z_ctrl_4[2:0]),
.z_address_4 (z_address_4),
.z_out (z_out)
);
assign pc_mc_busy = pc_busy;
assign psize_4 = {ps32_4,ps16_4,ps8_4}; // Needed for cactrl
endmodule |
module mt48lc4m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter addr_bits = 12;
parameter data_bits = 16;
parameter col_bits = 8;
parameter mem_sizes = 1048575;
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [1 : 0] Dqm;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank)
reg Read_precharge [0 : 3]; // R Auto Precharge
reg Write_precharge [0 : 3]; // W Auto Precharge
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank
integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter
integer Count_precharge [0 : 3]; // RW Auto Precharge Counter
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Prev_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
wire Debug = 1'b1; // Debug messages : 1 = On
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign Dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define WRITE 3
`define PRECH 4
`define A_REF 5
`define BST 6
`define LMR 7
// Timing Parameters for -7E PC133 CL2
parameter tAC = 5.4;
parameter tHZ = 5.4;
parameter tOH = 3.0;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 37.0;
parameter tRC = 60.0;
parameter tRCD = 15.0;
parameter tRFC = 66.0;
parameter tRP = 15.0;
parameter tRRD = 14.0;
parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns)
parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns)
// Timing Check variable
time MRD_chk;
time WR_chkm [0 : 3];
time RFC_chk, RRD_chk;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
initial begin
Dq_reg = {data_bits{1'bz}};
Data_in_enable = 0; Data_out_enable = 0;
Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0;
RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
$timeformat (-9, 1, " ns", 12);
end
// System clock generator
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] === 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] === 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] === 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] === 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// Read or Write Interrupt Counter
if (RW_interrupt_write[0] === 1'b1) begin
RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
end
if (RW_interrupt_write[1] === 1'b1) begin
RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
end
if (RW_interrupt_write[2] === 1'b1) begin
RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
end
if (RW_interrupt_write[3] === 1'b1) begin
RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// Auto Refresh
if (Aref_enable === 1'b1) begin
if (Debug) begin
$display ("%m : at time %t AREF : Auto Refresh", $time);
end
// Auto Refresh to Auto Refresh
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Load Mode Register to Auto Refresh
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Record Current tRFC time
RFC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
// Register Mode
Mode_reg = Addr;
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Debug) begin
$display ("%m : at time %t LMR : Load Mode Register", $time);
// CAS Latency
case (Addr[6 : 4])
3'b010 : $display ("%m : CAS Latency = 2");
3'b011 : $display ("%m : CAS Latency = 3");
default : $display ("%m : CAS Latency = Reserved");
endcase
// Burst Length
case (Addr[2 : 0])
3'b000 : $display ("%m : Burst Length = 1");
3'b001 : $display ("%m : Burst Length = 2");
3'b010 : $display ("%m : Burst Length = 4");
3'b011 : $display ("%m : Burst Length = 8");
3'b111 : $display ("%m : Burst Length = Full");
default : $display ("%m : Burst Length = Reserved");
endcase
// Burst Type
if (Addr[3] === 1'b0) begin
$display ("%m : Burst Type = Sequential");
end else if (Addr[3] === 1'b1) begin
$display ("%m : Burst Type = Interleaved");
end else begin
$display ("%m : Burst Type = Reserved");
end
// Write Burst Mode
if (Addr[9] === 1'b0) begin
$display ("%m : Write Burst Mode = Programmed Burst Length");
end else if (Addr[9] === 1'b1) begin
$display ("%m : Write Burst Mode = Single Location Access");
end else begin
$display ("%m : Write Burst Mode = Reserved");
end
end
// Precharge to Load Mode Register
if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// Precharge to Load Mode Register
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);
end
// Auto Refresh to Load Mode Register
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time);
end
// Load Mode Register to Load Mode Register
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Reset MRD Counter
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable === 1'b1) begin
// Activate an open bank can corrupt data
if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) ||
(Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin
$display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time);
end
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 0 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk0 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);
end
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);
end
// Record variables
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk0 = $time;
RC_chk0 = $time;
RCD_chk0 = $time;
end
if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 1 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk1 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);
end
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);
end
// Record variables
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk1 = $time;
RC_chk1 = $time;
RCD_chk1 = $time;
end
if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 2 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk2 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);
end
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);
end
// Record variables
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk2 = $time;
RC_chk2 = $time;
RCD_chk2 = $time;
end
if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 3 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk3 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);
end
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);
end
// Record variables
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk3 = $time;
RC_chk3 = $time;
RCD_chk3 = $time;
end
// Active Bank A to Active Bank B
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Prev_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
// Load Mode Register to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);
end
// Precharge Bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge
if ($time - RAS_chk0 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[0] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge
if ($time - RAS_chk1 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[1] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge
if ($time - RAS_chk2 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[2] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge
if ($time - RAS_chk3 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[3] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 === 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 === 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 === 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
// Display debug message
if (Debug) begin
$display ("%m : at time %t BST : Burst Terminate",$time);
end
end
// Read, Write, Column Latch
if (Read_enable === 1'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Read", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
Command[2] = `READ;
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `READ;
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
RW_interrupt_counter[RW_interrupt_bank] = 0;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Read_precharge[Ba] = 1'b1;
end
end
// Write Command
if (Write_enable == 1'b1) begin
// Activate to Write
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Write", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// Latch Write command, Bank, and Column
Command[0] = `WRITE;
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
// Interrupting a Read with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_read[RW_interrupt_bank] = 1'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Write_precharge[Ba] = 1'b1;
end
end
/*
Write with Auto Precharge Calculation
The device start internal precharge when:
1. Meet minimum tRAS requirement
and 2. tWR cycle(s) after last valid data
or 3. Interrupt by a Read or Write (with or without Auto Precharge)
Note: Model is starting the internal precharge 1 cycle after they meet all the
requirement but tRP will be compensate for the time after the 1 cycle.
*/
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. Meet minimum tRAS requirement
// and 2. CAS Latency - 1 cycles before last burst
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
if (Debug) begin
$display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0 [{Row, Col}];
2'b01 : Dq_dqm = Bank1 [{Row, Col}];
2'b10 : Dq_dqm = Bank2 [{Row, Col}];
2'b11 : Dq_dqm = Bank3 [{Row, Col}];
endcase
// Dqm operation
if (Dqm[0] == 1'b0) begin
Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
end
if (Dqm[1] == 1'b0) begin
Dq_dqm [15 : 8] = Dq [15 : 8];
end
// Write to memory
case (Bank)
2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
endcase
// Display debug message
if (Dqm !== 2'b11) begin
// Record tWR for manual precharge
WR_chkm [Bank] = $time;
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_dqm);
end
end else begin
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
#tHZ Burst_decode;
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0[{Row, Col}];
2'b01 : Dq_dqm = Bank1[{Row, Col}];
2'b10 : Dq_dqm = Bank2[{Row, Col}];
2'b11 : Dq_dqm = Bank3[{Row, Col}];
endcase
// Dqm operation
if (Dqm_reg0 [0] == 1'b1) begin
Dq_dqm [ 7 : 0] = 8'bz;
end
if (Dqm_reg0 [1] == 1'b1) begin
Dq_dqm [15 : 8] = 8'bz;
end
// Display debug message
if (Dqm_reg0 !== 2'b11) begin
Dq_reg = #tAC Dq_dqm;
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_reg);
end
end else begin
Dq_reg = #tHZ {data_bits{1'bz}};
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
Burst_decode;
end
end
// Burst counter decode
task Burst_decode;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
// Timing Parameters for -7E (133 MHz @ CL2)
specify
specparam
tAH = 0.8, // Addr, Ba Hold Time
tAS = 1.5, // Addr, Ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
tCK = 7.0, // Clock Cycle Time
tDH = 0.8, // Data-in Hold Time
tDS = 1.5, // Data-in Setup Time
tCKH = 0.8, // CKE Hold Time
tCKS = 1.5, // CKE Setup Time
tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
$width (posedge Clk, tCH);
$width (negedge Clk, tCL);
$period (negedge Clk, tCK);
$period (posedge Clk, tCK);
$setuphold(posedge Clk, Cke, tCKS, tCKH);
$setuphold(posedge Clk, Cs_n, tCMS, tCMH);
$setuphold(posedge Clk, Cas_n, tCMS, tCMH);
$setuphold(posedge Clk, Ras_n, tCMS, tCMH);
$setuphold(posedge Clk, We_n, tCMS, tCMH);
$setuphold(posedge Clk, Addr, tAS, tAH);
$setuphold(posedge Clk, Ba, tAS, tAH);
$setuphold(posedge Clk, Dqm, tCMS, tCMH);
$setuphold(posedge Dq_chk, Dq, tDS, tDH);
endspecify
endmodule |
module pcie3_7x_0_pipe_sync #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_LANE = 1, // PCIe lane
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align
parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align
)
(
//---------- Input -------------------------------------
input SYNC_CLK,
input SYNC_RST_N,
input SYNC_SLAVE,
input SYNC_GEN3,
input SYNC_RATE_IDLE,
input SYNC_MMCM_LOCK,
input SYNC_RXELECIDLE,
input SYNC_RXCDRLOCK,
input SYNC_ACTIVE_LANE,
input SYNC_TXSYNC_START,
input SYNC_TXPHINITDONE,
input SYNC_TXDLYSRESETDONE,
input SYNC_TXPHALIGNDONE,
input SYNC_TXSYNCDONE,
input SYNC_RXSYNC_START,
input SYNC_RXDLYSRESETDONE,
input SYNC_RXPHALIGNDONE_M,
input SYNC_RXPHALIGNDONE_S,
input SYNC_RXSYNC_DONEM_IN,
input SYNC_RXSYNCDONE,
//---------- Output ------------------------------------
output SYNC_TXPHDLYRESET,
output SYNC_TXPHALIGN,
output SYNC_TXPHALIGNEN,
output SYNC_TXPHINIT,
output SYNC_TXDLYBYPASS,
output SYNC_TXDLYSRESET,
output SYNC_TXDLYEN,
output SYNC_TXSYNC_DONE,
output [ 5:0] SYNC_FSM_TX,
output SYNC_RXPHALIGN,
output SYNC_RXPHALIGNEN,
output SYNC_RXDLYBYPASS,
output SYNC_RXDLYSRESET,
output SYNC_RXDLYEN,
output SYNC_RXDDIEN,
output SYNC_RXSYNC_DONEM_OUT,
output SYNC_RXSYNC_DONE,
output [ 6:0] SYNC_FSM_RX
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2;
//---------- Output Register ---------------------------
reg txdlyen = 1'd0;
reg txsync_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg rxdlyen = 1'd0;
reg rxsync_done = 1'd0;
reg [ 6:0] fsm_rx = 7'd0;
//---------- FSM ---------------------------------------
localparam FSM_TXSYNC_IDLE = 6'b000001;
localparam FSM_MMCM_LOCK = 6'b000010;
localparam FSM_TXSYNC_START = 6'b000100;
localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only
localparam FSM_TXSYNC_DONE1 = 6'b010000;
localparam FSM_TXSYNC_DONE2 = 6'b100000;
localparam FSM_RXSYNC_IDLE = 7'b0000001;
localparam FSM_RXCDRLOCK = 7'b0000010;
localparam FSM_RXSYNC_START = 7'b0000100;
localparam FSM_RXSYNC_DONE1 = 7'b0001000;
localparam FSM_RXSYNC_DONE2 = 7'b0010000;
localparam FSM_RXSYNC_DONES = 7'b0100000;
localparam FSM_RXSYNC_DONEM = 7'b1000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
rxelecidle_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
txsync_start_reg1 <= 1'd0;
txphinitdone_reg1 <= 1'd0;
txdlysresetdone_reg1 <= 1'd0;
txphaligndone_reg1 <= 1'd0;
txsyncdone_reg1 <= 1'd0;
rxsync_start_reg1 <= 1'd0;
rxdlysresetdone_reg1 <= 1'd0;
rxphaligndone_m_reg1 <= 1'd0;
rxphaligndone_s_reg1 <= 1'd0;
rxsync_donem_reg1 <= 1'd0;
rxsyncdone_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
rxelecidle_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
txsync_start_reg2 <= 1'd0;
txphinitdone_reg2 <= 1'd0;
txdlysresetdone_reg2 <= 1'd0;
txphaligndone_reg2 <= 1'd0;
txsyncdone_reg2 <= 1'd0;
rxsync_start_reg2 <= 1'd0;
rxdlysresetdone_reg2 <= 1'd0;
rxphaligndone_m_reg2 <= 1'd0;
rxphaligndone_s_reg2 <= 1'd0;
rxsync_donem_reg2 <= 1'd0;
rxsyncdone_reg2 <= 1'd0;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= 1'd0;
txphinitdone_reg3 <= 1'd0;
txdlysresetdone_reg3 <= 1'd0;
txphaligndone_reg3 <= 1'd0;
txsyncdone_reg3 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= SYNC_GEN3;
rate_idle_reg1 <= SYNC_RATE_IDLE;
mmcm_lock_reg1 <= SYNC_MMCM_LOCK;
rxelecidle_reg1 <= SYNC_RXELECIDLE;
rxcdrlock_reg1 <= SYNC_RXCDRLOCK;
txsync_start_reg1 <= SYNC_TXSYNC_START;
txphinitdone_reg1 <= SYNC_TXPHINITDONE;
txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
txphaligndone_reg1 <= SYNC_TXPHALIGNDONE;
txsyncdone_reg1 <= SYNC_TXSYNCDONE;
rxsync_start_reg1 <= SYNC_RXSYNC_START;
rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN;
rxsyncdone_reg1 <= SYNC_RXSYNCDONE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
rate_idle_reg2 <= rate_idle_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
rxelecidle_reg2 <= rxelecidle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
txsync_start_reg2 <= txsync_start_reg1;
txphinitdone_reg2 <= txphinitdone_reg1;
txdlysresetdone_reg2 <= txdlysresetdone_reg1;
txphaligndone_reg2 <= txphaligndone_reg1;
txsyncdone_reg2 <= txsyncdone_reg1;
rxsync_start_reg2 <= rxsync_start_reg1;
rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
rxsync_donem_reg2 <= rxsync_donem_reg1;
rxsyncdone_reg2 <= rxsyncdone_reg1;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= txsync_start_reg2;
txphinitdone_reg3 <= txphinitdone_reg2;
txdlysresetdone_reg3 <= txdlysresetdone_reg2;
txphaligndone_reg3 <= txphaligndone_reg2;
txsyncdone_reg3 <= txsyncdone_reg2;
end
end
//---------- Generate TX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE"))
begin : txsync_fsm
//---------- PIPE TX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ------------------------
FSM_TXSYNC_IDLE :
begin
//---------- Exiting Reset or Rate Change --
if (txsync_start_reg2)
begin
fsm_tx <= FSM_MMCM_LOCK;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= txdlyen;
txsync_done <= txsync_done;
end
end
//---------- Check MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- TX Delay Soft Reset ---------------
FSM_TXSYNC_START :
begin
fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Init Done (Manual Mode Only)
FSM_TXPHINITDONE :
begin
fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Alignment Done --
FSM_TXSYNC_DONE1 :
begin
if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
else
fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for Master TX Delay Alignment Done
FSM_TXSYNC_DONE2 :
begin
if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd1;
end
else
begin
fsm_tx <= FSM_TXSYNC_DONE2;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
endcase
end
end
end
//---------- TX Sync FSM Default------------------------------------------------
else
begin : txsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
end
endgenerate
//---------- Generate RX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))
begin : rxsync_fsm
//---------- PIPE RX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ------------------------
FSM_RXSYNC_IDLE :
begin
//---------- Exiting Rate Change -----------
if (rxsync_start_reg2)
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Exiting Electrical Idle without Rate Change
else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Idle --------------------------
else
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
end
end
//---------- Wait for RX Electrical Idle Exit and RX CDR Lock
FSM_RXCDRLOCK :
begin
fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Start RX Sync with RX Delay Soft Reset
FSM_RXSYNC_START :
begin
fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Wait for RX Phase Alignment Done --
FSM_RXSYNC_DONE1 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONE2 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd1;
end
else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
rxdlyen <= (PCIE_LANE == 1);
rxsync_done <= (PCIE_LANE == 1);
end
else
begin
fsm_rx <= FSM_RXSYNC_DONE2;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Slave RX Phase Alignment Done
FSM_RXSYNC_DONES :
begin
if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONES;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONEM :
begin
if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd1;
rxsync_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
endcase
end
end
end
//---------- RX Sync FSM Default -----------------------------------------------
else
begin : rxsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
endgenerate
//---------- PIPE Sync Output --------------------------------------------------
assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;
assign SYNC_TXDLYBYPASS = 1'd0;
//assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START);
assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);
assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
assign SYNC_TXSYNC_DONE = txsync_done;
assign SYNC_FSM_TX = fsm_tx;
assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;
assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START);
assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");
assign SYNC_RXSYNC_DONE = rxsync_done;
assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
assign SYNC_FSM_RX = fsm_rx;
endmodule |
module pcie (
input wire sys_clk_250, // 250 Mhz Clock
input wire sys_clk_125, // 125 Mhz Clock
input wire rst_n, // asynchronous system reset.
input wire inta_n,
input wire [7:0] msi,
input wire [15:0] vendor_id ,
input wire [15:0] device_id ,
input wire [7:0] rev_id ,
input wire [23:0] class_code ,
input wire [15:0] subsys_ven_id ,
input wire [15:0] subsys_id ,
input wire load_id ,
input wire force_lsm_active, // Force LSM Status Active
input wire force_rec_ei, // Force Received Electrical Idle
input wire force_phy_status, // Force PHY Connection Status
input wire force_disable_scr,// Force Disable Scrambler to PCS
input wire hl_snd_beacon, // HL req. to Send Beacon
input wire hl_disable_scr, // HL req. to Disable Scrambling bit in TS1/TS2
input wire hl_gto_dis, // HL req a jump to Disable
input wire hl_gto_det, // HL req a jump to detect
input wire hl_gto_hrst, // HL req a jump to Hot reset
input wire hl_gto_l0stx, // HL req a jump to TX L0s
input wire hl_gto_l1, // HL req a jump to L1
input wire hl_gto_l2, // HL req a jump to L2
input wire hl_gto_l0stxfts, // HL req a jump to L0s TX FTS
input wire hl_gto_lbk, // HL req a jump to Loopback
input wire hl_gto_rcvry, // HL req a jump to recovery
input wire hl_gto_cfg, // HL req a jump to CFG
input wire no_pcie_train, // Disable the training process
// Power Management Interface
input wire [1:0] tx_dllp_val, // Req for Sending PM/Vendor type DLLP
input wire [2:0] tx_pmtype, // Power Management Type
input wire [23:0] tx_vsd_data, // Vendor Type DLLP contents
// For VC Inputs
input wire tx_req_vc0, // VC0 Request from User
input wire [15:0] tx_data_vc0, // VC0 Input data from user logic
input wire tx_st_vc0, // VC0 start of pkt from user logic.
input wire tx_end_vc0, // VC0 End of pkt from user logic.
input wire tx_nlfy_vc0, // VC0 End of nullified pkt from user logic.
input wire ph_buf_status_vc0, // VC0 Indicate the Full/alm.Full status of the PH buffers
input wire pd_buf_status_vc0, // VC0 Indicate PD Buffer has got space less than Max Pkt size
input wire nph_buf_status_vc0, // VC0 For NPH
input wire npd_buf_status_vc0, // VC0 For NPD
input wire ph_processed_vc0, // VC0 TL has processed one TLP Header - PH Type
input wire pd_processed_vc0, // VC0 TL has processed one TLP Data - PD TYPE
input wire nph_processed_vc0, // VC0 For NPH
input wire npd_processed_vc0, // VC0 For NPD
input wire [7:0] pd_num_vc0, // VC0 For PD -- No. of Data processed
input wire [7:0] npd_num_vc0, // VC0 For PD
input wire [7:0] rxp_data, // CH0:PCI Express data from External Phy
input wire rxp_data_k, // CH0:PCI Express Control from External Phy
input wire rxp_valid, // CH0:Indicates a symbol lock and valid data on rx_data /rx_data_k
input wire rxp_elec_idle, // CH0:Inidicates receiver detection of an electrical signal
input wire [2:0] rxp_status, // CH0:Indicates receiver Staus/Error codes
input wire phy_status, // Indicates PHY status info
// From User logic
// From User logic
input wire cmpln_tout , // Completion time out.
input wire cmpltr_abort_np , // Completor abort.
input wire cmpltr_abort_p , // Completor abort.
input wire unexp_cmpln , // Unexpexted completion.
input wire ur_np_ext , // UR for NP type.
input wire ur_p_ext , // UR for P type.
input wire np_req_pend , // Non posted request is pending.
input wire pme_status , // PME status to reg 044h.
// User Loop back data
input wire [15:0] tx_lbk_data, // TX User Master Loopback data
input wire [1:0] tx_lbk_kcntl, // TX User Master Loopback control
output wire tx_lbk_rdy, // TX loop back is ready to accept data
output wire [15:0] rx_lbk_data, // RX User Master Loopback data
output wire [1:0] rx_lbk_kcntl, // RX User Master Loopback control
// Power Management/ Vendor specific DLLP
output wire tx_dllp_sent, // Requested PM DLLP is sent
output wire [2:0] rxdp_pmd_type, // PM DLLP type bits.
output wire [23:0] rxdp_vsd_data , // Vendor specific DLLP data.
output wire [1:0] rxdp_dllp_val, // PM/Vendor specific DLLP valid.
output wire [7:0] txp_data, // CH0:PCI Express data to External Phy
output wire txp_data_k, // CH0:PCI Express control to External Phy
output wire txp_elec_idle, // CH0:Tells PHY to output Electrical Idle
output wire txp_compliance, // CH0:Sets the PHY running disparity to -ve
output wire rxp_polarity, // CH0:Tells PHY to do polarity inversion on the received data
output wire txp_detect_rx_lb, // Tells PHY to begin receiver detection or begin Loopback
output wire reset_n, // Async reset to the PHY
output wire [1:0] power_down, // Tell sthe PHY to power Up or Down
output wire phy_pol_compliance, // Polling compliance
output wire [3:0] phy_ltssm_state, // Indicates the states of the ltssm
output wire [2:0] phy_ltssm_substate, // sub-states of the ltssm_state
output wire tx_rdy_vc0, // VC0 TX ready indicating signal
output wire [8:0] tx_ca_ph_vc0, // VC0 Available credit for Posted Type Headers
output wire [12:0] tx_ca_pd_vc0, // VC0 For Posted - Data
output wire [8:0] tx_ca_nph_vc0, // VC0 For Non-posted - Header
output wire [12:0] tx_ca_npd_vc0, // VC0 For Non-posted - Data
output wire [8:0] tx_ca_cplh_vc0, // VC0 For Completion - Header
output wire [12:0] tx_ca_cpld_vc0, // VC0 For Completion - Data
output wire tx_ca_p_recheck_vc0, //
output wire tx_ca_cpl_recheck_vc0, //
output wire [15:0] rx_data_vc0, // VC0 Receive data
output wire rx_st_vc0, // VC0 Receive data start
output wire rx_end_vc0, // VC0 Receive data end
output wire rx_us_req_vc0 , // VC0 unsupported req received
output wire rx_malf_tlp_vc0 ,// VC0 malformed TLP in received data
output wire [6:0] rx_bar_hit , // Bar hit
output wire [2:0] mm_enable , // Multiple message enable bits of Register
output wire msi_enable , // MSI enable bit of Register
// From Config Registers
output wire [7:0] bus_num , // Bus number
output wire [4:0] dev_num , // Device number
output wire [2:0] func_num , // Function number
output wire [1:0] pm_power_state , // Power state bits of Register at 044h
output wire pme_en , // PME_En at 044h
output wire [5:0] cmd_reg_out , // Bits 10,8,6,2,1,0 From register 004h
output wire [14:0] dev_cntl_out , // Divice control register at 060h
output wire [7:0] lnk_cntl_out , // Link control register at 068h
// To ASPM implementation outside the IP
output wire tx_rbuf_empty, // Transmit retry buffer is empty
output wire tx_dllp_pend, // DLPP is pending to be transmitted
output wire rx_tlp_rcvd, // Received a TLP
// Datal Link Control SM Status
output wire dl_inactive, // Data Link Control SM is in INACTIVE state
output wire dl_init, // INIT state
output wire dl_active, // ACTIVE state
output wire dl_up // Data Link Layer is UP
);
pci_exp_x1_core_wrap u1_dut(
// Clock and Reset
.sys_clk_250 ( sys_clk_250 ) ,
.sys_clk_125 ( sys_clk_125 ) ,
.rst_n ( rst_n ),
.inta_n ( inta_n ),
.msi ( msi ),
.vendor_id ( vendor_id ),
.device_id ( device_id ),
.rev_id ( rev_id ),
.class_code ( class_code ),
.subsys_ven_id ( subsys_ven_id ),
.subsys_id ( subsys_id ),
.load_id ( load_id ),
// Inputs
.force_lsm_active ( force_lsm_active ),
.force_rec_ei ( force_rec_ei ),
.force_phy_status ( force_phy_status ),
.force_disable_scr ( force_disable_scr ),
.hl_snd_beacon ( hl_snd_beacon ),
.hl_disable_scr ( hl_disable_scr ),
.hl_gto_dis ( hl_gto_dis ),
.hl_gto_det ( hl_gto_det ),
.hl_gto_hrst ( hl_gto_hrst ),
.hl_gto_l0stx ( hl_gto_l0stx ),
.hl_gto_l1 ( hl_gto_l1 ),
.hl_gto_l2 ( hl_gto_l2 ),
.hl_gto_l0stxfts ( hl_gto_l0stxfts ),
.hl_gto_lbk ( hl_gto_lbk ),
.hl_gto_rcvry ( hl_gto_rcvry ),
.hl_gto_cfg ( hl_gto_cfg ),
.no_pcie_train ( no_pcie_train ),
// Power Management Interface
.tx_dllp_val ( tx_dllp_val ),
.tx_pmtype ( tx_pmtype ),
.tx_vsd_data ( tx_vsd_data ),
.tx_req_vc0 ( tx_req_vc0 ),
.tx_data_vc0 ( tx_data_vc0 ),
.tx_st_vc0 ( tx_st_vc0 ),
.tx_end_vc0 ( tx_end_vc0 ),
.tx_nlfy_vc0 ( tx_nlfy_vc0 ),
.ph_buf_status_vc0 ( ph_buf_status_vc0 ),
.pd_buf_status_vc0 ( pd_buf_status_vc0 ),
.nph_buf_status_vc0 ( nph_buf_status_vc0 ),
.npd_buf_status_vc0 ( npd_buf_status_vc0 ),
.ph_processed_vc0 ( ph_processed_vc0 ),
.pd_processed_vc0 ( pd_processed_vc0 ),
.nph_processed_vc0 ( nph_processed_vc0 ),
.npd_processed_vc0 ( npd_processed_vc0 ),
.pd_num_vc0 ( pd_num_vc0 ),
.npd_num_vc0 ( npd_num_vc0 ),
// From External PHY (PIPE I/F)
.rxp_data ( rxp_data ),
.rxp_data_k ( rxp_data_k ),
.rxp_valid ( rxp_valid ),
.rxp_elec_idle ( rxp_elec_idle ),
.rxp_status ( rxp_status ),
.phy_status ( phy_status),
// From User logic
.cmpln_tout ( cmpln_tout ),
.cmpltr_abort_np ( cmpltr_abort_np ),
.cmpltr_abort_p ( cmpltr_abort_p ),
.unexp_cmpln ( unexp_cmpln ),
.ur_np_ext ( ur_np_ext ),
.ur_p_ext ( ur_p_ext ),
.np_req_pend ( np_req_pend ),
.pme_status ( pme_status ),
.tx_lbk_data ( tx_lbk_data ),
.tx_lbk_kcntl ( tx_lbk_kcntl ),
.tx_lbk_rdy ( tx_lbk_rdy ),
.rx_lbk_data ( rx_lbk_data ),
.rx_lbk_kcntl ( rx_lbk_kcntl ),
// Power Management
.tx_dllp_sent ( tx_dllp_sent ),
.rxdp_pmd_type ( rxdp_pmd_type ),
.rxdp_vsd_data ( rxdp_vsd_data ),
.rxdp_dllp_val ( rxdp_dllp_val ),
//-------- Outputs
// To External PHY (PIPE I/F)
.txp_data ( txp_data ),
.txp_data_k ( txp_data_k ),
.txp_elec_idle ( txp_elec_idle ),
.txp_compliance ( txp_compliance ),
.rxp_polarity ( rxp_polarity ),
.txp_detect_rx_lb ( txp_detect_rx_lb ),
.reset_n ( reset_n ),
.power_down ( power_down ),
// From TX User Interface
.phy_pol_compliance ( phy_pol_compliance ),
.phy_ltssm_state ( phy_ltssm_state ),
.phy_ltssm_substate ( phy_ltssm_substate ),
.tx_rdy_vc0 ( tx_rdy_vc0),
.tx_ca_ph_vc0 ( tx_ca_ph_vc0),
.tx_ca_pd_vc0 ( tx_ca_pd_vc0),
.tx_ca_nph_vc0 ( tx_ca_nph_vc0),
.tx_ca_npd_vc0 ( tx_ca_npd_vc0),
.tx_ca_cplh_vc0 ( tx_ca_cplh_vc0),
.tx_ca_cpld_vc0 ( tx_ca_cpld_vc0),
.tx_ca_p_recheck_vc0 ( tx_ca_p_recheck_vc0 ),
.tx_ca_cpl_recheck_vc0 ( tx_ca_cpl_recheck_vc0 ),
.rx_data_vc0 ( rx_data_vc0),
.rx_st_vc0 ( rx_st_vc0),
.rx_end_vc0 ( rx_end_vc0),
.rx_us_req_vc0 ( rx_us_req_vc0 ),
.rx_malf_tlp_vc0 ( rx_malf_tlp_vc0 ),
.rx_bar_hit ( rx_bar_hit ),
.mm_enable ( mm_enable ),
.msi_enable ( msi_enable ),
// From Config Registers
.bus_num ( bus_num ) ,
.dev_num ( dev_num ) ,
.func_num ( func_num ) ,
.pm_power_state ( pm_power_state ) ,
.pme_en ( pme_en ) ,
.cmd_reg_out ( cmd_reg_out ),
.dev_cntl_out ( dev_cntl_out ),
.lnk_cntl_out ( lnk_cntl_out ),
// To ASPM implementation outside the IP
.tx_rbuf_empty ( tx_rbuf_empty ),
.tx_dllp_pend ( tx_dllp_pend ),
.rx_tlp_rcvd ( rx_tlp_rcvd ),
// Datal Link Control SM Status
.dl_inactive ( dl_inactive ),
.dl_init ( dl_init ),
.dl_active ( dl_active ),
.dl_up ( dl_up )
);
endmodule |
module sky130_fd_sc_ls__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module pipeline_CPU (
input clk,
input rst,
input[`RegDataWidth-1:0] data_from_mem,
output[`MemAddrWidth-1:0] mem_addr,
output[3:0] mem_byte_slct,
output[`RegDataWidth-1:0] data_to_write_mem,
output mem_we,
output mem_re,
input[`InstDataWidth-1:0] inst_from_rom,
output[`InstAddrWidth-1:0] rom_addr,
output rom_ce
);
supply1 vcc;
supply0 gnd;
// Forwarding wire
wire[1:0] FWA;
wire[1:0] FWB;
wire[1:0] FWhi;
wire[1:0] FWlo;
wire FWLS;
wire[1:0] FW_br_A;
wire[1:0] FW_br_B;
// branch control wire
wire[`InstAddrWidth-1:0] branch_address;
wire is_branch;
wire is_rst_IF_ID;
// Hazard Control wire
wire is_hold_IF;
wire is_hold_IF_ID;
wire is_zeros_ID_EX;
wire[`InstAddrWidth-1:0] pc_plus4_IF;
wire[`InstDataWidth-1:0] inst_ID;
wire[`InstAddrWidth-1:0] pc_plus4_ID;
IF inst_fetch(.clk (clk),
.rst (rst),
.is_hold (is_hold_IF),
.is_branch(is_branch),
.branch_address(branch_address),
.ce(rom_ce),
.pc(rom_addr),
.pc_plus4(pc_plus4_IF)
);
wire IF_ID_controlor;
mux2x1 IF_ID_control(
.in_0(rst),
.in_1(vcc),
.slct(is_rst_IF_ID),
.out(IF_ID_controlor)
);
IF_ID if_id_reg(
.clk (clk),
.rst (IF_ID_controlor),
.is_hold (is_hold_IF_ID),
.pc_plus4_IF(pc_plus4_IF),
.inst_IF (inst_from_rom),
.pc_plus4_ID(pc_plus4_ID),
.inst_ID (inst_ID)
);
wire[`RegAddrWidth-1:0] raddr_1_ID;
wire[`RegDataWidth-1:0] rdata_1_ID;
wire[`RegAddrWidth-1:0] raddr_2_ID;
wire[`RegDataWidth-1:0] rdata_2_ID;
wire[`RegDataWidth-1:0] shamt_ID;
wire WriteReg_ID;
wire MemOrAlu_ID;
wire WriteMem_ID;
wire ReadMem_ID;
wire[`ALUTypeWidth-1:0] AluType_ID;
wire[`ALUOpWidth-1:0] AluOp_ID;
wire AluSrcA_ID;
wire AluSrcB_ID;
wire RegDes_ID;
wire ImmSigned_ID;
wire is_jal_ID;
wire[`RegAddrWidth-1:0] rt_ID;
wire[`RegAddrWidth-1:0] rd_ID;
wire[`RegDataWidth-1:0] imm_signed_ID;
wire[`RegDataWidth-1:0] imm_unsigned_ID;
wire[`OpcodeWidth-1:0] opcode_ID;
ID inst_decode(
.rst(rst),
.pc_plus4(pc_plus4_ID),
.inst(inst_ID),
.reg1_addr(raddr_1_ID),
.reg2_addr(raddr_2_ID),
.WriteReg(WriteReg_ID),
.MemOrAlu(MemOrAlu_ID),
.WriteMem(WriteMem_ID),
.ReadMem(ReadMem_ID),
.AluType(AluType_ID),
.AluOp(AluOp_ID),
.AluSrcA(AluSrcA_ID),
.AluSrcB(AluSrcB_ID),
.RegDes(RegDes_ID),
.ImmSigned(ImmSigned_ID),
.opcode(opcode_ID),
.rt(rt_ID),
.rd(rd_ID),
.imm_signed(imm_signed_ID),
.imm_unsigned(imm_unsigned_ID),
.shamt(shamt_ID),
.is_jal(is_jal_ID)
);
wire[`RegAddrWidth-1:0] reg_write_addr;
wire[`RegDataWidth-1:0] reg_write_data;
wire reg_we;
wire we_hi;
wire[`RegDataWidth-1:0] hi_data_in;
wire we_lo;
wire[`RegDataWidth-1:0] lo_data_in;
wire[`RegDataWidth-1:0] hi_data_out_ID;
wire[`RegDataWidth-1:0] lo_data_out_ID;
wire[`RegDataWidth-1:0] hi_data_to_EX;
wire[`RegDataWidth-1:0] lo_data_to_EX;
// force read regfile
regfile regs(
.clk(clk),
.rst(rst),
.waddr(reg_write_addr),
.wdata(reg_write_data),
.we(reg_we),
.re1(vcc),
.raddr_1(raddr_1_ID),
.rdata_1(rdata_1_ID),
.re2(vcc),
.raddr_2(raddr_2_ID),
.rdata_2(rdata_2_ID)
);
hilo_reg hilo_regs(
.clk(clk),
.rst(rst),
.we_hi(we_hi),
.hi_data_in(hi_data_in),
.we_lo(we_lo),
.lo_data_in(lo_data_in),
.hi_data_out(hi_data_out_ID),
.lo_data_out(lo_data_out_ID)
);
wire WriteReg_EX;
wire MemOrAlu_EX;
wire WriteMem_EX;
wire ReadMem_EX;
wire[`ALUTypeWidth-1:0] AluType_EX;
wire[`ALUOpWidth-1:0] AluOp_EX;
wire AluSrcA_EX;
wire AluSrcB_EX;
wire RegDes_EX;
wire ImmSigned_EX;
wire is_jal_EX;
wire[`RegAddrWidth-1:0] rt_EX;
wire[`RegAddrWidth-1:0] rd_EX;
wire[`RegDataWidth-1:0] imm_signed_EX;
wire[`RegDataWidth-1:0] imm_unsigned_EX;
wire[`OpcodeWidth-1:0] opcode_EX;
wire[`RegDataWidth-1:0] rdata_1_EX;
wire[`RegDataWidth-1:0] rdata_2_EX;
wire[`RegAddrWidth-1:0] raddr_1_EX;
wire[`RegAddrWidth-1:0] raddr_2_EX;
wire[`RegDataWidth-1:0] shamt_EX;
wire[`InstAddrWidth-1:0] pc_plus4_EX;
wire ID_EX_controlor;
mux2x1 ID_EX_control(
.in_0(rst),
.in_1(vcc),
.slct(is_zeros_ID_EX),
.out(ID_EX_controlor)
);
ID_EX id_ex_reg(
.clk(clk),
.rst(ID_EX_controlor),
.is_hold(gnd),
.rdata_1_ID(rdata_1_ID),
.rdata_2_ID(rdata_2_ID),
.raddr_1_ID(raddr_1_ID),
.raddr_2_ID(raddr_2_ID),
.shamt_ID(shamt_ID),
.WriteReg_ID(WriteReg_ID),
.MemOrAlu_ID(MemOrAlu_ID),
.WriteMem_ID(WriteMem_ID),
.ReadMem_ID(ReadMem_ID),
.AluType_ID(AluType_ID),
.AluOp_ID(AluOp_ID),
.AluSrcA_ID(AluSrcA_ID),
.AluSrcB_ID(AluSrcB_ID),
.RegDes_ID(RegDes_ID),
.ImmSigned_ID(ImmSigned_ID),
.is_jal_ID(is_jal_ID),
.rt_ID(rt_ID),
.rd_ID(rd_ID),
.imm_signed_ID(imm_signed_ID),
.imm_unsigned_ID(imm_unsigned_ID),
.opcode_ID(opcode_ID),
.hi_ID(hi_data_out_ID),
.lo_ID(lo_data_out_ID),
.pc_plus4_ID(pc_plus4_ID),
.rdata_1_EX(rdata_1_EX),
.rdata_2_EX(rdata_2_EX),
.raddr_1_EX(raddr_1_EX),
.raddr_2_EX(raddr_2_EX),
.shamt_EX(shamt_EX),
.WriteReg_EX(WriteReg_EX),
.MemOrAlu_EX(MemOrAlu_EX),
.ReadMem_EX(ReadMem_EX),
.WriteMem_EX(WriteMem_EX),
.AluType_EX(AluType_EX),
.AluOp_EX(AluOp_EX),
.AluSrcA_EX(AluSrcA_EX),
.AluSrcB_EX(AluSrcB_EX),
.RegDes_EX(RegDes_EX),
.ImmSigned_EX(ImmSigned_EX),
.is_jal_EX(is_jal_EX),
.rt_EX(rt_EX),
.rd_EX(rd_EX),
.imm_signed_EX(imm_signed_EX),
.imm_unsigned_EX(imm_unsigned_EX),
.opcode_EX(opcode_EX),
.hi_EX(hi_data_to_EX),
.lo_EX(lo_data_to_EX),
.pc_plus4_EX(pc_plus4_EX)
);
wire[`RegAddrWidth-1:0] target_EX;
wire is_Overflow;
wire[`RegDataWidth-1:0] data_out_EX;
wire we_hi_EX;
wire we_lo_EX;
wire[`RegDataWidth-1:0] hi_EX;
wire[`RegDataWidth-1:0] lo_EX;
wire[`RegDataWidth-1:0] rdata_2_EX_out;
wire[`RegDataWidth-1:0] hi_MEM;
wire[`RegDataWidth-1:0] lo_MEM;
wire[`RegDataWidth-1:0] data_from_ALU_MEM;
EX execution(
.rst(rst),
.shamt(shamt_EX),
.AluType_EX(AluType_EX),
.AluOp_EX(AluOp_EX),
.AluSrcA_EX(AluSrcA_EX),
.AluSrcB_EX(AluSrcB_EX),
.RegDes_EX(RegDes_EX),
.ImmSigned_EX(ImmSigned_EX),
.is_jal_EX(is_jal_EX),
.rt_EX(rt_EX),
.rd_EX(rd_EX),
.imm_signed_EX(imm_signed_EX),
.imm_unsigned_EX(imm_unsigned_EX),
.hi(hi_data_to_EX),
.lo(lo_data_to_EX),
.rdata_1(rdata_1_EX),
.rdata_2(rdata_2_EX),
.pc_plus4_EX(pc_plus4_EX),
// forwarding data in
.data_out_MEM(data_from_ALU_MEM),
.data_out_WB(reg_write_data),
.hi_MEM(hi_MEM),
.hi_WB(hi_data_in),
.lo_MEM(lo_MEM),
.lo_WB(lo_data_in),
.FWA(FWA),
.FWB(FWB),
.FWhi(FWhi),
.FWlo(FWlo),
.target_EX(target_EX),
.is_Overflow(is_Overflow),
.data_out_EX(data_out_EX),
.rdata_2_EX(rdata_2_EX_out),
.hi_EX(hi_EX),
.lo_EX(lo_EX),
.we_hi(we_hi_EX),
.we_lo(we_lo_EX)
);
wire[`RegAddrWidth-1:0] target_MEM;
wire we_hi_MEM;
wire we_lo_MEM;
wire[`RegDataWidth-1:0] rdata_2_MEM;
wire[`RegAddrWidth-1:0] raddr_2_MEM;
wire WriteReg_MEM;
wire MemOrAlu_MEM;
wire WriteMem_MEM;
wire ReadMem_MEM;
wire[`OpcodeWidth-1:0] opcode_MEM;
EX_MEM ex_mem_reg(
.clk(clk),
.rst(rst),
// set gnd temporarily
.is_hold(gnd),
.target_EX(target_EX),
.data_out_EX(data_out_EX),
.we_hi_EX(we_hi_EX),
.we_lo_EX(we_lo_EX),
.hi_EX(hi_EX),
.lo_EX(lo_EX),
.raddr_2_EX(raddr_2_EX),
.rdata_2_EX(rdata_2_EX_out),
.WriteReg_EX(WriteReg_EX),
.MemOrAlu_EX(MemOrAlu_EX),
.WriteMem_EX(WriteMem_EX),
.ReadMem_EX(ReadMem_EX),
.opcode_EX(opcode_EX),
.target_MEM(target_MEM),
.data_from_ALU_MEM(data_from_ALU_MEM),
.we_hi_MEM(we_hi_MEM),
.we_lo_MEM(we_lo_MEM),
.hi_MEM(hi_MEM),
.lo_MEM(lo_MEM),
.raddr_2_MEM(raddr_2_MEM),
.rdata_2_MEM(rdata_2_MEM),
.WriteReg_MEM(WriteReg_MEM),
.MemOrAlu_MEM(MemOrAlu_MEM),
.WriteMem_MEM(WriteMem_MEM),
.ReadMem_MEM(ReadMem_MEM),
.opcode_MEM(opcode_MEM)
);
wire[`RegDataWidth-1:0] MEM_data_MEM;
// memory read/write
MEM mem(
.rst(rst),
.FWLS(FWLS),
.reg_data_2(rdata_2_MEM),
.WB_data(reg_write_data),
.raw_mem_data(data_from_mem),
.ReadMem(ReadMem_MEM),
.WriteMem(WriteMem_MEM),
.mem_addr(data_from_ALU_MEM),
.opcode(opcode_MEM),
.data_to_write_mem(data_to_write_mem),
.data_to_reg(MEM_data_MEM),
.byte_slct(mem_byte_slct)
);
assign mem_addr = data_from_ALU_MEM;
assign mem_re = ReadMem_MEM;
assign mem_we = WriteMem_MEM;
wire[`RegDataWidth-1:0] ALU_data_WB;
wire[`RegDataWidth-1:0] MEM_data_WB;
MEM_WB mem_wb_reg(
.clk(clk),
.rst(rst),
// set gnd temporarily
.is_hold(gnd),
.target_MEM(target_MEM),
.ALU_data_MEM(data_from_ALU_MEM),
.MEM_data_MEM(MEM_data_MEM),
.we_hi_MEM(we_hi_MEM),
.we_lo_MEM(we_lo_MEM),
.hi_MEM(hi_MEM),
.lo_MEM(lo_MEM),
.WriteReg_MEM(WriteReg_MEM),
.MemOrAlu_MEM(MemOrAlu_MEM),
.target_WB(reg_write_addr),
.ALU_data_WB(ALU_data_WB),
.MEM_data_WB(MEM_data_WB),
.we_hi_WB(we_hi),
.we_lo_WB(we_lo),
.hi_WB(hi_data_in),
.lo_WB(lo_data_in),
.WriteReg_WB(reg_we),
.MemOrAlu_WB(MemOrAlu_WB)
);
// See define.v
// MemOrAlu
// `define ALU 1'b1
// `define Mem 1'b0
mux2x1 #(.data_width(`RegDataWidth)) result_mux(
.in_0(MEM_data_WB),
.in_1(ALU_data_WB),
.slct(MemOrAlu_WB),
.out(reg_write_data)
);
// Control center
ForwardControl forwarding_handler(
.rst(rst),
.reg_data_1_addr_ID(raddr_1_ID),
.reg_data_2_addr_ID(raddr_2_ID),
.reg_data_1_addr_EX(raddr_1_EX),
.reg_data_2_addr_EX(raddr_2_EX),
.target_EX(target_EX),
.WriteReg_EX(WriteReg_EX),
.reg_data_2_addr_MEM(raddr_2_MEM),
.target_MEM(target_MEM),
.WriteReg_MEM(WriteReg_MEM),
.MemOrAlu_MEM(MemOrAlu_MEM),
.we_hi_MEM(we_hi_MEM),
.we_lo_MEM(we_lo_MEM),
.target_WB(reg_write_addr),
.WriteReg_WB(reg_we),
.we_hi_WB(we_hi),
.we_lo_WB(we_lo),
.FWA(FWA),
.FWB(FWB),
.FWhi(FWhi),
.FWlo(FWlo),
.FWLS(FWLS),
.FW_br_A(FW_br_A),
.FW_br_B(FW_br_B)
);
BranchControl branch_handler(
.rst(rst),
.pc_plus4_ID(pc_plus4_ID),
.inst_ID(inst_ID),
.FW_br_A(FW_br_A),
.FW_br_B(FW_br_B),
.rdata_1_ID(rdata_1_ID),
.rdata_2_ID(rdata_2_ID),
.data_out_EX(data_out_EX),
.data_from_ALU_MEM(data_from_ALU_MEM),
.MEM_data_MEM(MEM_data_MEM),
.branch_address(branch_address),
.is_branch(is_branch),
.is_rst_IF_ID(is_rst_IF_ID)
);
HazardControl hazard_handler(
.rst(rst),
.ReadMem_EX(ReadMem_EX),
.WriteMem_ID(WriteMem_ID),
.raddr_1_ID(raddr_1_ID),
.raddr_2_ID(raddr_2_ID),
.target_EX(target_EX),
.is_hold_IF(is_hold_IF),
.is_hold_IF_ID(is_hold_IF_ID),
.is_zeros_ID_EX(is_zeros_ID_EX)
);
endmodule |
module
mulAddRecF16_add (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags,
output [15:0] out_imul
);
wire [16:0] recF16_1 = 'h08000;
mulAddRecFN#(5, 11)
mulAddRecFN(
control, {int_mul, 2'b0}, a, recF16_1, b, roundingMode, out, exceptionFlags, out_imul);
endmodule |
module
mulAddRecF32_add (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags,
output [31:0] out_imul
);
wire [32:0] recF32_1 = 33'h080000000;
mulAddRecFN#(8, 24)
mulAddRecFN(
control, {int_mul, 2'b0}, a, recF32_1, b, roundingMode, out, exceptionFlags, out_imul);
endmodule |
module
mulAddRecF64_add (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags,
output [63:0] out_imul
);
wire [64:0] recF64_1 = 65'h08000000000000000;
mulAddRecFN#(11, 53)
mulAddRecFN(
control, {int_mul, 2'b0}, a, recF64_1, b, roundingMode, out, exceptionFlags, out_imul);
endmodule |
module
mulAddRecF128_add (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [127:0] out_imul;
wire [128:0] recF128_1 = 129'h080000000000000000000000000000000;
mulAddRecFN#(15, 113, 0)
mulAddRecFN(
control, 3'b0, a, recF128_1, b, roundingMode, out, exceptionFlags, out_imul
);
endmodule |
module
mulAddRecF16_mul (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags,
output [15:0] out_imul
);
wire [16:0] zeroAddend = {a[16] ^ b[16], 16'b0};
mulAddRecFN#(5, 11)
mulAddRecFN(
control, {int_mul, 2'b0}, a, b, zeroAddend, roundingMode, out, exceptionFlags, out_imul
);
endmodule |
module
mulAddRecF32_mul (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags,
output [31:0] out_imul
);
wire [32:0] zeroAddend = {a[32] ^ b[32], 32'b0};
mulAddRecFN#(8, 24)
mulAddRecFN(
control, {int_mul, 2'b0}, a, b, zeroAddend, roundingMode, out, exceptionFlags, out_imul
);
endmodule |
module
mulAddRecF64_mul (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags,
output [63:0] out_imul
);
wire [64:0] zeroAddend = {a[64] ^ b[64], 64'b0};
mulAddRecFN#(11, 53)
mulAddRecFN(
control, {int_mul, 2'b0}, a, b, zeroAddend, roundingMode, out, exceptionFlags, out_imul
);
endmodule |
module
mulAddRecF128_mul (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [128:0] zeroAddend = {a[128] ^ b[128], 128'b0};
wire [127:0] out_imul;
mulAddRecFN#(15, 113, 0)
mulAddRecFN(
control, 3'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags,out_imul
);
endmodule |
module
mulAddRecF16 (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [2:0] op,
input [16:0] a,
input [16:0] b,
input [16:0] c,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags,
output [15:0] out_imul
);
mulAddRecFN#(5, 11)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul);
endmodule |
module
mulAddRecF32 (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [2:0] op,
input [32:0] a,
input [32:0] b,
input [32:0] c,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags,
output [31:0] out_imul
);
mulAddRecFN#(8, 24)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul);
endmodule |
module
mulAddRecF64 (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [2:0] op,
input [64:0] a,
input [64:0] b,
input [64:0] c,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags,
output [63:0] out_imul
);
mulAddRecFN#(11, 53)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul);
endmodule |
module
mulAddRecF128 (
input [(`floatControlWidth - 1):0] control,
input [2:0] op,
input [128:0] a,
input [128:0] b,
input [128:0] c,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [127:0] out_imul;
mulAddRecFN#(15, 113)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul);
endmodule |
module sky130_fd_sc_lp__dlygate4s50 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module wb_mux (sys_clk,
resetcpu,
// High priority bus
h_cyc,
h_stb,
h_we,
h_sel,
h_ack,
h_adr,
h_dat_o,
h_dat_i,
// Low priority bus
l_cyc,
l_stb,
l_we,
l_sel,
l_ack,
l_adr,
l_dat_o,
l_dat_i,
// Muxed bus
m_cyc,
m_stb,
m_we,
m_sel,
m_ack,
m_adr,
m_dat_o,
m_dat_i
);
input sys_clk;
input resetcpu;
input h_cyc;
input h_stb;
input h_we;
input [3:0] h_sel;
input [31:0] h_adr;
input [31:0] h_dat_o; // An input, but matches name of LM32 interface
output [31:0] h_dat_i; // An output, but matches name of LM32 interface
output h_ack;
input l_cyc;
input l_stb;
input l_we;
input [3:0] l_sel;
input [31:0] l_adr;
input [31:0] l_dat_o; // An input, but matches name of LM32 interface
output [31:0] l_dat_i; // An output, but matches name of LM32 interface
output l_ack;
output m_cyc;
output m_stb;
output m_we;
output [3:0] m_sel;
output [31:0] m_adr;
output [31:0] m_dat_o;
input [31:0] m_dat_i;
input m_ack;
reg active;
reg h_owns_bus_reg;
// Select high priority bus, if bus inactive and high priority bus
// requesting, or (when active), it is the selected bus.
wire sel_h = (h_cyc & ~active) | (h_owns_bus_reg & active);
// Mux the outputs from the two busses
assign m_cyc = h_cyc | l_cyc;
assign m_stb = sel_h ? h_stb : l_stb;
assign m_we = sel_h ? h_we : l_we;
assign m_sel = sel_h ? h_sel : l_sel;
assign m_adr = sel_h ? h_adr : l_adr;
assign m_dat_o = sel_h ? h_dat_o : l_dat_o;
// Route read data back to sources (regardless of bus selection)
assign h_dat_i = m_dat_i;
assign l_dat_i = m_dat_i;
// Route ACK back to selected bus.
// Using h_owns_bus_reg assumes there can be no ACK earlier than the
// next cycle. If ACK can be in the same cycle as assertion of m_cyc,
// then sel_h should be used, but this has slow timing and could, potentially,
// create a timing loop, as ack would then be dependant on <x>_cyc.
assign h_ack = h_owns_bus_reg & m_ack;
assign l_ack = ~h_owns_bus_reg & m_ack;
always @(posedge sys_clk or posedge resetcpu)
begin
if (resetcpu == 1'b1)
begin
active <= 1'b0;
h_owns_bus_reg <= 1'b0;
end
else
begin
// Go active (and hold) if either bus requesting, clearing state on the returned ACK
active <= (active | h_cyc | l_cyc) & ~m_ack;
// Flag high priority bus ownership, and hold, or if that bus requesting and inactive.
h_owns_bus_reg <= (active & h_owns_bus_reg) | (~active & h_cyc);
end
end
endmodule |
module okWireIn_sync (
input wire clk,
input wire okClk,
input wire [112:0] okHE,
input wire [7:0] ep_addr,
output reg [31:0] ep_dataout
);
wire [31:0] control_bus;
wire [31:0] q_buff;
wire rdempty;
reg rdreq;
always @( posedge clk ) begin
if ( rdreq ) begin
ep_dataout <= q_buff;
end
rdreq <= ~rdempty;
end
fifo32_shallow fifo32_shallow_inst (
.data ( control_bus ),
.rdclk ( clk ),
.rdreq ( rdreq ),
.wrclk ( okClk ),
.wrreq ( 1'b1 ),
.q ( q_buff ),
.rdempty ( rdempty ),
.wrfull ( )
);
okWireIn control_wires(
.okHE(okHE),
.ep_addr(ep_addr),
.ep_dataout(control_bus)
);
endmodule |
module pipeline(
input Clk,
output [31:0] PC_in,PC_out,
output [2:0]PCSrc,
//1
/*output[5:0] Op_IF,
output[4:0] Rs_IF,Rt_IF,Rd_IF,Shamt_IF,
output[5:0] Func_IF,
*/
//3
/*output[31:0] Branch_addr_EX,PC_Add_EX,
output[2:0] Condition_EX,
output Branch_EX,
output[2:0]PC_write_EX,
output[3:0]Mem_Write_Byte_en_EX,Rd_Write_Byte_en_EX,
output MemWBSrc_EX,OverflowEn_EX,
output[31:0] MemData_EX,WBData_EX,
output Less_EX,Zero_EX,Overflow_EX,
output[4:0]Rd_EX,
output flash_ID,flash_EX,
//4
output[31:0] MemData_Mem,Data_out,
output[31:0] WBData_Mem,
output MemWBSrc_Mem,
output[3:0] Rd_Write_Byte_en_Mem,
output[4:0] Rd_Mem,
output [31:0] Immediate32_IF,ALU_OpA,ALU_OpB,ALU_out,RegShift,
output [1:0] Rs_EX_Forward,Rt_EX_Forward,
output [4:0]ShiftAmount
*/
output flash_ID,flash_EX,
output [31:0] OperandA_ID,OperandB_ID,
output [4:0] Rs_ID,Rt_ID,Rd_ID,Rd_EX,Rd_Mem,
output [31:0] Immediate32_ID,
output [2:0] MemDataSrc_ID,
output ALUSrcA_ID,ALUSrcB_ID,Jump_ID,
output [3:0] ALUOp_ID,Rd_Write_Byte_en_Mem,MemWriteEn,RdWriteEn,
output [31:0] IR_IF,Shifter_out,Rd_in,MemData_EX,Data_out,WBData_EX,
output [4:0]ShiftAmount,
output [1:0] Rs_EX_Forward,Rt_EX_Forward,
output [31:0] Immediate32_IF,ALU_OpA,ALU_OpB,ALU_out,RegShift
);
//--------Harzard----------------------------------
//wire[2:0] PCSrc;
//--------PC---------------------------------------
//wire[31:0] PC_in,PC_out;
//--------PC+4-------------------------------------
wire[31:0] PC_Add_IF;
//--------InstruMemory-----------------------------
wire[31:0] ins_data;//,IR_IF;
//--------IF_ID Seg1-------------------------------
wire stall_IF;
wire flash_IF;
wire[5:0] Op_IF;
wire[4:0] Rs_IF,Rt_IF,Rd_IF,Shamt_IF;
wire[5:0] Func_IF;
//--------Controller-------------------------------
wire RegDt0_IF,ID_RsRead_IF,ID_RtRead_IF;
wire[1:0] Ex_top_IF;
wire BranchSel_IF;
wire OverflowEn_IF;
wire[2:0] Condition_IF;
wire Branch_IF;
wire[2:0] PC_write_IF;
wire[3:0] Mem_Write_Byte_en_IF,Rd_Write_Byte_en_IF,ALUOp_IF;
wire MemWBSrc_IF;
wire Jump_IF;
wire ALUShiftSel_IF;
wire[2:0] MemDataSrc_IF;
wire ALUSrcA_IF,ALUSrcB_IF;
//wire[3:0] ALUOp_IF;
wire[1:0] RegDst_IF;
wire ShiftAmountSrc_IF;
wire[1:0] Shift_Op_IF;
//---------Registers-------------------------------
wire[31:0] Rs_out,Rt_out;//Rd_in
//---------expansion-------------------------------
//wire[31:0] Immediate32_IF;
//---------ID_EX Seg2------------------------------
wire stall_ID;//flash_ID,
wire[31:0]PC_Add_ID;
wire OverflowEn_ID;
wire[2:0] Condition_ID;
wire Branch_ID,EX_RsRead_ID,EX_RtRead_ID;
wire[2:0] PC_write_ID;
wire[3:0] Mem_Write_Byte_en_ID,Rd_Write_Byte_en_ID;
wire MemWBSrc_ID,ALUShiftSel_ID;
//wire[2:0] MemDataSrc_ID;
//wire ALUSrcA_ID,ALUSrcB_ID;
//wire[3:0] ALUOp_ID;
wire[1:0] RegDst_ID;
wire ShiftAmountSrc_ID;
wire[1:0] Shift_Op_ID;
//wire[31:0] OperandA_ID,OperandB_ID;
//wire[4:0] Rs_ID,Rt_ID,Rd_ID;
//wire[31:0] Immediate32_ID;
wire[4:0]Shamt_ID;
//----------JUMP branch---------------------------
wire[31:0] Branch_addr_ID,Jump_Done;
//----------Forward-------------------------------
//wire[1:0] Rs_EX_Forward,Rt_EX_Forward;
wire Rs_LoudUse_Forward,Rt_LoudUse_Forward;
//----------After ALU and ID/EX mux---------------
wire[31:0] mux4one,mux4two,mux4three,mux8one;
wire Zero,Less,Overflow,BranchSel_ID;
//wire[31:0] ALU_out;
//----------Shifter-------------------------------
//wire[31:0] Shifter_out;
//wire [4:0]ShiftAmount;
//----------Ex_MEM Seg3--------------------------
wire stall_EX;//flash_EX
wire OverflowEn_EX;
wire[31:0] Branch_addr_EX,PC_Add_EX;
wire[2:0] Condition_EX;
wire Branch_EX,MemWBSrc_EX;
wire[2:0]PC_write_EX;
wire[3:0]Mem_Write_Byte_en_EX,Rd_Write_Byte_en_EX;
//wire[31:0] WBData_EX;//MemData_EX,
wire Less_EX,Zero_EX,Overflow_EX;
//wire[4:0]Rd_EX;
//----------Condition------------------------------
wire BranchValid;
//wire[3:0] RdWriteEn;//,MemWriteEn;
//----------DataMemory-----------------------------
wire [31:0]Mem_data_shift;
//----------MEM_WB Seg4---------------------------
wire stall_Mem,flash_Mem;
wire[31:0] MemData_Mem;
wire[31:0] WBData_Mem;
wire MemWBSrc_Mem;
//wire[3:0] Rd_Write_Byte_en_Mem;
//wire[4:0] Rd_Mem;
//-----------------------------------------------Hazard-------------------------------------------------------
HazardControl hazard(BranchValid,Jump_ID,MemWBSrc_ID,ID_RsRead_IF,ID_RtRead_IF,Rs_IF,Rt_IF,Rt_ID,
//output
stall_IF,stall_ID,stall_EX,stall_Mem,flash_IF,flash_ID,flash_EX,flash_Mem,PCSrc);
//-------------------------------------------------PC---------------------------------------------------------
wire[31:0] PC_Add_IF_in;
Mux4_1 PC_selcet(PC_Add_IF,Jump_Done,Branch_addr_EX,mux4one,PCSrc,PC_in);
PC pc(Clk,PC_in,PC_out);
//------------------------------------------------PC+4---------------------------------------------------------
assign PC_Add_IF_in = PC_out + 4;
//---------------------------------------------InstructMemory--------------------------------------------------
parameter ins_we = 4'b0000;
assign ins_data = 0;
InstruMemory instruct(ins_data,PC_out,ins_we,Clk,IR_IF);
//----------------------------------------------IF_ID_Seg Seg1-------------------------------------------------
IF_ID_Seg Seg1(Clk,stall_IF,flash_IF,PC_Add_IF_in,IR_IF,PC_Add_IF,Op_IF,Rs_IF,Rt_IF,Rd_IF,Shamt_IF,Func_IF);
//----------------------------------------------Controller-----------------------------------------------------
Controller controller(Op_IF,Rs_IF,Rt_IF,Rd_IF,Shamt_IF,Func_IF,RegDt0_IF,ID_RsRead_IF,ID_RtRead_IF,Ex_top_IF,BranchSel_IF,
OverflowEn_IF,Condition_IF,Branch_IF,PC_write_IF,Mem_Write_Byte_en_IF,Rd_Write_Byte_en_IF,MemWBSrc_IF,Jump_IF,
ALUShiftSel_IF,MemDataSrc_IF,ALUSrcA_IF,ALUSrcB_IF,ALUOp_IF,RegDst_IF,ShiftAmountSrc_IF,Shift_Op_IF);
//----------------------------------------------Registers------------------------------------------------------
assign Rd_in = (MemWBSrc_Mem == 0)?WBData_Mem:MemData_Mem;
MIPS_Register mipsregister(Rs_IF,((RegDt0_IF == 1'b1)?Rt_IF:5'b00000),Rd_Mem,Clk,Rd_Write_Byte_en_Mem,Rd_in,Rs_out,Rt_out);
//--------------------------------------------expansion--------------------------------------------------------
NumExpansion expansion({Rd_IF[4:0],Shamt_IF[4:0],Func_IF[5:0]},Ex_top_IF,Immediate32_IF);
//------------------------------------------ID_EX Seg2-------------------------------------------------------
ID_EX_Seg seg2(Clk,stall_ID,flash_ID,PC_Add_IF,OverflowEn_IF,Condition_IF,Branch_IF,PC_write_IF,
Mem_Write_Byte_en_IF,Rd_Write_Byte_en_IF,MemWBSrc_IF,Jump_IF,ALUShiftSel_IF,MemDataSrc_IF,ALUSrcA_IF,ALUSrcB_IF,
ALUOp_IF,RegDst_IF,ShiftAmountSrc_IF,Shift_Op_IF,(Rs_LoudUse_Forward == 0)?Rs_out:Rd_in,
(Rt_LoudUse_Forward == 0)?Rt_out:Rd_in,Rs_IF,Rt_IF,Rd_IF,Immediate32_IF,Shamt_IF,BranchSel_IF,
{ID_RsRead_IF,ID_RtRead_IF},
//output
PC_Add_ID,OverflowEn_ID,Condition_ID,Branch_ID,PC_write_ID,Mem_Write_Byte_en_ID,Rd_Write_Byte_en_ID,
MemWBSrc_ID,Jump_ID,ALUShiftSel_ID,MemDataSrc_ID,ALUSrcA_ID,ALUSrcB_ID,
ALUOp_ID,RegDst_ID,ShiftAmountSrc_ID,Shift_Op_ID,OperandA_ID,OperandB_ID,Rs_ID,Rt_ID,Rd_ID,Immediate32_ID,Shamt_ID,
BranchSel_ID,{EX_RsRead_ID,EX_RtRead_ID}
);
//----------------------------------------JUMP branch Module---------------------------------------------------
assign Branch_addr_ID = PC_Add_ID + {Immediate32_ID[29:0],2'b00};
assign Jump_Done = {PC_Add_ID[31:28],Rs_ID,Rt_ID,Immediate32_ID[15:0],2'b00};
//-----------------------------------------forward-------------------------------------------------------------
Forward forward({EX_RsRead_ID,EX_RtRead_ID},Rt_ID,Rs_ID,Rd_EX,RdWriteEn,Rd_Mem,Rd_Write_Byte_en_Mem,
//output
Rs_EX_Forward,Rt_EX_Forward,
//input
Rt_IF,Rs_IF,{ID_RsRead_IF,ID_RtRead_IF},
//output
Rs_LoudUse_Forward,Rt_LoudUse_Forward);
//--------------------------------------after ALU and ID/EX Mux------------------------------------------------
Mux4_1 mux4_one(OperandA_ID,WBData_EX,Rd_in,0,Rs_EX_Forward,mux4one);
Mux4_1 mux4_two(OperandB_ID,WBData_EX,Rd_in,0,Rt_EX_Forward,mux4two);
Mux4_1 mux4_three(Rd_ID,Rt_ID,5'b11111,0,RegDst_ID,mux4three);
MUX8_1_ALU mux8_one(MemDataSrc_ID,32'b0,mux4two,PC_Add_ID + 4,0,0,0,0,0,mux8one); //rt
assign ALU_OpA = (ALUSrcA_ID == 0)?mux4one:0;
assign ALU_OpB = (ALUSrcB_ID == 0)?mux4two:Immediate32_ID;
ALU alu(ALU_OpA,ALU_OpB,ALUOp_ID,Zero,Less,Overflow,ALU_out);
assign ShiftAmount = (ShiftAmountSrc_ID == 1)?mux4one[4:0]:Shamt_ID;
//--------------------------------------------shifter-----------------------------------------------------------
MIPS_Shifter shifter(mux4two,ShiftAmount,Shift_Op_ID,Shifter_out);
//-----------------------------------------EX_MEM---Seg3--------------------------------------------------------
EX_MEM_Seg seg3(Clk,stall_EX,flash_EX,Branch_addr_ID,PC_Add_ID,Condition_ID,Branch_ID,PC_write_ID,
Mem_Write_Byte_en_ID,Rd_Write_Byte_en_ID,MemWBSrc_ID,OverflowEn_ID,
mux8one,((BranchSel_ID == 1'b0) ? ((ALUShiftSel_ID == 1'b0)?Shifter_out:ALU_out): mux8one),Less,Zero,Overflow,mux4three,
//output
Branch_addr_EX,PC_Add_EX,Condition_EX,Branch_EX,PC_write_EX,Mem_Write_Byte_en_EX,
Rd_Write_Byte_en_EX,MemWBSrc_EX,OverflowEn_EX,
MemData_EX,WBData_EX,Less_EX,Zero_EX,Overflow_EX,Rd_EX
);
//----------------------------------------Condition--------------------------------------------------------------
Condition_Check condition_check(Condition_EX,PC_write_EX,WBData_EX[1:0],MemWBSrc_EX,OverflowEn_EX,Branch_EX,Overflow_EX,Mem_Write_Byte_en_EX,Rd_Write_Byte_en_EX,Less_EX,Zero_EX,
//output
BranchValid,RdWriteEn,MemWriteEn);
//---------------------------------------DataMemory--------------------------------------------------------------
//wire [31:0] RegShift;
Register_ShiftOutput regshift(MemData_EX,WBData_EX[1:0],{3'b101,PC_write_EX[2:0]},RegShift);
DataMemory datamemory(RegShift,WBData_EX,MemWriteEn,Clk,Data_out);
Memory_ShiftOutput memshift(Data_out,WBData_EX[1:0],{3'b100,PC_write_EX[2:0]},Mem_data_shift);
//---------------------------------------DataMemoryWithCache-----------------------------------------------------
//------------------------------You can choose one section from DataMemory or DataMemory with cache--------------
/*wire hit;
wire [63:0] ReadRam;
wire writeback;
wire [7:0] readramn,writeramn;
Register_ShiftOutput regshift(MemData_EX,WBData_EX[1:0],{3'b101,PC_write_EX[2:0]},RegShift);
Cache DataMemorywithCache(RegShift,WBData_EX,MemWriteEn,Clk,Data_out,hit,ReadRam,writeback,readramn,writeramn);
Memory_ShiftOutput memshift(Data_out,WBData_EX[1:0],{3'b100,PC_write_EX[2:0]},Mem_data_shift);
*/
//--------------------------------------MEM_WB---Seg4------------------------------------------------------------
MEM_WB_Seg seg4(Clk,stall_Mem,flash_Mem,Mem_data_shift,WBData_EX,MemWBSrc_EX,RdWriteEn,Rd_EX,
//output
MemData_Mem,WBData_Mem,MemWBSrc_Mem,Rd_Write_Byte_en_Mem,Rd_Mem);
endmodule |
module sky130_fd_sc_hdll__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module cls_spi_tb;
// Inputs
reg clock;
reg reset;
reg [31:0] data;
reg miso;
// Outputs
wire ss;
wire mosi;
wire sclk;
// Instantiate the Unit Under Test (UUT)
cls_spi uut (
.clock(clock),
.reset(reset),
.data(data),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sclk(sclk)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
data = 32'h89ABCDEF;
miso = 0;
// Wait 100 ns for global reset to finish
#100 reset = 0;
end
always begin
#10 clock = !clock;
end
endmodule |
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule |
module sky130_fd_sc_ms__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule |
module single_bit_cdc_synchronizer #(
parameter NUM_STAGES = 3 // minimum 2 stages, recommended 3 stages
// probability of metastability decreases
// exponentially with #stages
) (
input clk, //latch clock
input d_in,
output q_out;
);
reg[NUM_STAGES-1:0] r;
assign q_out=r[NUM_STAGES-1];
integer i;
always@(posedge latch_clk)
begin
for(i=1; i<NUM_STAGES; i=i+1) begin
r[i] <= r[i-1];
end
end
endmodule |
module SPIMemoryTest;
// SPI interface.
reg _select, sck, mosi;
wire miso;
// Memory interface.
wire [`SPI_MEM_ADDR_WIDTH-1:0] addr;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_in;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_out;
wire rd, wr;
// Instantiate the Unit Under Test (UUT).
SPIMemory spi_memory(
._select(_select), .sck(sck), .mosi(mosi), .miso(miso),
.addr(addr), .data_in(data_in), .data_out(data_out), .rd(rd), .wr(wr)
);
// Don't have actual memory, so just use the lower byte of address as the data
// read from memory.
assign data_in = rd ? addr[`SPI_MEM_DATA_WIDTH-1:0] : 'bx;
initial begin
_select = 0;
sck = 0;
mosi = 0;
#1 _select = 1;
// Perform some writes.
#10
_select = 0;
spi_transmit(8'hde); // Write to address 0x5ead.
spi_transmit(8'had);
spi_transmit(8'h01); // These are the data bytes written.
spi_transmit(8'h02);
spi_transmit(8'h04);
spi_transmit(8'h08);
_select = 1;
#10
_select = 0;
spi_transmit(8'hbe); // Write to address 0x3eef.
spi_transmit(8'hef);
spi_transmit(8'h11); // These are the data bytes written.
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
// Perform some reads.
#10
_select = 0;
spi_transmit(8'h5a); // Read from address 0x5afe.
spi_transmit(8'hfe);
spi_transmit(8'h01); // These dummy data bytes should not show up.
spi_transmit(8'h02);
spi_transmit(8'h04);
spi_transmit(8'h08);
_select = 1;
#10
_select = 0;
spi_transmit(8'h7f); // Test wraparound during read.
spi_transmit(8'hfe);
spi_transmit(8'h11); // These dummy data bytes should not show up.
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
#10
_select = 0;
spi_transmit(8'hff); // Test wraparound during write.
spi_transmit(8'hfe);
spi_transmit(8'h11); // These dummy data bytes should not show up.
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
end
// Task to send a byte over SPI.
task spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
sck = 0;
#2
sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
mosi = data[`BYTE_WIDTH - 1 - i];
#1
sck = 1;
#1
sck = 0;
end
#2
sck = 0;
end
endtask
endmodule |
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
reg SLEEP;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
SLEEP = 1'bX;
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 SLEEP = 1'b0;
#40 UDP_IN = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 SLEEP = 1'b1;
#120 UDP_IN = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 SLEEP = 1'b0;
#200 UDP_IN = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 UDP_IN = 1'b1;
#320 SLEEP = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 UDP_IN = 1'bx;
#400 SLEEP = 1'bx;
end
sky130_fd_sc_lp__udp_pwrgood_pp$PG$S dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .SLEEP(SLEEP), .UDP_OUT(UDP_OUT));
endmodule |
module counter_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Datos de salida del contador
wire [26:0] data;
//-- Registro para comprobar si el contador cuenta correctamente
reg [26:0] counter_check = 1;
//-- Instanciar el contador
counter C1(
.clk(clk),
.data(data)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Comprobacion del valor del contador
//-- En cada flanco de bajada se comprueba la salida del contador
//-- y se incrementa el valor esperado
always @(negedge clk) begin
if (counter_check != data)
$display("-->ERROR!. Esperado: %d. Leido: %d",counter_check, data);
counter_check <= counter_check + 1;
end
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("counter_tb.vcd");
$dumpvars(0, counter_tb);
//-- Comprobación del reset.
# 0.5 if (data != 0)
$display("ERROR! Contador NO está a 0!");
else
$display("Contador inicializado. OK.");
# 99 $display("FIN de la simulacion");
# 100 $finish;
end
endmodule |
module sky130_fd_sc_hs__o41ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule |
module sky130_fd_sc_lp__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule |
module sky130_fd_sc_ms__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module bsg_channel_tunnel #(parameter width_p = 1
, parameter `BSG_INV_PARAM(num_in_p)
, parameter `BSG_INV_PARAM(remote_credits_p)
, use_pseudo_large_fifo_p = 0
, harden_small_fifo_p = 0
, lg_remote_credits_lp = $clog2(remote_credits_p+1)
, lg_credit_decimation_p = `BSG_MIN(lg_remote_credits_lp,4)
, tag_width_lp = $clog2(num_in_p+1)
, tagged_width_lp = tag_width_lp + width_p
)
(input clk_i
,input reset_i
// incoming multiplexed data
,input [tagged_width_lp-1:0] multi_data_i
,input multi_v_i
,output multi_yumi_o
// outgoing multiplexed data
, output [tagged_width_lp-1:0] multi_data_o
, output multi_v_o
, input multi_yumi_i
// incoming demultiplexed data
, input [num_in_p-1:0][width_p-1:0] data_i
, input [num_in_p-1:0] v_i
, output [num_in_p-1:0] yumi_o
// outgoing demultiplexed data
, output [num_in_p-1:0][width_p-1:0] data_o
, output [num_in_p-1:0] v_o
, input [num_in_p-1:0] yumi_i
);
// synopsys translate_off
initial
assert(lg_credit_decimation_p <= lg_remote_credits_lp)
else
begin
$error("%m bad params; insufficient remote credits 2^%d to allow for decimation factor 2^%d"
,lg_remote_credits_lp,lg_credit_decimation_p);
$finish;
end
initial
assert(width_p >= num_in_p*lg_remote_credits_lp)
else
begin
$error("%m bad params; channel width (%d) must be at least wide enough to route back credits (%d)"
,width_p
,num_in_p*lg_remote_credits_lp);
$finish;
end
// synopsys translate_on
wire [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_local_return_data_oi;
wire credit_local_return_v_oi;
wire [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_remote_return_data_oi;
wire credit_remote_return_yumi_io;
bsg_channel_tunnel_out #(.width_p (width_p)
,.num_in_p (num_in_p)
,.remote_credits_p (remote_credits_p)
,.lg_credit_decimation_p(lg_credit_decimation_p)
) bcto
(.clk_i
,.reset_i
,.data_i
,.v_i
,.yumi_o
,.data_o (multi_data_o )
,.v_o(multi_v_o)
,.yumi_i (multi_yumi_i )
,.credit_local_return_data_i (credit_local_return_data_oi )
,.credit_local_return_v_i (credit_local_return_v_oi )
,.credit_remote_return_data_i(credit_remote_return_data_oi)
,.credit_remote_return_yumi_o(credit_remote_return_yumi_io)
);
bsg_channel_tunnel_in #(.width_p (width_p )
,.num_in_p (num_in_p )
,.remote_credits_p (remote_credits_p)
,.use_pseudo_large_fifo_p(use_pseudo_large_fifo_p)
,.harden_small_fifo_p (harden_small_fifo_p)
,.lg_credit_decimation_p(lg_credit_decimation_p)
) bcti
(.clk_i
,.reset_i
,.data_i (multi_data_i )
,.v_i (multi_v_i)
,.yumi_o (multi_yumi_o )
,.data_o
,.v_o
,.yumi_i
,.credit_local_return_data_o (credit_local_return_data_oi )
,.credit_local_return_v_o (credit_local_return_v_oi )
,.credit_remote_return_data_o(credit_remote_return_data_oi)
,.credit_remote_return_yumi_i(credit_remote_return_yumi_io)
);
endmodule |
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64,
n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149,
n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160,
n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215,
n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226,
n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n246, n247, n248, n249,
n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260,
n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n369, n370;
OAI2BB1X2TS U43 ( .A0N(n264), .A1N(n274), .B0(n19), .Y(res[32]) );
XOR2X2TS U44 ( .A(n204), .B(n203), .Y(res[26]) );
XOR2X2TS U45 ( .A(n239), .B(n238), .Y(res[27]) );
XOR2X2TS U46 ( .A(n244), .B(n243), .Y(res[25]) );
XOR2X2TS U47 ( .A(n248), .B(n247), .Y(res[28]) );
NAND2X1TS U48 ( .A(n237), .B(n89), .Y(n238) );
NAND2X1TS U49 ( .A(n242), .B(n241), .Y(n243) );
NAND2X1TS U50 ( .A(n246), .B(n257), .Y(n247) );
NAND2X1TS U51 ( .A(n228), .B(n256), .Y(n229) );
NAND2X1TS U52 ( .A(n272), .B(n271), .Y(n273) );
NAND2XLTS U53 ( .A(n83), .B(n294), .Y(n295) );
NAND2XLTS U54 ( .A(n86), .B(n291), .Y(n292) );
NAND2XLTS U55 ( .A(n311), .B(n310), .Y(n313) );
NAND2XLTS U56 ( .A(n87), .B(n275), .Y(n276) );
NAND2X1TS U57 ( .A(n285), .B(n284), .Y(n286) );
NAND2X1TS U58 ( .A(n306), .B(n305), .Y(n307) );
NAND2XLTS U59 ( .A(n326), .B(n325), .Y(n327) );
NAND2XLTS U60 ( .A(n301), .B(n300), .Y(n302) );
NAND2X4TS U61 ( .A(n274), .B(n22), .Y(n77) );
OA21XLTS U62 ( .A0(n267), .A1(n271), .B0(n268), .Y(n19) );
OAI21X1TS U63 ( .A0(n308), .A1(n304), .B0(n305), .Y(n303) );
INVX6TS U64 ( .A(n45), .Y(n287) );
NOR2X1TS U65 ( .A(n231), .B(n233), .Y(n236) );
INVX2TS U66 ( .A(n289), .Y(n296) );
CLKBUFX2TS U67 ( .A(n297), .Y(n298) );
OR2X2TS U68 ( .A(n270), .B(n266), .Y(n79) );
NOR2X2TS U69 ( .A(n262), .B(in1[30]), .Y(n265) );
NAND2X2TS U70 ( .A(n263), .B(in1[31]), .Y(n268) );
NAND2X1TS U71 ( .A(n227), .B(in1[29]), .Y(n256) );
CLKMX2X2TS U72 ( .A(in2[30]), .B(n253), .S0(n252), .Y(n262) );
NAND2X2TS U73 ( .A(n219), .B(in1[28]), .Y(n257) );
NAND2X2TS U74 ( .A(n180), .B(in1[22]), .Y(n284) );
NAND2X1TS U75 ( .A(n181), .B(in1[23]), .Y(n280) );
OR2X2TS U76 ( .A(n168), .B(in1[20]), .Y(n83) );
NOR2X2TS U77 ( .A(n299), .B(n304), .Y(n160) );
NAND2X2TS U78 ( .A(n193), .B(in1[24]), .Y(n275) );
CLKMX2X4TS U79 ( .A(in2[29]), .B(n226), .S0(n225), .Y(n227) );
INVX2TS U80 ( .A(n291), .Y(n170) );
OR2X4TS U81 ( .A(n214), .B(in1[27]), .Y(n89) );
NAND2X2TS U82 ( .A(n157), .B(in1[18]), .Y(n305) );
NAND2X2TS U83 ( .A(n158), .B(in1[19]), .Y(n300) );
NOR2X2TS U84 ( .A(n251), .B(in2[30]), .Y(n249) );
CLKMX2X3TS U85 ( .A(in2[23]), .B(n175), .S0(n225), .Y(n181) );
OR2X2TS U86 ( .A(n142), .B(in1[16]), .Y(n82) );
NAND2X2TS U87 ( .A(n169), .B(in1[21]), .Y(n291) );
NOR2X1TS U88 ( .A(n224), .B(n223), .Y(n211) );
MX2X2TS U89 ( .A(in2[25]), .B(n189), .S0(add_sub), .Y(n194) );
MXI2X2TS U90 ( .A(n167), .B(n166), .S0(n225), .Y(n168) );
XOR2X1TS U91 ( .A(n174), .B(n173), .Y(n175) );
OR2X1TS U92 ( .A(n210), .B(in2[27]), .Y(n223) );
INVX4TS U93 ( .A(add_sub), .Y(n353) );
NOR3X2TS U94 ( .A(n176), .B(in2[22]), .C(n184), .Y(n174) );
INVX2TS U95 ( .A(n187), .Y(n153) );
NAND2X1TS U96 ( .A(n206), .B(n205), .Y(n210) );
INVX4TS U97 ( .A(n63), .Y(n61) );
INVX2TS U98 ( .A(in2[20]), .Y(n167) );
NOR2X2TS U99 ( .A(n176), .B(in2[20]), .Y(n163) );
CLKINVX2TS U100 ( .A(n128), .Y(n67) );
INVX2TS U101 ( .A(in2[26]), .Y(n205) );
NAND2X2TS U102 ( .A(n131), .B(in1[14]), .Y(n321) );
NAND2X4TS U103 ( .A(n127), .B(in1[12]), .Y(n330) );
NAND2X2TS U104 ( .A(n18), .B(in1[13]), .Y(n325) );
OR2X2TS U105 ( .A(in2[21]), .B(in2[20]), .Y(n184) );
NOR2X4TS U106 ( .A(in2[17]), .B(in2[16]), .Y(n162) );
XNOR2X2TS U107 ( .A(n112), .B(in2[11]), .Y(n113) );
NOR2X1TS U108 ( .A(in2[19]), .B(in2[18]), .Y(n161) );
OR2X6TS U109 ( .A(n104), .B(in1[8]), .Y(n84) );
CLKINVX6TS U110 ( .A(n346), .Y(n105) );
BUFX4TS U111 ( .A(add_sub), .Y(n252) );
NOR2X2TS U112 ( .A(in2[13]), .B(in2[12]), .Y(n133) );
XNOR2X2TS U113 ( .A(n111), .B(in2[10]), .Y(n93) );
OR2X4TS U114 ( .A(n115), .B(n116), .Y(n111) );
NAND2X6TS U115 ( .A(n52), .B(n350), .Y(n101) );
INVX4TS U116 ( .A(n54), .Y(n97) );
BUFX8TS U117 ( .A(add_sub), .Y(n225) );
INVX8TS U118 ( .A(add_sub), .Y(n94) );
INVX12TS U119 ( .A(in2[3]), .Y(n90) );
CLKINVX6TS U120 ( .A(in2[8]), .Y(n103) );
AND2X2TS U121 ( .A(n118), .B(n117), .Y(n119) );
NAND2X2TS U122 ( .A(in2[6]), .B(add_sub), .Y(n96) );
NOR2X1TS U123 ( .A(n176), .B(n184), .Y(n177) );
AOI21X2TS U124 ( .A0(n89), .A1(n216), .B0(n215), .Y(n217) );
NOR2X4TS U125 ( .A(n219), .B(in1[28]), .Y(n254) );
NOR2XLTS U126 ( .A(n11), .B(in2[2]), .Y(n364) );
OR2X2TS U127 ( .A(n193), .B(in1[24]), .Y(n87) );
OAI21X2TS U128 ( .A0(n220), .A1(n254), .B0(n257), .Y(n221) );
OA21XLTS U129 ( .A0(n336), .A1(n333), .B0(n334), .Y(n20) );
INVX2TS U130 ( .A(n298), .Y(n308) );
NAND2X1TS U131 ( .A(n209), .B(n232), .Y(n203) );
AND2X4TS U132 ( .A(n261), .B(n255), .Y(n9) );
AND2X2TS U133 ( .A(n94), .B(n95), .Y(n10) );
NAND2X2TS U134 ( .A(n92), .B(n352), .Y(n11) );
INVX2TS U135 ( .A(n275), .Y(n240) );
NOR2X4TS U136 ( .A(n227), .B(in1[29]), .Y(n258) );
NOR2X4TS U137 ( .A(n16), .B(n27), .Y(n29) );
INVX2TS U138 ( .A(n260), .Y(n220) );
NOR2X6TS U139 ( .A(n218), .B(n231), .Y(n255) );
INVX3TS U140 ( .A(n267), .Y(n269) );
INVX4TS U141 ( .A(n182), .Y(n46) );
INVX2TS U142 ( .A(n232), .Y(n216) );
NOR2X4TS U143 ( .A(n202), .B(in1[26]), .Y(n233) );
INVX2TS U144 ( .A(n254), .Y(n246) );
NOR2X4TS U145 ( .A(n258), .B(n254), .Y(n261) );
XNOR2X2TS U146 ( .A(n200), .B(in2[26]), .Y(n201) );
XOR2X2TS U147 ( .A(n177), .B(in2[22]), .Y(n178) );
MXI2X4TS U148 ( .A(n192), .B(n191), .S0(n225), .Y(n193) );
NAND2BX2TS U149 ( .AN(n153), .B(n162), .Y(n154) );
NAND2X4TS U150 ( .A(n269), .B(n268), .Y(n270) );
NAND2X4TS U151 ( .A(n209), .B(n89), .Y(n218) );
INVX2TS U152 ( .A(n183), .Y(n42) );
NOR2X4TS U153 ( .A(n196), .B(n195), .Y(n234) );
INVX4TS U154 ( .A(n233), .Y(n209) );
INVX2TS U155 ( .A(n36), .Y(n69) );
OAI21X2TS U156 ( .A0(n258), .A1(n257), .B0(n256), .Y(n259) );
INVX2TS U157 ( .A(n299), .Y(n301) );
INVX4TS U158 ( .A(n190), .Y(n242) );
INVX2TS U159 ( .A(n237), .Y(n215) );
MXI2X4TS U160 ( .A(n205), .B(n201), .S0(n252), .Y(n202) );
NAND2X4TS U161 ( .A(n147), .B(in1[17]), .Y(n310) );
INVX4TS U162 ( .A(n294), .Y(n290) );
MXI2X4TS U163 ( .A(n179), .B(n178), .S0(n252), .Y(n180) );
MX2X4TS U164 ( .A(in2[28]), .B(n212), .S0(n225), .Y(n219) );
NAND2X2TS U165 ( .A(n199), .B(n206), .Y(n200) );
NAND2X2TS U166 ( .A(n142), .B(in1[16]), .Y(n314) );
NOR2X4TS U167 ( .A(n149), .B(n153), .Y(n151) );
OR2X4TS U168 ( .A(n110), .B(in1[10]), .Y(n85) );
INVX6TS U169 ( .A(in2[10]), .Y(n117) );
INVX2TS U170 ( .A(in2[17]), .Y(n144) );
XNOR2X1TS U171 ( .A(n303), .B(n302), .Y(res[19]) );
NAND2X6TS U172 ( .A(n43), .B(n41), .Y(n47) );
XOR2X1TS U173 ( .A(n308), .B(n307), .Y(res[18]) );
NAND2X4TS U174 ( .A(n182), .B(n9), .Y(n71) );
OR2X4TS U175 ( .A(n213), .B(n254), .Y(n222) );
NOR2X4TS U176 ( .A(n16), .B(n79), .Y(n72) );
AND2X2TS U177 ( .A(n63), .B(n25), .Y(n24) );
AND2X2TS U178 ( .A(n270), .B(n272), .Y(n22) );
NOR2X1TS U179 ( .A(n267), .B(n265), .Y(n264) );
XOR2X1TS U180 ( .A(n20), .B(n332), .Y(res[12]) );
INVX2TS U181 ( .A(n231), .Y(n198) );
AND2X2TS U182 ( .A(n281), .B(n280), .Y(n23) );
XOR2X1TS U183 ( .A(n337), .B(n336), .Y(res[11]) );
NOR2X6TS U184 ( .A(n263), .B(in1[31]), .Y(n267) );
CLKAND2X2TS U185 ( .A(n271), .B(n265), .Y(n76) );
XNOR2X2TS U186 ( .A(n249), .B(in2[31]), .Y(n250) );
NOR2X4TS U187 ( .A(n194), .B(in1[25]), .Y(n190) );
NAND2X4TS U188 ( .A(n340), .B(n85), .Y(n37) );
MX2X2TS U189 ( .A(in2[27]), .B(n208), .S0(add_sub), .Y(n214) );
XOR2X1TS U190 ( .A(n345), .B(n13), .Y(res[9]) );
XNOR2X1TS U191 ( .A(n81), .B(in2[29]), .Y(n226) );
NAND2X4TS U192 ( .A(n320), .B(n321), .Y(n63) );
INVX4TS U193 ( .A(n333), .Y(n335) );
NAND2X4TS U194 ( .A(n114), .B(in1[11]), .Y(n334) );
NAND2X4TS U195 ( .A(n104), .B(in1[8]), .Y(n346) );
OAI21XLTS U196 ( .A0(n358), .A1(n353), .B0(n357), .Y(res[6]) );
OAI21XLTS U197 ( .A0(n366), .A1(n353), .B0(n365), .Y(res[3]) );
NAND3X6TS U198 ( .A(n35), .B(n32), .C(n30), .Y(n350) );
OAI21XLTS U199 ( .A0(n361), .A1(n353), .B0(n360), .Y(res[5]) );
OAI21XLTS U200 ( .A0(n363), .A1(n353), .B0(n362), .Y(res[2]) );
OAI21XLTS U201 ( .A0(n370), .A1(n353), .B0(n369), .Y(res[4]) );
OAI21XLTS U202 ( .A0(n355), .A1(n353), .B0(n354), .Y(res[1]) );
OR2X2TS U203 ( .A(in2[18]), .B(n148), .Y(n149) );
CLKINVX6TS U204 ( .A(n11), .Y(n12) );
OR2X1TS U205 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
OAI21X4TS U206 ( .A0(n279), .A1(n284), .B0(n280), .Y(n182) );
NOR2X4TS U207 ( .A(n181), .B(in1[23]), .Y(n279) );
NAND3X4TS U208 ( .A(n78), .B(n77), .C(n74), .Y(res[31]) );
MX2X6TS U209 ( .A(in2[13]), .B(n124), .S0(n225), .Y(n18) );
NOR2X4TS U210 ( .A(n61), .B(n60), .Y(n62) );
NAND4X4TS U211 ( .A(n352), .B(n92), .C(n91), .D(n90), .Y(n48) );
XNOR2X2TS U212 ( .A(n154), .B(in2[18]), .Y(n155) );
INVX12TS U213 ( .A(in2[7]), .Y(n49) );
XNOR2X4TS U214 ( .A(n115), .B(in2[8]), .Y(n102) );
AOI21X1TS U215 ( .A0(n347), .A1(n84), .B0(n105), .Y(n13) );
XOR2X2TS U216 ( .A(n134), .B(in2[12]), .Y(n125) );
NOR2X4TS U217 ( .A(n147), .B(in1[17]), .Y(n309) );
MX2X4TS U218 ( .A(in2[17]), .B(n146), .S0(n225), .Y(n147) );
AND4X8TS U219 ( .A(n90), .B(n95), .C(n91), .D(n92), .Y(n14) );
INVX12TS U220 ( .A(in2[6]), .Y(n95) );
INVX12TS U221 ( .A(n277), .Y(n40) );
NAND2X8TS U222 ( .A(n187), .B(n186), .Y(n224) );
NOR4X2TS U223 ( .A(n185), .B(n184), .C(in2[23]), .D(in2[22]), .Y(n186) );
AND2X4TS U224 ( .A(n183), .B(n9), .Y(n80) );
XOR2X1TS U225 ( .A(n176), .B(n167), .Y(n166) );
NOR2X4TS U226 ( .A(n10), .B(n59), .Y(n58) );
NAND2BX4TS U227 ( .AN(in2[29]), .B(n81), .Y(n251) );
NOR3X4TS U228 ( .A(n224), .B(in2[28]), .C(n223), .Y(n81) );
NOR2X2TS U229 ( .A(n99), .B(in2[7]), .Y(n31) );
NAND2X4TS U230 ( .A(n90), .B(n91), .Y(n99) );
XOR2X1TS U231 ( .A(n293), .B(n292), .Y(res[21]) );
AOI21X4TS U232 ( .A0(n296), .A1(n83), .B0(n290), .Y(n293) );
NAND2X4TS U233 ( .A(n168), .B(in1[20]), .Y(n294) );
NAND2BX4TS U234 ( .AN(n185), .B(n187), .Y(n176) );
NOR2X4TS U235 ( .A(in2[25]), .B(in2[24]), .Y(n206) );
OAI21X4TS U236 ( .A0(n234), .A1(n218), .B0(n217), .Y(n260) );
XOR2X2TS U237 ( .A(n163), .B(in2[21]), .Y(n165) );
MXI2X4TS U238 ( .A(n165), .B(n164), .S0(n353), .Y(n169) );
NAND2X4TS U239 ( .A(n86), .B(n83), .Y(n172) );
MX2X4TS U240 ( .A(in2[19]), .B(n152), .S0(add_sub), .Y(n158) );
NAND2X8TS U241 ( .A(n134), .B(n133), .Y(n139) );
NAND2X8TS U242 ( .A(n103), .B(n108), .Y(n116) );
NOR2X4TS U243 ( .A(n224), .B(n210), .Y(n207) );
XNOR2X4TS U244 ( .A(n188), .B(in2[25]), .Y(n189) );
NOR2X4TS U245 ( .A(n224), .B(in2[24]), .Y(n188) );
MXI2X4TS U246 ( .A(n103), .B(n102), .S0(n225), .Y(n104) );
NOR2X6TS U247 ( .A(n70), .B(n334), .Y(n68) );
NAND2X4TS U248 ( .A(n134), .B(n126), .Y(n123) );
INVX2TS U249 ( .A(in2[16]), .Y(n141) );
INVX2TS U250 ( .A(in2[18]), .Y(n156) );
INVX2TS U251 ( .A(in1[7]), .Y(n53) );
NAND2X2TS U252 ( .A(n109), .B(in1[9]), .Y(n342) );
NAND2X4TS U253 ( .A(n110), .B(in1[10]), .Y(n338) );
NOR2X2TS U254 ( .A(n131), .B(in1[14]), .Y(n320) );
NOR2X4TS U255 ( .A(n180), .B(in1[22]), .Y(n283) );
INVX4TS U256 ( .A(n71), .Y(n27) );
INVX2TS U257 ( .A(n116), .Y(n120) );
INVX2TS U258 ( .A(in2[11]), .Y(n118) );
INVX2TS U259 ( .A(n96), .Y(n57) );
OAI21X2TS U260 ( .A0(n96), .A1(n17), .B0(in1[6]), .Y(n59) );
INVX6TS U261 ( .A(in2[9]), .Y(n108) );
INVX2TS U262 ( .A(in2[12]), .Y(n126) );
INVX12TS U263 ( .A(in2[5]), .Y(n51) );
INVX8TS U264 ( .A(in2[4]), .Y(n50) );
CLKAND2X2TS U265 ( .A(n49), .B(add_sub), .Y(n15) );
NAND2X1TS U266 ( .A(n34), .B(in2[7]), .Y(n33) );
INVX2TS U267 ( .A(n99), .Y(n34) );
CLKINVX6TS U268 ( .A(n68), .Y(n28) );
INVX2TS U269 ( .A(n88), .Y(n60) );
XOR2X1TS U270 ( .A(n151), .B(n150), .Y(n152) );
INVX2TS U271 ( .A(in2[19]), .Y(n150) );
INVX2TS U272 ( .A(in2[21]), .Y(n164) );
INVX2TS U273 ( .A(n224), .Y(n199) );
INVX2TS U274 ( .A(n241), .Y(n195) );
NOR2X2TS U275 ( .A(n275), .B(n190), .Y(n196) );
INVX2TS U276 ( .A(n171), .Y(n44) );
INVX2TS U277 ( .A(n255), .Y(n213) );
NOR2X4TS U278 ( .A(n279), .B(n283), .Y(n183) );
INVX2TS U279 ( .A(n314), .Y(n143) );
NOR2X4TS U280 ( .A(n158), .B(in1[19]), .Y(n299) );
OR2X4TS U281 ( .A(n169), .B(in1[21]), .Y(n86) );
CLKBUFX2TS U282 ( .A(n288), .Y(n289) );
NAND2X2TS U283 ( .A(n194), .B(in1[25]), .Y(n241) );
NAND2X4TS U284 ( .A(n202), .B(in1[26]), .Y(n232) );
INVX2TS U285 ( .A(n234), .Y(n197) );
NAND2X2TS U286 ( .A(n214), .B(in1[27]), .Y(n237) );
NAND2X2TS U287 ( .A(n242), .B(n87), .Y(n231) );
OAI21X1TS U288 ( .A0(n234), .A1(n233), .B0(n232), .Y(n235) );
NAND2X1TS U289 ( .A(n270), .B(n271), .Y(n75) );
NOR2XLTS U290 ( .A(n48), .B(in2[4]), .Y(n359) );
NAND2X1TS U291 ( .A(n349), .B(n52), .Y(n351) );
NAND2X1TS U292 ( .A(n84), .B(n346), .Y(n348) );
NAND2X1TS U293 ( .A(n343), .B(n342), .Y(n345) );
INVX2TS U294 ( .A(n341), .Y(n343) );
NAND2X1TS U295 ( .A(n85), .B(n338), .Y(n339) );
NAND2X1TS U296 ( .A(n335), .B(n334), .Y(n337) );
NAND2X1TS U297 ( .A(n331), .B(n330), .Y(n332) );
INVX2TS U298 ( .A(n329), .Y(n331) );
OAI21XLTS U299 ( .A0(n20), .A1(n329), .B0(n330), .Y(n328) );
INVX2TS U300 ( .A(n324), .Y(n326) );
NAND2X1TS U301 ( .A(n322), .B(n321), .Y(n323) );
INVX2TS U302 ( .A(n320), .Y(n322) );
NAND2X1TS U303 ( .A(n88), .B(n317), .Y(n318) );
CLKBUFX2TS U304 ( .A(n64), .Y(n25) );
NAND2X1TS U305 ( .A(n82), .B(n314), .Y(n315) );
XOR2XLTS U306 ( .A(n313), .B(n312), .Y(res[17]) );
INVX2TS U307 ( .A(n309), .Y(n311) );
XNOR2X1TS U308 ( .A(n296), .B(n295), .Y(res[20]) );
XOR2X1TS U309 ( .A(n287), .B(n286), .Y(res[22]) );
INVX2TS U310 ( .A(n283), .Y(n285) );
XOR2X2TS U311 ( .A(n282), .B(n23), .Y(res[23]) );
INVX2TS U312 ( .A(n279), .Y(n281) );
INVX2TS U313 ( .A(n258), .Y(n228) );
OAI21X1TS U314 ( .A0(n270), .A1(n76), .B0(n75), .Y(n74) );
NAND3X2TS U315 ( .A(n73), .B(n72), .C(n71), .Y(n78) );
NAND2X4TS U316 ( .A(n100), .B(n367), .Y(n55) );
NAND3X6TS U317 ( .A(n335), .B(n38), .C(n129), .Y(n36) );
CLKINVX12TS U318 ( .A(n26), .Y(n134) );
XNOR2X2TS U319 ( .A(n139), .B(in2[14]), .Y(n130) );
BUFX8TS U320 ( .A(n278), .Y(n45) );
NOR2X4TS U321 ( .A(in2[8]), .B(n115), .Y(n106) );
INVX8TS U322 ( .A(n115), .Y(n122) );
XNOR2X1TS U323 ( .A(n277), .B(n276), .Y(res[24]) );
NOR2X4TS U324 ( .A(n109), .B(in1[9]), .Y(n341) );
INVX16TS U325 ( .A(in2[0]), .Y(n352) );
NAND2X4TS U326 ( .A(n262), .B(in1[30]), .Y(n271) );
NOR2X4TS U327 ( .A(n157), .B(in1[18]), .Y(n304) );
AO21X4TS U328 ( .A0(n260), .A1(n261), .B0(n259), .Y(n16) );
AND2X8TS U329 ( .A(n50), .B(n51), .Y(n17) );
INVX2TS U330 ( .A(n271), .Y(n266) );
AND4X8TS U331 ( .A(n50), .B(n352), .C(n51), .D(n49), .Y(n21) );
INVX2TS U332 ( .A(n265), .Y(n272) );
INVX2TS U333 ( .A(n38), .Y(n336) );
CLKINVX6TS U334 ( .A(n48), .Y(n367) );
NOR2X4TS U335 ( .A(n114), .B(in1[11]), .Y(n333) );
XOR2X2TS U336 ( .A(n187), .B(in2[16]), .Y(n140) );
NAND2X8TS U337 ( .A(n14), .B(n21), .Y(n115) );
INVX8TS U338 ( .A(n129), .Y(n70) );
NAND2X8TS U339 ( .A(n122), .B(n121), .Y(n26) );
NAND3X8TS U340 ( .A(n55), .B(n58), .C(n56), .Y(n54) );
NOR2X8TS U341 ( .A(n39), .B(n221), .Y(n230) );
AND2X8TS U342 ( .A(n36), .B(n28), .Y(n65) );
AOI21X4TS U343 ( .A0(n347), .A1(n84), .B0(n105), .Y(n344) );
NAND2X8TS U344 ( .A(n101), .B(n349), .Y(n347) );
NAND2X8TS U345 ( .A(n73), .B(n29), .Y(n274) );
NAND2X8TS U346 ( .A(n45), .B(n80), .Y(n73) );
OAI2BB1X4TS U347 ( .A0N(n31), .A1N(n12), .B0(n98), .Y(n30) );
NAND3BX4TS U348 ( .AN(n33), .B(n12), .C(n100), .Y(n32) );
NAND2BX4TS U349 ( .AN(n100), .B(n15), .Y(n35) );
NAND2X8TS U350 ( .A(n64), .B(n62), .Y(n138) );
NAND2X8TS U351 ( .A(n65), .B(n66), .Y(n64) );
NAND2X8TS U352 ( .A(n37), .B(n338), .Y(n38) );
OAI21X4TS U353 ( .A0(n344), .A1(n341), .B0(n342), .Y(n340) );
NOR2X8TS U354 ( .A(n40), .B(n222), .Y(n39) );
AOI21X4TS U355 ( .A0(n171), .A1(n172), .B0(n42), .Y(n41) );
NAND2BX4TS U356 ( .AN(n44), .B(n288), .Y(n43) );
OAI21X2TS U357 ( .A0(n288), .A1(n172), .B0(n171), .Y(n278) );
NAND2X8TS U358 ( .A(n47), .B(n46), .Y(n277) );
XOR2X4TS U359 ( .A(n123), .B(in2[13]), .Y(n124) );
MXI2X8TS U360 ( .A(n126), .B(n125), .S0(n225), .Y(n127) );
MXI2X4TS U361 ( .A(n132), .B(n130), .S0(n252), .Y(n131) );
NAND2X8TS U362 ( .A(n54), .B(n53), .Y(n52) );
NAND2BX4TS U363 ( .AN(n367), .B(n57), .Y(n56) );
NOR3XLTS U364 ( .A(n68), .B(n69), .C(n128), .Y(n319) );
AND2X8TS U365 ( .A(n67), .B(n321), .Y(n66) );
INVX16TS U366 ( .A(in2[1]), .Y(n92) );
INVX16TS U367 ( .A(in2[2]), .Y(n91) );
XNOR2X1TS U368 ( .A(n315), .B(n316), .Y(res[16]) );
XNOR2X1TS U369 ( .A(n348), .B(n347), .Y(res[8]) );
XNOR2X1TS U370 ( .A(n340), .B(n339), .Y(res[10]) );
XNOR2X2TS U371 ( .A(n274), .B(n273), .Y(res[30]) );
OR2X8TS U372 ( .A(n137), .B(in1[15]), .Y(n88) );
MX2X4TS U373 ( .A(in2[11]), .B(n113), .S0(n252), .Y(n114) );
MXI2X4TS U374 ( .A(n117), .B(n93), .S0(n252), .Y(n110) );
AND2X4TS U375 ( .A(n17), .B(n95), .Y(n100) );
NAND2X8TS U376 ( .A(n97), .B(in1[7]), .Y(n349) );
XOR2X1TS U377 ( .A(add_sub), .B(in2[7]), .Y(n98) );
XNOR2X4TS U378 ( .A(n106), .B(n108), .Y(n107) );
MXI2X4TS U379 ( .A(n108), .B(n107), .S0(n225), .Y(n109) );
NOR2X4TS U380 ( .A(n111), .B(in2[10]), .Y(n112) );
AND2X8TS U381 ( .A(n120), .B(n119), .Y(n121) );
NOR2X8TS U382 ( .A(n18), .B(in1[13]), .Y(n324) );
NOR2X8TS U383 ( .A(n127), .B(in1[12]), .Y(n329) );
NOR2X8TS U384 ( .A(n324), .B(n329), .Y(n129) );
OAI21X4TS U385 ( .A0(n324), .A1(n330), .B0(n325), .Y(n128) );
INVX2TS U386 ( .A(in2[14]), .Y(n132) );
NAND3X1TS U387 ( .A(n134), .B(n133), .C(n132), .Y(n135) );
XOR2X1TS U388 ( .A(n135), .B(in2[15]), .Y(n136) );
MX2X4TS U389 ( .A(in2[15]), .B(n136), .S0(n252), .Y(n137) );
NAND2X6TS U390 ( .A(n137), .B(in1[15]), .Y(n317) );
NAND2X8TS U391 ( .A(n138), .B(n317), .Y(n316) );
NOR3X8TS U392 ( .A(n139), .B(in2[15]), .C(in2[14]), .Y(n187) );
MXI2X2TS U393 ( .A(n141), .B(n140), .S0(n252), .Y(n142) );
AOI21X4TS U394 ( .A0(n316), .A1(n82), .B0(n143), .Y(n312) );
NOR2X2TS U395 ( .A(n153), .B(in2[16]), .Y(n145) );
XOR2X1TS U396 ( .A(n145), .B(n144), .Y(n146) );
OAI21X4TS U397 ( .A0(n312), .A1(n309), .B0(n310), .Y(n297) );
INVX2TS U398 ( .A(n162), .Y(n148) );
MXI2X4TS U399 ( .A(n156), .B(n155), .S0(n252), .Y(n157) );
OAI21X4TS U400 ( .A0(n299), .A1(n305), .B0(n300), .Y(n159) );
AOI21X4TS U401 ( .A0(n297), .A1(n160), .B0(n159), .Y(n288) );
NAND2X2TS U402 ( .A(n162), .B(n161), .Y(n185) );
AOI21X4TS U403 ( .A0(n86), .A1(n290), .B0(n170), .Y(n171) );
INVX2TS U404 ( .A(in2[23]), .Y(n173) );
INVX2TS U405 ( .A(in2[22]), .Y(n179) );
INVX2TS U406 ( .A(in2[24]), .Y(n192) );
XNOR2X4TS U407 ( .A(n224), .B(in2[24]), .Y(n191) );
AOI21X4TS U408 ( .A0(n277), .A1(n198), .B0(n197), .Y(n204) );
XNOR2X1TS U409 ( .A(n207), .B(in2[27]), .Y(n208) );
XNOR2X1TS U410 ( .A(n211), .B(in2[28]), .Y(n212) );
XOR2X4TS U411 ( .A(n230), .B(n229), .Y(res[29]) );
AOI21X4TS U412 ( .A0(n277), .A1(n236), .B0(n235), .Y(n239) );
AOI21X4TS U413 ( .A0(n277), .A1(n87), .B0(n240), .Y(n244) );
AOI21X4TS U414 ( .A0(n277), .A1(n255), .B0(n260), .Y(n248) );
MX2X4TS U415 ( .A(in2[31]), .B(n250), .S0(n252), .Y(n263) );
XOR2X1TS U416 ( .A(n251), .B(in2[30]), .Y(n253) );
OAI21X4TS U417 ( .A0(n287), .A1(n283), .B0(n284), .Y(n282) );
INVX2TS U418 ( .A(n304), .Y(n306) );
XNOR2X1TS U419 ( .A(n24), .B(n318), .Y(res[15]) );
XOR2XLTS U420 ( .A(n319), .B(n323), .Y(res[14]) );
XNOR2X1TS U421 ( .A(n328), .B(n327), .Y(res[13]) );
XNOR2X1TS U422 ( .A(n351), .B(n350), .Y(res[7]) );
XOR2X1TS U423 ( .A(n352), .B(in2[1]), .Y(n355) );
AOI21X1TS U424 ( .A0(n94), .A1(in2[1]), .B0(in1[1]), .Y(n354) );
NAND2X1TS U425 ( .A(n367), .B(n17), .Y(n356) );
XNOR2X1TS U426 ( .A(n356), .B(in2[6]), .Y(n358) );
AOI21X1TS U427 ( .A0(n94), .A1(in2[6]), .B0(in1[6]), .Y(n357) );
XOR2X1TS U428 ( .A(n359), .B(in2[5]), .Y(n361) );
AOI21X1TS U429 ( .A0(n94), .A1(in2[5]), .B0(in1[5]), .Y(n360) );
XNOR2X1TS U430 ( .A(n11), .B(in2[2]), .Y(n363) );
AOI21X1TS U431 ( .A0(n353), .A1(in2[2]), .B0(in1[2]), .Y(n362) );
XNOR2X1TS U432 ( .A(n364), .B(n90), .Y(n366) );
AOI21X1TS U433 ( .A0(n94), .A1(in2[3]), .B0(in1[3]), .Y(n365) );
XOR2X1TS U434 ( .A(n367), .B(in2[4]), .Y(n370) );
AOI21X1TS U435 ( .A0(n94), .A1(in2[4]), .B0(in1[4]), .Y(n369) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL7_syn.sdf");
endmodule |
module gayle
(
input clk,
input clk7_en,
input reset,
input [23:1] address_in,
input [15:0] data_in,
output [15:0] data_out,
input rd,
input hwr,
input lwr,
input sel_ide, // $DAxxxx
input sel_gayle, // $DExxxx
output irq,
output nrdy, // fifo is not ready for reading
input [1:0] hdd_ena, // enables Master & Slave drives
output hdd_cmd_req,
output hdd_dat_req,
input [2:0] hdd_addr,
input [15:0] hdd_data_out,
output [15:0] hdd_data_in,
input hdd_wr,
input hdd_status_wr,
input hdd_data_wr,
input hdd_data_rd,
output hd_fwr,
output hd_frd
);
localparam VCC = 1'b1;
localparam GND = 1'b0;
//0xda2000 Data
//0xda2004 Error | Feature
//0xda2008 SectorCount
//0xda200c SectorNumber
//0xda2010 CylinderLow
//0xda2014 CylinderHigh
//0xda2018 Device/Head
//0xda201c Status | Command
//0xda3018 Control
/*
memory map:
$DA0000 - $DA0FFFF : CS1 16-bit speed
$DA1000 - $DA1FFFF : CS2 16-bit speed
$DA2000 - $DA2FFFF : CS1 8-bit speed
$DA3000 - $DA3FFFF : CS2 8-bit speed
$DA4000 - $DA7FFFF : reserved
$DA8000 - $DA8FFFF : IDE INTREQ state status register (not implemented as scsi.device doesn't use it)
$DA9000 - $DA9FFFF : IDE INTREQ change status register (writing zeros resets selected bits, writing ones doesn't change anything)
$DAA000 - $DAAFFFF : IDE INTENA register (r/w, only MSB matters)
command class:
PI (PIO In)
PO (PIO Out)
ND (No Data)
Status:
#6 - DRDY - Drive Ready
#7 - BSY - Busy
#3 - DRQ - Data Request
#0 - ERR - Error
INTRQ - Interrupt Request
*/
// address decoding signals
wire sel_gayleid; // Gayle ID register select
wire sel_tfr; // HDD task file registers select
wire sel_fifo; // HDD data port select (FIFO buffer)
wire sel_status; // HDD status register select
wire sel_command; // HDD command register select
wire sel_cs; // Gayle IDE CS
wire sel_intreq; // Gayle interrupt request status register select
wire sel_intena; // Gayle interrupt enable register select
wire sel_cfg; // Gayle CFG
// internal registers
reg intena; // Gayle IDE interrupt enable bit
reg intreq; // Gayle IDE interrupt request bit
reg busy; // busy status (command processing state)
reg pio_in; // pio in command type is being processed
reg pio_out; // pio out command type is being processed
reg error; // error status (command processing failed)
reg [3:0] cfg;
reg [1:0] cs;
reg [5:0] cs_mask;
reg dev; // drive select (Master/Slave)
wire bsy; // busy
wire drdy; // drive ready
wire drq; // data request
wire err; // error
wire [7:0] status; // HDD status
// FIFO control
wire fifo_reset;
wire [15:0] fifo_data_in;
wire [15:0] fifo_data_out;
wire fifo_rd;
wire fifo_wr;
wire fifo_full;
wire fifo_empty;
wire fifo_last; // last word of a sector is being read
// gayle id reg
reg [1:0] gayleid_cnt; // sequence counter
wire gayleid; // output data (one bit wide)
// hd leds
assign hd_fwr = fifo_wr;
assign hd_frd = fifo_rd;
// HDD status register
assign status = {bsy,drdy,2'b00,drq,2'b00,err};
// status debug
reg [7:0] status_dbg /* synthesis syn_noprune */;
always @ (posedge clk) status_dbg <= #1 status;
// HDD status register bits
assign bsy = busy & ~drq;
assign drdy = ~(bsy|drq);
assign err = error;
// address decoding
assign sel_gayleid = sel_gayle && address_in[15:12]==4'b0001 ? VCC : GND; // GAYLEID, $DE1xxx
assign sel_tfr = sel_ide && address_in[15:14]==2'b00 && !address_in[12] ? VCC : GND; // $DA0xxx, $DA2xxx
assign sel_status = rd && sel_tfr && address_in[4:2]==3'b111 ? VCC : GND;
assign sel_command = hwr && sel_tfr && address_in[4:2]==3'b111 ? VCC : GND;
assign sel_fifo = sel_tfr && address_in[4:2]==3'b000 ? VCC : GND;
assign sel_cs = sel_ide && address_in[15:12]==4'b1000 ? VCC : GND; // GAYLE_CS_1200, $DA8xxx
assign sel_intreq = sel_ide && address_in[15:12]==4'b1001 ? VCC : GND; // GAYLE_IRQ_1200, $DA9xxx
assign sel_intena = sel_ide && address_in[15:12]==4'b1010 ? VCC : GND; // GAYLE_INT_1200, $DAAxxx
assign sel_cfg = sel_ide && address_in[15:12]==4'b1011 ? VCC : GND; // GAYLE_CFG_1200, $DABxxx
//===============================================================================================//
// gayle cs
always @ (posedge clk) begin
if (clk7_en) begin
if (reset) begin
cs_mask <= #1 6'd0;
cs <= #1 2'd0;
end else if (hwr && sel_cs) begin
cs_mask <= #1 data_in[15:10];
cs <= #1 data_in[9:8];
end
end
end
// gayle cfg
always @ (posedge clk) begin
if (clk7_en) begin
if (reset)
cfg <= #1 4'd0;
if (hwr && sel_cfg) begin
cfg <= #1 data_in[15:12];
end
end
end
// task file registers
reg [7:0] tfr [7:0];
wire [2:0] tfr_sel;
wire [7:0] tfr_in;
wire [7:0] tfr_out;
wire tfr_we;
reg [7:0] sector_count; // sector counter
wire sector_count_dec; // decrease sector counter
always @(posedge clk)
if (clk7_en) begin
if (hwr && sel_tfr && address_in[4:2] == 3'b010) // sector count register loaded by the host
sector_count <= data_in[15:8];
else if (sector_count_dec)
sector_count <= sector_count - 8'd1;
end
assign sector_count_dec = pio_in & fifo_last & sel_fifo & rd;
// task file register control
assign tfr_we = busy ? hdd_wr : sel_tfr & hwr;
assign tfr_sel = busy ? hdd_addr : address_in[4:2];
assign tfr_in = busy ? hdd_data_out[7:0] : data_in[15:8];
// input multiplexer for SPI host
assign hdd_data_in = tfr_sel==0 ? fifo_data_out : {8'h00,tfr_out};
// task file registers
always @(posedge clk)
if (clk7_en) begin
if (tfr_we)
tfr[tfr_sel] <= tfr_in;
end
assign tfr_out = tfr[tfr_sel];
// master/slave drive select
always @(posedge clk)
if (clk7_en) begin
if (reset)
dev <= 0;
else if (sel_tfr && address_in[4:2]==6 && hwr)
dev <= data_in[12];
end
// IDE interrupt enable register
always @(posedge clk)
if (clk7_en) begin
if (reset)
intena <= GND;
else if (sel_intena && hwr)
intena <= data_in[15];
end
// gayle id register: reads 1->1->0->1 on MSB
always @(posedge clk)
if (clk7_en) begin
if (sel_gayleid)
if (hwr) // a write resets sequence counter
gayleid_cnt <= 2'd0;
else if (rd)
gayleid_cnt <= gayleid_cnt + 2'd1;
end
assign gayleid = ~gayleid_cnt[1] | gayleid_cnt[0]; // Gayle ID output data
// status register (write only from SPI host)
// 7 - busy status (write zero to finish command processing: allow host access to task file registers)
// 6
// 5
// 4 - intreq
// 3 - drq enable for pio in (PI) command type
// 2 - drq enable for pio out (PO) command type
// 1
// 0 - error flag (remember about setting error task file register)
// command busy status
always @(posedge clk)
if (clk7_en) begin
if (reset)
busy <= GND;
else if (hdd_status_wr && hdd_data_out[7] || (sector_count_dec && sector_count == 8'h01)) // reset by SPI host (by clearing BSY status bit)
busy <= GND;
else if (sel_command) // set when the CPU writes command register
busy <= VCC;
end
// IDE interrupt request register
always @(posedge clk)
if (clk7_en) begin
if (reset)
intreq <= GND;
else if (busy && hdd_status_wr && hdd_data_out[4] && intena) // set by SPI host
intreq <= VCC;
else if (sel_intreq && hwr && !data_in[15]) // cleared by the CPU
intreq <= GND;
end
assign irq = (~pio_in | drq) & intreq; // interrupt request line (INT2)
// pio in command type
always @(posedge clk)
if (clk7_en) begin
if (reset)
pio_in <= GND;
else if (drdy) // reset when processing of the current command ends
pio_in <= GND;
else if (busy && hdd_status_wr && hdd_data_out[3]) // set by SPI host
pio_in <= VCC;
end
// pio out command type
always @(posedge clk)
if (clk7_en) begin
if (reset)
pio_out <= GND;
else if (busy && hdd_status_wr && hdd_data_out[7]) // reset by SPI host when command processing completes
pio_out <= GND;
else if (busy && hdd_status_wr && hdd_data_out[2]) // set by SPI host
pio_out <= VCC;
end
assign drq = (fifo_full & pio_in) | (~fifo_full & pio_out); // HDD data request status bit
// error status
always @(posedge clk)
if (clk7_en) begin
if (reset)
error <= GND;
else if (sel_command) // reset by the CPU when command register is written
error <= GND;
else if (busy && hdd_status_wr && hdd_data_out[0]) // set by SPI host
error <= VCC;
end
assign hdd_cmd_req = bsy; // bsy is set when command register is written, tells the SPI host about new command
assign hdd_dat_req = (fifo_full & pio_out); // the FIFO is full so SPI host may read it
// FIFO in/out multiplexer
assign fifo_reset = reset | sel_command;
assign fifo_data_in = pio_in ? hdd_data_out : data_in;
assign fifo_rd = pio_out ? hdd_data_rd : sel_fifo & rd;
assign fifo_wr = pio_in ? hdd_data_wr : sel_fifo & hwr & lwr;
//sector data buffer (FIFO)
gayle_fifo SECBUF1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(fifo_reset),
.data_in(fifo_data_in),
.data_out(fifo_data_out),
.rd(fifo_rd),
.wr(fifo_wr),
.full(fifo_full),
.empty(fifo_empty),
.last(fifo_last)
);
// fifo is not ready for reading
assign nrdy = pio_in & sel_fifo & fifo_empty;
//data_out multiplexer
assign data_out = (sel_fifo && rd ? fifo_data_out : sel_status ? (!dev && hdd_ena[0]) || (dev && hdd_ena[1]) ? {status,8'h00} : 16'h00_00 : sel_tfr && rd ? {tfr_out,8'h00} : 16'h00_00)
| (sel_cs && rd ? {(cs_mask[5] || intreq), cs_mask[4:0], cs, 8'h0} : 16'h00_00)
| (sel_intreq && rd ? {intreq, 15'b000_0000_0000_0000} : 16'h00_00)
| (sel_intena && rd ? {intena, 15'b000_0000_0000_0000} : 16'h00_00)
| (sel_gayleid && rd ? {gayleid,15'b000_0000_0000_0000} : 16'h00_00)
| (sel_cfg && rd ? {cfg, 12'b0000_0000_0000} : 16'h00_00);
//===============================================================================================//
endmodule |
module qsys_serial_device#(
parameter address_size=8)(
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output reg[31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [7:0] avs_ctrl_address,
input avs_ctrl_write,
input avs_ctrl_read,
input avs_ctrl_chipselect,
output reg avs_ctrl_waitrequest,
output reg avs_ctrl_readdatavalid,
// Qsys serial interface
output reg sdo,
input sdi,
output clk,
output reg sle,
input srdy
);
reg [64:0] data_buffer;
assign clk = csi_MCLK_clk;
parameter initial_state = 8'd0;
parameter bus_data_wait = initial_state+8'd1;
parameter bus_data_ready = bus_data_wait+8'd1;
parameter bus_transmit_start = bus_data_ready + 8'd1;
parameter bus_transmit_ready = bus_transmit_start + 8'd64;
parameter bus_transmit_finish = bus_transmit_ready + 8'd1;
parameter bus_ready_wait = bus_transmit_finish + 8'd1;
parameter bus_transmit_back = bus_ready_wait + 8'd1;
parameter bus_data_read = bus_transmit_back + 8'd1;
parameter bus_data_read_finish = bus_data_read + 8'd2;
reg [7:0] state;
reg [7:0] nextstate;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if (rsi_MRST_reset)
state <= initial_state;
else
state <= nextstate;
end
always@(state or srdy or avs_ctrl_write or avs_ctrl_read)
begin
case(state)
initial_state: nextstate <= bus_data_wait;
bus_data_wait: begin
if(avs_ctrl_write == 1'b1 || avs_ctrl_read == 1'b1)
begin
if(avs_ctrl_chipselect == 1'b1)
nextstate <= bus_data_ready;
else
nextstate <= bus_data_wait;
end
else
nextstate <= bus_data_wait;
end
bus_data_ready: nextstate <= bus_transmit_start;
bus_transmit_start: nextstate <= state + 1;
bus_transmit_ready: nextstate <= bus_transmit_finish;
bus_transmit_finish: nextstate <= bus_ready_wait;
bus_ready_wait:
begin
if(srdy == 1'b1)
nextstate <= bus_transmit_back;
else
nextstate <= bus_ready_wait;
end
bus_transmit_back:
begin
if(srdy == 1'b0)
nextstate <= bus_data_read;
else
nextstate <= bus_transmit_back;
end
bus_data_read: nextstate <= state +1;
bus_data_read_finish: nextstate <= bus_data_wait;
default: nextstate <= state + 1;
endcase
end
always@(posedge csi_MCLK_clk)
begin
if (state == bus_data_wait)
begin
data_buffer[63:32] <= avs_ctrl_address;
if (avs_ctrl_write == 1'b1)
begin
data_buffer[64] <= 1'b1; //write
data_buffer[31:0] <= avs_ctrl_writedata;
end
else if (avs_ctrl_read == 1'b1)
begin
data_buffer[64] <= 1'b0; //read
data_buffer[31:0] <= 32'd0;
end
end
else if (state >= bus_transmit_start && state <= bus_transmit_ready)
begin
integer i;
for(i=0;i<64;i=i+1)
data_buffer[i+1] <= data_buffer[i];
sdo <= data_buffer[64];
end
else if (state == bus_transmit_back)
begin
integer i;
for(i=0;i<64;i=i+1)
data_buffer[i+1] <= data_buffer[i];
data_buffer[0]<= sdi;
end
end
always@(posedge csi_MCLK_clk)
begin
if (state >= bus_data_ready && state < bus_transmit_ready)
sle <= 1;
else
sle <= 0;
end
always@(state)
begin
if (state >= bus_data_ready && state <= bus_data_read)
avs_ctrl_waitrequest = 1'b1;
else
avs_ctrl_waitrequest = 1'b0;
end
always@(posedge csi_MCLK_clk)
begin
if (state == bus_data_read )
avs_ctrl_readdatavalid <= 1'b1;
else
avs_ctrl_readdatavalid <= 1'b0;
end
always@(posedge csi_MCLK_clk)
begin
if (state == bus_data_read)
begin
avs_ctrl_readdata <= data_buffer[31:0];
end
end
endmodule |
module t (
input wire CLK
);
foo #(.WIDTH (1)) foo1 (.*);
foo #(.WIDTH (7)) foo7 (.*);
foo #(.WIDTH (8)) foo8 (.*);
foo #(.WIDTH (32)) foo32 (.*);
foo #(.WIDTH (33)) foo33 (.*);
foo #(.WIDTH (40)) foo40 (.*);
foo #(.WIDTH (41)) foo41 (.*);
foo #(.WIDTH (64)) foo64 (.*);
foo #(.WIDTH (65)) foo65 (.*);
foo #(.WIDTH (96)) foo96 (.*);
foo #(.WIDTH (97)) foo97 (.*);
foo #(.WIDTH (128)) foo128 (.*);
foo #(.WIDTH (256)) foo256 (.*);
foo #(.WIDTH (1024)) foo1024 (.*);
bar #(.WIDTH (1024)) bar1024 (.*);
endmodule |
module foo
#(
parameter WIDTH = 32
)
(
input CLK
);
logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value;
logic [ WIDTH - 1 : 0 ] value_q /* verilator public */;
integer i;
initial begin
initial_value = '1;
for (i = 0; i < WIDTH / 8; i++)
initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ];
value_q = initial_value[ WIDTH - 1 : 0 ];
end
always @(posedge CLK)
value_q <= ~value_q;
endmodule |
module bar
#(
parameter WIDTH = 32
)
(
input CLK
);
foo #(.WIDTH (WIDTH)) foo (.*);
endmodule |
module spi_slave_0_base(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1]==2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1]==2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
*read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge)begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
received_memory <= (byte_data_received == bytecnt) ? (received_memory + 1'b1) : received_memory;
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= 8'h0;
else begin
if(byte_received)
cnt<=cnt+8'h1; // count the messages
else
cnt<=cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_data_sent <= 8'h0;
else begin
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b000)
byte_data_sent <= cnt; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else
recived_status <= (received_memory == 8'd64) ? 1'b1 : 1'b0;
end
endmodule |
module redFour__NMOSwk_X_1_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
rtranif1 #(100) NMOSfwk_0 (d, s, g);
endmodule |
module redFour__PMOSwk_X_0_833_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
rtranif0 #(100) PMOSfwk_0 (d, s, g);
endmodule |
module scanChainFive__scanL(in, out);
input in;
output out;
supply1 vdd;
supply0 gnd;
wire net_4, net_7;
redFour__NMOSwk_X_1_Delay_100 NMOSwk_0(.g(out), .d(in), .s(net_7));
redFour__NMOSwk_X_1_Delay_100 NMOSwk_1(.g(out), .d(net_7), .s(gnd));
redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_0(.g(out), .d(net_4), .s(vdd));
redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_1(.g(out), .d(in), .s(net_4));
not (strong0, strong1) #(100) invV_0 (out, in);
endmodule |
module redFour__NMOS_X_6_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule |
module redFour__PMOS_X_3_333_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule |
module scanChainFive__scanP(in, src, drn);
input in;
input src;
output drn;
supply1 vdd;
supply0 gnd;
wire net_1;
redFour__NMOS_X_6_667_Delay_100 NMOS_0(.g(in), .d(drn), .s(src));
redFour__PMOS_X_3_333_Delay_100 PMOS_0(.g(net_1), .d(drn), .s(src));
not (strong0, strong1) #(0) inv_0 (net_1, in);
endmodule |
module scanChainFive__scanRL(phi1, phi2, rd, sin, sout);
input phi1;
input phi2;
input rd;
input sin;
output sout;
supply1 vdd;
supply0 gnd;
wire net_0, net_2, net_3;
scanChainFive__scanL foo1(.in(net_2), .out(net_3));
scanChainFive__scanL foo2(.in(net_0), .out(sout));
scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_0));
scanChainFive__scanP scanP_1(.in(phi1), .src(net_3), .drn(net_0));
scanChainFive__scanP scanP_2(.in(phi2), .src(sin), .drn(net_2));
endmodule |
module jtag__BR(SDI, phi1, phi2, read, SDO);
input SDI;
input phi1;
input phi2;
input read;
output SDO;
supply1 vdd;
supply0 gnd;
scanChainFive__scanRL scanRL_0(.phi1(phi1), .phi2(phi2), .rd(read),
.sin(SDI), .sout(SDO));
endmodule |
module scanChainFive__scanIRH(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
sout);
input mclr;
input phi1;
input phi2;
input rd;
input sin;
input wr;
output dout;
output doutb;
output sout;
supply1 vdd;
supply0 gnd;
wire net_2, net_4, net_6, net_7;
scanChainFive__scanL foo1(.in(net_6), .out(net_7));
scanChainFive__scanL foo2(.in(net_2), .out(sout));
scanChainFive__scanL foo3(.in(net_4), .out(doutb));
not (strong0, strong1) #(100) invLT_0 (dout, doutb);
scanChainFive__scanP scanP_0(.in(wr), .src(sout), .drn(net_4));
scanChainFive__scanP scanP_1(.in(rd), .src(gnd), .drn(net_2));
scanChainFive__scanP scanP_2(.in(mclr), .src(vdd), .drn(net_4));
scanChainFive__scanP scanP_3(.in(phi1), .src(net_7), .drn(net_2));
scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_6));
endmodule |
module scanChainFive__scanIRL(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
sout);
input mclr;
input phi1;
input phi2;
input rd;
input sin;
input wr;
output dout;
output doutb;
output sout;
supply1 vdd;
supply0 gnd;
wire net_2, net_3, net_4, net_6;
scanChainFive__scanL foo1(.in(net_2), .out(net_3));
scanChainFive__scanL foo2(.in(net_4), .out(sout));
scanChainFive__scanL foo3(.in(net_6), .out(doutb));
not (strong0, strong1) #(100) invLT_0 (dout, doutb);
scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_4));
scanChainFive__scanP scanP_1(.in(mclr), .src(vdd), .drn(net_6));
scanChainFive__scanP scanP_2(.in(wr), .src(sout), .drn(net_6));
scanChainFive__scanP scanP_3(.in(phi1), .src(net_3), .drn(net_4));
scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_2));
endmodule |
module jtag__IR(SDI, phi1, phi2, read, reset, write, IR, IRb, SDO);
input SDI;
input phi1;
input phi2;
input read;
input reset;
input write;
output [8:1] IR;
output [8:1] IRb;
output SDO;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4, net_5, net_6, net_7;
scanChainFive__scanIRH scanIRH_0(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_1), .wr(write), .dout(IR[1]), .doutb(IRb[1]),
.sout(SDO));
scanChainFive__scanIRL scanIRL_0(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_3), .wr(write), .dout(IR[7]), .doutb(IRb[7]),
.sout(net_2));
scanChainFive__scanIRL scanIRL_1(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_5), .wr(write), .dout(IR[5]), .doutb(IRb[5]),
.sout(net_4));
scanChainFive__scanIRL scanIRL_2(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_2), .wr(write), .dout(IR[6]), .doutb(IRb[6]),
.sout(net_5));
scanChainFive__scanIRL scanIRL_3(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_7), .wr(write), .dout(IR[3]), .doutb(IRb[3]),
.sout(net_6));
scanChainFive__scanIRL scanIRL_4(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_6), .wr(write), .dout(IR[2]), .doutb(IRb[2]),
.sout(net_1));
scanChainFive__scanIRL scanIRL_5(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_4), .wr(write), .dout(IR[4]), .doutb(IRb[4]),
.sout(net_7));
scanChainFive__scanIRL scanIRL_6(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(SDI), .wr(write), .dout(IR[8]), .doutb(IRb[8]),
.sout(net_3));
endmodule |
module redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
endmodule |
module jtag__IRdecode(IR, IRb, Bypass, ExTest, SamplePreload, ScanPath);
input [4:1] IR;
input [4:1] IRb;
output Bypass;
output ExTest;
output SamplePreload;
output [12:0] ScanPath;
supply1 vdd;
supply0 gnd;
wire H00, H01, H10, H11, L00, L01, L10, L11, net_19, net_21, net_23, net_25;
wire net_26, net_27, net_28, net_29, net_30, net_31, net_32, net_33, net_34;
wire net_35, net_36, net_37;
not (strong0, strong1) #(100) inv_0 (Bypass, net_19);
not (strong0, strong1) #(100) inv_1 (SamplePreload, net_21);
not (strong0, strong1) #(100) inv_2 (ExTest, net_23);
not (strong0, strong1) #(100) inv_3 (ScanPath[12], net_25);
not (strong0, strong1) #(100) inv_4 (ScanPath[11], net_26);
not (strong0, strong1) #(100) inv_5 (ScanPath[10], net_27);
not (strong0, strong1) #(100) inv_6 (ScanPath[9], net_28);
not (strong0, strong1) #(100) inv_7 (ScanPath[8], net_29);
not (strong0, strong1) #(100) inv_8 (ScanPath[7], net_30);
not (strong0, strong1) #(100) inv_9 (ScanPath[6], net_31);
not (strong0, strong1) #(100) inv_10 (ScanPath[5], net_32);
not (strong0, strong1) #(100) inv_11 (ScanPath[4], net_33);
not (strong0, strong1) #(100) inv_12 (ScanPath[3], net_34);
not (strong0, strong1) #(100) inv_13 (ScanPath[2], net_35);
not (strong0, strong1) #(100) inv_14 (ScanPath[1], net_36);
not (strong0, strong1) #(100) inv_15 (ScanPath[0], net_37);
nand (strong0, strong1) #(100) nand2_0 (net_19, L11, H11);
nand (strong0, strong1) #(100) nand2_1 (net_21, L10, H11);
nand (strong0, strong1) #(100) nand2_2 (net_23, L01, H11);
nand (strong0, strong1) #(100) nand2_3 (net_25, L00, H11);
nand (strong0, strong1) #(100) nand2_4 (net_26, L11, H10);
nand (strong0, strong1) #(100) nand2_5 (net_27, L10, H10);
nand (strong0, strong1) #(100) nand2_6 (net_28, L01, H10);
nand (strong0, strong1) #(100) nand2_7 (net_29, L00, H10);
nand (strong0, strong1) #(100) nand2_8 (net_30, L11, H01);
nand (strong0, strong1) #(100) nand2_9 (net_31, L10, H01);
nand (strong0, strong1) #(100) nand2_10 (net_32, L01, H01);
nand (strong0, strong1) #(100) nand2_11 (net_33, L00, H01);
nand (strong0, strong1) #(100) nand2_12 (net_34, L11, H00);
nand (strong0, strong1) #(100) nand2_13 (net_35, L10, H00);
nand (strong0, strong1) #(100) nand2_14 (net_36, L01, H00);
nand (strong0, strong1) #(100) nand2_15 (net_37, L00, H00);
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(IR[1]), .inb(IR[2]), .out(L00));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_1(.ina(IRb[1]), .inb(IR[2]), .out(L01));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_2(.ina(IR[1]), .inb(IRb[2]), .out(L10));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_3(.ina(IRb[1]), .inb(IRb[2]), .out(L11));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_4(.ina(IR[3]), .inb(IR[4]), .out(H00));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_5(.ina(IRb[3]), .inb(IR[4]), .out(H01));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_6(.ina(IR[3]), .inb(IRb[4]), .out(H10));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_7(.ina(IRb[3]), .inb(IRb[4]), .out(H11));
endmodule |
module redFour__PMOSwk_X_0_222_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
rtranif0 #(100) PMOSfwk_0 (d, s, g);
endmodule |
module jtag__clockGen(clk, phi1_fb, phi2_fb, phi1_out, phi2_out);
input clk;
input phi1_fb;
input phi2_fb;
output phi1_out;
output phi2_out;
supply1 vdd;
supply0 gnd;
wire net_0, net_1, net_3, net_4, net_6;
not (strong0, strong1) #(100) inv_0 (phi2_out, net_3);
not (strong0, strong1) #(100) inv_1 (phi1_out, net_6);
not (strong0, strong1) #(100) inv_2 (net_4, clk);
not (strong0, strong1) #(100) invLT_0 (net_0, phi1_fb);
not (strong0, strong1) #(100) invLT_1 (net_1, phi2_fb);
nand (strong0, strong1) #(100) nand2_0 (net_3, net_0, net_4);
nand (strong0, strong1) #(100) nand2_1 (net_6, net_1, clk);
endmodule |