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module jtag__capture_ctl(capture, phi2, sel, out, phi1);
input capture;
input phi2;
input sel;
output out;
input phi1;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4;
scanChainFive__scanL foo(.in(net_2), .out(net_3));
not (strong0, strong1) #(100) inv_0 (net_1, capture);
not (strong0, strong1) #(100) inv_1 (out, net_4);
nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1);
scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2));
endmodule |
module jtag__shift_ctl(phi1_fb, phi2_fb, sel, shift, phi1_out, phi2_out,
phi1_in, phi2_in);
input phi1_fb;
input phi2_fb;
input sel;
input shift;
output phi1_out;
output phi2_out;
input phi1_in;
input phi2_in;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4, net_7;
jtag__clockGen clockGen_0(.clk(net_7), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb),
.phi1_out(phi1_out), .phi2_out(phi2_out));
scanChainFive__scanL foo(.in(net_2), .out(net_3));
not (strong0, strong1) #(100) inv_0 (net_7, net_4);
not (strong0, strong1) #(100) inv_1 (net_1, shift);
nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1_in);
scanChainFive__scanP scanP_0(.in(phi2_in), .src(net_1), .drn(net_2));
endmodule |
module jtag__update_ctl(sel, update, out, phi2);
input sel;
input update;
output out;
input phi2;
supply1 vdd;
supply0 gnd;
wire net_1;
not (strong0, strong1) #(100) inv_0 (out, net_1);
nand (strong0, strong1) #(100) nand3_0 (net_1, sel, update, phi2);
endmodule |
module jtag__jtagIRControl(capture, phi1_fb, phi1_in, phi2_fb, phi2_in, shift,
update, phi1_out, phi2_out, read, write);
input capture;
input phi1_fb;
input phi1_in;
input phi2_fb;
input phi2_in;
input shift;
input update;
output phi1_out;
output phi2_out;
output read;
output write;
supply1 vdd;
supply0 gnd;
jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(vdd),
.out(read), .phi1(phi1_in));
jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(vdd),
.shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out),
.phi1_in(phi1_in), .phi2_in(phi2_in));
jtag__update_ctl update_c_0(.sel(vdd), .update(update), .out(write),
.phi2(phi2_in));
endmodule |
module redFour__NMOS_X_8_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule |
module redFour__PMOS_X_4_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule |
module jtag__tsinvBig(Din, en, enb, Dout);
input Din;
input en;
input enb;
output Dout;
supply1 vdd;
supply0 gnd;
wire net_13, net_14, net_22, net_23;
redFour__NMOS_X_8_Delay_100 NMOS_0(.g(Din), .d(net_13), .s(gnd));
redFour__NMOS_X_8_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_13));
redFour__NMOS_X_8_Delay_100 NMOS_2(.g(en), .d(Dout), .s(net_23));
redFour__NMOS_X_8_Delay_100 NMOS_3(.g(Din), .d(net_23), .s(gnd));
redFour__PMOS_X_4_Delay_100 PMOS_0(.g(enb), .d(Dout), .s(net_14));
redFour__PMOS_X_4_Delay_100 PMOS_1(.g(Din), .d(net_14), .s(vdd));
redFour__PMOS_X_4_Delay_100 PMOS_2(.g(enb), .d(Dout), .s(net_22));
redFour__PMOS_X_4_Delay_100 PMOS_3(.g(Din), .d(net_22), .s(vdd));
endmodule |
module jtag__jtagScanControl(TDI, capture, phi1_fb, phi1_in, phi2_fb, phi2_in,
sel, shift, update, TDO, phi1_out, phi2_out, read, write);
input TDI;
input capture;
input phi1_fb;
input phi1_in;
input phi2_fb;
input phi2_in;
input sel;
input shift;
input update;
output TDO;
output phi1_out;
output phi2_out;
output read;
output write;
supply1 vdd;
supply0 gnd;
wire net_0, net_2;
jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(sel),
.out(read), .phi1(phi1_in));
not (strong0, strong1) #(100) inv_0 (net_2, sel);
not (strong0, strong1) #(100) inv_1 (net_0, TDI);
jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(sel),
.shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out),
.phi1_in(phi1_in), .phi2_in(phi2_in));
jtag__tsinvBig tsinvBig_0(.Din(net_0), .en(sel), .enb(net_2), .Dout(TDO));
jtag__update_ctl update_c_0(.sel(sel), .update(update), .out(write),
.phi2(phi2_in));
endmodule |
module redFour__NMOS_X_5_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule |
module redFour__PMOS_X_2_833_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule |
module jtag__tsinv(Din, Dout, en, enb);
input Din;
input Dout;
input en;
input enb;
supply1 vdd;
supply0 gnd;
wire net_1, net_2;
redFour__NMOS_X_5_667_Delay_100 NMOS_0(.g(Din), .d(net_1), .s(gnd));
redFour__NMOS_X_5_667_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_1));
redFour__PMOS_X_2_833_Delay_100 PMOS_0(.g(Din), .d(net_2), .s(vdd));
redFour__PMOS_X_2_833_Delay_100 PMOS_1(.g(enb), .d(Dout), .s(net_2));
endmodule |
module jtag__mux2_phi2(Din0, Din1, phi2, sel, Dout);
input Din0;
input Din1;
input phi2;
input sel;
output Dout;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_5, net_6;
not (strong0, strong1) #(100) inv_0 (net_5, sel);
not (strong0, strong1) #(100) inv_1 (net_1, net_6);
not (strong0, strong1) #(100) inv_2 (Dout, net_3);
scanChainFive__scanL scanL_0(.in(net_2), .out(net_3));
scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2));
jtag__tsinv tsinv_0(.Din(Din0), .Dout(net_6), .en(net_5), .enb(sel));
jtag__tsinv tsinv_1(.Din(Din1), .Dout(net_6), .en(sel), .enb(net_5));
endmodule |
module jtag__scanAmp1w1648(in, out);
input in;
output out;
supply1 vdd;
supply0 gnd;
wire net_0;
tranif1 nmos_0(gnd, net_0, in);
tranif1 nmos_1(gnd, out, net_0);
tranif0 pmos_0(net_0, vdd, in);
tranif0 pmos_1(out, vdd, net_0);
endmodule |
module redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
endmodule |
module redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
endmodule |
module redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
endmodule |
module orangeTSMC180nm__wire_R_26m_100_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_100_C_0_025f wire_0(.a(a));
endmodule |
module jtag__o2a(inAa, inAb, inOb, out);
input inAa;
input inAb;
input inOb;
output out;
supply1 vdd;
supply0 gnd;
wire net_0;
nor (strong0, strong1) #(100) nor2_0 (net_0, inAa, inAb);
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(inOb), .inb(net_0), .out(out));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_0));
endmodule |
module orangeTSMC180nm__wire_R_26m_500_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_500_C_0_025f wire_0(.a(a));
endmodule |
module jtag__slaveBit(din, phi2, slave);
input din;
input phi2;
output slave;
supply1 vdd;
supply0 gnd;
wire net_6, net_7;
not (strong0, strong1) #(100) inv_0 (slave, net_7);
scanChainFive__scanL scanL_0(.in(net_6), .out(net_7));
scanChainFive__scanP scanP_0(.in(phi2), .src(din), .drn(net_6));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 wire180_0(.a(slave));
endmodule |
module redFour__NMOS_X_1_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule |
module orangeTSMC180nm__wire_R_26m_750_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_750_C_0_025f wire_0(.a(a));
endmodule |
module orangeTSMC180nm__wire_R_26m_1000_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_1000_C_0_025f wire_0(.a(a));
endmodule |
module jtag__stateBit(next, phi1, phi2, rst, master, slave, slaveBar);
input next;
input phi1;
input phi2;
input rst;
output master;
output slave;
output slaveBar;
supply1 vdd;
supply0 gnd;
wire net_12, net_13, net_14, net_17;
redFour__NMOS_X_1_667_Delay_100 NMOS_0(.g(rst), .d(net_12), .s(gnd));
not (strong0, strong1) #(100) inv_0 (slave, slaveBar);
not (strong0, strong1) #(100) inv_1 (slaveBar, net_17);
not (strong0, strong1) #(100) inv_2 (master, net_13);
scanChainFive__scanL scanL_0(.in(net_12), .out(net_13));
scanChainFive__scanL scanL_1(.in(net_14), .out(net_17));
scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12));
scanChainFive__scanP scanP_1(.in(phi2), .src(net_13), .drn(net_14));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_0(.a(master));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_1(.a(slave));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500
wire180_2(.a(slaveBar));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_3(.a(next));
endmodule |
module redFour__PMOS_X_1_5_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule |
module jtag__stateBitHI(next, phi1, phi2, rstb, master, slave, slaveBar);
input next;
input phi1;
input phi2;
input rstb;
output master;
output slave;
output slaveBar;
supply1 vdd;
supply0 gnd;
wire net_10, net_11, net_12, net_15;
redFour__PMOS_X_1_5_Delay_100 PMOS_0(.g(rstb), .d(net_12), .s(vdd));
not (strong0, strong1) #(100) inv_0 (slave, slaveBar);
not (strong0, strong1) #(100) inv_1 (slaveBar, net_15);
not (strong0, strong1) #(100) inv_2 (master, net_10);
scanChainFive__scanL scanL_0(.in(net_12), .out(net_10));
scanChainFive__scanL scanL_1(.in(net_11), .out(net_15));
scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12));
scanChainFive__scanP scanP_1(.in(phi2), .src(net_10), .drn(net_11));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_0(.a(slave));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500
wire180_1(.a(slaveBar));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(next));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_3(.a(master));
endmodule |
module orangeTSMC180nm__wire_R_26m_675_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_675_C_0_025f wire_0(.a(a));
endmodule |
module orangeTSMC180nm__wire_R_26m_1500_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_1500_C_0_025f wire_0(.a(a));
endmodule |
module jtag__tapCtlJKL(TMS, TRSTb, phi1, phi2, CapDR, CapIR, Idle, PauseDR,
PauseIR, Reset, Reset_s, SelDR, SelIR, ShftDR, ShftIR, UpdDR, UpdIR,
X1DR, X1IR, X2DR, X2IR);
input TMS;
input TRSTb;
input phi1;
input phi2;
output CapDR;
output CapIR;
output Idle;
output PauseDR;
output PauseIR;
output Reset;
output Reset_s;
output SelDR;
output SelIR;
output ShftDR;
output ShftIR;
output UpdDR;
output UpdIR;
output X1DR;
output X1IR;
output X2DR;
output X2IR;
supply1 vdd;
supply0 gnd;
wire net_0, net_2, net_4, net_6, net_12, net_13, net_14, net_15, net_16;
wire net_17, net_18, net_19, net_20, net_22, net_23, net_24, net_25, net_26;
wire net_28, net_29, net_31, net_32, net_34, net_40, net_43, net_44, net_48;
wire net_50, net_52, net_54, net_55, net_56, net_58, net_59, net_60, net_64;
wire net_67, net_68, net_70, net_71, net_72, net_74, net_75, net_76, net_79;
wire net_80, rst, stateBit_1_slave, stateBit_5_slaveBar, stateBit_6_slaveBar;
wire stateBit_9_slaveBar, stateBit_10_slaveBar, stateBit_11_slave;
wire stateBit_12_slave;
not (strong0, strong1) #(100) inv_0 (rst, TRSTb);
not (strong0, strong1) #(100) inv_1 (net_24, net_12);
redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1
nand2n_0(.ina(net_13), .inb(net_14), .out(net_0));
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nand2n_1(.ina(net_15), .inb(net_16), .out(net_4));
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nand2n_2(.ina(net_17), .inb(net_18), .out(net_2));
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nand2n_3(.ina(net_19), .inb(net_20), .out(net_6));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(net_12), .inb(net_23), .out(net_22));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_1(.ina(net_24), .inb(net_26), .out(net_25));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_2(.ina(net_24), .inb(net_29), .out(net_28));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_3(.ina(net_24), .inb(net_32), .out(net_31));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_4(.ina(net_12), .inb(net_26), .out(net_34));
jtag__o2a o2a_0(.inAa(net_2), .inAb(net_43), .inOb(net_12), .out(net_40));
jtag__o2a o2a_1(.inAa(net_6), .inAb(net_0), .inOb(net_12), .out(net_44));
jtag__o2a o2a_2(.inAa(net_50), .inAb(net_0), .inOb(net_24), .out(net_48));
jtag__o2a o2a_3(.inAa(net_54), .inAb(net_55), .inOb(net_12), .out(net_52));
jtag__o2a o2a_4(.inAa(net_58), .inAb(net_59), .inOb(net_12), .out(net_56));
jtag__o2a o2a_5(.inAa(net_58), .inAb(net_43), .inOb(net_24), .out(net_60));
jtag__o2a o2a_6(.inAa(net_54), .inAb(net_67), .inOb(net_24), .out(net_64));
jtag__o2a o2a_7(.inAa(net_70), .inAb(net_71), .inOb(net_24), .out(net_68));
jtag__o2a o2a_8(.inAa(net_74), .inAb(net_75), .inOb(net_24), .out(net_72));
jtag__o2a o2a_9(.inAa(Reset_s), .inAb(net_79), .inOb(net_24), .out(net_76));
jtag__o2a o2a_10(.inAa(net_4), .inAb(net_67), .inOb(net_12), .out(net_80));
jtag__slaveBit slaveBit_0(.din(TMS), .phi2(phi2), .slave(net_12));
jtag__stateBit stateBit_0(.next(net_25), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(SelIR), .slave(net_79), .slaveBar(net_23));
jtag__stateBit stateBit_1(.next(net_48), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(SelDR), .slave(stateBit_1_slave), .slaveBar(net_26));
jtag__stateBit stateBit_2(.next(net_34), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(CapDR), .slave(net_75), .slaveBar(net_16));
jtag__stateBit stateBit_3(.next(net_22), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(CapIR), .slave(net_71), .slaveBar(net_18));
jtag__stateBit stateBit_4(.next(net_44), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(Idle), .slave(net_50), .slaveBar(net_20));
jtag__stateBit stateBit_5(.next(net_68), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(X1IR), .slave(net_58), .slaveBar(stateBit_5_slaveBar));
jtag__stateBit stateBit_6(.next(net_72), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(X1DR), .slave(net_54), .slaveBar(stateBit_6_slaveBar));
jtag__stateBit stateBit_7(.next(net_80), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(ShftDR), .slave(net_74), .slaveBar(net_15));
jtag__stateBit stateBit_8(.next(net_40), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(ShftIR), .slave(net_70), .slaveBar(net_17));
jtag__stateBit stateBit_9(.next(net_28), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(X2IR), .slave(net_43), .slaveBar(stateBit_9_slaveBar));
jtag__stateBit stateBit_10(.next(net_31), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(X2DR), .slave(net_67),
.slaveBar(stateBit_10_slaveBar));
jtag__stateBit stateBit_11(.next(net_64), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(UpdDR), .slave(stateBit_11_slave),
.slaveBar(net_14));
jtag__stateBit stateBit_12(.next(net_60), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(UpdIR), .slave(stateBit_12_slave),
.slaveBar(net_13));
jtag__stateBit stateBit_13(.next(net_56), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(PauseIR), .slave(net_59), .slaveBar(net_29));
jtag__stateBit stateBit_14(.next(net_52), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(PauseDR), .slave(net_55), .slaveBar(net_32));
jtag__stateBitHI stateBit_15(.next(net_76), .phi1(phi1), .phi2(phi2),
.rstb(TRSTb), .master(Reset), .slave(Reset_s), .slaveBar(net_19));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_4));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_1(.a(net_2));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(net_6));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675 wire180_3(.a(net_0));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500 wire180_4(.a(rst));
endmodule |
module jtag__jtagControl(TCK, TDI, TDIx, TMS, TRSTb, phi1_fb, phi2_fb, Cap,
ExTest, SelBS, SelDR, Shft, TDOb, Upd, phi1, phi2);
input TCK;
input TDI;
input TDIx;
input TMS;
input TRSTb;
input phi1_fb;
input phi2_fb;
output Cap;
output ExTest;
output SelBS;
output [12:0] SelDR;
output Shft;
output TDOb;
output Upd;
output phi1;
output phi2;
supply1 vdd;
supply0 gnd;
wire jtagScan_0_write, net_0, net_1, net_2, net_3, net_6, net_8, net_10;
wire net_33, net_35, net_37, net_38, net_41, net_47, net_48, net_50, net_51;
wire net_52, net_55, net_56, net_62, net_64, net_68, net_73, net_75, net_79;
wire net_97, net_99, net_103, net_128, tapCtlJK_0_Idle, tapCtlJK_0_PauseDR;
wire tapCtlJK_0_PauseIR, tapCtlJK_0_Reset, tapCtlJK_0_SelDR, tapCtlJK_0_SelIR;
wire tapCtlJK_0_X1DR, tapCtlJK_0_X2DR, tapCtlJK_0_X2IR;
wire [8:1] IR;
wire [8:1] IRb;
jtag__BR BR_0(.SDI(TDI), .phi1(net_68), .phi2(net_73), .read(net_99),
.SDO(net_97));
jtag__IR IR_0(.SDI(TDI), .phi1(net_79), .phi2(net_75), .read(net_55),
.reset(net_56), .write(net_103), .IR(IR[8:1]), .IRb(IRb[8:1]),
.SDO(net_128));
jtag__IRdecode IRdecode_0(.IR(IR[4:1]), .IRb(IRb[4:1]), .Bypass(net_41),
.ExTest(ExTest), .SamplePreload(net_47), .ScanPath(SelDR[12:0]));
redFour__PMOSwk_X_0_222_Delay_100 PMOSwk_0(.g(gnd), .d(TDIx), .s(vdd));
jtag__clockGen clockGen_0(.clk(TCK), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb),
.phi1_out(net_10), .phi2_out(net_8));
not (strong0, strong1) #(100) inv_0 (net_0, net_3);
not (strong0, strong1) #(100) inv_1 (SelBS, net_48);
not (strong0, strong1) #(100) inv_2 (net_6, net_50);
not (strong0, strong1) #(100) inv_3 (Cap, net_37);
not (strong0, strong1) #(100) inv_4 (Shft, net_51);
not (strong0, strong1) #(100) inv_5 (net_51, net_52);
not (strong0, strong1) #(100) inv_6 (Upd, net_38);
jtag__jtagIRControl jtagIRCo_0(.capture(net_62), .phi1_fb(net_79),
.phi1_in(phi1), .phi2_fb(net_75), .phi2_in(phi2), .shift(net_2),
.update(net_64), .phi1_out(net_79), .phi2_out(net_75), .read(net_55),
.write(net_103));
jtag__jtagScanControl jtagScan_0(.TDI(net_97), .capture(Cap),
.phi1_fb(net_68), .phi1_in(phi1), .phi2_fb(net_73), .phi2_in(phi2),
.sel(net_41), .shift(Shft), .update(gnd), .TDO(TDIx), .phi1_out(net_68),
.phi2_out(net_73), .read(net_99), .write(jtagScan_0_write));
jtag__mux2_phi2 mux2_phi_0(.Din0(TDIx), .Din1(net_128), .phi2(phi2),
.sel(net_0), .Dout(net_50));
nand (strong0, strong1) #(100) nand2_0 (net_37, IR[8], net_35);
nand (strong0, strong1) #(100) nand2_1 (net_38, IR[7], net_33);
nor (strong0, strong1) #(100) nor2_0 (net_3, net_1, net_2);
nor (strong0, strong1) #(100) nor2_1 (net_48, net_47, ExTest);
jtag__scanAmp1w1648 scanAmp1_0(.in(net_6), .out(TDOb));
jtag__scanAmp1w1648 scanAmp1_1(.in(net_8), .out(phi2));
jtag__scanAmp1w1648 scanAmp1_2(.in(net_10), .out(phi1));
jtag__tapCtlJKL tapCtlJK_0(.TMS(TMS), .TRSTb(TRSTb), .phi1(phi1),
.phi2(phi2), .CapDR(net_35), .CapIR(net_62), .Idle(tapCtlJK_0_Idle),
.PauseDR(tapCtlJK_0_PauseDR), .PauseIR(tapCtlJK_0_PauseIR),
.Reset(tapCtlJK_0_Reset), .Reset_s(net_56), .SelDR(tapCtlJK_0_SelDR),
.SelIR(tapCtlJK_0_SelIR), .ShftDR(net_52), .ShftIR(net_2),
.UpdDR(net_33), .UpdIR(net_64), .X1DR(tapCtlJK_0_X1DR), .X1IR(net_1),
.X2DR(tapCtlJK_0_X2DR), .X2IR(tapCtlJK_0_X2IR));
endmodule |
module jtag__JTAGamp(leaf, root);
input [8:1] leaf;
input [5:1] root;
supply1 vdd;
supply0 gnd;
jtag__scanAmp1w1648 toLeaf_5_(.in(root[5]), .out(leaf[5]));
jtag__scanAmp1w1648 toLeaf_4_(.in(root[4]), .out(leaf[4]));
jtag__scanAmp1w1648 toLeaf_3_(.in(root[3]), .out(leaf[3]));
jtag__scanAmp1w1648 toLeaf_2_(.in(root[2]), .out(leaf[2]));
jtag__scanAmp1w1648 toLeaf_1_(.in(root[1]), .out(leaf[1]));
endmodule |
module jtag__jtagScanCtlWBuf(TDI, cap, phi1, phi2, sel, shift, upd, TDO,
leaf);
input TDI;
input cap;
input phi1;
input phi2;
input sel;
input shift;
input upd;
output TDO;
input [8:1] leaf;
supply1 vdd;
supply0 gnd;
wire [5:2] a;
jtag__JTAGamp JTAGamp_0(.leaf(leaf[8:1]), .root({a[5], a[4], a[3], a[2],
TDI}));
jtag__jtagScanControl jtagScan_0(.TDI(leaf[8]), .capture(cap),
.phi1_fb(leaf[6]), .phi1_in(phi1), .phi2_fb(leaf[7]), .phi2_in(phi2),
.sel(sel), .shift(shift), .update(upd), .TDO(TDO), .phi1_out(a[3]),
.phi2_out(a[2]), .read(a[5]), .write(a[4]));
endmodule |
module jtag__jtagScanCtlGroup(TDI, capture, phi1_in, phi2_in, selBS, sel,
shift, update, TDO, BS, leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6,
leaf7, leaf8, leaf9, leaf10, leaf11, leaf12);
input TDI;
input capture;
input phi1_in;
input phi2_in;
input selBS;
input [12:0] sel;
input shift;
input update;
output TDO;
input [8:1] BS;
input [8:1] leaf0;
input [8:1] leaf1;
input [8:1] leaf2;
input [8:1] leaf3;
input [8:1] leaf4;
input [8:1] leaf5;
input [8:1] leaf6;
input [8:1] leaf7;
input [8:1] leaf8;
input [8:1] leaf9;
input [8:1] leaf10;
input [8:1] leaf11;
input [8:1] leaf12;
supply1 vdd;
supply0 gnd;
jtag__jtagScanCtlWBuf jtagScan_1(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[0]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf0[8:1]));
jtag__jtagScanCtlWBuf jtagScan_2(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[10]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf10[8:1]));
jtag__jtagScanCtlWBuf jtagScan_3(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[12]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf12[8:1]));
jtag__jtagScanCtlWBuf jtagScan_4(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[11]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf11[8:1]));
jtag__jtagScanCtlWBuf jtagScan_5(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[9]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf9[8:1]));
jtag__jtagScanCtlWBuf jtagScan_6(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[8]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf8[8:1]));
jtag__jtagScanCtlWBuf jtagScan_7(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[6]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf6[8:1]));
jtag__jtagScanCtlWBuf jtagScan_8(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[5]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf5[8:1]));
jtag__jtagScanCtlWBuf jtagScan_9(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[4]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf4[8:1]));
jtag__jtagScanCtlWBuf jtagScan_10(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[3]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf3[8:1]));
jtag__jtagScanCtlWBuf jtagScan_11(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[2]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf2[8:1]));
jtag__jtagScanCtlWBuf jtagScan_12(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[1]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf1[8:1]));
jtag__jtagScanCtlWBuf jtagScan_13(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[7]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf7[8:1]));
jtag__jtagScanCtlWBuf jtagScan_16(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(selBS), .shift(shift), .upd(update), .TDO(TDO),
.leaf(BS[8:1]));
endmodule |
module jtag__jtagCentral_LEIGNORE_1(TCK, TDI, TMS, TRSTb, ExTest, TDOb, BS,
leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6, leaf7, leaf8, leaf9,
leaf10, leaf11, leaf12);
input TCK;
input TDI;
input TMS;
input TRSTb;
output ExTest;
output TDOb;
input [8:1] BS;
input [8:1] leaf0;
input [8:1] leaf1;
input [8:1] leaf2;
input [8:1] leaf3;
input [8:1] leaf4;
input [8:1] leaf5;
input [8:1] leaf6;
input [8:1] leaf7;
input [8:1] leaf8;
input [8:1] leaf9;
input [8:1] leaf10;
input [8:1] leaf11;
input [8:1] leaf12;
supply1 vdd;
supply0 gnd;
wire net_10, net_14, net_15, net_17, net_24, net_25, net_50;
wire [0:12] net_6;
jtag__jtagControl jtagCont_0(.TCK(TCK), .TDI(TDI), .TDIx(net_15), .TMS(TMS),
.TRSTb(TRSTb), .phi1_fb(net_24), .phi2_fb(net_10), .Cap(net_25),
.ExTest(ExTest), .SelBS(net_50), .SelDR({net_6[0], net_6[1], net_6[2],
net_6[3], net_6[4], net_6[5], net_6[6], net_6[7], net_6[8], net_6[9],
net_6[10], net_6[11], net_6[12]}), .Shft(net_17), .TDOb(TDOb),
.Upd(net_14), .phi1(net_24), .phi2(net_10));
jtag__jtagScanCtlGroup jtagScan_0(.TDI(TDI), .capture(net_25),
.phi1_in(net_24), .phi2_in(net_10), .selBS(net_50), .sel({net_6[0],
net_6[1], net_6[2], net_6[3], net_6[4], net_6[5], net_6[6], net_6[7],
net_6[8], net_6[9], net_6[10], net_6[11], net_6[12]}), .shift(net_17),
.update(net_14), .TDO(net_15), .BS(BS[8:1]), .leaf0(leaf0[8:1]),
.leaf1(leaf1[8:1]), .leaf2(leaf2[8:1]), .leaf3(leaf3[8:1]),
.leaf4(leaf4[8:1]), .leaf5(leaf5[8:1]), .leaf6(leaf6[8:1]),
.leaf7(leaf7[8:1]), .leaf8(leaf8[8:1]), .leaf9(leaf9[8:1]),
.leaf10(leaf10[8:1]), .leaf11(leaf11[8:1]), .leaf12(leaf12[8:1]));
endmodule |
module scanFansFour__jtag_endcap(jtag);
input [8:4] jtag;
endmodule |
module testCell(TCK, TDI, TMS, TRSTb, TDOb);
input TCK;
input TDI;
input TMS;
input TRSTb;
output TDOb;
supply1 vdd;
supply0 gnd;
wire jtagCent_0_ExTest;
wire [4:0] net_5;
wire [4:0] net_6;
wire [4:0] net_7;
wire [4:0] net_8;
wire [4:0] net_9;
wire [4:0] net_10;
wire [4:0] net_11;
wire [4:0] net_12;
wire [4:0] net_13;
wire [4:0] net_14;
wire [4:0] net_15;
wire [4:0] net_16;
wire [4:0] net_17;
wire [4:0] net_18;
jtag__jtagCentral_LEIGNORE_1 jtagCent_0(.TCK(TCK), .TDI(TDI), .TMS(TMS),
.TRSTb(TRSTb), .ExTest(jtagCent_0_ExTest), .TDOb(TDOb), .BS({net_6[0],
net_6[1], net_6[2], net_6[3], net_6[4], net_6[2], net_6[1], net_6[0]}),
.leaf0({net_7[0], net_7[1], net_7[2], net_7[3], net_7[4], net_7[2],
net_7[1], net_7[0]}), .leaf1({net_18[0], net_18[1], net_18[2], net_18[3],
net_18[4], net_18[2], net_18[1], net_18[0]}), .leaf2({net_17[0],
net_17[1], net_17[2], net_17[3], net_17[4], net_17[2], net_17[1],
net_17[0]}), .leaf3({net_16[0], net_16[1], net_16[2], net_16[3],
net_16[4], net_16[2], net_16[1], net_16[0]}), .leaf4({net_15[0],
net_15[1], net_15[2], net_15[3], net_15[4], net_15[2], net_15[1],
net_15[0]}), .leaf5({net_14[0], net_14[1], net_14[2], net_14[3],
net_14[4], net_14[2], net_14[1], net_14[0]}), .leaf6({net_13[0],
net_13[1], net_13[2], net_13[3], net_13[4], net_13[2], net_13[1],
net_13[0]}), .leaf7({net_12[0], net_12[1], net_12[2], net_12[3],
net_12[4], net_12[2], net_12[1], net_12[0]}), .leaf8({net_11[0],
net_11[1], net_11[2], net_11[3], net_11[4], net_11[2], net_11[1],
net_11[0]}), .leaf9({net_10[0], net_10[1], net_10[2], net_10[3],
net_10[4], net_10[2], net_10[1], net_10[0]}), .leaf10({net_9[0],
net_9[1], net_9[2], net_9[3], net_9[4], net_9[2], net_9[1], net_9[0]}),
.leaf11({net_8[0], net_8[1], net_8[2], net_8[3], net_8[4], net_8[2],
net_8[1], net_8[0]}), .leaf12({net_5[0], net_5[1], net_5[2], net_5[3],
net_5[4], net_5[2], net_5[1], net_5[0]}));
scanFansFour__jtag_endcap jtag_end_0(.jtag({net_5[0], net_5[1], net_5[2],
net_5[4], net_5[3]}));
scanFansFour__jtag_endcap jtag_end_1(.jtag({net_8[0], net_8[1], net_8[2],
net_8[4], net_8[3]}));
scanFansFour__jtag_endcap jtag_end_2(.jtag({net_9[0], net_9[1], net_9[2],
net_9[4], net_9[3]}));
scanFansFour__jtag_endcap jtag_end_3(.jtag({net_10[0], net_10[1], net_10[2],
net_10[4], net_10[3]}));
scanFansFour__jtag_endcap jtag_end_4(.jtag({net_11[0], net_11[1], net_11[2],
net_11[4], net_11[3]}));
scanFansFour__jtag_endcap jtag_end_5(.jtag({net_12[0], net_12[1], net_12[2],
net_12[4], net_12[3]}));
scanFansFour__jtag_endcap jtag_end_6(.jtag({net_13[0], net_13[1], net_13[2],
net_13[4], net_13[3]}));
scanFansFour__jtag_endcap jtag_end_7(.jtag({net_14[0], net_14[1], net_14[2],
net_14[4], net_14[3]}));
scanFansFour__jtag_endcap jtag_end_8(.jtag({net_15[0], net_15[1], net_15[2],
net_15[4], net_15[3]}));
scanFansFour__jtag_endcap jtag_end_9(.jtag({net_16[0], net_16[1], net_16[2],
net_16[4], net_16[3]}));
scanFansFour__jtag_endcap jtag_end_10(.jtag({net_17[0], net_17[1], net_17[2],
net_17[4], net_17[3]}));
scanFansFour__jtag_endcap jtag_end_11(.jtag({net_18[0], net_18[1], net_18[2],
net_18[4], net_18[3]}));
scanFansFour__jtag_endcap jtag_end_12(.jtag({net_7[0], net_7[1], net_7[2],
net_7[4], net_7[3]}));
scanFansFour__jtag_endcap jtag_end_13(.jtag({net_6[0], net_6[1], net_6[2],
net_6[4], net_6[3]}));
endmodule |
module tb_cocotb (
//Parameters
//Registers/Wires
input rst, //reset
input clk,
output linkup, //link is finished
output sata_ready,
output sata_busy,
//input write_data_stb,
//input read_data_stb,
input [7:0] hard_drive_command,
input execute_command_stb,
input command_layer_reset,
input [15:0] sector_count,
input [47:0] sector_address,
output d2h_interrupt,
output d2h_notification,
output [3:0] d2h_port_mult,
output [7:0] d2h_device,
output [47:0] d2h_lba,
output [15:0] d2h_sector_count,
output [7:0] d2h_status,
output [7:0] d2h_error,
input u2h_write_enable,
output u2h_write_finished,
input [23:0] u2h_write_count,
input h2u_read_enable,
output [23:0] h2u_read_total_count,
output h2u_read_error,
output h2u_read_busy,
output u2h_read_error,
output transport_layer_ready,
output link_layer_ready,
output phy_ready,
input prim_scrambler_en,
input data_scrambler_en,
//Data Interface
output tx_set_elec_idle,
output rx_is_elec_idle,
output hd_ready,
input platform_ready,
//Debug
input hold,
input single_rdwr
);
reg [31:0] test_id = 0;
wire [31:0] tx_dout;
wire tx_is_k;
wire tx_comm_reset;
wire tx_comm_wake;
wire tx_elec_idle;
wire [31:0] rx_din;
wire [3:0] rx_is_k;
wire rx_elec_idle;
wire comm_init_detect;
wire comm_wake_detect;
reg r_rst;
reg r_write_data_stb;
reg r_read_data_stb;
reg r_command_layer_reset;
reg [15:0] r_sector_count;
reg [47:0] r_sector_address;
reg r_prim_scrambler_en;
reg r_data_scrambler_en;
reg r_platform_ready;
reg r_dout_count;
reg r_hold;
reg r_u2h_write_enable;
reg [23:0] r_u2h_write_count;
reg r_h2u_read_enable;
reg [7:0] r_hard_drive_command;
reg r_execute_command_stb;
wire hd_read_from_host;
wire [31:0] hd_data_from_host;
wire hd_write_to_host;
wire [31:0] hd_data_to_host;
wire [31:0] user_dout;
wire user_dout_ready;
wire user_dout_activate;
wire user_dout_stb;
wire [23:0] user_dout_size;
wire [31:0] user_din;
wire user_din_stb;
wire [1:0] user_din_ready;
wire [1:0] user_din_activate;
wire [23:0] user_din_size;
wire dma_activate_stb;
wire d2h_reg_stb;
wire pio_setup_stb;
wire d2h_data_stb;
wire dma_setup_stb;
wire set_device_bits_stb;
wire [7:0] d2h_fis;
wire i_rx_byte_is_aligned;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//always @ (*) r_write_data_stb = write_data_stb;
//always @ (*) r_read_data_stb = read_data_stb;
always @ (*) r_command_layer_reset= command_layer_reset;
always @ (*) r_sector_count = sector_count;
always @ (*) r_sector_address = sector_address;
always @ (*) r_prim_scrambler_en = prim_scrambler_en;
always @ (*) r_data_scrambler_en = data_scrambler_en;
always @ (*) r_platform_ready = platform_ready;
always @ (*) r_hold = hold;
always @ (*) r_u2h_write_enable = u2h_write_enable;
always @ (*) r_u2h_write_count = u2h_write_count;
always @ (*) r_h2u_read_enable = h2u_read_enable;
always @ (*) r_hard_drive_command = hard_drive_command;
always @ (*) r_execute_command_stb= execute_command_stb;
//Submodules
//User Generated Test Data
test_in user_2_hd_generator(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.finished (u2h_write_finished ),
.write_count (r_u2h_write_count ),
.ready (user_din_ready ),
.activate (user_din_activate ),
.fifo_data (user_din ),
.fifo_size (user_din_size ),
.strobe (user_din_stb )
);
//Module to process data from Hard Drive to User
test_out hd_2_user_reader(
.clk (clk ),
.rst (rst ),
.busy (h2u_read_busy ),
.enable (r_h2u_read_enable ),
.error (h2u_read_error ),
.total_count (h2u_read_total_count ),
.ready (user_dout_ready ),
.activate (user_dout_activate ),
.size (user_dout_size ),
.data (user_dout ),
.strobe (user_dout_stb )
);
//hd data reader core
hd_data_reader user_2_hd_reader(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.error (u2h_read_error ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host )
);
//hd data writer core
hd_data_writer hd_2_user_generator(
.clk (clk ),
.rst (rst ),
.enable (r_h2u_read_enable ),
.data (hd_data_to_host ),
.strobe (hd_write_to_host )
);
sata_stack ss (
.rst (r_rst ), //reset
.clk (clk ), //clock used to run the stack
.command_layer_reset (r_command_layer_reset),
.platform_ready (platform_ready ), //the underlying physical platform is
.platform_error ( ),
.linkup (linkup ), //link is finished
.sata_ready (sata_ready ),
.sata_busy (sata_busy ),
.send_sync_escape (1'b0 ),
.hard_drive_error ( ),
.pio_data_ready ( ),
//Host to Device Control
// .write_data_stb (r_write_data_stb ),
// .read_data_stb (r_read_data_stb ),
.hard_drive_command (r_hard_drive_command ),
.execute_command_stb (r_execute_command_stb),
.user_features (16'h0000 ),
.sector_count (r_sector_count ),
.sector_address (r_sector_address ),
.dma_activate_stb (dma_activate_stb ),
.d2h_reg_stb (d2h_reg_stb ),
.pio_setup_stb (pio_setup_stb ),
.d2h_data_stb (d2h_data_stb ),
.dma_setup_stb (dma_setup_stb ),
.set_device_bits_stb (set_device_bits_stb ),
.d2h_fis (d2h_fis ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//Data from host to the hard drive path
.data_in_clk (clk ),
.data_in_clk_valid (1'b1 ),
.user_din (user_din ), //User Data Here
.user_din_stb (user_din_stb ), //Strobe Each Data word in here
.user_din_ready (user_din_ready ), //Using PPFIFO Ready Signal
.user_din_activate (user_din_activate ), //Activate PPFIFO Channel
.user_din_size (user_din_size ), //Find the size of the data to write to the device
//Data from hard drive to host path
.data_out_clk (clk ),
.data_out_clk_valid (1'b1 ),
.user_dout (user_dout ),
.user_dout_ready (user_dout_ready ),
.user_dout_activate (user_dout_activate ),
.user_dout_stb (user_dout_stb ),
.user_dout_size (user_dout_size ),
.transport_layer_ready (transport_layer_ready),
.link_layer_ready (link_layer_ready ),
.phy_ready (phy_ready ),
.phy_error (1'b0 ),
.tx_dout (tx_dout ),
.tx_is_k (tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_elec_idle (tx_elec_idle ),
.tx_oob_complete (1'b1 ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.rx_elec_idle (rx_elec_idle ),
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
//.prim_scrambler_en (r_prim_scrambler_en ),
.prim_scrambler_en (1'b1 ),
//.data_scrambler_en (r_data_scrambler_en )
.data_scrambler_en (1'b1 )
);
faux_sata_hd fshd (
.rst (r_rst ),
.clk (clk ),
.tx_dout (rx_din ),
.tx_is_k (rx_is_k ),
.rx_din (tx_dout ),
.rx_is_k ({3'b000, tx_is_k} ),
.rx_is_elec_idle (tx_elec_idle ),
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
.comm_reset_detect (tx_comm_reset ),
.comm_wake_detect (tx_comm_wake ),
.tx_comm_reset (comm_init_detect ),
.tx_comm_wake (comm_wake_detect ),
.hd_ready (hd_ready ),
// .phy_ready (phy_ready ),
//.dbg_data_scrambler_en (r_data_scrambler_en ),
.dbg_data_scrambler_en (1'b1 ),
.dbg_hold (r_hold ),
.dbg_ll_write_start (1'b0 ),
.dbg_ll_write_data (32'h0 ),
.dbg_ll_write_size (0 ),
.dbg_ll_write_hold (1'b0 ),
.dbg_ll_write_abort (1'b0 ),
.dbg_ll_read_ready (1'b0 ),
.dbg_t_en (1'b0 ),
.dbg_send_reg_stb (1'b0 ),
.dbg_send_dma_act_stb (1'b0 ),
.dbg_send_data_stb (1'b0 ),
.dbg_send_pio_stb (1'b0 ),
.dbg_send_dev_bits_stb (1'b0 ),
.dbg_pio_transfer_count(16'h0000 ),
.dbg_pio_direction (1'b0 ),
.dbg_pio_e_status (8'h00 ),
.dbg_d2h_interrupt (1'b0 ),
.dbg_d2h_notification (1'b0 ),
.dbg_d2h_status (8'b0 ),
.dbg_d2h_error (8'b0 ),
.dbg_d2h_port_mult (4'b0000 ),
.dbg_d2h_device (8'h00 ),
.dbg_d2h_lba (48'h000000000000 ),
.dbg_d2h_sector_count (16'h0000 ),
.dbg_cl_if_data (32'b0 ),
.dbg_cl_if_ready (1'b0 ),
.dbg_cl_if_size (24'h0 ),
.dbg_cl_of_ready (2'b0 ),
.dbg_cl_of_size (24'h0 ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host ),
.hd_write_to_host (hd_write_to_host ),
.hd_data_to_host (hd_data_to_host )
);
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule |
module receives an Ethernet frame on an AXI stream interface, decodes
and strips the headers, then produces the header fields in parallel along
with the payload in a separate AXI stream.
*/
reg read_eth_header_reg = 1'b1, read_eth_header_next;
reg read_eth_payload_reg = 1'b0, read_eth_payload_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg flush_save;
reg transfer_in_save;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg [DATA_WIDTH-1:0] save_axis_tdata_reg = 64'd0;
reg [KEEP_WIDTH-1:0] save_axis_tkeep_reg = 8'd0;
reg save_axis_tlast_reg = 1'b0;
reg save_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] shift_axis_tdata;
reg [KEEP_WIDTH-1:0] shift_axis_tkeep;
reg shift_axis_tvalid;
reg shift_axis_tlast;
reg shift_axis_tuser;
reg shift_axis_input_tready;
reg shift_axis_extra_cycle_reg = 1'b0;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
always @* begin
if (OFFSET == 0) begin
// passthrough if no overlap
shift_axis_tdata = s_axis_tdata;
shift_axis_tkeep = s_axis_tkeep;
shift_axis_tvalid = s_axis_tvalid;
shift_axis_tlast = s_axis_tlast;
shift_axis_tuser = s_axis_tuser;
shift_axis_input_tready = 1'b1;
end else if (shift_axis_extra_cycle_reg) begin
shift_axis_tdata = {s_axis_tdata, save_axis_tdata_reg} >> (OFFSET*8);
shift_axis_tkeep = {{KEEP_WIDTH{1'b0}}, save_axis_tkeep_reg} >> OFFSET;
shift_axis_tvalid = 1'b1;
shift_axis_tlast = save_axis_tlast_reg;
shift_axis_tuser = save_axis_tuser_reg;
shift_axis_input_tready = flush_save;
end else begin
shift_axis_tdata = {s_axis_tdata, save_axis_tdata_reg} >> (OFFSET*8);
shift_axis_tkeep = {s_axis_tkeep, save_axis_tkeep_reg} >> OFFSET;
shift_axis_tvalid = s_axis_tvalid;
shift_axis_tlast = (s_axis_tlast && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) == 0));
shift_axis_tuser = (s_axis_tuser && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) == 0));
shift_axis_input_tready = !(s_axis_tlast && s_axis_tready && s_axis_tvalid);
end
end
always @* begin
read_eth_header_next = read_eth_header_reg;
read_eth_payload_next = read_eth_payload_reg;
ptr_next = ptr_reg;
s_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_axis_input_tready && (!m_eth_hdr_valid || m_eth_hdr_ready);
flush_save = 1'b0;
transfer_in_save = 1'b0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
error_header_early_termination_next = 1'b0;
m_eth_payload_axis_tdata_int = shift_axis_tdata;
m_eth_payload_axis_tkeep_int = shift_axis_tkeep;
m_eth_payload_axis_tvalid_int = 1'b0;
m_eth_payload_axis_tlast_int = shift_axis_tlast;
m_eth_payload_axis_tuser_int = shift_axis_tuser;
if ((s_axis_tready && s_axis_tvalid) || (m_eth_payload_axis_tready_int_reg && shift_axis_extra_cycle_reg)) begin
transfer_in_save = 1'b1;
if (read_eth_header_reg) begin
// word transfer in - store it
ptr_next = ptr_reg + 1;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[offset%KEEP_WIDTH])) begin \
field = s_axis_tdata[(offset%KEEP_WIDTH)*8 +: 8]; \
end
`_HEADER_FIELD_(0, m_eth_dest_mac_next[5*8 +: 8])
`_HEADER_FIELD_(1, m_eth_dest_mac_next[4*8 +: 8])
`_HEADER_FIELD_(2, m_eth_dest_mac_next[3*8 +: 8])
`_HEADER_FIELD_(3, m_eth_dest_mac_next[2*8 +: 8])
`_HEADER_FIELD_(4, m_eth_dest_mac_next[1*8 +: 8])
`_HEADER_FIELD_(5, m_eth_dest_mac_next[0*8 +: 8])
`_HEADER_FIELD_(6, m_eth_src_mac_next[5*8 +: 8])
`_HEADER_FIELD_(7, m_eth_src_mac_next[4*8 +: 8])
`_HEADER_FIELD_(8, m_eth_src_mac_next[3*8 +: 8])
`_HEADER_FIELD_(9, m_eth_src_mac_next[2*8 +: 8])
`_HEADER_FIELD_(10, m_eth_src_mac_next[1*8 +: 8])
`_HEADER_FIELD_(11, m_eth_src_mac_next[0*8 +: 8])
`_HEADER_FIELD_(12, m_eth_type_next[1*8 +: 8])
`_HEADER_FIELD_(13, m_eth_type_next[0*8 +: 8])
if (ptr_reg == 13/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[13%KEEP_WIDTH])) begin
if (!shift_axis_tlast) begin
m_eth_hdr_valid_next = 1'b1;
read_eth_header_next = 1'b0;
read_eth_payload_next = 1'b1;
end
end
`undef _HEADER_FIELD_
end
if (read_eth_payload_reg) begin
// transfer payload
m_eth_payload_axis_tdata_int = shift_axis_tdata;
m_eth_payload_axis_tkeep_int = shift_axis_tkeep;
m_eth_payload_axis_tvalid_int = 1'b1;
m_eth_payload_axis_tlast_int = shift_axis_tlast;
m_eth_payload_axis_tuser_int = shift_axis_tuser;
end
if (shift_axis_tlast) begin
if (read_eth_header_next) begin
// don't have the whole header
error_header_early_termination_next = 1'b1;
end
flush_save = 1'b1;
ptr_next = 1'b0;
read_eth_header_next = 1'b1;
read_eth_payload_next = 1'b0;
end
end
end
always @(posedge clk) begin
read_eth_header_reg <= read_eth_header_next;
read_eth_payload_reg <= read_eth_payload_next;
ptr_reg <= ptr_next;
s_axis_tready_reg <= s_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
error_header_early_termination_reg <= error_header_early_termination_next;
busy_reg <= (read_eth_payload_next || ptr_next != 0);
if (transfer_in_save) begin
save_axis_tdata_reg <= s_axis_tdata;
save_axis_tkeep_reg <= s_axis_tkeep;
save_axis_tuser_reg <= s_axis_tuser;
end
if (flush_save) begin
save_axis_tlast_reg <= 1'b0;
shift_axis_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_axis_tlast_reg <= s_axis_tlast;
shift_axis_extra_cycle_reg <= OFFSET ? s_axis_tlast && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) != 0) : 1'b0;
end
if (rst) begin
read_eth_header_reg <= 1'b1;
read_eth_payload_reg <= 1'b0;
ptr_reg <= 0;
s_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 1'b0;
save_axis_tlast_reg <= 1'b0;
shift_axis_extra_cycle_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_eth_payload_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule |
module sky130_fd_sc_hs__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_hs__u_edf_p_no_pg u_edf_p_no_pg0 (buf_Q , D_delayed, CLK_delayed, DE_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule |
module tb_top();
reg clk;
reg lfextclk;
reg rst_n;
wire hfclkrst;
wire hfclk = clk & (~hfclkrst);
`define CPU_TOP u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top
`define EXU `CPU_TOP.u_e200_cpu.u_e200_core.u_e200_exu
`define ITCM `CPU_TOP.u_e200_srams.u_e200_itcm_ram.u_e200_itcm_gnrl_ram.u_sirv_sim_ram
`define PC_WRITE_TOHOST `E200_PC_SIZE'h80000086
`define PC_EXT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000a6
`define PC_SFT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000be
`define PC_TMR_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000d6
`define PC_AFTER_SETMTVEC `E200_PC_SIZE'h80000148
wire [`E200_XLEN-1:0] x3 = `EXU.u_e200_exu_regfile.rf_r[3];
wire [`E200_PC_SIZE-1:0] pc = `EXU.u_e200_exu_commit.alu_cmt_i_pc;
reg [31:0] pc_write_to_host_cnt;
reg [31:0] pc_write_to_host_cycle;
reg [31:0] valid_ir_cycle;
reg [31:0] cycle_count;
reg pc_write_to_host_flag;
always @(posedge hfclk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
pc_write_to_host_cnt <= 32'b0;
pc_write_to_host_flag <= 1'b0;
pc_write_to_host_cycle <= 32'b0;
end
else if (pc == `PC_WRITE_TOHOST) begin
pc_write_to_host_cnt <= pc_write_to_host_cnt + 1'b1;
pc_write_to_host_flag <= 1'b1;
if (pc_write_to_host_flag == 1'b0) begin
pc_write_to_host_cycle <= cycle_count;
end
end
end
always @(posedge hfclk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
cycle_count <= 32'b0;
end
else begin
cycle_count <= cycle_count + 1'b1;
end
end
wire i_valid = `EXU.i_valid;
wire i_ready = `EXU.i_ready;
always @(posedge hfclk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
valid_ir_cycle <= 32'b0;
end
else if(i_valid & i_ready & (pc_write_to_host_flag == 1'b0)) begin
valid_ir_cycle <= valid_ir_cycle + 1'b1;
end
end
// Randomly force the external interrupt
`define EXT_IRQ u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.plic_ext_irq
`define SFT_IRQ u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_sft_irq
`define TMR_IRQ u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_tmr_irq
`define U_CPU u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top.u_e200_cpu
`define ITCM_BUS_ERR `U_CPU.u_e200_itcm_ctrl.chk_icb_rsp_err
`define ITCM_BUS_READ `U_CPU.u_e200_itcm_ctrl.e2_icb_read_r
`define STATUS_MIE `U_CPU.u_e200_core.u_e200_exu.u_e200_exu_commit.u_e200_exu_excp.status_mie_r
wire stop_assert_irq = (pc_write_to_host_cnt > 32);
reg tb_itcm_bus_err;
reg tb_ext_irq;
reg tb_tmr_irq;
reg tb_sft_irq;
initial begin
tb_ext_irq = 1'b0;
tb_tmr_irq = 1'b0;
tb_sft_irq = 1'b0;
end
`ifdef ENABLE_TB_FORCE
initial begin
tb_itcm_bus_err = 1'b0;
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 20)) @(posedge clk) tb_itcm_bus_err = 1'b0; // Wait random times
repeat ($urandom_range(1, 200)) @(posedge clk) tb_itcm_bus_err = 1'b1; // Wait random times
if(stop_assert_irq) begin
break;
end
end
end
initial begin
force `EXT_IRQ = tb_ext_irq;
force `SFT_IRQ = tb_sft_irq;
force `TMR_IRQ = tb_tmr_irq;
// We force the bus-error only when:
// It is in common code, not in exception code, by checking MIE bit
// It is in read operation, not write, otherwise the test cannot recover
force `ITCM_BUS_ERR = tb_itcm_bus_err
& `STATUS_MIE
& `ITCM_BUS_READ
;
end
initial begin
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 200)) @(posedge clk) tb_ext_irq = 1'b0; // Wait random times
tb_ext_irq = 1'b1; // assert the irq
@((pc == `PC_EXT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values
tb_ext_irq = 1'b0;
if(stop_assert_irq) begin
break;
end
end
end
initial begin
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 200)) @(posedge clk) tb_sft_irq = 1'b0; // Wait random times
tb_sft_irq = 1'b1; // assert the irq
@((pc == `PC_SFT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values
tb_sft_irq = 1'b0;
if(stop_assert_irq) begin
break;
end
end
end
initial begin
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 200)) @(posedge clk) tb_tmr_irq = 1'b0; // Wait random times
tb_tmr_irq = 1'b1; // assert the irq
@((pc == `PC_TMR_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values
tb_tmr_irq = 1'b0;
if(stop_assert_irq) begin
break;
end
end
end
`endif
reg[8*300:1] testcase;
integer dumpwave;
initial begin
$display("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
if($value$plusargs("TESTCASE=%s",testcase))begin
$display("TESTCASE=%s",testcase);
end
pc_write_to_host_flag <=0;
clk <=0;
lfextclk <=0;
rst_n <=0;
#120 rst_n <=1;
@(pc_write_to_host_cnt == 32'd8) #10 rst_n <=1;
`ifdef ENABLE_TB_FORCE
@((~tb_tmr_irq) & (~tb_sft_irq) & (~tb_ext_irq)) #10 rst_n <=1;// Wait the interrupt to complete
`endif
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~ Test Result Summary ~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~TESTCASE: %s ~~~~~~~~~~~~~", testcase);
$display("~~~~~~~~~~~~~~Total cycle_count value: %d ~~~~~~~~~~~~~", cycle_count);
$display("~~~~~~~~~~The valid Instruction Count: %d ~~~~~~~~~~~~~", valid_ir_cycle);
$display("~~~~~The test ending reached at cycle: %d ~~~~~~~~~~~~~", pc_write_to_host_cycle);
$display("~~~~~~~~~~~~~~~The final x3 Reg value: %d ~~~~~~~~~~~~~", x3);
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
if (x3 == 1) begin
$display("~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ ##### ###### # #~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # # # # #~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # #### #### ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
end
else begin
$display("~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~###### ## # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~##### # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# ###### # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# # # # ######~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
end
#10
$finish;
end
initial begin
#10000000
$display("Time Out !!!");
$finish;
end
always
begin
#2 clk <= ~clk;
end
always
begin
#33 lfextclk <= ~lfextclk;
end
//initial begin
// $value$plusargs("DUMPWAVE=%d",dumpwave);
// if(dumpwave != 0)begin
// // To add your waveform generation function
// end
//end
integer i;
reg [7:0] itcm_mem [0:(`E200_ITCM_RAM_DP*8)-1];
initial begin
$readmemh({testcase, ".verilog"}, itcm_mem);
for (i=0;i<(`E200_ITCM_RAM_DP);i=i+1) begin
`ITCM.mem_r[i][00+7:00] = itcm_mem[i*8+0];
`ITCM.mem_r[i][08+7:08] = itcm_mem[i*8+1];
`ITCM.mem_r[i][16+7:16] = itcm_mem[i*8+2];
`ITCM.mem_r[i][24+7:24] = itcm_mem[i*8+3];
`ITCM.mem_r[i][32+7:32] = itcm_mem[i*8+4];
`ITCM.mem_r[i][40+7:40] = itcm_mem[i*8+5];
`ITCM.mem_r[i][48+7:48] = itcm_mem[i*8+6];
`ITCM.mem_r[i][56+7:56] = itcm_mem[i*8+7];
end
$display("ITCM 0x00: %h", `ITCM.mem_r[8'h00]);
$display("ITCM 0x01: %h", `ITCM.mem_r[8'h01]);
$display("ITCM 0x02: %h", `ITCM.mem_r[8'h02]);
$display("ITCM 0x03: %h", `ITCM.mem_r[8'h03]);
$display("ITCM 0x04: %h", `ITCM.mem_r[8'h04]);
$display("ITCM 0x05: %h", `ITCM.mem_r[8'h05]);
$display("ITCM 0x06: %h", `ITCM.mem_r[8'h06]);
$display("ITCM 0x07: %h", `ITCM.mem_r[8'h07]);
$display("ITCM 0x16: %h", `ITCM.mem_r[8'h16]);
$display("ITCM 0x20: %h", `ITCM.mem_r[8'h20]);
end
wire jtag_TDI = 1'b0;
wire jtag_TDO;
wire jtag_TCK = 1'b0;
wire jtag_TMS = 1'b0;
wire jtag_TRST = 1'b0;
wire jtag_DRV_TDO = 1'b0;
e200_fpga_soc_top u_e200_fpga_soc_top(
.hfclk(hfclk),
.hfclkrst(hfclkrst),
.io_pads_jtag_TCK_i_ival (jtag_TCK),
.io_pads_jtag_TCK_o_oval (),
.io_pads_jtag_TCK_o_oe (),
.io_pads_jtag_TCK_o_ie (),
.io_pads_jtag_TCK_o_pue (),
.io_pads_jtag_TCK_o_ds (),
.io_pads_jtag_TMS_i_ival (jtag_TMS),
.io_pads_jtag_TMS_o_oval (),
.io_pads_jtag_TMS_o_oe (),
.io_pads_jtag_TMS_o_ie (),
.io_pads_jtag_TMS_o_pue (),
.io_pads_jtag_TMS_o_ds (),
.io_pads_jtag_TDI_i_ival (jtag_TDI),
.io_pads_jtag_TDI_o_oval (),
.io_pads_jtag_TDI_o_oe (),
.io_pads_jtag_TDI_o_ie (),
.io_pads_jtag_TDI_o_pue (),
.io_pads_jtag_TDI_o_ds (),
.io_pads_jtag_TDO_i_ival (1'b1),
.io_pads_jtag_TDO_o_oval (jtag_TDO),
.io_pads_jtag_TDO_o_oe (),
.io_pads_jtag_TDO_o_ie (),
.io_pads_jtag_TDO_o_pue (),
.io_pads_jtag_TDO_o_ds (),
.io_pads_jtag_TRST_n_i_ival (jtag_TRST),
.io_pads_jtag_TRST_n_o_oval (),
.io_pads_jtag_TRST_n_o_oe (),
.io_pads_jtag_TRST_n_o_ie (),
.io_pads_jtag_TRST_n_o_pue (),
.io_pads_jtag_TRST_n_o_ds (),
.io_pads_gpio_0_i_ival (1'b0),
.io_pads_gpio_0_o_oval (),
.io_pads_gpio_0_o_oe (),
.io_pads_gpio_0_o_ie (),
.io_pads_gpio_0_o_pue (),
.io_pads_gpio_0_o_ds (),
.io_pads_gpio_1_i_ival (1'b0),
.io_pads_gpio_1_o_oval (),
.io_pads_gpio_1_o_oe (),
.io_pads_gpio_1_o_ie (),
.io_pads_gpio_1_o_pue (),
.io_pads_gpio_1_o_ds (),
.io_pads_gpio_2_i_ival (1'b0),
.io_pads_gpio_2_o_oval (),
.io_pads_gpio_2_o_oe (),
.io_pads_gpio_2_o_ie (),
.io_pads_gpio_2_o_pue (),
.io_pads_gpio_2_o_ds (),
.io_pads_gpio_3_i_ival (1'b0),
.io_pads_gpio_3_o_oval (),
.io_pads_gpio_3_o_oe (),
.io_pads_gpio_3_o_ie (),
.io_pads_gpio_3_o_pue (),
.io_pads_gpio_3_o_ds (),
.io_pads_gpio_4_i_ival (1'b0),
.io_pads_gpio_4_o_oval (),
.io_pads_gpio_4_o_oe (),
.io_pads_gpio_4_o_ie (),
.io_pads_gpio_4_o_pue (),
.io_pads_gpio_4_o_ds (),
.io_pads_gpio_5_i_ival (1'b0),
.io_pads_gpio_5_o_oval (),
.io_pads_gpio_5_o_oe (),
.io_pads_gpio_5_o_ie (),
.io_pads_gpio_5_o_pue (),
.io_pads_gpio_5_o_ds (),
.io_pads_gpio_6_i_ival (1'b0),
.io_pads_gpio_6_o_oval (),
.io_pads_gpio_6_o_oe (),
.io_pads_gpio_6_o_ie (),
.io_pads_gpio_6_o_pue (),
.io_pads_gpio_6_o_ds (),
.io_pads_gpio_7_i_ival (1'b0),
.io_pads_gpio_7_o_oval (),
.io_pads_gpio_7_o_oe (),
.io_pads_gpio_7_o_ie (),
.io_pads_gpio_7_o_pue (),
.io_pads_gpio_7_o_ds (),
.io_pads_gpio_8_i_ival (1'b0),
.io_pads_gpio_8_o_oval (),
.io_pads_gpio_8_o_oe (),
.io_pads_gpio_8_o_ie (),
.io_pads_gpio_8_o_pue (),
.io_pads_gpio_8_o_ds (),
.io_pads_gpio_9_i_ival (1'b0),
.io_pads_gpio_9_o_oval (),
.io_pads_gpio_9_o_oe (),
.io_pads_gpio_9_o_ie (),
.io_pads_gpio_9_o_pue (),
.io_pads_gpio_9_o_ds (),
.io_pads_gpio_10_i_ival (1'b0),
.io_pads_gpio_10_o_oval (),
.io_pads_gpio_10_o_oe (),
.io_pads_gpio_10_o_ie (),
.io_pads_gpio_10_o_pue (),
.io_pads_gpio_10_o_ds (),
.io_pads_gpio_11_i_ival (1'b0),
.io_pads_gpio_11_o_oval (),
.io_pads_gpio_11_o_oe (),
.io_pads_gpio_11_o_ie (),
.io_pads_gpio_11_o_pue (),
.io_pads_gpio_11_o_ds (),
.io_pads_gpio_12_i_ival (1'b0),
.io_pads_gpio_12_o_oval (),
.io_pads_gpio_12_o_oe (),
.io_pads_gpio_12_o_ie (),
.io_pads_gpio_12_o_pue (),
.io_pads_gpio_12_o_ds (),
.io_pads_gpio_13_i_ival (1'b0),
.io_pads_gpio_13_o_oval (),
.io_pads_gpio_13_o_oe (),
.io_pads_gpio_13_o_ie (),
.io_pads_gpio_13_o_pue (),
.io_pads_gpio_13_o_ds (),
.io_pads_gpio_14_i_ival (1'b0),
.io_pads_gpio_14_o_oval (),
.io_pads_gpio_14_o_oe (),
.io_pads_gpio_14_o_ie (),
.io_pads_gpio_14_o_pue (),
.io_pads_gpio_14_o_ds (),
.io_pads_gpio_15_i_ival (1'b0),
.io_pads_gpio_15_o_oval (),
.io_pads_gpio_15_o_oe (),
.io_pads_gpio_15_o_ie (),
.io_pads_gpio_15_o_pue (),
.io_pads_gpio_15_o_ds (),
.io_pads_gpio_16_i_ival (1'b0),
.io_pads_gpio_16_o_oval (),
.io_pads_gpio_16_o_oe (),
.io_pads_gpio_16_o_ie (),
.io_pads_gpio_16_o_pue (),
.io_pads_gpio_16_o_ds (),
.io_pads_gpio_17_i_ival (1'b0),
.io_pads_gpio_17_o_oval (),
.io_pads_gpio_17_o_oe (),
.io_pads_gpio_17_o_ie (),
.io_pads_gpio_17_o_pue (),
.io_pads_gpio_17_o_ds (),
.io_pads_gpio_18_i_ival (1'b0),
.io_pads_gpio_18_o_oval (),
.io_pads_gpio_18_o_oe (),
.io_pads_gpio_18_o_ie (),
.io_pads_gpio_18_o_pue (),
.io_pads_gpio_18_o_ds (),
.io_pads_gpio_19_i_ival (1'b0),
.io_pads_gpio_19_o_oval (),
.io_pads_gpio_19_o_oe (),
.io_pads_gpio_19_o_ie (),
.io_pads_gpio_19_o_pue (),
.io_pads_gpio_19_o_ds (),
.io_pads_gpio_20_i_ival (1'b0),
.io_pads_gpio_20_o_oval (),
.io_pads_gpio_20_o_oe (),
.io_pads_gpio_20_o_ie (),
.io_pads_gpio_20_o_pue (),
.io_pads_gpio_20_o_ds (),
.io_pads_gpio_21_i_ival (1'b0),
.io_pads_gpio_21_o_oval (),
.io_pads_gpio_21_o_oe (),
.io_pads_gpio_21_o_ie (),
.io_pads_gpio_21_o_pue (),
.io_pads_gpio_21_o_ds (),
.io_pads_gpio_22_i_ival (1'b0),
.io_pads_gpio_22_o_oval (),
.io_pads_gpio_22_o_oe (),
.io_pads_gpio_22_o_ie (),
.io_pads_gpio_22_o_pue (),
.io_pads_gpio_22_o_ds (),
.io_pads_gpio_23_i_ival (1'b0),
.io_pads_gpio_23_o_oval (),
.io_pads_gpio_23_o_oe (),
.io_pads_gpio_23_o_ie (),
.io_pads_gpio_23_o_pue (),
.io_pads_gpio_23_o_ds (),
.io_pads_gpio_24_i_ival (1'b0),
.io_pads_gpio_24_o_oval (),
.io_pads_gpio_24_o_oe (),
.io_pads_gpio_24_o_ie (),
.io_pads_gpio_24_o_pue (),
.io_pads_gpio_24_o_ds (),
.io_pads_gpio_25_i_ival (1'b0),
.io_pads_gpio_25_o_oval (),
.io_pads_gpio_25_o_oe (),
.io_pads_gpio_25_o_ie (),
.io_pads_gpio_25_o_pue (),
.io_pads_gpio_25_o_ds (),
.io_pads_gpio_26_i_ival (1'b0),
.io_pads_gpio_26_o_oval (),
.io_pads_gpio_26_o_oe (),
.io_pads_gpio_26_o_ie (),
.io_pads_gpio_26_o_pue (),
.io_pads_gpio_26_o_ds (),
.io_pads_gpio_27_i_ival (1'b0),
.io_pads_gpio_27_o_oval (),
.io_pads_gpio_27_o_oe (),
.io_pads_gpio_27_o_ie (),
.io_pads_gpio_27_o_pue (),
.io_pads_gpio_27_o_ds (),
.io_pads_gpio_28_i_ival (1'b0),
.io_pads_gpio_28_o_oval (),
.io_pads_gpio_28_o_oe (),
.io_pads_gpio_28_o_ie (),
.io_pads_gpio_28_o_pue (),
.io_pads_gpio_28_o_ds (),
.io_pads_gpio_29_i_ival (1'b0),
.io_pads_gpio_29_o_oval (),
.io_pads_gpio_29_o_oe (),
.io_pads_gpio_29_o_ie (),
.io_pads_gpio_29_o_pue (),
.io_pads_gpio_29_o_ds (),
.io_pads_gpio_30_i_ival (1'b0),
.io_pads_gpio_30_o_oval (),
.io_pads_gpio_30_o_oe (),
.io_pads_gpio_30_o_ie (),
.io_pads_gpio_30_o_pue (),
.io_pads_gpio_30_o_ds (),
.io_pads_gpio_31_i_ival (1'b0),
.io_pads_gpio_31_o_oval (),
.io_pads_gpio_31_o_oe (),
.io_pads_gpio_31_o_ie (),
.io_pads_gpio_31_o_pue (),
.io_pads_gpio_31_o_ds (),
.io_pads_qspi_sck_i_ival (1'b1),
.io_pads_qspi_sck_o_oval (),
.io_pads_qspi_sck_o_oe (),
.io_pads_qspi_sck_o_ie (),
.io_pads_qspi_sck_o_pue (),
.io_pads_qspi_sck_o_ds (),
.io_pads_qspi_dq_0_i_ival (1'b1),
.io_pads_qspi_dq_0_o_oval (),
.io_pads_qspi_dq_0_o_oe (),
.io_pads_qspi_dq_0_o_ie (),
.io_pads_qspi_dq_0_o_pue (),
.io_pads_qspi_dq_0_o_ds (),
.io_pads_qspi_dq_1_i_ival (1'b1),
.io_pads_qspi_dq_1_o_oval (),
.io_pads_qspi_dq_1_o_oe (),
.io_pads_qspi_dq_1_o_ie (),
.io_pads_qspi_dq_1_o_pue (),
.io_pads_qspi_dq_1_o_ds (),
.io_pads_qspi_dq_2_i_ival (1'b1),
.io_pads_qspi_dq_2_o_oval (),
.io_pads_qspi_dq_2_o_oe (),
.io_pads_qspi_dq_2_o_ie (),
.io_pads_qspi_dq_2_o_pue (),
.io_pads_qspi_dq_2_o_ds (),
.io_pads_qspi_dq_3_i_ival (1'b1),
.io_pads_qspi_dq_3_o_oval (),
.io_pads_qspi_dq_3_o_oe (),
.io_pads_qspi_dq_3_o_ie (),
.io_pads_qspi_dq_3_o_pue (),
.io_pads_qspi_dq_3_o_ds (),
.io_pads_qspi_cs_0_i_ival (1'b1),
.io_pads_qspi_cs_0_o_oval (),
.io_pads_qspi_cs_0_o_oe (),
.io_pads_qspi_cs_0_o_ie (),
.io_pads_qspi_cs_0_o_pue (),
.io_pads_qspi_cs_0_o_ds (),
.io_pads_aon_erst_n_i_ival (rst_n),//This is the real reset, active low
.io_pads_aon_erst_n_o_oval (),
.io_pads_aon_erst_n_o_oe (),
.io_pads_aon_erst_n_o_ie (),
.io_pads_aon_erst_n_o_pue (),
.io_pads_aon_erst_n_o_ds (),
.io_pads_aon_lfextclk_i_ival (lfextclk),
.io_pads_aon_lfextclk_o_oval (),
.io_pads_aon_lfextclk_o_oe (),
.io_pads_aon_lfextclk_o_ie (),
.io_pads_aon_lfextclk_o_pue (),
.io_pads_aon_lfextclk_o_ds (),
.io_pads_aon_pmu_dwakeup_n_i_ival (1'b1),
.io_pads_aon_pmu_dwakeup_n_o_oval (),
.io_pads_aon_pmu_dwakeup_n_o_oe (),
.io_pads_aon_pmu_dwakeup_n_o_ie (),
.io_pads_aon_pmu_dwakeup_n_o_pue (),
.io_pads_aon_pmu_dwakeup_n_o_ds (),
.io_pads_aon_pmu_vddpaden_i_ival (1'b1),
.io_pads_aon_pmu_vddpaden_o_oval (),
.io_pads_aon_pmu_vddpaden_o_oe (),
.io_pads_aon_pmu_vddpaden_o_ie (),
.io_pads_aon_pmu_vddpaden_o_pue (),
.io_pads_aon_pmu_vddpaden_o_ds ()
);
endmodule |
module sparc_exu_byp
( /*AUTOARG*/
// Outputs
so, byp_alu_rs1_data_e, byp_alu_rs2_data_e_l, byp_alu_rs2_data_e,
exu_lsu_rs3_data_e, exu_spu_rs3_data_e, exu_lsu_rs2_data_e,
byp_alu_rcc_data_e, byp_irf_rd_data_w, exu_tlu_wsr_data_m,
byp_irf_rd_data_w2, byp_ecc_rs3_data_e, byp_ecc_rcc_data_e,
byp_ecl_rs2_31_e, byp_ecl_rs1_31_e, byp_ecl_rs1_63_e,
byp_ecl_rs1_2_0_e, byp_ecl_rs2_3_0_e, byp_ecc_rs1_synd_d,
byp_ecc_rs2_synd_d, byp_ecc_rs3_synd_d,
// Inputs
rclk, se, si, sehold, ecl_byp_rs1_mux2_sel_e,
ecl_byp_rs1_mux2_sel_rf, ecl_byp_rs1_mux2_sel_ld,
ecl_byp_rs1_mux2_sel_usemux1, ecl_byp_rs1_mux1_sel_m,
ecl_byp_rs1_mux1_sel_w, ecl_byp_rs1_mux1_sel_w2,
ecl_byp_rs1_mux1_sel_other, ecl_byp_rcc_mux2_sel_e,
ecl_byp_rcc_mux2_sel_rf, ecl_byp_rcc_mux2_sel_ld,
ecl_byp_rcc_mux2_sel_usemux1, ecl_byp_rcc_mux1_sel_m,
ecl_byp_rcc_mux1_sel_w, ecl_byp_rcc_mux1_sel_w2,
ecl_byp_rcc_mux1_sel_other, ecl_byp_rs2_mux2_sel_e,
ecl_byp_rs2_mux2_sel_rf, ecl_byp_rs2_mux2_sel_ld,
ecl_byp_rs2_mux2_sel_usemux1, ecl_byp_rs2_mux1_sel_m,
ecl_byp_rs2_mux1_sel_w, ecl_byp_rs2_mux1_sel_w2,
ecl_byp_rs2_mux1_sel_other, ecl_byp_rs3_mux2_sel_e,
ecl_byp_rs3_mux2_sel_rf, ecl_byp_rs3_mux2_sel_ld,
ecl_byp_rs3_mux2_sel_usemux1, ecl_byp_rs3_mux1_sel_m,
ecl_byp_rs3_mux1_sel_w, ecl_byp_rs3_mux1_sel_w2,
ecl_byp_rs3_mux1_sel_other, ecl_byp_rs3h_mux2_sel_e,
ecl_byp_rs3h_mux2_sel_rf, ecl_byp_rs3h_mux2_sel_ld,
ecl_byp_rs3h_mux2_sel_usemux1, ecl_byp_rs3h_mux1_sel_m,
ecl_byp_rs3h_mux1_sel_w, ecl_byp_rs3h_mux1_sel_w2,
ecl_byp_rs3h_mux1_sel_other, ecl_byp_rs1_longmux_sel_g2,
ecl_byp_rs1_longmux_sel_w2, ecl_byp_rs1_longmux_sel_ldxa,
ecl_byp_rs2_longmux_sel_g2, ecl_byp_rs2_longmux_sel_w2,
ecl_byp_rs2_longmux_sel_ldxa, ecl_byp_rs3_longmux_sel_g2,
ecl_byp_rs3_longmux_sel_w2, ecl_byp_rs3_longmux_sel_ldxa,
ecl_byp_rs3h_longmux_sel_g2, ecl_byp_rs3h_longmux_sel_w2,
ecl_byp_rs3h_longmux_sel_ldxa, ecl_byp_sel_load_m,
ecl_byp_sel_pipe_m, ecl_byp_sel_ecc_m, ecl_byp_sel_muldiv_g,
ecl_byp_sel_load_g, ecl_byp_sel_restore_g, ecl_byp_std_e_l,
ecl_byp_ldxa_g, alu_byp_rd_data_e, ifu_exu_imm_data_d,
irf_byp_rs1_data_d_l, irf_byp_rs2_data_d_l, irf_byp_rs3_data_d_l,
irf_byp_rs3h_data_d_l, lsu_exu_dfill_data_g, lsu_exu_ldxa_data_g,
div_byp_muldivout_g, ecc_byp_ecc_result_m, ecl_byp_ecc_mask_m_l,
ifu_exu_pc_d, ecl_byp_3lsb_m, ecl_byp_restore_m,
ecl_byp_sel_restore_m, ecl_byp_eclpr_e, div_byp_yreg_e,
ifu_exu_pcver_e, tlu_exu_rsr_data_m, ffu_exu_rsr_data_m,
ecl_byp_sel_yreg_e, ecl_byp_sel_eclpr_e, ecl_byp_sel_ifusr_e,
ecl_byp_sel_alu_e, ecl_byp_sel_ifex_m, ecl_byp_sel_ffusr_m,
ecl_byp_sel_tlusr_m
);
input rclk;
input se; // scan enable
input si;
input sehold;
input ecl_byp_rs1_mux2_sel_e;// select lines for bypass muxes for rs1
input ecl_byp_rs1_mux2_sel_rf;
input ecl_byp_rs1_mux2_sel_ld;
input ecl_byp_rs1_mux2_sel_usemux1;
input ecl_byp_rs1_mux1_sel_m;
input ecl_byp_rs1_mux1_sel_w;
input ecl_byp_rs1_mux1_sel_w2;
input ecl_byp_rs1_mux1_sel_other;
input ecl_byp_rcc_mux2_sel_e;// select lines for bypass muxes for reg condition code
input ecl_byp_rcc_mux2_sel_rf;
input ecl_byp_rcc_mux2_sel_ld;
input ecl_byp_rcc_mux2_sel_usemux1;
input ecl_byp_rcc_mux1_sel_m;
input ecl_byp_rcc_mux1_sel_w;
input ecl_byp_rcc_mux1_sel_w2;
input ecl_byp_rcc_mux1_sel_other;
input ecl_byp_rs2_mux2_sel_e;// select lines for bypass muxes for rs2
input ecl_byp_rs2_mux2_sel_rf;
input ecl_byp_rs2_mux2_sel_ld;
input ecl_byp_rs2_mux2_sel_usemux1;
input ecl_byp_rs2_mux1_sel_m;
input ecl_byp_rs2_mux1_sel_w;
input ecl_byp_rs2_mux1_sel_w2;
input ecl_byp_rs2_mux1_sel_other;
input ecl_byp_rs3_mux2_sel_e;// select lines for bypass muxes for rs3
input ecl_byp_rs3_mux2_sel_rf;
input ecl_byp_rs3_mux2_sel_ld;
input ecl_byp_rs3_mux2_sel_usemux1;
input ecl_byp_rs3_mux1_sel_m;
input ecl_byp_rs3_mux1_sel_w;
input ecl_byp_rs3_mux1_sel_w2;
input ecl_byp_rs3_mux1_sel_other;
input ecl_byp_rs3h_mux2_sel_e;// select lines for bypass muxes for rs3 double
input ecl_byp_rs3h_mux2_sel_rf;
input ecl_byp_rs3h_mux2_sel_ld;
input ecl_byp_rs3h_mux2_sel_usemux1;
input ecl_byp_rs3h_mux1_sel_m;
input ecl_byp_rs3h_mux1_sel_w;
input ecl_byp_rs3h_mux1_sel_w2;
input ecl_byp_rs3h_mux1_sel_other;
input ecl_byp_rs1_longmux_sel_g2;
input ecl_byp_rs1_longmux_sel_w2;
input ecl_byp_rs1_longmux_sel_ldxa;
input ecl_byp_rs2_longmux_sel_g2;
input ecl_byp_rs2_longmux_sel_w2;
input ecl_byp_rs2_longmux_sel_ldxa;
input ecl_byp_rs3_longmux_sel_g2;
input ecl_byp_rs3_longmux_sel_w2;
input ecl_byp_rs3_longmux_sel_ldxa;
input ecl_byp_rs3h_longmux_sel_g2;
input ecl_byp_rs3h_longmux_sel_w2;
input ecl_byp_rs3h_longmux_sel_ldxa;
input ecl_byp_sel_load_m; // m instruction uses load in w1 port
input ecl_byp_sel_pipe_m;
input ecl_byp_sel_ecc_m;
input ecl_byp_sel_muldiv_g;
input ecl_byp_sel_load_g;
input ecl_byp_sel_restore_g;
input ecl_byp_std_e_l;
input ecl_byp_ldxa_g;
input [63:0] alu_byp_rd_data_e; // data from alu for bypass
input [31:0] ifu_exu_imm_data_d; // immediate
input [71:0] irf_byp_rs1_data_d_l; // RF rs1_data
input [71:0] irf_byp_rs2_data_d_l; // RF rs2_data
input [71:0] irf_byp_rs3_data_d_l; // RF rs3_data
input [31:0] irf_byp_rs3h_data_d_l;// RF rs3 double data
input [63:0] lsu_exu_dfill_data_g; // load data
input [63:0] lsu_exu_ldxa_data_g;
input [63:0] div_byp_muldivout_g;
input [63:0] ecc_byp_ecc_result_m;// result from ecc
input [7:0] ecl_byp_ecc_mask_m_l;
input [47:0] ifu_exu_pc_d;
input [2:0] ecl_byp_3lsb_m;
input ecl_byp_restore_m;
input ecl_byp_sel_restore_m;
input [7:0] ecl_byp_eclpr_e;
input [31:0] div_byp_yreg_e;
input [63:0] ifu_exu_pcver_e;
input [63:0] tlu_exu_rsr_data_m;
input [63:0] ffu_exu_rsr_data_m;
input ecl_byp_sel_yreg_e;
input ecl_byp_sel_eclpr_e;
input ecl_byp_sel_ifusr_e;
input ecl_byp_sel_alu_e;
input ecl_byp_sel_ifex_m;
input ecl_byp_sel_ffusr_m;
input ecl_byp_sel_tlusr_m;
output so;
output [63:0] byp_alu_rs1_data_e; // rs1_data operand for alu
output [63:0] byp_alu_rs2_data_e_l; // rs2_data operand for alu
output [63:0] byp_alu_rs2_data_e;
output [63:0] exu_lsu_rs3_data_e; // rs3_data operand for lsu
output [63:0] exu_spu_rs3_data_e;// rs3 data for spu
output [63:0] exu_lsu_rs2_data_e;
output [63:0] byp_alu_rcc_data_e;// data for reg condition codes
output [71:0] byp_irf_rd_data_w;
output [63:0] exu_tlu_wsr_data_m; // data for writeback
output [71:0] byp_irf_rd_data_w2;
output [63:0] byp_ecc_rs3_data_e;
output [63:0] byp_ecc_rcc_data_e;
output byp_ecl_rs2_31_e;
output byp_ecl_rs1_31_e;
output byp_ecl_rs1_63_e;
output [2:0] byp_ecl_rs1_2_0_e;
output [3:0] byp_ecl_rs2_3_0_e;
output [7:0] byp_ecc_rs1_synd_d;
output [7:0] byp_ecc_rs2_synd_d;
output [7:0] byp_ecc_rs3_synd_d;
wire clk;
wire sehold_clk;
wire [63:0] irf_byp_rs1_data_d; // RF rs1_data
wire [63:0] irf_byp_rs2_data_d; // RF rs2_data
wire [63:0] irf_byp_rs3_data_d; // RF rs3_data
wire [31:0] irf_byp_rs3h_data_d; // RF rs3_data double
wire [63:0] byp_alu_rs1_data_d; // rs1 operand for alu
wire [63:0] byp_alu_rcc_data_d; // rcc operand for alu
wire [63:0] byp_alu_rs2_data_d; // rs2_data operand for alu
wire [63:0] rd_data_e; // e stage rd_data
wire [63:0] rd_data_m; // m stage non-load rd_data
wire [63:0] full_rd_data_m; // m stage non-load rd_data including rdsr
wire [63:0] rd_data_g;
wire [63:0] byp_irf_rd_data_m;// m stage rd_data
wire [63:0] rs1_data_btwn_mux; // intermediate net for rs1_data muxes
wire [63:0] rcc_data_btwn_mux; // intermediate net for rs1_data muxes
wire [63:0] rs2_data_btwn_mux; // intermediate net for rs2_data muxes
wire [63:0] rs3_data_btwn_mux; // intermediate net for rs3_data muxes
wire [31:0] rs3h_data_btwn_mux; // intermediate net for rs3h_data muxes
wire [63:0] rs3_data_d;
wire [63:0] rs3_data_e;
wire [31:0] rs3h_data_d;
wire [31:0] rs3h_data_e;
wire [63:0] restore_rd_data;
wire [63:0] restore_rd_data_next;
wire [63:0] dfill_data_g;
wire [63:0] dfill_data_g2;
wire ecl_byp_std_e;
wire [7:0] rd_synd_w_l;
wire [7:0] rd_synd_w2_l;
assign clk = rclk;
`ifdef FPGA_SYN_CLK_EN
`else
clken_buf irf_write_clkbuf (
.rclk (clk),
.enb_l (sehold),
.tmb_l (~se),
.clk (sehold_clk)
) ;
`endif
assign byp_ecc_rs1_synd_d[7:0] = ~irf_byp_rs1_data_d_l[71:64];
assign byp_ecc_rs2_synd_d[7:0] = ~irf_byp_rs2_data_d_l[71:64];
assign byp_ecc_rs3_synd_d[7:0] = ~irf_byp_rs3_data_d_l[71:64];
/////////////////////////////////////////
// Load returns go straight into a flop after mux with ldxa_data
/////////////////////////////////////////
dp_mux2es #(64) dfill_data_mux (.dout(dfill_data_g[63:0]),
.in0(lsu_exu_dfill_data_g[63:0]),
.in1(lsu_exu_ldxa_data_g[63:0]),
.sel(ecl_byp_ldxa_g));
dff_s #(64) dfill_data_dff (.din(dfill_data_g[63:0]), .clk(clk),
.q(dfill_data_g2[63:0]), .se(se), .si(), .so());
//////////////////////////////////////////////////
// RD of PR or SR
//////////////////////////////////////////////////
// Mux outputs for rdpr/rdsr
mux4ds #(64) ifu_exu_sr_mux(.dout(rd_data_e[63:0]),
.in0({32'b0, div_byp_yreg_e[31:0]}),
.in1({56'b0, ecl_byp_eclpr_e[7:0]}),
.in2(ifu_exu_pcver_e[63:0]),
.in3(alu_byp_rd_data_e[63:0]),
.sel0(ecl_byp_sel_yreg_e),
.sel1(ecl_byp_sel_eclpr_e),
.sel2(ecl_byp_sel_ifusr_e),
.sel3(ecl_byp_sel_alu_e));
// mux in the rdsr data from ffu and tlu
mux3ds #(64) sr_out_mux(.dout(full_rd_data_m[63:0]),
.in0({rd_data_m[63:3], ecl_byp_3lsb_m[2:0]}),
.in1(ffu_exu_rsr_data_m[63:0]),
.in2(tlu_exu_rsr_data_m[63:0]),
.sel0(ecl_byp_sel_ifex_m),
.sel1(ecl_byp_sel_ffusr_m),
.sel2(ecl_byp_sel_tlusr_m));
// Pipeline registers for rd_data
dff_s #(64) dff_rd_data_e2m(.din(rd_data_e[63:0]), .clk(clk), .q(rd_data_m[63:0]),
.se(se), .si(), .so());
dp_buffer #(64) wsr_data_buf(.dout(exu_tlu_wsr_data_m[63:0]), .in(rd_data_m[63:0]));
// Flop for storing result from restore
dp_mux2es #(64) restore_buf_mux(.dout(restore_rd_data_next[63:0]),
.in0(restore_rd_data[63:0]),
.in1(rd_data_m[63:0]),
.sel(ecl_byp_restore_m));
dff_s #(64) dff_restore_buf(.din(restore_rd_data_next[63:0]),
.q(restore_rd_data[63:0]), .clk(clk),
.se(se), .si(), .so());
// Mux for rd_data_m between ALU and load data and ECC result and restore result
mux4ds #(64) rd_data_m_mux(.dout(byp_irf_rd_data_m[63:0]),
.in0(full_rd_data_m[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(ecc_byp_ecc_result_m[63:0]),
.in3(restore_rd_data[63:0]),
.sel0(ecl_byp_sel_pipe_m),
.sel1(ecl_byp_sel_load_m),
.sel2(ecl_byp_sel_ecc_m),
.sel3(ecl_byp_sel_restore_m));
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(64) dff_rd_data_m2w(.din(byp_irf_rd_data_m[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w[63:0]),
.se(se), .si(), .so());
`else
dff_s #(64) dff_rd_data_m2w(.din(byp_irf_rd_data_m[63:0]), .clk(sehold_clk), .q(byp_irf_rd_data_w[63:0]),
.se(se), .si(), .so());
`endif
// W2 flop
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(64) dff_rd_data_g2w(.din(rd_data_g[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w2[63:0]),
.se(se), .si(), .so());
`else
dff_s #(64) dff_rd_data_g2w(.din(rd_data_g[63:0]), .clk(sehold_clk), .q(byp_irf_rd_data_w2[63:0]),
.se(se), .si(), .so());
`endif
// D-E pipeline registers for rs_data
dff_s #(64) rs1_data_dff(.din(byp_alu_rs1_data_d[63:0]), .clk(clk),
.q(byp_alu_rs1_data_e[63:0]), .se(se),
.si(), .so());
dff_s #(64) rs2_data_dff(.din(byp_alu_rs2_data_d[63:0]), .clk(clk),
.q(byp_alu_rs2_data_e[63:0]), .se(se),
.si(), .so());
assign byp_alu_rs2_data_e_l[63:0] = ~byp_alu_rs2_data_e[63:0];
assign byp_ecl_rs2_31_e = byp_alu_rs2_data_e[31];
assign byp_ecl_rs1_63_e = byp_alu_rs1_data_e[63];
assign byp_ecl_rs1_31_e = byp_alu_rs1_data_e[31];
assign byp_ecl_rs1_2_0_e[2:0] = byp_alu_rs1_data_e[2:0];
assign byp_ecl_rs2_3_0_e[3:0] = byp_alu_rs2_data_e[3:0];
dff_s #(64) rs3_data_dff(.din(rs3_data_d[63:0]), .clk(clk),
.q(rs3_data_e[63:0]), .se(se),
.si(), .so());
dff_s #(32) rs3h_data_dff(.din(rs3h_data_d[31:0]), .clk(clk),
.q(rs3h_data_e[31:0]), .se(se),
.si(), .so());
dff_s #(64) rcc_data_dff(.din(byp_alu_rcc_data_d[63:0]), .clk(clk),
.q(byp_alu_rcc_data_e[63:0]), .se(se),
.si(), .so());
assign ecl_byp_std_e = ~ecl_byp_std_e_l;
dp_mux2es #(64) rs2_data_out_mux(.dout(exu_lsu_rs2_data_e[63:0]),
.in0(byp_alu_rs2_data_e[63:0]),
.in1(rs3_data_e[63:0]),
.sel(ecl_byp_std_e));
dp_mux2es #(64) rs3_data_out_mux(.dout(exu_lsu_rs3_data_e[63:0]),
.in0(rs3_data_e[63:0]),
.in1({32'b0,rs3h_data_e[31:0]}),
.sel(ecl_byp_std_e));
// part of rs3 goes to spu. Buffer off to help timing/loading
assign exu_spu_rs3_data_e[63:0] = rs3_data_e[63:0];
assign byp_ecc_rs3_data_e[63:0] = rs3_data_e[63:0];
assign byp_ecc_rcc_data_e[63:0] = byp_alu_rcc_data_e[63:0];
// Forwarding Muxes
// Select lines are as follows:
// mux1[M, W, W2, OTHER(optional)]
// mux2[mux1, RF, E, LD]
assign irf_byp_rs1_data_d[63:0] = ~irf_byp_rs1_data_d_l[63:0];
assign irf_byp_rs2_data_d[63:0] = ~irf_byp_rs2_data_d_l[63:0];
assign irf_byp_rs3_data_d[63:0] = ~irf_byp_rs3_data_d_l[63:0];
assign irf_byp_rs3h_data_d[31:0] = ~irf_byp_rs3h_data_d_l[31:0];
/* -----\/----- EXCLUDED -----\/-----
// the w2 bypass path is either what is being written that cycle
// or the load result that will be written next cycle.
-----/\----- EXCLUDED -----/\----- */
wire [63:0] rs1_data_w2;
wire [63:0] rs2_data_w2;
wire [63:0] rs3_data_w2;
wire [31:0] rs3h_data_w2;
mux3ds #(64) rs1_w2_mux(.dout(rs1_data_w2[63:0]),
.in0(byp_irf_rd_data_w2[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(lsu_exu_ldxa_data_g[63:0]),
.sel0(ecl_byp_rs1_longmux_sel_w2),
.sel1(ecl_byp_rs1_longmux_sel_g2),
.sel2(ecl_byp_rs1_longmux_sel_ldxa));
mux3ds #(64) rs2_w2_mux(.dout(rs2_data_w2[63:0]),
.in0(byp_irf_rd_data_w2[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(lsu_exu_ldxa_data_g[63:0]),
.sel0(ecl_byp_rs2_longmux_sel_w2),
.sel1(ecl_byp_rs2_longmux_sel_g2),
.sel2(ecl_byp_rs2_longmux_sel_ldxa));
mux3ds #(64) rs3_w2_mux(.dout(rs3_data_w2[63:0]),
.in0(byp_irf_rd_data_w2[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(lsu_exu_ldxa_data_g[63:0]),
.sel0(ecl_byp_rs3_longmux_sel_w2),
.sel1(ecl_byp_rs3_longmux_sel_g2),
.sel2(ecl_byp_rs3_longmux_sel_ldxa));
mux3ds #(32) rs3h_w2_mux(.dout(rs3h_data_w2[31:0]),
.in0(byp_irf_rd_data_w2[31:0]),
.in1(dfill_data_g2[31:0]),
.in2(lsu_exu_ldxa_data_g[31:0]),
.sel0(ecl_byp_rs3h_longmux_sel_w2),
.sel1(ecl_byp_rs3h_longmux_sel_g2),
.sel2(ecl_byp_rs3h_longmux_sel_ldxa));
// rs1_data muxes: RF and E are critical paths
mux4ds #(64) mux_rs1_data_1(.dout(rs1_data_btwn_mux[63:0]),
.in0(rd_data_m[63:0]),
.in1(byp_irf_rd_data_w[63:0]),
.in2(rs1_data_w2[63:0]),
.in3({{16{ifu_exu_pc_d[47]}}, ifu_exu_pc_d[47:0]}),
.sel0(ecl_byp_rs1_mux1_sel_m),
.sel1(ecl_byp_rs1_mux1_sel_w),
.sel2(ecl_byp_rs1_mux1_sel_w2),
.sel3(ecl_byp_rs1_mux1_sel_other));
mux4ds #(64) mux_rs1_data_2(.dout(byp_alu_rs1_data_d[63:0]),
.in0(rs1_data_btwn_mux[63:0]),
.in1(irf_byp_rs1_data_d[63:0]),
.in2(alu_byp_rd_data_e[63:0]),
.in3(lsu_exu_dfill_data_g[63:0]),
.sel0(ecl_byp_rs1_mux2_sel_usemux1),
.sel1(ecl_byp_rs1_mux2_sel_rf),
.sel2(ecl_byp_rs1_mux2_sel_e),
.sel3(ecl_byp_rs1_mux2_sel_ld));
// rcc_data muxes: RF and E are critical paths
mux4ds #(64) mux_rcc_data_1(.dout(rcc_data_btwn_mux[63:0]),
.in0(rd_data_m[63:0]),
.in1(byp_irf_rd_data_w[63:0]),
.in2(rs1_data_w2[63:0]),
.in3({64{1'b0}}),
.sel0(ecl_byp_rcc_mux1_sel_m),
.sel1(ecl_byp_rcc_mux1_sel_w),
.sel2(ecl_byp_rcc_mux1_sel_w2),
.sel3(ecl_byp_rcc_mux1_sel_other));
mux4ds #(64) mux_rcc_data_2(.dout(byp_alu_rcc_data_d[63:0]),
.in0(rcc_data_btwn_mux[63:0]),
.in1(irf_byp_rs1_data_d[63:0]),
.in2(alu_byp_rd_data_e[63:0]),
.in3(lsu_exu_dfill_data_g[63:0]),
.sel0(ecl_byp_rcc_mux2_sel_usemux1),
.sel1(ecl_byp_rcc_mux2_sel_rf),
.sel2(ecl_byp_rcc_mux2_sel_e),
.sel3(ecl_byp_rcc_mux2_sel_ld));
// rs2_data muxes: RF and E are critical paths, optional is imm
mux4ds #(64) mux_rs2_data_1(.dout(rs2_data_btwn_mux[63:0]),
.in0(rd_data_m[63:0]),
.in1(byp_irf_rd_data_w[63:0]),
.in2(rs2_data_w2[63:0]),
.in3({{32{ifu_exu_imm_data_d[31]}},
ifu_exu_imm_data_d[31:0]}),
.sel0(ecl_byp_rs2_mux1_sel_m),
.sel1(ecl_byp_rs2_mux1_sel_w),
.sel2(ecl_byp_rs2_mux1_sel_w2),
.sel3(ecl_byp_rs2_mux1_sel_other));
mux4ds #(64) mux_rs2_data_2(.dout(byp_alu_rs2_data_d[63:0]),
.in0(rs2_data_btwn_mux[63:0]),
.in1(irf_byp_rs2_data_d[63:0]),
.in2(alu_byp_rd_data_e[63:0]),
.in3(lsu_exu_dfill_data_g[63:0]),
.sel0(ecl_byp_rs2_mux2_sel_usemux1),
.sel1(ecl_byp_rs2_mux2_sel_rf),
.sel2(ecl_byp_rs2_mux2_sel_e),
.sel3(ecl_byp_rs2_mux2_sel_ld));
// rs3_data muxes: RF and E are critical paths, no optional
mux4ds #(64) mux_rs3_data_1(.dout(rs3_data_btwn_mux[63:0]),
.in0(rd_data_m[63:0]),
.in1(byp_irf_rd_data_w[63:0]),
.in2(rs3_data_w2[63:0]), .in3({64{1'b0}}),
.sel0(ecl_byp_rs3_mux1_sel_m),
.sel1(ecl_byp_rs3_mux1_sel_w),
.sel2(ecl_byp_rs3_mux1_sel_w2),
.sel3(ecl_byp_rs3_mux1_sel_other));
mux4ds #(64) mux_rs3_data_2(.dout(rs3_data_d[63:0]),
.in0(rs3_data_btwn_mux[63:0]),
.in1(irf_byp_rs3_data_d[63:0]),
.in2(alu_byp_rd_data_e[63:0]),
.in3(lsu_exu_dfill_data_g[63:0]),
.sel0(ecl_byp_rs3_mux2_sel_usemux1),
.sel1(ecl_byp_rs3_mux2_sel_rf),
.sel2(ecl_byp_rs3_mux2_sel_e),
.sel3(ecl_byp_rs3_mux2_sel_ld));
// rs3_data muxes: RF and E are critical paths, no optional
mux4ds #(32) mux_rs3h_data_1(.dout(rs3h_data_btwn_mux[31:0]),
.in0(rd_data_m[31:0]),
.in1(byp_irf_rd_data_w[31:0]),
.in2(rs3h_data_w2[31:0]), .in3({32{1'b0}}),
.sel0(ecl_byp_rs3h_mux1_sel_m),
.sel1(ecl_byp_rs3h_mux1_sel_w),
.sel2(ecl_byp_rs3h_mux1_sel_w2),
.sel3(ecl_byp_rs3h_mux1_sel_other));
mux4ds #(32) mux_rs3h_data_2(.dout(rs3h_data_d[31:0]),
.in0(rs3h_data_btwn_mux[31:0]),
.in1(irf_byp_rs3h_data_d[31:0]),
.in2(alu_byp_rd_data_e[31:0]),
.in3(lsu_exu_dfill_data_g[31:0]),
.sel0(ecl_byp_rs3h_mux2_sel_usemux1),
.sel1(ecl_byp_rs3h_mux2_sel_rf),
.sel2(ecl_byp_rs3h_mux2_sel_e),
.sel3(ecl_byp_rs3h_mux2_sel_ld));
// ECC for W1
`ifdef FPGA_SYN_CLK_DFF
sparc_exu_byp_eccgen w1_eccgen(.d(byp_irf_rd_data_m[63:0]),
.msk(ecl_byp_ecc_mask_m_l[7:0]),
.p(rd_synd_w_l[7:0]),
.clk(clk), .se(se));
`else
sparc_exu_byp_eccgen w1_eccgen(.d(byp_irf_rd_data_m[63:0]),
.msk(ecl_byp_ecc_mask_m_l[7:0]),
.p(rd_synd_w_l[7:0]),
.clk(sehold_clk), .se(se));
`endif
assign byp_irf_rd_data_w[71:64] = ~rd_synd_w_l[7:0];
////////////////////////
// G arbitration muxes and W2 ECC
////////////////////////
mux3ds #(64) mux_w2_data(.dout(rd_data_g[63:0]),
.in0(div_byp_muldivout_g[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(restore_rd_data[63:0]),
.sel0(ecl_byp_sel_muldiv_g),
.sel1(ecl_byp_sel_load_g),
.sel2(ecl_byp_sel_restore_g));
`ifdef FPGA_SYN_CLK_DFF
sparc_exu_byp_eccgen w2_eccgen(.d(rd_data_g[63:0]),
.msk(ecl_byp_ecc_mask_m_l[7:0]),
.p(rd_synd_w2_l[7:0]),
.clk(clk), .se(se));
`else
sparc_exu_byp_eccgen w2_eccgen(.d(rd_data_g[63:0]),
.msk(ecl_byp_ecc_mask_m_l[7:0]),
.p(rd_synd_w2_l[7:0]),
.clk(sehold_clk), .se(se));
`endif
assign byp_irf_rd_data_w2[71:64] = ~rd_synd_w2_l[7:0];
endmodule |
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [17:0] sw,
output wire [8:0] ledg,
output wire [17:0] ledr,
output wire [6:0] hex0,
output wire [6:0] hex1,
output wire [6:0] hex2,
output wire [6:0] hex3,
output wire [6:0] hex4,
output wire [6:0] hex5,
output wire [6:0] hex6,
output wire [6:0] hex7,
output wire [35:0] gpio,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy0_rx_clk,
input wire [3:0] phy0_rxd,
input wire phy0_rx_ctl,
output wire phy0_tx_clk,
output wire [3:0] phy0_txd,
output wire phy0_tx_ctl,
output wire phy0_reset_n,
input wire phy0_int_n,
input wire phy1_rx_clk,
input wire [3:0] phy1_rxd,
input wire phy1_rx_ctl,
output wire phy1_tx_clk,
output wire [3:0] phy1_txd,
output wire phy1_tx_ctl,
output wire phy1_reset_n,
input wire phy1_int_n
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
if (rst) begin
led_reg <= 0;
end
end
// place dest IP onto 7 segment displays
reg [31:0] dest_ip_reg = 0;
always @(posedge clk) begin
if (tx_udp_hdr_valid) begin
dest_ip_reg <= tx_udp_ip_dest_ip;
end
if (rst) begin
dest_ip_reg <= 0;
end
end
hex_display #(
.INVERT(1)
)
hex_display_0 (
.in(dest_ip_reg[3:0]),
.enable(1),
.out(hex0)
);
hex_display #(
.INVERT(1)
)
hex_display_1 (
.in(dest_ip_reg[7:4]),
.enable(1),
.out(hex1)
);
hex_display #(
.INVERT(1)
)
hex_display_2 (
.in(dest_ip_reg[11:8]),
.enable(1),
.out(hex2)
);
hex_display #(
.INVERT(1)
)
hex_display_3 (
.in(dest_ip_reg[15:12]),
.enable(1),
.out(hex3)
);
hex_display #(
.INVERT(1)
)
hex_display_4 (
.in(dest_ip_reg[19:16]),
.enable(1),
.out(hex4)
);
hex_display #(
.INVERT(1)
)
hex_display_5 (
.in(dest_ip_reg[23:20]),
.enable(1),
.out(hex5)
);
hex_display #(
.INVERT(1)
)
hex_display_6 (
.in(dest_ip_reg[27:24]),
.enable(1),
.out(hex6)
);
hex_display #(
.INVERT(1)
)
hex_display_7 (
.in(dest_ip_reg[31:28]),
.enable(1),
.out(hex7)
);
//assign led = sw;
assign ledg = led_reg;
assign ledr = sw;
assign phy0_reset_n = ~rst;
assign phy1_reset_n = ~rst;
assign gpio = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy0_rx_clk),
.rgmii_rxd(phy0_rxd),
.rgmii_rx_ctl(phy0_rx_ctl),
.rgmii_tx_clk(phy0_tx_clk),
.rgmii_txd(phy0_txd),
.rgmii_tx_ctl(phy0_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule |
module axi_ad9144_if (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
dac_data_2_0,
dac_data_2_1,
dac_data_2_2,
dac_data_2_3,
dac_data_3_0,
dac_data_3_1,
dac_data_3_2,
dac_data_3_3);
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [255:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [15:0] dac_data_0_0;
input [15:0] dac_data_0_1;
input [15:0] dac_data_0_2;
input [15:0] dac_data_0_3;
input [15:0] dac_data_1_0;
input [15:0] dac_data_1_1;
input [15:0] dac_data_1_2;
input [15:0] dac_data_1_3;
input [15:0] dac_data_2_0;
input [15:0] dac_data_2_1;
input [15:0] dac_data_2_2;
input [15:0] dac_data_2_3;
input [15:0] dac_data_3_0;
input [15:0] dac_data_3_1;
input [15:0] dac_data_3_2;
input [15:0] dac_data_3_3;
// internal registers
reg [255:0] tx_data = 'd0;
// reorder data for the jesd links
assign dac_clk = tx_clk;
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
tx_data <= 256'd0;
end else begin
tx_data[255:248] <= dac_data_3_3[ 7: 0];
tx_data[247:240] <= dac_data_3_2[ 7: 0];
tx_data[239:232] <= dac_data_3_1[ 7: 0];
tx_data[231:224] <= dac_data_3_0[ 7: 0];
tx_data[223:216] <= dac_data_3_3[15: 8];
tx_data[215:208] <= dac_data_3_2[15: 8];
tx_data[207:200] <= dac_data_3_1[15: 8];
tx_data[199:192] <= dac_data_3_0[15: 8];
tx_data[191:184] <= dac_data_2_3[ 7: 0];
tx_data[183:176] <= dac_data_2_2[ 7: 0];
tx_data[175:168] <= dac_data_2_1[ 7: 0];
tx_data[167:160] <= dac_data_2_0[ 7: 0];
tx_data[159:152] <= dac_data_2_3[15: 8];
tx_data[151:144] <= dac_data_2_2[15: 8];
tx_data[143:136] <= dac_data_2_1[15: 8];
tx_data[135:128] <= dac_data_2_0[15: 8];
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];
tx_data[103: 96] <= dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= dac_data_1_3[15: 8];
tx_data[ 87: 80] <= dac_data_1_2[15: 8];
tx_data[ 79: 72] <= dac_data_1_1[15: 8];
tx_data[ 71: 64] <= dac_data_1_0[15: 8];
tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= dac_data_0_3[15: 8];
tx_data[ 23: 16] <= dac_data_0_2[15: 8];
tx_data[ 15: 8] <= dac_data_0_1[15: 8];
tx_data[ 7: 0] <= dac_data_0_0[15: 8];
end
end
endmodule |
module sky130_fd_sc_lp__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module Lab2Part1Fall2015AJM(Rows, ClockIn, Load, Reset, RotateOnce, Columns, KeyNumberLEDs, ClockLocked);
parameter LENGTH = 4;
input [LENGTH-1:0] Rows;
input ClockIn, Load, Reset, RotateOnce;
output [LENGTH-1:0] Columns;
output [LENGTH:0] KeyNumberLEDs;
output ClockLocked;
wire DebouncedShift, Rotate;
Clock50MHz KeypadScanClock(ClockIn, Clock, ClockLocked);
DebouncerWithoutLatch RotateOnceSwitch(RotateOnce, DebouncedRotate, Reset, Clock);
ClockedOneShot RotateOnceUnit(DebouncedRotate, Rotate, Reset, Clock);
ShiftReg4bits ColumnPattern(4'b1110, Clock, Load, Reset, Rotate, Columns);
KeyEncoderAJM KeyMapUnit(Columns, Rows, KeyNumberLEDs);
endmodule |
module outputs
wire [63 : 0] cpu_dmem_master_araddr,
cpu_dmem_master_awaddr,
cpu_dmem_master_wdata,
cpu_imem_master_araddr,
cpu_imem_master_awaddr,
cpu_imem_master_wdata;
wire [7 : 0] cpu_dmem_master_arlen,
cpu_dmem_master_awlen,
cpu_dmem_master_wstrb,
cpu_imem_master_arlen,
cpu_imem_master_awlen,
cpu_imem_master_wstrb;
wire [3 : 0] cpu_dmem_master_arcache,
cpu_dmem_master_arid,
cpu_dmem_master_arqos,
cpu_dmem_master_arregion,
cpu_dmem_master_awcache,
cpu_dmem_master_awid,
cpu_dmem_master_awqos,
cpu_dmem_master_awregion,
cpu_imem_master_arcache,
cpu_imem_master_arid,
cpu_imem_master_arqos,
cpu_imem_master_arregion,
cpu_imem_master_awcache,
cpu_imem_master_awid,
cpu_imem_master_awqos,
cpu_imem_master_awregion;
wire [2 : 0] cpu_dmem_master_arprot,
cpu_dmem_master_arsize,
cpu_dmem_master_awprot,
cpu_dmem_master_awsize,
cpu_imem_master_arprot,
cpu_imem_master_arsize,
cpu_imem_master_awprot,
cpu_imem_master_awsize;
wire [1 : 0] cpu_dmem_master_arburst,
cpu_dmem_master_awburst,
cpu_imem_master_arburst,
cpu_imem_master_awburst;
wire RDY_cpu_reset_server_request_put,
RDY_cpu_reset_server_response_get,
RDY_set_verbosity,
RDY_set_watch_tohost,
cpu_dmem_master_arlock,
cpu_dmem_master_arvalid,
cpu_dmem_master_awlock,
cpu_dmem_master_awvalid,
cpu_dmem_master_bready,
cpu_dmem_master_rready,
cpu_dmem_master_wlast,
cpu_dmem_master_wvalid,
cpu_imem_master_arlock,
cpu_imem_master_arvalid,
cpu_imem_master_awlock,
cpu_imem_master_awvalid,
cpu_imem_master_bready,
cpu_imem_master_rready,
cpu_imem_master_wlast,
cpu_imem_master_wvalid,
cpu_reset_server_response_get;
// ports of submodule cpu
wire [63 : 0] cpu$dmem_master_araddr,
cpu$dmem_master_awaddr,
cpu$dmem_master_rdata,
cpu$dmem_master_wdata,
cpu$imem_master_araddr,
cpu$imem_master_awaddr,
cpu$imem_master_rdata,
cpu$imem_master_wdata,
cpu$set_verbosity_logdelay,
cpu$set_watch_tohost_tohost_addr;
wire [7 : 0] cpu$dmem_master_arlen,
cpu$dmem_master_awlen,
cpu$dmem_master_wstrb,
cpu$imem_master_arlen,
cpu$imem_master_awlen,
cpu$imem_master_wstrb;
wire [3 : 0] cpu$dmem_master_arcache,
cpu$dmem_master_arid,
cpu$dmem_master_arqos,
cpu$dmem_master_arregion,
cpu$dmem_master_awcache,
cpu$dmem_master_awid,
cpu$dmem_master_awqos,
cpu$dmem_master_awregion,
cpu$dmem_master_bid,
cpu$dmem_master_rid,
cpu$imem_master_arcache,
cpu$imem_master_arid,
cpu$imem_master_arqos,
cpu$imem_master_arregion,
cpu$imem_master_awcache,
cpu$imem_master_awid,
cpu$imem_master_awqos,
cpu$imem_master_awregion,
cpu$imem_master_bid,
cpu$imem_master_rid,
cpu$set_verbosity_verbosity;
wire [2 : 0] cpu$dmem_master_arprot,
cpu$dmem_master_arsize,
cpu$dmem_master_awprot,
cpu$dmem_master_awsize,
cpu$imem_master_arprot,
cpu$imem_master_arsize,
cpu$imem_master_awprot,
cpu$imem_master_awsize;
wire [1 : 0] cpu$dmem_master_arburst,
cpu$dmem_master_awburst,
cpu$dmem_master_bresp,
cpu$dmem_master_rresp,
cpu$imem_master_arburst,
cpu$imem_master_awburst,
cpu$imem_master_bresp,
cpu$imem_master_rresp;
wire cpu$EN_hart0_server_reset_request_put,
cpu$EN_hart0_server_reset_response_get,
cpu$EN_set_verbosity,
cpu$EN_set_watch_tohost,
cpu$RDY_hart0_server_reset_request_put,
cpu$RDY_hart0_server_reset_response_get,
cpu$dmem_master_arlock,
cpu$dmem_master_arready,
cpu$dmem_master_arvalid,
cpu$dmem_master_awlock,
cpu$dmem_master_awready,
cpu$dmem_master_awvalid,
cpu$dmem_master_bready,
cpu$dmem_master_bvalid,
cpu$dmem_master_rlast,
cpu$dmem_master_rready,
cpu$dmem_master_rvalid,
cpu$dmem_master_wlast,
cpu$dmem_master_wready,
cpu$dmem_master_wvalid,
cpu$hart0_server_reset_request_put,
cpu$hart0_server_reset_response_get,
cpu$imem_master_arlock,
cpu$imem_master_arready,
cpu$imem_master_arvalid,
cpu$imem_master_awlock,
cpu$imem_master_awready,
cpu$imem_master_awvalid,
cpu$imem_master_bready,
cpu$imem_master_bvalid,
cpu$imem_master_rlast,
cpu$imem_master_rready,
cpu$imem_master_rvalid,
cpu$imem_master_wlast,
cpu$imem_master_wready,
cpu$imem_master_wvalid,
cpu$m_external_interrupt_req_set_not_clear,
cpu$nmi_req_set_not_clear,
cpu$s_external_interrupt_req_set_not_clear,
cpu$set_watch_tohost_watch_tohost,
cpu$software_interrupt_req_set_not_clear,
cpu$timer_interrupt_req_set_not_clear;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule fabric_2x3
wire [63 : 0] fabric_2x3$v_from_masters_0_araddr,
fabric_2x3$v_from_masters_0_awaddr,
fabric_2x3$v_from_masters_0_rdata,
fabric_2x3$v_from_masters_0_wdata,
fabric_2x3$v_from_masters_1_araddr,
fabric_2x3$v_from_masters_1_awaddr,
fabric_2x3$v_from_masters_1_wdata,
fabric_2x3$v_to_slaves_0_araddr,
fabric_2x3$v_to_slaves_0_awaddr,
fabric_2x3$v_to_slaves_0_rdata,
fabric_2x3$v_to_slaves_0_wdata,
fabric_2x3$v_to_slaves_1_araddr,
fabric_2x3$v_to_slaves_1_awaddr,
fabric_2x3$v_to_slaves_1_rdata,
fabric_2x3$v_to_slaves_1_wdata,
fabric_2x3$v_to_slaves_2_araddr,
fabric_2x3$v_to_slaves_2_awaddr,
fabric_2x3$v_to_slaves_2_rdata,
fabric_2x3$v_to_slaves_2_wdata;
wire [7 : 0] fabric_2x3$v_from_masters_0_arlen,
fabric_2x3$v_from_masters_0_awlen,
fabric_2x3$v_from_masters_0_wstrb,
fabric_2x3$v_from_masters_1_arlen,
fabric_2x3$v_from_masters_1_awlen,
fabric_2x3$v_from_masters_1_wstrb,
fabric_2x3$v_to_slaves_0_arlen,
fabric_2x3$v_to_slaves_0_awlen,
fabric_2x3$v_to_slaves_0_wstrb,
fabric_2x3$v_to_slaves_1_arlen,
fabric_2x3$v_to_slaves_1_awlen,
fabric_2x3$v_to_slaves_1_wstrb,
fabric_2x3$v_to_slaves_2_arlen,
fabric_2x3$v_to_slaves_2_awlen,
fabric_2x3$v_to_slaves_2_wstrb;
wire [3 : 0] fabric_2x3$set_verbosity_verbosity,
fabric_2x3$v_from_masters_0_arcache,
fabric_2x3$v_from_masters_0_arid,
fabric_2x3$v_from_masters_0_arqos,
fabric_2x3$v_from_masters_0_arregion,
fabric_2x3$v_from_masters_0_awcache,
fabric_2x3$v_from_masters_0_awid,
fabric_2x3$v_from_masters_0_awqos,
fabric_2x3$v_from_masters_0_awregion,
fabric_2x3$v_from_masters_0_bid,
fabric_2x3$v_from_masters_0_rid,
fabric_2x3$v_from_masters_1_arcache,
fabric_2x3$v_from_masters_1_arid,
fabric_2x3$v_from_masters_1_arqos,
fabric_2x3$v_from_masters_1_arregion,
fabric_2x3$v_from_masters_1_awcache,
fabric_2x3$v_from_masters_1_awid,
fabric_2x3$v_from_masters_1_awqos,
fabric_2x3$v_from_masters_1_awregion,
fabric_2x3$v_to_slaves_0_arcache,
fabric_2x3$v_to_slaves_0_arid,
fabric_2x3$v_to_slaves_0_arqos,
fabric_2x3$v_to_slaves_0_arregion,
fabric_2x3$v_to_slaves_0_awcache,
fabric_2x3$v_to_slaves_0_awid,
fabric_2x3$v_to_slaves_0_awqos,
fabric_2x3$v_to_slaves_0_awregion,
fabric_2x3$v_to_slaves_0_bid,
fabric_2x3$v_to_slaves_0_rid,
fabric_2x3$v_to_slaves_1_arcache,
fabric_2x3$v_to_slaves_1_arid,
fabric_2x3$v_to_slaves_1_arqos,
fabric_2x3$v_to_slaves_1_arregion,
fabric_2x3$v_to_slaves_1_awcache,
fabric_2x3$v_to_slaves_1_awid,
fabric_2x3$v_to_slaves_1_awqos,
fabric_2x3$v_to_slaves_1_awregion,
fabric_2x3$v_to_slaves_1_bid,
fabric_2x3$v_to_slaves_1_rid,
fabric_2x3$v_to_slaves_2_arcache,
fabric_2x3$v_to_slaves_2_arid,
fabric_2x3$v_to_slaves_2_arqos,
fabric_2x3$v_to_slaves_2_arregion,
fabric_2x3$v_to_slaves_2_awcache,
fabric_2x3$v_to_slaves_2_awid,
fabric_2x3$v_to_slaves_2_awqos,
fabric_2x3$v_to_slaves_2_awregion,
fabric_2x3$v_to_slaves_2_bid,
fabric_2x3$v_to_slaves_2_rid;
wire [2 : 0] fabric_2x3$v_from_masters_0_arprot,
fabric_2x3$v_from_masters_0_arsize,
fabric_2x3$v_from_masters_0_awprot,
fabric_2x3$v_from_masters_0_awsize,
fabric_2x3$v_from_masters_1_arprot,
fabric_2x3$v_from_masters_1_arsize,
fabric_2x3$v_from_masters_1_awprot,
fabric_2x3$v_from_masters_1_awsize,
fabric_2x3$v_to_slaves_0_arprot,
fabric_2x3$v_to_slaves_0_arsize,
fabric_2x3$v_to_slaves_0_awprot,
fabric_2x3$v_to_slaves_0_awsize,
fabric_2x3$v_to_slaves_1_arprot,
fabric_2x3$v_to_slaves_1_arsize,
fabric_2x3$v_to_slaves_1_awprot,
fabric_2x3$v_to_slaves_1_awsize,
fabric_2x3$v_to_slaves_2_arprot,
fabric_2x3$v_to_slaves_2_arsize,
fabric_2x3$v_to_slaves_2_awprot,
fabric_2x3$v_to_slaves_2_awsize;
wire [1 : 0] fabric_2x3$v_from_masters_0_arburst,
fabric_2x3$v_from_masters_0_awburst,
fabric_2x3$v_from_masters_0_bresp,
fabric_2x3$v_from_masters_0_rresp,
fabric_2x3$v_from_masters_1_arburst,
fabric_2x3$v_from_masters_1_awburst,
fabric_2x3$v_to_slaves_0_arburst,
fabric_2x3$v_to_slaves_0_awburst,
fabric_2x3$v_to_slaves_0_bresp,
fabric_2x3$v_to_slaves_0_rresp,
fabric_2x3$v_to_slaves_1_arburst,
fabric_2x3$v_to_slaves_1_awburst,
fabric_2x3$v_to_slaves_1_bresp,
fabric_2x3$v_to_slaves_1_rresp,
fabric_2x3$v_to_slaves_2_arburst,
fabric_2x3$v_to_slaves_2_awburst,
fabric_2x3$v_to_slaves_2_bresp,
fabric_2x3$v_to_slaves_2_rresp;
wire fabric_2x3$EN_reset,
fabric_2x3$EN_set_verbosity,
fabric_2x3$RDY_reset,
fabric_2x3$v_from_masters_0_arlock,
fabric_2x3$v_from_masters_0_arready,
fabric_2x3$v_from_masters_0_arvalid,
fabric_2x3$v_from_masters_0_awlock,
fabric_2x3$v_from_masters_0_awready,
fabric_2x3$v_from_masters_0_awvalid,
fabric_2x3$v_from_masters_0_bready,
fabric_2x3$v_from_masters_0_bvalid,
fabric_2x3$v_from_masters_0_rlast,
fabric_2x3$v_from_masters_0_rready,
fabric_2x3$v_from_masters_0_rvalid,
fabric_2x3$v_from_masters_0_wlast,
fabric_2x3$v_from_masters_0_wready,
fabric_2x3$v_from_masters_0_wvalid,
fabric_2x3$v_from_masters_1_arlock,
fabric_2x3$v_from_masters_1_arvalid,
fabric_2x3$v_from_masters_1_awlock,
fabric_2x3$v_from_masters_1_awvalid,
fabric_2x3$v_from_masters_1_bready,
fabric_2x3$v_from_masters_1_rready,
fabric_2x3$v_from_masters_1_wlast,
fabric_2x3$v_from_masters_1_wvalid,
fabric_2x3$v_to_slaves_0_arlock,
fabric_2x3$v_to_slaves_0_arready,
fabric_2x3$v_to_slaves_0_arvalid,
fabric_2x3$v_to_slaves_0_awlock,
fabric_2x3$v_to_slaves_0_awready,
fabric_2x3$v_to_slaves_0_awvalid,
fabric_2x3$v_to_slaves_0_bready,
fabric_2x3$v_to_slaves_0_bvalid,
fabric_2x3$v_to_slaves_0_rlast,
fabric_2x3$v_to_slaves_0_rready,
fabric_2x3$v_to_slaves_0_rvalid,
fabric_2x3$v_to_slaves_0_wlast,
fabric_2x3$v_to_slaves_0_wready,
fabric_2x3$v_to_slaves_0_wvalid,
fabric_2x3$v_to_slaves_1_arlock,
fabric_2x3$v_to_slaves_1_arready,
fabric_2x3$v_to_slaves_1_arvalid,
fabric_2x3$v_to_slaves_1_awlock,
fabric_2x3$v_to_slaves_1_awready,
fabric_2x3$v_to_slaves_1_awvalid,
fabric_2x3$v_to_slaves_1_bready,
fabric_2x3$v_to_slaves_1_bvalid,
fabric_2x3$v_to_slaves_1_rlast,
fabric_2x3$v_to_slaves_1_rready,
fabric_2x3$v_to_slaves_1_rvalid,
fabric_2x3$v_to_slaves_1_wlast,
fabric_2x3$v_to_slaves_1_wready,
fabric_2x3$v_to_slaves_1_wvalid,
fabric_2x3$v_to_slaves_2_arlock,
fabric_2x3$v_to_slaves_2_arready,
fabric_2x3$v_to_slaves_2_arvalid,
fabric_2x3$v_to_slaves_2_awlock,
fabric_2x3$v_to_slaves_2_awready,
fabric_2x3$v_to_slaves_2_awvalid,
fabric_2x3$v_to_slaves_2_bready,
fabric_2x3$v_to_slaves_2_bvalid,
fabric_2x3$v_to_slaves_2_rlast,
fabric_2x3$v_to_slaves_2_rready,
fabric_2x3$v_to_slaves_2_rvalid,
fabric_2x3$v_to_slaves_2_wlast,
fabric_2x3$v_to_slaves_2_wready,
fabric_2x3$v_to_slaves_2_wvalid;
// ports of submodule near_mem_io
wire [63 : 0] near_mem_io$axi4_slave_araddr,
near_mem_io$axi4_slave_awaddr,
near_mem_io$axi4_slave_rdata,
near_mem_io$axi4_slave_wdata,
near_mem_io$set_addr_map_addr_base,
near_mem_io$set_addr_map_addr_lim;
wire [7 : 0] near_mem_io$axi4_slave_arlen,
near_mem_io$axi4_slave_awlen,
near_mem_io$axi4_slave_wstrb;
wire [3 : 0] near_mem_io$axi4_slave_arcache,
near_mem_io$axi4_slave_arid,
near_mem_io$axi4_slave_arqos,
near_mem_io$axi4_slave_arregion,
near_mem_io$axi4_slave_awcache,
near_mem_io$axi4_slave_awid,
near_mem_io$axi4_slave_awqos,
near_mem_io$axi4_slave_awregion,
near_mem_io$axi4_slave_bid,
near_mem_io$axi4_slave_rid;
wire [2 : 0] near_mem_io$axi4_slave_arprot,
near_mem_io$axi4_slave_arsize,
near_mem_io$axi4_slave_awprot,
near_mem_io$axi4_slave_awsize;
wire [1 : 0] near_mem_io$axi4_slave_arburst,
near_mem_io$axi4_slave_awburst,
near_mem_io$axi4_slave_bresp,
near_mem_io$axi4_slave_rresp;
wire near_mem_io$EN_get_sw_interrupt_req_get,
near_mem_io$EN_get_timer_interrupt_req_get,
near_mem_io$EN_server_reset_request_put,
near_mem_io$EN_server_reset_response_get,
near_mem_io$EN_set_addr_map,
near_mem_io$RDY_get_sw_interrupt_req_get,
near_mem_io$RDY_get_timer_interrupt_req_get,
near_mem_io$RDY_server_reset_request_put,
near_mem_io$RDY_server_reset_response_get,
near_mem_io$axi4_slave_arlock,
near_mem_io$axi4_slave_arready,
near_mem_io$axi4_slave_arvalid,
near_mem_io$axi4_slave_awlock,
near_mem_io$axi4_slave_awready,
near_mem_io$axi4_slave_awvalid,
near_mem_io$axi4_slave_bready,
near_mem_io$axi4_slave_bvalid,
near_mem_io$axi4_slave_rlast,
near_mem_io$axi4_slave_rready,
near_mem_io$axi4_slave_rvalid,
near_mem_io$axi4_slave_wlast,
near_mem_io$axi4_slave_wready,
near_mem_io$axi4_slave_wvalid,
near_mem_io$get_sw_interrupt_req_get,
near_mem_io$get_timer_interrupt_req_get;
// ports of submodule plic
wire [63 : 0] plic$axi4_slave_araddr,
plic$axi4_slave_awaddr,
plic$axi4_slave_rdata,
plic$axi4_slave_wdata,
plic$set_addr_map_addr_base,
plic$set_addr_map_addr_lim;
wire [7 : 0] plic$axi4_slave_arlen,
plic$axi4_slave_awlen,
plic$axi4_slave_wstrb;
wire [3 : 0] plic$axi4_slave_arcache,
plic$axi4_slave_arid,
plic$axi4_slave_arqos,
plic$axi4_slave_arregion,
plic$axi4_slave_awcache,
plic$axi4_slave_awid,
plic$axi4_slave_awqos,
plic$axi4_slave_awregion,
plic$axi4_slave_bid,
plic$axi4_slave_rid,
plic$set_verbosity_verbosity;
wire [2 : 0] plic$axi4_slave_arprot,
plic$axi4_slave_arsize,
plic$axi4_slave_awprot,
plic$axi4_slave_awsize;
wire [1 : 0] plic$axi4_slave_arburst,
plic$axi4_slave_awburst,
plic$axi4_slave_bresp,
plic$axi4_slave_rresp;
wire plic$EN_server_reset_request_put,
plic$EN_server_reset_response_get,
plic$EN_set_addr_map,
plic$EN_set_verbosity,
plic$EN_show_PLIC_state,
plic$RDY_server_reset_request_put,
plic$RDY_server_reset_response_get,
plic$axi4_slave_arlock,
plic$axi4_slave_arready,
plic$axi4_slave_arvalid,
plic$axi4_slave_awlock,
plic$axi4_slave_awready,
plic$axi4_slave_awvalid,
plic$axi4_slave_bready,
plic$axi4_slave_bvalid,
plic$axi4_slave_rlast,
plic$axi4_slave_rready,
plic$axi4_slave_rvalid,
plic$axi4_slave_wlast,
plic$axi4_slave_wready,
plic$axi4_slave_wvalid,
plic$v_sources_0_m_interrupt_req_set_not_clear,
plic$v_sources_10_m_interrupt_req_set_not_clear,
plic$v_sources_11_m_interrupt_req_set_not_clear,
plic$v_sources_12_m_interrupt_req_set_not_clear,
plic$v_sources_13_m_interrupt_req_set_not_clear,
plic$v_sources_14_m_interrupt_req_set_not_clear,
plic$v_sources_15_m_interrupt_req_set_not_clear,
plic$v_sources_1_m_interrupt_req_set_not_clear,
plic$v_sources_2_m_interrupt_req_set_not_clear,
plic$v_sources_3_m_interrupt_req_set_not_clear,
plic$v_sources_4_m_interrupt_req_set_not_clear,
plic$v_sources_5_m_interrupt_req_set_not_clear,
plic$v_sources_6_m_interrupt_req_set_not_clear,
plic$v_sources_7_m_interrupt_req_set_not_clear,
plic$v_sources_8_m_interrupt_req_set_not_clear,
plic$v_sources_9_m_interrupt_req_set_not_clear,
plic$v_targets_0_m_eip,
plic$v_targets_1_m_eip;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete,
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
CAN_FIRE_RL_rl_rd_addr_channel,
CAN_FIRE_RL_rl_rd_addr_channel_1,
CAN_FIRE_RL_rl_rd_addr_channel_2,
CAN_FIRE_RL_rl_rd_addr_channel_3,
CAN_FIRE_RL_rl_rd_data_channel,
CAN_FIRE_RL_rl_rd_data_channel_1,
CAN_FIRE_RL_rl_rd_data_channel_2,
CAN_FIRE_RL_rl_rd_data_channel_3,
CAN_FIRE_RL_rl_relay_external_interrupts,
CAN_FIRE_RL_rl_relay_sw_interrupts,
CAN_FIRE_RL_rl_relay_timer_interrupts,
CAN_FIRE_RL_rl_wr_addr_channel,
CAN_FIRE_RL_rl_wr_addr_channel_1,
CAN_FIRE_RL_rl_wr_addr_channel_2,
CAN_FIRE_RL_rl_wr_addr_channel_3,
CAN_FIRE_RL_rl_wr_data_channel,
CAN_FIRE_RL_rl_wr_data_channel_1,
CAN_FIRE_RL_rl_wr_data_channel_2,
CAN_FIRE_RL_rl_wr_data_channel_3,
CAN_FIRE_RL_rl_wr_response_channel,
CAN_FIRE_RL_rl_wr_response_channel_1,
CAN_FIRE_RL_rl_wr_response_channel_2,
CAN_FIRE_RL_rl_wr_response_channel_3,
CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
CAN_FIRE_cpu_dmem_master_m_arready,
CAN_FIRE_cpu_dmem_master_m_awready,
CAN_FIRE_cpu_dmem_master_m_bvalid,
CAN_FIRE_cpu_dmem_master_m_rvalid,
CAN_FIRE_cpu_dmem_master_m_wready,
CAN_FIRE_cpu_imem_master_m_arready,
CAN_FIRE_cpu_imem_master_m_awready,
CAN_FIRE_cpu_imem_master_m_bvalid,
CAN_FIRE_cpu_imem_master_m_rvalid,
CAN_FIRE_cpu_imem_master_m_wready,
CAN_FIRE_cpu_reset_server_request_put,
CAN_FIRE_cpu_reset_server_response_get,
CAN_FIRE_nmi_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
WILL_FIRE_RL_rl_cpu_hart0_reset_complete,
WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
WILL_FIRE_RL_rl_rd_addr_channel,
WILL_FIRE_RL_rl_rd_addr_channel_1,
WILL_FIRE_RL_rl_rd_addr_channel_2,
WILL_FIRE_RL_rl_rd_addr_channel_3,
WILL_FIRE_RL_rl_rd_data_channel,
WILL_FIRE_RL_rl_rd_data_channel_1,
WILL_FIRE_RL_rl_rd_data_channel_2,
WILL_FIRE_RL_rl_rd_data_channel_3,
WILL_FIRE_RL_rl_relay_external_interrupts,
WILL_FIRE_RL_rl_relay_sw_interrupts,
WILL_FIRE_RL_rl_relay_timer_interrupts,
WILL_FIRE_RL_rl_wr_addr_channel,
WILL_FIRE_RL_rl_wr_addr_channel_1,
WILL_FIRE_RL_rl_wr_addr_channel_2,
WILL_FIRE_RL_rl_wr_addr_channel_3,
WILL_FIRE_RL_rl_wr_data_channel,
WILL_FIRE_RL_rl_wr_data_channel_1,
WILL_FIRE_RL_rl_wr_data_channel_2,
WILL_FIRE_RL_rl_wr_data_channel_3,
WILL_FIRE_RL_rl_wr_response_channel,
WILL_FIRE_RL_rl_wr_response_channel_1,
WILL_FIRE_RL_rl_wr_response_channel_2,
WILL_FIRE_RL_rl_wr_response_channel_3,
WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
WILL_FIRE_cpu_dmem_master_m_arready,
WILL_FIRE_cpu_dmem_master_m_awready,
WILL_FIRE_cpu_dmem_master_m_bvalid,
WILL_FIRE_cpu_dmem_master_m_rvalid,
WILL_FIRE_cpu_dmem_master_m_wready,
WILL_FIRE_cpu_imem_master_m_arready,
WILL_FIRE_cpu_imem_master_m_awready,
WILL_FIRE_cpu_imem_master_m_bvalid,
WILL_FIRE_cpu_imem_master_m_rvalid,
WILL_FIRE_cpu_imem_master_m_wready,
WILL_FIRE_cpu_reset_server_request_put,
WILL_FIRE_cpu_reset_server_response_get,
WILL_FIRE_nmi_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4255;
reg [31 : 0] v__h4496;
reg [31 : 0] v__h4249;
reg [31 : 0] v__h4490;
// synopsys translate_on
// remaining internal signals
wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method cpu_reset_server_request_put
assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_cpu_reset_server_request_put =
EN_cpu_reset_server_request_put ;
// actionvalue method cpu_reset_server_response_get
assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ;
assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_cpu_reset_server_response_get =
EN_cpu_reset_server_response_get ;
// value method cpu_imem_master_m_awvalid
assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ;
// value method cpu_imem_master_m_awid
assign cpu_imem_master_awid = cpu$imem_master_awid ;
// value method cpu_imem_master_m_awaddr
assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ;
// value method cpu_imem_master_m_awlen
assign cpu_imem_master_awlen = cpu$imem_master_awlen ;
// value method cpu_imem_master_m_awsize
assign cpu_imem_master_awsize = cpu$imem_master_awsize ;
// value method cpu_imem_master_m_awburst
assign cpu_imem_master_awburst = cpu$imem_master_awburst ;
// value method cpu_imem_master_m_awlock
assign cpu_imem_master_awlock = cpu$imem_master_awlock ;
// value method cpu_imem_master_m_awcache
assign cpu_imem_master_awcache = cpu$imem_master_awcache ;
// value method cpu_imem_master_m_awprot
assign cpu_imem_master_awprot = cpu$imem_master_awprot ;
// value method cpu_imem_master_m_awqos
assign cpu_imem_master_awqos = cpu$imem_master_awqos ;
// value method cpu_imem_master_m_awregion
assign cpu_imem_master_awregion = cpu$imem_master_awregion ;
// action method cpu_imem_master_m_awready
assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ;
// value method cpu_imem_master_m_wvalid
assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ;
// value method cpu_imem_master_m_wdata
assign cpu_imem_master_wdata = cpu$imem_master_wdata ;
// value method cpu_imem_master_m_wstrb
assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ;
// value method cpu_imem_master_m_wlast
assign cpu_imem_master_wlast = cpu$imem_master_wlast ;
// action method cpu_imem_master_m_wready
assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ;
// action method cpu_imem_master_m_bvalid
assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
// value method cpu_imem_master_m_bready
assign cpu_imem_master_bready = cpu$imem_master_bready ;
// value method cpu_imem_master_m_arvalid
assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ;
// value method cpu_imem_master_m_arid
assign cpu_imem_master_arid = cpu$imem_master_arid ;
// value method cpu_imem_master_m_araddr
assign cpu_imem_master_araddr = cpu$imem_master_araddr ;
// value method cpu_imem_master_m_arlen
assign cpu_imem_master_arlen = cpu$imem_master_arlen ;
// value method cpu_imem_master_m_arsize
assign cpu_imem_master_arsize = cpu$imem_master_arsize ;
// value method cpu_imem_master_m_arburst
assign cpu_imem_master_arburst = cpu$imem_master_arburst ;
// value method cpu_imem_master_m_arlock
assign cpu_imem_master_arlock = cpu$imem_master_arlock ;
// value method cpu_imem_master_m_arcache
assign cpu_imem_master_arcache = cpu$imem_master_arcache ;
// value method cpu_imem_master_m_arprot
assign cpu_imem_master_arprot = cpu$imem_master_arprot ;
// value method cpu_imem_master_m_arqos
assign cpu_imem_master_arqos = cpu$imem_master_arqos ;
// value method cpu_imem_master_m_arregion
assign cpu_imem_master_arregion = cpu$imem_master_arregion ;
// action method cpu_imem_master_m_arready
assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ;
// action method cpu_imem_master_m_rvalid
assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
// value method cpu_imem_master_m_rready
assign cpu_imem_master_rready = cpu$imem_master_rready ;
// value method cpu_dmem_master_m_awvalid
assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ;
// value method cpu_dmem_master_m_awid
assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ;
// value method cpu_dmem_master_m_awaddr
assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ;
// value method cpu_dmem_master_m_awlen
assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ;
// value method cpu_dmem_master_m_awsize
assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ;
// value method cpu_dmem_master_m_awburst
assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ;
// value method cpu_dmem_master_m_awlock
assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ;
// value method cpu_dmem_master_m_awcache
assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ;
// value method cpu_dmem_master_m_awprot
assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ;
// value method cpu_dmem_master_m_awqos
assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ;
// value method cpu_dmem_master_m_awregion
assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ;
// action method cpu_dmem_master_m_awready
assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ;
// value method cpu_dmem_master_m_wvalid
assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ;
// value method cpu_dmem_master_m_wdata
assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ;
// value method cpu_dmem_master_m_wstrb
assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ;
// value method cpu_dmem_master_m_wlast
assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ;
// action method cpu_dmem_master_m_wready
assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ;
// action method cpu_dmem_master_m_bvalid
assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ;
// value method cpu_dmem_master_m_bready
assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ;
// value method cpu_dmem_master_m_arvalid
assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ;
// value method cpu_dmem_master_m_arid
assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ;
// value method cpu_dmem_master_m_araddr
assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ;
// value method cpu_dmem_master_m_arlen
assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ;
// value method cpu_dmem_master_m_arsize
assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ;
// value method cpu_dmem_master_m_arburst
assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ;
// value method cpu_dmem_master_m_arlock
assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ;
// value method cpu_dmem_master_m_arcache
assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ;
// value method cpu_dmem_master_m_arprot
assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ;
// value method cpu_dmem_master_m_arqos
assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ;
// value method cpu_dmem_master_m_arregion
assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ;
// action method cpu_dmem_master_m_arready
assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ;
// action method cpu_dmem_master_m_rvalid
assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ;
// value method cpu_dmem_master_m_rready
assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ;
// action method core_external_interrupt_sources_0_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_1_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_2_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_3_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_4_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_5_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_6_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_7_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_8_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_9_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_10_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_11_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_12_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_13_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_14_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_15_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// submodule cpu
mkCPU cpu(.CLK(CLK),
.RST_N(RST_N),
.dmem_master_arready(cpu$dmem_master_arready),
.dmem_master_awready(cpu$dmem_master_awready),
.dmem_master_bid(cpu$dmem_master_bid),
.dmem_master_bresp(cpu$dmem_master_bresp),
.dmem_master_bvalid(cpu$dmem_master_bvalid),
.dmem_master_rdata(cpu$dmem_master_rdata),
.dmem_master_rid(cpu$dmem_master_rid),
.dmem_master_rlast(cpu$dmem_master_rlast),
.dmem_master_rresp(cpu$dmem_master_rresp),
.dmem_master_rvalid(cpu$dmem_master_rvalid),
.dmem_master_wready(cpu$dmem_master_wready),
.hart0_server_reset_request_put(cpu$hart0_server_reset_request_put),
.imem_master_arready(cpu$imem_master_arready),
.imem_master_awready(cpu$imem_master_awready),
.imem_master_bid(cpu$imem_master_bid),
.imem_master_bresp(cpu$imem_master_bresp),
.imem_master_bvalid(cpu$imem_master_bvalid),
.imem_master_rdata(cpu$imem_master_rdata),
.imem_master_rid(cpu$imem_master_rid),
.imem_master_rlast(cpu$imem_master_rlast),
.imem_master_rresp(cpu$imem_master_rresp),
.imem_master_rvalid(cpu$imem_master_rvalid),
.imem_master_wready(cpu$imem_master_wready),
.m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear),
.nmi_req_set_not_clear(cpu$nmi_req_set_not_clear),
.s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear),
.set_verbosity_logdelay(cpu$set_verbosity_logdelay),
.set_verbosity_verbosity(cpu$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(cpu$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(cpu$set_watch_tohost_watch_tohost),
.software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear),
.timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear),
.EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put),
.EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get),
.EN_set_verbosity(cpu$EN_set_verbosity),
.EN_set_watch_tohost(cpu$EN_set_watch_tohost),
.RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put),
.hart0_server_reset_response_get(cpu$hart0_server_reset_response_get),
.RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get),
.imem_master_awvalid(cpu$imem_master_awvalid),
.imem_master_awid(cpu$imem_master_awid),
.imem_master_awaddr(cpu$imem_master_awaddr),
.imem_master_awlen(cpu$imem_master_awlen),
.imem_master_awsize(cpu$imem_master_awsize),
.imem_master_awburst(cpu$imem_master_awburst),
.imem_master_awlock(cpu$imem_master_awlock),
.imem_master_awcache(cpu$imem_master_awcache),
.imem_master_awprot(cpu$imem_master_awprot),
.imem_master_awqos(cpu$imem_master_awqos),
.imem_master_awregion(cpu$imem_master_awregion),
.imem_master_wvalid(cpu$imem_master_wvalid),
.imem_master_wdata(cpu$imem_master_wdata),
.imem_master_wstrb(cpu$imem_master_wstrb),
.imem_master_wlast(cpu$imem_master_wlast),
.imem_master_bready(cpu$imem_master_bready),
.imem_master_arvalid(cpu$imem_master_arvalid),
.imem_master_arid(cpu$imem_master_arid),
.imem_master_araddr(cpu$imem_master_araddr),
.imem_master_arlen(cpu$imem_master_arlen),
.imem_master_arsize(cpu$imem_master_arsize),
.imem_master_arburst(cpu$imem_master_arburst),
.imem_master_arlock(cpu$imem_master_arlock),
.imem_master_arcache(cpu$imem_master_arcache),
.imem_master_arprot(cpu$imem_master_arprot),
.imem_master_arqos(cpu$imem_master_arqos),
.imem_master_arregion(cpu$imem_master_arregion),
.imem_master_rready(cpu$imem_master_rready),
.dmem_master_awvalid(cpu$dmem_master_awvalid),
.dmem_master_awid(cpu$dmem_master_awid),
.dmem_master_awaddr(cpu$dmem_master_awaddr),
.dmem_master_awlen(cpu$dmem_master_awlen),
.dmem_master_awsize(cpu$dmem_master_awsize),
.dmem_master_awburst(cpu$dmem_master_awburst),
.dmem_master_awlock(cpu$dmem_master_awlock),
.dmem_master_awcache(cpu$dmem_master_awcache),
.dmem_master_awprot(cpu$dmem_master_awprot),
.dmem_master_awqos(cpu$dmem_master_awqos),
.dmem_master_awregion(cpu$dmem_master_awregion),
.dmem_master_wvalid(cpu$dmem_master_wvalid),
.dmem_master_wdata(cpu$dmem_master_wdata),
.dmem_master_wstrb(cpu$dmem_master_wstrb),
.dmem_master_wlast(cpu$dmem_master_wlast),
.dmem_master_bready(cpu$dmem_master_bready),
.dmem_master_arvalid(cpu$dmem_master_arvalid),
.dmem_master_arid(cpu$dmem_master_arid),
.dmem_master_araddr(cpu$dmem_master_araddr),
.dmem_master_arlen(cpu$dmem_master_arlen),
.dmem_master_arsize(cpu$dmem_master_arsize),
.dmem_master_arburst(cpu$dmem_master_arburst),
.dmem_master_arlock(cpu$dmem_master_arlock),
.dmem_master_arcache(cpu$dmem_master_arcache),
.dmem_master_arprot(cpu$dmem_master_arprot),
.dmem_master_arqos(cpu$dmem_master_arqos),
.dmem_master_arregion(cpu$dmem_master_arregion),
.dmem_master_rready(cpu$dmem_master_rready),
.RDY_set_verbosity(),
.RDY_set_watch_tohost());
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule fabric_2x3
mkFabric_2x3 fabric_2x3(.CLK(CLK),
.RST_N(RST_N),
.set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity),
.v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr),
.v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst),
.v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache),
.v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid),
.v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen),
.v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock),
.v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot),
.v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos),
.v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion),
.v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize),
.v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid),
.v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr),
.v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst),
.v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache),
.v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid),
.v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen),
.v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock),
.v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot),
.v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos),
.v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion),
.v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize),
.v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid),
.v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready),
.v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready),
.v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata),
.v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast),
.v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb),
.v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid),
.v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr),
.v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst),
.v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache),
.v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid),
.v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen),
.v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock),
.v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot),
.v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos),
.v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion),
.v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize),
.v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid),
.v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr),
.v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst),
.v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache),
.v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid),
.v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen),
.v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock),
.v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot),
.v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos),
.v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion),
.v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize),
.v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid),
.v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready),
.v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready),
.v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata),
.v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast),
.v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb),
.v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid),
.v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready),
.v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready),
.v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid),
.v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp),
.v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid),
.v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata),
.v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid),
.v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast),
.v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp),
.v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid),
.v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready),
.v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready),
.v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready),
.v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid),
.v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp),
.v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid),
.v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata),
.v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid),
.v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast),
.v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp),
.v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid),
.v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready),
.v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready),
.v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready),
.v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid),
.v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp),
.v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid),
.v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata),
.v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid),
.v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast),
.v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp),
.v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid),
.v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready),
.EN_reset(fabric_2x3$EN_reset),
.EN_set_verbosity(fabric_2x3$EN_set_verbosity),
.RDY_reset(fabric_2x3$RDY_reset),
.RDY_set_verbosity(),
.v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready),
.v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready),
.v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid),
.v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid),
.v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp),
.v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready),
.v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid),
.v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid),
.v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata),
.v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp),
.v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast),
.v_from_masters_1_awready(),
.v_from_masters_1_wready(),
.v_from_masters_1_bvalid(),
.v_from_masters_1_bid(),
.v_from_masters_1_bresp(),
.v_from_masters_1_arready(),
.v_from_masters_1_rvalid(),
.v_from_masters_1_rid(),
.v_from_masters_1_rdata(),
.v_from_masters_1_rresp(),
.v_from_masters_1_rlast(),
.v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid),
.v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid),
.v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr),
.v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen),
.v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize),
.v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst),
.v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock),
.v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache),
.v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot),
.v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos),
.v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion),
.v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid),
.v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata),
.v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb),
.v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast),
.v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready),
.v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid),
.v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid),
.v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr),
.v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen),
.v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize),
.v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst),
.v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock),
.v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache),
.v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot),
.v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos),
.v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion),
.v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready),
.v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid),
.v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid),
.v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr),
.v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen),
.v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize),
.v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst),
.v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock),
.v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache),
.v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot),
.v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos),
.v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion),
.v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid),
.v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata),
.v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb),
.v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast),
.v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready),
.v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid),
.v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid),
.v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr),
.v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen),
.v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize),
.v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst),
.v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock),
.v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache),
.v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot),
.v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos),
.v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion),
.v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready),
.v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid),
.v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid),
.v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr),
.v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen),
.v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize),
.v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst),
.v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock),
.v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache),
.v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot),
.v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos),
.v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion),
.v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid),
.v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata),
.v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb),
.v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast),
.v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready),
.v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid),
.v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid),
.v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr),
.v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen),
.v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize),
.v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst),
.v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock),
.v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache),
.v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot),
.v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos),
.v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion),
.v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready));
// submodule near_mem_io
mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK),
.RST_N(RST_N),
.axi4_slave_araddr(near_mem_io$axi4_slave_araddr),
.axi4_slave_arburst(near_mem_io$axi4_slave_arburst),
.axi4_slave_arcache(near_mem_io$axi4_slave_arcache),
.axi4_slave_arid(near_mem_io$axi4_slave_arid),
.axi4_slave_arlen(near_mem_io$axi4_slave_arlen),
.axi4_slave_arlock(near_mem_io$axi4_slave_arlock),
.axi4_slave_arprot(near_mem_io$axi4_slave_arprot),
.axi4_slave_arqos(near_mem_io$axi4_slave_arqos),
.axi4_slave_arregion(near_mem_io$axi4_slave_arregion),
.axi4_slave_arsize(near_mem_io$axi4_slave_arsize),
.axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid),
.axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr),
.axi4_slave_awburst(near_mem_io$axi4_slave_awburst),
.axi4_slave_awcache(near_mem_io$axi4_slave_awcache),
.axi4_slave_awid(near_mem_io$axi4_slave_awid),
.axi4_slave_awlen(near_mem_io$axi4_slave_awlen),
.axi4_slave_awlock(near_mem_io$axi4_slave_awlock),
.axi4_slave_awprot(near_mem_io$axi4_slave_awprot),
.axi4_slave_awqos(near_mem_io$axi4_slave_awqos),
.axi4_slave_awregion(near_mem_io$axi4_slave_awregion),
.axi4_slave_awsize(near_mem_io$axi4_slave_awsize),
.axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid),
.axi4_slave_bready(near_mem_io$axi4_slave_bready),
.axi4_slave_rready(near_mem_io$axi4_slave_rready),
.axi4_slave_wdata(near_mem_io$axi4_slave_wdata),
.axi4_slave_wlast(near_mem_io$axi4_slave_wlast),
.axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb),
.axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid),
.set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base),
.set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim),
.EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put),
.EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get),
.EN_set_addr_map(near_mem_io$EN_set_addr_map),
.EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get),
.EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get),
.RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put),
.RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get),
.RDY_set_addr_map(),
.axi4_slave_awready(near_mem_io$axi4_slave_awready),
.axi4_slave_wready(near_mem_io$axi4_slave_wready),
.axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid),
.axi4_slave_bid(near_mem_io$axi4_slave_bid),
.axi4_slave_bresp(near_mem_io$axi4_slave_bresp),
.axi4_slave_arready(near_mem_io$axi4_slave_arready),
.axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid),
.axi4_slave_rid(near_mem_io$axi4_slave_rid),
.axi4_slave_rdata(near_mem_io$axi4_slave_rdata),
.axi4_slave_rresp(near_mem_io$axi4_slave_rresp),
.axi4_slave_rlast(near_mem_io$axi4_slave_rlast),
.get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get),
.RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get),
.get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get),
.RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get));
// submodule plic
mkPLIC_16_2_7 plic(.CLK(CLK),
.RST_N(RST_N),
.axi4_slave_araddr(plic$axi4_slave_araddr),
.axi4_slave_arburst(plic$axi4_slave_arburst),
.axi4_slave_arcache(plic$axi4_slave_arcache),
.axi4_slave_arid(plic$axi4_slave_arid),
.axi4_slave_arlen(plic$axi4_slave_arlen),
.axi4_slave_arlock(plic$axi4_slave_arlock),
.axi4_slave_arprot(plic$axi4_slave_arprot),
.axi4_slave_arqos(plic$axi4_slave_arqos),
.axi4_slave_arregion(plic$axi4_slave_arregion),
.axi4_slave_arsize(plic$axi4_slave_arsize),
.axi4_slave_arvalid(plic$axi4_slave_arvalid),
.axi4_slave_awaddr(plic$axi4_slave_awaddr),
.axi4_slave_awburst(plic$axi4_slave_awburst),
.axi4_slave_awcache(plic$axi4_slave_awcache),
.axi4_slave_awid(plic$axi4_slave_awid),
.axi4_slave_awlen(plic$axi4_slave_awlen),
.axi4_slave_awlock(plic$axi4_slave_awlock),
.axi4_slave_awprot(plic$axi4_slave_awprot),
.axi4_slave_awqos(plic$axi4_slave_awqos),
.axi4_slave_awregion(plic$axi4_slave_awregion),
.axi4_slave_awsize(plic$axi4_slave_awsize),
.axi4_slave_awvalid(plic$axi4_slave_awvalid),
.axi4_slave_bready(plic$axi4_slave_bready),
.axi4_slave_rready(plic$axi4_slave_rready),
.axi4_slave_wdata(plic$axi4_slave_wdata),
.axi4_slave_wlast(plic$axi4_slave_wlast),
.axi4_slave_wstrb(plic$axi4_slave_wstrb),
.axi4_slave_wvalid(plic$axi4_slave_wvalid),
.set_addr_map_addr_base(plic$set_addr_map_addr_base),
.set_addr_map_addr_lim(plic$set_addr_map_addr_lim),
.set_verbosity_verbosity(plic$set_verbosity_verbosity),
.v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear),
.v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear),
.v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear),
.v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear),
.v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear),
.v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear),
.v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear),
.v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear),
.v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear),
.v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear),
.v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear),
.v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear),
.v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear),
.v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear),
.v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear),
.v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear),
.EN_set_verbosity(plic$EN_set_verbosity),
.EN_show_PLIC_state(plic$EN_show_PLIC_state),
.EN_server_reset_request_put(plic$EN_server_reset_request_put),
.EN_server_reset_response_get(plic$EN_server_reset_response_get),
.EN_set_addr_map(plic$EN_set_addr_map),
.RDY_set_verbosity(),
.RDY_show_PLIC_state(),
.RDY_server_reset_request_put(plic$RDY_server_reset_request_put),
.RDY_server_reset_response_get(plic$RDY_server_reset_response_get),
.RDY_set_addr_map(),
.axi4_slave_awready(plic$axi4_slave_awready),
.axi4_slave_wready(plic$axi4_slave_wready),
.axi4_slave_bvalid(plic$axi4_slave_bvalid),
.axi4_slave_bid(plic$axi4_slave_bid),
.axi4_slave_bresp(plic$axi4_slave_bresp),
.axi4_slave_arready(plic$axi4_slave_arready),
.axi4_slave_rvalid(plic$axi4_slave_rvalid),
.axi4_slave_rid(plic$axi4_slave_rid),
.axi4_slave_rdata(plic$axi4_slave_rdata),
.axi4_slave_rresp(plic$axi4_slave_rresp),
.axi4_slave_rlast(plic$axi4_slave_rlast),
.v_targets_0_m_eip(plic$v_targets_0_m_eip),
.v_targets_1_m_eip(plic$v_targets_1_m_eip));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_wr_addr_channel
assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
// rule RL_rl_wr_data_channel
assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ;
// rule RL_rl_wr_response_channel
assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ;
// rule RL_rl_rd_addr_channel
assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
// rule RL_rl_rd_data_channel
assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ;
// rule RL_rl_wr_addr_channel_1
assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
// rule RL_rl_wr_data_channel_1
assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_response_channel_1
assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
// rule RL_rl_rd_addr_channel_1
assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
// rule RL_rl_rd_data_channel_1
assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_addr_channel_2
assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
// rule RL_rl_wr_data_channel_2
assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_response_channel_2
assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
// rule RL_rl_rd_addr_channel_2
assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
// rule RL_rl_rd_data_channel_2
assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_addr_channel_3
assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
// rule RL_rl_wr_data_channel_3
assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
// rule RL_rl_wr_response_channel_3
assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
// rule RL_rl_rd_addr_channel_3
assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
// rule RL_rl_rd_data_channel_3
assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
// rule RL_rl_relay_sw_interrupts
assign CAN_FIRE_RL_rl_relay_sw_interrupts =
near_mem_io$RDY_get_sw_interrupt_req_get ;
assign WILL_FIRE_RL_rl_relay_sw_interrupts =
near_mem_io$RDY_get_sw_interrupt_req_get ;
// rule RL_rl_relay_timer_interrupts
assign CAN_FIRE_RL_rl_relay_timer_interrupts =
near_mem_io$RDY_get_timer_interrupt_req_get ;
assign WILL_FIRE_RL_rl_relay_timer_interrupts =
near_mem_io$RDY_get_timer_interrupt_req_get ;
// rule RL_rl_relay_external_interrupts
assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
// rule RL_rl_cpu_hart0_reset_from_soc_start
assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
near_mem_io$RDY_server_reset_request_put &&
plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ;
assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
// rule RL_rl_cpu_hart0_reset_complete
assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete =
near_mem_io$RDY_server_reset_response_get &&
plic$RDY_server_reset_response_get &&
cpu$RDY_hart0_server_reset_response_get &&
f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
// submodule cpu
assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ;
assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ;
assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ;
assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ;
assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ;
assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ;
assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ;
assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ;
assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ;
assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ;
assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ;
assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ;
assign cpu$imem_master_arready = cpu_imem_master_arready ;
assign cpu$imem_master_awready = cpu_imem_master_awready ;
assign cpu$imem_master_bid = cpu_imem_master_bid ;
assign cpu$imem_master_bresp = cpu_imem_master_bresp ;
assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ;
assign cpu$imem_master_rdata = cpu_imem_master_rdata ;
assign cpu$imem_master_rid = cpu_imem_master_rid ;
assign cpu$imem_master_rlast = cpu_imem_master_rlast ;
assign cpu$imem_master_rresp = cpu_imem_master_rresp ;
assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ;
assign cpu$imem_master_wready = cpu_imem_master_wready ;
assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ;
assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ;
assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ;
assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ;
assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ;
assign cpu$set_watch_tohost_tohost_addr = set_watch_tohost_tohost_addr ;
assign cpu$set_watch_tohost_watch_tohost = set_watch_tohost_watch_tohost ;
assign cpu$software_interrupt_req_set_not_clear =
near_mem_io$get_sw_interrupt_req_get ;
assign cpu$timer_interrupt_req_set_not_clear =
near_mem_io$get_timer_interrupt_req_get ;
assign cpu$EN_hart0_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign cpu$EN_hart0_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign cpu$EN_set_verbosity = EN_set_verbosity ;
assign cpu$EN_set_watch_tohost = EN_set_watch_tohost ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = cpu_reset_server_request_put ;
assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ;
assign f_reset_reqs$DEQ =
near_mem_io$RDY_server_reset_request_put &&
plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ;
assign f_reset_rsps$ENQ =
near_mem_io$RDY_server_reset_response_get &&
plic$RDY_server_reset_response_get &&
cpu$RDY_hart0_server_reset_response_get &&
f_reset_rsps$FULL_N ;
assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule fabric_2x3
assign fabric_2x3$set_verbosity_verbosity = 4'h0 ;
assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ;
assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ;
assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ;
assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ;
assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ;
assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ;
assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ;
assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ;
assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ;
assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ;
assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ;
assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ;
assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ;
assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ;
assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ;
assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ;
assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ;
assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ;
assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ;
assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ;
assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ;
assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ;
assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ;
assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ;
assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ;
assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ;
assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ;
assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ;
assign fabric_2x3$v_from_masters_1_araddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arburst =
2'b10 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arcache =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arlen =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arprot =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arqos =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arregion =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arsize =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ;
assign fabric_2x3$v_from_masters_1_awaddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awburst =
2'b10 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awcache =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awlen =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awprot =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awqos =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awregion =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awsize =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ;
assign fabric_2x3$v_from_masters_1_bready = 1'd0 ;
assign fabric_2x3$v_from_masters_1_rready = 1'd0 ;
assign fabric_2x3$v_from_masters_1_wdata =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wstrb =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ;
assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ;
assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ;
assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ;
assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ;
assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ;
assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ;
assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ;
assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ;
assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ;
assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ;
assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ;
assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ;
assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ;
assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ;
assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ;
assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ;
assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ;
assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ;
assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ;
assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ;
assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ;
assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ;
assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ;
assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ;
assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ;
assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ;
assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ;
assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ;
assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ;
assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ;
assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ;
assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ;
assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ;
assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign fabric_2x3$EN_set_verbosity = 1'b0 ;
// submodule near_mem_io
assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ;
assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ;
assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ;
assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ;
assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ;
assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ;
assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ;
assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ;
assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ;
assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ;
assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ;
assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ;
assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ;
assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ;
assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ;
assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ;
assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ;
assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ;
assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ;
assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ;
assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ;
assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ;
assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ;
assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ;
assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ;
assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ;
assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ;
assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ;
assign near_mem_io$set_addr_map_addr_base =
soc_map$m_near_mem_io_addr_base ;
assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ;
assign near_mem_io$EN_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign near_mem_io$EN_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign near_mem_io$EN_set_addr_map =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign near_mem_io$EN_get_timer_interrupt_req_get =
near_mem_io$RDY_get_timer_interrupt_req_get ;
assign near_mem_io$EN_get_sw_interrupt_req_get =
near_mem_io$RDY_get_sw_interrupt_req_get ;
// submodule plic
assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ;
assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ;
assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ;
assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ;
assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ;
assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ;
assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ;
assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ;
assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ;
assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ;
assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ;
assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ;
assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ;
assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ;
assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ;
assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ;
assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ;
assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ;
assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ;
assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ;
assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ;
assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ;
assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ;
assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ;
assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ;
assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ;
assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ;
assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ;
assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ;
assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ;
assign plic$set_verbosity_verbosity = 4'h0 ;
assign plic$v_sources_0_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ;
assign plic$v_sources_10_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ;
assign plic$v_sources_11_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ;
assign plic$v_sources_12_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ;
assign plic$v_sources_13_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ;
assign plic$v_sources_14_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ;
assign plic$v_sources_15_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ;
assign plic$v_sources_1_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ;
assign plic$v_sources_2_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ;
assign plic$v_sources_3_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ;
assign plic$v_sources_4_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ;
assign plic$v_sources_5_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ;
assign plic$v_sources_6_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ;
assign plic$v_sources_7_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ;
assign plic$v_sources_8_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ;
assign plic$v_sources_9_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ;
assign plic$EN_set_verbosity = 1'b0 ;
assign plic$EN_show_PLIC_state = 1'b0 ;
assign plic$EN_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign plic$EN_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 =
plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset &&
cpu$RDY_hart0_server_reset_request_put &&
f_reset_reqs$EMPTY_N ;
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
begin
v__h4255 = $stime;
#0;
end
v__h4249 = v__h4255 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
$display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4249);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
begin
v__h4496 = $stime;
#0;
end
v__h4490 = v__h4496 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
$display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4490);
end
// synopsys translate_on
endmodule |
module antiDroopIIR_16 (
input clk,
input trig,
input signed [15:0] din,
input signed [6:0] tapWeight,
input accClr_en,
//input oflowClr,
(* shreg_extract = "no" *) output reg oflowDetect = 1'd0,
output reg signed [15:0] dout = 16'sd0);
parameter IIR_scale = 15; // define the scaling factor for the IIR multiplier, eg for 0.002 (din = 63, IIR_scale = 15).
//`define ADDPIPEREG
(* shreg_extract = "no" *) reg signed [15:0] din_del = 16'sd0;
`ifdef ADDPIPEREG (* shreg_extract = "no" *) reg signed [15:0] din_del_b = 16'sd0;
`endif
reg signed [47:0] tap = 48'sd0;
reg signed [22:0] multreg = 23'sd0;
(* equivalent_register_removal = "no" *) reg trig_a = 1'b0, trig_b = 1'b0;
wire trig_edge = trig_a & ~trig_b;
//reg trig_edge = 1'b0;
(* shreg_extract = "no" *) reg signed [6:0] tapWeight_a = 7'sd0, tapWeight_b = 7'sd0;
//wire oflow = (^tap[IIR_scale+16:IIR_scale+15]);
wire oflow = (~&tap[47:IIR_scale+15] && ~&(~tap[47:IIR_scale+15]));
always @(posedge clk) begin
//trig_edge <= trig_a & ~trig_b;
tapWeight_a <= tapWeight;
tapWeight_b <= tapWeight_a;
trig_a <= trig;
trig_b <= trig_a;
din_del <= din;
`ifdef ADDPIPEREG
din_del_b <= din_del;
multreg <= din_del*tapWeight_b;
//dout <= din_del_b + tap[IIR_scale+15:IIR_scale];
if (oflow) dout <= (tap[IIR_scale+16]) ? -16'sd32768 : 16'sd32767;
else dout <= din_del_b + tap[IIR_scale+15:IIR_scale];
`else
multreg <= din*tapWeight_b;
//dout <= din_del + tap[IIR_scale+15:IIR_scale];
if (oflow) dout <= (tap[IIR_scale+16]) ? -16'sd32768 : 16'sd32767;
else dout <= din_del + tap[IIR_scale+15:IIR_scale];
`endif
if (trig_edge && accClr_en) tap <= 48'sd0;
else tap <= multreg + tap;
//tap <= din*tapWeight + tap;
//if (oflowDetect && oflowClr) oflowDetect <= 1'b0;
//else if ((~& tap[47:IIR_scale+12]) || (& ~tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if ((~& tap[47:IIR_scale+12]) || (& tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if (^ tap[IIR_scale+16:IIR_scale+15]) oflowDetect <= 1'b1;
//else oflowDetect <= oflowDetect;
//oflowDetect <= (^tap[IIR_scale+16:IIR_scale+15]) ? 1'b1 : 1'b0;
oflowDetect <= oflow;
end
endmodule |
module dsu_uartlite(
clk, rst,
txd, rxd,
spr_dat_i,
reg_txdata, reg_txdata_we,
reg_ctrl, reg_ctrl_we,
reg_sta, reg_sta_we,
reg_rxdata, reg_rxdata_we,
sram_ce,
sram_we,
sram_addr,
sram_wdata,
download_enable
);
//
input clk;
input rst;
// uart inout
input rxd;
output txd;
// spr access interface
input [7:0] spr_dat_i;
input reg_txdata_we;
input reg_ctrl_we;
input reg_rxdata_we;
input reg_sta_we;
output [7:0] reg_txdata;
output [7:0] reg_ctrl;
output [7:0] reg_sta;
output [7:0] reg_rxdata;
// sram interface
output sram_ce;
output sram_we;
output [31:0] sram_wdata;
output [`IOCM_Word_BW-1:0] sram_addr;
// backdoor control
input download_enable;
//
// four internal SPRs for uartlite
//
reg [7:0] reg_ctrl;
reg [7:0] reg_sta;
reg [7:0] reg_txdata;
reg [7:0] reg_rxdata;
//
wire tx_start;
wire rx_enable;
reg tx_busy_d;
reg interrupt_tx;
reg interrupt_rx;
//
//
//
wire txd;
wire rxd;
wire [7:0] rx_data;
wire [7:0] rx_data_to_sram;
wire rx_data_rdy;
wire tx_busy;
wire rx_idle;
wire interrupt;
//
// SPR: control register
//
// [TBV]: coding style of auto-cleared
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_ctrl <= 8'h00;
else if(reg_ctrl[0]) // the tx_enable bit (ctrl[0]) will auto cleared after write 1
reg_ctrl[0] <= 1'b0;
else if(reg_ctrl_we)
reg_ctrl <= spr_dat_i;
else if(reg_ctrl[4]) // the int_clear bit (ctrl[4]) will auto cleared after write 1
reg_ctrl[4] <= 1'b0;
end
assign tx_start = reg_ctrl[0];
assign rx_enable = !reg_ctrl[1];
assign int_clear = reg_ctrl[4];
//
// SPR: status register
//
// tx interrupt detect
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
tx_busy_d <= 1'b0;
else
tx_busy_d <= tx_busy;
//when detect the negedge of tx_busy that means transmitter is finished
//if the tx_interrupt enable then generate interrupt of transmitter.
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_tx <= 1'b0;
else if(!tx_busy && tx_busy_d)
interrupt_tx <= 1'b1;
else if(int_clear)
interrupt_tx <= 1'b0;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_rx <= 1'b0;
else if(rx_data_rdy && rx_enable)
interrupt_rx <= 1'b1;
else if(int_clear)
interrupt_rx <= 1'b0;
assign interrupt = interrupt_rx || interrupt_tx;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
reg_sta <= 8'h00;
else if(reg_sta_we)
reg_sta <= spr_dat_i;
else
reg_sta <= {3'b000, interrupt_rx, interrupt_tx, interrupt, !rx_idle, tx_busy};
//
// SPR: receive data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_rxdata <= 8'h00;
else if(rx_data_rdy && rx_enable )
reg_rxdata <= rx_data;
end
//
// SPR: transmit data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_txdata <= 8'h00;
else if(reg_txdata_we)
reg_txdata <= spr_dat_i;
end
//
// transmitter and receiver
//
dsu_Tx tx(
.clk(clk),
.rst(rst),
.TxD_start(tx_start),
.TxD_data(reg_txdata),
.TxD(txd),
.TxD_busy(tx_busy)
);
dsu_Rx rx(
.clk(clk),
.rst(rst),
.RxD(rxd),
.RxD_data_ready(rx_data_rdy),
.RxD_data(rx_data),
.RxD_endofpacket(),
.RxD_idle(rx_idle)
);
//
// back door mode: burn sram using received data
//
assign rx_data_to_sram = download_enable ? rx_data : 8'h00;
dsu_sram_ctrl sram_ctrl(
.clk(clk),
.rst(rst),
.rxd(rx_data_to_sram),
.rxd_ready(rx_data_rdy && download_enable),
.sram_ce(sram_ce),
.sram_we(sram_we),
.sram_addr(sram_addr),
.sram_wdata(sram_wdata),
.download_enable(download_enable)
);
endmodule |
module execute_mul_booth32(
//iDATA
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
//oDATA
output wire [63:0] oDATA,
output wire oHSF,
output wire oHOF,
output wire oHCF,
output wire oHPF,
output wire oHZF,
output wire oLSF,
output wire oLOF,
output wire oLCF,
output wire oLPF,
output wire oLZF
);
/****************************************
wire
****************************************/
wire [63:0] w_tmp_out;
wire [63:0] w0_tmp;
wire [63:0] w1_tmp;
wire [63:0] w2_tmp;
wire [63:0] w3_tmp;
wire [63:0] w4_tmp;
wire [63:0] w5_tmp;
wire [63:0] w6_tmp;
wire [63:0] w7_tmp;
wire [63:0] w8_tmp;
wire [63:0] w9_tmp;
wire [63:0] w10_tmp;
wire [63:0] w11_tmp;
wire [63:0] w12_tmp;
wire [63:0] w13_tmp;
wire [63:0] w14_tmp;
wire [63:0] w15_tmp;
wire [63:0] w16_tmp;
/****************************************
Booth - Encoder
****************************************/
assign w0_tmp = func_booth_algorithm(iDATA_0, iDATA_1[1], iDATA_1[0], 1'b0);
assign w1_tmp = func_booth_algorithm(iDATA_0, iDATA_1[3], iDATA_1[2], iDATA_1[1]);
assign w2_tmp = func_booth_algorithm(iDATA_0, iDATA_1[5], iDATA_1[4], iDATA_1[3]);
assign w3_tmp = func_booth_algorithm(iDATA_0, iDATA_1[7], iDATA_1[6], iDATA_1[5]);
assign w4_tmp = func_booth_algorithm(iDATA_0, iDATA_1[9], iDATA_1[8], iDATA_1[7]);
assign w5_tmp = func_booth_algorithm(iDATA_0, iDATA_1[11], iDATA_1[10], iDATA_1[9]);
assign w6_tmp = func_booth_algorithm(iDATA_0, iDATA_1[13], iDATA_1[12], iDATA_1[11]);
assign w7_tmp = func_booth_algorithm(iDATA_0, iDATA_1[15], iDATA_1[14], iDATA_1[13]);
assign w8_tmp = func_booth_algorithm(iDATA_0, iDATA_1[17], iDATA_1[16], iDATA_1[15]);
assign w9_tmp = func_booth_algorithm(iDATA_0, iDATA_1[19], iDATA_1[18], iDATA_1[17]);
assign w10_tmp = func_booth_algorithm(iDATA_0, iDATA_1[21], iDATA_1[20], iDATA_1[19]);
assign w11_tmp = func_booth_algorithm(iDATA_0, iDATA_1[23], iDATA_1[22], iDATA_1[21]);
assign w12_tmp = func_booth_algorithm(iDATA_0, iDATA_1[25], iDATA_1[24], iDATA_1[23]);
assign w13_tmp = func_booth_algorithm(iDATA_0, iDATA_1[27], iDATA_1[26], iDATA_1[25]);
assign w14_tmp = func_booth_algorithm(iDATA_0, iDATA_1[29], iDATA_1[28], iDATA_1[27]);
assign w15_tmp = func_booth_algorithm(iDATA_0, iDATA_1[31], iDATA_1[30], iDATA_1[29]);
assign w16_tmp = func_booth_algorithm(iDATA_0, 1'b0, 1'b0, iDATA_1[31]);
/****************************************
Booth - Exeout
****************************************/
assign w_tmp_out = w0_tmp + w1_tmp<<2 + w2_tmp<<4 + w3_tmp<<6 +
w4_tmp<<8 + w5_tmp<<10 + w6_tmp<<12 + w7_tmp<<14 +
w8_tmp<<16 + w9_tmp<<18 + w10_tmp<<20 + w11_tmp<<22 +
w12_tmp<<24 + w13_tmp<<26 + w14_tmp<<28 + w15_tmp<<30 + w16_tmp<<32;
function [63:0] func_booth_algorithm;
input [31:0] func_booth_algorithm_a;
input func_booth_algorithm_b2;
input func_booth_algorithm_b1;
input func_booth_algorithm_b0;
reg [2:0] reg_func_booth_algorithm_tmp;
reg [2:0] reg_func_booth_algorithm_cmd;
begin
reg_func_booth_algorithm_tmp = {func_booth_algorithm_b2, func_booth_algorithm_b1, func_booth_algorithm_b0};
case(reg_func_booth_algorithm_tmp)
3'h0 : reg_func_booth_algorithm_cmd = 3'h0;
3'h1 : reg_func_booth_algorithm_cmd = 3'h1;
3'h2 : reg_func_booth_algorithm_cmd = 3'h1;
3'h3 : reg_func_booth_algorithm_cmd = 3'h2;
3'h4 : reg_func_booth_algorithm_cmd = {1'b1, 2'h2};
3'h5 : reg_func_booth_algorithm_cmd = {1'b1, 2'h1};
3'h6 : reg_func_booth_algorithm_cmd = {1'b1, 2'h1};
default : reg_func_booth_algorithm_cmd = 3'h0;
endcase
if(reg_func_booth_algorithm_cmd[2] == 0)begin
//Plus
if(reg_func_booth_algorithm_cmd[1:0] == 2'h0)begin
func_booth_algorithm = {32{1'b0}};
end
else if(reg_func_booth_algorithm_cmd[1:0] == 2'h1)begin
func_booth_algorithm = {{32{1'b0}}, func_booth_algorithm_a};
end
else begin
func_booth_algorithm = {{32{1'b0}}, func_booth_algorithm_a} << 1;
end
end
else begin
if(reg_func_booth_algorithm_cmd[1:0] == 2'h0)begin
func_booth_algorithm = {32{1'b0}};
end
else if(reg_func_booth_algorithm_cmd[1:0] == 2'h1)begin
func_booth_algorithm = -{{32{1'b0}}, func_booth_algorithm_a};//(~{{32{1'b0}}, func_booth_algorithm_a}) + {{63{1'b0}}, 1'b1};
end
else begin
func_booth_algorithm = -({{32{1'b0}}, func_booth_algorithm_a} << 1);//(~({{32{1'b0}}, func_booth_algorithm_a} << 1)) + {{63{1'b0}}, 1'b1};
end
end
end
endfunction
/****************************************
Assign
****************************************/
assign oDATA = w_tmp_out;
assign oLSF = w_tmp_out[31];
assign oLCF = w_tmp_out[32];
assign oLOF = w_tmp_out[32] ^ w_tmp_out[31];
assign oLPF = w_tmp_out[0];
assign oLZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; //(w_tmp_out[32:0] == {33{1'b0}})? 1'b1 : 1'b0;
assign oHSF = w_tmp_out[32];
assign oHCF = 1'b0;
assign oHOF = w_tmp_out[63];
assign oHPF = w_tmp_out[32];
assign oHZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; //(w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0;
endmodule |
module daala_zynq_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB,
);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1 : 0] S_AXI_HP0_BRESP;
output [1 : 0] S_AXI_HP0_RRESP;
output [5 : 0] S_AXI_HP0_BID;
output [5 : 0] S_AXI_HP0_RID;
output [63 : 0] S_AXI_HP0_RDATA;
output [7 : 0] S_AXI_HP0_RCOUNT;
output [7 : 0] S_AXI_HP0_WCOUNT;
output [2 : 0] S_AXI_HP0_RACOUNT;
output [5 : 0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1 : 0] S_AXI_HP0_ARBURST;
input [1 : 0] S_AXI_HP0_ARLOCK;
input [2 : 0] S_AXI_HP0_ARSIZE;
input [1 : 0] S_AXI_HP0_AWBURST;
input [1 : 0] S_AXI_HP0_AWLOCK;
input [2 : 0] S_AXI_HP0_AWSIZE;
input [2 : 0] S_AXI_HP0_ARPROT;
input [2 : 0] S_AXI_HP0_AWPROT;
input [31 : 0] S_AXI_HP0_ARADDR;
input [31 : 0] S_AXI_HP0_AWADDR;
input [3 : 0] S_AXI_HP0_ARCACHE;
input [3 : 0] S_AXI_HP0_ARLEN;
input [3 : 0] S_AXI_HP0_ARQOS;
input [3 : 0] S_AXI_HP0_AWCACHE;
input [3 : 0] S_AXI_HP0_AWLEN;
input [3 : 0] S_AXI_HP0_AWQOS;
input [5 : 0] S_AXI_HP0_ARID;
input [5 : 0] S_AXI_HP0_AWID;
input [5 : 0] S_AXI_HP0_WID;
input [63 : 0] S_AXI_HP0_WDATA;
input [7 : 0] S_AXI_HP0_WSTRB;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(1),
.C_FCLK_CLK0_FREQ(100),
.C_FCLK_CLK1_FREQ(142),
.C_FCLK_CLK2_FREQ(50),
.C_FCLK_CLK3_FREQ(50)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule |
module bsg_cache_non_blocking_dma
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
, parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
, parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p)
, parameter byte_sel_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, parameter tag_width_lp=(addr_width_p-lg_sets_lp-lg_block_size_in_words_lp-byte_sel_width_lp)
, parameter dma_cmd_width_lp=`bsg_cache_non_blocking_dma_cmd_width(ways_p,sets_p,tag_width_lp)
, parameter dma_pkt_width_lp=`bsg_cache_non_blocking_dma_pkt_width(addr_width_p)
, parameter data_mem_pkt_width_lp=
`bsg_cache_non_blocking_data_mem_pkt_width(ways_p,sets_p,block_size_in_words_p,data_width_p)
)
(
input clk_i
, input reset_i
// MHU
, input [dma_cmd_width_lp-1:0] dma_cmd_i
, input dma_cmd_v_i
, output logic [dma_cmd_width_lp-1:0] dma_cmd_return_o
, output logic done_o
, output logic pending_o
, input ack_i
, output logic [lg_ways_lp-1:0] curr_dma_way_id_o
, output logic [lg_sets_lp-1:0] curr_dma_index_o
, output logic curr_dma_v_o
// data_mem
, output logic data_mem_pkt_v_o
, output logic [data_mem_pkt_width_lp-1:0] data_mem_pkt_o
, input [data_width_p-1:0] data_mem_data_i
// DMA request
, output logic [dma_pkt_width_lp-1:0] dma_pkt_o
, output logic dma_pkt_v_o
, input dma_pkt_yumi_i
// DMA data in
, input [data_width_p-1:0] dma_data_i
, input dma_data_v_i
, output logic dma_data_ready_o
// DMA data out
, output logic [data_width_p-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_yumi_i
);
// localparam
//
localparam counter_width_lp=`BSG_SAFE_CLOG2(block_size_in_words_p+1);
localparam block_offset_width_lp=byte_sel_width_lp+lg_block_size_in_words_lp;
localparam data_mask_width_lp=(data_width_p>>3);
// casting structs
//
`declare_bsg_cache_non_blocking_dma_cmd_s(ways_p,sets_p,tag_width_lp);
`declare_bsg_cache_non_blocking_dma_pkt_s(addr_width_p);
bsg_cache_non_blocking_dma_cmd_s dma_cmd_in;
bsg_cache_non_blocking_dma_cmd_s dma_cmd_r;
bsg_cache_non_blocking_dma_pkt_s dma_pkt;
assign dma_cmd_in = dma_cmd_i;
assign dma_cmd_return_o = dma_cmd_r;
assign dma_pkt_o = dma_pkt;
`declare_bsg_cache_non_blocking_data_mem_pkt_s(ways_p,sets_p,block_size_in_words_p,data_width_p);
bsg_cache_non_blocking_data_mem_pkt_s data_mem_pkt;
assign data_mem_pkt_o = data_mem_pkt;
// data_cmd dff
//
logic dma_cmd_dff_en;
bsg_dff_reset_en #(
.width_p(dma_cmd_width_lp)
) dma_cmd_dff (
.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(dma_cmd_dff_en)
,.data_i(dma_cmd_in)
,.data_o(dma_cmd_r)
);
// dma states
//
typedef enum logic [2:0] {
DMA_IDLE
,SEND_REFILL_ADDR
,SEND_EVICT_ADDR
,SEND_EVICT_DATA
,RECV_REFILL_DATA
,DMA_DONE
} dma_state_e;
dma_state_e dma_state_r;
dma_state_e dma_state_n;
// dma counter
//
logic counter_clear;
logic counter_up;
logic [counter_width_lp-1:0] counter_r;
bsg_counter_clear_up #(
.max_val_p(block_size_in_words_p)
,.init_val_p(0)
) dma_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(counter_clear)
,.up_i(counter_up)
,.count_o(counter_r)
);
logic counter_fill_max;
logic counter_evict_max;
assign counter_fill_max = counter_r == (block_size_in_words_p-1);
assign counter_evict_max = counter_r == block_size_in_words_p;
// in fifo
//
logic in_fifo_v_lo;
logic [data_width_p-1:0] in_fifo_data_lo;
logic in_fifo_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(data_width_p)
,.els_p(block_size_in_words_p)
) in_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_data_i)
,.v_i(dma_data_v_i)
,.ready_o(dma_data_ready_o)
,.data_o(in_fifo_data_lo)
,.v_o(in_fifo_v_lo)
,.yumi_i(in_fifo_yumi_li)
);
// out fifo
//
logic out_fifo_v_li;
logic out_fifo_ready_lo;
logic [data_width_p-1:0] out_fifo_data_li;
bsg_two_fifo #(
.width_p(data_width_p)
) out_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(out_fifo_v_li)
,.data_i(out_fifo_data_li)
,.ready_o(out_fifo_ready_lo)
,.v_o(dma_data_v_o)
,.data_o(dma_data_o)
,.yumi_i(dma_data_yumi_i)
);
// comb logic
//
assign out_fifo_data_li = data_mem_data_i;
logic [addr_width_p-1:0] dma_pkt_refill_addr;
logic [addr_width_p-1:0] dma_pkt_evict_addr;
assign dma_pkt_refill_addr = {
dma_cmd_r.refill_tag,
dma_cmd_r.index,
{block_offset_width_lp{1'b0}}
};
assign dma_pkt_evict_addr = {
dma_cmd_r.evict_tag,
dma_cmd_r.index,
{block_offset_width_lp{1'b0}}
};
always_comb begin
done_o = 1'b0;
pending_o = 1'b0;
dma_cmd_dff_en = 1'b0;
counter_clear = 1'b0;
counter_up = 1'b0;
out_fifo_v_li = 1'b0;
in_fifo_yumi_li = 1'b0;
data_mem_pkt_v_o = 1'b0;
data_mem_pkt.write_not_read = 1'b0;
data_mem_pkt.way_id = dma_cmd_r.way_id;
data_mem_pkt.addr = {
dma_cmd_r.index,
counter_r[0+:lg_block_size_in_words_lp]
};
// for load
data_mem_pkt.sigext_op = 1'b0;
data_mem_pkt.size_op = (2)'($clog2(data_width_p>>3));
data_mem_pkt.byte_sel = (byte_sel_width_lp)'(0);
// for store
data_mem_pkt.mask_op = 1'b1;
data_mem_pkt.mask = {data_mask_width_lp{1'b1}};
data_mem_pkt.data = in_fifo_data_lo;
dma_pkt_v_o = 1'b0;
dma_pkt.write_not_read = 1'b0;
dma_pkt.addr = dma_pkt_refill_addr;
case (dma_state_r)
// Wait for dma_cmd from MHU.
DMA_IDLE: begin
dma_cmd_dff_en = dma_cmd_v_i;
dma_state_n = dma_cmd_v_i
? (dma_cmd_in.refill ? SEND_REFILL_ADDR : SEND_EVICT_ADDR)
: DMA_IDLE;
end
// Send refill address by dma_req channel.
SEND_REFILL_ADDR: begin
dma_pkt_v_o = 1'b1;
dma_pkt.write_not_read = 1'b0;
dma_pkt.addr = dma_pkt_refill_addr;
pending_o = 1'b1;
dma_state_n = dma_pkt_yumi_i
? (dma_cmd_r.evict ? SEND_EVICT_ADDR : RECV_REFILL_DATA)
: SEND_REFILL_ADDR;
end
// Send evict address by dma_req channel.
SEND_EVICT_ADDR: begin
data_mem_pkt_v_o = dma_pkt_yumi_i; // read the first word in block.
counter_up = dma_pkt_yumi_i;
counter_clear = dma_pkt_yumi_i;
dma_pkt_v_o = 1'b1;
dma_pkt.write_not_read = 1'b1;
dma_pkt.addr = dma_pkt_evict_addr;
pending_o = 1'b1;
dma_state_n = dma_pkt_yumi_i
? SEND_EVICT_DATA
: SEND_EVICT_ADDR;
end
// Read the cache block word by word, send it out by dma_data_o channel.
SEND_EVICT_DATA: begin
data_mem_pkt_v_o = out_fifo_ready_lo & ~counter_evict_max;
out_fifo_v_li = 1'b1;
counter_up = out_fifo_ready_lo & ~counter_evict_max;
counter_clear = out_fifo_ready_lo & counter_evict_max;
pending_o = 1'b1;
dma_state_n = (out_fifo_ready_lo & counter_evict_max)
? (dma_cmd_r.refill ? RECV_REFILL_DATA : DMA_DONE)
: SEND_EVICT_DATA;
end
// Receive the cache block word by word from dma_data_i channel,
// and write it to data_mem.
RECV_REFILL_DATA: begin
data_mem_pkt_v_o = in_fifo_v_lo;
data_mem_pkt.write_not_read = 1'b1;
in_fifo_yumi_li = in_fifo_v_lo;
counter_up = in_fifo_v_lo & ~counter_fill_max;
counter_clear = in_fifo_v_lo & counter_fill_max;
pending_o = 1'b1;
dma_state_n = in_fifo_v_lo & counter_fill_max
? DMA_DONE
: RECV_REFILL_DATA;
end
// DMA transaction is over, and wait for MHU to acknowledge it.
DMA_DONE: begin
done_o = 1'b1;
counter_clear = ack_i;
dma_state_n = ack_i
? DMA_IDLE
: DMA_DONE;
end
// this should never happen, but if it does, return to IDLE.
default: begin
dma_state_n = DMA_IDLE;
end
endcase
end
assign curr_dma_v_o = (dma_state_r != DMA_IDLE);
assign curr_dma_way_id_o = dma_cmd_r.way_id;
assign curr_dma_index_o = dma_cmd_r.index;
// synopsys sync_set_reset "reset_i"
always_ff @ (posedge clk_i) begin
if (reset_i) begin
dma_state_r <= DMA_IDLE;
end
else begin
dma_state_r <= dma_state_n;
end
end
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam [ 0:0] one1_lp = 1;
localparam [ 1:0] one2_lp = 1;
localparam [ 2:0] one3_lp = 1;
localparam [ 3:0] one4_lp = 1;
localparam [ 4:0] one5_lp = 1;
localparam [ 5:0] one6_lp = 1;
localparam [ 6:0] one7_lp = 1;
localparam [ 7:0] one8_lp = 1;
localparam [ 8:0] one9_lp = 1;
localparam [ 9:0] one10_lp = 1;
localparam [19:0] one20_lp = 1;
localparam [29:0] one30_lp = 1;
localparam [30:0] one31_lp = 1;
localparam [31:0] one32_lp = 1;
localparam [32:0] one33_lp = 1;
localparam [33:0] one34_lp = 1;
localparam [34:0] one35_lp = 1;
localparam [35:0] one36_lp = 1;
localparam [36:0] one37_lp = 1;
localparam [37:0] one38_lp = 1;
localparam [38:0] one39_lp = 1;
localparam [39:0] one40_lp = 1;
localparam [49:0] one50_lp = 1;
localparam [59:0] one60_lp = 1;
localparam [60:0] one61_lp = 1;
localparam [61:0] one62_lp = 1;
localparam [62:0] one63_lp = 1;
localparam [63:0] one64_lp = 1;
localparam [64:0] one65_lp = 1;
localparam [65:0] one66_lp = 1;
localparam [66:0] one67_lp = 1;
localparam [67:0] one68_lp = 1;
localparam [68:0] one69_lp = 1;
localparam [69:0] one70_lp = 1;
bit all_ok = 1;
initial begin
`ifdef TEST_VERBOSE
$display("one1_lp : %x %d", one1_lp, one1_lp==1);
$display("one2_lp : %x %d", one2_lp, one2_lp==1);
$display("one3_lp : %x %d", one3_lp, one3_lp==1);
$display("one4_lp : %x %d", one4_lp, one4_lp==1);
$display("one5_lp : %x %d", one5_lp, one5_lp==1);
$display("one6_lp : %x %d", one6_lp, one6_lp==1);
$display("one7_lp : %x %d", one7_lp, one7_lp==1);
$display("one8_lp : %x %d", one8_lp, one8_lp==1);
$display("one9_lp : %x %d", one9_lp, one9_lp==1);
$display("one10_lp: %x %d", one10_lp, one10_lp==1);
$display("one20_lp: %x %d", one20_lp, one20_lp==1);
$display("one30_lp: %x %d", one30_lp, one30_lp==1);
$display("one31_lp: %x %d", one31_lp, one31_lp==1);
$display("one32_lp: %x %d", one32_lp, one32_lp==1);
$display("one33_lp: %x %d", one33_lp, one33_lp==1);
$display("one34_lp: %x %d", one34_lp, one34_lp==1);
$display("one35_lp: %x %d", one35_lp, one35_lp==1);
$display("one36_lp: %x %d", one36_lp, one36_lp==1);
$display("one37_lp: %x %d", one37_lp, one37_lp==1);
$display("one38_lp: %x %d", one38_lp, one38_lp==1);
$display("one39_lp: %x %d", one39_lp, one39_lp==1);
$display("one40_lp: %x %d", one40_lp, one40_lp==1);
$display("one50_lp: %x %d", one50_lp, one50_lp==1);
$display("one60_lp: %x %d", one60_lp, one60_lp==1);
$display("one61_lp: %x %d", one61_lp, one61_lp==1);
$display("one62_lp: %x %d", one62_lp, one62_lp==1);
$display("one63_lp: %x %d", one63_lp, one63_lp==1);
$display("one64_lp: %x %d", one64_lp, one64_lp==1);
$display("one65_lp: %x %d", one65_lp, one65_lp==1);
$display("one66_lp: %x %d", one66_lp, one66_lp==1);
$display("one67_lp: %x %d", one67_lp, one67_lp==1);
$display("one68_lp: %x %d", one68_lp, one68_lp==1);
$display("one69_lp: %x %d", one69_lp, one69_lp==1);
$display("one70_lp: %x %d", one70_lp, one70_lp==1);
`endif
all_ok &= one1_lp == 1;
all_ok &= one2_lp == 1;
all_ok &= one3_lp == 1;
all_ok &= one4_lp == 1;
all_ok &= one5_lp == 1;
all_ok &= one6_lp == 1;
all_ok &= one7_lp == 1;
all_ok &= one8_lp == 1;
all_ok &= one9_lp == 1;
all_ok &= one10_lp == 1;
all_ok &= one20_lp == 1;
all_ok &= one30_lp == 1;
all_ok &= one31_lp == 1;
all_ok &= one32_lp == 1;
all_ok &= one33_lp == 1;
all_ok &= one34_lp == 1;
all_ok &= one35_lp == 1;
all_ok &= one36_lp == 1;
all_ok &= one37_lp == 1;
all_ok &= one38_lp == 1;
all_ok &= one39_lp == 1;
all_ok &= one40_lp == 1;
all_ok &= one50_lp == 1;
all_ok &= one60_lp == 1;
all_ok &= one61_lp == 1;
all_ok &= one62_lp == 1;
all_ok &= one63_lp == 1;
all_ok &= one64_lp == 1;
all_ok &= one65_lp == 1;
all_ok &= one66_lp == 1;
all_ok &= one67_lp == 1;
all_ok &= one68_lp == 1;
all_ok &= one69_lp == 1;
all_ok &= one70_lp == 1;
if (!all_ok) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule |
module th44w3 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th44w3";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N6 ( .d(net042), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net042), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net32), .g(y), .s(net042), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net042), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net042), .b(cds_globals.gnd_));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net027), .d(net34));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net49), .d(net32));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net027));
pfet_b P3 ( .b(cds_globals.vdd_), .g(d), .s(net47), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net027));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule |
module dex_smblt
(
input de_clk,
input de_rstn,
input [1:0] dir,
input goblt,
input stpl_pk_1,
input mcrdy,
input cache_rdy,
input signx,
input signy,
input yeqz,
input xeqz,
input read_2,
input ps16_1,
input ps32_1,
input ps8_2,
input ps16_2,
input ps32_2,
input apat8_2,
input apat32_2,
input frst_pass,
input last_pass,
input multi,
input soc,
input rmw,
input eor,
input local_sol,
input frst8_1,
input mw_fip,
input eol_2,
input end_pass,
output reg [21:0] b_op,
output reg [4:0] b_ksel,
output reg b_set_busy,
output reg b_clr_busy,
output reg b_mem_req,
output reg b_mem_rd,
output reg b_ld_wcnt,
output reg b_dchgy,
output reg b_rstn_wad,
output reg b_ld_rad,
output reg b_set_sol,
output reg b_set_eol,
output reg b_set_eor,
output reg b_ld_msk,
output reg b_mul,
output reg b_mod8,
output reg b_mod32,
output reg b_rst_cr,
output reg b_set_soc,
output reg b_clr_soc,
output reg b_set_multi,
output reg b_clr_multi,
output reg b_set_frst_pass,
output reg b_clr_frst_pass,
output reg b_set_end,
output reg b_clr_end,
output reg b_set_last_pass,
output reg b_clr_last_pass,
output reg b_clr_ld_disab,
output reg b_cin,
output b_sdwn,
output b_ddwn
);
// The following are from de_param.h
//`include "de_param.h"
parameter one = 5'h1,
B_WAIT = 5'h0,
BS1 = 5'h1,
BS2 = 5'h2,
BS3 = 5'h3,
BS4 = 5'h4,
BS5 = 5'h5,
BS6 = 5'h6,
BS7 = 5'h7,
BS8 = 5'h8,
BS9 = 5'h9,
BS10 = 5'ha,
BS11 = 5'hb,
BS12 = 5'hc,
BS13 = 5'hd,
BR1 = 5'he,
BR2 = 5'hf,
BR3 = 5'h10,
BR4 = 5'h11,
BR5 = 5'h12,
BW1 = 5'h13,
BW2 = 5'h14,
BW3 = 5'h15,
BW4 = 5'h16,
BW5 = 5'h17,
BW6 = 5'h18,
BNL1 = 5'h19,
BNL2 = 5'h1a,
BNL3 = 5'h1b,
BNL4 = 5'h1c,
BNL5 = 5'h1d,
BNL6 = 5'h1e,
BNL7 = 5'h1f,
size = 5'h2, // wrk0x and wrk0y
wr_seg = 5'hd, // wrk7x
noop = 5'h0, // noop address.
pline = 5'h10,// pipeline address.
sorgl = 5'he, // src org address low nibble.
dorgl = 5'hf, // src org address low nibble.
amcn = 5'h4, // ax-k, ay-k
apcn_d = 5'h8, // {ax + const,ax + const}
amcn_d = 5'h14,// {ax - const,ax - const}
sub_d = 5'h17,// {ax - bx,ax - bx}
wrhl = 2'b00,// define write enables
wrhi = 2'b01,
wrlo = 2'b10,// define write enables
wrno = 2'b11,// define write enables
D24 = 5'hd, // not used
D48 = 5'he, // not used
D95 = 5'h10,
D94 = 5'h12,
D96 = 5'h13,
dst = 5'h1, // destination/end point
add = 5'h1, // ax + bx, ay + by
sub = 5'h12,// ax - bx, ay - by
addnib = 5'h2, // ax + bx(nibble)
movx = 5'hf, // bx--> fy, by--> fx
dst_sav = 5'h9, // dst & wrk1y
src = 5'h0, // source/start point register
src_sav = 5'ha, // src & wrk1x
mov = 5'hd, // bx--> fx, by--> fy
mov_k = 5'he, // move constant
rd_wrds = 5'h5, // wrk3x
rd_wrds_sav = 5'hb, // wrk3x & wrk5x
wr_wrds_sav = 5'hc, // wrk4x & wrk6x
div16 = 5'ha, // bx/16 + wadj.
two = 5'h2,
four = 5'h4,
eight = 5'h6,
movmod = 5'h5, // ay + by mod 8 or 32
adr_ofs = 5'h5,
mod_src = 5'h6,
apcn = 5'h6, // ax+k, ay+k
zoom = 5'h4, // wrk2x & wrk2y
nib = 5'h11,// nibble
sav_yzoom = 5'h5, // wrk3y
wr_wrds = 5'h6, // wrk4x
D16 = 5'h8,
seven = 5'h5,
D64 = 5'h11,
D112 = 5'h14,
D128 = 5'h15,
D256 = 5'h7,
sav_rd_wrds = 5'h7, // wrk5x
sav_wr_wrds = 5'h8, // wrk6x
sav_src_dst = 5'h3; // wrk1x & wrk1y
/****************************************************************/
/* DEFINE PARAMETERS */
/****************************************************************/
/* define internal wires and make assignments */
reg [4:0] b_cs;
reg [4:0] b_ns;
assign b_sdwn = ~dir[0];
assign b_ddwn = ~dir[0];
/* create the state register */
always @(posedge de_clk or negedge de_rstn) begin
if(!de_rstn) b_cs <= 5'b0;
else b_cs <= b_ns;
end
always @*
begin
b_op = 22'b00000_00000_00000_00000_11;
b_ksel = one;
b_set_busy = 1'b0;
b_clr_busy = 1'b0;
b_ld_wcnt = 1'b0;
b_mem_req = 1'b0;
b_mem_rd = 1'b0;
b_dchgy = 1'b0;
b_rstn_wad = 1'b0;
b_ld_rad = 1'b0;
b_set_sol = 1'b0;
b_set_eol = 1'b0;
b_mem_req = 1'b0;
b_mem_rd = 1'b0;
b_set_eor = 1'b0;
b_ld_msk = 1'b0;
b_mul = 1'b0;
b_mod32 = 1'b0;
b_mod8 = 1'b0;
b_rst_cr = 1'b0;
b_set_soc = 1'b0;
b_clr_soc = 1'b0;
b_set_multi = 1'b0;
b_clr_multi = 1'b0;
b_set_frst_pass = 1'b0;
b_clr_frst_pass = 1'b0;
b_set_end = 1'b0;
b_clr_end = 1'b0;
b_set_last_pass = 1'b0;
b_clr_last_pass = 1'b0;
b_clr_ld_disab = 1'b0;
b_cin = 1'b0;
case(b_cs) /* synopsys full_case parallel_case */
/* Wait for goblt. */
B_WAIT: if(goblt && !stpl_pk_1)
begin
b_ns=BS1;
b_set_busy = 1'b1;
b_set_frst_pass = 1'b1;
b_mul = 1'b1;
b_op={size,noop,amcn,noop,wrno};
if(ps32_1)b_ksel=D24;
else if(ps16_1)b_ksel=D48;
else b_ksel=D96;
end
else b_ns= B_WAIT;
/* multiply the src, dst, and size by 2 for 16BPP, or 4 for 32BPP. */
/* add org low nibble to destination point */
/* save the original destination X, to use on the next scan line. */
BS1: begin
if(frst_pass)
begin
// b_op={dst,noop,apcn_d,dst_sav,wrhl};
b_op={dorgl,dst,addnib,dst_sav,wrhl};
if(read_2)b_cin = 1'b1;
end
else b_op={wr_seg,noop,movx,size,wrlo};
if(!read_2)b_ns=BS5;
else b_ns=BS2;
b_set_sol=1'b1;
b_set_soc=1'b1;
b_clr_ld_disab = 1'b1;
// if(ps32_2) b_ksel=four;
// else if(ps16_2)b_ksel=two;
// else b_ksel=one;
end
BS2: begin
if(!read_2)b_ns=BS5;
else b_ns=BS3;
if(dir[1] & !signx & !xeqz)
begin
b_set_multi = 1'b1;
if(frst_pass)b_op={pline,noop,amcn_d,dst_sav,wrhl};
else b_op={dst,noop,amcn_d,dst_sav,wrhl};
end
else if (dir[1])
begin
b_set_last_pass = 1'b1;
if(frst_pass) b_op={pline,size,sub_d,dst_sav,wrhl};
else b_op={dst,size,sub_d,dst_sav,wrhl};
end
else b_op={pline,noop,amcn_d,dst_sav,wrhl};
if (dir[1] & frst_pass & ps32_2)b_ksel=D94;
else if(dir[1] & frst_pass & ps16_2)b_ksel=D95;
// if (dir[1] & frst_pass & ps32_2)b_ksel=D95;
// else if(dir[1] & frst_pass & ps16_2)b_ksel=D96;
else if(dir[1]) b_ksel=D96;
else b_ksel=one;
end
/* add org low nibble to source point */
/* save the original source X, to use on the next scan line. */
BS3: begin
if(frst_pass)
begin
b_op={sorgl,src,add,src_sav,wrhi};
b_cin = 1'b1;
// b_op={src,noop,apcn_d,dst_sav,wrhl};
end
// if(ps32_2) b_ksel=four;
// else if(ps16_2)b_ksel=two;
// else b_ksel=one;
b_ns=BS4;
end
BS4: begin
b_ns=BS5;
if (multi & frst_pass & !last_pass) b_op={pline,noop,amcn,src_sav,wrhi};
else if(multi & !frst_pass & !last_pass) b_op={src,noop,amcn,src_sav,wrhi};
else if(multi & frst_pass & last_pass) b_op={pline,size,sub,src_sav,wrhi};
else if(multi & !frst_pass & last_pass) b_op={src,size,sub,src_sav,wrhi};
else if(dir[1]) b_op={pline,size,sub,src_sav,wrhi};
else b_op={pline,noop,amcn,src_sav,wrhi};
if (dir[1] & frst_pass & ps32_2)b_ksel=D94;
else if(dir[1] & frst_pass & ps16_2)b_ksel=D95;
// if (dir[1] & frst_pass & ps32_2)b_ksel=D95;
// else if(dir[1] & frst_pass & ps16_2)b_ksel=D96;
else if(dir[1]) b_ksel=D96;
else b_ksel=one;
end
/* calculate the read words per line adjusted X size. */
BS5: begin
if(apat32_2 | apat8_2 | (multi & ~last_pass))b_ns=BS6;
else b_ns=BS8;
if(apat32_2 | apat8_2)b_op={noop,noop,mov_k,rd_wrds_sav,wrhi};
else if(multi & ~last_pass)b_op={size,noop,amcn,size,wrhi};
else b_op={pline,size,div16,rd_wrds_sav,wrhi};
if(multi)b_ksel=D96;
if(ps32_2 & apat32_2 & ~multi)b_ksel=eight;
if(ps16_2 & apat32_2 & ~multi)b_ksel=four;
if(ps8_2 & apat32_2 & ~multi) b_ksel=two;
if(ps32_2 & apat8_2 & ~multi)b_ksel=two;
if((ps16_2 | ps8_2) & apat8_2 & ~multi)b_ksel=one;
end
/* Calculate the offset between the source and destination. */
/* this code is exicuted for area patterns only.*/
BS6: begin
b_ns=BS7;
if(apat32_2)b_mod32 = 1'b1;
if(apat8_2)b_mod8 = 1'b1;
if(multi)b_op={noop,noop,mov_k,noop,wrno};
else b_op={noop,src,movmod,adr_ofs,wrlo};
b_ksel=D96;
end
/* this code is exicuted for area patterns only.*/
/* clear the lower 3 or 5 bits of the Y source.*/
BS7: begin
b_ns=BS8;
if(multi)b_op={src,pline,div16,rd_wrds_sav,wrhi};
else b_op={src,src,sub,mod_src,wrno};
if(apat32_2)b_mod32 = 1'b1;
if(apat8_2)b_mod8 = 1'b1;
end
/* this code is exicuted for area patterns only.*/
/* add the source offset to the source. */
BS8: begin
b_ns=BS9;
if(multi & ~last_pass)b_op={noop,noop,mov_k,noop,wrno};
else b_op={pline,dst,add,mod_src,wrlo};
if(apat32_2)b_mod32 = 1'b1;
if(apat8_2)b_mod8 = 1'b1;
b_ksel=D96;
end
/* calculate the write words per line adjusted X size. */
BS9: begin
b_ns=BS10;
if(multi & ~last_pass)b_op={dst,pline,div16,wr_wrds_sav,wrhi};
else b_op={dst,size,div16,wr_wrds_sav,wrhi};
end
/* generate the start and end mask to be loaded in BS10. */
BS10: begin
b_ns=BS11;
if(!dir[1] | last_pass)b_op={dst,size,add,noop,wrno};
else b_op={dst,size,apcn,noop,wrno};
b_rstn_wad = 1'b1;
b_ksel=D96;
end
BS11: begin
b_ld_msk=1'b1; /* load the mask. */
b_ns=BS12;
if(multi)b_op={noop,src,mov,zoom,wrlo};
end
/* source minus destination nibble mode. for FIFO ADDRESS read = write, read = write-1. */
/* this will set the first read 8 flag if source nibble is less than destination nibble.*/
BS12: begin
if(mcrdy) begin
b_ns=BS13;
b_ld_rad = 1'b1;
if(apat32_2 || apat8_2)b_op={mod_src,adr_ofs,add,src,wrlo};
else b_op={src,dst,nib,noop,wrno};
end
else b_ns=BS12;
end
BS13: begin
b_ns=BR1;
if(multi && soc)b_op={noop,dst,mov,sav_yzoom,wrlo};
b_clr_soc = 1'b1;
end
/* write words minus max page count of eight for no reads. */
/* or seven for commands with reads. */
BR1: begin
if(!read_2)
begin
b_ns=BW3;
b_op={wr_wrds,noop,amcn,noop,wrno};
if(!rmw)b_ksel=eight;
else b_ksel=four;
end
else if(eor && (apat32_2 || apat8_2))
begin
b_ns=BW3;
b_op={wr_wrds,noop,amcn,noop,wrno};
if(!rmw)b_ksel=eight;
else b_ksel=four;
end
else if(eor)
begin
b_ns=BW3;
b_ksel=seven;
b_op={wr_wrds,noop,amcn,noop,wrno};
end
else if(frst_pass)
begin
b_ns=BR2;
b_op={noop,size,movx,wr_seg,wrhi};
end
else b_ns=BR2;
b_clr_frst_pass = 1'b1;
end
/* read words minus max page count of eight reads. */
BR2: begin
b_op={rd_wrds,noop,amcn,noop,wrno};
b_ns=BR3;
if((local_sol & !frst8_1) | apat32_2 | apat8_2)b_ksel=eight;
else b_ksel=seven;
end
/* wait for the pipeline. */
/* subtract 7 or 8 from the read words. */
BR3: begin
b_ns=BR4;
b_op={rd_wrds,noop,amcn,rd_wrds,wrhi};
if((local_sol & !frst8_1) | apat32_2 | apat8_2)b_ksel=eight;
else b_ksel=seven;
end
BR4: begin
b_ld_wcnt=1'b1; /* this signal is externally delayed one clock. */
if(signx || xeqz) b_op={noop,rd_wrds,mov,noop,wrno};
if(!signx && !xeqz)b_op={noop,noop,mov_k,noop,wrno};
if(local_sol & !frst8_1)b_ksel=eight;
else b_ksel=seven;
b_ns=BR5;
end
BR5: begin
if(signx | xeqz) b_set_eor=1'b1;
b_ns=BW1;
end
/* Begin the write portion of the bit blt state machine. */
/* read words minus max page count of eight reads. */
BW1: if(mcrdy && !mw_fip)
begin
b_op={wr_wrds,noop,amcn,noop,wrno};
if(read_2 && apat32_2 && (ps8_2 || ps16_2))b_ns=BW2;
else if(read_2 && apat8_2)b_ns=BW2;
else b_ns=BW3;
if(read_2)begin
b_mem_req=1'b1;
b_mem_rd=1'b1;
end
if(read_2 && !(apat32_2 || apat8_2)) b_ksel=seven;
else if(!rmw)b_ksel=eight;
else b_ksel=four;
end
else b_ns=BW1;
BW2: if(mcrdy && !mw_fip)
begin
b_op={wr_wrds,noop,amcn,noop,wrno};
b_ns=BW3;
b_mem_req=1'b1;
b_mem_rd=1'b1;
if(read_2 && !(apat32_2 || apat8_2)) b_ksel=seven;
else if(!rmw)b_ksel=eight;
else b_ksel=four;
end
else b_ns=BW2;
/* add 128 or 112 to the source x pointer. */
BW3: begin
b_ns=BW4;
if(local_sol & !frst8_1)b_ksel=D128;
else b_ksel=D112;
if(!apat32_2)b_op={src,noop,apcn,src,wrhi};
end
/* test to see which is less and use that one. */
/* and wait if memory controller is busy. */
BW4: begin
b_ns=BW5;
if(read_2 && !(apat32_2 || apat8_2))b_ksel=seven;
else if(rmw)b_ksel=four;
else b_ksel=eight;
b_ld_wcnt=1'b1;
if(signx | xeqz)
begin
b_op={noop,wr_wrds,mov,noop,wrno};
b_set_eol=1'b1;
end
else begin
b_op={noop,noop,mov_k,noop,wrno};
end
end
/* subtract 7 from the write words. */
BW5: begin
b_ns=BW6;
b_op={wr_wrds,noop,amcn,wr_wrds,wrhi};
if(read_2 && !(apat32_2 || apat8_2))b_ksel=seven;
else if(rmw)b_ksel=four;
else b_ksel=eight;
end
/* add 128 to the destination x pointer. */
BW6: begin
if(mcrdy && !eol_2 && cache_rdy)
begin
b_mem_req=1'b1;
b_ns=BR1;
b_op={dst,noop,apcn,dst,wrhi};
if(read_2 && !(apat32_2 || apat8_2))b_ksel=D112;
else if(rmw)b_ksel=D64;
else b_ksel=D128;
end
else if(mcrdy && eol_2 && cache_rdy) /* decrement the Y size register. */
begin
b_mem_req=1'b1;
b_ns=BNL1;
b_op={size,noop,amcn,size,wrlo};
end
else b_ns=BW6;
end
/* restore the write words per line. */
BNL1: begin
b_dchgy = 1'b1;
b_op={noop,sav_wr_wrds,mov,wr_wrds,wrhi};
b_ns=BNL2;
end
/* If Y size register goes to zero the bit blt is all done. */
/* else go back and read more data. */
/* Restore the original X destination registers. */
BNL2: begin
if(yeqz & multi & ~last_pass)
begin
b_rst_cr = 1'b1;
b_ns=BNL4;
b_op={noop,sav_yzoom,mov,dst,wrlo}; // restore dst Y
b_set_end = 1'b1;
end
else if(yeqz)
begin
b_clr_last_pass = 1'b1;
b_clr_multi = 1'b1;
b_rst_cr = 1'b1;
b_clr_busy = 1'b1;
b_ns=B_WAIT;
end
else begin
if(read_2 && (apat32_2 || apat8_2))b_ns=BNL4;
else if(read_2)b_ns=BNL3;
else b_ns=BS13;
b_set_sol=1'b1;
b_op={noop,sav_src_dst,movx,dst,wrhi}; // restore dst Y
end
end
/* Increment or decrement the source Y registers. */
BNL3: begin
b_ns=BNL6;
if(dir[0])b_op={src,noop,amcn,src,wrlo};
else b_op={src,noop,apcn,src,wrlo};
end
/* increment the modulo source Y counter. */
BNL4: begin
b_ns=BNL5;
b_ksel=one;
// b_rstn_wad=1'b1;
if(apat32_2)b_mod32 = 1'b1;
if(apat8_2)b_mod8 = 1'b1;
if(multi)b_op={noop,zoom,mov,src,wrlo}; // restore src Y
else b_op={mod_src,noop,apcn,mod_src,wrlo};
end
/* add the source Y offset to the source Y. */
BNL5: begin
if(multi)
begin
b_op={noop,sav_src_dst,movx,dst,wrhi}; // restore dstx
b_ns=BNL6;
end
else
begin
b_op={pline,adr_ofs,add,src,wrlo};
b_ns=BNL6;
end
end
/* Restore the original X source registers. */
BNL6: begin
b_op={noop,sav_src_dst,mov,src,wrhi};
b_ns=BNL7;
end
/* restore the read words per line. */
BNL7: begin
if(multi & end_pass)
begin
b_op={size,noop,amcn,noop,wrno};
b_ns=BS1;
b_clr_end = 1'b1;
end
else begin
b_op={noop,sav_rd_wrds,mov,rd_wrds,wrhi};
b_ns=BS13;
end
b_ksel=D96;
end
endcase
end
endmodule |
module cpx_buf_p3(/*AUTOARG*/
// Outputs
scache3_cpx_req_bufp3_cq, scache3_cpx_atom_bufp3_cq,
io_cpx_req_bufp3_cq, cpx_scache3_grant_bufp3_ca_l,
cpx_spc5_data_rdy_bufp3_cx, cpx_spc6_data_rdy_bufp3_cx,
cpx_spc7_data_rdy_bufp3_cx, arbcp0_cpxdp_grant_bufp3_ca_l_5,
arbcp0_cpxdp_q0_hold_bufp3_ca_5, arbcp0_cpxdp_qsel0_bufp3_ca_l_5,
arbcp0_cpxdp_qsel1_bufp3_ca_5, arbcp0_cpxdp_shift_bufp3_cx_l_5,
arbcp1_cpxdp_grant_bufp3_ca_l_5, arbcp1_cpxdp_q0_hold_bufp3_ca_5,
arbcp1_cpxdp_qsel0_bufp3_ca_l_5, arbcp1_cpxdp_qsel1_bufp3_ca_5,
arbcp1_cpxdp_shift_bufp3_cx_l_5, arbcp2_cpxdp_grant_bufp3_ca_l_5,
arbcp2_cpxdp_q0_hold_bufp3_ca_5, arbcp2_cpxdp_qsel0_bufp3_ca_l_5,
arbcp2_cpxdp_qsel1_bufp3_ca_5, arbcp2_cpxdp_shift_bufp3_cx_l_5,
arbcp3_cpxdp_grant_bufp3_ca_l_5, arbcp3_cpxdp_q0_hold_bufp3_ca_5,
arbcp3_cpxdp_qsel0_bufp3_ca_l_5, arbcp3_cpxdp_qsel1_bufp3_ca_5,
arbcp3_cpxdp_shift_bufp3_cx_l_5, arbcp4_cpxdp_grant_bufp3_ca_l_5,
arbcp4_cpxdp_q0_hold_bufp3_ca_5, arbcp4_cpxdp_qsel0_bufp3_ca_l_5,
arbcp4_cpxdp_qsel1_bufp3_ca_5, arbcp4_cpxdp_shift_bufp3_cx_l_5,
arbcp5_cpxdp_grant_bufp3_ca_l_5, arbcp5_cpxdp_q0_hold_bufp3_ca_5,
arbcp5_cpxdp_qsel0_bufp3_ca_l_5, arbcp5_cpxdp_qsel1_bufp3_ca_5,
arbcp5_cpxdp_shift_bufp3_cx_l_5, arbcp6_cpxdp_grant_bufp3_ca_l_5,
arbcp6_cpxdp_q0_hold_bufp3_ca_5, arbcp6_cpxdp_qsel0_bufp3_ca_l_5,
arbcp6_cpxdp_qsel1_bufp3_ca_5, arbcp6_cpxdp_shift_bufp3_cx_l_5,
arbcp7_cpxdp_grant_bufp3_ca_l_5, arbcp7_cpxdp_q0_hold_bufp3_ca_5,
arbcp7_cpxdp_qsel0_bufp3_ca_l_5, arbcp7_cpxdp_qsel1_bufp3_ca_5,
arbcp7_cpxdp_shift_bufp3_cx_l_5, arbcp0_cpxdp_grant_bufp3_ca_l_2,
arbcp0_cpxdp_q0_hold_bufp3_ca_2, arbcp0_cpxdp_qsel0_bufp3_ca_l_2,
arbcp0_cpxdp_qsel1_bufp3_ca_2, arbcp0_cpxdp_shift_bufp3_cx_l_2,
arbcp1_cpxdp_grant_bufp3_ca_l_2, arbcp1_cpxdp_q0_hold_bufp3_ca_2,
arbcp1_cpxdp_qsel0_bufp3_ca_l_2, arbcp1_cpxdp_qsel1_bufp3_ca_2,
arbcp1_cpxdp_shift_bufp3_cx_l_2, arbcp2_cpxdp_grant_bufp3_ca_l_2,
arbcp2_cpxdp_q0_hold_bufp3_ca_2, arbcp2_cpxdp_qsel0_bufp3_ca_l_2,
arbcp2_cpxdp_qsel1_bufp3_ca_2, arbcp2_cpxdp_shift_bufp3_cx_l_2,
arbcp3_cpxdp_grant_bufp3_ca_l_2, arbcp3_cpxdp_q0_hold_bufp3_ca_2,
arbcp3_cpxdp_qsel0_bufp3_ca_l_2, arbcp3_cpxdp_qsel1_bufp3_ca_2,
arbcp3_cpxdp_shift_bufp3_cx_l_2, arbcp4_cpxdp_grant_bufp3_ca_l_2,
arbcp4_cpxdp_q0_hold_bufp3_ca_2, arbcp4_cpxdp_qsel0_bufp3_ca_l_2,
arbcp4_cpxdp_qsel1_bufp3_ca_2, arbcp4_cpxdp_shift_bufp3_cx_l_2,
arbcp5_cpxdp_grant_bufp3_ca_l_2, arbcp5_cpxdp_q0_hold_bufp3_ca_2,
arbcp5_cpxdp_qsel0_bufp3_ca_l_2, arbcp5_cpxdp_qsel1_bufp3_ca_2,
arbcp5_cpxdp_shift_bufp3_cx_l_2, arbcp6_cpxdp_grant_bufp3_ca_l_2,
arbcp6_cpxdp_q0_hold_bufp3_ca_2, arbcp6_cpxdp_qsel0_bufp3_ca_l_2,
arbcp6_cpxdp_qsel1_bufp3_ca_2, arbcp6_cpxdp_shift_bufp3_cx_l_2,
arbcp7_cpxdp_grant_bufp3_ca_l_2, arbcp7_cpxdp_q0_hold_bufp3_ca_2,
arbcp7_cpxdp_qsel0_bufp3_ca_l_2, arbcp7_cpxdp_qsel1_bufp3_ca_2,
arbcp7_cpxdp_shift_bufp3_cx_l_2,
// Inputs
scache3_cpx_req_bufp4_cq, scache3_cpx_atom_bufp4_cq,
io_cpx_req_bufp4_cq, cpx_scache3_grant_ca, cpx_spc5_data_rdy_cx,
cpx_spc6_data_rdy_cx, cpx_spc7_data_rdy_cx,
arbcp0_cpxdp_grant_arbbf_ca_5, arbcp0_cpxdp_q0_hold_arbbf_ca_l_5,
arbcp0_cpxdp_qsel0_arbbf_ca_5, arbcp0_cpxdp_qsel1_arbbf_ca_l_5,
arbcp0_cpxdp_shift_arbbf_cx_5, arbcp1_cpxdp_grant_arbbf_ca_5,
arbcp1_cpxdp_q0_hold_arbbf_ca_l_5, arbcp1_cpxdp_qsel0_arbbf_ca_5,
arbcp1_cpxdp_qsel1_arbbf_ca_l_5, arbcp1_cpxdp_shift_arbbf_cx_5,
arbcp2_cpxdp_grant_arbbf_ca_5, arbcp2_cpxdp_q0_hold_arbbf_ca_l_5,
arbcp2_cpxdp_qsel0_arbbf_ca_5, arbcp2_cpxdp_qsel1_arbbf_ca_l_5,
arbcp2_cpxdp_shift_arbbf_cx_5, arbcp3_cpxdp_grant_arbbf_ca_5,
arbcp3_cpxdp_q0_hold_arbbf_ca_l_5, arbcp3_cpxdp_qsel0_arbbf_ca_5,
arbcp3_cpxdp_qsel1_arbbf_ca_l_5, arbcp3_cpxdp_shift_arbbf_cx_5,
arbcp4_cpxdp_grant_arbbf_ca_5, arbcp4_cpxdp_q0_hold_arbbf_ca_l_5,
arbcp4_cpxdp_qsel0_arbbf_ca_5, arbcp4_cpxdp_qsel1_arbbf_ca_l_5,
arbcp4_cpxdp_shift_arbbf_cx_5, arbcp5_cpxdp_grant_arbbf_ca_5,
arbcp5_cpxdp_q0_hold_arbbf_ca_l_5, arbcp5_cpxdp_qsel0_arbbf_ca_5,
arbcp5_cpxdp_qsel1_arbbf_ca_l_5, arbcp5_cpxdp_shift_arbbf_cx_5,
arbcp6_cpxdp_grant_arbbf_ca_5, arbcp6_cpxdp_q0_hold_arbbf_ca_l_5,
arbcp6_cpxdp_qsel0_arbbf_ca_5, arbcp6_cpxdp_qsel1_arbbf_ca_l_5,
arbcp6_cpxdp_shift_arbbf_cx_5, arbcp7_cpxdp_grant_arbbf_ca_5,
arbcp7_cpxdp_q0_hold_arbbf_ca_l_5, arbcp7_cpxdp_qsel0_arbbf_ca_5,
arbcp7_cpxdp_qsel1_arbbf_ca_l_5, arbcp7_cpxdp_shift_arbbf_cx_5,
arbcp0_cpxdp_grant_arbbf_ca_2, arbcp0_cpxdp_q0_hold_arbbf_ca_l_2,
arbcp0_cpxdp_qsel0_arbbf_ca_2, arbcp0_cpxdp_qsel1_arbbf_ca_l_2,
arbcp0_cpxdp_shift_arbbf_cx_2, arbcp1_cpxdp_grant_arbbf_ca_2,
arbcp1_cpxdp_q0_hold_arbbf_ca_l_2, arbcp1_cpxdp_qsel0_arbbf_ca_2,
arbcp1_cpxdp_qsel1_arbbf_ca_l_2, arbcp1_cpxdp_shift_arbbf_cx_2,
arbcp2_cpxdp_grant_arbbf_ca_2, arbcp2_cpxdp_q0_hold_arbbf_ca_l_2,
arbcp2_cpxdp_qsel0_arbbf_ca_2, arbcp2_cpxdp_qsel1_arbbf_ca_l_2,
arbcp2_cpxdp_shift_arbbf_cx_2, arbcp3_cpxdp_grant_arbbf_ca_2,
arbcp3_cpxdp_q0_hold_arbbf_ca_l_2, arbcp3_cpxdp_qsel0_arbbf_ca_2,
arbcp3_cpxdp_qsel1_arbbf_ca_l_2, arbcp3_cpxdp_shift_arbbf_cx_2,
arbcp4_cpxdp_grant_arbbf_ca_2, arbcp4_cpxdp_q0_hold_arbbf_ca_l_2,
arbcp4_cpxdp_qsel0_arbbf_ca_2, arbcp4_cpxdp_qsel1_arbbf_ca_l_2,
arbcp4_cpxdp_shift_arbbf_cx_2, arbcp5_cpxdp_grant_arbbf_ca_2,
arbcp5_cpxdp_q0_hold_arbbf_ca_l_2, arbcp5_cpxdp_qsel0_arbbf_ca_2,
arbcp5_cpxdp_qsel1_arbbf_ca_l_2, arbcp5_cpxdp_shift_arbbf_cx_2,
arbcp6_cpxdp_grant_arbbf_ca_2, arbcp6_cpxdp_q0_hold_arbbf_ca_l_2,
arbcp6_cpxdp_qsel0_arbbf_ca_2, arbcp6_cpxdp_qsel1_arbbf_ca_l_2,
arbcp6_cpxdp_shift_arbbf_cx_2, arbcp7_cpxdp_grant_arbbf_ca_2,
arbcp7_cpxdp_q0_hold_arbbf_ca_l_2, arbcp7_cpxdp_qsel0_arbbf_ca_2,
arbcp7_cpxdp_qsel1_arbbf_ca_l_2, arbcp7_cpxdp_shift_arbbf_cx_2
);
output [7:0] scache3_cpx_req_bufp3_cq ;
output scache3_cpx_atom_bufp3_cq ;
output [7:0] io_cpx_req_bufp3_cq ;
output [7:0] cpx_scache3_grant_bufp3_ca_l;
output cpx_spc5_data_rdy_bufp3_cx;
output cpx_spc6_data_rdy_bufp3_cx;
output cpx_spc7_data_rdy_bufp3_cx;
output arbcp0_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp0_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp0_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp0_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp0_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp1_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp1_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp1_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp1_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp1_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp2_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp2_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp2_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp2_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp2_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp3_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp3_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp3_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp3_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp3_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp4_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp4_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp4_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp4_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp4_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp5_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp5_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp5_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp5_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp5_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp6_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp6_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp6_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp6_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp6_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp7_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp7_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp7_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp7_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp7_cpxdp_shift_bufp3_cx_l_5 ;
input [7:0] scache3_cpx_req_bufp4_cq;
input scache3_cpx_atom_bufp4_cq;
input [7:0] io_cpx_req_bufp4_cq;
input [7:0] cpx_scache3_grant_ca;
input cpx_spc5_data_rdy_cx;
input cpx_spc6_data_rdy_cx;
input cpx_spc7_data_rdy_cx;
input arbcp0_cpxdp_grant_arbbf_ca_5;
input arbcp0_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp0_cpxdp_qsel0_arbbf_ca_5;
input arbcp0_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp0_cpxdp_shift_arbbf_cx_5;
input arbcp1_cpxdp_grant_arbbf_ca_5;
input arbcp1_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp1_cpxdp_qsel0_arbbf_ca_5;
input arbcp1_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp1_cpxdp_shift_arbbf_cx_5;
input arbcp2_cpxdp_grant_arbbf_ca_5;
input arbcp2_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp2_cpxdp_qsel0_arbbf_ca_5;
input arbcp2_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp2_cpxdp_shift_arbbf_cx_5;
input arbcp3_cpxdp_grant_arbbf_ca_5;
input arbcp3_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp3_cpxdp_qsel0_arbbf_ca_5;
input arbcp3_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp3_cpxdp_shift_arbbf_cx_5;
input arbcp4_cpxdp_grant_arbbf_ca_5;
input arbcp4_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp4_cpxdp_qsel0_arbbf_ca_5;
input arbcp4_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp4_cpxdp_shift_arbbf_cx_5;
input arbcp5_cpxdp_grant_arbbf_ca_5;
input arbcp5_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp5_cpxdp_qsel0_arbbf_ca_5;
input arbcp5_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp5_cpxdp_shift_arbbf_cx_5;
input arbcp6_cpxdp_grant_arbbf_ca_5;
input arbcp6_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp6_cpxdp_qsel0_arbbf_ca_5;
input arbcp6_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp6_cpxdp_shift_arbbf_cx_5;
input arbcp7_cpxdp_grant_arbbf_ca_5;
input arbcp7_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp7_cpxdp_qsel0_arbbf_ca_5;
input arbcp7_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp7_cpxdp_shift_arbbf_cx_5;
output arbcp0_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp0_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp0_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp0_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp0_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp1_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp1_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp1_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp1_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp1_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp2_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp2_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp2_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp2_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp2_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp3_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp3_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp3_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp3_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp3_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp4_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp4_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp4_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp4_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp4_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp5_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp5_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp5_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp5_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp5_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp6_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp6_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp6_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp6_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp6_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp7_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp7_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp7_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp7_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp7_cpxdp_shift_bufp3_cx_l_2 ;
input arbcp0_cpxdp_grant_arbbf_ca_2;
input arbcp0_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp0_cpxdp_qsel0_arbbf_ca_2;
input arbcp0_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp0_cpxdp_shift_arbbf_cx_2;
input arbcp1_cpxdp_grant_arbbf_ca_2;
input arbcp1_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp1_cpxdp_qsel0_arbbf_ca_2;
input arbcp1_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp1_cpxdp_shift_arbbf_cx_2;
input arbcp2_cpxdp_grant_arbbf_ca_2;
input arbcp2_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp2_cpxdp_qsel0_arbbf_ca_2;
input arbcp2_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp2_cpxdp_shift_arbbf_cx_2;
input arbcp3_cpxdp_grant_arbbf_ca_2;
input arbcp3_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp3_cpxdp_qsel0_arbbf_ca_2;
input arbcp3_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp3_cpxdp_shift_arbbf_cx_2;
input arbcp4_cpxdp_grant_arbbf_ca_2;
input arbcp4_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp4_cpxdp_qsel0_arbbf_ca_2;
input arbcp4_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp4_cpxdp_shift_arbbf_cx_2;
input arbcp5_cpxdp_grant_arbbf_ca_2;
input arbcp5_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp5_cpxdp_qsel0_arbbf_ca_2;
input arbcp5_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp5_cpxdp_shift_arbbf_cx_2;
input arbcp6_cpxdp_grant_arbbf_ca_2;
input arbcp6_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp6_cpxdp_qsel0_arbbf_ca_2;
input arbcp6_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp6_cpxdp_shift_arbbf_cx_2;
input arbcp7_cpxdp_grant_arbbf_ca_2;
input arbcp7_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp7_cpxdp_qsel0_arbbf_ca_2;
input arbcp7_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp7_cpxdp_shift_arbbf_cx_2;
assign scache3_cpx_req_bufp3_cq[7:0] = scache3_cpx_req_bufp4_cq[7:0];
assign scache3_cpx_atom_bufp3_cq = scache3_cpx_atom_bufp4_cq;
assign io_cpx_req_bufp3_cq[7:0] = io_cpx_req_bufp4_cq[7:0];
assign cpx_scache3_grant_bufp3_ca_l = ~cpx_scache3_grant_ca;
assign cpx_spc5_data_rdy_bufp3_cx = cpx_spc5_data_rdy_cx;
assign cpx_spc6_data_rdy_bufp3_cx = cpx_spc6_data_rdy_cx;
assign cpx_spc7_data_rdy_bufp3_cx = cpx_spc7_data_rdy_cx;
assign arbcp0_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp0_cpxdp_grant_arbbf_ca_5;
assign arbcp0_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp0_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp0_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp0_cpxdp_qsel0_arbbf_ca_5;
assign arbcp0_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp0_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp0_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp0_cpxdp_shift_arbbf_cx_5;
assign arbcp1_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp1_cpxdp_grant_arbbf_ca_5;
assign arbcp1_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp1_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp1_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp1_cpxdp_qsel0_arbbf_ca_5;
assign arbcp1_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp1_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp1_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp1_cpxdp_shift_arbbf_cx_5;
assign arbcp2_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp2_cpxdp_grant_arbbf_ca_5;
assign arbcp2_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp2_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp2_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp2_cpxdp_qsel0_arbbf_ca_5;
assign arbcp2_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp2_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp2_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp2_cpxdp_shift_arbbf_cx_5;
assign arbcp3_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp3_cpxdp_grant_arbbf_ca_5;
assign arbcp3_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp3_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp3_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp3_cpxdp_qsel0_arbbf_ca_5;
assign arbcp3_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp3_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp3_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp3_cpxdp_shift_arbbf_cx_5;
assign arbcp4_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp4_cpxdp_grant_arbbf_ca_5;
assign arbcp4_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp4_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp4_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp4_cpxdp_qsel0_arbbf_ca_5;
assign arbcp4_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp4_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp4_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp4_cpxdp_shift_arbbf_cx_5;
assign arbcp5_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp5_cpxdp_grant_arbbf_ca_5;
assign arbcp5_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp5_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp5_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp5_cpxdp_qsel0_arbbf_ca_5;
assign arbcp5_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp5_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp5_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp5_cpxdp_shift_arbbf_cx_5;
assign arbcp6_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp6_cpxdp_grant_arbbf_ca_5;
assign arbcp6_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp6_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp6_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp6_cpxdp_qsel0_arbbf_ca_5;
assign arbcp6_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp6_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp6_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp6_cpxdp_shift_arbbf_cx_5;
assign arbcp7_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp7_cpxdp_grant_arbbf_ca_5;
assign arbcp7_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp7_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp7_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp7_cpxdp_qsel0_arbbf_ca_5;
assign arbcp7_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp7_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp7_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp7_cpxdp_shift_arbbf_cx_5;
assign arbcp0_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp0_cpxdp_grant_arbbf_ca_2;
assign arbcp0_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp0_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp0_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp0_cpxdp_qsel0_arbbf_ca_2;
assign arbcp0_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp0_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp0_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp0_cpxdp_shift_arbbf_cx_2;
assign arbcp1_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp1_cpxdp_grant_arbbf_ca_2;
assign arbcp1_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp1_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp1_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp1_cpxdp_qsel0_arbbf_ca_2;
assign arbcp1_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp1_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp1_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp1_cpxdp_shift_arbbf_cx_2;
assign arbcp2_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp2_cpxdp_grant_arbbf_ca_2;
assign arbcp2_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp2_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp2_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp2_cpxdp_qsel0_arbbf_ca_2;
assign arbcp2_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp2_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp2_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp2_cpxdp_shift_arbbf_cx_2;
assign arbcp3_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp3_cpxdp_grant_arbbf_ca_2;
assign arbcp3_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp3_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp3_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp3_cpxdp_qsel0_arbbf_ca_2;
assign arbcp3_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp3_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp3_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp3_cpxdp_shift_arbbf_cx_2;
assign arbcp4_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp4_cpxdp_grant_arbbf_ca_2;
assign arbcp4_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp4_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp4_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp4_cpxdp_qsel0_arbbf_ca_2;
assign arbcp4_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp4_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp4_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp4_cpxdp_shift_arbbf_cx_2;
assign arbcp5_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp5_cpxdp_grant_arbbf_ca_2;
assign arbcp5_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp5_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp5_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp5_cpxdp_qsel0_arbbf_ca_2;
assign arbcp5_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp5_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp5_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp5_cpxdp_shift_arbbf_cx_2;
assign arbcp6_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp6_cpxdp_grant_arbbf_ca_2;
assign arbcp6_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp6_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp6_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp6_cpxdp_qsel0_arbbf_ca_2;
assign arbcp6_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp6_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp6_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp6_cpxdp_shift_arbbf_cx_2;
assign arbcp7_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp7_cpxdp_grant_arbbf_ca_2;
assign arbcp7_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp7_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp7_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp7_cpxdp_qsel0_arbbf_ca_2;
assign arbcp7_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp7_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp7_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp7_cpxdp_shift_arbbf_cx_2;
endmodule |
module bcam_tb;
// simulation parameter
localparam CAMD = `CAMD ; // memory depth
localparam CAMW = `CAMW ; // data width
localparam SEGW = `SEGW ; // segment width for Segmented Transposed-RAM implementation
localparam CYCC = `CYCC ; // simulation cycles count
localparam CYCT = 10 ; // cycle time
localparam RSTT = 5.2*CYCT ; // reset time
localparam VERBOSE = 2 ; // verbose logging (0: no; 1: level 1; 2: level 2)
localparam TERFAIL = 0 ; // terminate if fail?
localparam TIMEOUT = 2*CYCT*CYCC; // simulation time
localparam ADDRW = `log2(CAMD); // CAM address width = log2 (CAM depth)
// enumerate implementations
localparam REG = 3'b000; // register-based
localparam TRS = 3'b001; // transposed-RAM stage
localparam TRC = 3'b010; // transposed-RAM cascade
localparam STR = 3'b011; // segmented transposed-RAM
localparam ALL = 3'b100; // all implementations
reg clk = 1'b0; // global clock
reg rst = 1'b1; // global reset
reg wEnb= 1'b0; // write enable
reg [CAMW -1:0] wPatt, mPatt; // patterns
reg [ADDRW-1:0] wAddr ; // write address
wire [ADDRW-1:0] mAddrBhv, mAddrReg, mAddrTRS, mAddrTRC, mAddrSTR; // match addresses
wire matchBhv, matchReg, matchTRS, matchTRC, matchSTR; // match indicators
// registered outputs
reg [ADDRW-1:0] mAddrRegR; // addresses
reg matchRegR; // match indicator
integer cycc=0; // cycles count
// generate clock and reset
always #(CYCT/2) clk = !clk; // toggle clock
integer rep_fd, ferr;
initial begin
// lower reset
#(RSTT ) rst = 1'b0;
//////////////////////////////////////////////
// print header to results file
rep_fd = $fopen("sim.res","r"); // try to open report file for read
$ferror(rep_fd,ferr); // detect error
$fclose(rep_fd);
rep_fd = $fopen("sim.res","a+"); // open report file for append
if (ferr) begin // if file is new (can't open for read); write header
$fwrite(rep_fd,"* REG: Register-based Binary Content Addressasble Memory\n");
$fwrite(rep_fd,"* TRS: Transposed-RAM Binary Content Addressasble Memory stage\n");
$fwrite(rep_fd,"* TRC: Transposed-RAM Binary Content Addressasble Memory cascade\n");
$fwrite(rep_fd,"* STR: Segmented Transposed-RAM Binary Content Addressasble Memory\n\n");
$fwrite(rep_fd,"BCAM Architectural Parameters # Simulation Mismatches\n");
$fwrite(rep_fd,"=============================== =======================\n");
$fwrite(rep_fd,"CAM Pattern Segment Simula. REG TRS TRC STR \n");
$fwrite(rep_fd,"Depth Width Width Cycles \n");
$fwrite(rep_fd,"=========================================================\n");
end
// print header
$write("Simulating BAM with the following parameters:\n");
$write("CAM depth : %0d\n",CAMD);
$write("Pattern width : %0d\n",CAMW);
$write("Segment width (STRAM): %0d\n",SEGW);
$write("Simulation Cycles : %0d\n",CYCC);
// print header if no verbose
if (VERBOSE==1)
$write("\n 1k 2k 3k 4k 5k 6k 7k 8k 9k ");
end
reg [5:0] pass; // result for each implementation
integer failCntReg = 0; // failures count
integer failCntTRS = 0; // failures count
integer failCntTRC = 0; // failures count
integer failCntSTR = 0; // failures count
integer failCntAll = 0; // failures count
integer failCntTmp = 0; // failures count / temporal/ per few cycles
always @(negedge clk) begin
if (!rst) begin
// Generate random inputs
if ( !wEnb) begin
`GETRAND( wEnb,1 );
`GETRAND(wAddr,ADDRW);
`GETRAND(wPatt,CAMW );
end else wEnb = 1'b0;
`GETRAND(mPatt,CAMW );
// write input data
if (VERBOSE==2) $write("%-7d: ",cycc);
#(CYCT/10) // a little after falling edge
if (VERBOSE==2) $write("Before rise: wEnb=%h; wAddr=%h; wPatt=%h; mPatt=%h --- ",wEnb,wAddr,wPatt,mPatt);
#(CYCT/2) // a little after rising edge
if (VERBOSE==2) $write("After rise: match=(%b,%b,%b,%b,%b); mAddr=(%h,%h,%h,%h,%h) --- ",matchBhv,matchRegR,matchTRS,matchTRC,matchSTR,mAddrBhv,mAddrRegR,mAddrTRS,mAddrTRC,mAddrSTR);
pass[REG] = !(matchBhv || matchRegR) || (matchBhv && matchRegR && (mAddrBhv===mAddrRegR));
pass[TRS] = !(matchBhv || matchTRS ) || (matchBhv && matchTRS && (mAddrBhv===mAddrTRS ));
pass[TRC] = !(matchBhv || matchTRC ) || (matchBhv && matchTRC && (mAddrBhv===mAddrTRC ));
pass[STR] = !(matchBhv || matchSTR ) || (matchBhv && matchSTR && (mAddrBhv===mAddrSTR ));
pass[ALL] = pass[REG] && pass[TRS] && pass[TRC] && pass[STR];
if (!pass[REG]) failCntReg = failCntReg + 1;
if (!pass[TRS]) failCntTRS = failCntTRS + 1;
if (!pass[TRC]) failCntTRC = failCntTRC + 1;
if (!pass[STR]) failCntSTR = failCntSTR + 1;
if (!pass[ALL]) failCntAll = failCntAll + 1;
failCntTmp = failCntAll ;
if (VERBOSE==2) $write("%s\n",pass[ALL]?"Pass":"Fail");
if (VERBOSE==1) begin
if ((cycc%10000)==0) $write("\n%4d X 10k: ",cycc/10000);
else if ((cycc%1000 )==0) $write("|");
if ((cycc%100 )==0) begin
if (failCntTmp>0) $write("x"); else $write("-");
end
failCntTmp = 0;
end
// finish if terminate on any failure
if (TERFAIL && (!pass[ALL])) begin
$write("*** Simulation terminated due to output mismatch\n");
$fclose(rep_fd);
$finish;
end
if (cycc==CYCC) begin
// write to report file
$fwrite(rep_fd,"%-7d %-7d %-7d %-7d %-5d %-5d %-5d %-5d\n",CAMD,CAMW,SEGW,CYCC,failCntReg,failCntTRS,failCntTRC,failCntSTR);
// write to STDOUT
$write("\n*** Simulation terminated after %0d cycles with %0d failures. Results:\n",CYCC,failCntAll);
$write("REG = %-5d mismatches\n",failCntReg);
$write("TRS = %-5d mismatches\n",failCntTRS);
$write("TRC = %-5d mismatches\n",failCntTRC);
$write("STR = %-5d mismatches\n",failCntSTR);
$fclose(rep_fd);
$finish;
end
cycc=cycc+1;
end
end
// Behavioral BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 1 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 1 ), // binary / register outputs match & mAddr?
.TYPE ( "BHV" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_bhv_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address
.wPatt( wPatt ), // write pattern
.mPatt( mPatt ), // patern to match
.match( matchBhv ), // match indicator
.mAddr( mAddrBhv )); // matched address
// Register-based BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 1 ), // binary / register outputs match & mAddr?
.TYPE ( "REG" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_reg_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address / [`log2(CAMD)-1:0]
.wPatt( wPatt ), // write pattern / [ CAMW -1:0]
.mPatt( mPatt ), // patern to match / [ CAMW -1:0]
.match( matchReg ), // match indicator
.mAddr( mAddrReg )); // matched address / [`log2(CAMD)-1:0]
// Transposed-RAM stage (Brute-Force) BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 1 ), // binary / register outputs match & mAddr?
.BRAM ( "M20K" ), // BRAM type- "M20K":Altera's M20K; "GEN":generic
.TYPE ( "TRS" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_trs_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address / [`log2(CAMD)-1:0]
.wPatt( wPatt ), // write pattern / [ CAMW -1:0]
.mPatt( mPatt ), // patern to match / [ CAMW -1:0]
.match( matchTRS ), // match indicator
.mAddr( mAddrTRS )); // matched address / [`log2(CAMD)-1:0]
// Transposed-RAM cascade (Brute-Force) BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 1 ), // binary / register outputs match & mAddr?
.BRAM ( "M20K" ), // BRAM type- "M20K":Altera's M20K; "GEN":generic
.TYPE ( "TRC" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_trc_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address / [`log2(CAMD)-1:0]
.wPatt( wPatt ), // write pattern / [ CAMW -1:0]
.mPatt( mPatt ), // patern to match / [ CAMW -1:0]
.match( matchTRC ), // match indicator
.mAddr( mAddrTRC )); // matched address / [`log2(CAMD)-1:0]
// Segmented Transposed-RAM BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.SEGW ( SEGW ), // Segment width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 0 ), // binary / register outputs match & mAddr?
.BRAM ( "M20K" ), // BRAM type- "M20K":Altera's M20K; "GEN":generic
.TYPE ( "STRAM" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_str_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address / [`log2(CAMD)-1:0]
.wPatt( wPatt ), // write pattern / [ CAMW -1:0]
.mPatt( mPatt ), // patern to match / [ CAMW -1:0]
.match( matchSTR ), // match indicator
.mAddr( mAddrSTR )); // matched address / [`log2(CAMD)-1:0]
// Register outputs / second stage
always @(posedge clk, posedge rst)
if (rst) {mAddrRegR,matchRegR} <= {(ADDRW +1 ){1'b0}};
else {mAddrRegR,matchRegR} <= { mAddrReg,matchReg };
endmodule |
module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] core_mem_master_araddr,
core_mem_master_awaddr,
core_mem_master_wdata,
cpu_imem_master_araddr,
cpu_imem_master_awaddr,
cpu_imem_master_wdata,
mv_tohost_value;
wire [15 : 0] dma_server_bid, dma_server_rid;
wire [7 : 0] core_mem_master_arlen,
core_mem_master_awlen,
core_mem_master_wstrb,
cpu_imem_master_arlen,
cpu_imem_master_awlen,
cpu_imem_master_wstrb,
mv_status;
wire [3 : 0] core_mem_master_arcache,
core_mem_master_arid,
core_mem_master_arqos,
core_mem_master_arregion,
core_mem_master_awcache,
core_mem_master_awid,
core_mem_master_awqos,
core_mem_master_awregion,
cpu_imem_master_arcache,
cpu_imem_master_arid,
cpu_imem_master_arqos,
cpu_imem_master_arregion,
cpu_imem_master_awcache,
cpu_imem_master_awid,
cpu_imem_master_awqos,
cpu_imem_master_awregion;
wire [2 : 0] core_mem_master_arprot,
core_mem_master_arsize,
core_mem_master_awprot,
core_mem_master_awsize,
cpu_imem_master_arprot,
cpu_imem_master_arsize,
cpu_imem_master_awprot,
cpu_imem_master_awsize;
wire [1 : 0] core_mem_master_arburst,
core_mem_master_awburst,
cpu_imem_master_arburst,
cpu_imem_master_awburst,
dma_server_bresp,
dma_server_rresp;
wire RDY_cpu_reset_server_request_put,
RDY_cpu_reset_server_response_get,
RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_set_verbosity,
RDY_set_watch_tohost,
core_mem_master_arlock,
core_mem_master_arvalid,
core_mem_master_awlock,
core_mem_master_awvalid,
core_mem_master_bready,
core_mem_master_rready,
core_mem_master_wlast,
core_mem_master_wvalid,
cpu_imem_master_arlock,
cpu_imem_master_arvalid,
cpu_imem_master_awlock,
cpu_imem_master_awvalid,
cpu_imem_master_bready,
cpu_imem_master_rready,
cpu_imem_master_wlast,
cpu_imem_master_wvalid,
cpu_reset_server_response_get,
dma_server_arready,
dma_server_awready,
dma_server_bvalid,
dma_server_rlast,
dma_server_rvalid,
dma_server_wready;
// ports of submodule cpu
wire [511 : 0] cpu$dma_server_rdata, cpu$dma_server_wdata;
wire [63 : 0] cpu$dma_server_araddr,
cpu$dma_server_awaddr,
cpu$dma_server_wstrb,
cpu$imem_master_araddr,
cpu$imem_master_awaddr,
cpu$imem_master_rdata,
cpu$imem_master_wdata,
cpu$mem_master_araddr,
cpu$mem_master_awaddr,
cpu$mem_master_rdata,
cpu$mem_master_wdata,
cpu$mv_tohost_value,
cpu$set_verbosity_logdelay,
cpu$set_watch_tohost_tohost_addr;
wire [15 : 0] cpu$dma_server_arid,
cpu$dma_server_awid,
cpu$dma_server_bid,
cpu$dma_server_rid;
wire [7 : 0] cpu$dma_server_arlen,
cpu$dma_server_awlen,
cpu$imem_master_arlen,
cpu$imem_master_awlen,
cpu$imem_master_wstrb,
cpu$mem_master_arlen,
cpu$mem_master_awlen,
cpu$mem_master_wstrb,
cpu$mv_status;
wire [3 : 0] cpu$dma_server_arcache,
cpu$dma_server_arqos,
cpu$dma_server_arregion,
cpu$dma_server_awcache,
cpu$dma_server_awqos,
cpu$dma_server_awregion,
cpu$imem_master_arcache,
cpu$imem_master_arid,
cpu$imem_master_arqos,
cpu$imem_master_arregion,
cpu$imem_master_awcache,
cpu$imem_master_awid,
cpu$imem_master_awqos,
cpu$imem_master_awregion,
cpu$imem_master_bid,
cpu$imem_master_rid,
cpu$mem_master_arcache,
cpu$mem_master_arid,
cpu$mem_master_arqos,
cpu$mem_master_arregion,
cpu$mem_master_awcache,
cpu$mem_master_awid,
cpu$mem_master_awqos,
cpu$mem_master_awregion,
cpu$mem_master_bid,
cpu$mem_master_rid,
cpu$set_verbosity_verbosity;
wire [2 : 0] cpu$dma_server_arprot,
cpu$dma_server_arsize,
cpu$dma_server_awprot,
cpu$dma_server_awsize,
cpu$imem_master_arprot,
cpu$imem_master_arsize,
cpu$imem_master_awprot,
cpu$imem_master_awsize,
cpu$mem_master_arprot,
cpu$mem_master_arsize,
cpu$mem_master_awprot,
cpu$mem_master_awsize;
wire [1 : 0] cpu$dma_server_arburst,
cpu$dma_server_awburst,
cpu$dma_server_bresp,
cpu$dma_server_rresp,
cpu$imem_master_arburst,
cpu$imem_master_awburst,
cpu$imem_master_bresp,
cpu$imem_master_rresp,
cpu$mem_master_arburst,
cpu$mem_master_awburst,
cpu$mem_master_bresp,
cpu$mem_master_rresp;
wire cpu$EN_hart0_server_reset_request_put,
cpu$EN_hart0_server_reset_response_get,
cpu$EN_ma_ddr4_ready,
cpu$EN_set_verbosity,
cpu$EN_set_watch_tohost,
cpu$RDY_hart0_server_reset_request_put,
cpu$RDY_hart0_server_reset_response_get,
cpu$dma_server_arlock,
cpu$dma_server_arready,
cpu$dma_server_arvalid,
cpu$dma_server_awlock,
cpu$dma_server_awready,
cpu$dma_server_awvalid,
cpu$dma_server_bready,
cpu$dma_server_bvalid,
cpu$dma_server_rlast,
cpu$dma_server_rready,
cpu$dma_server_rvalid,
cpu$dma_server_wlast,
cpu$dma_server_wready,
cpu$dma_server_wvalid,
cpu$hart0_server_reset_request_put,
cpu$hart0_server_reset_response_get,
cpu$imem_master_arlock,
cpu$imem_master_arready,
cpu$imem_master_arvalid,
cpu$imem_master_awlock,
cpu$imem_master_awready,
cpu$imem_master_awvalid,
cpu$imem_master_bready,
cpu$imem_master_bvalid,
cpu$imem_master_rlast,
cpu$imem_master_rready,
cpu$imem_master_rvalid,
cpu$imem_master_wlast,
cpu$imem_master_wready,
cpu$imem_master_wvalid,
cpu$m_external_interrupt_req_set_not_clear,
cpu$mem_master_arlock,
cpu$mem_master_arready,
cpu$mem_master_arvalid,
cpu$mem_master_awlock,
cpu$mem_master_awready,
cpu$mem_master_awvalid,
cpu$mem_master_bready,
cpu$mem_master_bvalid,
cpu$mem_master_rlast,
cpu$mem_master_rready,
cpu$mem_master_rvalid,
cpu$mem_master_wlast,
cpu$mem_master_wready,
cpu$mem_master_wvalid,
cpu$nmi_req_set_not_clear,
cpu$s_external_interrupt_req_set_not_clear,
cpu$set_watch_tohost_watch_tohost,
cpu$software_interrupt_req_set_not_clear,
cpu$timer_interrupt_req_set_not_clear;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule fabric_2x3
wire [63 : 0] fabric_2x3$v_from_masters_0_araddr,
fabric_2x3$v_from_masters_0_awaddr,
fabric_2x3$v_from_masters_0_rdata,
fabric_2x3$v_from_masters_0_wdata,
fabric_2x3$v_from_masters_1_araddr,
fabric_2x3$v_from_masters_1_awaddr,
fabric_2x3$v_from_masters_1_wdata,
fabric_2x3$v_to_slaves_0_araddr,
fabric_2x3$v_to_slaves_0_awaddr,
fabric_2x3$v_to_slaves_0_rdata,
fabric_2x3$v_to_slaves_0_wdata,
fabric_2x3$v_to_slaves_1_araddr,
fabric_2x3$v_to_slaves_1_awaddr,
fabric_2x3$v_to_slaves_1_rdata,
fabric_2x3$v_to_slaves_1_wdata,
fabric_2x3$v_to_slaves_2_araddr,
fabric_2x3$v_to_slaves_2_awaddr,
fabric_2x3$v_to_slaves_2_rdata,
fabric_2x3$v_to_slaves_2_wdata;
wire [7 : 0] fabric_2x3$v_from_masters_0_arlen,
fabric_2x3$v_from_masters_0_awlen,
fabric_2x3$v_from_masters_0_wstrb,
fabric_2x3$v_from_masters_1_arlen,
fabric_2x3$v_from_masters_1_awlen,
fabric_2x3$v_from_masters_1_wstrb,
fabric_2x3$v_to_slaves_0_arlen,
fabric_2x3$v_to_slaves_0_awlen,
fabric_2x3$v_to_slaves_0_wstrb,
fabric_2x3$v_to_slaves_1_arlen,
fabric_2x3$v_to_slaves_1_awlen,
fabric_2x3$v_to_slaves_1_wstrb,
fabric_2x3$v_to_slaves_2_arlen,
fabric_2x3$v_to_slaves_2_awlen,
fabric_2x3$v_to_slaves_2_wstrb;
wire [3 : 0] fabric_2x3$set_verbosity_verbosity,
fabric_2x3$v_from_masters_0_arcache,
fabric_2x3$v_from_masters_0_arid,
fabric_2x3$v_from_masters_0_arqos,
fabric_2x3$v_from_masters_0_arregion,
fabric_2x3$v_from_masters_0_awcache,
fabric_2x3$v_from_masters_0_awid,
fabric_2x3$v_from_masters_0_awqos,
fabric_2x3$v_from_masters_0_awregion,
fabric_2x3$v_from_masters_0_bid,
fabric_2x3$v_from_masters_0_rid,
fabric_2x3$v_from_masters_1_arcache,
fabric_2x3$v_from_masters_1_arid,
fabric_2x3$v_from_masters_1_arqos,
fabric_2x3$v_from_masters_1_arregion,
fabric_2x3$v_from_masters_1_awcache,
fabric_2x3$v_from_masters_1_awid,
fabric_2x3$v_from_masters_1_awqos,
fabric_2x3$v_from_masters_1_awregion,
fabric_2x3$v_to_slaves_0_arcache,
fabric_2x3$v_to_slaves_0_arid,
fabric_2x3$v_to_slaves_0_arqos,
fabric_2x3$v_to_slaves_0_arregion,
fabric_2x3$v_to_slaves_0_awcache,
fabric_2x3$v_to_slaves_0_awid,
fabric_2x3$v_to_slaves_0_awqos,
fabric_2x3$v_to_slaves_0_awregion,
fabric_2x3$v_to_slaves_0_bid,
fabric_2x3$v_to_slaves_0_rid,
fabric_2x3$v_to_slaves_1_arcache,
fabric_2x3$v_to_slaves_1_arid,
fabric_2x3$v_to_slaves_1_arqos,
fabric_2x3$v_to_slaves_1_arregion,
fabric_2x3$v_to_slaves_1_awcache,
fabric_2x3$v_to_slaves_1_awid,
fabric_2x3$v_to_slaves_1_awqos,
fabric_2x3$v_to_slaves_1_awregion,
fabric_2x3$v_to_slaves_1_bid,
fabric_2x3$v_to_slaves_1_rid,
fabric_2x3$v_to_slaves_2_arcache,
fabric_2x3$v_to_slaves_2_arid,
fabric_2x3$v_to_slaves_2_arqos,
fabric_2x3$v_to_slaves_2_arregion,
fabric_2x3$v_to_slaves_2_awcache,
fabric_2x3$v_to_slaves_2_awid,
fabric_2x3$v_to_slaves_2_awqos,
fabric_2x3$v_to_slaves_2_awregion,
fabric_2x3$v_to_slaves_2_bid,
fabric_2x3$v_to_slaves_2_rid;
wire [2 : 0] fabric_2x3$v_from_masters_0_arprot,
fabric_2x3$v_from_masters_0_arsize,
fabric_2x3$v_from_masters_0_awprot,
fabric_2x3$v_from_masters_0_awsize,
fabric_2x3$v_from_masters_1_arprot,
fabric_2x3$v_from_masters_1_arsize,
fabric_2x3$v_from_masters_1_awprot,
fabric_2x3$v_from_masters_1_awsize,
fabric_2x3$v_to_slaves_0_arprot,
fabric_2x3$v_to_slaves_0_arsize,
fabric_2x3$v_to_slaves_0_awprot,
fabric_2x3$v_to_slaves_0_awsize,
fabric_2x3$v_to_slaves_1_arprot,
fabric_2x3$v_to_slaves_1_arsize,
fabric_2x3$v_to_slaves_1_awprot,
fabric_2x3$v_to_slaves_1_awsize,
fabric_2x3$v_to_slaves_2_arprot,
fabric_2x3$v_to_slaves_2_arsize,
fabric_2x3$v_to_slaves_2_awprot,
fabric_2x3$v_to_slaves_2_awsize;
wire [1 : 0] fabric_2x3$v_from_masters_0_arburst,
fabric_2x3$v_from_masters_0_awburst,
fabric_2x3$v_from_masters_0_bresp,
fabric_2x3$v_from_masters_0_rresp,
fabric_2x3$v_from_masters_1_arburst,
fabric_2x3$v_from_masters_1_awburst,
fabric_2x3$v_to_slaves_0_arburst,
fabric_2x3$v_to_slaves_0_awburst,
fabric_2x3$v_to_slaves_0_bresp,
fabric_2x3$v_to_slaves_0_rresp,
fabric_2x3$v_to_slaves_1_arburst,
fabric_2x3$v_to_slaves_1_awburst,
fabric_2x3$v_to_slaves_1_bresp,
fabric_2x3$v_to_slaves_1_rresp,
fabric_2x3$v_to_slaves_2_arburst,
fabric_2x3$v_to_slaves_2_awburst,
fabric_2x3$v_to_slaves_2_bresp,
fabric_2x3$v_to_slaves_2_rresp;
wire fabric_2x3$EN_reset,
fabric_2x3$EN_set_verbosity,
fabric_2x3$RDY_reset,
fabric_2x3$v_from_masters_0_arlock,
fabric_2x3$v_from_masters_0_arready,
fabric_2x3$v_from_masters_0_arvalid,
fabric_2x3$v_from_masters_0_awlock,
fabric_2x3$v_from_masters_0_awready,
fabric_2x3$v_from_masters_0_awvalid,
fabric_2x3$v_from_masters_0_bready,
fabric_2x3$v_from_masters_0_bvalid,
fabric_2x3$v_from_masters_0_rlast,
fabric_2x3$v_from_masters_0_rready,
fabric_2x3$v_from_masters_0_rvalid,
fabric_2x3$v_from_masters_0_wlast,
fabric_2x3$v_from_masters_0_wready,
fabric_2x3$v_from_masters_0_wvalid,
fabric_2x3$v_from_masters_1_arlock,
fabric_2x3$v_from_masters_1_arvalid,
fabric_2x3$v_from_masters_1_awlock,
fabric_2x3$v_from_masters_1_awvalid,
fabric_2x3$v_from_masters_1_bready,
fabric_2x3$v_from_masters_1_rready,
fabric_2x3$v_from_masters_1_wlast,
fabric_2x3$v_from_masters_1_wvalid,
fabric_2x3$v_to_slaves_0_arlock,
fabric_2x3$v_to_slaves_0_arready,
fabric_2x3$v_to_slaves_0_arvalid,
fabric_2x3$v_to_slaves_0_awlock,
fabric_2x3$v_to_slaves_0_awready,
fabric_2x3$v_to_slaves_0_awvalid,
fabric_2x3$v_to_slaves_0_bready,
fabric_2x3$v_to_slaves_0_bvalid,
fabric_2x3$v_to_slaves_0_rlast,
fabric_2x3$v_to_slaves_0_rready,
fabric_2x3$v_to_slaves_0_rvalid,
fabric_2x3$v_to_slaves_0_wlast,
fabric_2x3$v_to_slaves_0_wready,
fabric_2x3$v_to_slaves_0_wvalid,
fabric_2x3$v_to_slaves_1_arlock,
fabric_2x3$v_to_slaves_1_arready,
fabric_2x3$v_to_slaves_1_arvalid,
fabric_2x3$v_to_slaves_1_awlock,
fabric_2x3$v_to_slaves_1_awready,
fabric_2x3$v_to_slaves_1_awvalid,
fabric_2x3$v_to_slaves_1_bready,
fabric_2x3$v_to_slaves_1_bvalid,
fabric_2x3$v_to_slaves_1_rlast,
fabric_2x3$v_to_slaves_1_rready,
fabric_2x3$v_to_slaves_1_rvalid,
fabric_2x3$v_to_slaves_1_wlast,
fabric_2x3$v_to_slaves_1_wready,
fabric_2x3$v_to_slaves_1_wvalid,
fabric_2x3$v_to_slaves_2_arlock,
fabric_2x3$v_to_slaves_2_arready,
fabric_2x3$v_to_slaves_2_arvalid,
fabric_2x3$v_to_slaves_2_awlock,
fabric_2x3$v_to_slaves_2_awready,
fabric_2x3$v_to_slaves_2_awvalid,
fabric_2x3$v_to_slaves_2_bready,
fabric_2x3$v_to_slaves_2_bvalid,
fabric_2x3$v_to_slaves_2_rlast,
fabric_2x3$v_to_slaves_2_rready,
fabric_2x3$v_to_slaves_2_rvalid,
fabric_2x3$v_to_slaves_2_wlast,
fabric_2x3$v_to_slaves_2_wready,
fabric_2x3$v_to_slaves_2_wvalid;
// ports of submodule near_mem_io
wire [63 : 0] near_mem_io$axi4_slave_araddr,
near_mem_io$axi4_slave_awaddr,
near_mem_io$axi4_slave_rdata,
near_mem_io$axi4_slave_wdata,
near_mem_io$set_addr_map_addr_base,
near_mem_io$set_addr_map_addr_lim;
wire [7 : 0] near_mem_io$axi4_slave_arlen,
near_mem_io$axi4_slave_awlen,
near_mem_io$axi4_slave_wstrb;
wire [3 : 0] near_mem_io$axi4_slave_arcache,
near_mem_io$axi4_slave_arid,
near_mem_io$axi4_slave_arqos,
near_mem_io$axi4_slave_arregion,
near_mem_io$axi4_slave_awcache,
near_mem_io$axi4_slave_awid,
near_mem_io$axi4_slave_awqos,
near_mem_io$axi4_slave_awregion,
near_mem_io$axi4_slave_bid,
near_mem_io$axi4_slave_rid;
wire [2 : 0] near_mem_io$axi4_slave_arprot,
near_mem_io$axi4_slave_arsize,
near_mem_io$axi4_slave_awprot,
near_mem_io$axi4_slave_awsize;
wire [1 : 0] near_mem_io$axi4_slave_arburst,
near_mem_io$axi4_slave_awburst,
near_mem_io$axi4_slave_bresp,
near_mem_io$axi4_slave_rresp;
wire near_mem_io$EN_get_sw_interrupt_req_get,
near_mem_io$EN_get_timer_interrupt_req_get,
near_mem_io$EN_server_reset_request_put,
near_mem_io$EN_server_reset_response_get,
near_mem_io$EN_set_addr_map,
near_mem_io$RDY_get_sw_interrupt_req_get,
near_mem_io$RDY_get_timer_interrupt_req_get,
near_mem_io$RDY_server_reset_request_put,
near_mem_io$RDY_server_reset_response_get,
near_mem_io$axi4_slave_arlock,
near_mem_io$axi4_slave_arready,
near_mem_io$axi4_slave_arvalid,
near_mem_io$axi4_slave_awlock,
near_mem_io$axi4_slave_awready,
near_mem_io$axi4_slave_awvalid,
near_mem_io$axi4_slave_bready,
near_mem_io$axi4_slave_bvalid,
near_mem_io$axi4_slave_rlast,
near_mem_io$axi4_slave_rready,
near_mem_io$axi4_slave_rvalid,
near_mem_io$axi4_slave_wlast,
near_mem_io$axi4_slave_wready,
near_mem_io$axi4_slave_wvalid,
near_mem_io$get_sw_interrupt_req_get,
near_mem_io$get_timer_interrupt_req_get;
// ports of submodule plic
wire [63 : 0] plic$axi4_slave_araddr,
plic$axi4_slave_awaddr,
plic$axi4_slave_rdata,
plic$axi4_slave_wdata,
plic$set_addr_map_addr_base,
plic$set_addr_map_addr_lim;
wire [7 : 0] plic$axi4_slave_arlen,
plic$axi4_slave_awlen,
plic$axi4_slave_wstrb;
wire [3 : 0] plic$axi4_slave_arcache,
plic$axi4_slave_arid,
plic$axi4_slave_arqos,
plic$axi4_slave_arregion,
plic$axi4_slave_awcache,
plic$axi4_slave_awid,
plic$axi4_slave_awqos,
plic$axi4_slave_awregion,
plic$axi4_slave_bid,
plic$axi4_slave_rid,
plic$set_verbosity_verbosity;
wire [2 : 0] plic$axi4_slave_arprot,
plic$axi4_slave_arsize,
plic$axi4_slave_awprot,
plic$axi4_slave_awsize;
wire [1 : 0] plic$axi4_slave_arburst,
plic$axi4_slave_awburst,
plic$axi4_slave_bresp,
plic$axi4_slave_rresp;
wire plic$EN_server_reset_request_put,
plic$EN_server_reset_response_get,
plic$EN_set_addr_map,
plic$EN_set_verbosity,
plic$EN_show_PLIC_state,
plic$RDY_server_reset_request_put,
plic$RDY_server_reset_response_get,
plic$axi4_slave_arlock,
plic$axi4_slave_arready,
plic$axi4_slave_arvalid,
plic$axi4_slave_awlock,
plic$axi4_slave_awready,
plic$axi4_slave_awvalid,
plic$axi4_slave_bready,
plic$axi4_slave_bvalid,
plic$axi4_slave_rlast,
plic$axi4_slave_rready,
plic$axi4_slave_rvalid,
plic$axi4_slave_wlast,
plic$axi4_slave_wready,
plic$axi4_slave_wvalid,
plic$v_sources_0_m_interrupt_req_set_not_clear,
plic$v_sources_10_m_interrupt_req_set_not_clear,
plic$v_sources_11_m_interrupt_req_set_not_clear,
plic$v_sources_12_m_interrupt_req_set_not_clear,
plic$v_sources_13_m_interrupt_req_set_not_clear,
plic$v_sources_14_m_interrupt_req_set_not_clear,
plic$v_sources_15_m_interrupt_req_set_not_clear,
plic$v_sources_1_m_interrupt_req_set_not_clear,
plic$v_sources_2_m_interrupt_req_set_not_clear,
plic$v_sources_3_m_interrupt_req_set_not_clear,
plic$v_sources_4_m_interrupt_req_set_not_clear,
plic$v_sources_5_m_interrupt_req_set_not_clear,
plic$v_sources_6_m_interrupt_req_set_not_clear,
plic$v_sources_7_m_interrupt_req_set_not_clear,
plic$v_sources_8_m_interrupt_req_set_not_clear,
plic$v_sources_9_m_interrupt_req_set_not_clear,
plic$v_targets_0_m_eip,
plic$v_targets_1_m_eip;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete,
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
CAN_FIRE_RL_rl_rd_addr_channel,
CAN_FIRE_RL_rl_rd_addr_channel_1,
CAN_FIRE_RL_rl_rd_addr_channel_2,
CAN_FIRE_RL_rl_rd_addr_channel_3,
CAN_FIRE_RL_rl_rd_data_channel,
CAN_FIRE_RL_rl_rd_data_channel_1,
CAN_FIRE_RL_rl_rd_data_channel_2,
CAN_FIRE_RL_rl_rd_data_channel_3,
CAN_FIRE_RL_rl_relay_external_interrupts,
CAN_FIRE_RL_rl_relay_sw_interrupts,
CAN_FIRE_RL_rl_relay_timer_interrupts,
CAN_FIRE_RL_rl_wr_addr_channel,
CAN_FIRE_RL_rl_wr_addr_channel_1,
CAN_FIRE_RL_rl_wr_addr_channel_2,
CAN_FIRE_RL_rl_wr_addr_channel_3,
CAN_FIRE_RL_rl_wr_data_channel,
CAN_FIRE_RL_rl_wr_data_channel_1,
CAN_FIRE_RL_rl_wr_data_channel_2,
CAN_FIRE_RL_rl_wr_data_channel_3,
CAN_FIRE_RL_rl_wr_response_channel,
CAN_FIRE_RL_rl_wr_response_channel_1,
CAN_FIRE_RL_rl_wr_response_channel_2,
CAN_FIRE_RL_rl_wr_response_channel_3,
CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
CAN_FIRE_core_mem_master_m_arready,
CAN_FIRE_core_mem_master_m_awready,
CAN_FIRE_core_mem_master_m_bvalid,
CAN_FIRE_core_mem_master_m_rvalid,
CAN_FIRE_core_mem_master_m_wready,
CAN_FIRE_cpu_imem_master_m_arready,
CAN_FIRE_cpu_imem_master_m_awready,
CAN_FIRE_cpu_imem_master_m_bvalid,
CAN_FIRE_cpu_imem_master_m_rvalid,
CAN_FIRE_cpu_imem_master_m_wready,
CAN_FIRE_cpu_reset_server_request_put,
CAN_FIRE_cpu_reset_server_response_get,
CAN_FIRE_dma_server_m_arvalid,
CAN_FIRE_dma_server_m_awvalid,
CAN_FIRE_dma_server_m_bready,
CAN_FIRE_dma_server_m_rready,
CAN_FIRE_dma_server_m_wvalid,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_nmi_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
WILL_FIRE_RL_rl_cpu_hart0_reset_complete,
WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
WILL_FIRE_RL_rl_rd_addr_channel,
WILL_FIRE_RL_rl_rd_addr_channel_1,
WILL_FIRE_RL_rl_rd_addr_channel_2,
WILL_FIRE_RL_rl_rd_addr_channel_3,
WILL_FIRE_RL_rl_rd_data_channel,
WILL_FIRE_RL_rl_rd_data_channel_1,
WILL_FIRE_RL_rl_rd_data_channel_2,
WILL_FIRE_RL_rl_rd_data_channel_3,
WILL_FIRE_RL_rl_relay_external_interrupts,
WILL_FIRE_RL_rl_relay_sw_interrupts,
WILL_FIRE_RL_rl_relay_timer_interrupts,
WILL_FIRE_RL_rl_wr_addr_channel,
WILL_FIRE_RL_rl_wr_addr_channel_1,
WILL_FIRE_RL_rl_wr_addr_channel_2,
WILL_FIRE_RL_rl_wr_addr_channel_3,
WILL_FIRE_RL_rl_wr_data_channel,
WILL_FIRE_RL_rl_wr_data_channel_1,
WILL_FIRE_RL_rl_wr_data_channel_2,
WILL_FIRE_RL_rl_wr_data_channel_3,
WILL_FIRE_RL_rl_wr_response_channel,
WILL_FIRE_RL_rl_wr_response_channel_1,
WILL_FIRE_RL_rl_wr_response_channel_2,
WILL_FIRE_RL_rl_wr_response_channel_3,
WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
WILL_FIRE_core_mem_master_m_arready,
WILL_FIRE_core_mem_master_m_awready,
WILL_FIRE_core_mem_master_m_bvalid,
WILL_FIRE_core_mem_master_m_rvalid,
WILL_FIRE_core_mem_master_m_wready,
WILL_FIRE_cpu_imem_master_m_arready,
WILL_FIRE_cpu_imem_master_m_awready,
WILL_FIRE_cpu_imem_master_m_bvalid,
WILL_FIRE_cpu_imem_master_m_rvalid,
WILL_FIRE_cpu_imem_master_m_wready,
WILL_FIRE_cpu_reset_server_request_put,
WILL_FIRE_cpu_reset_server_response_get,
WILL_FIRE_dma_server_m_arvalid,
WILL_FIRE_dma_server_m_awvalid,
WILL_FIRE_dma_server_m_bready,
WILL_FIRE_dma_server_m_rready,
WILL_FIRE_dma_server_m_wvalid,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_nmi_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4601;
reg [31 : 0] v__h4817;
reg [31 : 0] v__h4595;
reg [31 : 0] v__h4811;
// synopsys translate_on
// remaining internal signals
wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8;
// action method cpu_reset_server_request_put
assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_cpu_reset_server_request_put =
EN_cpu_reset_server_request_put ;
// actionvalue method cpu_reset_server_response_get
assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ;
assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_cpu_reset_server_response_get =
EN_cpu_reset_server_response_get ;
// value method cpu_imem_master_m_awvalid
assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ;
// value method cpu_imem_master_m_awid
assign cpu_imem_master_awid = cpu$imem_master_awid ;
// value method cpu_imem_master_m_awaddr
assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ;
// value method cpu_imem_master_m_awlen
assign cpu_imem_master_awlen = cpu$imem_master_awlen ;
// value method cpu_imem_master_m_awsize
assign cpu_imem_master_awsize = cpu$imem_master_awsize ;
// value method cpu_imem_master_m_awburst
assign cpu_imem_master_awburst = cpu$imem_master_awburst ;
// value method cpu_imem_master_m_awlock
assign cpu_imem_master_awlock = cpu$imem_master_awlock ;
// value method cpu_imem_master_m_awcache
assign cpu_imem_master_awcache = cpu$imem_master_awcache ;
// value method cpu_imem_master_m_awprot
assign cpu_imem_master_awprot = cpu$imem_master_awprot ;
// value method cpu_imem_master_m_awqos
assign cpu_imem_master_awqos = cpu$imem_master_awqos ;
// value method cpu_imem_master_m_awregion
assign cpu_imem_master_awregion = cpu$imem_master_awregion ;
// action method cpu_imem_master_m_awready
assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ;
// value method cpu_imem_master_m_wvalid
assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ;
// value method cpu_imem_master_m_wdata
assign cpu_imem_master_wdata = cpu$imem_master_wdata ;
// value method cpu_imem_master_m_wstrb
assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ;
// value method cpu_imem_master_m_wlast
assign cpu_imem_master_wlast = cpu$imem_master_wlast ;
// action method cpu_imem_master_m_wready
assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ;
// action method cpu_imem_master_m_bvalid
assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
// value method cpu_imem_master_m_bready
assign cpu_imem_master_bready = cpu$imem_master_bready ;
// value method cpu_imem_master_m_arvalid
assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ;
// value method cpu_imem_master_m_arid
assign cpu_imem_master_arid = cpu$imem_master_arid ;
// value method cpu_imem_master_m_araddr
assign cpu_imem_master_araddr = cpu$imem_master_araddr ;
// value method cpu_imem_master_m_arlen
assign cpu_imem_master_arlen = cpu$imem_master_arlen ;
// value method cpu_imem_master_m_arsize
assign cpu_imem_master_arsize = cpu$imem_master_arsize ;
// value method cpu_imem_master_m_arburst
assign cpu_imem_master_arburst = cpu$imem_master_arburst ;
// value method cpu_imem_master_m_arlock
assign cpu_imem_master_arlock = cpu$imem_master_arlock ;
// value method cpu_imem_master_m_arcache
assign cpu_imem_master_arcache = cpu$imem_master_arcache ;
// value method cpu_imem_master_m_arprot
assign cpu_imem_master_arprot = cpu$imem_master_arprot ;
// value method cpu_imem_master_m_arqos
assign cpu_imem_master_arqos = cpu$imem_master_arqos ;
// value method cpu_imem_master_m_arregion
assign cpu_imem_master_arregion = cpu$imem_master_arregion ;
// action method cpu_imem_master_m_arready
assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ;
// action method cpu_imem_master_m_rvalid
assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
// value method cpu_imem_master_m_rready
assign cpu_imem_master_rready = cpu$imem_master_rready ;
// value method core_mem_master_m_awvalid
assign core_mem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ;
// value method core_mem_master_m_awid
assign core_mem_master_awid = fabric_2x3$v_to_slaves_0_awid ;
// value method core_mem_master_m_awaddr
assign core_mem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ;
// value method core_mem_master_m_awlen
assign core_mem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ;
// value method core_mem_master_m_awsize
assign core_mem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ;
// value method core_mem_master_m_awburst
assign core_mem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ;
// value method core_mem_master_m_awlock
assign core_mem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ;
// value method core_mem_master_m_awcache
assign core_mem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ;
// value method core_mem_master_m_awprot
assign core_mem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ;
// value method core_mem_master_m_awqos
assign core_mem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ;
// value method core_mem_master_m_awregion
assign core_mem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ;
// action method core_mem_master_m_awready
assign CAN_FIRE_core_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_awready = 1'd1 ;
// value method core_mem_master_m_wvalid
assign core_mem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ;
// value method core_mem_master_m_wdata
assign core_mem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ;
// value method core_mem_master_m_wstrb
assign core_mem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ;
// value method core_mem_master_m_wlast
assign core_mem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ;
// action method core_mem_master_m_wready
assign CAN_FIRE_core_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_wready = 1'd1 ;
// action method core_mem_master_m_bvalid
assign CAN_FIRE_core_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_bvalid = 1'd1 ;
// value method core_mem_master_m_bready
assign core_mem_master_bready = fabric_2x3$v_to_slaves_0_bready ;
// value method core_mem_master_m_arvalid
assign core_mem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ;
// value method core_mem_master_m_arid
assign core_mem_master_arid = fabric_2x3$v_to_slaves_0_arid ;
// value method core_mem_master_m_araddr
assign core_mem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ;
// value method core_mem_master_m_arlen
assign core_mem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ;
// value method core_mem_master_m_arsize
assign core_mem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ;
// value method core_mem_master_m_arburst
assign core_mem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ;
// value method core_mem_master_m_arlock
assign core_mem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ;
// value method core_mem_master_m_arcache
assign core_mem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ;
// value method core_mem_master_m_arprot
assign core_mem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ;
// value method core_mem_master_m_arqos
assign core_mem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ;
// value method core_mem_master_m_arregion
assign core_mem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ;
// action method core_mem_master_m_arready
assign CAN_FIRE_core_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_arready = 1'd1 ;
// action method core_mem_master_m_rvalid
assign CAN_FIRE_core_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_rvalid = 1'd1 ;
// value method core_mem_master_m_rready
assign core_mem_master_rready = fabric_2x3$v_to_slaves_0_rready ;
// action method dma_server_m_awvalid
assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;
// value method dma_server_m_awready
assign dma_server_awready = cpu$dma_server_awready ;
// action method dma_server_m_wvalid
assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;
// value method dma_server_m_wready
assign dma_server_wready = cpu$dma_server_wready ;
// value method dma_server_m_bvalid
assign dma_server_bvalid = cpu$dma_server_bvalid ;
// value method dma_server_m_bid
assign dma_server_bid = cpu$dma_server_bid ;
// value method dma_server_m_bresp
assign dma_server_bresp = cpu$dma_server_bresp ;
// action method dma_server_m_bready
assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
assign WILL_FIRE_dma_server_m_bready = 1'd1 ;
// action method dma_server_m_arvalid
assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;
// value method dma_server_m_arready
assign dma_server_arready = cpu$dma_server_arready ;
// value method dma_server_m_rvalid
assign dma_server_rvalid = cpu$dma_server_rvalid ;
// value method dma_server_m_rid
assign dma_server_rid = cpu$dma_server_rid ;
// value method dma_server_m_rdata
assign dma_server_rdata = cpu$dma_server_rdata ;
// value method dma_server_m_rresp
assign dma_server_rresp = cpu$dma_server_rresp ;
// value method dma_server_m_rlast
assign dma_server_rlast = cpu$dma_server_rlast ;
// action method dma_server_m_rready
assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
assign WILL_FIRE_dma_server_m_rready = 1'd1 ;
// action method core_external_interrupt_sources_0_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_1_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_2_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_3_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_4_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_5_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_6_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_7_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_8_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_9_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_10_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_11_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_12_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_13_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_14_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_15_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = cpu$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = cpu$mv_status ;
// submodule cpu
mkCPU cpu(.CLK(CLK),
.RST_N(RST_N),
.dma_server_araddr(cpu$dma_server_araddr),
.dma_server_arburst(cpu$dma_server_arburst),
.dma_server_arcache(cpu$dma_server_arcache),
.dma_server_arid(cpu$dma_server_arid),
.dma_server_arlen(cpu$dma_server_arlen),
.dma_server_arlock(cpu$dma_server_arlock),
.dma_server_arprot(cpu$dma_server_arprot),
.dma_server_arqos(cpu$dma_server_arqos),
.dma_server_arregion(cpu$dma_server_arregion),
.dma_server_arsize(cpu$dma_server_arsize),
.dma_server_arvalid(cpu$dma_server_arvalid),
.dma_server_awaddr(cpu$dma_server_awaddr),
.dma_server_awburst(cpu$dma_server_awburst),
.dma_server_awcache(cpu$dma_server_awcache),
.dma_server_awid(cpu$dma_server_awid),
.dma_server_awlen(cpu$dma_server_awlen),
.dma_server_awlock(cpu$dma_server_awlock),
.dma_server_awprot(cpu$dma_server_awprot),
.dma_server_awqos(cpu$dma_server_awqos),
.dma_server_awregion(cpu$dma_server_awregion),
.dma_server_awsize(cpu$dma_server_awsize),
.dma_server_awvalid(cpu$dma_server_awvalid),
.dma_server_bready(cpu$dma_server_bready),
.dma_server_rready(cpu$dma_server_rready),
.dma_server_wdata(cpu$dma_server_wdata),
.dma_server_wlast(cpu$dma_server_wlast),
.dma_server_wstrb(cpu$dma_server_wstrb),
.dma_server_wvalid(cpu$dma_server_wvalid),
.hart0_server_reset_request_put(cpu$hart0_server_reset_request_put),
.imem_master_arready(cpu$imem_master_arready),
.imem_master_awready(cpu$imem_master_awready),
.imem_master_bid(cpu$imem_master_bid),
.imem_master_bresp(cpu$imem_master_bresp),
.imem_master_bvalid(cpu$imem_master_bvalid),
.imem_master_rdata(cpu$imem_master_rdata),
.imem_master_rid(cpu$imem_master_rid),
.imem_master_rlast(cpu$imem_master_rlast),
.imem_master_rresp(cpu$imem_master_rresp),
.imem_master_rvalid(cpu$imem_master_rvalid),
.imem_master_wready(cpu$imem_master_wready),
.m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear),
.mem_master_arready(cpu$mem_master_arready),
.mem_master_awready(cpu$mem_master_awready),
.mem_master_bid(cpu$mem_master_bid),
.mem_master_bresp(cpu$mem_master_bresp),
.mem_master_bvalid(cpu$mem_master_bvalid),
.mem_master_rdata(cpu$mem_master_rdata),
.mem_master_rid(cpu$mem_master_rid),
.mem_master_rlast(cpu$mem_master_rlast),
.mem_master_rresp(cpu$mem_master_rresp),
.mem_master_rvalid(cpu$mem_master_rvalid),
.mem_master_wready(cpu$mem_master_wready),
.nmi_req_set_not_clear(cpu$nmi_req_set_not_clear),
.s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear),
.set_verbosity_logdelay(cpu$set_verbosity_logdelay),
.set_verbosity_verbosity(cpu$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(cpu$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(cpu$set_watch_tohost_watch_tohost),
.software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear),
.timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear),
.EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put),
.EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get),
.EN_set_verbosity(cpu$EN_set_verbosity),
.EN_set_watch_tohost(cpu$EN_set_watch_tohost),
.EN_ma_ddr4_ready(cpu$EN_ma_ddr4_ready),
.RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put),
.hart0_server_reset_response_get(cpu$hart0_server_reset_response_get),
.RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get),
.imem_master_awvalid(cpu$imem_master_awvalid),
.imem_master_awid(cpu$imem_master_awid),
.imem_master_awaddr(cpu$imem_master_awaddr),
.imem_master_awlen(cpu$imem_master_awlen),
.imem_master_awsize(cpu$imem_master_awsize),
.imem_master_awburst(cpu$imem_master_awburst),
.imem_master_awlock(cpu$imem_master_awlock),
.imem_master_awcache(cpu$imem_master_awcache),
.imem_master_awprot(cpu$imem_master_awprot),
.imem_master_awqos(cpu$imem_master_awqos),
.imem_master_awregion(cpu$imem_master_awregion),
.imem_master_wvalid(cpu$imem_master_wvalid),
.imem_master_wdata(cpu$imem_master_wdata),
.imem_master_wstrb(cpu$imem_master_wstrb),
.imem_master_wlast(cpu$imem_master_wlast),
.imem_master_bready(cpu$imem_master_bready),
.imem_master_arvalid(cpu$imem_master_arvalid),
.imem_master_arid(cpu$imem_master_arid),
.imem_master_araddr(cpu$imem_master_araddr),
.imem_master_arlen(cpu$imem_master_arlen),
.imem_master_arsize(cpu$imem_master_arsize),
.imem_master_arburst(cpu$imem_master_arburst),
.imem_master_arlock(cpu$imem_master_arlock),
.imem_master_arcache(cpu$imem_master_arcache),
.imem_master_arprot(cpu$imem_master_arprot),
.imem_master_arqos(cpu$imem_master_arqos),
.imem_master_arregion(cpu$imem_master_arregion),
.imem_master_rready(cpu$imem_master_rready),
.mem_master_awvalid(cpu$mem_master_awvalid),
.mem_master_awid(cpu$mem_master_awid),
.mem_master_awaddr(cpu$mem_master_awaddr),
.mem_master_awlen(cpu$mem_master_awlen),
.mem_master_awsize(cpu$mem_master_awsize),
.mem_master_awburst(cpu$mem_master_awburst),
.mem_master_awlock(cpu$mem_master_awlock),
.mem_master_awcache(cpu$mem_master_awcache),
.mem_master_awprot(cpu$mem_master_awprot),
.mem_master_awqos(cpu$mem_master_awqos),
.mem_master_awregion(cpu$mem_master_awregion),
.mem_master_wvalid(cpu$mem_master_wvalid),
.mem_master_wdata(cpu$mem_master_wdata),
.mem_master_wstrb(cpu$mem_master_wstrb),
.mem_master_wlast(cpu$mem_master_wlast),
.mem_master_bready(cpu$mem_master_bready),
.mem_master_arvalid(cpu$mem_master_arvalid),
.mem_master_arid(cpu$mem_master_arid),
.mem_master_araddr(cpu$mem_master_araddr),
.mem_master_arlen(cpu$mem_master_arlen),
.mem_master_arsize(cpu$mem_master_arsize),
.mem_master_arburst(cpu$mem_master_arburst),
.mem_master_arlock(cpu$mem_master_arlock),
.mem_master_arcache(cpu$mem_master_arcache),
.mem_master_arprot(cpu$mem_master_arprot),
.mem_master_arqos(cpu$mem_master_arqos),
.mem_master_arregion(cpu$mem_master_arregion),
.mem_master_rready(cpu$mem_master_rready),
.dma_server_awready(cpu$dma_server_awready),
.dma_server_wready(cpu$dma_server_wready),
.dma_server_bvalid(cpu$dma_server_bvalid),
.dma_server_bid(cpu$dma_server_bid),
.dma_server_bresp(cpu$dma_server_bresp),
.dma_server_arready(cpu$dma_server_arready),
.dma_server_rvalid(cpu$dma_server_rvalid),
.dma_server_rid(cpu$dma_server_rid),
.dma_server_rdata(cpu$dma_server_rdata),
.dma_server_rresp(cpu$dma_server_rresp),
.dma_server_rlast(cpu$dma_server_rlast),
.RDY_set_verbosity(),
.RDY_set_watch_tohost(),
.mv_tohost_value(cpu$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(cpu$mv_status));
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule fabric_2x3
mkFabric_2x3 fabric_2x3(.CLK(CLK),
.RST_N(RST_N),
.set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity),
.v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr),
.v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst),
.v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache),
.v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid),
.v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen),
.v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock),
.v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot),
.v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos),
.v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion),
.v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize),
.v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid),
.v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr),
.v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst),
.v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache),
.v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid),
.v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen),
.v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock),
.v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot),
.v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos),
.v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion),
.v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize),
.v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid),
.v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready),
.v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready),
.v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata),
.v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast),
.v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb),
.v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid),
.v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr),
.v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst),
.v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache),
.v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid),
.v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen),
.v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock),
.v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot),
.v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos),
.v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion),
.v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize),
.v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid),
.v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr),
.v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst),
.v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache),
.v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid),
.v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen),
.v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock),
.v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot),
.v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos),
.v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion),
.v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize),
.v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid),
.v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready),
.v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready),
.v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata),
.v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast),
.v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb),
.v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid),
.v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready),
.v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready),
.v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid),
.v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp),
.v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid),
.v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata),
.v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid),
.v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast),
.v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp),
.v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid),
.v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready),
.v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready),
.v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready),
.v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid),
.v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp),
.v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid),
.v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata),
.v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid),
.v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast),
.v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp),
.v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid),
.v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready),
.v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready),
.v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready),
.v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid),
.v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp),
.v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid),
.v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata),
.v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid),
.v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast),
.v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp),
.v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid),
.v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready),
.EN_reset(fabric_2x3$EN_reset),
.EN_set_verbosity(fabric_2x3$EN_set_verbosity),
.RDY_reset(fabric_2x3$RDY_reset),
.RDY_set_verbosity(),
.v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready),
.v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready),
.v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid),
.v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid),
.v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp),
.v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready),
.v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid),
.v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid),
.v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata),
.v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp),
.v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast),
.v_from_masters_1_awready(),
.v_from_masters_1_wready(),
.v_from_masters_1_bvalid(),
.v_from_masters_1_bid(),
.v_from_masters_1_bresp(),
.v_from_masters_1_arready(),
.v_from_masters_1_rvalid(),
.v_from_masters_1_rid(),
.v_from_masters_1_rdata(),
.v_from_masters_1_rresp(),
.v_from_masters_1_rlast(),
.v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid),
.v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid),
.v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr),
.v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen),
.v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize),
.v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst),
.v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock),
.v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache),
.v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot),
.v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos),
.v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion),
.v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid),
.v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata),
.v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb),
.v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast),
.v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready),
.v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid),
.v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid),
.v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr),
.v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen),
.v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize),
.v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst),
.v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock),
.v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache),
.v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot),
.v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos),
.v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion),
.v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready),
.v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid),
.v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid),
.v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr),
.v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen),
.v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize),
.v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst),
.v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock),
.v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache),
.v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot),
.v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos),
.v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion),
.v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid),
.v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata),
.v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb),
.v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast),
.v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready),
.v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid),
.v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid),
.v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr),
.v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen),
.v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize),
.v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst),
.v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock),
.v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache),
.v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot),
.v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos),
.v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion),
.v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready),
.v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid),
.v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid),
.v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr),
.v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen),
.v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize),
.v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst),
.v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock),
.v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache),
.v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot),
.v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos),
.v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion),
.v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid),
.v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata),
.v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb),
.v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast),
.v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready),
.v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid),
.v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid),
.v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr),
.v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen),
.v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize),
.v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst),
.v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock),
.v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache),
.v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot),
.v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos),
.v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion),
.v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready));
// submodule near_mem_io
mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK),
.RST_N(RST_N),
.axi4_slave_araddr(near_mem_io$axi4_slave_araddr),
.axi4_slave_arburst(near_mem_io$axi4_slave_arburst),
.axi4_slave_arcache(near_mem_io$axi4_slave_arcache),
.axi4_slave_arid(near_mem_io$axi4_slave_arid),
.axi4_slave_arlen(near_mem_io$axi4_slave_arlen),
.axi4_slave_arlock(near_mem_io$axi4_slave_arlock),
.axi4_slave_arprot(near_mem_io$axi4_slave_arprot),
.axi4_slave_arqos(near_mem_io$axi4_slave_arqos),
.axi4_slave_arregion(near_mem_io$axi4_slave_arregion),
.axi4_slave_arsize(near_mem_io$axi4_slave_arsize),
.axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid),
.axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr),
.axi4_slave_awburst(near_mem_io$axi4_slave_awburst),
.axi4_slave_awcache(near_mem_io$axi4_slave_awcache),
.axi4_slave_awid(near_mem_io$axi4_slave_awid),
.axi4_slave_awlen(near_mem_io$axi4_slave_awlen),
.axi4_slave_awlock(near_mem_io$axi4_slave_awlock),
.axi4_slave_awprot(near_mem_io$axi4_slave_awprot),
.axi4_slave_awqos(near_mem_io$axi4_slave_awqos),
.axi4_slave_awregion(near_mem_io$axi4_slave_awregion),
.axi4_slave_awsize(near_mem_io$axi4_slave_awsize),
.axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid),
.axi4_slave_bready(near_mem_io$axi4_slave_bready),
.axi4_slave_rready(near_mem_io$axi4_slave_rready),
.axi4_slave_wdata(near_mem_io$axi4_slave_wdata),
.axi4_slave_wlast(near_mem_io$axi4_slave_wlast),
.axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb),
.axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid),
.set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base),
.set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim),
.EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put),
.EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get),
.EN_set_addr_map(near_mem_io$EN_set_addr_map),
.EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get),
.EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get),
.RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put),
.RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get),
.RDY_set_addr_map(),
.axi4_slave_awready(near_mem_io$axi4_slave_awready),
.axi4_slave_wready(near_mem_io$axi4_slave_wready),
.axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid),
.axi4_slave_bid(near_mem_io$axi4_slave_bid),
.axi4_slave_bresp(near_mem_io$axi4_slave_bresp),
.axi4_slave_arready(near_mem_io$axi4_slave_arready),
.axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid),
.axi4_slave_rid(near_mem_io$axi4_slave_rid),
.axi4_slave_rdata(near_mem_io$axi4_slave_rdata),
.axi4_slave_rresp(near_mem_io$axi4_slave_rresp),
.axi4_slave_rlast(near_mem_io$axi4_slave_rlast),
.get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get),
.RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get),
.get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get),
.RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get));
// submodule plic
mkPLIC_16_2_7 plic(.CLK(CLK),
.RST_N(RST_N),
.axi4_slave_araddr(plic$axi4_slave_araddr),
.axi4_slave_arburst(plic$axi4_slave_arburst),
.axi4_slave_arcache(plic$axi4_slave_arcache),
.axi4_slave_arid(plic$axi4_slave_arid),
.axi4_slave_arlen(plic$axi4_slave_arlen),
.axi4_slave_arlock(plic$axi4_slave_arlock),
.axi4_slave_arprot(plic$axi4_slave_arprot),
.axi4_slave_arqos(plic$axi4_slave_arqos),
.axi4_slave_arregion(plic$axi4_slave_arregion),
.axi4_slave_arsize(plic$axi4_slave_arsize),
.axi4_slave_arvalid(plic$axi4_slave_arvalid),
.axi4_slave_awaddr(plic$axi4_slave_awaddr),
.axi4_slave_awburst(plic$axi4_slave_awburst),
.axi4_slave_awcache(plic$axi4_slave_awcache),
.axi4_slave_awid(plic$axi4_slave_awid),
.axi4_slave_awlen(plic$axi4_slave_awlen),
.axi4_slave_awlock(plic$axi4_slave_awlock),
.axi4_slave_awprot(plic$axi4_slave_awprot),
.axi4_slave_awqos(plic$axi4_slave_awqos),
.axi4_slave_awregion(plic$axi4_slave_awregion),
.axi4_slave_awsize(plic$axi4_slave_awsize),
.axi4_slave_awvalid(plic$axi4_slave_awvalid),
.axi4_slave_bready(plic$axi4_slave_bready),
.axi4_slave_rready(plic$axi4_slave_rready),
.axi4_slave_wdata(plic$axi4_slave_wdata),
.axi4_slave_wlast(plic$axi4_slave_wlast),
.axi4_slave_wstrb(plic$axi4_slave_wstrb),
.axi4_slave_wvalid(plic$axi4_slave_wvalid),
.set_addr_map_addr_base(plic$set_addr_map_addr_base),
.set_addr_map_addr_lim(plic$set_addr_map_addr_lim),
.set_verbosity_verbosity(plic$set_verbosity_verbosity),
.v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear),
.v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear),
.v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear),
.v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear),
.v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear),
.v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear),
.v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear),
.v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear),
.v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear),
.v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear),
.v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear),
.v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear),
.v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear),
.v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear),
.v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear),
.v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear),
.EN_set_verbosity(plic$EN_set_verbosity),
.EN_show_PLIC_state(plic$EN_show_PLIC_state),
.EN_server_reset_request_put(plic$EN_server_reset_request_put),
.EN_server_reset_response_get(plic$EN_server_reset_response_get),
.EN_set_addr_map(plic$EN_set_addr_map),
.RDY_set_verbosity(),
.RDY_show_PLIC_state(),
.RDY_server_reset_request_put(plic$RDY_server_reset_request_put),
.RDY_server_reset_response_get(plic$RDY_server_reset_response_get),
.RDY_set_addr_map(),
.axi4_slave_awready(plic$axi4_slave_awready),
.axi4_slave_wready(plic$axi4_slave_wready),
.axi4_slave_bvalid(plic$axi4_slave_bvalid),
.axi4_slave_bid(plic$axi4_slave_bid),
.axi4_slave_bresp(plic$axi4_slave_bresp),
.axi4_slave_arready(plic$axi4_slave_arready),
.axi4_slave_rvalid(plic$axi4_slave_rvalid),
.axi4_slave_rid(plic$axi4_slave_rid),
.axi4_slave_rdata(plic$axi4_slave_rdata),
.axi4_slave_rresp(plic$axi4_slave_rresp),
.axi4_slave_rlast(plic$axi4_slave_rlast),
.v_targets_0_m_eip(plic$v_targets_0_m_eip),
.v_targets_1_m_eip(plic$v_targets_1_m_eip));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_wr_addr_channel
assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
// rule RL_rl_wr_data_channel
assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ;
// rule RL_rl_wr_response_channel
assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ;
// rule RL_rl_rd_addr_channel
assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
// rule RL_rl_rd_data_channel
assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ;
// rule RL_rl_wr_addr_channel_1
assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
// rule RL_rl_wr_data_channel_1
assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_response_channel_1
assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
// rule RL_rl_rd_addr_channel_1
assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
// rule RL_rl_rd_data_channel_1
assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_addr_channel_2
assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
// rule RL_rl_wr_data_channel_2
assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_response_channel_2
assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
// rule RL_rl_rd_addr_channel_2
assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
// rule RL_rl_rd_data_channel_2
assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_addr_channel_3
assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
// rule RL_rl_wr_data_channel_3
assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
// rule RL_rl_wr_response_channel_3
assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
// rule RL_rl_rd_addr_channel_3
assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
// rule RL_rl_rd_data_channel_3
assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
// rule RL_rl_relay_sw_interrupts
assign CAN_FIRE_RL_rl_relay_sw_interrupts =
near_mem_io$RDY_get_sw_interrupt_req_get ;
assign WILL_FIRE_RL_rl_relay_sw_interrupts =
near_mem_io$RDY_get_sw_interrupt_req_get ;
// rule RL_rl_relay_timer_interrupts
assign CAN_FIRE_RL_rl_relay_timer_interrupts =
near_mem_io$RDY_get_timer_interrupt_req_get ;
assign WILL_FIRE_RL_rl_relay_timer_interrupts =
near_mem_io$RDY_get_timer_interrupt_req_get ;
// rule RL_rl_relay_external_interrupts
assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
// rule RL_rl_cpu_hart0_reset_from_soc_start
assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
near_mem_io$RDY_server_reset_request_put &&
plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ;
assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
// rule RL_rl_cpu_hart0_reset_complete
assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete =
near_mem_io$RDY_server_reset_response_get &&
plic$RDY_server_reset_response_get &&
cpu$RDY_hart0_server_reset_response_get &&
f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
// submodule cpu
assign cpu$dma_server_araddr = dma_server_araddr ;
assign cpu$dma_server_arburst = dma_server_arburst ;
assign cpu$dma_server_arcache = dma_server_arcache ;
assign cpu$dma_server_arid = dma_server_arid ;
assign cpu$dma_server_arlen = dma_server_arlen ;
assign cpu$dma_server_arlock = dma_server_arlock ;
assign cpu$dma_server_arprot = dma_server_arprot ;
assign cpu$dma_server_arqos = dma_server_arqos ;
assign cpu$dma_server_arregion = dma_server_arregion ;
assign cpu$dma_server_arsize = dma_server_arsize ;
assign cpu$dma_server_arvalid = dma_server_arvalid ;
assign cpu$dma_server_awaddr = dma_server_awaddr ;
assign cpu$dma_server_awburst = dma_server_awburst ;
assign cpu$dma_server_awcache = dma_server_awcache ;
assign cpu$dma_server_awid = dma_server_awid ;
assign cpu$dma_server_awlen = dma_server_awlen ;
assign cpu$dma_server_awlock = dma_server_awlock ;
assign cpu$dma_server_awprot = dma_server_awprot ;
assign cpu$dma_server_awqos = dma_server_awqos ;
assign cpu$dma_server_awregion = dma_server_awregion ;
assign cpu$dma_server_awsize = dma_server_awsize ;
assign cpu$dma_server_awvalid = dma_server_awvalid ;
assign cpu$dma_server_bready = dma_server_bready ;
assign cpu$dma_server_rready = dma_server_rready ;
assign cpu$dma_server_wdata = dma_server_wdata ;
assign cpu$dma_server_wlast = dma_server_wlast ;
assign cpu$dma_server_wstrb = dma_server_wstrb ;
assign cpu$dma_server_wvalid = dma_server_wvalid ;
assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ;
assign cpu$imem_master_arready = cpu_imem_master_arready ;
assign cpu$imem_master_awready = cpu_imem_master_awready ;
assign cpu$imem_master_bid = cpu_imem_master_bid ;
assign cpu$imem_master_bresp = cpu_imem_master_bresp ;
assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ;
assign cpu$imem_master_rdata = cpu_imem_master_rdata ;
assign cpu$imem_master_rid = cpu_imem_master_rid ;
assign cpu$imem_master_rlast = cpu_imem_master_rlast ;
assign cpu$imem_master_rresp = cpu_imem_master_rresp ;
assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ;
assign cpu$imem_master_wready = cpu_imem_master_wready ;
assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ;
assign cpu$mem_master_arready = fabric_2x3$v_from_masters_0_arready ;
assign cpu$mem_master_awready = fabric_2x3$v_from_masters_0_awready ;
assign cpu$mem_master_bid = fabric_2x3$v_from_masters_0_bid ;
assign cpu$mem_master_bresp = fabric_2x3$v_from_masters_0_bresp ;
assign cpu$mem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ;
assign cpu$mem_master_rdata = fabric_2x3$v_from_masters_0_rdata ;
assign cpu$mem_master_rid = fabric_2x3$v_from_masters_0_rid ;
assign cpu$mem_master_rlast = fabric_2x3$v_from_masters_0_rlast ;
assign cpu$mem_master_rresp = fabric_2x3$v_from_masters_0_rresp ;
assign cpu$mem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ;
assign cpu$mem_master_wready = fabric_2x3$v_from_masters_0_wready ;
assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ;
assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ;
assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ;
assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ;
assign cpu$set_watch_tohost_tohost_addr = set_watch_tohost_tohost_addr ;
assign cpu$set_watch_tohost_watch_tohost = set_watch_tohost_watch_tohost ;
assign cpu$software_interrupt_req_set_not_clear =
near_mem_io$get_sw_interrupt_req_get ;
assign cpu$timer_interrupt_req_set_not_clear =
near_mem_io$get_timer_interrupt_req_get ;
assign cpu$EN_hart0_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign cpu$EN_hart0_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign cpu$EN_set_verbosity = EN_set_verbosity ;
assign cpu$EN_set_watch_tohost = EN_set_watch_tohost ;
assign cpu$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = cpu_reset_server_request_put ;
assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ;
assign f_reset_reqs$DEQ =
near_mem_io$RDY_server_reset_request_put &&
plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ;
assign f_reset_rsps$ENQ =
near_mem_io$RDY_server_reset_response_get &&
plic$RDY_server_reset_response_get &&
cpu$RDY_hart0_server_reset_response_get &&
f_reset_rsps$FULL_N ;
assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule fabric_2x3
assign fabric_2x3$set_verbosity_verbosity = 4'h0 ;
assign fabric_2x3$v_from_masters_0_araddr = cpu$mem_master_araddr ;
assign fabric_2x3$v_from_masters_0_arburst = cpu$mem_master_arburst ;
assign fabric_2x3$v_from_masters_0_arcache = cpu$mem_master_arcache ;
assign fabric_2x3$v_from_masters_0_arid = cpu$mem_master_arid ;
assign fabric_2x3$v_from_masters_0_arlen = cpu$mem_master_arlen ;
assign fabric_2x3$v_from_masters_0_arlock = cpu$mem_master_arlock ;
assign fabric_2x3$v_from_masters_0_arprot = cpu$mem_master_arprot ;
assign fabric_2x3$v_from_masters_0_arqos = cpu$mem_master_arqos ;
assign fabric_2x3$v_from_masters_0_arregion = cpu$mem_master_arregion ;
assign fabric_2x3$v_from_masters_0_arsize = cpu$mem_master_arsize ;
assign fabric_2x3$v_from_masters_0_arvalid = cpu$mem_master_arvalid ;
assign fabric_2x3$v_from_masters_0_awaddr = cpu$mem_master_awaddr ;
assign fabric_2x3$v_from_masters_0_awburst = cpu$mem_master_awburst ;
assign fabric_2x3$v_from_masters_0_awcache = cpu$mem_master_awcache ;
assign fabric_2x3$v_from_masters_0_awid = cpu$mem_master_awid ;
assign fabric_2x3$v_from_masters_0_awlen = cpu$mem_master_awlen ;
assign fabric_2x3$v_from_masters_0_awlock = cpu$mem_master_awlock ;
assign fabric_2x3$v_from_masters_0_awprot = cpu$mem_master_awprot ;
assign fabric_2x3$v_from_masters_0_awqos = cpu$mem_master_awqos ;
assign fabric_2x3$v_from_masters_0_awregion = cpu$mem_master_awregion ;
assign fabric_2x3$v_from_masters_0_awsize = cpu$mem_master_awsize ;
assign fabric_2x3$v_from_masters_0_awvalid = cpu$mem_master_awvalid ;
assign fabric_2x3$v_from_masters_0_bready = cpu$mem_master_bready ;
assign fabric_2x3$v_from_masters_0_rready = cpu$mem_master_rready ;
assign fabric_2x3$v_from_masters_0_wdata = cpu$mem_master_wdata ;
assign fabric_2x3$v_from_masters_0_wlast = cpu$mem_master_wlast ;
assign fabric_2x3$v_from_masters_0_wstrb = cpu$mem_master_wstrb ;
assign fabric_2x3$v_from_masters_0_wvalid = cpu$mem_master_wvalid ;
assign fabric_2x3$v_from_masters_1_araddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arburst =
2'b10 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arcache =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arlen =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arprot =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arqos =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arregion =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arsize =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ;
assign fabric_2x3$v_from_masters_1_awaddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awburst =
2'b10 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awcache =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awlen =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awprot =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awqos =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awregion =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awsize =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ;
assign fabric_2x3$v_from_masters_1_bready = 1'd0 ;
assign fabric_2x3$v_from_masters_1_rready = 1'd0 ;
assign fabric_2x3$v_from_masters_1_wdata =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wstrb =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ;
assign fabric_2x3$v_to_slaves_0_arready = core_mem_master_arready ;
assign fabric_2x3$v_to_slaves_0_awready = core_mem_master_awready ;
assign fabric_2x3$v_to_slaves_0_bid = core_mem_master_bid ;
assign fabric_2x3$v_to_slaves_0_bresp = core_mem_master_bresp ;
assign fabric_2x3$v_to_slaves_0_bvalid = core_mem_master_bvalid ;
assign fabric_2x3$v_to_slaves_0_rdata = core_mem_master_rdata ;
assign fabric_2x3$v_to_slaves_0_rid = core_mem_master_rid ;
assign fabric_2x3$v_to_slaves_0_rlast = core_mem_master_rlast ;
assign fabric_2x3$v_to_slaves_0_rresp = core_mem_master_rresp ;
assign fabric_2x3$v_to_slaves_0_rvalid = core_mem_master_rvalid ;
assign fabric_2x3$v_to_slaves_0_wready = core_mem_master_wready ;
assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ;
assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ;
assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ;
assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ;
assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ;
assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ;
assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ;
assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ;
assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ;
assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ;
assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ;
assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ;
assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ;
assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ;
assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ;
assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ;
assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ;
assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ;
assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ;
assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ;
assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ;
assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ;
assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign fabric_2x3$EN_set_verbosity = 1'b0 ;
// submodule near_mem_io
assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ;
assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ;
assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ;
assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ;
assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ;
assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ;
assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ;
assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ;
assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ;
assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ;
assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ;
assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ;
assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ;
assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ;
assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ;
assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ;
assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ;
assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ;
assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ;
assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ;
assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ;
assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ;
assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ;
assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ;
assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ;
assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ;
assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ;
assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ;
assign near_mem_io$set_addr_map_addr_base =
soc_map$m_near_mem_io_addr_base ;
assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ;
assign near_mem_io$EN_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign near_mem_io$EN_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign near_mem_io$EN_set_addr_map =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign near_mem_io$EN_get_timer_interrupt_req_get =
near_mem_io$RDY_get_timer_interrupt_req_get ;
assign near_mem_io$EN_get_sw_interrupt_req_get =
near_mem_io$RDY_get_sw_interrupt_req_get ;
// submodule plic
assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ;
assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ;
assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ;
assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ;
assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ;
assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ;
assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ;
assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ;
assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ;
assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ;
assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ;
assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ;
assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ;
assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ;
assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ;
assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ;
assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ;
assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ;
assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ;
assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ;
assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ;
assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ;
assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ;
assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ;
assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ;
assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ;
assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ;
assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ;
assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ;
assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ;
assign plic$set_verbosity_verbosity = 4'h0 ;
assign plic$v_sources_0_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ;
assign plic$v_sources_10_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ;
assign plic$v_sources_11_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ;
assign plic$v_sources_12_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ;
assign plic$v_sources_13_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ;
assign plic$v_sources_14_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ;
assign plic$v_sources_15_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ;
assign plic$v_sources_1_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ;
assign plic$v_sources_2_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ;
assign plic$v_sources_3_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ;
assign plic$v_sources_4_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ;
assign plic$v_sources_5_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ;
assign plic$v_sources_6_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ;
assign plic$v_sources_7_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ;
assign plic$v_sources_8_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ;
assign plic$v_sources_9_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ;
assign plic$EN_set_verbosity = 1'b0 ;
assign plic$EN_show_PLIC_state = 1'b0 ;
assign plic$EN_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign plic$EN_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 =
plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset &&
cpu$RDY_hart0_server_reset_request_put &&
f_reset_reqs$EMPTY_N ;
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
begin
v__h4601 = $stime;
#0;
end
v__h4595 = v__h4601 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
$display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4595);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
begin
v__h4817 = $stime;
#0;
end
v__h4811 = v__h4817 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
$display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4811);
end
// synopsys translate_on
endmodule |
module \$__inpad (input I, output O);
PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
endmodule |
module \$__outpad (input I, output O);
PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
endmodule |
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
// VT: This is not consistent and ACE will complain: assign Y = ~A[0];
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
end else
if (WIDTH == 2) begin
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
end else
if(WIDTH == 3) begin
LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
end else
if(WIDTH == 4) begin
LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule |
module \$_DFF_P_ (input D, C, output Q);
DFF _TECHMAP_REPLACE_
(.q(Q), .d(D), .ck(C));
endmodule |
module sky130_fd_sc_hs__sdfstp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_s_pg `UNIT_DELAY u_df_p_s_pg0 (buf_Q , mux_out, CLK, SET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule |
module outputs
wire [69 : 0] deq;
wire [1 : 0] notEmpty, notFull;
// inlined wires
wire [2 : 0] inputVCQueues_ifc_mf_ifc_new_head$wget,
inputVCQueues_ifc_mf_ifc_new_tail$wget;
wire [1 : 0] inputVCQueues_ifc_mf_ifc_rdFIFO$wget,
inputVCQueues_ifc_mf_ifc_wrFIFO$wget;
// register inputVCQueues_ifc_mf_ifc_heads
reg [2 : 0] inputVCQueues_ifc_mf_ifc_heads;
wire [2 : 0] inputVCQueues_ifc_mf_ifc_heads$D_IN;
wire inputVCQueues_ifc_mf_ifc_heads$EN;
// register inputVCQueues_ifc_mf_ifc_heads_1
reg [2 : 0] inputVCQueues_ifc_mf_ifc_heads_1;
wire [2 : 0] inputVCQueues_ifc_mf_ifc_heads_1$D_IN;
wire inputVCQueues_ifc_mf_ifc_heads_1$EN;
// register inputVCQueues_ifc_mf_ifc_not_empty
reg inputVCQueues_ifc_mf_ifc_not_empty;
wire inputVCQueues_ifc_mf_ifc_not_empty$D_IN,
inputVCQueues_ifc_mf_ifc_not_empty$EN;
// register inputVCQueues_ifc_mf_ifc_not_empty_1
reg inputVCQueues_ifc_mf_ifc_not_empty_1;
wire inputVCQueues_ifc_mf_ifc_not_empty_1$D_IN,
inputVCQueues_ifc_mf_ifc_not_empty_1$EN;
// register inputVCQueues_ifc_mf_ifc_not_full
reg inputVCQueues_ifc_mf_ifc_not_full;
wire inputVCQueues_ifc_mf_ifc_not_full$D_IN,
inputVCQueues_ifc_mf_ifc_not_full$EN;
// register inputVCQueues_ifc_mf_ifc_not_full_1
reg inputVCQueues_ifc_mf_ifc_not_full_1;
wire inputVCQueues_ifc_mf_ifc_not_full_1$D_IN,
inputVCQueues_ifc_mf_ifc_not_full_1$EN;
// register inputVCQueues_ifc_mf_ifc_tails
reg [2 : 0] inputVCQueues_ifc_mf_ifc_tails;
wire [2 : 0] inputVCQueues_ifc_mf_ifc_tails$D_IN;
wire inputVCQueues_ifc_mf_ifc_tails$EN;
// register inputVCQueues_ifc_mf_ifc_tails_1
reg [2 : 0] inputVCQueues_ifc_mf_ifc_tails_1;
wire [2 : 0] inputVCQueues_ifc_mf_ifc_tails_1$D_IN;
wire inputVCQueues_ifc_mf_ifc_tails_1$EN;
// ports of submodule inputVCQueues_ifc_mf_ifc_fifoMem
wire [69 : 0] inputVCQueues_ifc_mf_ifc_fifoMem$D_IN,
inputVCQueues_ifc_mf_ifc_fifoMem$D_OUT;
wire [3 : 0] inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_IN,
inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_OUT;
wire inputVCQueues_ifc_mf_ifc_fifoMem$WE;
// remaining internal signals
wire [2 : 0] fifoRdPtr__h4019,
fifoWrPtr__h3549,
x__h2444,
x__h3036,
y__h2445,
y__h3037;
wire IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89,
IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88,
IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58,
IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36,
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38,
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41,
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d43,
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d60,
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d63,
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d65,
inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d52,
inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d54,
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30,
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32;
// actionvalue method deq
assign deq = inputVCQueues_ifc_mf_ifc_fifoMem$D_OUT ;
// value method notEmpty
assign notEmpty =
{ inputVCQueues_ifc_mf_ifc_not_empty_1,
inputVCQueues_ifc_mf_ifc_not_empty } ;
// value method notFull
assign notFull =
{ inputVCQueues_ifc_mf_ifc_not_full_1,
inputVCQueues_ifc_mf_ifc_not_full } ;
// submodule inputVCQueues_ifc_mf_ifc_fifoMem
RegFile_1port #( /*data_width*/ 32'd70,
/*addr_width*/ 32'd4) inputVCQueues_ifc_mf_ifc_fifoMem(.CLK(CLK),
.rst_n(RST_N),
.ADDR_IN(inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_IN),
.ADDR_OUT(inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_OUT),
.D_IN(inputVCQueues_ifc_mf_ifc_fifoMem$D_IN),
.WE(inputVCQueues_ifc_mf_ifc_fifoMem$WE),
.D_OUT(inputVCQueues_ifc_mf_ifc_fifoMem$D_OUT));
// inlined wires
assign inputVCQueues_ifc_mf_ifc_wrFIFO$wget = { 1'd1, enq_fifo_in } ;
assign inputVCQueues_ifc_mf_ifc_rdFIFO$wget = { 1'd1, deq_fifo_out } ;
assign inputVCQueues_ifc_mf_ifc_new_tail$wget = fifoWrPtr__h3549 + 3'd1 ;
assign inputVCQueues_ifc_mf_ifc_new_head$wget = fifoRdPtr__h4019 + 3'd1 ;
// register inputVCQueues_ifc_mf_ifc_heads
assign inputVCQueues_ifc_mf_ifc_heads$D_IN = x__h3036 ;
assign inputVCQueues_ifc_mf_ifc_heads$EN =
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
!inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
// register inputVCQueues_ifc_mf_ifc_heads_1
assign inputVCQueues_ifc_mf_ifc_heads_1$D_IN = x__h3036 ;
assign inputVCQueues_ifc_mf_ifc_heads_1$EN =
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
// register inputVCQueues_ifc_mf_ifc_not_empty
assign inputVCQueues_ifc_mf_ifc_not_empty$D_IN =
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32 ;
assign inputVCQueues_ifc_mf_ifc_not_empty$EN =
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32 ||
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d63 ;
// register inputVCQueues_ifc_mf_ifc_not_empty_1
assign inputVCQueues_ifc_mf_ifc_not_empty_1$D_IN =
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30 ;
assign inputVCQueues_ifc_mf_ifc_not_empty_1$EN =
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30 ||
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d60 ;
// register inputVCQueues_ifc_mf_ifc_not_full
assign inputVCQueues_ifc_mf_ifc_not_full$D_IN =
!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
!NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41 ;
assign inputVCQueues_ifc_mf_ifc_not_full$EN =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41 ||
inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d54 ;
// register inputVCQueues_ifc_mf_ifc_not_full_1
assign inputVCQueues_ifc_mf_ifc_not_full_1$D_IN =
!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
!NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38 ;
assign inputVCQueues_ifc_mf_ifc_not_full_1$EN =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38 ||
inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d52 ;
// register inputVCQueues_ifc_mf_ifc_tails
assign inputVCQueues_ifc_mf_ifc_tails$D_IN = x__h2444 ;
assign inputVCQueues_ifc_mf_ifc_tails$EN =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
!inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
// register inputVCQueues_ifc_mf_ifc_tails_1
assign inputVCQueues_ifc_mf_ifc_tails_1$D_IN = x__h2444 ;
assign inputVCQueues_ifc_mf_ifc_tails_1$EN =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
// submodule inputVCQueues_ifc_mf_ifc_fifoMem
assign inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_IN =
{ enq_fifo_in, fifoWrPtr__h3549 } ;
assign inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_OUT =
{ deq_fifo_out, fifoRdPtr__h4019 } ;
assign inputVCQueues_ifc_mf_ifc_fifoMem$D_IN = enq_data_in ;
assign inputVCQueues_ifc_mf_ifc_fifoMem$WE = EN_enq ;
// remaining internal signals
assign IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89 =
deq_fifo_out ?
!inputVCQueues_ifc_mf_ifc_not_empty_1 :
!inputVCQueues_ifc_mf_ifc_not_empty ;
assign IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88 =
enq_fifo_in ?
!inputVCQueues_ifc_mf_ifc_not_full_1 :
!inputVCQueues_ifc_mf_ifc_not_full ;
assign IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 =
x__h3036 == y__h3037 ;
assign IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 =
x__h2444 == y__h2445 ;
assign NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38 =
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 &&
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
assign NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41 =
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 &&
!inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
assign NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d43 =
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 ;
assign NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d60 =
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 &&
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
assign NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d63 =
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 &&
!inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
assign NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d65 =
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 ;
assign fifoRdPtr__h4019 =
deq_fifo_out ?
inputVCQueues_ifc_mf_ifc_heads_1 :
inputVCQueues_ifc_mf_ifc_heads ;
assign fifoWrPtr__h3549 =
enq_fifo_in ?
inputVCQueues_ifc_mf_ifc_tails_1 :
inputVCQueues_ifc_mf_ifc_tails ;
assign inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d52 =
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
assign inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d54 =
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
!inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
assign inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30 =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
assign inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32 =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
!inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
assign x__h2444 = EN_enq ? inputVCQueues_ifc_mf_ifc_new_tail$wget : 3'd0 ;
assign x__h3036 = EN_deq ? inputVCQueues_ifc_mf_ifc_new_head$wget : 3'd0 ;
assign y__h2445 =
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ?
inputVCQueues_ifc_mf_ifc_heads_1 :
inputVCQueues_ifc_mf_ifc_heads ;
assign y__h3037 =
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ?
inputVCQueues_ifc_mf_ifc_tails_1 :
inputVCQueues_ifc_mf_ifc_tails ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
inputVCQueues_ifc_mf_ifc_heads <= `BSV_ASSIGNMENT_DELAY 3'd0;
inputVCQueues_ifc_mf_ifc_heads_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inputVCQueues_ifc_mf_ifc_not_empty <= `BSV_ASSIGNMENT_DELAY 1'd0;
inputVCQueues_ifc_mf_ifc_not_empty_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
inputVCQueues_ifc_mf_ifc_not_full <= `BSV_ASSIGNMENT_DELAY 1'd1;
inputVCQueues_ifc_mf_ifc_not_full_1 <= `BSV_ASSIGNMENT_DELAY 1'd1;
inputVCQueues_ifc_mf_ifc_tails <= `BSV_ASSIGNMENT_DELAY 3'd0;
inputVCQueues_ifc_mf_ifc_tails_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (inputVCQueues_ifc_mf_ifc_heads$EN)
inputVCQueues_ifc_mf_ifc_heads <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_heads$D_IN;
if (inputVCQueues_ifc_mf_ifc_heads_1$EN)
inputVCQueues_ifc_mf_ifc_heads_1 <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_heads_1$D_IN;
if (inputVCQueues_ifc_mf_ifc_not_empty$EN)
inputVCQueues_ifc_mf_ifc_not_empty <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_not_empty$D_IN;
if (inputVCQueues_ifc_mf_ifc_not_empty_1$EN)
inputVCQueues_ifc_mf_ifc_not_empty_1 <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_not_empty_1$D_IN;
if (inputVCQueues_ifc_mf_ifc_not_full$EN)
inputVCQueues_ifc_mf_ifc_not_full <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_not_full$D_IN;
if (inputVCQueues_ifc_mf_ifc_not_full_1$EN)
inputVCQueues_ifc_mf_ifc_not_full_1 <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_not_full_1$D_IN;
if (inputVCQueues_ifc_mf_ifc_tails$EN)
inputVCQueues_ifc_mf_ifc_tails <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_tails$D_IN;
if (inputVCQueues_ifc_mf_ifc_tails_1$EN)
inputVCQueues_ifc_mf_ifc_tails_1 <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_tails_1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
inputVCQueues_ifc_mf_ifc_heads = 3'h2;
inputVCQueues_ifc_mf_ifc_heads_1 = 3'h2;
inputVCQueues_ifc_mf_ifc_not_empty = 1'h0;
inputVCQueues_ifc_mf_ifc_not_empty_1 = 1'h0;
inputVCQueues_ifc_mf_ifc_not_full = 1'h0;
inputVCQueues_ifc_mf_ifc_not_full_1 = 1'h0;
inputVCQueues_ifc_mf_ifc_tails = 3'h2;
inputVCQueues_ifc_mf_ifc_tails_1 = 3'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N)
if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88)
$write("");
if (RST_N)
if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88)
$write("");
if (RST_N)
if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88)
$display("Dynamic assertion failed: \"MultiFIFOMem.bsv\", line 156, column 38\nEnqueing to full FIFO in MultiFIFOMem!");
if (RST_N)
if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88)
$finish(32'd0);
if (RST_N) if (EN_enq) $write("");
if (RST_N)
if (EN_deq && IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89)
$display("Dynamic assertion failed: \"MultiFIFOMem.bsv\", line 190, column 40\nDequeing from empty FIFO in MultiFIFOMem!");
if (RST_N)
if (EN_deq && IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89)
$finish(32'd0);
if (RST_N) if (EN_deq) $write("");
if (RST_N)
if (EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d43)
$write("");
if (RST_N)
if (EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d65)
$write("");
end
// synopsys translate_on
endmodule |
module system_ov7670_controller_1_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule |
module system_ov7670_controller_1_0_ov7670_controller
(config_finished,
siod,
xclk,
sioc,
resend,
clk);
output config_finished;
output siod;
output xclk;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire sys_clk_i_1_n_0;
wire taken;
wire xclk;
system_ov7670_controller_1_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_1_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
LUT1 #(
.INIT(2'h1))
sys_clk_i_1
(.I0(xclk),
.O(sys_clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
sys_clk_reg
(.C(clk),
.CE(1'b1),
.D(sys_clk_i_1_n_0),
.Q(xclk),
.R(1'b0));
endmodule |
module system_ov7670_controller_1_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule |
module system_ov7670_controller_1_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
wire xclk;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_1_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod),
.xclk(xclk));
VCC VCC
(.P(\<const1> ));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module tmu2_geninterp18(
input sys_clk,
input load,
input next_point,
input signed [17:0] init,
input positive,
input [16:0] q,
input [16:0] r,
input [16:0] divisor,
output signed [17:0] o
);
reg positive_r;
reg [16:0] q_r;
reg [16:0] r_r;
reg [16:0] divisor_r;
always @(posedge sys_clk) begin
if(load) begin
positive_r <= positive;
q_r <= q;
r_r <= r;
divisor_r <= divisor;
end
end
reg [17:0] err;
reg correct;
reg signed [17:0] o_r;
assign o = o_r;
always @(posedge sys_clk) begin
if(load) begin
err = 18'd0;
o_r = init;
end else if(next_point) begin
err = err + r_r;
correct = (err[16:0] > {1'b0, divisor_r[16:1]}) & ~err[17];
if(positive_r) begin
o_r = o_r + {1'b0, q_r};
if(correct)
o_r = o_r + 18'd1;
end else begin
o_r = o_r - {1'b0, q_r};
if(correct)
o_r = o_r - 18'd1;
end
if(correct)
err = err - {1'b0, divisor_r};
end
end
endmodule |
module proj1_testbench;
//Inputs: Regs
//Out: Wires
reg A;
reg B;
wire out;
reg select;
reg clk;
toplevel DUT(A, B, select, out, clk);
always
#5 clk=~clk;
initial begin
select = 1'b0;
clk = 1'b0;
A = 1'b0;
B = 1'b0;
end
always @(posedge clk)
begin
if (select) select <= 0;
else select <= 1;
end
endmodule |
module sky130_fd_sc_ls__udp_pwrgood_pp$PG (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule |
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ls__dlxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule |
module RIOT(A, // Address bus input
Din, // Data bus input
Dout, // Data bus output
CS, // Chip select input
CS_n, // Active low chip select input
R_W_n, // Active low read/write input
RS_n, // Active low rom select input
RES_n, // Active low reset input
IRQ_n, // Active low interrupt output
CLK, // Clock input
PAin, // 8 bit port A input
PAout, // 8 bit port A output
PBin, // 8 bit port B input
PBout);// 8 bit port B output
input [6:0] A;
input [7:0] Din;
output [7:0] Dout;
input CS, CS_n, R_W_n, RS_n, RES_n, CLK;
output IRQ_n;
input [7:0] PAin, PBin;
output [7:0] PAout, PBout; // Output register
reg [7:0] Dout; // RAM allocation
reg [7:0] RAM[127:0]; // I/O registers
reg [7:0] DRA, DRB; // Data registers
reg [7:0] DDRA, DDRB; // Data direction registers
wire PA7;
reg R_PA7;
assign PA7 = (PAin[7] & ~DDRA[7]) | (DRA[7] & DDRA[7]);
assign PAout = DRA & DDRA;
assign PBout = DRB & DDRB;
// Timer registers
reg [8:0] Timer;
reg [9:0] Prescaler;
reg [1:0] Timer_Mode;
reg Timer_Int_Flag, PA7_Int_Flag, Timer_Int_Enable, PA7_Int_Enable, PA7_Int_Mode; // Timer prescaler constants
wire [9:0] PRESCALER_VALS[3:0];
assign PRESCALER_VALS[0] = 10'd0;
assign PRESCALER_VALS[1] = 10'd7;
assign PRESCALER_VALS[2] = 10'd63;
assign PRESCALER_VALS[3] = 10'd1023;
// Interrupt
assign IRQ_n = ~(Timer_Int_Flag & Timer_Int_Enable | PA7_Int_Flag & PA7_Int_Enable);
// Operation decoding
wire [6:0] op;
reg [6:0] R_op;
assign op = {RS_n, R_W_n, A[4:0]};
// Registered data in
reg [7:0] R_Din;
integer cnt;
// Software operations
always @(posedge CLK)
begin
// Reset operation
if (~RES_n) begin
DRA <= 8'b0;
DDRA <= 8'b0;
DRB <= 8'b0;
DDRB <= 8'b0;
Timer_Int_Flag <= 1'b0;
PA7_Int_Flag <= 1'b0;
PA7_Int_Enable <= 1'b0;
PA7_Int_Mode <= 1'b0;
// Fill RAM with 0s
for (cnt = 0; cnt < 128; cnt = cnt + 1)
RAM[cnt] <= 8'b0;
R_PA7 <= 1'b0;
R_op <= `NOP;
R_Din <= 8'b0;
end
// If the chip is enabled, execute an operation
else if (CS & ~CS_n) begin
// Register inputs for use later
R_PA7 <= PA7;
R_op <= op;
R_Din <= Din;
// Update the timer interrupt flag
casex (op)
`WRITE_TIMER: Timer_Int_Flag <= 1'b0;
`READ_TIMER: Timer_Int_Flag <= 1'b0;
default: if (Timer == 9'b111111111) Timer_Int_Flag <= 1'b1;
endcase
// Update the port A interrupt flag
casex (op)
`READ_INT_FLAG: PA7_Int_Flag <= 1'b0;
default: PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode);
endcase
// Process the current operation
casex(op) // RAM access
`READ_RAM: Dout <= RAM[A];
`WRITE_RAM: RAM[A] <= Din;
// Port A data access
`READ_DRA : Dout <= (PAin & ~DDRA) | (DRA & DDRA);
`WRITE_DRA: DRA <= Din;
// Port A direction register access
`READ_DDRA: Dout <= DDRA;
`WRITE_DDRA: DDRA <= Din;
// Port B data access
`READ_DRB: Dout <= (PBin & ~DDRB) | (DRB & DDRB);
`WRITE_DRB: DRB <= Din;
// Port B direction register access
`READ_DDRB: Dout <= DDRB;
`WRITE_DDRB: DDRB <= Din;
// Timer access
`READ_TIMER: Dout <= Timer[7:0];
// Status register access
`READ_INT_FLAG: Dout <= {Timer_Int_Flag, PA7_Int_Flag, 6'b0};
// Enable the port A interrupt
`WRITE_EDGE_DETECT: begin
PA7_Int_Mode <= A[0]; PA7_Int_Enable <= A[1];
end
endcase
end
// Even if the chip is not enabled, update background functions
else begin
// Update the timer interrupt
if (Timer == 9'b111111111)
Timer_Int_Flag <= 1'b1;
// Update the port A interrupt
R_PA7 <= PA7;
PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode);
// Set the operation to a NOP
R_op <=`NOP;
end
end
// Update the timer at the negative edge of the clock
always @(negedge CLK)begin
// Reset operation
if (~RES_n) begin
Timer <= 9'b0;
Timer_Mode <= 2'b0;
Prescaler <= 10'b0;
Timer_Int_Enable <= 1'b0;
end
// Otherwise, process timer operations
else
casex
(R_op)
// Write value to the timer and update the prescaler based on the address
`WRITE_TIMER:begin
Timer <= {1'b0, R_Din};
Timer_Mode <= R_op[1:0];
Prescaler <= PRESCALER_VALS[R_op[1:0]];
Timer_Int_Enable <= R_op[3];
end
// Otherwise decrement the prescaler and if necessary the timer.
// The prescaler holds a variable number of counts that must be
// run before the timer is decremented
default:if (Timer != 9'b100000000) begin
if (Prescaler != 10'b0)
Prescaler <= Prescaler - 10'b1;
else begin
if (Timer == 9'b0)
begin
Prescaler <= 10'b0;
Timer_Mode <= 2'b0;
end
else
Prescaler <= PRESCALER_VALS[Timer_Mode];
Timer <= Timer - 9'b1;
end
end
endcase
end
endmodule |
module sineTable #(
parameter ANGLE_WIDTH = 12,
parameter OUT_WIDTH = 18
) (
input wire clk, ///< System Clock
input wire [ANGLE_WIDTH-1:0] angle, ///< Angle to take sine of
output reg signed [OUT_WIDTH-1:0] sine ///< Sine of angle
);
///////////////////////////////////////////////////////////////////////////
// PARAMETER AND SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
localparam TABLE_LEN = 2**(ANGLE_WIDTH-2);
wire [ANGLE_WIDTH-3:0] quarterAngle;
reg [OUT_WIDTH-2:0] sineTable [TABLE_LEN-1:0];
reg signBit;
reg [OUT_WIDTH-2:0] halfSine;
integer i;
///////////////////////////////////////////////////////////////////////////
// MAIN CODE
///////////////////////////////////////////////////////////////////////////
assign quarterAngle = (angle[ANGLE_WIDTH-2]) ? ~angle[ANGLE_WIDTH-3:0] : angle[ANGLE_WIDTH-3:0];
initial begin
signBit = 1'b0;
halfSine = 'd0;
sine = 'd0;
for(i=0; i<TABLE_LEN; i=i+1) begin
sineTable[i] = $rtoi($floor($sin((i+0.5)*3.14159/(TABLE_LEN*2))*(2**(OUT_WIDTH-1)-1)+0.5));
end
end
always @(posedge clk) begin
signBit <= angle[ANGLE_WIDTH-1];
halfSine <= sineTable[quarterAngle];
sine <= signBit ? -$signed({1'b0,halfSine}) : $signed({1'b0, halfSine});
end
endmodule |
module Image_viewer_top(ClkPort,
Hsync, Vsync, vgaRed, vgaGreen, vgaBlue,
MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE,
MemAdr, data,
An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp, Led,
btnC, btnR, btnL, btnU, btnD
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input ClkPort;
output MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE;
output [26:1] MemAdr;
inout [15:0] data;
//Button
input btnC, btnR, btnL, btnU, btnD;
//Light/Display
output An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp;
output Vsync, Hsync;
output [2:0] vgaRed;
output [2:0] vgaGreen;
output [2:1] vgaBlue;
output [1:0] Led;
reg [2:0] _vgaRed;
reg [2:0] _vgaGreen;
reg [1:0] _vgaBlue;
wire inDisplayArea;
wire [9:0] CounterX;
wire [9:0] CounterY;
reg [5:0] bitCounter;
assign vgaRed = _vgaRed;
assign vgaGreen = _vgaGreen;
assign vgaBlue = _vgaBlue;
assign Led = readImage;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
//Global Stuff
wire ClkPort, sys_clk, Reset;
reg [26:0] DIV_CLK;
assign sys_clk = ClkPort;
assign MemClk = DIV_CLK[0];
//Memory Stuff
reg [22:0] address;
reg [15:0] dataRegister[0:127];
reg [22:0] imageRegister[0:3];
always@(posedge sys_clk)
begin
imageRegister[2'b00][22:0] <= 23'b00000000000000000000000;
imageRegister[2'b01][22:0] <= 23'b00000000000000010000000;
imageRegister[2'b10][22:0] <= 23'b00000000000000100000000;
imageRegister[2'b11][22:0] <= 23'b00000000000000110000000;
end
wire [7:0] uByte;
wire [7:0] lByte;
reg [1:0] readImage;
reg [6:0] readAddress;
reg [6:0] writePointer;
reg [6:0] readRow;
assign uByte = data[15:8];
assign lByte = data[7:0];
//Button Stuff
wire BtnR_Pulse, BtnL_Pulse, BtnU_Pulse, BtnD_Pulse;
assign Reset = btnC;
//-------------------------------------------------------------------//
always @ (posedge sys_clk, posedge Reset)
begin : CLOCK_DIVIDER
if (Reset)
DIV_CLK <= 0;
else
DIV_CLK <= DIV_CLK + 1;
end
//--------------------Debounce Controllers--------------------//
ee201_debouncer #(.N_dc(20)) ee201_debouncer_left
(.CLK(MemClk), .RESET(Reset), .PB(btnL), .DPB( ),
.SCEN(BtnL_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_right
(.CLK(MemClk), .RESET(Reset), .PB(btnR), .DPB( ),
.SCEN(BtnR_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_up
(.CLK(MemClk), .RESET(Reset), .PB(btnU), .DPB( ),
.SCEN(BtnU_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_down
(.CLK(MemClk), .RESET(Reset), .PB(btnD), .DPB( ),
.SCEN(BtnD_Pulse), .MCEN( ), .CCEN( ));
//--------------------Display Controller--------------------//
DisplayCtrl display (.Clk(DIV_CLK), .reset(Reset), .memoryData(dataRegister[readRow][15:0]),
.An0(An0), .An1(An1), .An2(An2), .An3(An3),
.Ca(Ca), .Cb(Cb), .Cc(Cc), .Cd(Cd), .Ce(Ce), .Cf(Cf), .Cg(Cg), .Dp(Dp)
);
//--------------------Memory Controller--------------------//
MemoryCtrl memory(.Clk(MemClk), .Reset(Reset), .MemAdr(MemAdr), .MemOE(MemOE), .MemWR(MemWR),
.RamCS(RamCS), .RamUB(RamUB), .RamLB(RamLB), .RamAdv(RamAdv), .RamCRE(RamCRE), .writeData(writeData),
.AddressIn(address), .BtnU_Pulse(BtnU_Pulse), .BtnD_Pulse(BtnD_Pulse)
);
//--------------------VGA Controller--------------------//
VGACtrl vga(.clk(DIV_CLK[1]), .reset(Reset), .vga_h_sync(Hsync),
.vga_v_sync(Vsync), .inDisplayArea(inDisplayArea),
.CounterX(CounterX), .CounterY(CounterY)
);
reg toggleByte;
always @(posedge DIV_CLK[1], posedge Reset)
begin
if(Reset)
begin
bitCounter <= 0;
toggleByte <= 0;
readAddress <= 0;
end
else if(CounterY > 192 && CounterY < 288)
begin
if(CounterX == 0)
begin
bitCounter <= 0;
toggleByte <= 1'b0;
end
else if(CounterX > 284 && bitCounter < 35)
begin
if(toggleByte == 1'b0)
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][7:0];
toggleByte <= 1'b1;
end
else
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][15:8];
toggleByte <= 1'b0;
bitCounter <= bitCounter + 1;
readAddress <= readAddress + 1;
end
end
else
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= 0;
end
end
else if (CounterY == 288)
readAddress <= 0;
end
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
readImage <= 0;
else if(BtnU_Pulse)
readImage <= readImage + 1;
else if(BtnD_Pulse)
readImage <= readImage - 1;
else
address <= imageRegister[readImage][22:0];
end
//--------------------Process Data--------------------//
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
begin
writePointer <= 0;
end
else
if(writeData == 1'b1)
begin
dataRegister[writePointer][15:0] <= {lByte, uByte};
writePointer <= writePointer + 1;
end
else
writePointer <= 0;
end
//--------------------SSD Display Data--------------------//
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
readRow <= 0;
else if(BtnR_Pulse)
readRow <= readRow + 1;
else if(BtnL_Pulse)
readRow <= readRow - 1;
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(In0, In1, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],dout[1:0]" */;
input [0:0]In0;
input [0:0]In1;
output [1:0]dout;
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [1:0] [3:0] [3:0] array_simp; // big endian array
logic [3:0] array_oned;
initial begin
array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
if (array_oned != 4'b0101) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if (array_simp[0] !== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if (array_simp[0] !== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//if (array_simp[0] !== 16'h3210) $stop;
//array_simp[0] = '{ 1:4'd3, default:13};
//if (array_simp[0] !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if (array_simp !== 32'h3210_1234) $stop;
// IEEE says '{} allowed only on assignments, not !=, ==.
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if (array_simp !== 32'h3210_3210) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if (array_simp !== 32'h3333_3333) $stop;
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
$write("*-* All Finished *-*\n");
$finish;
end
//====================
// parameters for array sizes
localparam WA = 4; // address dimension size
localparam WB = 4; // bit dimension size
localparam NO = 11; // number of access events
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_bg <= '0;
else if (cnt[30:2]== 1) array_bg <= '0;
else if (cnt[30:2]== 2) array_bg <= '0;
else if (cnt[30:2]== 3) array_bg <= '0;
else if (cnt[30:2]== 4) array_bg <= '0;
else if (cnt[30:2]== 5) array_bg <= '0;
else if (cnt[30:2]== 6) array_bg <= '0;
else if (cnt[30:2]== 7) array_bg <= '0;
else if (cnt[30:2]== 8) array_bg <= '0;
else if (cnt[30:2]== 9) array_bg <= '0;
else if (cnt[30:2]==10) array_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_bg <= '{default:13};
else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7};
else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13};
else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 6) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_lt <= '0;
else if (cnt[30:2]== 1) array_lt <= '0;
else if (cnt[30:2]== 2) array_lt <= '0;
else if (cnt[30:2]== 3) array_lt <= '0;
else if (cnt[30:2]== 4) array_lt <= '0;
else if (cnt[30:2]== 5) array_lt <= '0;
else if (cnt[30:2]== 6) array_lt <= '0;
else if (cnt[30:2]== 7) array_lt <= '0;
else if (cnt[30:2]== 8) array_lt <= '0;
else if (cnt[30:2]== 9) array_lt <= '0;
else if (cnt[30:2]==10) array_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_lt <= '{default:13};
else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7};
else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13};
else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end
end
endmodule |
module top_tb;
// Inputs
reg ClkPort;
reg btnC;
reg btnR;
reg btnL;
// Outputs
wire Hsync;
wire Vsync;
wire [2:0] vgaRed;
wire [2:0] vgaGreen;
wire [2:1] vgaBlue;
wire MemOE;
wire MemWR;
wire MemClk;
wire RamCS;
wire RamUB;
wire RamLB;
wire RamAdv;
wire RamCRE;
wire [26:1] MemAdr;
wire An0;
wire An1;
wire An2;
wire An3;
wire Ca;
wire Cb;
wire Cc;
wire Cd;
wire Ce;
wire Cf;
wire Cg;
wire Dp;
wire [1:0] Led;
// Bidirs
wire [15:0] data;
// Instantiate the Unit Under Test (UUT)
Image_viewer_top uut (
.ClkPort(ClkPort),
.Hsync(Hsync),
.Vsync(Vsync),
.vgaRed(vgaRed),
.vgaGreen(vgaGreen),
.vgaBlue(vgaBlue),
.MemOE(MemOE),
.MemWR(MemWR),
.MemClk(MemClk),
.RamCS(RamCS),
.RamUB(RamUB),
.RamLB(RamLB),
.RamAdv(RamAdv),
.RamCRE(RamCRE),
.MemAdr(MemAdr),
.data(data),
.An0(An0),
.An1(An1),
.An2(An2),
.An3(An3),
.Ca(Ca),
.Cb(Cb),
.Cc(Cc),
.Cd(Cd),
.Ce(Ce),
.Cf(Cf),
.Cg(Cg),
.Dp(Dp),
.Led(Led),
.btnC(btnC),
.btnR(btnR),
.btnL(btnL)
);
initial
begin
ClkPort = 0;
forever
#5 ClkPort = ~ClkPort;
end
initial begin
// Initialize Inputs
btnC = 1;
btnR = 0;
btnL = 0;
// Wait 100 ns for global reset to finish
#100;
btnC = 0;
// Add stimulus here
end
endmodule |
module sky130_fd_sc_lp__and4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hd__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule |
module ymplayer(
input clk50,
input rst,
// sound
output reg speaker_left,
output reg speaker_right,
// switches
input [3:0] sw_sel, //
input send_data, // 1=Send music over UART, 0=stop
// UART wires
input uart_rx,
output uart_tx,
output [7:0] led
);
wire locked, rst_clk, rst_clk50;
// Send data
reg [9:0] send_data_shr;
wire send_data_s = &send_data_shr;
always @(posedge clk50)
send_data_shr <= { send_data_shr[8:0], send_data };
wire E, Q, clk_dac;
clocks u_clocks(
.rst ( rst ),
.clk50 ( clk50 ),
.locked ( locked ),
.divide_more( send_data_s ),
//.clk_cpu( clk ),
.clk_dac( clk_dac ),
.clk_dac_sel( sw_sel[1] ),
.E ( E ),
.Q ( Q )
);
wire cpu_rw;
wire AVMA;
//wire BS, BA, BUSY, LIC;
wire clk_per = E; // mc6809i
wire cpu_rst_req;
rst_sync u_rst1(
.rst_in ( rst|(~locked)|cpu_rst_req ),
.clk ( Q ),
.rst_out( rst_clk )
);
/*
rst_sync u_rst2(
.rst_in ( rst_clk ),
.clk ( clk_dac ),
.rst_out( rst_fast )
);
*/
rst_sync u_rst50(
.rst_in ( rst|(~locked) ),
.clk ( clk50 ),
.rst_out( rst_clk50 )
);
wire [7:0] cpu_data_in, cpu_data_out;
wire [15:0] cpu_addr;
wire [7:0]jt_data_out;
wire jt_sample;
// JT51
`ifndef NOJT
wire signed [15:0] direct_l, direct_r;
jt51 u_jt51(
.clk ( clk_per ),
.rst ( rst_clk ),
.cs_n ( jt_cs_n ), // chip select
.wr_n ( cpu_rw ), // write
.a0 ( cpu_addr[0] ),
.d_in ( cpu_data_out ), // data in
.d_out ( jt_data_out ), // data out
.irq_n ( jt_irq_n ),
// uso salidas exactas para el DAC
.sample ( jt_sample ),
.xleft ( direct_l ),
.xright ( direct_r )
);
wire [15:0] inter_l, inter_r;
jt51_interpol i_jt51_interpol (
.clk (clk50 ),
.rst (rst ),
.sample_in (jt_sample ),
.left_in (direct_l ),
.right_in (direct_r ),
.left_other (16'd0 ),
.right_other(16'd0 ),
.out_l (inter_l ),
.out_r (inter_r ),
.sample_out (fir_sample )
);
reg [15:0] dacin_l, dacin_r;
always @(posedge clk_dac)
if( sw_sel[2] ) begin
dacin_l <= inter_l;
dacin_r <= inter_r;
end
else begin
dacin_l <= direct_l;
dacin_r <= direct_r;
end
wire dac2_l, dac2_r;
wire dacmist_l, dacmist_r;
speaker u_speaker(
.clk100 ( clk_dac ),
.left_in ( dacin_l ),
.right_in ( dacin_r ),
.left_out ( dacmist_l ),
.right_out ( dacmist_r )
);
always @(posedge clk_per)
if( sw_sel[3] ) begin
speaker_left <= dac2_l;
speaker_right<= dac2_r;
end
else begin
speaker_left<= dacmist_l;
speaker_right<=dacmist_r;
end
jt51_dac2 i_jt51_dac2_l (.clk(clk_dac), .rst(rst), .din(dacin_l), .dout(dac2_l));
jt51_dac2 i_jt51_dac2_r (.clk(clk_dac), .rst(rst), .din(dacin_r), .dout(dac2_r));
`else
wire jt_irq_n = 1'b1;
wire [15:0] dacin_l = 16'd0, dacin_r=16'd0;
`endif
parameter RAM_MSB = 10; // 10 for Contra;
wire [7:0] ROM_data_out, RAM_data;
wire fsm_wr;
wire [ 7:0] fsm_data;
wire [14:0] fsm_addr;
wire rom_prog;
//synthesis attribute box_type ram32 "black_box"
ram32 ROM( // 32kb
.clka ( clk_per ),
.dina ( fsm_data ),
.wea ( fsm_wr ),
.douta ( ROM_data_out ),
.addra ( rom_prog ? fsm_addr : cpu_addr[14:0])
);
//synthesis attribute box_type ram2 "black_box"
ram2 RAM( // 2kb
.clka ( clk_per ),
.dina ( cpu_data_out ),
.douta ( RAM_data ),
.addra ( cpu_addr[RAM_MSB:0] ),
.ena ( RAM_cs ),
.wea ( ~cpu_rw )
);
wire [7:0] sound_latch;
wire clear_irq;
assign led = rom_prog ? fsm_addr[14:7] : sound_latch;
fsm_control fsm_ctrl(
.clk ( clk50 ),
.clk_cpu ( E ),
.rst ( rst_clk50 ),
// Sound
.sound_latch(sound_latch),
.jt_left ( dacin_l ),
.jt_right ( dacin_r ),
.jt_sample ( jt_sample ),
.irq ( irq ),
.clear_irq ( clear_irq ),
// Programming
.cpu_rst ( cpu_rst_req),
.rom_prog ( rom_prog ),
.rom_wr ( fsm_wr ),
.rom_addr ( fsm_addr ),
.rom_data ( fsm_data ),
// UART wires
.uart_rx ( uart_rx ),
.uart_tx ( uart_tx )
);
reg cpu_vma;
always @(negedge E)
cpu_vma <= AVMA;
bus_manager #(RAM_MSB) bus_mng(
// .rst50 ( rst_clk50 ),
// .clk50 ( clk50 ),
// .clk_per ( clk_per ),
.game_sel ( sw_sel[0] ),
.ROM_data_out ( ROM_data_out ),
.RAM_data ( RAM_data ),
.sound_latch ( sound_latch ),
.clear_irq ( clear_irq ),
// .cpu_data_out ( cpu_data_out ),
.jt_data_out ( jt_data_out ),
//
.cpu_data_in ( cpu_data_in ),
.cpu_rw ( cpu_rw ),
.addr ( cpu_addr ),
.cpu_vma ( cpu_vma ),
.RAM_cs ( RAM_cs ),
.opm_cs_n ( jt_cs_n )
);
`ifndef NOCPU
wire cpu_firq_n = sw_sel[0] ? jt_irq_n : 1'b1;
mc6809i cpu_good(
.D ( cpu_data_in ),
.DOut ( cpu_data_out ),
.ADDR ( cpu_addr ),
.RnW ( cpu_rw ),
// .BS ( BS ),
// .BA ( BA ),
.nIRQ ( ~irq ),
.nFIRQ ( cpu_firq_n ),
.nNMI ( 1'b1 ),
.AVMA ( AVMA ),
// .BUSY ( BUSY ),
// .LIC ( LIC ),
.nRESET ( ~rst_clk ),
.nHALT ( 1'b1 ),
.nDMABREQ( 1'b1 ),
.E ( E ),
.Q ( Q )
);
`endif
endmodule |
module mac_scale
(input wire signed [39:0] to_scaling,
input wire [2:0] c_scalefactor,
output wire scale_overflow,
output reg [39:0] from_scaling);
reg scale_pos_overflow;
reg scale_neg_overflow;
assign scale_overflow = scale_neg_overflow | scale_pos_overflow;
// Mux for scaling
always@(*) begin
scale_pos_overflow = 0;
scale_neg_overflow = 0;
case (c_scalefactor)
3'b000: begin
from_scaling=to_scaling; // *1
end
3'b001: begin
from_scaling=to_scaling << 1; // *2
scale_pos_overflow = ~to_scaling[39] & to_scaling[38];
scale_neg_overflow = to_scaling[39] & ~to_scaling[38];
end
3'b010: begin
from_scaling=to_scaling << 2; // *4
scale_pos_overflow = ~to_scaling[39] & (|to_scaling[38:37]);
scale_neg_overflow = to_scaling[39] & ~(&to_scaling[38:37]);
end
3'b011: begin
from_scaling={to_scaling[39],to_scaling[39:1]}; // *0.5
end
3'b100: begin
from_scaling={{2{to_scaling[39]}},to_scaling[39:2]}; // *0.25
end
3'b101: begin
from_scaling={{3{to_scaling[39]}},to_scaling[39:3]}; // *0.125
end
3'b110: begin
from_scaling={{4{to_scaling[39]}},to_scaling[39:4]}; // *0.0625
end
3'b111: begin
from_scaling=to_scaling << 16; // *2^16
scale_pos_overflow = ~to_scaling[39] & (|to_scaling[38:23]);
scale_neg_overflow = to_scaling[39] & ~(&to_scaling[38:23]);
end
endcase
end
endmodule |
module FifoCore32w8r(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full,
prog_empty
);
input rst;
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
output prog_full;
output prog_empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(8),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(511),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(512),
.C_PROG_EMPTY_TYPE(1),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(384),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(383),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(11),
.C_RD_DEPTH(2048),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(11),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_FULL(prog_full),
.PROG_EMPTY(prog_empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule |
module axi_ad9234_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [63:0] adc_data;
input adc_or;
// channel interface
output [63:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad9234_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
assign adc_dfmt_data = adc_data;
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule |
module wb_intercon
(input wb_clk_i,
input wb_rst_i,
input [31:0] wb_iwmb_adr_i,
input [31:0] wb_iwmb_dat_i,
input [3:0] wb_iwmb_sel_i,
input wb_iwmb_we_i,
input wb_iwmb_cyc_i,
input wb_iwmb_stb_i,
input [2:0] wb_iwmb_cti_i,
input [1:0] wb_iwmb_bte_i,
output [31:0] wb_iwmb_dat_o,
output wb_iwmb_ack_o,
output wb_iwmb_err_o,
output wb_iwmb_rty_o,
input [31:0] wb_dwmb_adr_i,
input [31:0] wb_dwmb_dat_i,
input [3:0] wb_dwmb_sel_i,
input wb_dwmb_we_i,
input wb_dwmb_cyc_i,
input wb_dwmb_stb_i,
input [2:0] wb_dwmb_cti_i,
input [1:0] wb_dwmb_bte_i,
output [31:0] wb_dwmb_dat_o,
output wb_dwmb_ack_o,
output wb_dwmb_err_o,
output wb_dwmb_rty_o,
output [31:0] wb_uart_adr_o,
output [31:0] wb_uart_dat_o,
output [3:0] wb_uart_sel_o,
output wb_uart_we_o,
output wb_uart_cyc_o,
output wb_uart_stb_o,
output [2:0] wb_uart_cti_o,
output [1:0] wb_uart_bte_o,
input [31:0] wb_uart_dat_i,
input wb_uart_ack_i,
input wb_uart_err_i,
input wb_uart_rty_i,
output [31:0] wb_ram_adr_o,
output [31:0] wb_ram_dat_o,
output [3:0] wb_ram_sel_o,
output wb_ram_we_o,
output wb_ram_cyc_o,
output wb_ram_stb_o,
output [2:0] wb_ram_cti_o,
output [1:0] wb_ram_bte_o,
input [31:0] wb_ram_dat_i,
input wb_ram_ack_i,
input wb_ram_err_i,
input wb_ram_rty_i,
output [31:0] wb_rom_adr_o,
output [31:0] wb_rom_dat_o,
output [3:0] wb_rom_sel_o,
output wb_rom_we_o,
output wb_rom_cyc_o,
output wb_rom_stb_o,
output [2:0] wb_rom_cti_o,
output [1:0] wb_rom_bte_o,
input [31:0] wb_rom_dat_i,
input wb_rom_ack_i,
input wb_rom_err_i,
input wb_rom_rty_i,
output [31:0] wb_fw_interface_adr_o,
output [31:0] wb_fw_interface_dat_o,
output [3:0] wb_fw_interface_sel_o,
output wb_fw_interface_we_o,
output wb_fw_interface_cyc_o,
output wb_fw_interface_stb_o,
output [2:0] wb_fw_interface_cti_o,
output [1:0] wb_fw_interface_bte_o,
input [31:0] wb_fw_interface_dat_i,
input wb_fw_interface_ack_i,
input wb_fw_interface_err_i,
input wb_fw_interface_rty_i);
wire [31:0] wb_m2s_iwmb_ram_adr;
wire [31:0] wb_m2s_iwmb_ram_dat;
wire [3:0] wb_m2s_iwmb_ram_sel;
wire wb_m2s_iwmb_ram_we;
wire wb_m2s_iwmb_ram_cyc;
wire wb_m2s_iwmb_ram_stb;
wire [2:0] wb_m2s_iwmb_ram_cti;
wire [1:0] wb_m2s_iwmb_ram_bte;
wire [31:0] wb_s2m_iwmb_ram_dat;
wire wb_s2m_iwmb_ram_ack;
wire wb_s2m_iwmb_ram_err;
wire wb_s2m_iwmb_ram_rty;
wire [31:0] wb_m2s_iwmb_rom_adr;
wire [31:0] wb_m2s_iwmb_rom_dat;
wire [3:0] wb_m2s_iwmb_rom_sel;
wire wb_m2s_iwmb_rom_we;
wire wb_m2s_iwmb_rom_cyc;
wire wb_m2s_iwmb_rom_stb;
wire [2:0] wb_m2s_iwmb_rom_cti;
wire [1:0] wb_m2s_iwmb_rom_bte;
wire [31:0] wb_s2m_iwmb_rom_dat;
wire wb_s2m_iwmb_rom_ack;
wire wb_s2m_iwmb_rom_err;
wire wb_s2m_iwmb_rom_rty;
wire [31:0] wb_m2s_iwmb_uart_adr;
wire [31:0] wb_m2s_iwmb_uart_dat;
wire [3:0] wb_m2s_iwmb_uart_sel;
wire wb_m2s_iwmb_uart_we;
wire wb_m2s_iwmb_uart_cyc;
wire wb_m2s_iwmb_uart_stb;
wire [2:0] wb_m2s_iwmb_uart_cti;
wire [1:0] wb_m2s_iwmb_uart_bte;
wire [31:0] wb_s2m_iwmb_uart_dat;
wire wb_s2m_iwmb_uart_ack;
wire wb_s2m_iwmb_uart_err;
wire wb_s2m_iwmb_uart_rty;
wire [31:0] wb_m2s_iwmb_fw_interface_adr;
wire [31:0] wb_m2s_iwmb_fw_interface_dat;
wire [3:0] wb_m2s_iwmb_fw_interface_sel;
wire wb_m2s_iwmb_fw_interface_we;
wire wb_m2s_iwmb_fw_interface_cyc;
wire wb_m2s_iwmb_fw_interface_stb;
wire [2:0] wb_m2s_iwmb_fw_interface_cti;
wire [1:0] wb_m2s_iwmb_fw_interface_bte;
wire [31:0] wb_s2m_iwmb_fw_interface_dat;
wire wb_s2m_iwmb_fw_interface_ack;
wire wb_s2m_iwmb_fw_interface_err;
wire wb_s2m_iwmb_fw_interface_rty;
wire [31:0] wb_m2s_dwmb_uart_adr;
wire [31:0] wb_m2s_dwmb_uart_dat;
wire [3:0] wb_m2s_dwmb_uart_sel;
wire wb_m2s_dwmb_uart_we;
wire wb_m2s_dwmb_uart_cyc;
wire wb_m2s_dwmb_uart_stb;
wire [2:0] wb_m2s_dwmb_uart_cti;
wire [1:0] wb_m2s_dwmb_uart_bte;
wire [31:0] wb_s2m_dwmb_uart_dat;
wire wb_s2m_dwmb_uart_ack;
wire wb_s2m_dwmb_uart_err;
wire wb_s2m_dwmb_uart_rty;
wire [31:0] wb_m2s_dwmb_ram_adr;
wire [31:0] wb_m2s_dwmb_ram_dat;
wire [3:0] wb_m2s_dwmb_ram_sel;
wire wb_m2s_dwmb_ram_we;
wire wb_m2s_dwmb_ram_cyc;
wire wb_m2s_dwmb_ram_stb;
wire [2:0] wb_m2s_dwmb_ram_cti;
wire [1:0] wb_m2s_dwmb_ram_bte;
wire [31:0] wb_s2m_dwmb_ram_dat;
wire wb_s2m_dwmb_ram_ack;
wire wb_s2m_dwmb_ram_err;
wire wb_s2m_dwmb_ram_rty;
wire [31:0] wb_m2s_dwmb_rom_adr;
wire [31:0] wb_m2s_dwmb_rom_dat;
wire [3:0] wb_m2s_dwmb_rom_sel;
wire wb_m2s_dwmb_rom_we;
wire wb_m2s_dwmb_rom_cyc;
wire wb_m2s_dwmb_rom_stb;
wire [2:0] wb_m2s_dwmb_rom_cti;
wire [1:0] wb_m2s_dwmb_rom_bte;
wire [31:0] wb_s2m_dwmb_rom_dat;
wire wb_s2m_dwmb_rom_ack;
wire wb_s2m_dwmb_rom_err;
wire wb_s2m_dwmb_rom_rty;
wire [31:0] wb_m2s_dwmb_fw_interface_adr;
wire [31:0] wb_m2s_dwmb_fw_interface_dat;
wire [3:0] wb_m2s_dwmb_fw_interface_sel;
wire wb_m2s_dwmb_fw_interface_we;
wire wb_m2s_dwmb_fw_interface_cyc;
wire wb_m2s_dwmb_fw_interface_stb;
wire [2:0] wb_m2s_dwmb_fw_interface_cti;
wire [1:0] wb_m2s_dwmb_fw_interface_bte;
wire [31:0] wb_s2m_dwmb_fw_interface_dat;
wire wb_s2m_dwmb_fw_interface_ack;
wire wb_s2m_dwmb_fw_interface_err;
wire wb_s2m_dwmb_fw_interface_rty;
wb_mux
#(.num_slaves (4),
.MATCH_ADDR ({32'h20000000, 32'h00000000, 32'h40000000, 32'he0000000}),
.MATCH_MASK ({32'hffff8000, 32'hffff8000, 32'hffffffe0, 32'hffffff80}))
wb_mux_iwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_iwmb_adr_i),
.wbm_dat_i (wb_iwmb_dat_i),
.wbm_sel_i (wb_iwmb_sel_i),
.wbm_we_i (wb_iwmb_we_i),
.wbm_cyc_i (wb_iwmb_cyc_i),
.wbm_stb_i (wb_iwmb_stb_i),
.wbm_cti_i (wb_iwmb_cti_i),
.wbm_bte_i (wb_iwmb_bte_i),
.wbm_dat_o (wb_iwmb_dat_o),
.wbm_ack_o (wb_iwmb_ack_o),
.wbm_err_o (wb_iwmb_err_o),
.wbm_rty_o (wb_iwmb_rty_o),
.wbs_adr_o ({wb_m2s_iwmb_ram_adr, wb_m2s_iwmb_rom_adr, wb_m2s_iwmb_uart_adr, wb_m2s_iwmb_fw_interface_adr}),
.wbs_dat_o ({wb_m2s_iwmb_ram_dat, wb_m2s_iwmb_rom_dat, wb_m2s_iwmb_uart_dat, wb_m2s_iwmb_fw_interface_dat}),
.wbs_sel_o ({wb_m2s_iwmb_ram_sel, wb_m2s_iwmb_rom_sel, wb_m2s_iwmb_uart_sel, wb_m2s_iwmb_fw_interface_sel}),
.wbs_we_o ({wb_m2s_iwmb_ram_we, wb_m2s_iwmb_rom_we, wb_m2s_iwmb_uart_we, wb_m2s_iwmb_fw_interface_we}),
.wbs_cyc_o ({wb_m2s_iwmb_ram_cyc, wb_m2s_iwmb_rom_cyc, wb_m2s_iwmb_uart_cyc, wb_m2s_iwmb_fw_interface_cyc}),
.wbs_stb_o ({wb_m2s_iwmb_ram_stb, wb_m2s_iwmb_rom_stb, wb_m2s_iwmb_uart_stb, wb_m2s_iwmb_fw_interface_stb}),
.wbs_cti_o ({wb_m2s_iwmb_ram_cti, wb_m2s_iwmb_rom_cti, wb_m2s_iwmb_uart_cti, wb_m2s_iwmb_fw_interface_cti}),
.wbs_bte_o ({wb_m2s_iwmb_ram_bte, wb_m2s_iwmb_rom_bte, wb_m2s_iwmb_uart_bte, wb_m2s_iwmb_fw_interface_bte}),
.wbs_dat_i ({wb_s2m_iwmb_ram_dat, wb_s2m_iwmb_rom_dat, wb_s2m_iwmb_uart_dat, wb_s2m_iwmb_fw_interface_dat}),
.wbs_ack_i ({wb_s2m_iwmb_ram_ack, wb_s2m_iwmb_rom_ack, wb_s2m_iwmb_uart_ack, wb_s2m_iwmb_fw_interface_ack}),
.wbs_err_i ({wb_s2m_iwmb_ram_err, wb_s2m_iwmb_rom_err, wb_s2m_iwmb_uart_err, wb_s2m_iwmb_fw_interface_err}),
.wbs_rty_i ({wb_s2m_iwmb_ram_rty, wb_s2m_iwmb_rom_rty, wb_s2m_iwmb_uart_rty, wb_s2m_iwmb_fw_interface_rty}));
wb_mux
#(.num_slaves (4),
.MATCH_ADDR ({32'h40000000, 32'h20000000, 32'h00000000, 32'he0000000}),
.MATCH_MASK ({32'hffffffe0, 32'hffff8000, 32'hffff8000, 32'hffffff80}))
wb_mux_dwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_dwmb_adr_i),
.wbm_dat_i (wb_dwmb_dat_i),
.wbm_sel_i (wb_dwmb_sel_i),
.wbm_we_i (wb_dwmb_we_i),
.wbm_cyc_i (wb_dwmb_cyc_i),
.wbm_stb_i (wb_dwmb_stb_i),
.wbm_cti_i (wb_dwmb_cti_i),
.wbm_bte_i (wb_dwmb_bte_i),
.wbm_dat_o (wb_dwmb_dat_o),
.wbm_ack_o (wb_dwmb_ack_o),
.wbm_err_o (wb_dwmb_err_o),
.wbm_rty_o (wb_dwmb_rty_o),
.wbs_adr_o ({wb_m2s_dwmb_uart_adr, wb_m2s_dwmb_ram_adr, wb_m2s_dwmb_rom_adr, wb_m2s_dwmb_fw_interface_adr}),
.wbs_dat_o ({wb_m2s_dwmb_uart_dat, wb_m2s_dwmb_ram_dat, wb_m2s_dwmb_rom_dat, wb_m2s_dwmb_fw_interface_dat}),
.wbs_sel_o ({wb_m2s_dwmb_uart_sel, wb_m2s_dwmb_ram_sel, wb_m2s_dwmb_rom_sel, wb_m2s_dwmb_fw_interface_sel}),
.wbs_we_o ({wb_m2s_dwmb_uart_we, wb_m2s_dwmb_ram_we, wb_m2s_dwmb_rom_we, wb_m2s_dwmb_fw_interface_we}),
.wbs_cyc_o ({wb_m2s_dwmb_uart_cyc, wb_m2s_dwmb_ram_cyc, wb_m2s_dwmb_rom_cyc, wb_m2s_dwmb_fw_interface_cyc}),
.wbs_stb_o ({wb_m2s_dwmb_uart_stb, wb_m2s_dwmb_ram_stb, wb_m2s_dwmb_rom_stb, wb_m2s_dwmb_fw_interface_stb}),
.wbs_cti_o ({wb_m2s_dwmb_uart_cti, wb_m2s_dwmb_ram_cti, wb_m2s_dwmb_rom_cti, wb_m2s_dwmb_fw_interface_cti}),
.wbs_bte_o ({wb_m2s_dwmb_uart_bte, wb_m2s_dwmb_ram_bte, wb_m2s_dwmb_rom_bte, wb_m2s_dwmb_fw_interface_bte}),
.wbs_dat_i ({wb_s2m_dwmb_uart_dat, wb_s2m_dwmb_ram_dat, wb_s2m_dwmb_rom_dat, wb_s2m_dwmb_fw_interface_dat}),
.wbs_ack_i ({wb_s2m_dwmb_uart_ack, wb_s2m_dwmb_ram_ack, wb_s2m_dwmb_rom_ack, wb_s2m_dwmb_fw_interface_ack}),
.wbs_err_i ({wb_s2m_dwmb_uart_err, wb_s2m_dwmb_ram_err, wb_s2m_dwmb_rom_err, wb_s2m_dwmb_fw_interface_err}),
.wbs_rty_i ({wb_s2m_dwmb_uart_rty, wb_s2m_dwmb_ram_rty, wb_s2m_dwmb_rom_rty, wb_s2m_dwmb_fw_interface_rty}));
wb_arbiter
#(.num_masters (2))
wb_arbiter_uart
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_uart_adr, wb_m2s_dwmb_uart_adr}),
.wbm_dat_i ({wb_m2s_iwmb_uart_dat, wb_m2s_dwmb_uart_dat}),
.wbm_sel_i ({wb_m2s_iwmb_uart_sel, wb_m2s_dwmb_uart_sel}),
.wbm_we_i ({wb_m2s_iwmb_uart_we, wb_m2s_dwmb_uart_we}),
.wbm_cyc_i ({wb_m2s_iwmb_uart_cyc, wb_m2s_dwmb_uart_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_uart_stb, wb_m2s_dwmb_uart_stb}),
.wbm_cti_i ({wb_m2s_iwmb_uart_cti, wb_m2s_dwmb_uart_cti}),
.wbm_bte_i ({wb_m2s_iwmb_uart_bte, wb_m2s_dwmb_uart_bte}),
.wbm_dat_o ({wb_s2m_iwmb_uart_dat, wb_s2m_dwmb_uart_dat}),
.wbm_ack_o ({wb_s2m_iwmb_uart_ack, wb_s2m_dwmb_uart_ack}),
.wbm_err_o ({wb_s2m_iwmb_uart_err, wb_s2m_dwmb_uart_err}),
.wbm_rty_o ({wb_s2m_iwmb_uart_rty, wb_s2m_dwmb_uart_rty}),
.wbs_adr_o (wb_uart_adr_o),
.wbs_dat_o (wb_uart_dat_o),
.wbs_sel_o (wb_uart_sel_o),
.wbs_we_o (wb_uart_we_o),
.wbs_cyc_o (wb_uart_cyc_o),
.wbs_stb_o (wb_uart_stb_o),
.wbs_cti_o (wb_uart_cti_o),
.wbs_bte_o (wb_uart_bte_o),
.wbs_dat_i (wb_uart_dat_i),
.wbs_ack_i (wb_uart_ack_i),
.wbs_err_i (wb_uart_err_i),
.wbs_rty_i (wb_uart_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_ram
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_ram_adr, wb_m2s_dwmb_ram_adr}),
.wbm_dat_i ({wb_m2s_iwmb_ram_dat, wb_m2s_dwmb_ram_dat}),
.wbm_sel_i ({wb_m2s_iwmb_ram_sel, wb_m2s_dwmb_ram_sel}),
.wbm_we_i ({wb_m2s_iwmb_ram_we, wb_m2s_dwmb_ram_we}),
.wbm_cyc_i ({wb_m2s_iwmb_ram_cyc, wb_m2s_dwmb_ram_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_ram_stb, wb_m2s_dwmb_ram_stb}),
.wbm_cti_i ({wb_m2s_iwmb_ram_cti, wb_m2s_dwmb_ram_cti}),
.wbm_bte_i ({wb_m2s_iwmb_ram_bte, wb_m2s_dwmb_ram_bte}),
.wbm_dat_o ({wb_s2m_iwmb_ram_dat, wb_s2m_dwmb_ram_dat}),
.wbm_ack_o ({wb_s2m_iwmb_ram_ack, wb_s2m_dwmb_ram_ack}),
.wbm_err_o ({wb_s2m_iwmb_ram_err, wb_s2m_dwmb_ram_err}),
.wbm_rty_o ({wb_s2m_iwmb_ram_rty, wb_s2m_dwmb_ram_rty}),
.wbs_adr_o (wb_ram_adr_o),
.wbs_dat_o (wb_ram_dat_o),
.wbs_sel_o (wb_ram_sel_o),
.wbs_we_o (wb_ram_we_o),
.wbs_cyc_o (wb_ram_cyc_o),
.wbs_stb_o (wb_ram_stb_o),
.wbs_cti_o (wb_ram_cti_o),
.wbs_bte_o (wb_ram_bte_o),
.wbs_dat_i (wb_ram_dat_i),
.wbs_ack_i (wb_ram_ack_i),
.wbs_err_i (wb_ram_err_i),
.wbs_rty_i (wb_ram_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_rom
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_rom_adr, wb_m2s_dwmb_rom_adr}),
.wbm_dat_i ({wb_m2s_iwmb_rom_dat, wb_m2s_dwmb_rom_dat}),
.wbm_sel_i ({wb_m2s_iwmb_rom_sel, wb_m2s_dwmb_rom_sel}),
.wbm_we_i ({wb_m2s_iwmb_rom_we, wb_m2s_dwmb_rom_we}),
.wbm_cyc_i ({wb_m2s_iwmb_rom_cyc, wb_m2s_dwmb_rom_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_rom_stb, wb_m2s_dwmb_rom_stb}),
.wbm_cti_i ({wb_m2s_iwmb_rom_cti, wb_m2s_dwmb_rom_cti}),
.wbm_bte_i ({wb_m2s_iwmb_rom_bte, wb_m2s_dwmb_rom_bte}),
.wbm_dat_o ({wb_s2m_iwmb_rom_dat, wb_s2m_dwmb_rom_dat}),
.wbm_ack_o ({wb_s2m_iwmb_rom_ack, wb_s2m_dwmb_rom_ack}),
.wbm_err_o ({wb_s2m_iwmb_rom_err, wb_s2m_dwmb_rom_err}),
.wbm_rty_o ({wb_s2m_iwmb_rom_rty, wb_s2m_dwmb_rom_rty}),
.wbs_adr_o (wb_rom_adr_o),
.wbs_dat_o (wb_rom_dat_o),
.wbs_sel_o (wb_rom_sel_o),
.wbs_we_o (wb_rom_we_o),
.wbs_cyc_o (wb_rom_cyc_o),
.wbs_stb_o (wb_rom_stb_o),
.wbs_cti_o (wb_rom_cti_o),
.wbs_bte_o (wb_rom_bte_o),
.wbs_dat_i (wb_rom_dat_i),
.wbs_ack_i (wb_rom_ack_i),
.wbs_err_i (wb_rom_err_i),
.wbs_rty_i (wb_rom_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_fw_interface
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_fw_interface_adr, wb_m2s_dwmb_fw_interface_adr}),
.wbm_dat_i ({wb_m2s_iwmb_fw_interface_dat, wb_m2s_dwmb_fw_interface_dat}),
.wbm_sel_i ({wb_m2s_iwmb_fw_interface_sel, wb_m2s_dwmb_fw_interface_sel}),
.wbm_we_i ({wb_m2s_iwmb_fw_interface_we, wb_m2s_dwmb_fw_interface_we}),
.wbm_cyc_i ({wb_m2s_iwmb_fw_interface_cyc, wb_m2s_dwmb_fw_interface_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_fw_interface_stb, wb_m2s_dwmb_fw_interface_stb}),
.wbm_cti_i ({wb_m2s_iwmb_fw_interface_cti, wb_m2s_dwmb_fw_interface_cti}),
.wbm_bte_i ({wb_m2s_iwmb_fw_interface_bte, wb_m2s_dwmb_fw_interface_bte}),
.wbm_dat_o ({wb_s2m_iwmb_fw_interface_dat, wb_s2m_dwmb_fw_interface_dat}),
.wbm_ack_o ({wb_s2m_iwmb_fw_interface_ack, wb_s2m_dwmb_fw_interface_ack}),
.wbm_err_o ({wb_s2m_iwmb_fw_interface_err, wb_s2m_dwmb_fw_interface_err}),
.wbm_rty_o ({wb_s2m_iwmb_fw_interface_rty, wb_s2m_dwmb_fw_interface_rty}),
.wbs_adr_o (wb_fw_interface_adr_o),
.wbs_dat_o (wb_fw_interface_dat_o),
.wbs_sel_o (wb_fw_interface_sel_o),
.wbs_we_o (wb_fw_interface_we_o),
.wbs_cyc_o (wb_fw_interface_cyc_o),
.wbs_stb_o (wb_fw_interface_stb_o),
.wbs_cti_o (wb_fw_interface_cti_o),
.wbs_bte_o (wb_fw_interface_bte_o),
.wbs_dat_i (wb_fw_interface_dat_i),
.wbs_ack_i (wb_fw_interface_ack_i),
.wbs_err_i (wb_fw_interface_err_i),
.wbs_rty_i (wb_fw_interface_rty_i));
endmodule |
module dmix_t;
// ins
reg rst;
reg clk;
parameter TCLK = 40;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg signal;
reg sck;
parameter TCLK_SCK = 80;
reg mosi;
reg ss;
parameter TclkSPDIF = 40; // 24.576MHz == 192Khz * 32 bit * 2 (biphase)
nkmdhpa uut(
.rst(rst),
.clk245760_pad(clk),
.spdif_i(signal),
.csr_sck(sck),
.csr_mosi(mosi),
.csr_ss(ss));
task recv_rawbit;
input b;
begin
signal = b;
#(TclkSPDIF);//*6);
end
endtask
task recv_B;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_M;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
end
end
endtask
task recv_W;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_bmcbit;
input b;
begin
if(signal) begin
if(b) begin
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(0);
recv_rawbit(0);
end
end else begin
if(b) begin
recv_rawbit(1);
recv_rawbit(0);
end else begin
recv_rawbit(1);
recv_rawbit(1);
end
end
end
endtask
task recv_bmcbyte;
input [7:0] byte;
begin
recv_bmcbit(byte[0]);
recv_bmcbit(byte[1]);
recv_bmcbit(byte[2]);
recv_bmcbit(byte[3]);
recv_bmcbit(byte[4]);
recv_bmcbit(byte[5]);
recv_bmcbit(byte[6]);
recv_bmcbit(byte[7]);
end
endtask
task recv_bmcctl;
begin
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
end
endtask
task recv_subframe;
input [23:0] data;
begin
recv_bmcbyte(data[7:0]);
recv_bmcbyte(data[15:8]);
recv_bmcbyte(data[23:16]);
recv_bmcctl();
end
endtask
task spi_cycle;
input [7:0] data;
begin
#(TCLK_SCK/2);
ss = 0;
#(TCLK_SCK/2);
mosi = data[7];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[6];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[5];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[4];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[3];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[2];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[1];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[0];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
#(TCLK_SCK/2);
ss = 1;
#(TCLK_SCK/2);
end
endtask
`define USE_CAPTURE
`define PROGCMD_LEN 112
reg [7:0] progcmd [(`PROGCMD_LEN-1):0];
initial $readmemh("progcmd.memh", progcmd);
reg replay_capture;
initial replay_capture = 1'b0;
integer i;
reg [22:0] counter;
initial begin
$dumpfile("nkmdhpa_t.lxt");
$dumpvars(0, uut);
rst = 1'b0;
signal = 0;
counter = 0;
mosi = 1'b0;
ss = 1'b1;
#(100);
rst = 1'b1;
#(200);
rst = 1'b0;
#(1500);
for (i = 0; i < `PROGCMD_LEN; i = i + 1) begin
spi_cycle(progcmd[i]);
end
#(100);
$display("--- NKMD dbgin");
#(TCLK*3);
spi_cycle({4'b1_11_0, 4'h6});
spi_cycle(8'h00); // offset
spi_cycle(8'h01);
spi_cycle(8'h02);
spi_cycle(8'h03);
spi_cycle(8'h04);
spi_cycle(8'h05);
spi_cycle(8'h06);
spi_cycle(8'h07);
spi_cycle(8'h08);
spi_cycle(8'h09);
spi_cycle(8'h0a);
spi_cycle(8'h0b);
spi_cycle(8'h0c);
spi_cycle(8'h0d);
spi_cycle(8'h0e);
spi_cycle(8'h0f);
spi_cycle(8'h10);
#(TCLK*3);
$display("--- NKMD rst => 0");
#(TCLK*3);
spi_cycle({4'b1_01_0, 4'h4});
spi_cycle(8'h00); // offset
spi_cycle(8'h00); // data
#(TCLK*3);
replay_capture = 1'b1;
#(30000);
$finish(2);
end
`ifndef USE_CAPTURE
always begin
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
$finish(2);
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
if (counter > 512)
$finish(2);
end
`else
reg [31:0] capture [262143:0];
integer capture_iter;
initial $readmemh("spdif_capture3", capture);
initial capture_iter = 0;
always begin
if (replay_capture) begin
signal = capture[capture_iter][2];
capture_iter = capture_iter + 1;
if (capture_iter > 262143)
$finish(2);
end
#(5);
end
`endif
endmodule |
module sky130_fd_sc_ms__a221o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__a221o_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule |
module watchdog(
input nLDS, RW,
input A23I, A22I,
input [21:17] M68K_ADDR_U,
//input [12:1] M68K_ADDR_L,
input WDCLK,
output nHALT,
output nRESET,
input nRST
);
reg [3:0] WDCNT;
initial
WDCNT <= 4'b0000;
// IMPORTANT:
// nRESET is an open-collector output on B1, so that the 68k can drive it (RESET instruction)
// The line has a 4.7k pullup (schematics page 1)
// nRESET changes state on posedge nBNKB (posedge mclk), but takes a slightly variable amount of time to
// return high after it is released. Low during 8 frames, released during 8 frames.
assign nRESET = nRST & ~WDCNT[3];
assign nHALT = nRESET;
// $300001 (LDS)
// 0011000xxxxxxxxxxxxxxxx1
// MAME says 00110001xxxxxxxxxxxxxxx1 but NEO-B1 doesn't have A16
assign WDRESET = &{nRST, ~|{nLDS, RW, A23I, A22I}, M68K_ADDR_U[21:20], ~|{M68K_ADDR_U[19:17]}};
always @(posedge WDCLK or posedge WDRESET or posedge ~nRST)
begin
if (WDRESET)
begin
WDCNT <= 4'b0000;
end
else if (!nRST)
begin
WDCNT <= 4'b1110; // DEBUG - Used to speed up simulation
//WDCNT <= 4'b1000; // Correct value
end
else
WDCNT <= WDCNT + 1'b1;
end
endmodule |
module fifo_over_ufc_tb
#(
parameter FIFO_DATA_WIDTH = 32,
parameter AURORA_DATA_WIDTH = 64
)
();
reg clk;
reg reset;
wire a_tx_req;
wire [7:0] a_tx_ms;
reg a_tx_tready;
wire [AURORA_DATA_WIDTH-1:0] a_tx_tdata;
wire a_tx_tvalid;
wire [AURORA_DATA_WIDTH-1:0] a_rx_tdata;
reg a_rx_tvalid;
wire fifo_clk;
wire [FIFO_DATA_WIDTH-1:0] tx_fifo_q;
wire tx_fifo_wren;
reg tx_fifo_full;
reg [FIFO_DATA_WIDTH-1:0] rx_fifo_q;
wire rx_fifo_rden;
reg rx_fifo_empty;
wire err;
fifo_over_ufc #(.FIFO_DATA_WIDTH(FIFO_DATA_WIDTH), .AURORA_DATA_WIDTH(AURORA_DATA_WIDTH))
uut
(
.RESET(reset),
.AURORA_USER_CLK(clk),
.AURORA_TX_REQ(a_tx_req),
.AURORA_TX_MS(a_tx_ms),
.AURORA_TX_TREADY(a_tx_tready),
.AURORA_TX_TDATA(a_tx_tdata),
.AURORA_TX_TVALID(a_tx_tvalid),
.AURORA_RX_TDATA(a_rx_tdata),
.AURORA_RX_TVALID(a_rx_tvalid),
.FIFO_CLK(fifo_clk),
.TX_FIFO_Q(tx_fifo_q),
.TX_FIFO_WREN(tx_fifo_wren),
.TX_FIFO_FULL(tx_fifo_full),
.RX_FIFO_Q(rx_fifo_q),
.RX_FIFO_RDEN(rx_fifo_rden),
.RX_FIFO_EMPTY(rx_fifo_empty),
.ERR(err)
);
//initial begin
//$dumpfile("fifo_over_ufc.vcd");
//$dumpvars(0, fifo_over_ufc);
//end
initial begin
clk = 0;
reset = 0;
#16 reset = 1;
#26 reset = 0;
#200 reset = 1;
#10 reset = 0;
end
always #5 clk = ~clk;
initial begin
rx_fifo_empty = 1;
a_rx_tvalid = 0;
tx_fifo_full = 0;
#46 rx_fifo_empty = 0;
#120 rx_fifo_empty = 1;
#40 a_rx_tvalid = 1;
#10 a_rx_tvalid = 0; tx_fifo_full = 1;
end
// emulate Aurora UFC interface
reg [1:0] state;
localparam S0 = 2'h0;
localparam S1 = 2'h1;
localparam S2 = 2'h2;
localparam S3 = 2'h3;
always @ (posedge clk or posedge reset) begin
if (reset) begin
state <= S0;
a_tx_tready <= 1;
end
else begin
a_tx_tready <= 1;
case (state)
S0: begin
state <= S0;
if (a_tx_req == 1) begin
state <= S1;
a_tx_tready <= 0;
end
end
S1: begin
state <= S2;
a_tx_tready <= 0;
end
S2: begin
state <= S3;
a_tx_tready <= 1;
end
S3: begin
state <= S3;
a_tx_tready <= 1;
if (a_tx_tvalid == 1) begin
state <= S0;
end
end
default: begin
state <= S0;
end
endcase
end
end
endmodule |
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module sky130_fd_sc_hs__bufbuf_16 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A)
);
endmodule |
module sky130_fd_sc_lp__buflp_m (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |