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module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module oh_iddr #(parameter DW = 1 // width of data inputs
)
(
input clk, // clock
input ce, // clock enable, set to high to clock in data
input [DW-1:0] din, // data input sampled on both edges of clock
output reg [DW-1:0] q1, // iddr rising edge sampled data
output reg [DW-1:0] q2 // iddr falling edge sampled data
);
//regs("sl"=stable low, "sh"=stable high)
reg [DW-1:0] q1_sl;
reg [DW-1:0] q2_sh;
// rising edge sample
always @ (posedge clk)
if(ce)
q1_sl[DW-1:0] <= din[DW-1:0];
// falling edge sample
always @ (negedge clk)
q2_sh[DW-1:0] <= din[DW-1:0];
// pipeline for alignment
always @ (posedge clk)
begin
q1[DW-1:0] <= q1_sl[DW-1:0];
q2[DW-1:0] <= q2_sh[DW-1:0];
end
endmodule |
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 UDP_IN = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 UDP_IN = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 UDP_IN = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 UDP_IN = 1'bx;
end
sky130_fd_sc_hvl__udp_pwrgood_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule |
module io_cpx_reqdata_ff(/*AUTOARG*/
// Outputs
io_cpx_data_ca2, io_cpx_req_cq2, scan_out,
// Inputs
io_cpx_data_ca, io_cpx_req_cq, rclk, scan_in, se
);
output [`CPX_WIDTH-1:0] io_cpx_data_ca2;
output [7:0] io_cpx_req_cq2;
output scan_out;
input [`CPX_WIDTH-1:0] io_cpx_data_ca;
input [7:0] io_cpx_req_cq;
input rclk;
input scan_in;
input se;
dff_s #(`CPX_WIDTH) dff_io_cpx_data(
.din (io_cpx_data_ca[`CPX_WIDTH-1:0]),
.q (io_cpx_data_ca2[`CPX_WIDTH-1:0]),
.clk (rclk),
.se (se),
.si (`CPX_WIDTH'd0),
.so ());
dff_s #(8) dff_cpx_datardy_io(
.din (io_cpx_req_cq[7:0]),
.q (io_cpx_req_cq2[7:0]),
.clk (rclk),
.se (se),
.si (8'd0),
.so ());
endmodule |
module sky130_fd_sc_hd__dfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module sky130_fd_sc_ms__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule |
module mwm20k
#( parameter WWID = 5 , // write width
parameter RWID = 40 , // read width
parameter WDEP = 4096, // write lines depth
parameter OREG = 0 , // read output reg
parameter INIT = 1 ) // initialize to zeros
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(WDEP)-1 :0] wAddr , // write address
input [WWID-1 :0] wData , // write data
input [`log2(WDEP/(RWID/WWID))-1:0] rAddr , // read address
output [RWID-1 :0] rData ); // read data
localparam RDEP = WDEP/(RWID/WWID); // read lines depth
localparam WAWID = `log2(WDEP) ; // write address width
localparam RAWID = `log2(RDEP) ; // read address width
// Altera's M20K mixed width RAM instantiation
altsyncram #( .address_aclr_b ("CLEAR0" ),
.address_reg_b ("CLOCK0" ),
.clock_enable_input_a ("BYPASS" ),
.clock_enable_input_b ("BYPASS" ),
.clock_enable_output_b ("BYPASS" ),
.intended_device_family ("Stratix V" ),
.lpm_type ("altsyncram" ),
.numwords_a (WDEP ),
.numwords_b (RDEP ),
.operation_mode ("DUAL_PORT" ),
.outdata_aclr_b ("CLEAR0" ),
.outdata_reg_b (OREG?"CLOCK0":"UNREGISTERED"),
.power_up_uninitialized (INIT?"FALSE":"TRUE"),
.ram_block_type ("M20K" ),
.read_during_write_mode_mixed_ports ("OLD_DATA" ),
.widthad_a (WAWID ),
.widthad_b (RAWID ),
.width_a (WWID ),
.width_b (RWID ),
.width_byteena_a (1 ))
altsyncm20k ( .aclr0 (rst ),
.address_a (wAddr ),
.clock0 (clk ),
.data_a (wData ),
.wren_a (wEnb ),
.address_b (rAddr ),
.q_b (rData ),
.aclr1 (1'b0 ),
.addressstall_a (1'b0 ),
.addressstall_b (1'b0 ),
.byteena_a (1'b1 ),
.byteena_b (1'b1 ),
.clock1 (1'b1 ),
.clocken0 (1'b1 ),
.clocken1 (1'b1 ),
.clocken2 (1'b1 ),
.clocken3 (1'b1 ),
.data_b ({RWID{1'b1}} ),
.eccstatus ( ),
.q_a ( ),
.rden_a (1'b1 ),
.rden_b (1'b1 ),
.wren_b (1'b0 ));
endmodule |
module wb_i2c (
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
inout scl,
inout sda
);
localparam ADDR_CONTROL = 32'h00000000;
localparam ADDR_STATUS = 32'h00000001;
localparam ADDR_CLOCK_RATE = 32'h00000002;
localparam ADDR_CLOCK_DIVIDER = 32'h00000003;
localparam ADDR_COMMAND = 32'h00000004;
localparam ADDR_TRANSMIT = 32'h00000005;
localparam ADDR_RECEIVE = 32'h00000006;
//Registers/Wires
reg [15:0] clock_divider;
reg [7:0] control;
reg [7:0] transmit;
wire [7:0] receive;
reg [7:0] command;
wire [7:0] status;
wire done;
//core enable signal
wire core_en;
wire ien;
//Control Register bits
wire start;
wire stop;
wire read;
wire write;
wire ack;
reg iack;
wire core_reset;
//Status Register
wire irxack;
reg rxack; //Received acknowledge from slave
reg tip; //Tranfer in progress
reg irq_flag; //interrupt pending flag
wire i2c_busy; //busy (start sigal detected)
wire i2c_al; //arbitration lost
reg al; //arbitration lost
//Assigns
//Command
assign start = command[0];
assign stop = command[1];
assign read = command[2];
assign write = command[3];
assign ack = command[4];
// Control
assign core_en = control[0];
assign ien = control[1];
assign set_100khz = control[2];
assign set_400khz = control[3];
assign core_reset = control[7];
// assign status register bits
assign status[7] = rxack;
assign status[6] = i2c_busy;
assign status[5] = al;
assign status[4:2] = 3'h0; // reserved
assign status[1] = tip;
assign status[0] = irq_flag;
assign scl = scl_oen ? 1'hZ : scl_out;
assign sda = sda_oen ? 1'hZ : sda_out;
i2c_master_byte_ctrl byte_controller (
.clk (clk ),
.rst (rst | core_reset ),
.nReset (1 ),
.ena (core_en ),
.clk_cnt (clock_divider ),
.start (start ),
.stop (stop ),
.read (read ),
.write (write ),
.ack_in (ack ),
.din (transmit ),
.cmd_ack (done ),
.ack_out (irxack ),
.dout (receive ),
.i2c_busy (i2c_busy ),
.i2c_al (i2c_al ),
.scl_i (scl ),
.scl_o (scl_out ),
.scl_oen (scl_oen ),
.sda_i (sda ),
.sda_o (sda_out ),
.sda_oen (sda_oen )
);
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
clock_divider <= `CLK_DIVIDE_100KHZ;
control <= 8'h01;
transmit <= 8'h00;
command <= 8'h00;
al <= 0;
rxack <= 0;
tip <= 0;
irq_flag <= 0;
iack <= 0;
end
else begin
iack <= 0;
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
//clear IRQ ACK bit
command[0] <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting something
o_wbs_int <= 0;
//acknowledge an interrupt
iack <= 1;
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_CONTROL: begin
control <= i_wbs_dat[7:0];
end
ADDR_CLOCK_DIVIDER: begin
clock_divider <= i_wbs_dat[15:0];
end
ADDR_COMMAND: begin
command <= i_wbs_dat[7:0];
end
ADDR_TRANSMIT: begin
transmit <= i_wbs_dat[7:0];
end
default: begin
end
endcase
end
else begin
//reset the interrupt when the user reads anything
//read request
case (i_wbs_adr)
ADDR_CONTROL: begin
o_wbs_dat <= {24'h000000, control};
end
ADDR_STATUS: begin
o_wbs_dat <= {24'h000000, status};
end
ADDR_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
ADDR_CLOCK_DIVIDER: begin
o_wbs_dat <= {16'h0000, clock_divider};
end
ADDR_COMMAND: begin
o_wbs_dat <= {24'h000000, command};
end
ADDR_TRANSMIT: begin
o_wbs_dat <= {24'h000000, transmit};
end
ADDR_RECEIVE: begin
o_wbs_dat <= {24'h000000, receive};
end
default: begin
o_wbs_dat <= 32'h0000000;
end
endcase
end
o_wbs_ack <= 1;
end
//clear the reserved bits
command[7:5] <= 2'b00;
if (set_100khz) begin
clock_divider <= `CLK_DIVIDE_100KHZ;
//reset the control so they don't keep firing off
control[2] <= 0;
control[3] <= 0;
end
if (set_400khz) begin
//reset the control so they don't keep firing off
clock_divider <= `CLK_DIVIDE_400KHZ;
control[2] <= 0;
control[3] <= 0;
end
if (core_reset) begin
control[7] <= 0;
end
//control/status
al <= i2c_al | (al & ~start);
rxack <= irxack;
tip <= (read | write);
irq_flag <= (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
if (irq_flag && ien) begin
//interrupt enable and irq_flag fired off
o_wbs_int <= 1;
end
//Handle Status/Control oneshots
if (done | i2c_al) begin
command[3:0] <= 4'h0;
end
end
end
endmodule |
module blk_mem_gen_0 (
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [8 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [63 : 0] doutb;
blk_mem_gen_v8_3_6 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("blk_mem_gen_0.mif"),
.C_INIT_FILE("blk_mem_gen_0.mem"),
.C_USE_DEFAULT_DATA(1),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(4000),
.C_READ_DEPTH_A(4000),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(64),
.C_READ_WIDTH_B(64),
.C_WRITE_DEPTH_B(500),
.C_READ_DEPTH_B(500),
.C_ADDRB_WIDTH(9),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 4.4085 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(enb),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(64'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule |
module aurora_64b66b_25p4G_RX_LL
(
//AXI4-Stream Interface
m_axi_rx_tdata,
m_axi_rx_tvalid,
m_axi_rx_tkeep,
m_axi_rx_tlast,
// Aurora Lane Interface
RX_PE_DATA,
RX_PE_DATA_V,
RX_SEP,
RX_SEP7,
RX_SEP_NB,
RXDATAVALID_TO_LL,
RX_CC,
RX_IDLE,
// Global Logic
CHANNEL_UP,
// System Interface
USER_CLK,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
//AXI4-Stream Interface
output [0:63] m_axi_rx_tdata;
output m_axi_rx_tvalid;
output [0:7] m_axi_rx_tkeep;
output m_axi_rx_tlast;
// Aurora Lane Interface
input [0:63] RX_PE_DATA;
input RX_PE_DATA_V;
input RX_SEP;
input RX_SEP7;
input [0:2] RX_SEP_NB;
input RX_CC;
input RXDATAVALID_TO_LL;
input RX_IDLE;
// Global Logic
input CHANNEL_UP;
// System Interface
input USER_CLK;
input RESET;
//*********************************Main Body of Code**********************************
//____________________________RX LL Datapath _____________________________
aurora_64b66b_25p4G_RX_LL_DATAPATH rx_ll_datapath_i
(
// Aurora lane Interface
.RX_PE_DATA(RX_PE_DATA),
.RX_PE_DATA_V(RX_PE_DATA_V),
.RX_SEP(RX_SEP),
.RX_SEP7(RX_SEP7),
.RX_SEP_NB(RX_SEP_NB),
.RX_CC(RX_CC),
.RXDATAVALID_TO_LL(RXDATAVALID_TO_LL),
.RX_IDLE(RX_IDLE),
//Gobal Interface
.CHANNEL_UP(CHANNEL_UP),
//AXI4-Stream Interface
.m_axi_rx_tdata (m_axi_rx_tdata),
.m_axi_rx_tvalid (m_axi_rx_tvalid),
.m_axi_rx_tkeep (m_axi_rx_tkeep),
.m_axi_rx_tlast (m_axi_rx_tlast),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET)
);
endmodule |
module nukv_Value_Get #(
parameter KEY_WIDTH = 128,
parameter HEADER_WIDTH = 42, //vallen + val addr
parameter META_WIDTH = 96,
parameter MEMORY_WIDTH = 512,
parameter SUPPORT_SCANS = 0
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+HEADER_WIDTH+META_WIDTH-1:0] input_data,
input wire input_valid,
output reg input_ready,
input wire cond_drop,
input wire cond_valid,
output reg cond_ready,
input wire [MEMORY_WIDTH-1:0] value_data,
input wire value_valid,
output wire value_ready,
output wire [META_WIDTH+64-1:0] output_data,
output reg output_valid,
output reg output_last,
input wire output_ready,
input wire scan_mode
);
localparam [2:0]
ST_IDLE = 0,
ST_HEADER = 1,
ST_KEY = 2,
ST_VALUE = 3,
ST_DROP = 4;
reg [2:0] state;
reg [9:0] toread;
reg [3:0] idx;
reg hasvalue;
reg [63:0] meta_data;
reg [63:0] output_word;
reg flush;
reg dropit;
reg scanning;
reg[9:0] words_since_last;
reg must_last;
reg first_value_word;
wire[11:0] actual_value_len;
assign actual_value_len = (value_data[11:0]+7)/8;
assign value_ready = (idx==7 && output_valid==1 && output_ready==1 && state==ST_VALUE) ? 1 : flush;
assign output_data = {meta_data,output_word};
always @(posedge clk) begin
if (rst) begin
// reset
output_valid <= 0;
output_last <= 0;
input_ready <= 0;
flush <= 0;
cond_ready <= 0;
dropit <= 0;
scanning <= 0;
state <= ST_IDLE;
words_since_last <= 0;
must_last <= 0;
end
else begin
if (output_valid==1 && output_ready==1) begin
output_valid <= 0;
output_last <= 0;
end
if (SUPPORT_SCANS==1) begin
if (output_last==1 && output_valid==1 && output_ready==1) begin
words_since_last <= 1;
end else if (output_valid==1 && output_ready==1) begin
words_since_last <= words_since_last+1;
end
if (words_since_last>127) begin
must_last <= 1;
end else begin
must_last <= 0;
end
if (scanning==1 && scan_mode==0 && (output_valid!=1 || output_last!=1)) begin
output_valid <= 1;
output_last <= 1;
must_last <= 1;
words_since_last <= 128;
output_word <= 64'h00000000FEEBDAED;
end
end
input_ready <= 0;
cond_ready <= 0;
case (state)
ST_IDLE: begin
flush <= 0;
dropit <= 0;
scanning <= scan_mode;
if (flush==0 && output_ready==1) begin
if (input_valid==1 && (input_data[KEY_WIDTH+HEADER_WIDTH+META_WIDTH-7:KEY_WIDTH+HEADER_WIDTH+META_WIDTH-8]==2'b01 || input_data[KEY_WIDTH+HEADER_WIDTH+META_WIDTH-7:KEY_WIDTH+HEADER_WIDTH+META_WIDTH-8]==2'b10) ) begin
hasvalue <= 0;
state <= ST_HEADER;
meta_data <= input_data[KEY_WIDTH+HEADER_WIDTH +: META_WIDTH];
input_ready <= 1;
if (input_data[KEY_WIDTH +: 30]==0) begin
output_word <= {32'h0, 32'h0, 16'h0, 16'hffff};
end else begin
output_word <= {32'h0, 32'h0, 16'h1, 16'hffff};
end
output_valid <= 1;
end else if (input_valid==1 && (input_data[KEY_WIDTH+HEADER_WIDTH+META_WIDTH-7:KEY_WIDTH+HEADER_WIDTH+META_WIDTH-8]==2'b00 || (SUPPORT_SCANS==1 && input_data[KEY_WIDTH+HEADER_WIDTH+META_WIDTH-8 +: 4]==4'b1111))) begin
if (input_data[KEY_WIDTH+HEADER_WIDTH+META_WIDTH-8 +: 4]==4'b1000 || cond_valid==1 || input_data[KEY_WIDTH+31 +: 10]==0) begin
hasvalue <= (input_data[KEY_WIDTH+31 +: 10]==0) ? 0 : 1;
state <= ST_HEADER;
meta_data <= input_data[KEY_WIDTH+HEADER_WIDTH +: META_WIDTH];
if (SUPPORT_SCANS==1 && input_data[KEY_WIDTH+HEADER_WIDTH+META_WIDTH-8 +: 4]==4'b1111 && cond_drop==1) begin
output_word <= {32'h0, 32'h0, 16'h2, 16'hffff};
output_valid <= 0;
input_ready <= 1;
//jump over the header state to make sure we can process the input in two cycles, especially if it is a drop!
output_valid <= 1;
output_word <= 0;
first_value_word <= 1;
if (input_data[KEY_WIDTH+31 +: 10]!=0 && cond_drop==0) begin
state <= ST_VALUE;
end else if (input_data[KEY_WIDTH+31 +: 10]!=0 && cond_drop==1) begin
state <= ST_DROP;
output_valid <= 0;
flush <= 1;
output_last <= (SUPPORT_SCANS==1 && scanning==1) ? must_last : 1;
end else begin
output_last <= (SUPPORT_SCANS==1 && scanning==1) ? must_last : 1;
state <= ST_IDLE;
end
end else begin
if (input_data[KEY_WIDTH+31 +: 10]==0) begin
output_word <= {32'h0, 22'h0, input_data[KEY_WIDTH+31 +: 10], 16'h0, 16'hffff};
end else begin
output_word <= {32'h0, 22'h0, actual_value_len[9:0], 16'h1, 16'hffff};
end
if (input_data[KEY_WIDTH+31 +: 10]!=0) begin
//if (value_valid==1) begin
input_ready <= 1;
output_valid <= 1;
//end
end else begin
input_ready <= 1;
output_valid <= 1;
end
end
if (input_data[KEY_WIDTH+HEADER_WIDTH+META_WIDTH-8 +: 4]!=4'b1000 && input_data[KEY_WIDTH+31 +: 10]!=0) begin
cond_ready <= 1;
dropit <= cond_drop;
if (cond_drop==1) begin
output_word[32 +: 10] <= 0;
if (scanning==0) begin
output_last <= 1;
end
end
end
toread <= input_data[KEY_WIDTH+31 +: 10];
idx <= 0;
end
end else if (input_valid==1) begin
output_valid <= 1;
hasvalue <= 0;
state <= ST_HEADER;
meta_data <= input_data[KEY_WIDTH+HEADER_WIDTH +: META_WIDTH];
input_ready <= 1;
output_word <= {32'h0, 32'h0, 16'h0, 16'hffff};
end
end
end
ST_HEADER: begin
if (output_ready==1) begin
output_valid <= 1;
output_word <= 0;
first_value_word <= 1;
if (hasvalue==1 && toread>0 && dropit==0) begin
state <= ST_VALUE;
end else if (hasvalue==1 && toread>0 && dropit==1) begin
state <= ST_DROP;
output_valid <= 0;
output_last <= 0;
flush <= 1;
end else begin
output_last <= (SUPPORT_SCANS==1 && scanning==1) ? must_last : 1;
state <= ST_IDLE;
end
end
end
ST_VALUE: begin
if (output_ready==1 && value_valid==1) begin
first_value_word <= 0;
idx <= idx+1;
if (idx==7) begin
toread <= toread-8;
idx <= 0;
end
output_valid <= 1;
output_word <= value_data[idx*64 +: 64];
if (first_value_word==1 && value_data[15:0]<1024) begin
toread <= (value_data[15:0]+7)/8;
end else
if (toread<=8 && idx==toread-1) begin
state <= ST_IDLE;
output_last <= (SUPPORT_SCANS==1 && scanning==1) ? must_last : 1;
if (toread<8) begin
flush <= 1;
end
end
end
end
ST_DROP: begin
if (value_valid==1 && value_ready==1) begin
toread <= toread-8;
first_value_word <= 0;
if (first_value_word==1 && value_data[15:0]<1024) begin
toread <= (value_data[15:0]+7)/8-8;
if (((value_data[15:0]+7)/8)<=8) begin
flush <= 0;
state <= ST_IDLE;
end
end
else if (toread<=8) begin
flush <= 0;
state <= ST_IDLE;
end
end
end
endcase
end
end
endmodule |
module sky130_fd_sc_lp__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule |
module sram1024x18 (
clk_a,
cen_a,
wen_a,
addr_a,
wmsk_a,
wdata_a,
rdata_a,
clk_b,
cen_b,
wen_b,
addr_b,
wmsk_b,
wdata_b,
rdata_b
);
(* clkbuf_sink *)
input wire clk_a;
input wire cen_a;
input wire wen_a;
input wire [9:0] addr_a;
input wire [17:0] wmsk_a;
input wire [17:0] wdata_a;
output reg [17:0] rdata_a;
(* clkbuf_sink *)
input wire clk_b;
input wire cen_b;
input wire wen_b;
input wire [9:0] addr_b;
input wire [17:0] wmsk_b;
input wire [17:0] wdata_b;
output reg [17:0] rdata_b;
reg [17:0] ram [1023:0];
reg [9:0] laddr_a;
reg [9:0] laddr_b;
reg lcen_a;
reg lwen_a;
reg [17:0] lwdata_a;
reg lcen_b;
reg lwen_b;
reg [17:0] lwdata_b;
reg [17:0] lwmsk_a;
reg [17:0] lwmsk_b;
always @(posedge clk_a) begin
laddr_a <= addr_a;
lwdata_a <= wdata_a;
lwmsk_a <= wmsk_a;
lcen_a <= cen_a;
lwen_a <= wen_a;
end
always @(posedge clk_b) begin
laddr_b <= addr_b;
lwdata_b <= wdata_b;
lwmsk_b <= wmsk_b;
lcen_b <= cen_b;
lwen_b <= wen_b;
end
always @(*) begin
if ((lwen_b == 0) && (lcen_b == 0)) begin
ram[laddr_b][0] = (lwmsk_b[0] ? ram[laddr_b][0] : lwdata_b[0]);
ram[laddr_b][1] = (lwmsk_b[1] ? ram[laddr_b][1] : lwdata_b[1]);
ram[laddr_b][2] = (lwmsk_b[2] ? ram[laddr_b][2] : lwdata_b[2]);
ram[laddr_b][3] = (lwmsk_b[3] ? ram[laddr_b][3] : lwdata_b[3]);
ram[laddr_b][4] = (lwmsk_b[4] ? ram[laddr_b][4] : lwdata_b[4]);
ram[laddr_b][5] = (lwmsk_b[5] ? ram[laddr_b][5] : lwdata_b[5]);
ram[laddr_b][6] = (lwmsk_b[6] ? ram[laddr_b][6] : lwdata_b[6]);
ram[laddr_b][7] = (lwmsk_b[7] ? ram[laddr_b][7] : lwdata_b[7]);
ram[laddr_b][8] = (lwmsk_b[8] ? ram[laddr_b][8] : lwdata_b[8]);
ram[laddr_b][9] = (lwmsk_b[9] ? ram[laddr_b][9] : lwdata_b[9]);
ram[laddr_b][10] = (lwmsk_b[10] ? ram[laddr_b][10] : lwdata_b[10]);
ram[laddr_b][11] = (lwmsk_b[11] ? ram[laddr_b][11] : lwdata_b[11]);
ram[laddr_b][12] = (lwmsk_b[12] ? ram[laddr_b][12] : lwdata_b[12]);
ram[laddr_b][13] = (lwmsk_b[13] ? ram[laddr_b][13] : lwdata_b[13]);
ram[laddr_b][14] = (lwmsk_b[14] ? ram[laddr_b][14] : lwdata_b[14]);
ram[laddr_b][15] = (lwmsk_b[15] ? ram[laddr_b][15] : lwdata_b[15]);
ram[laddr_b][16] = (lwmsk_b[16] ? ram[laddr_b][16] : lwdata_b[16]);
ram[laddr_b][17] = (lwmsk_b[17] ? ram[laddr_b][17] : lwdata_b[17]);
lwen_b = 1;
end
if (lcen_b == 0) begin
rdata_b = ram[laddr_b];
lcen_b = 1;
end
else
rdata_b = rdata_b;
end
always @(*) begin
if ((lwen_a == 0) && (lcen_a == 0)) begin
ram[laddr_a][0] = (lwmsk_a[0] ? ram[laddr_a][0] : lwdata_a[0]);
ram[laddr_a][1] = (lwmsk_a[1] ? ram[laddr_a][1] : lwdata_a[1]);
ram[laddr_a][2] = (lwmsk_a[2] ? ram[laddr_a][2] : lwdata_a[2]);
ram[laddr_a][3] = (lwmsk_a[3] ? ram[laddr_a][3] : lwdata_a[3]);
ram[laddr_a][4] = (lwmsk_a[4] ? ram[laddr_a][4] : lwdata_a[4]);
ram[laddr_a][5] = (lwmsk_a[5] ? ram[laddr_a][5] : lwdata_a[5]);
ram[laddr_a][6] = (lwmsk_a[6] ? ram[laddr_a][6] : lwdata_a[6]);
ram[laddr_a][7] = (lwmsk_a[7] ? ram[laddr_a][7] : lwdata_a[7]);
ram[laddr_a][8] = (lwmsk_a[8] ? ram[laddr_a][8] : lwdata_a[8]);
ram[laddr_a][9] = (lwmsk_a[9] ? ram[laddr_a][9] : lwdata_a[9]);
ram[laddr_a][10] = (lwmsk_a[10] ? ram[laddr_a][10] : lwdata_a[10]);
ram[laddr_a][11] = (lwmsk_a[11] ? ram[laddr_a][11] : lwdata_a[11]);
ram[laddr_a][12] = (lwmsk_a[12] ? ram[laddr_a][12] : lwdata_a[12]);
ram[laddr_a][13] = (lwmsk_a[13] ? ram[laddr_a][13] : lwdata_a[13]);
ram[laddr_a][14] = (lwmsk_a[14] ? ram[laddr_a][14] : lwdata_a[14]);
ram[laddr_a][15] = (lwmsk_a[15] ? ram[laddr_a][15] : lwdata_a[15]);
ram[laddr_a][16] = (lwmsk_a[16] ? ram[laddr_a][16] : lwdata_a[16]);
ram[laddr_a][17] = (lwmsk_a[17] ? ram[laddr_a][17] : lwdata_a[17]);
lwen_a = 1;
end
if (lcen_a == 0) begin
rdata_a = ram[laddr_a];
lcen_a = 1;
end
else
rdata_a = rdata_a;
end
endmodule |
module vconv(
VCLK,
nRST,
nEN_YPbPr, // enables color transformation on '0'
vdata_valid_i,
vdata_i,
vdata_valid_o,
vdata_o
);
`include "vh/n64adv_vparams.vh"
localparam coeff_width = 20;
input VCLK;
input nRST;
input nEN_YPbPr;
input vdata_valid_i;
input [`VDATA_O_FU_SLICE] vdata_i;
output reg vdata_valid_o = 1'b0;
output [`VDATA_O_FU_SLICE] vdata_o;
// pre-assignments
wire [3:0] S_i = vdata_i[`VDATA_O_SY_SLICE];
wire unsigned [color_width_o-1:0] R_i = vdata_i[`VDATA_O_RE_SLICE];
wire unsigned [color_width_o-1:0] G_i = vdata_i[`VDATA_O_GR_SLICE];
wire unsigned [color_width_o-1:0] B_i = vdata_i[`VDATA_O_BL_SLICE];
reg [3:0] S_o = 4'h0;
reg unsigned [color_width_o-1:0] V1_o = {color_width_o{1'b0}};
reg unsigned [color_width_o-1:0] V2_o = {color_width_o{1'b0}};
reg unsigned [color_width_o-1:0] V3_o = {color_width_o{1'b0}};
// start of rtl
// delay Sync along with the pipeline stages of the video conversion
reg vdata_valid[0:2];
reg [3:0] S[0:2];
reg [color_width_o-1:0] R[0:2], G[0:2], B[0:2];
integer idx;
initial begin
for (idx = 0; idx < 3; idx = idx+1) begin
vdata_valid[idx] = 1'b0;
S[idx] = 4'h0;
R[idx] = {color_width_o{1'b0}};
G[idx] = {color_width_o{1'b0}};
B[idx] = {color_width_o{1'b0}};
end
end
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
for (idx = 0; idx < 3; idx = idx+1) begin
vdata_valid[idx] = 1'b0;
S[idx] <= 4'h0;
R[idx] <= {color_width_o{1'b0}};
G[idx] <= {color_width_o{1'b0}};
B[idx] <= {color_width_o{1'b0}};
end
end else begin
for (idx = 1; idx < 3; idx = idx+1) begin
vdata_valid[idx] <= vdata_valid[idx-1];
S[idx] <= S[idx-1];
R[idx] <= R[idx-1];
G[idx] <= G[idx-1];
B[idx] <= B[idx-1];
end
vdata_valid[0] <= vdata_valid_i;
S[0] <= S_i;
R[0] <= R_i;
G[0] <= G_i;
B[0] <= B_i;
end
// Transformation to YPbPr
// =======================
// Transformation Rec. 601:
// Y = 0.299 R + 0.587 G + 0.114 B
// Pb = -0.168736 R - 0.331264 G + 0.5 B + 2^9
// Pr = 0.5 R - 0.418688 G - 0.08132 B + 2^9
localparam msb_vo = color_width_o+coeff_width-1; // position of MSB after altmult_add (Pb and Pr neg. parts are shifted to that)
localparam lsb_vo = coeff_width; // position of LSB after altmult_add (Pb and Pr neg. parts are shifted to that)
localparam fyr = 20'd313524;
localparam fyg = 20'd615514;
localparam fyb = 20'd119538;
reg [color_width_o+coeff_width+1:0] Y_addmult = {(color_width_o+coeff_width+2){1'b0}};
reg [color_width_o+coeff_width-1:0] R4Y_scaled = {(color_width_o+coeff_width){1'b0}};
reg [color_width_o+coeff_width-1:0] G4Y_scaled = {(color_width_o+coeff_width){1'b0}};
reg [color_width_o+coeff_width-1:0] B4Y_scaled = {(color_width_o+coeff_width){1'b0}};
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
Y_addmult <= {(color_width_o+coeff_width+2){1'b0}};
R4Y_scaled <= {(color_width_o+coeff_width){1'b0}};
G4Y_scaled <= {(color_width_o+coeff_width){1'b0}};
B4Y_scaled <= {(color_width_o+coeff_width){1'b0}};
end else begin
Y_addmult <= R4Y_scaled + G4Y_scaled + B4Y_scaled;
R4Y_scaled <= fyr * (* multstyle = "dsp" *) R[0];
G4Y_scaled <= fyg * (* multstyle = "dsp" *) G[0];
B4Y_scaled <= fyb * (* multstyle = "dsp" *) B[0];
end
localparam fpbr = 20'd353865;
localparam fpbg = 20'd694711;
reg [color_width_o+coeff_width :0] Pb_nPart_addmult = {(color_width_o+coeff_width+1){1'b0}};
reg [color_width_o+coeff_width-1:0] R4Pb_scaled = {(color_width_o+coeff_width){1'b0}};
reg [color_width_o+coeff_width-1:0] G4Pb_scaled = {(color_width_o+coeff_width){1'b0}};
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
Pb_nPart_addmult <= {(color_width_o+coeff_width+1){1'b0}};
R4Pb_scaled <= {(color_width_o+coeff_width){1'b0}};
G4Pb_scaled <= {(color_width_o+coeff_width){1'b0}};
end else begin
Pb_nPart_addmult <= R4Pb_scaled + G4Pb_scaled;
R4Pb_scaled <= fpbr * (* multstyle = "dsp" *) R[0];
G4Pb_scaled <= fpbg * (* multstyle = "dsp" *) G[0];
end
wire [color_width_o+1:0] Pb_addmult = {1'b0,B[2],1'b0}- Pb_nPart_addmult[msb_vo+1:lsb_vo-1];
localparam fprg = 20'd878052;
localparam fprb = 20'd170524;
reg [color_width_o+coeff_width :0] Pr_nPart_addmult = {(color_width_o+coeff_width+1){1'b0}};
reg [color_width_o+coeff_width-1:0] G4Pr_scaled = {(color_width_o+coeff_width){1'b0}};
reg [color_width_o+coeff_width-1:0] B4Pr_scaled = {(color_width_o+coeff_width){1'b0}};
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
Pr_nPart_addmult <= {(color_width_o+coeff_width+1){1'b0}};
G4Pr_scaled <= {(color_width_o+coeff_width){1'b0}};
B4Pr_scaled <= {(color_width_o+coeff_width){1'b0}};
end else begin
Pr_nPart_addmult <= G4Pr_scaled + B4Pr_scaled;
G4Pr_scaled <= fprg * (* multstyle = "dsp" *) G[0];
B4Pr_scaled <= fprb * (* multstyle = "dsp" *) B[0];
end
wire [color_width_o+1:0] Pr_addmult = {1'b0,R[2],1'b0}- Pr_nPart_addmult[msb_vo+1:lsb_vo-1];
// get final results:
wire [color_width_o-1:0] Y_tmp = Y_addmult[msb_vo:lsb_vo] + Y_addmult[lsb_vo-1];
wire [color_width_o :0] Pb_tmp = Pb_addmult[color_width_o+1:1] + Pb_addmult[0];
wire [color_width_o :0] Pr_tmp = Pr_addmult[color_width_o+1:1] + Pr_addmult[0];
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
vdata_valid_o <= 1'b0;
S_o <= 4'h0;
V1_o <= {color_width_o{1'b0}};
V2_o <= {color_width_o{1'b0}};
V3_o <= {color_width_o{1'b0}};
end else begin
vdata_valid_o <= vdata_valid[2];
if (!nEN_YPbPr) begin
S_o <= S[2];
V1_o <= {~Pr_tmp[color_width_o],Pr_tmp[color_width_o-1:1]};
V2_o <= Y_tmp;
V3_o <= {~Pb_tmp[color_width_o],Pb_tmp[color_width_o-1:1]};
end else begin
S_o <= S[2];
V1_o <= R[2];
V2_o <= G[2];
V3_o <= B[2];
end
end
// post-assignment
assign vdata_o = {S_o,V1_o,V2_o,V3_o};
endmodule |
module RegisterFile(Read1, Read2, Writedata, Raddr1, Raddr2, Waddr, RegWr, CLK, RESET);
output [31:0] Read1;
output [31:0] Read2;
input [31:0] Writedata;
input [4:0] Raddr1, Raddr2, Waddr;
input RegWr, CLK, RESET;
reg [31:0] registers [0:31];
always @(posedge RESET)
begin
registers[0]=0;
registers[1]=0;
registers[2]=0;
registers[3]=0;
registers[4]=0;
registers[5]=0;
registers[6]=0;
registers[7]=0;
registers[8]=0;
registers[9]=0;
registers[10]=0;
registers[11]=0;
registers[12]=0;
registers[13]=0;
registers[14]=0;
registers[15]=0;
registers[16]=0;
registers[17]=0;
registers[18]=0;
registers[19]=0;
registers[20]=0;
registers[21]=0;
registers[22]=0;
registers[23]=0;
registers[24]=0;
registers[25]=0;
registers[26]=0;
registers[27]=0;
registers[28]=0;
registers[29]=0;
registers[30]=0;
registers[31]=0;
end
assign Read1 =registers[Raddr1];
assign Read2 =registers[Raddr2];
always @(negedge CLK)
begin
if(RegWr)
begin
registers[Waddr] = Writedata;
$display("Reg %d current %d new %d" ,Waddr, registers[Waddr], Writedata );
end
end
always @ (RegWr or Writedata)
begin
$display("----------------------------------------------\n");
$display("time %0d\t \n", $time);
$display("Reg10 %d " ,registers[10] );
$display("Reg11 %d " ,registers[11] );
$display("Reg12 %d " ,registers[12] );
$display("Reg13 %d " ,registers[13] );
$display("Reg14 %d " ,registers[14] );
$display("Reg15 %d " ,registers[15] );
$display("Reg16 %d " ,registers[16] );
end
endmodule |
module system_nfa_accept_samples_generic_hw_top_3_wrapper
(
aclk,
aresetn,
indices_MPLB_Clk,
indices_MPLB_Rst,
indices_M_request,
indices_M_priority,
indices_M_busLock,
indices_M_RNW,
indices_M_BE,
indices_M_MSize,
indices_M_size,
indices_M_type,
indices_M_TAttribute,
indices_M_lockErr,
indices_M_abort,
indices_M_UABus,
indices_M_ABus,
indices_M_wrDBus,
indices_M_wrBurst,
indices_M_rdBurst,
indices_PLB_MAddrAck,
indices_PLB_MSSize,
indices_PLB_MRearbitrate,
indices_PLB_MTimeout,
indices_PLB_MBusy,
indices_PLB_MRdErr,
indices_PLB_MWrErr,
indices_PLB_MIRQ,
indices_PLB_MRdDBus,
indices_PLB_MRdWdAddr,
indices_PLB_MRdDAck,
indices_PLB_MRdBTerm,
indices_PLB_MWrDAck,
indices_PLB_MWrBTerm,
nfa_finals_buckets_MPLB_Clk,
nfa_finals_buckets_MPLB_Rst,
nfa_finals_buckets_M_request,
nfa_finals_buckets_M_priority,
nfa_finals_buckets_M_busLock,
nfa_finals_buckets_M_RNW,
nfa_finals_buckets_M_BE,
nfa_finals_buckets_M_MSize,
nfa_finals_buckets_M_size,
nfa_finals_buckets_M_type,
nfa_finals_buckets_M_TAttribute,
nfa_finals_buckets_M_lockErr,
nfa_finals_buckets_M_abort,
nfa_finals_buckets_M_UABus,
nfa_finals_buckets_M_ABus,
nfa_finals_buckets_M_wrDBus,
nfa_finals_buckets_M_wrBurst,
nfa_finals_buckets_M_rdBurst,
nfa_finals_buckets_PLB_MAddrAck,
nfa_finals_buckets_PLB_MSSize,
nfa_finals_buckets_PLB_MRearbitrate,
nfa_finals_buckets_PLB_MTimeout,
nfa_finals_buckets_PLB_MBusy,
nfa_finals_buckets_PLB_MRdErr,
nfa_finals_buckets_PLB_MWrErr,
nfa_finals_buckets_PLB_MIRQ,
nfa_finals_buckets_PLB_MRdDBus,
nfa_finals_buckets_PLB_MRdWdAddr,
nfa_finals_buckets_PLB_MRdDAck,
nfa_finals_buckets_PLB_MRdBTerm,
nfa_finals_buckets_PLB_MWrDAck,
nfa_finals_buckets_PLB_MWrBTerm,
nfa_forward_buckets_MPLB_Clk,
nfa_forward_buckets_MPLB_Rst,
nfa_forward_buckets_M_request,
nfa_forward_buckets_M_priority,
nfa_forward_buckets_M_busLock,
nfa_forward_buckets_M_RNW,
nfa_forward_buckets_M_BE,
nfa_forward_buckets_M_MSize,
nfa_forward_buckets_M_size,
nfa_forward_buckets_M_type,
nfa_forward_buckets_M_TAttribute,
nfa_forward_buckets_M_lockErr,
nfa_forward_buckets_M_abort,
nfa_forward_buckets_M_UABus,
nfa_forward_buckets_M_ABus,
nfa_forward_buckets_M_wrDBus,
nfa_forward_buckets_M_wrBurst,
nfa_forward_buckets_M_rdBurst,
nfa_forward_buckets_PLB_MAddrAck,
nfa_forward_buckets_PLB_MSSize,
nfa_forward_buckets_PLB_MRearbitrate,
nfa_forward_buckets_PLB_MTimeout,
nfa_forward_buckets_PLB_MBusy,
nfa_forward_buckets_PLB_MRdErr,
nfa_forward_buckets_PLB_MWrErr,
nfa_forward_buckets_PLB_MIRQ,
nfa_forward_buckets_PLB_MRdDBus,
nfa_forward_buckets_PLB_MRdWdAddr,
nfa_forward_buckets_PLB_MRdDAck,
nfa_forward_buckets_PLB_MRdBTerm,
nfa_forward_buckets_PLB_MWrDAck,
nfa_forward_buckets_PLB_MWrBTerm,
nfa_initials_buckets_MPLB_Clk,
nfa_initials_buckets_MPLB_Rst,
nfa_initials_buckets_M_request,
nfa_initials_buckets_M_priority,
nfa_initials_buckets_M_busLock,
nfa_initials_buckets_M_RNW,
nfa_initials_buckets_M_BE,
nfa_initials_buckets_M_MSize,
nfa_initials_buckets_M_size,
nfa_initials_buckets_M_type,
nfa_initials_buckets_M_TAttribute,
nfa_initials_buckets_M_lockErr,
nfa_initials_buckets_M_abort,
nfa_initials_buckets_M_UABus,
nfa_initials_buckets_M_ABus,
nfa_initials_buckets_M_wrDBus,
nfa_initials_buckets_M_wrBurst,
nfa_initials_buckets_M_rdBurst,
nfa_initials_buckets_PLB_MAddrAck,
nfa_initials_buckets_PLB_MSSize,
nfa_initials_buckets_PLB_MRearbitrate,
nfa_initials_buckets_PLB_MTimeout,
nfa_initials_buckets_PLB_MBusy,
nfa_initials_buckets_PLB_MRdErr,
nfa_initials_buckets_PLB_MWrErr,
nfa_initials_buckets_PLB_MIRQ,
nfa_initials_buckets_PLB_MRdDBus,
nfa_initials_buckets_PLB_MRdWdAddr,
nfa_initials_buckets_PLB_MRdDAck,
nfa_initials_buckets_PLB_MRdBTerm,
nfa_initials_buckets_PLB_MWrDAck,
nfa_initials_buckets_PLB_MWrBTerm,
sample_buffer_MPLB_Clk,
sample_buffer_MPLB_Rst,
sample_buffer_M_request,
sample_buffer_M_priority,
sample_buffer_M_busLock,
sample_buffer_M_RNW,
sample_buffer_M_BE,
sample_buffer_M_MSize,
sample_buffer_M_size,
sample_buffer_M_type,
sample_buffer_M_TAttribute,
sample_buffer_M_lockErr,
sample_buffer_M_abort,
sample_buffer_M_UABus,
sample_buffer_M_ABus,
sample_buffer_M_wrDBus,
sample_buffer_M_wrBurst,
sample_buffer_M_rdBurst,
sample_buffer_PLB_MAddrAck,
sample_buffer_PLB_MSSize,
sample_buffer_PLB_MRearbitrate,
sample_buffer_PLB_MTimeout,
sample_buffer_PLB_MBusy,
sample_buffer_PLB_MRdErr,
sample_buffer_PLB_MWrErr,
sample_buffer_PLB_MIRQ,
sample_buffer_PLB_MRdDBus,
sample_buffer_PLB_MRdWdAddr,
sample_buffer_PLB_MRdDAck,
sample_buffer_PLB_MRdBTerm,
sample_buffer_PLB_MWrDAck,
sample_buffer_PLB_MWrBTerm,
splb_slv0_SPLB_Clk,
splb_slv0_SPLB_Rst,
splb_slv0_PLB_ABus,
splb_slv0_PLB_UABus,
splb_slv0_PLB_PAValid,
splb_slv0_PLB_SAValid,
splb_slv0_PLB_rdPrim,
splb_slv0_PLB_wrPrim,
splb_slv0_PLB_masterID,
splb_slv0_PLB_abort,
splb_slv0_PLB_busLock,
splb_slv0_PLB_RNW,
splb_slv0_PLB_BE,
splb_slv0_PLB_MSize,
splb_slv0_PLB_size,
splb_slv0_PLB_type,
splb_slv0_PLB_lockErr,
splb_slv0_PLB_wrDBus,
splb_slv0_PLB_wrBurst,
splb_slv0_PLB_rdBurst,
splb_slv0_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri,
splb_slv0_PLB_reqPri,
splb_slv0_PLB_TAttribute,
splb_slv0_Sl_addrAck,
splb_slv0_Sl_SSize,
splb_slv0_Sl_wait,
splb_slv0_Sl_rearbitrate,
splb_slv0_Sl_wrDAck,
splb_slv0_Sl_wrComp,
splb_slv0_Sl_wrBTerm,
splb_slv0_Sl_rdDBus,
splb_slv0_Sl_rdWdAddr,
splb_slv0_Sl_rdDAck,
splb_slv0_Sl_rdComp,
splb_slv0_Sl_rdBTerm,
splb_slv0_Sl_MBusy,
splb_slv0_Sl_MWrErr,
splb_slv0_Sl_MRdErr,
splb_slv0_Sl_MIRQ
);
input aclk;
input aresetn;
input indices_MPLB_Clk;
input indices_MPLB_Rst;
output indices_M_request;
output [0:1] indices_M_priority;
output indices_M_busLock;
output indices_M_RNW;
output [0:7] indices_M_BE;
output [0:1] indices_M_MSize;
output [0:3] indices_M_size;
output [0:2] indices_M_type;
output [0:15] indices_M_TAttribute;
output indices_M_lockErr;
output indices_M_abort;
output [0:31] indices_M_UABus;
output [0:31] indices_M_ABus;
output [0:63] indices_M_wrDBus;
output indices_M_wrBurst;
output indices_M_rdBurst;
input indices_PLB_MAddrAck;
input [0:1] indices_PLB_MSSize;
input indices_PLB_MRearbitrate;
input indices_PLB_MTimeout;
input indices_PLB_MBusy;
input indices_PLB_MRdErr;
input indices_PLB_MWrErr;
input indices_PLB_MIRQ;
input [0:63] indices_PLB_MRdDBus;
input [0:3] indices_PLB_MRdWdAddr;
input indices_PLB_MRdDAck;
input indices_PLB_MRdBTerm;
input indices_PLB_MWrDAck;
input indices_PLB_MWrBTerm;
input nfa_finals_buckets_MPLB_Clk;
input nfa_finals_buckets_MPLB_Rst;
output nfa_finals_buckets_M_request;
output [0:1] nfa_finals_buckets_M_priority;
output nfa_finals_buckets_M_busLock;
output nfa_finals_buckets_M_RNW;
output [0:7] nfa_finals_buckets_M_BE;
output [0:1] nfa_finals_buckets_M_MSize;
output [0:3] nfa_finals_buckets_M_size;
output [0:2] nfa_finals_buckets_M_type;
output [0:15] nfa_finals_buckets_M_TAttribute;
output nfa_finals_buckets_M_lockErr;
output nfa_finals_buckets_M_abort;
output [0:31] nfa_finals_buckets_M_UABus;
output [0:31] nfa_finals_buckets_M_ABus;
output [0:63] nfa_finals_buckets_M_wrDBus;
output nfa_finals_buckets_M_wrBurst;
output nfa_finals_buckets_M_rdBurst;
input nfa_finals_buckets_PLB_MAddrAck;
input [0:1] nfa_finals_buckets_PLB_MSSize;
input nfa_finals_buckets_PLB_MRearbitrate;
input nfa_finals_buckets_PLB_MTimeout;
input nfa_finals_buckets_PLB_MBusy;
input nfa_finals_buckets_PLB_MRdErr;
input nfa_finals_buckets_PLB_MWrErr;
input nfa_finals_buckets_PLB_MIRQ;
input [0:63] nfa_finals_buckets_PLB_MRdDBus;
input [0:3] nfa_finals_buckets_PLB_MRdWdAddr;
input nfa_finals_buckets_PLB_MRdDAck;
input nfa_finals_buckets_PLB_MRdBTerm;
input nfa_finals_buckets_PLB_MWrDAck;
input nfa_finals_buckets_PLB_MWrBTerm;
input nfa_forward_buckets_MPLB_Clk;
input nfa_forward_buckets_MPLB_Rst;
output nfa_forward_buckets_M_request;
output [0:1] nfa_forward_buckets_M_priority;
output nfa_forward_buckets_M_busLock;
output nfa_forward_buckets_M_RNW;
output [0:7] nfa_forward_buckets_M_BE;
output [0:1] nfa_forward_buckets_M_MSize;
output [0:3] nfa_forward_buckets_M_size;
output [0:2] nfa_forward_buckets_M_type;
output [0:15] nfa_forward_buckets_M_TAttribute;
output nfa_forward_buckets_M_lockErr;
output nfa_forward_buckets_M_abort;
output [0:31] nfa_forward_buckets_M_UABus;
output [0:31] nfa_forward_buckets_M_ABus;
output [0:63] nfa_forward_buckets_M_wrDBus;
output nfa_forward_buckets_M_wrBurst;
output nfa_forward_buckets_M_rdBurst;
input nfa_forward_buckets_PLB_MAddrAck;
input [0:1] nfa_forward_buckets_PLB_MSSize;
input nfa_forward_buckets_PLB_MRearbitrate;
input nfa_forward_buckets_PLB_MTimeout;
input nfa_forward_buckets_PLB_MBusy;
input nfa_forward_buckets_PLB_MRdErr;
input nfa_forward_buckets_PLB_MWrErr;
input nfa_forward_buckets_PLB_MIRQ;
input [0:63] nfa_forward_buckets_PLB_MRdDBus;
input [0:3] nfa_forward_buckets_PLB_MRdWdAddr;
input nfa_forward_buckets_PLB_MRdDAck;
input nfa_forward_buckets_PLB_MRdBTerm;
input nfa_forward_buckets_PLB_MWrDAck;
input nfa_forward_buckets_PLB_MWrBTerm;
input nfa_initials_buckets_MPLB_Clk;
input nfa_initials_buckets_MPLB_Rst;
output nfa_initials_buckets_M_request;
output [0:1] nfa_initials_buckets_M_priority;
output nfa_initials_buckets_M_busLock;
output nfa_initials_buckets_M_RNW;
output [0:7] nfa_initials_buckets_M_BE;
output [0:1] nfa_initials_buckets_M_MSize;
output [0:3] nfa_initials_buckets_M_size;
output [0:2] nfa_initials_buckets_M_type;
output [0:15] nfa_initials_buckets_M_TAttribute;
output nfa_initials_buckets_M_lockErr;
output nfa_initials_buckets_M_abort;
output [0:31] nfa_initials_buckets_M_UABus;
output [0:31] nfa_initials_buckets_M_ABus;
output [0:63] nfa_initials_buckets_M_wrDBus;
output nfa_initials_buckets_M_wrBurst;
output nfa_initials_buckets_M_rdBurst;
input nfa_initials_buckets_PLB_MAddrAck;
input [0:1] nfa_initials_buckets_PLB_MSSize;
input nfa_initials_buckets_PLB_MRearbitrate;
input nfa_initials_buckets_PLB_MTimeout;
input nfa_initials_buckets_PLB_MBusy;
input nfa_initials_buckets_PLB_MRdErr;
input nfa_initials_buckets_PLB_MWrErr;
input nfa_initials_buckets_PLB_MIRQ;
input [0:63] nfa_initials_buckets_PLB_MRdDBus;
input [0:3] nfa_initials_buckets_PLB_MRdWdAddr;
input nfa_initials_buckets_PLB_MRdDAck;
input nfa_initials_buckets_PLB_MRdBTerm;
input nfa_initials_buckets_PLB_MWrDAck;
input nfa_initials_buckets_PLB_MWrBTerm;
input sample_buffer_MPLB_Clk;
input sample_buffer_MPLB_Rst;
output sample_buffer_M_request;
output [0:1] sample_buffer_M_priority;
output sample_buffer_M_busLock;
output sample_buffer_M_RNW;
output [0:7] sample_buffer_M_BE;
output [0:1] sample_buffer_M_MSize;
output [0:3] sample_buffer_M_size;
output [0:2] sample_buffer_M_type;
output [0:15] sample_buffer_M_TAttribute;
output sample_buffer_M_lockErr;
output sample_buffer_M_abort;
output [0:31] sample_buffer_M_UABus;
output [0:31] sample_buffer_M_ABus;
output [0:63] sample_buffer_M_wrDBus;
output sample_buffer_M_wrBurst;
output sample_buffer_M_rdBurst;
input sample_buffer_PLB_MAddrAck;
input [0:1] sample_buffer_PLB_MSSize;
input sample_buffer_PLB_MRearbitrate;
input sample_buffer_PLB_MTimeout;
input sample_buffer_PLB_MBusy;
input sample_buffer_PLB_MRdErr;
input sample_buffer_PLB_MWrErr;
input sample_buffer_PLB_MIRQ;
input [0:63] sample_buffer_PLB_MRdDBus;
input [0:3] sample_buffer_PLB_MRdWdAddr;
input sample_buffer_PLB_MRdDAck;
input sample_buffer_PLB_MRdBTerm;
input sample_buffer_PLB_MWrDAck;
input sample_buffer_PLB_MWrBTerm;
input splb_slv0_SPLB_Clk;
input splb_slv0_SPLB_Rst;
input [0:31] splb_slv0_PLB_ABus;
input [0:31] splb_slv0_PLB_UABus;
input splb_slv0_PLB_PAValid;
input splb_slv0_PLB_SAValid;
input splb_slv0_PLB_rdPrim;
input splb_slv0_PLB_wrPrim;
input [0:2] splb_slv0_PLB_masterID;
input splb_slv0_PLB_abort;
input splb_slv0_PLB_busLock;
input splb_slv0_PLB_RNW;
input [0:7] splb_slv0_PLB_BE;
input [0:1] splb_slv0_PLB_MSize;
input [0:3] splb_slv0_PLB_size;
input [0:2] splb_slv0_PLB_type;
input splb_slv0_PLB_lockErr;
input [0:63] splb_slv0_PLB_wrDBus;
input splb_slv0_PLB_wrBurst;
input splb_slv0_PLB_rdBurst;
input splb_slv0_PLB_wrPendReq;
input splb_slv0_PLB_rdPendReq;
input [0:1] splb_slv0_PLB_wrPendPri;
input [0:1] splb_slv0_PLB_rdPendPri;
input [0:1] splb_slv0_PLB_reqPri;
input [0:15] splb_slv0_PLB_TAttribute;
output splb_slv0_Sl_addrAck;
output [0:1] splb_slv0_Sl_SSize;
output splb_slv0_Sl_wait;
output splb_slv0_Sl_rearbitrate;
output splb_slv0_Sl_wrDAck;
output splb_slv0_Sl_wrComp;
output splb_slv0_Sl_wrBTerm;
output [0:63] splb_slv0_Sl_rdDBus;
output [0:3] splb_slv0_Sl_rdWdAddr;
output splb_slv0_Sl_rdDAck;
output splb_slv0_Sl_rdComp;
output splb_slv0_Sl_rdBTerm;
output [0:5] splb_slv0_Sl_MBusy;
output [0:5] splb_slv0_Sl_MWrErr;
output [0:5] splb_slv0_Sl_MRdErr;
output [0:5] splb_slv0_Sl_MIRQ;
nfa_accept_samples_generic_hw_top
#(
.RESET_ACTIVE_LOW ( 1 ),
.C_indices_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_indices_AWIDTH ( 32 ),
.C_indices_DWIDTH ( 64 ),
.C_indices_NATIVE_DWIDTH ( 64 ),
.C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_finals_buckets_AWIDTH ( 32 ),
.C_nfa_finals_buckets_DWIDTH ( 64 ),
.C_nfa_finals_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_forward_buckets_AWIDTH ( 32 ),
.C_nfa_forward_buckets_DWIDTH ( 64 ),
.C_nfa_forward_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_initials_buckets_AWIDTH ( 32 ),
.C_nfa_initials_buckets_DWIDTH ( 64 ),
.C_nfa_initials_buckets_NATIVE_DWIDTH ( 64 ),
.C_sample_buffer_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_sample_buffer_AWIDTH ( 32 ),
.C_sample_buffer_DWIDTH ( 64 ),
.C_sample_buffer_NATIVE_DWIDTH ( 64 ),
.C_SPLB_SLV0_BASEADDR ( 32'hD3000000 ),
.C_SPLB_SLV0_HIGHADDR ( 32'hD30000FF ),
.C_SPLB_SLV0_AWIDTH ( 32 ),
.C_SPLB_SLV0_DWIDTH ( 64 ),
.C_SPLB_SLV0_NUM_MASTERS ( 6 ),
.C_SPLB_SLV0_MID_WIDTH ( 3 ),
.C_SPLB_SLV0_NATIVE_DWIDTH ( 32 ),
.C_SPLB_SLV0_P2P ( 0 ),
.C_SPLB_SLV0_SUPPORT_BURSTS ( 0 ),
.C_SPLB_SLV0_SMALLEST_MASTER ( 32 ),
.C_SPLB_SLV0_INCLUDE_DPHASE_TIMER ( 0 )
)
nfa_accept_samples_generic_hw_top_3 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.indices_MPLB_Clk ( indices_MPLB_Clk ),
.indices_MPLB_Rst ( indices_MPLB_Rst ),
.indices_M_request ( indices_M_request ),
.indices_M_priority ( indices_M_priority ),
.indices_M_busLock ( indices_M_busLock ),
.indices_M_RNW ( indices_M_RNW ),
.indices_M_BE ( indices_M_BE ),
.indices_M_MSize ( indices_M_MSize ),
.indices_M_size ( indices_M_size ),
.indices_M_type ( indices_M_type ),
.indices_M_TAttribute ( indices_M_TAttribute ),
.indices_M_lockErr ( indices_M_lockErr ),
.indices_M_abort ( indices_M_abort ),
.indices_M_UABus ( indices_M_UABus ),
.indices_M_ABus ( indices_M_ABus ),
.indices_M_wrDBus ( indices_M_wrDBus ),
.indices_M_wrBurst ( indices_M_wrBurst ),
.indices_M_rdBurst ( indices_M_rdBurst ),
.indices_PLB_MAddrAck ( indices_PLB_MAddrAck ),
.indices_PLB_MSSize ( indices_PLB_MSSize ),
.indices_PLB_MRearbitrate ( indices_PLB_MRearbitrate ),
.indices_PLB_MTimeout ( indices_PLB_MTimeout ),
.indices_PLB_MBusy ( indices_PLB_MBusy ),
.indices_PLB_MRdErr ( indices_PLB_MRdErr ),
.indices_PLB_MWrErr ( indices_PLB_MWrErr ),
.indices_PLB_MIRQ ( indices_PLB_MIRQ ),
.indices_PLB_MRdDBus ( indices_PLB_MRdDBus ),
.indices_PLB_MRdWdAddr ( indices_PLB_MRdWdAddr ),
.indices_PLB_MRdDAck ( indices_PLB_MRdDAck ),
.indices_PLB_MRdBTerm ( indices_PLB_MRdBTerm ),
.indices_PLB_MWrDAck ( indices_PLB_MWrDAck ),
.indices_PLB_MWrBTerm ( indices_PLB_MWrBTerm ),
.nfa_finals_buckets_MPLB_Clk ( nfa_finals_buckets_MPLB_Clk ),
.nfa_finals_buckets_MPLB_Rst ( nfa_finals_buckets_MPLB_Rst ),
.nfa_finals_buckets_M_request ( nfa_finals_buckets_M_request ),
.nfa_finals_buckets_M_priority ( nfa_finals_buckets_M_priority ),
.nfa_finals_buckets_M_busLock ( nfa_finals_buckets_M_busLock ),
.nfa_finals_buckets_M_RNW ( nfa_finals_buckets_M_RNW ),
.nfa_finals_buckets_M_BE ( nfa_finals_buckets_M_BE ),
.nfa_finals_buckets_M_MSize ( nfa_finals_buckets_M_MSize ),
.nfa_finals_buckets_M_size ( nfa_finals_buckets_M_size ),
.nfa_finals_buckets_M_type ( nfa_finals_buckets_M_type ),
.nfa_finals_buckets_M_TAttribute ( nfa_finals_buckets_M_TAttribute ),
.nfa_finals_buckets_M_lockErr ( nfa_finals_buckets_M_lockErr ),
.nfa_finals_buckets_M_abort ( nfa_finals_buckets_M_abort ),
.nfa_finals_buckets_M_UABus ( nfa_finals_buckets_M_UABus ),
.nfa_finals_buckets_M_ABus ( nfa_finals_buckets_M_ABus ),
.nfa_finals_buckets_M_wrDBus ( nfa_finals_buckets_M_wrDBus ),
.nfa_finals_buckets_M_wrBurst ( nfa_finals_buckets_M_wrBurst ),
.nfa_finals_buckets_M_rdBurst ( nfa_finals_buckets_M_rdBurst ),
.nfa_finals_buckets_PLB_MAddrAck ( nfa_finals_buckets_PLB_MAddrAck ),
.nfa_finals_buckets_PLB_MSSize ( nfa_finals_buckets_PLB_MSSize ),
.nfa_finals_buckets_PLB_MRearbitrate ( nfa_finals_buckets_PLB_MRearbitrate ),
.nfa_finals_buckets_PLB_MTimeout ( nfa_finals_buckets_PLB_MTimeout ),
.nfa_finals_buckets_PLB_MBusy ( nfa_finals_buckets_PLB_MBusy ),
.nfa_finals_buckets_PLB_MRdErr ( nfa_finals_buckets_PLB_MRdErr ),
.nfa_finals_buckets_PLB_MWrErr ( nfa_finals_buckets_PLB_MWrErr ),
.nfa_finals_buckets_PLB_MIRQ ( nfa_finals_buckets_PLB_MIRQ ),
.nfa_finals_buckets_PLB_MRdDBus ( nfa_finals_buckets_PLB_MRdDBus ),
.nfa_finals_buckets_PLB_MRdWdAddr ( nfa_finals_buckets_PLB_MRdWdAddr ),
.nfa_finals_buckets_PLB_MRdDAck ( nfa_finals_buckets_PLB_MRdDAck ),
.nfa_finals_buckets_PLB_MRdBTerm ( nfa_finals_buckets_PLB_MRdBTerm ),
.nfa_finals_buckets_PLB_MWrDAck ( nfa_finals_buckets_PLB_MWrDAck ),
.nfa_finals_buckets_PLB_MWrBTerm ( nfa_finals_buckets_PLB_MWrBTerm ),
.nfa_forward_buckets_MPLB_Clk ( nfa_forward_buckets_MPLB_Clk ),
.nfa_forward_buckets_MPLB_Rst ( nfa_forward_buckets_MPLB_Rst ),
.nfa_forward_buckets_M_request ( nfa_forward_buckets_M_request ),
.nfa_forward_buckets_M_priority ( nfa_forward_buckets_M_priority ),
.nfa_forward_buckets_M_busLock ( nfa_forward_buckets_M_busLock ),
.nfa_forward_buckets_M_RNW ( nfa_forward_buckets_M_RNW ),
.nfa_forward_buckets_M_BE ( nfa_forward_buckets_M_BE ),
.nfa_forward_buckets_M_MSize ( nfa_forward_buckets_M_MSize ),
.nfa_forward_buckets_M_size ( nfa_forward_buckets_M_size ),
.nfa_forward_buckets_M_type ( nfa_forward_buckets_M_type ),
.nfa_forward_buckets_M_TAttribute ( nfa_forward_buckets_M_TAttribute ),
.nfa_forward_buckets_M_lockErr ( nfa_forward_buckets_M_lockErr ),
.nfa_forward_buckets_M_abort ( nfa_forward_buckets_M_abort ),
.nfa_forward_buckets_M_UABus ( nfa_forward_buckets_M_UABus ),
.nfa_forward_buckets_M_ABus ( nfa_forward_buckets_M_ABus ),
.nfa_forward_buckets_M_wrDBus ( nfa_forward_buckets_M_wrDBus ),
.nfa_forward_buckets_M_wrBurst ( nfa_forward_buckets_M_wrBurst ),
.nfa_forward_buckets_M_rdBurst ( nfa_forward_buckets_M_rdBurst ),
.nfa_forward_buckets_PLB_MAddrAck ( nfa_forward_buckets_PLB_MAddrAck ),
.nfa_forward_buckets_PLB_MSSize ( nfa_forward_buckets_PLB_MSSize ),
.nfa_forward_buckets_PLB_MRearbitrate ( nfa_forward_buckets_PLB_MRearbitrate ),
.nfa_forward_buckets_PLB_MTimeout ( nfa_forward_buckets_PLB_MTimeout ),
.nfa_forward_buckets_PLB_MBusy ( nfa_forward_buckets_PLB_MBusy ),
.nfa_forward_buckets_PLB_MRdErr ( nfa_forward_buckets_PLB_MRdErr ),
.nfa_forward_buckets_PLB_MWrErr ( nfa_forward_buckets_PLB_MWrErr ),
.nfa_forward_buckets_PLB_MIRQ ( nfa_forward_buckets_PLB_MIRQ ),
.nfa_forward_buckets_PLB_MRdDBus ( nfa_forward_buckets_PLB_MRdDBus ),
.nfa_forward_buckets_PLB_MRdWdAddr ( nfa_forward_buckets_PLB_MRdWdAddr ),
.nfa_forward_buckets_PLB_MRdDAck ( nfa_forward_buckets_PLB_MRdDAck ),
.nfa_forward_buckets_PLB_MRdBTerm ( nfa_forward_buckets_PLB_MRdBTerm ),
.nfa_forward_buckets_PLB_MWrDAck ( nfa_forward_buckets_PLB_MWrDAck ),
.nfa_forward_buckets_PLB_MWrBTerm ( nfa_forward_buckets_PLB_MWrBTerm ),
.nfa_initials_buckets_MPLB_Clk ( nfa_initials_buckets_MPLB_Clk ),
.nfa_initials_buckets_MPLB_Rst ( nfa_initials_buckets_MPLB_Rst ),
.nfa_initials_buckets_M_request ( nfa_initials_buckets_M_request ),
.nfa_initials_buckets_M_priority ( nfa_initials_buckets_M_priority ),
.nfa_initials_buckets_M_busLock ( nfa_initials_buckets_M_busLock ),
.nfa_initials_buckets_M_RNW ( nfa_initials_buckets_M_RNW ),
.nfa_initials_buckets_M_BE ( nfa_initials_buckets_M_BE ),
.nfa_initials_buckets_M_MSize ( nfa_initials_buckets_M_MSize ),
.nfa_initials_buckets_M_size ( nfa_initials_buckets_M_size ),
.nfa_initials_buckets_M_type ( nfa_initials_buckets_M_type ),
.nfa_initials_buckets_M_TAttribute ( nfa_initials_buckets_M_TAttribute ),
.nfa_initials_buckets_M_lockErr ( nfa_initials_buckets_M_lockErr ),
.nfa_initials_buckets_M_abort ( nfa_initials_buckets_M_abort ),
.nfa_initials_buckets_M_UABus ( nfa_initials_buckets_M_UABus ),
.nfa_initials_buckets_M_ABus ( nfa_initials_buckets_M_ABus ),
.nfa_initials_buckets_M_wrDBus ( nfa_initials_buckets_M_wrDBus ),
.nfa_initials_buckets_M_wrBurst ( nfa_initials_buckets_M_wrBurst ),
.nfa_initials_buckets_M_rdBurst ( nfa_initials_buckets_M_rdBurst ),
.nfa_initials_buckets_PLB_MAddrAck ( nfa_initials_buckets_PLB_MAddrAck ),
.nfa_initials_buckets_PLB_MSSize ( nfa_initials_buckets_PLB_MSSize ),
.nfa_initials_buckets_PLB_MRearbitrate ( nfa_initials_buckets_PLB_MRearbitrate ),
.nfa_initials_buckets_PLB_MTimeout ( nfa_initials_buckets_PLB_MTimeout ),
.nfa_initials_buckets_PLB_MBusy ( nfa_initials_buckets_PLB_MBusy ),
.nfa_initials_buckets_PLB_MRdErr ( nfa_initials_buckets_PLB_MRdErr ),
.nfa_initials_buckets_PLB_MWrErr ( nfa_initials_buckets_PLB_MWrErr ),
.nfa_initials_buckets_PLB_MIRQ ( nfa_initials_buckets_PLB_MIRQ ),
.nfa_initials_buckets_PLB_MRdDBus ( nfa_initials_buckets_PLB_MRdDBus ),
.nfa_initials_buckets_PLB_MRdWdAddr ( nfa_initials_buckets_PLB_MRdWdAddr ),
.nfa_initials_buckets_PLB_MRdDAck ( nfa_initials_buckets_PLB_MRdDAck ),
.nfa_initials_buckets_PLB_MRdBTerm ( nfa_initials_buckets_PLB_MRdBTerm ),
.nfa_initials_buckets_PLB_MWrDAck ( nfa_initials_buckets_PLB_MWrDAck ),
.nfa_initials_buckets_PLB_MWrBTerm ( nfa_initials_buckets_PLB_MWrBTerm ),
.sample_buffer_MPLB_Clk ( sample_buffer_MPLB_Clk ),
.sample_buffer_MPLB_Rst ( sample_buffer_MPLB_Rst ),
.sample_buffer_M_request ( sample_buffer_M_request ),
.sample_buffer_M_priority ( sample_buffer_M_priority ),
.sample_buffer_M_busLock ( sample_buffer_M_busLock ),
.sample_buffer_M_RNW ( sample_buffer_M_RNW ),
.sample_buffer_M_BE ( sample_buffer_M_BE ),
.sample_buffer_M_MSize ( sample_buffer_M_MSize ),
.sample_buffer_M_size ( sample_buffer_M_size ),
.sample_buffer_M_type ( sample_buffer_M_type ),
.sample_buffer_M_TAttribute ( sample_buffer_M_TAttribute ),
.sample_buffer_M_lockErr ( sample_buffer_M_lockErr ),
.sample_buffer_M_abort ( sample_buffer_M_abort ),
.sample_buffer_M_UABus ( sample_buffer_M_UABus ),
.sample_buffer_M_ABus ( sample_buffer_M_ABus ),
.sample_buffer_M_wrDBus ( sample_buffer_M_wrDBus ),
.sample_buffer_M_wrBurst ( sample_buffer_M_wrBurst ),
.sample_buffer_M_rdBurst ( sample_buffer_M_rdBurst ),
.sample_buffer_PLB_MAddrAck ( sample_buffer_PLB_MAddrAck ),
.sample_buffer_PLB_MSSize ( sample_buffer_PLB_MSSize ),
.sample_buffer_PLB_MRearbitrate ( sample_buffer_PLB_MRearbitrate ),
.sample_buffer_PLB_MTimeout ( sample_buffer_PLB_MTimeout ),
.sample_buffer_PLB_MBusy ( sample_buffer_PLB_MBusy ),
.sample_buffer_PLB_MRdErr ( sample_buffer_PLB_MRdErr ),
.sample_buffer_PLB_MWrErr ( sample_buffer_PLB_MWrErr ),
.sample_buffer_PLB_MIRQ ( sample_buffer_PLB_MIRQ ),
.sample_buffer_PLB_MRdDBus ( sample_buffer_PLB_MRdDBus ),
.sample_buffer_PLB_MRdWdAddr ( sample_buffer_PLB_MRdWdAddr ),
.sample_buffer_PLB_MRdDAck ( sample_buffer_PLB_MRdDAck ),
.sample_buffer_PLB_MRdBTerm ( sample_buffer_PLB_MRdBTerm ),
.sample_buffer_PLB_MWrDAck ( sample_buffer_PLB_MWrDAck ),
.sample_buffer_PLB_MWrBTerm ( sample_buffer_PLB_MWrBTerm ),
.splb_slv0_SPLB_Clk ( splb_slv0_SPLB_Clk ),
.splb_slv0_SPLB_Rst ( splb_slv0_SPLB_Rst ),
.splb_slv0_PLB_ABus ( splb_slv0_PLB_ABus ),
.splb_slv0_PLB_UABus ( splb_slv0_PLB_UABus ),
.splb_slv0_PLB_PAValid ( splb_slv0_PLB_PAValid ),
.splb_slv0_PLB_SAValid ( splb_slv0_PLB_SAValid ),
.splb_slv0_PLB_rdPrim ( splb_slv0_PLB_rdPrim ),
.splb_slv0_PLB_wrPrim ( splb_slv0_PLB_wrPrim ),
.splb_slv0_PLB_masterID ( splb_slv0_PLB_masterID ),
.splb_slv0_PLB_abort ( splb_slv0_PLB_abort ),
.splb_slv0_PLB_busLock ( splb_slv0_PLB_busLock ),
.splb_slv0_PLB_RNW ( splb_slv0_PLB_RNW ),
.splb_slv0_PLB_BE ( splb_slv0_PLB_BE ),
.splb_slv0_PLB_MSize ( splb_slv0_PLB_MSize ),
.splb_slv0_PLB_size ( splb_slv0_PLB_size ),
.splb_slv0_PLB_type ( splb_slv0_PLB_type ),
.splb_slv0_PLB_lockErr ( splb_slv0_PLB_lockErr ),
.splb_slv0_PLB_wrDBus ( splb_slv0_PLB_wrDBus ),
.splb_slv0_PLB_wrBurst ( splb_slv0_PLB_wrBurst ),
.splb_slv0_PLB_rdBurst ( splb_slv0_PLB_rdBurst ),
.splb_slv0_PLB_wrPendReq ( splb_slv0_PLB_wrPendReq ),
.splb_slv0_PLB_rdPendReq ( splb_slv0_PLB_rdPendReq ),
.splb_slv0_PLB_wrPendPri ( splb_slv0_PLB_wrPendPri ),
.splb_slv0_PLB_rdPendPri ( splb_slv0_PLB_rdPendPri ),
.splb_slv0_PLB_reqPri ( splb_slv0_PLB_reqPri ),
.splb_slv0_PLB_TAttribute ( splb_slv0_PLB_TAttribute ),
.splb_slv0_Sl_addrAck ( splb_slv0_Sl_addrAck ),
.splb_slv0_Sl_SSize ( splb_slv0_Sl_SSize ),
.splb_slv0_Sl_wait ( splb_slv0_Sl_wait ),
.splb_slv0_Sl_rearbitrate ( splb_slv0_Sl_rearbitrate ),
.splb_slv0_Sl_wrDAck ( splb_slv0_Sl_wrDAck ),
.splb_slv0_Sl_wrComp ( splb_slv0_Sl_wrComp ),
.splb_slv0_Sl_wrBTerm ( splb_slv0_Sl_wrBTerm ),
.splb_slv0_Sl_rdDBus ( splb_slv0_Sl_rdDBus ),
.splb_slv0_Sl_rdWdAddr ( splb_slv0_Sl_rdWdAddr ),
.splb_slv0_Sl_rdDAck ( splb_slv0_Sl_rdDAck ),
.splb_slv0_Sl_rdComp ( splb_slv0_Sl_rdComp ),
.splb_slv0_Sl_rdBTerm ( splb_slv0_Sl_rdBTerm ),
.splb_slv0_Sl_MBusy ( splb_slv0_Sl_MBusy ),
.splb_slv0_Sl_MWrErr ( splb_slv0_Sl_MWrErr ),
.splb_slv0_Sl_MRdErr ( splb_slv0_Sl_MRdErr ),
.splb_slv0_Sl_MIRQ ( splb_slv0_Sl_MIRQ )
);
endmodule |
module axi_ad9361_rx_pnmon (
// adc interface
adc_clk,
adc_valid,
adc_data_i,
adc_data_q,
// pn out of sync and error
adc_pn_oos,
adc_pn_err);
// adc interface
input adc_clk;
input adc_valid;
input [11:0] adc_data_i;
input [11:0] adc_data_q;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// internal registers
reg [15:0] adc_data = 'd0;
reg [15:0] adc_pn_data = 'd0;
reg adc_valid_d = 'd0;
reg adc_iq_match = 'd0;
reg adc_pn_match_d = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
// internal signals
wire [11:0] adc_data_i_s;
wire [11:0] adc_data_q_s;
wire [11:0] adc_data_q_rev_s;
wire [15:0] adc_data_s;
wire adc_iq_match_s;
wire [15:0] adc_pn_data_s;
wire adc_pn_match_d_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// prbs function
function [15:0] pnfn;
input [15:0] din;
reg [15:0] dout;
begin
dout = {din[14:0], ~((^din[15:4]) ^ (^din[2:1]))};
pnfn = dout;
end
endfunction
// bit reversal function
function [11:0] brfn;
input [11:0] din;
reg [11:0] dout;
begin
dout[11] = din[ 0];
dout[10] = din[ 1];
dout[ 9] = din[ 2];
dout[ 8] = din[ 3];
dout[ 7] = din[ 4];
dout[ 6] = din[ 5];
dout[ 5] = din[ 6];
dout[ 4] = din[ 7];
dout[ 3] = din[ 8];
dout[ 2] = din[ 9];
dout[ 1] = din[10];
dout[ 0] = din[11];
brfn = dout;
end
endfunction
// assuming lower nibble is lost-
assign adc_data_i_s = ~adc_data_i;
assign adc_data_q_s = ~adc_data_q;
assign adc_data_q_rev_s = brfn(adc_data_q_s);
assign adc_data_s = {adc_data_i_s, adc_data_q_rev_s[3:0]};
assign adc_iq_match_s = (adc_data_i_s[7:0] == adc_data_q_rev_s[11:4]) ? 1'b1 : 1'b0;
// pn sequence checking algorithm is commonly used in most applications.
// if oos is asserted (pn is out of sync):
// next sequence is generated from the incoming data.
// if 64 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_data_s : adc_pn_data;
assign adc_pn_match_d_s = (adc_data_s == adc_pn_data) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_data_s == adc_data) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_iq_match & adc_pn_match_d & adc_pn_match_z;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn oos and counters (64 to clear and set).
always @(posedge adc_clk) begin
if (adc_valid == 1'b1) begin
adc_data <= adc_data_s;
adc_pn_data <= pnfn(adc_pn_data_s);
end
adc_valid_d <= adc_valid;
adc_iq_match <= adc_iq_match_s;
adc_pn_match_d <= adc_pn_match_d_s;
adc_pn_match_z <= adc_pn_match_z_s;
if (adc_valid_d == 1'b1) begin
adc_pn_err <= adc_pn_err_s;
if (adc_pn_update_s == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
end
endmodule |
module
);
//always @(*)
// $display("%m async_reset_neg=%b fb_clk=%b adg_int=%b fb_tag_r=%b fb_we_r=%b",
// async_reset_neg,fb_clk,adg_int,fb_tag_r,fb_we_r);
endmodule |
module pcie_bram_top_s6 #(
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
parameter VC0_TX_LASTPACKET = 31,
parameter TLM_TX_OVERHEAD = 20,
parameter TL_TX_RAM_RADDR_LATENCY = 1,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 1,
parameter VC0_RX_LIMIT = 'h1FFF,
parameter TL_RX_RAM_RADDR_LATENCY = 1,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 1
) (
input user_clk_i,
input reset_i,
input mim_tx_wen,
input [11:0] mim_tx_waddr,
input [35:0] mim_tx_wdata,
input mim_tx_ren,
input mim_tx_rce,
input [11:0] mim_tx_raddr,
output [35:0] mim_tx_rdata,
input mim_rx_wen,
input [11:0] mim_rx_waddr,
input [35:0] mim_rx_wdata,
input mim_rx_ren,
input mim_rx_rce,
input [11:0] mim_rx_raddr,
output [35:0] mim_rx_rdata
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
512 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 2048) ? 1 :
(BYTES_TX <= 4096) ? 2 :
(BYTES_TX <= 8192) ? 4 :
9
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
(VC0_RX_LIMIT < 'h0400) ? 2 :
(VC0_RX_LIMIT < 'h0800) ? 4 :
9
);
pcie_brams_s6 #(
.NUM_BRAMS (COLS_TX),
.RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
pcie_brams_tx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_tx_waddr),
.wen(mim_tx_wen),
.ren(mim_tx_ren),
.rce(mim_tx_rce),
.wdata(mim_tx_wdata),
.raddr(mim_tx_raddr),
.rdata(mim_tx_rdata)
);
pcie_brams_s6 #(
.NUM_BRAMS (COLS_RX),
.RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
pcie_brams_rx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_rx_waddr),
.wen(mim_rx_wen),
.ren(mim_rx_ren),
.rce(mim_rx_rce),
.wdata(mim_rx_wdata),
.raddr(mim_rx_raddr),
.rdata(mim_rx_rdata)
);
endmodule |
module system_vga_color_test_0_0(clk_25, xaddr, yaddr, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]" */;
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
endmodule |
module timing_signal_generator_tb(
);
parameter CYCLE = 5;
parameter LEN = 4;
parameter TIME = 500;
reg clr_n, on, off;
reg [3:0] power;
wire [(LEN-1):0] T;
timing_signal_generator #(.CYCLE(CYCLE), .LEN(LEN)) DUT (
.clr_n(clr_n),
.on(on),
.off(off),
.power(power),
.T(T));
initial begin
#TIME $stop;
end
initial begin
clr_n = 1;
on = 0; off = 1;
power = 4'b0000;
#10 clr_n = 0;
#10 clr_n = 1;
#10 power = 4'b0001;
end
endmodule |
module sky130_fd_sc_hd__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule |
module pezhman_mem(
clka,
addra,
douta
);
input clka;
input [14 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("pezhman_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule |
module pcie_7x_v1_3_pipe_reset #
(
//---------- Global ------------------------------------
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable
parameter PCIE_LANE = 1, // PCIe number of lanes
//---------- Local -------------------------------------
parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
)
(
//---------- Input -------------------------------------
input RST_CLK,
input RST_RXUSRCLK,
input RST_DCLK,
input RST_RST_N,
input [PCIE_LANE-1:0] RST_CPLLLOCK,
input RST_QPLL_IDLE,
input [PCIE_LANE-1:0] RST_RATE_IDLE,
input [PCIE_LANE-1:0] RST_RXCDRLOCK,
input RST_MMCM_LOCK,
input [PCIE_LANE-1:0] RST_RESETDONE,
input [PCIE_LANE-1:0] RST_PHYSTATUS,
input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
//---------- Output ------------------------------------
output RST_CPLLRESET,
output RST_CPLLPD,
output RST_RXUSRCLK_RESET,
output RST_DCLK_RESET,
output RST_GTRESET,
output RST_USERRDY,
output RST_TXSYNC_START,
output RST_IDLE,
output [10:0] RST_FSM
);
//---------- Input Register ----------------------------
reg [PCIE_LANE-1:0] cplllock_reg1;
reg qpll_idle_reg1;
reg [PCIE_LANE-1:0] rate_idle_reg1;
reg [PCIE_LANE-1:0] rxcdrlock_reg1;
reg mmcm_lock_reg1;
reg [PCIE_LANE-1:0] resetdone_reg1;
reg [PCIE_LANE-1:0] phystatus_reg1;
reg [PCIE_LANE-1:0] txsync_done_reg1;
reg [PCIE_LANE-1:0] cplllock_reg2;
reg qpll_idle_reg2;
reg [PCIE_LANE-1:0] rate_idle_reg2;
reg [PCIE_LANE-1:0] rxcdrlock_reg2;
reg mmcm_lock_reg2;
reg [PCIE_LANE-1:0] resetdone_reg2;
reg [PCIE_LANE-1:0] phystatus_reg2;
reg [PCIE_LANE-1:0] txsync_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 5:0] cfg_wait_cnt = 6'd0;
//---------- Output Register ---------------------------
reg cpllreset = 1'd0;
reg cpllpd = 1'd0;
reg rxusrclk_rst_reg1 = 1'd0;
reg rxusrclk_rst_reg2 = 1'd0;
reg dclk_rst_reg1 = 1'd0;
reg dclk_rst_reg2 = 1'd0;
reg gtreset = 1'd0;
reg userrdy = 1'd0;
reg [10:0] fsm = 11'd2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 11'b00000000001;
localparam FSM_CFG_WAIT = 11'b00000000010;
localparam FSM_CPLLRESET = 11'b00000000100;
localparam FSM_CPLLLOCK = 11'b00000001000;
localparam FSM_DRP = 11'b00000010000;
localparam FSM_GTRESET = 11'b00000100000;
localparam FSM_MMCM_LOCK = 11'b00001000000;
localparam FSM_RESETDONE = 11'b00010000000;
localparam FSM_CPLL_PD = 11'b00100000000;
localparam FSM_TXSYNC_START = 11'b01000000000;
localparam FSM_TXSYNC_DONE = 11'b10000000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
//---------- 1st Stage FF --------------------------
cplllock_reg1 <= {PCIE_LANE{1'd0}};
qpll_idle_reg1 <= 1'd0;
rate_idle_reg1 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg1 <= 1'd0;
resetdone_reg1 <= {PCIE_LANE{1'd0}};
phystatus_reg1 <= {PCIE_LANE{1'd0}};
txsync_done_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
cplllock_reg2 <= {PCIE_LANE{1'd0}};
qpll_idle_reg2 <= 1'd0;
rate_idle_reg2 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg2 <= 1'd0;
resetdone_reg2 <= {PCIE_LANE{1'd0}};
phystatus_reg2 <= {PCIE_LANE{1'd0}};
txsync_done_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
cplllock_reg1 <= RST_CPLLLOCK;
qpll_idle_reg1 <= RST_QPLL_IDLE;
rate_idle_reg1 <= RST_RATE_IDLE;
rxcdrlock_reg1 <= RST_RXCDRLOCK;
mmcm_lock_reg1 <= RST_MMCM_LOCK;
resetdone_reg1 <= RST_RESETDONE;
phystatus_reg1 <= RST_PHYSTATUS;
txsync_done_reg1 <= RST_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
cplllock_reg2 <= cplllock_reg1;
qpll_idle_reg2 <= qpll_idle_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
resetdone_reg2 <= resetdone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Configuration Reset Wait Counter ----------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
cfg_wait_cnt <= 6'd0;
else
//---------- Increment Configuration Reset Wait Counter
if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
//---------- Hold Configuration Reset Wait Counter -
else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt;
//---------- Reset Configuration Reset Wait Counter
else
cfg_wait_cnt <= 6'd0;
end
//---------- PIPE Reset FSM ----------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
end
//---------- Wait for Configuration Reset Delay ---
FSM_CFG_WAIT :
begin
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_CPLLRESET : FSM_CFG_WAIT);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Hold CPLL and GTX Channel in Reset ----
FSM_CPLLRESET :
begin
fsm <= ((&(~cplllock_reg2) && (&(~resetdone_reg2))) ? FSM_CPLLLOCK : FSM_CPLLRESET);
cpllreset <= 1'd1;
cpllpd <= cpllpd;
gtreset <= 1'd1;
userrdy <= userrdy;
end
//---------- Wait for CPLL Lock --------------------
FSM_CPLLLOCK :
begin
fsm <= (&cplllock_reg2 ? FSM_DRP : FSM_CPLLLOCK);
cpllreset <= 1'd0;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP Done to Setup Gen1 -------
FSM_DRP :
begin
fsm <= (&rate_idle_reg2 ? FSM_GTRESET : FSM_DRP);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Release GTX Channel Reset -------------
FSM_GTRESET :
begin
fsm <= FSM_MMCM_LOCK;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= 1'b0;
userrdy <= userrdy;
end
//---------- Wait for MMCM and RX CDR Lock ---------
FSM_MMCM_LOCK :
begin
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)) && (qpll_idle_reg2 || (PCIE_PLL_SEL == "CPLL")))
begin
fsm <= FSM_RESETDONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd1;
end
else
begin
fsm <= FSM_MMCM_LOCK;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd0;
end
end
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
FSM_RESETDONE :
begin
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_CPLL_PD : FSM_RESETDONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Power-Down CPLL if QPLL is Used for Gen1/Gen2
FSM_CPLL_PD :
begin
fsm <= ((PCIE_TXBUF_EN == "TRUE") ? FSM_IDLE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START :
begin
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE :
begin
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
endcase
end
end
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
always @ (posedge RST_RXUSRCLK)
begin
if (cpllreset)
begin
rxusrclk_rst_reg1 <= 1'd1;
rxusrclk_rst_reg2 <= 1'd1;
end
else
begin
rxusrclk_rst_reg1 <= 1'd0;
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
end
end
//---------- DCLK Reset Synchronizer -------------------------------------------
always @ (posedge RST_DCLK)
begin
if (cpllreset)
begin
dclk_rst_reg1 <= 1'd1;
dclk_rst_reg2 <= 1'd1;
end
else
begin
dclk_rst_reg1 <= 1'd0;
dclk_rst_reg2 <= dclk_rst_reg1;
end
end
//---------- PIPE Reset Output -------------------------------------------------
assign RST_CPLLRESET = cpllreset;
assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
assign RST_DCLK_RESET = dclk_rst_reg2;
assign RST_GTRESET = gtreset;
assign RST_USERRDY = userrdy;
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RST_IDLE = (fsm == FSM_IDLE);
assign RST_FSM = fsm;
endmodule |
module sky130_fd_sc_hs__tapvgnd2 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule |
module bsg_barrier
#(`BSG_INV_PARAM(dirs_p),lg_dirs_lp=`BSG_SAFE_CLOG2(dirs_p+1))
(
input clk_i
,input reset_i
// to remote nodes
,input [dirs_p-1:0] data_i // late
,output [dirs_p-1:0] data_o // early-ish
//
// control of the barrier:
//
// which inputs we will gather from
// and which outputs we send the gather output to
// and for the broadcast phase, the opposite.
//
// usually comes from a CSR (or bsg_tag)
//
,input [dirs_p-1:0] src_r_i
,input [lg_dirs_lp-1:0] dest_r_i
);
wire [dirs_p:0] data_r;
wire activate_n;
wire data_broadcast_in = data_r[dest_r_i];
wire sense_n, sense_r;
wire gather_and = & (~src_r_i | data_r[dirs_p-1:0]); // true if all selected bits are set to 1
wire gather_or = | (src_r_i & data_r[dirs_p-1:0]); // false if all selected bits are set to 0
// the barrier should go forward, based on the sense bit, if we are either all 0 or all 1.
wire gather_out = sense_r ? gather_or : gather_and;
//
// flip sense bit if we are receiving the incoming broadcast
// we are relying on the P bit still being high at the leaves
// sense_r broadcast_in sense_n
// 0 0 0
// 0 1 1
// 1 1 1
// 1 0 0
// if we see a transition on data_broadcast_in, then we have completed the barrier
assign sense_n = data_broadcast_in;
bsg_dff_reset #(.width_p(dirs_p+2)) dff
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i({activate_n, data_i[dirs_p-1:0], sense_n})
,.data_o({data_r[dirs_p], data_r[dirs_p-1:0], sense_r})
);
// this is simply a matter of propagating the value in question
wire [dirs_p-1:0] data_broadcast_out = { dirs_p { data_broadcast_in } } & src_r_i;
// here we propagate the gather_out value, either to network outputs, or to the local activate reg (at the root of the broadcast)
wire [dirs_p:0] dest_decode = 1 << (dest_r_i);
wire [dirs_p:0] data_gather_out = dest_decode & { (dirs_p+1) { gather_out } };
assign data_o = data_broadcast_out | data_gather_out[dirs_p-1:0];
assign activate_n = data_gather_out[dirs_p];
localparam debug_p = 0;
if (debug_p)
always @(negedge clk_i)
$display("%d: %m %b %b %b %b %b %b", $time, gather_and, gather_or, gather_out, sense_n, data_i, data_o);
endmodule |
module jbi_pktout_mux (/*AUTOARG*/
// Outputs
jbi_io_j_adtype, jbi_io_j_ad, jbi_io_j_adp,
// Inputs
sel_queue, sel_j_adbus, sct0rdq_install_state, sct0rdq_unmapped_error,
sct0rdq_jid, sct0rdq_data, sct0rdq_ue_err, sct1rdq_install_state,
sct1rdq_unmapped_error, sct1rdq_jid, sct1rdq_data, sct1rdq_ue_err,
sct2rdq_install_state, sct2rdq_unmapped_error, sct2rdq_jid, sct2rdq_data,
sct2rdq_ue_err, sct3rdq_install_state, sct3rdq_unmapped_error, sct3rdq_jid,
sct3rdq_data, sct3rdq_ue_err, ncio_pio_ue, ncio_pio_be, ncio_pio_ad,
ncio_mondo_agnt_id, ncio_mondo_cpu_id, dbg_data, unused_jid, inj_err_j_ad,
csr_jbi_debug_info_enb, thread_id, sct0rdq_trans_count, sct1rdq_trans_count,
sct2rdq_trans_count, sct3rdq_trans_count, ncio_prqq_level, ncio_makq_level,
clk
);
`include "jbi_mout.h"
// Select.
input [2:0] sel_queue;
input [3:0] sel_j_adbus;
// Input sources
// SCT0 RDQ.
input sct0rdq_install_state;
input sct0rdq_unmapped_error;
input [5:0] sct0rdq_jid;
input [127:0] sct0rdq_data;
input sct0rdq_ue_err;
// SCT1 RDQ.
input sct1rdq_install_state;
input sct1rdq_unmapped_error;
input [5:0] sct1rdq_jid;
input [127:0] sct1rdq_data;
input sct1rdq_ue_err;
// SCT2 RDQ.
input sct2rdq_install_state;
input sct2rdq_unmapped_error;
input [5:0] sct2rdq_jid;
input [127:0] sct2rdq_data;
input sct2rdq_ue_err;
// SCT3 RDQ.
input sct3rdq_install_state;
input sct3rdq_unmapped_error;
input [5:0] sct3rdq_jid;
input [127:0] sct3rdq_data;
input sct3rdq_ue_err;
// PIO RQQ.
input ncio_pio_ue;
input [15:0] ncio_pio_be;
input [63:0] ncio_pio_ad;
// PIO ACKQ.
input [4:0] ncio_mondo_agnt_id;
input [4:0] ncio_mondo_cpu_id;
// DBGQ.
input [127:0] dbg_data;
// YID-to-JID Translation.
input [5:0] unused_jid;
// J_ADTYPE, J_AD, J_ADP busses.
output [7:0] jbi_io_j_adtype;
output [127:0] jbi_io_j_ad;
output [3:0] jbi_io_j_adp;
// Error injection.
input [3:0] inj_err_j_ad; // Inject an error on the J_AD[] (bit3=J_AD[96], bit2=J_AD[64], bit1=J_AD[32], bit0=J_AD[0]).
// Debug Info.
input csr_jbi_debug_info_enb; // Put these data fields in high half of JBus Address Cycles.
input [4:0] thread_id;
input [3:0] sct0rdq_trans_count;
input [3:0] sct1rdq_trans_count;
input [3:0] sct2rdq_trans_count;
input [3:0] sct3rdq_trans_count;
input [4:0] ncio_prqq_level;
input [4:0] ncio_makq_level;
// Clock.
input clk;
// Wires and Regs.
wire sct0rdq_ue_err_p1;
wire sct1rdq_ue_err_p1;
wire sct2rdq_ue_err_p1;
wire sct3rdq_ue_err_p1;
reg [127:0] j_ad;
reg [7:0] jbi_io_j_adtype;
// Preformatting Debug Info field.
wire [111:64] debug_info = { 11'b000_0000_0000, thread_id[4:0], sct0rdq_trans_count[3:0], sct1rdq_trans_count[3:0], sct2rdq_trans_count[3:0], sct3rdq_trans_count[3:0],
3'b000, ncio_prqq_level[4:0], 3'b000, ncio_makq_level[4:0] };
// IDLE Output formatting.
//
wire [7:0] idle_adtype = { 8'hff };
wire [127:0] idle_ad = csr_jbi_debug_info_enb? { 16'hffff, debug_info[111:64], 64'hffff_ffff_ffff_ffff }:
{ 64'hffff_ffff_ffff_ffff, 64'hffff_ffff_ffff_ffff };
// SCT0 RDQ Output formatting.
//
// RD16
wire [3:0] sct0rdq_target_aid = sct0rdq_jid[5:2];
wire [1:0] sct0rdq_trans_id = sct0rdq_jid[1:0];
wire [7:0] sct0rdq_rd16_adtype = { 2'h2, sct0rdq_target_aid, sct0rdq_trans_id };
wire [127:0] sct0rdq_rd16_ad = { sct0rdq_data[127:0] };
// RD64
wire [2:0] sct0rdq_state = (sct0rdq_install_state == `JBI_SCTAG_TAG_INSTALL_INVALID)? INSTALL_INVALID:
INSTALL_SHARED;
wire [1:0] sct0rdq_uece_err = { sct0rdq_ue_err, 1'b0 };
wire [1:0] sct0rdq_uece_err_p1 = { sct0rdq_ue_err_p1, 1'b0 };
dff_ns sct0rdq_ue_err_p1_reg (.din(sct0rdq_ue_err), .q(sct0rdq_ue_err_p1), .clk(clk));
//
wire [7:0] sct0rdq_rd64_0_adtype = { 2'h1, sct0rdq_target_aid, sct0rdq_trans_id };
wire [127:0] sct0rdq_rd64_0_ad = { sct0rdq_data[127:0] };
//
wire [7:0] sct0rdq_rd64_1_adtype = { 1'h0, sct0rdq_uece_err_p1, sct0rdq_uece_err, sct0rdq_state };
wire [127:0] sct0rdq_rd64_1_ad = { sct0rdq_data[127:0] };
//
wire [7:0] sct0rdq_rd64_2_adtype = { 3'h0, sct0rdq_uece_err, 3'h0 };
wire [127:0] sct0rdq_rd64_2_ad = { sct0rdq_data[127:0] };
//
wire [7:0] sct0rdq_rd64_3_adtype = { 3'h0, sct0rdq_uece_err, 3'h0 };
wire [127:0] sct0rdq_rd64_3_ad = { sct0rdq_data[127:0] };
// RDER
wire [7:0] sct0rdq_rder_adtype = { 2'h0, sct0rdq_target_aid, sct0rdq_trans_id };
wire [2:0] sct0rdq_rder_error = (sct0rdq_unmapped_error)? RDER_UNMAPPED: RDER_BUS_ERROR;
wire [127:0] sct0rdq_rder_ad = { sct0rdq_data[127:3], sct0rdq_rder_error[2:0] };
// SCT1 RDQ Output formatting.
//
// RD16
wire [3:0] sct1rdq_target_aid = sct1rdq_jid[5:2];
wire [1:0] sct1rdq_trans_id = sct1rdq_jid[1:0];
wire [7:0] sct1rdq_rd16_adtype = { 2'h2, sct1rdq_target_aid, sct1rdq_trans_id };
wire [127:0] sct1rdq_rd16_ad = { sct1rdq_data[127:0] };
// RD64
wire [2:0] sct1rdq_state = (sct1rdq_install_state == `JBI_SCTAG_TAG_INSTALL_INVALID)? INSTALL_INVALID:
INSTALL_SHARED;
wire [1:0] sct1rdq_uece_err = { sct1rdq_ue_err, 1'b0 };
wire [1:0] sct1rdq_uece_err_p1 = { sct1rdq_ue_err_p1, 1'b0 };
dff_ns sct1rdq_ue_err_p1_reg (.din(sct1rdq_ue_err), .q(sct1rdq_ue_err_p1), .clk(clk));
//
wire [7:0] sct1rdq_rd64_0_adtype = { 2'h1, sct1rdq_target_aid, sct1rdq_trans_id };
wire [127:0] sct1rdq_rd64_0_ad = { sct1rdq_data[127:0] };
//
wire [7:0] sct1rdq_rd64_1_adtype = { 1'h0, sct1rdq_uece_err_p1, sct1rdq_uece_err, sct1rdq_state };
wire [127:0] sct1rdq_rd64_1_ad = { sct1rdq_data[127:0] };
//
wire [7:0] sct1rdq_rd64_2_adtype = { 3'h0, sct1rdq_uece_err, 3'h0 };
wire [127:0] sct1rdq_rd64_2_ad = { sct1rdq_data[127:0] };
//
wire [7:0] sct1rdq_rd64_3_adtype = { 3'h0, sct1rdq_uece_err, 3'h0 };
wire [127:0] sct1rdq_rd64_3_ad = { sct1rdq_data[127:0] };
// RDER
wire [7:0] sct1rdq_rder_adtype = { 2'h0, sct1rdq_target_aid, sct1rdq_trans_id };
wire [2:0] sct1rdq_rder_error = (sct1rdq_unmapped_error)? RDER_UNMAPPED: RDER_BUS_ERROR;
wire [127:0] sct1rdq_rder_ad = { sct1rdq_data[127:3], sct1rdq_rder_error[2:0] };
// SCT2 RDQ Output formatting.
//
// RD16
wire [3:0] sct2rdq_target_aid = sct2rdq_jid[5:2];
wire [1:0] sct2rdq_trans_id = sct2rdq_jid[1:0];
wire [7:0] sct2rdq_rd16_adtype = { 2'h2, sct2rdq_target_aid, sct2rdq_trans_id };
wire [127:0] sct2rdq_rd16_ad = { sct2rdq_data[127:0] };
// RD64
wire [2:0] sct2rdq_state = (sct2rdq_install_state == `JBI_SCTAG_TAG_INSTALL_INVALID)? INSTALL_INVALID:
INSTALL_SHARED;
wire [1:0] sct2rdq_uece_err = { sct2rdq_ue_err, 1'b0 };
wire [1:0] sct2rdq_uece_err_p1 = { sct2rdq_ue_err_p1, 1'b0 };
dff_ns sct2rdq_ue_err_p1_reg (.din(sct2rdq_ue_err), .q(sct2rdq_ue_err_p1), .clk(clk));
//
wire [7:0] sct2rdq_rd64_0_adtype = { 2'h1, sct2rdq_target_aid, sct2rdq_trans_id };
wire [127:0] sct2rdq_rd64_0_ad = { sct2rdq_data[127:0] };
//
wire [7:0] sct2rdq_rd64_1_adtype = { 1'h0, sct2rdq_uece_err_p1, sct2rdq_uece_err, sct2rdq_state };
wire [127:0] sct2rdq_rd64_1_ad = { sct2rdq_data[127:0] };
//
wire [7:0] sct2rdq_rd64_2_adtype = { 3'h0, sct2rdq_uece_err, 3'h0 };
wire [127:0] sct2rdq_rd64_2_ad = { sct2rdq_data[127:0] };
//
wire [7:0] sct2rdq_rd64_3_adtype = { 3'h0, sct2rdq_uece_err, 3'h0 };
wire [127:0] sct2rdq_rd64_3_ad = { sct2rdq_data[127:0] };
// RDER
wire [7:0] sct2rdq_rder_adtype = { 2'h0, sct2rdq_target_aid, sct2rdq_trans_id };
wire [2:0] sct2rdq_rder_error = (sct2rdq_unmapped_error)? RDER_UNMAPPED: RDER_BUS_ERROR;
wire [127:0] sct2rdq_rder_ad = { sct2rdq_data[127:3], sct2rdq_rder_error[2:0] };
// SCT3 RDQ Output formatting.
//
// RD16
wire [3:0] sct3rdq_target_aid = sct3rdq_jid[5:2];
wire [1:0] sct3rdq_trans_id = sct3rdq_jid[1:0];
wire [7:0] sct3rdq_rd16_adtype = { 2'h2, sct3rdq_target_aid[3:0], sct3rdq_trans_id[1:0] };
wire [127:0] sct3rdq_rd16_ad = { sct3rdq_data[127:0] };
// RD64
wire [2:0] sct3rdq_state = (sct3rdq_install_state == `JBI_SCTAG_TAG_INSTALL_INVALID)? INSTALL_INVALID:
INSTALL_SHARED;
wire [1:0] sct3rdq_uece_err = { sct3rdq_ue_err, 1'b0 };
wire [1:0] sct3rdq_uece_err_p1 = { sct3rdq_ue_err_p1, 1'b0 };
dff_ns sct3rdq_ue_err_p1_reg (.din(sct3rdq_ue_err), .q(sct3rdq_ue_err_p1), .clk(clk));
//
wire [7:0] sct3rdq_rd64_0_adtype = { 2'h1, sct3rdq_target_aid[3:0], sct3rdq_trans_id[1:0] };
wire [127:0] sct3rdq_rd64_0_ad = { sct3rdq_data[127:0] };
//
wire [7:0] sct3rdq_rd64_1_adtype = { 1'h0, sct3rdq_uece_err_p1, sct3rdq_uece_err, sct3rdq_state };
wire [127:0] sct3rdq_rd64_1_ad = { sct3rdq_data[127:0] };
//
wire [7:0] sct3rdq_rd64_2_adtype = { 3'h0, sct3rdq_uece_err, 3'h0 };
wire [127:0] sct3rdq_rd64_2_ad = { sct3rdq_data[127:0] };
//
wire [7:0] sct3rdq_rd64_3_adtype = { 3'h0, sct3rdq_uece_err, 3'h0 };
wire [127:0] sct3rdq_rd64_3_ad = { sct3rdq_data[127:0] };
// RDER
wire [7:0] sct3rdq_rder_adtype = { 2'h0, sct3rdq_target_aid, sct3rdq_trans_id };
wire [2:0] sct3rdq_rder_error = (sct3rdq_unmapped_error)? RDER_UNMAPPED: RDER_BUS_ERROR;
wire [127:0] sct3rdq_rder_ad = { sct3rdq_data[127:3], sct3rdq_rder_error[2:0] };
// PIO RQQ Output formatting.
//
// NCRD
wire [7:0] piorqq_ncrd_adtype = { 2'h3, unused_jid[5:2], unused_jid[1:0] };
wire [127:0] piorqq_ncrd_ad = csr_jbi_debug_info_enb? { ncio_pio_be[15:0], debug_info[111:64], ncio_pio_be[15:0], TRANS_NCRD, ncio_pio_ad[42:0] }:
{ ncio_pio_be[15:0], TRANS_NCRD, ncio_pio_ad[42:0], ncio_pio_be[15:0], TRANS_NCRD, ncio_pio_ad[42:0] };
// NCWR
wire [7:0] piorqq_ncwr_0_adtype = { 2'h3, 4'h0, 2'h0 };
wire [127:0] piorqq_ncwr_0_ad = csr_jbi_debug_info_enb? { ncio_pio_be[15:0], debug_info[111:64], ncio_pio_be[15:0], TRANS_NCWR, ncio_pio_ad[42:0] }:
{ ncio_pio_be[15:0], TRANS_NCWR, ncio_pio_ad[42:0], ncio_pio_be[15:0], TRANS_NCWR, ncio_pio_ad[42:0] };
//
wire [7:0] piorqq_ncwr_1_adtype = { 3'h0, ncio_pio_ue, 1'h0, 3'h0 };
wire [127:0] piorqq_ncwr_1_ad = { ncio_pio_ad[63:0], ncio_pio_ad[63:0] };
// PIO ACKQ Output formatting.
//
// INTACK
wire [4:0] pioackq_target_aid = ncio_mondo_agnt_id;
wire [4:0] pioackq_source_aid = ncio_mondo_cpu_id;
//
wire [7:0] pioackq_intack_adtype = { 2'h3, 4'h0, 2'h0 };
wire [127:0] pioackq_intack_ad = csr_jbi_debug_info_enb? { 16'h0000, debug_info[111:64],
16'h0000, TRANS_INTACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000 }:
{ 16'h0000, TRANS_INTACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000,
16'h0000, TRANS_INTACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000 };
// INTNACK
wire [7:0] pioackq_intnack_adtype = { 2'h3, 4'h0, 2'h0 };
wire [127:0] pioackq_intnack_ad = csr_jbi_debug_info_enb? { 16'h0000, debug_info[111:64],
16'h0000, TRANS_INTNACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000 }:
{ 16'h0000, TRANS_INTNACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000,
16'h0000, TRANS_INTNACK, 2'h0, pioackq_target_aid[4:0], pioackq_source_aid[4:0], 31'h0000_0000 };
// DBGQ
wire [3:0] dbgq_target_aid = 4'h4;
wire [1:0] dbgq_trans_id = 2'h0;
wire [7:0] dbgq_rd16_adtype = { 2'h2, dbgq_target_aid[3:0], dbgq_trans_id[1:0] };
wire [127:0] dbgq_rd16_ad = { dbg_data[127:0] };
// Packet assembly multiplexer.
always @(/*AS*/dbgq_rd16_ad or dbgq_rd16_adtype or idle_ad or idle_adtype
or pioackq_intack_ad or pioackq_intack_adtype or pioackq_intnack_ad
or pioackq_intnack_adtype or piorqq_ncrd_ad or piorqq_ncrd_adtype
or piorqq_ncwr_0_ad or piorqq_ncwr_0_adtype or piorqq_ncwr_1_ad
or piorqq_ncwr_1_adtype or sct0rdq_rd16_ad or sct0rdq_rd16_adtype
or sct0rdq_rd64_0_ad or sct0rdq_rd64_0_adtype or sct0rdq_rd64_1_ad
or sct0rdq_rd64_1_adtype or sct0rdq_rd64_2_ad
or sct0rdq_rd64_2_adtype or sct0rdq_rd64_3_ad
or sct0rdq_rd64_3_adtype or sct0rdq_rder_ad or sct0rdq_rder_adtype
or sct1rdq_rd16_ad or sct1rdq_rd16_adtype or sct1rdq_rd64_0_ad
or sct1rdq_rd64_0_adtype or sct1rdq_rd64_1_ad
or sct1rdq_rd64_1_adtype or sct1rdq_rd64_2_ad
or sct1rdq_rd64_2_adtype or sct1rdq_rd64_3_ad
or sct1rdq_rd64_3_adtype or sct1rdq_rder_ad or sct1rdq_rder_adtype
or sct2rdq_rd16_ad or sct2rdq_rd16_adtype or sct2rdq_rd64_0_ad
or sct2rdq_rd64_0_adtype or sct2rdq_rd64_1_ad
or sct2rdq_rd64_1_adtype or sct2rdq_rd64_2_ad
or sct2rdq_rd64_2_adtype or sct2rdq_rd64_3_ad
or sct2rdq_rd64_3_adtype or sct2rdq_rder_ad or sct2rdq_rder_adtype
or sct3rdq_rd16_ad or sct3rdq_rd16_adtype or sct3rdq_rd64_0_ad
or sct3rdq_rd64_0_adtype or sct3rdq_rd64_1_ad
or sct3rdq_rd64_1_adtype or sct3rdq_rd64_2_ad
or sct3rdq_rd64_2_adtype or sct3rdq_rd64_3_ad
or sct3rdq_rd64_3_adtype or sct3rdq_rder_ad or sct3rdq_rder_adtype
or sel_j_adbus or sel_queue) begin
casex ({ sel_queue, sel_j_adbus })
{ LRQ_X, SEL_IDLE }: { jbi_io_j_adtype, j_ad } = { idle_adtype, idle_ad };
{ LRQ_SCT0RDQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd16_adtype, sct0rdq_rd16_ad };
{ LRQ_SCT0RDQ, SEL_RD64_0 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd64_0_adtype, sct0rdq_rd64_0_ad };
{ LRQ_SCT0RDQ, SEL_RD64_1 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd64_1_adtype, sct0rdq_rd64_1_ad };
{ LRQ_SCT0RDQ, SEL_RD64_2 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd64_2_adtype, sct0rdq_rd64_2_ad };
{ LRQ_SCT0RDQ, SEL_RD64_3 }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rd64_3_adtype, sct0rdq_rd64_3_ad };
{ LRQ_SCT0RDQ, SEL_RDER }: { jbi_io_j_adtype, j_ad } = { sct0rdq_rder_adtype, sct0rdq_rder_ad };
{ LRQ_SCT1RDQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd16_adtype, sct1rdq_rd16_ad };
{ LRQ_SCT1RDQ, SEL_RD64_0 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd64_0_adtype, sct1rdq_rd64_0_ad };
{ LRQ_SCT1RDQ, SEL_RD64_1 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd64_1_adtype, sct1rdq_rd64_1_ad };
{ LRQ_SCT1RDQ, SEL_RD64_2 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd64_2_adtype, sct1rdq_rd64_2_ad };
{ LRQ_SCT1RDQ, SEL_RD64_3 }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rd64_3_adtype, sct1rdq_rd64_3_ad };
{ LRQ_SCT1RDQ, SEL_RDER }: { jbi_io_j_adtype, j_ad } = { sct1rdq_rder_adtype, sct1rdq_rder_ad };
{ LRQ_SCT2RDQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd16_adtype, sct2rdq_rd16_ad };
{ LRQ_SCT2RDQ, SEL_RD64_0 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd64_0_adtype, sct2rdq_rd64_0_ad };
{ LRQ_SCT2RDQ, SEL_RD64_1 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd64_1_adtype, sct2rdq_rd64_1_ad };
{ LRQ_SCT2RDQ, SEL_RD64_2 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd64_2_adtype, sct2rdq_rd64_2_ad };
{ LRQ_SCT2RDQ, SEL_RD64_3 }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rd64_3_adtype, sct2rdq_rd64_3_ad };
{ LRQ_SCT2RDQ, SEL_RDER }: { jbi_io_j_adtype, j_ad } = { sct2rdq_rder_adtype, sct2rdq_rder_ad };
{ LRQ_SCT3RDQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd16_adtype, sct3rdq_rd16_ad };
{ LRQ_SCT3RDQ, SEL_RD64_0 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd64_0_adtype, sct3rdq_rd64_0_ad };
{ LRQ_SCT3RDQ, SEL_RD64_1 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd64_1_adtype, sct3rdq_rd64_1_ad };
{ LRQ_SCT3RDQ, SEL_RD64_2 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd64_2_adtype, sct3rdq_rd64_2_ad };
{ LRQ_SCT3RDQ, SEL_RD64_3 }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rd64_3_adtype, sct3rdq_rd64_3_ad };
{ LRQ_SCT3RDQ, SEL_RDER }: { jbi_io_j_adtype, j_ad } = { sct3rdq_rder_adtype, sct3rdq_rder_ad };
{ LRQ_PIORQQ, SEL_NCRD }: { jbi_io_j_adtype, j_ad } = { piorqq_ncrd_adtype, piorqq_ncrd_ad };
{ LRQ_PIORQQ, SEL_NCWR_0 }: { jbi_io_j_adtype, j_ad } = { piorqq_ncwr_0_adtype, piorqq_ncwr_0_ad };
{ LRQ_PIORQQ, SEL_NCWR_1 }: { jbi_io_j_adtype, j_ad } = { piorqq_ncwr_1_adtype, piorqq_ncwr_1_ad };
{ LRQ_PIOACKQ, SEL_INTACK }: { jbi_io_j_adtype, j_ad } = { pioackq_intack_adtype, pioackq_intack_ad };
{ LRQ_PIOACKQ, SEL_INTNACK }: { jbi_io_j_adtype, j_ad } = { pioackq_intnack_adtype, pioackq_intnack_ad };
{ LRQ_DBGQ, SEL_RD16 }: { jbi_io_j_adtype, j_ad } = { dbgq_rd16_adtype, dbgq_rd16_ad };
default: { jbi_io_j_adtype, j_ad } = { 8'bX, 128'bX };
endcase
end
// Error injection (inj_err_j_ad[3]=J_AD[96], [2]=J_AD[64], [1]=J_AD[32], [0]=J_AD[0]).
assign jbi_io_j_ad[127:0] = { j_ad[127:97], (j_ad[96]^inj_err_j_ad[3]),
j_ad[ 95:65], (j_ad[64]^inj_err_j_ad[2]),
j_ad[ 63:33], (j_ad[32]^inj_err_j_ad[1]),
j_ad[ 31: 1], (j_ad[ 0]^inj_err_j_ad[0]) };
// J_ADP odd parity bits generation (undriven, 1's, is correct parity [JBus Spec pg 20]).
assign jbi_io_j_adp[3] = ~((^ j_ad[127:96]) ^ (^ jbi_io_j_adtype[7:0]));
assign jbi_io_j_adp[2] = ~ (^ j_ad[ 95:64]);
assign jbi_io_j_adp[1] = ~ (^ j_ad[ 63:32]);
assign jbi_io_j_adp[0] = ~ (^ j_ad[ 31: 0]);
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Check: Address halves are the same for address cycles.
always @(posedge clk) begin
if ((sel_j_adbus == SEL_IDLE || sel_j_adbus == SEL_INTACK || sel_j_adbus == SEL_INTNACK || sel_j_adbus == SEL_NCRD || sel_j_adbus == SEL_NCWR_0) &&
(j_ad[127:64] != j_ad[63:0]) && !csr_jbi_debug_info_enb) begin
$dispmon ("jbi_mout_jbi_pktout_mux", 49, "%d %m: ERROR - Upper and halves of J_AD[] must match on address cycles. (%h, %h)", $time, j_ad[127:64], j_ad[63:0]);
end
end
// Check: Select of case has a valid state.
always @(posedge clk) begin
if ({ jbi_io_j_adtype, j_ad } === { 8'bX, 128'bX }) begin
$dispmon ("jbi_mout_jbi_pktout_mux", 49, "%d %m: ERROR - Invalid multiplexer select value. (%b)", $time, sel_j_adbus);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule |
module addrgen(
clk,
nrst,
start,
n,
wraddr,
wren,
rdaddr,
vexaddr
);
input clk;
input nrst;
input start;
input [15:0]n;
output [10:0]wraddr;
output [10:0]rdaddr;
output [13:0]vexaddr;
output wren;
reg [15:0]counter1;
reg [15:0]counter2;
reg [15:0]counter3;
reg [15:0]counter4;
reg [15:0]timer1;
reg [15:0]timer2;
reg [15:0]timer3;
reg [29:0]t1_exp_dly;
reg [29:0]t2_exp_dly;
reg [29:0]start_dly;
wire t1_expire = timer1[15];
wire t2_expire = timer2[15];
wire t3_expire = timer3[15];
assign rdaddr = counter1[10:0];
assign vexaddr = counter3[13:0];
assign wraddr = counter4[10:0];
//---------------------------------------------------------------------//
// Timers
//---------------------------------------------------------------------//
// Timer T1
// - Loads 'n' on start.
// - Stops counting when it reaches -1.
// - Decrements on t2_expire;
always @(posedge clk)
if (~nrst) timer1 <= -1;
else if(start) timer1 <= {1'b0,n[14:0]};
else if(!t1_expire && t2_expire) timer1 <= timer1 - 1;
// Timer T2
// - Counts down from T1 divided by 4.
// - Resets when it hits -1.
// - Stops decrementing the initial input once t3 expires.
wire [15:0] t2_startval = {3'b0, n[15:2]} - 1;
wire [15:0] t1_minus = timer1 - 5;
always @(posedge clk)
if (~nrst) timer2 <= -1;
else if(start) timer2 <= t2_startval;
else if(!t1_expire && t2_expire && !t3_expire) timer2 <= {3'b0, t1_minus[15:2]};
else if(!t1_expire && t2_expire && t3_expire) timer2 <= 30;
else if(!t1_expire && !t2_expire) timer2 <= timer2 - 1;
// Timer T3
always @(posedge clk)
if(~nrst) timer3 <= -1;
else if(start) timer3 <= n-128; // For a 30 cycle pipeline.
else if(!t3_expire && t2_expire) timer3 <= timer3 - 1;
// Shift registers for delayed counting.
always@(posedge clk)
if (~nrst) t1_exp_dly <= 0;
else t1_exp_dly <= {t1_exp_dly[28:0], t1_expire};
always@(posedge clk)
if(~nrst) t2_exp_dly <= 0;
else t2_exp_dly <= {t2_exp_dly[28:0], t2_expire};
always@(posedge clk)
if(~nrst) start_dly <= 0;
else start_dly <= {start_dly[28:0], start};
wire sig_a = t1_exp_dly[24];
wire sig_b = t2_exp_dly[24];
wire sig_c = start_dly[24];
wire sig_d = t1_exp_dly[29];
wire sig_e = t2_exp_dly[29];
wire sig_f = start_dly[29];
assign wren = !sig_d;
//---------------------------------------------------------------------//
// Logic for generating rdaddr.
//---------------------------------------------------------------------//
// Counter C1
// - Counts up from 0.
// - Resets when t2 expires.
// - Stops when t1 expires.
always @(posedge clk)
if (~nrst) counter1 <= -1;
else if(start) counter1 <= 0;
else if(!t1_expire && t2_expire) counter1 <= 0;
else if(!t1_expire && !t2_expire) counter1 <= counter1 + 1;
//---------------------------------------------------------------------//
// Logic for generating vex_addr.
//---------------------------------------------------------------------//
// Counter C2
// - Counts up from 0.
// - Resets at start.
// - Stops counting when t4 expires.
always @(posedge clk)
if(~nrst) counter2 <= -1;
else if(sig_c) counter2 <= 0;
else if(!sig_a && sig_b) counter2 <= counter2 + 1;
// Counter C3
// - Counts up from 0.
// - Resets at start.
// - Stops counting when t1 expires.
always @(posedge clk)
if(~nrst) counter3 <= -1;
else if(sig_c) counter3 <= 0;
else if(!sig_a && sig_b) counter3 <= counter2 + 1;
else if(!sig_a && !sig_b) counter3 <= counter3 + 8;
//---------------------------------------------------------------------//
// Logic for generating wraddr.
//---------------------------------------------------------------------//
// Counter C4
// - Counts up from 0.
// - Resets when t2 expires.
// - Stops when t1 expires.
always @(posedge clk)
if (~nrst) counter4 <= -1;
else if(sig_f) counter4 <= 0;
else if(!sig_d && sig_e) counter4 <= 0;
else if(!sig_d && !sig_e) counter4 <= counter4 + 1;
endmodule |
module sky130_fd_sc_hd__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module top(
input i_ce,
input i_clk,
input i_clkb,
input i_rst,
input [11:0] io,
output o_q1,
output o_q2
);
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_AO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_AO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_A_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_BO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_BO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_B_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_CO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_CO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_C_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_DO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_DO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X0Y42_D_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_AMUX;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_AO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_A_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_BMUX;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_BO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_BO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_B_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_CMUX;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_CO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_CO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_C_XOR;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D1;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D2;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D3;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D4;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_DO5;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_DO6;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D_CY;
wire [0:0] CLBLL_L_X2Y42_SLICE_X1Y42_D_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_AMUX;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_AO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_A_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_BMUX;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_BO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_BO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_B_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_CMUX;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_CO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_CO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_C_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_DO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_DO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X0Y43_D_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_AO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_AO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_A_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_BO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_BO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_B_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_CO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_CO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_C_XOR;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D1;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D2;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D3;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D4;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_DO5;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_DO6;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D_CY;
wire [0:0] CLBLL_L_X2Y43_SLICE_X1Y43_D_XOR;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S1;
wire [0:0] LIOB33_X0Y33_IOB_X0Y34_I;
wire [0:0] LIOB33_X0Y35_IOB_X0Y35_I;
wire [0:0] LIOB33_X0Y35_IOB_X0Y36_I;
wire [0:0] LIOB33_X0Y37_IOB_X0Y37_I;
wire [0:0] LIOB33_X0Y37_IOB_X0Y38_I;
wire [0:0] LIOB33_X0Y39_IOB_X0Y39_I;
wire [0:0] LIOB33_X0Y39_IOB_X0Y40_I;
wire [0:0] LIOB33_X0Y41_IOB_X0Y41_I;
wire [0:0] LIOB33_X0Y41_IOB_X0Y42_I;
wire [0:0] LIOB33_X0Y43_IOB_X0Y43_I;
wire [0:0] LIOB33_X0Y45_IOB_X0Y45_I;
wire [0:0] LIOB33_X0Y45_IOB_X0Y46_I;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CE1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CLK;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CLKB;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_D;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q2;
wire [0:0] LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_SR;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CE1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CLK;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CLKB;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_D;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q2;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_SR;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CE1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CLK;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CLKB;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_D;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q2;
wire [0:0] LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_SR;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_CE1;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_CLK;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_CLKB;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_D;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_Q1;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_Q2;
wire [0:0] LIOI3_X0Y33_ILOGIC_X0Y34_SR;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_CE1;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_CLK;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_CLKB;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_D;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_Q1;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_Q2;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y35_SR;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_CE1;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_CLK;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_CLKB;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_D;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_Q1;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_Q2;
wire [0:0] LIOI3_X0Y35_ILOGIC_X0Y36_SR;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_CE1;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_CLK;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_CLKB;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_D;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_Q1;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_Q2;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y39_SR;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_CE1;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_CLK;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_CLKB;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_D;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_Q1;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_Q2;
wire [0:0] LIOI3_X0Y39_ILOGIC_X0Y40_SR;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_CE1;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_CLK;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_CLKB;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_D;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_Q1;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_Q2;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y41_SR;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_CE1;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_CLK;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_CLKB;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_D;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_Q1;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_Q2;
wire [0:0] LIOI3_X0Y41_ILOGIC_X0Y42_SR;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_CE1;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_CLK;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_CLKB;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_D;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_Q1;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_Q2;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y45_SR;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_CE1;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_CLK;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_CLKB;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_D;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_Q1;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_Q2;
wire [0:0] LIOI3_X0Y45_ILOGIC_X0Y46_SR;
wire [0:0] RIOB33_X43Y23_IOB_X1Y24_I;
wire [0:0] RIOB33_X43Y25_IOB_X1Y26_I;
wire [0:0] RIOB33_X43Y43_IOB_X1Y43_O;
wire [0:0] RIOB33_X43Y43_IOB_X1Y44_O;
wire [0:0] RIOB33_X43Y45_IOB_X1Y45_I;
wire [0:0] RIOB33_X43Y45_IOB_X1Y46_I;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_D1;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_OQ;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_T1;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_TQ;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_D1;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_OQ;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_T1;
wire [0:0] RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_TQ;
wire [0:0] RIOI3_X43Y23_ILOGIC_X1Y24_D;
wire [0:0] RIOI3_X43Y23_ILOGIC_X1Y24_O;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_D;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_O;
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X0Y42_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X0Y42_DO5),
.O6(CLBLL_L_X2Y42_SLICE_X0Y42_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X0Y42_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X0Y42_CO5),
.O6(CLBLL_L_X2Y42_SLICE_X0Y42_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X0Y42_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X0Y42_BO5),
.O6(CLBLL_L_X2Y42_SLICE_X0Y42_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X0Y42_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X0Y42_AO5),
.O6(CLBLL_L_X2Y42_SLICE_X0Y42_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y42_SLICE_X1Y42_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X1Y42_DO5),
.O6(CLBLL_L_X2Y42_SLICE_X1Y42_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000010100000000)
) CLBLL_L_X2Y42_SLICE_X1Y42_CLUT (
.I0(LIOI3_X0Y35_ILOGIC_X0Y36_Q1),
.I1(LIOI3_X0Y33_ILOGIC_X0Y34_Q1),
.I2(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q1),
.I3(1'b1),
.I4(LIOI3_X0Y35_ILOGIC_X0Y35_Q1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X1Y42_CO5),
.O6(CLBLL_L_X2Y42_SLICE_X1Y42_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000500000000)
) CLBLL_L_X2Y42_SLICE_X1Y42_BLUT (
.I0(LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q1),
.I1(1'b1),
.I2(LIOI3_X0Y45_ILOGIC_X0Y45_Q1),
.I3(LIOI3_X0Y41_ILOGIC_X0Y42_Q1),
.I4(LIOI3_X0Y45_ILOGIC_X0Y46_Q1),
.I5(1'b1),
.O5(CLBLL_L_X2Y42_SLICE_X1Y42_BO5),
.O6(CLBLL_L_X2Y42_SLICE_X1Y42_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'hfffffffdffffffff)
) CLBLL_L_X2Y42_SLICE_X1Y42_ALUT (
.I0(CLBLL_L_X2Y42_SLICE_X1Y42_BO6),
.I1(LIOI3_X0Y39_ILOGIC_X0Y39_Q1),
.I2(LIOI3_X0Y41_ILOGIC_X0Y41_Q1),
.I3(LIOI3_X0Y39_ILOGIC_X0Y40_Q1),
.I4(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q1),
.I5(CLBLL_L_X2Y42_SLICE_X1Y42_CO6),
.O5(CLBLL_L_X2Y42_SLICE_X1Y42_AO5),
.O6(CLBLL_L_X2Y42_SLICE_X1Y42_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X0Y43_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X0Y43_DO5),
.O6(CLBLL_L_X2Y43_SLICE_X0Y43_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000010100000000)
) CLBLL_L_X2Y43_SLICE_X0Y43_CLUT (
.I0(LIOI3_X0Y35_ILOGIC_X0Y36_Q2),
.I1(LIOI3_X0Y33_ILOGIC_X0Y34_Q2),
.I2(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q2),
.I3(1'b1),
.I4(LIOI3_X0Y35_ILOGIC_X0Y35_Q2),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X0Y43_CO5),
.O6(CLBLL_L_X2Y43_SLICE_X0Y43_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000500000000)
) CLBLL_L_X2Y43_SLICE_X0Y43_BLUT (
.I0(LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q2),
.I1(1'b1),
.I2(LIOI3_X0Y45_ILOGIC_X0Y45_Q2),
.I3(LIOI3_X0Y41_ILOGIC_X0Y42_Q2),
.I4(LIOI3_X0Y45_ILOGIC_X0Y46_Q2),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X0Y43_BO5),
.O6(CLBLL_L_X2Y43_SLICE_X0Y43_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'hfffffffdffffffff)
) CLBLL_L_X2Y43_SLICE_X0Y43_ALUT (
.I0(CLBLL_L_X2Y43_SLICE_X0Y43_BO6),
.I1(LIOI3_X0Y39_ILOGIC_X0Y39_Q2),
.I2(LIOI3_X0Y41_ILOGIC_X0Y41_Q2),
.I3(LIOI3_X0Y39_ILOGIC_X0Y40_Q2),
.I4(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q2),
.I5(CLBLL_L_X2Y43_SLICE_X0Y43_CO6),
.O5(CLBLL_L_X2Y43_SLICE_X0Y43_AO5),
.O6(CLBLL_L_X2Y43_SLICE_X0Y43_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X1Y43_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X1Y43_DO5),
.O6(CLBLL_L_X2Y43_SLICE_X1Y43_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X1Y43_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X1Y43_CO5),
.O6(CLBLL_L_X2Y43_SLICE_X1Y43_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X1Y43_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X1Y43_BO5),
.O6(CLBLL_L_X2Y43_SLICE_X1Y43_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y43_SLICE_X1Y43_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y43_SLICE_X1Y43_AO5),
.O6(CLBLL_L_X2Y43_SLICE_X1Y43_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(RIOB33_X43Y25_IOB_X1Y26_I),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(RIOB33_X43Y23_IOB_X1Y24_I),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y33_IOB_X0Y34_IBUF (
.I(io[11]),
.O(LIOB33_X0Y33_IOB_X0Y34_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y35_IOB_X0Y35_IBUF (
.I(io[10]),
.O(LIOB33_X0Y35_IOB_X0Y35_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y35_IOB_X0Y36_IBUF (
.I(io[9]),
.O(LIOB33_X0Y35_IOB_X0Y36_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y37_IOB_X0Y37_IBUF (
.I(io[8]),
.O(LIOB33_X0Y37_IOB_X0Y37_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y37_IOB_X0Y38_IBUF (
.I(io[7]),
.O(LIOB33_X0Y37_IOB_X0Y38_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y39_IOB_X0Y39_IBUF (
.I(io[6]),
.O(LIOB33_X0Y39_IOB_X0Y39_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y39_IOB_X0Y40_IBUF (
.I(io[5]),
.O(LIOB33_X0Y39_IOB_X0Y40_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y41_IOB_X0Y41_IBUF (
.I(io[4]),
.O(LIOB33_X0Y41_IOB_X0Y41_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y41_IOB_X0Y42_IBUF (
.I(io[3]),
.O(LIOB33_X0Y41_IOB_X0Y42_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y43_IOB_X0Y43_IBUF (
.I(io[2]),
.O(LIOB33_X0Y43_IOB_X0Y43_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y45_IOB_X0Y45_IBUF (
.I(io[1]),
.O(LIOB33_X0Y45_IOB_X0Y45_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y45_IOB_X0Y46_IBUF (
.I(io[0]),
.O(LIOB33_X0Y45_IOB_X0Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b1),
.SRTYPE("SYNC")
) LIOI3_X0Y33_ILOGIC_X0Y34_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y33_IOB_X0Y34_I),
.Q1(LIOI3_X0Y33_ILOGIC_X0Y34_Q1),
.Q2(LIOI3_X0Y33_ILOGIC_X0Y34_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b1),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y35_ILOGIC_X0Y36_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y35_IOB_X0Y36_I),
.Q1(LIOI3_X0Y35_ILOGIC_X0Y36_Q1),
.Q2(LIOI3_X0Y35_ILOGIC_X0Y36_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y35_ILOGIC_X0Y35_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y35_IOB_X0Y35_I),
.Q1(LIOI3_X0Y35_ILOGIC_X0Y35_Q1),
.Q2(LIOI3_X0Y35_ILOGIC_X0Y35_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y39_ILOGIC_X0Y40_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y39_IOB_X0Y40_I),
.Q1(LIOI3_X0Y39_ILOGIC_X0Y40_Q1),
.Q2(LIOI3_X0Y39_ILOGIC_X0Y40_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y39_ILOGIC_X0Y39_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y39_IOB_X0Y39_I),
.Q1(LIOI3_X0Y39_ILOGIC_X0Y39_Q1),
.Q2(LIOI3_X0Y39_ILOGIC_X0Y39_Q2),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y41_ILOGIC_X0Y42_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y41_IOB_X0Y42_I),
.Q1(LIOI3_X0Y41_ILOGIC_X0Y42_Q1),
.Q2(LIOI3_X0Y41_ILOGIC_X0Y42_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y41_ILOGIC_X0Y41_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y41_IOB_X0Y41_I),
.Q1(LIOI3_X0Y41_ILOGIC_X0Y41_Q1),
.Q2(LIOI3_X0Y41_ILOGIC_X0Y41_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y45_ILOGIC_X0Y46_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y45_IOB_X0Y46_I),
.Q1(LIOI3_X0Y45_ILOGIC_X0Y46_Q1),
.Q2(LIOI3_X0Y45_ILOGIC_X0Y46_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y45_ILOGIC_X0Y45_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y45_IOB_X0Y45_I),
.Q1(LIOI3_X0Y45_ILOGIC_X0Y45_Q1),
.Q2(LIOI3_X0Y45_ILOGIC_X0Y45_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y43_IOB_X0Y43_I),
.Q1(LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q1),
.Q2(LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y37_IOB_X0Y38_I),
.Q1(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q1),
.Q2(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q2),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "IFF" *)
IDDR_2CLK #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_IDDR_2CLK (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CB(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D(LIOB33_X0Y37_IOB_X0Y37_I),
.Q1(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q1),
.Q2(LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q2),
.R(1'b0),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y23_IOB_X1Y24_IBUF (
.I(i_clkb),
.O(RIOB33_X43Y23_IOB_X1Y24_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y25_IOB_X1Y26_IBUF (
.I(i_clk),
.O(RIOB33_X43Y25_IOB_X1Y26_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y43_IOB_X1Y43_OBUF (
.I(CLBLL_L_X2Y43_SLICE_X0Y43_AO6),
.O(o_q2)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) RIOB33_X43Y43_IOB_X1Y44_OBUF (
.I(CLBLL_L_X2Y42_SLICE_X1Y42_AO6),
.O(o_q1)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y45_IBUF (
.I(i_ce),
.O(RIOB33_X43Y45_IOB_X1Y45_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y46_IBUF (
.I(i_rst),
.O(RIOB33_X43Y45_IOB_X1Y46_I)
);
assign CLBLL_L_X2Y42_SLICE_X0Y42_COUT = CLBLL_L_X2Y42_SLICE_X0Y42_D_CY;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A = CLBLL_L_X2Y42_SLICE_X0Y42_AO6;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B = CLBLL_L_X2Y42_SLICE_X0Y42_BO6;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C = CLBLL_L_X2Y42_SLICE_X0Y42_CO6;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D = CLBLL_L_X2Y42_SLICE_X0Y42_DO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_COUT = CLBLL_L_X2Y42_SLICE_X1Y42_D_CY;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B = CLBLL_L_X2Y42_SLICE_X1Y42_BO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C = CLBLL_L_X2Y42_SLICE_X1Y42_CO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D = CLBLL_L_X2Y42_SLICE_X1Y42_DO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_AMUX = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_BMUX = CLBLL_L_X2Y42_SLICE_X1Y42_BO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_CMUX = CLBLL_L_X2Y42_SLICE_X1Y42_CO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_COUT = CLBLL_L_X2Y43_SLICE_X0Y43_D_CY;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B = CLBLL_L_X2Y43_SLICE_X0Y43_BO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C = CLBLL_L_X2Y43_SLICE_X0Y43_CO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D = CLBLL_L_X2Y43_SLICE_X0Y43_DO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_AMUX = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_BMUX = CLBLL_L_X2Y43_SLICE_X0Y43_BO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_CMUX = CLBLL_L_X2Y43_SLICE_X0Y43_CO6;
assign CLBLL_L_X2Y43_SLICE_X1Y43_COUT = CLBLL_L_X2Y43_SLICE_X1Y43_D_CY;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A = CLBLL_L_X2Y43_SLICE_X1Y43_AO6;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B = CLBLL_L_X2Y43_SLICE_X1Y43_BO6;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C = CLBLL_L_X2Y43_SLICE_X1Y43_CO6;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D = CLBLL_L_X2Y43_SLICE_X1Y43_DO6;
assign RIOI3_X43Y23_ILOGIC_X1Y24_O = RIOB33_X43Y23_IOB_X1Y24_I;
assign RIOI3_X43Y25_ILOGIC_X1Y26_O = RIOB33_X43Y25_IOB_X1Y26_I;
assign RIOI3_X43Y45_ILOGIC_X1Y46_O = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_O = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_OQ = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_TQ = 1'b1;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_OQ = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_TQ = 1'b1;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_D1 = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign LIOI3_X0Y39_ILOGIC_X0Y40_D = LIOB33_X0Y39_IOB_X0Y40_I;
assign LIOI3_X0Y39_ILOGIC_X0Y39_D = LIOB33_X0Y39_IOB_X0Y39_I;
assign LIOI3_X0Y39_ILOGIC_X0Y40_SR = 1'b0;
assign LIOI3_X0Y39_ILOGIC_X0Y39_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y44_T1 = 1'b1;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_D1 = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign LIOI3_X0Y39_ILOGIC_X0Y39_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y33_ILOGIC_X0Y34_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_OLOGIC_X1Y43_T1 = 1'b1;
assign LIOI3_X0Y33_ILOGIC_X0Y34_D = LIOB33_X0Y33_IOB_X0Y34_I;
assign RIOI3_X43Y23_ILOGIC_X1Y24_D = RIOB33_X43Y23_IOB_X1Y24_I;
assign LIOI3_X0Y33_ILOGIC_X0Y34_SR = 1'b0;
assign LIOI3_X0Y41_ILOGIC_X0Y41_SR = 1'b0;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A1 = CLBLL_L_X2Y43_SLICE_X0Y43_BO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A2 = LIOI3_X0Y39_ILOGIC_X0Y39_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A3 = LIOI3_X0Y41_ILOGIC_X0Y41_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A4 = LIOI3_X0Y39_ILOGIC_X0Y40_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A5 = LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_A6 = CLBLL_L_X2Y43_SLICE_X0Y43_CO6;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B1 = LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B3 = LIOI3_X0Y45_ILOGIC_X0Y45_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B4 = LIOI3_X0Y41_ILOGIC_X0Y42_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B5 = LIOI3_X0Y45_ILOGIC_X0Y46_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_B6 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C1 = LIOI3_X0Y35_ILOGIC_X0Y36_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C2 = LIOI3_X0Y33_ILOGIC_X0Y34_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C3 = LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C5 = LIOI3_X0Y35_ILOGIC_X0Y35_Q2;
assign CLBLL_L_X2Y43_SLICE_X0Y43_C6 = 1'b1;
assign LIOI3_X0Y35_ILOGIC_X0Y36_SR = 1'b0;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X0Y43_D6 = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_D = LIOB33_X0Y37_IOB_X0Y38_I;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_D = LIOB33_X0Y37_IOB_X0Y37_I;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y41_ILOGIC_X0Y42_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_A6 = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_SR = 1'b0;
assign LIOI3_X0Y41_ILOGIC_X0Y42_D = LIOB33_X0Y41_IOB_X0Y42_I;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_B6 = 1'b1;
assign LIOI3_X0Y41_ILOGIC_X0Y42_SR = 1'b0;
assign LIOI3_X0Y41_ILOGIC_X0Y41_D = LIOB33_X0Y41_IOB_X0Y41_I;
assign LIOI3_X0Y41_ILOGIC_X0Y41_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_C6 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D1 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D2 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D3 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D4 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D5 = 1'b1;
assign CLBLL_L_X2Y43_SLICE_X1Y43_D6 = 1'b1;
assign LIOI3_X0Y35_ILOGIC_X0Y36_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y35_ILOGIC_X0Y36_D = LIOB33_X0Y35_IOB_X0Y36_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1 = 1'b1;
assign LIOI3_X0Y35_ILOGIC_X0Y35_D = LIOB33_X0Y35_IOB_X0Y35_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S1 = 1'b1;
assign LIOI3_X0Y35_ILOGIC_X0Y35_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y35_ILOGIC_X0Y35_SR = 1'b0;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_A6 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_B6 = 1'b1;
assign RIOI3_X43Y45_ILOGIC_X1Y46_D = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_D = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_C6 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X0Y42_D6 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0 = RIOB33_X43Y25_IOB_X1Y26_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A1 = CLBLL_L_X2Y42_SLICE_X1Y42_BO6;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I0 = RIOB33_X43Y23_IOB_X1Y24_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A2 = LIOI3_X0Y39_ILOGIC_X0Y39_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A3 = LIOI3_X0Y41_ILOGIC_X0Y41_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A4 = LIOI3_X0Y39_ILOGIC_X0Y40_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A5 = LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_A6 = CLBLL_L_X2Y42_SLICE_X1Y42_CO6;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B1 = LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B3 = LIOI3_X0Y45_ILOGIC_X0Y45_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B4 = LIOI3_X0Y41_ILOGIC_X0Y42_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B5 = LIOI3_X0Y45_ILOGIC_X0Y46_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_B6 = 1'b1;
assign RIOI3_X43Y25_ILOGIC_X1Y26_D = RIOB33_X43Y25_IOB_X1Y26_I;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_D = LIOB33_X0Y43_IOB_X0Y43_I;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C1 = LIOI3_X0Y35_ILOGIC_X0Y36_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C2 = LIOI3_X0Y33_ILOGIC_X0Y34_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C3 = LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C5 = LIOI3_X0Y35_ILOGIC_X0Y35_Q1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_C6 = 1'b1;
assign LIOI3_X0Y45_ILOGIC_X0Y46_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D1 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D2 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D3 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D4 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D5 = 1'b1;
assign CLBLL_L_X2Y42_SLICE_X1Y42_D6 = 1'b1;
assign LIOI3_X0Y45_ILOGIC_X0Y46_D = LIOB33_X0Y45_IOB_X0Y46_I;
assign LIOI3_X0Y45_ILOGIC_X0Y45_D = LIOB33_X0Y45_IOB_X0Y45_I;
assign LIOI3_X0Y45_ILOGIC_X0Y46_SR = 1'b0;
assign LIOI3_X0Y45_ILOGIC_X0Y45_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_SR = 1'b0;
assign RIOB33_X43Y43_IOB_X1Y43_O = CLBLL_L_X2Y43_SLICE_X0Y43_AO6;
assign RIOB33_X43Y43_IOB_X1Y44_O = CLBLL_L_X2Y42_SLICE_X1Y42_AO6;
assign LIOI3_X0Y45_ILOGIC_X0Y45_SR = 1'b0;
assign LIOI3_X0Y39_ILOGIC_X0Y40_CE1 = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y39_ILOGIC_X0Y39_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y33_ILOGIC_X0Y34_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y41_ILOGIC_X0Y42_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y41_ILOGIC_X0Y41_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y35_ILOGIC_X0Y36_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y35_ILOGIC_X0Y35_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y45_ILOGIC_X0Y46_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y45_ILOGIC_X0Y45_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y39_ILOGIC_X0Y40_CLKB = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign LIOI3_X0Y39_ILOGIC_X0Y39_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y33_ILOGIC_X0Y34_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y38_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTETERM_X0Y37_ILOGIC_X0Y37_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y41_ILOGIC_X0Y42_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y41_ILOGIC_X0Y41_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y35_ILOGIC_X0Y36_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y35_ILOGIC_X0Y35_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTESRC_X0Y43_ILOGIC_X0Y43_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y45_ILOGIC_X0Y46_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y45_ILOGIC_X0Y45_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y39_ILOGIC_X0Y40_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
endmodule |
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module axis_srl_register_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_reg[1:0];
reg valid_reg[1:0];
reg ptr_reg = 0;
reg full_reg = 0;
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_reg[ptr_reg];
assign input_axis_tready = ~full_reg;
assign output_axis_tvalid = valid_reg[ptr_reg];
integer i;
initial begin
for (i = 0; i < 2; i = i + 1) begin
data_reg[i] <= 0;
valid_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
end else begin
// transfer empty to full
full_reg <= ~output_axis_tready & output_axis_tvalid;
// transfer in if not full
if (input_axis_tready) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
valid_reg[0] <= input_axis_tvalid;
for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
valid_reg[i+1] <= valid_reg[i];
end
ptr_reg <= valid_reg[0];
end
if (output_axis_tready) begin
ptr_reg <= 0;
end
end
end
endmodule |
module inicial ( botao, aberto, fechado, motor, sentido, ledVerde, ledVermelho, display, clock );
input botao, aberto, fechado, motor, sentido, clock;
output ledVerde, ledVermelho;
output [6:0] display;
reg [1:0] estado;
reg [4:0] entrada;
reg [6:0] tmpDisplay;
reg tmpLedVerde, tmpLedVermelho;
parameter Fechado = 2'b00, Abrindo = 2'b01, Aberto = 2'b10, Fechando = 2'b11;
initial estado = Fechado;
always @(posedge clock)begin
entrada[4] = botao;
entrada[3] = aberto;
entrada[2] = fechado;
entrada[1] = motor;
entrada[0] = sentido;
case( estado )
Fechado: begin
tmpDisplay = 7'b0001110;
tmpLedVerde = 0;
tmpLedVermelho = 0;
if( entrada == 5'b10110 ) // botao == 1 && aberto == 0 && fechado == 1 && motor == 1 && sentido == 0
estado = Abrindo;
end
Abrindo: begin
tmpDisplay = 7'b1000000;
tmpLedVerde = 1;
tmpLedVermelho = 0;
if( entrada == 5'b10010 ) // botao == 1 && aberto == 0 && fechado == 0 && motor == 1 && sentido == 0
estado = Aberto;
if( entrada == 5'b00010 ) // botao == 0 && aberto == 0 && fechado == 0 && motor == 1 && sentido == 0
estado = Fechando;
end
Aberto: begin
tmpDisplay = 7'b0001000;
tmpLedVerde = 0;
tmpLedVermelho = 0;
if( entrada == 5'b01011 ) // botao == 0 && aberto == 1 && fechado == 0 && motor == 1 && sentido == 1
estado = Fechando;
end
Fechando: begin
tmpDisplay = 7'b1000000;
tmpLedVerde = 0;
tmpLedVermelho = 1;
if( entrada == 5'b10011 ) // botao == 1 && aberto == 0 && fechado == 0 && motor == 1 && sentido == 1
estado = Abrindo;
if( entrada == 5'b00011 ) // botao == 0 && aberto == 0 && fechado == 0 && motor == 1 && sentido == 1
estado = Fechado;
end
default: estado = Fechado;
endcase
end
assign display= tmpDisplay;
assign ledVerde = tmpLedVerde;
assign ledVermelho = tmpLedVermelho;
endmodule |
module maquina(SW,LEDG,LEDR,HEX0, CLK);
input [4:0] SW;
input CLK;
output [0:0] LEDG, LEDR;
output [6:0] HEX0;
inicial a( SW[4], SW[3], SW[2], SW[1], SW[0], LEDG[0], LEDR[0], HEX0, CLK);
endmodule |
module sky130_fd_sc_ms__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module regaccess(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output [6:0] regnum,
input [7:0] regdata_read,
output [7:0] regdata_write,
output read,
output write
);
wire done;
wire [7:0] din;
wire [7:0] dout;
reg [6:0] regnum_d, regnum_q;
reg we_d, we_q;
reg ss_d, ss_q;
reg first_d, first_q;
reg read_d, read_q;
reg write_d, write_q;
assign regnum = regnum_q;
assign read = read_q;
assign write = write_q;
assign regdata_write = dout;
assign din = (read_q? regdata_read : 8'b0);
spi_slave reg_spi
(
.clk(clk), .rst(rst),
.ss(ss), .mosi(mosi), .miso(miso), .sck(sck),
.done(done), .din(din), .din_update(read_q), .dout(dout)
);
always @(*) begin
ss_d = ss;
we_d = we_q;
first_d = first_q;
regnum_d = regnum_q;
read_d = 1'b0;
write_d = 1'b0;
if (ss_q) begin
we_d = 1'b0;
first_d = 1'b1;
end else if (done) begin
if (first_q) begin
regnum_d = dout[6:0];
we_d = !dout[7];
read_d = dout[7];
end else if (we_q) begin
write_d = 1'b1;
end else begin
regnum_d = dout[6:0];
read_d = 1'b1;
end
first_d = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
we_q <= 1'b0;
first_q <= 1'b1;
regnum_q <= 6'b0;
read_q <= 1'b0;
write_q <= 1'b0;
end else begin
we_q <= we_d;
first_q <= first_d;
regnum_q <= regnum_d;
read_q <= read_d;
write_q <= write_d;
end
ss_q <= ss_d;
end
endmodule |
module sky130_fd_sc_ls__o2111a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
reg [15:0] v1;
reg [15:0] v2;
reg [15:0] v3;
integer nosplit;
always @ (posedge clk) begin
// write needed so that V3Dead doesn't kill v0..v3
$write(" values %x %x %x\n", v1, v2, v3);
// Locally-set 'nosplit' will prevent the if from splitting
// in splitAlwaysAll(). This whole always block should still be
// intact when we call splitReorderAll() which is the subject
// of this test.
nosplit = cyc;
if (nosplit > 2) begin
/* S1 */ v1 <= 16'h0;
/* S2 */ v1 <= m_din;
/* S3 */ if (m_din == 16'h0) begin
/* X1 */ v2 <= v1;
/* X2 */ v3 <= v2;
end
end
// We expect to swap S2 and S3, and to swap X1 and X2.
// We can check that this worked by the absense of dly vars
// in the generated output; if the reorder fails (or is disabled)
// we should see dly vars for v1 and v2.
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule |
module Divide(
input clock,
input reset,
input OP_div, // True to initiate a signed divide
input OP_divu, // True to initiate an unsigned divide
input [31:0] Dividend,
input [31:0] Divisor,
output [31:0] Quotient,
output [31:0] Remainder,
output Stall, // True while calculating
//Voter Signals for Registers
input active, // True if the divider is running
input neg, // True if the result will be negative
input [31:0] result, // Begin with dividend, end with quotient
input [31:0] denom, // Divisor
input [31:0] work,
output reg vote_active, // True if the divider is running
output reg vote_neg, // True if the result will be negative
output reg [31:0] vote_result, // Begin with dividend, end with quotient
output reg [31:0] vote_denom, // Divisor
output reg [31:0] vote_work
);
reg [4:0] cycle; // Number of cycles to go
// Calculate the current digit
wire [32:0] sub = { work[30:0], result[31] } - denom;
// Send the results to our master
assign Quotient = !neg ? result : -result;
assign Remainder = work;
assign Stall = active;
// The state machine
always @(posedge clock) begin
if (reset) begin
vote_active <= 0;
vote_neg <= 0;
cycle <= 0;
vote_result <= 0;
vote_denom <= 0;
vote_work <= 0;
end
else begin
if (OP_div) begin
// Set up for a signed divide. Remember the resulting sign,
// and make the operands positive.
cycle <= 5'd31;
vote_result <= (Dividend[31] == 0) ? Dividend : -Dividend;
vote_denom <= (Divisor[31] == 0) ? Divisor : -Divisor;
vote_work <= 32'b0;
vote_neg <= Dividend[31] ^ Divisor[31];
vote_active <= 1;
end
else if (OP_divu) begin
// Set up for an unsigned divide.
cycle <= 5'd31;
vote_result <= Dividend;
vote_denom <= Divisor;
vote_work <= 32'b0;
vote_neg <= 0;
vote_active <= 1;
end
else if (active) begin
// Run an iteration of the divide.
if (sub[32] == 0) begin
vote_work <= sub[31:0];
vote_result <= {result[30:0], 1'b1};
end
else begin
vote_work <= {work[30:0], result[31]};
vote_result <= {result[30:0], 1'b0};
end
if (cycle == 0) begin
vote_active <= 0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule |
module pass_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/pass_new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule |
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire clkn;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , GATE, clkn );
and and0 (GCLK , m0, CLK );
endmodule |
module UpCounter(clock,reset,count,data_o);
parameter Size = 8;
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
input wire [('b1) - ('b1):0] count;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (count) begin
data_o <= data_o + 1;
end
end
end
endmodule |
module UDCounter(clock,reset,count,direction,data_o);
parameter Size = 8;
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
input wire [('b1) - ('b1):0] count;
input wire [('b1) - ('b1):0] direction;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (count) begin
case (direction)
'b0: data_o <= data_o + 1;
'b1: data_o <= data_o - 1;
endcase
end
end
end
endmodule |
module Mux2(select,data_i00,data_i01,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
output reg [(Size) - ('b1):0] data_o;
always @ (select or data_i00 or data_i01) begin
case (select)
'b0:data_o = data_i00;
'b1:data_o = data_i01;
endcase // case (select)
end
endmodule |
module Mux4(select,data_i00,data_i01,data_i02,data_i03,data_o);
parameter Size = 8;
input wire [('d2) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03) begin
case (select)
'b00: data_o = data_i00;
'b01: data_o = data_i01;
'b10: data_o = data_i02;
'b11: data_o = data_i03;
endcase
end
endmodule |
module Mux8(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_o);
parameter Size = 8;
input wire [('d3) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07) begin
case (select)
'b000: data_o = data_i00;
'b001: data_o = data_i01;
'b010: data_o = data_i02;
'b011: data_o = data_i03;
'b100: data_o = data_i04;
'b101: data_o = data_i05;
'b110: data_o = data_i06;
'b111: data_o = data_i07;
endcase
end
endmodule |
module Mux16(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_o);
parameter Size = 8;
input wire [('d4) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15) begin
case (select)
'b0000: data_o = data_i00;
'b0001: data_o = data_i01;
'b0010: data_o = data_i02;
'b0011: data_o = data_i03;
'b0100: data_o = data_i04;
'b0101: data_o = data_i05;
'b0110: data_o = data_i06;
'b0111: data_o = data_i07;
'b1000: data_o = data_i08;
'b1001: data_o = data_i09;
'b1010: data_o = data_i10;
'b1011: data_o = data_i11;
'b1100: data_o = data_i12;
'b1101: data_o = data_i13;
'b1110: data_o = data_i14;
'b1111: data_o = data_i15;
endcase
end
endmodule |
module Mux32(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_i16,data_i17,data_i18,data_i19,data_i20,data_i21,data_i22,data_i23,data_i24,data_i25,data_i26,data_i27,data_i28,data_i29,data_i30,data_i31,data_o);
parameter Size = 8;
input wire [('d5) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
input wire [(Size) - ('b1):0] data_i16;
input wire [(Size) - ('b1):0] data_i17;
input wire [(Size) - ('b1):0] data_i18;
input wire [(Size) - ('b1):0] data_i19;
input wire [(Size) - ('b1):0] data_i20;
input wire [(Size) - ('b1):0] data_i21;
input wire [(Size) - ('b1):0] data_i22;
input wire [(Size) - ('b1):0] data_i23;
input wire [(Size) - ('b1):0] data_i24;
input wire [(Size) - ('b1):0] data_i25;
input wire [(Size) - ('b1):0] data_i26;
input wire [(Size) - ('b1):0] data_i27;
input wire [(Size) - ('b1):0] data_i28;
input wire [(Size) - ('b1):0] data_i29;
input wire [(Size) - ('b1):0] data_i30;
input wire [(Size) - ('b1):0] data_i31;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15 or
data_i16 or data_i17 or data_i18 or data_i19 or data_i20 or data_i21 or data_i22 or data_i23 or
data_i24 or data_i25 or data_i26 or data_i27 or data_i28 or data_i29 or data_i30 or data_i31) begin
case (select)
'b00000: data_o = data_i00;
'b00001: data_o = data_i01;
'b00010: data_o = data_i02;
'b00011: data_o = data_i03;
'b00100: data_o = data_i04;
'b00101: data_o = data_i05;
'b00110: data_o = data_i06;
'b00111: data_o = data_i07;
'b01000: data_o = data_i08;
'b01001: data_o = data_i09;
'b01010: data_o = data_i10;
'b01011: data_o = data_i11;
'b01100: data_o = data_i12;
'b01101: data_o = data_i13;
'b01110: data_o = data_i14;
'b01111: data_o = data_i15;
'b10000: data_o = data_i16;
'b10001: data_o = data_i17;
'b10010: data_o = data_i18;
'b10011: data_o = data_i19;
'b10100: data_o = data_i20;
'b10101: data_o = data_i21;
'b10110: data_o = data_i22;
'b10111: data_o = data_i23;
'b11000: data_o = data_i24;
'b11001: data_o = data_i25;
'b11010: data_o = data_i26;
'b11011: data_o = data_i27;
'b11100: data_o = data_i28;
'b11101: data_o = data_i29;
'b11110: data_o = data_i30;
'b11111: data_o = data_i31;
endcase
end
endmodule |
module Reg(clock,reset,data_i,writeEn,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] clock;
input wire [('d1) - ('b1):0] reset;
input wire [(Size) - ('b1):0] data_i;
input wire [('d1) - ('b1):0] writeEn;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (writeEn) begin
data_o <= data_i;
end
end
end
endmodule |
module FPGADCM(clock,reset,locked,clock_o0,clock_o90,clock_o180,clock_o270,clock_o2x,clock_o2x180);
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
output wire [('b1) - ('b1):0] locked;
output wire [('b1) - ('b1):0] clock_o0;
output wire [('b1) - ('b1):0] clock_o90;
output wire [('b1) - ('b1):0] clock_o180;
output wire [('b1) - ('b1):0] clock_o270;
output wire [('b1) - ('b1):0] clock_o2x;
output wire [('b1) - ('b1):0] clock_o2x180;
wire FPGABUFG_o;
wire FPGASPDCM_CLK0;
assign clock_o0 = FPGASPDCM_CLK0;
DCM_SP #(.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(0.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE"))
FPGASPDCM (.CLKIN(clock),
.CLKFB(FPGABUFG_o),
.RST(reset),
.DSSEN(0),
.PSINCDEC(0),
.PSEN(0),
.PSCLK(0),
.LOCKED(locked),
.CLK0(FPGASPDCM_CLK0),
.CLK90(clock_o90),
.CLK180(clock_o180),
.CLK270(clock_o270),
.CLK2X(clock_o2x),
.CLK2X180(clock_o2x180));
BUFG
FPGABUFG (.I(FPGASPDCM_CLK0),
.O(FPGABUFG_o));
endmodule |
module VGAVideo(
input wire [('b1) - ('b1):0] clock,
input wire [('b1) - ('b1):0] reset,
output wire [('b1) - ('b1):0] vga_r,
output wire [('b1) - ('b1):0] vga_g,
output wire [('b1) - ('b1):0] vga_b,
output wire [('b1) - ('b1):0] vga_hsync,
output wire [('b1) - ('b1):0] vga_vsync);
parameter hack_hcounter_Size = 'b1011;
parameter hack_vcounter_Size = 'b1010;
wire [(hack_hcounter_Size) - ('b1):0] hcounter_data_o;
wire [(hack_vcounter_Size) - ('b1):0] vcounter_data_o;
assign vga_r = 'b1;
assign vga_g = 'b0;
assign vga_b = 'b0;
assign vga_hsync = (hcounter_data_o['b1010:'b101] == 'b0);
assign vga_vsync = (vcounter_data_o == 'b0);
UpCounter #(
.Size('b1011))
hcounter(
.clock(clock),
.reset((hcounter_data_o == 'b1011111111)),
.count('b1),
.data_o(hcounter_data_o));
UpCounter #(
.Size('b1010))
vcounter(
.clock(clock),
.reset('b0),
.count('b1),
.data_o(vcounter_data_o));
endmodule |
module flag_domain_crossing_ce(
input wire CLK_A,
input wire CLK_A_CE,
input wire CLK_B,
input wire CLK_B_CE,
input wire FLAG_IN_CLK_A,
output wire FLAG_OUT_CLK_B
);
reg FLAG_TOGGLE_CLK_A;
initial FLAG_TOGGLE_CLK_A = 0;
reg [2:0] SYNC_CLK_B;
always @ (posedge CLK_A)
begin
if (CLK_A_CE)
begin
if (FLAG_IN_CLK_A)
begin
FLAG_TOGGLE_CLK_A <= ~FLAG_TOGGLE_CLK_A;
end
end
end
always @ (posedge CLK_B)
begin
if (CLK_B_CE)
begin
SYNC_CLK_B <= {SYNC_CLK_B[1:0], FLAG_TOGGLE_CLK_A};
end
end
assign FLAG_OUT_CLK_B = (SYNC_CLK_B[2] ^ SYNC_CLK_B[1]); // XOR
endmodule |
module sky130_fd_sc_hd__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module ABRO_blif(clk, rst, O, A, B, R);
input clk, rst;
output O;
input A;
input B;
input R;
wire A;
wire B;
wire R;
wire O;
wire w_0;
wire w_1;
wire R_O;
wire SM1_chk_0;
wire w_7;
wire w_8;
wire w_9;
wire SM3_chk_0;
wire w_10;
wire SM3_chk_1;
wire w_11;
wire SM10_chk_0;
wire w_12;
wire SM10_chk_1;
wire w_13;
wire B_O;
wire w_14;
wire w_15;
wire w_16;
wire w_17;
wire SM6_chk_0;
wire w_18;
wire SM6_chk_1;
wire w_19;
wire A_O;
wire w_20;
wire w_21;
wire w_22;
wire w_23;
wire w_24;
wire tick_O;
wire w_30;
wire w_31;
wire SM1_chk_1;
wire w_32;
wire SM1_goto_0;
wire SM1_goto_1;
wire SM1_hold;
wire w_36;
wire SM3_goto_0;
wire w_38;
wire SM3_goto_1;
wire SM3_hold;
wire SM6_goto_0;
wire w_42;
wire SM6_goto_1;
wire SM6_hold;
wire SM10_goto_0;
wire w_46;
wire SM10_goto_1;
wire SM10_hold;
wire ff_1_0_q;
wire ff_1_0_d;
wire g57;
wire ff_3_0_q;
wire ff_3_0_d;
wire g60;
wire ff_6_0_q;
wire ff_6_0_d;
wire g63;
wire ff_10_0_q;
wire ff_10_0_d;
wire g66;
assign O = w_24;
assign w_0 = 0;
assign w_1 = 1;
assign R_O = R;
assign SM1_chk_0 = !ff_1_0_q;
assign w_7 = R_O & SM1_chk_0;
assign w_8 = !R_O;
assign w_9 = w_8 & SM1_chk_0;
assign SM3_chk_0 = !ff_3_0_q;
assign w_10 = w_9 & SM3_chk_0;
assign SM3_chk_1 = ff_3_0_q;
assign w_11 = w_9 & SM3_chk_1;
assign SM10_chk_0 = !ff_10_0_q;
assign w_12 = w_11 & SM10_chk_0;
assign SM10_chk_1 = ff_10_0_q;
assign w_13 = w_11 & SM10_chk_1;
assign B_O = B;
assign w_14 = w_13 & B_O;
assign w_15 = !B_O;
assign w_16 = w_13 & w_15;
assign w_17 = w_14 | w_12;
assign SM6_chk_0 = !ff_6_0_q;
assign w_18 = w_11 & SM6_chk_0;
assign SM6_chk_1 = ff_6_0_q;
assign w_19 = w_11 & SM6_chk_1;
assign A_O = A;
assign w_20 = w_19 & A_O;
assign w_21 = !A_O;
assign w_22 = w_21 & w_19;
assign w_23 = w_20 | w_18;
assign w_24 = w_17 & w_23;
assign tick_O = w_1;
assign w_30 = !w_24;
assign w_31 = w_11 & w_30;
assign SM1_chk_1 = ff_1_0_q;
assign w_32 = w_9 | w_7 | SM1_chk_1;
assign SM1_goto_0 = w_32;
assign SM1_goto_1 = w_0;
assign SM1_hold = w_0;
assign w_36 = w_10 | w_24;
assign SM3_goto_0 = w_36;
assign w_38 = w_7 | w_31 | SM1_chk_1;
assign SM3_goto_1 = w_38;
assign SM3_hold = w_0;
assign SM6_goto_0 = w_23;
assign w_42 = w_7 | w_22 | SM1_chk_1;
assign SM6_goto_1 = w_42;
assign SM6_hold = w_0;
assign SM10_goto_0 = w_17;
assign w_46 = w_7 | w_16 | SM1_chk_1;
assign SM10_goto_1 = w_46;
assign SM10_hold = w_0;
d_ff1 u0(rst, clk, ff_1_0_q, ff_1_0_d);
assign ff_1_0_d = g57 | SM1_goto_1;
assign g57 = SM1_hold & ff_1_0_q;
d_ff0 u1(rst, clk, ff_3_0_q, ff_3_0_d);
assign ff_3_0_d = g60 | SM3_goto_1;
assign g60 = SM3_hold & ff_3_0_q;
d_ff0 u2(rst, clk, ff_6_0_q, ff_6_0_d);
assign ff_6_0_d = g63 | SM6_goto_1;
assign g63 = SM6_hold & ff_6_0_q;
d_ff0 u3(rst, clk, ff_10_0_q, ff_10_0_d);
assign ff_10_0_d = g66 | SM10_goto_1;
assign g66 = SM10_hold & ff_10_0_q;
endmodule |
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_tx1_pcie s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule |
module sky130_fd_sc_hd__a21oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module sky130_fd_sc_ls__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module top (
input clk,
input [15:0] sw,
output [15:0] led,
// not used
input rx,
output tx
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [4:0] addr;
wire ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(5)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(ram_out),
.ram_in(ram_in)
);
RAM64X1D #(
.INIT(64'h96A5_96A5_96A5_96A5)
) ram0 (
.WCLK(clk),
.A5(sw[0]),
.A4(addr[4]),
.A3(addr[3]),
.A2(addr[2]),
.A1(addr[1]),
.A0(addr[0]),
.DPRA5(~sw[0]),
.DPRA4(addr[4]),
.DPRA3(addr[3]),
.DPRA2(addr[2]),
.DPRA1(addr[1]),
.DPRA0(addr[0]),
.DPO(ram_out),
.D(ram_in),
.WE(1'b1)
);
endmodule |
module entropy(input wire clk,
input wire nreset,
input wire cs,
input wire we,
input wire [7:0] addr,
input wire [15:0] dwrite,
output wire [31:0] dread,
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Symbolic names.
//----------------------------------------------------------------
// Delay in cycles between sampling random values
// and updating the debug port.
// Corresponds to about 1/10s with clock @ 50 MHz.
parameter DELAY_MAX = 32'h004c4b40;
parameter ADDR_ENT_WR_RNG1 = 8'h00;
parameter ADDR_ENT_WR_RNG2 = 8'h01;
parameter ADDR_ENT_RD_RNG1_RNG2 = 8'h10;
parameter ADDR_ENT_RD_P = 8'h11;
parameter ADDR_ENT_RD_N = 8'h12;
parameter ADDR_ENT_MIX = 8'h20;
parameter ADDR_ENT_CONCAT = 8'h21;
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg [7:0] rng1, rng2; // must be inverse to each other
reg [31 : 0] delay_ctr_reg;
reg [31 : 0] delay_ctr_new;
reg [7 : 0] debug_reg;
reg [31 : 0] mix_reg;
reg [31 : 0] concat_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [31 : 0] p, n;
reg [31 : 0] tmp_dread;
//----------------------------------------------------------------
// Module instantiations.
//----------------------------------------------------------------
genvar i;
generate
for(i=0; i<32; i=i+1) begin: tworoscs
rosc px(clk, nreset, rng1, rng2, p[i]);
rosc nx(clk, nreset, rng1, rng2, n[i]);
end
endgenerate
//----------------------------------------------------------------
// Concurrent assignments to connect output ports.
//----------------------------------------------------------------
assign dread = tmp_dread;
assign debug = debug_reg;
//----------------------------------------------------------------
// reg updates
//----------------------------------------------------------------
always @(posedge clk or negedge nreset)
begin
if(!nreset)
begin
rng1 <= 8'h55;
rng2 <= 8'haa;
delay_ctr_reg <= 32'h00000000;
mix_reg <= 32'h00000000;
concat_reg <= 32'h00000000;
debug_reg <= 8'h00;
end
else
begin
delay_ctr_reg <= delay_ctr_new;
mix_reg <= n ^ p;
concat_reg <= {n[31 : 16] ^ n[15 : 0], p[31 : 16] ^ p[15 : 0]};
if (delay_ctr_reg == 32'h00000000)
begin
debug_reg <= n[7 : 0];
end
if(cs & we)
begin
case(addr)
ADDR_ENT_WR_RNG1: rng1 <= dwrite[15:8];
ADDR_ENT_WR_RNG2: rng2 <= dwrite[7:0];
default:;
endcase
end
end
end
//----------------------------------------------------------------
// read_data
//----------------------------------------------------------------
always @*
begin : read_data
tmp_dread = 16'h0000;
if(cs & ~we)
case(addr)
ADDR_ENT_RD_RNG1_RNG2: tmp_dread = {16'h0000, rng1, rng2};
ADDR_ENT_RD_P: tmp_dread = p;
ADDR_ENT_RD_N: tmp_dread = n;
ADDR_ENT_MIX: tmp_dread = mix_reg;
ADDR_ENT_CONCAT: tmp_dread = concat_reg;
default:;
endcase
end
//----------------------------------------------------------------
// delay_ctr
//
// Simple counter that counts to DELAY_MAC. Used to slow down
// the debug port updates to human speeds.
//----------------------------------------------------------------
always @*
begin : delay_ctr
if (delay_ctr_reg == DELAY_MAX)
begin
delay_ctr_new = 32'h00000000;
end
else
begin
delay_ctr_new = delay_ctr_reg + 1'b1;
end
end // delay_ctr
endmodule |
module REG_OUT_INTERFACE(ow_od, r_address, iw_od_0x00, iw_od_0x01, iw_od_0x02, iw_od_0x03, iw_od_0x04, iw_od_0x05, iw_od_0x06, iw_od_0x07, iw_od_0x08, iw_od_0x09, iw_od_0x0A, iw_od_0x0B, iw_od_0x10, iw_od_0x11, iw_od_0x12, iw_od_0x13, iw_od_0x14, iw_od_0x15, iw_od_0x18, iw_od_0x19, iw_od_0x1A, iw_od_0x1B, iw_od_0x1C, iw_od_0x1D, iw_od_0x1E, iw_od_0x1F, iw_od_0x23, iw_od_0x24, iw_od_0x25, iw_od_0x26, iw_od_0x27, iw_od_0x28, iw_od_0x29, iw_od_0x2E, iw_od_0x2F, iw_od_0x30, iw_od_0x31, iw_od_0x32, iw_od_0x33, iw_od_0x34, iw_od_0x35, iw_od_0x36, iw_od_0x37, iw_od_0x38, iw_od_0x39, iw_od_0x3A, iw_od_0x3B, iw_od_0x3C, iw_od_0x3D, iw_od_0x3E, iw_od_0x3F, iw_od_0x40, iw_od_0x41, iw_od_0x42, iw_od_0x43, iw_od_0x44, iw_od_0x45, iw_od_0x46, iw_od_0x47, iw_od_0x48, iw_od_0x49, iw_od_0x4A, iw_od_0x4B, iw_od_0x4C, iw_od_0x4D, iw_od_0x4E, iw_od_0x4F, iw_od_0x50, iw_od_0x51, iw_od_0x52, iw_od_0x53, iw_od_0x54, iw_od_0x55, iw_od_0x56, iw_od_0x57, iw_od_0x58, iw_od_0x59, iw_od_0x5A, iw_od_0x5B, iw_od_0x5C, iw_od_0x5D, iw_od_0x5E, iw_od_0x5F, iw_od_0x60, iw_od_0x61, iw_od_0x62, iw_od_0x63, iw_od_0x64, iw_od_0x65, iw_od_0x66, iw_od_0x67, iw_od_0x68, iw_od_0x69, iw_od_0x6A, iw_od_0x6B, iw_od_0x6C, iw_od_0x6D, iw_od_0x6E, iw_od_0x6F);
output wire[7:0] ow_od;
input wire [7:0] r_address;
input wire [7:0] iw_od_0x00, iw_od_0x01, iw_od_0x02, iw_od_0x03, iw_od_0x04, iw_od_0x05, iw_od_0x06, iw_od_0x07, iw_od_0x08, iw_od_0x09, iw_od_0x0A, iw_od_0x0B, iw_od_0x10, iw_od_0x11, iw_od_0x12, iw_od_0x13, iw_od_0x14, iw_od_0x15, iw_od_0x18, iw_od_0x19, iw_od_0x1A, iw_od_0x1B, iw_od_0x1C, iw_od_0x1D, iw_od_0x1E, iw_od_0x1F, iw_od_0x23, iw_od_0x24, iw_od_0x25, iw_od_0x26, iw_od_0x27, iw_od_0x28, iw_od_0x29, iw_od_0x2E, iw_od_0x2F, iw_od_0x30, iw_od_0x31, iw_od_0x32, iw_od_0x33, iw_od_0x34, iw_od_0x35, iw_od_0x36, iw_od_0x37, iw_od_0x38, iw_od_0x39, iw_od_0x3A, iw_od_0x3B, iw_od_0x3C, iw_od_0x3D, iw_od_0x3E, iw_od_0x3F, iw_od_0x40, iw_od_0x41, iw_od_0x42, iw_od_0x43, iw_od_0x44, iw_od_0x45, iw_od_0x46, iw_od_0x47, iw_od_0x48, iw_od_0x49, iw_od_0x4A, iw_od_0x4B, iw_od_0x4C, iw_od_0x4D, iw_od_0x4E, iw_od_0x4F, iw_od_0x50, iw_od_0x51, iw_od_0x52, iw_od_0x53, iw_od_0x54, iw_od_0x55, iw_od_0x56, iw_od_0x57, iw_od_0x58, iw_od_0x59, iw_od_0x5A, iw_od_0x5B, iw_od_0x5C, iw_od_0x5D, iw_od_0x5E, iw_od_0x5F, iw_od_0x60, iw_od_0x61, iw_od_0x62, iw_od_0x63, iw_od_0x64, iw_od_0x65, iw_od_0x66, iw_od_0x67, iw_od_0x68, iw_od_0x69, iw_od_0x6A, iw_od_0x6B, iw_od_0x6C, iw_od_0x6D, iw_od_0x6E, iw_od_0x6F;
assign ow_od=(r_address==8'h00)? iw_od_0x00 : (r_address==8'h01)? iw_od_0x01 : (r_address==8'h02)? iw_od_0x02 : (r_address==8'h03)? iw_od_0x03 : (r_address==8'h04)? iw_od_0x04 : (r_address==8'h05)? iw_od_0x05 : (r_address==8'h06)? iw_od_0x06 : (r_address==8'h07)? iw_od_0x07 : (r_address==8'h08)? iw_od_0x08 : (r_address==8'h09)? iw_od_0x09 : (r_address==8'h0A)? iw_od_0x0A : (r_address==8'h0B)? iw_od_0x0B : (r_address==8'h10)? iw_od_0x10 : (r_address==8'h11)? iw_od_0x11 : (r_address==8'h12)? iw_od_0x12 : (r_address==8'h13)? iw_od_0x13 : (r_address==8'h14)? iw_od_0x14 : (r_address==8'h15)? iw_od_0x15 : (r_address==8'h18)? iw_od_0x18 : (r_address==8'h19)? iw_od_0x19 : (r_address==8'h1A)? iw_od_0x1A : (r_address==8'h1B)? iw_od_0x1B : (r_address==8'h1C)? iw_od_0x1C : (r_address==8'h1D)? iw_od_0x1D : (r_address==8'h1E)? iw_od_0x1E : (r_address==8'h1F)? iw_od_0x1F : (r_address==8'h23)? iw_od_0x23 : (r_address==8'h24)? iw_od_0x24 : (r_address==8'h25)? iw_od_0x25 : (r_address==8'h26)? iw_od_0x26 : (r_address==8'h27)? iw_od_0x27 : (r_address==8'h28)? iw_od_0x28 : (r_address==8'h29)? iw_od_0x29 : (r_address==8'h2E)? iw_od_0x2E : (r_address==8'h2F)? iw_od_0x2F : (r_address==8'h30)? iw_od_0x30 : (r_address==8'h31)? iw_od_0x31 : (r_address==8'h32)? iw_od_0x32 : (r_address==8'h33)? iw_od_0x33 : (r_address==8'h34)? iw_od_0x34 : (r_address==8'h35)? iw_od_0x35 : (r_address==8'h36)? iw_od_0x36 : (r_address==8'h37)? iw_od_0x37 : (r_address==8'h38)? iw_od_0x38 : (r_address==8'h39)? iw_od_0x39 : (r_address==8'h3A)? iw_od_0x3A : (r_address==8'h3B)? iw_od_0x3B : (r_address==8'h3C)? iw_od_0x3C : (r_address==8'h3D)? iw_od_0x3D : (r_address==8'h3E)? iw_od_0x3E : (r_address==8'h3F)? iw_od_0x3F : (r_address==8'h40)? iw_od_0x40 : (r_address==8'h41)? iw_od_0x41 : (r_address==8'h42)? iw_od_0x42 : (r_address==8'h43)? iw_od_0x43 : (r_address==8'h44)? iw_od_0x44 : (r_address==8'h45)? iw_od_0x45 : (r_address==8'h46)? iw_od_0x46 : (r_address==8'h47)? iw_od_0x47 : (r_address==8'h48)? iw_od_0x48 : (r_address==8'h49)? iw_od_0x49 : (r_address==8'h4A)? iw_od_0x4A : (r_address==8'h4B)? iw_od_0x4B : (r_address==8'h4C)? iw_od_0x4C : (r_address==8'h4D)? iw_od_0x4D : (r_address==8'h4E)? iw_od_0x4E : (r_address==8'h4F)? iw_od_0x4F : (r_address==8'h50)? iw_od_0x50 : (r_address==8'h51)? iw_od_0x51 : (r_address==8'h52)? iw_od_0x52 : (r_address==8'h53)? iw_od_0x53 : (r_address==8'h54)? iw_od_0x54 : (r_address==8'h55)? iw_od_0x55 : (r_address==8'h56)? iw_od_0x56 : (r_address==8'h57)? iw_od_0x57 : (r_address==8'h58)? iw_od_0x58 : (r_address==8'h59)? iw_od_0x59 : (r_address==8'h5A)? iw_od_0x5A : (r_address==8'h5B)? iw_od_0x5B : (r_address==8'h5C)? iw_od_0x5C : (r_address==8'h5D)? iw_od_0x5D : (r_address==8'h5E)? iw_od_0x5E : (r_address==8'h5F)? iw_od_0x5F : (r_address==8'h60)? iw_od_0x60 : (r_address==8'h61)? iw_od_0x61 : (r_address==8'h62)? iw_od_0x62 : (r_address==8'h63)? iw_od_0x63 : (r_address==8'h64)? iw_od_0x64 : (r_address==8'h65)? iw_od_0x65 : (r_address==8'h66)? iw_od_0x66 : (r_address==8'h67)? iw_od_0x67 : (r_address==8'h68)? iw_od_0x68 : (r_address==8'h69)? iw_od_0x69 : (r_address==8'h6A)? iw_od_0x6A : (r_address==8'h6B)? iw_od_0x6B : (r_address==8'h6C)? iw_od_0x6C : (r_address==8'h6D)? iw_od_0x6D : (r_address==8'h6E)? iw_od_0x6E : (r_address==8'h6F)? iw_od_0x6F : 8'bzzzzzzzz;
endmodule |
module REG_IN_INTERFACE(ow_id_0x10, ow_id_0x11, ow_id_0x12, ow_id_0x13, ow_id_0x14, ow_id_0x15, ow_id_0x18, ow_id_0x19, ow_id_0x1A, ow_id_0x1B, ow_id_0x1C, ow_id_0x1D, ow_id_0x1E, ow_id_0x1F, ow_id_0x23, ow_id_0x24, ow_id_0x25, ow_id_0x26, ow_id_0x27, ow_id_0x28, ow_id_0x29, ow_id_0x2E, ow_id_0x2F, ow_id_0x30, ow_id_0x31, ow_id_0x32, ow_id_0x33, ow_id_0x34, ow_id_0x35, ow_id_0x36, ow_id_0x37, ow_id_0x38, ow_id_0x39, ow_id_0x3A, ow_id_0x3B, ow_id_0x3C, ow_id_0x3D, ow_id_0x3E, ow_id_0x3F, ow_id_0x40, ow_id_0x41, ow_id_0x42, ow_id_0x43, ow_id_0x44, ow_id_0x45, ow_id_0x46, ow_id_0x47, ow_id_0x48, ow_id_0x49, ow_id_0x4A, ow_id_0x4B, ow_id_0x4C, ow_id_0x4D, ow_id_0x4E, ow_id_0x4F, ow_id_0x50, ow_id_0x51, ow_id_0x52, ow_id_0x53, ow_id_0x54, ow_id_0x55, ow_id_0x56, ow_id_0x57, ow_id_0x58, ow_id_0x59, ow_id_0x5A, ow_id_0x5B, ow_id_0x5C, ow_id_0x5D, ow_id_0x5E, ow_id_0x5F, ow_id_0x60, ow_id_0x61, ow_id_0x62, ow_id_0x63, ow_id_0x64, ow_id_0x65, ow_id_0x66, ow_id_0x67, ow_id_0x68, ow_id_0x69, ow_id_0x6A, ow_id_0x6B, ow_id_0x6C, ow_id_0x6D, ow_id_0x6E, ow_id_0x6F, ow_enb_0x10, ow_enb_0x11, ow_enb_0x12, ow_enb_0x13, ow_enb_0x14, ow_enb_0x15, ow_enb_0x18, ow_enb_0x19, ow_enb_0x1A, ow_enb_0x1B, ow_enb_0x1C, ow_enb_0x1D, ow_enb_0x1E, ow_enb_0x1F, ow_enb_0x23, ow_enb_0x24, ow_enb_0x25, ow_enb_0x26, ow_enb_0x27, ow_enb_0x28, ow_enb_0x29, ow_enb_0x2E, ow_enb_0x2F, ow_enb_0x30, ow_enb_0x31, ow_enb_0x32, ow_enb_0x33, ow_enb_0x34, ow_enb_0x35, ow_enb_0x36, ow_enb_0x37, ow_enb_0x38, ow_enb_0x39, ow_enb_0x3A, ow_enb_0x3B, ow_enb_0x3C, ow_enb_0x3D, ow_enb_0x3E, ow_enb_0x3F, ow_enb_0x40, ow_enb_0x41, ow_enb_0x42, ow_enb_0x43, ow_enb_0x44, ow_enb_0x45, ow_enb_0x46, ow_enb_0x47, ow_enb_0x48, ow_enb_0x49, ow_enb_0x4A, ow_enb_0x4B, ow_enb_0x4C, ow_enb_0x4D, ow_enb_0x4E, ow_enb_0x4F, ow_enb_0x50, ow_enb_0x51, ow_enb_0x52, ow_enb_0x53, ow_enb_0x54, ow_enb_0x55, ow_enb_0x56, ow_enb_0x57, ow_enb_0x58, ow_enb_0x59, ow_enb_0x5A, ow_enb_0x5B, ow_enb_0x5C, ow_enb_0x5D, ow_enb_0x5E, ow_enb_0x5F, ow_enb_0x60, ow_enb_0x61, ow_enb_0x62, ow_enb_0x63, ow_enb_0x64, ow_enb_0x65, ow_enb_0x66, ow_enb_0x67, ow_enb_0x68, ow_enb_0x69, ow_enb_0x6A, ow_enb_0x6B, ow_enb_0x6C, ow_enb_0x6D, ow_enb_0x6E, ow_enb_0x6F, r_address, iw_id, iw_r_enb);
output wire [7:0] ow_id_0x10, ow_id_0x11, ow_id_0x12, ow_id_0x13, ow_id_0x14, ow_id_0x15, ow_id_0x18, ow_id_0x19, ow_id_0x1A, ow_id_0x1B, ow_id_0x1C, ow_id_0x1D, ow_id_0x1E, ow_id_0x1F, ow_id_0x23, ow_id_0x24, ow_id_0x25, ow_id_0x26, ow_id_0x27, ow_id_0x28, ow_id_0x29, ow_id_0x2E, ow_id_0x2F, ow_id_0x30, ow_id_0x31, ow_id_0x32, ow_id_0x33, ow_id_0x34, ow_id_0x35, ow_id_0x36, ow_id_0x37, ow_id_0x38, ow_id_0x39, ow_id_0x3A, ow_id_0x3B, ow_id_0x3C, ow_id_0x3D, ow_id_0x3E, ow_id_0x3F, ow_id_0x40, ow_id_0x41, ow_id_0x42, ow_id_0x43, ow_id_0x44, ow_id_0x45, ow_id_0x46, ow_id_0x47, ow_id_0x48, ow_id_0x49, ow_id_0x4A, ow_id_0x4B, ow_id_0x4C, ow_id_0x4D, ow_id_0x4E, ow_id_0x4F, ow_id_0x50, ow_id_0x51, ow_id_0x52, ow_id_0x53, ow_id_0x54, ow_id_0x55, ow_id_0x56, ow_id_0x57, ow_id_0x58, ow_id_0x59, ow_id_0x5A, ow_id_0x5B, ow_id_0x5C, ow_id_0x5D, ow_id_0x5E, ow_id_0x5F, ow_id_0x60, ow_id_0x61, ow_id_0x62, ow_id_0x63, ow_id_0x64, ow_id_0x65, ow_id_0x66, ow_id_0x67, ow_id_0x68, ow_id_0x69, ow_id_0x6A, ow_id_0x6B, ow_id_0x6C, ow_id_0x6D, ow_id_0x6E, ow_id_0x6F;
output wire ow_enb_0x10, ow_enb_0x11, ow_enb_0x12, ow_enb_0x13, ow_enb_0x14, ow_enb_0x15, ow_enb_0x18, ow_enb_0x19, ow_enb_0x1A, ow_enb_0x1B, ow_enb_0x1C, ow_enb_0x1D, ow_enb_0x1E, ow_enb_0x1F, ow_enb_0x23, ow_enb_0x24, ow_enb_0x25, ow_enb_0x26, ow_enb_0x27, ow_enb_0x28, ow_enb_0x29, ow_enb_0x2E, ow_enb_0x2F, ow_enb_0x30, ow_enb_0x31, ow_enb_0x32, ow_enb_0x33, ow_enb_0x34, ow_enb_0x35, ow_enb_0x36, ow_enb_0x37, ow_enb_0x38, ow_enb_0x39, ow_enb_0x3A, ow_enb_0x3B, ow_enb_0x3C, ow_enb_0x3D, ow_enb_0x3E, ow_enb_0x3F, ow_enb_0x40, ow_enb_0x41, ow_enb_0x42, ow_enb_0x43, ow_enb_0x44, ow_enb_0x45, ow_enb_0x46, ow_enb_0x47, ow_enb_0x48, ow_enb_0x49, ow_enb_0x4A, ow_enb_0x4B, ow_enb_0x4C, ow_enb_0x4D, ow_enb_0x4E, ow_enb_0x4F, ow_enb_0x50, ow_enb_0x51, ow_enb_0x52, ow_enb_0x53, ow_enb_0x54, ow_enb_0x55, ow_enb_0x56, ow_enb_0x57, ow_enb_0x58, ow_enb_0x59, ow_enb_0x5A, ow_enb_0x5B, ow_enb_0x5C, ow_enb_0x5D, ow_enb_0x5E, ow_enb_0x5F, ow_enb_0x60, ow_enb_0x61, ow_enb_0x62, ow_enb_0x63, ow_enb_0x64, ow_enb_0x65, ow_enb_0x66, ow_enb_0x67, ow_enb_0x68, ow_enb_0x69, ow_enb_0x6A, ow_enb_0x6B, ow_enb_0x6C, ow_enb_0x6D, ow_enb_0x6E, ow_enb_0x6F;
input wire [7:0] iw_id, r_address;
input wire iw_r_enb;
assign ow_id_0x10=(r_address==8'h10)?iw_id:8'h00;
assign ow_enb_0x10=(r_address==8'h10)?iw_r_enb:1'b1;
assign ow_id_0x11=(r_address==8'h11)?iw_id:8'h00;
assign ow_enb_0x11=(r_address==8'h11)?iw_r_enb:1'b1;
assign ow_id_0x12=(r_address==8'h12)?iw_id:8'h00;
assign ow_enb_0x12=(r_address==8'h12)?iw_r_enb:1'b1;
assign ow_id_0x13=(r_address==8'h13)?iw_id:8'h00;
assign ow_enb_0x13=(r_address==8'h13)?iw_r_enb:1'b1;
assign ow_id_0x14=(r_address==8'h14)?iw_id:8'h00;
assign ow_enb_0x14=(r_address==8'h14)?iw_r_enb:1'b1;
assign ow_id_0x15=(r_address==8'h15)?iw_id:8'h00;
assign ow_enb_0x15=(r_address==8'h15)?iw_r_enb:1'b1;
assign ow_id_0x18=(r_address==8'h18)?iw_id:8'h00;
assign ow_enb_0x18=(r_address==8'h18)?iw_r_enb:1'b1;
assign ow_id_0x19=(r_address==8'h19)?iw_id:8'h00;
assign ow_enb_0x19=(r_address==8'h19)?iw_r_enb:1'b1;
assign ow_id_0x1A=(r_address==8'h1A)?iw_id:8'h00;
assign ow_enb_0x1A=(r_address==8'h1A)?iw_r_enb:1'b1;
assign ow_id_0x1B=(r_address==8'h1B)?iw_id:8'h00;
assign ow_enb_0x1B=(r_address==8'h1B)?iw_r_enb:1'b1;
assign ow_id_0x1C=(r_address==8'h1C)?iw_id:8'h00;
assign ow_enb_0x1C=(r_address==8'h1C)?iw_r_enb:1'b1;
assign ow_id_0x1D=(r_address==8'h1D)?iw_id:8'h00;
assign ow_enb_0x1D=(r_address==8'h1D)?iw_r_enb:1'b1;
assign ow_id_0x1E=(r_address==8'h1E)?iw_id:8'h00;
assign ow_enb_0x1E=(r_address==8'h1E)?iw_r_enb:1'b1;
assign ow_id_0x1F=(r_address==8'h1F)?iw_id:8'h00;
assign ow_enb_0x1F=(r_address==8'h1F)?iw_r_enb:1'b1;
assign ow_id_0x23=(r_address==8'h23)?iw_id:8'h00;
assign ow_enb_0x23=(r_address==8'h23)?iw_r_enb:1'b1;
assign ow_id_0x24=(r_address==8'h24)?iw_id:8'h00;
assign ow_enb_0x24=(r_address==8'h24)?iw_r_enb:1'b1;
assign ow_id_0x25=(r_address==8'h25)?iw_id:8'h00;
assign ow_enb_0x25=(r_address==8'h25)?iw_r_enb:1'b1;
assign ow_id_0x26=(r_address==8'h26)?iw_id:8'h00;
assign ow_enb_0x26=(r_address==8'h26)?iw_r_enb:1'b1;
assign ow_id_0x27=(r_address==8'h27)?iw_id:8'h00;
assign ow_enb_0x27=(r_address==8'h27)?iw_r_enb:1'b1;
assign ow_id_0x28=(r_address==8'h28)?iw_id:8'h00;
assign ow_enb_0x28=(r_address==8'h28)?iw_r_enb:1'b1;
assign ow_id_0x29=(r_address==8'h29)?iw_id:8'h00;
assign ow_enb_0x29=(r_address==8'h29)?iw_r_enb:1'b1;
assign ow_id_0x2E=(r_address==8'h2E)?iw_id:8'h00;
assign ow_enb_0x2E=(r_address==8'h2E)?iw_r_enb:1'b1;
assign ow_id_0x2F=(r_address==8'h2F)?iw_id:8'h00;
assign ow_enb_0x2F=(r_address==8'h2F)?iw_r_enb:1'b1;
assign ow_id_0x30=(r_address==8'h30)?iw_id:8'h00;
assign ow_enb_0x30=(r_address==8'h30)?iw_r_enb:1'b1;
assign ow_id_0x31=(r_address==8'h31)?iw_id:8'h00;
assign ow_enb_0x31=(r_address==8'h31)?iw_r_enb:1'b1;
assign ow_id_0x32=(r_address==8'h32)?iw_id:8'h00;
assign ow_enb_0x32=(r_address==8'h32)?iw_r_enb:1'b1;
assign ow_id_0x33=(r_address==8'h33)?iw_id:8'h00;
assign ow_enb_0x33=(r_address==8'h33)?iw_r_enb:1'b1;
assign ow_id_0x34=(r_address==8'h34)?iw_id:8'h00;
assign ow_enb_0x34=(r_address==8'h34)?iw_r_enb:1'b1;
assign ow_id_0x35=(r_address==8'h35)?iw_id:8'h00;
assign ow_enb_0x35=(r_address==8'h35)?iw_r_enb:1'b1;
assign ow_id_0x36=(r_address==8'h36)?iw_id:8'h00;
assign ow_enb_0x36=(r_address==8'h36)?iw_r_enb:1'b1;
assign ow_id_0x37=(r_address==8'h37)?iw_id:8'h00;
assign ow_enb_0x37=(r_address==8'h37)?iw_r_enb:1'b1;
assign ow_id_0x38=(r_address==8'h38)?iw_id:8'h00;
assign ow_enb_0x38=(r_address==8'h38)?iw_r_enb:1'b1;
assign ow_id_0x39=(r_address==8'h39)?iw_id:8'h00;
assign ow_enb_0x39=(r_address==8'h39)?iw_r_enb:1'b1;
assign ow_id_0x3A=(r_address==8'h3A)?iw_id:8'h00;
assign ow_enb_0x3A=(r_address==8'h3A)?iw_r_enb:1'b1;
assign ow_id_0x3B=(r_address==8'h3B)?iw_id:8'h00;
assign ow_enb_0x3B=(r_address==8'h3B)?iw_r_enb:1'b1;
assign ow_id_0x3C=(r_address==8'h3C)?iw_id:8'h00;
assign ow_enb_0x3C=(r_address==8'h3C)?iw_r_enb:1'b1;
assign ow_id_0x3D=(r_address==8'h3D)?iw_id:8'h00;
assign ow_enb_0x3D=(r_address==8'h3D)?iw_r_enb:1'b1;
assign ow_id_0x3E=(r_address==8'h3E)?iw_id:8'h00;
assign ow_enb_0x3E=(r_address==8'h3E)?iw_r_enb:1'b1;
assign ow_id_0x3F=(r_address==8'h3F)?iw_id:8'h00;
assign ow_enb_0x3F=(r_address==8'h3F)?iw_r_enb:1'b1;
assign ow_id_0x40=(r_address==8'h40)?iw_id:8'h00;
assign ow_enb_0x40=(r_address==8'h40)?iw_r_enb:1'b1;
assign ow_id_0x41=(r_address==8'h41)?iw_id:8'h00;
assign ow_enb_0x41=(r_address==8'h41)?iw_r_enb:1'b1;
assign ow_id_0x42=(r_address==8'h42)?iw_id:8'h00;
assign ow_enb_0x42=(r_address==8'h42)?iw_r_enb:1'b1;
assign ow_id_0x43=(r_address==8'h43)?iw_id:8'h00;
assign ow_enb_0x43=(r_address==8'h43)?iw_r_enb:1'b1;
assign ow_id_0x44=(r_address==8'h44)?iw_id:8'h00;
assign ow_enb_0x44=(r_address==8'h44)?iw_r_enb:1'b1;
assign ow_id_0x45=(r_address==8'h45)?iw_id:8'h00;
assign ow_enb_0x45=(r_address==8'h45)?iw_r_enb:1'b1;
assign ow_id_0x46=(r_address==8'h46)?iw_id:8'h00;
assign ow_enb_0x46=(r_address==8'h46)?iw_r_enb:1'b1;
assign ow_id_0x47=(r_address==8'h47)?iw_id:8'h00;
assign ow_enb_0x47=(r_address==8'h47)?iw_r_enb:1'b1;
assign ow_id_0x48=(r_address==8'h48)?iw_id:8'h00;
assign ow_enb_0x48=(r_address==8'h48)?iw_r_enb:1'b1;
assign ow_id_0x49=(r_address==8'h49)?iw_id:8'h00;
assign ow_enb_0x49=(r_address==8'h49)?iw_r_enb:1'b1;
assign ow_id_0x4A=(r_address==8'h4A)?iw_id:8'h00;
assign ow_enb_0x4A=(r_address==8'h4A)?iw_r_enb:1'b1;
assign ow_id_0x4B=(r_address==8'h4B)?iw_id:8'h00;
assign ow_enb_0x4B=(r_address==8'h4B)?iw_r_enb:1'b1;
assign ow_id_0x4C=(r_address==8'h4C)?iw_id:8'h00;
assign ow_enb_0x4C=(r_address==8'h4C)?iw_r_enb:1'b1;
assign ow_id_0x4D=(r_address==8'h4D)?iw_id:8'h00;
assign ow_enb_0x4D=(r_address==8'h4D)?iw_r_enb:1'b1;
assign ow_id_0x4E=(r_address==8'h4E)?iw_id:8'h00;
assign ow_enb_0x4E=(r_address==8'h4E)?iw_r_enb:1'b1;
assign ow_id_0x4F=(r_address==8'h4F)?iw_id:8'h00;
assign ow_enb_0x4F=(r_address==8'h4F)?iw_r_enb:1'b1;
assign ow_id_0x50=(r_address==8'h50)?iw_id:8'h00;
assign ow_enb_0x50=(r_address==8'h50)?iw_r_enb:1'b1;
assign ow_id_0x51=(r_address==8'h51)?iw_id:8'h00;
assign ow_enb_0x51=(r_address==8'h51)?iw_r_enb:1'b1;
assign ow_id_0x52=(r_address==8'h52)?iw_id:8'h00;
assign ow_enb_0x52=(r_address==8'h52)?iw_r_enb:1'b1;
assign ow_id_0x53=(r_address==8'h53)?iw_id:8'h00;
assign ow_enb_0x53=(r_address==8'h53)?iw_r_enb:1'b1;
assign ow_id_0x54=(r_address==8'h54)?iw_id:8'h00;
assign ow_enb_0x54=(r_address==8'h54)?iw_r_enb:1'b1;
assign ow_id_0x55=(r_address==8'h55)?iw_id:8'h00;
assign ow_enb_0x55=(r_address==8'h55)?iw_r_enb:1'b1;
assign ow_id_0x56=(r_address==8'h56)?iw_id:8'h00;
assign ow_enb_0x56=(r_address==8'h56)?iw_r_enb:1'b1;
assign ow_id_0x57=(r_address==8'h57)?iw_id:8'h00;
assign ow_enb_0x57=(r_address==8'h57)?iw_r_enb:1'b1;
assign ow_id_0x58=(r_address==8'h58)?iw_id:8'h00;
assign ow_enb_0x58=(r_address==8'h58)?iw_r_enb:1'b1;
assign ow_id_0x59=(r_address==8'h59)?iw_id:8'h00;
assign ow_enb_0x59=(r_address==8'h59)?iw_r_enb:1'b1;
assign ow_id_0x5A=(r_address==8'h5A)?iw_id:8'h00;
assign ow_enb_0x5A=(r_address==8'h5A)?iw_r_enb:1'b1;
assign ow_id_0x5B=(r_address==8'h5B)?iw_id:8'h00;
assign ow_enb_0x5B=(r_address==8'h5B)?iw_r_enb:1'b1;
assign ow_id_0x5C=(r_address==8'h5C)?iw_id:8'h00;
assign ow_enb_0x5C=(r_address==8'h5C)?iw_r_enb:1'b1;
assign ow_id_0x5D=(r_address==8'h5D)?iw_id:8'h00;
assign ow_enb_0x5D=(r_address==8'h5D)?iw_r_enb:1'b1;
assign ow_id_0x5E=(r_address==8'h5E)?iw_id:8'h00;
assign ow_enb_0x5E=(r_address==8'h5E)?iw_r_enb:1'b1;
assign ow_id_0x5F=(r_address==8'h5F)?iw_id:8'h00;
assign ow_enb_0x5F=(r_address==8'h5F)?iw_r_enb:1'b1;
assign ow_id_0x60=(r_address==8'h60)?iw_id:8'h00;
assign ow_enb_0x60=(r_address==8'h60)?iw_r_enb:1'b1;
assign ow_id_0x61=(r_address==8'h61)?iw_id:8'h00;
assign ow_enb_0x61=(r_address==8'h61)?iw_r_enb:1'b1;
assign ow_id_0x62=(r_address==8'h62)?iw_id:8'h00;
assign ow_enb_0x62=(r_address==8'h62)?iw_r_enb:1'b1;
assign ow_id_0x63=(r_address==8'h63)?iw_id:8'h00;
assign ow_enb_0x63=(r_address==8'h63)?iw_r_enb:1'b1;
assign ow_id_0x64=(r_address==8'h64)?iw_id:8'h00;
assign ow_enb_0x64=(r_address==8'h64)?iw_r_enb:1'b1;
assign ow_id_0x65=(r_address==8'h65)?iw_id:8'h00;
assign ow_enb_0x65=(r_address==8'h65)?iw_r_enb:1'b1;
assign ow_id_0x66=(r_address==8'h66)?iw_id:8'h00;
assign ow_enb_0x66=(r_address==8'h66)?iw_r_enb:1'b1;
assign ow_id_0x67=(r_address==8'h67)?iw_id:8'h00;
assign ow_enb_0x67=(r_address==8'h67)?iw_r_enb:1'b1;
assign ow_id_0x68=(r_address==8'h68)?iw_id:8'h00;
assign ow_enb_0x68=(r_address==8'h68)?iw_r_enb:1'b1;
assign ow_id_0x69=(r_address==8'h69)?iw_id:8'h00;
assign ow_enb_0x69=(r_address==8'h69)?iw_r_enb:1'b1;
assign ow_id_0x6A=(r_address==8'h6A)?iw_id:8'h00;
assign ow_enb_0x6A=(r_address==8'h6A)?iw_r_enb:1'b1;
assign ow_id_0x6B=(r_address==8'h6B)?iw_id:8'h00;
assign ow_enb_0x6B=(r_address==8'h6B)?iw_r_enb:1'b1;
assign ow_id_0x6C=(r_address==8'h6C)?iw_id:8'h00;
assign ow_enb_0x6C=(r_address==8'h6C)?iw_r_enb:1'b1;
assign ow_id_0x6D=(r_address==8'h6D)?iw_id:8'h00;
assign ow_enb_0x6D=(r_address==8'h6D)?iw_r_enb:1'b1;
assign ow_id_0x6E=(r_address==8'h6E)?iw_id:8'h00;
assign ow_enb_0x6E=(r_address==8'h6E)?iw_r_enb:1'b1;
assign ow_id_0x6F=(r_address==8'h6F)?iw_id:8'h00;
assign ow_enb_0x6F=(r_address==8'h6F)?iw_r_enb:1'b1;
endmodule |
module REG_INTERFACE(ow_od_0, ow_od_1, ow_od_2, ow_od_transmit, ow_od_TX_BUF_HEADER_BYTE_1, ow_od_RX_BUF_HEADER_BYTE_1, ow_od_RX_BUF_FRAME_TYPE, r_address_0, r_address_1, r_address_2, iw_id_0, iw_id_1, iw_id_2, iw_enb_0, iw_enb_1, iw_enb_2, reset, clk);
output wire [7:0] ow_od_0, ow_od_1, ow_od_2, ow_od_transmit, ow_od_TX_BUF_HEADER_BYTE_1, ow_od_RX_BUF_HEADER_BYTE_1, ow_od_RX_BUF_FRAME_TYPE;
input wire [7:0] r_address_0, r_address_1, r_address_2, iw_id_0, iw_id_1, iw_id_2;
input wire iw_enb_0, iw_enb_1, iw_enb_2;
input wire reset, clk;
wire [7:0] ow_reg_0x00, ow_reg_0x01, ow_reg_0x02, ow_reg_0x03, ow_reg_0x04, ow_reg_0x05, ow_reg_0x06, ow_reg_0x07, ow_reg_0x08, ow_reg_0x09, ow_reg_0x0A, ow_reg_0x0B, ow_reg_0x10, ow_reg_0x11, ow_reg_0x12, ow_reg_0x13, ow_reg_0x14, ow_reg_0x15, ow_reg_0x18, ow_reg_0x19, ow_reg_0x1A, ow_reg_0x1B, ow_reg_0x1C, ow_reg_0x1D, ow_reg_0x1E, ow_reg_0x1F, ow_reg_0x23, ow_reg_0x24, ow_reg_0x25, ow_reg_0x26, ow_reg_0x27, ow_reg_0x28, ow_reg_0x29, ow_reg_0x2E, ow_reg_0x2F, ow_reg_0x30, ow_reg_0x31, ow_reg_0x32, ow_reg_0x33, ow_reg_0x34, ow_reg_0x35, ow_reg_0x36, ow_reg_0x37, ow_reg_0x38, ow_reg_0x39, ow_reg_0x3A, ow_reg_0x3B, ow_reg_0x3C, ow_reg_0x3D, ow_reg_0x3E, ow_reg_0x3F, ow_reg_0x40, ow_reg_0x41, ow_reg_0x42, ow_reg_0x43, ow_reg_0x44, ow_reg_0x45, ow_reg_0x46, ow_reg_0x47, ow_reg_0x48, ow_reg_0x49, ow_reg_0x4A, ow_reg_0x4B, ow_reg_0x4C, ow_reg_0x4D, ow_reg_0x4E, ow_reg_0x4F, ow_reg_0x50, ow_reg_0x51, ow_reg_0x52, ow_reg_0x53, ow_reg_0x54, ow_reg_0x55, ow_reg_0x56, ow_reg_0x57, ow_reg_0x58, ow_reg_0x59, ow_reg_0x5A, ow_reg_0x5B, ow_reg_0x5C, ow_reg_0x5D, ow_reg_0x5E, ow_reg_0x5F, ow_reg_0x60, ow_reg_0x61, ow_reg_0x62, ow_reg_0x63, ow_reg_0x64, ow_reg_0x65, ow_reg_0x66, ow_reg_0x67, ow_reg_0x68, ow_reg_0x69, ow_reg_0x6A, ow_reg_0x6B, ow_reg_0x6C, ow_reg_0x6D, ow_reg_0x6E, ow_reg_0x6F;
wire [7:0] iw_reg_0x10, iw_reg_0x11, iw_reg_0x12, iw_reg_0x13, iw_reg_0x14, iw_reg_0x15, iw_reg_0x18, iw_reg_0x19, iw_reg_0x1A, iw_reg_0x1B, iw_reg_0x1C, iw_reg_0x1D, iw_reg_0x1E, iw_reg_0x1F, iw_reg_0x23, iw_reg_0x24, iw_reg_0x25, iw_reg_0x26, iw_reg_0x27, iw_reg_0x28, iw_reg_0x29, iw_reg_0x2E, iw_reg_0x2F, iw_reg_0x30, iw_reg_0x31, iw_reg_0x32, iw_reg_0x33, iw_reg_0x34, iw_reg_0x35, iw_reg_0x36, iw_reg_0x37, iw_reg_0x38, iw_reg_0x39, iw_reg_0x3A, iw_reg_0x3B, iw_reg_0x3C, iw_reg_0x3D, iw_reg_0x3E, iw_reg_0x3F, iw_reg_0x40, iw_reg_0x41, iw_reg_0x42, iw_reg_0x43, iw_reg_0x44, iw_reg_0x45, iw_reg_0x46, iw_reg_0x47, iw_reg_0x48, iw_reg_0x49, iw_reg_0x4A, iw_reg_0x4B, iw_reg_0x4C, iw_reg_0x4D, iw_reg_0x4E, iw_reg_0x4F, iw_reg_0x50, iw_reg_0x51, iw_reg_0x52, iw_reg_0x53, iw_reg_0x54, iw_reg_0x55, iw_reg_0x56, iw_reg_0x57, iw_reg_0x58, iw_reg_0x59, iw_reg_0x5A, iw_reg_0x5B, iw_reg_0x5C, iw_reg_0x5D, iw_reg_0x5E, iw_reg_0x5F, iw_reg_0x60, iw_reg_0x61, iw_reg_0x62, iw_reg_0x63, iw_reg_0x64, iw_reg_0x65, iw_reg_0x66, iw_reg_0x67, iw_reg_0x68, iw_reg_0x69, iw_reg_0x6A, iw_reg_0x6B, iw_reg_0x6C, iw_reg_0x6D, iw_reg_0x6E, iw_reg_0x6F;
wire enb_0x10, enb_0x11, enb_0x12, enb_0x13, enb_0x14, enb_0x15, enb_0x18, enb_0x19, enb_0x1A, enb_0x1B, enb_0x1C, enb_0x1D, enb_0x1E, enb_0x1F, enb_0x23, enb_0x24, enb_0x25, enb_0x26, enb_0x27, enb_0x28, enb_0x29, enb_0x2E, enb_0x2F, enb_0x30, enb_0x31, enb_0x32, enb_0x33, enb_0x34, enb_0x35, enb_0x36, enb_0x37, enb_0x38, enb_0x39, enb_0x3A, enb_0x3B, enb_0x3C, enb_0x3D, enb_0x3E, enb_0x3F, enb_0x40, enb_0x41, enb_0x42, enb_0x43, enb_0x44, enb_0x45, enb_0x46, enb_0x47, enb_0x48, enb_0x49, enb_0x4A, enb_0x4B, enb_0x4C, enb_0x4D, enb_0x4E, enb_0x4F, enb_0x50, enb_0x51, enb_0x52, enb_0x53, enb_0x54, enb_0x55, enb_0x56, enb_0x57, enb_0x58, enb_0x59, enb_0x5A, enb_0x5B, enb_0x5C, enb_0x5D, enb_0x5E, enb_0x5F, enb_0x60, enb_0x61, enb_0x62, enb_0x63, enb_0x64, enb_0x65, enb_0x66, enb_0x67, enb_0x68, enb_0x69, enb_0x6A, enb_0x6B, enb_0x6C, enb_0x6D, enb_0x6E, enb_0x6F;
wire [7:0] ow_i0_id_0x10, ow_i0_id_0x11, ow_i0_id_0x12, ow_i0_id_0x13, ow_i0_id_0x14, ow_i0_id_0x15, ow_i0_id_0x18, ow_i0_id_0x19, ow_i0_id_0x1A, ow_i0_id_0x1B, ow_i0_id_0x1C, ow_i0_id_0x1D, ow_i0_id_0x1E, ow_i0_id_0x1F, ow_i0_id_0x23, ow_i0_id_0x24, ow_i0_id_0x25, ow_i0_id_0x26, ow_i0_id_0x27, ow_i0_id_0x28, ow_i0_id_0x29, ow_i0_id_0x2E, ow_i0_id_0x2F, ow_i0_id_0x30, ow_i0_id_0x31, ow_i0_id_0x32, ow_i0_id_0x33, ow_i0_id_0x34, ow_i0_id_0x35, ow_i0_id_0x36, ow_i0_id_0x37, ow_i0_id_0x38, ow_i0_id_0x39, ow_i0_id_0x3A, ow_i0_id_0x3B, ow_i0_id_0x3C, ow_i0_id_0x3D, ow_i0_id_0x3E, ow_i0_id_0x3F, ow_i0_id_0x40, ow_i0_id_0x41, ow_i0_id_0x42, ow_i0_id_0x43, ow_i0_id_0x44, ow_i0_id_0x45, ow_i0_id_0x46, ow_i0_id_0x47, ow_i0_id_0x48, ow_i0_id_0x49, ow_i0_id_0x4A, ow_i0_id_0x4B, ow_i0_id_0x4C, ow_i0_id_0x4D, ow_i0_id_0x4E, ow_i0_id_0x4F, ow_i0_id_0x50, ow_i0_id_0x51, ow_i0_id_0x52, ow_i0_id_0x53, ow_i0_id_0x54, ow_i0_id_0x55, ow_i0_id_0x56, ow_i0_id_0x57, ow_i0_id_0x58, ow_i0_id_0x59, ow_i0_id_0x5A, ow_i0_id_0x5B, ow_i0_id_0x5C, ow_i0_id_0x5D, ow_i0_id_0x5E, ow_i0_id_0x5F, ow_i0_id_0x60, ow_i0_id_0x61, ow_i0_id_0x62, ow_i0_id_0x63, ow_i0_id_0x64, ow_i0_id_0x65, ow_i0_id_0x66, ow_i0_id_0x67, ow_i0_id_0x68, ow_i0_id_0x69, ow_i0_id_0x6A, ow_i0_id_0x6B, ow_i0_id_0x6C, ow_i0_id_0x6D, ow_i0_id_0x6E, ow_i0_id_0x6F, ow_i1_id_0x10, ow_i1_id_0x11, ow_i1_id_0x12, ow_i1_id_0x13, ow_i1_id_0x14, ow_i1_id_0x15, ow_i1_id_0x18, ow_i1_id_0x19, ow_i1_id_0x1A, ow_i1_id_0x1B, ow_i1_id_0x1C, ow_i1_id_0x1D, ow_i1_id_0x1E, ow_i1_id_0x1F, ow_i1_id_0x23, ow_i1_id_0x24, ow_i1_id_0x25, ow_i1_id_0x26, ow_i1_id_0x27, ow_i1_id_0x28, ow_i1_id_0x29, ow_i1_id_0x2E, ow_i1_id_0x2F, ow_i1_id_0x30, ow_i1_id_0x31, ow_i1_id_0x32, ow_i1_id_0x33, ow_i1_id_0x34, ow_i1_id_0x35, ow_i1_id_0x36, ow_i1_id_0x37, ow_i1_id_0x38, ow_i1_id_0x39, ow_i1_id_0x3A, ow_i1_id_0x3B, ow_i1_id_0x3C, ow_i1_id_0x3D, ow_i1_id_0x3E, ow_i1_id_0x3F, ow_i1_id_0x40, ow_i1_id_0x41, ow_i1_id_0x42, ow_i1_id_0x43, ow_i1_id_0x44, ow_i1_id_0x45, ow_i1_id_0x46, ow_i1_id_0x47, ow_i1_id_0x48, ow_i1_id_0x49, ow_i1_id_0x4A, ow_i1_id_0x4B, ow_i1_id_0x4C, ow_i1_id_0x4D, ow_i1_id_0x4E, ow_i1_id_0x4F, ow_i1_id_0x50, ow_i1_id_0x51, ow_i1_id_0x52, ow_i1_id_0x53, ow_i1_id_0x54, ow_i1_id_0x55, ow_i1_id_0x56, ow_i1_id_0x57, ow_i1_id_0x58, ow_i1_id_0x59, ow_i1_id_0x5A, ow_i1_id_0x5B, ow_i1_id_0x5C, ow_i1_id_0x5D, ow_i1_id_0x5E, ow_i1_id_0x5F, ow_i1_id_0x60, ow_i1_id_0x61, ow_i1_id_0x62, ow_i1_id_0x63, ow_i1_id_0x64, ow_i1_id_0x65, ow_i1_id_0x66, ow_i1_id_0x67, ow_i1_id_0x68, ow_i1_id_0x69, ow_i1_id_0x6A, ow_i1_id_0x6B, ow_i1_id_0x6C, ow_i1_id_0x6D, ow_i1_id_0x6E, ow_i1_id_0x6F, ow_i2_id_0x10, ow_i2_id_0x11, ow_i2_id_0x12, ow_i2_id_0x13, ow_i2_id_0x14, ow_i2_id_0x15, ow_i2_id_0x18, ow_i2_id_0x19, ow_i2_id_0x1A, ow_i2_id_0x1B, ow_i2_id_0x1C, ow_i2_id_0x1D, ow_i2_id_0x1E, ow_i2_id_0x1F, ow_i2_id_0x23, ow_i2_id_0x24, ow_i2_id_0x25, ow_i2_id_0x26, ow_i2_id_0x27, ow_i2_id_0x28, ow_i2_id_0x29, ow_i2_id_0x2E, ow_i2_id_0x2F, ow_i2_id_0x30, ow_i2_id_0x31, ow_i2_id_0x32, ow_i2_id_0x33, ow_i2_id_0x34, ow_i2_id_0x35, ow_i2_id_0x36, ow_i2_id_0x37, ow_i2_id_0x38, ow_i2_id_0x39, ow_i2_id_0x3A, ow_i2_id_0x3B, ow_i2_id_0x3C, ow_i2_id_0x3D, ow_i2_id_0x3E, ow_i2_id_0x3F, ow_i2_id_0x40, ow_i2_id_0x41, ow_i2_id_0x42, ow_i2_id_0x43, ow_i2_id_0x44, ow_i2_id_0x45, ow_i2_id_0x46, ow_i2_id_0x47, ow_i2_id_0x48, ow_i2_id_0x49, ow_i2_id_0x4A, ow_i2_id_0x4B, ow_i2_id_0x4C, ow_i2_id_0x4D, ow_i2_id_0x4E, ow_i2_id_0x4F, ow_i2_id_0x50, ow_i2_id_0x51, ow_i2_id_0x52, ow_i2_id_0x53, ow_i2_id_0x54, ow_i2_id_0x55, ow_i2_id_0x56, ow_i2_id_0x57, ow_i2_id_0x58, ow_i2_id_0x59, ow_i2_id_0x5A, ow_i2_id_0x5B, ow_i2_id_0x5C, ow_i2_id_0x5D, ow_i2_id_0x5E, ow_i2_id_0x5F, ow_i2_id_0x60, ow_i2_id_0x61, ow_i2_id_0x62, ow_i2_id_0x63, ow_i2_id_0x64, ow_i2_id_0x65, ow_i2_id_0x66, ow_i2_id_0x67, ow_i2_id_0x68, ow_i2_id_0x69, ow_i2_id_0x6A, ow_i2_id_0x6B, ow_i2_id_0x6C, ow_i2_id_0x6D, ow_i2_id_0x6E, ow_i2_id_0x6F;
wire ow_i0_enb_0x10, ow_i0_enb_0x11, ow_i0_enb_0x12, ow_i0_enb_0x13, ow_i0_enb_0x14, ow_i0_enb_0x15, ow_i0_enb_0x18, ow_i0_enb_0x19, ow_i0_enb_0x1A, ow_i0_enb_0x1B, ow_i0_enb_0x1C, ow_i0_enb_0x1D, ow_i0_enb_0x1E, ow_i0_enb_0x1F, ow_i0_enb_0x23, ow_i0_enb_0x24, ow_i0_enb_0x25, ow_i0_enb_0x26, ow_i0_enb_0x27, ow_i0_enb_0x28, ow_i0_enb_0x29, ow_i0_enb_0x2E, ow_i0_enb_0x2F, ow_i0_enb_0x30, ow_i0_enb_0x31, ow_i0_enb_0x32, ow_i0_enb_0x33, ow_i0_enb_0x34, ow_i0_enb_0x35, ow_i0_enb_0x36, ow_i0_enb_0x37, ow_i0_enb_0x38, ow_i0_enb_0x39, ow_i0_enb_0x3A, ow_i0_enb_0x3B, ow_i0_enb_0x3C, ow_i0_enb_0x3D, ow_i0_enb_0x3E, ow_i0_enb_0x3F, ow_i0_enb_0x40, ow_i0_enb_0x41, ow_i0_enb_0x42, ow_i0_enb_0x43, ow_i0_enb_0x44, ow_i0_enb_0x45, ow_i0_enb_0x46, ow_i0_enb_0x47, ow_i0_enb_0x48, ow_i0_enb_0x49, ow_i0_enb_0x4A, ow_i0_enb_0x4B, ow_i0_enb_0x4C, ow_i0_enb_0x4D, ow_i0_enb_0x4E, ow_i0_enb_0x4F, ow_i0_enb_0x50, ow_i0_enb_0x51, ow_i0_enb_0x52, ow_i0_enb_0x53, ow_i0_enb_0x54, ow_i0_enb_0x55, ow_i0_enb_0x56, ow_i0_enb_0x57, ow_i0_enb_0x58, ow_i0_enb_0x59, ow_i0_enb_0x5A, ow_i0_enb_0x5B, ow_i0_enb_0x5C, ow_i0_enb_0x5D, ow_i0_enb_0x5E, ow_i0_enb_0x5F, ow_i0_enb_0x60, ow_i0_enb_0x61, ow_i0_enb_0x62, ow_i0_enb_0x63, ow_i0_enb_0x64, ow_i0_enb_0x65, ow_i0_enb_0x66, ow_i0_enb_0x67, ow_i0_enb_0x68, ow_i0_enb_0x69, ow_i0_enb_0x6A, ow_i0_enb_0x6B, ow_i0_enb_0x6C, ow_i0_enb_0x6D, ow_i0_enb_0x6E, ow_i0_enb_0x6F, ow_i1_enb_0x10, ow_i1_enb_0x11, ow_i1_enb_0x12, ow_i1_enb_0x13, ow_i1_enb_0x14, ow_i1_enb_0x15, ow_i1_enb_0x18, ow_i1_enb_0x19, ow_i1_enb_0x1A, ow_i1_enb_0x1B, ow_i1_enb_0x1C, ow_i1_enb_0x1D, ow_i1_enb_0x1E, ow_i1_enb_0x1F, ow_i1_enb_0x23, ow_i1_enb_0x24, ow_i1_enb_0x25, ow_i1_enb_0x26, ow_i1_enb_0x27, ow_i1_enb_0x28, ow_i1_enb_0x29, ow_i1_enb_0x2E, ow_i1_enb_0x2F, ow_i1_enb_0x30, ow_i1_enb_0x31, ow_i1_enb_0x32, ow_i1_enb_0x33, ow_i1_enb_0x34, ow_i1_enb_0x35, ow_i1_enb_0x36, ow_i1_enb_0x37, ow_i1_enb_0x38, ow_i1_enb_0x39, ow_i1_enb_0x3A, ow_i1_enb_0x3B, ow_i1_enb_0x3C, ow_i1_enb_0x3D, ow_i1_enb_0x3E, ow_i1_enb_0x3F, ow_i1_enb_0x40, ow_i1_enb_0x41, ow_i1_enb_0x42, ow_i1_enb_0x43, ow_i1_enb_0x44, ow_i1_enb_0x45, ow_i1_enb_0x46, ow_i1_enb_0x47, ow_i1_enb_0x48, ow_i1_enb_0x49, ow_i1_enb_0x4A, ow_i1_enb_0x4B, ow_i1_enb_0x4C, ow_i1_enb_0x4D, ow_i1_enb_0x4E, ow_i1_enb_0x4F, ow_i1_enb_0x50, ow_i1_enb_0x51, ow_i1_enb_0x52, ow_i1_enb_0x53, ow_i1_enb_0x54, ow_i1_enb_0x55, ow_i1_enb_0x56, ow_i1_enb_0x57, ow_i1_enb_0x58, ow_i1_enb_0x59, ow_i1_enb_0x5A, ow_i1_enb_0x5B, ow_i1_enb_0x5C, ow_i1_enb_0x5D, ow_i1_enb_0x5E, ow_i1_enb_0x5F, ow_i1_enb_0x60, ow_i1_enb_0x61, ow_i1_enb_0x62, ow_i1_enb_0x63, ow_i1_enb_0x64, ow_i1_enb_0x65, ow_i1_enb_0x66, ow_i1_enb_0x67, ow_i1_enb_0x68, ow_i1_enb_0x69, ow_i1_enb_0x6A, ow_i1_enb_0x6B, ow_i1_enb_0x6C, ow_i1_enb_0x6D, ow_i1_enb_0x6E, ow_i1_enb_0x6F, ow_i2_enb_0x10,ow_i2_enb_0x11, ow_i2_enb_0x12, ow_i2_enb_0x13, ow_i2_enb_0x14, ow_i2_enb_0x15, ow_i2_enb_0x18, ow_i2_enb_0x19, ow_i2_enb_0x1A, ow_i2_enb_0x1B, ow_i2_enb_0x1C, ow_i2_enb_0x1D, ow_i2_enb_0x1E, ow_i2_enb_0x1F, ow_i2_enb_0x23, ow_i2_enb_0x24, ow_i2_enb_0x25, ow_i2_enb_0x26, ow_i2_enb_0x27, ow_i2_enb_0x28, ow_i2_enb_0x29, ow_i2_enb_0x2E, ow_i2_enb_0x2F, ow_i2_enb_0x30, ow_i2_enb_0x31, ow_i2_enb_0x32, ow_i2_enb_0x33, ow_i2_enb_0x34, ow_i2_enb_0x35, ow_i2_enb_0x36, ow_i2_enb_0x37, ow_i2_enb_0x38, ow_i2_enb_0x39, ow_i2_enb_0x3A, ow_i2_enb_0x3B, ow_i2_enb_0x3C, ow_i2_enb_0x3D, ow_i2_enb_0x3E, ow_i2_enb_0x3F, ow_i2_enb_0x40, ow_i2_enb_0x41, ow_i2_enb_0x42, ow_i2_enb_0x43, ow_i2_enb_0x44, ow_i2_enb_0x45, ow_i2_enb_0x46, ow_i2_enb_0x47, ow_i2_enb_0x48, ow_i2_enb_0x49, ow_i2_enb_0x4A, ow_i2_enb_0x4B, ow_i2_enb_0x4C, ow_i2_enb_0x4D, ow_i2_enb_0x4E, ow_i2_enb_0x4F, ow_i2_enb_0x50, ow_i2_enb_0x51, ow_i2_enb_0x52, ow_i2_enb_0x53, ow_i2_enb_0x54, ow_i2_enb_0x55, ow_i2_enb_0x56, ow_i2_enb_0x57, ow_i2_enb_0x58, ow_i2_enb_0x59, ow_i2_enb_0x5A, ow_i2_enb_0x5B, ow_i2_enb_0x5C, ow_i2_enb_0x5D, ow_i2_enb_0x5E, ow_i2_enb_0x5F, ow_i2_enb_0x60, ow_i2_enb_0x61, ow_i2_enb_0x62, ow_i2_enb_0x63, ow_i2_enb_0x64, ow_i2_enb_0x65, ow_i2_enb_0x66, ow_i2_enb_0x67, ow_i2_enb_0x68, ow_i2_enb_0x69, ow_i2_enb_0x6A, ow_i2_enb_0x6B, ow_i2_enb_0x6C, ow_i2_enb_0x6D, ow_i2_enb_0x6E, ow_i2_enb_0x6F;
r_VENDOR_ID_LOW reg_0x00(ow_reg_0x00);
r_VENDOR_ID_HIGH reg_0x01(ow_reg_0x01);
r_PRODUCT_ID_LOW reg_0x02(ow_reg_0x02);
r_PRODUCT_ID_HIGH reg_0x03(ow_reg_0x03);
r_DEVICE_ID_LOW reg_0x04(ow_reg_0x04);
r_DEVICE_ID_HIGH reg_0x05(ow_reg_0x05);
r_USBTYPEC_REV_LOW reg_0x06(ow_reg_0x06);
r_USBTYPEC_REV_HIGH reg_0x07(ow_reg_0x07);
r_USBPD_REV_VER_LOW reg_0x08(ow_reg_0x08);
r_USBPD_REV_VER_HIGH reg_0x09(ow_reg_0x09);
r_PD_INTERFACE_REV_LOW reg_0x0A(ow_reg_0x0A);
r_PD_INTERFACE_REV_HIGH reg_0x0B(ow_reg_0x0B);
r_ALERT_LOW reg_0x10(ow_reg_0x10, reset, enb_0x10, iw_reg_0x10, clk);
r_ALERT_HIGH reg_0x11(ow_reg_0x11, reset, enb_0x11, iw_reg_0x11, clk);
r_ALERT_MASK_LOW reg_0x12(ow_reg_0x12, reset, enb_0x12, iw_reg_0x12, clk);
r_ALERT_MASK_HIGH reg_0x13(ow_reg_0x13, reset, enb_0x13, iw_reg_0x13, clk);
r_POWER_STATUS_MASK reg_0x14(ow_reg_0x14, reset, enb_0x14, iw_reg_0x14, clk);
r_FAULT_STATUS_MASK reg_0x15(ow_reg_0x15, reset, enb_0x15, iw_reg_0x15, clk);
r_CONFIG_STANDARD_OUTPUT reg_0x18(ow_reg_0x18, reset, enb_0x18, iw_reg_0x18, clk);
r_TCPC_CONTROL reg_0x19(ow_reg_0x19, reset, enb_0x19, iw_reg_0x19, clk);
r_ROLE_CONTROL reg_0x1A(ow_reg_0x1A, reset, enb_0x1A, iw_reg_0x1A, clk);
r_FAULT_CONTROL reg_0x1B(ow_reg_0x1B, reset, enb_0x1B, iw_reg_0x1B, clk);
r_POWER_CONTROL reg_0x1C(ow_reg_0x1C, reset, enb_0x1C, iw_reg_0x1C, clk);
r_CC_STATUS reg_0x1D(ow_reg_0x1D, reset, enb_0x1D, iw_reg_0x1D, clk);
r_POWER_STATUS reg_0x1E(ow_reg_0x1E, reset, enb_0x1E, iw_reg_0x1E, clk);
r_FAULT_STATUS reg_0x1F(ow_reg_0x1F, reset, enb_0x1F, iw_reg_0x1F, clk);
r_COMMAND reg_0x23(ow_reg_0x23, reset, enb_0x23, iw_reg_0x23, clk);
r_DEVICE_CAPABILITIES_1_LOW reg_0x24(ow_reg_0x24, reset, enb_0x24, iw_reg_0x24, clk);
r_DEVICE_CAPABILITIES_1_HIGH reg_0x25(ow_reg_0x25, reset, enb_0x25, iw_reg_0x25, clk);
r_DEVICE_CAPABILITIES_2_LOW reg_0x26(ow_reg_0x26, reset, enb_0x26, iw_reg_0x26, clk);
r_DEVICE_CAPABILITIES_2_HIGH reg_0x27(ow_reg_0x27, reset, enb_0x27, iw_reg_0x27, clk);
r_STANDARD_INPUT_CAPABILITIES reg_0x28(ow_reg_0x28, reset, enb_0x28, iw_reg_0x28, clk);
r_STANDARD_OUTPUT_CAPABILITIES reg_0x29(ow_reg_0x29, reset, enb_0x29, iw_reg_0x29, clk);
r_MESSAGE_HEADER_INFO reg_0x2E(ow_reg_0x2E, reset, enb_0x2E, iw_reg_0x2E, clk);
r_RECEIVE_DETECT reg_0x2F(ow_reg_0x2F, reset, enb_0x2F, iw_reg_0x2F, clk);
r_RECEIVE_BYTE_COUNT reg_0x30(ow_reg_0x30, reset, enb_0x30, iw_reg_0x30, clk);
r_RX_BUF_FRAME_TYPE reg_0x31(ow_reg_0x31, reset, enb_0x31, iw_reg_0x31, clk);
r_RX_BUF_HEADER_BYTE_0 reg_0x32(ow_reg_0x32, reset, enb_0x32, iw_reg_0x32, clk);
r_RX_BUF_HEADER_BYTE_1 reg_0x33(ow_reg_0x33, reset, enb_0x33, iw_reg_0x33, clk);
r_RX_BUF_OBJ1_BYTE_0 reg_0x34(ow_reg_0x34, reset, enb_0x34, iw_reg_0x34, clk);
r_RX_BUF_OBJ1_BYTE_1 reg_0x35(ow_reg_0x35, reset, enb_0x35, iw_reg_0x35, clk);
r_RX_BUF_OBJ1_BYTE_2 reg_0x36(ow_reg_0x36, reset, enb_0x36, iw_reg_0x36, clk);
r_RX_BUF_OBJ1_BYTE_3 reg_0x37(ow_reg_0x37, reset, enb_0x37, iw_reg_0x37, clk);
r_RX_BUF_OBJ2_BYTE_0 reg_0x38(ow_reg_0x38, reset, enb_0x38, iw_reg_0x38, clk);
r_RX_BUF_OBJ2_BYTE_1 reg_0x39(ow_reg_0x39, reset, enb_0x39, iw_reg_0x39, clk);
r_RX_BUF_OBJ2_BYTE_2 reg_0x3A(ow_reg_0x3A, reset, enb_0x3A, iw_reg_0x3A, clk);
r_RX_BUF_OBJ2_BYTE_3 reg_0x3B(ow_reg_0x3B, reset, enb_0x3B, iw_reg_0x3B, clk);
r_RX_BUF_OBJ3_BYTE_0 reg_0x3C(ow_reg_0x3C, reset, enb_0x3C, iw_reg_0x3C, clk);
r_RX_BUF_OBJ3_BYTE_1 reg_0x3D(ow_reg_0x3D, reset, enb_0x3D, iw_reg_0x3D, clk);
r_RX_BUF_OBJ3_BYTE_2 reg_0x3E(ow_reg_0x3E, reset, enb_0x3E, iw_reg_0x3E, clk);
r_RX_BUF_OBJ3_BYTE_3 reg_0x3F(ow_reg_0x3F, reset, enb_0x3F, iw_reg_0x3F, clk);
r_RX_BUF_OBJ4_BYTE_0 reg_0x40(ow_reg_0x40, reset, enb_0x40, iw_reg_0x40, clk);
r_RX_BUF_OBJ4_BYTE_1 reg_0x41(ow_reg_0x41, reset, enb_0x41, iw_reg_0x41, clk);
r_RX_BUF_OBJ4_BYTE_2 reg_0x42(ow_reg_0x42, reset, enb_0x42, iw_reg_0x42, clk);
r_RX_BUF_OBJ4_BYTE_3 reg_0x43(ow_reg_0x43, reset, enb_0x43, iw_reg_0x43, clk);
r_RX_BUF_OBJ5_BYTE_0 reg_0x44(ow_reg_0x44, reset, enb_0x44, iw_reg_0x44, clk);
r_RX_BUF_OBJ5_BYTE_1 reg_0x45(ow_reg_0x45, reset, enb_0x45, iw_reg_0x45, clk);
r_RX_BUF_OBJ5_BYTE_2 reg_0x46(ow_reg_0x46, reset, enb_0x46, iw_reg_0x46, clk);
r_RX_BUF_OBJ5_BYTE_3 reg_0x47(ow_reg_0x47, reset, enb_0x47, iw_reg_0x47, clk);
r_RX_BUF_OBJ6_BYTE_0 reg_0x48(ow_reg_0x48, reset, enb_0x48, iw_reg_0x48, clk);
r_RX_BUF_OBJ6_BYTE_1 reg_0x49(ow_reg_0x49, reset, enb_0x49, iw_reg_0x49, clk);
r_RX_BUF_OBJ6_BYTE_2 reg_0x4A(ow_reg_0x4A, reset, enb_0x4A, iw_reg_0x4A, clk);
r_RX_BUF_OBJ6_BYTE_3 reg_0x4B(ow_reg_0x4B, reset, enb_0x4B, iw_reg_0x4B, clk);
r_RX_BUF_OBJ7_BYTE_0 reg_0x4C(ow_reg_0x4C, reset, enb_0x4C, iw_reg_0x4C, clk);
r_RX_BUF_OBJ7_BYTE_1 reg_0x4D(ow_reg_0x4D, reset, enb_0x4D, iw_reg_0x4D, clk);
r_RX_BUF_OBJ7_BYTE_2 reg_0x4E(ow_reg_0x4E, reset, enb_0x4E, iw_reg_0x4E, clk);
r_RX_BUF_OBJ7_BYTE_3 reg_0x4F(ow_reg_0x4F, reset, enb_0x4F, iw_reg_0x4F, clk);
r_TRANSMIT reg_0x50(ow_reg_0x50, reset, enb_0x50, iw_reg_0x50, clk);
r_TRANSMIT_BYTE_COUNT reg_0x51(ow_reg_0x51, reset, enb_0x51, iw_reg_0x51, clk);
r_TX_BUF_HEADER_BYTE_0 reg_0x52(ow_reg_0x52, reset, enb_0x52, iw_reg_0x52, clk);
r_TX_BUF_HEADER_BYTE_1 reg_0x53(ow_reg_0x53, reset, enb_0x53, iw_reg_0x53, clk);
r_TX_BUF_OBJ1_BYTE_0 reg_0x54(ow_reg_0x54, reset, enb_0x54, iw_reg_0x54, clk);
r_TX_BUF_OBJ1_BYTE_1 reg_0x55(ow_reg_0x55, reset, enb_0x55, iw_reg_0x55, clk);
r_TX_BUF_OBJ1_BYTE_2 reg_0x56(ow_reg_0x56, reset, enb_0x56, iw_reg_0x56, clk);
r_TX_BUF_OBJ1_BYTE_3 reg_0x57(ow_reg_0x57, reset, enb_0x57, iw_reg_0x57, clk);
r_TX_BUF_OBJ2_BYTE_0 reg_0x58(ow_reg_0x58, reset, enb_0x58, iw_reg_0x58, clk);
r_TX_BUF_OBJ2_BYTE_1 reg_0x59(ow_reg_0x59, reset, enb_0x59, iw_reg_0x59, clk);
r_TX_BUF_OBJ2_BYTE_2 reg_0x5A(ow_reg_0x5A, reset, enb_0x5A, iw_reg_0x5A, clk);
r_TX_BUF_OBJ2_BYTE_3 reg_0x5B(ow_reg_0x5B, reset, enb_0x5B, iw_reg_0x5B, clk);
r_TX_BUF_OBJ3_BYTE_0 reg_0x5C(ow_reg_0x5C, reset, enb_0x5C, iw_reg_0x5C, clk);
r_TX_BUF_OBJ3_BYTE_1 reg_0x5D(ow_reg_0x5D, reset, enb_0x5D, iw_reg_0x5D, clk);
r_TX_BUF_OBJ3_BYTE_2 reg_0x5E(ow_reg_0x5E, reset, enb_0x5E, iw_reg_0x5E, clk);
r_TX_BUF_OBJ3_BYTE_3 reg_0x5F(ow_reg_0x5F, reset, enb_0x5F, iw_reg_0x5F, clk);
r_TX_BUF_OBJ4_BYTE_0 reg_0x60(ow_reg_0x60, reset, enb_0x60, iw_reg_0x60, clk);
r_TX_BUF_OBJ4_BYTE_1 reg_0x61(ow_reg_0x61, reset, enb_0x61, iw_reg_0x61, clk);
r_TX_BUF_OBJ4_BYTE_2 reg_0x62(ow_reg_0x62, reset, enb_0x62, iw_reg_0x62, clk);
r_TX_BUF_OBJ4_BYTE_3 reg_0x63(ow_reg_0x63, reset, enb_0x63, iw_reg_0x63, clk);
r_TX_BUF_OBJ5_BYTE_0 reg_0x64(ow_reg_0x64, reset, enb_0x64, iw_reg_0x64, clk);
r_TX_BUF_OBJ5_BYTE_1 reg_0x65(ow_reg_0x65, reset, enb_0x65, iw_reg_0x65, clk);
r_TX_BUF_OBJ5_BYTE_2 reg_0x66(ow_reg_0x66, reset, enb_0x66, iw_reg_0x66, clk);
r_TX_BUF_OBJ5_BYTE_3 reg_0x67(ow_reg_0x67, reset, enb_0x67, iw_reg_0x67, clk);
r_TX_BUF_OBJ6_BYTE_0 reg_0x68(ow_reg_0x68, reset, enb_0x68, iw_reg_0x68, clk);
r_TX_BUF_OBJ6_BYTE_1 reg_0x69(ow_reg_0x69, reset, enb_0x69, iw_reg_0x69, clk);
r_TX_BUF_OBJ6_BYTE_2 reg_0x6A(ow_reg_0x6A, reset, enb_0x6A, iw_reg_0x6A, clk);
r_TX_BUF_OBJ6_BYTE_3 reg_0x6B(ow_reg_0x6B, reset, enb_0x6B, iw_reg_0x6B, clk);
r_TX_BUF_OBJ7_BYTE_0 reg_0x6C(ow_reg_0x6C, reset, enb_0x6C, iw_reg_0x6C, clk);
r_TX_BUF_OBJ7_BYTE_1 reg_0x6D(ow_reg_0x6D, reset, enb_0x6D, iw_reg_0x6D, clk);
r_TX_BUF_OBJ7_BYTE_2 reg_0x6E(ow_reg_0x6E, reset, enb_0x6E, iw_reg_0x6E, clk);
r_TX_BUF_OBJ7_BYTE_3 reg_0x6F(ow_reg_0x6F, reset, enb_0x6F, iw_reg_0x6F, clk);
assign ow_od_transmit=ow_reg_0x50;
assign ow_od_TX_BUF_HEADER_BYTE_1=ow_reg_0x53;
assign ow_od_RX_BUF_HEADER_BYTE_1=ow_reg_0x33;
assign ow_od_RX_BUF_FRAME_TYPE=ow_reg_0x31;
REG_OUT_INTERFACE rout_int0(ow_od_0, r_address_0, ow_reg_0x00, ow_reg_0x01, ow_reg_0x02, ow_reg_0x03, ow_reg_0x04, ow_reg_0x05, ow_reg_0x06, ow_reg_0x07, ow_reg_0x08, ow_reg_0x09, ow_reg_0x0A, ow_reg_0x0B, ow_reg_0x10, ow_reg_0x11, ow_reg_0x12, ow_reg_0x13, ow_reg_0x14, ow_reg_0x15, ow_reg_0x18, ow_reg_0x19, ow_reg_0x1A, ow_reg_0x1B, ow_reg_0x1C, ow_reg_0x1D, ow_reg_0x1E, ow_reg_0x1F, ow_reg_0x23, ow_reg_0x24, ow_reg_0x25, ow_reg_0x26, ow_reg_0x27, ow_reg_0x28, ow_reg_0x29, ow_reg_0x2E, ow_reg_0x2F, ow_reg_0x30, ow_reg_0x31, ow_reg_0x32, ow_reg_0x33, ow_reg_0x34, ow_reg_0x35, ow_reg_0x36, ow_reg_0x37, ow_reg_0x38, ow_reg_0x39, ow_reg_0x3A, ow_reg_0x3B, ow_reg_0x3C, ow_reg_0x3D, ow_reg_0x3E, ow_reg_0x3F, ow_reg_0x40, ow_reg_0x41, ow_reg_0x42, ow_reg_0x43, ow_reg_0x44, ow_reg_0x45, ow_reg_0x46, ow_reg_0x47, ow_reg_0x48, ow_reg_0x49, ow_reg_0x4A, ow_reg_0x4B, ow_reg_0x4C, ow_reg_0x4D, ow_reg_0x4E, ow_reg_0x4F, ow_reg_0x50, ow_reg_0x51, ow_reg_0x52, ow_reg_0x53, ow_reg_0x54, ow_reg_0x55, ow_reg_0x56, ow_reg_0x57, ow_reg_0x58, ow_reg_0x59, ow_reg_0x5A, ow_reg_0x5B, ow_reg_0x5C, ow_reg_0x5D, ow_reg_0x5E, ow_reg_0x5F, ow_reg_0x60, ow_reg_0x61, ow_reg_0x62, ow_reg_0x63, ow_reg_0x64, ow_reg_0x65, ow_reg_0x66, ow_reg_0x67, ow_reg_0x68, ow_reg_0x69, ow_reg_0x6A, ow_reg_0x6B, ow_reg_0x6C, ow_reg_0x6D, ow_reg_0x6E, ow_reg_0x6F);
REG_OUT_INTERFACE rout_int1(ow_od_1, r_address_1, ow_reg_0x00, ow_reg_0x01, ow_reg_0x02, ow_reg_0x03, ow_reg_0x04, ow_reg_0x05, ow_reg_0x06, ow_reg_0x07, ow_reg_0x08, ow_reg_0x09, ow_reg_0x0A, ow_reg_0x0B, ow_reg_0x10, ow_reg_0x11, ow_reg_0x12, ow_reg_0x13, ow_reg_0x14, ow_reg_0x15, ow_reg_0x18, ow_reg_0x19, ow_reg_0x1A, ow_reg_0x1B, ow_reg_0x1C, ow_reg_0x1D, ow_reg_0x1E, ow_reg_0x1F, ow_reg_0x23, ow_reg_0x24, ow_reg_0x25, ow_reg_0x26, ow_reg_0x27, ow_reg_0x28, ow_reg_0x29, ow_reg_0x2E, ow_reg_0x2F, ow_reg_0x30, ow_reg_0x31, ow_reg_0x32, ow_reg_0x33, ow_reg_0x34, ow_reg_0x35, ow_reg_0x36, ow_reg_0x37, ow_reg_0x38, ow_reg_0x39, ow_reg_0x3A, ow_reg_0x3B, ow_reg_0x3C, ow_reg_0x3D, ow_reg_0x3E, ow_reg_0x3F, ow_reg_0x40, ow_reg_0x41, ow_reg_0x42, ow_reg_0x43, ow_reg_0x44, ow_reg_0x45, ow_reg_0x46, ow_reg_0x47, ow_reg_0x48, ow_reg_0x49, ow_reg_0x4A, ow_reg_0x4B, ow_reg_0x4C, ow_reg_0x4D, ow_reg_0x4E, ow_reg_0x4F, ow_reg_0x50, ow_reg_0x51, ow_reg_0x52, ow_reg_0x53, ow_reg_0x54, ow_reg_0x55, ow_reg_0x56, ow_reg_0x57, ow_reg_0x58, ow_reg_0x59, ow_reg_0x5A, ow_reg_0x5B, ow_reg_0x5C, ow_reg_0x5D, ow_reg_0x5E, ow_reg_0x5F, ow_reg_0x60, ow_reg_0x61, ow_reg_0x62, ow_reg_0x63, ow_reg_0x64, ow_reg_0x65, ow_reg_0x66, ow_reg_0x67, ow_reg_0x68, ow_reg_0x69, ow_reg_0x6A, ow_reg_0x6B, ow_reg_0x6C, ow_reg_0x6D, ow_reg_0x6E, ow_reg_0x6F);
REG_OUT_INTERFACE rout_int2(ow_od_2, r_address_2, ow_reg_0x00, ow_reg_0x01, ow_reg_0x02, ow_reg_0x03, ow_reg_0x04, ow_reg_0x05, ow_reg_0x06, ow_reg_0x07, ow_reg_0x08, ow_reg_0x09, ow_reg_0x0A, ow_reg_0x0B, ow_reg_0x10, ow_reg_0x11, ow_reg_0x12, ow_reg_0x13, ow_reg_0x14, ow_reg_0x15, ow_reg_0x18, ow_reg_0x19, ow_reg_0x1A, ow_reg_0x1B, ow_reg_0x1C, ow_reg_0x1D, ow_reg_0x1E, ow_reg_0x1F, ow_reg_0x23, ow_reg_0x24, ow_reg_0x25, ow_reg_0x26, ow_reg_0x27, ow_reg_0x28, ow_reg_0x29, ow_reg_0x2E, ow_reg_0x2F, ow_reg_0x30, ow_reg_0x31, ow_reg_0x32, ow_reg_0x33, ow_reg_0x34, ow_reg_0x35, ow_reg_0x36, ow_reg_0x37, ow_reg_0x38, ow_reg_0x39, ow_reg_0x3A, ow_reg_0x3B, ow_reg_0x3C, ow_reg_0x3D, ow_reg_0x3E, ow_reg_0x3F, ow_reg_0x40, ow_reg_0x41, ow_reg_0x42, ow_reg_0x43, ow_reg_0x44, ow_reg_0x45, ow_reg_0x46, ow_reg_0x47, ow_reg_0x48, ow_reg_0x49, ow_reg_0x4A, ow_reg_0x4B, ow_reg_0x4C, ow_reg_0x4D, ow_reg_0x4E, ow_reg_0x4F, ow_reg_0x50, ow_reg_0x51, ow_reg_0x52, ow_reg_0x53, ow_reg_0x54, ow_reg_0x55, ow_reg_0x56, ow_reg_0x57, ow_reg_0x58, ow_reg_0x59, ow_reg_0x5A, ow_reg_0x5B, ow_reg_0x5C, ow_reg_0x5D, ow_reg_0x5E, ow_reg_0x5F, ow_reg_0x60, ow_reg_0x61, ow_reg_0x62, ow_reg_0x63, ow_reg_0x64, ow_reg_0x65, ow_reg_0x66, ow_reg_0x67, ow_reg_0x68, ow_reg_0x69, ow_reg_0x6A, ow_reg_0x6B, ow_reg_0x6C, ow_reg_0x6D, ow_reg_0x6E, ow_reg_0x6F);
REG_IN_INTERFACE rin_int0(ow_i0_id_0x10, ow_i0_id_0x11, ow_i0_id_0x12, ow_i0_id_0x13, ow_i0_id_0x14, ow_i0_id_0x15, ow_i0_id_0x18, ow_i0_id_0x19, ow_i0_id_0x1A, ow_i0_id_0x1B, ow_i0_id_0x1C, ow_i0_id_0x1D, ow_i0_id_0x1E, ow_i0_id_0x1F, ow_i0_id_0x23, ow_i0_id_0x24, ow_i0_id_0x25, ow_i0_id_0x26, ow_i0_id_0x27, ow_i0_id_0x28, ow_i0_id_0x29, ow_i0_id_0x2E, ow_i0_id_0x2F, ow_i0_id_0x30, ow_i0_id_0x31, ow_i0_id_0x32, ow_i0_id_0x33, ow_i0_id_0x34, ow_i0_id_0x35, ow_i0_id_0x36, ow_i0_id_0x37, ow_i0_id_0x38, ow_i0_id_0x39, ow_i0_id_0x3A, ow_i0_id_0x3B, ow_i0_id_0x3C, ow_i0_id_0x3D, ow_i0_id_0x3E, ow_i0_id_0x3F, ow_i0_id_0x40, ow_i0_id_0x41, ow_i0_id_0x42, ow_i0_id_0x43, ow_i0_id_0x44, ow_i0_id_0x45, ow_i0_id_0x46, ow_i0_id_0x47, ow_i0_id_0x48, ow_i0_id_0x49, ow_i0_id_0x4A, ow_i0_id_0x4B, ow_i0_id_0x4C, ow_i0_id_0x4D, ow_i0_id_0x4E, ow_i0_id_0x4F, ow_i0_id_0x50, ow_i0_id_0x51, ow_i0_id_0x52, ow_i0_id_0x53, ow_i0_id_0x54, ow_i0_id_0x55, ow_i0_id_0x56, ow_i0_id_0x57, ow_i0_id_0x58, ow_i0_id_0x59, ow_i0_id_0x5A, ow_i0_id_0x5B, ow_i0_id_0x5C, ow_i0_id_0x5D, ow_i0_id_0x5E, ow_i0_id_0x5F, ow_i0_id_0x60, ow_i0_id_0x61, ow_i0_id_0x62, ow_i0_id_0x63, ow_i0_id_0x64, ow_i0_id_0x65, ow_i0_id_0x66, ow_i0_id_0x67, ow_i0_id_0x68, ow_i0_id_0x69, ow_i0_id_0x6A, ow_i0_id_0x6B, ow_i0_id_0x6C, ow_i0_id_0x6D, ow_i0_id_0x6E, ow_i0_id_0x6F, ow_i0_enb_0x10, ow_i0_enb_0x11, ow_i0_enb_0x12, ow_i0_enb_0x13, ow_i0_enb_0x14, ow_i0_enb_0x15, ow_i0_enb_0x18, ow_i0_enb_0x19, ow_i0_enb_0x1A, ow_i0_enb_0x1B, ow_i0_enb_0x1C, ow_i0_enb_0x1D, ow_i0_enb_0x1E, ow_i0_enb_0x1F, ow_i0_enb_0x23, ow_i0_enb_0x24, ow_i0_enb_0x25, ow_i0_enb_0x26, ow_i0_enb_0x27, ow_i0_enb_0x28, ow_i0_enb_0x29, ow_i0_enb_0x2E, ow_i0_enb_0x2F, ow_i0_enb_0x30, ow_i0_enb_0x31, ow_i0_enb_0x32, ow_i0_enb_0x33, ow_i0_enb_0x34, ow_i0_enb_0x35, ow_i0_enb_0x36, ow_i0_enb_0x37, ow_i0_enb_0x38, ow_i0_enb_0x39, ow_i0_enb_0x3A, ow_i0_enb_0x3B, ow_i0_enb_0x3C, ow_i0_enb_0x3D, ow_i0_enb_0x3E, ow_i0_enb_0x3F, ow_i0_enb_0x40, ow_i0_enb_0x41, ow_i0_enb_0x42, ow_i0_enb_0x43, ow_i0_enb_0x44, ow_i0_enb_0x45, ow_i0_enb_0x46, ow_i0_enb_0x47, ow_i0_enb_0x48, ow_i0_enb_0x49, ow_i0_enb_0x4A, ow_i0_enb_0x4B, ow_i0_enb_0x4C, ow_i0_enb_0x4D, ow_i0_enb_0x4E, ow_i0_enb_0x4F, ow_i0_enb_0x50, ow_i0_enb_0x51, ow_i0_enb_0x52, ow_i0_enb_0x53, ow_i0_enb_0x54, ow_i0_enb_0x55, ow_i0_enb_0x56, ow_i0_enb_0x57, ow_i0_enb_0x58, ow_i0_enb_0x59, ow_i0_enb_0x5A, ow_i0_enb_0x5B, ow_i0_enb_0x5C, ow_i0_enb_0x5D, ow_i0_enb_0x5E, ow_i0_enb_0x5F, ow_i0_enb_0x60, ow_i0_enb_0x61, ow_i0_enb_0x62, ow_i0_enb_0x63, ow_i0_enb_0x64, ow_i0_enb_0x65, ow_i0_enb_0x66, ow_i0_enb_0x67, ow_i0_enb_0x68, ow_i0_enb_0x69, ow_i0_enb_0x6A, ow_i0_enb_0x6B, ow_i0_enb_0x6C, ow_i0_enb_0x6D, ow_i0_enb_0x6E, ow_i0_enb_0x6F, r_address_0, iw_id_0, iw_enb_0);
REG_IN_INTERFACE rin_int1(ow_i1_id_0x10, ow_i1_id_0x11, ow_i1_id_0x12, ow_i1_id_0x13, ow_i1_id_0x14, ow_i1_id_0x15, ow_i1_id_0x18, ow_i1_id_0x19, ow_i1_id_0x1A, ow_i1_id_0x1B, ow_i1_id_0x1C, ow_i1_id_0x1D, ow_i1_id_0x1E, ow_i1_id_0x1F, ow_i1_id_0x23, ow_i1_id_0x24, ow_i1_id_0x25, ow_i1_id_0x26, ow_i1_id_0x27, ow_i1_id_0x28, ow_i1_id_0x29, ow_i1_id_0x2E, ow_i1_id_0x2F, ow_i1_id_0x30, ow_i1_id_0x31, ow_i1_id_0x32, ow_i1_id_0x33, ow_i1_id_0x34, ow_i1_id_0x35, ow_i1_id_0x36, ow_i1_id_0x37, ow_i1_id_0x38, ow_i1_id_0x39, ow_i1_id_0x3A, ow_i1_id_0x3B, ow_i1_id_0x3C, ow_i1_id_0x3D, ow_i1_id_0x3E, ow_i1_id_0x3F, ow_i1_id_0x40, ow_i1_id_0x41, ow_i1_id_0x42, ow_i1_id_0x43, ow_i1_id_0x44, ow_i1_id_0x45, ow_i1_id_0x46, ow_i1_id_0x47, ow_i1_id_0x48, ow_i1_id_0x49, ow_i1_id_0x4A, ow_i1_id_0x4B, ow_i1_id_0x4C, ow_i1_id_0x4D, ow_i1_id_0x4E, ow_i1_id_0x4F, ow_i1_id_0x50, ow_i1_id_0x51, ow_i1_id_0x52, ow_i1_id_0x53, ow_i1_id_0x54, ow_i1_id_0x55, ow_i1_id_0x56, ow_i1_id_0x57, ow_i1_id_0x58, ow_i1_id_0x59, ow_i1_id_0x5A, ow_i1_id_0x5B, ow_i1_id_0x5C, ow_i1_id_0x5D, ow_i1_id_0x5E, ow_i1_id_0x5F, ow_i1_id_0x60, ow_i1_id_0x61, ow_i1_id_0x62, ow_i1_id_0x63, ow_i1_id_0x64, ow_i1_id_0x65, ow_i1_id_0x66, ow_i1_id_0x67, ow_i1_id_0x68, ow_i1_id_0x69, ow_i1_id_0x6A, ow_i1_id_0x6B, ow_i1_id_0x6C, ow_i1_id_0x6D, ow_i1_id_0x6E, ow_i1_id_0x6F, ow_i1_enb_0x10, ow_i1_enb_0x11, ow_i1_enb_0x12, ow_i1_enb_0x13, ow_i1_enb_0x14, ow_i1_enb_0x15, ow_i1_enb_0x18, ow_i1_enb_0x19, ow_i1_enb_0x1A, ow_i1_enb_0x1B, ow_i1_enb_0x1C, ow_i1_enb_0x1D, ow_i1_enb_0x1E, ow_i1_enb_0x1F, ow_i1_enb_0x23, ow_i1_enb_0x24, ow_i1_enb_0x25, ow_i1_enb_0x26, ow_i1_enb_0x27, ow_i1_enb_0x28, ow_i1_enb_0x29, ow_i1_enb_0x2E, ow_i1_enb_0x2F, ow_i1_enb_0x30, ow_i1_enb_0x31, ow_i1_enb_0x32, ow_i1_enb_0x33, ow_i1_enb_0x34, ow_i1_enb_0x35, ow_i1_enb_0x36, ow_i1_enb_0x37, ow_i1_enb_0x38, ow_i1_enb_0x39, ow_i1_enb_0x3A, ow_i1_enb_0x3B, ow_i1_enb_0x3C, ow_i1_enb_0x3D, ow_i1_enb_0x3E, ow_i1_enb_0x3F, ow_i1_enb_0x40, ow_i1_enb_0x41, ow_i1_enb_0x42, ow_i1_enb_0x43, ow_i1_enb_0x44, ow_i1_enb_0x45, ow_i1_enb_0x46, ow_i1_enb_0x47, ow_i1_enb_0x48, ow_i1_enb_0x49, ow_i1_enb_0x4A, ow_i1_enb_0x4B, ow_i1_enb_0x4C, ow_i1_enb_0x4D, ow_i1_enb_0x4E, ow_i1_enb_0x4F, ow_i1_enb_0x50, ow_i1_enb_0x51, ow_i1_enb_0x52, ow_i1_enb_0x53, ow_i1_enb_0x54, ow_i1_enb_0x55, ow_i1_enb_0x56, ow_i1_enb_0x57, ow_i1_enb_0x58, ow_i1_enb_0x59, ow_i1_enb_0x5A, ow_i1_enb_0x5B, ow_i1_enb_0x5C, ow_i1_enb_0x5D, ow_i1_enb_0x5E, ow_i1_enb_0x5F, ow_i1_enb_0x60, ow_i1_enb_0x61, ow_i1_enb_0x62, ow_i1_enb_0x63, ow_i1_enb_0x64, ow_i1_enb_0x65, ow_i1_enb_0x66, ow_i1_enb_0x67, ow_i1_enb_0x68, ow_i1_enb_0x69, ow_i1_enb_0x6A, ow_i1_enb_0x6B, ow_i1_enb_0x6C, ow_i1_enb_0x6D, ow_i1_enb_0x6E, ow_i1_enb_0x6F, r_address_1, iw_id_1, iw_enb_1);
REG_IN_INTERFACE rin_int2(ow_i2_id_0x10, ow_i2_id_0x11, ow_i2_id_0x12, ow_i2_id_0x13, ow_i2_id_0x14, ow_i2_id_0x15, ow_i2_id_0x18, ow_i2_id_0x19, ow_i2_id_0x1A, ow_i2_id_0x1B, ow_i2_id_0x1C, ow_i2_id_0x1D, ow_i2_id_0x1E, ow_i2_id_0x1F, ow_i2_id_0x23, ow_i2_id_0x24, ow_i2_id_0x25, ow_i2_id_0x26, ow_i2_id_0x27, ow_i2_id_0x28, ow_i2_id_0x29, ow_i2_id_0x2E, ow_i2_id_0x2F, ow_i2_id_0x30, ow_i2_id_0x31, ow_i2_id_0x32, ow_i2_id_0x33, ow_i2_id_0x34, ow_i2_id_0x35, ow_i2_id_0x36, ow_i2_id_0x37, ow_i2_id_0x38, ow_i2_id_0x39, ow_i2_id_0x3A, ow_i2_id_0x3B, ow_i2_id_0x3C, ow_i2_id_0x3D, ow_i2_id_0x3E, ow_i2_id_0x3F, ow_i2_id_0x40, ow_i2_id_0x41, ow_i2_id_0x42, ow_i2_id_0x43, ow_i2_id_0x44, ow_i2_id_0x45, ow_i2_id_0x46, ow_i2_id_0x47, ow_i2_id_0x48, ow_i2_id_0x49, ow_i2_id_0x4A, ow_i2_id_0x4B, ow_i2_id_0x4C, ow_i2_id_0x4D, ow_i2_id_0x4E, ow_i2_id_0x4F, ow_i2_id_0x50, ow_i2_id_0x51, ow_i2_id_0x52, ow_i2_id_0x53, ow_i2_id_0x54, ow_i2_id_0x55, ow_i2_id_0x56, ow_i2_id_0x57, ow_i2_id_0x58, ow_i2_id_0x59, ow_i2_id_0x5A, ow_i2_id_0x5B, ow_i2_id_0x5C, ow_i2_id_0x5D, ow_i2_id_0x5E, ow_i2_id_0x5F, ow_i2_id_0x60, ow_i2_id_0x61, ow_i2_id_0x62, ow_i2_id_0x63, ow_i2_id_0x64, ow_i2_id_0x65, ow_i2_id_0x66, ow_i2_id_0x67, ow_i2_id_0x68, ow_i2_id_0x69, ow_i2_id_0x6A, ow_i2_id_0x6B, ow_i2_id_0x6C, ow_i2_id_0x6D, ow_i2_id_0x6E, ow_i2_id_0x6F, ow_i2_enb_0x10, ow_i2_enb_0x11, ow_i2_enb_0x12, ow_i2_enb_0x13, ow_i2_enb_0x14, ow_i2_enb_0x15, ow_i2_enb_0x18, ow_i2_enb_0x19, ow_i2_enb_0x1A, ow_i2_enb_0x1B, ow_i2_enb_0x1C, ow_i2_enb_0x1D, ow_i2_enb_0x1E, ow_i2_enb_0x1F, ow_i2_enb_0x23, ow_i2_enb_0x24, ow_i2_enb_0x25, ow_i2_enb_0x26, ow_i2_enb_0x27, ow_i2_enb_0x28, ow_i2_enb_0x29, ow_i2_enb_0x2E, ow_i2_enb_0x2F, ow_i2_enb_0x30, ow_i2_enb_0x31, ow_i2_enb_0x32, ow_i2_enb_0x33, ow_i2_enb_0x34, ow_i2_enb_0x35, ow_i2_enb_0x36, ow_i2_enb_0x37, ow_i2_enb_0x38, ow_i2_enb_0x39, ow_i2_enb_0x3A, ow_i2_enb_0x3B, ow_i2_enb_0x3C, ow_i2_enb_0x3D, ow_i2_enb_0x3E, ow_i2_enb_0x3F, ow_i2_enb_0x40, ow_i2_enb_0x41, ow_i2_enb_0x42, ow_i2_enb_0x43, ow_i2_enb_0x44, ow_i2_enb_0x45, ow_i2_enb_0x46, ow_i2_enb_0x47, ow_i2_enb_0x48, ow_i2_enb_0x49, ow_i2_enb_0x4A, ow_i2_enb_0x4B, ow_i2_enb_0x4C, ow_i2_enb_0x4D, ow_i2_enb_0x4E, ow_i2_enb_0x4F, ow_i2_enb_0x50, ow_i2_enb_0x51, ow_i2_enb_0x52, ow_i2_enb_0x53, ow_i2_enb_0x54, ow_i2_enb_0x55, ow_i2_enb_0x56, ow_i2_enb_0x57, ow_i2_enb_0x58, ow_i2_enb_0x59, ow_i2_enb_0x5A, ow_i2_enb_0x5B, ow_i2_enb_0x5C, ow_i2_enb_0x5D, ow_i2_enb_0x5E, ow_i2_enb_0x5F, ow_i2_enb_0x60, ow_i2_enb_0x61, ow_i2_enb_0x62, ow_i2_enb_0x63, ow_i2_enb_0x64, ow_i2_enb_0x65, ow_i2_enb_0x66, ow_i2_enb_0x67, ow_i2_enb_0x68, ow_i2_enb_0x69, ow_i2_enb_0x6A, ow_i2_enb_0x6B, ow_i2_enb_0x6C, ow_i2_enb_0x6D, ow_i2_enb_0x6E, ow_i2_enb_0x6F, r_address_2, iw_id_2, iw_enb_2);
assign iw_reg_0x10=ow_i0_id_0x10+ow_i1_id_0x10+ow_i2_id_0x10;
assign enb_0x10=ow_i0_enb_0x10+ow_i1_enb_0x10+ow_i2_enb_0x10;
assign iw_reg_0x11=ow_i0_id_0x11+ow_i1_id_0x11+ow_i2_id_0x11;
assign enb_0x11=ow_i0_enb_0x11+ow_i1_enb_0x11+ow_i2_enb_0x11;
assign iw_reg_0x12=ow_i0_id_0x12+ow_i1_id_0x12+ow_i2_id_0x12;
assign enb_0x12=ow_i0_enb_0x12+ow_i1_enb_0x12+ow_i2_enb_0x12;
assign iw_reg_0x13=ow_i0_id_0x13+ow_i1_id_0x13+ow_i2_id_0x13;
assign enb_0x13=ow_i0_enb_0x13+ow_i1_enb_0x13+ow_i2_enb_0x13;
assign iw_reg_0x14=ow_i0_id_0x14+ow_i1_id_0x14+ow_i2_id_0x14;
assign enb_0x14=ow_i0_enb_0x14+ow_i1_enb_0x14+ow_i2_enb_0x14;
assign iw_reg_0x15=ow_i0_id_0x15+ow_i1_id_0x15+ow_i2_id_0x15;
assign enb_0x15=ow_i0_enb_0x15+ow_i1_enb_0x15+ow_i2_enb_0x15;
assign iw_reg_0x18=ow_i0_id_0x18+ow_i1_id_0x18+ow_i2_id_0x18;
assign enb_0x18=ow_i0_enb_0x18+ow_i1_enb_0x18+ow_i2_enb_0x18;
assign iw_reg_0x19=ow_i0_id_0x19+ow_i1_id_0x19+ow_i2_id_0x19;
assign enb_0x19=ow_i0_enb_0x19+ow_i1_enb_0x19+ow_i2_enb_0x19;
assign iw_reg_0x1A=ow_i0_id_0x1A+ow_i1_id_0x1A+ow_i2_id_0x1A;
assign enb_0x1A=ow_i0_enb_0x1A+ow_i1_enb_0x1A+ow_i2_enb_0x1A;
assign iw_reg_0x1B=ow_i0_id_0x1B+ow_i1_id_0x1B+ow_i2_id_0x1B;
assign enb_0x1B=ow_i0_enb_0x1B+ow_i1_enb_0x1B+ow_i2_enb_0x1B;
assign iw_reg_0x1C=ow_i0_id_0x1C+ow_i1_id_0x1C+ow_i2_id_0x1C;
assign enb_0x1C=ow_i0_enb_0x1C+ow_i1_enb_0x1C+ow_i2_enb_0x1C;
assign iw_reg_0x1D=ow_i0_id_0x1D+ow_i1_id_0x1D+ow_i2_id_0x1D;
assign enb_0x1D=ow_i0_enb_0x1D+ow_i1_enb_0x1D+ow_i2_enb_0x1D;
assign iw_reg_0x1E=ow_i0_id_0x1E+ow_i1_id_0x1E+ow_i2_id_0x1E;
assign enb_0x1E=ow_i0_enb_0x1E+ow_i1_enb_0x1E+ow_i2_enb_0x1E;
assign iw_reg_0x1F=ow_i0_id_0x1F+ow_i1_id_0x1F+ow_i2_id_0x1F;
assign enb_0x1F=ow_i0_enb_0x1F+ow_i1_enb_0x1F+ow_i2_enb_0x1F;
assign iw_reg_0x23=ow_i0_id_0x23+ow_i1_id_0x23+ow_i2_id_0x23;
assign enb_0x23=ow_i0_enb_0x23+ow_i1_enb_0x23+ow_i2_enb_0x23;
assign iw_reg_0x24=ow_i0_id_0x24+ow_i1_id_0x24+ow_i2_id_0x24;
assign enb_0x24=ow_i0_enb_0x24+ow_i1_enb_0x24+ow_i2_enb_0x24;
assign iw_reg_0x25=ow_i0_id_0x25+ow_i1_id_0x25+ow_i2_id_0x25;
assign enb_0x25=ow_i0_enb_0x25+ow_i1_enb_0x25+ow_i2_enb_0x25;
assign iw_reg_0x26=ow_i0_id_0x26+ow_i1_id_0x26+ow_i2_id_0x26;
assign enb_0x26=ow_i0_enb_0x26+ow_i1_enb_0x26+ow_i2_enb_0x26;
assign iw_reg_0x27=ow_i0_id_0x27+ow_i1_id_0x27+ow_i2_id_0x27;
assign enb_0x27=ow_i0_enb_0x27+ow_i1_enb_0x27+ow_i2_enb_0x27;
assign iw_reg_0x28=ow_i0_id_0x28+ow_i1_id_0x28+ow_i2_id_0x28;
assign enb_0x28=ow_i0_enb_0x28+ow_i1_enb_0x28+ow_i2_enb_0x28;
assign iw_reg_0x29=ow_i0_id_0x29+ow_i1_id_0x29+ow_i2_id_0x29;
assign enb_0x29=ow_i0_enb_0x29+ow_i1_enb_0x29+ow_i2_enb_0x29;
assign iw_reg_0x2E=ow_i0_id_0x2E+ow_i1_id_0x2E+ow_i2_id_0x2E;
assign enb_0x2E=ow_i0_enb_0x2E+ow_i1_enb_0x2E+ow_i2_enb_0x2E;
assign iw_reg_0x2F=ow_i0_id_0x2F+ow_i1_id_0x2F+ow_i2_id_0x2F;
assign enb_0x2F=ow_i0_enb_0x2F+ow_i1_enb_0x2F+ow_i2_enb_0x2F;
assign iw_reg_0x30=ow_i0_id_0x30+ow_i1_id_0x30+ow_i2_id_0x30;
assign enb_0x30=ow_i0_enb_0x30+ow_i1_enb_0x30+ow_i2_enb_0x30;
assign iw_reg_0x31=ow_i0_id_0x31+ow_i1_id_0x31+ow_i2_id_0x31;
assign enb_0x31=ow_i0_enb_0x31+ow_i1_enb_0x31+ow_i2_enb_0x31;
assign iw_reg_0x32=ow_i0_id_0x32+ow_i1_id_0x32+ow_i2_id_0x32;
assign enb_0x32=ow_i0_enb_0x32+ow_i1_enb_0x32+ow_i2_enb_0x32;
assign iw_reg_0x33=ow_i0_id_0x33+ow_i1_id_0x33+ow_i2_id_0x33;
assign enb_0x33=ow_i0_enb_0x33+ow_i1_enb_0x33+ow_i2_enb_0x33;
assign iw_reg_0x34=ow_i0_id_0x34+ow_i1_id_0x34+ow_i2_id_0x34;
assign enb_0x34=ow_i0_enb_0x34+ow_i1_enb_0x34+ow_i2_enb_0x34;
assign iw_reg_0x35=ow_i0_id_0x35+ow_i1_id_0x35+ow_i2_id_0x35;
assign enb_0x35=ow_i0_enb_0x35+ow_i1_enb_0x35+ow_i2_enb_0x35;
assign iw_reg_0x36=ow_i0_id_0x36+ow_i1_id_0x36+ow_i2_id_0x36;
assign enb_0x36=ow_i0_enb_0x36+ow_i1_enb_0x36+ow_i2_enb_0x36;
assign iw_reg_0x37=ow_i0_id_0x37+ow_i1_id_0x37+ow_i2_id_0x37;
assign enb_0x37=ow_i0_enb_0x37+ow_i1_enb_0x37+ow_i2_enb_0x37;
assign iw_reg_0x38=ow_i0_id_0x38+ow_i1_id_0x38+ow_i2_id_0x38;
assign enb_0x38=ow_i0_enb_0x38+ow_i1_enb_0x38+ow_i2_enb_0x38;
assign iw_reg_0x39=ow_i0_id_0x39+ow_i1_id_0x39+ow_i2_id_0x39;
assign enb_0x39=ow_i0_enb_0x39+ow_i1_enb_0x39+ow_i2_enb_0x39;
assign iw_reg_0x3A=ow_i0_id_0x3A+ow_i1_id_0x3A+ow_i2_id_0x3A;
assign enb_0x3A=ow_i0_enb_0x3A+ow_i1_enb_0x3A+ow_i2_enb_0x3A;
assign iw_reg_0x3B=ow_i0_id_0x3B+ow_i1_id_0x3B+ow_i2_id_0x3B;
assign enb_0x3B=ow_i0_enb_0x3B+ow_i1_enb_0x3B+ow_i2_enb_0x3B;
assign iw_reg_0x3C=ow_i0_id_0x3C+ow_i1_id_0x3C+ow_i2_id_0x3C;
assign enb_0x3C=ow_i0_enb_0x3C+ow_i1_enb_0x3C+ow_i2_enb_0x3C;
assign iw_reg_0x3D=ow_i0_id_0x3D+ow_i1_id_0x3D+ow_i2_id_0x3D;
assign enb_0x3D=ow_i0_enb_0x3D+ow_i1_enb_0x3D+ow_i2_enb_0x3D;
assign iw_reg_0x3E=ow_i0_id_0x3E+ow_i1_id_0x3E+ow_i2_id_0x3E;
assign enb_0x3E=ow_i0_enb_0x3E+ow_i1_enb_0x3E+ow_i2_enb_0x3E;
assign iw_reg_0x3F=ow_i0_id_0x3F+ow_i1_id_0x3F+ow_i2_id_0x3F;
assign enb_0x3F=ow_i0_enb_0x3F+ow_i1_enb_0x3F+ow_i2_enb_0x3F;
assign iw_reg_0x40=ow_i0_id_0x40+ow_i1_id_0x40+ow_i2_id_0x40;
assign enb_0x40=ow_i0_enb_0x40+ow_i1_enb_0x40+ow_i2_enb_0x40;
assign iw_reg_0x41=ow_i0_id_0x41+ow_i1_id_0x41+ow_i2_id_0x41;
assign enb_0x41=ow_i0_enb_0x41+ow_i1_enb_0x41+ow_i2_enb_0x41;
assign iw_reg_0x42=ow_i0_id_0x42+ow_i1_id_0x42+ow_i2_id_0x42;
assign enb_0x42=ow_i0_enb_0x42+ow_i1_enb_0x42+ow_i2_enb_0x42;
assign iw_reg_0x43=ow_i0_id_0x43+ow_i1_id_0x43+ow_i2_id_0x43;
assign enb_0x43=ow_i0_enb_0x43+ow_i1_enb_0x43+ow_i2_enb_0x43;
assign iw_reg_0x44=ow_i0_id_0x44+ow_i1_id_0x44+ow_i2_id_0x44;
assign enb_0x44=ow_i0_enb_0x44+ow_i1_enb_0x44+ow_i2_enb_0x44;
assign iw_reg_0x45=ow_i0_id_0x45+ow_i1_id_0x45+ow_i2_id_0x45;
assign enb_0x45=ow_i0_enb_0x45+ow_i1_enb_0x45+ow_i2_enb_0x45;
assign iw_reg_0x46=ow_i0_id_0x46+ow_i1_id_0x46+ow_i2_id_0x46;
assign enb_0x46=ow_i0_enb_0x46+ow_i1_enb_0x46+ow_i2_enb_0x46;
assign iw_reg_0x47=ow_i0_id_0x47+ow_i1_id_0x47+ow_i2_id_0x47;
assign enb_0x47=ow_i0_enb_0x47+ow_i1_enb_0x47+ow_i2_enb_0x47;
assign iw_reg_0x48=ow_i0_id_0x48+ow_i1_id_0x48+ow_i2_id_0x48;
assign enb_0x48=ow_i0_enb_0x48+ow_i1_enb_0x48+ow_i2_enb_0x48;
assign iw_reg_0x49=ow_i0_id_0x49+ow_i1_id_0x49+ow_i2_id_0x49;
assign enb_0x49=ow_i0_enb_0x49+ow_i1_enb_0x49+ow_i2_enb_0x49;
assign iw_reg_0x4A=ow_i0_id_0x4A+ow_i1_id_0x4A+ow_i2_id_0x4A;
assign enb_0x4A=ow_i0_enb_0x4A+ow_i1_enb_0x4A+ow_i2_enb_0x4A;
assign iw_reg_0x4B=ow_i0_id_0x4B+ow_i1_id_0x4B+ow_i2_id_0x4B;
assign enb_0x4B=ow_i0_enb_0x4B+ow_i1_enb_0x4B+ow_i2_enb_0x4B;
assign iw_reg_0x4C=ow_i0_id_0x4C+ow_i1_id_0x4C+ow_i2_id_0x4C;
assign enb_0x4C=ow_i0_enb_0x4C+ow_i1_enb_0x4C+ow_i2_enb_0x4C;
assign iw_reg_0x4D=ow_i0_id_0x4D+ow_i1_id_0x4D+ow_i2_id_0x4D;
assign enb_0x4D=ow_i0_enb_0x4D+ow_i1_enb_0x4D+ow_i2_enb_0x4D;
assign iw_reg_0x4E=ow_i0_id_0x4E+ow_i1_id_0x4E+ow_i2_id_0x4E;
assign enb_0x4E=ow_i0_enb_0x4E+ow_i1_enb_0x4E+ow_i2_enb_0x4E;
assign iw_reg_0x4F=ow_i0_id_0x4F+ow_i1_id_0x4F+ow_i2_id_0x4F;
assign enb_0x4F=ow_i0_enb_0x4F+ow_i1_enb_0x4F+ow_i2_enb_0x4F;
assign iw_reg_0x50=ow_i0_id_0x50+ow_i1_id_0x50+ow_i2_id_0x50;
assign enb_0x50=ow_i0_enb_0x50+ow_i1_enb_0x50+ow_i2_enb_0x50;
assign iw_reg_0x51=ow_i0_id_0x51+ow_i1_id_0x51+ow_i2_id_0x51;
assign enb_0x51=ow_i0_enb_0x51+ow_i1_enb_0x51+ow_i2_enb_0x51;
assign iw_reg_0x52=ow_i0_id_0x52+ow_i1_id_0x52+ow_i2_id_0x52;
assign enb_0x52=ow_i0_enb_0x52+ow_i1_enb_0x52+ow_i2_enb_0x52;
assign iw_reg_0x53=ow_i0_id_0x53+ow_i1_id_0x53+ow_i2_id_0x53;
assign enb_0x53=ow_i0_enb_0x53+ow_i1_enb_0x53+ow_i2_enb_0x53;
assign iw_reg_0x54=ow_i0_id_0x54+ow_i1_id_0x54+ow_i2_id_0x54;
assign enb_0x54=ow_i0_enb_0x54+ow_i1_enb_0x54+ow_i2_enb_0x54;
assign iw_reg_0x55=ow_i0_id_0x55+ow_i1_id_0x55+ow_i2_id_0x55;
assign enb_0x55=ow_i0_enb_0x55+ow_i1_enb_0x55+ow_i2_enb_0x55;
assign iw_reg_0x56=ow_i0_id_0x56+ow_i1_id_0x56+ow_i2_id_0x56;
assign enb_0x56=ow_i0_enb_0x56+ow_i1_enb_0x56+ow_i2_enb_0x56;
assign iw_reg_0x57=ow_i0_id_0x57+ow_i1_id_0x57+ow_i2_id_0x57;
assign enb_0x57=ow_i0_enb_0x57+ow_i1_enb_0x57+ow_i2_enb_0x57;
assign iw_reg_0x58=ow_i0_id_0x58+ow_i1_id_0x58+ow_i2_id_0x58;
assign enb_0x58=ow_i0_enb_0x58+ow_i1_enb_0x58+ow_i2_enb_0x58;
assign iw_reg_0x59=ow_i0_id_0x59+ow_i1_id_0x59+ow_i2_id_0x59;
assign enb_0x59=ow_i0_enb_0x59+ow_i1_enb_0x59+ow_i2_enb_0x59;
assign iw_reg_0x5A=ow_i0_id_0x5A+ow_i1_id_0x5A+ow_i2_id_0x5A;
assign enb_0x5A=ow_i0_enb_0x5A+ow_i1_enb_0x5A+ow_i2_enb_0x5A;
assign iw_reg_0x5B=ow_i0_id_0x5B+ow_i1_id_0x5B+ow_i2_id_0x5B;
assign enb_0x5B=ow_i0_enb_0x5B+ow_i1_enb_0x5B+ow_i2_enb_0x5B;
assign iw_reg_0x5C=ow_i0_id_0x5C+ow_i1_id_0x5C+ow_i2_id_0x5C;
assign enb_0x5C=ow_i0_enb_0x5C+ow_i1_enb_0x5C+ow_i2_enb_0x5C;
assign iw_reg_0x5D=ow_i0_id_0x5D+ow_i1_id_0x5D+ow_i2_id_0x5D;
assign enb_0x5D=ow_i0_enb_0x5D+ow_i1_enb_0x5D+ow_i2_enb_0x5D;
assign iw_reg_0x5E=ow_i0_id_0x5E+ow_i1_id_0x5E+ow_i2_id_0x5E;
assign enb_0x5E=ow_i0_enb_0x5E+ow_i1_enb_0x5E+ow_i2_enb_0x5E;
assign iw_reg_0x5F=ow_i0_id_0x5F+ow_i1_id_0x5F+ow_i2_id_0x5F;
assign enb_0x5F=ow_i0_enb_0x5F+ow_i1_enb_0x5F+ow_i2_enb_0x5F;
assign iw_reg_0x60=ow_i0_id_0x60+ow_i1_id_0x60+ow_i2_id_0x60;
assign enb_0x60=ow_i0_enb_0x60+ow_i1_enb_0x60+ow_i2_enb_0x60;
assign iw_reg_0x61=ow_i0_id_0x61+ow_i1_id_0x61+ow_i2_id_0x61;
assign enb_0x61=ow_i0_enb_0x61+ow_i1_enb_0x61+ow_i2_enb_0x61;
assign iw_reg_0x62=ow_i0_id_0x62+ow_i1_id_0x62+ow_i2_id_0x62;
assign enb_0x62=ow_i0_enb_0x62+ow_i1_enb_0x62+ow_i2_enb_0x62;
assign iw_reg_0x63=ow_i0_id_0x63+ow_i1_id_0x63+ow_i2_id_0x63;
assign enb_0x63=ow_i0_enb_0x63+ow_i1_enb_0x63+ow_i2_enb_0x63;
assign iw_reg_0x64=ow_i0_id_0x64+ow_i1_id_0x64+ow_i2_id_0x64;
assign enb_0x64=ow_i0_enb_0x64+ow_i1_enb_0x64+ow_i2_enb_0x64;
assign iw_reg_0x65=ow_i0_id_0x65+ow_i1_id_0x65+ow_i2_id_0x65;
assign enb_0x65=ow_i0_enb_0x65+ow_i1_enb_0x65+ow_i2_enb_0x65;
assign iw_reg_0x66=ow_i0_id_0x66+ow_i1_id_0x66+ow_i2_id_0x66;
assign enb_0x66=ow_i0_enb_0x66+ow_i1_enb_0x66+ow_i2_enb_0x66;
assign iw_reg_0x67=ow_i0_id_0x67+ow_i1_id_0x67+ow_i2_id_0x67;
assign enb_0x67=ow_i0_enb_0x67+ow_i1_enb_0x67+ow_i2_enb_0x67;
assign iw_reg_0x68=ow_i0_id_0x68+ow_i1_id_0x68+ow_i2_id_0x68;
assign enb_0x68=ow_i0_enb_0x68+ow_i1_enb_0x68+ow_i2_enb_0x68;
assign iw_reg_0x69=ow_i0_id_0x69+ow_i1_id_0x69+ow_i2_id_0x69;
assign enb_0x69=ow_i0_enb_0x69+ow_i1_enb_0x69+ow_i2_enb_0x69;
assign iw_reg_0x6A=ow_i0_id_0x6A+ow_i1_id_0x6A+ow_i2_id_0x6A;
assign enb_0x6A=ow_i0_enb_0x6A+ow_i1_enb_0x6A+ow_i2_enb_0x6A;
assign iw_reg_0x6B=ow_i0_id_0x6B+ow_i1_id_0x6B+ow_i2_id_0x6B;
assign enb_0x6B=ow_i0_enb_0x6B+ow_i1_enb_0x6B+ow_i2_enb_0x6B;
assign iw_reg_0x6C=ow_i0_id_0x6C+ow_i1_id_0x6C+ow_i2_id_0x6C;
assign enb_0x6C=ow_i0_enb_0x6C+ow_i1_enb_0x6C+ow_i2_enb_0x6C;
assign iw_reg_0x6D=ow_i0_id_0x6D+ow_i1_id_0x6D+ow_i2_id_0x6D;
assign enb_0x6D=ow_i0_enb_0x6D+ow_i1_enb_0x6D+ow_i2_enb_0x6D;
assign iw_reg_0x6E=ow_i0_id_0x6E+ow_i1_id_0x6E+ow_i2_id_0x6E;
assign enb_0x6E=ow_i0_enb_0x6E+ow_i1_enb_0x6E+ow_i2_enb_0x6E;
assign iw_reg_0x6F=ow_i0_id_0x6F+ow_i1_id_0x6F+ow_i2_id_0x6F;
assign enb_0x6F=ow_i0_enb_0x6F+ow_i1_enb_0x6F+ow_i2_enb_0x6F;
endmodule |
module simuart(input wire clk,
input wire cs,
input wire [31:0] bus_addr,
input wire [31:0] bus_wr_val,
input wire [3:0] bus_bytesel,
output reg bus_ack,
output reg [31:0] bus_data,
output reg inter,
input wire intack
);
task write_data;
begin
$uart_put(bus_wr_val[7:0]);
end
endtask
task read_data;
begin
$uart_get(uart_buf);
end
endtask
reg [8:0] uart_buf = 9'b0;
wire uart_rdy = uart_buf[8];
wire [31:0] status_reg = (uart_rdy ? 32'b10 : 32'b0);
reg ff;
reg ffold;
initial begin
bus_ack = 1'b0;
bus_data = 32'b0;
inter = 1'b0;
end
always @(posedge clk) begin
bus_data <= 32'b0;
ff <= 1'b0;
ffold <= 1'b0;
if (~uart_rdy && ~cs)
read_data();
ff<=ffold;
if (uart_rdy && (uart_buf[7:0]==8'h3)) begin
if(intack==1'b0) begin
inter <=1'b1;
end else begin
uart_buf[8]<=1'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4'b0001) begin
if (bus_addr[3:0] == 4'b0000) begin
write_data();
end
if (bus_addr[3:0] == 4'b1000) begin
inter<=1'b0;
end
end else if (cs) begin
if (bus_addr[3:0] == 4'b0000) begin
bus_data <= {24'b0, uart_buf[7:0]};
ff <= 1'b1;
if (ff && ~ffold) uart_buf[8] <= 1'b0;
end else if (bus_addr[3:0] == 4'b0100) begin
/* Status register read. */
bus_data <= status_reg;
end
end
end
bus_ack <= cs;
end
endmodule |
module ascii (
input scan_ready,
input [7:0] scan_code,
output [7:0] ascii
);
// @todo: shift, alt etc
reg [7:0] r_ascii;
assign ascii = r_ascii;
reg keyup = 0;
always @(posedge scan_ready) begin
if (scan_code == 8'hf0) begin
keyup <= 1;
end else begin
if (keyup) begin
keyup <= 0;
r_ascii <= 8'd0;
end else
case (scan_code)
8'h29: r_ascii <= 8'd32; // [space]
8'h45: r_ascii <= 8'd48; // 0
8'h16: r_ascii <= 8'd49; // 1
8'h1e: r_ascii <= 8'd50; // 2
8'h26: r_ascii <= 8'd51; // 3
8'h25: r_ascii <= 8'd52; // 4
8'h2e: r_ascii <= 8'd53; // 5
8'h36: r_ascii <= 8'd54; // 6
8'h3d: r_ascii <= 8'd55; // 7
8'h3e: r_ascii <= 8'd56; // 8
8'h46: r_ascii <= 8'd57; // 9
8'h1c: r_ascii <= 8'd97; // a
8'h32: r_ascii <= 8'd98; // b
8'h21: r_ascii <= 8'd99; // c
8'h23: r_ascii <= 8'd100; // d
8'h24: r_ascii <= 8'd101; // e
8'h2b: r_ascii <= 8'd102; // f
8'h34: r_ascii <= 8'd103; // g
8'h33: r_ascii <= 8'd104; // h
8'h43: r_ascii <= 8'd105; // i
8'h3b: r_ascii <= 8'd106; // j
8'h42: r_ascii <= 8'd107; // k
8'h4b: r_ascii <= 8'd108; // l
8'h3a: r_ascii <= 8'd109; // m
8'h31: r_ascii <= 8'd110; // n
8'h44: r_ascii <= 8'd111; // o
8'h4d: r_ascii <= 8'd112; // p
8'h15: r_ascii <= 8'd113; // q
8'h2d: r_ascii <= 8'd114; // r
8'h1b: r_ascii <= 8'd115; // s
8'h2c: r_ascii <= 8'd116; // t
8'h3c: r_ascii <= 8'd117; // u
8'h2a: r_ascii <= 8'd118; // v
8'h1d: r_ascii <= 8'd119; // w
8'h22: r_ascii <= 8'd120; // x
8'h35: r_ascii <= 8'd121; // y
8'h1a: r_ascii <= 8'd122; // z
default: r_ascii <= 8'd0; // nothing
endcase
end
end
endmodule |
module data_access
#(
parameter B=32, // ancho de la direccion
parameter W=5 //ancho de
)
(
input wire clk,
/*Data signals input*/
input wire [B-1:0] addr_in,
input wire [B-1:0] write_data,
/*Control signals input*/
input wire [5:0] opcode,
input wire mem_write,
//input wire mem_read,
//input wire zero,
//input wire branch_in,
//input wire branchNot_in,
/*Data signals output*/
output wire [B-1:0] data_out
/*Control signals output*/
//output wire pcSrc_out
);
wire [3:0] we;
assign we[3]=mem_write;
assign we[2]=mem_write;
assign we[1]=mem_write;
assign we[0]=mem_write;
//Manejo de los "store"
wire [B-1:0] sb;
wire [B-1:0] sh;
sig_extend #(8) sb_sign
(
.reg_in(write_data[7:0]),
.reg_out(sb)
);
sig_extend sh_sign
(
.reg_in(write_data[15:0]),
.reg_out(sh)
);
wire [B-1:0] write_data_mem;
mux4 mux_store
(
.sel(opcode[1:0]),
.item_a(sb),
.item_b(sh),
.item_c(),
.item_d(write_data),
.signal(write_data_mem)
);
wire [B-1:0] data_mem;
dataMemory dm( .clka(~clk),
.rsta(1'b0),
.ena(1'b1),
.wea(we),
.addra(addr_in),
.dina(write_data_mem),
.douta(data_mem));
//Manejo de los "load"
wire [B-1:0] lb;
wire [B-1:0] lh;
wire [B-1:0] lbu;
wire [B-1:0] lhu;
wire [B-1:0] l;
wire [B-1:0] lu;
sig_extend #(8) lb_sign
(
.reg_in(data_mem[7:0]),
.reg_out(lb)
);
sig_extend lh_sign
(
.reg_in(data_mem[15:0]),
.reg_out(lh)
);
assign lbu = {{(24){1'b0}}, data_mem[7:0]};
assign lhu = {{(16){1'b0}}, data_mem[15:0]};
mux4 mux_l
(
.sel(opcode[1:0]),
.item_a(lb),
.item_b(lh),
.item_c(),
.item_d(data_mem),
.signal(l)
);
mux4 mux_lu
(
.sel(opcode[1:0]),
.item_a(lbu),
.item_b(lhu),
.item_c(),
.item_d(data_mem),
.signal(lu)
);
mux mux_data_out
(
.select(opcode[2]),
.item_a(l),
.item_b(lu),
.signal(data_out)
);
/*
//Manejo de beq y bne
wire and1;
assign and1 = branch_in && zero;
wire and2;
assign and2 = branchNot_in && (~zero);
assign pcSrc_out = and1 || and2;
*/
endmodule |
module sfifo_12x16_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [11:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [11:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [11:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [11:0] q = sub_wire3[11:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 12,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hdll__tapvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule |
module main_0(output_rs232_tx_ack,clk,rst,output_rs232_tx,output_rs232_tx_stb,exception);
integer file_count;
parameter stop = 3'd0,
instruction_fetch = 3'd1,
operand_fetch = 3'd2,
execute = 3'd3,
load = 3'd4,
wait_state = 3'd5,
read = 3'd6,
write = 3'd7;
input output_rs232_tx_ack;
input clk;
input rst;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
reg [31:0] timer;
reg [63:0] timer_clock;
reg [15:0] program_counter;
reg [15:0] program_counter_1;
reg [15:0] program_counter_2;
reg [43:0] instruction;
reg [3:0] opcode_2;
reg [3:0] a;
reg [3:0] b;
reg [3:0] z;
reg write_enable;
reg [3:0] address_a_2;
reg [3:0] address_b_2;
reg [3:0] address_z_2;
reg [3:0] address_z_3;
reg [31:0] load_data;
reg [31:0] write_output;
reg [31:0] write_value;
reg [31:0] read_input;
reg [15:0] literal_2;
reg [31:0] a_hi;
reg [31:0] b_hi;
reg [31:0] a_lo;
reg [31:0] b_lo;
reg [63:0] long_result;
reg [31:0] result;
reg [15:0] address;
reg [31:0] data_out;
reg [31:0] data_in;
reg [31:0] carry;
reg [31:0] s_output_rs232_tx_stb;
reg [31:0] s_output_rs232_tx;
reg [7:0] state;
output reg exception;
reg [27:0] instructions [165:0];
reg [31:0] memory [4096:0];
reg [31:0] registers [15:0];
wire [31:0] operand_a;
wire [31:0] operand_b;
wire [31:0] register_a;
wire [31:0] register_b;
wire [15:0] literal;
wire [3:0] opcode;
wire [3:0] address_a;
wire [3:0] address_b;
wire [3:0] address_z;
wire [15:0] load_address;
wire [15:0] store_address;
wire [31:0] store_data;
wire store_enable;
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'literal': True, 'op': 'literal'}
// 1 {'literal': True, 'op': 'addl'}
// 2 {'literal': False, 'op': 'store'}
// 3 {'literal': True, 'op': 'call'}
// 4 {'literal': False, 'op': 'stop'}
// 5 {'literal': False, 'op': 'load'}
// 6 {'literal': False, 'op': 'return'}
// 7 {'literal': False, 'op': 'add'}
// 8 {'literal': True, 'op': 'jmp_if_false'}
// 9 {'literal': False, 'op': 'write'}
// 10 {'literal': True, 'op': 'goto'}
// Intructions
// ===========
initial
begin
instructions[0] = {4'd0, 4'd3, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'literal': 0, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'literal'}
instructions[1] = {4'd0, 4'd4, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'literal': 0, 'z': 4, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'literal'}
instructions[2] = {4'd1, 4'd3, 4'd3, 16'd16};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'a': 3, 'literal': 16, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'addl'}
instructions[3] = {4'd0, 4'd8, 4'd0, 16'd72};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 72, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[4] = {4'd0, 4'd2, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 0, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[5] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[6] = {4'd0, 4'd8, 4'd0, 16'd101};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 101, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[7] = {4'd0, 4'd2, 4'd0, 16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 1, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[8] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[9] = {4'd0, 4'd8, 4'd0, 16'd108};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 108, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[10] = {4'd0, 4'd2, 4'd0, 16'd2};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 2, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[11] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[12] = {4'd0, 4'd8, 4'd0, 16'd108};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 108, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[13] = {4'd0, 4'd2, 4'd0, 16'd3};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 3, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[14] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[15] = {4'd0, 4'd8, 4'd0, 16'd111};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 111, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[16] = {4'd0, 4'd2, 4'd0, 16'd4};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 4, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[17] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[18] = {4'd0, 4'd8, 4'd0, 16'd32};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 32, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[19] = {4'd0, 4'd2, 4'd0, 16'd5};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 5, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[20] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[21] = {4'd0, 4'd8, 4'd0, 16'd87};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 87, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[22] = {4'd0, 4'd2, 4'd0, 16'd6};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 6, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[23] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[24] = {4'd0, 4'd8, 4'd0, 16'd111};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 111, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[25] = {4'd0, 4'd2, 4'd0, 16'd7};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 7, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[26] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[27] = {4'd0, 4'd8, 4'd0, 16'd114};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 114, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[28] = {4'd0, 4'd2, 4'd0, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 8, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[29] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[30] = {4'd0, 4'd8, 4'd0, 16'd108};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 108, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[31] = {4'd0, 4'd2, 4'd0, 16'd9};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 9, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[32] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[33] = {4'd0, 4'd8, 4'd0, 16'd100};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 100, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[34] = {4'd0, 4'd2, 4'd0, 16'd10};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 10, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[35] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[36] = {4'd0, 4'd8, 4'd0, 16'd33};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 33, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[37] = {4'd0, 4'd2, 4'd0, 16'd11};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 11, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[38] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[39] = {4'd0, 4'd8, 4'd0, 16'd10};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 10, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[40] = {4'd0, 4'd2, 4'd0, 16'd12};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 12, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[41] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[42] = {4'd0, 4'd8, 4'd0, 16'd32};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 32, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[43] = {4'd0, 4'd2, 4'd0, 16'd13};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 13, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[44] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[45] = {4'd0, 4'd8, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 0, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[46] = {4'd0, 4'd2, 4'd0, 16'd14};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 14, 'z': 2, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[47] = {4'd2, 4'd0, 4'd2, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'a': 2, 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'store'}
instructions[48] = {4'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'literal'}
instructions[49] = {4'd0, 4'd2, 4'd0, 16'd15};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'literal': 15, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'literal'}
instructions[50] = {4'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'store'}
instructions[51] = {4'd1, 4'd7, 4'd4, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'a': 4, 'literal': 0, 'z': 7, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'addl'}
instructions[52] = {4'd1, 4'd4, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'a': 3, 'literal': 0, 'z': 4, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'addl'}
instructions[53] = {4'd3, 4'd6, 4'd0, 16'd55};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'z': 6, 'label': 55, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'call'}
instructions[54] = {4'd4, 4'd0, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 8 {'trace': /tmp/tmpEtvNgA/inline_c_file.c : 8, 'op': 'stop'}
instructions[55] = {4'd1, 4'd3, 4'd3, 16'd15};///tmp/tmpEtvNgA/inline_c_file.c : 4 {'a': 3, 'literal': 15, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 4, 'op': 'addl'}
instructions[56] = {4'd2, 4'd0, 4'd3, 16'd6};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'store'}
instructions[57] = {4'd1, 4'd3, 4'd3, 16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 1, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[58] = {4'd2, 4'd0, 4'd3, 16'd7};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'store'}
instructions[59] = {4'd1, 4'd3, 4'd3, 16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 1, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[60] = {4'd0, 4'd8, 4'd0, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 6 {'literal': 0, 'z': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 6, 'op': 'literal'}
instructions[61] = {4'd2, 4'd0, 4'd3, 16'd8};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'store'}
instructions[62] = {4'd1, 4'd3, 4'd3, 16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 1, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[63] = {4'd1, 4'd7, 4'd4, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 4, 'literal': 0, 'z': 7, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[64] = {4'd1, 4'd4, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 0, 'z': 4, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[65] = {4'd3, 4'd6, 4'd0, 16'd75};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'z': 6, 'label': 75, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'call'}
instructions[66] = {4'd1, 4'd3, 4'd3, -16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': -1, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[67] = {4'd1, 4'd3, 4'd3, -16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'pop', 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[68] = {4'd5, 4'd7, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'z': 7, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'load'}
instructions[69] = {4'd1, 4'd3, 4'd3, -16'd1};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'comment': 'pop', 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[70] = {4'd5, 4'd6, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'z': 6, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'load'}
instructions[71] = {4'd1, 4'd3, 4'd3, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 5 {'a': 3, 'literal': 0, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 5, 'op': 'addl'}
instructions[72] = {4'd1, 4'd3, 4'd4, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 4 {'a': 4, 'literal': 0, 'z': 3, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 4, 'op': 'addl'}
instructions[73] = {4'd1, 4'd4, 4'd7, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 4 {'a': 7, 'literal': 0, 'z': 4, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 4, 'op': 'addl'}
instructions[74] = {4'd6, 4'd0, 4'd6, 16'd0};///tmp/tmpEtvNgA/inline_c_file.c : 4 {'a': 6, 'trace': /tmp/tmpEtvNgA/inline_c_file.c : 4, 'op': 'return'}
instructions[75] = {4'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[76] = {4'd2, 4'd0, 4'd3, 16'd6};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[77] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[78] = {4'd2, 4'd0, 4'd3, 16'd7};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[79] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[80] = {4'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[81] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[82] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[83] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[84] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[85] = {4'd0, 4'd8, 4'd0, 16'd15};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'literal': 15, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'literal'}
instructions[86] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[87] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[88] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[89] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[90] = {4'd1, 4'd7, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 4, 'literal': 0, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[91] = {4'd1, 4'd4, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[92] = {4'd3, 4'd6, 4'd0, 16'd102};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'z': 6, 'label': 102, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'call'}
instructions[93] = {4'd1, 4'd3, 4'd3, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': -2, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[94] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[95] = {4'd5, 4'd7, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[96] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[97] = {4'd5, 4'd6, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'z': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[98] = {4'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[99] = {4'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[100] = {4'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[101] = {4'd6, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'return'}
instructions[102] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[103] = {4'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'literal'}
instructions[104] = {4'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'addl'}
instructions[105] = {4'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'store'}
instructions[106] = {4'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[107] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[108] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[109] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'store'}
instructions[110] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[111] = {4'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[112] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[113] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[114] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[115] = {4'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[116] = {4'd7, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'add'}
instructions[117] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[118] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[119] = {4'd8, 4'd0, 4'd8, 16'd161};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'a': 8, 'label': 161, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'jmp_if_false'}
instructions[120] = {4'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[121] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[122] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[123] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'store'}
instructions[124] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[125] = {4'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[126] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[127] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[128] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'store'}
instructions[129] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[130] = {4'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[131] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[132] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[133] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[134] = {4'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[135] = {4'd7, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'add'}
instructions[136] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[137] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[138] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[139] = {4'd5, 4'd0, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'z': 0, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[140] = {4'd9, 4'd0, 4'd0, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 0, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'write'}
instructions[141] = {4'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[142] = {4'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[143] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[144] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[145] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[146] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[147] = {4'd0, 4'd8, 4'd0, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'literal': 1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'literal'}
instructions[148] = {4'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[149] = {4'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[150] = {4'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[151] = {4'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[152] = {4'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[153] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[154] = {4'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[155] = {4'd7, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'add'}
instructions[156] = {4'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[157] = {4'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[158] = {4'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[159] = {4'd5, 4'd8, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[160] = {4'd10, 4'd0, 4'd0, 16'd162};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'label': 162, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'goto'}
instructions[161] = {4'd10, 4'd0, 4'd0, 16'd163};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'label': 163, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'goto'}
instructions[162] = {4'd10, 4'd0, 4'd0, 16'd106};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'label': 106, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'goto'}
instructions[163] = {4'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[164] = {4'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[165] = {4'd6, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'return'}
end
always @(posedge clk)
begin
load_data <= memory[load_address];
if(store_enable && state == execute) begin
memory[store_address] <= store_data;
end
end
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 1 -- FETCH INSTRUCTION
//
always @(posedge clk)
begin
//implement memory for instructions
if (state == instruction_fetch || state == operand_fetch || state == execute) begin
instruction <= instructions[program_counter];
program_counter_1 <= program_counter;
end
end
assign opcode = instruction[27:24];
assign address_z = instruction[23:20];
assign address_a = instruction[19:16];
assign address_b = instruction[3:0];
assign literal = instruction[15:0];
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 2 -- FETCH OPERANDS
//
always @(posedge clk)
begin
if (write_enable) begin
registers[address_z_3] <= result;
end
if (state == operand_fetch || state == execute) begin
opcode_2 <= opcode;
literal_2 <= literal;
address_a_2 <= address_a;
address_b_2 <= address_b;
address_z_2 <= address_z;
program_counter_2 <= program_counter_1;
end
end
assign register_a = registers[address_a_2];
assign register_b = registers[address_b_2];
assign operand_a = (address_a_2 == address_z_3 && write_enable)?result:register_a;
assign operand_b = (address_b_2 == address_z_3 && write_enable)?result:register_b;
assign store_address = operand_a;
assign load_address = operand_a;
assign store_data = operand_b;
assign store_enable = (opcode_2==2);
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 3 -- EXECUTE
//
always @(posedge clk)
begin
write_enable <= 0;
timer_clock <= timer_clock + 1;
case(state)
//instruction_fetch
instruction_fetch: begin
program_counter <= program_counter + 1;
state <= operand_fetch;
end
//operand_fetch
operand_fetch: begin
program_counter <= program_counter + 1;
state <= execute;
end
//execute
execute: begin
program_counter <= program_counter + 1;
address_z_3 <= address_z_2;
case(opcode_2)
//literal
16'd0:
begin
result<=$signed(literal_2);
write_enable <= 1;
end
//addl
16'd1:
begin
result<=operand_a + literal_2;
write_enable <= 1;
end
//store
16'd2:
begin
end
//call
16'd3:
begin
result <= program_counter_2 + 1;
write_enable <= 1;
program_counter <= literal_2;
state <= instruction_fetch;
end
//stop
16'd4:
begin
state <= stop;
end
//load
16'd5:
begin
state <= load;
end
//return
16'd6:
begin
program_counter <= operand_a;
state <= instruction_fetch;
end
//add
16'd7:
begin
long_result = operand_a + operand_b;
result <= long_result[31:0];
carry[0] <= long_result[32];
write_enable <= 1;
end
//jmp_if_false
16'd8:
begin
if (operand_a == 0) begin
program_counter <= literal_2;
state <= instruction_fetch;
end
end
//write
16'd9:
begin
state <= write;
write_output <= operand_a;
write_value <= operand_b;
end
//goto
16'd10:
begin
program_counter <= literal_2;
state <= instruction_fetch;
end
endcase
end
write:
begin
case(write_output)
0:
begin
s_output_rs232_tx_stb <= 1;
s_output_rs232_tx <= write_value;
if (output_rs232_tx_ack && s_output_rs232_tx_stb) begin
s_output_rs232_tx_stb <= 0;
state <= execute;
end
end
endcase
end
load:
begin
result <= load_data;
write_enable <= 1;
state <= execute;
end
wait_state:
begin
if (timer) begin
timer <= timer - 1;
end else begin
state <= execute;
end
end
stop:
begin
end
endcase
if (rst == 1'b1) begin
timer <= 0;
timer_clock <= 0;
program_counter <= 0;
address_z_3 <= 0;
result <= 0;
a = 0;
b = 0;
z = 0;
state <= instruction_fetch;
s_output_rs232_tx_stb <= 0;
end
end
assign output_rs232_tx_stb = s_output_rs232_tx_stb;
assign output_rs232_tx = s_output_rs232_tx;
endmodule |
module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
function integer round_up2;
input integer N;
begin
round_up2 = ((N + 1) / 2) * 2;
end
endfunction
localparam Y_WIDTH2 = round_up2(Y_WIDTH);
(* force_downto *)
wire [Y_WIDTH2-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] BX = B_buf;
(* force_downto *)
wire [Y_WIDTH2-1:0] C = {CO, CI};
(* force_downto *)
wire [Y_WIDTH2-1:0] FCO, Y1;
genvar i;
generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
CCU2C #(
.INIT0(16'b1001011010101010),
.INIT1(16'b1001011010101010),
.INJECT1_0("NO"),
.INJECT1_1("NO")
) ccu2c_i (
.CIN(C[i]),
.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
.S0(Y[i]), .S1(Y1[i]),
.COUT(FCO[i])
);
assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
if (i+1 < Y_WIDTH) begin
assign CO[i+1] = FCO[i];
assign Y[i+1] = Y1[i];
end
end endgenerate
assign X = AA ^ BB;
endmodule |
module DemoInterconnect_uart_transceiver_0_0(i_Clk, i_RX_Serial, o_RX_Done, o_RX_Byte,
i_TX_Load, i_TX_Byte, o_TX_Active, o_TX_Serial, o_TX_Done)
/* synthesis syn_black_box black_box_pad_pin="i_Clk,i_RX_Serial,o_RX_Done,o_RX_Byte[7:0],i_TX_Load,i_TX_Byte[7:0],o_TX_Active,o_TX_Serial,o_TX_Done" */;
input i_Clk;
input i_RX_Serial;
output o_RX_Done;
output [7:0]o_RX_Byte;
input i_TX_Load;
input [7:0]i_TX_Byte;
output o_TX_Active;
output o_TX_Serial;
output o_TX_Done;
endmodule |
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule |
module TOP;
reg l0, l1, re;
wire le, r0, r1;
DELAY #(.delay(`inv_delay)) d0(l0, r0);
DELAY #(.delay(`inv_delay)) d1(l1, r1);
DELAY #(.delay(`inv_delay)) de(re, le);
// prsim stuff
initial
begin
// @haco@ channel-source-sink.haco-c
$prsim_options("-I subdir");
$prsim("channel-source-sink.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("echo-commands on");
// $prsim_cmd("addpath subdir");
$from_prsim("L.d[0]","TOP.l0");
$from_prsim("L.d[1]","TOP.l1");
$to_prsim("TOP.le", "L.e");
$to_prsim("TOP.r0", "R.d[0]");
$to_prsim("TOP.r1", "R.d[1]");
$from_prsim("R.e", "TOP.re");
$prsim_cmd("breaks");
$prsim_cmd("watchall");
// $prsim_cmd("watchall-queue");
$prsim_cmd("channel L e:0 :0 d:2");
$prsim_cmd("channel R e:1 :0 d:2");
$prsim_cmd("channel-source-file-loop L channel-values-X.txt");
$prsim_cmd("channel-sink R");
$prsim_cmd("channel-watchall");
$prsim_cmd("channel-reset-all");
$prsim_cmd("channel-show-all");
$prsim_cmd("breaks");
end
initial #5 $prsim_cmd("channel-release-all");
initial #5 $prsim_cmd("channel-show-all");
initial #6 $prsim_cmd("nowatchall");
initial #9 $prsim_cmd("why-not-verbose R.e");
initial #9 $prsim_cmd("why-not-verbose R.d[0]");
initial #10 $finish;
/**
initial
$monitor("@%7.3f: l = %d,%d:%d; r = %d,%d:%d", $realtime,
l0, l1, le, r0, r1, re);
**/
endmodule |
module foc_cmd
(input c,
input udp_cmd_dv,
input [31:0] udp_target_reg,
input [31:0] udp_damping_reg,
input udp_foc_active_reg,
input [31:0] temperature,
input [31:0] temperature_limit,
input ignore_temperature,
input overtemp_rst,
input [7:0] submsg_rxd,
input submsg_rxdv,
input submsg_rxlast,
output [31:0] foc_target,
output [31:0] foc_damping,
output [31:0] control_id,
output foc_active,
output float);
wire [7:0] foc_cmd_rx_control_mode;
wire [31:0] foc_cmd_rx_control_id;
wire [31:0] foc_cmd_rx_target;
wire [31:0] foc_cmd_rx_damping; // = 32'hbf80_0000;
wire foc_cmd_rx_rx;
foc_cmd_rx foc_cmd_rx_inst
(.c(c),
.submsg_rxd(submsg_rxd), .submsg_rxdv(submsg_rxdv),
.submsg_rxlast(submsg_rxlast),
.control_mode(foc_cmd_rx_control_mode),
.control_id(control_id),
.target(foc_cmd_rx_target),
.damping(foc_cmd_rx_damping),
.cmd_rx(foc_cmd_rx_rx));
wire last_cmd_from_foc_cmd;
r last_cmd_from_foc_cmd_r
(.c(c), .d(1'b1), .q(last_cmd_from_foc_cmd),
.rst(udp_cmd_dv), .en(foc_cmd_rx_rx));
wire udp_cmd_dv_d1, udp_cmd_dv_d2;
d1 udp_cmd_dv_d1_r(.c(c), .d(udp_cmd_dv), .q(udp_cmd_dv_d1));
d1 udp_cmd_dv_d2_r(.c(c), .d(udp_cmd_dv_d1), .q(udp_cmd_dv_d2));
localparam [31:0] HARD_OVERTEMP_LIMIT = 32'h42d2_0000; // 105.0 celsius
wire hard_overtemp;
fp_compare hard_overtemp_compare_r
(.clock(c), .ageb(hard_overtemp),
.dataa(temperature),
.datab(HARD_OVERTEMP_LIMIT));
wire soft_overtemp_ageb;
wire soft_overtemp = soft_overtemp_ageb & |temperature_limit;
fp_compare soft_overtemp_compare_r
(.clock(c), .ageb(soft_overtemp_ageb),
.dataa(temperature),
.datab(temperature_limit));
wire [23:0] overtemp_cnt;
r #(24) overtemp_cnt_r
(.c(c), .rst(ignore_temperature), .en(1'b1),
.d((hard_overtemp | soft_overtemp) ? overtemp_cnt + 1'b1 :
(|overtemp_cnt ? overtemp_cnt - 1'b1 : overtemp_cnt)),
.q(overtemp_cnt));
`ifdef SIM
localparam TARGET_TIMEOUT = 24'd100_000; // 1 ms
localparam ZERO_TIMEOUT = 24'd001_000;
localparam OVERTEMP_TIMEOUT = 24'd000_100;
`else
localparam TARGET_TIMEOUT = 24'd10_000_000; // 100ms timeout
localparam ZERO_TIMEOUT = 24'd10_000_000; // command zero amps for 100ms
localparam OVERTEMP_TIMEOUT = 24'd01_000_000; // 10ms overtemp timeout
`endif
localparam ST_IDLE = 4'd0;
localparam ST_RUNNING = 4'd1;
localparam ST_DRIVE_ZERO = 4'd2;
localparam ST_OVERTEMP = 4'd3;
localparam SW=4, CW=4;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire state_cnt_rst = ctrl[0];
wire [17:0] state_cnt;
r #(18) state_cnt_r
(.c(c), .rst(state_cnt_rst), .en(1'b1), .d(state_cnt+1'b1), .q(state_cnt));
always @* begin
case (state)
ST_IDLE:
if (udp_cmd_dv_d2 | foc_cmd_rx_rx) ctrl = { ST_RUNNING , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0000 };
ST_RUNNING:
if (overtemp_cnt > OVERTEMP_TIMEOUT) ctrl = { ST_DRIVE_ZERO, 4'b0010 };
else if (timeout) ctrl = { ST_DRIVE_ZERO, 4'b0001 };
else ctrl = { ST_RUNNING , 4'b0000 };
ST_DRIVE_ZERO:
if ((udp_cmd_dv_d2 | foc_cmd_rx_rx) &
~overtemp_latch) ctrl = { ST_RUNNING , 4'b0000 };
else if (state_cnt == ZERO_TIMEOUT)
if (overtemp_latch) ctrl = { ST_OVERTEMP , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0000 };
else ctrl = { ST_DRIVE_ZERO, 4'b0000 };
ST_OVERTEMP:
if (~overtemp_latch) ctrl = { ST_IDLE , 4'b0000 };
else ctrl = { ST_OVERTEMP , 4'b0000 };
default: ctrl = { ST_IDLE , 4'b0000 };
endcase
end
wire overtemp_latch;
r overtemp_latch_r
(.c(c), .rst(overtemp_rst), .en(ctrl[1]), .d(1'b1), .q(overtemp_latch));
wire [23:0] timeout_cnt;
r #(24) timeout_cnt_r
(.c(c), .rst(udp_cmd_dv | foc_cmd_rx_rx), .en(1'b1),
.d(timeout_cnt+1'b1), .q(timeout_cnt));
wire timeout = timeout_cnt == TARGET_TIMEOUT;
wire [31:0] next_foc_target;
d1 #(32) next_foc_target_r
(.c(c), .d(last_cmd_from_foc_cmd ? foc_cmd_rx_target : udp_target_reg),
.q(next_foc_target));
wire [31:0] next_foc_damping;
d1 #(32) next_foc_damping_r
(.c(c), .d(last_cmd_from_foc_cmd ? foc_cmd_rx_damping : udp_damping_reg),
.q(next_foc_damping));
r #(32) foc_target_r
(.c(c), .rst(1'b0), .en(1'b1),
.d(state == ST_RUNNING ? next_foc_target : 32'h0), .q(foc_target));
r #(32) foc_damping_r
(.c(c), .rst(1'b0), .en(1'b1),
.d(state == ST_RUNNING ? next_foc_damping : 32'h0), .q(foc_damping));
//assign foc_damping = foc_cmd_rx_damping;
assign float = state == ST_IDLE | state == ST_OVERTEMP;
assign foc_active = udp_foc_active_reg &
(state == ST_RUNNING |
state == ST_DRIVE_ZERO);
endmodule |
module LCD_Display(iCLK_50MHZ, iRST_N, state_code,
LCD_RS,LCD_E,LCD_RW,DATA_BUS);
input iCLK_50MHZ, iRST_N; //In Feed Beep this reset will not be used, so need RST_N=1
input [4:0] state_code;
output LCD_RS, LCD_E, LCD_RW;
inout [7:0] DATA_BUS;
parameter
HOLD = 4'h0,
FUNC_SET = 4'h1,
DISPLAY_ON = 4'h2,
MODE_SET = 4'h3,
Print_String = 4'h4,
LINE2 = 4'h5,
RETURN_HOME = 4'h6,
DROP_LCD_E = 4'h7,
RESET1 = 4'h8,
RESET2 = 4'h9,
RESET3 = 4'ha,
DISPLAY_OFF = 4'hb,
DISPLAY_CLEAR = 4'hc;
reg [3:0] state, next_command;
// Enter new ASCII hex data above for LCD Display
reg [7:0] DATA_BUS_VALUE;
wire [7:0] Next_Char;
reg [19:0] CLK_COUNT_400HZ;
reg [4:0] CHAR_COUNT;
reg CLK_400HZ, LCD_RW_INT, LCD_E, LCD_RS;
// BIDIRECTIONAL TRI STATE LCD DATA BUS
assign DATA_BUS = (LCD_RW_INT? 8'bZZZZZZZZ: DATA_BUS_VALUE);
LCD_display_string u1(
.index(CHAR_COUNT),
.out(Next_Char),
.state_code(state_code));
assign LCD_RW = LCD_RW_INT;
always @(posedge iCLK_50MHZ or negedge iRST_N)
if (!iRST_N)
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= 1'b0;
end
else if (CLK_COUNT_400HZ < 20'h0F424)
begin
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1'b1;
end
else
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= ~CLK_400HZ;
end
// State Machine to send commands and data to LCD DISPLAY
always @(posedge CLK_400HZ or negedge iRST_N)
if (!iRST_N)
begin
state <= RESET1;
end
else
case (state)
RESET1:
// Set Function to 8-bit transfer and 2 line display with 5x8 Font size
// see Hitachi HD44780 family data sheet for LCD command and timing details
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET2;
CHAR_COUNT <= 5'b00000;
end
RESET2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET3;
end
RESET3:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= FUNC_SET;
end
// EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
FUNC_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= DISPLAY_OFF;
end
// Turn off Display and Turn off cursor
DISPLAY_OFF:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h08;
state <= DROP_LCD_E;
next_command <= DISPLAY_CLEAR;
end
// Clear Display and Turn off cursor
DISPLAY_CLEAR:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h01;
state <= DROP_LCD_E;
next_command <= DISPLAY_ON;
end
// Turn on Display and Turn off cursor
DISPLAY_ON:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h0C;
state <= DROP_LCD_E;
next_command <= MODE_SET;
end
// Set write mode to auto increment address and move cursor to the right
MODE_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h06;
state <= DROP_LCD_E;
next_command <= Print_String;
end
// Write ASCII hex character in first LCD character location
Print_String:
begin
state <= DROP_LCD_E;
LCD_E <= 1'b1;
LCD_RS <= 1'b1;
LCD_RW_INT <= 1'b0;
// ASCII character to output
if (Next_Char[7:4] != 4'h0)
DATA_BUS_VALUE <= Next_Char;
// Convert 4-bit value to an ASCII hex digit
else if (Next_Char[3:0] >9)
// ASCII A...F
DATA_BUS_VALUE <= {4'h4,Next_Char[3:0]-4'h9};
else
// ASCII 0...9
DATA_BUS_VALUE <= {4'h3,Next_Char[3:0]};
// Loop to send out 32 characters to LCD Display (16 by 2 lines)
if ((CHAR_COUNT < 31) && (Next_Char != 8'hFE))
CHAR_COUNT <= CHAR_COUNT + 1'b1;
else
CHAR_COUNT <= 5'b00000;
// Jump to second line?
if (CHAR_COUNT == 15)
next_command <= LINE2;
// Return to first line?
else if ((CHAR_COUNT == 31) || (Next_Char == 8'hFE))
next_command <= RETURN_HOME;
else
next_command <= Print_String;
end
// Set write address to line 2 character 1
LINE2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'hC0;
state <= DROP_LCD_E;
next_command <= Print_String;
end
// Return write address to first character postion on line 1
RETURN_HOME:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h80;
state <= DROP_LCD_E;
next_command <= Print_String;
end
// The next three states occur at the end of each command or data transfer to the LCD
// Drop LCD E line - falling edge loads inst/data to LCD controller
DROP_LCD_E:
begin
LCD_E <= 1'b0;
state <= HOLD;
end
// Hold LCD inst/data valid after falling edge of E line
HOLD:
begin
state <= next_command;
end
endcase
endmodule |
module image_processing_2d_design_frequency_analyzer_manager_0_1 (
data,
pixel_clock,
start,
stop,
clear,
irq,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
input wire [7 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire start;
input wire stop;
input wire clear;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 irq INTERRUPT" *)
output wire irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [9 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [9 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
frequency_analyzer_manager #(
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(10),
.PIXEL0_INDEX(63),
.PIXEL1_INDEX(511),
.PIXEL2_INDEX(1000),
.PIXEL0_FREQUENCY0(5000),
.PIXEL0_FREQUENCY1(10000),
.PIXEL1_FREQUENCY0(15000),
.PIXEL1_FREQUENCY1(20000),
.PIXEL2_FREQUENCY0(40000),
.PIXEL2_FREQUENCY1(50000),
.FREQUENCY_DEVIATION(20),
.CLOCK_FREQUENCY(100000000)
) inst (
.data(data),
.pixel_clock(pixel_clock),
.start(start),
.stop(stop),
.clear(clear),
.irq(irq),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule |
module artemis_pcie_interface #(
parameter CONTROL_FIFO_DEPTH = 7,
parameter DATA_FIFO_DEPTH = 9,
parameter SERIAL_NUMBER = 64'h000000000000C594
)(
input clk,
input rst,
//The Following Signals are clocked at 62.5MHz
// PCI Express Fabric Interface
input gtp_clk_p,
input gtp_clk_n,
output pci_exp_txp,
output pci_exp_txn,
input pci_exp_rxp,
input pci_exp_rxn,
// Transaction (TRN) Interface
output user_lnk_up,
output pcie_clk,
// Flow Control
input [2:0] fc_sel,
output [7:0] fc_nph,
output [11:0] fc_npd,
output [7:0] fc_ph,
output [11:0] fc_pd,
output [7:0] fc_cplh,
output [11:0] fc_cpld,
// Host (CFG) Interface
output [31:0] cfg_do,
output cfg_rd_wr_done,
input [9:0] cfg_dwaddr,
input cfg_rd_en,
// Configuration: Error
input cfg_err_ur,
input cfg_err_cor,
input cfg_err_ecrc,
input cfg_err_cpl_timeout,
input cfg_err_cpl_abort,
input cfg_err_posted,
input cfg_err_locked,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy,
// Conifguration: Interrupt
input cfg_interrupt,
output cfg_interrupt_rdy,
input cfg_interrupt_assert,
output [7:0] cfg_interrupt_do,
input [7:0] cfg_interrupt_di,
output [2:0] cfg_interrupt_mmenable,
output cfg_interrupt_msienable,
// Configuration: Power Management
input cfg_turnoff_ok,
output cfg_to_turnoff,
input cfg_pm_wake,
// Configuration: System/Status
output [2:0] cfg_pcie_link_state,
input cfg_trn_pending_stb,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
// System Interface
output pcie_reset,
output pll_lock_detect,
output gtp_pll_lock_detect,
output gtp_reset_done,
output rx_elec_idle,
output received_hot_reset,
input i_cmd_in_rd_stb,
output o_cmd_in_rd_ready,
input i_cmd_in_rd_activate,
output [23:0] o_cmd_in_rd_count,
output [31:0] o_cmd_in_rd_data,
output [1:0] o_cmd_out_wr_ready,
input [1:0] i_cmd_out_wr_activate,
output [23:0] o_cmd_out_wr_size,
input i_cmd_out_wr_stb,
input [31:0] i_cmd_out_wr_data,
input i_data_in_rd_stb,
output o_data_in_rd_ready,
input i_data_in_rd_activate,
output [23:0] o_data_in_rd_count,
output [31:0] o_data_in_rd_data,
output [1:0] o_data_out_wr_ready,
input [1:0] i_data_out_wr_activate,
output [23:0] o_data_out_wr_size,
input i_data_out_wr_stb,
input [31:0] i_data_out_wr_data,
input [1:0] rx_equalizer_ctrl,
input [3:0] tx_diff_ctrl,
input [2:0] tx_pre_emphasis,
output [4:0] cfg_ltssm_state,
output dbg_reg_detected_correctable,
output dbg_reg_detected_fatal,
output dbg_reg_detected_non_fatal,
output dbg_reg_detected_unsupported,
output dbg_bad_dllp_status,
output dbg_bad_tlp_lcrc,
output dbg_bad_tlp_seq_num,
output dbg_bad_tlp_status,
output dbg_dl_protocol_status,
output dbg_fc_protocol_err_status,
output dbg_mlfrmd_length,
output dbg_mlfrmd_mps,
output dbg_mlfrmd_tcvc,
output dbg_mlfrmd_tlp_status,
output dbg_mlfrmd_unrec_type,
output dbg_poistlpstatus,
output dbg_rcvr_overflow_status,
output dbg_rply_rollover_status,
output dbg_rply_timeout_status,
output dbg_ur_no_bar_hit,
output dbg_ur_pois_cfg_wr,
output dbg_ur_status,
output dbg_ur_unsup_msg
);
//local parameters
localparam CONTROL_FIFO_SIZE = (2 ** CONTROL_FIFO_DEPTH);
localparam DATA_FIFO_SIZE = (2 ** DATA_FIFO_DEPTH);
localparam CONTROL_FUNCTION_ID = 1'b0;
localparam DATA_FUNCTION_ID = 1'b1;
//registes/wires
(* KEEP = "TRUE" *) wire clk_62p5;
//Control Signals
wire [1:0] c_in_wr_ready;
wire [1:0] c_in_wr_activate;
wire [23:0] c_in_wr_size;
wire c_in_wr_stb;
wire [31:0] c_in_wr_data;
wire c_out_rd_stb;
wire c_out_rd_ready;
wire c_out_rd_activate;
wire [23:0] c_out_rd_size;
wire [31:0] c_out_rd_data;
//Data
wire [1:0] d_in_wr_ready;
wire [1:0] d_in_wr_activate;
wire [23:0] d_in_wr_size;
wire d_in_wr_stb;
wire [31:0] d_in_wr_data;
wire d_out_rd_stb;
wire d_out_rd_ready;
wire d_out_rd_activate;
wire [23:0] d_out_rd_size;
wire [31:0] d_out_rd_data;
wire axi_clk;
//Control Signals
wire c_in_axi_ready;
wire [31:0] c_in_axi_data;
wire [3:0] c_in_axi_keep;
wire c_in_axi_last;
wire c_in_axi_valid;
wire c_out_axi_ready;
wire [31:0] c_out_axi_data;
wire [3:0] c_out_axi_keep;
wire c_out_axi_last;
wire c_out_axi_valid;
//Data Signals
wire d_in_axi_ready;
wire [31:0] d_in_axi_data;
wire [3:0] d_in_axi_keep;
wire d_in_axi_last;
wire d_in_axi_valid;
wire d_out_axi_ready;
wire [31:0] d_out_axi_data;
wire [3:0] d_out_axi_keep;
wire d_out_axi_last;
wire d_out_axi_valid;
wire [31:0] m_axis_rx_tdata;
wire [3:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire s_axis_tx_tready;
wire [31:0] s_axis_tx_tdata;
wire [3:0] s_axis_tx_tkeep;
wire [3:0] s_axis_tx_tuser;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
wire cfg_trn_pending;
assign s_axis_tx_tuser = 0;
//submodules
/*
cross_clock_strobe trn_pnd (
.rst (rst ),
.in_clk (clk ),
.in_stb (cfg_trn_pending_stb),
.out_clk (clk_62p5 ),
.out_stb (cfg_trn_pending )
);
*/
assign cfg_trn_pending = 0;
wire tx_cfg_gnt;
wire rx_np_ok;
/*** ALLOW THE Normal PRIORITIZATION! ***/
assign tx_cfg_gnt = 1'b1;
//READY TO ACCEPT NON POSTED THIMAGIGGERS
assign rx_np_ok = 1'b1;
pcie_axi_bridge pcie_interface (
// PCI Express Fabric Interface
.pci_exp_txp (pci_exp_txp ),
.pci_exp_txn (pci_exp_txn ),
.pci_exp_rxp (pci_exp_rxp ),
.pci_exp_rxn (pci_exp_rxn ),
// Transaction (TRN) Interface
.user_lnk_up (user_lnk_up ),
// Tx
.s_axis_tx_tready (s_axis_tx_tready ),
.s_axis_tx_tdata (s_axis_tx_tdata ),
.s_axis_tx_tkeep (s_axis_tx_tkeep ),
.s_axis_tx_tuser (s_axis_tx_tuser ),
.s_axis_tx_tlast (s_axis_tx_tlast ),
.s_axis_tx_tvalid (s_axis_tx_tvalid ),
/*
//TODO
output reg [5:0] tx_buf_av,
output reg tx_err_drop,
output reg tx_cfg_req,
*/
.tx_cfg_gnt (tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata (m_axis_rx_tdata ),
.m_axis_rx_tkeep (m_axis_rx_tkeep ),
.m_axis_rx_tlast (m_axis_rx_tlast ),
.m_axis_rx_tvalid (m_axis_rx_tvalid ),
.m_axis_rx_tready (m_axis_rx_tready ),
// output reg [21:0] m_axis_rx_tuser,
// input rx_np_ok,
.rx_np_ok (rx_np_ok ),
// Flow Control
.fc_sel (fc_sel ),
.fc_nph (fc_nph ),
.fc_npd (fc_npd ),
.fc_ph (fc_ph ),
.fc_pd (fc_pd ),
.fc_cplh (fc_cplh ),
.fc_cpld (fc_cpld ),
// Host Interface
.cfg_do (cfg_do ),
.cfg_rd_wr_done (cfg_rd_wr_done ),
.cfg_dwaddr (cfg_dwaddr ),
.cfg_rd_en (cfg_rd_en ),
// Configuration: Error
.cfg_err_ur (cfg_err_ur ),
.cfg_err_cor (cfg_err_cor ),
.cfg_err_ecrc (cfg_err_ecrc ),
.cfg_err_cpl_timeout (cfg_err_cpl_timeout ),
.cfg_err_cpl_abort (cfg_err_cpl_abort ),
.cfg_err_posted (cfg_err_posted ),
.cfg_err_locked (cfg_err_locked ),
.cfg_err_tlp_cpl_header (cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy (cfg_err_cpl_rdy ),
// Conifguration: Interrupt
.cfg_interrupt (cfg_interrupt ),
.cfg_interrupt_rdy (cfg_interrupt_rdy ),
.cfg_interrupt_assert (cfg_interrupt_assert ),
.cfg_interrupt_do (cfg_interrupt_do ),
.cfg_interrupt_di (cfg_interrupt_di ),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable ),
.cfg_interrupt_msienable (cfg_interrupt_msienable ),
// Configuration: Power Management
.cfg_turnoff_ok (cfg_turnoff_ok ),
.cfg_to_turnoff (cfg_to_turnoff ),
.cfg_pm_wake (cfg_pm_wake ),
// Configuration: System/Status
.cfg_pcie_link_state (cfg_pcie_link_state ),
.cfg_trn_pending (cfg_trn_pending ),
.cfg_dsn (SERIAL_NUMBER ),
.cfg_bus_number (cfg_bus_number ),
.cfg_device_number (cfg_device_number ),
.cfg_function_number (cfg_function_number ),
.cfg_status (cfg_status ),
.cfg_command (cfg_command ),
.cfg_dstatus (cfg_dstatus ),
.cfg_dcommand (cfg_dcommand ),
.cfg_lstatus (cfg_lstatus ),
.cfg_lcommand (cfg_lcommand ),
// System Interface
.sys_clk_p (gtp_clk_p ),
.sys_clk_n (gtp_clk_n ),
.sys_reset (rst ),
.user_clk_out (clk_62p5 ),
.user_reset_out (pcie_reset ),
.received_hot_reset (received_hot_reset ),
.pll_lock_detect (pll_lock_detect ),
.gtp_pll_lock_detect (gtp_pll_lock_detect ),
.gtp_reset_done (gtp_reset_done ),
.rx_elec_idle (rx_elec_idle ),
.rx_equalizer_ctrl (rx_equalizer_ctrl ),
.tx_diff_ctrl (tx_diff_ctrl ),
.tx_pre_emphasis (tx_pre_emphasis ),
.cfg_ltssm_state (cfg_ltssm_state ),
.dbg_reg_detected_correctable (dbg_reg_detected_correctable ),
.dbg_reg_detected_fatal (dbg_reg_detected_fatal ),
.dbg_reg_detected_non_fatal (dbg_reg_detected_non_fatal ),
.dbg_reg_detected_unsupported (dbg_reg_detected_unsupported ),
.dbg_bad_dllp_status (dbg_bad_dllp_status ),
.dbg_bad_tlp_lcrc (dbg_bad_tlp_lcrc ),
.dbg_bad_tlp_seq_num (dbg_bad_tlp_seq_num ),
.dbg_bad_tlp_status (dbg_bad_tlp_status ),
.dbg_dl_protocol_status (dbg_dl_protocol_status ),
.dbg_fc_protocol_err_status (dbg_fc_protocol_err_status ),
.dbg_mlfrmd_length (dbg_mlfrmd_length ),
.dbg_mlfrmd_mps (dbg_mlfrmd_mps ),
.dbg_mlfrmd_tcvc (dbg_mlfrmd_tcvc ),
.dbg_mlfrmd_tlp_status (dbg_mlfrmd_tlp_status ),
.dbg_mlfrmd_unrec_type (dbg_mlfrmd_unrec_type ),
.dbg_poistlpstatus (dbg_poistlpstatus ),
.dbg_rcvr_overflow_status (dbg_rcvr_overflow_status ),
.dbg_rply_rollover_status (dbg_rply_rollover_status ),
.dbg_rply_timeout_status (dbg_rply_timeout_status ),
.dbg_ur_no_bar_hit (dbg_ur_no_bar_hit ),
.dbg_ur_pois_cfg_wr (dbg_ur_pois_cfg_wr ),
.dbg_ur_status (dbg_ur_status ),
.dbg_ur_unsup_msg (dbg_ur_unsup_msg )
);
adapter_axi_stream_2_ppfifo cntrl_a2p (
.rst (pcie_reset ),
//AXI Stream Input
.i_axi_clk (axi_clk ),
.o_axi_ready (c_in_axi_ready ),
.i_axi_data (c_in_axi_data ),
.i_axi_keep (c_in_axi_keep ),
.i_axi_last (c_in_axi_last ),
.i_axi_valid (c_in_axi_valid ),
//Ping Pong FIFO Write Controller
.o_ppfifo_clk (axi_clk ),
.i_ppfifo_rdy (c_in_wr_ready ),
.o_ppfifo_act (c_in_wr_activate ),
.i_ppfifo_size (c_in_wr_size ),
.o_ppfifo_stb (c_in_wr_stb ),
.o_ppfifo_data (c_in_wr_data )
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (CONTROL_FIFO_DEPTH - 2)
) pcie_control_ingress (
//Control Signals
.reset (pcie_reset ),
//Write Side
.write_clock (axi_clk ),
.write_ready (c_in_wr_ready ),
.write_activate (c_in_wr_activate ),
.write_fifo_size (c_in_wr_size ),
.write_strobe (c_in_wr_stb ),
.write_data (c_in_wr_data ),
.starved ( ),
//Read Size
.read_clock (clk ),
.read_strobe (i_cmd_in_rd_stb ),
.read_ready (o_cmd_in_rd_ready ),
.read_activate (i_cmd_in_rd_activate ),
.read_count (o_cmd_in_rd_count ),
.read_data (o_cmd_in_rd_data ),
.inactive ( )
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (CONTROL_FIFO_DEPTH - 2)
) pcie_control_egress (
//Control Signals
.reset (pcie_reset ),
//Write Side
.write_clock (clk ),
.write_ready (o_cmd_out_wr_ready ),
.write_activate (i_cmd_out_wr_activate),
.write_fifo_size (o_cmd_out_wr_size ),
.write_strobe (i_cmd_out_wr_stb ),
.write_data (i_cmd_out_wr_data ),
.starved ( ),
//Read Size
.read_clock (axi_clk ),
.read_strobe (c_out_rd_stb ),
.read_ready (c_out_rd_ready ),
.read_activate (c_out_rd_activate),
.read_count (c_out_rd_size ),
.read_data (c_out_rd_data ),
.inactive ( )
);
adapter_ppfifo_2_axi_stream control_p2a (
.rst (pcie_reset ),
//Ping Poing FIFO Read Interface
.i_ppfifo_clk (axi_clk ),
.i_ppfifo_rdy (c_out_rd_ready ),
.o_ppfifo_act (c_out_rd_activate),
.i_ppfifo_size (c_out_rd_size ),
.i_ppfifo_data (c_out_rd_data ),
.o_ppfifo_stb (c_out_rd_stb ),
//AXI Stream Output
.o_axi_clk ( ),
.i_axi_ready (c_out_axi_ready ),
.o_axi_data (c_out_axi_data ),
.o_axi_keep (c_out_axi_keep ),
.o_axi_last (c_out_axi_last ),
.o_axi_valid (c_out_axi_valid )
);
//Data FIFOs
adapter_axi_stream_2_ppfifo data_a2p (
.rst (pcie_reset ),
//AXI Stream Input
.i_axi_clk (axi_clk ),
.o_axi_ready (d_in_axi_ready ),
.i_axi_data (d_in_axi_data ),
.i_axi_keep (d_in_axi_keep ),
.i_axi_last (d_in_axi_last ),
.i_axi_valid (d_in_axi_valid ),
//Ping Pong FIFO Write Controller
.o_ppfifo_clk ( ),
.i_ppfifo_rdy (d_in_wr_ready ),
.o_ppfifo_act (d_in_wr_activate ),
.i_ppfifo_size (d_in_wr_size ),
.o_ppfifo_stb (d_in_wr_stb ),
.o_ppfifo_data (d_in_wr_data )
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (DATA_FIFO_DEPTH - 2 )
) pcie_data_ingress (
//Control Signals
.reset (pcie_reset ),
//Write Side
.write_clock (axi_clk ),
.write_ready (d_in_wr_ready ),
.write_activate (d_in_wr_activate ),
.write_fifo_size (d_in_wr_size ),
.write_strobe (d_in_wr_stb ),
.write_data (d_in_wr_data ),
.starved (),
//Read Size
.read_clock (clk ),
.read_strobe (i_data_in_rd_stb ),
.read_ready (o_data_in_rd_ready ),
.read_activate (i_data_in_rd_activate ),
.read_count (o_data_in_rd_count ),
.read_data (o_data_in_rd_data ),
.inactive ()
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (DATA_FIFO_DEPTH - 2 )
) pcie_data_egress (
//Control Signals
.reset (pcie_reset ),
//Write Side
.write_clock (clk ),
.write_ready (o_data_out_wr_ready ),
.write_activate (i_data_out_wr_activate),
.write_fifo_size (o_data_out_wr_size ),
.write_strobe (i_data_out_wr_stb ),
.write_data (i_data_out_wr_data ),
.starved (),
//Read Size
.read_clock (axi_clk ),
.read_strobe (d_out_rd_stb ),
.read_ready (d_out_rd_ready ),
.read_activate (d_out_rd_activate),
.read_count (d_out_rd_size ),
.read_data (d_out_rd_data ),
.inactive ()
);
adapter_ppfifo_2_axi_stream data_p2a (
.rst (pcie_reset ),
//Ping Poing FIFO Read Interface
.i_ppfifo_clk (axi_clk ),
.i_ppfifo_rdy (d_out_rd_ready ),
.o_ppfifo_act (d_out_rd_activate),
.i_ppfifo_size (d_out_rd_size ),
.i_ppfifo_data (d_out_rd_data ),
.o_ppfifo_stb (d_out_rd_stb ),
//AXI Stream Output
.o_axi_clk ( ),
.i_axi_ready (d_out_axi_ready ),
.o_axi_data (d_out_axi_data ),
.o_axi_keep (d_out_axi_keep ),
.o_axi_last (d_out_axi_last ),
.o_axi_valid (d_out_axi_valid )
);
//asynchronous logic
assign axi_clk = clk_62p5;
assign pcie_clk = clk_62p5;
//Map the PCIE to PPFIFO FIFO
assign m_axis_rx_tready = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_in_axi_ready : d_in_axi_ready;
assign c_in_axi_data = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? m_axis_rx_tdata: 32'h00000000;
assign d_in_axi_data = (cfg_function_number[0] == DATA_FUNCTION_ID) ? m_axis_rx_tdata: 32'h00000000;
assign c_in_axi_keep = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? m_axis_rx_tkeep: 32'h00000000;
assign d_in_axi_keep = (cfg_function_number[0] == DATA_FUNCTION_ID) ? m_axis_rx_tkeep: 32'h00000000;
assign c_in_axi_last = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? m_axis_rx_tlast: 32'h00000000;
assign d_in_axi_last = (cfg_function_number[0] == DATA_FUNCTION_ID) ? m_axis_rx_tlast: 32'h00000000;
assign c_in_axi_valid = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? m_axis_rx_tvalid: 32'h00000000;
assign d_in_axi_valid = (cfg_function_number[0] == DATA_FUNCTION_ID) ? m_axis_rx_tvalid: 32'h00000000;
assign c_out_axi_ready = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? s_axis_tx_tready: 32'h00000000;
assign d_out_axi_ready = (cfg_function_number[0] == DATA_FUNCTION_ID) ? s_axis_tx_tready: 32'h00000000;
assign s_axis_tx_tdata = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_out_axi_data : d_out_axi_data;
assign s_axis_tx_tkeep = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_out_axi_keep : d_out_axi_keep;
assign s_axis_tx_tlast = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_out_axi_last : d_out_axi_last;
assign s_axis_tx_tvalid = (cfg_function_number[0] == CONTROL_FUNCTION_ID) ? c_out_axi_valid : d_out_axi_valid;
//synchronous logic
endmodule |
module UART_fifo_interface #(parameter bits_depth=4)(
input write_flag,
input read_next,
input [7:0] data_in,
input clock,
input reset,
output reg [7:0] data_out,
output reg empty_flag,
output reg full_flag
);
localparam depth= 1<<(bits_depth);
reg [7:0] FIFO [depth-1:0];
reg [(bits_depth-1):0] read_pointer,
write_pointer;
reg [(bits_depth):0] free_space;
always @* begin
full_flag = (free_space==0);
empty_flag = (free_space==depth);
data_out <= FIFO[read_pointer];
end
always @(posedge clock, posedge reset) begin
if(reset) begin
write_pointer <= 0;
read_pointer <= 0;
free_space <= depth;
end
else begin
if(read_next) begin
if(!empty_flag) begin
read_pointer <= read_pointer + 'b1;
free_space <= free_space + 'b1;
end
end
if(write_flag) begin
FIFO[write_pointer] <= data_in;
write_pointer <= write_pointer + 'b1;
if(!full_flag) begin
free_space <= (free_space - 'b1) ;
end
else if(!empty_flag) begin
read_pointer <= read_pointer + 'b1;
end
end
end
end
endmodule |
module for actual values.
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0
)
(
input clk,
input rst,
input wr_data_en,
input rd_data_valid,
output app_wdf_wren,
output reg [APPDATA_WIDTH-1:0] app_wdf_data,
output reg [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output [APPDATA_WIDTH-1:0] app_cmp_data
);
localparam WR_IDLE_FIRST_DATA = 2'b00;
localparam WR_SECOND_DATA = 2'b01;
localparam WR_THIRD_DATA = 2'b10;
localparam WR_FOURTH_DATA = 2'b11;
localparam RD_IDLE_FIRST_DATA = 2'b00;
localparam RD_SECOND_DATA = 2'b01;
localparam RD_THIRD_DATA = 2'b10;
localparam RD_FOURTH_DATA = 2'b11;
reg [APPDATA_WIDTH-1:0] app_wdf_data_r;
reg [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data_r;
wire app_wdf_wren_r;
reg [(APPDATA_WIDTH/2)-1:0] rd_data_pat_fall;
reg [(APPDATA_WIDTH/2)-1:0] rd_data_pat_rise;
wire rd_data_valid_r;
reg [1:0] rd_state;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
wire [APPDATA_WIDTH-1:0] wr_data;
reg wr_data_en_r;
reg [(APPDATA_WIDTH/2)-1:0] wr_data_fall
/* synthesis syn_maxfan = 2 */;
reg [(APPDATA_WIDTH/2)-1:0] wr_data_rise
/* synthesis syn_maxfan = 2 */;
wire [(APPDATA_WIDTH/8)-1:0] wr_mask_data;
wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_fall;
wire [(APPDATA_WIDTH/16)-1:0] wr_mask_data_rise;
reg [1:0] wr_state;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//***************************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
always @(posedge clk) begin
app_wdf_data_r <= wr_data;
app_wdf_mask_data_r <= wr_mask_data;
app_wdf_data <= app_wdf_data_r;
app_wdf_mask_data <= app_wdf_mask_data_r;
end
// inst ff for timing
FDRSE ff_wdf_wren
(
.Q (app_wdf_wren_r),
.C (clk),
.CE (1'b1),
.D (wr_data_en_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_wdf_wren_r
(
.Q (app_wdf_wren),
.C (clk),
.CE (1'b1),
.D (app_wdf_wren_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_rd_data_valid_r
(
.Q (rd_data_valid_r),
.C (clk),
.CE (1'b1),
.D (rd_data_valid),
.R (1'b0),
.S (1'b0)
);
//***************************************************************************
// DATA generation for WRITE DATA FIFOs & for READ DATA COMPARE
//***************************************************************************
assign wr_data = {wr_data_fall, wr_data_rise};
assign wr_mask_data = {wr_mask_data_fall, wr_mask_data_rise};
//*****************************************************************
// For now, don't vary data masks
//*****************************************************************
assign wr_mask_data_rise = {(APPDATA_WIDTH/8){1'b0}};
assign wr_mask_data_fall = {(APPDATA_WIDTH/8){1'b0}};
//*****************************************************************
// Write data logic
//*****************************************************************
// write data generation
//synthesis attribute max_fanout of wr_data_fall is 2
//synthesis attribute max_fanout of wr_data_rise is 2
always @(posedge clk) begin
if (rst_r1) begin
wr_data_rise <= {(APPDATA_WIDTH/2){1'bx}};
wr_data_fall <= {(APPDATA_WIDTH/2){1'bx}};
wr_state <= WR_IDLE_FIRST_DATA;
end else begin
case (wr_state)
WR_IDLE_FIRST_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/2){1'b1}}; // 0xF
wr_data_fall <= {(APPDATA_WIDTH/2){1'b0}}; // 0x0
wr_state <= WR_SECOND_DATA;
end
WR_SECOND_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
wr_data_fall <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
wr_state <= WR_THIRD_DATA;
end
WR_THIRD_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
wr_data_fall <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
wr_state <= WR_FOURTH_DATA;
end
WR_FOURTH_DATA:
if (wr_data_en) begin
wr_data_rise <= {(APPDATA_WIDTH/8){4'b1001}}; // 0x9
wr_data_fall <= {(APPDATA_WIDTH/8){4'b0110}}; // 0x6
wr_state <= WR_IDLE_FIRST_DATA;
end
endcase
end
end
always @(posedge clk)
if (rst_r1)
wr_data_en_r <= 1'b0;
else
wr_data_en_r <= wr_data_en;
//*****************************************************************
// Read data logic
//*****************************************************************
// read comparison data generation
always @(posedge clk)
if (rst_r1) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/2){1'bx}};
rd_data_pat_fall <= {(APPDATA_WIDTH/2){1'bx}};
rd_state <= RD_IDLE_FIRST_DATA;
end else begin
case (rd_state)
RD_IDLE_FIRST_DATA:
if (rd_data_valid_r)
begin
rd_data_pat_rise <= {(APPDATA_WIDTH/2){1'b1}}; // 0xF
rd_data_pat_fall <= {(APPDATA_WIDTH/2){1'b0}}; // 0x0
rd_state <= RD_SECOND_DATA;
end
RD_SECOND_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
rd_data_pat_fall <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
rd_state <= RD_THIRD_DATA;
end
RD_THIRD_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/4){2'b01}}; // 0x5
rd_data_pat_fall <= {(APPDATA_WIDTH/4){2'b10}}; // 0xA
rd_state <= RD_FOURTH_DATA;
end
RD_FOURTH_DATA:
if (rd_data_valid_r) begin
rd_data_pat_rise <= {(APPDATA_WIDTH/8){4'b1001}}; // 0x9
rd_data_pat_fall <= {(APPDATA_WIDTH/8){4'b0110}}; // 0x6
rd_state <= RD_IDLE_FIRST_DATA;
end
endcase
end
//data to the compare circuit during read
assign app_cmp_data = {rd_data_pat_fall, rd_data_pat_rise};
endmodule |
module HaarFilter_tb ();
parameter STAGES = 8;
parameter INTERNAL_WIDTH = 18;
parameter IN_WIDTH = 16;
parameter OUT_WIDTH = 16;
reg clk; ///< System clock
reg rst; ///< Reset, synchronous and active high
reg en; ///< Enable (once per new sample)
reg signed [IN_WIDTH-1:0] dataIn; ///< Input samples
wire [STAGES:0] outStrobes; ///< Strobes for each output
wire [OUT_WIDTH*(STAGES+1)-1:0] dataOut; ///< Outputs from analysis filter
integer i;
integer j;
reg [OUT_WIDTH-1:0] results [STAGES:0];
always #1 clk = ~clk;
initial begin
clk = 1'b0;
rst = 1'b0;
en = 1'b0;
dataIn = 'd0;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b0;
@(posedge clk) rst = 1'b0;
@(posedge clk) en = 1'b0;
@(posedge clk) en = 1'b1; dataIn = 'd0;
@(posedge clk) en = 1'b0;
for (i=0; i<2**8; i=i+2) begin
@(posedge clk) en = 1'b1; dataIn = i;
@(posedge clk) en = 1'b0;
end
for (i=0; i<2**8; i=i+2) begin
@(posedge clk) en = 1'b1; dataIn = 2**8-i;
@(posedge clk) en = 1'b0;
end
for (i=0; i<2**8; i=i+2) begin
@(posedge clk) en = 1'b1; dataIn = -i;
@(posedge clk) en = 1'b0;
end
for (i=0; i<2**8; i=i+2) begin
@(posedge clk) en = 1'b1; dataIn = -(2**8)+i;
@(posedge clk) en = 1'b0;
end
for (i=0; i<2**20; i=i+1) begin
@(posedge clk) en = 1'b1; dataIn = $rtoi((2.0**(IN_WIDTH-1)-1)*$sin(3.141259*2.0*($itor(i)/2.0**15 + $itor(i)**2/2.0**23)));
@(posedge clk) en = 1'b0;
end
#1000 $stop;
end
always @(dataOut) begin
for (j=0; j<=STAGES; j=j+1) begin
results[j] = dataOut[(OUT_WIDTH*j)+:OUT_WIDTH];
end
end
HaarFilter #(
.STAGES(STAGES),
.INTERNAL_WIDTH(INTERNAL_WIDTH),
.IN_WIDTH(IN_WIDTH),
.OUT_WIDTH(OUT_WIDTH)
)
uut (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, synchronous and active high
.en(en), ///< Enable (once per new sample)
.dataIn(dataIn), ///< [IN_WIDTH-1:0] Input samples
.outStrobes(outStrobes), ///< [STAGES:0] Strobes for each output
.dataOut(dataOut) ///< [OUT_WIDTH*(STAGES+1)-1:0] Outputs from analysis filter
);
endmodule |
module sky130_fd_sc_lp__sleep_pargate_plv (
//# {{power|Power}}
input SLEEP ,
output VIRTPWR
);
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
endmodule |
module PicoBlaze_OutReg
#(parameter LOCAL_PORT_ID = 8'h00)
(
clk,
reset,
port_id,
write_strobe,
out_port,
new_out_port);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
input wire clk;
input wire reset;
input wire [7:0] port_id;
input wire write_strobe;
input wire [7:0] out_port;
output reg [7:0] new_out_port;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg RegEnable=1;
//=======================================================
// Structural coding
//=======================================================
always @ (*)
begin
if (write_strobe == 1)
begin
case (port_id)
LOCAL_PORT_ID: RegEnable = 1;
default: RegEnable = 0;
endcase
end
else
RegEnable=0;
end
always @ (posedge clk, posedge reset)
begin
if(reset == 1)
new_out_port <= 8'h00;
else
begin
if(RegEnable == 1)
new_out_port <= out_port;
else
new_out_port <= new_out_port;
end
end
//=======================================================
// Connections & assigns
//=======================================================
endmodule |
module sky130_fd_sc_ls__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule |
module ID_EX(
clk,rst,
id_a, id_b, id_td, id_d2, id_Aluc, id_WREG, id_WMEM, id_LW,id_instr,
ex_a, ex_b, ex_td, ex_d2, ex_Aluc, ex_WREG, ex_WMEM, ex_LW,ex_instr
);
input clk,rst;
input wire [31:0] id_a,id_b,id_d2,id_instr;
input wire [4:0] id_td,id_Aluc;
input wire id_WREG,id_WMEM,id_LW;
output reg [31:0] ex_a,ex_b,ex_d2,ex_instr;
output reg [4:0] ex_td,ex_Aluc;
output reg ex_WREG,ex_WMEM,ex_LW;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
ex_a <= 0;
ex_b <= 0;
ex_d2 <= 0;
ex_td <= 0;
ex_Aluc <= 0;
ex_WREG <= 0;
ex_WMEM <= 0;
ex_LW <= 0;
ex_instr<=32'b100000;
end
// else if(BJ)
// begin
// ex_a <= 0;
// ex_b <= 0;
// ex_d2 <= 0;
// ex_td <= 0;
// ex_Aluc <= 0;
// ex_WREG <= 0;
// ex_WMEM <= 0;
// ex_LW <= 0;
// ex_instr<=32'b100000;
// end
else
begin
ex_a <= id_a;
ex_b <= id_b;
ex_d2 <= id_d2;
ex_td <= id_td;
ex_Aluc <= id_Aluc;
ex_WREG <= id_WREG;
ex_WMEM <= id_WMEM;
ex_LW <= id_LW;
ex_instr<=id_instr;
end
end
endmodule |
module sky130_fd_sc_ls__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule |
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81,
n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95,
n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107,
n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,
n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151,
n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162,
n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173,
n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184,
n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206,
n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239,
n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250,
n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261,
n262, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272,
n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283,
n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294,
n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305,
n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316,
n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327,
n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338,
n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371,
n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382,
n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493;
AO21XLTS U95 ( .A0(n476), .A1(n444), .B0(n443), .Y(res[6]) );
NAND2X1TS U96 ( .A(n95), .B(n317), .Y(n318) );
NAND2X1TS U97 ( .A(n334), .B(n333), .Y(n335) );
NAND2X1TS U98 ( .A(n312), .B(n311), .Y(n313) );
NAND2X1TS U99 ( .A(n342), .B(n341), .Y(n343) );
NAND2X1TS U100 ( .A(n326), .B(n325), .Y(n327) );
NAND2X1TS U101 ( .A(n263), .B(n337), .Y(n264) );
NAND2X1TS U102 ( .A(n358), .B(n357), .Y(n359) );
NAND2X1TS U103 ( .A(n399), .B(n398), .Y(n400) );
NAND2XLTS U104 ( .A(n381), .B(n380), .Y(n383) );
NAND2XLTS U105 ( .A(n369), .B(n368), .Y(n370) );
NAND2XLTS U106 ( .A(n376), .B(n375), .Y(n377) );
NAND2X1TS U107 ( .A(n365), .B(n364), .Y(n366) );
NAND2X1TS U108 ( .A(n351), .B(n350), .Y(n352) );
NAND2XLTS U109 ( .A(n393), .B(n392), .Y(n394) );
NAND2XLTS U110 ( .A(n80), .B(n406), .Y(n407) );
NOR2X6TS U111 ( .A(n69), .B(n294), .Y(n304) );
OAI21X2TS U112 ( .A0(n382), .A1(n379), .B0(n380), .Y(n378) );
NAND2X1TS U113 ( .A(n329), .B(n334), .Y(n323) );
NAND2X2TS U114 ( .A(n300), .B(in1[31]), .Y(n303) );
NOR2X1TS U115 ( .A(n441), .B(in1[6]), .Y(n475) );
INVX2TS U116 ( .A(n320), .Y(n334) );
NOR2X2TS U117 ( .A(n293), .B(n316), .Y(n295) );
AOI2BB1X2TS U118 ( .A0N(n291), .A1N(n317), .B0(n290), .Y(n292) );
OAI21X1TS U119 ( .A0(n489), .A1(n435), .B0(n434), .Y(n470) );
OAI21X2TS U120 ( .A0(n333), .A1(n324), .B0(n325), .Y(n286) );
NAND2X2TS U121 ( .A(n289), .B(in1[30]), .Y(n311) );
NAND2XLTS U122 ( .A(n479), .B(in1[8]), .Y(n450) );
NOR2X1TS U123 ( .A(n297), .B(in2[30]), .Y(n298) );
NAND2X4TS U124 ( .A(n252), .B(in1[21]), .Y(n368) );
CLKMX2X2TS U125 ( .A(n271), .B(in2[29]), .S0(n276), .Y(n288) );
NOR2X4TS U126 ( .A(n235), .B(in1[19]), .Y(n379) );
NAND2X2TS U127 ( .A(n283), .B(in1[26]), .Y(n341) );
NAND2X2TS U128 ( .A(n253), .B(in1[22]), .Y(n364) );
NAND2X2TS U129 ( .A(n285), .B(in1[28]), .Y(n325) );
NOR2X1TS U130 ( .A(n447), .B(n446), .Y(n469) );
CLKMX2X4TS U131 ( .A(n277), .B(in2[28]), .S0(n276), .Y(n285) );
NOR2X4TS U132 ( .A(n356), .B(n349), .Y(n257) );
CLKMX2X4TS U133 ( .A(n230), .B(in2[19]), .S0(n276), .Y(n235) );
INVX2TS U134 ( .A(n402), .Y(n213) );
MXI2X2TS U135 ( .A(n234), .B(n239), .S0(n423), .Y(n236) );
NOR2X4TS U136 ( .A(n223), .B(in1[17]), .Y(n391) );
NAND2X6TS U137 ( .A(n81), .B(n80), .Y(n76) );
NAND2X2TS U138 ( .A(n209), .B(in1[14]), .Y(n406) );
NOR2X6TS U139 ( .A(n254), .B(in1[23]), .Y(n356) );
NAND2X2TS U140 ( .A(n223), .B(in1[17]), .Y(n392) );
XOR2X1TS U141 ( .A(n245), .B(in2[20]), .Y(n234) );
NAND2X2TS U142 ( .A(n212), .B(in1[15]), .Y(n402) );
CLKMX2X4TS U143 ( .A(n211), .B(in2[15]), .S0(n276), .Y(n212) );
NOR2X2TS U144 ( .A(n279), .B(n278), .Y(n280) );
NOR2X2TS U145 ( .A(n279), .B(in2[24]), .Y(n260) );
XNOR2X1TS U146 ( .A(n268), .B(in2[16]), .Y(n221) );
XNOR2X1TS U147 ( .A(n228), .B(in2[18]), .Y(n217) );
XOR2X2TS U148 ( .A(n279), .B(n266), .Y(n251) );
OR2X6TS U149 ( .A(n268), .B(n267), .Y(n279) );
NAND2X2TS U150 ( .A(n202), .B(in1[13]), .Y(n413) );
XOR2X1TS U151 ( .A(n428), .B(in2[3]), .Y(n429) );
INVX2TS U152 ( .A(n484), .Y(n455) );
NAND2X1TS U153 ( .A(in2[0]), .B(in1[0]), .Y(n422) );
NOR2X2TS U154 ( .A(n479), .B(in1[8]), .Y(n451) );
NAND2X2TS U155 ( .A(n266), .B(n265), .Y(n278) );
CLKINVX6TS U156 ( .A(n268), .Y(n233) );
NAND2X1TS U157 ( .A(n190), .B(n187), .Y(n456) );
INVX2TS U158 ( .A(in2[24]), .Y(n266) );
INVX2TS U159 ( .A(in2[25]), .Y(n265) );
NOR2X1TS U160 ( .A(in2[23]), .B(in2[22]), .Y(n248) );
NAND2X2TS U161 ( .A(n91), .B(n89), .Y(n484) );
NOR2X1TS U162 ( .A(n161), .B(in2[7]), .Y(n167) );
NOR2X2TS U163 ( .A(in2[21]), .B(in2[20]), .Y(n249) );
NOR2X1TS U164 ( .A(n431), .B(n139), .Y(n437) );
XNOR2X2TS U165 ( .A(n215), .B(in2[12]), .Y(n200) );
NAND2X1TS U166 ( .A(n190), .B(n92), .Y(n91) );
NOR4X2TS U167 ( .A(in2[9]), .B(n111), .C(in2[2]), .D(n109), .Y(n121) );
AOI21X1TS U168 ( .A0(n97), .A1(n181), .B0(n90), .Y(n89) );
NOR2X2TS U169 ( .A(in2[17]), .B(in2[16]), .Y(n232) );
NAND2X1TS U170 ( .A(n205), .B(n204), .Y(n214) );
NOR2X2TS U171 ( .A(n112), .B(n111), .Y(n118) );
BUFX3TS U172 ( .A(n438), .Y(n276) );
NAND4X1TS U173 ( .A(n110), .B(in2[9]), .C(n113), .D(n426), .Y(n112) );
OR2X2TS U174 ( .A(in2[5]), .B(n73), .Y(n135) );
INVX4TS U175 ( .A(in2[13]), .Y(n204) );
CLKINVX6TS U176 ( .A(n431), .Y(n164) );
NAND2X2TS U177 ( .A(add_sub), .B(in2[4]), .Y(n134) );
INVX12TS U178 ( .A(add_sub), .Y(n438) );
INVX2TS U179 ( .A(in2[6]), .Y(n439) );
INVX12TS U180 ( .A(n139), .Y(n157) );
NOR2X4TS U181 ( .A(in2[3]), .B(in2[2]), .Y(n85) );
INVX8TS U182 ( .A(in2[5]), .Y(n141) );
INVX12TS U183 ( .A(in2[4]), .Y(n142) );
NOR2XLTS U184 ( .A(in2[19]), .B(in2[18]), .Y(n231) );
OAI21XLTS U185 ( .A0(in2[6]), .A1(add_sub), .B0(in1[6]), .Y(n158) );
NOR2X6TS U186 ( .A(in2[9]), .B(in2[8]), .Y(n177) );
CLKINVX3TS U187 ( .A(in2[2]), .Y(n426) );
NAND3X2TS U188 ( .A(n439), .B(n142), .C(n141), .Y(n144) );
INVX2TS U189 ( .A(in2[12]), .Y(n205) );
BUFX8TS U190 ( .A(n438), .Y(n423) );
NAND2X1TS U191 ( .A(n181), .B(n180), .Y(n182) );
NAND2X1TS U192 ( .A(n441), .B(in1[6]), .Y(n474) );
NAND2X4TS U193 ( .A(n82), .B(n79), .Y(n75) );
AOI21X1TS U194 ( .A0(n330), .A1(n334), .B0(n321), .Y(n322) );
NAND2X1TS U195 ( .A(n94), .B(n388), .Y(n389) );
INVX8TS U196 ( .A(n296), .Y(n339) );
OR2X4TS U197 ( .A(n431), .B(n144), .Y(n161) );
NAND2X2TS U198 ( .A(n94), .B(n384), .Y(n227) );
NAND2X1TS U199 ( .A(n414), .B(n413), .Y(n415) );
NAND2X1TS U200 ( .A(n93), .B(n402), .Y(n403) );
INVX2TS U201 ( .A(in2[20]), .Y(n239) );
INVX2TS U202 ( .A(n355), .Y(n345) );
INVX2TS U203 ( .A(n315), .Y(n308) );
INVX2TS U204 ( .A(n388), .Y(n225) );
INVX4TS U205 ( .A(n291), .Y(n312) );
NOR2X4TS U206 ( .A(n320), .B(n324), .Y(n287) );
NOR2X4TS U207 ( .A(n262), .B(in1[25]), .Y(n338) );
NOR2X6TS U208 ( .A(n285), .B(in1[28]), .Y(n324) );
NOR2X4TS U209 ( .A(n284), .B(in1[27]), .Y(n320) );
MXI2X4TS U210 ( .A(n217), .B(n216), .S0(n423), .Y(n224) );
NOR2X4TS U211 ( .A(n255), .B(in1[24]), .Y(n349) );
NAND2X4TS U212 ( .A(n233), .B(n232), .Y(n228) );
NAND3X2TS U213 ( .A(n164), .B(in2[5]), .C(n142), .Y(n126) );
NAND2X4TS U214 ( .A(n355), .B(n257), .Y(n259) );
NAND2X4TS U215 ( .A(n287), .B(n329), .Y(n316) );
NOR2X4TS U216 ( .A(n379), .B(n374), .Y(n238) );
NAND2X4TS U217 ( .A(n312), .B(n95), .Y(n293) );
NOR2X4TS U218 ( .A(n300), .B(in1[31]), .Y(n305) );
NAND2X4TS U219 ( .A(n254), .B(in1[23]), .Y(n357) );
NOR2X6TS U220 ( .A(n253), .B(in1[22]), .Y(n363) );
NOR2X6TS U221 ( .A(n252), .B(in1[21]), .Y(n361) );
NOR2X6TS U222 ( .A(n338), .B(n340), .Y(n329) );
NOR2X6TS U223 ( .A(n78), .B(n196), .Y(n82) );
NOR2X4TS U224 ( .A(n236), .B(in1[20]), .Y(n374) );
NOR2X4TS U225 ( .A(n391), .B(n397), .Y(n384) );
MXI2X4TS U226 ( .A(n243), .B(n244), .S0(n423), .Y(n253) );
MX2X4TS U227 ( .A(n241), .B(in2[21]), .S0(n276), .Y(n252) );
NOR2X4TS U228 ( .A(n289), .B(in1[30]), .Y(n291) );
NAND2X4TS U229 ( .A(n262), .B(in1[25]), .Y(n337) );
NAND2X4TS U230 ( .A(n284), .B(in1[27]), .Y(n333) );
XOR2X2TS U231 ( .A(n240), .B(in2[21]), .Y(n241) );
INVX2TS U232 ( .A(n473), .Y(n453) );
NAND2X4TS U233 ( .A(n288), .B(in1[29]), .Y(n317) );
INVX2TS U234 ( .A(n397), .Y(n399) );
NAND2X2TS U235 ( .A(n245), .B(n239), .Y(n240) );
OR2X4TS U236 ( .A(n212), .B(in1[15]), .Y(n93) );
NOR2X4TS U237 ( .A(n222), .B(in1[16]), .Y(n397) );
NAND2X4TS U238 ( .A(n222), .B(in1[16]), .Y(n398) );
NAND2X2TS U239 ( .A(n245), .B(n249), .Y(n242) );
NOR2X2TS U240 ( .A(n228), .B(in2[18]), .Y(n229) );
NOR3X4TS U241 ( .A(n279), .B(in2[26]), .C(n278), .Y(n272) );
NAND2X4TS U242 ( .A(n201), .B(in1[12]), .Y(n417) );
NOR2X4TS U243 ( .A(n201), .B(in1[12]), .Y(n410) );
NAND2X6TS U244 ( .A(n168), .B(n96), .Y(n448) );
XOR2X2TS U245 ( .A(n206), .B(in2[14]), .Y(n208) );
NOR2X4TS U246 ( .A(n140), .B(n437), .Y(n446) );
AND2X4TS U247 ( .A(n187), .B(n184), .Y(n185) );
AND2X4TS U248 ( .A(n232), .B(n231), .Y(n250) );
NAND2X2TS U249 ( .A(n100), .B(n426), .Y(n104) );
INVX4TS U250 ( .A(n177), .Y(n179) );
INVX4TS U251 ( .A(n373), .Y(n382) );
NOR2X1TS U252 ( .A(n345), .B(n356), .Y(n348) );
NAND3X6TS U253 ( .A(n76), .B(n75), .C(n406), .Y(n404) );
XOR2X1TS U254 ( .A(n408), .B(n407), .Y(res[14]) );
XOR2X1TS U255 ( .A(n486), .B(n485), .Y(res[10]) );
XOR2X1TS U256 ( .A(n416), .B(n415), .Y(res[13]) );
NAND2X6TS U257 ( .A(n77), .B(n70), .Y(n81) );
INVX2TS U258 ( .A(n385), .Y(n386) );
NAND2X4TS U259 ( .A(n235), .B(in1[19]), .Y(n380) );
OR2X6TS U260 ( .A(n224), .B(in1[18]), .Y(n94) );
MX2X4TS U261 ( .A(n247), .B(in2[23]), .S0(n276), .Y(n254) );
INVX2TS U262 ( .A(n317), .Y(n307) );
NAND2X2TS U263 ( .A(n236), .B(in1[20]), .Y(n375) );
NAND2X4TS U264 ( .A(n224), .B(in1[18]), .Y(n388) );
NAND2X2TS U265 ( .A(n255), .B(in1[24]), .Y(n350) );
OR2X6TS U266 ( .A(n288), .B(in1[29]), .Y(n95) );
MX2X4TS U267 ( .A(n269), .B(in2[30]), .S0(n276), .Y(n289) );
XOR2X1TS U268 ( .A(n473), .B(n472), .Y(res[9]) );
MX2X4TS U269 ( .A(n273), .B(in2[27]), .S0(n276), .Y(n284) );
MXI2X1TS U270 ( .A(n482), .B(n481), .S0(n480), .Y(res[8]) );
XNOR2X2TS U271 ( .A(n272), .B(in2[27]), .Y(n273) );
XNOR2X2TS U272 ( .A(n275), .B(in2[28]), .Y(n277) );
XOR2X2TS U273 ( .A(n297), .B(in2[30]), .Y(n269) );
MXI2X4TS U274 ( .A(n208), .B(n207), .S0(n423), .Y(n209) );
XNOR2X2TS U275 ( .A(n218), .B(in2[17]), .Y(n219) );
NAND2BX2TS U276 ( .AN(in2[29]), .B(n270), .Y(n297) );
OAI21X1TS U277 ( .A0(n476), .A1(n475), .B0(n474), .Y(n478) );
XOR2X1TS U278 ( .A(n470), .B(n469), .Y(res[5]) );
NOR2X4TS U279 ( .A(n489), .B(n488), .Y(n487) );
XOR2XLTS U280 ( .A(n468), .B(n467), .Y(res[3]) );
XOR2X1TS U281 ( .A(n441), .B(in1[6]), .Y(n444) );
NAND3X2TS U282 ( .A(n138), .B(in1[5]), .C(n137), .Y(n140) );
XOR2XLTS U283 ( .A(n464), .B(n463), .Y(res[2]) );
NOR2BX2TS U284 ( .AN(n116), .B(n115), .Y(n117) );
NOR2X6TS U285 ( .A(n179), .B(in2[10]), .Y(n187) );
NAND2BX1TS U286 ( .AN(n491), .B(n490), .Y(n492) );
OR3X2TS U287 ( .A(n278), .B(in2[27]), .C(in2[26]), .Y(n274) );
NAND3X2TS U288 ( .A(n250), .B(n249), .C(n248), .Y(n267) );
NAND2BX1TS U289 ( .AN(in1[1]), .B(n422), .Y(n490) );
NOR2X1TS U290 ( .A(n73), .B(in1[7]), .Y(n160) );
INVX2TS U291 ( .A(in2[9]), .Y(n114) );
INVX4TS U292 ( .A(n72), .Y(n68) );
XOR2XLTS U293 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
XNOR2X2TS U294 ( .A(n328), .B(n327), .Y(res[28]) );
NOR2X2TS U295 ( .A(n146), .B(n145), .Y(n147) );
NAND2X2TS U296 ( .A(n301), .B(n303), .Y(n302) );
MX2X4TS U297 ( .A(n299), .B(in2[31]), .S0(n438), .Y(n300) );
XNOR2X2TS U298 ( .A(n319), .B(n318), .Y(res[29]) );
XNOR2X2TS U299 ( .A(n314), .B(n313), .Y(res[30]) );
MXI2X8TS U300 ( .A(n199), .B(n204), .S0(n423), .Y(n202) );
AOI21X2TS U301 ( .A0(n486), .A1(n483), .B0(n455), .Y(n460) );
AOI211X4TS U302 ( .A0(n149), .A1(n431), .B0(n148), .C0(n147), .Y(n477) );
OAI21X2TS U303 ( .A0(n305), .A1(n304), .B0(n303), .Y(res[32]) );
XNOR2X1TS U304 ( .A(n378), .B(n377), .Y(res[20]) );
AND2X8TS U305 ( .A(n250), .B(n233), .Y(n245) );
AOI211X4TS U306 ( .A0(n132), .A1(n128), .B0(n127), .C0(in1[5]), .Y(n447) );
NAND2X6TS U307 ( .A(n141), .B(n142), .Y(n139) );
INVX16TS U308 ( .A(n181), .Y(n190) );
XOR2X1TS U309 ( .A(n383), .B(n382), .Y(res[19]) );
NOR2X8TS U310 ( .A(n361), .B(n363), .Y(n355) );
MXI2X4TS U311 ( .A(n266), .B(n251), .S0(add_sub), .Y(n255) );
NAND2X6TS U312 ( .A(n84), .B(n83), .Y(n371) );
NAND2X4TS U313 ( .A(n372), .B(n238), .Y(n84) );
NOR2X6TS U314 ( .A(in2[7]), .B(in2[6]), .Y(n103) );
NAND2X8TS U315 ( .A(n157), .B(n103), .Y(n111) );
OR4X8TS U316 ( .A(n215), .B(in2[15]), .C(in2[14]), .D(n214), .Y(n268) );
NAND2X2TS U317 ( .A(n110), .B(n103), .Y(n102) );
INVX2TS U318 ( .A(in2[8]), .Y(n99) );
AND2X2TS U319 ( .A(n484), .B(n176), .Y(n194) );
NOR2XLTS U320 ( .A(n72), .B(in2[6]), .Y(n150) );
NAND2BX1TS U321 ( .AN(n445), .B(in1[4]), .Y(n434) );
CLKAND2X2TS U322 ( .A(n445), .B(n433), .Y(n435) );
NAND3X4TS U323 ( .A(n197), .B(n448), .C(n203), .Y(n77) );
NAND2X1TS U324 ( .A(add_sub), .B(in2[6]), .Y(n163) );
NOR2X4TS U325 ( .A(n215), .B(in2[12]), .Y(n198) );
XNOR2X1TS U326 ( .A(in2[1]), .B(in2[0]), .Y(n420) );
NOR2BX2TS U327 ( .AN(in1[3]), .B(n430), .Y(n465) );
INVX2TS U328 ( .A(n447), .Y(n436) );
XNOR2X1TS U329 ( .A(in2[9]), .B(add_sub), .Y(n120) );
NOR2X2TS U330 ( .A(n118), .B(n117), .Y(n119) );
AND2X2TS U331 ( .A(n177), .B(in2[10]), .Y(n92) );
XOR2X1TS U332 ( .A(n456), .B(in2[11]), .Y(n457) );
INVX2TS U333 ( .A(n410), .Y(n418) );
INVX2TS U334 ( .A(n417), .Y(n411) );
INVX2TS U335 ( .A(n405), .Y(n79) );
INVX2TS U336 ( .A(n333), .Y(n321) );
INVX2TS U337 ( .A(n316), .Y(n306) );
NOR2X2TS U338 ( .A(in2[0]), .B(in2[8]), .Y(n113) );
INVX2TS U339 ( .A(n471), .Y(n174) );
NAND3X1TS U340 ( .A(n479), .B(in1[8]), .C(in1[9]), .Y(n173) );
NAND3X1TS U341 ( .A(n124), .B(n123), .C(n122), .Y(n176) );
NAND2X1TS U342 ( .A(n73), .B(in2[11]), .Y(n124) );
NOR4X2TS U343 ( .A(n268), .B(in2[28]), .C(n267), .D(n274), .Y(n270) );
INVX2TS U344 ( .A(n259), .Y(n87) );
OAI21X1TS U345 ( .A0(n357), .A1(n349), .B0(n350), .Y(n256) );
INVX2TS U346 ( .A(n144), .Y(n145) );
XNOR2X1TS U347 ( .A(in2[7]), .B(in1[7]), .Y(n143) );
OAI21X1TS U348 ( .A0(n164), .A1(n135), .B0(n126), .Y(n127) );
INVX2TS U349 ( .A(in2[0]), .Y(n100) );
AND2X2TS U350 ( .A(n157), .B(n103), .Y(n106) );
NOR2X4TS U351 ( .A(in2[1]), .B(in2[3]), .Y(n110) );
OAI21X1TS U352 ( .A0(n98), .A1(n177), .B0(n71), .Y(n90) );
NOR2X4TS U353 ( .A(n412), .B(n410), .Y(n203) );
XNOR2X1TS U354 ( .A(n229), .B(in2[19]), .Y(n230) );
INVX2TS U355 ( .A(n311), .Y(n290) );
CLKXOR2X2TS U356 ( .A(n445), .B(in1[4]), .Y(n488) );
CLKBUFX2TS U357 ( .A(n372), .Y(n373) );
INVX2TS U358 ( .A(n361), .Y(n369) );
INVX2TS U359 ( .A(n368), .Y(n362) );
OAI21X1TS U360 ( .A0(n346), .A1(n356), .B0(n357), .Y(n347) );
INVX2TS U361 ( .A(n237), .Y(n83) );
NAND2BX1TS U362 ( .AN(n462), .B(n461), .Y(n464) );
NOR2BX1TS U363 ( .AN(n466), .B(n465), .Y(n468) );
XNOR2X1TS U364 ( .A(n479), .B(in1[8]), .Y(n481) );
XOR2X1TS U365 ( .A(n471), .B(in1[9]), .Y(n472) );
NAND2X1TS U366 ( .A(n484), .B(n483), .Y(n485) );
XOR2X1TS U367 ( .A(n460), .B(n459), .Y(res[11]) );
NAND2X1TS U368 ( .A(n418), .B(n417), .Y(n419) );
AOI21X1TS U369 ( .A0(n409), .A1(n418), .B0(n411), .Y(n416) );
INVX2TS U370 ( .A(n412), .Y(n414) );
NOR2XLTS U371 ( .A(n81), .B(n82), .Y(n408) );
OAI21XLTS U372 ( .A0(n397), .A1(n396), .B0(n398), .Y(n395) );
INVX2TS U373 ( .A(n391), .Y(n393) );
OAI21XLTS U374 ( .A0(n387), .A1(n396), .B0(n386), .Y(n390) );
INVX2TS U375 ( .A(n384), .Y(n387) );
INVX2TS U376 ( .A(n379), .Y(n381) );
INVX2TS U377 ( .A(n374), .Y(n376) );
XNOR2X1TS U378 ( .A(n371), .B(n370), .Y(res[21]) );
XOR2X1TS U379 ( .A(n367), .B(n366), .Y(res[22]) );
AOI21X2TS U380 ( .A0(n371), .A1(n369), .B0(n362), .Y(n367) );
INVX2TS U381 ( .A(n363), .Y(n365) );
XOR2X1TS U382 ( .A(n360), .B(n359), .Y(res[23]) );
AOI21X2TS U383 ( .A0(n371), .A1(n355), .B0(n354), .Y(n360) );
INVX2TS U384 ( .A(n356), .Y(n358) );
XOR2X1TS U385 ( .A(n353), .B(n352), .Y(res[24]) );
AOI21X2TS U386 ( .A0(n371), .A1(n348), .B0(n347), .Y(n353) );
INVX2TS U387 ( .A(n349), .Y(n351) );
XOR2X1TS U388 ( .A(n339), .B(n264), .Y(res[25]) );
INVX2TS U389 ( .A(n338), .Y(n263) );
XNOR2X2TS U390 ( .A(n344), .B(n343), .Y(res[26]) );
INVX2TS U391 ( .A(n340), .Y(n342) );
XNOR2X2TS U392 ( .A(n336), .B(n335), .Y(res[27]) );
INVX2TS U393 ( .A(n329), .Y(n332) );
INVX2TS U394 ( .A(n324), .Y(n326) );
NAND2X1TS U395 ( .A(n306), .B(n95), .Y(n310) );
INVX2TS U396 ( .A(n305), .Y(n301) );
CLKINVX3TS U397 ( .A(n72), .Y(n74) );
INVX4TS U398 ( .A(add_sub), .Y(n72) );
AND2X4TS U399 ( .A(n296), .B(n295), .Y(n69) );
OA21X2TS U400 ( .A0(n412), .A1(n417), .B0(n413), .Y(n70) );
AOI21X1TS U401 ( .A0(n438), .A1(in2[10]), .B0(in1[10]), .Y(n71) );
NOR2X4TS U402 ( .A(n209), .B(in1[14]), .Y(n405) );
INVX2TS U403 ( .A(n405), .Y(n80) );
XOR2X1TS U404 ( .A(in2[8]), .B(add_sub), .Y(n101) );
NAND2X2TS U405 ( .A(n114), .B(n74), .Y(n115) );
NOR3X4TS U406 ( .A(n455), .B(n451), .C(n125), .Y(n197) );
NAND3X4TS U407 ( .A(n372), .B(n87), .C(n238), .Y(n86) );
INVX2TS U408 ( .A(add_sub), .Y(n73) );
OAI21X2TS U409 ( .A0(n192), .A1(n483), .B0(n191), .Y(n193) );
NOR2X2TS U410 ( .A(n215), .B(n214), .Y(n206) );
NAND4X2TS U411 ( .A(n106), .B(in2[8]), .C(n105), .D(n110), .Y(n107) );
AOI21X4TS U412 ( .A0(n404), .A1(n93), .B0(n213), .Y(n396) );
INVX2TS U413 ( .A(n203), .Y(n78) );
OAI2BB1X1TS U414 ( .A0N(n448), .A1N(n197), .B0(n196), .Y(n409) );
NAND2X8TS U415 ( .A(n427), .B(n85), .Y(n431) );
NOR2X8TS U416 ( .A(in2[1]), .B(in2[0]), .Y(n427) );
XOR2X4TS U417 ( .A(n304), .B(n302), .Y(res[31]) );
NAND3X8TS U418 ( .A(n88), .B(n86), .C(n258), .Y(n296) );
NAND2BX4TS U419 ( .AN(n259), .B(n237), .Y(n88) );
OAI21X4TS U420 ( .A0(n467), .A1(n465), .B0(n466), .Y(n489) );
AOI21X4TS U421 ( .A0(n463), .A1(n461), .B0(n462), .Y(n467) );
NOR2X6TS U422 ( .A(n477), .B(n151), .Y(n449) );
OAI21X4TS U423 ( .A0(n121), .A1(n120), .B0(n119), .Y(n471) );
OAI21X2TS U424 ( .A0(n315), .A1(n293), .B0(n292), .Y(n294) );
XNOR2X4TS U425 ( .A(n242), .B(in2[22]), .Y(n243) );
NOR2X4TS U426 ( .A(n279), .B(n274), .Y(n275) );
XOR2X4TS U427 ( .A(n280), .B(in2[26]), .Y(n282) );
XOR2X4TS U428 ( .A(n260), .B(in2[25]), .Y(n261) );
NOR2X4TS U429 ( .A(in2[16]), .B(n268), .Y(n218) );
AOI31X4TS U430 ( .A0(n449), .A1(n487), .A2(n469), .B0(n448), .Y(n480) );
CLKINVX1TS U431 ( .A(n396), .Y(n401) );
MXI2X4TS U432 ( .A(n221), .B(n220), .S0(n423), .Y(n222) );
OA21X4TS U433 ( .A0(n167), .A1(n166), .B0(n165), .Y(n96) );
NOR2X6TS U434 ( .A(n283), .B(in1[26]), .Y(n340) );
NOR2BX1TS U435 ( .AN(in1[1]), .B(n422), .Y(n491) );
MXI2X1TS U436 ( .A(in2[11]), .B(n457), .S0(n74), .Y(n458) );
XNOR2X1TS U437 ( .A(n390), .B(n389), .Y(res[18]) );
OR2X8TS U438 ( .A(n111), .B(n431), .Y(n181) );
NOR2X2TS U439 ( .A(n438), .B(in2[10]), .Y(n97) );
INVX2TS U440 ( .A(n97), .Y(n98) );
NAND2X2TS U441 ( .A(n99), .B(n74), .Y(n171) );
OAI31X2TS U442 ( .A0(n102), .A1(in2[8]), .A2(n104), .B0(n101), .Y(n108) );
INVX2TS U443 ( .A(n104), .Y(n105) );
OAI211X4TS U444 ( .A0(n157), .A1(n171), .B0(n108), .C0(n107), .Y(n479) );
INVX2TS U445 ( .A(n110), .Y(n109) );
INVX2TS U446 ( .A(n113), .Y(n116) );
INVX2TS U447 ( .A(in2[11]), .Y(n184) );
NAND2X1TS U448 ( .A(n184), .B(n68), .Y(n123) );
INVX2TS U449 ( .A(in1[11]), .Y(n122) );
OAI21X2TS U450 ( .A0(n471), .A1(in1[9]), .B0(n176), .Y(n125) );
NAND2X4TS U451 ( .A(n74), .B(in2[5]), .Y(n132) );
NAND2X1TS U452 ( .A(n134), .B(n141), .Y(n128) );
INVX2TS U453 ( .A(n134), .Y(n129) );
NAND2X1TS U454 ( .A(n431), .B(n129), .Y(n130) );
OAI211X1TS U455 ( .A0(in2[4]), .A1(n68), .B0(n130), .C0(in1[4]), .Y(n131) );
AOI211X2TS U456 ( .A0(n142), .A1(n164), .B0(n447), .C0(n131), .Y(n152) );
INVX2TS U457 ( .A(n132), .Y(n133) );
NAND2X1TS U458 ( .A(n431), .B(n133), .Y(n138) );
NAND2X1TS U459 ( .A(n134), .B(in2[5]), .Y(n136) );
NAND2X1TS U460 ( .A(n136), .B(n135), .Y(n137) );
NAND2X2TS U461 ( .A(n143), .B(n68), .Y(n146) );
INVX2TS U462 ( .A(n146), .Y(n149) );
AOI21X1TS U463 ( .A0(n161), .A1(n68), .B0(n143), .Y(n148) );
AOI211X1TS U464 ( .A0(in2[6]), .A1(n276), .B0(n150), .C0(in1[6]), .Y(n151)
);
OAI21X4TS U465 ( .A0(n152), .A1(n446), .B0(n449), .Y(n168) );
INVX2TS U466 ( .A(n161), .Y(n155) );
NAND2X1TS U467 ( .A(n68), .B(in2[7]), .Y(n154) );
INVX2TS U468 ( .A(in2[7]), .Y(n153) );
NAND2X1TS U469 ( .A(n153), .B(n438), .Y(n156) );
OAI211X1TS U470 ( .A0(n155), .A1(n154), .B0(in1[7]), .C0(n156), .Y(n166) );
OAI22X1TS U471 ( .A0(n157), .A1(n163), .B0(n156), .B1(in1[7]), .Y(n159) );
AOI211X1TS U472 ( .A0(in2[7]), .A1(n160), .B0(n159), .C0(n158), .Y(n162) );
OAI211X1TS U473 ( .A0(n164), .A1(n163), .B0(n162), .C0(n161), .Y(n165) );
INVX2TS U474 ( .A(in1[8]), .Y(n170) );
AOI31X1TS U475 ( .A0(n73), .A1(in2[8]), .A2(in1[8]), .B0(in1[9]), .Y(n169)
);
OAI31X1TS U476 ( .A0(n190), .A1(n171), .A2(n170), .B0(n169), .Y(n172) );
AOI31X1TS U477 ( .A0(n190), .A1(in2[8]), .A2(in1[8]), .B0(n172), .Y(n175) );
OAI21X2TS U478 ( .A0(n175), .A1(n174), .B0(n173), .Y(n195) );
INVX2TS U479 ( .A(n176), .Y(n192) );
AND2X4TS U480 ( .A(in2[10]), .B(n68), .Y(n180) );
OAI21X1TS U481 ( .A0(in2[10]), .A1(n74), .B0(in1[10]), .Y(n178) );
AOI21X1TS U482 ( .A0(n179), .A1(n180), .B0(n178), .Y(n183) );
NAND3X2TS U483 ( .A(n456), .B(n183), .C(n182), .Y(n483) );
NAND2X1TS U484 ( .A(add_sub), .B(in2[11]), .Y(n189) );
NAND2X8TS U485 ( .A(n190), .B(n185), .Y(n215) );
OAI21X1TS U486 ( .A0(n68), .A1(in2[11]), .B0(in1[11]), .Y(n186) );
AOI2BB1X1TS U487 ( .A0N(n187), .A1N(n189), .B0(n186), .Y(n188) );
OAI211X1TS U488 ( .A0(n190), .A1(n189), .B0(n215), .C0(n188), .Y(n191) );
AOI21X4TS U489 ( .A0(n195), .A1(n194), .B0(n193), .Y(n196) );
XNOR2X4TS U490 ( .A(n198), .B(n204), .Y(n199) );
NOR2X8TS U491 ( .A(n202), .B(in1[13]), .Y(n412) );
MXI2X4TS U492 ( .A(n200), .B(n205), .S0(n423), .Y(n201) );
INVX2TS U493 ( .A(in2[14]), .Y(n207) );
NOR3X1TS U494 ( .A(n215), .B(in2[14]), .C(n214), .Y(n210) );
XNOR2X1TS U495 ( .A(n210), .B(in2[15]), .Y(n211) );
INVX2TS U496 ( .A(in2[18]), .Y(n216) );
MX2X4TS U497 ( .A(n219), .B(in2[17]), .S0(n276), .Y(n223) );
INVX2TS U498 ( .A(in2[16]), .Y(n220) );
OAI21X4TS U499 ( .A0(n391), .A1(n398), .B0(n392), .Y(n385) );
AOI21X4TS U500 ( .A0(n94), .A1(n385), .B0(n225), .Y(n226) );
OAI21X4TS U501 ( .A0(n396), .A1(n227), .B0(n226), .Y(n372) );
OAI21X4TS U502 ( .A0(n380), .A1(n374), .B0(n375), .Y(n237) );
INVX2TS U503 ( .A(in2[22]), .Y(n244) );
NAND3X4TS U504 ( .A(n245), .B(n249), .C(n244), .Y(n246) );
XOR2X4TS U505 ( .A(n246), .B(in2[23]), .Y(n247) );
OAI21X4TS U506 ( .A0(n368), .A1(n363), .B0(n364), .Y(n354) );
AOI21X4TS U507 ( .A0(n257), .A1(n354), .B0(n256), .Y(n258) );
MXI2X4TS U508 ( .A(n261), .B(n265), .S0(n423), .Y(n262) );
XNOR2X1TS U509 ( .A(n270), .B(in2[29]), .Y(n271) );
INVX2TS U510 ( .A(in2[26]), .Y(n281) );
MXI2X4TS U511 ( .A(n282), .B(n281), .S0(n423), .Y(n283) );
OAI21X4TS U512 ( .A0(n340), .A1(n337), .B0(n341), .Y(n330) );
AOI21X4TS U513 ( .A0(n330), .A1(n287), .B0(n286), .Y(n315) );
XNOR2X1TS U514 ( .A(n298), .B(in2[31]), .Y(n299) );
AOI21X4TS U515 ( .A0(n308), .A1(n95), .B0(n307), .Y(n309) );
OAI21X4TS U516 ( .A0(n339), .A1(n310), .B0(n309), .Y(n314) );
OAI21X4TS U517 ( .A0(n339), .A1(n316), .B0(n315), .Y(n319) );
OAI21X4TS U518 ( .A0(n339), .A1(n323), .B0(n322), .Y(n328) );
INVX2TS U519 ( .A(n330), .Y(n331) );
OAI21X4TS U520 ( .A0(n339), .A1(n332), .B0(n331), .Y(n336) );
OAI21X4TS U521 ( .A0(n339), .A1(n338), .B0(n337), .Y(n344) );
INVX2TS U522 ( .A(n354), .Y(n346) );
XNOR2X1TS U523 ( .A(n395), .B(n394), .Y(res[17]) );
XNOR2X1TS U524 ( .A(n401), .B(n400), .Y(res[16]) );
XNOR2X1TS U525 ( .A(n404), .B(n403), .Y(res[15]) );
XNOR2X1TS U526 ( .A(n409), .B(n419), .Y(res[12]) );
INVX2TS U527 ( .A(in2[1]), .Y(n421) );
MXI2X2TS U528 ( .A(n421), .B(n420), .S0(n68), .Y(n493) );
OAI21X2TS U529 ( .A0(n493), .A1(n491), .B0(n490), .Y(n463) );
XOR2X1TS U530 ( .A(in2[2]), .B(n427), .Y(n424) );
MXI2X2TS U531 ( .A(n424), .B(n426), .S0(n423), .Y(n425) );
NAND2X2TS U532 ( .A(n425), .B(in1[2]), .Y(n461) );
NOR2X2TS U533 ( .A(n425), .B(in1[2]), .Y(n462) );
NAND2X1TS U534 ( .A(n427), .B(n426), .Y(n428) );
MXI2X2TS U535 ( .A(n429), .B(in2[3]), .S0(n438), .Y(n430) );
NAND2BX2TS U536 ( .AN(in1[3]), .B(n430), .Y(n466) );
XOR2X1TS U537 ( .A(n431), .B(in2[4]), .Y(n432) );
MXI2X2TS U538 ( .A(n432), .B(in2[4]), .S0(n438), .Y(n445) );
INVX2TS U539 ( .A(in1[4]), .Y(n433) );
OAI21X2TS U540 ( .A0(n470), .A1(n446), .B0(n436), .Y(n476) );
XNOR2X1TS U541 ( .A(n437), .B(n439), .Y(n440) );
MXI2X2TS U542 ( .A(n440), .B(n439), .S0(n438), .Y(n441) );
INVX2TS U543 ( .A(n475), .Y(n442) );
AOI21X1TS U544 ( .A0(n474), .A1(n442), .B0(n476), .Y(n443) );
OAI21X4TS U545 ( .A0(n480), .A1(n451), .B0(n450), .Y(n473) );
INVX2TS U546 ( .A(in1[9]), .Y(n452) );
NAND2X2TS U547 ( .A(n453), .B(n452), .Y(n454) );
AOI22X2TS U548 ( .A0(n473), .A1(in1[9]), .B0(n471), .B1(n454), .Y(n486) );
XNOR2X1TS U549 ( .A(n458), .B(in1[11]), .Y(n459) );
XNOR2X1TS U550 ( .A(n478), .B(n477), .Y(res[7]) );
INVX2TS U551 ( .A(n481), .Y(n482) );
AOI21X1TS U552 ( .A0(n489), .A1(n488), .B0(n487), .Y(res[4]) );
XNOR2X1TS U553 ( .A(n493), .B(n492), .Y(res[1]) );
initial $sdf_annotate("Approx_adder_GDAN16M4P8_syn.sdf");
endmodule |
module system_top (
// clock and resets
sys_clk,
sys_resetn,
// ddr3
ddr3_a,
ddr3_ba,
ddr3_clk_p,
ddr3_clk_n,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_ras_n,
ddr3_cas_n,
ddr3_we_n,
ddr3_reset_n,
ddr3_dq,
ddr3_dqs_p,
ddr3_dqs_n,
ddr3_odt,
ddr3_rzq,
// ethernet
eth_rx_clk,
eth_rx_data,
eth_rx_cntrl,
eth_tx_clk_out,
eth_tx_data,
eth_tx_cntrl,
eth_mdc,
eth_mdio_i,
eth_mdio_o,
eth_mdio_t,
eth_phy_resetn,
// board gpio
led_grn,
led_red,
push_buttons,
dip_switches,
// lane interface
ref_clk,
rx_data,
rx_sync,
rx_sysref,
// spi
spi_csn,
spi_clk,
spi_sdio);
// clock and resets
input sys_clk;
input sys_resetn;
// ddr3
output [ 13:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_clk_p;
output ddr3_clk_n;
output ddr3_cke;
output ddr3_cs_n;
output [ 7:0] ddr3_dm;
output ddr3_ras_n;
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
inout [ 63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_p;
inout [ 7:0] ddr3_dqs_n;
output ddr3_odt;
input ddr3_rzq;
// ethernet
input eth_rx_clk;
input [ 3:0] eth_rx_data;
input eth_rx_cntrl;
output eth_tx_clk_out;
output [ 3:0] eth_tx_data;
output eth_tx_cntrl;
output eth_mdc;
input eth_mdio_i;
output eth_mdio_o;
output eth_mdio_t;
output eth_phy_resetn;
// board gpio
output [ 7:0] led_grn;
output [ 7:0] led_red;
input [ 2:0] push_buttons;
input [ 7:0] dip_switches;
// lane interface
input ref_clk;
input [ 3:0] rx_data;
output rx_sync;
output rx_sysref;
// spi
output spi_csn;
output spi_clk;
inout spi_sdio;
// internal registers
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_m3 = 'd0;
reg rx_sysref = 'd0;
reg [ 3:0] phy_rst_cnt = 0;
reg phy_rst_reg = 0;
// internal clocks and resets
wire sys_125m_clk;
wire sys_25m_clk;
wire sys_2m5_clk;
wire eth_tx_clk;
wire rx_clk;
// internal signals
wire sys_pll_locked_s;
wire eth_tx_reset_s;
wire eth_tx_mode_1g_s;
wire eth_tx_mode_10m_100m_n_s;
wire spi_mosi;
wire spi_miso;
wire [ 3:0] rx_ip_sof_s;
wire [127:0] rx_ip_data_s;
wire [127:0] rx_data_s;
wire rx_sw_rstn_s;
wire rx_sysref_s;
wire rx_err_s;
wire rx_ready_s;
wire [ 3:0] rx_rst_state_s;
wire rx_lane_aligned_s;
wire [ 3:0] rx_analog_reset_s;
wire [ 3:0] rx_digital_reset_s;
wire [ 3:0] rx_cdr_locked_s;
wire [ 3:0] rx_cal_busy_s;
wire rx_pll_locked_s;
wire [ 15:0] rx_xcvr_status_s;
// ethernet transmit clock
assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
(eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
assign eth_phy_resetn = phy_rst_reg;
always@ (posedge eth_mdc) begin
phy_rst_cnt <= phy_rst_cnt + 4'd1;
if (phy_rst_cnt == 4'h0) begin
phy_rst_reg <= sys_pll_locked_s;
end
end
altddio_out #(.width(1)) i_eth_tx_clk_out (
.aset (1'b0),
.sset (1'b0),
.sclr (1'b0),
.oe (1'b1),
.oe_out (),
.datain_h (1'b1),
.datain_l (1'b0),
.outclocken (1'b1),
.aclr (eth_tx_reset_s),
.outclock (eth_tx_clk),
.dataout (eth_tx_clk_out));
assign eth_tx_reset_s = ~sys_pll_locked_s;
always @(posedge rx_clk) begin
rx_sysref_m1 <= rx_sysref_s;
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_m3 <= rx_sysref_m2;
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
end
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_align_1
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof_s),
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_data (rx_data_s[n*32+31:n*32]));
end
endgenerate
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (130),
.sld_data_bit_cntr_bits (8),
.sld_enable_advanced_trigger (0),
.sld_mem_address_bits (10),
.sld_node_crc_bits (32),
.sld_node_crc_hiword (10311),
.sld_node_crc_loword (14297),
.sld_node_info (1076736),
.sld_ram_block_type ("AUTO"),
.sld_sample_depth (1024),
.sld_storage_qualifier_gap_record (0),
.sld_storage_qualifier_mode ("OFF"),
.sld_trigger_bits (2),
.sld_trigger_in_enabled (0),
.sld_trigger_level (1),
.sld_trigger_level_pipeline (1))
i_signaltap (
.acq_clk (rx_clk),
.acq_data_in ({ rx_sysref,
rx_sync,
rx_ip_data_s}),
.acq_trigger_in ({rx_sysref, rx_sync}));
assign rx_xcvr_status_s[15:15] = 1'd0;
assign rx_xcvr_status_s[14:14] = rx_sync;
assign rx_xcvr_status_s[13:13] = rx_ready_s;
assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
.rx_clk (rx_clk),
.rx_rstn (sys_resetn),
.rx_sw_rstn (rx_sw_rstn_s),
.rx_pll_locked (rx_pll_locked_s),
.rx_cal_busy (rx_cal_busy_s),
.rx_cdr_locked (rx_cdr_locked_s),
.rx_analog_reset (rx_analog_reset_s),
.rx_digital_reset (rx_digital_reset_s),
.rx_ready (rx_ready_s),
.rx_rst_state (rx_rst_state_s));
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_reset_reset_n (sys_resetn),
.sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk),
.sys_ddr3_phy_mem_a (ddr3_a),
.sys_ddr3_phy_mem_ba (ddr3_ba),
.sys_ddr3_phy_mem_ck (ddr3_clk_p),
.sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
.sys_ddr3_phy_mem_cke (ddr3_cke),
.sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
.sys_ddr3_phy_mem_dm (ddr3_dm),
.sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
.sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
.sys_ddr3_phy_mem_we_n (ddr3_we_n),
.sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
.sys_ddr3_phy_mem_dq (ddr3_dq),
.sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
.sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
.sys_ddr3_phy_mem_odt (ddr3_odt),
.sys_ddr3_oct_rzqin (ddr3_rzq),
.sys_ethernet_tx_clk_clk (eth_tx_clk),
.sys_ethernet_rx_clk_clk (eth_rx_clk),
.sys_ethernet_status_set_10 (),
.sys_ethernet_status_set_1000 (),
.sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_gpio_in_export ({rx_xcvr_status_s, 5'd0, push_buttons, dip_switches}),
.sys_gpio_out_export ({14'd0, rx_sw_rstn_s, rx_sysref_s, led_grn, led_red}),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn),
.axi_ad9250_0_xcvr_clk_clk (rx_clk),
.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
.axi_ad9250_1_xcvr_clk_clk (rx_clk),
.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
.sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
.sys_jesd204b_s1_rx_link_valid (),
.sys_jesd204b_s1_rx_link_ready (1'b1),
.sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sysref_export (rx_sysref),
.sys_jesd204b_s1_rx_ferr_export (rx_err_s),
.sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sync_n_export (rx_sync),
.sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
.sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
.sys_jesd204b_s1_locked_rx_is_lockedtodata (rx_cdr_locked_s),
.sys_jesd204b_s1_rx_cal_busy_rx_cal_busy (rx_cal_busy_s),
.sys_jesd204b_s1_ref_clk_clk (ref_clk),
.sys_jesd204b_s1_rx_clk_clk (rx_clk),
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
.sys_pll_locked_export (sys_pll_locked_s));
endmodule |
module sky130_fd_sc_hd__nand3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hd__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule |
module mult(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] addr,
input wire [(API_WIDTH - 1) : 0] write_data,
output wire [(API_WIDTH - 1) : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter API_WIDTH = 16;
parameter OPA_WIDTH = 256;
parameter OPB_WIDTH = 64;
localparam OPA_WORDS = OPA_WIDTH / API_WIDTH;
localparam OPA_BASE_ADDR = 8'h00;
localparam OPA_TOP_ADDR = (OPA_BASE_ADDR + OPA_WORDS - 1);
localparam OPB_WORDS = OPB_WIDTH / API_WIDTH;
localparam OPB_BASE_ADDR = 8'h40;
localparam OPB_TOP_ADDR = (OPB_BASE_ADDR + OPB_WORDS - 1);
localparam PROD_WIDTH = OPA_WIDTH + OPB_WIDTH;
localparam PROD_WORDS = PROD_WIDTH / API_WIDTH;
localparam PROD_BASE_ADDR = 8'h80;
localparam PROD_TOP_ADDR = (PROD_BASE_ADDR + PROD_WORDS - 1);
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [(OPA_WIDTH - 1) : 0] opa_reg;
reg [(OPA_WIDTH - 1) : 0] opa_new;
reg opa_we;
reg [(OPA_WIDTH - 1) : 0] opb_reg;
reg [(OPA_WIDTH - 1) : 0] opb_new;
reg opb_we;
reg [(PROD_WIDTH - 1) : 0] prod_reg;
reg [(PROD_WIDTH - 1) : 0] prod_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [(API_WIDTH -1) : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
opa_reg <= {(OPA_WIDTH){1'h0}};
opb_reg <= {(OPB_WIDTH){1'h0}};
prod_reg <= {(PROD_WIDTH){1'h0}};
end
else
begin
prod_reg <= prod_new;
if (opa_we)
opa_reg <= opa_new;
if (opb_we)
opb_reg <= opb_new;
end
end // reg_update
//----------------------------------------------------------------
// mult_logic
//
// This is where the action is.
//----------------------------------------------------------------
always @*
begin : mult_logic
prod_new = opa_reg * opb_reg;
end
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
tmp_read_data = {(API_WIDTH){1'h0}};
opa_new = opa_reg;
opa_we = 0;
opb_new = opb_reg;
opb_we = 0;
if (cs)
begin
if (we)
begin
if ((addr >= OPA_BASE_ADDR) && (addr <= OPA_TOP_ADDR))
begin
opa_new[API_WIDTH * (addr - OPA_BASE_ADDR) +: API_WIDTH] = write_data;
opa_we = 1;
end
if ((addr >= OPB_BASE_ADDR) && (addr <= OPB_TOP_ADDR))
begin
opb_new[API_WIDTH * (addr - OPB_BASE_ADDR) +: API_WIDTH] = write_data;
opb_we = 1;
end
end
else
begin
if ((addr >= PROD_BASE_ADDR) && (addr <= PROD_TOP_ADDR))
tmp_read_data = prod_reg[API_WIDTH * (addr - PROD_BASE_ADDR) +: API_WIDTH];
end
end
end // addr_decoder
endmodule |
module sky130_fd_sc_hdll__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module data_memory2 (clk, addr, din, dout, pc, access_size, rw, busy, enable);
parameter ROM_FILE = "SimpleAdd.x";
`define MEMSIZE 1024
`define START_ADDR 32'h8002_0000
// input
input clk;
input [31:0] addr;
input [31:0] din;
input [2:0] access_size;
input rw; //1 is write, 0 is read
input enable;
// output
output reg busy;
output reg [31:0] dout;
output reg [31:0] pc;
// memory
reg [7:0] mem[0:`MEMSIZE];
// local
reg [31:0] reg_cur_addr = 'hffff; // current address
reg [5:0] reg_counter = 0; // number of cycles remaining
reg reg_rw = 0; // rw status
reg [31:0] reg_din = 'hffff; // prev datain
// comb
initial
begin
$readmemh(ROM_FILE, mem);
end
// proc
always @(posedge clk)
begin
reg_din = din;
// update current address
if (reg_counter > 1)
begin
reg_cur_addr = reg_cur_addr + 4;
end
else if (enable == 'b1) // + check address
begin
reg_cur_addr = addr - `START_ADDR;
end
else
begin
reg_cur_addr = reg_cur_addr; // no change
end
// update counter/rw
if (!(reg_counter > 1) && enable == 'b1)
begin
case (access_size)
3'b000 : reg_counter = 'd1; // word
3'b001 : reg_counter = 'd4; // 4 words
3'b010 : reg_counter = 'd8; // 8 words
3'b011 : reg_counter = 'd16; // 16 words
3'b100 : reg_counter = 'd1; // byte
3'b101 : reg_counter = 'd1; // half word
default : reg_counter = 'd0;
endcase
reg_rw = rw;
end
else
begin
reg_counter = reg_counter == 0 ? 0 : reg_counter - 1;
reg_rw = reg_rw;
end
// read
if ((reg_counter != 0) && reg_rw == 'b0)
begin
if (access_size == 3'b100)
begin
dout[31:24] = 0;
dout[23:16] = 0;
dout[15:8] = 0;
dout[7:0] = mem[reg_cur_addr]; // LSB
end
else if (access_size == 3'b101)
begin
dout[31:24] = 0;
dout[23:16] = 0;
dout[15:8] = mem[reg_cur_addr];
dout[7:0] = mem[reg_cur_addr+1]; // LSB
end
else
begin
dout[31:24] = mem[reg_cur_addr]; // MSB
dout[23:16] = mem[reg_cur_addr+1];
dout[15:8] = mem[reg_cur_addr+2];
dout[7:0] = mem[reg_cur_addr+3]; // LSB
end
pc = reg_cur_addr + `START_ADDR;
end
else
begin
dout[31:0] = 'bx;
end
// write
if ((reg_counter != 0) && reg_rw == 'b1)
begin
if (access_size == 3'b100)
begin
mem[reg_cur_addr] = reg_din[7:0];
end
else if (access_size == 3'b101)
begin
mem[reg_cur_addr] = reg_din[15:8]; // MSB
mem[reg_cur_addr+1] = reg_din[7:0];
end
else
begin
mem[reg_cur_addr] = reg_din[31:24]; // MSB
mem[reg_cur_addr+1] = reg_din[23:16];
mem[reg_cur_addr+2] = reg_din[15:8];
mem[reg_cur_addr+3] = reg_din[7:0]; // LSB
end
end
busy = (reg_counter > 1);
end
endmodule |
module debouncer(
input clk,
input I0,
input I1,
output reg O0,
output reg O1
);
reg [4:0]cnt0, cnt1;
reg Iv0=0,Iv1=0;
reg out0, out1;
always@(posedge(clk))begin
if (I0==Iv0)begin
if (cnt0==19)O0<=I0;
else cnt0<=cnt0+1;
end
else begin
cnt0<="00000";
Iv0<=I0;
end
if (I1==Iv1)begin
if (cnt1==19)O1<=I1;
else cnt1<=cnt1+1;
end
else begin
cnt1<="00000";
Iv1<=I1;
end
end
endmodule |
module sky130_fd_sc_lp__dlrbn_lp (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__dlrbn_lp (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule |
module sky130_fd_sc_ms__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule |
module
//------------------------------------------------------------------------------------------------
/********** Xilinx FPGA Block RAM : two ports RAM **********/
symmetric_mem_core x_s3e_dpram (
/********** port A : IF stage **********/
.clockA (clk), //clock
.addressA (if_spm_addr), //address
.input_dataA (if_spm_wr_data), //
.write_enableA (wea), //
.output_dataA (if_spm_rd_data), //
/********** port B : MEM Stage **********/
.clockB (clk), //
.addressB (mem_spm_addr), //
.input_dataB (mem_spm_wr_data), //
.write_enableB (web), //
.output_dataB (mem_spm_rd_data) //read data
);
endmodule |
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|Pa%dPb%d|%d%d%d|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.phase_b[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("(%d)", u.core.state);
$write("| %d %d %d %d %d %d %d %d| %d %d %d %d %d %d %d %d|",
u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt,
u.core.im04_a.imf.cnt, u.core.im05_a.imf.cnt, u.core.im06_a.imf.cnt, u.core.im07_a.imf.cnt,
u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt,
u.core.im04_b.imf.cnt, u.core.im05_b.imf.cnt, u.core.im06_b.imf.cnt, u.core.im07_b.imf.cnt);
$write(" ");
if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" ");
if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule |
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule |
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