module_content
stringlengths 18
1.05M
|
|---|
module sky130_fd_sc_lp__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule |
module pcie_2_1_rport_7x # (
parameter CFG_VEND_ID = 16'h10ee,
parameter CFG_DEV_ID = 16'h7121,
parameter CFG_REV_ID = 8'h00,
parameter CFG_SUBSYS_VEND_ID = 16'h10ee,
parameter CFG_SUBSYS_ID = 16'h0007,
parameter PIPE_SIM_MODE = "FALSE",
// PCIE_2_1 params
parameter REF_CLK_FREQ = 0,
parameter PCIE_EXT_CLK = "FALSE",
parameter PIPE_PIPELINE_STAGES = 0,
parameter [11:0] AER_BASE_PTR = 12'h128,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h160,
parameter AER_CAP_ON = "FALSE",
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFF00,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'hFFFF000C,
parameter [31:0] BAR3 = 32'hFFFFFFFF,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 64,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [23:0] CLASS_CODE = 24'h000000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "FALSE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "FALSE",
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter integer DEV_CAP_RSVD_14_12 = 0,
parameter integer DEV_CAP_RSVD_17_16 = 0,
parameter integer DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C,
parameter DSN_CAP_ON = "TRUE",
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h01,
parameter [4:0] INFER_EI = 5'h00,
parameter [7:0] INTERRUPT_PIN = 8'h01,
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter IS_SWITCH = "FALSE",
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE",
parameter integer LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter integer LINK_CAP_RSVD_23 = 0,
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter integer LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH,
parameter MPS_FORCE = "FALSE",
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter integer MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter integer MSI_CAP_MULTIMSGCAP = 0,
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter integer N_FTS_COMCLK_GEN1 = 255,
parameter integer N_FTS_COMCLK_GEN2 = 255,
parameter integer N_FTS_GEN1 = 255,
parameter integer N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h4,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C,
parameter PCIE_CAP_ON = "TRUE",
parameter integer PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter integer PCIE_REVISION = 2,
parameter integer PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter integer PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_DSI = "FALSE",
parameter [7:0] PM_CAP_ID = 8'h01,
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter integer PM_CAP_RSVD_04 = 0,
parameter integer PM_CAP_VERSION = 3,
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [7:0] PM_DATA0 = 8'h01,
parameter [7:0] PM_DATA1 = 8'h01,
parameter [7:0] PM_DATA2 = 8'h01,
parameter [7:0] PM_DATA3 = 8'h01,
parameter [7:0] PM_DATA4 = 8'h01,
parameter [7:0] PM_DATA5 = 8'h01,
parameter [7:0] PM_DATA6 = 8'h01,
parameter [7:0] PM_DATA7 = 8'h01,
parameter [1:0] PM_DATA_SCALE0 = 2'h1,
parameter [1:0] PM_DATA_SCALE1 = 2'h1,
parameter [1:0] PM_DATA_SCALE2 = 2'h1,
parameter [1:0] PM_DATA_SCALE3 = 2'h1,
parameter [1:0] PM_DATA_SCALE4 = 2'h1,
parameter [1:0] PM_DATA_SCALE5 = 2'h1,
parameter [1:0] PM_DATA_SCALE6 = 2'h1,
parameter [1:0] PM_DATA_SCALE7 = 2'h1,
parameter PM_MF = "FALSE",
parameter [11:0] RBAR_BASE_PTR = 12'h178,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter [2:0] RBAR_NUM = 3'h1,
parameter integer RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SELECT_DLL_IF = "FALSE",
parameter SIM_VERSION = "1.0",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter TECRC_EP_INV = "FALSE",
parameter TL_RBYPASS = "FALSE",
parameter integer TL_RX_RAM_RADDR_LATENCY = 0,
parameter integer TL_RX_RAM_RDATA_LATENCY = 2,
parameter integer TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter integer TL_TX_RAM_RADDR_LATENCY = 0,
parameter integer TL_TX_RAM_RDATA_LATENCY = 2,
parameter integer TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_DW = "FALSE",
parameter TRN_NP_FC = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "FALSE",
parameter UR_ATOMIC = "TRUE",
parameter UR_CFG1 = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK2_DIV2 = "FALSE",
parameter integer USER_CLK_FREQ = 3,
parameter USE_RID_PINS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF,
parameter integer VC0_TOTAL_CREDITS_CD = 127,
parameter integer VC0_TOTAL_CREDITS_CH = 31,
parameter integer VC0_TOTAL_CREDITS_NPD = 24,
parameter integer VC0_TOTAL_CREDITS_NPH = 12,
parameter integer VC0_TOTAL_CREDITS_PD = 288,
parameter integer VC0_TOTAL_CREDITS_PH = 32,
parameter integer VC0_TX_LASTPACKET = 31,
parameter [11:0] VC_BASE_PTR = 12'h10C,
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [11:0] VC_CAP_NEXTPTR = 12'h128,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [11:0] VSEC_BASE_PTR = 12'h160,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1,
parameter PCIE_USE_MODE = "3.0",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_CHAN_BOND = 0,
parameter PCIE_PLL_SEL = "CPLL",
parameter PCIE_ASYNC_EN = "FALSE",
parameter PCIE_TXBUF_EN = "FALSE"
)
(
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock Inputs - For Partial Reconfig Support //
//----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input PIPE_RXUSRCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk_out,
output reg user_reset_out,
output reg user_lnk_up,
// AXI TX
//-----------
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input s_axis_tx_tvalid,
output s_axis_tx_tready,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input s_axis_tx_tlast,
input [3:0] s_axis_tx_tuser,
input tx_cfg_gnt,
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//-------------------------------------------------------
// 4. Configuration (CFG) Interface
//-------------------------------------------------------
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
output wire cfg_pmcsr_pme_en,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_status,
output wire cfg_received_func_lvl_rst,
// Management Interface
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_en,
input wire cfg_mgmt_rd_en,
input wire cfg_mgmt_wr_readonly,
// Error Reporting Interface
input wire cfg_err_ecrc,
input wire cfg_err_ur,
input wire cfg_err_cpl_timeout,
input wire cfg_err_cpl_unexpect,
input wire cfg_err_cpl_abort,
input wire cfg_err_posted,
input wire cfg_err_cor,
input wire cfg_err_atomic_egress_blocked,
input wire cfg_err_internal_cor,
input wire cfg_err_malformed,
input wire cfg_err_mc_blocked,
input wire cfg_err_poisoned,
input wire cfg_err_norecovery,
input wire [47:0] cfg_err_tlp_cpl_header,
output wire cfg_err_cpl_rdy,
input wire cfg_err_locked,
input wire cfg_err_acs,
input wire cfg_err_internal_uncor,
input wire cfg_trn_pending,
input wire cfg_pm_halt_aspm_l0s,
input wire cfg_pm_halt_aspm_l1,
input wire cfg_pm_force_state_en,
input wire [1:0] cfg_pm_force_state,
input wire [63:0] cfg_dsn,
output cfg_msg_received,
output [15:0] cfg_msg_data,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
input wire cfg_interrupt,
output wire cfg_interrupt_rdy,
input wire cfg_interrupt_assert,
input wire [7:0] cfg_interrupt_di,
output wire [7:0] cfg_interrupt_do,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
input wire cfg_interrupt_stat,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
output cfg_to_turnoff,
input wire cfg_turnoff_ok,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
input wire cfg_pm_wake,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_msg_received_setslotpowerlimit,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire cfg_pm_send_pme_to,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire cfg_mgmt_wr_rw1c_as_rw,
output wire cfg_bridge_serr_en,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_deassert_int_d,
//-------------------------------------------------------
// 5. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
output wire pl_received_hot_rst,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire pl_downstream_deemph_source,
input wire pl_transmit_hot_rst,
//----------------------------------------------------------------------------------------------------------------//
// 6. AER interface //
//----------------------------------------------------------------------------------------------------------------//
input wire [127:0] cfg_err_aer_headerlog,
input wire [4:0] cfg_aer_interrupt_msgnum,
output wire cfg_err_aer_headerlog_set,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
output wire [6:0] cfg_vc_tcvc_map,
//----------------------------------------------------------------------------------------------------------------//
// 8. System(SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire sys_clk,
input wire sys_rst_n
);
wire user_clk;
wire user_clk2;
wire [15:0] cfg_vend_id = CFG_VEND_ID;
wire [15:0] cfg_dev_id = CFG_DEV_ID;
wire [7:0] cfg_rev_id = CFG_REV_ID;
wire [15:0] cfg_subsys_vend_id = CFG_SUBSYS_VEND_ID;
wire [15:0] cfg_subsys_id = CFG_SUBSYS_ID;
// PIPE Interface Wires
wire phy_rdy_n;
wire pipe_rx0_polarity_gt;
wire pipe_rx1_polarity_gt;
wire pipe_rx2_polarity_gt;
wire pipe_rx3_polarity_gt;
wire pipe_rx4_polarity_gt;
wire pipe_rx5_polarity_gt;
wire pipe_rx6_polarity_gt;
wire pipe_rx7_polarity_gt;
wire pipe_tx_deemph_gt;
wire [2:0] pipe_tx_margin_gt;
wire pipe_tx_rate_gt;
wire pipe_tx_rcvr_det_gt;
wire [1:0] pipe_tx0_char_is_k_gt;
wire pipe_tx0_compliance_gt;
wire [15:0] pipe_tx0_data_gt;
wire pipe_tx0_elec_idle_gt;
wire [1:0] pipe_tx0_powerdown_gt;
wire [1:0] pipe_tx1_char_is_k_gt;
wire pipe_tx1_compliance_gt;
wire [15:0] pipe_tx1_data_gt;
wire pipe_tx1_elec_idle_gt;
wire [1:0] pipe_tx1_powerdown_gt;
wire [1:0] pipe_tx2_char_is_k_gt;
wire pipe_tx2_compliance_gt;
wire [15:0] pipe_tx2_data_gt;
wire pipe_tx2_elec_idle_gt;
wire [1:0] pipe_tx2_powerdown_gt;
wire [1:0] pipe_tx3_char_is_k_gt;
wire pipe_tx3_compliance_gt;
wire [15:0] pipe_tx3_data_gt;
wire pipe_tx3_elec_idle_gt;
wire [1:0] pipe_tx3_powerdown_gt;
wire [1:0] pipe_tx4_char_is_k_gt;
wire pipe_tx4_compliance_gt;
wire [15:0] pipe_tx4_data_gt;
wire pipe_tx4_elec_idle_gt;
wire [1:0] pipe_tx4_powerdown_gt;
wire [1:0] pipe_tx5_char_is_k_gt;
wire pipe_tx5_compliance_gt;
wire [15:0] pipe_tx5_data_gt;
wire pipe_tx5_elec_idle_gt;
wire [1:0] pipe_tx5_powerdown_gt;
wire [1:0] pipe_tx6_char_is_k_gt;
wire pipe_tx6_compliance_gt;
wire [15:0] pipe_tx6_data_gt;
wire pipe_tx6_elec_idle_gt;
wire [1:0] pipe_tx6_powerdown_gt;
wire [1:0] pipe_tx7_char_is_k_gt;
wire pipe_tx7_compliance_gt;
wire [15:0] pipe_tx7_data_gt;
wire pipe_tx7_elec_idle_gt;
wire [1:0] pipe_tx7_powerdown_gt;
wire pipe_rx0_chanisaligned_gt;
wire [1:0] pipe_rx0_char_is_k_gt;
wire [15:0] pipe_rx0_data_gt;
wire pipe_rx0_elec_idle_gt;
wire pipe_rx0_phy_status_gt;
wire [2:0] pipe_rx0_status_gt;
wire pipe_rx0_valid_gt;
wire pipe_rx1_chanisaligned_gt;
wire [1:0] pipe_rx1_char_is_k_gt;
wire [15:0] pipe_rx1_data_gt;
wire pipe_rx1_elec_idle_gt;
wire pipe_rx1_phy_status_gt;
wire [2:0] pipe_rx1_status_gt;
wire pipe_rx1_valid_gt;
wire pipe_rx2_chanisaligned_gt;
wire [1:0] pipe_rx2_char_is_k_gt;
wire [15:0] pipe_rx2_data_gt;
wire pipe_rx2_elec_idle_gt;
wire pipe_rx2_phy_status_gt;
wire [2:0] pipe_rx2_status_gt;
wire pipe_rx2_valid_gt;
wire pipe_rx3_chanisaligned_gt;
wire [1:0] pipe_rx3_char_is_k_gt;
wire [15:0] pipe_rx3_data_gt;
wire pipe_rx3_elec_idle_gt;
wire pipe_rx3_phy_status_gt;
wire [2:0] pipe_rx3_status_gt;
wire pipe_rx3_valid_gt;
wire pipe_rx4_chanisaligned_gt;
wire [1:0] pipe_rx4_char_is_k_gt;
wire [15:0] pipe_rx4_data_gt;
wire pipe_rx4_elec_idle_gt;
wire pipe_rx4_phy_status_gt;
wire [2:0] pipe_rx4_status_gt;
wire pipe_rx4_valid_gt;
wire pipe_rx5_chanisaligned_gt;
wire [1:0] pipe_rx5_char_is_k_gt;
wire [15:0] pipe_rx5_data_gt;
wire pipe_rx5_elec_idle_gt;
wire pipe_rx5_phy_status_gt;
wire [2:0] pipe_rx5_status_gt;
wire pipe_rx5_valid_gt;
wire pipe_rx6_chanisaligned_gt;
wire [1:0] pipe_rx6_char_is_k_gt;
wire [15:0] pipe_rx6_data_gt;
wire pipe_rx6_elec_idle_gt;
wire pipe_rx6_phy_status_gt;
wire [2:0] pipe_rx6_status_gt;
wire pipe_rx6_valid_gt;
wire pipe_rx7_chanisaligned_gt;
wire [1:0] pipe_rx7_char_is_k_gt;
wire [15:0] pipe_rx7_data_gt;
wire pipe_rx7_elec_idle_gt;
wire pipe_rx7_phy_status_gt;
wire [2:0] pipe_rx7_status_gt;
wire pipe_rx7_valid_gt;
reg user_lnk_up_int;
reg user_reset_int;
wire user_rst_n;
reg pl_received_hot_rst_q;
wire pl_received_hot_rst_wire;
reg pl_phy_lnk_up_q;
wire pl_phy_lnk_up_wire;
wire sys_or_hot_rst;
wire trn_lnk_up;
// wire sys_rst_n;
wire [5:0] pl_ltssm_state_int;
localparam TCQ = 100;
// Assign outputs
assign pl_ltssm_state = pl_ltssm_state_int;
assign pl_received_hot_rst = pl_received_hot_rst_q;
assign pl_phy_lnk_up = pl_phy_lnk_up_q;
// Register block outputs pl_received_hot_rst and phy_lnk_up to ease timing on block output
assign sys_or_hot_rst = !sys_rst_n || pl_received_hot_rst_q;
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
pl_received_hot_rst_q <= #TCQ 1'b0;
pl_phy_lnk_up_q <= #TCQ 1'b0;
end else begin
pl_received_hot_rst_q <= #TCQ pl_received_hot_rst_wire;
pl_phy_lnk_up_q <= #TCQ pl_phy_lnk_up_wire;
end
end
// Convert incomign reset from AXI required active High
// to active low as that is what is required by GT and PCIe Block
// assign sys_rst_n = ~sys_reset;
// Generate user_lnk_up
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up <= #TCQ 1'b0;
end else begin
user_lnk_up <= #TCQ user_lnk_up_int;
end
end
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up_int <= #TCQ 1'b0;
end else begin
user_lnk_up_int <= #TCQ trn_lnk_up;
end
end
// Generate user_reset_out
// Once user reset output of PCIE and Phy Layer is active, de-assert reset
// Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
user_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_out <= #TCQ 1'b1;
end else begin
user_reset_out <= #TCQ user_reset_int;
end
end
//--------------------------------------------------------------------------------------------------------------------//
// **** PCI Express Core Wrapper **** //
// The PCI Express Core Wrapper includes the following: //
// 1) AXI Streaming Bridge //
// 2) PCIE 2_1 Hard Block //
// 3) PCIE PIPE Interface Pipeline //
//--------------------------------------------------------------------------------------------------------------------//
pcie_core_pcie_top # (
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
// .REF_CLK_FREQ ( REF_CLK_FREQ ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS ( USE_RID_PINS ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
// I/O
) pcie_top_i (
// AXI Interface
.user_clk_out ( user_clk_out ),
.user_reset ( user_reset_out ),
.user_lnk_up ( user_lnk_up ),
.user_rst_n ( user_rst_n ),
.trn_lnk_up ( trn_lnk_up ),
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( trn_tcfg_gnt ),
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cm_rst_n ( 1'b1 ),
.func_lvl_rst_n ( 1'b1 ),
.lnk_clk_en ( ),
.cfg_dev_id ( cfg_dev_id ),
.cfg_vend_id ( cfg_vend_id ),
.cfg_rev_id ( cfg_rev_id ),
.cfg_subsys_id ( cfg_subsys_id ),
.cfg_subsys_vend_id ( cfg_subsys_vend_id ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_bridge_serr_en ( cfg_bridge_serr_en ),
.cfg_command_bus_master_enable ( ),
.cfg_command_interrupt_disable ( ),
.cfg_command_io_enable ( ),
.cfg_command_mem_enable ( ),
.cfg_command_serr_en ( ),
.cfg_dev_control_aux_power_en ( ),
.cfg_dev_control_corr_err_reporting_en ( ),
.cfg_dev_control_enable_ro ( ),
.cfg_dev_control_ext_tag_en ( ),
.cfg_dev_control_fatal_err_reporting_en ( ),
.cfg_dev_control_max_payload ( ),
.cfg_dev_control_max_read_req ( ),
.cfg_dev_control_non_fatal_reporting_en ( ),
.cfg_dev_control_no_snoop_en ( ),
.cfg_dev_control_phantom_en ( ),
.cfg_dev_control_ur_err_reporting_en ( ),
.cfg_dev_control2_cpl_timeout_dis ( ),
.cfg_dev_control2_cpl_timeout_val ( ),
.cfg_dev_control2_ari_forward_en ( ),
.cfg_dev_control2_atomic_requester_en ( ),
.cfg_dev_control2_atomic_egress_block ( ),
.cfg_dev_control2_ido_req_en ( ),
.cfg_dev_control2_ido_cpl_en ( ),
.cfg_dev_control2_ltr_en ( ),
.cfg_dev_control2_tlp_prefix_block ( ),
.cfg_dev_status_corr_err_detected ( ),
.cfg_dev_status_fatal_err_detected ( ),
.cfg_dev_status_non_fatal_err_detected ( ),
.cfg_dev_status_ur_detected ( ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_link_control_rcb ( ),
.cfg_link_control_aspm_control ( ),
.cfg_link_control_auto_bandwidth_int_en ( ),
.cfg_link_control_bandwidth_int_en ( ),
.cfg_link_control_clock_pm_en ( ),
.cfg_link_control_common_clock ( ),
.cfg_link_control_extended_sync ( ),
.cfg_link_control_hw_auto_width_dis ( ),
.cfg_link_control_link_disable ( ),
.cfg_link_control_retrain_link ( ),
.cfg_link_status_auto_bandwidth_status ( ),
.cfg_link_status_bandwidth_status ( ),
.cfg_link_status_current_speed ( ),
.cfg_link_status_dll_active ( ),
.cfg_link_status_link_training ( ),
.cfg_link_status_negotiated_width ( ),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a ),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b ),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c ),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d ),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a ),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b ),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c ),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d ),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor ),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal ),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal ),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak ),
.cfg_msg_received_pme_to ( ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack ),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme ),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit ),
.cfg_msg_received_unlock ( ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_pm_rcv_as_req_l1_n ( ),
.cfg_pm_rcv_enter_l1_n ( ),
.cfg_pm_rcv_enter_l23_n ( ),
.cfg_pm_rcv_req_ack_n ( ),
.cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ),
.cfg_slot_control_electromech_il_ctl_pulse ( cfg_slot_control_electromech_il_ctl_pulse ),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en ),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en ),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en ),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( cfg_aer_rooterr_non_fatal_err_reporting_en ),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en ),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received ),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received ),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( ),
.cfg_transaction_addr ( ),
.cfg_transaction_type ( ),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map ),
.cfg_mgmt_byte_en_n ( ~cfg_mgmt_byte_en ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( ~cfg_err_cor ),
.cfg_err_cpl_abort_n ( ~cfg_err_cpl_abort ),
.cfg_err_cpl_timeout_n ( ~cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect_n ( ~cfg_err_cpl_unexpect ),
.cfg_err_ecrc_n ( ~cfg_err_ecrc ),
.cfg_err_locked_n ( ~cfg_err_locked ),
.cfg_err_posted_n ( ~cfg_err_posted ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( ~cfg_err_ur ),
.cfg_err_malformed_n ( ~cfg_err_malformed ),
.cfg_err_poisoned_n ( ~cfg_err_poisoned ),
.cfg_err_atomic_egress_blocked_n ( ~cfg_err_atomic_egress_blocked ),
.cfg_err_mc_blocked_n ( ~cfg_err_mc_blocked ),
.cfg_err_internal_uncor_n ( ~cfg_err_internal_uncor ),
.cfg_err_internal_cor_n ( ~cfg_err_internal_cor ),
.cfg_err_norecovery_n ( ~cfg_err_norecovery ),
.cfg_interrupt_assert_n ( ~cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( ~cfg_interrupt ),
.cfg_interrupt_stat_n ( ~cfg_interrupt_stat ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_pm_send_pme_to_n ( 1'b1 ),
.cfg_pm_wake_n ( ~cfg_pm_wake ),
.cfg_pm_halt_aspm_l0s_n ( ~cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1_n ( ~cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en_n ( ~cfg_pm_force_state_en),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( 3'b0 ),
.cfg_force_common_clock_off ( 1'b0 ),
.cfg_force_extended_sync_on ( 1'b0 ),
.cfg_port_number ( 8'b0 ),
.cfg_mgmt_rd_en_n ( ~cfg_mgmt_rd_en ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( ~cfg_mgmt_wr_en ),
.cfg_mgmt_wr_readonly_n ( ~cfg_mgmt_wr_readonly ),
.cfg_mgmt_wr_rw1c_as_rw_n ( ~cfg_mgmt_wr_rw1c_as_rw ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state_int ),
.pl_phy_lnk_up ( pl_phy_lnk_up_wire ),
.pl_received_hot_rst ( pl_received_hot_rst_wire ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( 1'b0 ),
.pl_directed_ltssm_new ( 6'b0 ),
.pl_directed_ltssm_stall ( 1'b0 ),
.pl_directed_change_done ( pl_directed_change_done ),
.phy_rdy_n ( phy_rdy_n ),
.dbg_sclr_a ( ),
.dbg_sclr_b ( ),
.dbg_sclr_c ( ),
.dbg_sclr_d ( ),
.dbg_sclr_e ( ),
.dbg_sclr_f ( ),
.dbg_sclr_g ( ),
.dbg_sclr_h ( ),
.dbg_sclr_i ( ),
.dbg_sclr_j ( ),
.dbg_sclr_k ( ),
.dbg_vec_a ( ),
.dbg_vec_b ( ),
.dbg_vec_c ( ),
.pl_dbg_vec ( ),
.trn_rdllp_data ( ),
.trn_rdllp_src_rdy ( ),
.dbg_mode ( ),
.dbg_sub_mode ( ),
.pl_dbg_mode ( ),
.drp_clk ( 1'b0 ),
.drp_do ( ),
.drp_rdy ( ),
.drp_addr ( 9'b0 ),
.drp_en ( 1'b0 ),
.drp_di ( 16'b0 ),
.drp_we ( 1'b0 ),
// Pipe Interface
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.pipe_rx0_polarity_gt ( pipe_rx0_polarity_gt ),
.pipe_rx1_polarity_gt ( pipe_rx1_polarity_gt ),
.pipe_rx2_polarity_gt ( pipe_rx2_polarity_gt ),
.pipe_rx3_polarity_gt ( pipe_rx3_polarity_gt ),
.pipe_rx4_polarity_gt ( pipe_rx4_polarity_gt ),
.pipe_rx5_polarity_gt ( pipe_rx5_polarity_gt ),
.pipe_rx6_polarity_gt ( pipe_rx6_polarity_gt ),
.pipe_rx7_polarity_gt ( pipe_rx7_polarity_gt ),
.pipe_tx_deemph_gt ( pipe_tx_deemph_gt ),
.pipe_tx_margin_gt ( pipe_tx_margin_gt ),
.pipe_tx_rate_gt ( pipe_tx_rate_gt ),
.pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det_gt ),
.pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_compliance_gt ( pipe_tx0_compliance_gt ),
.pipe_tx0_data_gt ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_gt ( pipe_tx0_powerdown_gt ),
.pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_compliance_gt ( pipe_tx1_compliance_gt ),
.pipe_tx1_data_gt ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_gt ( pipe_tx1_powerdown_gt ),
.pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_compliance_gt ( pipe_tx2_compliance_gt ),
.pipe_tx2_data_gt ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_gt ( pipe_tx2_powerdown_gt ),
.pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_compliance_gt ( pipe_tx3_compliance_gt ),
.pipe_tx3_data_gt ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_gt ( pipe_tx3_powerdown_gt ),
.pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_compliance_gt ( pipe_tx4_compliance_gt ),
.pipe_tx4_data_gt ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_gt ( pipe_tx4_powerdown_gt ),
.pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_compliance_gt ( pipe_tx5_compliance_gt ),
.pipe_tx5_data_gt ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_gt ( pipe_tx5_powerdown_gt ),
.pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_compliance_gt ( pipe_tx6_compliance_gt ),
.pipe_tx6_data_gt ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_gt ( pipe_tx6_powerdown_gt ),
.pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_compliance_gt ( pipe_tx7_compliance_gt ),
.pipe_tx7_data_gt ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_gt ( pipe_tx7_powerdown_gt ),
.pipe_rx0_chanisaligned_gt ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_gt ( pipe_rx0_data_gt ),
.pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_phy_status_gt ( pipe_rx0_phy_status_gt ),
.pipe_rx0_status_gt ( pipe_rx0_status_gt ),
.pipe_rx0_valid_gt ( pipe_rx0_valid_gt ),
.pipe_rx1_chanisaligned_gt ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_gt ( pipe_rx1_data_gt ),
.pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_phy_status_gt ( pipe_rx1_phy_status_gt ),
.pipe_rx1_status_gt ( pipe_rx1_status_gt ),
.pipe_rx1_valid_gt ( pipe_rx1_valid_gt ),
.pipe_rx2_chanisaligned_gt ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_gt ( pipe_rx2_data_gt ),
.pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_phy_status_gt ( pipe_rx2_phy_status_gt ),
.pipe_rx2_status_gt ( pipe_rx2_status_gt ),
.pipe_rx2_valid_gt ( pipe_rx2_valid_gt ),
.pipe_rx3_chanisaligned_gt ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_gt ( pipe_rx3_data_gt ),
.pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_phy_status_gt ( pipe_rx3_phy_status_gt ),
.pipe_rx3_status_gt ( pipe_rx3_status_gt ),
.pipe_rx3_valid_gt ( pipe_rx3_valid_gt ),
.pipe_rx4_chanisaligned_gt ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_gt ( pipe_rx4_data_gt ),
.pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_phy_status_gt ( pipe_rx4_phy_status_gt ),
.pipe_rx4_status_gt ( pipe_rx4_status_gt ),
.pipe_rx4_valid_gt ( pipe_rx4_valid_gt ),
.pipe_rx5_chanisaligned_gt ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_gt ( pipe_rx5_data_gt ),
.pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_phy_status_gt ( pipe_rx5_phy_status_gt ),
.pipe_rx5_status_gt ( pipe_rx5_status_gt ),
.pipe_rx5_valid_gt ( pipe_rx5_valid_gt ),
.pipe_rx6_chanisaligned_gt ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_gt ( pipe_rx6_data_gt ),
.pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_phy_status_gt ( pipe_rx6_phy_status_gt ),
.pipe_rx6_status_gt ( pipe_rx6_status_gt ),
.pipe_rx6_valid_gt ( pipe_rx6_valid_gt ),
.pipe_rx7_chanisaligned_gt ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_gt ( pipe_rx7_data_gt ),
.pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_phy_status_gt ( pipe_rx7_phy_status_gt ),
.pipe_rx7_status_gt ( pipe_rx7_status_gt ),
.pipe_rx7_valid_gt ( pipe_rx7_valid_gt )
);
//--------------------------------------------------------------------------------------------------------------------//
// **** Virtex7 GTX Wrapper **** //
// The Virtex7 GTX Wrapper includes the following: //
// 1) Virtex-7 GTX //
//--------------------------------------------------------------------------------------------------------------------//
// Selection of pipe_sim should instantiate both gt_top & gt_top_pipe_mode modules, If not selected then only gt_top//
// Printed the code such a way that bydefault it will keep gt_top and gt_top & gt_top_pipe_mode on pipe_sim mode //
//------------------------------------------------------------------------------------------------------------------//
generate
if (PIPE_SIM_MODE == "FALSE")
begin : gt_top
pcie_core_gt_top #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND )
) gt_top_i (
// pl ltssm
.pl_ltssm_state ( pl_ltssm_state_int ),
// Pipe Common Signals
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset ( 1'b0 ),
.pipe_tx_rate ( pipe_tx_rate_gt ),
.pipe_tx_deemph ( pipe_tx_deemph_gt ),
.pipe_tx_margin ( pipe_tx_margin_gt ),
.pipe_tx_swing ( 1'b0 ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt),
.pipe_rx0_data ( pipe_rx0_data_gt ),
.pipe_rx0_valid ( pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_status ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity ( pipe_rx0_polarity_gt ),
.pipe_tx0_compliance ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt),
.pipe_rx1_data ( pipe_rx1_data_gt ),
.pipe_rx1_valid ( pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_status ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity ( pipe_rx1_polarity_gt ),
.pipe_tx1_compliance ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt),
.pipe_rx2_data ( pipe_rx2_data_gt ),
.pipe_rx2_valid ( pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_status ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity ( pipe_rx2_polarity_gt ),
.pipe_tx2_compliance ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt),
.pipe_rx3_data ( pipe_rx3_data_gt ),
.pipe_rx3_valid ( pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_status ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity ( pipe_rx3_polarity_gt ),
.pipe_tx3_compliance ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt),
.pipe_rx4_data ( pipe_rx4_data_gt ),
.pipe_rx4_valid ( pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_status ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity ( pipe_rx4_polarity_gt ),
.pipe_tx4_compliance ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt),
.pipe_rx5_data ( pipe_rx5_data_gt ),
.pipe_rx5_valid ( pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_status ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity ( pipe_rx5_polarity_gt ),
.pipe_tx5_compliance ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt),
.pipe_rx6_data ( pipe_rx6_data_gt ),
.pipe_rx6_valid ( pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_status ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity ( pipe_rx6_polarity_gt ),
.pipe_tx6_compliance ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt),
.pipe_rx7_data ( pipe_rx7_data_gt ),
.pipe_rx7_valid ( pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_status ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity ( pipe_rx7_polarity_gt ),
.pipe_tx7_compliance ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ),
// PCI Express Signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
// Non PIPE Signals
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.phy_rdy_n ( phy_rdy_n ),
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT )
);
end
else
begin : gt_top
pcie_core_gt_top_pipe_mode #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND )
) gt_top_i (
// pl ltssm
.pl_ltssm_state ( pl_ltssm_state_int ),
// Pipe Common Signals
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset ( 1'b0 ),
.pipe_tx_rate ( pipe_tx_rate_gt ),
.pipe_tx_deemph ( pipe_tx_deemph_gt ),
.pipe_tx_margin ( pipe_tx_margin_gt ),
.pipe_tx_swing ( 1'b0 ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt),
.pipe_rx0_data ( pipe_rx0_data_gt ),
.pipe_rx0_valid ( pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_status ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity ( pipe_rx0_polarity_gt ),
.pipe_tx0_compliance ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt),
.pipe_rx1_data ( pipe_rx1_data_gt ),
.pipe_rx1_valid ( pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_status ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity ( pipe_rx1_polarity_gt ),
.pipe_tx1_compliance ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt),
.pipe_rx2_data ( pipe_rx2_data_gt ),
.pipe_rx2_valid ( pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_status ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity ( pipe_rx2_polarity_gt ),
.pipe_tx2_compliance ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt),
.pipe_rx3_data ( pipe_rx3_data_gt ),
.pipe_rx3_valid ( pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_status ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity ( pipe_rx3_polarity_gt ),
.pipe_tx3_compliance ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt),
.pipe_rx4_data ( pipe_rx4_data_gt ),
.pipe_rx4_valid ( pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_status ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity ( pipe_rx4_polarity_gt ),
.pipe_tx4_compliance ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt),
.pipe_rx5_data ( pipe_rx5_data_gt ),
.pipe_rx5_valid ( pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_status ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity ( pipe_rx5_polarity_gt ),
.pipe_tx5_compliance ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt),
.pipe_rx6_data ( pipe_rx6_data_gt ),
.pipe_rx6_valid ( pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_status ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity ( pipe_rx6_polarity_gt ),
.pipe_tx6_compliance ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt),
.pipe_rx7_data ( pipe_rx7_data_gt ),
.pipe_rx7_valid ( pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_status ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity ( pipe_rx7_polarity_gt ),
.pipe_tx7_compliance ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ),
// PCI Express Signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
// Non PIPE Signals
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.phy_rdy_n ( phy_rdy_n ),
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT )
);
end
endgenerate
endmodule |
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule |
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule |
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule |
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule |
module DE0_NANO_SOC_QSYS_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule |
module pcie_command_rec_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
almost_full,
empty,
almost_empty,
rd_data_count,
wr_data_count
);
input rst;
input wr_clk;
input rd_clk;
input [127 : 0] din;
input wr_en;
input rd_en;
output [127 : 0] dout;
output full;
output almost_full;
output empty;
output almost_empty;
output [3 : 0] rd_data_count;
output [3 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(128),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(128),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(1),
.C_HAS_ALMOST_FULL(1),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(32),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.ALMOST_FULL(almost_full),
.EMPTY(empty),
.ALMOST_EMPTY(almost_empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.WR_ACK(),
.OVERFLOW(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule |
module sky130_fd_sc_lp__decap_3 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__decap_3 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__decap base ();
endmodule |
module sky130_fd_sc_ms__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module
// ring and then returns the replies back
// to the core
//
//--------------------------------------------------
udp_reg_master #(
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH)
) udp_reg_master (
// Core register interface signals
.core_reg_req (reg_req),
.core_reg_ack (reg_ack),
.core_reg_rd_wr_L (reg_rd_wr_L),
.core_reg_addr (reg_addr),
.core_reg_rd_data (reg_rd_data),
.core_reg_wr_data (reg_wr_data),
// UDP register interface signals (output)
.reg_req_out (in_arb_in_reg_req),
.reg_ack_out (in_arb_in_reg_ack),
.reg_rd_wr_L_out (in_arb_in_reg_rd_wr_L),
.reg_addr_out (in_arb_in_reg_addr),
.reg_data_out (in_arb_in_reg_data),
.reg_src_out (in_arb_in_reg_src),
// UDP register interface signals (input)
.reg_req_in (udp_reg_req_in),
.reg_ack_in (udp_reg_ack_in),
.reg_rd_wr_L_in (udp_reg_rd_wr_L_in),
.reg_addr_in (udp_reg_addr_in),
.reg_data_in (udp_reg_data_in),
.reg_src_in (udp_reg_src_in),
//
.clk (clk),
.reset (reset)
);
endmodule |
module outputs)
wire [7:0] atom_a; // From q0 of ccx_arb_srcq.v, ...
wire [7:0] ctl_qsel0_a; // From q0 of ccx_arb_srcq.v, ...
wire [7:0] ctl_qsel1_a_l; // From q0 of ccx_arb_srcq.v, ...
wire [7:0] ctl_shift_a; // From q0 of ccx_arb_srcq.v, ...
// End of automatics
wire ccx_reset_l_d1,ccx_reset2_l_d1;
wire dbginit_d1;
// Global signals
//assign dbginit = ~dbginit_l;
assign dbginit_d1 = ~ccx_reset2_l_d1;
// reset flop
dffrl_async ff_rstl(
.din(reset_l),
.q(ccx_reset_l_d1),
.clk(rclk),
.se(se),
.rst_l(adbginit_l));
assign reset_d1 = ~ccx_reset_l_d1;
// dff dff_ccx_arb_dbginit(
// .din (dbginit),
// .q (dbginit_d1),
// .clk (rclk),
// .se (1'd0),
// .si (1'd0),
// .so ());
dffrl_async ff_rstl2(
.din(reset_l),
.q(ccx_reset2_l_d1),
.clk(rclk),
.se(se),
.rst_l(adbginit_l));
// Generate direction bit for use in setting priority direction for
// incoming request packets.
assign direction_in = ~direction | dbginit_d1;
dff_s #(1) dff_ccx_com_dir(
.din (direction_in),
.q (direction),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//Priority Encoder related logic
// Logic to generate selects for request mux
assign current_req_sel = ~req_pkt_empty & ~reset_d1;
assign fifo_req_sel = req_pkt_empty & (fifo_valid & ~input_req_sel_d1) & ~reset_d1;
assign input_req_sel = req_pkt_empty & ~(fifo_valid & ~input_req_sel_d1) | reset_d1;
//flop and drive data ready signal
dff_s #(1) dff_ccx_com_dr( //relocate this flop to ctl
.din (ccx_dest_data_rdy_a), //section.
.q (ccx_dest_data_rdy_x),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_atom_dr(
.din (ccx_dest_atom_a),
.q (ccx_dest_atom_x),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
// generate stall signal
dff_s dff_ccx_arb_stall1(
.din (stall1_q),
.q (stall1_a),
.clk (rclk),
.se (1'd0),
.si (1'd0),
.so ());
dff_s dff_ccx_arb_stall2(
.din (stall2_q),
.q (stall2_a),
.clk (rclk),
.se (1'd0),
.si (1'd0),
.so ());
assign stall_a = stall1_a | stall2_a;
dff_s dff_ccx_arb_inpsel(
.din (input_req_sel),
.q (input_req_sel_d1),
.clk (rclk),
.se (1'd0),
.si (1'd0),
.so ());
// FIFO related logic
// setup flops for control
// dff #(16) dff_ccx_com_fifo_vvecd1(
// .din (vvec_d1[15:0]),
// .q (vvec_d2[15:0]),
// .clk (rclk),
// .se (1'b0),
// .si (16'd0),
// .so ());
// dff #(16) dff_ccx_com_fifo_wrptrd1(
dff_s #(5) dff_ccx_com_fifo_wrptrd1(
.din (wrptr[4:0]),
.q (wrptr_d1[4:0]),
.clk (rclk),
.se (1'b0),
.si (5'd0),
.so ());
// dff #(16) dff_ccx_com_fifo_rdptrd1(
// .din (rdptr[15:0]),
dff_s #(5) dff_ccx_com_fifo_rdptrd1(
.din (rdptr_mux[4:0]),
.q (rdptr_d1[4:0]),
.clk (rclk),
.se (1'b0),
.si (5'd0),
.so ());
dff_s #(1) dff_ccx_com_fifo_wrend1(
.din (wr_en),
.q (wr_en_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_rdend1(
.din (rd_en),
.q (rd_en_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_emptyd1(
.din (fifo_empty_d1),
.q (fifo_empty_d2),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_bypassd1(
.din (fifo_bypass),
.q (fifo_bypass_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_fifoseld1(
.din (fifo_req_sel),
.q (fifo_req_sel_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(1) dff_ccx_com_fifo_currseld1(
.din (current_req_sel),
.q (current_req_sel_d1),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
dff_s #(5) dff_ccx_rdptr_incd1(
.din (rdptr_inc[4:0]),
.q (rdptr_inc_d1[4:0]),
.clk (rclk),
.se (1'b0),
.si (5'd0),
.so ());
//see if any valid requests in flopped request packet.
// assign inreg_req_vld_d1 = |(req_d1[9:0]) ;
//compute if valid read, write ops were performed in prev cycle
assign fifo_rd_vld_d1 = rd_en_d1 & ~fifo_bypass_d1 & fifo_req_sel_d1;
assign fifo_wr_vld_d1 = wr_en_d1 & ~(fifo_bypass_d1 & fifo_req_sel_d1);
//if valid read/write ops then compute new fifo state (vvec_d1)
// assign vvec_wr_update_d1[15:0] = fifo_wr_vld_d1 ? wrptr_d1[15:0] : 16'd0;
// assign vvec_rd_update_d1[15:0] = fifo_rd_vld_d1 ? rdptr_d1[15:0] : 16'd0;
// assign vvec_unq_d1[15:0] = (vvec_wr_update_d1[15:0] | (vvec_d2[15:0] & ~vvec_rd_update_d1[15:0]));
// assign vvec_d1[15:0] = reset_d1 ? 16'd0 : vvec_unq_d1[15:0];
//Determine if fifo is empty
// assign fifo_empty_d1 =~( |(vvec_d1[15:0]));
// need extra state to detect full(overflow) condition
//--------------------------------------------------------------------------------------------
// 0 1 2 3 4 5
//--------------------------------------------------------------------------------------------
// req=1 req=1 req=1 req=1
// wrptr=0 1 2 3 0 0
// rdptr=0 0 0 0 0 0
// (empty) (full) (full)
//--------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------
// 0 1 2 3 4 5
//--------------------------------------------------------------------------------------------
// spc_req=1 fifo wr fifo rd arb(pa) px1
// wrptr=0 wrptr=1
// rdptr=0 rdptr=0 rdptr=1
// rdptr_inc=1 rdptr_inc=2
//--------------------------------------------------------------------------------------------
assign fifo_empty_d1 = &(wrptr[4:0] ~^ rdptr_mux[4:0]);
assign fifo_empty_d1_l = ~fifo_empty_d1 ;
//Determine if data needs to be bypassed around flop array.
assign fifo_bypass = inreg_req_vld_d1 & fifo_empty_d1 ;
assign fifo_bypass_l = ~fifo_bypass;
//Determine if fifo contains valid request packet.
assign fifo_valid = inreg_req_vld_d1 | fifo_empty_d1_l;
//Compute new read and write pointers
// assign rdptr_inc[15:0] = {rdptr_d1[14:0],rdptr_d1[15]};
// assign wrptr_inc[15:0] = {wrptr_d1[14:0],wrptr_d1[15]};
// increment - rdptr + 1
assign rdptr_inc[0] = ~rdptr_mux[0];
assign rdptr_inc[1] = rdptr_mux[1] ^ rdptr_mux[0];
assign rdptr_inc[2] = (~&(rdptr_mux[1:0]) ~^ rdptr_mux[2]);
assign rdptr_inc[3] = (~&(rdptr_mux[2:0]) ~^ rdptr_mux[3]);
assign rdptr_inc[4] = (~&(rdptr_mux[3:0]) ~^ rdptr_mux[4]);
// increment - wrptr + 1
assign wrptr_inc[0] = ~wrptr_d1[0];
assign wrptr_inc[1] = wrptr_d1[1] ^ wrptr_d1[0];
assign wrptr_inc[2] = (~&(wrptr_d1[1:0]) ~^ wrptr_d1[2]);
assign wrptr_inc[3] = (~&(wrptr_d1[2:0]) ~^ wrptr_d1[3]);
assign wrptr_inc[4] = (~&(wrptr_d1[3:0]) ~^ wrptr_d1[4]);
// assign wrptr[15:0]=(fifo_empty_d2 & ~fifo_wr_vld_d1| reset_d1) ? {15'd0,1'b1} : (fifo_wr_vld_d1 ? wrptr_inc[15:0] : wrptr_d1[15:0]);
// assign rdptr[15:0]=(fifo_empty_d2 & ~fifo_wr_vld_d1 | reset_d1) ? {15'd0,1'b1} : (fifo_rd_vld_d1 ? rdptr_inc[15:0] : rdptr_d1[15:0]);
assign wrptr[4:0] = (fifo_empty_d2 & ~fifo_wr_vld_d1| reset_d1) ? 5'h0 : (fifo_wr_vld_d1 ? wrptr_inc[4:0] : wrptr_d1[4:0]);
// decode write pointer
assign wrptr_dcd[0] = (~wrptr[3] & ~wrptr[2] & ~wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[1] = (~wrptr[3] & ~wrptr[2] & ~wrptr[1] & wrptr[0]);
assign wrptr_dcd[2] = (~wrptr[3] & ~wrptr[2] & wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[3] = (~wrptr[3] & ~wrptr[2] & wrptr[1] & wrptr[0]);
assign wrptr_dcd[4] = (~wrptr[3] & wrptr[2] & ~wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[5] = (~wrptr[3] & wrptr[2] & ~wrptr[1] & wrptr[0]);
assign wrptr_dcd[6] = (~wrptr[3] & wrptr[2] & wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[7] = (~wrptr[3] & wrptr[2] & wrptr[1] & wrptr[0]);
assign wrptr_dcd[8] = ( wrptr[3] & ~wrptr[2] & ~wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[9] = ( wrptr[3] & ~wrptr[2] & ~wrptr[1] & wrptr[0]);
assign wrptr_dcd[10] = ( wrptr[3] & ~wrptr[2] & wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[11] = ( wrptr[3] & ~wrptr[2] & wrptr[1] & wrptr[0]);
assign wrptr_dcd[12] = ( wrptr[3] & wrptr[2] & ~wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[13] = ( wrptr[3] & wrptr[2] & ~wrptr[1] & wrptr[0]);
assign wrptr_dcd[14] = ( wrptr[3] & wrptr[2] & wrptr[1] & ~wrptr[0]);
assign wrptr_dcd[15] = ( wrptr[3] & wrptr[2] & wrptr[1] & wrptr[0]);
assign wrptr_l[15:0] = ~(wrptr_dcd[15:0]);
assign rdptr_mux[4:0]=(fifo_empty_d2 & ~fifo_wr_vld_d1 | reset_d1) ? 5'h0 : (fifo_rd_vld_d1 ? rdptr_inc_d1[4:0] : rdptr_d1[4:0]);
// decode read pointer
assign rdptr[0] = (~rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[1] = (~rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[2] = (~rdptr_mux[3] & ~rdptr_mux[2] & rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[3] = ~|rdptr[2:0];
assign rdptr_dcd_3 = (~rdptr_mux[3] & ~rdptr_mux[2] & rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[4] = (~rdptr_mux[3] & rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[5] = (~rdptr_mux[3] & rdptr_mux[2] & ~rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[6] = (~rdptr_mux[3] & rdptr_mux[2] & rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[7] = ~|rdptr[6:4];
assign rdptr_dcd_7 = (~rdptr_mux[3] & rdptr_mux[2] & rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[8] = ( rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[9] = ( rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[10] = ( rdptr_mux[3] & ~rdptr_mux[2] & rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[11] = ~|rdptr[10:8];
assign rdptr_dcd_11 = ( rdptr_mux[3] & ~rdptr_mux[2] & rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[12] = ( rdptr_mux[3] & rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[13] = ( rdptr_mux[3] & rdptr_mux[2] & ~rdptr_mux[1] & rdptr_mux[0]);
assign rdptr[14] = ( rdptr_mux[3] & rdptr_mux[2] & rdptr_mux[1] & ~rdptr_mux[0]);
assign rdptr[15] = ~|rdptr[14:12];
assign rdptr_dcd_15 = ( rdptr_mux[3] & rdptr_mux[2] & rdptr_mux[1] & rdptr_mux[0]);
assign fifo_sel15_12 = |({rdptr_dcd_15,rdptr[14:12]});
assign fifo_sel11_8 = |({rdptr_dcd_11,rdptr[10:8]});
assign fifo_sel7_4 = |({rdptr_dcd_7, rdptr[6:4]});
assign fifo_sel3_0 = |({rdptr_dcd_3, rdptr[2:0]});
//Determine if a valid write was performed in current cycle. - wrptr will not catch up w/ rdptr 'cos the req source stalls.
// assign wrap_wren = ~(|(wrptr_inc[15:0] & rdptr_d1[15:0])) | fifo_empty_d1;
assign wrap_wren = ~(&(wrptr[3:0] ~^ rdptr_mux[3:0]) & (wrptr_inc[4] ^ rdptr_inc[4])) | fifo_empty_d1;
assign wr_en = (inreg_req_vld_d1 & (fifo_req_sel_d1 | current_req_sel_d1)) & wrap_wren & ~reset_d1;
//Determine if valid read was performed in current cycle.
assign rd_en = fifo_empty_d1_l & ~reset_d1 ;
// ARB SRC Q LOGIC
/*
ccx_arb_srcq AUTO_TEMPLATE(
// Outputs
.qfull (qfull[@]),
.qsel0 (arb_dp_qsel0_a[@]),
.qsel1 (arb_dp_qsel1_a[@]),
.shift_x (arb_dp_shift_x[@]),
.shift_a (arb_ctl_shift_a[@]),
.q0_hold_a (arb_dp_q0_hold_a[@]),
.atom_a(atom_a[@]),
.ctl_qsel0_a (ctl_qsel0_a[@]),
.ctl_qsel1_a_l (ctl_qsel1_a_l[@]),
.ctl_shift_a (ctl_shift_a[@]),
// Inputs
.req_q (src@_arb_req_q),
.atom_q (src@_arb_atom_q),
.grant_a (grant_a[@]),
.reset_d1 (reset_d1));
*/
ccx_arb_srcq q0(/*AUTOINST*/
// Outputs
.qfull (qfull[0]), // Templated
.qsel0 (arb_dp_qsel0_a[0]), // Templated
.qsel1 (arb_dp_qsel1_a[0]), // Templated
.shift_x (arb_dp_shift_x[0]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[0]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[0]), // Templated
.ctl_shift_a (ctl_shift_a[0]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[0]), // Templated
.atom_a (atom_a[0]), // Templated
// Inputs
.req_q (src0_arb_req_q), // Templated
.atom_q (src0_arb_atom_q), // Templated
.grant_a (grant_a[0]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q1(/*AUTOINST*/
// Outputs
.qfull (qfull[1]), // Templated
.qsel0 (arb_dp_qsel0_a[1]), // Templated
.qsel1 (arb_dp_qsel1_a[1]), // Templated
.shift_x (arb_dp_shift_x[1]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[1]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[1]), // Templated
.ctl_shift_a (ctl_shift_a[1]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[1]), // Templated
.atom_a (atom_a[1]), // Templated
// Inputs
.req_q (src1_arb_req_q), // Templated
.atom_q (src1_arb_atom_q), // Templated
.grant_a (grant_a[1]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q2(/*AUTOINST*/
// Outputs
.qfull (qfull[2]), // Templated
.qsel0 (arb_dp_qsel0_a[2]), // Templated
.qsel1 (arb_dp_qsel1_a[2]), // Templated
.shift_x (arb_dp_shift_x[2]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[2]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[2]), // Templated
.ctl_shift_a (ctl_shift_a[2]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[2]), // Templated
.atom_a (atom_a[2]), // Templated
// Inputs
.req_q (src2_arb_req_q), // Templated
.atom_q (src2_arb_atom_q), // Templated
.grant_a (grant_a[2]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q3(/*AUTOINST*/
// Outputs
.qfull (qfull[3]), // Templated
.qsel0 (arb_dp_qsel0_a[3]), // Templated
.qsel1 (arb_dp_qsel1_a[3]), // Templated
.shift_x (arb_dp_shift_x[3]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[3]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[3]), // Templated
.ctl_shift_a (ctl_shift_a[3]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[3]), // Templated
.atom_a (atom_a[3]), // Templated
// Inputs
.req_q (src3_arb_req_q), // Templated
.atom_q (src3_arb_atom_q), // Templated
.grant_a (grant_a[3]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q4(/*AUTOINST*/
// Outputs
.qfull (qfull[4]), // Templated
.qsel0 (arb_dp_qsel0_a[4]), // Templated
.qsel1 (arb_dp_qsel1_a[4]), // Templated
.shift_x (arb_dp_shift_x[4]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[4]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[4]), // Templated
.ctl_shift_a (ctl_shift_a[4]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[4]), // Templated
.atom_a (atom_a[4]), // Templated
// Inputs
.req_q (src4_arb_req_q), // Templated
.atom_q (src4_arb_atom_q), // Templated
.grant_a (grant_a[4]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q5(/*AUTOINST*/
// Outputs
.qfull (qfull[5]), // Templated
.qsel0 (arb_dp_qsel0_a[5]), // Templated
.qsel1 (arb_dp_qsel1_a[5]), // Templated
.shift_x (arb_dp_shift_x[5]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[5]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[5]), // Templated
.ctl_shift_a (ctl_shift_a[5]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[5]), // Templated
.atom_a (atom_a[5]), // Templated
// Inputs
.req_q (src5_arb_req_q), // Templated
.atom_q (src5_arb_atom_q), // Templated
.grant_a (grant_a[5]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q6(/*AUTOINST*/
// Outputs
.qfull (qfull[6]), // Templated
.qsel0 (arb_dp_qsel0_a[6]), // Templated
.qsel1 (arb_dp_qsel1_a[6]), // Templated
.shift_x (arb_dp_shift_x[6]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[6]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[6]), // Templated
.ctl_shift_a (ctl_shift_a[6]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[6]), // Templated
.atom_a (atom_a[6]), // Templated
// Inputs
.req_q (src6_arb_req_q), // Templated
.atom_q (src6_arb_atom_q), // Templated
.grant_a (grant_a[6]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
ccx_arb_srcq q7(/*AUTOINST*/
// Outputs
.qfull (qfull[7]), // Templated
.qsel0 (arb_dp_qsel0_a[7]), // Templated
.qsel1 (arb_dp_qsel1_a[7]), // Templated
.shift_x (arb_dp_shift_x[7]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[7]), // Templated
.ctl_qsel1_a_l (ctl_qsel1_a_l[7]), // Templated
.ctl_shift_a (ctl_shift_a[7]), // Templated
.q0_hold_a (arb_dp_q0_hold_a[7]), // Templated
.atom_a (atom_a[7]), // Templated
// Inputs
.req_q (src7_arb_req_q), // Templated
.atom_q (src7_arb_atom_q), // Templated
.grant_a (grant_a[7]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1)); // Templated
/*
// queue to hold atomic bit - 8 instances of 2 deep entries
ccx_arb_atomq AUTO_TEMPLATE(
// Outputs
.q0_dataout(arbctl_atom[@]),
// Inputs
.ctl_qsel0_a (ctl_qsel0_a[@]),
.ctl_qsel1_a_l (ctl_qsel1_a_l[@]),
.ctl_shift_a (ctl_shift_a[@]),
.atom_a(atom_a[@]));
*/
ccx_arb_atomq atomq0(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[0]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[0]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[0]), // Templated
.ctl_shift_a (ctl_shift_a[0]), // Templated
.atom_a (atom_a[0]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq1(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[1]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[1]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[1]), // Templated
.ctl_shift_a (ctl_shift_a[1]), // Templated
.atom_a (atom_a[1]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq2(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[2]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[2]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[2]), // Templated
.ctl_shift_a (ctl_shift_a[2]), // Templated
.atom_a (atom_a[2]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq3(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[3]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[3]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[3]), // Templated
.ctl_shift_a (ctl_shift_a[3]), // Templated
.atom_a (atom_a[3]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq4(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[4]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[4]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[4]), // Templated
.ctl_shift_a (ctl_shift_a[4]), // Templated
.atom_a (atom_a[4]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq5(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[5]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[5]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[5]), // Templated
.ctl_shift_a (ctl_shift_a[5]), // Templated
.atom_a (atom_a[5]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq6(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[6]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[6]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[6]), // Templated
.ctl_shift_a (ctl_shift_a[6]), // Templated
.atom_a (atom_a[6]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
ccx_arb_atomq atomq7(/*AUTOINST*/
// Outputs
.q0_dataout (arbctl_atom[7]), // Templated
`ifdef FPGA_SYN
.scan_out (/*scan_out*/),
`else
.scan_out (scan_out),
`endif
// Inputs
.ctl_qsel1_a_l (ctl_qsel1_a_l[7]), // Templated
.ctl_qsel0_a (ctl_qsel0_a[7]), // Templated
.ctl_shift_a (ctl_shift_a[7]), // Templated
.atom_a (atom_a[7]), // Templated
.rclk (rclk),
.reset_d1 (reset_d1));
endmodule |
module sky130_fd_sc_hdll__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *)
input wire [0 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
output wire [0 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8]" *)
output wire [15 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2]" *)
output wire [3 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [63:0] [127:64]" *)
output wire [127 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [7:0] [15:8]" *)
output wire [15 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8]" *)
output wire [15 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2]" *)
output wire [3 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [63:0] [127:64]" *)
input wire [127 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_15_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H00000000c00000000000000000000000),
.C_M_AXI_ADDR_WIDTH(64'H0000000d0000001d),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000000),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000002),
.C_S_AXI_READ_ACCEPTANCE(32'H00000002),
.C_M_AXI_WRITE_ISSUING(64'H0000000200000008),
.C_M_AXI_READ_ISSUING(64'H0000000200000008),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module IN_FIFO (
ALMOSTEMPTY,
ALMOSTFULL,
EMPTY,
FULL,
Q0,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7,
Q8,
Q9,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
RDCLK,
RDEN,
RESET,
WRCLK,
WREN
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter integer ALMOST_EMPTY_VALUE = 1;
parameter integer ALMOST_FULL_VALUE = 1;
parameter ARRAY_MODE = "ARRAY_MODE_4_X_8";
parameter SYNCHRONOUS_MODE = "FALSE";
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam out_delay = 10;
`endif
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
localparam MODULE_NAME = "IN_FIFO";
output ALMOSTEMPTY;
output ALMOSTFULL;
output EMPTY;
output FULL;
output [7:0] Q0;
output [7:0] Q1;
output [7:0] Q2;
output [7:0] Q3;
output [7:0] Q4;
output [7:0] Q5;
output [7:0] Q6;
output [7:0] Q7;
output [7:0] Q8;
output [7:0] Q9;
input RDCLK;
input RDEN;
input RESET;
input WRCLK;
input WREN;
input [3:0] D0;
input [3:0] D1;
input [3:0] D2;
input [3:0] D3;
input [3:0] D4;
input [3:0] D7;
input [3:0] D8;
input [3:0] D9;
input [7:0] D5;
input [7:0] D6;
reg [0:0] ARRAY_MODE_BINARY;
reg [0:0] SLOW_RD_CLK_BINARY;
reg [0:0] SLOW_WR_CLK_BINARY;
reg [0:0] SYNCHRONOUS_MODE_BINARY;
reg [3:0] SPARE_BINARY;
reg [7:0] ALMOST_EMPTY_VALUE_BINARY;
reg [7:0] ALMOST_FULL_VALUE_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (ALMOST_EMPTY_VALUE)
1 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_EMPTY_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_EMPTY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_EMPTY_VALUE);
#1 $finish;
end
endcase
case (ALMOST_FULL_VALUE)
1 : ALMOST_FULL_VALUE_BINARY <= 8'b01000001;
2 : ALMOST_FULL_VALUE_BINARY <= 8'b01100011;
default : begin
$display("Attribute Syntax Error : The Attribute ALMOST_FULL_VALUE on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALMOST_FULL_VALUE);
#1 $finish;
end
endcase
case (ARRAY_MODE)
"ARRAY_MODE_4_X_8" : ARRAY_MODE_BINARY <= 1'b1;
"ARRAY_MODE_4_X_4" : ARRAY_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ARRAY_MODE on %s instance %m is set to %s. Legal values for this attribute are ARRAY_MODE_4_X_8 or ARRAY_MODE_4_X_4.", MODULE_NAME, ARRAY_MODE);
#1 $finish;
end
endcase
SLOW_RD_CLK_BINARY <= 1'b0;
SLOW_WR_CLK_BINARY <= 1'b0;
SPARE_BINARY <= 4'b0;
case (SYNCHRONOUS_MODE)
"FALSE" : SYNCHRONOUS_MODE_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SYNCHRONOUS_MODE on %s instance %m is set to %s. The legal value for this attribute is FALSE.", MODULE_NAME, SYNCHRONOUS_MODE);
#1 $finish;
end
endcase
end
wire [7:0] delay_Q0;
wire [7:0] delay_Q1;
wire [7:0] delay_Q2;
wire [7:0] delay_Q3;
wire [7:0] delay_Q4;
wire [7:0] delay_Q5;
wire [7:0] delay_Q6;
wire [7:0] delay_Q7;
wire [7:0] delay_Q8;
wire [7:0] delay_Q9;
wire delay_ALMOSTEMPTY;
wire delay_ALMOSTFULL;
wire delay_EMPTY;
wire delay_FULL;
wire [3:0] delay_SCANOUT;
wire [3:0] delay_D0;
wire [3:0] delay_D1;
wire [3:0] delay_D2;
wire [3:0] delay_D3;
wire [3:0] delay_D4;
wire [3:0] delay_D7;
wire [3:0] delay_D8;
wire [3:0] delay_D9;
wire [7:0] delay_D5;
wire [7:0] delay_D6;
wire delay_RDCLK;
wire delay_RDEN;
wire delay_RESET;
wire delay_SCANENB = 1'b1;
wire delay_TESTMODEB = 1'b1;
wire delay_TESTREADDISB = 1'b1;
wire delay_TESTWRITEDISB = 1'b1;
wire [3:0] delay_SCANIN = 4'hf;
wire delay_WRCLK;
wire delay_WREN;
wire delay_GSR;
assign #(out_delay) ALMOSTEMPTY = delay_ALMOSTEMPTY;
assign #(out_delay) ALMOSTFULL = delay_ALMOSTFULL;
assign #(out_delay) EMPTY = delay_EMPTY;
assign #(out_delay) FULL = delay_FULL;
assign #(out_delay) Q0 = delay_Q0;
assign #(out_delay) Q1 = delay_Q1;
assign #(out_delay) Q2 = delay_Q2;
assign #(out_delay) Q3 = delay_Q3;
assign #(out_delay) Q4 = delay_Q4;
assign #(out_delay) Q5 = delay_Q5;
assign #(out_delay) Q6 = delay_Q6;
assign #(out_delay) Q7 = delay_Q7;
assign #(out_delay) Q8 = delay_Q8;
assign #(out_delay) Q9 = delay_Q9;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_RDCLK = RDCLK;
assign #(INCLK_DELAY) delay_WRCLK = WRCLK;
assign #(in_delay) delay_D0 = D0;
assign #(in_delay) delay_D1 = D1;
assign #(in_delay) delay_D2 = D2;
assign #(in_delay) delay_D3 = D3;
assign #(in_delay) delay_D4 = D4;
assign #(in_delay) delay_D5 = D5;
assign #(in_delay) delay_D6 = D6;
assign #(in_delay) delay_D7 = D7;
assign #(in_delay) delay_D8 = D8;
assign #(in_delay) delay_D9 = D9;
assign #(in_delay) delay_RDEN = RDEN;
`endif
assign #(in_delay) delay_RESET = RESET;
`ifndef XIL_TIMING
assign #(in_delay) delay_WREN = WREN;
`endif
assign delay_GSR = GSR;
SIP_IN_FIFO IN_FIFO_INST
(
.ALMOST_EMPTY_VALUE (ALMOST_EMPTY_VALUE_BINARY),
.ALMOST_FULL_VALUE (ALMOST_FULL_VALUE_BINARY),
.ARRAY_MODE (ARRAY_MODE_BINARY),
.SLOW_RD_CLK (SLOW_RD_CLK_BINARY),
.SLOW_WR_CLK (SLOW_WR_CLK_BINARY),
.SPARE (SPARE_BINARY),
.SYNCHRONOUS_MODE (SYNCHRONOUS_MODE_BINARY),
.ALMOSTEMPTY (delay_ALMOSTEMPTY),
.ALMOSTFULL (delay_ALMOSTFULL),
.EMPTY (delay_EMPTY),
.FULL (delay_FULL),
.Q0 (delay_Q0),
.Q1 (delay_Q1),
.Q2 (delay_Q2),
.Q3 (delay_Q3),
.Q4 (delay_Q4),
.Q5 (delay_Q5),
.Q6 (delay_Q6),
.Q7 (delay_Q7),
.Q8 (delay_Q8),
.Q9 (delay_Q9),
.SCANOUT (delay_SCANOUT),
.D0 (delay_D0),
.D1 (delay_D1),
.D2 (delay_D2),
.D3 (delay_D3),
.D4 (delay_D4),
.D5 (delay_D5),
.D6 (delay_D6),
.D7 (delay_D7),
.D8 (delay_D8),
.D9 (delay_D9),
.RDCLK (delay_RDCLK),
.RDEN (delay_RDEN),
.RESET (delay_RESET),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.TESTMODEB (delay_TESTMODEB),
.TESTREADDISB (delay_TESTREADDISB),
.TESTWRITEDISB (delay_TESTWRITEDISB),
.WRCLK (delay_WRCLK),
.WREN (delay_WREN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,,, delay_RDCLK, delay_RDEN);
$setuphold (posedge WRCLK, negedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, negedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, negedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, negedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, negedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, negedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, negedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, negedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, negedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, negedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$setuphold (posedge WRCLK, posedge D0, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D0);
$setuphold (posedge WRCLK, posedge D1, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D1);
$setuphold (posedge WRCLK, posedge D2, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D2);
$setuphold (posedge WRCLK, posedge D3, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D3);
$setuphold (posedge WRCLK, posedge D4, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D4);
$setuphold (posedge WRCLK, posedge D5, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D5);
$setuphold (posedge WRCLK, posedge D6, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D6);
$setuphold (posedge WRCLK, posedge D7, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D7);
$setuphold (posedge WRCLK, posedge D8, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D8);
$setuphold (posedge WRCLK, posedge D9, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_D9);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,,, delay_WRCLK, delay_WREN);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (negedge RESET, 0:0:0, 0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (posedge RESET, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
( RDCLK *> ALMOSTEMPTY) = (10:10:10, 10:10:10);
( RDCLK *> EMPTY) = (10:10:10, 10:10:10);
( RDCLK *> Q0) = (10:10:10, 10:10:10);
( RDCLK *> Q1) = (10:10:10, 10:10:10);
( RDCLK *> Q2) = (10:10:10, 10:10:10);
( RDCLK *> Q3) = (10:10:10, 10:10:10);
( RDCLK *> Q4) = (10:10:10, 10:10:10);
( RDCLK *> Q5) = (10:10:10, 10:10:10);
( RDCLK *> Q6) = (10:10:10, 10:10:10);
( RDCLK *> Q7) = (10:10:10, 10:10:10);
( RDCLK *> Q8) = (10:10:10, 10:10:10);
( RDCLK *> Q9) = (10:10:10, 10:10:10);
( WRCLK *> ALMOSTFULL) = (10:10:10, 10:10:10);
( WRCLK *> FULL) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule |
module sky130_fd_sc_ls__or4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module pwm_capture(
pwm_input,clk,rst_n,enable,tx_start,tx_data,tx_complete,capture_tx_rst,bps_start_t
);
input pwm_input;
input clk;
input rst_n;
input enable;
input tx_complete;
input capture_tx_rst;
input bps_start_t;
output tx_start;
output[7:0] tx_data;
reg ready;
reg[31:0] counter;
reg[31:0] pos_counter;
reg[31:0] neg_counter;
reg[31:0] nextpos_counter;
reg[31:0] periodcounter;
reg[31:0] dutycyclecounter;
reg pos_counter_flag;
reg neg_counter_flag;
reg nextpos_counter_flag;
wire pos_btn;
wire neg_btn;
wire tx_end;
/*******************************************************************************
*counter
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n) begin
counter <= 'h0;
end
else if(enable) begin
counter <= (counter < 32'hFFFFFFFF) ? (counter + 1'b1) : 'h0 ;
end
end
/*******************************************************************************
*Instance
*********************************************************************************/
neg_capture neg_capture_instance(
.pwm_input(pwm_input),
.clk(clk),
.rst_n(rst_n),
.enable(enable),
.neg_btn(neg_btn)
);
pos_capture pos_capture_instance(
.pwm_input(pwm_input),
.clk(clk),
.rst_n(rst_n),
.enable(enable),
.pos_btn(pos_btn)
);
captuer_tx captuer_tx_instance(
.clk(clk),
.rst_n(rst_n),
.tx_start(tx_start),
.capture_ready(ready),
.periodcounter(periodcounter),
.dutycyclecounter(dutycyclecounter),
.tx_data(tx_data),
.tx_complete(tx_complete),
.capture_tx_rst(capture_tx_rst),
.tx_end(tx_end),
.bps_start_t(bps_start_t)
);
/*******************************************************************************
*Capture pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
pos_counter <= 'h0;
pos_counter_flag <= 'h0;
end
else if(pos_btn && (pos_counter_flag != 1'b1))begin
pos_counter <= counter;
pos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Capture neg counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
neg_counter <= 'h0;
neg_counter_flag <= 'h0;
end
else if(neg_btn && pos_counter_flag && (neg_counter_flag != 1'b1))begin
neg_counter <= counter;
neg_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Capture next pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
nextpos_counter <= 'h0;
nextpos_counter_flag <= 'h0;
end
else if(pos_btn && pos_counter_flag && neg_counter_flag && (nextpos_counter_flag != 1'b1))begin
nextpos_counter <= counter;
nextpos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Calculate the dutycycle
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
dutycyclecounter <= 'h0;
end
else if(neg_counter_flag && pos_counter_flag)begin
dutycyclecounter <= neg_counter - pos_counter;
end
end
/*******************************************************************************
*Calculate the period
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
periodcounter <= 'h0;
ready <= 'h0;
end
else if(neg_counter_flag && pos_counter_flag && nextpos_counter_flag)begin
periodcounter <= nextpos_counter - pos_counter;
ready <=(tx_end) ? 'h0:'h1;
end
end
endmodule |
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule |
module sky130_fd_sc_hdll__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module select_clk_buf #(
parameter BUFFER_TYPE = "BUFR" // to use clr
)(
output o,
input i,
input clr // for BUFR_only
);
generate
if (BUFFER_TYPE == "BUFG") BUFG clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFH") BUFH clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFR") BUFR clk1x_i (.O(o), .I(i), .CE(1'b1), .CLR(clr));
else if (BUFFER_TYPE == "BUFMR") BUFMR clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFIO") BUFIO clk1x_i (.O(o), .I(i));
else assign o = i;
endgenerate
endmodule |
module sky130_fd_sc_lp__srdlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule |
module butterfly3_32(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
input signed [27:0] i_8;
input signed [27:0] i_9;
input signed [27:0] i_10;
input signed [27:0] i_11;
input signed [27:0] i_12;
input signed [27:0] i_13;
input signed [27:0] i_14;
input signed [27:0] i_15;
input signed [27:0] i_16;
input signed [27:0] i_17;
input signed [27:0] i_18;
input signed [27:0] i_19;
input signed [27:0] i_20;
input signed [27:0] i_21;
input signed [27:0] i_22;
input signed [27:0] i_23;
input signed [27:0] i_24;
input signed [27:0] i_25;
input signed [27:0] i_26;
input signed [27:0] i_27;
input signed [27:0] i_28;
input signed [27:0] i_29;
input signed [27:0] i_30;
input signed [27:0] i_31;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
output signed [27:0] o_8;
output signed [27:0] o_9;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
output signed [27:0] o_16;
output signed [27:0] o_17;
output signed [27:0] o_18;
output signed [27:0] o_19;
output signed [27:0] o_20;
output signed [27:0] o_21;
output signed [27:0] o_22;
output signed [27:0] o_23;
output signed [27:0] o_24;
output signed [27:0] o_25;
output signed [27:0] o_26;
output signed [27:0] o_27;
output signed [27:0] o_28;
output signed [27:0] o_29;
output signed [27:0] o_30;
output signed [27:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [27:0] b_0;
wire signed [27:0] b_1;
wire signed [27:0] b_2;
wire signed [27:0] b_3;
wire signed [27:0] b_4;
wire signed [27:0] b_5;
wire signed [27:0] b_6;
wire signed [27:0] b_7;
wire signed [27:0] b_8;
wire signed [27:0] b_9;
wire signed [27:0] b_10;
wire signed [27:0] b_11;
wire signed [27:0] b_12;
wire signed [27:0] b_13;
wire signed [27:0] b_14;
wire signed [27:0] b_15;
wire signed [27:0] b_16;
wire signed [27:0] b_17;
wire signed [27:0] b_18;
wire signed [27:0] b_19;
wire signed [27:0] b_20;
wire signed [27:0] b_21;
wire signed [27:0] b_22;
wire signed [27:0] b_23;
wire signed [27:0] b_24;
wire signed [27:0] b_25;
wire signed [27:0] b_26;
wire signed [27:0] b_27;
wire signed [27:0] b_28;
wire signed [27:0] b_29;
wire signed [27:0] b_30;
wire signed [27:0] b_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_31;
assign b_1=i_1+i_30;
assign b_2=i_2+i_29;
assign b_3=i_3+i_28;
assign b_4=i_4+i_27;
assign b_5=i_5+i_26;
assign b_6=i_6+i_25;
assign b_7=i_7+i_24;
assign b_8=i_8+i_23;
assign b_9=i_9+i_22;
assign b_10=i_10+i_21;
assign b_11=i_11+i_20;
assign b_12=i_12+i_19;
assign b_13=i_13+i_18;
assign b_14=i_14+i_17;
assign b_15=i_15+i_16;
assign b_16=i_15-i_16;
assign b_17=i_14-i_17;
assign b_18=i_13-i_18;
assign b_19=i_12-i_19;
assign b_20=i_11-i_20;
assign b_21=i_10-i_21;
assign b_22=i_9-i_22;
assign b_23=i_8-i_23;
assign b_24=i_7-i_24;
assign b_25=i_6-i_25;
assign b_26=i_5-i_26;
assign b_27=i_4-i_27;
assign b_28=i_3-i_28;
assign b_29=i_2-i_29;
assign b_30=i_1-i_30;
assign b_31=i_0-i_31;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
assign o_8=enable?b_8:i_8;
assign o_9=enable?b_9:i_9;
assign o_10=enable?b_10:i_10;
assign o_11=enable?b_11:i_11;
assign o_12=enable?b_12:i_12;
assign o_13=enable?b_13:i_13;
assign o_14=enable?b_14:i_14;
assign o_15=enable?b_15:i_15;
assign o_16=enable?b_16:i_16;
assign o_17=enable?b_17:i_17;
assign o_18=enable?b_18:i_18;
assign o_19=enable?b_19:i_19;
assign o_20=enable?b_20:i_20;
assign o_21=enable?b_21:i_21;
assign o_22=enable?b_22:i_22;
assign o_23=enable?b_23:i_23;
assign o_24=enable?b_24:i_24;
assign o_25=enable?b_25:i_25;
assign o_26=enable?b_26:i_26;
assign o_27=enable?b_27:i_27;
assign o_28=enable?b_28:i_28;
assign o_29=enable?b_29:i_29;
assign o_30=enable?b_30:i_30;
assign o_31=enable?b_31:i_31;
endmodule |
module tb_adder_tree;
parameter WORD_SIZE = 8;
parameter BANK_SIZE = 4;
reg clk;
reg rst_n;
reg [WORD_SIZE*BANK_SIZE-1:0] in;
wire [(WORD_SIZE+1)*(BANK_SIZE/2)-1:0] out;
adder_tree
#(
.WORD_SIZE(WORD_SIZE),
.BANK_SIZE(BANK_SIZE)
) _adder_tree
(
.clk ( clk ) ,
.rst_n ( rst_n ) ,
.in ( in ) ,
.out ( out )
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_adder_tree.vcd");
$dumpvars(0, tb_adder_tree);
#1 rst_n<=1'bx;clk<=1'bx;in<=32'hxxxx_xxxx;
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;in<=0;
repeat(5) @(posedge clk);
rst_n<=1;
@(posedge clk);
in<={8'd1,8'd2,8'd3,8'd4};
repeat(2) @(posedge clk);
if(out !== {9'd3,9'd7})
$display("result == ", 9'd3, ", ", 9'd7, " expected but ", out[17:9], ", ", out[8:0]);
in<={8'd15,8'd255,8'd255,8'd255};
repeat(2) @(posedge clk);
if(out !== {9'd270,9'd510})
$display("result == ", 9'd270, ", ", 9'd510, " expected but ", out[17:9], ", ", out[8:0]);
repeat(5) @(posedge clk);
$finish(2);
end
endmodule |
module sky130_fd_sc_hd__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module ddr_des
#(
parameter CLKDV = 4
)(
input wire CLK2X,
input wire CLK,
input wire WCLK,
input wire IN,
output reg [CLKDV*4-1:0] OUT,
output wire [1:0] OUT_FAST
);
wire [1:0] DDRQ;
IDDR IDDR_inst (
.Q1(DDRQ[1]), // 1-bit output for positive edge of clock
.Q2(DDRQ[0]), // 1-bit output for negative edge of clock
.C(CLK2X), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(IN), // 1-bit DDR data input
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
assign OUT_FAST = DDRQ;
reg [1:0] DDRQ_DLY;
always@(posedge CLK2X)
DDRQ_DLY[1:0] <= DDRQ[1:0];
reg [3:0] DDRQ_DATA;
always@(posedge CLK2X)
DDRQ_DATA[3:0] <= {DDRQ_DLY[1:0], DDRQ[1:0]};
reg [3:0] DDRQ_DATA_BUF;
always@(posedge CLK2X)
DDRQ_DATA_BUF[3:0] <= DDRQ_DATA[3:0];
reg [3:0] DATA_IN;
always@(posedge CLK)
DATA_IN[3:0] <= DDRQ_DATA_BUF[3:0];
reg [CLKDV*4-1:0] DATA_IN_SR;
always@(posedge CLK)
DATA_IN_SR <= {DATA_IN_SR[CLKDV*4-5:0],DATA_IN[3:0]};
always@(posedge WCLK)
OUT <= DATA_IN_SR;
endmodule |
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc,
pmod_spi_cs,
pmod_spi_miso,
pmod_spi_clk,
pmod_spi_convst,
pmod_gpio);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
output pmod_spi_cs;
input pmod_spi_miso;
output pmod_spi_clk;
output pmod_spi_convst;
input pmod_gpio;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t),
.dio_i(gpio_o),
.dio_o(gpio_i),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.pmod_spi_cs (pmod_spi_cs),
.pmod_spi_miso (pmod_spi_miso),
.pmod_spi_clk (pmod_spi_clk),
.pmod_spi_convst (pmod_spi_convst),
.pmod_gpio (pmod_gpio));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[7:0],probe2[0:0],probe3[7:0]" */;
input clk;
input [0:0]probe0;
input [7:0]probe1;
input [0:0]probe2;
input [7:0]probe3;
endmodule |
module jt51_mmr(
input rst,
input clk, // P1
input [7:0] d_in,
input write,
input a0,
output reg busy,
// CT
output reg ct1,
output reg ct2,
// Noise
output reg ne,
output reg [4:0] nfrq,
// LFO
output reg [7:0] lfo_freq,
output reg [1:0] lfo_w,
output reg [6:0] lfo_amd,
output reg [6:0] lfo_pmd,
output reg lfo_rst,
// Timers
output reg [9:0] value_A,
output reg [7:0] value_B,
output reg load_A,
output reg load_B,
output reg enable_irq_A,
output reg enable_irq_B,
output reg clr_flag_A,
output reg clr_flag_B,
output reg clr_run_A,
output reg clr_run_B,
output reg set_run_A,
output reg set_run_B,
input overflow_A,
`ifdef TEST_SUPPORT
// Test
output reg test_eg,
output reg test_op0,
`endif
// REG
output [1:0] rl_I,
output [2:0] fb_II,
output [2:0] con_I,
output [6:0] kc_I,
output [5:0] kf_I,
output [2:0] pms_I,
output [1:0] ams_VII,
output [2:0] dt1_II,
output [3:0] mul_VI,
output [6:0] tl_VII,
output [1:0] ks_III,
output [4:0] arate_II,
output amsen_VII,
output [4:0] rate1_II,
output [1:0] dt2_I,
output [4:0] rate2_II,
output [3:0] d1l_I,
output [3:0] rrate_II,
output keyon_II,
output [1:0] cur_op,
output op31_no,
output op31_acc,
output zero,
output m1_enters,
output m2_enters,
output c1_enters,
output c2_enters,
// Operator
output use_prevprev1,
output use_internal_x,
output use_internal_y,
output use_prev2,
output use_prev1
);
reg [7:0] selected_register, din_latch;
reg up_clr;
reg up_rl, up_kc, up_kf, up_pms,
up_dt1, up_tl, up_ks, up_dt2,
up_d1l, up_keyon, up_amsen;
wire busy_reg;
`ifdef SIMULATION
reg mmr_dump;
`endif
parameter REG_TEST = 8'h01,
REG_TEST2 = 8'h02,
REG_KON = 8'h08,
REG_NOISE = 8'h0f,
REG_CLKA1 = 8'h10,
REG_CLKA2 = 8'h11,
REG_CLKB = 8'h12,
REG_TIMER = 8'h14,
REG_LFRQ = 8'h18,
REG_PMDAMD = 8'h19,
REG_CTW = 8'h1b,
REG_DUMP = 8'h1f;
reg csm;
always @(posedge clk) begin : memory_mapped_registers
if( rst ) begin
selected_register <= 8'h0;
busy <= 1'b0;
{ up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,
up_ks, up_amsen, up_dt2, up_d1l, up_keyon } <= 11'd0;
`ifdef TEST_SUPPORT
{ test_eg, test_op0 } <= 2'd0;
`endif
// timers
{ value_A, value_B } <= 18'd0;
{ clr_flag_B, clr_flag_A,
enable_irq_B, enable_irq_A, load_B, load_A } <= 6'd0;
{ clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'b1100;
up_clr <= 1'b0;
// LFO
{ lfo_amd, lfo_pmd } <= 14'h0;
lfo_freq <= 8'd0;
lfo_w <= 2'd0;
lfo_rst <= 1'b0;
{ ct2, ct1 } <= 2'd0;
csm <= 1'b0;
din_latch <= 8'd0;
`ifdef SIMULATION
mmr_dump <= 1'b0;
`endif
end else begin
// WRITE IN REGISTERS
if( write && !busy ) begin
busy <= 1'b1;
if( !a0 )
selected_register <= d_in;
else begin
din_latch <= d_in;
// Global registers
if( selected_register < 8'h20 ) begin
case( selected_register)
// registros especiales
REG_TEST: lfo_rst <= 1'b1; // regardless of d_in
`ifdef TEST_SUPPORT
REG_TEST2: { test_op0, test_eg } <= d_in[1:0];
`endif
REG_KON: up_keyon <= 1'b1;
REG_NOISE: { ne, nfrq } <= { d_in[7], d_in[4:0] };
REG_CLKA1: value_A[9:2]<= d_in;
REG_CLKA2: value_A[1:0]<= d_in[1:0];
REG_CLKB: value_B <= d_in;
REG_TIMER: begin
csm <= d_in[7];
{ clr_flag_B, clr_flag_A,
enable_irq_B, enable_irq_A,
load_B, load_A } <= d_in[5:0];
clr_run_A <= ~d_in[0];
set_run_A <= d_in[0];
clr_run_B <= ~d_in[1];
set_run_B <= d_in[1];
end
REG_LFRQ: lfo_freq <= d_in;
REG_PMDAMD: begin
if( !d_in[7] )
lfo_amd <= d_in[6:0];
else
lfo_pmd <= d_in[6:0];
end
REG_CTW: begin
{ ct2, ct1 } <= d_in[7:6];
lfo_w <= d_in[1:0];
end
`ifdef SIMULATION
REG_DUMP:
mmr_dump <= 1'b1;
`endif
endcase
end else
// channel registers
if( selected_register < 8'h40 ) begin
case( selected_register[4:3] )
2'h0: up_rl <= 1'b1;
2'h1: up_kc <= 1'b1;
2'h2: up_kf <= 1'b1;
2'h3: up_pms<= 1'b1;
endcase
end
else
// operator registers
begin
case( selected_register[7:5] )
3'h2: up_dt1 <= 1'b1;
3'h3: up_tl <= 1'b1;
3'h4: up_ks <= 1'b1;
3'h5: up_amsen <= 1'b1;
3'h6: up_dt2 <= 1'b1;
3'h7: up_d1l <= 1'b1;
endcase
end
end
end
else begin /* clear once-only bits */
`ifdef SIMULATION
mmr_dump <= 1'b0;
`endif
csm <= 1'b0;
lfo_rst <= 1'b0;
{ clr_flag_B, clr_flag_A, load_B, load_A } <= 4'd0;
{ clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'd0;
if( |{ up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,
up_ks, up_amsen, up_dt2, up_d1l, up_keyon } == 1'b0 )
busy <= busy_reg;
else
busy <= 1'b1;
if( busy_reg ) begin
up_clr <= 1'b1;
end
else begin
up_clr <= 1'b0;
if( up_clr )
{ up_rl, up_kc, up_kf, up_pms, up_dt1,
up_tl, up_ks, up_amsen, up_dt2, up_d1l,
up_keyon } <= 11'd0;
end
end
end
end
jt51_reg u_reg(
.rst ( rst ),
.clk ( clk ), // P1
.d_in ( din_latch ),
.up_rl ( up_rl ),
.up_kc ( up_kc ),
.up_kf ( up_kf ),
.up_pms ( up_pms ),
.up_dt1 ( up_dt1 ),
.up_tl ( up_tl ),
.up_ks ( up_ks ),
.up_amsen ( up_amsen ),
.up_dt2 ( up_dt2 ),
.up_d1l ( up_d1l ),
.up_keyon ( up_keyon ),
.op( selected_register[4:3] ), // operator to update
.ch( selected_register[2:0] ), // channel to update
.csm ( csm ),
.overflow_A ( overflow_A),
.busy ( busy_reg ),
.rl_I ( rl_I ),
.fb_II ( fb_II ),
.con_I ( con_I ),
.kc_I ( kc_I ),
.kf_I ( kf_I ),
.pms_I ( pms_I ),
.ams_VII ( ams_VII ),
.dt1_II ( dt1_II ),
.dt2_I ( dt2_I ),
.mul_VI ( mul_VI ),
.tl_VII ( tl_VII ),
.ks_III ( ks_III ),
.arate_II ( arate_II ),
.amsen_VII ( amsen_VII ),
.rate1_II ( rate1_II ),
.rate2_II ( rate2_II ),
.rrate_II ( rrate_II ),
.d1l_I ( d1l_I ),
.keyon_II ( keyon_II ),
.cur_op ( cur_op ),
.op31_no ( op31_no ),
.op31_acc ( op31_acc ),
.zero ( zero ),
.m1_enters ( m1_enters ),
.m2_enters ( m2_enters ),
.c1_enters ( c1_enters ),
.c2_enters ( c2_enters ),
// Operator
.use_prevprev1 ( use_prevprev1 ),
.use_internal_x ( use_internal_x ),
.use_internal_y ( use_internal_y ),
.use_prev2 ( use_prev2 ),
.use_prev1 ( use_prev1 )
);
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt_aux;
sep32_cnt u_sep32_cnt (.clk(clk), .zero(zero), .cnt(cnt_aux));
sep32 #(.width(2),.stg(1)) sep_rl (.clk(clk),.cnt(cnt_aux),.mixed( rl_I ));
sep32 #(.width(3),.stg(2)) sep_fb (.clk(clk),.cnt(cnt_aux),.mixed( fb_II ));
sep32 #(.width(3),.stg(1)) sep_con(.clk(clk),.cnt(cnt_aux),.mixed( con_I ));
sep32 #(.width(7),.stg(1)) sep_kc (.clk(clk),.cnt(cnt_aux),.mixed( kc_I ));
sep32 #(.width(6),.stg(1)) sep_kf (.clk(clk),.cnt(cnt_aux),.mixed( kf_I ));
sep32 #(.width(3),.stg(1)) sep_pms(.clk(clk),.cnt(cnt_aux),.mixed( pms_I ));
sep32 #(.width(2),.stg(7)) sep_ams(.clk(clk),.cnt(cnt_aux),.mixed( ams_VII ));
sep32 #(.width(3),.stg(2)) sep_dt1(.clk(clk),.cnt(cnt_aux),.mixed( dt1_II ));
sep32 #(.width(2),.stg(1)) sep_dt2(.clk(clk),.cnt(cnt_aux),.mixed( dt2_I ));
sep32 #(.width(4),.stg(6)) sep_mul(.clk(clk),.cnt(cnt_aux),.mixed( mul_VI ));
sep32 #(.width(7),.stg(7)) sep_tl (.clk(clk),.cnt(cnt_aux),.mixed( tl_VII ));
sep32 #(.width(2),.stg(3)) sep_ks (.clk(clk),.cnt(cnt_aux),.mixed( ks_III ));
sep32 #(.width(5),.stg(2)) sep_ar (.clk(clk),.cnt(cnt_aux),.mixed( arate_II ));
sep32 #(.width(1),.stg(7)) sep_ame(.clk(clk),.cnt(cnt_aux),.mixed( amsen_VII));
sep32 #(.width(5),.stg(2)) sep_dr1(.clk(clk),.cnt(cnt_aux),.mixed( rate1_II ));
sep32 #(.width(5),.stg(2)) sep_dr2(.clk(clk),.cnt(cnt_aux),.mixed( rate2_II ));
sep32 #(.width(4),.stg(2)) sep_rr (.clk(clk),.cnt(cnt_aux),.mixed( rrate_II ));
sep32 #(.width(4),.stg(1)) sep_d1l(.clk(clk),.cnt(cnt_aux),.mixed( d1l_I ));
`endif
endmodule |
module tb_layer_ctrl();
`include "include/mbus_func.v"
parameter LC_INT_DEPTH=13;
parameter LC_MEM_DEPTH=65536;
parameter LC_RF_DEPTH=256;
localparam BULK_MEM_CTRL_REG_IDX = 242;
localparam STREAM_CH0_REG0_IDX = 236;
localparam STREAM_CH0_REG1_IDX = 237;
localparam STREAM_CH0_REG2_IDX = 238;
localparam STREAM_CH1_REG0_IDX = 232;
localparam STREAM_CH1_REG1_IDX = 233;
localparam STREAM_CH1_REG2_IDX = 234;
reg clk, resetn;
wire SCLK;
// n0 connections
reg [LC_INT_DEPTH-1:0] n0_int_vector;
wire [LC_INT_DEPTH-1:0] n0_clr_int;
// end of n0 connections
// n1 connections
reg [LC_INT_DEPTH-1:0] n1_int_vector;
wire [LC_INT_DEPTH-1:0] n1_clr_int;
// end of n1 connections
// n2 connections
reg [LC_INT_DEPTH-1:0] n2_int_vector;
wire [LC_INT_DEPTH-1:0] n2_clr_int;
// end of n2 connections
// n3 connections
reg [LC_INT_DEPTH-1:0] n3_int_vector;
wire [LC_INT_DEPTH-1:0] n3_clr_int;
// end of n3 connections
// c0 connections
reg [`ADDR_WIDTH-1:0] c0_tx_addr;
reg [`DATA_WIDTH-1:0] c0_tx_data;
reg c0_tx_req, c0_priority, c0_tx_pend, c0_tx_resp_ack, c0_req_int;
wire c0_tx_ack, c0_tx_succ, c0_tx_fail;
wire [`ADDR_WIDTH-1:0] c0_rx_addr;
wire [`DATA_WIDTH-1:0] c0_rx_data;
wire c0_rx_req, c0_rx_fail, c0_rx_pend, c0_rx_broadcast;
reg c0_rx_ack;
wire c0_lc_pwr_on, c0_lc_release_clk, c0_lc_release_rst, c0_lc_release_iso;
// end of c0 connections
// connection between nodes
wire w_n0n1, w_n1n2, w_n2n3, w_n3c0, w_c0n0;
wire w_n0_clk_out, w_n1_clk_out, w_n2_clk_out, w_n3_clk_out;
// testbench variables
reg [31:0] rand_dat, rand_dat2;
reg [4:0] state;
reg [5:0] word_counter;
reg [7:0] rf_read_length;
reg [7:0] rf_addr;
reg [29:0] mem_addr;
reg mem_ptr_set;
reg [1:0] mem_access_state;
reg [7:0] relay_addr;
reg [29:0] mem_relay_loc;
reg [7:0] rf_relay_loc;
reg [3:0] dest_short_addr;
reg [23:0] rf_data;
reg [31:0] mem_data;
reg [19:0] mem_read_length;
reg [3:0] enum_short_addr;
reg [19:0] long_addr;
reg [1:0] layer_number;
reg [LC_INT_DEPTH-1:0] int_vec;
reg [31:0] mem_w_data;
reg [3:0] functional_id;
reg [23:0] rf_w_data;
reg [1:0] stream_channel;
integer handle;
integer task_counter;
localparam TB_PROC_UP = 0;
localparam TB_QUERY = 1;
localparam TB_ENUM = 2;
localparam TB_ALL_WAKEUP = 3;
localparam TB_RF_WRITE = 4;
localparam TB_RF_READ = 5;
localparam TB_MEM_WRITE = 6;
localparam TB_MEM_READ = 7;
localparam TB_SEL_SLEEP_FULL_PREFIX = 8;
localparam TB_ALL_SLEEP = 9;
localparam TB_ALL_SHORT_ADDR_INVALID = 10;
localparam TB_SINGLE_INTERRUPT = 11;
localparam TB_MULTIPLE_INTERRUPT = 12;
localparam TB_SINGLE_MEM_WRITE = 13;
localparam TB_ARBITRARY_CMD = 14;
localparam TB_SINGLE_RF_WRITE = 15;
localparam TB_SHORT_MEM_READ = 16;
localparam TB_STREAMING = 17;
localparam TX_WAIT = 31;
reg c0_auto_rx_ack;
layer_wrapper #(.ADDRESS(20'hbbbb0), .LC_INT_DEPTH(LC_INT_DEPTH)) layer0(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n0_int_vector),
.CLR_INT_EXTERNAL(n0_clr_int),
// mbus
.CLKIN(SCLK), .CLKOUT(w_n0_clk_out), .DIN(w_c0n0), .DOUT(w_n0n1));
layer_wrapper #(.ADDRESS(20'hbbbb1), .LC_INT_DEPTH(LC_INT_DEPTH)) layer1(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n1_int_vector),
.CLR_INT_EXTERNAL(n1_clr_int),
// mbus
.CLKIN(w_n0_clk_out), .CLKOUT(w_n1_clk_out), .DIN(w_n0n1), .DOUT(w_n1n2));
layer_wrapper #(.ADDRESS(20'hbbbb2), .LC_INT_DEPTH(LC_INT_DEPTH)) layer2(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n2_int_vector),
.CLR_INT_EXTERNAL(n2_clr_int),
// mbus
.CLKIN(w_n1_clk_out), .CLKOUT(w_n2_clk_out), .DIN(w_n1n2), .DOUT(w_n2n3));
layer_wrapper #(.ADDRESS(20'hbbbb2), .LC_INT_DEPTH(LC_INT_DEPTH)) layer3(
.CLK(clk), .RESETn(resetn),
.INT_VECTOR(n3_int_vector),
.CLR_INT_EXTERNAL(n3_clr_int),
// mbus
.CLKIN(w_n2_clk_out), .CLKOUT(w_n3_clk_out), .DIN(w_n2n3), .DOUT(w_n3c0));
mbus_ctrl_layer_wrapper #(.ADDRESS(20'haaaa0)) c0
(.CLK_EXT(clk), .CLKIN(w_n3_clk_out), .CLKOUT(SCLK), .RESETn(resetn), .DIN(w_n3c0), .DOUT(w_c0n0),
.TX_ADDR(c0_tx_addr), .TX_DATA(c0_tx_data), .TX_REQ(c0_tx_req), .TX_ACK(c0_tx_ack), .TX_PEND(c0_tx_pend), .TX_PRIORITY(c0_priority),
.RX_ADDR(c0_rx_addr), .RX_DATA(c0_rx_data), .RX_REQ(c0_rx_req), .RX_ACK(c0_rx_ack), .RX_FAIL(c0_rx_fail), .RX_PEND(c0_rx_pend),
.TX_SUCC(c0_tx_succ), .TX_FAIL(c0_tx_fail), .TX_RESP_ACK(c0_tx_resp_ack), .RX_BROADCAST(c0_rx_broadcast),
.LC_POWER_ON(c0_lc_pwr_on), .LC_RELEASE_CLK(c0_lc_release_clk), .LC_RELEASE_RST(c0_lc_release_rst), .LC_RELEASE_ISO(c0_lc_release_iso),
.REQ_INT(c0_req_int));
`include "tasks.v"
initial
begin
task_counter = 0;
clk = 0;
resetn = 1;
mem_addr = 0;
mem_ptr_set = 0;
mem_access_state = 0;
mem_data = 0;
mem_relay_loc = 0;
mem_read_length = 0;
rf_addr = 0;
rf_data = 0;
rf_read_length = 0;
rf_relay_loc = 0;
relay_addr = 0;
enum_short_addr = 4'h2;
long_addr = 20'haaaa0;
layer_number = 0;
int_vec = 0;
mem_w_data = 0;
functional_id = 0;
stream_channel = 0;
@ (posedge clk);
@ (posedge clk);
@ (posedge clk);
`SD resetn = 0;
@ (posedge clk);
@ (posedge clk);
`SD resetn = 1;
@ (posedge clk);
@ (posedge clk);
//VCD DUMP SECTION
//`ifdef APR
/*
`ifdef TASK4
$dumpfile("task4.vcd");
`elsif TASK5
$dumpfile("task5.vcd");
`endif
$dumpvars(0, tb_ulpb_node32);
*/
//`endif
//SDF ANNOTATION
`ifdef SYN
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer0.lc0);
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer1.lc0);
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer2.lc0);
$sdf_annotate("../syn/layer_ctrl_v2.dc.sdf", layer3.lc0);
`endif
/*
`elsif APR
$sdf_annotate("../apr/ulpb_ctrl_wrapper/ulpb_ctrl_wrapper.apr.sdf", c0);
$sdf_annotate("../apr/ulpb_node32_ab/ulpb_node32_ab.apr.sdf", n0);
$sdf_annotate("../apr/ulpb_node32_cd/ulpb_node32_cd.apr.sdf", n1);
$sdf_annotate("../apr/ulpb_node32_ef/ulpb_node32_ef.apr.sdf", n2);
`endif
*/
//************************
//TESTBENCH BEGINS
//Calls Tasks from tasks.v
//***********************
task0();
end // initial begin
//Changed to 400K for primetime calculations
always #1250 clk = ~clk;
`include "task_list.v"
always @ (posedge layer0.lc_pwr_on)
$fdisplay(handle, "N0 LC Sleep");
always @ (posedge layer1.lc_pwr_on)
$fdisplay(handle, "N1 LC Sleep");
always @ (posedge layer2.lc_pwr_on)
$fdisplay(handle, "N2 LC Sleep");
always @ (posedge layer3.lc_pwr_on)
$fdisplay(handle, "N3 LC Sleep");
always @ (posedge c0_lc_pwr_on)
$fdisplay(handle, "Processor Sleep");
always @ (negedge layer0.lc_pwr_on)
$fdisplay(handle, "N0 LC Wakeup");
always @ (negedge layer1.lc_pwr_on)
$fdisplay(handle, "N1 LC Wakeup");
always @ (negedge layer2.lc_pwr_on)
$fdisplay(handle, "N2 LC Wakeup");
always @ (negedge layer3.lc_pwr_on)
$fdisplay(handle, "N3 LC Wakeup");
always @ (negedge c0_lc_pwr_on)
$fdisplay(handle, "Processor Wakeup");
always @ (posedge clk or negedge resetn)
begin
if (~resetn)
begin
n0_int_vector <= 0;
n1_int_vector <= 0;
n2_int_vector <= 0;
n3_int_vector <= 0;
c0_tx_addr <= 0;
c0_tx_data <= 0;
c0_tx_pend <= 0;
c0_tx_req <= 0;
c0_priority <= 0;
c0_req_int <= 0;
c0_auto_rx_ack <= 1;
word_counter <= 0;
end
else
begin
if (c0_tx_ack) c0_tx_req <= 0;
if (c0_tx_fail & c0_tx_req) c0_tx_req <= 0;
end
end
// n0 interrupt control
wire [LC_INT_DEPTH-1:0] n0_int_clr_mask = (n0_clr_int & n0_int_vector);
always @ (posedge clk)
begin
if (n0_int_clr_mask)
n0_int_vector <= `SD (n0_int_vector & (~n0_int_clr_mask));
end
always @ (posedge layer0.rx_fail)
$fdisplay(handle, "N0 RX Fail");
always @ (posedge layer0.rx_req)
begin
$fdisplay(handle, "N0 RX Success");
//$fdisplay(handle, "N0 Data out =\t32'h%h", layer0.rx_data);
end
always @ (posedge layer0.tx_succ)
$fdisplay(handle, "N0 TX Success\n");
always @ (posedge layer0.tx_fail)
$fdisplay(handle, "N0 TX Fail\n");
// end of n0 interrupt control
// n1 interrupt control
wire [LC_INT_DEPTH-1:0] n1_int_clr_mask = (n1_clr_int & n1_int_vector);
always @ (posedge clk)
begin
if (n1_int_clr_mask)
n1_int_vector <= `SD (n1_int_vector & (~n1_int_clr_mask));
end
always @ (posedge layer1.rx_fail)
$fdisplay(handle, "N1 RX Fail");
always @ (posedge layer1.rx_req)
begin
$fdisplay(handle, "N1 RX Success");
//$fdisplay(handle, "N1 Data out =\t32'h%h", layer1.rx_data);
end
always @ (posedge layer1.tx_succ)
$fdisplay(handle, "N1 TX Success\n");
always @ (posedge layer1.tx_fail)
$fdisplay(handle, "N1 TX Fail\n");
// end of n1 interrupt control
// n2 interrupt control
wire [LC_INT_DEPTH-1:0] n2_int_clr_mask = (n2_clr_int & n2_int_vector);
always @ (posedge clk)
begin
if (n2_int_clr_mask)
n2_int_vector <= `SD (n2_int_vector & (~n2_int_clr_mask));
end
always @ (posedge layer2.rx_fail)
$fdisplay(handle, "N2 RX Fail");
always @ (posedge layer2.rx_req)
begin
$fdisplay(handle, "N2 RX Success");
//$fdisplay(handle, "N2 Data out =\t32'h%h", layer2.rx_data);
end
always @ (posedge layer2.tx_succ)
$fdisplay(handle, "N2 TX Success\n");
always @ (posedge layer2.tx_fail)
$fdisplay(handle, "N2 TX Fail\n");
// end of n2 interrupt control
// n3 interrupt control
wire [LC_INT_DEPTH-1:0] n3_int_clr_mask = (n3_clr_int & n3_int_vector);
always @ (posedge clk)
begin
if (n3_int_clr_mask)
n3_int_vector <= `SD (n3_int_vector & (~n3_int_clr_mask));
end
always @ (posedge layer3.rx_fail)
$fdisplay(handle, "N3 RX Fail");
always @ (posedge layer3.rx_req)
begin
$fdisplay(handle, "N3 RX Success");
//$fdisplay(handle, "N3 Data out =\t32'h%h", layer3.rx_data);
end
always @ (posedge layer3.tx_succ)
$fdisplay(handle, "N3 TX Success\n");
always @ (posedge layer3.tx_fail)
$fdisplay(handle, "N3 TX Fail\n");
// end of n3 interrupt control
// c0 rx tx ack control
always @ (negedge resetn)
begin
c0_rx_ack <= 0;
c0_tx_resp_ack <= 0;
end
always @ (posedge c0_rx_fail)
$fdisplay(handle, "C0 RX Fail");
always @ (posedge c0_rx_req)
begin
$fdisplay(handle, "C0 RX Success");
$fdisplay(handle, "C0 Data out =\t32'h%h", c0_rx_data);
end
always @ (posedge clk)
begin
if ((c0_rx_req | c0_rx_fail) & c0_auto_rx_ack)
`SD c0_rx_ack <= 1;
if (c0_rx_ack & (~c0_rx_req))
`SD c0_rx_ack <= 0;
if (c0_rx_ack & (~c0_rx_fail))
`SD c0_rx_ack <= 0;
end
always @ (posedge c0_tx_succ)
$fdisplay(handle, "C0 TX Success");
always @ (posedge c0_tx_fail)
$fdisplay(handle, "C0 TX Fail");
always @ (posedge clk)
begin
if (c0_tx_succ | c0_tx_fail)
`SD c0_tx_resp_ack <= 1;
if (c0_tx_resp_ack & (~c0_tx_succ))
`SD c0_tx_resp_ack <= 0;
if (c0_tx_resp_ack & (~c0_tx_fail))
`SD c0_tx_resp_ack <= 0;
end
// end of c0 rx, tx ack control
always @ (posedge clk or negedge resetn) begin
if (~resetn) begin
rand_dat <= 0;
rand_dat2 <= 0;
end
else begin
rand_dat <= $random;
rand_dat2 <= $random;
end
end
// RF Write output
wire [31:0] layer0_rf0_addr = log2long(layer0.rf0.LOAD) - 1;
wire [31:0] layer1_rf0_addr = log2long(layer1.rf0.LOAD) - 1;
wire [31:0] layer2_rf0_addr = log2long(layer2.rf0.LOAD) - 1;
wire [31:0] layer3_rf0_addr = log2long(layer3.rf0.LOAD) - 1;
genvar idx;
generate
for (idx=0; idx<LC_RF_DEPTH; idx = idx+1)
begin: rf_write
always @ (posedge layer0.rf0.LOAD[idx])
$fdisplay(handle, "Layer 0, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer0_rf0_addr[7:0], layer0.rf0.DIN);
always @ (posedge layer1.rf0.LOAD[idx])
$fdisplay(handle, "Layer 1, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer1_rf0_addr[7:0], layer1.rf0.DIN);
always @ (posedge layer2.rf0.LOAD[idx])
$fdisplay(handle, "Layer 2, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer2_rf0_addr[7:0], layer2.rf0.DIN);
always @ (posedge layer3.rf0.LOAD[idx])
$fdisplay(handle, "Layer 3, RF Write, Addr: 8'h%h,\tData: 24'h%h", layer3_rf0_addr[7:0], layer3.rf0.DIN);
end
endgenerate
// End of RF Write output
// MEM Write output
always @ (posedge layer0.mem0.MEM_ACK_OUT)
if (layer0.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 0, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer0.mem0.ADDR, layer0.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 0, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer0.mem0.ADDR, layer0.mem0.DATA_OUT);
always @ (posedge layer1.mem0.MEM_ACK_OUT)
if (layer1.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 1, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer1.mem0.ADDR, layer1.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 1, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer1.mem0.ADDR, layer1.mem0.DATA_OUT);
always @ (posedge layer2.mem0.MEM_ACK_OUT)
if (layer2.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 2, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer2.mem0.ADDR, layer2.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 2, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer2.mem0.ADDR, layer2.mem0.DATA_OUT);
always @ (posedge layer3.mem0.MEM_ACK_OUT)
if (layer3.mem0.MEM_WRITE)
$fdisplay(handle, "Layer 3, MEM Write, Addr: 30'h%h,\tData: 32'h%h", layer3.mem0.ADDR, layer3.mem0.DATA_IN);
else
$fdisplay(handle, "Layer 3, MEM Read, Addr: 30'h%h,\tData: 32'h%h", layer3.mem0.ADDR, layer3.mem0.DATA_OUT);
// End of MEM Write output
endmodule |
module sky130_fd_sc_hs__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule |
module sky130_fd_sc_hd__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module Top(clk, reset, Segment, AN, VGA_R, VGA_G, VGA_B, hsync, vsync, kbd_clk, kbd_data, LED);
input clk;
input reset;
input kbd_clk;
input kbd_data;
output [7: 0] Segment;
output [3: 0] AN;
output [2: 0] VGA_R, VGA_G;
output [1: 0] VGA_B;
output hsync, vsync;
output [7: 0] LED;
// slow clock down
reg [5: 0] cnt = 0;
always @(posedge clk) begin
cnt <= cnt + 1;
end
wire sclk = cnt[5];
// ===========
// Wishbone IO
// ===========
// Master
wire CPU_STB, CPU_ACK, CPU_WE;
wire [31: 0] CPU_Data_I, CPU_Data_O, CPU_Addr;
// Slave
wire [16: 0] slave_ACK, slave_STB, slave_WE;
wire [31: 0] slave_DAT_I, slave_ADDR;
wire [511: 0] slave_DAT_O;
// Slave members
wire Keyboard_ACK, VGA_ACK, seven_seg_ACK, Ram_ACK, Counter_ACK;
wire [31: 0] Keyboard_DAT_O, VGA_DAT_O, seven_seg_DAT_O, Ram_DAT_O, Counter_DAT_O;
wire Ram_STB = slave_STB[1];
wire seven_seg_STB = slave_STB[0];
wire VGA_STB = slave_STB[2];
wire Keyboard_STB = slave_STB[3];
wire Counter_STB = slave_STB[4];
// ==================
// Instruction Memory
// 32 bit * 16384
// ==================
wire [31: 0] pc;
wire [31: 0] inst;
Instruction_Memory im(
.a(pc >> 2),
.spo(inst)
);
CPU cpu(
.clk(sclk),
.reset(reset),
.inst(inst),
.Data_I(CPU_Data_I),
.pc(pc),
.Addr(CPU_Addr),
.Data_O(CPU_Data_O),
.WE(CPU_WE),
.ACK(CPU_ACK),
.STB(CPU_STB)
);
// Device signal address defination:
// 0: Ram
// 1: Seven seg
// 2: VGA
// 3: Keyboard
// 4: Counter
assign slave_ACK = {10'b0,Counter_ACK, Keyboard_ACK, VGA_ACK, Ram_ACK, seven_seg_ACK};
assign slave_DAT_O = {320'b0, Counter_DAT_O, Keyboard_DAT_O, VGA_DAT_O, Ram_DAT_O, seven_seg_DAT_O};
WB_intercon intercon(
.master_STB(CPU_STB),
.master_DAT_I(CPU_Data_O),
.master_DAT_O(CPU_Data_I),
.master_ACK(CPU_ACK),
.master_WE(CPU_WE),
.master_ADDR(CPU_Addr),
.slave_STB(slave_STB),
.slave_ACK(slave_ACK),
.slave_WE(slave_WE),
.slave_DAT_O(slave_DAT_I),
.slave_DAT_I(slave_DAT_O),
.slave_ADDR(slave_ADDR)
);
// ==============
// Ram
// 32 bit * 16384
// ==============
Ram_driver ram_driver(
.clk(sclk),
.Ram_STB(Ram_STB),
.Ram_ACK(Ram_ACK)
);
Ram ram(
.clka(clk),
.addra(slave_ADDR >> 2),
.dina(slave_DAT_I),
.wea(slave_WE & Ram_STB),
.douta(Ram_DAT_O)
);
Seven_seg seven_seg(
.clk(clk),
.reset(reset),
//.DAT_I(slave_DAT_I),
.DAT_I(pc),
.DAT_O(seven_seg_DAT_O),
//.STB(seven_seg_STB),
.STB(1),
.ACK(seven_seg_ACK),
.WE(slave_WE),
.Segment(Segment),
.AN(AN)
);
Counter counter(
.clk(clk),
.reset(reset),
.DAT_O(Counter_DAT_O),
.STB(Counter_STB),
.ACK(Counter_ACK)
);
// ===
// VGA
// ===
wire [9: 0] x_ptr, y_ptr;
wire [7: 0] color;
Video_card video_card(
.clk(sclk),
.reset(reset),
.x_ptr(x_ptr),
.y_ptr(y_ptr),
.color(color),
.DAT_I(slave_DAT_I),
.DAT_O(VGA_DAT_O),
.WE(slave_WE),
.STB(VGA_STB),
.ACK(VGA_ACK),
.ADDR(slave_ADDR >> 2)
);
Vga_dev vga_dev(
.clk(clk),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.color(color),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.x_ptr(x_ptr),
.y_ptr(y_ptr)
);
// ==========
// Keyboard
// ==========
wire [7: 0] Keyboard_Data;
wire Keyboard_ready_pulse;
Keyboard_driver keyboard_driver(
.clk(clk),
.reset(reset),
.ready_pulse(Keyboard_ready_pulse),
.Keyboard_Data(Keyboard_Data),
.ACK(Keyboard_ACK),
.STB(Keyboard_STB),
.DAT_O(Keyboard_DAT_O)
);
Keyboard_dev keyboard(
.clk(clk),
.reset(reset),
.kbd_clk(kbd_clk),
.kbd_data(kbd_data),
.Keyboard_Data(Keyboard_Data),
.ready_pulse(Keyboard_ready_pulse)
);
assign LED = Keyboard_Data;
endmodule |
module soc_system_leds (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule |
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule |
module sky130_fd_sc_hd__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule |
module baudgen(wren, rden, reset, din, clk, sclr, baud, dout);
input wren, rden, reset, clk, sclr;
input [7:0] din;
output baud;
output [7:0] dout;
*/
reg [7:0] control, dout;
reg [9:0] shift_out;
reg wr_baud, rd_baud, wr_fifo, rd_fifo, wr_control;
reg ld_shift, stop, count, finish, rd_shift, bittime;
reg [3:0] bittimer, bitcounter;
reg [1:0] nstate, pstate;
parameter PERIOD = 8'h1A;
wire [7:0] to_shift, dout_baud;
wire [9:0] shift;
wire baud, full, empty;
`define period 3'b000
`define TXreg 3'b001
`define control 3'b011
`define WAIT 2'b00
`define SHIFT1 2'b01
`define SHIFT2 2'b10
`define TXFULL control[0]
`define TXDONE control[1]
baudgen #(.PERIOD(PERIOD)) baud1(
.wren (wr_baud),
.rden (rd_baud),
.reset (reset),
.din (din),
.clk (clk),
.stop (stop),
.baud (baud),
.dout (dout_baud)
);
fifo fifo1(
.clk (clk),
.rst (reset),
.din (din),
.wr_en (wr_fifo),
.rd_en (rd_fifo),
.dout (to_shift),
.full (full),
.empty (empty)
);
// assign shift_in
assign shift = ({1'b1, to_shift, 1'b0});
assign txout = shift_out[0];
// shift register
always @(posedge clk or posedge reset) begin
if(reset)
shift_out <= 10'b1111111111;
else begin
if (rd_shift)begin
//txout = shift_out[0];
shift_out <= {1'b1, shift_out[9:1]};
end
if (ld_shift)
shift_out <= shift;
end
end
// control register
always @(posedge clk or posedge reset) begin
if(reset) begin
control[7:0] = 8'b00000001;
end
else begin
`TXFULL = full;
if(finish)
`TXDONE = 1;
if(wr_control)
`TXDONE = 0;
end
end
// address mux logic
always @* begin
wr_baud = 0;
wr_fifo = 0; wr_control = 0;
case(addr)
`period: begin
if(wren)
wr_baud = 1;
end
`TXreg: begin
if(wren)
wr_fifo = 1;
end
`control: begin
if(wren)
wr_control = 1;
end
endcase
end
// out mux
always @* begin
rd_baud = 0;
dout = 8'b00000000;
case(addr)
`period: begin
if(rden)
rd_baud = 1;
dout = dout_baud;
end
`control: begin
if(rden)
dout = control;
end
endcase
end
// bittimer
always @(posedge baud or posedge reset) begin
if(reset)
bittimer <= 4'b0000;
else begin
if(bittime)
bittimer <= bittimer + 1;
end
end
// bitcounter
always @(posedge clk or posedge reset) begin
if(reset)begin
bitcounter <= 4'b0000;
end
else begin
if(count)
bitcounter <= bitcounter + 1;
if(finish)
bitcounter <= 4'b0000;
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if (reset)
pstate <= `WAIT;
else
pstate <= nstate;
end
// fsm
always @* begin
rd_fifo = 0; ld_shift = 0;
stop = 0; count = 0; finish = 0;
bittime = 0; rd_shift = 0;
nstate = pstate;
case (pstate)
`WAIT: begin
stop = 1;
if(~empty) begin
stop = 0;
rd_fifo = 1;
ld_shift = 1;
nstate = `SHIFT1;
end
end
`SHIFT1: begin
if(bitcounter == 4'b1010) begin
nstate = `WAIT;
finish = 1;
end
else begin
if(baud)
nstate = `SHIFT2;
bittime = 1;
end
end
`SHIFT2: begin
bittime = 1;
if(~baud & (bittimer == 4'b0000)) begin
count = 1;
rd_shift = 1;
nstate = `SHIFT1;
end
end
endcase
end
endmodule |
module m26_rx #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter HEADER = 0,
parameter IDENTIFIER = 0
) (
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK_RX,
input wire MKD_RX,
input wire [1:0] DATA_RX,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire [31:0] TIMESTAMP,
output wire LOST_ERROR,
output wire INVALID,
output wire INVALID_FLAG
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
m26_rx_core #(
.ABUSWIDTH(ABUSWIDTH),
.IDENTIFIER(IDENTIFIER),
.HEADER(HEADER)
) i_m26_rx_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK_RX(CLK_RX),
.MKD_RX(MKD_RX),
.DATA_RX(DATA_RX),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.TIMESTAMP(TIMESTAMP),
.LOST_ERROR(LOST_ERROR),
.INVALID(INVALID),
.INVALID_FLAG(INVALID_FLAG)
);
endmodule |
module ascii (
input clk,
input scan_ready,
input [7:0] scan_code,
output [7:0] ascii
);
reg [7:0] r_ascii;
reg [1:0] scan_ready_edge_detect = 2'b00;
assign ascii = r_ascii;
//reg keyup = 0;
reg extended = 0;
reg shift = 0;
reg [1:0] caps = 2'b00;
wire caps_lock;
reg [7:0] code;
reg [7:0] key_code [2:0];
reg [1:0] key_mem_index = 2'b00;
reg [1:0] key_current_index = 2'b00;
reg key_clear = 0;
reg [7:0] current_code;
reg [7:0] break_code;
reg [7:0] state_code;
reg [2:0] state_reg = 2'b00;
// state machine parameters
parameter st_idle = 3'b000;
parameter st_code_1 = 3'b001;
parameter st_code_2 = 3'b010;
parameter st_code_3 = 3'b011;
parameter st_break = 3'b100;
parameter st_extended = 3'b101;
parameter st_ready = 3'b110;
assign caps_lock = caps[0]; // odd number of presses
// posedge of the ps2 clock
always @(posedge clk) begin
scan_ready_edge_detect <= {scan_ready_edge_detect[0], scan_ready};
end
always @(posedge clk) begin
case (state_reg)
st_idle:
begin
if (scan_ready_edge_detect == 2'b01) begin
current_code <= scan_code;
state_reg <= st_code_1;
end
end
st_code_1:
begin
state_code <= current_code;
state_reg <= st_code_2;
end
st_code_2:
begin
// break code
if (state_code == 8'hf0) begin
state_reg <= st_break;
end else begin
state_reg <= st_code_3;
end
end
st_code_3:
begin
state_reg <= st_ready;
end
st_break:
begin
// key up
code <= 8'h00;
if (scan_ready_edge_detect == 2'b01) begin
state_reg <= st_idle;
break_code <= scan_code;
end
end
st_extended:
begin
end
st_ready:
begin
code <= state_code;
state_reg <= st_idle;
end
default:
begin
end
endcase
end
// Caps lock
always @(posedge clk) begin
if (scan_ready_edge_detect == 2'b01 && code == 8'h58) begin
caps <= caps + 2'b1;
end
end
// LEFT SHIFT || RIGHT SHIFT
always @(posedge clk) begin
if (code == 8'h12 || code == 8'h59) begin
shift <= 1;
end else if (break_code == 8'h12 || break_code == 8'h59) begin
shift <= 0;
end
end
always @(posedge clk) begin
if (extended) begin
//extended <= 0;
case (code)
// nand2tetris special codes
8'h6b: r_ascii <= 8'd130; // L ARROW
8'h75: r_ascii <= 8'd131; // UP ARROW
8'h74: r_ascii <= 8'd132; // R ARROW
8'h72: r_ascii <= 8'd133; // DOWN ARROW
8'h6c: r_ascii <= 8'd134; // HOME
8'h69: r_ascii <= 8'd135; // END
8'h7d: r_ascii <= 8'd136; // PAGE UP
8'h7a: r_ascii <= 8'd137; // PAGE DOWN
8'h70: r_ascii <= 8'd138; // INSERT
8'h71: r_ascii <= 8'd139; // DELETE
default: r_ascii <= 8'd0; // null
endcase
end else
if ((shift && !caps_lock) || (caps_lock && !shift)) begin
case (code)
8'h29: r_ascii <= 8'd32; // [space]
8'h16: r_ascii <= 8'd33; // !
8'h52: r_ascii <= 8'd34; // "
8'h26: r_ascii <= 8'd35; // #
8'h25: r_ascii <= 8'd36; // $
8'h2e: r_ascii <= 8'd37; // %
8'h3d: r_ascii <= 8'd38; // &
8'h46: r_ascii <= 8'd40; // (
8'h45: r_ascii <= 8'd41; // )
8'h3e: r_ascii <= 8'd42; // *
8'h55: r_ascii <= 8'd43; // +
8'h4c: r_ascii <= 8'd58; // :
8'h41: r_ascii <= 8'd60; // <
8'h49: r_ascii <= 8'd62; // >
8'h4a: r_ascii <= 8'd63; // ?
8'h1e: r_ascii <= 8'd64; // @
8'h1c: r_ascii <= 8'd65; // A
8'h32: r_ascii <= 8'd66; // B
8'h21: r_ascii <= 8'd67; // C
8'h23: r_ascii <= 8'd68; // D
8'h24: r_ascii <= 8'd69; // E
8'h2b: r_ascii <= 8'd70; // F
8'h34: r_ascii <= 8'd71; // G
8'h33: r_ascii <= 8'd72; // H
8'h43: r_ascii <= 8'd73; // I
8'h3b: r_ascii <= 8'd74; // J
8'h42: r_ascii <= 8'd75; // K
8'h4b: r_ascii <= 8'd76; // L
8'h3a: r_ascii <= 8'd77; // M
8'h31: r_ascii <= 8'd78; // N
8'h44: r_ascii <= 8'd79; // O
8'h4d: r_ascii <= 8'd80; // P
8'h15: r_ascii <= 8'd81; // Q
8'h2d: r_ascii <= 8'd82; // R
8'h1b: r_ascii <= 8'd83; // S
8'h2c: r_ascii <= 8'd84; // T
8'h3c: r_ascii <= 8'd85; // U
8'h2a: r_ascii <= 8'd86; // V
8'h1d: r_ascii <= 8'd87; // W
8'h22: r_ascii <= 8'd88; // X
8'h35: r_ascii <= 8'd89; // Y
8'h1a: r_ascii <= 8'd90; // Z
8'h36: r_ascii <= 8'd94; // ^
8'h4e: r_ascii <= 8'd95; // _
8'h54: r_ascii <= 8'd123; // {
8'h5d: r_ascii <= 8'd124; // |
8'h5b: r_ascii <= 8'd125; // }
8'h0e: r_ascii <= 8'd126; // ~
default: r_ascii <= 8'd0; // null
endcase
end else begin
case (code)
8'h0d: r_ascii <= 8'd9; // [tab]
//8'h14: r_ascii <= L CTRL
//8'h11: r_ascii <= L ALT
//8'h7e: r_ascii <= SCROLL
//8'h77: r_ascii <= NUM
8'h29: r_ascii <= 8'd32; // [space]
8'h52: r_ascii <= 8'd39; // '
8'h7c: r_ascii <= 8'd42; // KP *
8'h79: r_ascii <= 8'd43; // KP +
8'h41: r_ascii <= 8'd44; // ,
8'h49: r_ascii <= 8'd46; // .
8'h71: r_ascii <= 8'd46; // KP .
8'h4e: r_ascii <= 8'd45; // -
8'h7b: r_ascii <= 8'd45; // KP -
8'h4a: r_ascii <= 8'd47; // /
8'h45: r_ascii <= 8'd48; // 0
8'h70: r_ascii <= 8'd48; // KP 0
8'h16: r_ascii <= 8'd49; // 1
8'h69: r_ascii <= 8'd49; // KP 1
8'h1e: r_ascii <= 8'd50; // 2
8'h72: r_ascii <= 8'd50; // KP 2
8'h26: r_ascii <= 8'd51; // 3
8'h7a: r_ascii <= 8'd51; // KP 3
8'h25: r_ascii <= 8'd52; // 4
8'h6b: r_ascii <= 8'd52; // KP 4
8'h2e: r_ascii <= 8'd53; // 5
8'h73: r_ascii <= 8'd53; // KP 5
8'h36: r_ascii <= 8'd54; // 6
8'h74: r_ascii <= 8'd54; // KP 6
8'h3d: r_ascii <= 8'd55; // 7
8'h6c: r_ascii <= 8'd55; // KP 7
8'h3e: r_ascii <= 8'd56; // 8
8'h75: r_ascii <= 8'd56; // KP 8
8'h46: r_ascii <= 8'd57; // 9
8'h7d: r_ascii <= 8'd57; // KP 9
8'h4c: r_ascii <= 8'd59; // ;
8'h55: r_ascii <= 8'd61; // =
8'h54: r_ascii <= 8'd91; // [
8'h5d: r_ascii <= 8'd92; // \
8'h5b: r_ascii <= 8'd93; // ]
8'h0e: r_ascii <= 8'd96; // `
8'h1c: r_ascii <= 8'd97; // a
8'h32: r_ascii <= 8'd98; // b
8'h21: r_ascii <= 8'd99; // c
8'h23: r_ascii <= 8'd100; // d
8'h24: r_ascii <= 8'd101; // e
8'h2b: r_ascii <= 8'd102; // f
8'h34: r_ascii <= 8'd103; // g
8'h33: r_ascii <= 8'd104; // h
8'h43: r_ascii <= 8'd105; // i
8'h3b: r_ascii <= 8'd106; // j
8'h42: r_ascii <= 8'd107; // k
8'h4b: r_ascii <= 8'd108; // l
8'h3a: r_ascii <= 8'd109; // m
8'h31: r_ascii <= 8'd110; // n
8'h44: r_ascii <= 8'd111; // o
8'h4d: r_ascii <= 8'd112; // p
8'h15: r_ascii <= 8'd113; // q
8'h2d: r_ascii <= 8'd114; // r
8'h1b: r_ascii <= 8'd115; // s
8'h2c: r_ascii <= 8'd116; // t
8'h3c: r_ascii <= 8'd117; // u
8'h2a: r_ascii <= 8'd118; // v
8'h1d: r_ascii <= 8'd119; // w
8'h22: r_ascii <= 8'd120; // x
8'h35: r_ascii <= 8'd121; // y
8'h1a: r_ascii <= 8'd122; // z
// nand2tetris special codes
8'h5a: r_ascii <= 8'd128; // [enter]
8'h66: r_ascii <= 8'd129; // [back space]
8'h76: r_ascii <= 8'd140; // ESCAPE
8'h05: r_ascii <= 8'd141; // F1
8'h06: r_ascii <= 8'd142; // F2
8'h04: r_ascii <= 8'd143; // F3
8'h0c: r_ascii <= 8'd144; // F4
8'h03: r_ascii <= 8'd145; // F5
8'h0b: r_ascii <= 8'd146; // F6
8'h83: r_ascii <= 8'd147; // F7
8'h0a: r_ascii <= 8'd148; // F8
8'h01: r_ascii <= 8'd149; // F9
8'h09: r_ascii <= 8'd150; // F10
8'h78: r_ascii <= 8'd151; // F11
8'h07: r_ascii <= 8'd152; // F12
default: r_ascii <= 8'd0; // null
endcase
end
end
endmodule |
module lmcnt
(
input CLK,
input RESET_X,
//cpu
input SOFT_RESET,
input START,
output reg FINISH,
input [1:0] MSEL_INPUTA_SEL,
input [1:0] MSEL_INPUTB_SEL,
input [1:0] MSEL_OUTPUTC_SEL,
input [9:0] M1POS,
input [9:0] M1SIZE,
input [9:0] M2POS,
input [9:0] M3POS,
//local mem
input [7:0] M0_RDATA,
output M1_WR,
output [9:0] M1_WADR,
output [7:0] M1_WDATA,
output [9:0] M1_RADR,
input [7:0] M1_RDATA,
output M2_WR,
output [9:0] M2_WADR,
output [7:0] M2_WDATA,
output [9:0] M2_RADR,
input [7:0] M2_RDATA,
output M3_WR,
output [9:0] M3_WADR,
output [7:0] M3_WDATA,
output [9:0] M3_RADR,
input [7:0] M3_RDATA,
//npu
output reg NPU_EN,
output reg [7:0] A_RDATA,
output reg [7:0] B_RDATA,
input LM_EN,
input [7:0] C_WDATA
);
wire rst_x;
assign rst_x = RESET_X & ~SOFT_RESET;
reg npu_en_r;
wire npu_en_w;
assign npu_en_w = START | npu_en_r;
reg [9:0] rcnt;
reg [9:0] wcnt;
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
rcnt <= 0;
end else begin
if ((rcnt == 0) && (START == 1))begin
rcnt <= 1;
end else if((rcnt != 0) && (rcnt != 10'h3FF))begin
rcnt <= rcnt + 1;
end
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
NPU_EN <= 0;
npu_en_r <= 0;
end else begin
NPU_EN <= npu_en_w;
if (START == 1)begin
npu_en_r <= 1;
end else if(rcnt == 10'h3FF)begin
npu_en_r <= 0;
end
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
wcnt <= 0;
end else begin
if(LM_EN)begin
wcnt <= wcnt + 1;
end
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
FINISH <= 0;
end else begin
if(wcnt == 10'h3FF)begin
FINISH <= 1;
end
end
end
//read
assign M1_RADR = rcnt;
assign M2_RADR = rcnt;
assign M3_RADR = rcnt;
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
A_RDATA <= 0;
end else begin
case (MSEL_INPUTA_SEL)
2'b00: A_RDATA <= M0_RDATA;
2'b01: A_RDATA <= M1_RDATA;
2'b10: A_RDATA <= M2_RDATA;
2'b11: A_RDATA <= M3_RDATA;
endcase // case (MSEL_INPUTA_SEL)
end
end
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0)begin
B_RDATA <= 0;
end else begin
case (MSEL_INPUTB_SEL)
2'b00: B_RDATA <= M0_RDATA;
2'b01: B_RDATA <= M1_RDATA;
2'b10: B_RDATA <= M2_RDATA;
2'b11: B_RDATA <= M3_RDATA;
endcase // case (MSEL_INPUTB_SEL)
end
end
//write
assign M1_WR = (MSEL_OUTPUTC_SEL == 2'b01) ? LM_EN : 0;
assign M2_WR = (MSEL_OUTPUTC_SEL == 2'b10) ? LM_EN : 0;
assign M3_WR = (MSEL_OUTPUTC_SEL == 2'b11) ? LM_EN : 0;
assign M1_WADR = wcnt;
assign M2_WADR = wcnt;
assign M3_WADR = wcnt;
assign M1_WDATA = C_WDATA;
assign M2_WDATA = C_WDATA;
assign M3_WDATA = C_WDATA;
endmodule |
module sky130_fd_sc_lp__nand3b_lp (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__nand3b_lp (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule |
module pcie_7x_v1_3_gt_top #
(
parameter LINK_CAP_MAX_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
parameter USER_CLK2_DIV2 = "FALSE", // "FALSE" => user_clk2 = user_clk
// "TRUE" => user_clk2 = user_clk/2, where user_clk = 500 or 250 MHz.
parameter integer USER_CLK_FREQ = 3, // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking
parameter PCIE_USE_MODE = "1.0" // 1.0 = K325T IES, 1.1 = VX485T IES, 3.0 = K325T GES
)
(
//-----------------------------------------------------------------------------------------------------------------//
// pl ltssm
input wire [5:0] pl_ltssm_state ,
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det ,
input wire pipe_tx_reset ,
input wire pipe_tx_rate ,
input wire pipe_tx_deemph ,
input wire [2:0] pipe_tx_margin ,
input wire pipe_tx_swing ,
//-----------------------------------------------------------------------------------------------------------------//
// Clock Inputs //
//-----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXUSRCLK_IN,
input PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k ,
output wire [15:0] pipe_rx0_data ,
output wire pipe_rx0_valid ,
output wire pipe_rx0_chanisaligned ,
output wire [ 2:0] pipe_rx0_status ,
output wire pipe_rx0_phy_status ,
output wire pipe_rx0_elec_idle ,
input wire pipe_rx0_polarity ,
input wire pipe_tx0_compliance ,
input wire [ 1:0] pipe_tx0_char_is_k ,
input wire [15:0] pipe_tx0_data ,
input wire pipe_tx0_elec_idle ,
input wire [ 1:0] pipe_tx0_powerdown ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k ,
output wire [15:0] pipe_rx1_data ,
output wire pipe_rx1_valid ,
output wire pipe_rx1_chanisaligned ,
output wire [ 2:0] pipe_rx1_status ,
output wire pipe_rx1_phy_status ,
output wire pipe_rx1_elec_idle ,
input wire pipe_rx1_polarity ,
input wire pipe_tx1_compliance ,
input wire [ 1:0] pipe_tx1_char_is_k ,
input wire [15:0] pipe_tx1_data ,
input wire pipe_tx1_elec_idle ,
input wire [ 1:0] pipe_tx1_powerdown ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k ,
output wire [15:0] pipe_rx2_data ,
output wire pipe_rx2_valid ,
output wire pipe_rx2_chanisaligned ,
output wire [ 2:0] pipe_rx2_status ,
output wire pipe_rx2_phy_status ,
output wire pipe_rx2_elec_idle ,
input wire pipe_rx2_polarity ,
input wire pipe_tx2_compliance ,
input wire [ 1:0] pipe_tx2_char_is_k ,
input wire [15:0] pipe_tx2_data ,
input wire pipe_tx2_elec_idle ,
input wire [ 1:0] pipe_tx2_powerdown ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k ,
output wire [15:0] pipe_rx3_data ,
output wire pipe_rx3_valid ,
output wire pipe_rx3_chanisaligned ,
output wire [ 2:0] pipe_rx3_status ,
output wire pipe_rx3_phy_status ,
output wire pipe_rx3_elec_idle ,
input wire pipe_rx3_polarity ,
input wire pipe_tx3_compliance ,
input wire [ 1:0] pipe_tx3_char_is_k ,
input wire [15:0] pipe_tx3_data ,
input wire pipe_tx3_elec_idle ,
input wire [ 1:0] pipe_tx3_powerdown ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k ,
output wire [15:0] pipe_rx4_data ,
output wire pipe_rx4_valid ,
output wire pipe_rx4_chanisaligned ,
output wire [ 2:0] pipe_rx4_status ,
output wire pipe_rx4_phy_status ,
output wire pipe_rx4_elec_idle ,
input wire pipe_rx4_polarity ,
input wire pipe_tx4_compliance ,
input wire [ 1:0] pipe_tx4_char_is_k ,
input wire [15:0] pipe_tx4_data ,
input wire pipe_tx4_elec_idle ,
input wire [ 1:0] pipe_tx4_powerdown ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k ,
output wire [15:0] pipe_rx5_data ,
output wire pipe_rx5_valid ,
output wire pipe_rx5_chanisaligned ,
output wire [ 2:0] pipe_rx5_status ,
output wire pipe_rx5_phy_status ,
output wire pipe_rx5_elec_idle ,
input wire pipe_rx5_polarity ,
input wire pipe_tx5_compliance ,
input wire [ 1:0] pipe_tx5_char_is_k ,
input wire [15:0] pipe_tx5_data ,
input wire pipe_tx5_elec_idle ,
input wire [ 1:0] pipe_tx5_powerdown ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k ,
output wire [15:0] pipe_rx6_data ,
output wire pipe_rx6_valid ,
output wire pipe_rx6_chanisaligned ,
output wire [ 2:0] pipe_rx6_status ,
output wire pipe_rx6_phy_status ,
output wire pipe_rx6_elec_idle ,
input wire pipe_rx6_polarity ,
input wire pipe_tx6_compliance ,
input wire [ 1:0] pipe_tx6_char_is_k ,
input wire [15:0] pipe_tx6_data ,
input wire pipe_tx6_elec_idle ,
input wire [ 1:0] pipe_tx6_powerdown ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k ,
output wire [15:0] pipe_rx7_data ,
output wire pipe_rx7_valid ,
output wire pipe_rx7_chanisaligned ,
output wire [ 2:0] pipe_rx7_status ,
output wire pipe_rx7_phy_status ,
output wire pipe_rx7_elec_idle ,
input wire pipe_rx7_polarity ,
input wire pipe_tx7_compliance ,
input wire [ 1:0] pipe_tx7_char_is_k ,
input wire [15:0] pipe_tx7_data ,
input wire pipe_tx7_elec_idle ,
input wire [ 1:0] pipe_tx7_powerdown ,
// PCI Express signals
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn ,
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp ,
// Non PIPE signals
input wire sys_clk ,
input wire sys_rst_n ,
output wire pipe_clk ,
output wire user_clk ,
output wire user_clk2 ,
output wire phy_rdy_n
);
parameter TCQ = 1; // clock to out delay model
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 :
(USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ
: USER_CLK_FREQ;
wire [ 7:0] gt_rx_phy_status_wire ;
wire [ 7:0] gt_rxchanisaligned_wire ;
wire [ 31:0] gt_rx_data_k_wire ;
wire [255:0] gt_rx_data_wire ;
wire [ 7:0] gt_rx_elec_idle_wire ;
wire [ 23:0] gt_rx_status_wire ;
wire [ 7:0] gt_rx_valid_wire ;
wire [ 7:0] gt_rx_polarity ;
wire [ 15:0] gt_power_down ;
wire [ 7:0] gt_tx_char_disp_mode ;
wire [ 31:0] gt_tx_data_k ;
wire [255:0] gt_tx_data ;
wire gt_tx_detect_rx_loopback ;
wire [ 7:0] gt_tx_elec_idle ;
wire [ 7:0] gt_rx_elec_idle_reset ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] plllkdet ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] phystatus_rst ;
wire clock_locked ;
wire [ 7:0] gt_rx_phy_status_wire_filter ;
wire [ 31:0] gt_rx_data_k_wire_filter ;
wire [255:0] gt_rx_data_wire_filter ;
wire [ 7:0] gt_rx_elec_idle_wire_filter ;
wire [ 23:0] gt_rx_status_wire_filter ;
wire [ 7:0] gt_rx_valid_wire_filter ;
wire pipe_clk_int;
wire phy_rdy_n_int;
reg [5:0] pl_ltssm_state_q;
always @(posedge pipe_clk_int or negedge clock_locked) begin
if (!clock_locked)
pl_ltssm_state_q <= #TCQ 6'b0;
else
pl_ltssm_state_q <= #TCQ pl_ltssm_state;
end
assign pipe_clk = pipe_clk_int ;
wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
wire plm_in_rl = (pl_ltssm_state_q == 6'h1c);
wire plm_in_dt = (pl_ltssm_state_q == 6'h2d);
wire plm_in_rs = (pl_ltssm_state_q == 6'h1f);
//-------------RX FILTER Instantiation----------------------------------------------------------//
genvar i;
generate for (i=0; i<LINK_CAP_MAX_LINK_WIDTH; i=i+1)
begin : gt_rx_valid_filter
pcie_7x_v1_3_gt_rx_valid_filter_7x # (
.CLK_COR_MIN_LAT(28)
)
GT_RX_VALID_FILTER_7x_inst (
.USER_RXCHARISK ( gt_rx_data_k_wire [(2*i)+1 + (2*i):(2*i)+ (2*i)] ), //O
.USER_RXDATA ( gt_rx_data_wire [(16*i)+15+(16*i) :(16*i)+0 + (16*i)] ), //O
.USER_RXVALID ( gt_rx_valid_wire [i] ), //O
.USER_RXELECIDLE ( gt_rx_elec_idle_wire [i] ), //O
.USER_RX_STATUS ( gt_rx_status_wire [(3*i)+2:(3*i)] ), //O
.USER_RX_PHY_STATUS ( gt_rx_phy_status_wire [i] ), //O
.GT_RXCHARISK ( gt_rx_data_k_wire_filter [(2*i)+1+ (2*i):2*i+ (2*i)] ), //I
.GT_RXDATA ( gt_rx_data_wire_filter [(16*i)+15+(16*i) :(16*i)+0+(16*i)] ), //I
.GT_RXVALID ( gt_rx_valid_wire_filter [i] ), //I
.GT_RXELECIDLE ( gt_rx_elec_idle_wire_filter [i] ), //I
.GT_RX_STATUS ( gt_rx_status_wire_filter [(3*i)+2:(3*i)] ), //I
.GT_RX_PHY_STATUS ( gt_rx_phy_status_wire_filter [i] ),
.PLM_IN_L0 ( plm_in_l0 ), //I
.PLM_IN_RS ( plm_in_rs ), //I
.USER_CLK ( pipe_clk_int ), //I
.RESET ( phy_rdy_n_int ) //I
);
end
endgenerate
//---------- GT Instantiation ---------------------------------------------------------------
pcie_7x_v1_3_pipe_wrapper #
(
.PCIE_SIM_MODE ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_TXBUF_EN ( "FALSE" ),
.PCIE_CHAN_BOND ( 0 ),
.PCIE_PLL_SEL ( "CPLL" ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
`ifdef SIMULATION
.PCIE_LPM_DFE ( "DFE" ),
`else
.PCIE_LPM_DFE ( "LPM" ),
`endif
.PCIE_LANE ( LINK_CAP_MAX_LINK_WIDTH ),
`ifdef SIMULATION
.PCIE_LINK_SPEED ( 2 ),
`else
.PCIE_LINK_SPEED ( 3 ),
`endif
.PCIE_REFCLK_FREQ ( REF_CLK_FREQ ),
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ),
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 )
) pipe_wrapper_i (
//---------- PIPE Clock & Reset Ports ------------------
.PIPE_CLK ( sys_clk ),
.PIPE_RESET_N ( sys_rst_n ),
.PIPE_PCLK ( pipe_clk_int ),
//---------- PIPE TX Data Ports ------------------
.PIPE_TXDATA ( gt_tx_data[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXDATAK ( gt_tx_data_k[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXP ( pci_exp_txp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXN ( pci_exp_txn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE RX Data Ports ------------------
.PIPE_RXP ( pci_exp_rxp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXN ( pci_exp_rxn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATA ( gt_rx_data_wire_filter[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATAK ( gt_rx_data_k_wire_filter[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE Command Ports ------------------
.PIPE_TXDETECTRX ( gt_tx_detect_rx_loopback ),
.PIPE_TXELECIDLE ( gt_tx_elec_idle[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXCOMPLIANCE ( gt_tx_char_disp_mode[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXPOLARITY ( gt_rx_polarity[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_POWERDOWN ( gt_power_down[((2*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RATE ( {1'b0,pipe_tx_rate} ),
//---------- PIPE Electrical Command Ports ------------------
.PIPE_TXMARGIN ( pipe_tx_margin[2] ),
.PIPE_TXSWING ( pipe_tx_swing ),
.PIPE_TXDEEMPH ( {1*LINK_CAP_MAX_LINK_WIDTH{{5'd0,pipe_tx_deemph}}} ),
.PIPE_TXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET_DEFAULT ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_PRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_LFFS ( {6*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_TXPRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_FS ( ),
.PIPE_TXEQ_LF ( ),
.PIPE_TXEQ_DEEMPH ( ),
.PIPE_TXEQ_DONE ( ),
.PIPE_RXEQ_NEW_TXCOEFF ( ),
.PIPE_RXEQ_LFFS_SEL ( ),
.PIPE_RXEQ_ADAPT_DONE ( ),
.PIPE_RXEQ_DONE ( ),
//---------- PIPE Status Ports -------------------
.PIPE_RXVALID ( gt_rx_valid_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS ( gt_rx_phy_status_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS_RST ( phystatus_rst ),
.PIPE_RXELECIDLE ( gt_rx_elec_idle_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXSTATUS ( gt_rx_status_wire_filter[((3*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXBUFSTATUS ( ),
//---------- PIPE User Ports ---------------------------
.PIPE_RXSLIDE ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_CPLL_LOCK ( plllkdet ),
.PIPE_QPLL_LOCK ( ),
.PIPE_PCLK_LOCK ( clock_locked ),
.PIPE_RXCDRLOCK ( ),
.PIPE_USERCLK1 ( user_clk ),
.PIPE_USERCLK2 ( user_clk2 ),
.PIPE_RXUSRCLK ( ),
.PIPE_RXOUTCLK ( ),
.PIPE_TXSYNC_DONE ( ),
.PIPE_RXSYNC_DONE ( ),
.PIPE_GEN3_RDY ( ),
.PIPE_RXCHANISALIGNED ( gt_rxchanisaligned_wire ),
.PIPE_ACTIVE_LANE ( ),
//---------- External Clock Ports ---------------------------
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//---------- PRBS/Loopback Ports ---------------------------
.PIPE_TXPRBSSEL ( 3'b0 ),
.PIPE_RXPRBSSEL ( 3'b0 ),
.PIPE_TXPRBSFORCEERR ( 1'b0 ),
.PIPE_RXPRBSCNTRESET ( 1'b0 ),
.PIPE_LOOPBACK ( 3'b0 ),
.PIPE_RXPRBSERR ( ),
//---------- FSM Ports ---------------------------
.PIPE_RST_FSM ( ),
.PIPE_QRST_FSM ( ),
.PIPE_RATE_FSM ( ),
.PIPE_SYNC_FSM_TX ( ),
.PIPE_SYNC_FSM_RX ( ),
.PIPE_DRP_FSM ( ),
.PIPE_TXEQ_FSM ( ),
.PIPE_RXEQ_FSM ( ),
.PIPE_QDRP_FSM ( ),
.PIPE_RST_IDLE ( ),
.PIPE_QRST_IDLE ( ),
.PIPE_RATE_IDLE ( ),
//---------- DEBUG Ports ---------------------------
.PIPE_DEBUG_0 ( ),
.PIPE_DEBUG_1 ( ),
.PIPE_DEBUG_2 ( ),
.PIPE_DEBUG_3 ( ),
.PIPE_DEBUG_4 ( ),
.PIPE_DEBUG_5 ( ),
.PIPE_DEBUG_6 ( ),
.PIPE_DEBUG_7 ( ),
.PIPE_DEBUG_8 ( ),
.PIPE_DEBUG_9 ( ),
.PIPE_DEBUG ( ),
.PIPE_DMONITOROUT ( )
);
assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
assign pipe_rx1_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
assign pipe_rx2_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
assign pipe_rx3_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
assign pipe_rx4_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
assign pipe_rx5_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
assign pipe_rx6_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
assign pipe_rx7_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];
assign pipe_rx1_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;
assign pipe_rx2_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;
assign pipe_rx3_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;
assign pipe_rx4_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;
assign pipe_rx5_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;
assign pipe_rx6_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;
assign pipe_rx7_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
assign pipe_rx1_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;
assign pipe_rx2_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;
assign pipe_rx3_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;
assign pipe_rx4_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[17], gt_rx_data_k_wire[16]} : 2'b0 ;
assign pipe_rx5_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[21], gt_rx_data_k_wire[20]} : 2'b0 ;
assign pipe_rx6_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[25], gt_rx_data_k_wire[24]} : 2'b0 ;
assign pipe_rx7_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[29], gt_rx_data_k_wire[28]} : 2'b0 ;
assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};
assign pipe_rx1_data = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;
assign pipe_rx2_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;
assign pipe_rx3_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;
assign pipe_rx4_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[143:136], gt_rx_data_wire[135:128]} : 16'h0 ;
assign pipe_rx5_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[175:168], gt_rx_data_wire[167:160]} : 16'h0 ;
assign pipe_rx6_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[207:200], gt_rx_data_wire[199:192]} : 16'h0 ;
assign pipe_rx7_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[239:232], gt_rx_data_wire[231:224]} : 16'h0 ;
assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
assign pipe_rx1_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;
assign pipe_rx2_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;
assign pipe_rx3_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;
assign pipe_rx4_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;
assign pipe_rx5_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;
assign pipe_rx6_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;
assign pipe_rx7_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];
assign pipe_rx1_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;
assign pipe_rx2_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;
assign pipe_rx3_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;
assign pipe_rx4_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;
assign pipe_rx5_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;
assign pipe_rx6_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;
assign pipe_rx7_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;
assign pipe_rx0_valid = gt_rx_valid_wire[0];
assign pipe_rx1_valid = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;
assign pipe_rx2_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;
assign pipe_rx3_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;
assign pipe_rx4_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;
assign pipe_rx5_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;
assign pipe_rx6_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;
assign pipe_rx7_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;
assign gt_rx_polarity[0] = pipe_rx0_polarity;
assign gt_rx_polarity[1] = pipe_rx1_polarity;
assign gt_rx_polarity[2] = pipe_rx2_polarity;
assign gt_rx_polarity[3] = pipe_rx3_polarity;
assign gt_rx_polarity[4] = pipe_rx4_polarity;
assign gt_rx_polarity[5] = pipe_rx5_polarity;
assign gt_rx_polarity[6] = pipe_rx6_polarity;
assign gt_rx_polarity[7] = pipe_rx7_polarity;
assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
assign gt_power_down[11:10] = pipe_tx5_powerdown;
assign gt_power_down[13:12] = pipe_tx6_powerdown;
assign gt_power_down[15:14] = pipe_tx7_powerdown;
assign gt_tx_char_disp_mode = {pipe_tx7_compliance,
pipe_tx6_compliance,
pipe_tx5_compliance,
pipe_tx4_compliance,
pipe_tx3_compliance,
pipe_tx2_compliance,
pipe_tx1_compliance,
pipe_tx0_compliance};
assign gt_tx_data_k = {2'd0,
pipe_tx7_char_is_k,
2'd0,
pipe_tx6_char_is_k,
2'd0,
pipe_tx5_char_is_k,
2'd0,
pipe_tx4_char_is_k,
2'd0,
pipe_tx3_char_is_k,
2'd0,
pipe_tx2_char_is_k,
2'd0,
pipe_tx1_char_is_k,
2'd0,
pipe_tx0_char_is_k};
assign gt_tx_data = {16'd0,
pipe_tx7_data,
16'd0,
pipe_tx6_data,
16'd0,
pipe_tx5_data,
16'd0,
pipe_tx4_data,
16'd0,
pipe_tx3_data,
16'd0,
pipe_tx2_data,
16'd0,
pipe_tx1_data,
16'd0,
pipe_tx0_data};
assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
pipe_tx6_elec_idle,
pipe_tx5_elec_idle,
pipe_tx4_elec_idle,
pipe_tx3_elec_idle,
pipe_tx2_elec_idle,
pipe_tx1_elec_idle,
pipe_tx0_elec_idle};
assign phy_rdy_n_int = (&phystatus_rst[LINK_CAP_MAX_LINK_WIDTH-1:0] & clock_locked);
assign phy_rdy_n = phy_rdy_n_int;
endmodule |
module PLL_100M (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
endmodule |
module tb_mac_base;
// Inputs
reg clk;
reg sof;
reg [79:0] A;
reg [15:0] B;
// Outputs
wire [179:0] C;
wire [4:0] valid;
// Instantiate the Unit Under Test (UUT)
multi_MAC_Base uut (
.clk(clk),
.sof(sof),
.A(A),
.B(B),
.C(C),
.valid(valid)
);
initial begin
// Initialize Inputs
clk = 0;
sof = 0;
A = 0;
B = 0;
#310
A = 80'h00020007000900030005; B = 16'h0004;
#20
sof = 1'b1;
#200
#100
$stop;
end
always
#`clkperiodby2 clk <= ~clk;
endmodule |
module ad9361_1t1r
(
AD9361_RX_Frame_P,
AD9361_RX_Frame_N,
AD9361_DATA_CLK_P,
AD9361_DATA_CLK_N,
AD9361_RX_DATA_P,
AD9361_RX_DATA_N,
AD9361_TX_Frame_P,
AD9361_TX_Frame_N,
AD9361_FB_CLK_P,
AD9361_FB_CLK_N,
AD9361_TX_DATA_P,
AD9361_TX_DATA_N,
clk,
rst,
rx_I,
rx_Q,
tx_I,
tx_Q,
rx_ce,
tx_ce
);
input AD9361_RX_Frame_P; // : in std_logic;
input AD9361_RX_Frame_N; // : in std_logic;
input AD9361_DATA_CLK_P; // : in std_logic;
input AD9361_DATA_CLK_N; // : in std_logic;
input [5:0]AD9361_RX_DATA_P; // : in std_logic_vector(5 downto 0);
input [5:0]AD9361_RX_DATA_N; // : in std_logic_vector(5 downto 0);
output AD9361_TX_Frame_P; // : out std_logic;
output AD9361_TX_Frame_N; // : out std_logic;
output AD9361_FB_CLK_P; // : out std_logic;
output AD9361_FB_CLK_N; // : out std_logic;
output [5:0]AD9361_TX_DATA_P; // : out std_logic_vector(5 downto 0);
output [5:0]AD9361_TX_DATA_N; // : out std_logic_vector(5 downto 0);
output clk;
input rst;
output reg [11:0]rx_I;
output reg [11:0]rx_Q;
input [11:0]tx_I;
input [11:0]tx_Q;
output reg rx_ce;
output reg tx_ce;
wire clk_out;
wire [13:0]rx;
reg [13:0]rx_h;
reg [13:0]tx;
reg [11:0]tx_I_reg;
reg [11:0]tx_Q_reg;
ddr_rx rx_if (
.data_in_from_pins_p({AD9361_RX_Frame_P,AD9361_RX_DATA_P}), // input wire [6 : 0] data_in_from_pins_p
.data_in_from_pins_n({AD9361_RX_Frame_N,AD9361_RX_DATA_N}), // input wire [6 : 0] data_in_from_pins_n
.clk_in_p(AD9361_DATA_CLK_P), // input wire clk_in_p
.clk_in_n(AD9361_DATA_CLK_N), // input wire clk_in_n
.io_reset(rst), // input wire io_reset
.clk_out(clk_out), // output wire clk_out
.data_in_to_device(rx) // output wire [13 : 0] data_in_to_device
);
ddr_tx tx_if (
.data_out_to_pins_p({AD9361_TX_Frame_P,AD9361_TX_DATA_P}), // output wire [6 : 0] data_out_to_pins_p
.data_out_to_pins_n({AD9361_TX_Frame_N,AD9361_TX_DATA_N}), // output wire [6 : 0] data_out_to_pins_n
.clk_in(clk_out), // input wire clk_in
.data_out_from_device(tx), // input wire [13 : 0] data_out_from_device
.clk_reset(rst), // input wire clk_reset
.io_reset(rst), // input wire io_reset
.clk_to_pins_p(AD9361_FB_CLK_P), // output wire clk_to_pins_p
.clk_to_pins_n(AD9361_FB_CLK_N) // output wire clk_to_pins_n
);
always @(posedge clk_out or posedge rst) begin
if (rst) begin
rx_h <= 14'h0;
rx_I <= 12'h0;
rx_Q <= 12'h0;
rx_ce <= 1'b0;
end
else if (rx[13]==1'b1) begin
rx_ce <= 1'b1;
rx_h <= rx;
end
else if(rx_ce==1'b1) begin
rx_ce <= 1'b0;
rx_I[11:6] = rx_h[5:0];
rx_Q[11:6] = rx_h[12:7];
rx_I[5:0] = rx[5:0];
rx_Q[5:0] = rx[12:7];
end
end
assign clk = clk_out;
always @(posedge clk_out or posedge rst) begin
if (rst) begin
tx_ce <= 1'b0;
tx <= 14'h0;
tx_I_reg <= 12'h0;
tx_Q_reg <= 12'h0;
end
else if (tx_ce==1'b1) begin
tx_ce <= 1'b0;
tx_I_reg <= tx_I;
tx_Q_reg <= tx_Q;
tx[5:0] <= tx_I[11:6];
tx[12:7] <= tx_Q[11:6];
tx[6] <= 1'b1;
tx[13] <= 1'b1;
end
else begin
tx_ce <= 1'b1;
tx[5:0] <= tx_I_reg[5:0];
tx[12:7] <= tx_Q_reg[5:0];
tx[6] <= 1'b0;
tx[13] <= 1'b0;
end
end
endmodule |
module alt_mem_ddrx_ecc_decoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_DEC_REG = 1,
CFG_ECC_RDATA_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_data_valid,
output_data,
output_data_valid,
output_ecc_code,
err_corrected,
err_detected,
err_fatal,
err_sbe
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input input_data_valid;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
output output_data_valid;
output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg output_data_valid;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
reg err_corrected;
reg err_detected;
reg err_fatal;
reg err_sbe;
wire int_err_corrected;
wire int_err_detected;
wire int_err_fatal;
wire int_err_sbe;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
wire [CFG_DATA_WIDTH - 1 : 0] decoder_input;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
reg decoder_output_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
reg decoder_output_valid_r;
reg int_err_corrected_r;
reg int_err_detected_r;
reg int_err_fatal_r;
reg int_err_sbe_r;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code_r;
wire zero = 1'b0;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data splitting/masking logic:
// change
// <Empty data> - <ECC code> - <Data>
// into
// <ECC code> - <Empty data> - <Data>
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : decoder_input_per_data_width
always @ (*)
begin
int_decoder_input_data [i_data] = input_data [i_data];
end
end
endgenerate
generate
if (CFG_ECC_RDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_decoder_input <= 0;
end
else
begin
int_decoder_input <= int_decoder_input_data;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
decoder_output_valid <= 0;
end
else
begin
decoder_output_valid <= input_data_valid;
end
end
end
else
begin
always @ (*)
begin
int_decoder_input = int_decoder_input_data;
end
always @ (*)
begin
decoder_output_valid = input_data_valid;
end
end
endgenerate
// Decoder input assignment
assign decoder_input = int_decoder_input;
// Decoder output, registered
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
decoder_output_r <= {CFG_ECC_DATA_WIDTH{1'b0}};
decoder_output_valid_r <= 1'b0;
int_err_corrected_r <= 1'b0;
int_err_detected_r <= 1'b0;
int_err_fatal_r <= 1'b0;
int_err_sbe_r <= 1'b0;
int_output_ecc_code_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
end
else
begin
decoder_output_r <= decoder_output;
decoder_output_valid_r <= decoder_output_valid;
int_err_corrected_r <= int_err_corrected;
int_err_detected_r <= int_err_detected;
int_err_fatal_r <= int_err_fatal;
int_err_sbe_r <= int_err_sbe;
int_output_ecc_code_r <= int_output_ecc_code;
end
end
// Decoder output ecc code
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
else
int_output_ecc_code = 0;
end
end
endgenerate
// Decoder wrapper output assignment
generate
begin : gen_decoder_output_reg_select
if (CFG_ECC_DEC_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid_r;
err_corrected = int_err_corrected_r;
err_detected = int_err_detected_r;
err_fatal = int_err_fatal_r;
err_sbe = int_err_sbe_r;
output_ecc_code = int_output_ecc_code_r;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid;
err_corrected = int_err_corrected;
err_detected = int_err_detected;
err_fatal = int_err_fatal;
err_sbe = int_err_sbe;
output_ecc_code = int_output_ecc_code;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_64 decoder_inst
(
.data (decoder_input ),
.err_corrected (int_err_corrected),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule |
module Block_Mat_exit1573_p (
ap_clk,
ap_rst,
ap_start,
start_full_n,
ap_done,
ap_continue,
ap_idle,
ap_ready,
start_out,
start_write,
height,
width,
sat,
img0_rows_V_out_din,
img0_rows_V_out_full_n,
img0_rows_V_out_write,
img0_cols_V_out_din,
img0_cols_V_out_full_n,
img0_cols_V_out_write,
img2_rows_V_out_din,
img2_rows_V_out_full_n,
img2_rows_V_out_write,
img2_cols_V_out_din,
img2_cols_V_out_full_n,
img2_cols_V_out_write,
img3_rows_V_out_din,
img3_rows_V_out_full_n,
img3_rows_V_out_write,
img3_cols_V_out_din,
img3_cols_V_out_full_n,
img3_cols_V_out_write,
p_cols_assign_cast_out_out_din,
p_cols_assign_cast_out_out_full_n,
p_cols_assign_cast_out_out_write,
p_rows_assign_cast_out_out_din,
p_rows_assign_cast_out_out_full_n,
p_rows_assign_cast_out_out_write,
sat_out_din,
sat_out_full_n,
sat_out_write
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
input start_full_n;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output start_out;
output start_write;
input [15:0] height;
input [15:0] width;
input [7:0] sat;
output [15:0] img0_rows_V_out_din;
input img0_rows_V_out_full_n;
output img0_rows_V_out_write;
output [15:0] img0_cols_V_out_din;
input img0_cols_V_out_full_n;
output img0_cols_V_out_write;
output [15:0] img2_rows_V_out_din;
input img2_rows_V_out_full_n;
output img2_rows_V_out_write;
output [15:0] img2_cols_V_out_din;
input img2_cols_V_out_full_n;
output img2_cols_V_out_write;
output [15:0] img3_rows_V_out_din;
input img3_rows_V_out_full_n;
output img3_rows_V_out_write;
output [15:0] img3_cols_V_out_din;
input img3_cols_V_out_full_n;
output img3_cols_V_out_write;
output [11:0] p_cols_assign_cast_out_out_din;
input p_cols_assign_cast_out_out_full_n;
output p_cols_assign_cast_out_out_write;
output [11:0] p_rows_assign_cast_out_out_din;
input p_rows_assign_cast_out_out_full_n;
output p_rows_assign_cast_out_out_write;
output [7:0] sat_out_din;
input sat_out_full_n;
output sat_out_write;
reg ap_done;
reg ap_idle;
reg start_write;
reg img0_rows_V_out_write;
reg img0_cols_V_out_write;
reg img2_rows_V_out_write;
reg img2_cols_V_out_write;
reg img3_rows_V_out_write;
reg img3_cols_V_out_write;
reg p_cols_assign_cast_out_out_write;
reg p_rows_assign_cast_out_out_write;
reg sat_out_write;
reg real_start;
reg start_once_reg;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg internal_ap_ready;
reg img0_rows_V_out_blk_n;
reg img0_cols_V_out_blk_n;
reg img2_rows_V_out_blk_n;
reg img2_cols_V_out_blk_n;
reg img3_rows_V_out_blk_n;
reg img3_cols_V_out_blk_n;
reg p_cols_assign_cast_out_out_blk_n;
reg p_rows_assign_cast_out_out_blk_n;
reg sat_out_blk_n;
reg ap_block_state1;
reg [0:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 start_once_reg = 1'b0;
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
start_once_reg <= 1'b0;
end else begin
if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
start_once_reg <= 1'b1;
end else if ((internal_ap_ready == 1'b1)) begin
start_once_reg <= 1'b0;
end
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img0_cols_V_out_blk_n = img0_cols_V_out_full_n;
end else begin
img0_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img0_cols_V_out_write = 1'b1;
end else begin
img0_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img0_rows_V_out_blk_n = img0_rows_V_out_full_n;
end else begin
img0_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img0_rows_V_out_write = 1'b1;
end else begin
img0_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img2_cols_V_out_blk_n = img2_cols_V_out_full_n;
end else begin
img2_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img2_cols_V_out_write = 1'b1;
end else begin
img2_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img2_rows_V_out_blk_n = img2_rows_V_out_full_n;
end else begin
img2_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img2_rows_V_out_write = 1'b1;
end else begin
img2_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_cols_V_out_blk_n = img3_cols_V_out_full_n;
end else begin
img3_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_cols_V_out_write = 1'b1;
end else begin
img3_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_rows_V_out_blk_n = img3_rows_V_out_full_n;
end else begin
img3_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_rows_V_out_write = 1'b1;
end else begin
img3_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
internal_ap_ready = 1'b1;
end else begin
internal_ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_cols_assign_cast_out_out_blk_n = p_cols_assign_cast_out_out_full_n;
end else begin
p_cols_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_out_out_write = 1'b1;
end else begin
p_cols_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_rows_assign_cast_out_out_blk_n = p_rows_assign_cast_out_out_full_n;
end else begin
p_rows_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_rows_assign_cast_out_out_write = 1'b1;
end else begin
p_rows_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
real_start = 1'b0;
end else begin
real_start = ap_start;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
sat_out_blk_n = sat_out_full_n;
end else begin
sat_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
sat_out_write = 1'b1;
end else begin
sat_out_write = 1'b0;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
start_write = 1'b1;
end else begin
start_write = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @ (*) begin
ap_block_state1 = ((sat_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (real_start == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (img2_cols_V_out_full_n == 1'b0) | (img2_rows_V_out_full_n == 1'b0) | (img0_cols_V_out_full_n == 1'b0) | (img0_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_ready = internal_ap_ready;
assign img0_cols_V_out_din = width;
assign img0_rows_V_out_din = height;
assign img2_cols_V_out_din = width;
assign img2_rows_V_out_din = height;
assign img3_cols_V_out_din = width;
assign img3_rows_V_out_din = height;
assign p_cols_assign_cast_out_out_din = width[11:0];
assign p_rows_assign_cast_out_out_din = height[11:0];
assign sat_out_din = sat;
assign start_out = real_start;
endmodule |
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_ms__udp_mux_2to1_N dut (.A0(A0), .A1(A1), .S(S), .Y(Y));
endmodule |
module DUAL_PORT_MEMORY_SIMULATION();
parameter MEMORY_WIDTH = 512 ;
parameter MEMORY_DEPTH = 512 ;
parameter MEMORY_LATENCY = "LOW_LATENCY" ;
parameter INIT_FILE = "" ;
// Inputs
reg clk ;
reg [$clog2(MEMORY_DEPTH-1) - 1 : 0] write_address ;
reg [MEMORY_WIDTH-1 : 0] data_in ;
reg write_enable ;
reg [$clog2(MEMORY_DEPTH-1)-1 : 0] read_address ;
reg read_enble ;
// Outputs
wire [MEMORY_WIDTH-1 : 0] data_out ;
// Instantiate the Unit Under Test (UUT)
DUAL_PORT_MEMORY uut(
.CLK(clk),
.WRITE_ADDRESS(write_address),
.DATA_IN(data_in),
.WRITE_ENABLE(write_enable),
.READ_ADDRESS(read_address),
.READ_ENBLE(read_enble),
.DATA_OUT(data_out)
);
initial
begin
// Initialize Inputs
clk = 1'b0 ;
write_address = 9'b1 ;
data_in = 512'b11 ;
write_enable = 1'b1 ;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_address = 9'b0 ;
data_in = 512'b1 ;
write_enable = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_address = 9'b0 ;
data_in = 512'b0 ;
write_enable = 1'b0 ;
read_address = 9'b0 ;
read_enble = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
read_enble = 1'b0 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
end
endmodule |
module spi_master #(
parameter CLK_DIVIDE=3 // divide clk by 2^CLK_DIVIDE to get spi_sclk
) (
input clk, // 50 MHz system clk
input reset,
input spi_start,
input [7:0] spi_data,
output spi_fin,
output spi_csn,
output spi_sdo,
output spi_sclk // max 10 MHz clk
);
`define SPI_MASTER_SM_W 2
localparam STATE_IDLE = `SPI_MASTER_SM_W'h0;
localparam STATE_SEND = `SPI_MASTER_SM_W'h1;
localparam STATE_HOLD = `SPI_MASTER_SM_W'h2;
localparam STATE_DONE = `SPI_MASTER_SM_W'h3;
reg [`SPI_MASTER_SM_W-1:0] spi_sm_state;
reg [CLK_DIVIDE-1:0] clk_divider;
reg [7:0] spi_data_shift;
reg [2:0] shift_counter;
assign spi_csn = ((spi_sm_state==STATE_IDLE) && (spi_start==1'b0)) ? 1'b1 : 1'b0;
assign spi_sdo = spi_data_shift[7];
assign spi_sclk = ((spi_sm_state==STATE_SEND) && (clk_divider[CLK_DIVIDE-1]==1'b1)) ? 1'b1 : 1'b0;
assign spi_fin = (spi_sm_state==STATE_DONE) ? 1'b1 : 1'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
spi_sm_state <= STATE_IDLE;
spi_data_shift <= 'b0;
clk_divider <= 'b0;
shift_counter <= 'b0;
end else begin
case (spi_sm_state)
STATE_IDLE: begin
if (spi_start==1'b1) begin
spi_sm_state <= STATE_SEND;
spi_data_shift <= spi_data;
clk_divider <= 'b0;
shift_counter <= 'b0;
end
end
STATE_SEND: begin
clk_divider <= clk_divider + 1;
if (clk_divider == {CLK_DIVIDE{1'b1}}) begin
shift_counter <= shift_counter + 1;
spi_data_shift <= {spi_data_shift[6:0], 1'b0};
if (shift_counter==3'b111) begin
spi_sm_state <= STATE_HOLD;
end
end
end
STATE_HOLD: begin
clk_divider <= clk_divider + 1;
if (clk_divider == {CLK_DIVIDE{1'b1}}) begin
spi_sm_state <= STATE_DONE;
end
end
STATE_DONE: begin
if (spi_start==1'b0) begin
spi_sm_state <= STATE_IDLE;
end
end
default:
spi_sm_state <= STATE_IDLE;
endcase
end
end
endmodule |
module sky130_fd_sc_hd__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sdr_data_path(
CLK,
RESET_N,
DATAIN,
DM,
DQOUT,
DQM
);
//`include "Sdram_Params.h"
input CLK; // System Clock
input RESET_N; // System Reset
input [`DSIZE-1:0] DATAIN; // Data input from the host
input [`DSIZE/8-1:0] DM; // byte data masks
output [`DSIZE-1:0] DQOUT;
output [`DSIZE/8-1:0] DQM; // SDRAM data mask ouputs
reg [`DSIZE/8-1:0] DQM;
// internal
reg [`DSIZE-1:0] DIN1;
reg [`DSIZE-1:0] DIN2;
reg [`DSIZE/8-1:0] DM1;
// Allign the input and output data to the SDRAM control path
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
begin
DIN1 <= 0;
DIN2 <= 0;
DM1 <= 0;
end
else
begin
DIN1 <= DATAIN;
DIN2 <= DIN1;
DQM <= DM;
end
end
assign DQOUT = DIN2;
endmodule |
module user_interface(clk, rst, dma_req, dma_appr, wr, add_wr, incr_add, clk_sel, entity_sel, pc_rd, mar_rd, rf_rd1, rf_rd2, ram_rd, stk_rd, alu_rd, data_in, sys_clk, sys_rst, sys_hrd_rst, sys_dma_req, mar_incr, we_out, d_out, add_out, data_out);
// Parameter Definitions
parameter width = 'd16; // Data Width
parameter add_width = 'd13; // Address Width
parameter disp_output_width = 'd20; // Display Driver Data Width
// Inputs
input wire clk /* External Clock */, rst /* External Reset Request */, dma_req /* External Direct Memory Access (DMA) Request */; // Management Interfaces
input wire dma_appr /* External Direct Memory Access (DMA) Request Approval Notification */; // Notification Interfaces
input wire wr /* External Write Request */, add_wr /* External Address Write Request */;
input wire incr_add /* Increment Address Request */, clk_sel /* Clock Select Toggle */;
input wire [2:0] entity_sel /* Read/Write Processor Entity Select */;
input wire [add_width-1:0] mar_rd /* Memory Address Register (MAR) Read */;
input wire [width-1:0] pc_rd /* Program Counter (PC) Read */, rf_rd1 /* Register File Port (RF) I Read */, rf_rd2 /* Register File (RF) Port II Read */, ram_rd /* Random Access Memory (RAM) Read */;
input wire [width-1:0] stk_rd /* Stack Read */, alu_rd /* ALU Result Read */;
input wire [width-1:0] data_in /* External Data Input Port */;
// Outputs
output wire sys_clk /* System Clock Output */, sys_rst /* System Reset Output */, sys_hrd_rst /* System Hard Reset Output */, sys_dma_req /* Request Direct Memory Access (DMA) from System */;
output wire mar_incr /* Increment MAR Request */;
output wire [2:0] we_out /* Control Matrix Write Enable Request */;
output wire [width-1:0] d_out /* Data Output for Direct Memory Access (DMA) Write Requests */;
output wire [disp_output_width-1:0] add_out /* External Address Output Port */;
output wire [disp_output_width:0] data_out /* External Data Output Port */;
// Internals
reg sclk /* Slow Clock Driver */, rst_buf /* External Reset Request Buffer */, dma_req_buf /* External Direct Memory Access (DMA) Request Buffer */, wr_buf /* External Write Request Buffer */;
reg add_wr_buf /* External Address Write Request Buffer */, incr_add_buf /* Increment Address Request Buffer */, incr_c /* Incrementation Complete Notification */;
reg [2:0] entity_sel_buf /* Read/Write Processor Entity Select Buffer */, entity_sel_buf_t /* True Entity Select Buffer */;
reg [3:0] stclk /* Reset LED State Clock */;
reg [width-1:0] data_in_buf /* Data Input Buffer */, data_conv_buf /* Hex Conversion Data Buffer */;
reg [disp_output_width:0] a_bus_disp; // Binary to Hex (Extended Binary, decoded by Display Driver) converted Address Output signal. Extra bit ignored.
reg [disp_output_width:0] d_bus_disp; // Binary to Hex (Extended Binary, decoded by Display Driver) converted Data Output signals. One extra bit for sign notation.
reg [23:0] counter /* Slow Clock Driver Counter */;
// Initialization
initial begin
sclk <= 1'b0;
stclk [3;0] <= 4'b0;
counter [23:0] <= 24'b0;
end
// Slow Clock Driver Block
always@(posedge clk) begin
if(counter [23:0] < 5000000) counter [23:0] <= counter [23:0] + 1'b1;
else begin
sclk <= !sclk;
counter [23:0] <= 24'b0;
end
end
// Write Request
assign we_out [2:0] = (wr_buf && dma_appr)?entity_sel_buf [2:0]:3'b0;
// Output Logic
assign sys_clk = (clk_sel)?sclk:clk; // System Clock Select
assign sys_rst = (rst_buf)?1'b1:1'b0; // Reset Enable
assign sys_hrd_rst = (rst_buf && wr_buf && add_wr_buf && incr_add_buf && (entity_sel_buf == 3'b0))?1'b1:1'b0; // Hard Reset Enable Logic
assign sys_dma_req = dma_req_buf; // Request Direct Memory Access (DMA) from Control Matrix
assign mar_incr = incr_add_buf; // Increment MAR contents.
assign d_out [width-1:0] = data_in_buf [width-1:0]; // Assigns the Direct Memory Access (DMA) Write Request Data Line based on input.
assign add_out [disp_output_width-1:0] = a_bus_disp [disp_output_width-1:0]; // Assigns the Address Output Port the value of the Address Output buffer.
assign data_out [disp_output_width:0] = d_bus_disp [disp_output_width:0]; // Assigns the Data Output Port the value of the Data Output buffer.
// Buffer Logic
always@(posedge sclk) begin
rst_buf <= rst; // External Reset Request Buffer
dma_req_buf <= dma_req; // External Direct Memory Access (DMA) Request Buffer
wr_buf <= wr; // External Write Request Buffer
add_wr_buf <= add_wr; // External Address Write Request Buffer
data_in_buf <= data_in; // External Data Input Buffer
// Entity Select
entity_sel_buf_t [2:0] <= entity_sel [2:0]; // True Entity Select Buffer based on input.
if(add_wr_buf) entity_sel_buf [2:0] <= 3'b101; // Select MAR to write address.
else entity_sel_buf [2:0] <= entity_sel [2:0]; // Select Entity based on input.
end
// Data Conversion Buffer
always@(entity_sel_buf_t, rf_rd1, rf_rd2, ram_rd, pc_rd, mar_rd, stk_rd, alu_rd) begin
case(entity_sel_buf_t) // synthesis parallel_case
3'b000: data_conv_buf [width-1:0] = {width{1'b0}};
3'b001: data_conv_buf [width-1:0] = rf_rd1 [width-1:0];
3'b010: data_conv_buf [width-1:0] = rf_rd2 [width-1:0];
3'b011: data_conv_buf [width-1:0] = ram_rd [width-1:0];
3'b100: data_conv_buf [width-1:0] = pc_rd [width-1:0];
3'b101: data_conv_buf [width-1:0] = {{width-add_width{1'b0}}, mar_rd [add_width-1:0]};
3'b110: data_conv_buf [width-1:0] = stk_rd [width-1:0];
3'b111: data_conv_buf [width-1:0] = alu_rd [width-1:0];
default: data_conv_buf [width-1:0] = {width{1'b0}};
endcase
end
// Incrementation Logic and signal buffer
// This block ensures that incrementation takes place only once for every increment request by using the 'Incrementation Complete (incr_c)' notification.
always@(posedge sclk) begin
if(!incr_add_buf && incr_add && !incr_c) incr_add_buf <= 1'b1;
else if(incr_add_buf && incr_add) begin
incr_add_buf <= 1'b0;
incr_c <= 1'b1;
end else if(!incr_add) begin
incr_add_buf <= 1'b0;
incr_c <= 1'b0;
end
end
// Binary to Hex (Extended Binary, decoded by Display Driver) Conversion Block
// Address Bus
always@(mar_rd) begin
a_bus_disp [disp_output_width:0] = {7'b0, mar_rd [add_width-1:0]};
end
// Data Bus
always@(data_conv_buf) begin
d_bus_disp [disp_output_width:0] = {data_conv_buf[width-1], 4'b0, data_conv_buf [width-2:0]};
end
endmodule |
module control_unit();
parameter ADDR_SIZE = 12;
parameter WORD_SIZE = 16;
reg sysclk;
initial begin //clock
sysclk <= 1'b1;
forever #1 sysclk = ~sysclk;
end
initial begin
$dumpfile("control_unit.vcd");
$dumpvars;
end
/*
* Instructions:
* 0: ACC := [S]
* 1: [S] := ACC
* 2: ACC:= ACC + [S]
* 3: ACC := ACC - [S]
* 4: PC := S
* 5: PC := S if ACC >=0
* 6: PC :=S if ACC != 0
* 7: HALT
* 8: [SP] := ACC, SP := SP + 1
* 9: ACC := [SP], SP := SP - 1
* a: IP := S, [SP] := IP, SP := SP + 1
* b: IP := [SP - 1], SP := SP - 1
* /
/*
* Specifications:
* posedge: exec
* negedge: fetch
*/
//Registers
reg [WORD_SIZE-1:0] acc;
reg [ADDR_SIZE-1:0] ip;
reg [WORD_SIZE-1:0] ir;
reg [ADDR_SIZE-1:0] sp;
//Memory
reg [ADDR_SIZE-1:0] mem_addr;
reg [WORD_SIZE-1:0] mem_in;
wire [WORD_SIZE-1:0] mem_out;
wire [WORD_SIZE-1:0] rom_out;
reg mem_write;
ram ram_blk(
.clk(sysclk),
.addr(mem_addr),
.data_in(mem_in),
.write_en(mem_write),
.data_out(mem_out),
.rom_addr(ip),
.rom_out(rom_out)
);
initial begin //default register values
ir <= 16'h4000;
ip <= 0;
sp <= 12'd191; //64 word stack
mem_addr <= 0;
mem_in <= 0;
mem_write <= 0;
acc <= 0;
end
//0/1 -> Fetch/Exec
reg state = 1;
//Determine pop operations
wire pop_op;
assign pop_op = (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'h9)
| (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'hb);
always @(posedge sysclk) begin
state <= ~state; //Alternate state
if (state) begin //Exec
case (ir[WORD_SIZE-1:WORD_SIZE-4])
4'h0: begin //ACC := [S]
acc <= mem_out;
end
4'h1: begin //[S] := ACC
mem_in <= acc;
mem_addr <= ir[WORD_SIZE-5:0];
mem_write <= 1;
end
4'h2: begin //ACC:= ACC + [S]
acc <= acc + mem_out;
end
4'h3: begin //ACC := ACC - [S]
acc <= acc - mem_out;
end
4'h4: begin // PC := S
ip <= ir[WORD_SIZE-5:0];
end
4'h5: begin //PC := S if ACC >=0
if (acc[WORD_SIZE-1] == 1'b0)
ip <= ir[WORD_SIZE-5:0];
end
4'h6: begin //PC := S if ACC != 0
if (acc != 8'd0)
ip <= ir[WORD_SIZE-5:0];
end
4'h7: begin // HALT
$finish;
end
4'h8: begin // [SP] := ACC, SP := SP + 1
mem_addr <= sp;
mem_in <= acc;
mem_write <= 1;
sp <= sp + 12'b1;
end
4'h9: begin // ACC := [SP - 1], SP := SP - 1
acc <= mem_out;
sp <= sp - 12'b1;
end
4'ha: begin // IP := S, [SP] := IP, SP := SP + 1
ip <= mem_addr ;
mem_addr <= sp;
mem_in <= ip;
mem_write <= 1;
sp <= sp + 12'b1;
end
4'hb: begin // IP := [SP - 1], SP := SP - 1
ip <= mem_out;
sp <= sp - 12'b1;
end
default: $finish;
endcase
end
else begin //Fetch
ir <= rom_out;
ip <= ip + 1;
mem_write <= 0;
//Get stack if pop/return
if (pop_op) //
mem_addr <= (sp - 12'b1);
else //Get memory
mem_addr <= rom_out[WORD_SIZE-5:0];
end
end
endmodule |
module COMMAND_RAM (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [10:0] rdaddress;
input [11:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule |
module sky130_fd_sc_lp__nor3b_2 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__nor3b_2 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule |
module sky130_fd_sc_lp__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule |
module dbl_buf (/*AUTOARG*/
// Outputs
dout, vld, full,
// Inputs
clk, rst_l, wr, rd, din
);
// synopsys template
parameter BUF_WIDTH = 64; // width of the buffer
// Globals
input clk;
input rst_l;
// Buffer Input
input wr;
input rd;
input [BUF_WIDTH-1:0] din;
// Buffer Output
output [BUF_WIDTH-1:0] dout;
output vld;
output full;
// Buffer Output
wire wr_buf0;
wire wr_buf1;
wire buf0_vld;
wire buf1_vld;
wire buf1_older;
wire rd_buf0;
wire rd_buf1;
wire rd_buf;
wire en_vld0;
wire en_vld1;
wire [BUF_WIDTH-1:0] buf0_obj;
wire [BUF_WIDTH-1:0] buf1_obj;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// if both entries are empty, write to entry pointed to by the older pointer
// if only one entry is empty, then write to the empty entry (duh!)
assign wr_buf0 = wr &
(buf1_vld | (~buf0_vld & ~buf1_older));
assign wr_buf1 = wr &
(buf0_vld | (~buf1_vld & buf1_older));
// read from the older entry
assign rd_buf0 = rd & ~buf1_older;
assign rd_buf1 = rd & buf1_older;
// flip older pointer when an entry is read
assign rd_buf = rd & (buf0_vld | buf1_vld);
dffrle_ns buf1_older_ff (.din(~buf1_older),
.rst_l(rst_l),
.en(rd_buf),
.clk(clk),
.q(buf1_older));
// set valid bit for writes and reset for reads
assign en_vld0 = wr_buf0 | rd_buf0;
assign en_vld1 = wr_buf1 | rd_buf1;
// the actual buffers
dffrle_ns buf0_vld_ff (.din(wr_buf0),
.rst_l(rst_l),
.en(en_vld0),
.clk(clk),
.q(buf0_vld));
dffrle_ns buf1_vld_ff (.din(wr_buf1),
.rst_l(rst_l),
.en(en_vld1),
.clk(clk),
.q(buf1_vld));
dffe_ns #(BUF_WIDTH) buf0_obj_ff (.din(din),
.en(wr_buf0),
.clk(clk),
.q(buf0_obj));
dffe_ns #(BUF_WIDTH) buf1_obj_ff (.din(din),
.en(wr_buf1),
.clk(clk),
.q(buf1_obj));
// mux out the older entry
assign dout = (buf1_older) ? buf1_obj:buf0_obj;
assign vld = buf0_vld | buf1_vld;
assign full = buf0_vld & buf1_vld;
endmodule |
module debouncer
(
input wire clk, reset,
input wire sw,
output reg db
);
// symbolic state declaration
localparam [2:0]
zero = 3'b000,
wait1_1 = 3'b001,
wait1_2 = 3'b010,
wait1_3 = 3'b011,
one = 3'b100,
wait0_1 = 3'b101,
wait0_2 = 3'b110,
wait0_3 = 3'b111;
// number of counter bits (2^N * 20ns = 10ms tick)
localparam N =19;
// signal declaration
reg [N-1:0] q_reg;
wire [N-1:0] q_next;
wire m_tick;
reg [2:0] state_reg, state_next;
// body
//=============================================
// counter to generate 10 ms tick
//=============================================
always @(posedge clk)
q_reg <= q_next;
// next-state logic
assign q_next = q_reg + 1;
// output tick
assign m_tick = (q_reg==0) ? 1'b1 : 1'b0;
//=============================================
// debouncing FSM
//=============================================
// state register
always @(posedge clk, posedge reset)
if (reset)
state_reg <= zero;
else
state_reg <= state_next;
// next-state logic and output logic
always @*
begin
state_next = state_reg; // default state: the same
db = 1'b0; // default output: 0
case (state_reg)
zero:
if (sw)
state_next = wait1_1;
wait1_1:
if (~sw)
state_next = zero;
else
if (m_tick)
state_next = wait1_2;
wait1_2:
if (~sw)
state_next = zero;
else
if (m_tick)
state_next = wait1_3;
wait1_3:
if (~sw)
state_next = zero;
else
if (m_tick)
state_next = one;
one:
begin
db = 1'b1;
if (~sw)
state_next = wait0_1;
end
wait0_1:
begin
db = 1'b1;
if (sw)
state_next = one;
else
if (m_tick)
state_next = wait0_2;
end
wait0_2:
begin
db = 1'b1;
if (sw)
state_next = one;
else
if (m_tick)
state_next = wait0_3;
end
wait0_3:
begin
db = 1'b1;
if (sw)
state_next = one;
else
if (m_tick)
state_next = zero;
end
default: state_next = zero;
endcase
end
endmodule |
module system_rgb565_to_rgb888_0_0_rgb565_to_rgb888
(rgb_888,
rgb_565,
clk);
output [15:0]rgb_888;
input [15:0]rgb_565;
input clk;
wire clk;
wire [15:0]rgb_565;
wire [15:0]rgb_888;
FDRE \rgb_888_reg[10]
(.C(clk),
.CE(1'b1),
.D(rgb_565[5]),
.Q(rgb_888[5]),
.R(1'b0));
FDRE \rgb_888_reg[11]
(.C(clk),
.CE(1'b1),
.D(rgb_565[6]),
.Q(rgb_888[6]),
.R(1'b0));
FDRE \rgb_888_reg[12]
(.C(clk),
.CE(1'b1),
.D(rgb_565[7]),
.Q(rgb_888[7]),
.R(1'b0));
FDRE \rgb_888_reg[13]
(.C(clk),
.CE(1'b1),
.D(rgb_565[8]),
.Q(rgb_888[8]),
.R(1'b0));
FDRE \rgb_888_reg[14]
(.C(clk),
.CE(1'b1),
.D(rgb_565[9]),
.Q(rgb_888[9]),
.R(1'b0));
FDRE \rgb_888_reg[15]
(.C(clk),
.CE(1'b1),
.D(rgb_565[10]),
.Q(rgb_888[10]),
.R(1'b0));
FDRE \rgb_888_reg[19]
(.C(clk),
.CE(1'b1),
.D(rgb_565[11]),
.Q(rgb_888[11]),
.R(1'b0));
FDRE \rgb_888_reg[20]
(.C(clk),
.CE(1'b1),
.D(rgb_565[12]),
.Q(rgb_888[12]),
.R(1'b0));
FDRE \rgb_888_reg[21]
(.C(clk),
.CE(1'b1),
.D(rgb_565[13]),
.Q(rgb_888[13]),
.R(1'b0));
FDRE \rgb_888_reg[22]
(.C(clk),
.CE(1'b1),
.D(rgb_565[14]),
.Q(rgb_888[14]),
.R(1'b0));
FDRE \rgb_888_reg[23]
(.C(clk),
.CE(1'b1),
.D(rgb_565[15]),
.Q(rgb_888[15]),
.R(1'b0));
FDRE \rgb_888_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_565[0]),
.Q(rgb_888[0]),
.R(1'b0));
FDRE \rgb_888_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_565[1]),
.Q(rgb_888[1]),
.R(1'b0));
FDRE \rgb_888_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_565[2]),
.Q(rgb_888[2]),
.R(1'b0));
FDRE \rgb_888_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_565[3]),
.Q(rgb_888[3]),
.R(1'b0));
FDRE \rgb_888_reg[7]
(.C(clk),
.CE(1'b1),
.D(rgb_565[4]),
.Q(rgb_888[4]),
.R(1'b0));
endmodule |
module system_rgb565_to_rgb888_0_0
(clk,
rgb_565,
rgb_888);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [15:0]rgb_565;
output [23:0]rgb_888;
wire \<const0> ;
wire clk;
wire [15:0]rgb_565;
wire [20:3]\^rgb_888 ;
assign rgb_888[23:21] = \^rgb_888 [18:16];
assign rgb_888[20:16] = \^rgb_888 [20:16];
assign rgb_888[15:14] = \^rgb_888 [9:8];
assign rgb_888[13:3] = \^rgb_888 [13:3];
assign rgb_888[2] = \<const0> ;
assign rgb_888[1] = \<const0> ;
assign rgb_888[0] = \<const0> ;
GND GND
(.G(\<const0> ));
system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 U0
(.clk(clk),
.rgb_565(rgb_565),
.rgb_888({\^rgb_888 [18:16],\^rgb_888 [20:19],\^rgb_888 [9:8],\^rgb_888 [13:10],\^rgb_888 [7:3]}));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module ddr3_int_example_driver (
// inputs:
clk,
local_rdata,
local_rdata_valid,
local_ready,
reset_n,
// outputs:
local_bank_addr,
local_be,
local_burstbegin,
local_col_addr,
local_cs_addr,
local_read_req,
local_row_addr,
local_size,
local_wdata,
local_write_req,
pnf_per_byte,
pnf_persist,
test_complete,
test_status
)
/* synthesis ALTERA_ATTRIBUTE = "MESSAGE_DISABLE=14130;MESSAGE_DISABLE=14110" */ ;
output [ 2: 0] local_bank_addr;
output [ 15: 0] local_be;
output local_burstbegin;
output [ 9: 0] local_col_addr;
output local_cs_addr;
output local_read_req;
output [ 13: 0] local_row_addr;
output [ 5: 0] local_size;
output [127: 0] local_wdata;
output local_write_req;
output [ 15: 0] pnf_per_byte;
output pnf_persist;
output test_complete;
output [ 7: 0] test_status;
input clk;
input [127: 0] local_rdata;
input local_rdata_valid;
input local_ready;
input reset_n;
wire [ 19: 0] COUNTER_VALUE;
wire [ 5: 0] LOCAL_BURST_LEN_s;
wire [ 2: 0] MAX_BANK;
wire MAX_CHIPSEL;
wire [ 9: 0] MAX_COL;
wire [ 13: 0] MAX_ROW;
wire [ 13: 0] MAX_ROW_PIN;
wire MIN_CHIPSEL;
wire [ 7: 0] addr_value;
wire avalon_burst_mode;
reg [ 2: 0] bank_addr;
reg [ 15: 0] be;
reg [ 5: 0] burst_beat_count;
reg burst_begin;
reg [ 9: 0] col_addr;
wire [ 15: 0] compare;
reg [ 15: 0] compare_reg;
reg [ 15: 0] compare_valid;
reg [ 15: 0] compare_valid_reg;
reg cs_addr;
wire [127: 0] dgen_data;
reg dgen_enable;
reg [127: 0] dgen_ldata;
reg dgen_load;
wire dgen_pause;
wire enable_be;
reg full_burst_on;
reg last_rdata_valid;
reg last_wdata_req;
wire [ 2: 0] local_bank_addr;
wire [ 15: 0] local_be;
wire local_burstbegin;
wire [ 9: 0] local_col_addr;
wire local_cs_addr;
wire local_read_req;
wire [ 13: 0] local_row_addr;
wire [ 5: 0] local_size;
wire [127: 0] local_wdata;
wire local_write_req;
wire [ 9: 0] max_col_value;
wire p_burst_begin;
wire p_read_req;
reg p_state_on;
wire pause_be;
wire [ 15: 0] pnf_per_byte;
reg pnf_persist;
reg pnf_persist1;
wire pnf_persist_compare;
wire powerdn_on;
reg rdata_valid_flag;
reg rdata_valid_flag_reg;
reg rdata_valid_flag_reg_2;
wire reached_max_address;
reg read_req;
reg [ 7: 0] reads_remaining;
reg reset_address;
reg reset_be;
reg reset_data;
wire restart_LFSR_n;
reg [ 13: 0] row_addr;
wire selfrfsh_on;
wire [ 5: 0] size;
reg [ 4: 0] state;
reg test_addr_pin;
reg test_addr_pin_mode;
wire test_addr_pin_on;
reg test_complete;
reg test_dm_pin;
reg test_dm_pin_mode;
wire test_dm_pin_on;
reg test_incomplete_writes;
reg test_incomplete_writes_mode;
wire test_incomplete_writes_on;
reg test_seq_addr;
reg test_seq_addr_mode;
wire test_seq_addr_on;
wire [ 7: 0] test_status;
reg wait_first_write_data;
wire [127: 0] wdata;
wire wdata_req;
reg write_req;
reg [ 7: 0] writes_remaining;
//
//Turn on this mode to test sequential address
assign test_seq_addr_on = 1'b1;
//Turn on this mode to test all address pins by a One-hot pattern address generator
assign test_addr_pin_on = 1'b1;
//Turn on this mode to make use of dm pins
assign test_dm_pin_on = 1'b1;
//This mode can only be used when LOCAL_BURST_LEN_s = 2
assign test_incomplete_writes_on = 1'b0;
//restart_LFSR_n is an active low signal, set it to 1'b0 to restart LFSR data generator after a complete test
assign restart_LFSR_n = 1'b1;
//Change COUNTER_VALUE to control the period of power down and self refresh mode
assign COUNTER_VALUE = 150;
//Change MAX_ROW to test more or lesser row address in test_seq_addr_mode, maximum value is 2^(row bits) -1, while minimum value is 0
assign MAX_ROW = 3;
//Change MAX_COL to test more or lesser column address in test_seq_addr_mode, maximum value is 2^(column bits) - (LOCAL_BURST_LEN_s * dwidth_ratio (aka half-rate (4) or full-rate (2))), while minimum value is 0 for Half rate and (LOCAL_BURST_LEN_s * dwidth_ratio) for Full rate
assign MAX_COL = 16;
//Decrease MAX_BANK to test lesser bank address, minimum value is 0
assign MAX_BANK = 7;
//Decrease MAX_CHIPSEL to test lesser memory chip, minimum value is MIN_CHIPSEL
assign MAX_CHIPSEL = 0;
//
assign MIN_CHIPSEL = 0;
assign MAX_ROW_PIN = {14{1'b1}};
assign max_col_value = ((addr_value == 4) == 0)? MAX_COL :
(MAX_COL + 4);
assign powerdn_on = 1'b0;
assign selfrfsh_on = 1'b0;
assign local_burstbegin = burst_begin | p_burst_begin;
assign avalon_burst_mode = 1;
//
//One hot decoder for test_status signal
assign test_status[0] = test_seq_addr_mode;
assign test_status[1] = test_incomplete_writes_mode;
assign test_status[2] = test_dm_pin_mode;
assign test_status[3] = test_addr_pin_mode;
assign test_status[4] = 0;
assign test_status[5] = 0;
assign test_status[6] = 0;
assign test_status[7] = test_complete;
assign p_read_req = 0;
assign p_burst_begin = 0;
assign local_cs_addr = cs_addr;
assign local_row_addr = row_addr;
assign local_bank_addr = bank_addr;
assign local_col_addr = col_addr;
assign local_write_req = write_req;
assign local_wdata = wdata;
assign local_read_req = read_req | p_read_req;
assign wdata = (reset_data == 0)? dgen_data :
128'd0;
//The LOCAL_BURST_LEN_s is a signal used insted of the parameter LOCAL_BURST_LEN
assign LOCAL_BURST_LEN_s = 2;
//LOCAL INTERFACE (AVALON)
assign wdata_req = write_req & local_ready;
// Generate new data (enable lfsr) when writing or reading valid data
assign dgen_pause = ~ ((wdata_req & ~reset_data) | (local_rdata_valid));
assign enable_be = (wdata_req & test_dm_pin_mode & ~reset_data) | (test_dm_pin_mode & local_rdata_valid);
assign pnf_per_byte = compare_valid_reg;
assign pause_be = (reset_data & test_dm_pin_mode) | ~test_dm_pin_mode;
assign local_be = be;
assign local_size = size;
assign size = (full_burst_on == 0)? 1'd1 :
LOCAL_BURST_LEN_s[5 : 0];
assign reached_max_address = ((test_dm_pin_mode | test_addr_pin_mode | state == 5'd9) & (row_addr == MAX_ROW_PIN)) || ((test_seq_addr_mode | test_incomplete_writes_mode) & (col_addr == (max_col_value)) & (row_addr == MAX_ROW) & (bank_addr == MAX_BANK) & (cs_addr == MAX_CHIPSEL));
assign addr_value = ((test_incomplete_writes_mode & write_req & ~full_burst_on) == 0)? 8 :
4;
assign pnf_persist_compare = (rdata_valid_flag_reg_2 == 0)? 1'd1 :
pnf_persist1;
ddr3_int_ex_lfsr8 LFSRGEN_0_lfsr_inst
(
.clk (clk),
.data (dgen_data[7 : 0]),
.enable (dgen_enable),
.ldata (dgen_ldata[7 : 0]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_0_lfsr_inst.seed = 1;
// 8 bit comparator per local byte lane
assign compare[0] = (dgen_data[7 : 0] & {8 {be[0]}}) === local_rdata[7 : 0];
ddr3_int_ex_lfsr8 LFSRGEN_1_lfsr_inst
(
.clk (clk),
.data (dgen_data[15 : 8]),
.enable (dgen_enable),
.ldata (dgen_ldata[15 : 8]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_1_lfsr_inst.seed = 11;
// 8 bit comparator per local byte lane
assign compare[1] = (dgen_data[15 : 8] & {8 {be[1]}}) === local_rdata[15 : 8];
ddr3_int_ex_lfsr8 LFSRGEN_2_lfsr_inst
(
.clk (clk),
.data (dgen_data[23 : 16]),
.enable (dgen_enable),
.ldata (dgen_ldata[23 : 16]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_2_lfsr_inst.seed = 21;
// 8 bit comparator per local byte lane
assign compare[2] = (dgen_data[23 : 16] & {8 {be[2]}}) === local_rdata[23 : 16];
ddr3_int_ex_lfsr8 LFSRGEN_3_lfsr_inst
(
.clk (clk),
.data (dgen_data[31 : 24]),
.enable (dgen_enable),
.ldata (dgen_ldata[31 : 24]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_3_lfsr_inst.seed = 31;
// 8 bit comparator per local byte lane
assign compare[3] = (dgen_data[31 : 24] & {8 {be[3]}}) === local_rdata[31 : 24];
ddr3_int_ex_lfsr8 LFSRGEN_4_lfsr_inst
(
.clk (clk),
.data (dgen_data[39 : 32]),
.enable (dgen_enable),
.ldata (dgen_ldata[39 : 32]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_4_lfsr_inst.seed = 41;
// 8 bit comparator per local byte lane
assign compare[4] = (dgen_data[39 : 32] & {8 {be[4]}}) === local_rdata[39 : 32];
ddr3_int_ex_lfsr8 LFSRGEN_5_lfsr_inst
(
.clk (clk),
.data (dgen_data[47 : 40]),
.enable (dgen_enable),
.ldata (dgen_ldata[47 : 40]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_5_lfsr_inst.seed = 51;
// 8 bit comparator per local byte lane
assign compare[5] = (dgen_data[47 : 40] & {8 {be[5]}}) === local_rdata[47 : 40];
ddr3_int_ex_lfsr8 LFSRGEN_6_lfsr_inst
(
.clk (clk),
.data (dgen_data[55 : 48]),
.enable (dgen_enable),
.ldata (dgen_ldata[55 : 48]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_6_lfsr_inst.seed = 61;
// 8 bit comparator per local byte lane
assign compare[6] = (dgen_data[55 : 48] & {8 {be[6]}}) === local_rdata[55 : 48];
ddr3_int_ex_lfsr8 LFSRGEN_7_lfsr_inst
(
.clk (clk),
.data (dgen_data[63 : 56]),
.enable (dgen_enable),
.ldata (dgen_ldata[63 : 56]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_7_lfsr_inst.seed = 71;
// 8 bit comparator per local byte lane
assign compare[7] = (dgen_data[63 : 56] & {8 {be[7]}}) === local_rdata[63 : 56];
ddr3_int_ex_lfsr8 LFSRGEN_8_lfsr_inst
(
.clk (clk),
.data (dgen_data[71 : 64]),
.enable (dgen_enable),
.ldata (dgen_ldata[71 : 64]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_8_lfsr_inst.seed = 81;
// 8 bit comparator per local byte lane
assign compare[8] = (dgen_data[71 : 64] & {8 {be[8]}}) === local_rdata[71 : 64];
ddr3_int_ex_lfsr8 LFSRGEN_9_lfsr_inst
(
.clk (clk),
.data (dgen_data[79 : 72]),
.enable (dgen_enable),
.ldata (dgen_ldata[79 : 72]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_9_lfsr_inst.seed = 91;
// 8 bit comparator per local byte lane
assign compare[9] = (dgen_data[79 : 72] & {8 {be[9]}}) === local_rdata[79 : 72];
ddr3_int_ex_lfsr8 LFSRGEN_10_lfsr_inst
(
.clk (clk),
.data (dgen_data[87 : 80]),
.enable (dgen_enable),
.ldata (dgen_ldata[87 : 80]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_10_lfsr_inst.seed = 101;
// 8 bit comparator per local byte lane
assign compare[10] = (dgen_data[87 : 80] & {8 {be[10]}}) === local_rdata[87 : 80];
ddr3_int_ex_lfsr8 LFSRGEN_11_lfsr_inst
(
.clk (clk),
.data (dgen_data[95 : 88]),
.enable (dgen_enable),
.ldata (dgen_ldata[95 : 88]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_11_lfsr_inst.seed = 111;
// 8 bit comparator per local byte lane
assign compare[11] = (dgen_data[95 : 88] & {8 {be[11]}}) === local_rdata[95 : 88];
ddr3_int_ex_lfsr8 LFSRGEN_12_lfsr_inst
(
.clk (clk),
.data (dgen_data[103 : 96]),
.enable (dgen_enable),
.ldata (dgen_ldata[103 : 96]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_12_lfsr_inst.seed = 121;
// 8 bit comparator per local byte lane
assign compare[12] = (dgen_data[103 : 96] & {8 {be[12]}}) === local_rdata[103 : 96];
ddr3_int_ex_lfsr8 LFSRGEN_13_lfsr_inst
(
.clk (clk),
.data (dgen_data[111 : 104]),
.enable (dgen_enable),
.ldata (dgen_ldata[111 : 104]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_13_lfsr_inst.seed = 131;
// 8 bit comparator per local byte lane
assign compare[13] = (dgen_data[111 : 104] & {8 {be[13]}}) === local_rdata[111 : 104];
ddr3_int_ex_lfsr8 LFSRGEN_14_lfsr_inst
(
.clk (clk),
.data (dgen_data[119 : 112]),
.enable (dgen_enable),
.ldata (dgen_ldata[119 : 112]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_14_lfsr_inst.seed = 141;
// 8 bit comparator per local byte lane
assign compare[14] = (dgen_data[119 : 112] & {8 {be[14]}}) === local_rdata[119 : 112];
ddr3_int_ex_lfsr8 LFSRGEN_15_lfsr_inst
(
.clk (clk),
.data (dgen_data[127 : 120]),
.enable (dgen_enable),
.ldata (dgen_ldata[127 : 120]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_15_lfsr_inst.seed = 151;
// 8 bit comparator per local byte lane
assign compare[15] = (dgen_data[127 : 120] & {8 {be[15]}}) === local_rdata[127 : 120];
//
//-----------------------------------------------------------------
//Main clocked process
//-----------------------------------------------------------------
//Read / Write control state machine & address counter
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
//Reset - asynchronously force all register outputs LOW
state <= 5'd0;
write_req <= 1'b0;
read_req <= 1'b0;
burst_begin <= 1'b0;
burst_beat_count <= 0;
dgen_load <= 1'b0;
wait_first_write_data <= 1'b0;
test_complete <= 1'b0;
reset_data <= 1'b0;
reset_be <= 1'b0;
writes_remaining <= 0;
reads_remaining <= 0;
test_addr_pin <= 1'b0;
test_dm_pin <= 1'b0;
test_seq_addr <= 1'b0;
test_incomplete_writes <= 1'b0;
test_addr_pin_mode <= 1'b0;
test_dm_pin_mode <= 1'b0;
test_seq_addr_mode <= 1'b0;
test_incomplete_writes_mode <= 1'b0;
full_burst_on <= 1'b1;
p_state_on <= 1'b0;
dgen_enable <= 1'b1;
end
else
begin
if (write_req & local_ready)
begin
if (wdata_req)
writes_remaining <= writes_remaining + (size - 1);
else
writes_remaining <= writes_remaining + size;
end
else if ((wdata_req) & (writes_remaining > 0))
//size
writes_remaining <= writes_remaining - 1'b1;
else
writes_remaining <= writes_remaining;
if ((read_req | p_read_req) & local_ready)
begin
if (local_rdata_valid)
reads_remaining <= reads_remaining + (size - 1);
else
reads_remaining <= reads_remaining + size;
end
else if ((local_rdata_valid) & (reads_remaining > 0))
reads_remaining <= reads_remaining - 1'b1;
else
reads_remaining <= reads_remaining;
case (state)
5'd0: begin
test_addr_pin <= test_addr_pin_on;
test_dm_pin <= test_dm_pin_on;
test_seq_addr <= test_seq_addr_on;
test_incomplete_writes <= test_incomplete_writes_on;
test_complete <= 1'b0;
state <= 5'd1;
end // 5'd0
5'd1: begin
//Reset just in case!
reset_address <= 1'b0;
reset_be <= 1'b0;
write_req <= 1'b1;
writes_remaining <= 1'b0;
reads_remaining <= 1'b0;
wait_first_write_data <= 1'b1;
dgen_enable <= 1'b1;
if (test_seq_addr == 1'b1)
begin
test_seq_addr_mode <= 1;
if (avalon_burst_mode == 0)
begin
state <= 5'd5;
burst_begin <= 1'b1;
end
else if (avalon_burst_mode == 1)
begin
state <= 5'd13;
burst_begin <= 1'b1;
end
end
else if (test_incomplete_writes == 1'b1)
begin
full_burst_on <= 1'b0;
test_incomplete_writes_mode <= 1;
state <= 5'd5;
if (avalon_burst_mode == 1)
burst_begin <= 1'b1;
end
else if (test_dm_pin == 1'b1)
begin
reset_data <= 1'b1;
test_dm_pin_mode <= 1;
if (avalon_burst_mode == 0)
begin
burst_begin <= 1'b1;
state <= 5'd2;
end
else
begin
burst_begin <= 1'b1;
state <= 5'd10;
end
end
else if (test_addr_pin == 1'b1)
begin
test_addr_pin_mode <= 1;
if (avalon_burst_mode == 0)
begin
burst_begin <= 1'b1;
state <= 5'd5;
end
else if (avalon_burst_mode == 1)
begin
state <= 5'd13;
burst_begin <= 1'b1;
end
end
else
begin
write_req <= 1'b0;
wait_first_write_data <= 1'b0;
state <= 5'd9;
end
end // 5'd1
5'd10: begin
wait_first_write_data <= 1'b0;
burst_begin <= 1'b0;
if (write_req & local_ready)
begin
burst_beat_count <= burst_beat_count + 1'b1;
state <= 5'd11;
end
end // 5'd10
5'd11: begin
if (write_req & local_ready)
if (burst_beat_count == size - 1'b1)
begin
burst_beat_count <= 0;
burst_begin <= 1'b1;
if (reached_max_address)
state <= 5'd12;
else
state <= 5'd10;
end
else
burst_beat_count <= burst_beat_count + 1'b1;
end // 5'd11
5'd12: begin
burst_begin <= 1'b0;
if (write_req & local_ready)
state <= 5'd3;
end // 5'd12
5'd13: begin
wait_first_write_data <= 1'b0;
burst_begin <= 1'b0;
reset_be <= 1'b0;
if (write_req & local_ready)
begin
burst_beat_count <= burst_beat_count + 1'b1;
state <= 5'd14;
end
end // 5'd13
5'd14: begin
if (write_req & local_ready)
if (burst_beat_count == size - 1'b1)
begin
burst_beat_count <= 0;
burst_begin <= 1'b1;
if (reached_max_address)
state <= 5'd15;
else
state <= 5'd13;
end
else
burst_beat_count <= burst_beat_count + 1'b1;
end // 5'd14
5'd15: begin
if (write_req & local_ready)
begin
reset_address <= 1'b1;
burst_begin <= 1'b0;
state <= 5'd6;
end
end // 5'd15
5'd16: begin
dgen_load <= 1'b0;
reset_be <= 1'b0;
if (local_ready & read_req)
if (reached_max_address)
begin
read_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd8;
end
end // 5'd16
5'd2: begin
wait_first_write_data <= 1'b0;
if (write_req & local_ready)
if (reached_max_address)
begin
write_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd3;
end
end // 5'd2
5'd3: begin
if (avalon_burst_mode == 0)
begin
if (!wdata_req)
if (writes_remaining == 0)
begin
reset_be <= 1'b1;
reset_address <= 1'b1;
dgen_load <= 1'b1;
state <= 5'd4;
end
end
else if (write_req & local_ready)
begin
reset_be <= 1'b1;
write_req <= 1'b0;
reset_address <= 1'b1;
dgen_load <= 1'b1;
state <= 5'd4;
end
end // 5'd3
5'd4: begin
reset_address <= 1'b0;
dgen_load <= 1'b0;
reset_be <= 1'b0;
reset_data <= 1'b0;
write_req <= 1'b1;
if (avalon_burst_mode == 0)
begin
burst_begin <= 1'b1;
state <= 5'd5;
end
else
begin
burst_begin <= 1'b1;
state <= 5'd13;
end
end // 5'd4
5'd5: begin
wait_first_write_data <= 1'b0;
if (write_req & local_ready)
if (reached_max_address)
begin
reset_address <= 1'b1;
write_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd6;
if (test_incomplete_writes_mode)
full_burst_on <= 1'b1;
end
end // 5'd5
5'd6: begin
reset_address <= 1'b0;
if (avalon_burst_mode == 0)
begin
if (writes_remaining == 0)
begin
dgen_load <= 1'b1;
reset_be <= 1'b1;
read_req <= 1'b1;
burst_begin <= 1'b1;
state <= 5'd7;
end
end
else if (test_incomplete_writes_mode)
begin
dgen_load <= 1'b1;
read_req <= 1'b1;
burst_begin <= 1'b1;
state <= 5'd16;
end
else if (write_req & local_ready)
begin
write_req <= 1'b0;
dgen_load <= 1'b1;
reset_be <= 1'b1;
read_req <= 1'b1;
burst_begin <= 1'b1;
state <= 5'd16;
end
end // 5'd6
5'd7: begin
dgen_load <= 1'b0;
reset_be <= 1'b0;
if (local_ready & read_req)
if (reached_max_address)
begin
read_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd8;
end
end // 5'd7
5'd8: begin
if (reads_remaining == 1'b0)
begin
reset_address <= 1'b1;
if (test_seq_addr)
begin
test_seq_addr <= 1'b0;
test_seq_addr_mode <= 1'b0;
state <= 5'd1;
end
else if (test_incomplete_writes)
begin
test_incomplete_writes <= 1'b0;
test_incomplete_writes_mode <= 1'b0;
state <= 5'd1;
end
else if (test_dm_pin)
begin
test_dm_pin <= 1'b0;
test_dm_pin_mode <= 1'b0;
state <= 5'd1;
end
else if (test_addr_pin)
begin
test_addr_pin_mode <= 1'b0;
dgen_load <= 1'b1;
state <= 5'd9;
end
else
state <= 5'd9;
end
end // 5'd8
5'd9: begin
reset_address <= 1'b0;
reset_be <= 1'b0;
dgen_load <= 1'b0;
if (powerdn_on == 1'b0 & selfrfsh_on == 1'b0)
begin
test_complete <= 1'b1;
p_state_on <= 1'b0;
dgen_enable <= restart_LFSR_n;
state <= 5'd0;
end
else if (reached_max_address & reads_remaining == 0)
begin
p_state_on <= 1'b1;
reset_address <= 1'b1;
reset_be <= 1'b1;
dgen_load <= 1'b1;
end
end // 5'd9
endcase // state
end
end
//
//-----------------------------------------------------------------
//Logics that detect the first read data
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rdata_valid_flag <= 1'b0;
else if (local_rdata_valid)
rdata_valid_flag <= 1'b1;
end
//
//-----------------------------------------------------------------
//Address Generator Process
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
cs_addr <= 0;
bank_addr <= 0;
row_addr <= 0;
col_addr <= 0;
end
else if (reset_address)
begin
cs_addr <= MIN_CHIPSEL;
row_addr <= 0;
bank_addr <= 0;
col_addr <= 0;
end
else if (((local_ready & write_req & (test_dm_pin_mode | test_addr_pin_mode)) & (state == 5'd2 | state == 5'd5 | state == 5'd10 | state == 5'd13)) | ((local_ready & read_req & (test_dm_pin_mode | test_addr_pin_mode)) & (state == 5'd7 | state == 5'd16)) | ((local_ready & p_read_req) & (state == 5'd9)))
begin
col_addr[9 : 3] <= {col_addr[8 : 3],col_addr[9]};
row_addr[13 : 0] <= {row_addr[12 : 0],row_addr[13]};
if (row_addr == 14'd0)
begin
col_addr <= 10'd8;
row_addr <= 14'd1;
end
else if (row_addr == {1'b1,{13{1'b0}}})
begin
col_addr <= {{6{1'b1}},{4{1'b0}}};
row_addr <= {{13{1'b1}},1'b0};
end
else if (row_addr == {1'b0,{13{1'b1}}})
begin
col_addr <= {{7{1'b1}},{3{1'b0}}};
row_addr <= {14{1'b1}};
end
if (bank_addr == MAX_BANK)
bank_addr <= 0;
else
bank_addr <= bank_addr + 1'b1;
if (cs_addr == MAX_CHIPSEL)
cs_addr <= MIN_CHIPSEL;
else
cs_addr <= cs_addr + 1'b1;
end
else if ((local_ready & write_req & (test_seq_addr_mode | test_incomplete_writes_mode) & (state == 5'd2 | state == 5'd5 | state == 5'd10 | state == 5'd13)) | ((local_ready & read_req & (test_seq_addr_mode | test_incomplete_writes_mode)) & (state == 5'd7 | state == 5'd16)))
if (col_addr >= max_col_value)
begin
col_addr <= 0;
if (row_addr == MAX_ROW)
begin
row_addr <= 0;
if (bank_addr == MAX_BANK)
begin
bank_addr <= 0;
if (cs_addr == MAX_CHIPSEL)
//reached_max_count <= TRUE
//(others => '0')
cs_addr <= MIN_CHIPSEL;
else
cs_addr <= cs_addr + 1'b1;
end
else
bank_addr <= bank_addr + 1'b1;
end
else
row_addr <= row_addr + 1'b1;
end
else
col_addr <= col_addr + addr_value;
end
//
//-----------------------------------------------------------------
//Byte Enable Generator Process
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
be <= {16{1'b1}};
else if (reset_be)
be <= 16'd1;
else if (enable_be)
be[15 : 0] <= {be[14 : 0],be[15]};
else if (pause_be)
be <= {16{1'b1}};
else
be <= be;
end
//------------------------------------------------------------
//LFSR re-load data storage
//Comparator masking and test pass signal generation
//------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dgen_ldata <= 0;
last_wdata_req <= 1'b0;
//all ones
compare_valid <= {16 {1'b1}};
//all ones
compare_valid_reg <= {16 {1'b1}};
pnf_persist <= 1'b0;
pnf_persist1 <= 1'b0;
//all ones
compare_reg <= {16 {1'b1}};
last_rdata_valid <= 1'b0;
rdata_valid_flag_reg <= 1'b0;
rdata_valid_flag_reg_2 <= 1'b0;
end
else
begin
last_wdata_req <= wdata_req;
last_rdata_valid <= local_rdata_valid;
rdata_valid_flag_reg <= rdata_valid_flag;
rdata_valid_flag_reg_2 <= rdata_valid_flag_reg;
compare_reg <= compare;
if (wait_first_write_data)
dgen_ldata <= dgen_data;
//Enable the comparator result when read data is valid
if (last_rdata_valid)
compare_valid <= compare_reg;
//Create the overall persistent passnotfail output
if (&compare_valid & rdata_valid_flag_reg & pnf_persist_compare)
pnf_persist1 <= 1'b1;
else
pnf_persist1 <= 1'b0;
//Extra register stage to help Tco / Fmax on comparator output pins
compare_valid_reg <= compare_valid;
pnf_persist <= pnf_persist1;
end
end
endmodule |
module sky130_fd_sc_lp__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module ISP1362 (
input wire avs_hc_clk_iCLK, // hc_clock.clk
input wire avs_hc_reset_n_iRST_N, // hc_reset_n.reset_n
input wire [15:0] avs_hc_writedata_iDATA, // hc.writedata
output wire [15:0] avs_hc_readdata_oDATA, // .readdata
input wire avs_hc_address_iADDR, // .address
input wire avs_hc_read_n_iRD_N, // .read_n
input wire avs_hc_write_n_iWR_N, // .write_n
input wire avs_hc_chipselect_n_iCS_N, // .chipselect_n
output wire avs_hc_irq_n_oINT0_N, // hc_irq.irq_n
input wire avs_dc_clk_iCLK, // dc_clock.clk
input wire avs_dc_reset_n_iRST_N, // dc_reset_n.reset_n
input wire [15:0] avs_dc_writedata_iDATA, // dc.writedata
output wire [15:0] avs_dc_readdata_oDATA, // .readdata
input wire avs_dc_address_iADDR, // .address
input wire avs_dc_read_n_iRD_N, // .read_n
input wire avs_dc_write_n_iWR_N, // .write_n
input wire avs_dc_chipselect_n_iCS_N, // .chipselect_n
output wire avs_dc_irq_n_oINT0_N, // dc_irq.irq_n
inout wire [15:0] USB_DATA, // conduit_end.export
output wire [1:0] USB_ADDR, // .export
output wire USB_RD_N, // .export
output wire USB_WR_N, // .export
output wire USB_CS_N, // .export
output wire USB_RST_N, // .export
input wire USB_INT0, // .export
input wire USB_INT1 // .export
);
ISP1362_IF isp1362 (
.avs_hc_clk_iCLK (avs_hc_clk_iCLK), // hc_clock.clk
.avs_hc_reset_n_iRST_N (avs_hc_reset_n_iRST_N), // hc_reset_n.reset_n
.avs_hc_writedata_iDATA (avs_hc_writedata_iDATA), // hc.writedata
.avs_hc_readdata_oDATA (avs_hc_readdata_oDATA), // .readdata
.avs_hc_address_iADDR (avs_hc_address_iADDR), // .address
.avs_hc_read_n_iRD_N (avs_hc_read_n_iRD_N), // .read_n
.avs_hc_write_n_iWR_N (avs_hc_write_n_iWR_N), // .write_n
.avs_hc_chipselect_n_iCS_N (avs_hc_chipselect_n_iCS_N), // .chipselect_n
.avs_hc_irq_n_oINT0_N (avs_hc_irq_n_oINT0_N), // hc_irq.irq_n
.avs_dc_clk_iCLK (avs_dc_clk_iCLK), // dc_clock.clk
.avs_dc_reset_n_iRST_N (avs_dc_reset_n_iRST_N), // dc_reset_n.reset_n
.avs_dc_writedata_iDATA (avs_dc_writedata_iDATA), // dc.writedata
.avs_dc_readdata_oDATA (avs_dc_readdata_oDATA), // .readdata
.avs_dc_address_iADDR (avs_dc_address_iADDR), // .address
.avs_dc_read_n_iRD_N (avs_dc_read_n_iRD_N), // .read_n
.avs_dc_write_n_iWR_N (avs_dc_write_n_iWR_N), // .write_n
.avs_dc_chipselect_n_iCS_N (avs_dc_chipselect_n_iCS_N), // .chipselect_n
.avs_dc_irq_n_oINT0_N (avs_dc_irq_n_oINT0_N), // dc_irq.irq_n
.USB_DATA (USB_DATA), // conduit_end.export
.USB_ADDR (USB_ADDR), // .export
.USB_RD_N (USB_RD_N), // .export
.USB_WR_N (USB_WR_N), // .export
.USB_CS_N (USB_CS_N), // .export
.USB_RST_N (USB_RST_N), // .export
.USB_INT0 (USB_INT0), // .export
.USB_INT1 (USB_INT1) // .export
);
endmodule |
module dmac_reset_manager_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`define TIMEOUT 1000000
`include "tb_base.v"
reg clk_a = 1'b0;
reg clk_b = 1'b0;
reg clk_c = 1'b0;
reg [5:0] resetn_shift = 'h0;
reg [10:0] counter = 'h00;
reg ctrl_enable = 1'b0;
reg ctrl_pause = 1'b0;
always #10 clk_a <= ~clk_a;
always #3 clk_b <= ~clk_b;
always #7 clk_c <= ~clk_c;
always @(posedge clk_a) begin
counter <= counter + 1'b1;
if (counter == 'h60 || counter == 'h150 || counter == 'h185) begin
ctrl_enable <= 1'b1;
end else if (counter == 'h100 || counter == 'h110 || counter == 'h180) begin
ctrl_enable <= 1'b0;
end
if (counter == 'h160) begin
ctrl_pause = 1'b1;
end else if (counter == 'h190) begin
ctrl_pause = 1'b0;
end
end
reg [15:0] req_enabled_shift;
wire req_enable;
wire req_enabled = req_enabled_shift[15];
reg [15:0] dest_enabled_shift;
wire dest_enable;
wire dest_enabled = dest_enabled_shift[15];
reg [15:0] src_enabled_shift;
wire src_enable;
wire src_enabled = src_enabled_shift[15];
always @(posedge clk_a) begin
req_enabled_shift <= {req_enabled_shift[14:0],req_enable};
end
always @(posedge clk_b) begin
dest_enabled_shift <= {dest_enabled_shift[14:0],dest_enable};
end
always @(posedge clk_c) begin
src_enabled_shift <= {src_enabled_shift[14:0],src_enable};
end
axi_dmac_reset_manager i_reset_manager (
.clk(clk_a),
.resetn(resetn),
.ctrl_pause(ctrl_pause),
.ctrl_enable(ctrl_enable),
.req_enable(req_enable),
.req_enabled(req_enabled),
.dest_clk(clk_b),
.dest_ext_resetn(1'b0),
.dest_enable(dest_enable),
.dest_enabled(dest_enabled),
.src_clk(clk_c),
.src_ext_resetn(1'b0),
.src_enable(src_enable),
.src_enabled(src_enabled)
);
endmodule |
module sky130_fd_sc_hs__nand4 (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule |
module FP16BMulS0Of2(
input clk,
input rst,
input [15:0] arg_0,
input [15:0] arg_1,
output ret_0,
output [7:0] ret_1,
output [7:0] ret_2,
output [8:0] ret_3);
wire s0;
wire s1;
wire [7:0] e0;
wire [7:0] e1;
wire [6:0] f0;
wire [6:0] f1;
wire [7:0] ff0;
wire [7:0] ff1;
wire [15:0] z;
wire [8:0] zz;
assign s0 = arg_0[15:15];
assign s1 = arg_1[15:15];
assign e0 = arg_0[14:7];
assign e1 = arg_1[14:7];
assign f0 = arg_0[6:0];
assign f1 = arg_1[6:0];
// sign
assign ret_0 = s0 ^ s1;
// exponent
assign ret_1 = e0;
assign ret_2 = e1;
assign ff0 = {(e0 == 0 ? 1'b0 : 1'b1), f0};
assign ff1 = {(e1 == 0 ? 1'b0 : 1'b1), f1};
assign z = ff0 * ff1;
assign zz = z[15:7];
// fraction
assign ret_3 = zz;
endmodule |
module FP16BMulS1Of2(
input clk,
input rst,
input arg_0,
input [7:0] arg_1,
input [7:0] arg_2,
input [8:0] arg_3,
output [15:0] ret_0);
wire s;
wire c;
wire [6:0] fc;
wire [6:0] uc;
wire [9:0] e10;
wire [7:0] e;
wire underflow;
wire overflow;
wire infinput;
assign s = arg_0;
assign c = arg_3[8:8];
assign e10 = arg_1 + arg_2 - 127 + c;
assign fc = c ? arg_3[7:1] : arg_3[6:0];
assign infinput = (arg_1 == 255) || (arg_2 == 255);
// e10[9:9] negative by subtraction.
// e10[8:8] overflow (> 255) by addition.
assign underflow = e10[9:9];
assign overflow = !underflow && (e10[8:8] || e10[7:0] == 255 || infinput);
assign e = underflow ? 0 : (overflow ? 255 : e10[7:0]);
assign uc = (underflow || e10[7:0] == 0) ? 0 : fc;
assign ret_0 = {s, e, uc};
endmodule |
module util_upack (
// dac interface
dac_clk,
dac_enable_0,
dac_valid_0,
dac_data_0,
upack_valid_0,
dac_enable_1,
dac_valid_1,
dac_data_1,
upack_valid_1,
dac_enable_2,
dac_valid_2,
dac_data_2,
upack_valid_2,
dac_enable_3,
dac_valid_3,
dac_data_3,
upack_valid_3,
dac_enable_4,
dac_valid_4,
dac_data_4,
upack_valid_4,
dac_enable_5,
dac_valid_5,
dac_data_5,
upack_valid_5,
dac_enable_6,
dac_valid_6,
dac_data_6,
upack_valid_6,
dac_enable_7,
dac_valid_7,
dac_data_7,
upack_valid_7,
dma_xfer_in,
dac_xfer_out,
// fifo interface
dac_valid,
dac_sync,
dac_data);
// parameters
parameter CH_DW = 32;
parameter CH_CNT = 8;
localparam M_CNT = 8;
localparam P_CNT = CH_CNT;
localparam CH_SCNT = CH_DW/16;
localparam M_WIDTH = CH_DW*M_CNT;
localparam P_WIDTH = CH_DW*P_CNT;
// dac interface
input dac_clk;
input dac_enable_0;
input dac_valid_0;
output [(CH_DW-1):0] dac_data_0;
output upack_valid_0;
input dac_enable_1;
input dac_valid_1;
output [(CH_DW-1):0] dac_data_1;
output upack_valid_1;
input dac_enable_2;
input dac_valid_2;
output [(CH_DW-1):0] dac_data_2;
output upack_valid_2;
input dac_enable_3;
input dac_valid_3;
output [(CH_DW-1):0] dac_data_3;
output upack_valid_3;
input dac_enable_4;
input dac_valid_4;
output [(CH_DW-1):0] dac_data_4;
output upack_valid_4;
input dac_enable_5;
input dac_valid_5;
output [(CH_DW-1):0] dac_data_5;
output upack_valid_5;
input dac_enable_6;
input dac_valid_6;
output [(CH_DW-1):0] dac_data_6;
output upack_valid_6;
input dac_enable_7;
input dac_valid_7;
output [(CH_DW-1):0] dac_data_7;
output upack_valid_7;
input dma_xfer_in;
output dac_xfer_out;
// fifo interface
output dac_valid;
output dac_sync;
input [((CH_CNT*CH_DW)-1):0] dac_data;
// internal registers
reg dac_valid = 'd0;
reg dac_sync = 'd0;
reg [(M_WIDTH-1):0] dac_dsf_data = 'd0;
reg [ 7:0] dac_dmx_enable = 'd0;
reg xfer_valid_d1;
reg xfer_valid_d2;
reg xfer_valid_d3;
reg xfer_valid_d4;
reg xfer_valid_d5;
reg dac_xfer_out;
// internal signals
wire dac_valid_s;
wire dac_dsf_valid_s[(M_CNT-1):0];
wire dac_dsf_sync_s[(M_CNT-1):0];
wire [(M_WIDTH-1):0] dac_dsf_data_s[(M_CNT-1):0];
wire [(CH_SCNT-1):0] dac_dmx_enable_7_s;
wire [(CH_SCNT-1):0] dac_dmx_enable_6_s;
wire [(CH_SCNT-1):0] dac_dmx_enable_5_s;
wire [(CH_SCNT-1):0] dac_dmx_enable_4_s;
wire [(CH_SCNT-1):0] dac_dmx_enable_3_s;
wire [(CH_SCNT-1):0] dac_dmx_enable_2_s;
wire [(CH_SCNT-1):0] dac_dmx_enable_1_s;
wire [(CH_SCNT-1):0] dac_dmx_enable_0_s;
// loop variables
genvar n;
// parameter breaks here (max. 8) -- reduce won't work across 2d arrays.
assign dac_valid_s = dac_valid_7 | dac_valid_6 | dac_valid_5 | dac_valid_4 |
dac_valid_3 | dac_valid_2 | dac_valid_1 | dac_valid_0;
assign upack_valid_0 = | dac_dmx_enable & dac_enable_0 & dac_xfer_out;
assign upack_valid_1 = | dac_dmx_enable & dac_enable_1 & dac_xfer_out;
assign upack_valid_2 = | dac_dmx_enable & dac_enable_2 & dac_xfer_out;
assign upack_valid_3 = | dac_dmx_enable & dac_enable_3 & dac_xfer_out;
assign upack_valid_4 = | dac_dmx_enable & dac_enable_4 & dac_xfer_out;
assign upack_valid_5 = | dac_dmx_enable & dac_enable_5 & dac_xfer_out;
assign upack_valid_6 = | dac_dmx_enable & dac_enable_6 & dac_xfer_out;
assign upack_valid_7 = | dac_dmx_enable & dac_enable_7 & dac_xfer_out;
always @(posedge dac_clk) begin
xfer_valid_d1 <= dma_xfer_in;
xfer_valid_d2 <= xfer_valid_d1;
xfer_valid_d3 <= xfer_valid_d2;
xfer_valid_d4 <= xfer_valid_d3;
xfer_valid_d5 <= xfer_valid_d4;
if (dac_dmx_enable[P_CNT-1] == 1'b1) begin
dac_xfer_out <= xfer_valid_d4;
end else begin
dac_xfer_out <= xfer_valid_d5;
end
end
always @(posedge dac_clk) begin
dac_valid <= dac_dsf_valid_s[7] | dac_dsf_valid_s[6] |
dac_dsf_valid_s[5] | dac_dsf_valid_s[4] |
dac_dsf_valid_s[3] | dac_dsf_valid_s[2] |
dac_dsf_valid_s[1] | dac_dsf_valid_s[0];
dac_sync <= dac_dsf_sync_s[7] | dac_dsf_sync_s[6] |
dac_dsf_sync_s[5] | dac_dsf_sync_s[4] |
dac_dsf_sync_s[3] | dac_dsf_sync_s[2] |
dac_dsf_sync_s[1] | dac_dsf_sync_s[0];
dac_dsf_data <= dac_dsf_data_s[7] | dac_dsf_data_s[6] |
dac_dsf_data_s[5] | dac_dsf_data_s[4] |
dac_dsf_data_s[3] | dac_dsf_data_s[2] |
dac_dsf_data_s[1] | dac_dsf_data_s[0];
dac_dmx_enable[7] <= | dac_dmx_enable_7_s;
dac_dmx_enable[6] <= | dac_dmx_enable_6_s;
dac_dmx_enable[5] <= | dac_dmx_enable_5_s;
dac_dmx_enable[4] <= | dac_dmx_enable_4_s;
dac_dmx_enable[3] <= | dac_dmx_enable_3_s;
dac_dmx_enable[2] <= | dac_dmx_enable_2_s;
dac_dmx_enable[1] <= | dac_dmx_enable_1_s;
dac_dmx_enable[0] <= | dac_dmx_enable_0_s;
end
// store & fwd
generate
if (P_CNT < M_CNT) begin
for (n = P_CNT; n < M_CNT; n = n + 1) begin: g_def
assign dac_dsf_valid_s[n] = 'd0;
assign dac_dsf_sync_s[n] = 'd0;
assign dac_dsf_data_s[n] = 'd0;
end
end
for (n = 0; n < P_CNT; n = n + 1) begin: g_dsf
util_upack_dsf #(
.P_CNT (P_CNT),
.M_CNT (M_CNT),
.CH_DW (CH_DW),
.CH_OCNT ((n+1)))
i_dsf (
.dac_clk (dac_clk),
.dac_valid (dac_valid_s),
.dac_data (dac_data),
.dac_dmx_enable (dac_dmx_enable[n]),
.dac_dsf_valid (dac_dsf_valid_s[n]),
.dac_dsf_sync (dac_dsf_sync_s[n]),
.dac_dsf_data (dac_dsf_data_s[n]));
end
endgenerate
// demux
generate
for (n = 0; n < CH_SCNT; n = n + 1) begin: g_dmx
util_upack_dmx i_dmx (
.dac_clk (dac_clk),
.dac_enable ({dac_enable_7, dac_enable_6, dac_enable_5, dac_enable_4,
dac_enable_3, dac_enable_2, dac_enable_1, dac_enable_0}),
.dac_data_0 (dac_data_0[((16*n)+15):(16*n)]),
.dac_data_1 (dac_data_1[((16*n)+15):(16*n)]),
.dac_data_2 (dac_data_2[((16*n)+15):(16*n)]),
.dac_data_3 (dac_data_3[((16*n)+15):(16*n)]),
.dac_data_4 (dac_data_4[((16*n)+15):(16*n)]),
.dac_data_5 (dac_data_5[((16*n)+15):(16*n)]),
.dac_data_6 (dac_data_6[((16*n)+15):(16*n)]),
.dac_data_7 (dac_data_7[((16*n)+15):(16*n)]),
.dac_dmx_enable ({dac_dmx_enable_7_s[n], dac_dmx_enable_6_s[n],
dac_dmx_enable_5_s[n], dac_dmx_enable_4_s[n],
dac_dmx_enable_3_s[n], dac_dmx_enable_2_s[n],
dac_dmx_enable_1_s[n], dac_dmx_enable_0_s[n]}),
.dac_dsf_data (dac_dsf_data[((M_CNT*16*(n+1))-1):(M_CNT*16*n)]));
end
endgenerate
endmodule |
module jtag_uart(
input clk_i,
input nreset_i,
input nwr_i,
input [7:0] data_i,
input rd_i,
output [7:0] data_o,
output txmt,
output txfl,
output rxmt,
output rxfl
);
//=======================================================
// JTAG Command Table
//=======================================================
`define TX 2'b00
`define RX 2'b01
`define STATUS 2'b10
`define BYPASS 2'b11
//=======================================================
// REG/WIRE declarations
//=======================================================
// Virtual JTAG signals, see Altera's Virtual JTAG Megafunction user guide for infoo
wire
[1:0] ir_out, ir_in;
wire
tdo,
tck,
tdi,
virtual_state_cdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir;
// VJTAG registers
wire [7:0] out_data; // Output buffer signals
reg [7:0] shift_buffer = 0; // Internal buffer for shifting in/out
reg cdr_delayed; // Capture data register delayed by half a clock cycle
reg sdr_delayed; // shift data register delayed by half a clock cycle
reg [1:0] bypass; // Bypass register
reg TXmt, TXfl, // Transmit empty, full signals
RXmt, RXfl; // Receive empty, full signals
// Stored instruction register, default to bypass
reg [1:0] ir = `BYPASS;
// Buffer management signals
wire out_full, out_empty;
wire in_full, in_empty;
//=======================================================
// Outputs
//=======================================================
assign ir_out = ir_in; // Just pass the IR out
// If the capture instruction register points to the bypass register then output
// the bypass register, or the shift register
assign tdo = (ir == `BYPASS) ? bypass[0] : shift_buffer[0];
assign txmt = TXmt;
assign txfl = TXfl;
assign rxmt = RXmt;
assign rxfl = RXfl;
//=======================================================
// Structural coding
//=======================================================
// Virtual JTAG - prep signals are on rising edge TCK, output on falling edge
// This connects to the internal signal trap hub - see the VJTAG MF User Guide
vjtag vjtag(
.ir_out(ir_out),
.tdo(tdo),
.ir_in(ir_in),
.tck(tck),
.tdi(tdi),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_cir(),
.virtual_state_e1dr(),
.virtual_state_e2dr(),
.virtual_state_pdr(),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.virtual_state_uir(virtual_state_uir)
);
// Output buffer FIFO, write clock is system clock
// read clock is the VJTAG TCK clock
buffer out(
.aclr(!nreset_i),
// Write signals
.data(data_i),
.wrclk(clk_i),
.wrreq(!nwr_i),
.wrfull(out_full),
// Read signals
.rdclk(!tck),
.rdreq(virtual_state_cdr & (ir == `TX)),
.q(out_data),
.rdempty(out_empty)
);
// Input buffer FIFO, write clock is VJTAG TCK clock
// read clock is the system clock
buffer in(
.aclr(!nreset_i),
// Write signals
.data(shift_buffer),
.wrclk(!tck),
.wrreq(virtual_state_udr & (ir == 2'h1)),
.wrfull(in_full),
// Read signals
.rdclk(!clk_i),
.rdreq(rd_i),
.q(data_o),
.rdempty(in_empty)
);
//=======================================================
// Procedural coding
//=======================================================
// Set the full/empty signals
always @(posedge tck)
begin
TXmt = out_empty;
RXfl = in_full;
end
// Set the full/empty signals
always @(posedge clk_i)
begin
TXfl = out_full;
RXmt = in_empty;
end
// VJTAG Controls for UART output
always @(negedge tck)
begin
// Delay the CDR signal by one half clock cycle
cdr_delayed = virtual_state_cdr;
sdr_delayed = virtual_state_sdr;
end
// Capture the instruction provided
always @(negedge tck)
begin
if( virtual_state_uir ) ir = ir_in;
end
// Data is clocked out on the falling edge, rising edge is for prep
always @(posedge tck)
begin
case( ir )
// Process output
`TX :
begin
if( cdr_delayed )
shift_buffer = out_data;
else
if( sdr_delayed )
shift_buffer = {tdi,shift_buffer[7:1]};
end
// Process input
`RX :
begin
if( sdr_delayed )
shift_buffer = {tdi,shift_buffer[7:1]};
end
// Process status request (only 4 bits are required to be shifted)
`STATUS :
begin
if( cdr_delayed )
shift_buffer = {4'b0000, RXfl, RXmt, TXfl, TXmt};
else
if( sdr_delayed )
shift_buffer = {tdi,shift_buffer[7:1]};
end
// Process input
default: // Bypass 2'b11
begin
if( sdr_delayed )
bypass = {tdi,bypass[1:1]};
end
endcase
end
endmodule |
module tbshftout(
output sout,
input [7:0] outbyte,
input ld,
input clk);
reg [7:0] register = 8'h00;
assign sout = register[7]; // MSB output
always @(negedge clk) begin
if(ld) begin
register <= outbyte;
end
else begin
register[7:1] <= register[6:0];
register[0] <= 0;
end
end
endmodule |
module tbshftin(
output [7:0] out,
input sin,
input clk);
reg [7:0] register = 8'h00;
assign out = register;
always @(posedge clk) begin
register[7:1] <= register[6:0];
register[0] = sin; // LSB input
end
endmodule |
module tbclkctr(
output [2:0] cycle,
input clk,
input enn);
reg [2:0] register = 3'b000;
assign cycle = register;
always @(posedge clk) begin
if(!enn)
register <= register + 1;
else
register = 0;
end
endmodule |
module tbseq(
output sold,
input [2:0] cycle);
reg [2:0] regsold = 0;
assign sold = regsold;
always @(cycle) begin
regsold = 0;
case(cycle)
4'h0:
regsold = 1;
4'h1, 4'h2, 4'h3, 4'h4,
4'h5, 4'h6, 4'h7:
regsold = 0;
default:
regsold = 1'bx;
endcase
end
endmodule |
module testbench;
reg sclk;
reg ssn;
reg clk;
reg currentlimit0;
reg currentlimit1;
reg currentlimit2;
reg tstn;
reg wdogdisn;
reg [7:0] outbyte;
reg [1:0] tach0;
reg [1:0] tach1;
reg [1:0] tach2;
wire mosi;
wire miso;
wire sold;
wire spioe;
wire motorena;
wire redled0;
wire [2:0] cycle;
wire [7:0] inbyte;
wire [1:0] pwm0;
wire [1:0] pwm1;
wire [1:0] pwm2;
wire [3:0] pwm40;
wire [3:0] pwm41;
wire [3:0] pwm42;
// Pull up miso so we don't get z's in the test shift register
pullup (pull1) (miso);
tbclkctr tbcc0(
.clk(sclk),
.enn(ssn),
.cycle(cycle));
tbseq tbs0(
.cycle(cycle),
.sold(sold));
tbshftout so0(
.clk(sclk),
.outbyte(outbyte),
.ld(sold),
.sout(mosi));
tbshftin si0(
.clk(sclk),
.sin(miso),
.out(inbyte));
root root0(
.clk(clk),
.sclk(sclk),
.ssn(ssn),
.mosi(mosi),
.tstn(tstn),
.wdogdisn(wdogdisn),
.currentlimit0(currentlimit0),
.currentlimit1(currentlimit1),
.currentlimit2(currentlimit2),
.tach0(tach0),
.tach1(tach1),
.tach2(tach2),
.miso(miso),
.motorena(motorena),
.redled0(redled0),
.pwm0(pwm0),
.pwm40(pwm40),
.pwm1(pwm1),
.pwm41(pwm41),
.pwm2(pwm2),
.pwm42(pwm42));
// Send a burst of 16 spiclks
task spiclkburst;
integer i;
begin
for(i = 0; i < 8; i = i + 1) begin
#16 sclk = 0;
#16 sclk= 1;
end
end
endtask
// Select the dut, and send a write transaction
task spiwrite([3:0] addr, [7:0] data);
begin
#80 ssn = 0;
#80 ssn = 0;
begin
outbyte = {1'b0, addr, 3'b0};
spiclkburst;
#80 outbyte = data;
spiclkburst;
end
#80 ssn = 0;
#80 ssn = 1;
end
endtask
// Select the dut, and send a read transaction
task spiread([3:0] addr);
begin
#80 ssn = 0;
#80 ssn = 0;
begin
outbyte = {1'b1, addr, 3'b0};
spiclkburst;
#80 outbyte = 8'h00;
spiclkburst;
end
#80 ssn = 0;
#80 ssn = 1;
end
endtask
// Crude assert task
task assert_compare_byte([7:0] actual, [7:0] expected);
begin
if(actual != expected) begin
$display("!!!!!************* Assertion Error in %m: is 8'h%h s/b 8'h%h *************!!!!!", actual, expected);
$finish;
end
end
endtask
// Combine spiread and assert_compare_byte tasks
task spiread_expect([3:0] addr, [7:0] expected);
begin
spiread(addr);
assert_compare_byte(inbyte, expected);
end
endtask
initial begin
$dumpvars(0, testbench);
outbyte = 0;
ssn = 1;
sclk = 0;
clk = 0;
currentlimit0 = 0;
currentlimit1 = 0;
currentlimit2 = 0;
tstn = 0;
wdogdisn = 1;
tach0 = 2'b00;
tach1 = 2'b00;
tach2 = 2'b00;
#2
sclk = 1;
// Clear any pending SPI transaction
#80
spiclkburst;
#80
spiclkburst;
#100
// Test async reset
ssn = 0;
#20
spiclkburst;
#20
ssn = 1;
#100
// Retrieve hardware configuration
spiread_expect(4'hd, 8'h30);
// Write motor0 config register
spiwrite(4'h2, 8'h01);
// Write motor1 config register
spiwrite(4'h6, 8'h02);
// Write motor2 config register
spiwrite(4'ha, 8'h04);
// Read them back
spiread_expect(4'h2, 8'h01);
spiread_expect(4'h6, 8'h02);
spiread_expect(4'ha, 8'h04);
// Set motor0,1, and 2 to 0 for other testing
spiwrite(4'h2, 8'h00);
spiwrite(4'h6, 8'h00);
spiwrite(4'ha, 8'h00);
// Set watchdog divisor
spiwrite(4'he, 8'h10);
// Test lower bits of watchdog register
spiwrite(4'hf, 8'h01);
spiread_expect(4'hf, 8'h01);
spiwrite(4'hf, 8'h03);
spiread_expect(4'hf, 8'h03);
spiwrite(4'hf, 8'h07);
spiread_expect(4'hf, 8'h07);
// Enable motor
spiwrite(4'hf,8'h0f);
// Wait for watchdog to trip
#10000
// Read watchdog register
spiread(4'hf);
spiread_expect(4'hf, 8'h8f);
// Reset the watchdog
spiwrite(4'hf,8'h80);
// Re-enable motor
spiwrite(4'hf,8'h0f);
// Read watchdog register
spiread_expect(4'hf, 8'h0f);
#20
// Disable watchdog
wdogdisn = 0;
// Read watchdog register
spiread(4'hf);
// Tickle tach signals
// Motor channel 0
tach0 = 2'b01;
#2000
spiread_expect(4'h0,8'h01);
spiread_expect(4'h1, 8'h00);
tach0 = 2'b11;
#2000
spiread_expect(4'h0,8'h02);
spiread_expect(4'h1, 8'h00);
tach0 = 2'b01;
#2000
spiread_expect(4'h0,8'h01);
spiread_expect(4'h1, 8'h00);
tach0 = 2'b00;
#2000
spiread_expect(4'h0,8'h00);
spiread_expect(4'h1, 8'h00);
tach0 = 2'b10;
#2000
spiread_expect(4'h0,8'hff);
spiread_expect(4'h1, 8'hff);
tach0 = 2'b00;
#2000
spiread_expect(4'h0,8'h00);
spiread_expect(4'h1, 8'h00);
// Motor channel 1
tach1 = 2'b01;
#2000
spiread_expect(4'h4,8'h01);
spiread_expect(4'h5, 8'h00);
tach1 = 2'b11;
#2000
spiread_expect(4'h4,8'h02);
spiread_expect(4'h5, 8'h00);
tach1 = 2'b01;
#2000
spiread_expect(4'h4,8'h01);
spiread_expect(4'h5, 8'h00);
tach1 = 2'b00;
#2000
spiread_expect(4'h4,8'h00);
spiread_expect(4'h5, 8'h00);
tach1 = 2'b10;
#2000
spiread_expect(4'h4,8'hff);
spiread_expect(4'h5, 8'hff);
tach1 = 2'b00;
#2000
spiread_expect(4'h4,8'h00);
spiread_expect(4'h5, 8'h00);
// Motor channel 2
tach2 = 2'b01;
#2000
spiread_expect(4'h8,8'h01);
spiread_expect(4'h9, 8'h00);
tach2 = 2'b11;
#2000
spiread_expect(4'h8,8'h02);
spiread_expect(4'h9, 8'h00);
tach2 = 2'b01;
#2000
spiread_expect(4'h8,8'h01);
spiread_expect(4'h9, 8'h00);
tach2 = 2'b00;
#2000
spiread_expect(4'h8,8'h00);
spiread_expect(4'h9, 8'h00);
tach2 = 2'b10;
#2000
spiread_expect(4'h8,8'hff);
spiread_expect(4'h9, 8'hff);
tach2 = 2'b00;
#2000
spiread_expect(4'h8,8'h00);
spiread_expect(4'h9, 8'h00);
// Set pwm to 25%
spiwrite(4'h0, 8'h40);
#100000
// Set the pwm to 75%
spiwrite(4'h0, 8'hC0);
#100000
// Set the pwm to 50%
spiwrite(4'h0, 8'h80);
#100000
// Set pwm to 25%
spiwrite(4'h4, 8'h40);
#100000
// Set the pwm to 75%
spiwrite(4'h4, 8'hC0);
#100000
// Set the pwm to 50%
spiwrite(4'h4, 8'h80);
#100000
// Set pwm to 25%
spiwrite(4'h8, 8'h40);
#100000
// Set the pwm to 75%
spiwrite(4'h8, 8'hC0);
#100000
// Set the pwm to 50%
spiwrite(4'h8, 8'h80);
#100000 $finish;
end
always #4 clk = ~clk;
endmodule |
module Testbench_Multiplier();
parameter PERIOD = 10;
parameter W = 24;
reg clk;
reg rst;
reg enable;
//Oper_Start_in signals
reg [W-1:0] in1;
reg [W-1:0] in2;
wire [2*W-1:0] res;
Simple_KOA_STAGE_1_approx #(
.SW(W)
) inst_Simple_KOA_STAGE_1 (
.clk (clk),
.rst (rst),
.load_b_i (enable),
.Data_A_i (in1),
.Data_B_i (in2),
.sgf_result_o (res)
);
`ifdef ACAIN8Q5
localparam STRINGHEX = "ResultadosACAIN8Q5HEX.txt";
localparam STRINGDEC = "ResultadosACAIN8Q5DEC.txt";
`endif
`ifdef ACAIIN8Q4
localparam STRINGHEX = "ResultadosACAIIN8Q4HEX.txt";
localparam STRINGDEC = "ResultadosACAIIN8Q4DEC.txt";
`endif
`ifdef GDAN8M8P1
localparam STRINGHEX = "ResultadosGDAN8M8P1HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P1DEC.txt";
`endif
`ifdef GDAN8M8P2
localparam STRINGHEX = "ResultadosGDAN8M8P2HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P2DEC.txt";
`endif
`ifdef GDAN8M8P3
localparam STRINGHEX = "ResultadosGDAN8M8P3HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P3DEC.txt";
`endif
`ifdef GDAN8M8P4
localparam STRINGHEX = "ResultadosGDAN8M8P4HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P4DEC.txt";
`endif
`ifdef GDAN8M8P5
localparam STRINGHEX = "ResultadosGDAN8M8P5HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P5DEC.txt";
`endif
`ifdef GDAN8M8P6
localparam STRINGHEX = "ResultadosGDAN8M8P6HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P6DEC.txt";
`endif
`ifdef GeArN8R1P1
localparam STRINGHEX = "ResultadosGeArN8R1P1HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P1DEC.txt";
`endif
`ifdef GeArN8R1P2
localparam STRINGHEX = "ResultadosGeArN8R1P2HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P2DEC.txt";
`endif
`ifdef GeArN8R1P3
localparam STRINGHEX = "ResultadosGeArN8R1P3HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P3DEC.txt";
`endif
`ifdef GeArN8R1P4
localparam STRINGHEX = "ResultadosGeArN8R1P4HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P4DEC.txt";
`endif
`ifdef GeArN8R1P5
localparam STRINGHEX = "ResultadosGeArN8R1P5HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P5DEC.txt";
`endif
`ifdef GeArN8R1P6
localparam STRINGHEX = "ResultadosGeArN8R1P6HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P6DEC.txt";
`endif
`ifdef GeArN8R2P2
localparam STRINGHEX = "ResultadosGeArN8R2P2HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R2P2DEC.txt";
`endif
`ifdef GeArN8R2P4
localparam STRINGHEX = "ResultadosGeArN8R2P4HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R2P4DEC.txt";
`endif
`ifdef GeArN8R4P1
localparam STRINGHEX = "ResultadosGeArN8R4P1HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R4P1DEC.txt";
`endif
`ifdef LOALPL4
localparam STRINGHEX = "ResultadosLOALPL4HEX.txt";
localparam STRINGDEC = "ResultadosLOALPL4DEC.txt";
`endif
`ifdef LOALPL5
localparam STRINGHEX = "ResultadosLOALPL5HEX.txt";
localparam STRINGDEC = "ResultadosLOALPL5DEC.txt";
`endif
`ifdef LOALPL6
localparam STRINGHEX = "ResultadosLOALPL6HEX.txt";
localparam STRINGDEC = "ResultadosLOALPL6DEC.txt";
`endif
`ifdef LOALPL7
localparam STRINGHEX = "ResultadosLOALPL7HEX.txt";
localparam STRINGDEC = "ResultadosLOALPL7DEC.txt";
`endif
`ifdef NADA
localparam STRINGHEX = "ResultadosNADAHEX.txt";
localparam STRINGDEC = "ResultadosNADADEC.txt";
`endif
integer FileResHex;
integer FileResDec;
reg [63:0] ValTeorico;
reg [63:0] Error = 0;
reg [63:0] RESULT;
real floatERROR = 0;
real sumErrors = 0;
initial begin
// Initialize Inputs
// $vcdpluson;
clk = 0;
in1 = 0;
in2 = 0;
rst = 1;
enable = 0;
#10;
rst = 0;
enable = 1;
#100;
FileResHex = $fopen(STRINGHEX,"w");
FileResDec = $fopen(STRINGDEC,"w");
runMultiplier(FileResHex,FileResDec,(200000));
$finish;
// $vcdplusclose;
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task runMultiplier;
input integer ResultsFileH;
input integer ResultsFileD;
input integer Vector_size;
begin
$fwrite(ResultsFileH, "Entrada 1, Entrada 2, Resultado, Teorico, Diff\n");
$fwrite(ResultsFileD, "Entrada 1, Entrada 2, Resultado, Teorico , Diff , Reltiv Error\n");
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
#4;
in1 = $random;
in2 = $random;
#2;
ValTeorico = in1 * in2;
RESULT = res;
if (RESULT > ValTeorico) begin
Error = (RESULT - ValTeorico);
end else begin
Error = (ValTeorico - RESULT);
end
floatERROR = ($bitstoreal(Error)*$itor(100))/$bitstoreal(ValTeorico);
sumErrors = sumErrors + floatERROR;
$fwrite(ResultsFileH, "%h, %h, %h, %h, %h\n", in1, in2, res, ValTeorico, Error);
$fwrite(ResultsFileD, "%d, %d, %d, %d, %d, %f\n", in1, in2, res, ValTeorico, Error, floatERROR);
end
$fwrite(ResultsFileD, "La suma de los errores es > %f\n", sumErrors);
$fwrite(ResultsFileD, "El numero de elementos es > %f\n", $itor(Vector_size));
$fwrite(ResultsFileD, "La media del error es> %f\n", sumErrors/$itor(Vector_size));
$fclose(ResultsFileH);
$fclose(ResultsFileD);
end
endtask
endmodule |
module pdp1_cpu(i_clk, i_rst,
mm_we, mm_adr, mm_unit, mm_din, mm_dout,
bs_stb, bs_adr, bs_wait, bs_din, bs_dout, bs_inh,
sw_sn, sw_tw,
cntrl_stop, cntrl_halt, cntrl_paused,
cntrl_resume, cntrl_reason,
sb_ireq, sb_disarm);
parameter pdp_model = "PDP-1"; // Or "PDP-1D"
parameter sbs_model = "SBS"; // Or "" or "SBS16"
parameter start_addr = 12'h000;
input i_clk;
input i_rst;
output reg mm_we;
output reg [0:11] mm_adr;
output reg [0:3] mm_unit;
input [0:17] mm_din;
output reg [0:17] mm_dout;
output reg bs_stb;
output [0:10] bs_adr;
output bs_wait;
output [0:17] bs_dout;
input [0:17] bs_din;
input bs_inh;
input [0:5] sw_sn;
input [0:17] sw_tw;
input cntrl_stop;
input cntrl_halt;
output cntrl_paused;
input cntrl_resume;
output reg [0:1] cntrl_reason;
input [0:3] sb_ireq;
output reg sb_disarm;
// Registers
reg [0:11] r_PC;
reg [0:3] r_PCU;
reg [0:17] r_AC;
reg [0:17] r_IO;
reg r_OV;
reg [0:5] r_PF;
reg r_EXTM;
reg r_IOP;
reg r_IOH;
// Instruction decoding
reg [0:17] r_inst;
wire [0:4] w_inst_op;
wire w_inst_i;
wire [0:11] w_inst_adr;
wire w_inst_w;
wire w_inst_p;
wire [0:4] w_inst_sop;
wire [0:5] w_inst_dev;
wire [0:8] w_inst_shftcnt;
wire [0:3] w_inst_shftop;
assign w_inst_op = r_inst[0:4];
assign w_inst_i = r_inst[5];
assign w_inst_adr = r_inst[6:17];
assign w_inst_w = r_inst[5];
assign w_inst_p = r_inst[6];
assign w_inst_sop = r_inst[7:11];
assign w_inst_dev = r_inst[12:17];
assign w_inst_shftcnt = r_inst[9:17];
assign w_inst_shftop = r_inst[5:8];
wire [0:5] w_din_op;
wire w_din_i;
wire [0:12] w_din_adr;
assign w_din_op = mm_din[0:4];
assign w_din_i = mm_din[5];
assign w_din_adr = mm_din[6:17];
// Sequence Break System
wire [0:11] sb_sav_pc;
wire [0:11] sb_sav_ac;
wire [0:11] sb_sav_io;
wire [0:11] sb_sav_jmp;
wire sb_intr;
wire [0:5] sb_sqb;
assign sb_intr = |sb_ireq;
generate
if(sbs_model == "") begin
assign sb_intr = 0;
end
else begin
assign sb_intr = |sb_ireq;
end
endgenerate
pdp1_sbs_decoder #(sbs_model) sbs_dec(.sb_ireq1(sb_ireq[0]),
.sb_ireq2(sb_ireq[1]),
.sb_ireq3(sb_ireq[2]),
.sb_ireq4(sb_ireq[3]),
.sav_ac(sb_sav_ac),
.sav_io(sb_sav_io),
.sav_pc(sb_sav_pc),
.sav_jmp(sb_sav_jmp));
wire [0:17] opr_ac;
wire [0:17] opr_io;
wire [0:5] opr_pf;
pdp1_opr_decoder #(pdp_model) odecode(.op_i(w_inst_i),
.op_mask(w_inst_adr),
.op_ac(r_AC),
.op_io(r_IO),
.op_pf(r_PF),
.op_tw(sw_tw),
.op_r_ac(opr_ac),
.op_r_io(opr_io),
.op_r_pf(opr_pf));
wire w_alu_op;
wire [0:17] w_alu_result;
wire w_alu_ovfl;
pdp1_alu alu(.al_op(w_inst_op),
.al_a(r_AC),
.al_b(mm_din),
.al_r(w_alu_result),
.al_ovfl(w_alu_ovfl),
.al_w(w_alu_op));
wire w_write_op;
wire [0:17] w_write_data;
pdp1_write_decoder ddecode(.ma_op(w_inst_op),
.ma_ac(r_AC),
.ma_io(r_IO),
.ma_cd(mm_din),
.ma_w(w_write_op),
.ma_r(w_write_data));
wire w_skip;
pdp1_skp_decoder #(pdp_model) sdecode(.sk_mask(w_inst_adr),
.sk_i(w_inst_i),
.sk_ac(r_AC),
.sk_io(r_IO),
.sk_ov(r_OV),
.sk_sw(sw_sn),
.sk_pf(r_PF),
.sk_skp(w_skip));
wire [0:17] w_shrot_io;
wire [0:17] w_shrot_ac;
wire w_shrot_dir = w_inst_shftop[0];
wire w_shrot_rot = ~w_inst_shftop[1];
pdp1_shrot ioshrot(.sh_cnt(w_inst_shftcnt),
.sh_dir(w_shrot_dir),
.sh_rot(w_shrot_rot),
.sh_d(r_IO),
.sh_q(w_shrot_io));
pdp1_shrot acshrot(.sh_cnt(w_inst_shftcnt),
.sh_dir(w_shrot_dir),
.sh_rot(w_shrot_rot),
.sh_d(r_AC),
.sh_q(w_shrot_ac));
wire w_intrisic_io;
assign bs_dout = r_IO;
assign bs_adr = {w_inst_dev|w_inst_sop};
assign bs_wait = w_inst_w|w_inst_p;
reg [0:2] r_state;
localparam SFETCH1 = 3'b000;
localparam SFETCH2 = 3'b001;
localparam SINDIR = 3'b010;
localparam SEXEC = 3'b011;
localparam SIEX1 = 3'b100; // (save IO) Interrupt exchange
localparam SIEX2 = 3'b101; // (save AC)
localparam SHALT = 3'b110;
reg r_cntrl_stop;
wire w_wrap_stop;
assign w_wrap_stop = cntrl_halt | cntrl_stop | r_cntrl_stop;
assign cntrl_paused = (r_state == SHALT);
always @(posedge i_clk) begin
if(i_rst) begin
r_PC <= start_addr;
r_PCU <= 0;
r_AC <= 0;
r_IO <= 0;
r_OV <= 0;
r_PF <= 0;
r_EXTM <= 0;
r_IOP <= 0;
r_IOH <= 0;
mm_dout <= 0;
mm_adr <= 0;
mm_unit <= 0;
mm_we <= 0;
sb_disarm <= 0;
cntrl_reason <= 0;
r_state <= SFETCH1;
r_cntrl_stop <= 0;
end
else begin
case(r_state)
SFETCH1:
begin
$display("%o %b %o %o %o %o",
r_PC-1, r_OV, r_AC, r_IO, r_PF, w_inst_op);
sb_disarm <= 1'b0;
if(w_wrap_stop) begin
mm_we <= 1'b0;
r_state <= SHALT;
end
else if(sb_intr) begin
mm_we <= 1'b1;
mm_adr <= sb_sav_pc;
mm_dout <= {r_OV, r_EXTM, r_PCU, r_PC};
r_state <= SIEX1;
r_EXTM <= 0;
mm_unit <= 0;
end
else begin
mm_we <= 1'b0;
mm_adr <= r_PC;
r_state <= SFETCH2;
end
end // case: SFETCH1
SFETCH2:
begin
r_inst <= mm_din;
mm_adr <= w_din_adr;
r_state <= (w_din_i & (w_din_op != `PDP1_OP_LAW &
w_din_op != `PDP1_OP_CAL &
w_din_op != `PDP1_OP_SFT &
w_din_op != `PDP1_OP_OPR &
w_din_op != `PDP1_OP_SKP &
w_din_op != `PDP1_OP_IOT)) ?
SINDIR : SEXEC;
r_PC = r_PC +1;
end
SINDIR:
begin
if(cntrl_halt) begin
r_PC = r_PC-1;
r_state <= SFETCH1;
end
if(r_EXTM) begin
{mm_unit, mm_adr} <= mm_din;
r_state <= SEXEC;
end
else begin
if(w_din_i)
mm_adr <= w_din_adr;
else
r_state <= SEXEC;
end
end
SIEX1:
begin
mm_adr <= sb_sav_io;
mm_dout <= r_IO;
r_state <= SIEX2;
end
SIEX2:
begin
mm_adr <= sb_sav_ac;
mm_dout <= r_AC;
r_PC <= sb_sav_jmp;
r_state <= SFETCH1;
sb_disarm <= 1'b1;
end
SEXEC:
begin
r_state = SFETCH1;
if(w_alu_op) begin
r_AC <= w_alu_result;
if(w_inst_op == `PDP1_OP_IDX |
w_inst_op == `PDP1_OP_ISP) begin
mm_we <= 1'b1;
mm_dout <= w_alu_result;
if(w_inst_op == `PDP1_OP_ISP & ~w_alu_result[0])
r_PC = r_PC + 1;
end
else
r_OV = (r_OV | w_alu_ovfl);
end // if (w_alu_op)
else if(w_write_op) begin
mm_dout <= w_write_data;
mm_we <= 1'b1;
if(w_inst_op == `PDP1_OP_CAL) begin
if(w_inst_i) begin
r_AC <= r_PC;
r_PC <= mm_adr+1;
end
else begin
mm_adr <= 12'o100;
r_AC <= r_PC;
r_PC <= 12'o101;
end
end
end // if (w_write_op)
else if(w_inst_op == `PDP1_OP_SKP) begin
if(w_skip)
r_PC = r_PC+1;
r_OV = w_inst_adr[2] ? 1'b0 : r_OV;
end
else if(w_inst_op == `PDP1_OP_IOT) begin
$display("IOT %o (%o) P=%b W=%b", w_inst_dev, w_inst_sop,
w_inst_p, w_inst_w);
if(~(|{w_inst_sop, w_inst_dev}) | r_IOH) begin // IOT 0000
if(r_IOP | ~bs_inh) begin
r_IOH <= 1'b0;
r_IOP <= 1'b0;
r_state = SFETCH1;
bs_stb <= 1'b0;
end
else
r_state = SEXEC;
end
else if(w_inst_w & ~r_IOH) begin
r_IOP <= 1'b0;
r_IOH <= 1'b1;
r_state = SEXEC;
bs_stb <= 1'b1;
end
end // if (w_inst_op == `PDP1_OP_IOT)
else if(w_inst_op == `PDP1_OP_SFT) begin
if(w_inst_shftop[3]) // 1&3
r_AC <= w_shrot_ac;
if(w_inst_shftop[2]) // 2&3
r_IO <= w_shrot_io;
// $display("SFT %b %o %o",
// w_inst_shftop[2:3], w_shrot_ac, w_shrot_io);
end
else begin
case(w_inst_op)
`PDP1_OP_XCT:
begin
r_inst <= mm_din;
r_state = SEXEC;
end
`PDP1_OP_LAC:
r_AC <= mm_din;
`PDP1_OP_LIO:
r_IO <= mm_din;
//TAD
`PDP1_OP_SAD:
begin
if(r_AC != mm_din)
r_PC = r_PC + 1;
end
`PDP1_OP_SAS:
begin
if(r_AC == mm_din)
r_PC = r_PC + 1;
end
// MUL, DIV
`PDP1_OP_JMP:
r_PC = w_inst_adr;
`PDP1_OP_JSP:
begin
r_PC <= w_inst_adr;
r_AC <= r_PC;
end
`PDP1_OP_OPR:
begin
if(w_inst_adr[3]) begin
r_cntrl_stop <= 1'b1;
cntrl_reason <= 2'b01;
end
r_AC <= opr_ac;
r_IO <= opr_io;
r_PF <= opr_pf;
end
`PDP1_OP_LAW:
r_AC <= (w_inst_i) ? ~w_inst_adr : w_inst_adr;
`PDP1_OP_CAL:
begin
if(w_inst_i) begin //JDA
mm_we <= 1'b1;
mm_dout <= r_AC;
r_AC <= r_PC;
r_PC <= w_inst_adr+1;
end
else begin //CAL
mm_adr <= 12'o100;
mm_we <= 1'b1;
mm_dout <= r_AC;
r_AC <= r_PC;
r_PC <= 12'o101;
end
end // case: `PDP1_OP_CAL
default:
begin
$display("Unknown OP=(%o %b %o) PC=%o",
w_inst_op, w_inst_i, w_inst_adr, mm_adr, r_PC-1);
r_cntrl_stop <= 1;
cntrl_reason <= 2'b10;
$finish();
end
endcase // case (w_inst_op)
end // else: !if(w_alu_op)
end
SHALT:
begin
$display("%m Stopped! PC=%o %b", r_PC, cntrl_reason);
end
endcase // case (r_state)
end
end // always @ (posedge i_clk)
endmodule |
module program_counter2a (next_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] next_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst)
begin
// Set its value to ZERO
next_pc<=32'd0;
end
else
begin
next_pc<=next_pc+32'd4;
end
end
endmodule |
module sky130_fd_sc_hdll__einvn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module DE1_TOP
(
//////////////////// Clock Input ////////////////////
CLOCK_24, // 24 MHz
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz
EXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
KEY, // Pushbutton[3:0]
//////////////////// DPDT Switch ////////////////////
SW, // Toggle Switch[9:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digit 0
HEX1, // Seven Segment Digit 1
HEX2, // Seven Segment Digit 2
HEX3, // Seven Segment Digit 3
//////////////////////// LED ////////////////////////
LEDG, // LED Green[7:0]
LEDR, // LED Red[9:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 0
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
//////////////////// USB JTAG link ////////////////////
TDI, // CPLD -> FPGA (data in)
TCK, // CPLD -> FPGA (clk)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (data out)
//////////////////// VGA ////////////////////////////
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_R, // VGA Red[3:0]
VGA_G, // VGA Green[3:0]
VGA_B, // VGA Blue[3:0]
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
//////////////////////// Clock Input ////////////////////////
input [1:0] CLOCK_24; // 24 MHz
input [1:0] CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [9:0] SW; // Toggle Switch[9:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
output [6:0] HEX0; // Seven Segment Digit 0
output [6:0] HEX1; // Seven Segment Digit 1
output [6:0] HEX2; // Seven Segment Digit 2
output [6:0] HEX3; // Seven Segment Digit 3
//////////////////////////// LED ////////////////////////////
output [7:0] LEDG; // LED Green[7:0]
output [9:0] LEDR; // LED Red[9:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output [3:0] VGA_R; // VGA Red[3:0]
output [3:0] VGA_G; // VGA Green[3:0]
output [3:0] VGA_B; // VGA Blue[3:0]
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
assign HEX0 = 7'h01;
assign HEX1 = 7'h01;
assign HEX2 = 7'h03;
assign HEX3 = 7'h00;
wire SIO_C1;
wire SIO_D1;
wire SYNC1;
wire HREF1;
wire PCLK1;
wire XCLK1;
wire [7:0] CCD_DATA1;
// WIRE
assign SIO_C1 = GPIO_1[1];
assign SYNC1 = GPIO_1[3];
assign PCLK1 = GPIO_1[5];
assign SIO_D1 = GPIO_1[0];
assign HREF1 = GPIO_1[2];
assign XCLK1 = CLOCK_24;
assign GPIO_1[4] = XCLK1;
assign CCD_DATA1[6] = GPIO_1[6];
assign CCD_DATA1[7] = GPIO_1[7];
assign CCD_DATA1[4] = GPIO_1[8];
assign CCD_DATA1[5] = GPIO_1[9];
assign CCD_DATA1[2] = GPIO_1[10];
assign CCD_DATA1[3] = GPIO_1[11];
assign CCD_DATA1[0] = GPIO_1[12];
assign CCD_DATA1[1] = GPIO_1[13];
//---------------------------------------------
// RESET DELAY
//---------------------------------------------
wire DLY_RST_0;
wire DLY_RST_1;
wire DLY_RST_2;
Reset_Delay u2
(
.iCLK (CLOCK_50),
.iRST (KEY[0]),
.oRST_0(DLY_RST_0),
.oRST_1(DLY_RST_1),
.oRST_2(DLY_RST_2)
);
//--------------------------------
// CONFIG I2C
//--------------------------------
always@(posedge OSC_50) clk_25 <= ~clk_25;
reg clk_25;
assign CLK_25 = clk_25;
I2C_AV_Config CCD_CF
(
//Global clock
.iCLK(CLK_25), //25MHz
.iRST_N(DLY_RST_2), //Global Reset
//I2C Side
.I2C_SCLK(SIO_C1),
.I2C_SDAT(SIO_D1),
.Config_Done(config_done2),//Config Done
.I2C_RDATA(I2C_RDATA2) //I2C Read Data
);
//------------------------------------
// DATA ACQUISITION
//------------------------------------
reg [7:0] rCCD_DATA1;// DICH DATA VAO BO DEM
reg rCCD_LVAL1;// OUTPUT LINE VALID
reg rCCD_FVAL1;// OUTPUT FRAME VALID
always@(posedge PCLK1)
begin
rCCD_DATA1 <= CCD_DATA1;
rCCD_FVAL1 <= SYNC1;
rCCD_LVAL1 <= HREF1;
end
// CAPTURE
wire [15:0] YCbCr1; // Camera Left YUV 4:2:2
wire [15:0] YCbCr2; // Camera Right YUV 4:2:2
wire oDVAL1;// OUPUT DATA VALID
wire oDVAL2;// OUPUT DATA VALID
wire [7:0] mCCD_DATA11;
wire [7:0] mCCD_DATA12;
wire [10:0] X_Cont1;
wire [9:0] Y_Cont1;
wire [31:0] Frame_Cont1;
CCD_Capture CAMERA_DECODER
(
.oYCbCr(YCbCr1),
.oDVAL(oDVAL1),
.oX_Cont(X_Cont1),
.oY_Cont(Y_Cont1),
.oFrame_Cont(Frame_Cont1),
// oPIXCLK,
.iDATA(rCCD_DATA1),
.iFVAL(rCCD_FVAL1),
.iLVAL(rCCD_LVAL1),
.iSTART(!KEY[1]),
.iEND(!KEY[2]),
.iCLK(PCLK1),
.iRST(DLY_RST_1)
);
// SDRAM PLL
wire sdram_ctrl_clk;
sdram_pll SDRAM_PLL
(
.inclk0(CLOCK_24),
.c0 (sdram_ctrl_clk),
.c1 (DRAM_CLK)
);
// DRAM CONTROL
Sdram_Control_4Port SDRAM_FRAME_BUFFER
(
// HOST Side
.REF_CLK (CLOCK_50),
.RESET_N ( 1'b1),
.CLK (sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA (YCbCr1),
.WR1 (oDVAL1),
.WR1_ADDR (0),
.WR1_MAX_ADDR (640*480),
.WR1_LENGTH (9'h100),
.WR1_LOAD (!DLY_RST_0),
.WR1_CLK (PCLK1),
// FIFO Write Side 2
.WR2_DATA (YCbCr2), // for dual camera
.WR2 (oDVAL2),
.WR2_ADDR (22'h100000),
.WR2_MAX_ADDR (22'h100000+640*480),
.WR2_LENGTH (9'h100),
.WR2_LOAD (!DLY_RST_0),
.WR2_CLK (PCLK2),
// FIFO Read Side 1
.RD1_DATA (READ_DATA1),
.RD1 (VGA_Read),
.RD1_ADDR (0),
.RD1_MAX_ADDR (640*480),
.RD1_LENGTH (9'h100),
.RD1_LOAD (!DLY_RST_0),
.RD1_CLK (CLOCK_24), //
// FIFO Read Side 1
.RD2_DATA (READ_DATA2),
.RD2 (VGA_Read),
.RD2_ADDR (22'h100000),
.RD2_MAX_ADDR (22'h100000+640*480),
.RD2_LENGTH (9'h100),
.RD2_LOAD (!DLY_RST_0),
.RD2_CLK (CLOCK_24), //
// SDRAM Side
.SA (DRAM_ADDR),
.BA ({DRAM_BA_1,DRAM_BA_0}),
.CS_N (DRAM_CS_N),
.CKE (DRAM_CKE),
.RAS_N (DRAM_RAS_N),
.CAS_N (DRAM_CAS_N),
.WE_N (DRAM_WE_N),
.DQ (DRAM_DQ),
.DQM ({DRAM_UDQM,DRAM_LDQM})
);
//-------------------------------------------------
// YUV 4:2:2 TO YUV 4:4:4
//-------------------------------------------------
wire [7:0] mY1;
wire [7:0] mCb1;
wire [7:0] mCr1;
wire [7:0] mY2;
wire [7:0] mCb2;
wire [7:0] mCr2;
YUV422_to_444 YUV422to444
(
// YUV 4:2:2 Input
.iYCbCr(READ_DATA1),
// YUV 4:4:4 Output
.oY (mY1),
.oCb(mCb1),
.oCr(mCr1),
// Control Signals
.iX(VGA_X),
.iCLK(CLOCK_24),
.iRST_N(DLY_RST_0)
);
wire mDVAL1,mDVAL2;
wire [9:0] mR1;
wire [9:0] mG1;
wire [9:0] mB1;
YCbCr2RGB YUV2RGB
(
// input data
.iY(mY1),
.iCb(mCb1),
.iCr(mCr1),
// output data
.Red(mR1),
.Green(mG1),
.Blue(mB1),
// controller
.oDVAL(mDVAL),
.iDVAL(VGA_Read),
.iRESET(!DLY_RST_2),
.iCLK(CLOCK_24)
);
VGA_Controller VGA_DISPLAY
(
// Host Side
.iRed(mR1),
.iGreen(mG1),
.iBlue(mB1),
//.oCurrent_X(VGA_X),
//.oCurrent_Y(VGA_Y),
.oRequest(VGA_Read),
// VGA Side
.oVGA_R(oVGA_R),
.oVGA_G(oVGA_G),
.oVGA_B(oVGA_B),
.oVGA_HS(VGA_HS),
.oVGA_VS(VGA_VS),
// Control Signal
.iCLK(CLOCK_24),
.iRST_N(DLY_RST_2)
);
endmodule |
module DriveTFT18(
input wire clk,
input wire rsth,
output wire SCL,
output wire WRX,
output wire RESX,
output wire CSX,
inout wire SDA,
output wire UART_TX,
output wire [6:0] LED
);
wire [24:0] w_mcs_gpo;
wire [31:0] w_rdata;
wire w_req = w_mcs_gpo[24];
wire [1:0] w_mod_sel = w_mcs_gpo[23:22];
wire [3:0] w_spi_command = w_mcs_gpo[21:18];
wire [17:0] w_wdata = w_mcs_gpo[17:0];
// W
[ZNgfR[h
// SPI select
wire w_sel_spi = (w_mod_sel == 2'b00);
wire w_sel_tft_rst = (w_mod_sel == 2'b11);
wire w_sel_timer = (w_mod_sel == 2'b01);
// ACK
wire w_ack_spi, w_ack_wait;
wire w_ack_all = w_ack_spi & w_ack_wait;
mcs mcs_0 (
.Clk(clk), // input Clk
.Reset(rsth), // input Reset
.UART_Tx(UART_TX), // output UART_Tx
.GPO1(w_mcs_gpo), // output [26 : 0] GPO1
.GPI1(w_ack_all), // input [0 : 0] GPI1
.GPI1_Interrupt(), // output GPI1_Interrupt
.GPI2(w_rdata), // input [31 : 0] GPI2
.GPI2_Interrupt() // output GPI2_Interrupt
);
// SPI
spi spi (
.clk(clk),
.rsth(rsth),
.mod_sel(w_sel_spi),
.req(w_req),
.command(w_spi_command),
.wdata(w_wdata),
.rdata(w_rdata),
.ack(w_ack_spi),
.oSCL(SCL),
.oDCX(WRX),
.oCSX(CSX),
.oSDA(SDA)
);
// TFT Zbg
reg r_rstn;
always @(posedge clk) begin
if(rsth) r_rstn <= 1'b0;
if(w_sel_tft_rst) r_rstn <= w_wdata[0];
end
// wait
timer_wait timer_wait (
.clk(clk),
.rsth(rsth),
.mod_sel(w_sel_timer),
.req(w_req),
.w_wdata(w_wdata),
.ack(w_ack_wait)
);
assign RESX = r_rstn;
assign LED[6] = SCL;
assign LED[5] = WRX;
assign LED[4] = CSX;
assign LED[3] = SDA;
assign LED[2] = w_req;
assign LED[1] = w_ack_spi;
assign LED[0] = w_ack_wait;
//assign LED[6:1] = {w_mod_sel[1:0], w_req, w_sel_spi, w_sel_tft_rst, w_sel_timer};
//assign LED[0] = RESX;
endmodule |
module sky130_fd_sc_hs__tap (
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module tlu_controller_fsm
#(
parameter DIVISOR = 8,
parameter TLU_TRIGGER_MAX_CLOCK_CYCLES = 17,
parameter TIMESTAMP_N_OF_BIT = 32
) (
input wire RESET,
input wire TRIGGER_CLK,
output reg TRIGGER_DATA_WRITE,
output reg [31:0] TRIGGER_DATA,
output reg FIFO_PREEMPT_REQ,
input wire FIFO_ACKNOWLEDGE,
output reg [TIMESTAMP_N_OF_BIT-1:0] TIMESTAMP,
output reg [31:0] TIMESTAMP_DATA,
output reg [31:0] TLU_TRIGGER_NUMBER_DATA,
output reg [31:0] TRIGGER_COUNTER_DATA,
input wire TRIGGER_COUNTER_SET,
input wire [31:0] TRIGGER_COUNTER_SET_VALUE,
input wire [1:0] TRIGGER_MODE,
input wire [7:0] TRIGGER_THRESHOLD,
input wire TRIGGER,
input wire TRIGGER_VETO,
input wire TRIGGER_ENABLE,
input wire TRIGGER_ACKNOWLEDGE,
output reg TRIGGER_ACCEPTED_FLAG,
input wire [7:0] TLU_TRIGGER_LOW_TIME_OUT,
// input wire [4:0] TLU_TRIGGER_CLOCK_CYCLES,
input wire [3:0] TLU_TRIGGER_DATA_DELAY,
input wire TLU_TRIGGER_DATA_MSB_FIRST,
input wire TLU_ENABLE_VETO,
input wire TLU_RESET_FLAG,
input wire [1:0] CONF_DATA_FORMAT,
output reg TLU_BUSY,
output reg TLU_CLOCK_ENABLE,
output reg TLU_ASSERT_VETO,
input wire [7:0] TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES,
input wire [7:0] TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES,
output wire TLU_TRIGGER_LOW_TIMEOUT_ERROR_FLAG, // error flag
output wire TLU_TRIGGER_ACCEPT_ERROR_FLAG // error flag
);
//assign TRIGGER_DATA[31:0] = (WRITE_TIMESTAMP==1'b1) ? {1'b1, TIMESTAMP_DATA[30:0]} : ((TRIGGER_MODE==2'b11) ? {1'b1, TLU_TRIGGER_NUMBER_DATA[30:0]} : ({1'b1, TRIGGER_COUNTER_DATA[30:0]}));
always@(*)
begin
if(TRIGGER_MODE == 2'b11) // TLU trigger number
TRIGGER_DATA[31:0] = {1'b1, TLU_TRIGGER_NUMBER_DATA[30:0]};
else // internally generated trigger number
TRIGGER_DATA[31:0] = {1'b1, TRIGGER_COUNTER_DATA[30:0]};
if(CONF_DATA_FORMAT == 2'b01) // time stamp only
TRIGGER_DATA[31:0] = {1'b1, TIMESTAMP_DATA[30:0]};
else if(CONF_DATA_FORMAT == 2'b10) // combined
TRIGGER_DATA[31:16] = {1'b1, TIMESTAMP_DATA[14:0]};
end
// shift register, serial to parallel, length of TLU_TRIGGER_MAX_CLOCK_CYCLES
reg [((TLU_TRIGGER_MAX_CLOCK_CYCLES+1)*DIVISOR)-1:0] tlu_data_sr;
always @ (posedge TRIGGER_CLK)
begin
if (RESET | TRIGGER_ACCEPTED_FLAG)
tlu_data_sr <= 0;
else
tlu_data_sr[((TLU_TRIGGER_MAX_CLOCK_CYCLES)*DIVISOR)-1:0] <= {tlu_data_sr[((TLU_TRIGGER_MAX_CLOCK_CYCLES)*DIVISOR)-2:0], TRIGGER};
end
// Trigger flag
reg TRIGGER_FF;
always @ (posedge TRIGGER_CLK)
TRIGGER_FF <= TRIGGER;
wire TRIGGER_FLAG;
assign TRIGGER_FLAG = ~TRIGGER_FF & TRIGGER;
// Trigger enable flag
reg TRIGGER_ENABLE_FF;
always @ (posedge TRIGGER_CLK)
TRIGGER_ENABLE_FF <= TRIGGER_ENABLE;
wire TRIGGER_ENABLE_FLAG;
assign TRIGGER_ENABLE_FLAG = ~TRIGGER_ENABLE_FF & TRIGGER_ENABLE;
// FSM
// workaround for TLU bug where short szintillator pulses lead to glitches on TLU trigger
reg TRIGGER_ACCEPT;
reg TLU_TRIGGER_HANDSHAKE_ACCEPT;
reg [7:0] counter_trigger_high;
// additional wait cycles for TLU veto after TLU handshake
reg [7:0] counter_tlu_handshake_veto;
// other
reg [7:0] counter_trigger_low_time_out;
integer counter_tlu_clock;
integer counter_sr_wait_cycles;
integer n; // for for-loop
reg TRIGGER_ACKNOWLEDGED, FIFO_ACKNOWLEDGED;
reg [31:0] TRIGGER_COUNTER;
reg TLU_TRIGGER_LOW_TIMEOUT_ERROR;
reg TLU_TRIGGER_ACCEPT_ERROR;
reg TLU_TRIGGER_LOW_TIMEOUT_ERROR_FF;
always @ (posedge TRIGGER_CLK)
TLU_TRIGGER_LOW_TIMEOUT_ERROR_FF <= TLU_TRIGGER_LOW_TIMEOUT_ERROR;
assign TLU_TRIGGER_LOW_TIMEOUT_ERROR_FLAG = ~TLU_TRIGGER_LOW_TIMEOUT_ERROR_FF & TLU_TRIGGER_LOW_TIMEOUT_ERROR;
reg TLU_TRIGGER_ACCEPT_ERROR_FF;
always @ (posedge TRIGGER_CLK)
TLU_TRIGGER_ACCEPT_ERROR_FF <= TLU_TRIGGER_ACCEPT_ERROR;
assign TLU_TRIGGER_ACCEPT_ERROR_FLAG = ~TLU_TRIGGER_ACCEPT_ERROR_FF & TLU_TRIGGER_ACCEPT_ERROR;
// standard state encoding
reg [2:0] state;
reg [2:0] next;
parameter [2:0]
IDLE = 3'b000,
SEND_COMMAND = 3'b001,
SEND_COMMAND_WAIT_FOR_TRIGGER_LOW = 3'b010,
SEND_TLU_CLOCK = 3'b011,
WAIT_BEFORE_LATCH = 3'b100,
LATCH_DATA = 3'b101,
WAIT_FOR_TLU_DATA_SAVED_CMD_READY = 3'b110;
// sequential always block, non-blocking assignments
always @ (posedge TRIGGER_CLK)
begin
if (RESET) state <= IDLE; // get D-FF for state
else state <= next;
end
// combinational always block, blocking assignments
always @ (state or TRIGGER_ACKNOWLEDGE or TRIGGER_ACKNOWLEDGED or FIFO_ACKNOWLEDGE or FIFO_ACKNOWLEDGED or TRIGGER_ENABLE or TRIGGER_ENABLE_FLAG or TRIGGER_FLAG or TRIGGER or TRIGGER_MODE or TLU_TRIGGER_LOW_TIMEOUT_ERROR or counter_tlu_clock /*or TLU_TRIGGER_CLOCK_CYCLES*/ or counter_sr_wait_cycles or TLU_TRIGGER_DATA_DELAY or TRIGGER_VETO or TRIGGER_ACCEPT or TLU_TRIGGER_HANDSHAKE_ACCEPT or TRIGGER_THRESHOLD or TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES or TLU_TRIGGER_MAX_CLOCK_CYCLES or DIVISOR)
begin
case (state)
IDLE:
begin
if ((TRIGGER_MODE == 2'b00 || TRIGGER_MODE == 2'b01)
&& (TRIGGER_ACKNOWLEDGE == 1'b0)
&& (FIFO_ACKNOWLEDGE == 1'b0)
&& (TRIGGER_ENABLE == 1'b1)
&& (TRIGGER_VETO == 1'b0)
&& ((TRIGGER_FLAG == 1'b1 && TRIGGER_THRESHOLD == 0) // trigger threshold disabled
|| (TRIGGER_ACCEPT == 1'b1 && TRIGGER_THRESHOLD != 0) // trigger threshold enabled
)
)
next = SEND_COMMAND;
else if ((TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11)
&& (TRIGGER_ACKNOWLEDGE == 1'b0)
&& (FIFO_ACKNOWLEDGE == 1'b0)
&& (TRIGGER_ENABLE == 1'b1)
&& ((TRIGGER == 1'b1 && TRIGGER_ENABLE_FLAG == 1'b1) // workaround TLU trigger high when FSM enabled
|| (TRIGGER_FLAG == 1'b1 && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES == 0) // trigger accept counter disabled
|| (TLU_TRIGGER_HANDSHAKE_ACCEPT == 1'b1 && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES != 0) // trigger accept counter enabled
)
)
next = SEND_COMMAND_WAIT_FOR_TRIGGER_LOW;
else
next = IDLE;
end
SEND_COMMAND:
begin
next = LATCH_DATA; // do not wait for trigger becoming low
end
SEND_COMMAND_WAIT_FOR_TRIGGER_LOW:
begin
if (TRIGGER_MODE == 2'b10 && (TRIGGER == 1'b0 || TLU_TRIGGER_LOW_TIMEOUT_ERROR == 1'b1))
next = LATCH_DATA; // wait for trigger low
else if (TRIGGER_MODE == 2'b11 && (TRIGGER == 1'b0 || TLU_TRIGGER_LOW_TIMEOUT_ERROR == 1'b1))
next = SEND_TLU_CLOCK; // wait for trigger low
else
next = SEND_COMMAND_WAIT_FOR_TRIGGER_LOW;
end
SEND_TLU_CLOCK:
begin
//if (TLU_TRIGGER_CLOCK_CYCLES == 5'b0) // send 32 clock cycles
if (counter_tlu_clock >= TLU_TRIGGER_MAX_CLOCK_CYCLES * DIVISOR)
next = WAIT_BEFORE_LATCH;
else
next = SEND_TLU_CLOCK;
/*
else
if (counter_tlu_clock == TLU_TRIGGER_CLOCK_CYCLES * DIVISOR)
next = WAIT_BEFORE_LATCH;
else
next = SEND_TLU_CLOCK;
*/
end
WAIT_BEFORE_LATCH:
begin
if (counter_sr_wait_cycles == TLU_TRIGGER_DATA_DELAY + 5) // wait at least 3 (2 + next state) clock cycles for sync of the signal
next = LATCH_DATA;
else
next = WAIT_BEFORE_LATCH;
end
LATCH_DATA:
begin
next = WAIT_FOR_TLU_DATA_SAVED_CMD_READY;
end
WAIT_FOR_TLU_DATA_SAVED_CMD_READY:
begin
if (TRIGGER_ACKNOWLEDGED == 1'b1 && FIFO_ACKNOWLEDGED == 1'b1)
next = IDLE;
else
next = WAIT_FOR_TLU_DATA_SAVED_CMD_READY;
end
// inferring FF
default:
begin
next = IDLE;
end
endcase
end
// sequential always block, non-blocking assignments, registered outputs
always @ (posedge TRIGGER_CLK)
begin
if (RESET) // get D-FF
begin
FIFO_PREEMPT_REQ <= 1'b0;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_TRIGGER_NUMBER_DATA <= 32'b0;
TIMESTAMP_DATA <= 32'b0;
TRIGGER_COUNTER_DATA <= 32'b0;
TLU_ASSERT_VETO <= 1'b0;
TLU_BUSY <= 1'b0;
TLU_CLOCK_ENABLE <= 1'b0;
counter_trigger_high <= 8'b0;
counter_tlu_handshake_veto <= TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES;
TRIGGER_ACCEPT <= 1'b0;
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b0;
counter_trigger_low_time_out <= 8'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b0;
TLU_TRIGGER_ACCEPT_ERROR <= 1'b0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
TRIGGER_ACKNOWLEDGED <= 1'b0;
FIFO_ACKNOWLEDGED <= 1'b0;
end
else
begin
FIFO_PREEMPT_REQ <= 1'b0;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_TRIGGER_NUMBER_DATA <= TLU_TRIGGER_NUMBER_DATA;
TIMESTAMP_DATA <= TIMESTAMP_DATA;
TRIGGER_COUNTER_DATA <= TRIGGER_COUNTER_DATA;
TLU_ASSERT_VETO <= 1'b0;
TLU_BUSY <= 1'b0;
TLU_CLOCK_ENABLE <= 1'b0;
counter_trigger_high <= 8'b0;
counter_tlu_handshake_veto <= TLU_HANDSHAKE_BUSY_VETO_WAIT_CYCLES;
TRIGGER_ACCEPT <= 1'b0;
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b0;
counter_trigger_low_time_out <= 8'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b0;
TLU_TRIGGER_ACCEPT_ERROR <= 1'b0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
TRIGGER_ACKNOWLEDGED <= TRIGGER_ACKNOWLEDGED;
FIFO_ACKNOWLEDGED <= FIFO_ACKNOWLEDGED;
case (next)
IDLE:
begin
if (TRIGGER_FLAG)
TIMESTAMP_DATA <= TIMESTAMP[31:0];
if (TRIGGER_ENABLE == 1'b1
&& TRIGGER == 1'b1
&& (((TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11) && (counter_trigger_high != 0 && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES != 0))
|| ((TRIGGER_MODE == 2'b00 || TRIGGER_MODE == 2'b01) && (counter_trigger_high != 0 && TRIGGER_THRESHOLD != 0))
)
)
FIFO_PREEMPT_REQ <= 1'b1;
else
FIFO_PREEMPT_REQ <= 1'b0;
TRIGGER_DATA_WRITE <= 1'b0;
if ((TRIGGER_ENABLE == 1'b0 || (TRIGGER_ENABLE == 1'b1 && TRIGGER_VETO == 1'b1 && counter_tlu_handshake_veto == 0)) && TLU_ENABLE_VETO == 1'b1 && (TRIGGER_MODE == 2'b10 || TRIGGER_MODE == 2'b11))
TLU_ASSERT_VETO <= 1'b1; // assert only outside Trigger/Busy handshake
else
TLU_ASSERT_VETO <= 1'b0;
// if (TRIGGER_ENABLE == 1'b0)
// TLU_BUSY <= 1'b1; // FIXME: temporary fix for accepting first TLU trigger
// else
// TLU_BUSY <= 1'b0;
TLU_BUSY <= 1'b0;
TLU_CLOCK_ENABLE <= 1'b0;
if (TRIGGER_ENABLE == 1'b1 && counter_trigger_high != 8'b1111_1111 && ((counter_trigger_high > 0 && TRIGGER == 1'b1) || (counter_trigger_high == 0 && TRIGGER_FLAG == 1'b1)))
counter_trigger_high <= counter_trigger_high + 1;
else if (TRIGGER_ENABLE == 1'b1 && counter_trigger_high == 8'b1111_1111 && TRIGGER == 1'b1)
counter_trigger_high <= counter_trigger_high;
else
counter_trigger_high <= 8'b0;
if (TRIGGER_ENABLE == 1'b0)
counter_tlu_handshake_veto <= 8'b0;
else if (counter_tlu_handshake_veto == 8'b0)
counter_tlu_handshake_veto <= counter_tlu_handshake_veto;
else
counter_tlu_handshake_veto <= counter_tlu_handshake_veto - 1;
if (counter_trigger_high >= TRIGGER_THRESHOLD && TRIGGER_THRESHOLD != 0)
TRIGGER_ACCEPT <= 1'b1;
else
TRIGGER_ACCEPT <= 1'b0;
if (counter_trigger_high >= TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES && TLU_TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES != 0)
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b1;
else
TLU_TRIGGER_HANDSHAKE_ACCEPT <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
TRIGGER_ACKNOWLEDGED <= 1'b0;
FIFO_ACKNOWLEDGED <= 1'b0;
end
SEND_COMMAND:
begin
// send flag at beginning of state
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
// get timestamp closest to the trigger
if (state != next) begin
// TIMESTAMP_DATA <= TIMESTAMP;
TRIGGER_COUNTER_DATA <= TRIGGER_COUNTER;
end
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
// send flag at beginning of state
if (state != next)
TRIGGER_ACCEPTED_FLAG <= 1'b1;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
SEND_COMMAND_WAIT_FOR_TRIGGER_LOW:
begin
// send flag at beginning of state
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
// get timestamp closest to the trigger
if (state != next) begin
// TIMESTAMP_DATA <= TIMESTAMP;
TRIGGER_COUNTER_DATA <= TRIGGER_COUNTER;
end
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_trigger_low_time_out <= counter_trigger_low_time_out + 1;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
if ((counter_trigger_low_time_out >= TLU_TRIGGER_LOW_TIME_OUT) && (TLU_TRIGGER_LOW_TIME_OUT != 8'b0))
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b1;
else
TLU_TRIGGER_LOW_TIMEOUT_ERROR <= 1'b0;
if (state != next)
TRIGGER_ACCEPTED_FLAG <= 1'b1;
else
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
SEND_TLU_CLOCK:
begin
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b1;
counter_tlu_clock <= counter_tlu_clock + 1;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
if (state != next && TRIGGER == 1'b0 && counter_trigger_low_time_out < 4) // 4 clocks cycles = 1 for output + 3 for sync
TLU_TRIGGER_ACCEPT_ERROR <= 1'b1;
end
WAIT_BEFORE_LATCH:
begin
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= counter_sr_wait_cycles + 1;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
LATCH_DATA:
begin
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b1;
if (TLU_TRIGGER_DATA_MSB_FIRST == 1'b0) begin // reverse bit order
for ( n=0 ; n < TLU_TRIGGER_MAX_CLOCK_CYCLES ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((TLU_TRIGGER_MAX_CLOCK_CYCLES-n)*DIVISOR)-1];
end
end
else begin // do not reverse
for ( n=0 ; n < TLU_TRIGGER_MAX_CLOCK_CYCLES ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((n+2)*DIVISOR)-1];
end
end
/*
if (TLU_TRIGGER_CLOCK_CYCLES == 5'b0_0000) begin // 0 results in 32 clock cycles -> 31bit trigger number
if (TLU_TRIGGER_DATA_MSB_FIRST == 1'b0) begin // reverse bit order
for ( n=0 ; n < 32 ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((32-n)*DIVISOR)-1];
end
end
else begin // do not reverse
for ( n=0 ; n < 32 ; n = n+1 ) begin
if (n > 31-1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((n+2)*DIVISOR)-1];
end
end
end
else begin // specific number of clock cycles
if (TLU_TRIGGER_DATA_MSB_FIRST == 1'b0) begin // reverse bit order
for ( n=31 ; n >= 0 ; n = n-1 ) begin
if (n + 1 > TLU_TRIGGER_CLOCK_CYCLES - 1)
TLU_TRIGGER_NUMBER_DATA[n] = 1'b0;
else if (n + 1 == TLU_TRIGGER_CLOCK_CYCLES - 1) begin
for ( i=0 ; i < 32 ; i = i+1 ) begin
if (i < TLU_TRIGGER_CLOCK_CYCLES-1)
TLU_TRIGGER_NUMBER_DATA[n-i] = tlu_data_sr[((i+2)*DIVISOR)-1];
end
end
end
end
else begin // do not reverse
for ( n=0 ; n < 32 ; n = n+1 ) begin
if (n + 1 > TLU_TRIGGER_CLOCK_CYCLES - 1)
TLU_TRIGGER_NUMBER_DATA[n] <= 1'b0;
else
TLU_TRIGGER_NUMBER_DATA[n] <= tlu_data_sr[((n+2)*DIVISOR)-1];
end
end
end
*/
TLU_BUSY <= 1'b1;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
if (state != next && TRIGGER == 1'b0 && counter_trigger_low_time_out < 4 && TRIGGER_MODE == 2'b10) // 4 clocks cycles = 1 for output + 3 for sync
TLU_TRIGGER_ACCEPT_ERROR <= 1'b1;
end
WAIT_FOR_TLU_DATA_SAVED_CMD_READY:
begin
//if ()
// FIFO_PREEMPT_REQ <= 1'b0;
//else
// FIFO_PREEMPT_REQ <= FIFO_PREEMPT_REQ;
FIFO_PREEMPT_REQ <= 1'b1;
TRIGGER_DATA_WRITE <= 1'b0;
// de-assert TLU busy as soon as possible
//if (TRIGGER_ACKNOWLEDGED == 1'b1 && FIFO_ACKNOWLEDGED == 1'b1)
// TLU_BUSY <= 1'b0;
//else
TLU_BUSY <= TLU_BUSY;
TLU_CLOCK_ENABLE <= 1'b0;
counter_tlu_clock <= 0;
counter_sr_wait_cycles <= 0;
TRIGGER_ACCEPTED_FLAG <= 1'b0;
if (TRIGGER_ACKNOWLEDGE == 1'b1)
TRIGGER_ACKNOWLEDGED <= 1'b1;
if (FIFO_ACKNOWLEDGE == 1'b1)
FIFO_ACKNOWLEDGED <= 1'b1;
end
endcase
end
end
// time stamp
always @ (posedge TRIGGER_CLK)
begin
if (RESET | TLU_RESET_FLAG)
TIMESTAMP <= {(TIMESTAMP_N_OF_BIT){1'b0}};
else
TIMESTAMP <= TIMESTAMP + 1;
end
// trigger counter
always @ (posedge TRIGGER_CLK)
begin
if (RESET)
TRIGGER_COUNTER <= 32'b0;
else if(TRIGGER_COUNTER_SET==1'b1)
TRIGGER_COUNTER <= TRIGGER_COUNTER_SET_VALUE;
else if(TRIGGER_ACCEPTED_FLAG)
TRIGGER_COUNTER <= TRIGGER_COUNTER + 1;
end
// Chipscope
`ifdef SYNTHESIS_NOT
//`ifdef SYNTHESIS
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.TRIGGER_CLK(TRIGGER_CLK),
.TRIG0({TRIGGER_ENABLE, TRIGGER_DATA_WRITE, TRIGGER_ACCEPTED_FLAG, TLU_CLOCK_ENABLE, TLU_ASSERT_VETO, TLU_BUSY, TRIGGER_ACKNOWLEDGE, TRIGGER_VETO, TLU_TRIGGER_ACCEPT_ERROR, TLU_TRIGGER_LOW_TIMEOUT_ERROR, TRIGGER_FLAG, TRIGGER, TRIGGER_MODE, state})
//.TRIGGER_CLK(CLK_160),
//.TRIG0({FMODE, FSTROBE, FREAD, CMD_BUS_WR, RX_BUS_WR, FIFO_WR, BUS_DATA_IN, FE_RX ,WR_B, RD_B})
);
`endif
endmodule |
module or1200_spram_32x24(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 24;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [31:24] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [31:24] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[23:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({4'b0000, addr}),
.DI({8'h00, di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule |
module FFT_TEST;
// Inputs
reg clk;
reg [15:0] data_in;
reg data_in_valid;
reg slave_ready;
// Outputs
wire [15:0] data_out;
wire data_in_ready;
wire data_out_valid;
wire [7:0] output_index;
// Instantiate the Unit Under Test (UUT)
wrap_FFT uut (
.clk(clk),
//.input_index(input_index),
.data_in(data_in),
.data_out(data_out),
.data_in_ready(data_in_ready),
.data_in_valid(data_in_valid),
.data_out_valid(data_out_valid),
.slave_ready(slave_ready),
.output_index(output_index)
);
always begin
#5 clk = ~clk;
end
initial begin
// Initialize Inputs
clk = 0;
data_in = 0;
data_in_valid = 0;
slave_ready = 0;
//input_index = 0;
// Wait 100 ns for global reset to finish
#10 data_in_valid = 1;slave_ready = 1;
#10 data_in = 10'b1010110011;//input_index = 8'd0;
#10 data_in = 10'b1010111111;//input_index = 8'd1;
#10 data_in = 10'b1010110111;//input_index = 8'd2;
#10 data_in = 10'b1011110011;//input_index = 8'd3;
#10 data_in = 10'b1010110011;//input_index = 8'd4;
#10 data_in = 10'b1010111111;//input_index = 8'd5;
#10 data_in = 10'b1010101111;//input_index = 8'd6;
#10 data_in = 10'b1010110011;//input_index = 8'd7;
#10 data_in = 10'b1010010111;//input_index = 8'd8;
#10 data_in = 10'b1010110011;//input_index = 8'd9;
#10 data_in = 10'b1010110011;//input_index = 8'd10;
#10 data_in = 10'b1010111011;//input_index = 8'd11;
#10 data_in = 10'b1010110011;//input_index = 8'd12;
#10 data_in = 10'b1010110011;//input_index = 8'd13;
#10 data_in = 10'b1010001011;//input_index = 8'd14;
#10 data_in = 10'b1010110011;//input_index = 8'd15;
#10 data_in = 10'b1010110011;//input_index = 8'd0;
#10 data_in = 10'b1010111111;//input_index = 8'd1;
#10 data_in = 10'b1010110111;//input_index = 8'd2;
#10 data_in = 10'b1011110011;//input_index = 8'd3;
#10 data_in = 10'b1010110011;//input_index = 8'd4;
#10 data_in = 10'b1010111111;//input_index = 8'd5;
#10 data_in = 10'b1010101111;//input_index = 8'd6;
#10 data_in = 10'b1010110011;//input_index = 8'd7;
#10 data_in = 10'b1010010111;//input_index = 8'd8;
#10 data_in = 10'b1010110011;//input_index = 8'd9;
#10 data_in = 10'b1010110011;//input_index = 8'd10;
#10 data_in = 10'b1010111011;//input_index = 8'd11;
#10 data_in = 10'b1010110011;//input_index = 8'd12;
#10 data_in = 10'b1010110011;//input_index = 8'd13;
#10 data_in = 10'b1010001011;//input_index = 8'd14;
#10 data_in = 10'b1010110011;//input_index = 8'd15;
#10 data_in = 10'b1010110011;//input_index = 8'd0;
#10 data_in = 10'b1010111111;//input_index = 8'd1;
#10 data_in = 10'b1010110111;//input_index = 8'd2;
#10 data_in = 10'b1011110011;//input_index = 8'd3;
#10 data_in = 10'b1010110011;//input_index = 8'd4;
#10 data_in = 10'b1010111111;//input_index = 8'd5;
#10 data_in = 10'b1010101111;//input_index = 8'd6;
#10 data_in = 10'b1010110011;//input_index = 8'd7;
#10 data_in = 10'b1010010111;//input_index = 8'd8;
#10 data_in = 10'b1010110011;//input_index = 8'd9;
#10 data_in = 10'b1010110011;//input_index = 8'd10;
#10 data_in = 10'b1010111011;//input_index = 8'd11;
#10 data_in = 10'b1010110011;//input_index = 8'd12;
#10 data_in = 10'b1010110011;//input_index = 8'd13;
#10 data_in = 10'b1010001011;//input_index = 8'd14;
#10 data_in = 10'b1010110011;//input_index = 8'd15;
#10 data_in = 10'b1010110011;//input_index = 8'd0;
#10 data_in = 10'b1010111111;//input_index = 8'd1;
#10 data_in = 10'b1010110111;//input_index = 8'd2;
#10 data_in = 10'b1011110011;//input_index = 8'd3;
#10 data_in = 10'b1010110011;//input_index = 8'd4;
#10 data_in = 10'b1010111111;//input_index = 8'd5;
#10 data_in = 10'b1010101111;//input_index = 8'd6;
#10 data_in = 10'b1010110011;//input_index = 8'd7;
#10 data_in = 10'b1010010111;//input_index = 8'd8;
#10 data_in = 10'b1010110011;//input_index = 8'd9;
#10 data_in = 10'b1010110011;//input_index = 8'd10;
#10 data_in = 10'b1010111011;//input_index = 8'd11;
#10 data_in = 10'b1010110011;//input_index = 8'd12;
#10 data_in = 10'b1010110011;//input_index = 8'd13;
#10 data_in = 10'b1010001011;//input_index = 8'd14;
#10 data_in = 10'b1010110011;//input_index = 8'd15;
#10 data_in = 10'b1010110011;//input_index = 8'd0;
#10 data_in = 10'b1010111111;//input_index = 8'd1;
#10 data_in = 10'b1010110111;//input_index = 8'd2;
#10 data_in = 10'b1011110011;//input_index = 8'd3;
#10 data_in = 10'b1010110011;//input_index = 8'd4;
#10 data_in = 10'b1010111111;//input_index = 8'd5;
#10 data_in = 10'b1010101111;//input_index = 8'd6;
#10 data_in = 10'b1010110011;//input_index = 8'd7;
#10 data_in = 10'b1010010111;//input_index = 8'd8;
#10 data_in = 10'b1010110011;//input_index = 8'd9;
#10 data_in = 10'b1010110011;//input_index = 8'd10;
#10 data_in = 10'b1010111011;//input_index = 8'd11;
#10 data_in = 10'b1010110011;//input_index = 8'd12;
#10 data_in = 10'b1010110011;//input_index = 8'd13;
#10 data_in = 10'b1010001011;//input_index = 8'd14;
#10 data_in = 10'b1010110011;//input_index = 8'd15;
#10 data_in = 10'b1010110011;//input_index = 8'd0;
#10 data_in = 10'b1010111111;//input_index = 8'd1;
#10 data_in = 10'b1010110111;//input_index = 8'd2;
#10 data_in = 10'b1011110011;//input_index = 8'd3;
#10 data_in = 10'b1010110011;//input_index = 8'd4;
#10 data_in = 10'b1010111111;//input_index = 8'd5;
#10 data_in = 10'b1010101111;//input_index = 8'd6;
#10 data_in = 10'b1010110011;//input_index = 8'd7;
#10 data_in = 10'b1010010111;//input_index = 8'd8;
#10 data_in = 10'b1010110011;//input_index = 8'd9;
#10 data_in = 10'b1010110011;//input_index = 8'd10;
#10 data_in = 10'b1010111011;//input_index = 8'd11;
#10 data_in = 10'b1010110011;//input_index = 8'd12;
#10 data_in = 10'b1010110011;//input_index = 8'd13;
#10 data_in = 10'b1010001011;//input_index = 8'd14;
#10 data_in = 10'b1010110011;//input_index = 8'd15;
#10 data_in = 10'b1010110011;//input_index = 8'd0;
#10 data_in = 10'b1010111111;//input_index = 8'd1;
#10 data_in = 10'b1010110111;//input_index = 8'd2;
#10 data_in = 10'b1011110011;//input_index = 8'd3;
#10 data_in = 10'b1010110011;//input_index = 8'd4;
#10 data_in = 10'b1010111111;//input_index = 8'd5;
#10 data_in = 10'b1010101111;//input_index = 8'd6;
#10 data_in = 10'b1010110011;//input_index = 8'd7;
#10 data_in = 10'b1010010111;//input_index = 8'd8;
#10 data_in = 10'b1010110011;//input_index = 8'd9;
#10 data_in = 10'b1010110011;//input_index = 8'd10;
#10 data_in = 10'b1010111011;//input_index = 8'd11;
#10 data_in = 10'b1010110011;//input_index = 8'd12;
#10 data_in = 10'b1010110011;//input_index = 8'd13;
#10 data_in = 10'b1010001011;//input_index = 8'd14;
#10 data_in = 10'b1010110011;//input_index = 8'd15;
#10 data_in = 10'b1010110011;//input_index = 8'd0;
#10 data_in = 10'b1010111111;//input_index = 8'd1;
#10 data_in = 10'b1010110111;//input_index = 8'd2;
#10 data_in = 10'b1011110011;//input_index = 8'd3;
#10 data_in = 10'b1010110011;//input_index = 8'd4;
#10 data_in = 10'b1010111111;//input_index = 8'd5;
#10 data_in = 10'b1010101111;//input_index = 8'd6;
#10 data_in = 10'b1010110011;//input_index = 8'd7;
#10 data_in = 10'b1010010111;//input_index = 8'd8;
#10 data_in = 10'b1010110011;//input_index = 8'd9;
#10 data_in = 10'b1010110011;//input_index = 8'd10;
#10 data_in = 10'b1010111011;//input_index = 8'd11;
#10 data_in = 10'b1010110011;//input_index = 8'd12;
#10 data_in = 10'b1010110011;//input_index = 8'd13;
#10 data_in = 10'b1010001011;//input_index = 8'd14;
#10 data_in = 10'b1010110011;//input_index = 8'd15;
// Add stimulus here
end
endmodule |
module sky130_fd_sc_lp__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module dff_async_reset
(input wire d, // Data Input
input wire clk, // Clock Input
input wire reset_b, // Reset input
output reg q); // Q output
always@(posedge clk or negedge reset_b)
if (~reset_b) q <= 1'b0;
else q <= d;
endmodule |
module sync
(input wire OutputClock, //
input wire reset_b, //
input wire InputData, //
output wire OutputData); //
/*************************************************************************
* Continuous Assignments *
*************************************************************************/
wire synch_flop_1;
/*************************************************************************
* Module Instantations *
*************************************************************************/
dff_async_reset
dff_1
(// Global Signals // ----------------------------
.clk (OutputClock),
.reset_b (reset_b),
// // ----------------------------
.d (InputData),
.q (synch_flop_1));
dff_async_reset
dff_2
(// Global Signals // ----------------------------
.clk (OutputClock),
.reset_b (reset_b),
// // ----------------------------
.d (synch_flop_1),
.q (OutputData));
endmodule |
module COMPARE
#(parameter DEPTH = 10, ALMOST_FULL = 4 /* 32 Elements */)
(input [DEPTH:0] wptr, rptr,
output wire empty, full);
/*************************************************************************
* Continuous Assignments *
*************************************************************************/
assign empty = (wptr[DEPTH:0] == rptr[DEPTH:0]);
// assign full = (wptr[DEPTH] != rptr[DEPTH]) & (wptr[DEPTH-1:0] == rptr[DEPTH-1:0]);
assign full = (wptr[DEPTH] != rptr[DEPTH]) & (wptr[DEPTH-1: ALMOST_FULL] == rptr[DEPTH-1: ALMOST_FULL]);
// synthesis translate off
always@(full or empty) begin
$display("current depth is %0d, current empty is %0d, current full is %0d", DEPTH, empty, full);
end
// synthesis translate on
endmodule |
module POINTER
#(parameter DEPTH = 5 /* 32 Elements */)
(input clk, reset_b, incr,
output reg [DEPTH:0] ptr);
// fifo control logic (register for read pointers)
always@(posedge clk, negedge reset_b)
if (~reset_b) ptr <= 0;
else if (incr) ptr <= ptr + 1;
endmodule |
module memory
#(parameter WIDTH = 7, DEPTH = 32, ADDR = 5)
(// Globals Signals
input wire clk, reset_b,
input wire write,
input wire [ADDR -1:0] waddr, raddr,
input wire [WIDTH-1:0] wdata,
output wire [WIDTH-1:0] rdata);
integer i;
reg [WIDTH-1:0] memory [DEPTH-1:0];
/*************************************************************************
* Continuous Assignments *
*************************************************************************/
assign rdata = memory [raddr]; // register file read operation
always @(posedge clk, negedge reset_b) // register file write operation
if (~reset_b) for (i = 0; i < DEPTH; i = i + 1) memory[i] <= 'd0;
else if (write) memory [waddr] <= wdata;
endmodule |
module async_fifo (reset_b, rclk, wclk, write, read, wdata, rdata, empty, full);
parameter WIDTH = 8;
parameter DEPTH = 32;
parameter ADDR = 5;
input wire reset_b;
input wire rclk;
input wire wclk;
input wire write;
input wire read;
input wire [WIDTH-1:0] wdata;
output wire [WIDTH-1:0] rdata;
output wire empty;
output wire full;
wire write_wclk;
wire read_rclk;
wire [WIDTH-1:0] wdata_wclk;
wire [WIDTH-1:0] rdata_wclk;
wire [ADDR :0] raddr_wclk;
wire [ADDR :0] waddr_wclk;
wire [ADDR :0] raddr_rclk;
wire [ADDR :0] waddr_rclk;
/*************************************************************************
* Continuous Assignments *
*************************************************************************/
assign wdata_wclk = wdata;
assign write_wclk = write;
assign read_rclk = read;
assign rdata = rdata_wclk;
/*************************************************************************
* Module Instantiation *
*************************************************************************/
memory #(WIDTH, DEPTH, ADDR)
i_memory
(// Globals Signals
.clk (wclk),
.reset_b (reset_b),
.write (write_wclk),
.waddr (waddr_wclk[ADDR-1:0]),
.raddr (raddr_wclk[ADDR-1:0]),
.wdata (wdata_wclk),
.rdata (rdata_wclk));
genvar i;
generate
for(i=0; i <= ADDR; i = i + 1) begin: Write_Address
sync
i_write_ClockSync
(// Global Signals
.OutputClock(rclk), // I
.reset_b (reset_b), // I
//
.InputData (waddr_wclk[i]), // I
//
.OutputData (waddr_rclk[i]));// O
end
endgenerate
genvar j;
generate
for(j = 0; j <= ADDR; j = j + 1) begin: Read_Address
sync
i_read_ClockSync
(// Glbal Signals
.OutputClock(wclk), // I
.reset_b (reset_b), // I
//
.InputData (raddr_rclk[j]), // I
//
.OutputData (raddr_wclk[j]));// O
end
endgenerate
POINTER #(ADDR)
read_pointer_rclk
(// Globals Signals
.clk (rclk),
.reset_b (reset_b),
//
.incr (read_rclk),
//
.ptr (raddr_rclk));
POINTER #(ADDR)
write_pointer_wclk
(.clk (wclk),
.reset_b (reset_b),
.incr (write_wclk),
.ptr (waddr_wclk));
COMPARE #(ADDR)
comparator_rclk (
.wptr (waddr_rclk),
.rptr (raddr_rclk),
.empty (empty),
.full ());
COMPARE #(ADDR)
comparator_wclk
(.wptr (waddr_wclk),
.rptr (raddr_wclk),
.empty (),
.full (full));
endmodule |
module output_sm (
// Global inputs
input wire clk, // System Clock
input wire reset_b, // Active high, asyn reset
// FIFO Interface
input wire fifo_empty, // FIFO is empty
output wire fifo_read, // FIFO read enable
input wire [8:0] fifo_data, // FIFO data
// Ouput Interface
output wire ready, // Output data valid
input wire read, // Output read enable
output reg [7:0] port // Data input
);
parameter IDLE = 3'b000,
PROCESS_PACKET = 3'b001,
PROCESS_LAST = 3'b010,
END_OF_PACKET_1 = 3'b011,
END_OF_PACKET_2 = 3'b100,
END_OF_PACKET_3 = 3'b101;
reg [02:00] state, next_state;
reg [08:00] last_fifo_data;
reg [07:00] next_port;
reg hold_off_ready;
wire end_of_packet;
/*************************************************************************
* Continuous Assignments *
*************************************************************************/
// Pass FIFO empty signal directly out as Output data valid,
// but also hold it until packet is processed
assign ready = (~fifo_empty && ~hold_off_ready) || (state == PROCESS_LAST);
// Pass read signal directly through as FIFO read, as long as we are in
// states that need new data
assign fifo_read = (~fifo_empty & read & ((next_state == PROCESS_PACKET) | (next_state == PROCESS_LAST)));
assign end_of_packet = fifo_data[8];
// Synchronous SM Logic
always @(posedge clk or negedge reset_b)
if (~reset_b) begin
state <= IDLE;
port <= 8'h0;
end
else begin
state <= next_state;
port <= next_port;
last_fifo_data <= fifo_data;
end
// Aynchronous SM Logic
always @*
case(state)
IDLE: begin
hold_off_ready = 1'b0; // Enforce inter-packet gap
if (read && ~fifo_empty) begin
next_state = PROCESS_PACKET;
next_port = fifo_data[7:0];
end
else begin
next_state = IDLE;
next_port = 8'h00;
end
end
PROCESS_PACKET: begin
hold_off_ready = 1'b0; // Enforce inter-packet gap
// We decide that we are done processing the current packet,
// either when the FIFO is empty or we see a different value
// in the FIFO Index from our current value.
if (end_of_packet | fifo_empty) begin
next_state = PROCESS_LAST;
next_port = fifo_data[7:0];
end
else begin
next_state = PROCESS_PACKET;
next_port = fifo_data[7:0];
end
end
PROCESS_LAST: begin
hold_off_ready = 1'b1; // Enforce inter-packet gap
next_state = END_OF_PACKET_1;
next_port = 8'h00;
end
END_OF_PACKET_1: begin
hold_off_ready = 1'b1; // Enforce inter-packet gap
next_state = END_OF_PACKET_2;
next_port = 8'h00;
end
END_OF_PACKET_2: begin
hold_off_ready = 1'b1; // Enforce inter-packet gap
next_state = END_OF_PACKET_3;
next_port = 8'h00;
end
END_OF_PACKET_3: begin
hold_off_ready = 1'b1; // Enforce inter-packet gap
next_state = IDLE;
next_port = 8'h00;
end
// Illegal state
default: begin
hold_off_ready = 1'b0; // Enforce inter-packet gap
next_state = IDLE;
next_port = 8'h00;
end
endcase
endmodule |
module packet_router (
// Global inputs // ------------------------------------
input wire clk, // System Clock
input wire reset_b, // Active Low, asyn reset
// Port address registers // ------------------------------------
input wire [07:00] address_port_0, // Address for each port
input wire [07:00] address_port_1, //
input wire [07:00] address_port_2, //
input wire [07:00] address_port_3, //
// Input port // ------------------------------------
input wire data_stall, // Stall the input stream
input wire data_valid, // Data valid input
input wire [07:00] data, // Data input
// Output ports // ------------------------------------
output reg ready_0, // Port 0 Output has data
output reg [07:00] port0, // Port 0 Data Output
output reg ready_1, // Output has data
output reg [07:00] port1, // Data input
output reg ready_2, // Output has data
output reg [07:00] port2, // Data input
output reg ready_3, // Output has data
output reg [07:00] port3); // Data input
parameter
IDLE = 1'b0,
PROCESS_PACKET = 1'b1;
reg state;
reg next_state;
reg [7:0] data_d;
reg data_ready;
reg [7:0] packet_address;
/*************************************************************************
* Continuous Assignments *
*************************************************************************/
// Synchronous SM Logic
always @(posedge clk or negedge reset_b) begin
if (~reset_b) begin
state <= IDLE;
data_d <= 9'h00;
data_ready <= 1'b0;
packet_address <= 8'h00;
end
else begin
state <= next_state;
data_d <= data;
data_ready <= data_valid;
if (state == IDLE)
packet_address <= data;
end
end
// Aynchronous SM Logic
always @*
case(state)
IDLE:
if (data_valid & ~data_stall) next_state = PROCESS_PACKET;
else next_state = IDLE;
PROCESS_PACKET:
if (data_valid & ~data_stall) next_state = PROCESS_PACKET;
else if (~data_valid) next_state = IDLE;
else next_state = PROCESS_PACKET;
endcase
// Route data to correct output port or drop
always @* begin
port0 = 8'd0;
ready_0 = 1'b0;
port1 = 8'd0;
ready_1 = 1'b0;
port2 = 8'd0;
ready_2 = 1'b0;
port3 = 8'd0;
ready_3 = 1'b0;
case(packet_address)
address_port_0: begin
port0 = data_d;
ready_0 = data_ready;
end
address_port_1: begin
port1 = data_d;
ready_1 = data_ready;
end
address_port_2: begin
port2 = data_d;
ready_2 = data_ready;
end
address_port_3: begin
port3 = data_d;
ready_3 = data_ready;
end
endcase
end
endmodule |
module port_address_reg
(// Global inputs // -------------------------------------
input wire clk, // System Clock
input wire reset_b, // Active high, asyn reset
// Memory inputs // -------------------------------------
input wire mem_en, // Memory enable
input wire mem_rd_wr, // Memory read/write
input wire [01:00] mem_addr, // Memory address
input wire [07:00] mem_wdata, // Memory data
output reg [07:00] mem_rdata, // Memory data
// Register outputs // -------------------------------------
output reg [07:00] address_port_0,// Port 0 address
output reg [07:00] address_port_1,// Port 1 address
output reg [07:00] address_port_2,// Port 2 address
output reg [07:00] address_port_3 // Port 3 address
);
always@*
case(mem_addr)
2'd0: mem_rdata <= address_port_0;
2'd1: mem_rdata <= address_port_1;
2'd2: mem_rdata <= address_port_2;
2'd3: mem_rdata <= address_port_3;
endcase
always @(posedge clk or negedge reset_b) begin
if (~reset_b) begin
address_port_0 <= 8'h00;
address_port_1 <= 8'h01;
address_port_2 <= 8'h02;
address_port_3 <= 8'h03;
end
else if (mem_en && mem_rd_wr) begin
case (mem_addr)
2'b00: address_port_0 <= mem_wdata;
2'b01: address_port_1 <= mem_wdata;
2'b10: address_port_2 <= mem_wdata;
2'b11: address_port_3 <= mem_wdata;
endcase
end
end
endmodule |
module switch (
// Global inputs // -------------------------------------
input wire fast_clk, // 1GHz Write Clock
input wire slow_clk, // 111MHz Read Clock
input wire reset_b, // Active Low, Asynchronous Reset
// Memory inputs // -------------------------------------
input wire mem_en, // Memory enable
input wire mem_rd_wr, // Memory read/write
input wire [01:00] mem_addr, // Memory address
input wire [07:00] mem_wdata, // Data to be written to the memory interface
output wire [07:00] mem_rdata, // Data read from the memory interface
// Input port // -------------------------------------
output wire data_stall, //
input wire data_valid, // Data valid input
input wire [07:00] data, // Data input
// Output ports // -------------------------------------
output wire ready_0, // Port 0 has data
input wire read_0, // Data valid input
output wire [07:00] port0, // Data input
output wire ready_1, // Output has data
input wire read_1, // Data valid input
output wire [7:0] port1, // Data input
output wire ready_2, // Output has data
input wire read_2, // Data valid input
output wire [7:0] port2, // Data input
output wire ready_3, // Output has data
input wire read_3, // Data valid input
output wire [7:0] port3); // Data input
// Internal signals
wire [07:00] address_port [03:00]; // Address for each port
wire [03:00] router_ready; // Router has data
wire [07:00] router_port [03:00]; // Router data
wire [03:00] fifo_empty;
wire [03:00] fifo_full; // FIFO has data
wire [03:00] fifo_read; //
wire [08:00] fifo_port [03:00]; // FIFO data
/*************************************************************************
* Continuous Assignments *
**************************************************************************/
assign data_stall = |fifo_full;
/*************************************************************************
* Module Instantations *
**************************************************************************/
port_address_reg // Instantiate Port address registers
i_port_address_reg
(// Global Signals // -------------------------------
.clk (fast_clk), //
.reset_b (reset_b), //
// Memory Configuration Interface // -------------------------------
.mem_en (mem_en), //
.mem_rd_wr (mem_rd_wr), //
.mem_addr (mem_addr), //
.mem_rdata (mem_rdata), //
.mem_wdata (mem_wdata), //
// Output Mux'ing Interface // -------------------------------
.address_port_0 (address_port[0]), //
.address_port_1 (address_port[1]), //
.address_port_2 (address_port[2]), //
.address_port_3 (address_port[3])); //
// Instantiate Port address registers
packet_router
i_packet_router (
// Global Signals // -------------------------------
.clk (fast_clk), // I
.reset_b (reset_b), // I
// // -------------------------------
.address_port_0 (address_port[0]), // O [07:00]
.address_port_1 (address_port[1]), // O [07:00]
.address_port_2 (address_port[2]), // O [07:00]
.address_port_3 (address_port[3]), //
.data_stall (data_stall), // I
.data_valid (data_valid), //
.data (data), //
.ready_0 (router_ready[0]), //
.port0 (router_port[0]), //
.ready_1 (router_ready[1]), //
.port1 (router_port[1]), //
.ready_2 (router_ready[2]), //
.port2 (router_port[2]), //
.ready_3 (router_ready[3]), //
.port3 (router_port[3])); //
genvar i;
generate
for(i=0; i < 4; i = i + 1) begin: Asynchronous_FIFOs
async_fifo #(9,1024,10) // Instantiate Packet FIFO's (1024 deep by 8 bits)
i_fifo (
// Global Signals // ---------------------------------
.reset_b (reset_b), // I Active-Low Asynchronous
// Read Interface // ---------------------------------
.rclk (slow_clk), // I 111MHz Read Clock
.read (fifo_read[i]), // I Advance read pointer
.empty (fifo_empty[i]), // O FIFO is Empty
.rdata (fifo_port[i]), // O [08:00] Data being read
// Write Interface // ---------------------------------
.wclk (fast_clk), // I 1GHz Write Clock
.write (router_ready[i]),// I Push Data Signal
.wdata ({~data_valid, router_port[i][7:0]}), // I [08:00] Data to be written
.full (fifo_full[i])); // O FIFO is Full
end
endgenerate
// Instantiate Output SM's
output_sm
i_output_sm_0 (
// Global Signals // ---------------------------------
.clk (slow_clk), // I 111MHz Read Clock
.reset_b (reset_b), // I Active-Low Asynchronous
// FIFO Interface // ---------------------------------
.fifo_empty (fifo_empty[0]), //
.fifo_read (fifo_read[0]), //
.fifo_data (fifo_port[0]), //
//
.ready (ready_0), //
.read (read_0), //
.port (port0)); //
output_sm
i_output_sm_1 (
// Global Signals // ----------------------------
.clk (slow_clk), // I 111MHz Read Clock
.reset_b (reset_b), // I Active-Low Asynchronous
// FIFO Interface // ----------------------------
.fifo_empty (fifo_empty[1]),
.fifo_read (fifo_read[1]),
.fifo_data (fifo_port[1]), // I [08:00]
// Output Interface
.ready (ready_1),
.read (read_1),
.port (port1));
output_sm
i_output_sm_2
(// Global Signals // ----------------------------
.clk (slow_clk), // I 111MHz Read Clock
.reset_b (reset_b), // I Active-Low Asynchronous
// FIFO Interface // ----------------------------
.fifo_empty (fifo_empty[2]), //
.fifo_read (fifo_read[2]), //
.fifo_data (fifo_port[2]), //
// Output Interface // -----------------------------
.ready (ready_2), //
.read (read_2), //
.port (port2)); //
output_sm
i_output_sm_3
(// Global Signals // ----------------------------
.clk (slow_clk), // I 111MHz Read Clock
.reset_b (reset_b), // I Active-Low Asynchronous
// FIFO Interface // ----------------------------
.fifo_empty (fifo_empty[3]),
.fifo_read (fifo_read[3]),
.fifo_data (fifo_port[3]),
// Output Interface // -----------------------------
.ready (ready_3),
.read (read_3),
.port (port3));
endmodule |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.