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module tb_elink
reg [1:0] elink_txrr_packet;
wire elink_txo_lclk_p;
wire elink_chip_resetb;
reg elink_rxrr_wait;
wire elink_txrd_wait;
wire elink_rxwr_access;
wire elink_cclk_p;
reg elink_rxrd_wait;
wire elink_cclk_n;
wire elink_rxrr_access;
reg elink_txwr_clk;
wire [3:0] elink_rowid;
reg elink_txwr_access;
wire [3:0] elink_colid;
wire elink_txo_lclk_n;
reg elink_rxwr_clk;
wire [1:0] elink_rxrr_packet;
reg elink_rxi_frame_n;
reg [7:0] elink_rxi_data_n;
reg elink_clkin;
reg elink_txrr_access;
reg elink_hard_reset;
reg elink_txi_rd_wait_p;
reg elink_rxrd_clk;
wire elink_txo_frame_n;
reg [1:0] elink_txrd_packet;
reg elink_txi_rd_wait_n;
reg elink_txi_wr_wait_p;
reg elink_txrd_clk;
reg [7:0] elink_rxi_data_p;
reg elink_rxi_frame_p;
wire [7:0] elink_txo_data_n;
reg elink_txrd_access;
wire elink_rxo_rd_wait_p;
reg elink_rxrr_clk;
wire [1:0] elink_rxwr_packet;
wire elink_rxo_rd_wait_n;
wire elink_mailbox_not_empty;
reg elink_txi_wr_wait_n;
wire elink_mailbox_full;
wire elink_txwr_wait;
wire [7:0] elink_txo_data_p;
wire elink_txo_frame_p;
reg elink_rxwr_wait;
wire [1:0] elink_rxrd_packet;
reg elink_rxi_lclk_p;
wire elink_rxo_wr_wait_p;
wire elink_txrr_wait;
reg [2:0] elink_clkbypass;
wire elink_rxrd_access;
reg [1:0] elink_txwr_packet;
wire elink_rxo_wr_wait_n;
reg elink_txrr_clk;
reg elink_rxi_lclk_n;
initial begin
$from_myhdl(
elink_txrr_packet,
elink_rxrr_wait,
elink_rxrd_wait,
elink_txwr_clk,
elink_txwr_access,
elink_rxwr_clk,
elink_rxi_frame_n,
elink_rxi_data_n,
elink_clkin,
elink_txrr_access,
elink_hard_reset,
elink_txi_rd_wait_p,
elink_rxrd_clk,
elink_txrd_packet,
elink_txi_rd_wait_n,
elink_txi_wr_wait_p,
elink_txrd_clk,
elink_rxi_data_p,
elink_rxi_frame_p,
elink_txrd_access,
elink_rxrr_clk,
elink_txi_wr_wait_n,
elink_rxwr_wait,
elink_rxi_lclk_p,
elink_clkbypass,
elink_txwr_packet,
elink_txrr_clk,
elink_rxi_lclk_n
);
$to_myhdl(
elink_txo_lclk_p,
elink_chip_resetb,
elink_txrd_wait,
elink_rxwr_access,
elink_cclk_p,
elink_cclk_n,
elink_rxrr_access,
elink_rowid,
elink_colid,
elink_txo_lclk_n,
elink_rxrr_packet,
elink_txo_frame_n,
elink_txo_data_n,
elink_rxo_rd_wait_p,
elink_rxwr_packet,
elink_rxo_rd_wait_n,
elink_mailbox_not_empty,
elink_mailbox_full,
elink_txwr_wait,
elink_txo_data_p,
elink_txo_frame_p,
elink_rxrd_packet,
elink_rxo_wr_wait_p,
elink_txrr_wait,
elink_rxrd_access,
elink_rxo_wr_wait_n
);
end
elink
dut(
elink_clkin,
elink_hard_reset,
elink_clkbypass,
elink_chip_resetb,
elink_rowid,
elink_colid,
elink_mailbox_full,
elink_mailbox_not_empty,
elink_cclk_p,
elink_cclk_n,
elink_rxrr_wait,
elink_txrd_wait,
elink_txrr_packet,
elink_rxwr_access,
elink_rxrd_wait,
elink_rxrr_access,
elink_txwr_clk,
elink_txwr_access,
elink_txrd_access,
elink_rxwr_clk,
elink_txrd_clk,
elink_rxrr_packet,
elink_txrr_access,
elink_rxrd_clk,
elink_txrd_packet,
elink_rxrr_clk,
elink_rxwr_packet,
elink_txwr_wait,
elink_rxwr_wait,
elink_rxrd_packet,
elink_txrr_wait,
elink_rxrd_access,
elink_txwr_packet,
elink_txrr_clk,
elink_txo_lclk_p,
elink_txo_lclk_n,
elink_txo_data_n,
elink_txo_frame_n,
elink_txi_wr_wait_p,
elink_txi_wr_wait_n,
elink_txi_rd_wait_p,
elink_txi_rd_wait_n,
elink_rxo_rd_wait_p,
elink_rxo_rd_wait_n,
elink_txo_data_p,
elink_txo_frame_p,
elink_rxo_wr_wait_p,
elink_rxo_wr_wait_n,
elink_rxi_frame_n,
elink_rxi_data_n,
elink_rxi_data_p,
elink_rxi_lclk_p,
elink_rxi_frame_p,
elink_rxi_lclk_n
);
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] a = crc[3:0];
wire [3:0] b = crc[19:16];
// TEST
wire [3:0] out1 = {a,b}[2 +: 4];
wire [3:0] out2 = {a,b}[5 -: 4];
wire [3:0] out3 = {a,b}[5 : 2];
wire [0:0] out4 = {a,b}[2];
// Aggregate outputs into a single result vector
wire [63:0] result = {51'h0, out4, out3, out2, out1};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule |
module sky130_fd_sc_ls__udp_dff$NRS (
Q ,
SET ,
RESET,
CLK_N,
D
);
output Q ;
input SET ;
input RESET;
input CLK_N;
input D ;
endmodule |
module top (
clk,
led
);
// FPGA Hello world multible pwm duty cycle controled leds
// https://timetoexplore.net/blog/arty-fpga-verilog-02
//
// Target:
// ZYNQ 7000 Board (Arty, PYNQ-Z1, PYNQ-Z2) with at least 4 leds
//
//
// Input:
// clk(bool): clock input
// Ouput:
// led(4bitVec): led output to PYNQ-Z1/2 (ect.)
//
input clk;
output [3:0] led;
wire [3:0] led;
wire [7:0] pwm0_0_1_dutyCount;
reg [7:0] pwm0_0_1_counter = 0;
wire [7:0] pwm1_0_dutyCount;
reg [7:0] pwm1_0_counter = 0;
wire [7:0] pwm2_dutyCount;
reg [7:0] pwm2_counter = 0;
wire [7:0] pwm3_dutyCount;
reg [7:0] pwm3_counter = 0;
reg led_i [0:4-1];
initial begin: INITIALIZE_LED_I
integer i;
for(i=0; i<4; i=i+1) begin
led_i[i] = 0;
end
end
assign pwm0_0_1_dutyCount = 8'd4;
assign pwm1_0_dutyCount = 8'd16;
assign pwm2_dutyCount = 8'd64;
assign pwm3_dutyCount = 8'd255;
always @(posedge clk) begin: TOP_PWM0_0_1_LOGIC
pwm0_0_1_counter <= (pwm0_0_1_counter + 1);
led_i[0] <= (pwm0_0_1_counter < pwm0_0_1_dutyCount);
end
always @(posedge clk) begin: TOP_PWM1_0_LOGIC
pwm1_0_counter <= (pwm1_0_counter + 1);
led_i[1] <= (pwm1_0_counter < pwm1_0_dutyCount);
end
always @(posedge clk) begin: TOP_PWM2_LOGIC
pwm2_counter <= (pwm2_counter + 1);
led_i[2] <= (pwm2_counter < pwm2_dutyCount);
end
always @(posedge clk) begin: TOP_PWM3_LOGIC
pwm3_counter <= (pwm3_counter + 1);
led_i[3] <= (pwm3_counter < pwm3_dutyCount);
end
assign led = {led_i[3], led_i[2], led_i[1], led_i[0]};
endmodule |
module user_logic (
hdmi_ref_clk,
hdmi_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
vdma_clk,
vdma_fs,
vdma_fs_ret,
vdma_empty,
vdma_almost_empty,
vdma_valid,
vdma_data,
vdma_be,
vdma_last,
vdma_ready,
up_status,
debug_trigger,
debug_data,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
input hdmi_ref_clk;
output hdmi_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [35:0] hdmi_data;
input vdma_clk;
output vdma_fs;
input vdma_fs_ret;
input vdma_empty;
input vdma_almost_empty;
input vdma_valid;
input [63:0] vdma_data;
input [ 7:0] vdma_be;
input vdma_last;
output vdma_ready;
output [ 7:0] up_status;
output [ 7:0] debug_trigger;
output [63:0] debug_data;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel;
reg up_rwn;
reg [ 4:0] up_addr;
reg [31:0] up_wdata;
reg IP2Bus_RdAck;
reg IP2Bus_WrAck;
reg [31:0] IP2Bus_Data;
reg IP2Bus_Error;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
cf_hdmi_tx_36b i_hdmi_tx_36b (
.hdmi_clk (hdmi_ref_clk),
.hdmi_vsync (hdmi_vsync),
.hdmi_hsync (hdmi_hsync),
.hdmi_data_e (hdmi_data_e),
.hdmi_data (hdmi_data),
.vdma_clk (vdma_clk),
.vdma_fs (vdma_fs),
.vdma_fs_ret (vdma_fs_ret),
.vdma_valid (vdma_valid),
.vdma_be (vdma_be),
.vdma_data (vdma_data),
.vdma_last (vdma_last),
.vdma_ready (vdma_ready),
.debug_trigger (debug_trigger),
.debug_data (debug_data),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s),
.up_status (up_status));
ODDR #(
.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC"))
i_ddr_hdmi_clk (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.C (hdmi_ref_clk),
.Q (hdmi_clk));
endmodule |
module pll(CLKIN_IN,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(6),
.CLKFX_MULTIPLY(2), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule |
module x_vector_cache_tb;
parameter SUB_WIDTH = 8;
parameter LOG2_SUB_WIDTH = log2(SUB_WIDTH - 1);
reg clk;
reg rst;
reg [31:0] col;
reg push_col;
reg [47:0] start_address;
wire req_mem;
wire [47:0] req_mem_addr;
reg rsp_mem_push;
reg [63:0] rsp_mem_q;
wire push_x;
wire [63:0] x_val;
reg stall;
wire almost_full;
x_vector_cache #(SUB_WIDTH) dut(clk, rst, col, push_col, start_address, req_mem, req_mem_addr, rsp_mem_push, rsp_mem_q, push_x, x_val, stall, almost_full);
initial begin
#1000 $display("watchdog timer reached");
$finish;
end
initial begin
clk = 0;
forever #5 clk = !clk;
end
initial begin
stall = 0;
rst = 1;
col = 0;
push_col = 0;
start_address = 0;
#100 rst = 0;
#100 push_col = 1;
#10 push_col = 0;
#10 push_col = 1;
col = 1;
#10 push_col = 1;
col = 0;
#10 push_col = 0;
end
reg [63:0] memory [0:9];
integer i;
initial begin
for(i = 0; i < 10; i = i + 1) begin
memory[i] = i;
end
end
always @(posedge clk) begin
rsp_mem_push <= req_mem;
rsp_mem_q <= memory[req_mem_addr / 8];
if(req_mem)
$display("memory request");
end
always @(posedge clk) begin
if(push_x)
$display("woot: %d", x_val);
end
`include "common.vh"
endmodule |
module sky130_fd_sc_ls__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0 (
input wire clk_clk, // clk.clk
input wire reset_reset, // reset.reset
output wire request, // tcm.request
input wire grant, // .grant
output wire [0:0] CS_N, // .CS_N_out
output wire [3:0] ByteEnable_N, // .ByteEnable_N_out
output wire [0:0] OutputEnable_N, // .OutputEnable_N_out
output wire [0:0] Write_N, // .Write_N_out
output wire [31:0] data, // .data_out
input wire [31:0] data_in, // .data_in
output wire data_outen, // .data_outen
output wire [18:0] addr, // .addr_out
output wire [0:0] rst_N, // .rst_N_out
output wire [0:0] begin_N, // .begin_N_out
input wire tcs0_request, // tcs0.request
output wire tcs0_grant, // .grant
input wire [0:0] tcs0_chipselect_n_out, // .chipselect_n_out
input wire [3:0] tcs0_byteenable_n_out, // .byteenable_n_out
input wire [0:0] tcs0_outputenable_n_out, // .outputenable_n_out
input wire [0:0] tcs0_write_n_out, // .write_n_out
input wire [31:0] tcs0_data_out, // .data_out
output wire [31:0] tcs0_data_in, // .data_in
input wire tcs0_data_outen, // .data_outen
input wire [18:0] tcs0_address_out, // .address_out
input wire [0:0] tcs0_reset_n_out, // .reset_n_out
input wire [0:0] tcs0_begintransfer_n_out // .begintransfer_n_out
);
wire [0:0] arbiter_grant_data; // arbiter:next_grant -> pin_sharer:next_grant
wire arbiter_grant_ready; // pin_sharer:ack -> arbiter:ack
wire pin_sharer_tcs0_arb_valid; // pin_sharer:arb_SRAM_tcm -> arbiter:sink0_valid
NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0_pin_sharer pin_sharer (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.request (request), // tcm.request
.grant (grant), // .grant
.CS_N (CS_N), // .CS_N_out
.ByteEnable_N (ByteEnable_N), // .ByteEnable_N_out
.OutputEnable_N (OutputEnable_N), // .OutputEnable_N_out
.Write_N (Write_N), // .Write_N_out
.data (data), // .data_out
.data_in (data_in), // .data_in
.data_outen (data_outen), // .data_outen
.addr (addr), // .addr_out
.rst_N (rst_N), // .rst_N_out
.begin_N (begin_N), // .begin_N_out
.tcs0_request (tcs0_request), // tcs0.request
.tcs0_grant (tcs0_grant), // .grant
.tcs0_tcm_chipselect_n_out (tcs0_chipselect_n_out), // .chipselect_n_out
.tcs0_tcm_byteenable_n_out (tcs0_byteenable_n_out), // .byteenable_n_out
.tcs0_tcm_outputenable_n_out (tcs0_outputenable_n_out), // .outputenable_n_out
.tcs0_tcm_write_n_out (tcs0_write_n_out), // .write_n_out
.tcs0_tcm_data_out (tcs0_data_out), // .data_out
.tcs0_tcm_data_in (tcs0_data_in), // .data_in
.tcs0_tcm_data_outen (tcs0_data_outen), // .data_outen
.tcs0_tcm_address_out (tcs0_address_out), // .address_out
.tcs0_tcm_reset_n_out (tcs0_reset_n_out), // .reset_n_out
.tcs0_tcm_begintransfer_n_out (tcs0_begintransfer_n_out), // .begintransfer_n_out
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.arb_SRAM_tcm (pin_sharer_tcs0_arb_valid) // tcs0_arb.valid
);
NIOS_SYSTEMV3_tristate_conduit_pin_sharer_0_arbiter arbiter (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // clk_reset.reset
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.sink0_valid (pin_sharer_tcs0_arb_valid) // sink0.valid
);
endmodule |
module sky130_fd_sc_lp__a211o_0 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__a211o_0 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule |
module rom (
dout,
addr
);
output [7:0] dout;
reg [7:0] dout;
input [6:0] addr;
always @(addr) begin: ROM_READ
case (addr)
0: dout = 0;
1: dout = 8;
2: dout = 28;
3: dout = 28;
4: dout = 28;
5: dout = 28;
6: dout = 28;
7: dout = 8;
8: dout = 0;
9: dout = 120;
10: dout = 14;
11: dout = 7;
12: dout = 3;
13: dout = 1;
14: dout = 1;
15: dout = 1;
16: dout = 0;
17: dout = 0;
18: dout = 0;
19: dout = 24;
20: dout = 62;
21: dout = 103;
22: dout = 65;
23: dout = 0;
24: dout = 0;
25: dout = 0;
26: dout = 12;
27: dout = 30;
28: dout = 63;
29: dout = 107;
30: dout = 73;
31: dout = 8;
32: dout = 0;
33: dout = 51;
34: dout = 102;
35: dout = 108;
36: dout = 123;
37: dout = 119;
38: dout = 101;
39: dout = 65;
40: dout = 0;
41: dout = 0;
42: dout = 0;
43: dout = 6;
44: dout = 63;
45: dout = 127;
46: dout = 59;
47: dout = 41;
48: dout = 0;
49: dout = 59;
50: dout = 30;
51: dout = 12;
52: dout = 8;
53: dout = 24;
54: dout = 60;
55: dout = 110;
56: dout = 0;
57: dout = 28;
58: dout = 94;
59: dout = 56;
60: dout = 24;
61: dout = 60;
62: dout = 102;
63: dout = 67;
64: dout = 0;
65: dout = 99;
66: dout = 62;
67: dout = 93;
68: dout = 127;
69: dout = 93;
70: dout = 62;
71: dout = 99;
72: dout = 0;
73: dout = 8;
74: dout = 68;
75: dout = 110;
76: dout = 127;
77: dout = 110;
78: dout = 68;
79: dout = 8;
80: dout = 0;
81: dout = 96;
82: dout = 120;
83: dout = 62;
84: dout = 47;
85: dout = 41;
86: dout = 97;
87: dout = 64;
88: dout = 0;
89: dout = 12;
90: dout = 30;
91: dout = 8;
92: dout = 60;
93: dout = 102;
94: dout = 65;
95: dout = 0;
96: dout = 0;
97: dout = 30;
98: dout = 3;
99: dout = 70;
100: dout = 92;
101: dout = 80;
102: dout = 120;
103: dout = 63;
104: dout = 0;
105: dout = 48;
106: dout = 88;
107: dout = 64;
108: dout = 67;
109: dout = 70;
110: dout = 108;
111: dout = 56;
112: dout = 0;
113: dout = 127;
114: dout = 63;
115: dout = 3;
116: dout = 3;
117: dout = 3;
118: dout = 3;
119: dout = 3;
120: dout = 0;
121: dout = 65;
122: dout = 99;
123: dout = 59;
124: dout = 63;
125: dout = 47;
126: dout = 99;
default: dout = 67;
endcase
end
endmodule |
module RAM128X1D #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [127:0] INIT = 128'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
) (
output DPO,
output SPO,
input [6:0] A,
input D,
input [6:0] DPRA,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM128X1D";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire D_in;
wire WCLK_in;
wire WE_in;
wire [6:0] A_in;
wire [6:0] DPRA_in;
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
`ifdef XIL_TIMING
wire D_dly;
wire WCLK_dly;
wire WE_dly;
wire [6:0] A_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign A_in = A_dly;
assign D_in = D_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign A_in = A;
assign D_in = D;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign DPRA_in = DPRA;
reg [127:0] mem;
initial
mem = INIT;
assign DPO = mem[DPRA_in];
assign SPO = mem[A_in];
always @(posedge WCLK_in)
if (WE_in == 1'b1) mem[A_in] <= #100 D_in;
`ifdef XIL_TIMING
always @(notifier) mem[A_in] <= 1'bx;
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => DPO) = (0:0:0, 0:0:0);
(WCLK => SPO) = (0:0:0, 0:0:0);
(A[0] => SPO) = (0:0:0, 0:0:0);
(A[1] => SPO) = (0:0:0, 0:0:0);
(A[2] => SPO) = (0:0:0, 0:0:0);
(A[3] => SPO) = (0:0:0, 0:0:0);
(A[4] => SPO) = (0:0:0, 0:0:0);
(A[5] => SPO) = (0:0:0, 0:0:0);
(A[6] => SPO) = (0:0:0, 0:0:0);
(DPRA[0] => DPO) = (0:0:0, 0:0:0);
(DPRA[1] => DPO) = (0:0:0, 0:0:0);
(DPRA[2] => DPO) = (0:0:0, 0:0:0);
(DPRA[3] => DPO) = (0:0:0, 0:0:0);
(DPRA[4] => DPO) = (0:0:0, 0:0:0);
(DPRA[5] => DPO) = (0:0:0, 0:0:0);
(DPRA[6] => DPO) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, negedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge A[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge A[6], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, posedge D, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule |
module sky130_fd_sc_lp__sleep_pargate_plv (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
// Module ports
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
// Local signals
wire vgnd ;
wire pwrgood_pp0_out_VIRTPWR;
// Name Output Other arguments
pulldown pulldown0 (vgnd );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_VIRTPWR, VPWR, VPWR, vgnd );
bufif0 bufif00 (VIRTPWR , pwrgood_pp0_out_VIRTPWR, SLEEP);
endmodule |
module RGB1_RGB2(
input clk,
input Btn_R,
input Btn_L,
output reg [2:0] RGB1 = 0,
output reg [2:0] RGB2 = 0
);
reg [1:0]state = 0;
reg [1:0]nextState = 0;
always @ (posedge clk)
begin
state <= nextState;
case(state)
0: begin
RGB1[0] <= 1;
RGB1[1] <= 0;
RGB1[2] <= 0;
RGB2[0] <= 1;
RGB2[1] <= 0;
RGB2[2] <= 0;
if (Btn_R == 1)
nextState <= 1;
if (Btn_L == 1)
nextState <= 2;
end
1: begin
RGB1[0] <= 0;
RGB1[1] <= 1;
RGB1[2] <= 0;
RGB2[0] <= 0;
RGB2[1] <= 1;
RGB2[2] <= 0;
if (Btn_R == 1)
nextState <= 2;
if (Btn_L == 1)
nextState <= 0;
end
2: begin
RGB1[0] <= 0;
RGB1[1] <= 0;
RGB1[2] <= 1;
RGB2[0] <= 0;
RGB2[1] <= 0;
RGB2[2] <= 1;
if (Btn_R == 1)
nextState <= 0;
if (Btn_L == 1)
nextState <= 1;
end
endcase
end
endmodule |
module amm_master_qsys_with_pcie_mm_interconnect_0 (
input wire altpll_qsys_c1_clk, // altpll_qsys_c1.clk
input wire clk_50_clk_clk, // clk_50_clk.clk
input wire pcie_ip_pcie_core_clk_clk, // pcie_ip_pcie_core_clk.clk
input wire altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset, // altpll_qsys_inclk_interface_reset_reset_bridge_in_reset.reset
input wire custom_module_reset_reset_bridge_in_reset_reset, // custom_module_reset_reset_bridge_in_reset.reset
input wire pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset, // pcie_ip_txs_translator_reset_reset_bridge_in_reset.reset
input wire sdram_reset_reset_bridge_in_reset_reset, // sdram_reset_reset_bridge_in_reset.reset
input wire sgdma_reset_reset_bridge_in_reset_reset, // sgdma_reset_reset_bridge_in_reset.reset
input wire video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset, // video_pixel_buffer_dma_0_reset_reset_bridge_in_reset.reset
input wire [27:0] custom_module_avalon_master_address, // custom_module_avalon_master.address
output wire custom_module_avalon_master_waitrequest, // .waitrequest
input wire custom_module_avalon_master_read, // .read
output wire [31:0] custom_module_avalon_master_readdata, // .readdata
output wire custom_module_avalon_master_readdatavalid, // .readdatavalid
input wire custom_module_avalon_master_write, // .write
input wire [31:0] custom_module_avalon_master_writedata, // .writedata
input wire [31:0] sgdma_descriptor_read_address, // sgdma_descriptor_read.address
output wire sgdma_descriptor_read_waitrequest, // .waitrequest
input wire sgdma_descriptor_read_read, // .read
output wire [31:0] sgdma_descriptor_read_readdata, // .readdata
output wire sgdma_descriptor_read_readdatavalid, // .readdatavalid
input wire [31:0] sgdma_descriptor_write_address, // sgdma_descriptor_write.address
output wire sgdma_descriptor_write_waitrequest, // .waitrequest
input wire sgdma_descriptor_write_write, // .write
input wire [31:0] sgdma_descriptor_write_writedata, // .writedata
input wire [31:0] sgdma_m_read_address, // sgdma_m_read.address
output wire sgdma_m_read_waitrequest, // .waitrequest
input wire [3:0] sgdma_m_read_burstcount, // .burstcount
input wire sgdma_m_read_read, // .read
output wire [63:0] sgdma_m_read_readdata, // .readdata
output wire sgdma_m_read_readdatavalid, // .readdatavalid
input wire [31:0] sgdma_m_write_address, // sgdma_m_write.address
output wire sgdma_m_write_waitrequest, // .waitrequest
input wire [7:0] sgdma_m_write_burstcount, // .burstcount
input wire [7:0] sgdma_m_write_byteenable, // .byteenable
input wire sgdma_m_write_write, // .write
input wire [63:0] sgdma_m_write_writedata, // .writedata
input wire [31:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_address, // video_pixel_buffer_dma_0_avalon_pixel_dma_master.address
output wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_waitrequest, // .waitrequest
input wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_read, // .read
output wire [31:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdata, // .readdata
output wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdatavalid, // .readdatavalid
input wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_lock, // .lock
output wire [1:0] altpll_qsys_pll_slave_address, // altpll_qsys_pll_slave.address
output wire altpll_qsys_pll_slave_write, // .write
output wire altpll_qsys_pll_slave_read, // .read
input wire [31:0] altpll_qsys_pll_slave_readdata, // .readdata
output wire [31:0] altpll_qsys_pll_slave_writedata, // .writedata
output wire [30:0] pcie_ip_txs_address, // pcie_ip_txs.address
output wire pcie_ip_txs_write, // .write
output wire pcie_ip_txs_read, // .read
input wire [63:0] pcie_ip_txs_readdata, // .readdata
output wire [63:0] pcie_ip_txs_writedata, // .writedata
output wire [6:0] pcie_ip_txs_burstcount, // .burstcount
output wire [7:0] pcie_ip_txs_byteenable, // .byteenable
input wire pcie_ip_txs_readdatavalid, // .readdatavalid
input wire pcie_ip_txs_waitrequest, // .waitrequest
output wire pcie_ip_txs_chipselect, // .chipselect
output wire [23:0] sdram_s1_address, // sdram_s1.address
output wire sdram_s1_write, // .write
output wire sdram_s1_read, // .read
input wire [31:0] sdram_s1_readdata, // .readdata
output wire [31:0] sdram_s1_writedata, // .writedata
output wire [3:0] sdram_s1_byteenable, // .byteenable
input wire sdram_s1_readdatavalid, // .readdatavalid
input wire sdram_s1_waitrequest, // .waitrequest
output wire sdram_s1_chipselect // .chipselect
);
wire custom_module_avalon_master_translator_avalon_universal_master_0_waitrequest; // custom_module_avalon_master_agent:av_waitrequest -> custom_module_avalon_master_translator:uav_waitrequest
wire [31:0] custom_module_avalon_master_translator_avalon_universal_master_0_readdata; // custom_module_avalon_master_agent:av_readdata -> custom_module_avalon_master_translator:uav_readdata
wire custom_module_avalon_master_translator_avalon_universal_master_0_debugaccess; // custom_module_avalon_master_translator:uav_debugaccess -> custom_module_avalon_master_agent:av_debugaccess
wire [31:0] custom_module_avalon_master_translator_avalon_universal_master_0_address; // custom_module_avalon_master_translator:uav_address -> custom_module_avalon_master_agent:av_address
wire custom_module_avalon_master_translator_avalon_universal_master_0_read; // custom_module_avalon_master_translator:uav_read -> custom_module_avalon_master_agent:av_read
wire [3:0] custom_module_avalon_master_translator_avalon_universal_master_0_byteenable; // custom_module_avalon_master_translator:uav_byteenable -> custom_module_avalon_master_agent:av_byteenable
wire custom_module_avalon_master_translator_avalon_universal_master_0_readdatavalid; // custom_module_avalon_master_agent:av_readdatavalid -> custom_module_avalon_master_translator:uav_readdatavalid
wire custom_module_avalon_master_translator_avalon_universal_master_0_lock; // custom_module_avalon_master_translator:uav_lock -> custom_module_avalon_master_agent:av_lock
wire custom_module_avalon_master_translator_avalon_universal_master_0_write; // custom_module_avalon_master_translator:uav_write -> custom_module_avalon_master_agent:av_write
wire [31:0] custom_module_avalon_master_translator_avalon_universal_master_0_writedata; // custom_module_avalon_master_translator:uav_writedata -> custom_module_avalon_master_agent:av_writedata
wire [2:0] custom_module_avalon_master_translator_avalon_universal_master_0_burstcount; // custom_module_avalon_master_translator:uav_burstcount -> custom_module_avalon_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> custom_module_avalon_master_agent:rp_valid
wire [113:0] rsp_mux_src_data; // rsp_mux:src_data -> custom_module_avalon_master_agent:rp_data
wire rsp_mux_src_ready; // custom_module_avalon_master_agent:rp_ready -> rsp_mux:src_ready
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> custom_module_avalon_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> custom_module_avalon_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> custom_module_avalon_master_agent:rp_endofpacket
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_waitrequest -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_waitrequest
wire [31:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_readdata -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_readdata
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_debugaccess -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_debugaccess
wire [31:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_address; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_address -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_address
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_read; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_read -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_read
wire [3:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_byteenable -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_byteenable
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_readdatavalid -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_readdatavalid
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_lock -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_lock
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_write; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_write -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_write
wire [31:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_writedata -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_writedata
wire [2:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator:uav_burstcount -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:av_burstcount
wire sgdma_m_read_translator_avalon_universal_master_0_waitrequest; // sgdma_m_read_agent:av_waitrequest -> sgdma_m_read_translator:uav_waitrequest
wire [63:0] sgdma_m_read_translator_avalon_universal_master_0_readdata; // sgdma_m_read_agent:av_readdata -> sgdma_m_read_translator:uav_readdata
wire sgdma_m_read_translator_avalon_universal_master_0_debugaccess; // sgdma_m_read_translator:uav_debugaccess -> sgdma_m_read_agent:av_debugaccess
wire [31:0] sgdma_m_read_translator_avalon_universal_master_0_address; // sgdma_m_read_translator:uav_address -> sgdma_m_read_agent:av_address
wire sgdma_m_read_translator_avalon_universal_master_0_read; // sgdma_m_read_translator:uav_read -> sgdma_m_read_agent:av_read
wire [7:0] sgdma_m_read_translator_avalon_universal_master_0_byteenable; // sgdma_m_read_translator:uav_byteenable -> sgdma_m_read_agent:av_byteenable
wire sgdma_m_read_translator_avalon_universal_master_0_readdatavalid; // sgdma_m_read_agent:av_readdatavalid -> sgdma_m_read_translator:uav_readdatavalid
wire sgdma_m_read_translator_avalon_universal_master_0_lock; // sgdma_m_read_translator:uav_lock -> sgdma_m_read_agent:av_lock
wire sgdma_m_read_translator_avalon_universal_master_0_write; // sgdma_m_read_translator:uav_write -> sgdma_m_read_agent:av_write
wire [63:0] sgdma_m_read_translator_avalon_universal_master_0_writedata; // sgdma_m_read_translator:uav_writedata -> sgdma_m_read_agent:av_writedata
wire [6:0] sgdma_m_read_translator_avalon_universal_master_0_burstcount; // sgdma_m_read_translator:uav_burstcount -> sgdma_m_read_agent:av_burstcount
wire sgdma_m_write_translator_avalon_universal_master_0_waitrequest; // sgdma_m_write_agent:av_waitrequest -> sgdma_m_write_translator:uav_waitrequest
wire [63:0] sgdma_m_write_translator_avalon_universal_master_0_readdata; // sgdma_m_write_agent:av_readdata -> sgdma_m_write_translator:uav_readdata
wire sgdma_m_write_translator_avalon_universal_master_0_debugaccess; // sgdma_m_write_translator:uav_debugaccess -> sgdma_m_write_agent:av_debugaccess
wire [31:0] sgdma_m_write_translator_avalon_universal_master_0_address; // sgdma_m_write_translator:uav_address -> sgdma_m_write_agent:av_address
wire sgdma_m_write_translator_avalon_universal_master_0_read; // sgdma_m_write_translator:uav_read -> sgdma_m_write_agent:av_read
wire [7:0] sgdma_m_write_translator_avalon_universal_master_0_byteenable; // sgdma_m_write_translator:uav_byteenable -> sgdma_m_write_agent:av_byteenable
wire sgdma_m_write_translator_avalon_universal_master_0_readdatavalid; // sgdma_m_write_agent:av_readdatavalid -> sgdma_m_write_translator:uav_readdatavalid
wire sgdma_m_write_translator_avalon_universal_master_0_lock; // sgdma_m_write_translator:uav_lock -> sgdma_m_write_agent:av_lock
wire sgdma_m_write_translator_avalon_universal_master_0_write; // sgdma_m_write_translator:uav_write -> sgdma_m_write_agent:av_write
wire [63:0] sgdma_m_write_translator_avalon_universal_master_0_writedata; // sgdma_m_write_translator:uav_writedata -> sgdma_m_write_agent:av_writedata
wire [10:0] sgdma_m_write_translator_avalon_universal_master_0_burstcount; // sgdma_m_write_translator:uav_burstcount -> sgdma_m_write_agent:av_burstcount
wire rsp_mux_003_src_valid; // rsp_mux_003:src_valid -> sgdma_m_write_agent:rp_valid
wire [149:0] rsp_mux_003_src_data; // rsp_mux_003:src_data -> sgdma_m_write_agent:rp_data
wire rsp_mux_003_src_ready; // sgdma_m_write_agent:rp_ready -> rsp_mux_003:src_ready
wire [5:0] rsp_mux_003_src_channel; // rsp_mux_003:src_channel -> sgdma_m_write_agent:rp_channel
wire rsp_mux_003_src_startofpacket; // rsp_mux_003:src_startofpacket -> sgdma_m_write_agent:rp_startofpacket
wire rsp_mux_003_src_endofpacket; // rsp_mux_003:src_endofpacket -> sgdma_m_write_agent:rp_endofpacket
wire sgdma_descriptor_read_translator_avalon_universal_master_0_waitrequest; // sgdma_descriptor_read_agent:av_waitrequest -> sgdma_descriptor_read_translator:uav_waitrequest
wire [31:0] sgdma_descriptor_read_translator_avalon_universal_master_0_readdata; // sgdma_descriptor_read_agent:av_readdata -> sgdma_descriptor_read_translator:uav_readdata
wire sgdma_descriptor_read_translator_avalon_universal_master_0_debugaccess; // sgdma_descriptor_read_translator:uav_debugaccess -> sgdma_descriptor_read_agent:av_debugaccess
wire [31:0] sgdma_descriptor_read_translator_avalon_universal_master_0_address; // sgdma_descriptor_read_translator:uav_address -> sgdma_descriptor_read_agent:av_address
wire sgdma_descriptor_read_translator_avalon_universal_master_0_read; // sgdma_descriptor_read_translator:uav_read -> sgdma_descriptor_read_agent:av_read
wire [3:0] sgdma_descriptor_read_translator_avalon_universal_master_0_byteenable; // sgdma_descriptor_read_translator:uav_byteenable -> sgdma_descriptor_read_agent:av_byteenable
wire sgdma_descriptor_read_translator_avalon_universal_master_0_readdatavalid; // sgdma_descriptor_read_agent:av_readdatavalid -> sgdma_descriptor_read_translator:uav_readdatavalid
wire sgdma_descriptor_read_translator_avalon_universal_master_0_lock; // sgdma_descriptor_read_translator:uav_lock -> sgdma_descriptor_read_agent:av_lock
wire sgdma_descriptor_read_translator_avalon_universal_master_0_write; // sgdma_descriptor_read_translator:uav_write -> sgdma_descriptor_read_agent:av_write
wire [31:0] sgdma_descriptor_read_translator_avalon_universal_master_0_writedata; // sgdma_descriptor_read_translator:uav_writedata -> sgdma_descriptor_read_agent:av_writedata
wire [2:0] sgdma_descriptor_read_translator_avalon_universal_master_0_burstcount; // sgdma_descriptor_read_translator:uav_burstcount -> sgdma_descriptor_read_agent:av_burstcount
wire rsp_mux_004_src_valid; // rsp_mux_004:src_valid -> sgdma_descriptor_read_agent:rp_valid
wire [113:0] rsp_mux_004_src_data; // rsp_mux_004:src_data -> sgdma_descriptor_read_agent:rp_data
wire rsp_mux_004_src_ready; // sgdma_descriptor_read_agent:rp_ready -> rsp_mux_004:src_ready
wire [5:0] rsp_mux_004_src_channel; // rsp_mux_004:src_channel -> sgdma_descriptor_read_agent:rp_channel
wire rsp_mux_004_src_startofpacket; // rsp_mux_004:src_startofpacket -> sgdma_descriptor_read_agent:rp_startofpacket
wire rsp_mux_004_src_endofpacket; // rsp_mux_004:src_endofpacket -> sgdma_descriptor_read_agent:rp_endofpacket
wire sgdma_descriptor_write_translator_avalon_universal_master_0_waitrequest; // sgdma_descriptor_write_agent:av_waitrequest -> sgdma_descriptor_write_translator:uav_waitrequest
wire [31:0] sgdma_descriptor_write_translator_avalon_universal_master_0_readdata; // sgdma_descriptor_write_agent:av_readdata -> sgdma_descriptor_write_translator:uav_readdata
wire sgdma_descriptor_write_translator_avalon_universal_master_0_debugaccess; // sgdma_descriptor_write_translator:uav_debugaccess -> sgdma_descriptor_write_agent:av_debugaccess
wire [31:0] sgdma_descriptor_write_translator_avalon_universal_master_0_address; // sgdma_descriptor_write_translator:uav_address -> sgdma_descriptor_write_agent:av_address
wire sgdma_descriptor_write_translator_avalon_universal_master_0_read; // sgdma_descriptor_write_translator:uav_read -> sgdma_descriptor_write_agent:av_read
wire [3:0] sgdma_descriptor_write_translator_avalon_universal_master_0_byteenable; // sgdma_descriptor_write_translator:uav_byteenable -> sgdma_descriptor_write_agent:av_byteenable
wire sgdma_descriptor_write_translator_avalon_universal_master_0_readdatavalid; // sgdma_descriptor_write_agent:av_readdatavalid -> sgdma_descriptor_write_translator:uav_readdatavalid
wire sgdma_descriptor_write_translator_avalon_universal_master_0_lock; // sgdma_descriptor_write_translator:uav_lock -> sgdma_descriptor_write_agent:av_lock
wire sgdma_descriptor_write_translator_avalon_universal_master_0_write; // sgdma_descriptor_write_translator:uav_write -> sgdma_descriptor_write_agent:av_write
wire [31:0] sgdma_descriptor_write_translator_avalon_universal_master_0_writedata; // sgdma_descriptor_write_translator:uav_writedata -> sgdma_descriptor_write_agent:av_writedata
wire [2:0] sgdma_descriptor_write_translator_avalon_universal_master_0_burstcount; // sgdma_descriptor_write_translator:uav_burstcount -> sgdma_descriptor_write_agent:av_burstcount
wire rsp_mux_005_src_valid; // rsp_mux_005:src_valid -> sgdma_descriptor_write_agent:rp_valid
wire [113:0] rsp_mux_005_src_data; // rsp_mux_005:src_data -> sgdma_descriptor_write_agent:rp_data
wire rsp_mux_005_src_ready; // sgdma_descriptor_write_agent:rp_ready -> rsp_mux_005:src_ready
wire [5:0] rsp_mux_005_src_channel; // rsp_mux_005:src_channel -> sgdma_descriptor_write_agent:rp_channel
wire rsp_mux_005_src_startofpacket; // rsp_mux_005:src_startofpacket -> sgdma_descriptor_write_agent:rp_startofpacket
wire rsp_mux_005_src_endofpacket; // rsp_mux_005:src_endofpacket -> sgdma_descriptor_write_agent:rp_endofpacket
wire [31:0] sdram_s1_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_agent:m0_readdata
wire sdram_s1_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_agent:m0_waitrequest
wire sdram_s1_agent_m0_debugaccess; // sdram_s1_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
wire [31:0] sdram_s1_agent_m0_address; // sdram_s1_agent:m0_address -> sdram_s1_translator:uav_address
wire [3:0] sdram_s1_agent_m0_byteenable; // sdram_s1_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
wire sdram_s1_agent_m0_read; // sdram_s1_agent:m0_read -> sdram_s1_translator:uav_read
wire sdram_s1_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_agent:m0_readdatavalid
wire sdram_s1_agent_m0_lock; // sdram_s1_agent:m0_lock -> sdram_s1_translator:uav_lock
wire [31:0] sdram_s1_agent_m0_writedata; // sdram_s1_agent:m0_writedata -> sdram_s1_translator:uav_writedata
wire sdram_s1_agent_m0_write; // sdram_s1_agent:m0_write -> sdram_s1_translator:uav_write
wire [2:0] sdram_s1_agent_m0_burstcount; // sdram_s1_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
wire sdram_s1_agent_rf_source_valid; // sdram_s1_agent:rf_source_valid -> sdram_s1_agent_rsp_fifo:in_valid
wire [114:0] sdram_s1_agent_rf_source_data; // sdram_s1_agent:rf_source_data -> sdram_s1_agent_rsp_fifo:in_data
wire sdram_s1_agent_rf_source_ready; // sdram_s1_agent_rsp_fifo:in_ready -> sdram_s1_agent:rf_source_ready
wire sdram_s1_agent_rf_source_startofpacket; // sdram_s1_agent:rf_source_startofpacket -> sdram_s1_agent_rsp_fifo:in_startofpacket
wire sdram_s1_agent_rf_source_endofpacket; // sdram_s1_agent:rf_source_endofpacket -> sdram_s1_agent_rsp_fifo:in_endofpacket
wire sdram_s1_agent_rsp_fifo_out_valid; // sdram_s1_agent_rsp_fifo:out_valid -> sdram_s1_agent:rf_sink_valid
wire [114:0] sdram_s1_agent_rsp_fifo_out_data; // sdram_s1_agent_rsp_fifo:out_data -> sdram_s1_agent:rf_sink_data
wire sdram_s1_agent_rsp_fifo_out_ready; // sdram_s1_agent:rf_sink_ready -> sdram_s1_agent_rsp_fifo:out_ready
wire sdram_s1_agent_rsp_fifo_out_startofpacket; // sdram_s1_agent_rsp_fifo:out_startofpacket -> sdram_s1_agent:rf_sink_startofpacket
wire sdram_s1_agent_rsp_fifo_out_endofpacket; // sdram_s1_agent_rsp_fifo:out_endofpacket -> sdram_s1_agent:rf_sink_endofpacket
wire sdram_s1_agent_rdata_fifo_src_valid; // sdram_s1_agent:rdata_fifo_src_valid -> sdram_s1_agent_rdata_fifo:in_valid
wire [33:0] sdram_s1_agent_rdata_fifo_src_data; // sdram_s1_agent:rdata_fifo_src_data -> sdram_s1_agent_rdata_fifo:in_data
wire sdram_s1_agent_rdata_fifo_src_ready; // sdram_s1_agent_rdata_fifo:in_ready -> sdram_s1_agent:rdata_fifo_src_ready
wire [63:0] pcie_ip_txs_agent_m0_readdata; // pcie_ip_txs_translator:uav_readdata -> pcie_ip_txs_agent:m0_readdata
wire pcie_ip_txs_agent_m0_waitrequest; // pcie_ip_txs_translator:uav_waitrequest -> pcie_ip_txs_agent:m0_waitrequest
wire pcie_ip_txs_agent_m0_debugaccess; // pcie_ip_txs_agent:m0_debugaccess -> pcie_ip_txs_translator:uav_debugaccess
wire [31:0] pcie_ip_txs_agent_m0_address; // pcie_ip_txs_agent:m0_address -> pcie_ip_txs_translator:uav_address
wire [7:0] pcie_ip_txs_agent_m0_byteenable; // pcie_ip_txs_agent:m0_byteenable -> pcie_ip_txs_translator:uav_byteenable
wire pcie_ip_txs_agent_m0_read; // pcie_ip_txs_agent:m0_read -> pcie_ip_txs_translator:uav_read
wire pcie_ip_txs_agent_m0_readdatavalid; // pcie_ip_txs_translator:uav_readdatavalid -> pcie_ip_txs_agent:m0_readdatavalid
wire pcie_ip_txs_agent_m0_lock; // pcie_ip_txs_agent:m0_lock -> pcie_ip_txs_translator:uav_lock
wire [63:0] pcie_ip_txs_agent_m0_writedata; // pcie_ip_txs_agent:m0_writedata -> pcie_ip_txs_translator:uav_writedata
wire pcie_ip_txs_agent_m0_write; // pcie_ip_txs_agent:m0_write -> pcie_ip_txs_translator:uav_write
wire [9:0] pcie_ip_txs_agent_m0_burstcount; // pcie_ip_txs_agent:m0_burstcount -> pcie_ip_txs_translator:uav_burstcount
wire pcie_ip_txs_agent_rf_source_valid; // pcie_ip_txs_agent:rf_source_valid -> pcie_ip_txs_agent_rsp_fifo:in_valid
wire [150:0] pcie_ip_txs_agent_rf_source_data; // pcie_ip_txs_agent:rf_source_data -> pcie_ip_txs_agent_rsp_fifo:in_data
wire pcie_ip_txs_agent_rf_source_ready; // pcie_ip_txs_agent_rsp_fifo:in_ready -> pcie_ip_txs_agent:rf_source_ready
wire pcie_ip_txs_agent_rf_source_startofpacket; // pcie_ip_txs_agent:rf_source_startofpacket -> pcie_ip_txs_agent_rsp_fifo:in_startofpacket
wire pcie_ip_txs_agent_rf_source_endofpacket; // pcie_ip_txs_agent:rf_source_endofpacket -> pcie_ip_txs_agent_rsp_fifo:in_endofpacket
wire pcie_ip_txs_agent_rsp_fifo_out_valid; // pcie_ip_txs_agent_rsp_fifo:out_valid -> pcie_ip_txs_agent:rf_sink_valid
wire [150:0] pcie_ip_txs_agent_rsp_fifo_out_data; // pcie_ip_txs_agent_rsp_fifo:out_data -> pcie_ip_txs_agent:rf_sink_data
wire pcie_ip_txs_agent_rsp_fifo_out_ready; // pcie_ip_txs_agent:rf_sink_ready -> pcie_ip_txs_agent_rsp_fifo:out_ready
wire pcie_ip_txs_agent_rsp_fifo_out_startofpacket; // pcie_ip_txs_agent_rsp_fifo:out_startofpacket -> pcie_ip_txs_agent:rf_sink_startofpacket
wire pcie_ip_txs_agent_rsp_fifo_out_endofpacket; // pcie_ip_txs_agent_rsp_fifo:out_endofpacket -> pcie_ip_txs_agent:rf_sink_endofpacket
wire pcie_ip_txs_agent_rdata_fifo_src_valid; // pcie_ip_txs_agent:rdata_fifo_src_valid -> pcie_ip_txs_agent_rdata_fifo:in_valid
wire [65:0] pcie_ip_txs_agent_rdata_fifo_src_data; // pcie_ip_txs_agent:rdata_fifo_src_data -> pcie_ip_txs_agent_rdata_fifo:in_data
wire pcie_ip_txs_agent_rdata_fifo_src_ready; // pcie_ip_txs_agent_rdata_fifo:in_ready -> pcie_ip_txs_agent:rdata_fifo_src_ready
wire [31:0] altpll_qsys_pll_slave_agent_m0_readdata; // altpll_qsys_pll_slave_translator:uav_readdata -> altpll_qsys_pll_slave_agent:m0_readdata
wire altpll_qsys_pll_slave_agent_m0_waitrequest; // altpll_qsys_pll_slave_translator:uav_waitrequest -> altpll_qsys_pll_slave_agent:m0_waitrequest
wire altpll_qsys_pll_slave_agent_m0_debugaccess; // altpll_qsys_pll_slave_agent:m0_debugaccess -> altpll_qsys_pll_slave_translator:uav_debugaccess
wire [31:0] altpll_qsys_pll_slave_agent_m0_address; // altpll_qsys_pll_slave_agent:m0_address -> altpll_qsys_pll_slave_translator:uav_address
wire [3:0] altpll_qsys_pll_slave_agent_m0_byteenable; // altpll_qsys_pll_slave_agent:m0_byteenable -> altpll_qsys_pll_slave_translator:uav_byteenable
wire altpll_qsys_pll_slave_agent_m0_read; // altpll_qsys_pll_slave_agent:m0_read -> altpll_qsys_pll_slave_translator:uav_read
wire altpll_qsys_pll_slave_agent_m0_readdatavalid; // altpll_qsys_pll_slave_translator:uav_readdatavalid -> altpll_qsys_pll_slave_agent:m0_readdatavalid
wire altpll_qsys_pll_slave_agent_m0_lock; // altpll_qsys_pll_slave_agent:m0_lock -> altpll_qsys_pll_slave_translator:uav_lock
wire [31:0] altpll_qsys_pll_slave_agent_m0_writedata; // altpll_qsys_pll_slave_agent:m0_writedata -> altpll_qsys_pll_slave_translator:uav_writedata
wire altpll_qsys_pll_slave_agent_m0_write; // altpll_qsys_pll_slave_agent:m0_write -> altpll_qsys_pll_slave_translator:uav_write
wire [2:0] altpll_qsys_pll_slave_agent_m0_burstcount; // altpll_qsys_pll_slave_agent:m0_burstcount -> altpll_qsys_pll_slave_translator:uav_burstcount
wire altpll_qsys_pll_slave_agent_rf_source_valid; // altpll_qsys_pll_slave_agent:rf_source_valid -> altpll_qsys_pll_slave_agent_rsp_fifo:in_valid
wire [114:0] altpll_qsys_pll_slave_agent_rf_source_data; // altpll_qsys_pll_slave_agent:rf_source_data -> altpll_qsys_pll_slave_agent_rsp_fifo:in_data
wire altpll_qsys_pll_slave_agent_rf_source_ready; // altpll_qsys_pll_slave_agent_rsp_fifo:in_ready -> altpll_qsys_pll_slave_agent:rf_source_ready
wire altpll_qsys_pll_slave_agent_rf_source_startofpacket; // altpll_qsys_pll_slave_agent:rf_source_startofpacket -> altpll_qsys_pll_slave_agent_rsp_fifo:in_startofpacket
wire altpll_qsys_pll_slave_agent_rf_source_endofpacket; // altpll_qsys_pll_slave_agent:rf_source_endofpacket -> altpll_qsys_pll_slave_agent_rsp_fifo:in_endofpacket
wire altpll_qsys_pll_slave_agent_rsp_fifo_out_valid; // altpll_qsys_pll_slave_agent_rsp_fifo:out_valid -> altpll_qsys_pll_slave_agent:rf_sink_valid
wire [114:0] altpll_qsys_pll_slave_agent_rsp_fifo_out_data; // altpll_qsys_pll_slave_agent_rsp_fifo:out_data -> altpll_qsys_pll_slave_agent:rf_sink_data
wire altpll_qsys_pll_slave_agent_rsp_fifo_out_ready; // altpll_qsys_pll_slave_agent:rf_sink_ready -> altpll_qsys_pll_slave_agent_rsp_fifo:out_ready
wire altpll_qsys_pll_slave_agent_rsp_fifo_out_startofpacket; // altpll_qsys_pll_slave_agent_rsp_fifo:out_startofpacket -> altpll_qsys_pll_slave_agent:rf_sink_startofpacket
wire altpll_qsys_pll_slave_agent_rsp_fifo_out_endofpacket; // altpll_qsys_pll_slave_agent_rsp_fifo:out_endofpacket -> altpll_qsys_pll_slave_agent:rf_sink_endofpacket
wire altpll_qsys_pll_slave_agent_rdata_fifo_src_valid; // altpll_qsys_pll_slave_agent:rdata_fifo_src_valid -> altpll_qsys_pll_slave_agent_rdata_fifo:in_valid
wire [33:0] altpll_qsys_pll_slave_agent_rdata_fifo_src_data; // altpll_qsys_pll_slave_agent:rdata_fifo_src_data -> altpll_qsys_pll_slave_agent_rdata_fifo:in_data
wire altpll_qsys_pll_slave_agent_rdata_fifo_src_ready; // altpll_qsys_pll_slave_agent_rdata_fifo:in_ready -> altpll_qsys_pll_slave_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> altpll_qsys_pll_slave_agent:cp_valid
wire [113:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> altpll_qsys_pll_slave_agent:cp_data
wire cmd_mux_002_src_ready; // altpll_qsys_pll_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> altpll_qsys_pll_slave_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> altpll_qsys_pll_slave_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> altpll_qsys_pll_slave_agent:cp_endofpacket
wire custom_module_avalon_master_agent_cp_valid; // custom_module_avalon_master_agent:cp_valid -> router:sink_valid
wire [113:0] custom_module_avalon_master_agent_cp_data; // custom_module_avalon_master_agent:cp_data -> router:sink_data
wire custom_module_avalon_master_agent_cp_ready; // router:sink_ready -> custom_module_avalon_master_agent:cp_ready
wire custom_module_avalon_master_agent_cp_startofpacket; // custom_module_avalon_master_agent:cp_startofpacket -> router:sink_startofpacket
wire custom_module_avalon_master_agent_cp_endofpacket; // custom_module_avalon_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [113:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [5:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_valid; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:cp_valid -> router_001:sink_valid
wire [113:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_data; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:cp_data -> router_001:sink_data
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_ready; // router_001:sink_ready -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:cp_ready
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_startofpacket; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_endofpacket; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire sgdma_m_read_agent_cp_valid; // sgdma_m_read_agent:cp_valid -> router_002:sink_valid
wire [149:0] sgdma_m_read_agent_cp_data; // sgdma_m_read_agent:cp_data -> router_002:sink_data
wire sgdma_m_read_agent_cp_ready; // router_002:sink_ready -> sgdma_m_read_agent:cp_ready
wire sgdma_m_read_agent_cp_startofpacket; // sgdma_m_read_agent:cp_startofpacket -> router_002:sink_startofpacket
wire sgdma_m_read_agent_cp_endofpacket; // sgdma_m_read_agent:cp_endofpacket -> router_002:sink_endofpacket
wire sgdma_m_write_agent_cp_valid; // sgdma_m_write_agent:cp_valid -> router_003:sink_valid
wire [149:0] sgdma_m_write_agent_cp_data; // sgdma_m_write_agent:cp_data -> router_003:sink_data
wire sgdma_m_write_agent_cp_ready; // router_003:sink_ready -> sgdma_m_write_agent:cp_ready
wire sgdma_m_write_agent_cp_startofpacket; // sgdma_m_write_agent:cp_startofpacket -> router_003:sink_startofpacket
wire sgdma_m_write_agent_cp_endofpacket; // sgdma_m_write_agent:cp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> cmd_demux_003:sink_valid
wire [149:0] router_003_src_data; // router_003:src_data -> cmd_demux_003:sink_data
wire router_003_src_ready; // cmd_demux_003:sink_ready -> router_003:src_ready
wire [5:0] router_003_src_channel; // router_003:src_channel -> cmd_demux_003:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> cmd_demux_003:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> cmd_demux_003:sink_endofpacket
wire sgdma_descriptor_read_agent_cp_valid; // sgdma_descriptor_read_agent:cp_valid -> router_004:sink_valid
wire [113:0] sgdma_descriptor_read_agent_cp_data; // sgdma_descriptor_read_agent:cp_data -> router_004:sink_data
wire sgdma_descriptor_read_agent_cp_ready; // router_004:sink_ready -> sgdma_descriptor_read_agent:cp_ready
wire sgdma_descriptor_read_agent_cp_startofpacket; // sgdma_descriptor_read_agent:cp_startofpacket -> router_004:sink_startofpacket
wire sgdma_descriptor_read_agent_cp_endofpacket; // sgdma_descriptor_read_agent:cp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> cmd_demux_004:sink_valid
wire [113:0] router_004_src_data; // router_004:src_data -> cmd_demux_004:sink_data
wire router_004_src_ready; // cmd_demux_004:sink_ready -> router_004:src_ready
wire [5:0] router_004_src_channel; // router_004:src_channel -> cmd_demux_004:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> cmd_demux_004:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> cmd_demux_004:sink_endofpacket
wire sgdma_descriptor_write_agent_cp_valid; // sgdma_descriptor_write_agent:cp_valid -> router_005:sink_valid
wire [113:0] sgdma_descriptor_write_agent_cp_data; // sgdma_descriptor_write_agent:cp_data -> router_005:sink_data
wire sgdma_descriptor_write_agent_cp_ready; // router_005:sink_ready -> sgdma_descriptor_write_agent:cp_ready
wire sgdma_descriptor_write_agent_cp_startofpacket; // sgdma_descriptor_write_agent:cp_startofpacket -> router_005:sink_startofpacket
wire sgdma_descriptor_write_agent_cp_endofpacket; // sgdma_descriptor_write_agent:cp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> cmd_demux_005:sink_valid
wire [113:0] router_005_src_data; // router_005:src_data -> cmd_demux_005:sink_data
wire router_005_src_ready; // cmd_demux_005:sink_ready -> router_005:src_ready
wire [5:0] router_005_src_channel; // router_005:src_channel -> cmd_demux_005:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> cmd_demux_005:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> cmd_demux_005:sink_endofpacket
wire sdram_s1_agent_rp_valid; // sdram_s1_agent:rp_valid -> router_006:sink_valid
wire [113:0] sdram_s1_agent_rp_data; // sdram_s1_agent:rp_data -> router_006:sink_data
wire sdram_s1_agent_rp_ready; // router_006:sink_ready -> sdram_s1_agent:rp_ready
wire sdram_s1_agent_rp_startofpacket; // sdram_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire sdram_s1_agent_rp_endofpacket; // sdram_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux:sink_valid
wire [113:0] router_006_src_data; // router_006:src_data -> rsp_demux:sink_data
wire router_006_src_ready; // rsp_demux:sink_ready -> router_006:src_ready
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux:sink_endofpacket
wire pcie_ip_txs_agent_rp_valid; // pcie_ip_txs_agent:rp_valid -> router_007:sink_valid
wire [149:0] pcie_ip_txs_agent_rp_data; // pcie_ip_txs_agent:rp_data -> router_007:sink_data
wire pcie_ip_txs_agent_rp_ready; // router_007:sink_ready -> pcie_ip_txs_agent:rp_ready
wire pcie_ip_txs_agent_rp_startofpacket; // pcie_ip_txs_agent:rp_startofpacket -> router_007:sink_startofpacket
wire pcie_ip_txs_agent_rp_endofpacket; // pcie_ip_txs_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_001:sink_valid
wire [149:0] router_007_src_data; // router_007:src_data -> rsp_demux_001:sink_data
wire router_007_src_ready; // rsp_demux_001:sink_ready -> router_007:src_ready
wire [5:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_001:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire altpll_qsys_pll_slave_agent_rp_valid; // altpll_qsys_pll_slave_agent:rp_valid -> router_008:sink_valid
wire [113:0] altpll_qsys_pll_slave_agent_rp_data; // altpll_qsys_pll_slave_agent:rp_data -> router_008:sink_data
wire altpll_qsys_pll_slave_agent_rp_ready; // router_008:sink_ready -> altpll_qsys_pll_slave_agent:rp_ready
wire altpll_qsys_pll_slave_agent_rp_startofpacket; // altpll_qsys_pll_slave_agent:rp_startofpacket -> router_008:sink_startofpacket
wire altpll_qsys_pll_slave_agent_rp_endofpacket; // altpll_qsys_pll_slave_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_002:sink_valid
wire [113:0] router_008_src_data; // router_008:src_data -> rsp_demux_002:sink_data
wire router_008_src_ready; // rsp_demux_002:sink_ready -> router_008:src_ready
wire [5:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_002:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_sink_valid
wire [113:0] router_001_src_data; // router_001:src_data -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_sink_data
wire router_001_src_ready; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_sink_ready -> router_001:src_ready
wire [5:0] router_001_src_channel; // router_001:src_channel -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_sink_endofpacket
wire [113:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_data; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_src_ready
wire [5:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_channel; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_startofpacket; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_endofpacket; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_sink_valid
wire [113:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [5:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_sink_endofpacket
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_valid; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_src_valid -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:rp_valid
wire [113:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_data; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_src_data -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:rp_data
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_ready; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:rp_ready -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_src_ready
wire [5:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_channel; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_src_channel -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:rp_channel
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_startofpacket; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_src_startofpacket -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:rp_startofpacket
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_endofpacket; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:rsp_src_endofpacket -> video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent:rp_endofpacket
wire router_002_src_valid; // router_002:src_valid -> sgdma_m_read_limiter:cmd_sink_valid
wire [149:0] router_002_src_data; // router_002:src_data -> sgdma_m_read_limiter:cmd_sink_data
wire router_002_src_ready; // sgdma_m_read_limiter:cmd_sink_ready -> router_002:src_ready
wire [5:0] router_002_src_channel; // router_002:src_channel -> sgdma_m_read_limiter:cmd_sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> sgdma_m_read_limiter:cmd_sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> sgdma_m_read_limiter:cmd_sink_endofpacket
wire [149:0] sgdma_m_read_limiter_cmd_src_data; // sgdma_m_read_limiter:cmd_src_data -> cmd_demux_002:sink_data
wire sgdma_m_read_limiter_cmd_src_ready; // cmd_demux_002:sink_ready -> sgdma_m_read_limiter:cmd_src_ready
wire [5:0] sgdma_m_read_limiter_cmd_src_channel; // sgdma_m_read_limiter:cmd_src_channel -> cmd_demux_002:sink_channel
wire sgdma_m_read_limiter_cmd_src_startofpacket; // sgdma_m_read_limiter:cmd_src_startofpacket -> cmd_demux_002:sink_startofpacket
wire sgdma_m_read_limiter_cmd_src_endofpacket; // sgdma_m_read_limiter:cmd_src_endofpacket -> cmd_demux_002:sink_endofpacket
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> sgdma_m_read_limiter:rsp_sink_valid
wire [149:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> sgdma_m_read_limiter:rsp_sink_data
wire rsp_mux_002_src_ready; // sgdma_m_read_limiter:rsp_sink_ready -> rsp_mux_002:src_ready
wire [5:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> sgdma_m_read_limiter:rsp_sink_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> sgdma_m_read_limiter:rsp_sink_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> sgdma_m_read_limiter:rsp_sink_endofpacket
wire sgdma_m_read_limiter_rsp_src_valid; // sgdma_m_read_limiter:rsp_src_valid -> sgdma_m_read_agent:rp_valid
wire [149:0] sgdma_m_read_limiter_rsp_src_data; // sgdma_m_read_limiter:rsp_src_data -> sgdma_m_read_agent:rp_data
wire sgdma_m_read_limiter_rsp_src_ready; // sgdma_m_read_agent:rp_ready -> sgdma_m_read_limiter:rsp_src_ready
wire [5:0] sgdma_m_read_limiter_rsp_src_channel; // sgdma_m_read_limiter:rsp_src_channel -> sgdma_m_read_agent:rp_channel
wire sgdma_m_read_limiter_rsp_src_startofpacket; // sgdma_m_read_limiter:rsp_src_startofpacket -> sgdma_m_read_agent:rp_startofpacket
wire sgdma_m_read_limiter_rsp_src_endofpacket; // sgdma_m_read_limiter:rsp_src_endofpacket -> sgdma_m_read_agent:rp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> sdram_s1_burst_adapter:sink0_valid
wire [113:0] cmd_mux_src_data; // cmd_mux:src_data -> sdram_s1_burst_adapter:sink0_data
wire cmd_mux_src_ready; // sdram_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> sdram_s1_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> sdram_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> sdram_s1_burst_adapter:sink0_endofpacket
wire sdram_s1_burst_adapter_source0_valid; // sdram_s1_burst_adapter:source0_valid -> sdram_s1_agent:cp_valid
wire [113:0] sdram_s1_burst_adapter_source0_data; // sdram_s1_burst_adapter:source0_data -> sdram_s1_agent:cp_data
wire sdram_s1_burst_adapter_source0_ready; // sdram_s1_agent:cp_ready -> sdram_s1_burst_adapter:source0_ready
wire [5:0] sdram_s1_burst_adapter_source0_channel; // sdram_s1_burst_adapter:source0_channel -> sdram_s1_agent:cp_channel
wire sdram_s1_burst_adapter_source0_startofpacket; // sdram_s1_burst_adapter:source0_startofpacket -> sdram_s1_agent:cp_startofpacket
wire sdram_s1_burst_adapter_source0_endofpacket; // sdram_s1_burst_adapter:source0_endofpacket -> sdram_s1_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> pcie_ip_txs_burst_adapter:sink0_valid
wire [149:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> pcie_ip_txs_burst_adapter:sink0_data
wire cmd_mux_001_src_ready; // pcie_ip_txs_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> pcie_ip_txs_burst_adapter:sink0_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> pcie_ip_txs_burst_adapter:sink0_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> pcie_ip_txs_burst_adapter:sink0_endofpacket
wire pcie_ip_txs_burst_adapter_source0_valid; // pcie_ip_txs_burst_adapter:source0_valid -> pcie_ip_txs_agent:cp_valid
wire [149:0] pcie_ip_txs_burst_adapter_source0_data; // pcie_ip_txs_burst_adapter:source0_data -> pcie_ip_txs_agent:cp_data
wire pcie_ip_txs_burst_adapter_source0_ready; // pcie_ip_txs_agent:cp_ready -> pcie_ip_txs_burst_adapter:source0_ready
wire [5:0] pcie_ip_txs_burst_adapter_source0_channel; // pcie_ip_txs_burst_adapter:source0_channel -> pcie_ip_txs_agent:cp_channel
wire pcie_ip_txs_burst_adapter_source0_startofpacket; // pcie_ip_txs_burst_adapter:source0_startofpacket -> pcie_ip_txs_agent:cp_startofpacket
wire pcie_ip_txs_burst_adapter_source0_endofpacket; // pcie_ip_txs_burst_adapter:source0_endofpacket -> pcie_ip_txs_agent:cp_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [113:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [5:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_001:sink0_valid
wire [149:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_002_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux_002:src1_ready
wire [5:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_003_src1_valid; // cmd_demux_003:src1_valid -> cmd_mux_001:sink1_valid
wire [149:0] cmd_demux_003_src1_data; // cmd_demux_003:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_003_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_003:src1_ready
wire [5:0] cmd_demux_003_src1_channel; // cmd_demux_003:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_003_src1_startofpacket; // cmd_demux_003:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_003_src1_endofpacket; // cmd_demux_003:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [113:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [5:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux_002:sink1_valid
wire [149:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux_002:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux_002:sink1_ready -> rsp_demux_001:src0_ready
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux_002:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux_002:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux_002:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_003:sink1_valid
wire [149:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_003:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_003:sink1_ready -> rsp_demux_001:src1_ready
wire [5:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_003:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_003:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_003:sink1_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> sgdma_m_read_to_sdram_s1_cmd_width_adapter:in_valid
wire [149:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> sgdma_m_read_to_sdram_s1_cmd_width_adapter:in_data
wire cmd_demux_002_src0_ready; // sgdma_m_read_to_sdram_s1_cmd_width_adapter:in_ready -> cmd_demux_002:src0_ready
wire [5:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> sgdma_m_read_to_sdram_s1_cmd_width_adapter:in_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> sgdma_m_read_to_sdram_s1_cmd_width_adapter:in_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> sgdma_m_read_to_sdram_s1_cmd_width_adapter:in_endofpacket
wire cmd_demux_003_src0_valid; // cmd_demux_003:src0_valid -> sgdma_m_write_to_sdram_s1_cmd_width_adapter:in_valid
wire [149:0] cmd_demux_003_src0_data; // cmd_demux_003:src0_data -> sgdma_m_write_to_sdram_s1_cmd_width_adapter:in_data
wire cmd_demux_003_src0_ready; // sgdma_m_write_to_sdram_s1_cmd_width_adapter:in_ready -> cmd_demux_003:src0_ready
wire [5:0] cmd_demux_003_src0_channel; // cmd_demux_003:src0_channel -> sgdma_m_write_to_sdram_s1_cmd_width_adapter:in_channel
wire cmd_demux_003_src0_startofpacket; // cmd_demux_003:src0_startofpacket -> sgdma_m_write_to_sdram_s1_cmd_width_adapter:in_startofpacket
wire cmd_demux_003_src0_endofpacket; // cmd_demux_003:src0_endofpacket -> sgdma_m_write_to_sdram_s1_cmd_width_adapter:in_endofpacket
wire cmd_demux_004_src0_valid; // cmd_demux_004:src0_valid -> sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:in_valid
wire [113:0] cmd_demux_004_src0_data; // cmd_demux_004:src0_data -> sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:in_data
wire cmd_demux_004_src0_ready; // sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:in_ready -> cmd_demux_004:src0_ready
wire [5:0] cmd_demux_004_src0_channel; // cmd_demux_004:src0_channel -> sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:in_channel
wire cmd_demux_004_src0_startofpacket; // cmd_demux_004:src0_startofpacket -> sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:in_startofpacket
wire cmd_demux_004_src0_endofpacket; // cmd_demux_004:src0_endofpacket -> sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:in_endofpacket
wire sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_valid; // sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:out_valid -> cmd_mux_001:sink2_valid
wire [149:0] sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_data; // sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:out_data -> cmd_mux_001:sink2_data
wire sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_ready; // cmd_mux_001:sink2_ready -> sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:out_ready
wire [5:0] sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_channel; // sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:out_channel -> cmd_mux_001:sink2_channel
wire sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_startofpacket; // sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:out_startofpacket -> cmd_mux_001:sink2_startofpacket
wire sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_endofpacket; // sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter:out_endofpacket -> cmd_mux_001:sink2_endofpacket
wire cmd_demux_005_src0_valid; // cmd_demux_005:src0_valid -> sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:in_valid
wire [113:0] cmd_demux_005_src0_data; // cmd_demux_005:src0_data -> sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:in_data
wire cmd_demux_005_src0_ready; // sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:in_ready -> cmd_demux_005:src0_ready
wire [5:0] cmd_demux_005_src0_channel; // cmd_demux_005:src0_channel -> sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:in_channel
wire cmd_demux_005_src0_startofpacket; // cmd_demux_005:src0_startofpacket -> sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:in_startofpacket
wire cmd_demux_005_src0_endofpacket; // cmd_demux_005:src0_endofpacket -> sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:in_endofpacket
wire sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_valid; // sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:out_valid -> cmd_mux_001:sink3_valid
wire [149:0] sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_data; // sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:out_data -> cmd_mux_001:sink3_data
wire sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_ready; // cmd_mux_001:sink3_ready -> sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:out_ready
wire [5:0] sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_channel; // sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:out_channel -> cmd_mux_001:sink3_channel
wire sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_startofpacket; // sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:out_startofpacket -> cmd_mux_001:sink3_startofpacket
wire sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_endofpacket; // sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter:out_endofpacket -> cmd_mux_001:sink3_endofpacket
wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> sdram_s1_to_sgdma_m_read_rsp_width_adapter:in_valid
wire [113:0] rsp_demux_src2_data; // rsp_demux:src2_data -> sdram_s1_to_sgdma_m_read_rsp_width_adapter:in_data
wire rsp_demux_src2_ready; // sdram_s1_to_sgdma_m_read_rsp_width_adapter:in_ready -> rsp_demux:src2_ready
wire [5:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> sdram_s1_to_sgdma_m_read_rsp_width_adapter:in_channel
wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> sdram_s1_to_sgdma_m_read_rsp_width_adapter:in_startofpacket
wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> sdram_s1_to_sgdma_m_read_rsp_width_adapter:in_endofpacket
wire rsp_demux_src3_valid; // rsp_demux:src3_valid -> sdram_s1_to_sgdma_m_write_rsp_width_adapter:in_valid
wire [113:0] rsp_demux_src3_data; // rsp_demux:src3_data -> sdram_s1_to_sgdma_m_write_rsp_width_adapter:in_data
wire rsp_demux_src3_ready; // sdram_s1_to_sgdma_m_write_rsp_width_adapter:in_ready -> rsp_demux:src3_ready
wire [5:0] rsp_demux_src3_channel; // rsp_demux:src3_channel -> sdram_s1_to_sgdma_m_write_rsp_width_adapter:in_channel
wire rsp_demux_src3_startofpacket; // rsp_demux:src3_startofpacket -> sdram_s1_to_sgdma_m_write_rsp_width_adapter:in_startofpacket
wire rsp_demux_src3_endofpacket; // rsp_demux:src3_endofpacket -> sdram_s1_to_sgdma_m_write_rsp_width_adapter:in_endofpacket
wire rsp_demux_001_src2_valid; // rsp_demux_001:src2_valid -> pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:in_valid
wire [149:0] rsp_demux_001_src2_data; // rsp_demux_001:src2_data -> pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:in_data
wire rsp_demux_001_src2_ready; // pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:in_ready -> rsp_demux_001:src2_ready
wire [5:0] rsp_demux_001_src2_channel; // rsp_demux_001:src2_channel -> pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:in_channel
wire rsp_demux_001_src2_startofpacket; // rsp_demux_001:src2_startofpacket -> pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:in_startofpacket
wire rsp_demux_001_src2_endofpacket; // rsp_demux_001:src2_endofpacket -> pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:in_endofpacket
wire pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_valid; // pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:out_valid -> rsp_mux_004:sink0_valid
wire [113:0] pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_data; // pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:out_data -> rsp_mux_004:sink0_data
wire pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_ready; // rsp_mux_004:sink0_ready -> pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:out_ready
wire [5:0] pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_channel; // pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:out_channel -> rsp_mux_004:sink0_channel
wire pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_startofpacket; // pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:out_startofpacket -> rsp_mux_004:sink0_startofpacket
wire pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_endofpacket; // pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter:out_endofpacket -> rsp_mux_004:sink0_endofpacket
wire rsp_demux_001_src3_valid; // rsp_demux_001:src3_valid -> pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:in_valid
wire [149:0] rsp_demux_001_src3_data; // rsp_demux_001:src3_data -> pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:in_data
wire rsp_demux_001_src3_ready; // pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:in_ready -> rsp_demux_001:src3_ready
wire [5:0] rsp_demux_001_src3_channel; // rsp_demux_001:src3_channel -> pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:in_channel
wire rsp_demux_001_src3_startofpacket; // rsp_demux_001:src3_startofpacket -> pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:in_startofpacket
wire rsp_demux_001_src3_endofpacket; // rsp_demux_001:src3_endofpacket -> pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:in_endofpacket
wire pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_valid; // pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:out_valid -> rsp_mux_005:sink0_valid
wire [113:0] pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_data; // pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:out_data -> rsp_mux_005:sink0_data
wire pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_ready; // rsp_mux_005:sink0_ready -> pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:out_ready
wire [5:0] pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_channel; // pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:out_channel -> rsp_mux_005:sink0_channel
wire pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_startofpacket; // pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:out_startofpacket -> rsp_mux_005:sink0_startofpacket
wire pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_endofpacket; // pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter:out_endofpacket -> rsp_mux_005:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire [113:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire [113:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire [5:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> crosser_001:in_valid
wire [113:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> crosser_001:in_data
wire cmd_demux_001_src1_ready; // crosser_001:in_ready -> cmd_demux_001:src1_ready
wire [5:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> crosser_001:in_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> crosser_001:in_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_002:sink0_valid
wire [113:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_002:sink0_data
wire crosser_001_out_ready; // cmd_mux_002:sink0_ready -> crosser_001:out_ready
wire [5:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_002:sink0_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_002:sink0_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_002:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_002:in_valid
wire [113:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_002:in_data
wire rsp_demux_src0_ready; // crosser_002:in_ready -> rsp_demux:src0_ready
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_002:in_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_002:in_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_002:in_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink0_valid
wire [113:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink0_data
wire crosser_002_out_ready; // rsp_mux:sink0_ready -> crosser_002:out_ready
wire [5:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink0_channel
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink0_startofpacket
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> crosser_003:in_valid
wire [113:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> crosser_003:in_data
wire rsp_demux_002_src0_ready; // crosser_003:in_ready -> rsp_demux_002:src0_ready
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> crosser_003:in_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> crosser_003:in_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> crosser_003:in_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux_001:sink1_valid
wire [113:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux_001:sink1_data
wire crosser_003_out_ready; // rsp_mux_001:sink1_ready -> crosser_003:out_ready
wire [5:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux_001:sink1_channel
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux_001:sink1_startofpacket
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux_001:sink1_endofpacket
wire sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_valid; // sgdma_m_read_to_sdram_s1_cmd_width_adapter:out_valid -> crosser_004:in_valid
wire [113:0] sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_data; // sgdma_m_read_to_sdram_s1_cmd_width_adapter:out_data -> crosser_004:in_data
wire sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_ready; // crosser_004:in_ready -> sgdma_m_read_to_sdram_s1_cmd_width_adapter:out_ready
wire [5:0] sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_channel; // sgdma_m_read_to_sdram_s1_cmd_width_adapter:out_channel -> crosser_004:in_channel
wire sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_startofpacket; // sgdma_m_read_to_sdram_s1_cmd_width_adapter:out_startofpacket -> crosser_004:in_startofpacket
wire sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_endofpacket; // sgdma_m_read_to_sdram_s1_cmd_width_adapter:out_endofpacket -> crosser_004:in_endofpacket
wire crosser_004_out_valid; // crosser_004:out_valid -> cmd_mux:sink2_valid
wire [113:0] crosser_004_out_data; // crosser_004:out_data -> cmd_mux:sink2_data
wire crosser_004_out_ready; // cmd_mux:sink2_ready -> crosser_004:out_ready
wire [5:0] crosser_004_out_channel; // crosser_004:out_channel -> cmd_mux:sink2_channel
wire crosser_004_out_startofpacket; // crosser_004:out_startofpacket -> cmd_mux:sink2_startofpacket
wire crosser_004_out_endofpacket; // crosser_004:out_endofpacket -> cmd_mux:sink2_endofpacket
wire sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_valid; // sgdma_m_write_to_sdram_s1_cmd_width_adapter:out_valid -> crosser_005:in_valid
wire [113:0] sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_data; // sgdma_m_write_to_sdram_s1_cmd_width_adapter:out_data -> crosser_005:in_data
wire sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_ready; // crosser_005:in_ready -> sgdma_m_write_to_sdram_s1_cmd_width_adapter:out_ready
wire [5:0] sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_channel; // sgdma_m_write_to_sdram_s1_cmd_width_adapter:out_channel -> crosser_005:in_channel
wire sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_startofpacket; // sgdma_m_write_to_sdram_s1_cmd_width_adapter:out_startofpacket -> crosser_005:in_startofpacket
wire sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_endofpacket; // sgdma_m_write_to_sdram_s1_cmd_width_adapter:out_endofpacket -> crosser_005:in_endofpacket
wire crosser_005_out_valid; // crosser_005:out_valid -> cmd_mux:sink3_valid
wire [113:0] crosser_005_out_data; // crosser_005:out_data -> cmd_mux:sink3_data
wire crosser_005_out_ready; // cmd_mux:sink3_ready -> crosser_005:out_ready
wire [5:0] crosser_005_out_channel; // crosser_005:out_channel -> cmd_mux:sink3_channel
wire crosser_005_out_startofpacket; // crosser_005:out_startofpacket -> cmd_mux:sink3_startofpacket
wire crosser_005_out_endofpacket; // crosser_005:out_endofpacket -> cmd_mux:sink3_endofpacket
wire sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_valid; // sdram_s1_to_sgdma_m_read_rsp_width_adapter:out_valid -> crosser_006:in_valid
wire [149:0] sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_data; // sdram_s1_to_sgdma_m_read_rsp_width_adapter:out_data -> crosser_006:in_data
wire sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_ready; // crosser_006:in_ready -> sdram_s1_to_sgdma_m_read_rsp_width_adapter:out_ready
wire [5:0] sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_channel; // sdram_s1_to_sgdma_m_read_rsp_width_adapter:out_channel -> crosser_006:in_channel
wire sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_startofpacket; // sdram_s1_to_sgdma_m_read_rsp_width_adapter:out_startofpacket -> crosser_006:in_startofpacket
wire sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_endofpacket; // sdram_s1_to_sgdma_m_read_rsp_width_adapter:out_endofpacket -> crosser_006:in_endofpacket
wire crosser_006_out_valid; // crosser_006:out_valid -> rsp_mux_002:sink0_valid
wire [149:0] crosser_006_out_data; // crosser_006:out_data -> rsp_mux_002:sink0_data
wire crosser_006_out_ready; // rsp_mux_002:sink0_ready -> crosser_006:out_ready
wire [5:0] crosser_006_out_channel; // crosser_006:out_channel -> rsp_mux_002:sink0_channel
wire crosser_006_out_startofpacket; // crosser_006:out_startofpacket -> rsp_mux_002:sink0_startofpacket
wire crosser_006_out_endofpacket; // crosser_006:out_endofpacket -> rsp_mux_002:sink0_endofpacket
wire sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_valid; // sdram_s1_to_sgdma_m_write_rsp_width_adapter:out_valid -> crosser_007:in_valid
wire [149:0] sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_data; // sdram_s1_to_sgdma_m_write_rsp_width_adapter:out_data -> crosser_007:in_data
wire sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_ready; // crosser_007:in_ready -> sdram_s1_to_sgdma_m_write_rsp_width_adapter:out_ready
wire [5:0] sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_channel; // sdram_s1_to_sgdma_m_write_rsp_width_adapter:out_channel -> crosser_007:in_channel
wire sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_startofpacket; // sdram_s1_to_sgdma_m_write_rsp_width_adapter:out_startofpacket -> crosser_007:in_startofpacket
wire sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_endofpacket; // sdram_s1_to_sgdma_m_write_rsp_width_adapter:out_endofpacket -> crosser_007:in_endofpacket
wire crosser_007_out_valid; // crosser_007:out_valid -> rsp_mux_003:sink0_valid
wire [149:0] crosser_007_out_data; // crosser_007:out_data -> rsp_mux_003:sink0_data
wire crosser_007_out_ready; // rsp_mux_003:sink0_ready -> crosser_007:out_ready
wire [5:0] crosser_007_out_channel; // crosser_007:out_channel -> rsp_mux_003:sink0_channel
wire crosser_007_out_startofpacket; // crosser_007:out_startofpacket -> rsp_mux_003:sink0_startofpacket
wire crosser_007_out_endofpacket; // crosser_007:out_endofpacket -> rsp_mux_003:sink0_endofpacket
wire [5:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_valid_data; // video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire [5:0] sgdma_m_read_limiter_cmd_valid_data; // sgdma_m_read_limiter:cmd_src_valid -> cmd_demux_002:sink_valid
wire sdram_s1_agent_rdata_fifo_out_valid; // sdram_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [33:0] sdram_s1_agent_rdata_fifo_out_data; // sdram_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire sdram_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> sdram_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> sdram_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> sdram_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // sdram_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> sdram_s1_agent:rdata_fifo_sink_error
wire pcie_ip_txs_agent_rdata_fifo_out_valid; // pcie_ip_txs_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
wire [65:0] pcie_ip_txs_agent_rdata_fifo_out_data; // pcie_ip_txs_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
wire pcie_ip_txs_agent_rdata_fifo_out_ready; // avalon_st_adapter_001:in_0_ready -> pcie_ip_txs_agent_rdata_fifo:out_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> pcie_ip_txs_agent:rdata_fifo_sink_valid
wire [65:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> pcie_ip_txs_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // pcie_ip_txs_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> pcie_ip_txs_agent:rdata_fifo_sink_error
wire altpll_qsys_pll_slave_agent_rdata_fifo_out_valid; // altpll_qsys_pll_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] altpll_qsys_pll_slave_agent_rdata_fifo_out_data; // altpll_qsys_pll_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_002:in_0_data
wire altpll_qsys_pll_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter_002:in_0_ready -> altpll_qsys_pll_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> altpll_qsys_pll_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> altpll_qsys_pll_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // altpll_qsys_pll_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> altpll_qsys_pll_slave_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (28),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) custom_module_avalon_master_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (custom_module_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (custom_module_avalon_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (custom_module_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (custom_module_avalon_master_translator_avalon_universal_master_0_read), // .read
.uav_write (custom_module_avalon_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (custom_module_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (custom_module_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (custom_module_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (custom_module_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (custom_module_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (custom_module_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (custom_module_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (custom_module_avalon_master_address), // avalon_anti_master_0.address
.av_waitrequest (custom_module_avalon_master_waitrequest), // .waitrequest
.av_read (custom_module_avalon_master_read), // .read
.av_readdata (custom_module_avalon_master_readdata), // .readdata
.av_readdatavalid (custom_module_avalon_master_readdatavalid), // .readdatavalid
.av_write (custom_module_avalon_master_write), // .write
.av_writedata (custom_module_avalon_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_read), // .read
.uav_write (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (video_pixel_buffer_dma_0_avalon_pixel_dma_master_address), // avalon_anti_master_0.address
.av_waitrequest (video_pixel_buffer_dma_0_avalon_pixel_dma_master_waitrequest), // .waitrequest
.av_read (video_pixel_buffer_dma_0_avalon_pixel_dma_master_read), // .read
.av_readdata (video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdata), // .readdata
.av_readdatavalid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdatavalid), // .readdatavalid
.av_lock (video_pixel_buffer_dma_0_avalon_pixel_dma_master_lock), // .lock
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (64),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (7),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) sgdma_m_read_translator (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sgdma_m_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (sgdma_m_read_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (sgdma_m_read_translator_avalon_universal_master_0_read), // .read
.uav_write (sgdma_m_read_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (sgdma_m_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (sgdma_m_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (sgdma_m_read_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (sgdma_m_read_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (sgdma_m_read_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (sgdma_m_read_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (sgdma_m_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (sgdma_m_read_address), // avalon_anti_master_0.address
.av_waitrequest (sgdma_m_read_waitrequest), // .waitrequest
.av_burstcount (sgdma_m_read_burstcount), // .burstcount
.av_read (sgdma_m_read_read), // .read
.av_readdata (sgdma_m_read_readdata), // .readdata
.av_readdatavalid (sgdma_m_read_readdatavalid), // .readdatavalid
.av_byteenable (8'b11111111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (64),
.AV_BURSTCOUNT_W (8),
.AV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (11),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) sgdma_m_write_translator (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sgdma_m_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (sgdma_m_write_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (sgdma_m_write_translator_avalon_universal_master_0_read), // .read
.uav_write (sgdma_m_write_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (sgdma_m_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (sgdma_m_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (sgdma_m_write_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (sgdma_m_write_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (sgdma_m_write_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (sgdma_m_write_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (sgdma_m_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (sgdma_m_write_address), // avalon_anti_master_0.address
.av_waitrequest (sgdma_m_write_waitrequest), // .waitrequest
.av_burstcount (sgdma_m_write_burstcount), // .burstcount
.av_byteenable (sgdma_m_write_byteenable), // .byteenable
.av_write (sgdma_m_write_write), // .write
.av_writedata (sgdma_m_write_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) sgdma_descriptor_read_translator (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sgdma_descriptor_read_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (sgdma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (sgdma_descriptor_read_translator_avalon_universal_master_0_read), // .read
.uav_write (sgdma_descriptor_read_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (sgdma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (sgdma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (sgdma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (sgdma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (sgdma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (sgdma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (sgdma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (sgdma_descriptor_read_address), // avalon_anti_master_0.address
.av_waitrequest (sgdma_descriptor_read_waitrequest), // .waitrequest
.av_read (sgdma_descriptor_read_read), // .read
.av_readdata (sgdma_descriptor_read_readdata), // .readdata
.av_readdatavalid (sgdma_descriptor_read_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) sgdma_descriptor_write_translator (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sgdma_descriptor_write_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (sgdma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (sgdma_descriptor_write_translator_avalon_universal_master_0_read), // .read
.uav_write (sgdma_descriptor_write_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (sgdma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (sgdma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (sgdma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (sgdma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (sgdma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (sgdma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (sgdma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (sgdma_descriptor_write_address), // avalon_anti_master_0.address
.av_waitrequest (sgdma_descriptor_write_waitrequest), // .waitrequest
.av_write (sgdma_descriptor_write_write), // .write
.av_writedata (sgdma_descriptor_write_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_agent_m0_read), // .read
.uav_write (sdram_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_s1_write), // .write
.av_read (sdram_s1_read), // .read
.av_readdata (sdram_s1_readdata), // .readdata
.av_writedata (sdram_s1_writedata), // .writedata
.av_byteenable (sdram_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_s1_waitrequest), // .waitrequest
.av_chipselect (sdram_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (31),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (7),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (10),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pcie_ip_txs_translator (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pcie_ip_txs_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pcie_ip_txs_agent_m0_burstcount), // .burstcount
.uav_read (pcie_ip_txs_agent_m0_read), // .read
.uav_write (pcie_ip_txs_agent_m0_write), // .write
.uav_waitrequest (pcie_ip_txs_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pcie_ip_txs_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pcie_ip_txs_agent_m0_byteenable), // .byteenable
.uav_readdata (pcie_ip_txs_agent_m0_readdata), // .readdata
.uav_writedata (pcie_ip_txs_agent_m0_writedata), // .writedata
.uav_lock (pcie_ip_txs_agent_m0_lock), // .lock
.uav_debugaccess (pcie_ip_txs_agent_m0_debugaccess), // .debugaccess
.av_address (pcie_ip_txs_address), // avalon_anti_slave_0.address
.av_write (pcie_ip_txs_write), // .write
.av_read (pcie_ip_txs_read), // .read
.av_readdata (pcie_ip_txs_readdata), // .readdata
.av_writedata (pcie_ip_txs_writedata), // .writedata
.av_burstcount (pcie_ip_txs_burstcount), // .burstcount
.av_byteenable (pcie_ip_txs_byteenable), // .byteenable
.av_readdatavalid (pcie_ip_txs_readdatavalid), // .readdatavalid
.av_waitrequest (pcie_ip_txs_waitrequest), // .waitrequest
.av_chipselect (pcie_ip_txs_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altpll_qsys_pll_slave_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (altpll_qsys_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altpll_qsys_pll_slave_agent_m0_burstcount), // .burstcount
.uav_read (altpll_qsys_pll_slave_agent_m0_read), // .read
.uav_write (altpll_qsys_pll_slave_agent_m0_write), // .write
.uav_waitrequest (altpll_qsys_pll_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altpll_qsys_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altpll_qsys_pll_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (altpll_qsys_pll_slave_agent_m0_readdata), // .readdata
.uav_writedata (altpll_qsys_pll_slave_agent_m0_writedata), // .writedata
.uav_lock (altpll_qsys_pll_slave_agent_m0_lock), // .lock
.uav_debugaccess (altpll_qsys_pll_slave_agent_m0_debugaccess), // .debugaccess
.av_address (altpll_qsys_pll_slave_address), // avalon_anti_slave_0.address
.av_write (altpll_qsys_pll_slave_write), // .write
.av_read (altpll_qsys_pll_slave_read), // .read
.av_readdata (altpll_qsys_pll_slave_readdata), // .readdata
.av_writedata (altpll_qsys_pll_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (113),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_QOS_H (94),
.PKT_QOS_L (94),
.PKT_DATA_SIDEBAND_H (92),
.PKT_DATA_SIDEBAND_L (92),
.PKT_ADDR_SIDEBAND_H (91),
.PKT_ADDR_SIDEBAND_L (91),
.PKT_BURST_TYPE_H (90),
.PKT_BURST_TYPE_L (89),
.PKT_CACHE_H (108),
.PKT_CACHE_L (105),
.PKT_THREAD_ID_H (101),
.PKT_THREAD_ID_L (101),
.PKT_BURST_SIZE_H (88),
.PKT_BURST_SIZE_L (86),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (93),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURSTWRAP_H (85),
.PKT_BURSTWRAP_L (85),
.PKT_BYTE_CNT_H (84),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (95),
.PKT_DEST_ID_H (100),
.PKT_DEST_ID_L (98),
.ST_DATA_W (114),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) custom_module_avalon_master_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (custom_module_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (custom_module_avalon_master_translator_avalon_universal_master_0_address), // av.address
.av_write (custom_module_avalon_master_translator_avalon_universal_master_0_write), // .write
.av_read (custom_module_avalon_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (custom_module_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (custom_module_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (custom_module_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (custom_module_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (custom_module_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (custom_module_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (custom_module_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (custom_module_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (custom_module_avalon_master_agent_cp_valid), // cp.valid
.cp_data (custom_module_avalon_master_agent_cp_data), // .data
.cp_startofpacket (custom_module_avalon_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (custom_module_avalon_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (custom_module_avalon_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (113),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_QOS_H (94),
.PKT_QOS_L (94),
.PKT_DATA_SIDEBAND_H (92),
.PKT_DATA_SIDEBAND_L (92),
.PKT_ADDR_SIDEBAND_H (91),
.PKT_ADDR_SIDEBAND_L (91),
.PKT_BURST_TYPE_H (90),
.PKT_BURST_TYPE_L (89),
.PKT_CACHE_H (108),
.PKT_CACHE_L (105),
.PKT_THREAD_ID_H (101),
.PKT_THREAD_ID_L (101),
.PKT_BURST_SIZE_H (88),
.PKT_BURST_SIZE_L (86),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (93),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURSTWRAP_H (85),
.PKT_BURSTWRAP_L (85),
.PKT_BYTE_CNT_H (84),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (95),
.PKT_DEST_ID_H (100),
.PKT_DEST_ID_L (98),
.ST_DATA_W (114),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (5),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_address), // av.address
.av_write (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_write), // .write
.av_read (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_valid), // cp.valid
.cp_data (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_data), // .data
.cp_startofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_ready), // .ready
.rp_valid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_valid), // rp.valid
.rp_data (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_data), // .data
.rp_channel (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (149),
.PKT_ORI_BURST_SIZE_L (147),
.PKT_RESPONSE_STATUS_H (146),
.PKT_RESPONSE_STATUS_L (145),
.PKT_QOS_H (130),
.PKT_QOS_L (130),
.PKT_DATA_SIDEBAND_H (128),
.PKT_DATA_SIDEBAND_L (128),
.PKT_ADDR_SIDEBAND_H (127),
.PKT_ADDR_SIDEBAND_L (127),
.PKT_BURST_TYPE_H (126),
.PKT_BURST_TYPE_L (125),
.PKT_CACHE_H (144),
.PKT_CACHE_L (141),
.PKT_THREAD_ID_H (137),
.PKT_THREAD_ID_L (137),
.PKT_BURST_SIZE_H (124),
.PKT_BURST_SIZE_L (122),
.PKT_TRANS_EXCLUSIVE (109),
.PKT_TRANS_LOCK (108),
.PKT_BEGIN_BURST (129),
.PKT_PROTECTION_H (140),
.PKT_PROTECTION_L (138),
.PKT_BURSTWRAP_H (121),
.PKT_BURSTWRAP_L (121),
.PKT_BYTE_CNT_H (120),
.PKT_BYTE_CNT_L (110),
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_POSTED (105),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (133),
.PKT_SRC_ID_L (131),
.PKT_DEST_ID_H (136),
.PKT_DEST_ID_L (134),
.ST_DATA_W (150),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (7),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (3),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sgdma_m_read_agent (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (sgdma_m_read_translator_avalon_universal_master_0_address), // av.address
.av_write (sgdma_m_read_translator_avalon_universal_master_0_write), // .write
.av_read (sgdma_m_read_translator_avalon_universal_master_0_read), // .read
.av_writedata (sgdma_m_read_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (sgdma_m_read_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (sgdma_m_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (sgdma_m_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (sgdma_m_read_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (sgdma_m_read_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (sgdma_m_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (sgdma_m_read_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (sgdma_m_read_agent_cp_valid), // cp.valid
.cp_data (sgdma_m_read_agent_cp_data), // .data
.cp_startofpacket (sgdma_m_read_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (sgdma_m_read_agent_cp_endofpacket), // .endofpacket
.cp_ready (sgdma_m_read_agent_cp_ready), // .ready
.rp_valid (sgdma_m_read_limiter_rsp_src_valid), // rp.valid
.rp_data (sgdma_m_read_limiter_rsp_src_data), // .data
.rp_channel (sgdma_m_read_limiter_rsp_src_channel), // .channel
.rp_startofpacket (sgdma_m_read_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (sgdma_m_read_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (sgdma_m_read_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (149),
.PKT_ORI_BURST_SIZE_L (147),
.PKT_RESPONSE_STATUS_H (146),
.PKT_RESPONSE_STATUS_L (145),
.PKT_QOS_H (130),
.PKT_QOS_L (130),
.PKT_DATA_SIDEBAND_H (128),
.PKT_DATA_SIDEBAND_L (128),
.PKT_ADDR_SIDEBAND_H (127),
.PKT_ADDR_SIDEBAND_L (127),
.PKT_BURST_TYPE_H (126),
.PKT_BURST_TYPE_L (125),
.PKT_CACHE_H (144),
.PKT_CACHE_L (141),
.PKT_THREAD_ID_H (137),
.PKT_THREAD_ID_L (137),
.PKT_BURST_SIZE_H (124),
.PKT_BURST_SIZE_L (122),
.PKT_TRANS_EXCLUSIVE (109),
.PKT_TRANS_LOCK (108),
.PKT_BEGIN_BURST (129),
.PKT_PROTECTION_H (140),
.PKT_PROTECTION_L (138),
.PKT_BURSTWRAP_H (121),
.PKT_BURSTWRAP_L (121),
.PKT_BYTE_CNT_H (120),
.PKT_BYTE_CNT_L (110),
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_POSTED (105),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (133),
.PKT_SRC_ID_L (131),
.PKT_DEST_ID_H (136),
.PKT_DEST_ID_L (134),
.ST_DATA_W (150),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (11),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (4),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sgdma_m_write_agent (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (sgdma_m_write_translator_avalon_universal_master_0_address), // av.address
.av_write (sgdma_m_write_translator_avalon_universal_master_0_write), // .write
.av_read (sgdma_m_write_translator_avalon_universal_master_0_read), // .read
.av_writedata (sgdma_m_write_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (sgdma_m_write_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (sgdma_m_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (sgdma_m_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (sgdma_m_write_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (sgdma_m_write_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (sgdma_m_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (sgdma_m_write_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (sgdma_m_write_agent_cp_valid), // cp.valid
.cp_data (sgdma_m_write_agent_cp_data), // .data
.cp_startofpacket (sgdma_m_write_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (sgdma_m_write_agent_cp_endofpacket), // .endofpacket
.cp_ready (sgdma_m_write_agent_cp_ready), // .ready
.rp_valid (rsp_mux_003_src_valid), // rp.valid
.rp_data (rsp_mux_003_src_data), // .data
.rp_channel (rsp_mux_003_src_channel), // .channel
.rp_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_003_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (113),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_QOS_H (94),
.PKT_QOS_L (94),
.PKT_DATA_SIDEBAND_H (92),
.PKT_DATA_SIDEBAND_L (92),
.PKT_ADDR_SIDEBAND_H (91),
.PKT_ADDR_SIDEBAND_L (91),
.PKT_BURST_TYPE_H (90),
.PKT_BURST_TYPE_L (89),
.PKT_CACHE_H (108),
.PKT_CACHE_L (105),
.PKT_THREAD_ID_H (101),
.PKT_THREAD_ID_L (101),
.PKT_BURST_SIZE_H (88),
.PKT_BURST_SIZE_L (86),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (93),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURSTWRAP_H (85),
.PKT_BURSTWRAP_L (85),
.PKT_BYTE_CNT_H (84),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (95),
.PKT_DEST_ID_H (100),
.PKT_DEST_ID_L (98),
.ST_DATA_W (114),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (1),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sgdma_descriptor_read_agent (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (sgdma_descriptor_read_translator_avalon_universal_master_0_address), // av.address
.av_write (sgdma_descriptor_read_translator_avalon_universal_master_0_write), // .write
.av_read (sgdma_descriptor_read_translator_avalon_universal_master_0_read), // .read
.av_writedata (sgdma_descriptor_read_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (sgdma_descriptor_read_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (sgdma_descriptor_read_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (sgdma_descriptor_read_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (sgdma_descriptor_read_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (sgdma_descriptor_read_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (sgdma_descriptor_read_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (sgdma_descriptor_read_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (sgdma_descriptor_read_agent_cp_valid), // cp.valid
.cp_data (sgdma_descriptor_read_agent_cp_data), // .data
.cp_startofpacket (sgdma_descriptor_read_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (sgdma_descriptor_read_agent_cp_endofpacket), // .endofpacket
.cp_ready (sgdma_descriptor_read_agent_cp_ready), // .ready
.rp_valid (rsp_mux_004_src_valid), // rp.valid
.rp_data (rsp_mux_004_src_data), // .data
.rp_channel (rsp_mux_004_src_channel), // .channel
.rp_startofpacket (rsp_mux_004_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_004_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_004_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (113),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_QOS_H (94),
.PKT_QOS_L (94),
.PKT_DATA_SIDEBAND_H (92),
.PKT_DATA_SIDEBAND_L (92),
.PKT_ADDR_SIDEBAND_H (91),
.PKT_ADDR_SIDEBAND_L (91),
.PKT_BURST_TYPE_H (90),
.PKT_BURST_TYPE_L (89),
.PKT_CACHE_H (108),
.PKT_CACHE_L (105),
.PKT_THREAD_ID_H (101),
.PKT_THREAD_ID_L (101),
.PKT_BURST_SIZE_H (88),
.PKT_BURST_SIZE_L (86),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (93),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURSTWRAP_H (85),
.PKT_BURSTWRAP_L (85),
.PKT_BYTE_CNT_H (84),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (95),
.PKT_DEST_ID_H (100),
.PKT_DEST_ID_L (98),
.ST_DATA_W (114),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (2),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sgdma_descriptor_write_agent (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (sgdma_descriptor_write_translator_avalon_universal_master_0_address), // av.address
.av_write (sgdma_descriptor_write_translator_avalon_universal_master_0_write), // .write
.av_read (sgdma_descriptor_write_translator_avalon_universal_master_0_read), // .read
.av_writedata (sgdma_descriptor_write_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (sgdma_descriptor_write_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (sgdma_descriptor_write_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (sgdma_descriptor_write_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (sgdma_descriptor_write_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (sgdma_descriptor_write_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (sgdma_descriptor_write_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (sgdma_descriptor_write_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (sgdma_descriptor_write_agent_cp_valid), // cp.valid
.cp_data (sgdma_descriptor_write_agent_cp_data), // .data
.cp_startofpacket (sgdma_descriptor_write_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (sgdma_descriptor_write_agent_cp_endofpacket), // .endofpacket
.cp_ready (sgdma_descriptor_write_agent_cp_ready), // .ready
.rp_valid (rsp_mux_005_src_valid), // rp.valid
.rp_data (rsp_mux_005_src_data), // .data
.rp_channel (rsp_mux_005_src_channel), // .channel
.rp_startofpacket (rsp_mux_005_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_005_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_005_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (113),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (88),
.PKT_BURST_SIZE_L (86),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (93),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURSTWRAP_H (85),
.PKT_BURSTWRAP_L (85),
.PKT_BYTE_CNT_H (84),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (95),
.PKT_DEST_ID_H (100),
.PKT_DEST_ID_L (98),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sdram_s1_agent (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_agent_rp_ready), // .ready
.rp_valid (sdram_s1_agent_rp_valid), // .valid
.rp_data (sdram_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sdram_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sdram_s1_burst_adapter_source0_valid), // .valid
.cp_data (sdram_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rsp_fifo (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rf_source_data), // in.data
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rdata_fifo (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (149),
.PKT_ORI_BURST_SIZE_L (147),
.PKT_RESPONSE_STATUS_H (146),
.PKT_RESPONSE_STATUS_L (145),
.PKT_BURST_SIZE_H (124),
.PKT_BURST_SIZE_L (122),
.PKT_TRANS_LOCK (108),
.PKT_BEGIN_BURST (129),
.PKT_PROTECTION_H (140),
.PKT_PROTECTION_L (138),
.PKT_BURSTWRAP_H (121),
.PKT_BURSTWRAP_L (121),
.PKT_BYTE_CNT_H (120),
.PKT_BYTE_CNT_L (110),
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_POSTED (105),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (133),
.PKT_SRC_ID_L (131),
.PKT_DEST_ID_H (136),
.PKT_DEST_ID_L (134),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (150),
.AVS_BURSTCOUNT_W (10),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) pcie_ip_txs_agent (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pcie_ip_txs_agent_m0_address), // m0.address
.m0_burstcount (pcie_ip_txs_agent_m0_burstcount), // .burstcount
.m0_byteenable (pcie_ip_txs_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pcie_ip_txs_agent_m0_debugaccess), // .debugaccess
.m0_lock (pcie_ip_txs_agent_m0_lock), // .lock
.m0_readdata (pcie_ip_txs_agent_m0_readdata), // .readdata
.m0_readdatavalid (pcie_ip_txs_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pcie_ip_txs_agent_m0_read), // .read
.m0_waitrequest (pcie_ip_txs_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pcie_ip_txs_agent_m0_writedata), // .writedata
.m0_write (pcie_ip_txs_agent_m0_write), // .write
.rp_endofpacket (pcie_ip_txs_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pcie_ip_txs_agent_rp_ready), // .ready
.rp_valid (pcie_ip_txs_agent_rp_valid), // .valid
.rp_data (pcie_ip_txs_agent_rp_data), // .data
.rp_startofpacket (pcie_ip_txs_agent_rp_startofpacket), // .startofpacket
.cp_ready (pcie_ip_txs_burst_adapter_source0_ready), // cp.ready
.cp_valid (pcie_ip_txs_burst_adapter_source0_valid), // .valid
.cp_data (pcie_ip_txs_burst_adapter_source0_data), // .data
.cp_startofpacket (pcie_ip_txs_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (pcie_ip_txs_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (pcie_ip_txs_burst_adapter_source0_channel), // .channel
.rf_sink_ready (pcie_ip_txs_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pcie_ip_txs_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pcie_ip_txs_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pcie_ip_txs_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pcie_ip_txs_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pcie_ip_txs_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pcie_ip_txs_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pcie_ip_txs_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pcie_ip_txs_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pcie_ip_txs_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (pcie_ip_txs_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pcie_ip_txs_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pcie_ip_txs_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (151),
.FIFO_DEPTH (9),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pcie_ip_txs_agent_rsp_fifo (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pcie_ip_txs_agent_rf_source_data), // in.data
.in_valid (pcie_ip_txs_agent_rf_source_valid), // .valid
.in_ready (pcie_ip_txs_agent_rf_source_ready), // .ready
.in_startofpacket (pcie_ip_txs_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pcie_ip_txs_agent_rf_source_endofpacket), // .endofpacket
.out_data (pcie_ip_txs_agent_rsp_fifo_out_data), // out.data
.out_valid (pcie_ip_txs_agent_rsp_fifo_out_valid), // .valid
.out_ready (pcie_ip_txs_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pcie_ip_txs_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pcie_ip_txs_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (1024),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pcie_ip_txs_agent_rdata_fifo (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pcie_ip_txs_agent_rdata_fifo_src_data), // in.data
.in_valid (pcie_ip_txs_agent_rdata_fifo_src_valid), // .valid
.in_ready (pcie_ip_txs_agent_rdata_fifo_src_ready), // .ready
.out_data (pcie_ip_txs_agent_rdata_fifo_out_data), // out.data
.out_valid (pcie_ip_txs_agent_rdata_fifo_out_valid), // .valid
.out_ready (pcie_ip_txs_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (113),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (88),
.PKT_BURST_SIZE_L (86),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (93),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURSTWRAP_H (85),
.PKT_BURSTWRAP_L (85),
.PKT_BYTE_CNT_H (84),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (95),
.PKT_DEST_ID_H (100),
.PKT_DEST_ID_L (98),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) altpll_qsys_pll_slave_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (altpll_qsys_pll_slave_agent_m0_address), // m0.address
.m0_burstcount (altpll_qsys_pll_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (altpll_qsys_pll_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altpll_qsys_pll_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (altpll_qsys_pll_slave_agent_m0_lock), // .lock
.m0_readdata (altpll_qsys_pll_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (altpll_qsys_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altpll_qsys_pll_slave_agent_m0_read), // .read
.m0_waitrequest (altpll_qsys_pll_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altpll_qsys_pll_slave_agent_m0_writedata), // .writedata
.m0_write (altpll_qsys_pll_slave_agent_m0_write), // .write
.rp_endofpacket (altpll_qsys_pll_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altpll_qsys_pll_slave_agent_rp_ready), // .ready
.rp_valid (altpll_qsys_pll_slave_agent_rp_valid), // .valid
.rp_data (altpll_qsys_pll_slave_agent_rp_data), // .data
.rp_startofpacket (altpll_qsys_pll_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (altpll_qsys_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altpll_qsys_pll_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altpll_qsys_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altpll_qsys_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altpll_qsys_pll_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altpll_qsys_pll_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altpll_qsys_pll_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altpll_qsys_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altpll_qsys_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altpll_qsys_pll_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (altpll_qsys_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altpll_qsys_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altpll_qsys_pll_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_qsys_pll_slave_agent_rsp_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_qsys_pll_slave_agent_rf_source_data), // in.data
.in_valid (altpll_qsys_pll_slave_agent_rf_source_valid), // .valid
.in_ready (altpll_qsys_pll_slave_agent_rf_source_ready), // .ready
.in_startofpacket (altpll_qsys_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altpll_qsys_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (altpll_qsys_pll_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (altpll_qsys_pll_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (altpll_qsys_pll_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altpll_qsys_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altpll_qsys_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_qsys_pll_slave_agent_rdata_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_qsys_pll_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (altpll_qsys_pll_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (altpll_qsys_pll_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (altpll_qsys_pll_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (altpll_qsys_pll_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (altpll_qsys_pll_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
amm_master_qsys_with_pcie_mm_interconnect_0_router router (
.sink_ready (custom_module_avalon_master_agent_cp_ready), // sink.ready
.sink_valid (custom_module_avalon_master_agent_cp_valid), // .valid
.sink_data (custom_module_avalon_master_agent_cp_data), // .data
.sink_startofpacket (custom_module_avalon_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (custom_module_avalon_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (custom_module_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_router_001 router_001 (
.sink_ready (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_ready), // sink.ready
.sink_valid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_valid), // .valid
.sink_data (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_data), // .data
.sink_startofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_router_002 router_002 (
.sink_ready (sgdma_m_read_agent_cp_ready), // sink.ready
.sink_valid (sgdma_m_read_agent_cp_valid), // .valid
.sink_data (sgdma_m_read_agent_cp_data), // .data
.sink_startofpacket (sgdma_m_read_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (sgdma_m_read_agent_cp_endofpacket), // .endofpacket
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_router_002 router_003 (
.sink_ready (sgdma_m_write_agent_cp_ready), // sink.ready
.sink_valid (sgdma_m_write_agent_cp_valid), // .valid
.sink_data (sgdma_m_write_agent_cp_data), // .data
.sink_startofpacket (sgdma_m_write_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (sgdma_m_write_agent_cp_endofpacket), // .endofpacket
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_router_004 router_004 (
.sink_ready (sgdma_descriptor_read_agent_cp_ready), // sink.ready
.sink_valid (sgdma_descriptor_read_agent_cp_valid), // .valid
.sink_data (sgdma_descriptor_read_agent_cp_data), // .data
.sink_startofpacket (sgdma_descriptor_read_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (sgdma_descriptor_read_agent_cp_endofpacket), // .endofpacket
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_router_004 router_005 (
.sink_ready (sgdma_descriptor_write_agent_cp_ready), // sink.ready
.sink_valid (sgdma_descriptor_write_agent_cp_valid), // .valid
.sink_data (sgdma_descriptor_write_agent_cp_data), // .data
.sink_startofpacket (sgdma_descriptor_write_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (sgdma_descriptor_write_agent_cp_endofpacket), // .endofpacket
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_router_006 router_006 (
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_agent_rp_valid), // .valid
.sink_data (sdram_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_router_007 router_007 (
.sink_ready (pcie_ip_txs_agent_rp_ready), // sink.ready
.sink_valid (pcie_ip_txs_agent_rp_valid), // .valid
.sink_data (pcie_ip_txs_agent_rp_data), // .data
.sink_startofpacket (pcie_ip_txs_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pcie_ip_txs_agent_rp_endofpacket), // .endofpacket
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_router_008 router_008 (
.sink_ready (altpll_qsys_pll_slave_agent_rp_ready), // sink.ready
.sink_valid (altpll_qsys_pll_slave_agent_rp_valid), // .valid
.sink_data (altpll_qsys_pll_slave_agent_rp_data), // .data
.sink_startofpacket (altpll_qsys_pll_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altpll_qsys_pll_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (100),
.PKT_DEST_ID_L (98),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (95),
.PKT_BYTE_CNT_H (84),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_data), // .data
.cmd_src_channel (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_data), // .data
.rsp_src_channel (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (136),
.PKT_DEST_ID_L (134),
.PKT_SRC_ID_H (133),
.PKT_SRC_ID_L (131),
.PKT_BYTE_CNT_H (120),
.PKT_BYTE_CNT_L (110),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_TRANS_POSTED (105),
.PKT_TRANS_WRITE (106),
.MAX_OUTSTANDING_RESPONSES (13),
.PIPELINED (0),
.ST_DATA_W (150),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) sgdma_m_read_limiter (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_002_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_002_src_valid), // .valid
.cmd_sink_data (router_002_src_data), // .data
.cmd_sink_channel (router_002_src_channel), // .channel
.cmd_sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.cmd_src_ready (sgdma_m_read_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (sgdma_m_read_limiter_cmd_src_data), // .data
.cmd_src_channel (sgdma_m_read_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (sgdma_m_read_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (sgdma_m_read_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_002_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_002_src_valid), // .valid
.rsp_sink_channel (rsp_mux_002_src_channel), // .channel
.rsp_sink_data (rsp_mux_002_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rsp_src_ready (sgdma_m_read_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (sgdma_m_read_limiter_rsp_src_valid), // .valid
.rsp_src_data (sgdma_m_read_limiter_rsp_src_data), // .data
.rsp_src_channel (sgdma_m_read_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (sgdma_m_read_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (sgdma_m_read_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (sgdma_m_read_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (93),
.PKT_BYTE_CNT_H (84),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (88),
.PKT_BURST_SIZE_L (86),
.PKT_BURST_TYPE_H (90),
.PKT_BURST_TYPE_L (89),
.PKT_BURSTWRAP_H (85),
.PKT_BURSTWRAP_L (85),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (6),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (85),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (1),
.BURSTWRAP_CONST_VALUE (1),
.ADAPTER_VERSION ("13.1")
) sdram_s1_burst_adapter (
.clk (altpll_qsys_c1_clk), // cr0.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (sdram_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sdram_s1_burst_adapter_source0_data), // .data
.source0_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sdram_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_BEGIN_BURST (129),
.PKT_BYTE_CNT_H (120),
.PKT_BYTE_CNT_L (110),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_BURST_SIZE_H (124),
.PKT_BURST_SIZE_L (122),
.PKT_BURST_TYPE_H (126),
.PKT_BURST_TYPE_L (125),
.PKT_BURSTWRAP_H (121),
.PKT_BURSTWRAP_L (121),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (150),
.ST_CHANNEL_W (6),
.OUT_BYTE_CNT_H (119),
.OUT_BURSTWRAP_H (121),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (1),
.BURSTWRAP_CONST_VALUE (1),
.ADAPTER_VERSION ("13.1")
) pcie_ip_txs_burst_adapter (
.clk (pcie_ip_pcie_core_clk_clk), // cr0.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (pcie_ip_txs_burst_adapter_source0_valid), // source0.valid
.source0_data (pcie_ip_txs_burst_adapter_source0_data), // .data
.source0_channel (pcie_ip_txs_burst_adapter_source0_channel), // .channel
.source0_startofpacket (pcie_ip_txs_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (pcie_ip_txs_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (pcie_ip_txs_burst_adapter_source0_ready) // .ready
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_50_clk_clk), // clk.clk
.reset (custom_module_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_channel), // .channel
.sink_data (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_data), // .data
.sink_startofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sgdma_m_read_limiter_cmd_src_ready), // sink.ready
.sink_channel (sgdma_m_read_limiter_cmd_src_channel), // .channel
.sink_data (sgdma_m_read_limiter_cmd_src_data), // .data
.sink_startofpacket (sgdma_m_read_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (sgdma_m_read_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (sgdma_m_read_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_demux_003 cmd_demux_003 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (cmd_demux_003_src0_ready), // src0.ready
.src0_valid (cmd_demux_003_src0_valid), // .valid
.src0_data (cmd_demux_003_src0_data), // .data
.src0_channel (cmd_demux_003_src0_channel), // .channel
.src0_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_003_src1_ready), // src1.ready
.src1_valid (cmd_demux_003_src1_valid), // .valid
.src1_data (cmd_demux_003_src1_data), // .data
.src1_channel (cmd_demux_003_src1_channel), // .channel
.src1_startofpacket (cmd_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_003_src1_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_demux_004 cmd_demux_004 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (cmd_demux_004_src0_ready), // src0.ready
.src0_valid (cmd_demux_004_src0_valid), // .valid
.src0_data (cmd_demux_004_src0_data), // .data
.src0_channel (cmd_demux_004_src0_channel), // .channel
.src0_startofpacket (cmd_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_004_src0_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_demux_004 cmd_demux_005 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (cmd_demux_005_src0_ready), // src0.ready
.src0_valid (cmd_demux_005_src0_valid), // .valid
.src0_data (cmd_demux_005_src0_data), // .data
.src0_channel (cmd_demux_005_src0_channel), // .channel
.src0_startofpacket (cmd_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_005_src0_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_mux cmd_mux (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (crosser_004_out_ready), // sink2.ready
.sink2_valid (crosser_004_out_valid), // .valid
.sink2_channel (crosser_004_out_channel), // .channel
.sink2_data (crosser_004_out_data), // .data
.sink2_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.sink2_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.sink3_ready (crosser_005_out_ready), // sink3.ready
.sink3_valid (crosser_005_out_valid), // .valid
.sink3_channel (crosser_005_out_channel), // .channel
.sink3_data (crosser_005_out_data), // .data
.sink3_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.sink3_endofpacket (crosser_005_out_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src1_valid), // .valid
.sink0_channel (cmd_demux_002_src1_channel), // .channel
.sink0_data (cmd_demux_002_src1_data), // .data
.sink0_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_003_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_003_src1_valid), // .valid
.sink1_channel (cmd_demux_003_src1_channel), // .channel
.sink1_data (cmd_demux_003_src1_data), // .data
.sink1_startofpacket (cmd_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_003_src1_endofpacket), // .endofpacket
.sink2_ready (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_ready), // sink2.ready
.sink2_valid (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_valid), // .valid
.sink2_channel (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_channel), // .channel
.sink2_data (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_data), // .data
.sink2_startofpacket (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink2_endofpacket (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink3_ready (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_ready), // sink3.ready
.sink3_valid (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_valid), // .valid
.sink3_channel (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_channel), // .channel
.sink3_data (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_data), // .data
.sink3_startofpacket (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink3_endofpacket (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (clk_50_clk_clk), // clk.clk
.reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_rsp_demux rsp_demux (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_src2_ready), // src2.ready
.src2_valid (rsp_demux_src2_valid), // .valid
.src2_data (rsp_demux_src2_data), // .data
.src2_channel (rsp_demux_src2_channel), // .channel
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.src3_ready (rsp_demux_src3_ready), // src3.ready
.src3_valid (rsp_demux_src3_valid), // .valid
.src3_data (rsp_demux_src3_data), // .data
.src3_channel (rsp_demux_src3_channel), // .channel
.src3_startofpacket (rsp_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (rsp_demux_src3_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_001_src2_ready), // src2.ready
.src2_valid (rsp_demux_001_src2_valid), // .valid
.src2_data (rsp_demux_001_src2_data), // .data
.src2_channel (rsp_demux_001_src2_channel), // .channel
.src2_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (rsp_demux_001_src3_ready), // src3.ready
.src3_valid (rsp_demux_001_src3_valid), // .valid
.src3_data (rsp_demux_001_src3_data), // .data
.src3_channel (rsp_demux_001_src3_channel), // .channel
.src3_startofpacket (rsp_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (rsp_demux_001_src3_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_cmd_demux rsp_demux_002 (
.clk (clk_50_clk_clk), // clk.clk
.reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_50_clk_clk), // clk.clk
.reset (custom_module_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (crosser_006_out_ready), // sink0.ready
.sink0_valid (crosser_006_out_valid), // .valid
.sink0_channel (crosser_006_out_channel), // .channel
.sink0_data (crosser_006_out_data), // .data
.sink0_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_006_out_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_rsp_mux_002 rsp_mux_003 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_003_src_ready), // src.ready
.src_valid (rsp_mux_003_src_valid), // .valid
.src_data (rsp_mux_003_src_data), // .data
.src_channel (rsp_mux_003_src_channel), // .channel
.src_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (crosser_007_out_ready), // sink0.ready
.sink0_valid (crosser_007_out_valid), // .valid
.sink0_channel (crosser_007_out_channel), // .channel
.sink0_data (crosser_007_out_data), // .data
.sink0_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_007_out_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_rsp_mux rsp_mux_004 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_004_src_ready), // src.ready
.src_valid (rsp_mux_004_src_valid), // .valid
.src_data (rsp_mux_004_src_data), // .data
.src_channel (rsp_mux_004_src_channel), // .channel
.src_startofpacket (rsp_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_ready), // sink0.ready
.sink0_valid (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_valid), // .valid
.sink0_channel (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_channel), // .channel
.sink0_data (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_data), // .data
.sink0_startofpacket (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_endofpacket) // .endofpacket
);
amm_master_qsys_with_pcie_mm_interconnect_0_rsp_mux rsp_mux_005 (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_005_src_ready), // src.ready
.src_valid (rsp_mux_005_src_valid), // .valid
.src_data (rsp_mux_005_src_data), // .data
.src_channel (rsp_mux_005_src_channel), // .channel
.src_startofpacket (rsp_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_ready), // sink0.ready
.sink0_valid (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_valid), // .valid
.sink0_channel (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_channel), // .channel
.sink0_data (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_data), // .data
.sink0_startofpacket (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (103),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (120),
.IN_PKT_BYTE_CNT_L (110),
.IN_PKT_TRANS_COMPRESSED_READ (104),
.IN_PKT_TRANS_WRITE (106),
.IN_PKT_BURSTWRAP_H (121),
.IN_PKT_BURSTWRAP_L (121),
.IN_PKT_BURST_SIZE_H (124),
.IN_PKT_BURST_SIZE_L (122),
.IN_PKT_RESPONSE_STATUS_H (146),
.IN_PKT_RESPONSE_STATUS_L (145),
.IN_PKT_TRANS_EXCLUSIVE (109),
.IN_PKT_BURST_TYPE_H (126),
.IN_PKT_BURST_TYPE_L (125),
.IN_PKT_ORI_BURST_SIZE_L (147),
.IN_PKT_ORI_BURST_SIZE_H (149),
.IN_ST_DATA_W (150),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (84),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (88),
.OUT_PKT_BURST_SIZE_L (86),
.OUT_PKT_RESPONSE_STATUS_H (110),
.OUT_PKT_RESPONSE_STATUS_L (109),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (90),
.OUT_PKT_BURST_TYPE_L (89),
.OUT_PKT_ORI_BURST_SIZE_L (111),
.OUT_PKT_ORI_BURST_SIZE_H (113),
.OUT_ST_DATA_W (114),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sgdma_m_read_to_sdram_s1_cmd_width_adapter (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_002_src0_valid), // sink.valid
.in_channel (cmd_demux_002_src0_channel), // .channel
.in_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.in_ready (cmd_demux_002_src0_ready), // .ready
.in_data (cmd_demux_002_src0_data), // .data
.out_endofpacket (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_data), // .data
.out_channel (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (103),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (120),
.IN_PKT_BYTE_CNT_L (110),
.IN_PKT_TRANS_COMPRESSED_READ (104),
.IN_PKT_TRANS_WRITE (106),
.IN_PKT_BURSTWRAP_H (121),
.IN_PKT_BURSTWRAP_L (121),
.IN_PKT_BURST_SIZE_H (124),
.IN_PKT_BURST_SIZE_L (122),
.IN_PKT_RESPONSE_STATUS_H (146),
.IN_PKT_RESPONSE_STATUS_L (145),
.IN_PKT_TRANS_EXCLUSIVE (109),
.IN_PKT_BURST_TYPE_H (126),
.IN_PKT_BURST_TYPE_L (125),
.IN_PKT_ORI_BURST_SIZE_L (147),
.IN_PKT_ORI_BURST_SIZE_H (149),
.IN_ST_DATA_W (150),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (84),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (88),
.OUT_PKT_BURST_SIZE_L (86),
.OUT_PKT_RESPONSE_STATUS_H (110),
.OUT_PKT_RESPONSE_STATUS_L (109),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (90),
.OUT_PKT_BURST_TYPE_L (89),
.OUT_PKT_ORI_BURST_SIZE_L (111),
.OUT_PKT_ORI_BURST_SIZE_H (113),
.OUT_ST_DATA_W (114),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sgdma_m_write_to_sdram_s1_cmd_width_adapter (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_003_src0_valid), // sink.valid
.in_channel (cmd_demux_003_src0_channel), // .channel
.in_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_003_src0_endofpacket), // .endofpacket
.in_ready (cmd_demux_003_src0_ready), // .ready
.in_data (cmd_demux_003_src0_data), // .data
.out_endofpacket (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_data), // .data
.out_channel (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (84),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_TRANS_WRITE (70),
.IN_PKT_BURSTWRAP_H (85),
.IN_PKT_BURSTWRAP_L (85),
.IN_PKT_BURST_SIZE_H (88),
.IN_PKT_BURST_SIZE_L (86),
.IN_PKT_RESPONSE_STATUS_H (110),
.IN_PKT_RESPONSE_STATUS_L (109),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (90),
.IN_PKT_BURST_TYPE_L (89),
.IN_PKT_ORI_BURST_SIZE_L (111),
.IN_PKT_ORI_BURST_SIZE_H (113),
.IN_ST_DATA_W (114),
.OUT_PKT_ADDR_H (103),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (120),
.OUT_PKT_BYTE_CNT_L (110),
.OUT_PKT_TRANS_COMPRESSED_READ (104),
.OUT_PKT_BURST_SIZE_H (124),
.OUT_PKT_BURST_SIZE_L (122),
.OUT_PKT_RESPONSE_STATUS_H (146),
.OUT_PKT_RESPONSE_STATUS_L (145),
.OUT_PKT_TRANS_EXCLUSIVE (109),
.OUT_PKT_BURST_TYPE_H (126),
.OUT_PKT_BURST_TYPE_L (125),
.OUT_PKT_ORI_BURST_SIZE_L (147),
.OUT_PKT_ORI_BURST_SIZE_H (149),
.OUT_ST_DATA_W (150),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_004_src0_valid), // sink.valid
.in_channel (cmd_demux_004_src0_channel), // .channel
.in_startofpacket (cmd_demux_004_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_004_src0_endofpacket), // .endofpacket
.in_ready (cmd_demux_004_src0_ready), // .ready
.in_data (cmd_demux_004_src0_data), // .data
.out_endofpacket (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_data), // .data
.out_channel (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_channel), // .channel
.out_valid (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_valid), // .valid
.out_ready (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sgdma_descriptor_read_to_pcie_ip_txs_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (84),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_TRANS_WRITE (70),
.IN_PKT_BURSTWRAP_H (85),
.IN_PKT_BURSTWRAP_L (85),
.IN_PKT_BURST_SIZE_H (88),
.IN_PKT_BURST_SIZE_L (86),
.IN_PKT_RESPONSE_STATUS_H (110),
.IN_PKT_RESPONSE_STATUS_L (109),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (90),
.IN_PKT_BURST_TYPE_L (89),
.IN_PKT_ORI_BURST_SIZE_L (111),
.IN_PKT_ORI_BURST_SIZE_H (113),
.IN_ST_DATA_W (114),
.OUT_PKT_ADDR_H (103),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (120),
.OUT_PKT_BYTE_CNT_L (110),
.OUT_PKT_TRANS_COMPRESSED_READ (104),
.OUT_PKT_BURST_SIZE_H (124),
.OUT_PKT_BURST_SIZE_L (122),
.OUT_PKT_RESPONSE_STATUS_H (146),
.OUT_PKT_RESPONSE_STATUS_L (145),
.OUT_PKT_TRANS_EXCLUSIVE (109),
.OUT_PKT_BURST_TYPE_H (126),
.OUT_PKT_BURST_TYPE_L (125),
.OUT_PKT_ORI_BURST_SIZE_L (147),
.OUT_PKT_ORI_BURST_SIZE_H (149),
.OUT_ST_DATA_W (150),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (sgdma_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_005_src0_valid), // sink.valid
.in_channel (cmd_demux_005_src0_channel), // .channel
.in_startofpacket (cmd_demux_005_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_005_src0_endofpacket), // .endofpacket
.in_ready (cmd_demux_005_src0_ready), // .ready
.in_data (cmd_demux_005_src0_data), // .data
.out_endofpacket (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_data), // .data
.out_channel (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_channel), // .channel
.out_valid (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_valid), // .valid
.out_ready (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sgdma_descriptor_write_to_pcie_ip_txs_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (84),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_TRANS_WRITE (70),
.IN_PKT_BURSTWRAP_H (85),
.IN_PKT_BURSTWRAP_L (85),
.IN_PKT_BURST_SIZE_H (88),
.IN_PKT_BURST_SIZE_L (86),
.IN_PKT_RESPONSE_STATUS_H (110),
.IN_PKT_RESPONSE_STATUS_L (109),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (90),
.IN_PKT_BURST_TYPE_L (89),
.IN_PKT_ORI_BURST_SIZE_L (111),
.IN_PKT_ORI_BURST_SIZE_H (113),
.IN_ST_DATA_W (114),
.OUT_PKT_ADDR_H (103),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (120),
.OUT_PKT_BYTE_CNT_L (110),
.OUT_PKT_TRANS_COMPRESSED_READ (104),
.OUT_PKT_BURST_SIZE_H (124),
.OUT_PKT_BURST_SIZE_L (122),
.OUT_PKT_RESPONSE_STATUS_H (146),
.OUT_PKT_RESPONSE_STATUS_L (145),
.OUT_PKT_TRANS_EXCLUSIVE (109),
.OUT_PKT_BURST_TYPE_H (126),
.OUT_PKT_BURST_TYPE_L (125),
.OUT_PKT_ORI_BURST_SIZE_L (147),
.OUT_PKT_ORI_BURST_SIZE_H (149),
.OUT_ST_DATA_W (150),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_to_sgdma_m_read_rsp_width_adapter (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_src2_valid), // sink.valid
.in_channel (rsp_demux_src2_channel), // .channel
.in_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.in_ready (rsp_demux_src2_ready), // .ready
.in_data (rsp_demux_src2_data), // .data
.out_endofpacket (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_data), // .data
.out_channel (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (84),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_TRANS_WRITE (70),
.IN_PKT_BURSTWRAP_H (85),
.IN_PKT_BURSTWRAP_L (85),
.IN_PKT_BURST_SIZE_H (88),
.IN_PKT_BURST_SIZE_L (86),
.IN_PKT_RESPONSE_STATUS_H (110),
.IN_PKT_RESPONSE_STATUS_L (109),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (90),
.IN_PKT_BURST_TYPE_L (89),
.IN_PKT_ORI_BURST_SIZE_L (111),
.IN_PKT_ORI_BURST_SIZE_H (113),
.IN_ST_DATA_W (114),
.OUT_PKT_ADDR_H (103),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (120),
.OUT_PKT_BYTE_CNT_L (110),
.OUT_PKT_TRANS_COMPRESSED_READ (104),
.OUT_PKT_BURST_SIZE_H (124),
.OUT_PKT_BURST_SIZE_L (122),
.OUT_PKT_RESPONSE_STATUS_H (146),
.OUT_PKT_RESPONSE_STATUS_L (145),
.OUT_PKT_TRANS_EXCLUSIVE (109),
.OUT_PKT_BURST_TYPE_H (126),
.OUT_PKT_BURST_TYPE_L (125),
.OUT_PKT_ORI_BURST_SIZE_L (147),
.OUT_PKT_ORI_BURST_SIZE_H (149),
.OUT_ST_DATA_W (150),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_to_sgdma_m_write_rsp_width_adapter (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_src3_valid), // sink.valid
.in_channel (rsp_demux_src3_channel), // .channel
.in_startofpacket (rsp_demux_src3_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src3_endofpacket), // .endofpacket
.in_ready (rsp_demux_src3_ready), // .ready
.in_data (rsp_demux_src3_data), // .data
.out_endofpacket (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_data), // .data
.out_channel (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (103),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (120),
.IN_PKT_BYTE_CNT_L (110),
.IN_PKT_TRANS_COMPRESSED_READ (104),
.IN_PKT_TRANS_WRITE (106),
.IN_PKT_BURSTWRAP_H (121),
.IN_PKT_BURSTWRAP_L (121),
.IN_PKT_BURST_SIZE_H (124),
.IN_PKT_BURST_SIZE_L (122),
.IN_PKT_RESPONSE_STATUS_H (146),
.IN_PKT_RESPONSE_STATUS_L (145),
.IN_PKT_TRANS_EXCLUSIVE (109),
.IN_PKT_BURST_TYPE_H (126),
.IN_PKT_BURST_TYPE_L (125),
.IN_PKT_ORI_BURST_SIZE_L (147),
.IN_PKT_ORI_BURST_SIZE_H (149),
.IN_ST_DATA_W (150),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (84),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (88),
.OUT_PKT_BURST_SIZE_L (86),
.OUT_PKT_RESPONSE_STATUS_H (110),
.OUT_PKT_RESPONSE_STATUS_L (109),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (90),
.OUT_PKT_BURST_TYPE_L (89),
.OUT_PKT_ORI_BURST_SIZE_L (111),
.OUT_PKT_ORI_BURST_SIZE_H (113),
.OUT_ST_DATA_W (114),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_001_src2_valid), // sink.valid
.in_channel (rsp_demux_001_src2_channel), // .channel
.in_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src2_endofpacket), // .endofpacket
.in_ready (rsp_demux_001_src2_ready), // .ready
.in_data (rsp_demux_001_src2_data), // .data
.out_endofpacket (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_data), // .data
.out_channel (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_channel), // .channel
.out_valid (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_valid), // .valid
.out_ready (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (pcie_ip_txs_to_sgdma_descriptor_read_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (103),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (120),
.IN_PKT_BYTE_CNT_L (110),
.IN_PKT_TRANS_COMPRESSED_READ (104),
.IN_PKT_TRANS_WRITE (106),
.IN_PKT_BURSTWRAP_H (121),
.IN_PKT_BURSTWRAP_L (121),
.IN_PKT_BURST_SIZE_H (124),
.IN_PKT_BURST_SIZE_L (122),
.IN_PKT_RESPONSE_STATUS_H (146),
.IN_PKT_RESPONSE_STATUS_L (145),
.IN_PKT_TRANS_EXCLUSIVE (109),
.IN_PKT_BURST_TYPE_H (126),
.IN_PKT_BURST_TYPE_L (125),
.IN_PKT_ORI_BURST_SIZE_L (147),
.IN_PKT_ORI_BURST_SIZE_H (149),
.IN_ST_DATA_W (150),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (84),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (88),
.OUT_PKT_BURST_SIZE_L (86),
.OUT_PKT_RESPONSE_STATUS_H (110),
.OUT_PKT_RESPONSE_STATUS_L (109),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (90),
.OUT_PKT_BURST_TYPE_L (89),
.OUT_PKT_ORI_BURST_SIZE_L (111),
.OUT_PKT_ORI_BURST_SIZE_H (113),
.OUT_ST_DATA_W (114),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_001_src3_valid), // sink.valid
.in_channel (rsp_demux_001_src3_channel), // .channel
.in_startofpacket (rsp_demux_001_src3_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src3_endofpacket), // .endofpacket
.in_ready (rsp_demux_001_src3_ready), // .ready
.in_data (rsp_demux_001_src3_data), // .data
.out_endofpacket (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_data), // .data
.out_channel (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_channel), // .channel
.out_valid (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_valid), // .valid
.out_ready (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (pcie_ip_txs_to_sgdma_descriptor_write_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (114),
.BITS_PER_SYMBOL (114),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (custom_module_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (altpll_qsys_c1_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (114),
.BITS_PER_SYMBOL (114),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (altpll_qsys_c1_clk), // in_clk.clk
.in_reset (video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_001_src1_ready), // in.ready
.in_valid (cmd_demux_001_src1_valid), // .valid
.in_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_001_src1_channel), // .channel
.in_data (cmd_demux_001_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (114),
.BITS_PER_SYMBOL (114),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (altpll_qsys_c1_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (custom_module_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (114),
.BITS_PER_SYMBOL (114),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (altpll_qsys_c1_clk), // out_clk.clk
.out_reset (video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_002_src0_ready), // in.ready
.in_valid (rsp_demux_002_src0_valid), // .valid
.in_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_002_src0_channel), // .channel
.in_data (rsp_demux_002_src0_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (114),
.BITS_PER_SYMBOL (114),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_004 (
.in_clk (pcie_ip_pcie_core_clk_clk), // in_clk.clk
.in_reset (sgdma_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (altpll_qsys_c1_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_ready), // in.ready
.in_valid (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_valid), // .valid
.in_startofpacket (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_endofpacket (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.in_channel (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_channel), // .channel
.in_data (sgdma_m_read_to_sdram_s1_cmd_width_adapter_src_data), // .data
.out_ready (crosser_004_out_ready), // out.ready
.out_valid (crosser_004_out_valid), // .valid
.out_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.out_channel (crosser_004_out_channel), // .channel
.out_data (crosser_004_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (114),
.BITS_PER_SYMBOL (114),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_005 (
.in_clk (pcie_ip_pcie_core_clk_clk), // in_clk.clk
.in_reset (sgdma_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (altpll_qsys_c1_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_ready), // in.ready
.in_valid (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_valid), // .valid
.in_startofpacket (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_endofpacket (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.in_channel (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_channel), // .channel
.in_data (sgdma_m_write_to_sdram_s1_cmd_width_adapter_src_data), // .data
.out_ready (crosser_005_out_ready), // out.ready
.out_valid (crosser_005_out_valid), // .valid
.out_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.out_channel (crosser_005_out_channel), // .channel
.out_data (crosser_005_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (150),
.BITS_PER_SYMBOL (150),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_006 (
.in_clk (altpll_qsys_c1_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pcie_ip_pcie_core_clk_clk), // out_clk.clk
.out_reset (sgdma_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_ready), // in.ready
.in_valid (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_valid), // .valid
.in_startofpacket (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_endofpacket), // .endofpacket
.in_channel (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_channel), // .channel
.in_data (sdram_s1_to_sgdma_m_read_rsp_width_adapter_src_data), // .data
.out_ready (crosser_006_out_ready), // out.ready
.out_valid (crosser_006_out_valid), // .valid
.out_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_006_out_endofpacket), // .endofpacket
.out_channel (crosser_006_out_channel), // .channel
.out_data (crosser_006_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (150),
.BITS_PER_SYMBOL (150),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_007 (
.in_clk (altpll_qsys_c1_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pcie_ip_pcie_core_clk_clk), // out_clk.clk
.out_reset (sgdma_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_ready), // in.ready
.in_valid (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_valid), // .valid
.in_startofpacket (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_endofpacket), // .endofpacket
.in_channel (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_channel), // .channel
.in_data (sdram_s1_to_sgdma_m_write_rsp_width_adapter_src_data), // .data
.out_ready (crosser_007_out_ready), // out.ready
.out_valid (crosser_007_out_valid), // .valid
.out_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_007_out_endofpacket), // .endofpacket
.out_channel (crosser_007_out_channel), // .channel
.out_data (crosser_007_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
amm_master_qsys_with_pcie_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (altpll_qsys_c1_clk), // in_clk_0.clk
.in_rst_0_reset (sdram_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sdram_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
amm_master_qsys_with_pcie_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (66),
.inUsePackets (0),
.inDataWidth (66),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (66),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (pcie_ip_pcie_core_clk_clk), // in_clk_0.clk
.in_rst_0_reset (pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (pcie_ip_txs_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (pcie_ip_txs_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (pcie_ip_txs_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
amm_master_qsys_with_pcie_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (clk_50_clk_clk), // in_clk_0.clk
.in_rst_0_reset (altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (altpll_qsys_pll_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (altpll_qsys_pll_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (altpll_qsys_pll_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
endmodule |
module processing_system7_0(ENET0_PTP_DELAY_REQ_RX, ENET0_PTP_DELAY_REQ_TX, ENET0_PTP_PDELAY_REQ_RX, ENET0_PTP_PDELAY_REQ_TX, ENET0_PTP_PDELAY_RESP_RX, ENET0_PTP_PDELAY_RESP_TX, ENET0_PTP_SYNC_FRAME_RX, ENET0_PTP_SYNC_FRAME_TX, ENET0_SOF_RX, ENET0_SOF_TX, GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, USB1_PORT_INDCTL, USB1_VBUS_PWRSELECT, USB1_VBUS_PWRFAULT, M_AXI_GP1_ARVALID, M_AXI_GP1_AWVALID, M_AXI_GP1_BREADY, M_AXI_GP1_RREADY, M_AXI_GP1_WLAST, M_AXI_GP1_WVALID, M_AXI_GP1_ARID, M_AXI_GP1_AWID, M_AXI_GP1_WID, M_AXI_GP1_ARBURST, M_AXI_GP1_ARLOCK, M_AXI_GP1_ARSIZE, M_AXI_GP1_AWBURST, M_AXI_GP1_AWLOCK, M_AXI_GP1_AWSIZE, M_AXI_GP1_ARPROT, M_AXI_GP1_AWPROT, M_AXI_GP1_ARADDR, M_AXI_GP1_AWADDR, M_AXI_GP1_WDATA, M_AXI_GP1_ARCACHE, M_AXI_GP1_ARLEN, M_AXI_GP1_ARQOS, M_AXI_GP1_AWCACHE, M_AXI_GP1_AWLEN, M_AXI_GP1_AWQOS, M_AXI_GP1_WSTRB, M_AXI_GP1_ACLK, M_AXI_GP1_ARREADY, M_AXI_GP1_AWREADY, M_AXI_GP1_BVALID, M_AXI_GP1_RLAST, M_AXI_GP1_RVALID, M_AXI_GP1_WREADY, M_AXI_GP1_BID, M_AXI_GP1_RID, M_AXI_GP1_BRESP, M_AXI_GP1_RRESP, M_AXI_GP1_RDATA, S_AXI_HP1_ARREADY, S_AXI_HP1_AWREADY, S_AXI_HP1_BVALID, S_AXI_HP1_RLAST, S_AXI_HP1_RVALID, S_AXI_HP1_WREADY, S_AXI_HP1_BRESP, S_AXI_HP1_RRESP, S_AXI_HP1_BID, S_AXI_HP1_RID, S_AXI_HP1_RDATA, S_AXI_HP1_RCOUNT, S_AXI_HP1_WCOUNT, S_AXI_HP1_RACOUNT, S_AXI_HP1_WACOUNT, S_AXI_HP1_ACLK, S_AXI_HP1_ARVALID, S_AXI_HP1_AWVALID, S_AXI_HP1_BREADY, S_AXI_HP1_RDISSUECAP1_EN, S_AXI_HP1_RREADY, S_AXI_HP1_WLAST, S_AXI_HP1_WRISSUECAP1_EN, S_AXI_HP1_WVALID, S_AXI_HP1_ARBURST, S_AXI_HP1_ARLOCK, S_AXI_HP1_ARSIZE, S_AXI_HP1_AWBURST, S_AXI_HP1_AWLOCK, S_AXI_HP1_AWSIZE, S_AXI_HP1_ARPROT, S_AXI_HP1_AWPROT, S_AXI_HP1_ARADDR, S_AXI_HP1_AWADDR, S_AXI_HP1_ARCACHE, S_AXI_HP1_ARLEN, S_AXI_HP1_ARQOS, S_AXI_HP1_AWCACHE, S_AXI_HP1_AWLEN, S_AXI_HP1_AWQOS, S_AXI_HP1_ARID, S_AXI_HP1_AWID, S_AXI_HP1_WID, S_AXI_HP1_WDATA, S_AXI_HP1_WSTRB, FCLK_CLK0, FCLK_CLK3, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="ENET0_PTP_DELAY_REQ_RX,ENET0_PTP_DELAY_REQ_TX,ENET0_PTP_PDELAY_REQ_RX,ENET0_PTP_PDELAY_REQ_TX,ENET0_PTP_PDELAY_RESP_RX,ENET0_PTP_PDELAY_RESP_TX,ENET0_PTP_SYNC_FRAME_RX,ENET0_PTP_SYNC_FRAME_TX,ENET0_SOF_RX,ENET0_SOF_TX,GPIO_I[47:0],GPIO_O[47:0],GPIO_T[47:0],I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,USB1_PORT_INDCTL[1:0],USB1_VBUS_PWRSELECT,USB1_VBUS_PWRFAULT,M_AXI_GP1_ARVALID,M_AXI_GP1_AWVALID,M_AXI_GP1_BREADY,M_AXI_GP1_RREADY,M_AXI_GP1_WLAST,M_AXI_GP1_WVALID,M_AXI_GP1_ARID[11:0],M_AXI_GP1_AWID[11:0],M_AXI_GP1_WID[11:0],M_AXI_GP1_ARBURST[1:0],M_AXI_GP1_ARLOCK[1:0],M_AXI_GP1_ARSIZE[2:0],M_AXI_GP1_AWBURST[1:0],M_AXI_GP1_AWLOCK[1:0],M_AXI_GP1_AWSIZE[2:0],M_AXI_GP1_ARPROT[2:0],M_AXI_GP1_AWPROT[2:0],M_AXI_GP1_ARADDR[31:0],M_AXI_GP1_AWADDR[31:0],M_AXI_GP1_WDATA[31:0],M_AXI_GP1_ARCACHE[3:0],M_AXI_GP1_ARLEN[3:0],M_AXI_GP1_ARQOS[3:0],M_AXI_GP1_AWCACHE[3:0],M_AXI_GP1_AWLEN[3:0],M_AXI_GP1_AWQOS[3:0],M_AXI_GP1_WSTRB[3:0],M_AXI_GP1_ACLK,M_AXI_GP1_ARREADY,M_AXI_GP1_AWREADY,M_AXI_GP1_BVALID,M_AXI_GP1_RLAST,M_AXI_GP1_RVALID,M_AXI_GP1_WREADY,M_AXI_GP1_BID[11:0],M_AXI_GP1_RID[11:0],M_AXI_GP1_BRESP[1:0],M_AXI_GP1_RRESP[1:0],M_AXI_GP1_RDATA[31:0],S_AXI_HP1_ARREADY,S_AXI_HP1_AWREADY,S_AXI_HP1_BVALID,S_AXI_HP1_RLAST,S_AXI_HP1_RVALID,S_AXI_HP1_WREADY,S_AXI_HP1_BRESP[1:0],S_AXI_HP1_RRESP[1:0],S_AXI_HP1_BID[5:0],S_AXI_HP1_RID[5:0],S_AXI_HP1_RDATA[63:0],S_AXI_HP1_RCOUNT[7:0],S_AXI_HP1_WCOUNT[7:0],S_AXI_HP1_RACOUNT[2:0],S_AXI_HP1_WACOUNT[5:0],S_AXI_HP1_ACLK,S_AXI_HP1_ARVALID,S_AXI_HP1_AWVALID,S_AXI_HP1_BREADY,S_AXI_HP1_RDISSUECAP1_EN,S_AXI_HP1_RREADY,S_AXI_HP1_WLAST,S_AXI_HP1_WRISSUECAP1_EN,S_AXI_HP1_WVALID,S_AXI_HP1_ARBURST[1:0],S_AXI_HP1_ARLOCK[1:0],S_AXI_HP1_ARSIZE[2:0],S_AXI_HP1_AWBURST[1:0],S_AXI_HP1_AWLOCK[1:0],S_AXI_HP1_AWSIZE[2:0],S_AXI_HP1_ARPROT[2:0],S_AXI_HP1_AWPROT[2:0],S_AXI_HP1_ARADDR[31:0],S_AXI_HP1_AWADDR[31:0],S_AXI_HP1_ARCACHE[3:0],S_AXI_HP1_ARLEN[3:0],S_AXI_HP1_ARQOS[3:0],S_AXI_HP1_AWCACHE[3:0],S_AXI_HP1_AWLEN[3:0],S_AXI_HP1_AWQOS[3:0],S_AXI_HP1_ARID[5:0],S_AXI_HP1_AWID[5:0],S_AXI_HP1_WID[5:0],S_AXI_HP1_WDATA[63:0],S_AXI_HP1_WSTRB[7:0],FCLK_CLK0,FCLK_CLK3,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
input [47:0]GPIO_I;
output [47:0]GPIO_O;
output [47:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output FCLK_CLK0;
output FCLK_CLK3;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule |
module serdes_1_to_n_data_s16_diff (use_phase_detector, datain_p, datain_n, rxioclk, rx_serdesstrobe, reset, rx_toggle, rx_bufg_pll_x2, rx_bufg_pll_x1, bitslip, data_out) ;
parameter integer S = 10 ; // Parameter to set the serdes factor 10,12,14,16
parameter integer D = 16 ; // Set the number of inputs and outputs
parameter DIFF_TERM = "FALSE" ; // Parameter to enable internal differential termination
input use_phase_detector ; // '1' enables the phase detcetor logic
input [D-1:0] datain_p ; // Input from LVDS receiver pin
input [D-1:0] datain_n ; // Input from LVDS receiver pin
input rxioclk ; // IO Clock network
input rx_serdesstrobe ; // Parallel data capture strobe
input reset ; // Reset line
input rx_toggle ; // Toggle control line
input rx_bufg_pll_x2 ; // Global clock x2
input rx_bufg_pll_x1 ; // Global clock
input bitslip ; // Bitslip control line
output [(D*S)-1:0] data_out ; // Output data
wire [D-1:0] ddly_m; // Master output from IODELAY1
wire [D-1:0] ddly_s; // Slave output from IODELAY1
wire [D-1:0] busys ; //
wire [D-1:0] busym ; //
wire [D-1:0] rx_data_in ; //
wire [D-1:0] rx_data_in_fix ; //
wire [D-1:0] cascade ; //
wire [D-1:0] pd_edge ; //
wire [(8*D)-1:0] mdataout ; //
reg [(D*S)-1:0] datain ; //
wire [(D*S/2)-1:0] rxd ; //
reg [(D*S/2)-1:0] datah ; //
reg [11:0] counter ;
reg [3:0] state ;
reg cal_data_sint ;
wire [D-1:0] busy_data ;
reg busy_data_d ;
wire cal_data_slave ;
reg enable ;
reg cal_data_master ;
reg rst_data ;
reg inc_data_int ;
wire inc_data ;
reg [D-1:0] ce_data ;
reg valid_data_d ;
reg incdec_data_d ;
reg [4:0] pdcounter ;
wire [D-1:0] valid_data ;
wire [D-1:0] incdec_data ;
reg flag ;
reg [D-1:0] mux ;
reg ce_data_inta ;
wire [D:0] incdec_data_or ;
wire [D-1:0] incdec_data_im ;
wire [D:0] valid_data_or ;
wire [D-1:0] valid_data_im ;
wire [D:0] busy_data_or ;
parameter SIM_TAP_DELAY = 49 ; //
parameter [D-1:0] RX_SWAP_MASK = 16'h0000 ; // pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
assign busy_data = busys ;
assign data_out = datain ;
genvar i ; // Limit the output data bus to the most significant 'S' number of bits
genvar j ;
assign cal_data_slave = cal_data_sint ;
always @ (posedge rx_bufg_pll_x1)
begin
datain <= {rxd, datah} ;
end
always @ (posedge rx_bufg_pll_x2)
begin
if (rx_toggle == 1'b1) begin
datah <= rxd ;
end
end
always @ (posedge rx_bufg_pll_x2 or posedge reset)
begin
if (reset == 1'b1) begin
state <= 0 ;
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
counter <= 9'h000 ;
enable <= 1'b0 ;
mux <= 16'h0001 ;
end
else begin
counter <= counter + 9'h001 ;
if (counter[8] == 1'b1) begin
counter <= 9'h000 ;
end
if (counter[5] == 1'b1) begin
enable <= 1'b1 ;
end
if (state == 0 && enable == 1'b1) begin // Wait for IODELAY to be available
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
rst_data <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 1 ;
end
end
else if (state == 1) begin // Issue calibrate command to both master and slave, needed for simulation, not for the silicon
cal_data_master <= 1'b1 ;
cal_data_sint <= 1'b1 ;
if (busy_data_d == 1'b1) begin // and wait for command to be accepted
state <= 2 ;
end
end
else if (state == 2) begin // Now RST master and slave IODELAYs needed for simulation, not for the silicon
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b0) begin
rst_data <= 1'b1 ;
state <= 3 ;
end
end
else if (state == 3) begin // Wait for IODELAY to be available
rst_data <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 4 ;
end
end
else if (state == 4) begin // Wait for occasional enable
if (counter[8] == 1'b1) begin
state <= 5 ;
end
end
else if (state == 5) begin // Calibrate slave only
if (busy_data_d == 1'b0) begin
cal_data_sint <= 1'b1 ;
state <= 6 ;
if (D != 1) begin
mux <= {mux[D-2:0], mux[D-1]} ;
end
end
end
else if (state == 6) begin // Wait for command to be accepted
if (busy_data_d == 1'b1) begin
cal_data_sint <= 1'b0 ;
state <= 7 ;
end
end
else if (state == 7) begin // Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 4 ;
end
end
end
end
always @ (posedge rx_bufg_pll_x2 or posedge reset) // Per-bit phase detection state machine
begin
if (reset == 1'b1) begin
pdcounter <= 5'b1000 ;
ce_data_inta <= 1'b0 ;
flag <= 1'b0 ; // flag is there to only allow one inc or dec per cal (test)
end
else begin
busy_data_d <= busy_data_or[D] ;
if (use_phase_detector == 1'b1) begin // decide whther pd is used
incdec_data_d <= incdec_data_or[D] ;
valid_data_d <= valid_data_or[D] ;
if (ce_data_inta == 1'b1) begin
ce_data = mux ;
end
else begin
ce_data = 64'h0000000000000000 ;
end
if (state == 7) begin
flag <= 1'b0 ;
end
else if (state != 4 || busy_data_d == 1'b1) begin // Reset filter if state machine issues a cal command or unit is busy
pdcounter <= 5'b10000 ;
ce_data_inta <= 1'b0 ;
end
else if (pdcounter == 5'b11111 && flag == 1'b0) begin // Filter has reached positive max - increment the tap count
ce_data_inta <= 1'b1 ;
inc_data_int <= 1'b1 ;
pdcounter <= 5'b10000 ;
flag <= 1'b0 ;
end
else if (pdcounter == 5'b00000 && flag == 1'b0) begin // Filter has reached negative max - decrement the tap count
ce_data_inta <= 1'b1 ;
inc_data_int <= 1'b0 ;
pdcounter <= 5'b10000 ;
flag <= 1'b0 ;
end
else if (valid_data_d == 1'b1) begin // increment filter
ce_data_inta <= 1'b0 ;
if (incdec_data_d == 1'b1 && pdcounter != 5'b11111) begin
pdcounter <= pdcounter + 5'b00001 ;
end
else if (incdec_data_d == 1'b0 && pdcounter != 5'b00000) begin // decrement filter
pdcounter <= pdcounter + 5'b11111 ;
end
end
else begin
ce_data_inta <= 1'b0 ;
end
end
else begin
ce_data = 64'h0000000000000000 ;
inc_data_int = 1'b0 ;
end
end
end
assign inc_data = inc_data_int ;
assign incdec_data_or[0] = 1'b0 ; // Input Mux - Initialise generate loop OR gates
assign valid_data_or[0] = 1'b0 ;
assign busy_data_or[0] = 1'b0 ;
generate
for (i = 0 ; i <= (D-1) ; i = i+1)
begin : loop0
assign incdec_data_im[i] = incdec_data[i] & mux[i] ; // Input muxes
assign incdec_data_or[i+1] = incdec_data_im[i] | incdec_data_or[i] ; // AND gates to allow just one signal through at a tome
assign valid_data_im[i] = valid_data[i] & mux[i] ; // followed by an OR
assign valid_data_or[i+1] = valid_data_im[i] | valid_data_or[i] ; // for the three inputs from each PD
assign busy_data_or[i+1] = busy_data[i] | busy_data_or[i] ; // The busy signals just need an OR gate
assign rx_data_in_fix[i] = rx_data_in[i] ^ RX_SWAP_MASK[i] ; // Invert signals as required
IBUFDS #(
.DIFF_TERM (DIFF_TERM))
data_in (
.I (datain_p[i]),
.IB (datain_n[i]),
.O (rx_data_in[i]));
IODELAY2 #(
.DATA_RATE ("SDR"), // <SDR>, DDR
.IDELAY_VALUE (0), // {0 ... 255}
.IDELAY2_VALUE (0), // {0 ... 255}
.IDELAY_MODE ("NORMAL" ), // NORMAL, PCI
.ODELAY_VALUE (0), // {0 ... 255}
.IDELAY_TYPE ("DIFF_PHASE_DETECTOR"),// "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
.COUNTER_WRAPAROUND ("WRAPAROUND" ), // <STAY_AT_LIMIT>, WRAPAROUND
.DELAY_SRC ("IDATAIN" ), // "IO", "IDATAIN", "ODATAIN"
.SERDES_MODE ("MASTER"), // <NONE>, MASTER, SLAVE
.SIM_TAPDELAY_VALUE (SIM_TAP_DELAY)) //
iodelay_m (
.IDATAIN (rx_data_in_fix[i]), // data from primary IOB
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_m[i]), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (rxioclk), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (rx_bufg_pll_x2), // Fabric clock (GCLK) for control signals
.CAL (cal_data_master), // Calibrate control signal
.INC (inc_data), // Increment counter
.CE (ce_data[i]), // Clock Enable
.RST (rst_data), // Reset delay line
.BUSY (busym[i])) ; // output signal indicating sync circuit has finished / calibration has finished
IODELAY2 #(
.DATA_RATE ("SDR"), // <SDR>, DDR
.IDELAY_VALUE (0), // {0 ... 255}
.IDELAY2_VALUE (0), // {0 ... 255}
.IDELAY_MODE ("NORMAL" ), // NORMAL, PCI
.ODELAY_VALUE (0), // {0 ... 255}
.IDELAY_TYPE ("DIFF_PHASE_DETECTOR"),// "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
.COUNTER_WRAPAROUND ("WRAPAROUND" ), // <STAY_AT_LIMIT>, WRAPAROUND
.DELAY_SRC ("IDATAIN" ), // "IO", "IDATAIN", "ODATAIN"
.SERDES_MODE ("SLAVE"), // <NONE>, MASTER, SLAVE
.SIM_TAPDELAY_VALUE (SIM_TAP_DELAY)) //
iodelay_s (
.IDATAIN (rx_data_in_fix[i]), // data from primary IOB
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_s[i]), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (rxioclk), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (rx_bufg_pll_x2), // Fabric clock (GCLK) for control signals
.CAL (cal_data_slave), // Calibrate control signal
.INC (inc_data), // Increment counter
.CE (ce_data[i]), // Clock Enable
.RST (rst_data), // Reset delay line
.BUSY (busys[i])) ; // output signal indicating sync circuit has finished / calibration has finished
ISERDES2 #(
.DATA_WIDTH (S/2), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE ("SDR"), // <SDR>, DDR
.BITSLIP_ENABLE ("TRUE"), // <FALSE>, TRUE
.SERDES_MODE ("MASTER"), // <DEFAULT>, MASTER, SLAVE
.INTERFACE_TYPE ("RETIMED")) // NETWORKING, NETWORKING_PIPELINED, <RETIMED>
iserdes_m (
.D (ddly_m[i]),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rx_serdesstrobe),
.RST (reset),
.CLKDIV (rx_bufg_pll_x2),
.SHIFTIN (pd_edge[i]),
.BITSLIP (bitslip),
.FABRICOUT (),
.Q4 (mdataout[(8*i)+7]),
.Q3 (mdataout[(8*i)+6]),
.Q2 (mdataout[(8*i)+5]),
.Q1 (mdataout[(8*i)+4]),
.DFB (),
.CFB0 (),
.CFB1 (),
.VALID (valid_data[i]),
.INCDEC (incdec_data[i]),
.SHIFTOUT (cascade[i]));
ISERDES2 #(
.DATA_WIDTH (S/2), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE ("SDR"), // <SDR>, DDR
.BITSLIP_ENABLE ("TRUE"), // <FALSE>, TRUE
.SERDES_MODE ("SLAVE"), // <DEFAULT>, MASTER, SLAVE
.INTERFACE_TYPE ("RETIMED")) // NETWORKING, NETWORKING_PIPELINED, <RETIMED>
iserdes_s (
.D (ddly_s[i]),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rx_serdesstrobe),
.RST (reset),
.CLKDIV (rx_bufg_pll_x2),
.SHIFTIN (cascade[i]),
.BITSLIP (bitslip),
.FABRICOUT (),
.Q4 (mdataout[(8*i)+3]),
.Q3 (mdataout[(8*i)+2]),
.Q2 (mdataout[(8*i)+1]),
.Q1 (mdataout[(8*i)+0]),
.DFB (),
.CFB0 (),
.CFB1 (),
.VALID (),
.INCDEC (),
.SHIFTOUT (pd_edge[i]));
// Assign received data bits to correct place in data word
for (j = 7 ; j >= (8-(S/2)) ; j = j-1) // j is for serdes factor
begin : loop1
assign rxd[((D*(j+(S/2)-8))+i)] = mdataout[(8*i)+j] ;
end
end
endgenerate
endmodule |
module zet_next_or_not (
input [1:0] prefix,
input [7:1] opcode,
input cx_zero,
input zf,
input ext_int,
output next_in_opco,
output next_in_exec,
output use_eintp
);
// Net declarations
wire exit_z, cmp_sca, exit_rep, valid_ops;
// Assignments
assign cmp_sca = opcode[7] & opcode[2] & opcode[1];
assign exit_z = prefix[0] ? /* repz */ (cmp_sca ? ~zf : 1'b0 )
: /* repnz */ (cmp_sca ? zf : 1'b0 );
assign exit_rep = cx_zero | exit_z;
assign valid_ops = (opcode[7:1]==7'b1010_010 // movs
|| opcode[7:1]==7'b1010_011 // cmps
|| opcode[7:1]==7'b1010_101 // stos
|| opcode[7:1]==7'b0110_110 // ins
|| opcode[7:1]==7'b0110_111 // outs
|| opcode[7:1]==7'b1010_110 // lods
|| opcode[7:1]==7'b1010_111); // scas
assign next_in_exec = prefix[1] && valid_ops && !exit_rep && !ext_int;
assign next_in_opco = prefix[1] && valid_ops && cx_zero;
assign use_eintp = prefix[1] && valid_ops && !exit_z;
endmodule |
module fifo_async_103x16(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, prog_full)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[102:0],wr_en,rd_en,dout[102:0],full,empty,prog_full" */;
input rst;
input wr_clk;
input rd_clk;
input [102:0]din;
input wr_en;
input rd_en;
output [102:0]dout;
output full;
output empty;
output prog_full;
assign empty =1'b0;
assign prog_full =1'b0;
assign dout[102:0] =103'b0;
assign full =1'b0;
endmodule |
module zynq_design_1_system_ila_0_0 (
clk,
SLOT_0_AXI_awaddr,
SLOT_0_AXI_awvalid,
SLOT_0_AXI_awready,
SLOT_0_AXI_wdata,
SLOT_0_AXI_wstrb,
SLOT_0_AXI_wvalid,
SLOT_0_AXI_wready,
SLOT_0_AXI_bresp,
SLOT_0_AXI_bvalid,
SLOT_0_AXI_bready,
SLOT_0_AXI_araddr,
SLOT_0_AXI_arvalid,
SLOT_0_AXI_arready,
SLOT_0_AXI_rdata,
SLOT_0_AXI_rresp,
SLOT_0_AXI_rvalid,
SLOT_0_AXI_rready,
resetn
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.clk CLK" *)
input wire clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR" *)
input wire [8 : 0] SLOT_0_AXI_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID" *)
input wire SLOT_0_AXI_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY" *)
input wire SLOT_0_AXI_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA" *)
input wire [31 : 0] SLOT_0_AXI_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB" *)
input wire [3 : 0] SLOT_0_AXI_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID" *)
input wire SLOT_0_AXI_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY" *)
input wire SLOT_0_AXI_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP" *)
input wire [1 : 0] SLOT_0_AXI_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID" *)
input wire SLOT_0_AXI_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY" *)
input wire SLOT_0_AXI_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR" *)
input wire [8 : 0] SLOT_0_AXI_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID" *)
input wire SLOT_0_AXI_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY" *)
input wire SLOT_0_AXI_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA" *)
input wire [31 : 0] SLOT_0_AXI_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP" *)
input wire [1 : 0] SLOT_0_AXI_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID" *)
input wire SLOT_0_AXI_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY" *)
input wire SLOT_0_AXI_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.resetn RST" *)
input wire resetn;
bd_c3fe inst (
.clk(clk),
.SLOT_0_AXI_awaddr(SLOT_0_AXI_awaddr),
.SLOT_0_AXI_awvalid(SLOT_0_AXI_awvalid),
.SLOT_0_AXI_awready(SLOT_0_AXI_awready),
.SLOT_0_AXI_wdata(SLOT_0_AXI_wdata),
.SLOT_0_AXI_wstrb(SLOT_0_AXI_wstrb),
.SLOT_0_AXI_wvalid(SLOT_0_AXI_wvalid),
.SLOT_0_AXI_wready(SLOT_0_AXI_wready),
.SLOT_0_AXI_bresp(SLOT_0_AXI_bresp),
.SLOT_0_AXI_bvalid(SLOT_0_AXI_bvalid),
.SLOT_0_AXI_bready(SLOT_0_AXI_bready),
.SLOT_0_AXI_araddr(SLOT_0_AXI_araddr),
.SLOT_0_AXI_arvalid(SLOT_0_AXI_arvalid),
.SLOT_0_AXI_arready(SLOT_0_AXI_arready),
.SLOT_0_AXI_rdata(SLOT_0_AXI_rdata),
.SLOT_0_AXI_rresp(SLOT_0_AXI_rresp),
.SLOT_0_AXI_rvalid(SLOT_0_AXI_rvalid),
.SLOT_0_AXI_rready(SLOT_0_AXI_rready),
.resetn(resetn)
);
endmodule |
module fpga_core
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
input wire uart_rts,
output wire uart_cts,
/*
* Ethernet: SFP+
*/
input wire sfp0_tx_clk,
input wire sfp0_tx_rst,
output wire [63:0] sfp0_txd,
output wire [7:0] sfp0_txc,
input wire sfp0_rx_clk,
input wire sfp0_rx_rst,
input wire [63:0] sfp0_rxd,
input wire [7:0] sfp0_rxc,
input wire sfp1_tx_clk,
input wire sfp1_tx_rst,
output wire [63:0] sfp1_txd,
output wire [7:0] sfp1_txc,
input wire sfp1_rx_clk,
input wire sfp1_rx_rst,
input wire [63:0] sfp1_rxd,
input wire [7:0] sfp1_rxc
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = ~match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((~match_cond_reg & ~no_match_reg) |
(rx_udp_payload_axis_tvalid & rx_udp_payload_axis_tready & rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid & match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready & match_cond) | no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid & match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready & match_cond_reg) | no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid & ~valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign led = led_reg;
assign sfp1_txd = 64'h0707070707070707;
assign sfp1_txc = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(sfp0_rx_clk),
.rx_rst(sfp0_rx_rst),
.tx_clk(sfp0_tx_clk),
.tx_rst(sfp0_tx_rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(sfp0_rxd),
.xgmii_rxc(sfp0_rxc),
.xgmii_txd(sfp0_txd),
.xgmii_txc(sfp0_txc),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule |
module sky130_fd_sc_ms__nor4bb_2 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__nor4bb_2 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule |
module outputs)
// End of automatics
wire thread0_e,thread1_e,thread2_e,thread3_e;
wire thread0_w2,thread1_w2,thread2_w2,thread3_w2;
wire ld0_inst_vld_e,ld1_inst_vld_e,ld2_inst_vld_e,ld3_inst_vld_e ;
wire ld0_inst_vld_g,ld1_inst_vld_g,ld2_inst_vld_g,ld3_inst_vld_g ;
wire ld0_inst_vld_w2,ld1_inst_vld_w2,ld2_inst_vld_w2,ld3_inst_vld_w2 ;
//wire st_inst_vld_m,st_inst_vld_g;
wire imiss_pcx_rq_sel_d1, strm_pcx_rq_sel_d1 ;
wire imiss_pcx_rq_sel_d2 ;
wire fpop_pcx_rq_sel_d1, fpop_pcx_rq_sel_d2 ;
wire imiss_pcx_rq_sel ;
wire imiss_pkt_vld ;
wire [2:0] imiss_l2bnk_addr ;
wire [4:0] imiss_l2bnk_dest ;
wire fpst_vld_m, fpst_vld_g ;
wire fpop_vld_reset ;
wire fpop_pcx_rq_sel ;
wire fpop_pcx_rq_sel_tmp ;
wire fpop_vld_en ;
wire fpop_pkt1 ;
wire fpop_pkt_vld,fpop_pkt_vld_unmasked ;
wire fpop_atom_req, fpop_atom_rq_pq ;
wire [4:0] fpop_l2bnk_dest ;
wire pcx_req_squash ;
wire [4:0] strm_l2bnk_dest ;
wire strm_pkt_vld;
wire st0_pkt_vld ;
wire st1_pkt_vld ;
wire st2_pkt_vld ;
wire st3_pkt_vld ;
wire st0_pcx_rq_sel_d1, st1_pcx_rq_sel_d1;
wire st2_pcx_rq_sel_d1, st3_pcx_rq_sel_d1;
wire st0_pcx_rq_sel_d2, st1_pcx_rq_sel_d2;
wire st2_pcx_rq_sel_d2, st3_pcx_rq_sel_d2;
wire st0_pcx_rq_sel_d3, st1_pcx_rq_sel_d3;
wire st2_pcx_rq_sel_d3, st3_pcx_rq_sel_d3;
wire st0_cas_vld, st1_cas_vld, st2_cas_vld, st3_cas_vld ;
wire st0_atomic_vld, st1_atomic_vld, st2_atomic_vld, st3_atomic_vld ;
wire [4:0] st0_l2bnk_dest,st1_l2bnk_dest ;
wire [4:0] st2_l2bnk_dest,st3_l2bnk_dest ;
wire bld_helper_cmplt_e, bld_helper_cmplt_m, bld_helper_cmplt_g ;
wire bld_din,bld_dout ;
wire bld_g ;
wire bld_en ;
wire [1:0] bld_cnt ;
wire [1:0] bcnt_din ;
wire [2:0] bld_rd_din, bld_rd_dout, bld_rd_dout_m ;
wire [3:0] bld_annul,bld_annul_d1 ;
wire bld_rd_en ;
wire casa_m, casa_g ;
wire ld0_vld_reset, ld0_pkt_vld ;
wire ld0_pcx_rq_sel_d2, ld1_pcx_rq_sel_d2 ;
wire ld2_pcx_rq_sel_d2, ld3_pcx_rq_sel_d2 ;
wire ld0_fill_reset, ld1_fill_reset,ld2_fill_reset,ld3_fill_reset;
wire ld0_fill_reset_d1,ld1_fill_reset_d1,ld2_fill_reset_d1,ld3_fill_reset_d1;
wire ld0_fill_reset_d2,ld1_fill_reset_d2,ld2_fill_reset_d2,ld3_fill_reset_d2;
wire ld0_fill_reset_d2_tmp,ld1_fill_reset_d2_tmp,ld2_fill_reset_d2_tmp,ld3_fill_reset_d2_tmp;
wire [4:0] ld0_l2bnk_dest, ld1_l2bnk_dest ;
wire [4:0] ld2_l2bnk_dest, ld3_l2bnk_dest ;
wire ld1_vld_reset, ld1_pkt_vld ;
wire ld2_vld_reset, ld2_pkt_vld ;
wire ld3_vld_reset, ld3_pkt_vld ;
//wire casa0_g, casa1_g, casa2_g, casa3_g;
wire ld0_rawp_reset,ld0_rawp_en,ld0_rawp_disabled;
wire ld1_rawp_reset,ld1_rawp_en,ld1_rawp_disabled;
wire ld2_rawp_reset,ld2_rawp_en,ld2_rawp_disabled;
wire ld3_rawp_reset,ld3_rawp_en,ld3_rawp_disabled;
wire [2:0] ld0_rawp_ackid,ld1_rawp_ackid ;
wire [2:0] ld2_rawp_ackid,ld3_rawp_ackid ;
wire ld0_pcx_rq_vld, ld1_pcx_rq_vld ;
wire ld2_pcx_rq_vld, ld3_pcx_rq_vld ;
wire [4:0] queue_write ;
wire mcycle_squash_d1 ;
//wire ld_pcx_rq_vld, st_pcx_rq_vld ;
wire [4:0] st0_q_wr,st1_q_wr,st2_q_wr,st3_q_wr ;
wire [4:0] sel_qentry0 ;
wire st0_atom_rq,st1_atom_rq,st2_atom_rq,st3_atom_rq ;
wire st0_atom_rq_d1,st1_atom_rq_d1,st2_atom_rq_d1,st3_atom_rq_d1 ;
wire st0_cas_vld_d1,st1_cas_vld_d1,st2_cas_vld_d1,st3_cas_vld_d1 ;
wire st0_atom_rq_d2,st1_atom_rq_d2,st2_atom_rq_d2,st3_atom_rq_d2 ;
wire st0_cas_vld_d2,st1_cas_vld_d2,st2_cas_vld_d2,st3_cas_vld_d2 ;
//wire st_cas_rq_d2,st_quad_rq_d2;
wire st_cas_rq_d2 ;
wire st0_pcx_rq_vld, st1_pcx_rq_vld;
wire st2_pcx_rq_vld, st3_pcx_rq_vld;
wire st_atom_rq ;
wire st_atom_rq_d1 ;
wire imiss_pcx_rq_vld ;
wire [4:0] spc_pcx_req_update_g,spc_pcx_req_update_w2 ;
wire strm_pcx_rq_vld ;
wire fwdpkt_rq_vld ;
wire intrpt_pcx_rq_vld ;
wire fpop_pcx_rq_vld ;
wire [4:0] pre_qwr ;
wire ld0_pcx_rq_sel, ld1_pcx_rq_sel ;
wire ld2_pcx_rq_sel, ld3_pcx_rq_sel ;
wire strm_pcx_rq_sel ;
wire intrpt_pcx_rq_sel ;
//wire imiss_strm_pcx_rq_sel ;
//wire [2:0] dest_pkt_sel ;
wire [4:0] spc_pcx_req_g ;
wire [1:0] strm_l2bnk_addr ;
wire [2:0] ld0_l2bnk_addr, ld1_l2bnk_addr ;
wire [2:0] ld2_l2bnk_addr, ld3_l2bnk_addr ;
wire [4:0] current_pkt_dest ;
wire [7:6] ldst_va_m, ldst_va_g ;
wire [4:0] ld_pkt_dest ;
wire [4:0] st_pkt_dest ;
wire [4:0] intrpt_l2bnk_dest ;
wire pcx_req_squash_d1, pcx_req_squash_d2 ;
wire intrpt_pcx_rq_sel_d1 ;
wire [2:0] intrpt_l2bnk_addr ;
//wire st0_stq_vld,st1_stq_vld,st2_stq_vld,st3_stq_vld ;
wire st0_pcx_rq_sel, st1_pcx_rq_sel;
wire st2_pcx_rq_sel, st3_pcx_rq_sel;
//wire ld0_sec_hit_g,ld1_sec_hit_g,ld2_sec_hit_g,ld3_sec_hit_g;
wire ld0_sec_hit_w2,ld1_sec_hit_w2,ld2_sec_hit_w2,ld3_sec_hit_w2;
//wire [3:0] dfq_byp_sel_m, dfq_byp_sel_g ;
//wire [3:0] dfq_byp_sel_m;
wire ld0_unfilled,ld1_unfilled,ld2_unfilled,ld3_unfilled;
wire ld0_unfilled_tmp,ld1_unfilled_tmp,ld2_unfilled_tmp,ld3_unfilled_tmp;
wire [1:0] ld0_unfilled_wy,ld1_unfilled_wy,ld2_unfilled_wy,ld3_unfilled_wy ;
wire ld0_l2cache_rq,ld1_l2cache_rq ;
wire ld2_l2cache_rq,ld3_l2cache_rq ;
wire ld0_pcx_rq_sel_d1, ld1_pcx_rq_sel_d1 ;
wire ld2_pcx_rq_sel_d1, ld3_pcx_rq_sel_d1 ;
wire intrpt_pkt_vld;
wire fwdpkt_pcx_rq_sel;
wire fwdpkt_pcx_rq_sel_d1,fwdpkt_pcx_rq_sel_d2,fwdpkt_pcx_rq_sel_d3 ;
wire reset,dbb_reset_l;
wire clk;
//wire st_inst_vld_unflushed;
wire ldst_dbl_g;
//wire lsu_ld_sec_hit_l2access_g ;
wire lsu_ld_sec_hit_l2access_w2 ;
//wire [1:0] lsu_ld_sec_hit_wy_g ;
wire [1:0] lsu_ld_sec_hit_wy_w2 ;
//wire [1:0] ld_way;
//wire [1:0] ld_pcx_pkt_wy_g ;
wire [3:0] lsu_dtag_perror_w2 ;
wire [3:0] lmq_enable_w2 ;
wire ld0_spec_pick_vld_g ,
ld0_spec_pick_vld_w2 ;
wire ld1_spec_pick_vld_g ,
ld1_spec_pick_vld_w2 ;
wire ld2_spec_pick_vld_g ,
ld2_spec_pick_vld_w2 ;
wire ld3_spec_pick_vld_g ,
ld3_spec_pick_vld_w2 ;
wire non_l2bnk_mx0_d1 ;
wire non_l2bnk_mx1_d1 ;
wire non_l2bnk_mx2_d1 ;
wire non_l2bnk_mx3_d1 ;
wire lsu_pcx_req_squash ;
wire spc_pcx_atom_pq_buf2 ;
wire [4:0] spc_pcx_req_pq_buf2 ;
wire lsu_ld0_pcx_rq_sel_d1, lsu_ld1_pcx_rq_sel_d1 ;
wire lsu_ld2_pcx_rq_sel_d1, lsu_ld3_pcx_rq_sel_d1 ;
wire [3:0] ld_thrd_force_d1 ;
wire [3:0] st_thrd_force_d1 ;
wire [3:0] misc_thrd_force_d1 ;
wire [3:0] ld_thrd_force_vld ;
wire [3:0] st_thrd_force_vld ;
wire [3:0] misc_thrd_force_vld ;
wire [3:0] all_thrd_force_vld ;
wire [3:0] ld_thrd_pick_din ;
wire [3:0] st_thrd_pick_din ;
wire [3:0] misc_thrd_pick_din ;
wire [3:0] ld_thrd_pick_status_din ;
wire [3:0] st_thrd_pick_status_din ;
wire [3:0] misc_thrd_pick_status_din ;
wire [3:0] ld_thrd_pick_status ;
wire [3:0] st_thrd_pick_status ;
wire [3:0] misc_thrd_pick_status ;
wire ld_thrd_pick_rst ;
wire st_thrd_pick_rst ;
wire misc_thrd_pick_rst ;
wire all_thrd_pick_rst ;
assign clk = rclk;
dffrl_async rstff(.din (grst_l),
.q (dbb_reset_l),
.clk (clk), .se(se), .si(), .so(),
.rst_l (arst_l));
assign reset = ~dbb_reset_l;
//assign lsu_ifu_flush_ireg = 1'b0 ;
//=================================================================================================
// TEMP !! rm from vlin.filter also !!
//=================================================================================================
wire atm_in_stb_g ;
assign atm_in_stb_g = 1'b0 ;
//=================================================================================================
// LOGIC MOVED FROM STB_RWCTL
//=================================================================================================
// pcx is making request for data in current cycle. Can be multi-hot.
//assign pcx_any_rq_for_stb = |pcx_rq_for_stb[3:0] ;
//assign pcx_any_rq_for_stb =
// (pcx_rq_for_stb[0] & ~lsu_st_pcx_rq_kill_w2[0]) |
// (pcx_rq_for_stb[1] & ~lsu_st_pcx_rq_kill_w2[1]) |
// (pcx_rq_for_stb[2] & ~lsu_st_pcx_rq_kill_w2[2]) |
// (pcx_rq_for_stb[3] & ~lsu_st_pcx_rq_kill_w2[3]) ;
//
//dff #(1) prvld_stgd1 (
// .din (pcx_any_rq_for_stb),
// .q (lsu_stb_pcx_rvld_d1),
// .clk (clk),
// .se (1'b0), .si (), .so ()
// );
// replacement for above logic - pcx_rq_for_stb is already qual'ed w/ lsu_st_pcx_rq_kill_w2
// this signal is used in qdp1 and qdp2 as pcx paket valids.
assign lsu_stb_pcx_rvld_d1 = st3_pcx_rq_sel_d1 |
st2_pcx_rq_sel_d1 |
st1_pcx_rq_sel_d1 |
st0_pcx_rq_sel_d1 ;
//assign stb_rd_tid[0] = pcx_rq_for_stb[1] | pcx_rq_for_stb[3] ;
//assign stb_rd_tid[1] = pcx_rq_for_stb[2] | pcx_rq_for_stb[3] ;
//
//dff #(2) stbtid_stgd1 (
// .din (stb_rd_tid[1:0]), .q (lsu_stb_rd_tid[1:0]),
// .clk (clk),
// .se (1'b0), .si (), .so ()
// );
assign lsu_stb_rd_tid[0] = st1_pcx_rq_sel_d1 | st3_pcx_rq_sel_d1;
assign lsu_stb_rd_tid[1] = st2_pcx_rq_sel_d1 | st3_pcx_rq_sel_d1;
//=================================================================================================
assign lsu_ramtest_rd_w = lsu_dcache_iob_rd_w | ifu_lsu_fwd_data_vld ;
//=================================================================================================
// LD PCX PKT WAY
//=================================================================================================
// For direct-map mode, assume that addition set-index bits 12:11 are
// used to file line in set.
// timing fix: 5/19/03: move secondary hit way generation to w2
//assign ld_way[1:0] =
// lsu_way_hit_or ? lsu_encd_way_hit[1:0]:
// lsu_ld_sec_hit_l2access_g ? lsu_ld_sec_hit_wy_g[1:0] :
// (dc_direct_map ? lsu_ldst_va_way_g[1:0] : lsu_dcache_rand[1:0]) ;
//
//assign lsu_lmq_pkt_way_g[1:0] =
//(ldst_dbl_g & st_inst_vld_unflushed & lsu_quad_asi_g) ? 2'b01 :
// casa_g ? 2'b00 : ld_way[1:0] ;
//
//assign ld_pcx_pkt_wy_g[1:0] = lsu_lmq_pkt_way_g[1:0];
wire [1:0] ld_way_mx1_g , ld_way_mx2_g , ld_way_mx2_w2;
assign ld_way_mx1_g[1:0] =
lsu_way_hit_or ? lsu_encd_way_hit[1:0]:
(dc_direct_map ? lsu_ldst_va_way_g[1:0] : lsu_dcache_rand[1:0]) ;
assign ld_way_mx2_g[1:0] =
//(ldst_dbl_g & st_inst_vld_unflushed & lsu_quad_asi_g) ? 2'b01 : //quad st, obsolete
casa_g ? 2'b00 : ld_way_mx1_g[1:0] ;
dff_s #(2) ff_ld_way_mx2_w2 (
.din (ld_way_mx2_g[1:0]),
.q (ld_way_mx2_w2[1:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire [1:0] lsu_lmq_pkt_way_w2;
assign lsu_lmq_pkt_way_w2[1:0] = lsu_ld_sec_hit_l2access_w2 ? lsu_ld_sec_hit_wy_w2[1:0] :
ld_way_mx2_w2[1:0];
//bug2705 - add mx for way in w2-cycle
wire [1:0] lmq0_pcx_pkt_way_tmp, lmq1_pcx_pkt_way_tmp, lmq2_pcx_pkt_way_tmp, lmq3_pcx_pkt_way_tmp ;
assign lmq0_pcx_pkt_way[1:0] = ld0_spec_pick_vld_w2 ? lsu_lmq_pkt_way_w2[1:0] : lmq0_pcx_pkt_way_tmp[1:0] ;
assign lmq1_pcx_pkt_way[1:0] = ld1_spec_pick_vld_w2 ? lsu_lmq_pkt_way_w2[1:0] : lmq1_pcx_pkt_way_tmp[1:0] ;
assign lmq2_pcx_pkt_way[1:0] = ld2_spec_pick_vld_w2 ? lsu_lmq_pkt_way_w2[1:0] : lmq2_pcx_pkt_way_tmp[1:0] ;
assign lmq3_pcx_pkt_way[1:0] = ld3_spec_pick_vld_w2 ? lsu_lmq_pkt_way_w2[1:0] : lmq3_pcx_pkt_way_tmp[1:0] ;
wire qword_access0,qword_access1,qword_access2,qword_access3;
// Extend by 1-b to add support for 3rd size bit for iospace.
// move the flops from qdp1 to qctl1
dffe_s #(2) ff_lmq0_pcx_pkt_way (
.din (lsu_lmq_pkt_way_w2[1:0]),
.q (lmq0_pcx_pkt_way_tmp[1:0]),
.en (lmq_enable_w2[0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s #(2) ff_lmq1_pcx_pkt_way (
.din (lsu_lmq_pkt_way_w2[1:0]),
.q (lmq1_pcx_pkt_way_tmp[1:0]),
.en (lmq_enable_w2[1]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s #(2) ff_lmq2_pcx_pkt_way (
.din (lsu_lmq_pkt_way_w2[1:0]),
.q (lmq2_pcx_pkt_way_tmp[1:0]),
.en (lmq_enable_w2[2]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s #(2) ff_lmq3_pcx_pkt_way (
.din (lsu_lmq_pkt_way_w2[1:0]),
.q (lmq3_pcx_pkt_way_tmp[1:0]),
.en (lmq_enable_w2[3]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Q Word Access to IO
dffe_s ff_lmq0_qw (
.din (lsu_quad_word_access_g),
.q (qword_access0),
.en (lmq_enable[0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s ff_lmq1_qw (
.din (lsu_quad_word_access_g),
.q (qword_access1),
.en (lmq_enable[1]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s ff_lmq2_qw(
.din (lsu_quad_word_access_g),
.q (qword_access2),
.en (lmq_enable[2]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s ff_lmq3_qw (
.din (lsu_quad_word_access_g),
.q (qword_access3),
.en (lmq_enable[3]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign lsu_pcx_rq_sz_b3 =
(ld0_pcx_rq_sel_d1 & qword_access0) |
(ld1_pcx_rq_sel_d1 & qword_access1) |
(ld2_pcx_rq_sel_d1 & qword_access2) |
(ld3_pcx_rq_sel_d1 & qword_access3) ;
//=================================================================================================
// SHADOW SCAN
//=================================================================================================
// Monitors outstanding loads. This would hang a thread.
assign lsu_sscan_data[3:0] =
{ld0_pcx_rq_vld, ld1_pcx_rq_vld , ld2_pcx_rq_vld , ld3_pcx_rq_vld} ;
// Monitors outstanding loads. This would hang issue from stb
assign lsu_sscan_data[7:4] =
{st0_pcx_rq_vld, st1_pcx_rq_vld, st2_pcx_rq_vld, st3_pcx_rq_vld} ;
assign lsu_sscan_data[8] = imiss_pcx_rq_vld ; // imiss
assign lsu_sscan_data[9] = strm_pcx_rq_vld ; // strm
assign lsu_sscan_data[10] = fwdpkt_rq_vld ; // fwd rply/rq
assign lsu_sscan_data[11] = intrpt_pcx_rq_vld ; // intrpt
assign lsu_sscan_data[12] = fpop_pcx_rq_vld ; // fpop
//=================================================================================================
// QDP1 selects
//=================================================================================================
wire [3:0] dfq_byp_tid_sel;
assign dfq_byp_tid_sel[0] = (lsu_dfq_byp_tid[1:0]==2'b00);
assign dfq_byp_tid_sel[1] = (lsu_dfq_byp_tid[1:0]==2'b01);
assign dfq_byp_tid_sel[2] = (lsu_dfq_byp_tid[1:0]==2'b10);
assign dfq_byp_tid_sel[3] = (lsu_dfq_byp_tid[1:0]==2'b11);
//assign dfq_byp_tid__sel[3] = ~|(lsu_dfq_byp_d1_sel[2:0]);
wire [3:0] lsu_dfq_byp_tid_d1_sel_tmp ;
dffe_s #(4) dfq_byp_tid_sel_ff (
.din (dfq_byp_tid_sel[3:0]),
.q (lsu_dfq_byp_tid_d1_sel_tmp[3:0]),
.en (dfq_byp_ff_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//11/21/03 - add rst_tri_en to lsu_dfq_byp_tid_d1_sel[3:0] going to qdp1 as dfq_byp_sel[3:0]
assign lsu_dfq_byp_tid_d1_sel[2:0] = lsu_dfq_byp_tid_d1_sel_tmp[2:0] & {3{~rst_tri_en}};
assign lsu_dfq_byp_tid_d1_sel[3] = lsu_dfq_byp_tid_d1_sel_tmp[3] | rst_tri_en;
//=================================================================================================
// INST_VLD_W GENERATION
//=================================================================================================
wire [1:0] thrid_m, thrid_g ;
dff_s #(2) stgm_thrid (
.din (ifu_tlu_thrid_e[1:0]),
.q (thrid_m[1:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(2) stgg_thrid (
.din (thrid_m[1:0]),
.q (thrid_g[1:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire flush_w_inst_vld_m ;
wire lsu_inst_vld_w,lsu_inst_vld_tmp ;
wire other_flush_pipe_w ;
wire qctl1_flush_pipe_w;
assign flush_w_inst_vld_m =
ifu_tlu_inst_vld_m &
~(qctl1_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
dff_s stgw_ivld (
.din (flush_w_inst_vld_m),
.q (lsu_inst_vld_tmp),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign other_flush_pipe_w = tlu_early_flush_pipe2_w | (lsu_ttype_vld_m2 & lsu_inst_vld_tmp);
assign qctl1_flush_pipe_w = other_flush_pipe_w | ifu_lsu_flush_w ;
assign lsu_inst_vld_w = lsu_inst_vld_tmp & ~qctl1_flush_pipe_w ;
//=================================================================================================
// SECONDARY VS. PRIMARY LOADS
//=================================================================================================
// An incoming load can hit can match addresses with an outstanding load request
// from another thread. In this case, the secondary load must wait until the primary
// load returns and then it will bypass (but not fill). There can only be one primary
// load but multiple secondary loads. The secondary loads will not enter the dfq.
// The primary load will however be recirculated until all secondary loads have bypassed.
// Could have multiple secondary hits. Only one thread can be chosen
// as primary though.
//An incoming load can match addresses with any outstanding load request from other threads.
//can be multiple hits
// timing fix: 5/19/03: move secondary hit way generation to w2
//
//assign ld0_sec_hit_g = ld_sec_hit_thrd0 & ld0_unfilled ;
//assign ld1_sec_hit_g = ld_sec_hit_thrd1 & ld1_unfilled ;
//assign ld2_sec_hit_g = ld_sec_hit_thrd2 & ld2_unfilled ;
//assign ld3_sec_hit_g = ld_sec_hit_thrd3 & ld3_unfilled ;
//
//
// Fix for Bug1606
//assign lsu_ld_sec_hit_l2access_g =
// ld0_sec_hit_g | ld1_sec_hit_g | ld2_sec_hit_g | ld3_sec_hit_g ;
//
//phase 2
//since can be multiple hits, it isn't one-hot mux, but fix priority-sel mux
//assign lsu_ld_sec_hit_wy_g[1:0] =
// ld0_sec_hit_g ? ld0_unfilled_wy[1:0] :
// ld1_sec_hit_g ? ld1_unfilled_wy[1:0] :
// ld2_sec_hit_g ? ld2_unfilled_wy[1:0] :
// ld3_sec_hit_g ? ld3_unfilled_wy[1:0] : 2'bxx ;
wire ld_sec_hit_thrd0_w2,ld_sec_hit_thrd1_w2,ld_sec_hit_thrd2_w2,ld_sec_hit_thrd3_w2;
dff_s #(4) ff_ld_sec_hit_thrd0to3_d1 (
.din ({ld_sec_hit_thrd0,ld_sec_hit_thrd1,ld_sec_hit_thrd2,ld_sec_hit_thrd3}),
.q ({ld_sec_hit_thrd0_w2,ld_sec_hit_thrd1_w2,ld_sec_hit_thrd2_w2,ld_sec_hit_thrd3_w2}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign ld0_sec_hit_w2 = ld_sec_hit_thrd0_w2 & ld0_unfilled ;
assign ld1_sec_hit_w2 = ld_sec_hit_thrd1_w2 & ld1_unfilled ;
assign ld2_sec_hit_w2 = ld_sec_hit_thrd2_w2 & ld2_unfilled ;
assign ld3_sec_hit_w2 = ld_sec_hit_thrd3_w2 & ld3_unfilled ;
// Fix for Bug1606
assign lsu_ld_sec_hit_l2access_w2 =
ld0_sec_hit_w2 | ld1_sec_hit_w2 | ld2_sec_hit_w2 | ld3_sec_hit_w2 ;
//phase 2
//since can be multiple hits, it isn't one-hot mux, but fix priority-sel mux
assign lsu_ld_sec_hit_wy_w2[1:0] =
ld0_sec_hit_w2 ? ld0_unfilled_wy[1:0] :
ld1_sec_hit_w2 ? ld1_unfilled_wy[1:0] :
ld2_sec_hit_w2 ? ld2_unfilled_wy[1:0] :
ld3_sec_hit_w2 ? ld3_unfilled_wy[1:0] : 2'bxx ;
//dff #(4) stgm_dbypsel (
// .din (dfq_byp_sel[3:0]),
// .q (dfq_byp_sel_m[3:0]),
// .clk (clk),
// .se (1'b0), .si (), .so ()
// );
//dff #(4) stgg_dbypsel (
// .din (dfq_byp_sel_m[3:0]),
// .q (dfq_byp_sel_g[3:0]),
// .clk (clk),
// .se (1'b0), .si (), .so ()
// );
// select g-stage lmq source.
// Selects for lmq contents shared by fill/hit and alternate sources such as ldxa/raw.
// Is qualification of dfq_byp_sel_g by ld_thrd_byp_sel necessary ???
wire [3:0] lmq_byp_misc_sel_e ;
assign lmq_byp_misc_sel_e[0] = ld_thrd_byp_sel_e[0] | // select for ldxa/raw.
dfq_byp_sel[0] ; // select for dfq.
assign lmq_byp_misc_sel_e[1] = ld_thrd_byp_sel_e[1] | // select for ldxa/raw.
dfq_byp_sel[1] ; // select for dfq.
assign lmq_byp_misc_sel_e[2] = ld_thrd_byp_sel_e[2] | // select for ldxa/raw.
dfq_byp_sel[2] ; // select for dfq.
assign lmq_byp_misc_sel_e[3] = ~|lmq_byp_misc_sel_e[2:0];
//ld_thrd_byp_sel_e[3] | // select for ldxa/raw.
//dfq_byp_sel[3] ; // select for dfq.
/*
assign lmq_byp_misc_sel_e[0] = ld_thrd_byp_sel_e[0] | // select for ldxa/raw.
(dfq_byp_sel[0] & ~ld_thrd_byp_sel_e[0]) ; // select for dfq.
assign lmq_byp_misc_sel_e[1] = ld_thrd_byp_sel_e[1] | // select for ldxa/raw.
(dfq_byp_sel[1] & ~ld_thrd_byp_sel_e[1]) ; // select for dfq.
assign lmq_byp_misc_sel_e[2] = ld_thrd_byp_sel_e[2] | // select for ldxa/raw.
(dfq_byp_sel[2] & ~ld_thrd_byp_sel_e[2]) ; // select for dfq.
assign lmq_byp_misc_sel_e[3] = ld_thrd_byp_sel_e[3] | // select for ldxa/raw.
(dfq_byp_sel[3] & ~ld_thrd_byp_sel_e[3]) ; // select for dfq.
*/
// M-Stage
//10/27/03 - add rst_tri_en for the select - lsu_lmq_byp_misc_sel to qdp1
wire [3:0] lsu_lmq_byp_misc_sel_tmp ;
dff_s #(4) stgg_lbsel (
.din (lmq_byp_misc_sel_e[3:0]),
.q (lsu_lmq_byp_misc_sel_tmp[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign lsu_lmq_byp_misc_sel[2:0]= lsu_lmq_byp_misc_sel_tmp[2:0] & {3{~rst_tri_en}} ;
assign lsu_lmq_byp_misc_sel[3] = lsu_lmq_byp_misc_sel_tmp[3] | rst_tri_en ;
/*
assign lsu_lmq_byp_misc_sel[0] = ld_thrd_byp_sel[0] | // select for ldxa/raw.
(dfq_byp_sel_g[0] & ~ld_thrd_byp_sel[0]) ; // select for dfq.
assign lsu_lmq_byp_misc_sel[1] = ld_thrd_byp_sel[1] | // select for ldxa/raw.
(dfq_byp_sel_g[1] & ~ld_thrd_byp_sel[1]) ; // select for dfq.
assign lsu_lmq_byp_misc_sel[2] = ld_thrd_byp_sel[2] | // select for ldxa/raw.
(dfq_byp_sel_g[2] & ~ld_thrd_byp_sel[2]) ; // select for dfq.
assign lsu_lmq_byp_misc_sel[3] = ld_thrd_byp_sel[3] | // select for ldxa/raw.
(dfq_byp_sel_g[3] & ~ld_thrd_byp_sel[3]) ; // select for dfq.
*/
//=================================================================================================
// Miscellaneous Staging
//=================================================================================================
assign thread0_e = ~ifu_tlu_thrid_e[1] & ~ifu_tlu_thrid_e[0] ;
assign thread1_e = ~ifu_tlu_thrid_e[1] & ifu_tlu_thrid_e[0] ;
assign thread2_e = ifu_tlu_thrid_e[1] & ~ifu_tlu_thrid_e[0] ;
assign thread3_e = ifu_tlu_thrid_e[1] & ifu_tlu_thrid_e[0] ;
assign ld0_inst_vld_e = ld_inst_vld_e & thread0_e ;
assign ld1_inst_vld_e = ld_inst_vld_e & thread1_e ;
assign ld2_inst_vld_e = ld_inst_vld_e & thread2_e ;
assign ld3_inst_vld_e = ld_inst_vld_e & thread3_e ;
assign ldst_va_m[7:6] = lsu_ldst_va_m[7:6];
dff_s #(6) stgm_ad_m (
.din ({ld0_inst_vld_e,ld1_inst_vld_e,
ld2_inst_vld_e,ld3_inst_vld_e,ifu_lsu_ldst_fp_e,
ifu_lsu_ldst_dbl_e}),
.q ({ld0_inst_vld_m,ld1_inst_vld_m,
ld2_inst_vld_m,ld3_inst_vld_m,ldst_fp_m,
ldst_dbl_m}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(8) stgm_ad_g (
.din ({ldst_va_m[7:6],ld0_inst_vld_m,ld1_inst_vld_m,
//.din ({ldst_va_m[8:6],ld0_inst_vld_m,ld1_inst_vld_m,
ld2_inst_vld_m,ld3_inst_vld_m,ldst_fp_m,
//ld2_inst_vld_m,ld3_inst_vld_m,st_inst_vld_m,ldst_fp_m,
ldst_dbl_m}),
.q ({ldst_va_g[7:6],ld0_inst_vld_unflushed,ld1_inst_vld_unflushed,
//.q ({ldst_va_g[8:6],ld0_inst_vld_unflushed,ld1_inst_vld_unflushed,
ld2_inst_vld_unflushed,ld3_inst_vld_unflushed,
//ld2_inst_vld_unflushed,ld3_inst_vld_unflushed,st_inst_vld_unflushed,
ldst_fp_g,ldst_dbl_g}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign ld0_inst_vld_g = ld0_inst_vld_unflushed & lsu_inst_vld_w ;
assign ld1_inst_vld_g = ld1_inst_vld_unflushed & lsu_inst_vld_w ;
assign ld2_inst_vld_g = ld2_inst_vld_unflushed & lsu_inst_vld_w ;
assign ld3_inst_vld_g = ld3_inst_vld_unflushed & lsu_inst_vld_w ;
//assign st_inst_vld_g = st_inst_vld_unflushed & lsu_inst_vld_w ;
dff_s #(4) ivld_stgw2 (
.din ({ld0_inst_vld_g,ld1_inst_vld_g,ld2_inst_vld_g,ld3_inst_vld_g}),
.q ({ld0_inst_vld_w2,ld1_inst_vld_w2,ld2_inst_vld_w2,ld3_inst_vld_w2}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(4) th_stgm (
.din ({thread0_e,thread1_e,thread2_e,thread3_e}),
.q ({thread0_m,thread1_m,thread2_m,thread3_m}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(4) th_stgg (
.din ({thread0_m,thread1_m,thread2_m,thread3_m}),
.q ({thread0_g,thread1_g,thread2_g,thread3_g}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(4) th_stgw2 (
.din ({thread0_g,thread1_g,thread2_g,thread3_g}),
.q ({thread0_w2,thread1_w2,thread2_w2,thread3_w2}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//=================================================================================================
//
// IMISS PCX PKT REQ CTL
//
//=================================================================================================
// ** ifu request packet should be sent out in e-stage **
// ** Prefer not to make dfq dual-ported **
// Format of IFU pcx packet (50b) :
// b49 - valid
// b48:44 - req type
// b43:42 - rep way (for "eviction" - maintains directory consistency )
// b41:40 - mil id
// b39:0 - imiss address
// *
// destid :
// b2 - b39 of pa
// b1 - b8 of pa
// b0 - b7 of pa
// pcxpkt :
// b51 - valid
// b50 - reserved
// b49 - NC
// b48:44 - req type
// b43:42 - rep way (for "eviction" - maintains directory consistency )
// b41:40 - mil id
// b39:0 - imiss address
// IMISS REQUEST CONTROL
// Vld is reset if imiss pkt requests and request is not subsequently
// squashed and new imiss pkt unavailable.
// Request rate is 1/3 cycles.
/*dff iack_stg (
.din (imiss_pcx_rq_sel),
.q (lsu_ifu_pcxpkt_ack_d),
.clk (clk),
.se (1'b0), .si (), .so ()
); */
assign lsu_ifu_pcxpkt_ack_d = imiss_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
assign imiss_pkt_vld = ifu_lsu_pcxreq_d & ~(imiss_pcx_rq_sel_d1 | imiss_pcx_rq_sel_d2) ;
//timing fix: 5/21/03 - ifu sends destid 1 cycle early
//assign imiss_l2bnk_addr[2:0] = ifu_lsu_destid_d[2:0] ;
wire ifu_destid_en ;
assign ifu_destid_en = ~ifu_lsu_pcxreq_d | (lsu_ifu_pcxpkt_ack_d & ~ifu_lsu_pcxpkt_e_b50);
wire [2:0] ifu_destid_d;
dffe_s #(3) ff_ifu_destid_d (
.din (ifu_lsu_destid_s[2:0]),
.q (ifu_destid_d[2:0]),
.en (ifu_destid_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign imiss_l2bnk_addr[2:0] = ifu_destid_d[2:0] ;
assign imiss_l2bnk_dest[0] =
~imiss_l2bnk_addr[2] & ~imiss_l2bnk_addr[1] & ~imiss_l2bnk_addr[0] ;
assign imiss_l2bnk_dest[1] =
~imiss_l2bnk_addr[2] & ~imiss_l2bnk_addr[1] & imiss_l2bnk_addr[0] ;
assign imiss_l2bnk_dest[2] =
~imiss_l2bnk_addr[2] & imiss_l2bnk_addr[1] & ~imiss_l2bnk_addr[0] ;
assign imiss_l2bnk_dest[3] =
~imiss_l2bnk_addr[2] & imiss_l2bnk_addr[1] & imiss_l2bnk_addr[0] ;
assign imiss_l2bnk_dest[4] = imiss_l2bnk_addr[2] ;
//=================================================================================================
// FPOP PCX RQ CTL
//=================================================================================================
assign fpst_vld_m = ffu_lsu_data[80] & ffu_lsu_data[79] ;
dff_s fpst_stg (
.din (fpst_vld_m),
.q (fpst_vld_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// ffu req is never speculative as it must always begin with the queue empty
assign lsu_ffu_ack =
fpop_pcx_rq_sel_d1 | // fpop needs to wait until selected;d1 for timing
//fpop_pcx_rq_sel | // fpop needs to wait until selected
fpst_vld_g ; // fpst responds immediately.
// req_squash needs to match up with rq_sel_d1 !!!
// keep vld around for two cycles.
assign fpop_vld_reset =
(reset | fpop_pcx_rq_sel) ;
//(reset | fpop_pcx_rq_sel_d1) ;
assign fpop_vld_en = ffu_lsu_fpop_rq_vld ;
// fpop valid
dffre_s #(1) fpop_vld (
.din (ffu_lsu_fpop_rq_vld),
.q (fpop_pkt_vld_unmasked),
.rst (fpop_vld_reset), .en (fpop_vld_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// ** fpop_pkt1 should not be required.
assign fpop_pkt1 = fpop_pkt_vld_unmasked & ~fpop_pcx_rq_sel_d1 ;
assign fpop_pkt_vld = fpop_pkt_vld_unmasked ; // & ~ffu_lsu_kill_fpop_rq ;
assign fpop_atom_req = fpop_pkt1 & fpop_pcx_rq_sel ;
dff_s fpatm_stg (
.din (fpop_atom_req),
.q (fpop_atom_rq_pq),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign fpop_l2bnk_dest[4:0] = 5'b10000 ;
//=================================================================================================
// SPU PCX PKT REQ CONTROL
//=================================================================================================
// If ack is sent in a given cycle, then the earliest the spu can send
// a response is in the same cycle.
wire strm_pcx_rq_sel_d2 ;
assign lsu_spu_ldst_ack =
strm_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ; // spu request sent to pcx.
//strm_pcx_rq_sel_d1 & ~pcx_req_squash ; // spu request sent to pcx.
dff_s #(1) rqsel_d2 (
.din (strm_pcx_rq_sel_d1),
.q (strm_pcx_rq_sel_d2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire spu_ack_d1 ;
dff_s #(1) spuack_d1 (
.din (lsu_spu_ldst_ack),
.q (spu_ack_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(2) ff_spu_lsu_ldst_pckt_d1 (
.din (spu_lsu_ldst_pckt[`PCX_AD_LO+7:`PCX_AD_LO+6]),
.q (strm_l2bnk_addr[1:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Streaming does not access io space.
assign strm_l2bnk_dest[0] =
~strm_l2bnk_addr[1] & ~strm_l2bnk_addr[0] ;
assign strm_l2bnk_dest[1] =
~strm_l2bnk_addr[1] & strm_l2bnk_addr[0] ;
assign strm_l2bnk_dest[2] =
strm_l2bnk_addr[1] & ~strm_l2bnk_addr[0] ;
assign strm_l2bnk_dest[3] =
strm_l2bnk_addr[1] & strm_l2bnk_addr[0] ;
assign strm_l2bnk_dest[4] = 1'b0 ;
wire strm_pkt_vld_unmasked ;
dff_s #(1) spu_pkt_vld_d1 (
.din (spu_lsu_ldst_pckt_vld),
.q (strm_pkt_vld_unmasked),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign strm_pkt_vld =
strm_pkt_vld_unmasked & ~(strm_pcx_rq_sel_d1 | lsu_spu_ldst_ack | spu_ack_d1);
// temp = remove strming interface
//assign strm_sldst_cam_vld = 1'b0 ;
//assign strm_sld_dc_rd_vld = 1'b0 ;
//assign strm_sldst_cam_d2 = 1'b0 ;
// temp = remove strming interface
//=================================================================================================
// STORE PCX PKT REQ CONTROL
//=================================================================================================
// Stage by a cycle.
// Thread0
wire [2:1] stb0_rqtype ;
wire [2:0] stb0_rqaddr ;
dff_s #(5) stgd1_s0rq (
.din ({stb0_atm_rq_type[2:1], stb0_l2b_addr[2:0]}),
.q ({stb0_rqtype[2:1],stb0_rqaddr[2:0]}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread1
wire [2:1] stb1_rqtype ;
wire [2:0] stb1_rqaddr ;
dff_s #(5) stgd1_s1rq (
.din ({stb1_atm_rq_type[2:1], stb1_l2b_addr[2:0]}),
.q ({stb1_rqtype[2:1],stb1_rqaddr[2:0]}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread2
wire [2:1] stb2_rqtype ;
wire [2:0] stb2_rqaddr ;
dff_s #(5) stgd1_s2rq (
.din ({stb2_atm_rq_type[2:1], stb2_l2b_addr[2:0]}),
.q ({stb2_rqtype[2:1],stb2_rqaddr[2:0]}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread3
wire [2:1] stb3_rqtype ;
wire [2:0] stb3_rqaddr ;
dff_s #(5) stgd1_s3rq (
.din ({stb3_atm_rq_type[2:1], stb3_l2b_addr[2:0]}),
.q ({stb3_rqtype[2:1],stb3_rqaddr[2:0]}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire stb0_rd_for_pcx,stb1_rd_for_pcx,stb2_rd_for_pcx,stb3_rd_for_pcx ;
wire stb0_rd_for_pcx_tmp,stb1_rd_for_pcx_tmp,stb2_rd_for_pcx_tmp,stb3_rd_for_pcx_tmp ;
dff_s #(4) stgd1_rdpcx (
.din (stb_rd_for_pcx[3:0]),
.q ({stb3_rd_for_pcx_tmp,stb2_rd_for_pcx_tmp,stb1_rd_for_pcx_tmp,stb0_rd_for_pcx_tmp}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// timing fix: 5/6 - move kill qual after store pick
//assign stb0_rd_for_pcx = stb0_rd_for_pcx_tmp & ~lsu_st_pcx_rq_kill_w2[0] ;
//assign stb1_rd_for_pcx = stb1_rd_for_pcx_tmp & ~lsu_st_pcx_rq_kill_w2[1] ;
//assign stb2_rd_for_pcx = stb2_rd_for_pcx_tmp & ~lsu_st_pcx_rq_kill_w2[2] ;
//assign stb3_rd_for_pcx = stb3_rd_for_pcx_tmp & ~lsu_st_pcx_rq_kill_w2[3] ;
assign stb0_rd_for_pcx = stb0_rd_for_pcx_tmp;
assign stb1_rd_for_pcx = stb1_rd_for_pcx_tmp;
assign stb2_rd_for_pcx = stb2_rd_for_pcx_tmp;
assign stb3_rd_for_pcx = stb3_rd_for_pcx_tmp;
// STORE REQUEST CONTROL
// ** Data must come from bypass mux output.
// THREAD0
// Reads for stores will have to be made non-speculative ????
// or delay when ced bit is set such that there is no need
// to replay store.
// The size of atm_rq_type can be reduced in stb_ctl etc !!!
assign st0_pkt_vld = stb0_rd_for_pcx & ~st0_pcx_rq_sel_d1 ;
assign st0_cas_vld = ~stb0_rqtype[2] & stb0_rqtype[1] ;
// stquad not supported.
//assign st0_stq_vld = 1'b0 ;
assign st0_atomic_vld = st0_cas_vld ;
//st0_stq_vld | // stq(1)
//(~stb0_rqtype[2] & stb0_rqtype[1] & ~stb0_rqtype[0]) ; // cas(1)
assign st1_pkt_vld = stb1_rd_for_pcx & ~st1_pcx_rq_sel_d1 ;
assign st1_cas_vld = ~stb1_rqtype[2] & stb1_rqtype[1] ;
//assign st1_stq_vld = 1'b0 ;
assign st1_atomic_vld = st1_cas_vld ;
assign st2_pkt_vld = stb2_rd_for_pcx & ~st2_pcx_rq_sel_d1 ;
assign st2_cas_vld = ~stb2_rqtype[2] & stb2_rqtype[1] ;
//assign st2_stq_vld = 1'b0 ;
assign st2_atomic_vld = st2_cas_vld ;
assign st3_pkt_vld = stb3_rd_for_pcx & ~st3_pcx_rq_sel_d1 ;
assign st3_cas_vld = ~stb3_rqtype[2] & stb3_rqtype[1] ;
//assign st3_stq_vld = 1'b0 ;
assign st3_atomic_vld = st3_cas_vld ;
// Can this be based on st0_pcx_rq_vld instead to ease critical path.
//assign pcx_rq_for_stb[0] = st_pcx_rq_mhot_sel[0] ;
//assign pcx_rq_for_stb[1] = st_pcx_rq_mhot_sel[1] ;
//assign pcx_rq_for_stb[2] = st_pcx_rq_mhot_sel[2] ;
//assign pcx_rq_for_stb[3] = st_pcx_rq_mhot_sel[3] ;
assign st0_l2bnk_dest[0] =
~stb0_rqaddr[2] & ~stb0_rqaddr[1] & ~stb0_rqaddr[0] ;
assign st0_l2bnk_dest[1] =
~stb0_rqaddr[2] & ~stb0_rqaddr[1] & stb0_rqaddr[0] ;
assign st0_l2bnk_dest[2] =
~stb0_rqaddr[2] & stb0_rqaddr[1] & ~stb0_rqaddr[0] ;
assign st0_l2bnk_dest[3] =
~stb0_rqaddr[2] & stb0_rqaddr[1] & stb0_rqaddr[0] ;
assign st0_l2bnk_dest[4] = stb0_rqaddr[2] ;
assign st1_l2bnk_dest[0] =
~stb1_rqaddr[2] & ~stb1_rqaddr[1] & ~stb1_rqaddr[0] ;
assign st1_l2bnk_dest[1] =
~stb1_rqaddr[2] & ~stb1_rqaddr[1] & stb1_rqaddr[0] ;
assign st1_l2bnk_dest[2] =
~stb1_rqaddr[2] & stb1_rqaddr[1] & ~stb1_rqaddr[0] ;
assign st1_l2bnk_dest[3] =
~stb1_rqaddr[2] & stb1_rqaddr[1] & stb1_rqaddr[0] ;
assign st1_l2bnk_dest[4] = stb1_rqaddr[2] ;
assign st2_l2bnk_dest[0] =
~stb2_rqaddr[2] & ~stb2_rqaddr[1] & ~stb2_rqaddr[0] ;
assign st2_l2bnk_dest[1] =
~stb2_rqaddr[2] & ~stb2_rqaddr[1] & stb2_rqaddr[0] ;
assign st2_l2bnk_dest[2] =
~stb2_rqaddr[2] & stb2_rqaddr[1] & ~stb2_rqaddr[0] ;
assign st2_l2bnk_dest[3] =
~stb2_rqaddr[2] & stb2_rqaddr[1] & stb2_rqaddr[0] ;
assign st2_l2bnk_dest[4] = stb2_rqaddr[2] ;
assign st3_l2bnk_dest[0] =
~stb3_rqaddr[2] & ~stb3_rqaddr[1] & ~stb3_rqaddr[0] ;
assign st3_l2bnk_dest[1] =
~stb3_rqaddr[2] & ~stb3_rqaddr[1] & stb3_rqaddr[0] ;
assign st3_l2bnk_dest[2] =
~stb3_rqaddr[2] & stb3_rqaddr[1] & ~stb3_rqaddr[0] ;
assign st3_l2bnk_dest[3] =
~stb3_rqaddr[2] & stb3_rqaddr[1] & stb3_rqaddr[0] ;
assign st3_l2bnk_dest[4] = stb3_rqaddr[2] ;
//=================================================================================================
// BLK-LOAD TRACKING
//=================================================================================================
// The 64B load request is divided into 4 16B requests, i.e., 4 pcx pkts.
// The last bld request to the pcx must be marked as so.
// Only one bld can be processed at any time.
wire [1:0] bld_thrd_din;
wire [1:0] bld_thrd_dout;
wire [3:0] bld_dcd_thrd;
wire ld_03_inst_vld_g;
wire bld_pcx_rq_sel_d1;
dff_s stgg_blkasi (
.din (lsu_blk_asi_m),
.q (blk_asi_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign bld_helper_cmplt_e = lsu_fldd_vld_en & bld_dout & (
bld_dcd_thrd[0] & lsu_dfill_dcd_thrd[0] |
bld_dcd_thrd[1] & lsu_dfill_dcd_thrd[1] |
bld_dcd_thrd[2] & lsu_dfill_dcd_thrd[2] |
bld_dcd_thrd[3] & lsu_dfill_dcd_thrd[3] );
dff_s #(1) stgm_bldhlpr (
.din (bld_helper_cmplt_e),
.q (bld_helper_cmplt_m),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign lsu_bld_helper_cmplt_m = bld_helper_cmplt_m ;
dff_s #(1) stgg_bldhlpr (
.din (bld_helper_cmplt_m),
.q (bld_helper_cmplt_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire alt_space_m, alt_space_g, alt_space_w2 ;
dff_s stg_aspacem(
.din (ifu_lsu_alt_space_e),
.q (alt_space_m),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s stg_aspaceg(
.din (alt_space_m),
.q (alt_space_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s stg_aspacew2 (
.din (alt_space_g),
.q (alt_space_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// PCX bld helper issue :
// 00-1st->01-2nd->10-3rd->11-4th->00
assign bld_thrd_din[0] = ld1_inst_vld_unflushed | ld3_inst_vld_unflushed;
assign bld_thrd_din[1] = ld2_inst_vld_unflushed | ld3_inst_vld_unflushed;
assign ld_03_inst_vld_g = lsu_inst_vld_w & (
ld0_inst_vld_unflushed | ld1_inst_vld_unflushed |
ld2_inst_vld_unflushed | ld3_inst_vld_unflushed );
assign bld_g = blk_asi_g & ldst_fp_g & ldst_dbl_g & alt_space_g & ld_03_inst_vld_g ;
//~lsu_tlb_perr_ld_rq_kill_w ; // Bug 4645
wire bld_w2 ;
dff_s #(1) bldstg (
.din (bld_g),
.q (bld_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire perr_ld_rq_kill_w2 ;
wire bld_perr_kill_w2 ;
assign bld_perr_kill_w2 = bld_w2 & perr_ld_rq_kill_w2 ;
dffre_s #(2) bld_thrd (
.din (bld_thrd_din[1:0] ),
.q (bld_thrd_dout[1:0]),
.rst (bld_reset), .en (bld_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign bld_dcd_thrd[0] = ~bld_thrd_dout[1] & ~bld_thrd_dout[0];
assign bld_dcd_thrd[1] = ~bld_thrd_dout[1] & bld_thrd_dout[0];
assign bld_dcd_thrd[2] = bld_thrd_dout[1] & ~bld_thrd_dout[0];
assign bld_dcd_thrd[3] = bld_thrd_dout[1] & bld_thrd_dout[0];
//bug 2757
assign bld_pcx_rq_sel_d1 = ld0_pcx_rq_sel_d1 & bld_dcd_thrd[0] |
ld1_pcx_rq_sel_d1 & bld_dcd_thrd[1] |
ld2_pcx_rq_sel_d1 & bld_dcd_thrd[2] |
ld3_pcx_rq_sel_d1 & bld_dcd_thrd[3];
//wire bld_pcx_rq_sel_d2, bld_pcx_rq_sel;
wire bld_pcx_rq_sel;
//bug 3322
// assign bld_pcx_rq_sel = bld_pcx_rq_sel_d2 & ~pcx_req_squash_d1;
//dff #(1) ff_bld_pcx_rq_sel_d2 (
// .din (bld_pcx_rq_sel_d1),
// .q (bld_pcx_rq_sel_d2),
// .clk (clk),
// .se (1'b0), .si (), .so ()
// );
assign bld_pcx_rq_sel = (ld0_pcx_rq_sel_d2 & bld_dcd_thrd[0] |
ld1_pcx_rq_sel_d2 & bld_dcd_thrd[1] |
ld2_pcx_rq_sel_d2 & bld_dcd_thrd[2] |
ld3_pcx_rq_sel_d2 & bld_dcd_thrd[3] ) &
~pcx_req_squash_d1;
assign bld_en = bld_g | (bld_pcx_rq_sel & bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ;
assign bld_din = bld_g | bld_dout ;
assign bcnt_din[1:0] = bld_cnt[1:0] + {1'b0,(bld_pcx_rq_sel & bld_dout)} ;
// Reset by last completing bld helper.
assign bld_reset =
reset | bld_perr_kill_w2 |
(bld_rd_dout[2] & bld_rd_dout[1] & bld_rd_dout[0] & bld_helper_cmplt_g) ;
assign lsu_bld_reset = bld_reset ;
wire bld_dout_tmp ;
dffre_s #(3) bld_pcx_cnt (
.din ({bcnt_din[1:0],bld_din}),
.q ({bld_cnt[1:0], bld_dout_tmp}),
.rst (bld_reset), .en (bld_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign bld_dout = bld_dout_tmp & ~bld_perr_kill_w2 ;
// Last one allows ld-rq-vld to be reset.
assign bld_annul[0] = bld_dcd_thrd[0] & (bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ;
assign bld_annul[1] = bld_dcd_thrd[1] & (bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ;
assign bld_annul[2] = bld_dcd_thrd[2] & (bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ;
assign bld_annul[3] = bld_dcd_thrd[3] & (bld_dout & ~(bld_cnt[1] & bld_cnt[0])) ;
dff_s #(4) bannul_d1 (
.din (bld_annul[3:0]),
.q (bld_annul_d1[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Maintain rd (cpx return pkt counter). This is based on when the blk ld helper completes.
// lower 3b of rd have to start out as zero.
// Should be asserted 8 times for the entire bld.
assign bld_rd_en = (bld_helper_cmplt_m & bld_dout) ;
assign bld_rd_din[2:0] = bld_rd_dout_m[2:0] + {2'b00,(bld_helper_cmplt_m & bld_dout)} ;
//assign bld_rd_en = (bld_helper_cmplt_g & bld_dout) ;
//assign bld_rd_din[2:0] = bld_rd_dout[2:0] + {2'b00,(bld_helper_cmplt_g & bld_dout)} ;
dffre_s #(3) bld_cpx_cnt (
.din (bld_rd_din[2:0]),
.q (bld_rd_dout_m[2:0]),
.rst (bld_reset), .en (bld_rd_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(3) bld_cnt_stg (
.din (bld_rd_dout_m[2:0]),
.q (bld_rd_dout[2:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Select appr. rd. (cpx return pkt counter)
assign lsu_ffu_bld_cnt_w[2:0] = bld_rd_dout[2:0] ;
assign lsu_bld_cnt_m[2:0] = bld_rd_dout_m[2:0] ;
// pcx pkt address cntrl.
wire [1:0] addr_b54 ;
assign addr_b54[1:0] = bld_cnt[1:0];
/*wire bld_rq_w2 ;
assign bld_rq_w2 = bld_dout; */
dff_s #(2) blkrq_d1 (
.din ({addr_b54[1:0]}),
.q ({lsu_bld_rq_addr[1:0]}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign lsu_bld_pcx_rq = bld_pcx_rq_sel_d1 & bld_dout ;
/*dff #(3) blkrq_d1 (
.din ({addr_b54[1:0],bld_rq_w2}),
.q ({lsu_bld_rq_addr[1:0],lsu_bld_pcx_rq}),
.clk (clk),
.se (1'b0), .si (), .so ()
);*/
//=================================================================================================
// LOAD PCX PKT REQ CONTROL
//=================================================================================================
// Staging pref.
wire pref_inst_m, pref_inst_g ;
dff_s stgm_prf (
.din (ifu_lsu_pref_inst_e),
.q (pref_inst_m),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s stgg_prf (
.din (pref_inst_m),
.q (pref_inst_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Performance Ctr Info
dff_s #(4) stgg_dmiss (
.din ({ld3_l2cache_rq,ld2_l2cache_rq,ld1_l2cache_rq,ld0_l2cache_rq}),
.q (lsu_tlu_dcache_miss_w2[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire ld0_l2cache_rq_w2, ld1_l2cache_rq_w2, ld2_l2cache_rq_w2, ld3_l2cache_rq_w2 ;
assign ld0_l2cache_rq_w2 = lsu_tlu_dcache_miss_w2[0];
assign ld1_l2cache_rq_w2 = lsu_tlu_dcache_miss_w2[1];
assign ld2_l2cache_rq_w2 = lsu_tlu_dcache_miss_w2[2];
assign ld3_l2cache_rq_w2 = lsu_tlu_dcache_miss_w2[3];
wire pref_vld0_g, pref_vld1_g, pref_vld2_g, pref_vld3_g ;
wire pref_rq_vld0_g, pref_rq_vld1_g, pref_rq_vld2_g, pref_rq_vld3_g ;
wire pref_vld_g ;
assign pref_vld_g = pref_inst_g & ~tlb_pgnum_g[39] & tlb_cam_hit_g ; // Bug 4318.
assign pref_rq_vld0_g = pref_vld_g & thread0_g & lsu_inst_vld_w ;
assign pref_rq_vld1_g = pref_vld_g & thread1_g & lsu_inst_vld_w ;
assign pref_rq_vld2_g = pref_vld_g & thread2_g & lsu_inst_vld_w ;
assign pref_rq_vld3_g = pref_vld_g & thread3_g & lsu_inst_vld_w ;
assign pref_vld0_g = pref_inst_g & thread0_g ;
assign pref_vld1_g = pref_inst_g & thread1_g ;
assign pref_vld2_g = pref_inst_g & thread2_g ;
assign pref_vld3_g = pref_inst_g & thread3_g ;
//=========================================================================================
// Shift full-raw/partial-raw logic from rw_ctl to qctl1
wire ldquad_inst_g ;
dff_s ldq_stgg (
.din (lsu_ldquad_inst_m), .q (ldquad_inst_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire io_ld,io_ld_w2 ;
assign io_ld = tlb_pgnum_g[39] ; // Bug 4362
//assign io_ld = tlb_pgnum_g[39] & ~(~tlb_pgnum_g[38] & tlb_pgnum_g[37]) ;
wire stb_not_empty ;
assign stb_not_empty =
thread0_g ? ~lsu_stb_empty[0] :
thread1_g ? ~lsu_stb_empty[1] :
thread2_g ? ~lsu_stb_empty[2] :
~lsu_stb_empty[3] ;
wire ldq_hit_g,ldq_hit_w2 ;
wire ldq_stb_cam_hit ;
assign ldq_stb_cam_hit = stb_cam_hit_bf & ldquad_inst_g ;
// Terms can be made common.
assign ldq_hit_g = ldq_stb_cam_hit ;
wire full_raw_g,partial_raw_g ;
wire full_raw_w2,partial_raw_w2 ;
assign full_raw_g = |stb_ld_full_raw[7:0] ;
assign partial_raw_g = |stb_ld_partial_raw[7:0] ;
wire stb_cam_mhit_w2 ;
wire stb_not_empty_w2 ;
dff_s #(6) stgw2_rawcond (
.din ({full_raw_g,partial_raw_g,stb_cam_mhit,ldq_hit_g,io_ld,stb_not_empty}),
.q ({full_raw_w2,partial_raw_w2,stb_cam_mhit_w2,ldq_hit_w2,io_ld_w2,
stb_not_empty_w2}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// BEGIN !!! ld_stb_full_raw_g for SAS support only !!!
//wire ld_stb_full_raw_g ;
//wire ld_stb_partial_raw_g ;
// END !!! ld_stb_full_raw_g for SAS support only !!!
assign ld_stb_full_raw_w2 =
(full_raw_w2 & ~(stb_cam_mhit_w2 | ldq_hit_w2 | io_ld_w2)) ;
//(full_raw_w2 & ~(stb_cam_mhit_w2 | ldq_hit_w2 | io_ld_w2)) ; // Bug 3624
wire ld_stb_partial_raw_w2 ;
wire stb_cam_hit_w2 ;
assign ld_stb_partial_raw_w2 =
(partial_raw_w2 | stb_cam_mhit_w2 | ldq_hit_w2 |
(io_ld_w2 & stb_not_empty_w2)) ;
//(partial_raw_w2 | stb_cam_mhit_w2 | ldq_hit_w2 | (io_ld_w2 & stb_not_empty_w2)) ;
//=========================================================================================
/*wire ld_stb_full_raw_w2 ;
dff_s #(1) stgw2_fraw (
.din (ld_stb_full_raw_g),
.q (ld_stb_full_raw_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
); */
// THREAD0 LOAD PCX REQUEST CONTROL
//=====
// For delayed ld0,1,2,3_l2cache_rq, we need to delay certain
// inputs to flops enabled by ld0,1,2,3_l2cache_rq.
wire ld0_ldbl_rq_w2 ;
wire ld1_ldbl_rq_w2 ;
wire ld2_ldbl_rq_w2 ;
wire ld3_ldbl_rq_w2 ;
// wire [1:0] ld_pcx_pkt_wy_w2 ;
wire pref_rq_vld0_w2,pref_rq_vld1_w2,pref_rq_vld2_w2,pref_rq_vld3_w2 ;
wire non_l2bnk ;
wire non_l2bnk_w2 ;
wire [7:6] ldst_va_w2 ;
dff_s #(7) stgw2_l2crqmx (
.din ({
//ld_pcx_pkt_wy_g[1:0],
pref_rq_vld0_g,pref_rq_vld1_g,pref_rq_vld2_g,pref_rq_vld3_g,
non_l2bnk,
ldst_va_g[7:6]}),
.q ({
//ld_pcx_pkt_wy_w2[1:0],
pref_rq_vld0_w2,pref_rq_vld1_w2,pref_rq_vld2_w2,pref_rq_vld3_w2,
non_l2bnk_w2,
ldst_va_w2[7:6]}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// wire [1:0] ld_pcx_pkt_wy_mx0,ld_pcx_pkt_wy_mx1,ld_pcx_pkt_wy_mx2,ld_pcx_pkt_wy_mx3 ;
wire pref_rq_vld0_mx,pref_rq_vld1_mx,pref_rq_vld2_mx,pref_rq_vld3_mx ;
wire non_l2bnk_mx0,non_l2bnk_mx1,non_l2bnk_mx2,non_l2bnk_mx3 ;
wire [7:6] ldst_va_mx0,ldst_va_mx1,ldst_va_mx2,ldst_va_mx3 ;
// timing fix: 5/19/03: move secondary hit way generation to w2
// remove ld_pcx_pkt_wy_mx[0-3] and replace w/ lsu_lmq_pkt_way_w2
// assign ld_pcx_pkt_wy_mx0[1:0] =
// ld0_ldbl_rq_w2 ? ld_pcx_pkt_wy_w2[1:0] : ld_pcx_pkt_wy_g[1:0] ;
// assign ld_pcx_pkt_wy_mx1[1:0] =
// ld1_ldbl_rq_w2 ? ld_pcx_pkt_wy_w2[1:0] : ld_pcx_pkt_wy_g[1:0] ;
// assign ld_pcx_pkt_wy_mx2[1:0] =
// ld2_ldbl_rq_w2 ? ld_pcx_pkt_wy_w2[1:0] : ld_pcx_pkt_wy_g[1:0] ;
// assign ld_pcx_pkt_wy_mx3[1:0] =
// ld3_ldbl_rq_w2 ? ld_pcx_pkt_wy_w2[1:0] : ld_pcx_pkt_wy_g[1:0] ;
assign pref_rq_vld0_mx =
ld0_ldbl_rq_w2 ? pref_rq_vld0_w2 : pref_rq_vld0_g ;
assign pref_rq_vld1_mx =
ld1_ldbl_rq_w2 ? pref_rq_vld1_w2 : pref_rq_vld1_g ;
assign pref_rq_vld2_mx =
ld2_ldbl_rq_w2 ? pref_rq_vld2_w2 : pref_rq_vld2_g ;
assign pref_rq_vld3_mx =
ld3_ldbl_rq_w2 ? pref_rq_vld3_w2 : pref_rq_vld3_g ;
assign non_l2bnk_mx0 =
ld0_ldbl_rq_w2 ? non_l2bnk_w2 : non_l2bnk ;
assign non_l2bnk_mx1 =
ld1_ldbl_rq_w2 ? non_l2bnk_w2 : non_l2bnk ;
assign non_l2bnk_mx2 =
ld2_ldbl_rq_w2 ? non_l2bnk_w2 : non_l2bnk ;
assign non_l2bnk_mx3 =
ld3_ldbl_rq_w2 ? non_l2bnk_w2 : non_l2bnk ;
//timing fix: 10/13/03 - ldst_va_mx[0-3] is used in the same cycle 'cos of perf bug fix-bug2705
// this delays the ld request valid which in turn delays pcx_rq_for_stb
// fix is to isolate this mux and the following l2bank addr mux from ld?_ldbl_rq_w2;
// use ld[0-3]_inst_vld_w2 instead of ld[0-3]_ldbl_rq_w2 as select
assign ldst_va_mx0[7:6] =
ld0_inst_vld_w2 ? ldst_va_w2[7:6] : ldst_va_g[7:6] ;
assign ldst_va_mx1[7:6] =
ld1_inst_vld_w2 ? ldst_va_w2[7:6] : ldst_va_g[7:6] ;
assign ldst_va_mx2[7:6] =
ld2_inst_vld_w2 ? ldst_va_w2[7:6] : ldst_va_g[7:6] ;
assign ldst_va_mx3[7:6] =
ld3_inst_vld_w2 ? ldst_va_w2[7:6] : ldst_va_g[7:6] ;
//=====
wire atomic_g ;
assign atomic_g = casa_g | lsu_swap_g | lsu_ldstub_g ;
wire dbl_force_l2access_g;
wire dbl_force_l2access_w2;
assign dbl_force_l2access_g = ldst_dbl_g & ~(ldst_fp_g & ~(alt_space_g & blk_asi_g));
dff_s #(2) stgw2_atm (
.din ({atomic_g, dbl_force_l2access_g}),
.q ({atomic_w2,dbl_force_l2access_w2}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(1) stgw2_perrkill (
.din (lsu_tlb_perr_ld_rq_kill_w),
.q (perr_ld_rq_kill_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire asi_internal_g,asi_internal_w2;
dff_s #(1) stgg_intasi (
.din (asi_internal_m),
.q (asi_internal_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(1) stgw2_intasi (
.din (asi_internal_g),
.q (asi_internal_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire ld0_l2cache_rq_kill ;
assign ld0_l2cache_rq_kill =
ld0_inst_vld_w2 & ((ld_stb_full_raw_w2 & ~dbl_force_l2access_w2) | perr_ld_rq_kill_w2) ;
// full-raw which looks like partial
assign ld0_ldbl_rq_w2 =
((ld_stb_full_raw_w2 & dbl_force_l2access_w2) | ld_stb_partial_raw_w2)
& ~atomic_w2 & ~perr_ld_rq_kill_w2 & ~(asi_internal_w2 & alt_space_w2)
& ld0_inst_vld_w2 ;
//bug:2877 - dtag parity error 2nd packet request; dont reset if dtag parity error 2nd pkt valid
// dtag error is reset 1 cycle after 1st pkt sent
//----------------------------------------------------------------------------------------------------------
// | 1 | 2 | 3 | 4 | 5 | 6 |
// spc_pcx_rq_pq=1 ld_err-pkt1 spc_pcx_rq_pq=1 ld_err-pkt2
// ld0_vld_reset=0 pick 2nd pkt
// error_rst=1
//----------------------------------------------------------------------------------------------------------
wire [3:0] dtag_perr_pkt2_vld_d1 ;
assign ld0_vld_reset =
(reset | (ld0_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld0_inst_vld_g | bld_annul_d1[0] | dtag_perr_pkt2_vld_d1[0]))) |
ld0_l2cache_rq_kill ;
//(reset | (ld0_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld0_inst_vld_g | bld_annul_d1[0]))) |
// The equation for partial raw has redundancy !! Change it.
// prefetch will not bypass from stb
/* prim vs sec phase 2 change
assign ld0_l2cache_rq =
(((lsu_ld_miss_g & ~ld_stb_full_raw_g & ~ld_sec_hit_g & ~ldxa_internal) |
((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g | (ld_stb_full_raw_g & ldst_dbl_g))))
& ~atomic_g & ld0_inst_vld_g) |
| (pref_inst_g & tlb_cam_hit_g & thread0_g) ;
*/
wire ld0_l2cache_rq_g;
assign ld0_l2cache_rq_g =
(((lsu_ld_miss_g & ~ldxa_internal))
//((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g)))
& ~atomic_g & ld0_inst_vld_g)
| pref_rq_vld0_g;
assign ld0_l2cache_rq = ld0_l2cache_rq_g | ld0_ldbl_rq_w2 ;
wire ld0_pkt_vld_unmasked ;
wire ld1_pkt_vld_unmasked ;
wire ld2_pkt_vld_unmasked ;
wire ld3_pkt_vld_unmasked ;
// ld valid until request made.
wire pref_rq_vld0;
dffre_s #(2) ld0_vld (
.din ({ld0_l2cache_rq, pref_rq_vld0_mx} ),
.q ({ld0_pkt_vld_unmasked, pref_rq_vld0}),
.rst (ld0_vld_reset), .en (ld0_l2cache_rq),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// bug2705 - speculative pick in w-cycle -begin
// dbl_force_l2access_g is set for ldd(f),std(f),ldq,stq
//perf fix: 7/29/03 - kill spec vld if other thread non-spec valids are set
//timing fix: 8/29/03 - flop atomic_m and ldxa_internal_m from dctl for spec req
wire atomic_or_ldxa_internal_rq_m ;
assign atomic_or_ldxa_internal_rq_m = atomic_m | lda_internal_m ;
dff_s #(1) ff_atomic_or_ldxa_internal_rq_g (
.din (atomic_or_ldxa_internal_rq_m),
.q (atomic_or_ldxa_internal_rq_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire ld0_spec_vld_g ;
assign ld0_spec_vld_g = ld0_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g &
~atomic_or_ldxa_internal_rq_g &
~(ld1_pkt_vld_unmasked | ld2_pkt_vld_unmasked | ld3_pkt_vld_unmasked);
//assign ld0_spec_vld_g = ld0_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g ;
dff_s #(1) ff_ld0_spec_pick_vld_w2 (
.din (ld0_spec_pick_vld_g),
.q (ld0_spec_pick_vld_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// kill packet valid if spec req is picked in w and stb hits in w2
// cannot use ld0_ldbl_rawp_en_w2 because it is late signal instead use ld0_ldbl_rq_w2
//timing fix: 7/21/03 - kill pkt vld if spec pick in w-cycle was to non$ address
//timing fix: 8/6/03 - kill pkt_vld if ld?_l2cache_rq_g=0 in w-cycle but spec_pick=1
wire ld0_pkt_vld_tmp ;
//bug 3964 - replace ld0_pkt_vld_unmasked w/ ld0_l2cache_rq_w2
//assign lsu_ld0_spec_vld_kill_w2 = ld0_spec_pick_vld_w2 & (~ld0_pkt_vld_unmasked | ld0_l2cache_rq_kill | ld0_ldbl_rq_w2 | non_l2bnk_mx0_d1) ;
assign lsu_ld0_spec_vld_kill_w2 = ld0_spec_pick_vld_w2 & (~ld0_l2cache_rq_w2 | ld0_l2cache_rq_kill | ld0_ldbl_rq_w2 | non_l2bnk_mx0_d1) ;
assign ld0_pkt_vld_tmp = ld0_pkt_vld_unmasked & ~(ld0_pcx_rq_sel_d1 | ld0_pcx_rq_sel_d2) &
~(ld0_l2cache_rq_kill | ld0_ldbl_rq_w2) &
~(pref_rq_vld0 & lsu_no_spc_pref[0]) ; // prefetch pending
assign ld0_pkt_vld = ld0_pkt_vld_tmp | ld0_spec_vld_g ;
// bug2705 - speculative pick in w-cycle -end
//assign ld0_pkt_vld = ld0_pkt_vld_unmasked & ~ld0_pcx_rq_sel_d1 ;
assign ld0_fill_reset = reset | (lsu_dfq_ld_vld & lsu_dcfill_active_e & dfq_byp_sel[0]) ;
dff_s #(4) stgm_lduwyd1 (
.din ({ld0_fill_reset,ld1_fill_reset,ld2_fill_reset,ld3_fill_reset}),
.q ({ld0_fill_reset_d1,ld1_fill_reset_d1,ld2_fill_reset_d1,ld3_fill_reset_d1}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(4) stgm_lduwyd2 (
.din ({ld0_fill_reset_d1,ld1_fill_reset_d1,ld2_fill_reset_d1,ld3_fill_reset_d1}),
.q ({ld0_fill_reset_d2_tmp,ld1_fill_reset_d2_tmp,ld2_fill_reset_d2_tmp,ld3_fill_reset_d2_tmp}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire ld0_l2cache_rq_w2_tmp;
wire ld0_l2cache_rq_g_tmp;
assign ld0_l2cache_rq_g_tmp = ld0_l2cache_rq_g & ~pref_inst_g ;
dff_s #(1) ff_ld0_l2cache_rq_w2 (
.din (ld0_l2cache_rq_g_tmp),
.q (ld0_l2cache_rq_w2_tmp),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//wire ld0_unfilled_en ;
//assign ld0_unfilled_en = ld0_l2cache_rq & ~pref_inst_g ;
wire ld0_unfilled_wy_en ;
assign ld0_unfilled_wy_en = ld0_l2cache_rq_w2_tmp | ld0_ldbl_rq_w2 ;
wire ld0_l2cache_rq_tmp;
assign ld0_l2cache_rq_tmp = ld0_unfilled_wy_en & ~ld0_l2cache_rq_kill;
// ld valid until fill occur.
dffre_s #(1) ld0out_state (
//.din (ld0_l2cache_rq),
.din (ld0_l2cache_rq_tmp),
.q (ld0_unfilled_tmp),
.rst (ld0_fill_reset_d2), .en (ld0_unfilled_wy_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffre_s #(2) ld0out_state_way (
//.din (ld_pcx_pkt_wy_mx0[1:0]}),
.din (lsu_lmq_pkt_way_w2[1:0]),
.q (ld0_unfilled_wy[1:0]),
.rst (ld0_fill_reset_d2), .en (ld0_unfilled_wy_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign ld0_fill_reset_d2 = ld0_fill_reset_d2_tmp | ld0_l2cache_rq_kill ;
//assign ld0_unfilled = ld0_unfilled_tmp & ~ld0_l2cache_rq_kill ;
assign ld0_unfilled = ld0_unfilled_tmp ;
//bug3516
//assign non_l2bnk = tlb_pgnum_g[39] & tlb_pgnum_g[38] ;
assign non_l2bnk = tlb_pgnum_g[39] & ~(~tlb_pgnum_g[38] & tlb_pgnum_g[37]) ;
// ld l2bank address
dffe_s #(3) ld0_l2bnka (
.din ({non_l2bnk_mx0,ldst_va_mx0[7:6]}),
.q (ld0_l2bnk_addr[2:0]),
.en (ld0_l2cache_rq),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug2705 - add byp for address to be available in w-cycle
//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps)
// this will cause timing paths in spec pick in w-cycle; hence assume $able access for
// spec pick and kill pkt vld in w2 if non_l2bnk_mx0=1 (non$ access)
wire [2:0] ld0_l2bnk_addr_mx ;
assign ld0_l2bnk_addr_mx[2:0] = ld0_pkt_vld_unmasked ? ld0_l2bnk_addr[2:0] :
{1'b0,ldst_va_mx0[7:6]} ; // assume $able access for spec pick
//assign ld0_l2bnk_addr_mx[2:0] = (ld0_inst_vld_unflushed & lsu_inst_vld_tmp) ?
// {1'b0,ldst_va_mx0[7:6]} : // assume $able access for spec pick
// //{non_l2bnk_mx0,ldst_va_mx0[7:6]} :
// ld0_l2bnk_addr[2:0] ;
//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps)
// this will cause timing paths in spec pick in w-cycle; hence assume $able access for
// spec pick and kill pkt vld in w2
dff_s #(1) ff_non_l2bnk_mx0_d1 (
.din (non_l2bnk_mx0),
.q (non_l2bnk_mx0_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug2705 - change ld0_l2bnk_addr[2:0] to ld0_l2bnk_addr_mx[2:0]
assign ld0_l2bnk_dest[0] = ~ld0_l2bnk_addr_mx[2] & ~ld0_l2bnk_addr_mx[1] & ~ld0_l2bnk_addr_mx[0] ;
assign ld0_l2bnk_dest[1] = ~ld0_l2bnk_addr_mx[2] & ~ld0_l2bnk_addr_mx[1] & ld0_l2bnk_addr_mx[0] ;
assign ld0_l2bnk_dest[2] = ~ld0_l2bnk_addr_mx[2] & ld0_l2bnk_addr_mx[1] & ~ld0_l2bnk_addr_mx[0] ;
assign ld0_l2bnk_dest[3] = ~ld0_l2bnk_addr_mx[2] & ld0_l2bnk_addr_mx[1] & ld0_l2bnk_addr_mx[0] ;
assign ld0_l2bnk_dest[4] = ld0_l2bnk_addr_mx[2] ;
// THREAD1 LOAD PCX REQUEST CONTROL
wire ld1_l2cache_rq_kill ;
assign ld1_l2cache_rq_kill =
ld1_inst_vld_w2 & ((ld_stb_full_raw_w2 & ~dbl_force_l2access_w2) | perr_ld_rq_kill_w2) ;
// full-raw which looks like partial
assign ld1_ldbl_rq_w2 =
((ld_stb_full_raw_w2 & dbl_force_l2access_w2) | ld_stb_partial_raw_w2)
& ~atomic_w2 & ~perr_ld_rq_kill_w2 & ~(asi_internal_w2 & alt_space_w2) &
ld1_inst_vld_w2 ;
assign ld1_vld_reset =
(reset | (ld1_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld1_inst_vld_g | bld_annul_d1[1] | dtag_perr_pkt2_vld_d1[1]))) |
ld1_l2cache_rq_kill ;
//(reset | (ld1_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld1_inst_vld_g | bld_annul_d1[1]))) | // bug2877
//(reset | (ld1_pcx_rq_sel_d1 & ~(pcx_req_squash | ld1_inst_vld_g | bld_annul[1]))) ;
wire ld1_l2cache_rq_g;
assign ld1_l2cache_rq_g =
(((lsu_ld_miss_g & ~ldxa_internal))
//((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g))) // ldst_dbl always rqs
& ~atomic_g & ld1_inst_vld_g)
| pref_rq_vld1_g ;
assign ld1_l2cache_rq = ld1_l2cache_rq_g | ld1_ldbl_rq_w2 ;
// ld valid
wire pref_rq_vld1;
dffre_s #(2) ld1_vld (
.din ({ld1_l2cache_rq, pref_rq_vld1_mx}),
.q ({ld1_pkt_vld_unmasked, pref_rq_vld1}),
.rst (ld1_vld_reset), .en (ld1_l2cache_rq),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// bug2705 - speculative pick in w-cycle-begin
wire ld1_spec_vld_g ;
assign ld1_spec_vld_g = ld1_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g &
~atomic_or_ldxa_internal_rq_g &
~(ld0_pkt_vld_unmasked | ld2_pkt_vld_unmasked | ld3_pkt_vld_unmasked);
//assign ld1_spec_vld_g = ld1_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g ;
dff_s #(1) ff_ld1_spec_pick_vld_w2 (
.din (ld1_spec_pick_vld_g),
.q (ld1_spec_pick_vld_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// kill packet valid if spec req is picked in w and stb hits in w2
wire ld1_pkt_vld_tmp ;
assign lsu_ld1_spec_vld_kill_w2 = ld1_spec_pick_vld_w2 & (~ld1_l2cache_rq_w2 | ld1_l2cache_rq_kill | ld1_ldbl_rq_w2 | non_l2bnk_mx1_d1) ;
assign ld1_pkt_vld_tmp = ld1_pkt_vld_unmasked & ~(ld1_pcx_rq_sel_d1 | ld1_pcx_rq_sel_d2) &
~(ld1_l2cache_rq_kill | ld1_ldbl_rq_w2) &
~(pref_rq_vld1 & lsu_no_spc_pref[1]) ;
assign ld1_pkt_vld = ld1_pkt_vld_tmp | ld1_spec_vld_g ;
// bug2705 - speculative pick in w-cycle-end
//assign ld1_pkt_vld = ld1_pkt_vld_unmasked & ~ld1_pcx_rq_sel_d1 ;
assign ld1_fill_reset = reset | (lsu_dfq_ld_vld & lsu_dcfill_active_e & dfq_byp_sel[1]) ;
wire ld1_l2cache_rq_g_tmp;
wire ld1_l2cache_rq_w2_tmp;
assign ld1_l2cache_rq_g_tmp = ld1_l2cache_rq_g & ~pref_inst_g ;
dff_s #(1) ff_ld1_l2cache_rq_w2 (
.din (ld1_l2cache_rq_g_tmp),
.q (ld1_l2cache_rq_w2_tmp),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//wire ld1_unfilled_en ;
//assign ld1_unfilled_en = ld1_l2cache_rq & ~pref_inst_g ;
wire ld1_unfilled_wy_en ;
assign ld1_unfilled_wy_en = ld1_l2cache_rq_w2_tmp | ld1_ldbl_rq_w2 ;
wire ld1_l2cache_rq_tmp;
assign ld1_l2cache_rq_tmp = ld1_unfilled_wy_en & ~ld1_l2cache_rq_kill;
// ld valid until fill occur.
dffre_s #(1) ld1out_state (
//.din (ld1_l2cache_rq),
.din (ld1_l2cache_rq_tmp),
.q (ld1_unfilled_tmp),
.rst (ld1_fill_reset_d2), .en (ld1_unfilled_wy_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffre_s #(2) ld1out_state_way (
//.din (ld_pcx_pkt_wy_mx1[1:0]),
.din (lsu_lmq_pkt_way_w2[1:0]),
.q (ld1_unfilled_wy[1:0]),
.rst (ld1_fill_reset_d2), .en (ld1_unfilled_wy_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign ld1_fill_reset_d2 = ld1_fill_reset_d2_tmp | ld1_l2cache_rq_kill ;
//assign ld1_unfilled = ld1_unfilled_tmp & ~ld1_l2cache_rq_kill ;
assign ld1_unfilled = ld1_unfilled_tmp ;
// ld l2bank address
dffe_s #(3) ld1_l2bnka (
.din ({non_l2bnk_mx1,ldst_va_mx1[7:6]}),
.q (ld1_l2bnk_addr[2:0]),
.en (ld1_l2cache_rq),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug2705 - add byp for address to be available in w-cycle
//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps)
// this will cause timing paths in spec pick in w-cycle; hence assume $able access for
// spec pick and kill pkt vld in w2 if non_l2bnk_mx0=1 (non$ access)
wire [2:0] ld1_l2bnk_addr_mx ;
assign ld1_l2bnk_addr_mx[2:0] = ld1_pkt_vld_unmasked ? ld1_l2bnk_addr[2:0] :
{1'b0,ldst_va_mx1[7:6]} ;
//assign ld1_l2bnk_addr_mx[2:0] = (ld1_inst_vld_unflushed & lsu_inst_vld_tmp) ?
// {1'b0,ldst_va_mx1[7:6]} :
// //{non_l2bnk_mx1,ldst_va_mx1[7:6]} :
// ld1_l2bnk_addr[2:0] ;
//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps)
// this will cause timing paths in spec pick in w-cycle; hence assume $able access for
// spec pick and kill pkt vld in w2
dff_s #(1) ff_non_l2bnk_mx1_d1 (
.din (non_l2bnk_mx1),
.q (non_l2bnk_mx1_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug2705 - change ld1_l2bnk_addr[2:0] to ld1_l2bnk_addr_mx[2:0]
assign ld1_l2bnk_dest[0] = ~ld1_l2bnk_addr_mx[2] & ~ld1_l2bnk_addr_mx[1] & ~ld1_l2bnk_addr_mx[0] ;
assign ld1_l2bnk_dest[1] = ~ld1_l2bnk_addr_mx[2] & ~ld1_l2bnk_addr_mx[1] & ld1_l2bnk_addr_mx[0] ;
assign ld1_l2bnk_dest[2] = ~ld1_l2bnk_addr_mx[2] & ld1_l2bnk_addr_mx[1] & ~ld1_l2bnk_addr_mx[0] ;
assign ld1_l2bnk_dest[3] = ~ld1_l2bnk_addr_mx[2] & ld1_l2bnk_addr_mx[1] & ld1_l2bnk_addr_mx[0] ;
assign ld1_l2bnk_dest[4] = ld1_l2bnk_addr_mx[2] ;
// THREAD2 LOAD PCX REQUEST CONTROL
wire ld2_l2cache_rq_kill ;
assign ld2_l2cache_rq_kill =
ld2_inst_vld_w2 & ((ld_stb_full_raw_w2 & ~dbl_force_l2access_w2) | perr_ld_rq_kill_w2) ;
// full-raw which looks like partial
assign ld2_ldbl_rq_w2 =
((ld_stb_full_raw_w2 & dbl_force_l2access_w2) | ld_stb_partial_raw_w2)
& ~atomic_w2 & ~perr_ld_rq_kill_w2 & ~(asi_internal_w2 & alt_space_w2) &
ld2_inst_vld_w2 ;
//assign ld2_l2cache_rq_kill = ld2_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 ;
//assign ld2_ldbl_rq_w2 = ld_stb_full_raw_w2 & dbl_force_l2access_w2 & ~atomic_w2 & ld2_inst_vld_w2 ;
assign ld2_vld_reset =
(reset | (ld2_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld2_inst_vld_g | bld_annul_d1[2] | dtag_perr_pkt2_vld_d1[2]))) |
ld2_l2cache_rq_kill ;
//(reset | (ld2_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld2_inst_vld_g | bld_annul_d1[2]))) | // bug2877
//(reset | (ld2_pcx_rq_sel_d1 & ~(pcx_req_squash | ld2_inst_vld_g | bld_annul[2]))) ;
wire ld2_l2cache_rq_g;
assign ld2_l2cache_rq_g =
(((lsu_ld_miss_g & ~ldxa_internal))
//((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g))) // ldst_dbl always rqs
& ~atomic_g & ld2_inst_vld_g )
| pref_rq_vld2_g ;
assign ld2_l2cache_rq = ld2_l2cache_rq_g | ld2_ldbl_rq_w2 ;
// ld valid
wire pref_rq_vld2;
dffre_s #(2) ld2_vld (
.din ({ld2_l2cache_rq, pref_rq_vld2_mx}),
.q ({ld2_pkt_vld_unmasked, pref_rq_vld2} ),
.rst (ld2_vld_reset), .en (ld2_l2cache_rq),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// bug2705 - speculative pick in w-cycle - begin
wire ld2_spec_vld_g ;
assign ld2_spec_vld_g = ld2_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g &
~atomic_or_ldxa_internal_rq_g &
~(ld0_pkt_vld_unmasked | ld1_pkt_vld_unmasked | ld3_pkt_vld_unmasked);
//assign ld2_spec_vld_g = ld2_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g ;
dff_s #(1) ff_ld2_spec_pick_vld_w2 (
.din (ld2_spec_pick_vld_g),
.q (ld2_spec_pick_vld_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// kill packet valid if spec req is picked in w and stb hits in w2
wire ld2_pkt_vld_tmp ;
assign lsu_ld2_spec_vld_kill_w2 = ld2_spec_pick_vld_w2 & (~ld2_l2cache_rq_w2 | ld2_l2cache_rq_kill | ld2_ldbl_rq_w2 | non_l2bnk_mx2_d1) ;
assign ld2_pkt_vld_tmp = ld2_pkt_vld_unmasked & ~(ld2_pcx_rq_sel_d1 | ld2_pcx_rq_sel_d2) &
~(ld2_l2cache_rq_kill | ld2_ldbl_rq_w2) &
~(pref_rq_vld2 & lsu_no_spc_pref[2]) ;
assign ld2_pkt_vld = ld2_pkt_vld_tmp | ld2_spec_vld_g ;
// bug2705 - speculative pick in w-cycle - end
//assign ld2_pkt_vld = ld2_pkt_vld_unmasked & ~ld2_pcx_rq_sel_d1 ;
assign ld2_fill_reset = reset | (lsu_dfq_ld_vld & lsu_dcfill_active_e & dfq_byp_sel[2]) ;
wire ld2_l2cache_rq_g_tmp;
wire ld2_l2cache_rq_w2_tmp;
assign ld2_l2cache_rq_g_tmp = ld2_l2cache_rq_g & ~pref_inst_g ;
dff_s #(1) ff_ld2_l2cache_rq_w2 (
.din (ld2_l2cache_rq_g_tmp),
.q (ld2_l2cache_rq_w2_tmp),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//wire ld2_unfilled_en ;
//assign ld2_unfilled_en = ld2_l2cache_rq & ~pref_inst_g ;
wire ld2_unfilled_wy_en ;
assign ld2_unfilled_wy_en = ld2_l2cache_rq_w2_tmp | ld2_ldbl_rq_w2 ;
wire ld2_l2cache_rq_tmp;
assign ld2_l2cache_rq_tmp = ld2_unfilled_wy_en & ~ld2_l2cache_rq_kill;
// ld valid until fill occur.
dffre_s #(1) ld2out_state (
//.din (ld2_l2cache_rq),
.din (ld2_l2cache_rq_tmp),
.q (ld2_unfilled_tmp),
.rst (ld2_fill_reset_d2), .en (ld2_unfilled_wy_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffre_s #(2) ld2out_state_way (
.din (lsu_lmq_pkt_way_w2[1:0]),
.q (ld2_unfilled_wy[1:0]),
.rst (ld2_fill_reset_d2), .en (ld2_unfilled_wy_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign ld2_fill_reset_d2 = ld2_fill_reset_d2_tmp | ld2_l2cache_rq_kill ;
//assign ld2_unfilled = ld2_unfilled_tmp & ~ld2_l2cache_rq_kill ;
assign ld2_unfilled = ld2_unfilled_tmp ;
// ld l2bank address
dffe_s #(3) ld2_l2bnka (
.din ({non_l2bnk_mx2,ldst_va_mx2[7:6]}),
.q (ld2_l2bnk_addr[2:0]),
.en (ld2_l2cache_rq),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug2705 - add byp for address to be available in w-cycle
//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps)
// this will cause timing paths in spec pick in w-cycle; hence assume $able access for
// spec pick and kill pkt vld in w2 if non_l2bnk_mx0=1 (non$ access)
wire [2:0] ld2_l2bnk_addr_mx ;
assign ld2_l2bnk_addr_mx[2:0] = ld2_pkt_vld_unmasked ? ld2_l2bnk_addr[2:0] :
{1'b0,ldst_va_mx2[7:6]} ;
//assign ld2_l2bnk_addr_mx[2:0] = (ld2_inst_vld_unflushed & lsu_inst_vld_tmp) ?
// {1'b0,ldst_va_mx2[7:6]} :
// //{non_l2bnk_mx2,ldst_va_mx2[7:6]} :
// ld2_l2bnk_addr[2:0] ;
//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps)
// this will cause timing paths in spec pick in w-cycle; hence assume $able access for
// spec pick and kill pkt vld in w2
dff_s #(1) ff_non_l2bnk_mx2_d1 (
.din (non_l2bnk_mx2),
.q (non_l2bnk_mx2_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug2705 - change ld2_l2bnk_addr[2:0] to ld2_l2bnk_addr_mx[2:0]
assign ld2_l2bnk_dest[0] = ~ld2_l2bnk_addr_mx[2] & ~ld2_l2bnk_addr_mx[1] & ~ld2_l2bnk_addr_mx[0] ;
assign ld2_l2bnk_dest[1] = ~ld2_l2bnk_addr_mx[2] & ~ld2_l2bnk_addr_mx[1] & ld2_l2bnk_addr_mx[0] ;
assign ld2_l2bnk_dest[2] = ~ld2_l2bnk_addr_mx[2] & ld2_l2bnk_addr_mx[1] & ~ld2_l2bnk_addr_mx[0] ;
assign ld2_l2bnk_dest[3] = ~ld2_l2bnk_addr_mx[2] & ld2_l2bnk_addr_mx[1] & ld2_l2bnk_addr_mx[0] ;
assign ld2_l2bnk_dest[4] = ld2_l2bnk_addr_mx[2] ;
// THREAD3 LOAD PCX REQUEST CONTROL
wire ld3_l2cache_rq_kill ;
assign ld3_l2cache_rq_kill =
ld3_inst_vld_w2 & ((ld_stb_full_raw_w2 & ~dbl_force_l2access_w2) | perr_ld_rq_kill_w2) ;
// full-raw which looks like partial
assign ld3_ldbl_rq_w2 =
((ld_stb_full_raw_w2 & dbl_force_l2access_w2) | ld_stb_partial_raw_w2)
& ~atomic_w2 & ~perr_ld_rq_kill_w2 & ~(asi_internal_w2 & alt_space_w2) &
ld3_inst_vld_w2 ;
//assign ld3_l2cache_rq_kill = ld3_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 ;
//assign ld3_ldbl_rq_w2 = ld_stb_full_raw_w2 & dbl_force_l2access_w2 & ~atomic_w2 & ld3_inst_vld_w2 ;
assign ld3_vld_reset =
(reset | (ld3_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld3_inst_vld_g | bld_annul_d1[3] | dtag_perr_pkt2_vld_d1[3]))) |
ld3_l2cache_rq_kill ;
//(reset | (ld3_pcx_rq_sel_d2 & ~(pcx_req_squash_d1 | ld3_inst_vld_g | bld_annul_d1[3]))) | // bug 2877
//(reset | (ld3_pcx_rq_sel_d1 & ~(pcx_req_squash | ld3_inst_vld_g | bld_annul[3]))) ;
wire ld3_l2cache_rq_g;
assign ld3_l2cache_rq_g =
(((lsu_ld_miss_g & ~ldxa_internal))
//((lsu_ld_hit_g | lsu_ld_miss_g) & (ld_stb_partial_raw_g))) // ldst_dbl always rqs
& ~atomic_g & ld3_inst_vld_g)
| pref_rq_vld3_g ;
assign ld3_l2cache_rq = ld3_l2cache_rq_g | ld3_ldbl_rq_w2 ;
// ld valid
wire pref_rq_vld3;
dffre_s #(2) ld3_vld (
.din ({ld3_l2cache_rq, pref_rq_vld3_mx} ),
.q ({ld3_pkt_vld_unmasked, pref_rq_vld3}),
.rst (ld3_vld_reset), .en (ld3_l2cache_rq),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// bug2705 - speculative pick in w-cycle - begin
wire ld3_spec_vld_g ;
assign ld3_spec_vld_g = ld3_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g &
~atomic_or_ldxa_internal_rq_g &
~(ld0_pkt_vld_unmasked | ld1_pkt_vld_unmasked | ld2_pkt_vld_unmasked);
//assign ld3_spec_vld_g = ld3_inst_vld_unflushed & lsu_inst_vld_tmp & ~dbl_force_l2access_g & tlb_cam_hit_g ;
dff_s #(1) ff_ld3_spec_pick_vld_w2 (
.din (ld3_spec_pick_vld_g),
.q (ld3_spec_pick_vld_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// kill packet valid if spec req is picked in w and stb hits in w2
wire ld3_pkt_vld_tmp ;
assign lsu_ld3_spec_vld_kill_w2 = ld3_spec_pick_vld_w2 & (~ld3_l2cache_rq_w2 | ld3_l2cache_rq_kill | ld3_ldbl_rq_w2 | non_l2bnk_mx3_d1) ;
assign ld3_pkt_vld_tmp = ld3_pkt_vld_unmasked & ~(ld3_pcx_rq_sel_d1 | ld3_pcx_rq_sel_d2) &
~(ld3_l2cache_rq_kill | ld3_ldbl_rq_w2) &
~(pref_rq_vld3 & lsu_no_spc_pref[3]) ;
assign ld3_pkt_vld = ld3_pkt_vld_tmp | ld3_spec_vld_g ;
// bug2705 - speculative pick in w-cycle - end
//assign ld3_pkt_vld = ld3_pkt_vld_unmasked & ~ld3_pcx_rq_sel_d1 ;
assign ld3_fill_reset = reset | (lsu_dfq_ld_vld & lsu_dcfill_active_e & dfq_byp_sel[3]) ;
wire ld3_l2cache_rq_g_tmp;
wire ld3_l2cache_rq_w2_tmp;
assign ld3_l2cache_rq_g_tmp = ld3_l2cache_rq_g & ~pref_inst_g ;
dff_s #(1) ff_ld3_l2cache_rq_w2 (
.din (ld3_l2cache_rq_g_tmp),
.q (ld3_l2cache_rq_w2_tmp),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//wire ld3_unfilled_en ;
//assign ld3_unfilled_en = ld3_l2cache_rq & ~pref_inst_g ;
wire ld3_unfilled_wy_en ;
assign ld3_unfilled_wy_en = ld3_l2cache_rq_w2_tmp | ld3_ldbl_rq_w2 ;
wire ld3_l2cache_rq_tmp;
assign ld3_l2cache_rq_tmp = ld3_unfilled_wy_en & ~ld3_l2cache_rq_kill;
// ld valid until fill occur.
dffre_s #(1) ld3out_state (
//.din (ld3_l2cache_rq),
.din (ld3_l2cache_rq_tmp),
.q (ld3_unfilled_tmp),
.rst (ld3_fill_reset_d2), .en (ld3_unfilled_wy_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffre_s #(2) ld3out_state_way (
.din (lsu_lmq_pkt_way_w2[1:0]),
.q (ld3_unfilled_wy[1:0]),
.rst (ld3_fill_reset_d2), .en (ld3_unfilled_wy_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign ld3_fill_reset_d2 = ld3_fill_reset_d2_tmp | ld3_l2cache_rq_kill ;
//assign ld3_unfilled = ld3_unfilled_tmp & ~ld3_l2cache_rq_kill ;
assign ld3_unfilled = ld3_unfilled_tmp;
// ld l2bank address
dffe_s #(3) ld3_l2bnka (
.din ({non_l2bnk_mx3,ldst_va_mx3[7:6]}),
.q (ld3_l2bnk_addr[2:0]),
.en (ld3_l2cache_rq),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug2705 - add byp for address to be available in w-cycle
//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps)
// this will cause timing paths in spec pick in w-cycle; hence assume $able access for
// spec pick and kill pkt vld in w2 if non_l2bnk_mx0=1 (non$ access)
wire [2:0] ld3_l2bnk_addr_mx ;
assign ld3_l2bnk_addr_mx[2:0] = ld3_pkt_vld_unmasked ? ld3_l2bnk_addr[2:0] :
{1'b0,ldst_va_mx3[7:6]} ;
//assign ld3_l2bnk_addr_mx[2:0] = (ld3_inst_vld_unflushed & lsu_inst_vld_tmp) ?
// {1'b0,ldst_va_mx3[7:6]} :
// //{non_l2bnk_mx3,ldst_va_mx3[7:6]} :
// ld3_l2bnk_addr[2:0] ;
//7/21/03: timing fix - non_l2bnk_mx0 (uses tlb_pgnum_g[39:37] which arrives in qctl1 ~400ps)
// this will cause timing paths in spec pick in w-cycle; hence assume $able access for
// spec pick and kill pkt vld in w2
dff_s #(1) ff_non_l2bnk_mx3_d1 (
.din (non_l2bnk_mx3),
.q (non_l2bnk_mx3_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug2705 - change ld3_l2bnk_addr[2:0] to ld3_l2bnk_addr_mx[2:0]
assign ld3_l2bnk_dest[0] = ~ld3_l2bnk_addr_mx[2] & ~ld3_l2bnk_addr_mx[1] & ~ld3_l2bnk_addr_mx[0] ;
assign ld3_l2bnk_dest[1] = ~ld3_l2bnk_addr_mx[2] & ~ld3_l2bnk_addr_mx[1] & ld3_l2bnk_addr_mx[0] ;
assign ld3_l2bnk_dest[2] = ~ld3_l2bnk_addr_mx[2] & ld3_l2bnk_addr_mx[1] & ~ld3_l2bnk_addr_mx[0] ;
assign ld3_l2bnk_dest[3] = ~ld3_l2bnk_addr_mx[2] & ld3_l2bnk_addr_mx[1] & ld3_l2bnk_addr_mx[0] ;
assign ld3_l2bnk_dest[4] = ld3_l2bnk_addr_mx[2] ;
//=================================================================================================
// LMQ Miscellaneous Control
//=================================================================================================
dff_s #(1) stgm_cas (
.din (ifu_lsu_casa_e),
.q (casa_m),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(1) stgg_cas (
.din (casa_m),
.q (casa_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//assign casa0_g = casa_g & thread0_g ;
//assign casa1_g = casa_g & thread1_g ;
//assign casa2_g = casa_g & thread2_g ;
//assign casa3_g = casa_g & thread3_g ;
// PARTIAL RAW BYPASSING.
// Partial raw of load in stb. Even if the load hits in the dcache, it must follow
// the st to the pcx, obtain merged data to bypass to the pipeline. This load will
// also fill the dcache. i.e., once the store is received it looks like a normal load.
// This path is also used for 2nd cas pkt. rs1(addr) and rs2(cmp data) are in 1st
// pkt which is written to stb. rd(swap value) is written to lmq as 2nd pkt. The
// 2nd pkt will wait in the lmq until the 1st pkt is sent.
// *** Atomics need to switch out the thread ***
// THREAD0
// timing fix: 9/15/03 - reduce loading on pcx_rq_for_stb[3:0] to stb_clt[0-3]. it had FO2 (stb_ctl,qdp2 - cap=0.5-0.8)
// move the flop from qdp2 to qctl1
dff_s #(4) ff_pcx_rq_for_stb_d1 (
.din (pcx_rq_for_stb[3:0]),
.q (pcx_rq_for_stb_d1[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(4) srqsel_d1 (
.din (pcx_rq_for_stb[3:0]),
//.q ({st3_pcx_rq_tmp, st2_pcx_rq_tmp,st1_pcx_rq_tmp, st0_pcx_rq_tmp}),
.q ({st3_pcx_rq_sel_d1, st2_pcx_rq_sel_d1,st1_pcx_rq_sel_d1, st0_pcx_rq_sel_d1}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(4) srqsel_d2 (
.din ({st3_pcx_rq_sel_d1, st2_pcx_rq_sel_d1,st1_pcx_rq_sel_d1, st0_pcx_rq_sel_d1}),
.q ({st3_pcx_rq_sel_d2, st2_pcx_rq_sel_d2,st1_pcx_rq_sel_d2, st0_pcx_rq_sel_d2}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(4) srqsel_d3 (
.din ({st3_pcx_rq_sel_d2, st2_pcx_rq_sel_d2,st1_pcx_rq_sel_d2, st0_pcx_rq_sel_d2}),
.q ({st3_pcx_rq_sel_d3, st2_pcx_rq_sel_d3,st1_pcx_rq_sel_d3, st0_pcx_rq_sel_d3}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire ld0_ldbl_rawp_en_w2 ;
assign ld0_ldbl_rawp_en_w2 = ld0_ldbl_rq_w2 & ~ld_rawp_st_ced_w2 & ~ld0_rawp_reset ;
/*assign st3_pcx_rq_sel_d1 = st3_pcx_rq_tmp & ~pcx_req_squash ;
assign st2_pcx_rq_sel_d1 = st2_pcx_rq_tmp & ~pcx_req_squash ;
assign st1_pcx_rq_sel_d1 = st1_pcx_rq_tmp & ~pcx_req_squash ;
assign st0_pcx_rq_sel_d1 = st0_pcx_rq_tmp & ~pcx_req_squash ;*/
assign ld0_rawp_reset =
(reset | (st0_pcx_rq_sel_d3 & ~pcx_req_squash_d2 & ld0_rawp_disabled & (ld0_rawp_ackid[2:0] == stb0_crnt_ack_id[2:0])));
//(reset | (st0_pcx_rq_sel_d2 & ~pcx_req_squash_d1 & ld0_rawp_disabled & (ld0_rawp_ackid[2:0] == stb0_crnt_ack_id[2:0])));
// TO BE REMOVED ALONG WITH defines !!!
//wire ld_rawp_st_ced_g ;
//assign ld_rawp_st_ced_g = 1'b0 ;
// reset needs to be dominant in case ack comes on fly.
// atomics will not set rawp_disabled
assign ld0_rawp_en =
//(((ld_stb_partial_raw_g) & ~ld_rawp_st_ced_g & ~ld0_rawp_reset) // partial_raw
//& ~atomic_g & ld0_inst_vld_g) | // cas inst - 2nd pkt
ld0_ldbl_rawp_en_w2 ;
// ack-id and wait-for-ack disable - Thread 0
dffre_s #(1) ldrawp0_dis (
.din (ld0_rawp_en),
.q (ld0_rawp_disabled),
.rst (ld0_rawp_reset), .en (ld0_rawp_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s #(3) ldrawp0_ackid (
.din (ld_rawp_st_ackid_w2[2:0]),
.q (ld0_rawp_ackid[2:0]),
.en (ld0_inst_vld_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// THREAD1
wire ld1_ldbl_rawp_en_w2 ;
assign ld1_ldbl_rawp_en_w2 = ld1_ldbl_rq_w2 & ~ld_rawp_st_ced_w2 & ~ld1_rawp_reset ;
// 1st st ack for st-quad will not cause ack.
assign ld1_rawp_reset =
(reset | (st1_pcx_rq_sel_d3 & ~pcx_req_squash_d2 & ld1_rawp_disabled &
//(reset | (st1_pcx_rq_sel_d2 & ~pcx_req_squash_d1 & ld1_rawp_disabled &
(ld1_rawp_ackid[2:0] == stb1_crnt_ack_id[2:0])));
// reset needs to be dominant in case ack comes on fly.
// atomics will not set rawp_disabled
assign ld1_rawp_en =
//(((ld_stb_partial_raw_g) & ~ld_rawp_st_ced_g & ~ld1_rawp_reset) // partial raw
//(((ld_stb_partial_raw_g | (ld_stb_full_raw_g & ldst_dbl_g)) & ~ld_rawp_st_ced_g & ~ld1_rawp_reset) // partial raw
//& ~atomic_g & ld1_inst_vld_g) | // cas inst - 2nd pkt
ld1_ldbl_rawp_en_w2 ;
// ack-id and wait-for-ack disable - Thread 0
dffre_s #(1) ldrawp1_dis (
.din (ld1_rawp_en),
.q (ld1_rawp_disabled),
.rst (ld1_rawp_reset), .en (ld1_rawp_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s #(3) ldrawp1_ackid (
.din (ld_rawp_st_ackid_w2[2:0]),
.q (ld1_rawp_ackid[2:0]),
.en (ld1_inst_vld_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// THREAD2
wire ld2_ldbl_rawp_en_w2 ;
assign ld2_ldbl_rawp_en_w2 = ld2_ldbl_rq_w2 & ~ld_rawp_st_ced_w2 & ~ld2_rawp_reset ;
assign ld2_rawp_reset =
(reset | (st2_pcx_rq_sel_d3 & ~pcx_req_squash_d2 & ld2_rawp_disabled &
//(reset | (st2_pcx_rq_sel_d2 & ~pcx_req_squash_d1 & ld2_rawp_disabled &
(ld2_rawp_ackid[2:0] == stb2_crnt_ack_id[2:0])));
// reset needs to be dominant in case ack comes on fly.
// atomics will not set rawp_disabled
assign ld2_rawp_en =
//(((ld_stb_partial_raw_g) & ~ld_rawp_st_ced_g & ~ld2_rawp_reset) // partial raw
//& ~atomic_g & ld2_inst_vld_g) | // cas inst - 2nd pkt
ld2_ldbl_rawp_en_w2 ;
// ack-id and wait-for-ack disable - Thread 0
dffre_s #(1) ldrawp2_dis (
.din (ld2_rawp_en),
.q (ld2_rawp_disabled),
.rst (ld2_rawp_reset), .en (ld2_rawp_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s #(3) ldrawp2_ackid (
.din (ld_rawp_st_ackid_w2[2:0]),
.q (ld2_rawp_ackid[2:0]),
.en (ld2_inst_vld_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// THREAD3
wire ld3_ldbl_rawp_en_w2 ;
assign ld3_ldbl_rawp_en_w2 = ld3_ldbl_rq_w2 & ~ld_rawp_st_ced_w2 & ~ld3_rawp_reset ;
assign ld3_rawp_reset =
(reset | (st3_pcx_rq_sel_d3 & ~pcx_req_squash_d2 & ld3_rawp_disabled &
//(reset | (st3_pcx_rq_sel_d2 & ~pcx_req_squash_d1 & ld3_rawp_disabled &
(ld3_rawp_ackid[2:0] == stb3_crnt_ack_id[2:0])));
// reset needs to be dominant in case ack comes on fly.
// atomics will not set rawp_disabled
assign ld3_rawp_en =
//(((ld_stb_partial_raw_g) & ~ld_rawp_st_ced_g & ~ld3_rawp_reset) // partial raw
//& ~atomic_g & ld3_inst_vld_g) | // cas inst - 2nd pkt
ld3_ldbl_rawp_en_w2 ;
// ack-id and wait-for-ack disable - Thread 0
dffre_s #(1) ldrawp3_dis (
.din (ld3_rawp_en),
.q (ld3_rawp_disabled),
.rst (ld3_rawp_reset), .en (ld3_rawp_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s #(3) ldrawp3_ackid (
.din (ld_rawp_st_ackid_w2[2:0]),
.q (ld3_rawp_ackid[2:0]),
.en (ld3_inst_vld_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//=================================================================================================
// INTERRUPT PCX PKT REQ CTL
//=================================================================================================
wire intrpt_pcx_rq_sel_d2 ;
wire intrpt_vld_reset;
wire intrpt_vld_en ;
wire [3:0] intrpt_thread ;
wire intrpt_clr ;
assign lsu_tlu_pcxpkt_ack = intrpt_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
assign intrpt_vld_reset =
reset | lsu_tlu_pcxpkt_ack ;
//reset | (intrpt_pcx_rq_sel_d1 & ~pcx_req_squash);
wire intrpt_pkt_vld_unmasked ;
// assumption is that pkt vld cannot be turned around in same cycle
assign intrpt_vld_en = ~intrpt_pkt_vld_unmasked ;
//assign intrpt_vld_en = ~lsu_intrpt_pkt_vld ;
dff_s #(1) intpkt_stgd2 (
.din (intrpt_pcx_rq_sel_d1),
.q (intrpt_pcx_rq_sel_d2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// intrpt valid
dffre_s intrpt_vld (
.din (tlu_lsu_pcxpkt_vld),
.q (intrpt_pkt_vld_unmasked),
.rst (intrpt_vld_reset), .en (intrpt_vld_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign intrpt_thread[0] = ~tlu_lsu_pcxpkt_tid[19] & ~tlu_lsu_pcxpkt_tid[18] ;
assign intrpt_thread[1] = ~tlu_lsu_pcxpkt_tid[19] & tlu_lsu_pcxpkt_tid[18] ;
assign intrpt_thread[2] = tlu_lsu_pcxpkt_tid[19] & ~tlu_lsu_pcxpkt_tid[18] ;
assign intrpt_thread[3] = tlu_lsu_pcxpkt_tid[19] & tlu_lsu_pcxpkt_tid[18] ;
assign intrpt_clr =
(intrpt_thread[0] & lsu_stb_empty[0]) |
(intrpt_thread[1] & lsu_stb_empty[1]) |
(intrpt_thread[2] & lsu_stb_empty[2]) |
(intrpt_thread[3] & lsu_stb_empty[3]) ;
wire intrpt_clr_d1 ;
dff_s #(1) intclr_stgd1 (
.din (intrpt_clr),
.q (intrpt_clr_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire [3:0] intrpt_cmplt ;
assign intrpt_cmplt[0] = lsu_tlu_pcxpkt_ack & intrpt_thread[0] ;
assign intrpt_cmplt[1] = lsu_tlu_pcxpkt_ack & intrpt_thread[1] ;
assign intrpt_cmplt[2] = lsu_tlu_pcxpkt_ack & intrpt_thread[2] ;
assign intrpt_cmplt[3] = lsu_tlu_pcxpkt_ack & intrpt_thread[3] ;
dff_s #(4) intrpt_stg (
.din (intrpt_cmplt[3:0]),
.q (lsu_intrpt_cmplt[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign intrpt_pkt_vld =
intrpt_pkt_vld_unmasked & ~(intrpt_pcx_rq_sel_d1 | intrpt_pcx_rq_sel_d2) & intrpt_clr_d1 ;
// ** enabled flop should not be required !!
// intrpt l2bank address
// ?? Can interrupt requests go to io-bridge ??
// Using upper 3b of 5b thread field of INTR_W to address 4 l2 banks
dffe_s #(3) intrpt_l2bnka (
.din ({1'b0,tlu_lsu_pcxpkt_l2baddr[11:10]}),
.q (intrpt_l2bnk_addr[2:0]),
.en (intrpt_vld_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// IO Requests should not go to iobrdge.
assign intrpt_l2bnk_dest[0] =
~intrpt_l2bnk_addr[2] & ~intrpt_l2bnk_addr[1] & ~intrpt_l2bnk_addr[0] ;
assign intrpt_l2bnk_dest[1] =
~intrpt_l2bnk_addr[2] & ~intrpt_l2bnk_addr[1] & intrpt_l2bnk_addr[0] ;
assign intrpt_l2bnk_dest[2] =
~intrpt_l2bnk_addr[2] & intrpt_l2bnk_addr[1] & ~intrpt_l2bnk_addr[0] ;
assign intrpt_l2bnk_dest[3] =
~intrpt_l2bnk_addr[2] & intrpt_l2bnk_addr[1] & intrpt_l2bnk_addr[0] ;
assign intrpt_l2bnk_dest[4] = intrpt_l2bnk_addr[2] ;
//=================================================================================================
//
// QDP Specific Control
//
//=================================================================================================
// Qualify with thread.
// Write cas pckt 2 to lmq
// Timing Change : ld0_l2cache_rq guarantees validity.
//assign lmq_enable[0] = lsu_ld_miss_g & thread0_g ;
//assign lmq_enable[0] = ld0_inst_vld_g | pref_vld0_g ;
//assign lmq_enable[0] = (ld0_inst_vld_unflushed & lsu_inst_vld_w) | pref_vld0_g ;
//assign lmq_enable[1] = (ld1_inst_vld_unflushed & lsu_inst_vld_w) | pref_vld1_g ;
//assign lmq_enable[2] = (ld2_inst_vld_unflushed & lsu_inst_vld_w) | pref_vld2_g ;
//assign lmq_enable[3] = (ld3_inst_vld_unflushed & lsu_inst_vld_w) | pref_vld3_g ;
//bug 2771; timing path - remove flush-pipe, add ifu's flush signal
//assign lmq_enable[0] = (ld0_inst_vld_unflushed | pref_vld0_g) & lsu_inst_vld_w ;
assign lmq_enable[0] = (ld0_inst_vld_unflushed | pref_vld0_g) & lsu_inst_vld_tmp & ~ifu_lsu_flush_w ;
assign lmq_enable[1] = (ld1_inst_vld_unflushed | pref_vld1_g) & lsu_inst_vld_tmp & ~ifu_lsu_flush_w ;
assign lmq_enable[2] = (ld2_inst_vld_unflushed | pref_vld2_g) & lsu_inst_vld_tmp & ~ifu_lsu_flush_w ;
assign lmq_enable[3] = (ld3_inst_vld_unflushed | pref_vld3_g) & lsu_inst_vld_tmp & ~ifu_lsu_flush_w ;
// timing fix: 5/19/03: move secondary hit way generation to w2
dff_s #(4) ff_lmq_enable_w2 (
.din (lmq_enable[3:0]),
.q (lmq_enable_w2[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// needs to be 1-hot always.
assign imiss_pcx_mx_sel = imiss_pcx_rq_sel_d1 ;
//assign imiss_pcx_mx_sel[1] = strm_pcx_rq_sel_d1 ;
//assign imiss_pcx_mx_sel[2] = intrpt_pcx_rq_sel_d1 ;
//assign imiss_pcx_mx_sel[3] = fpop_pcx_rq_sel_d1 ;
//11/7/03: add rst_tri_en
wire [2:0] fwd_int_fp_pcx_mx_sel_tmp ;
assign fwd_int_fp_pcx_mx_sel_tmp[0]= ~fwd_int_fp_pcx_mx_sel[1] & ~fwd_int_fp_pcx_mx_sel[2];
assign fwd_int_fp_pcx_mx_sel_tmp[1]= intrpt_pcx_rq_sel_d1 ;
assign fwd_int_fp_pcx_mx_sel_tmp[2]= fpop_pcx_rq_sel_d1 | fpop_pcx_rq_sel_d2 ;
assign fwd_int_fp_pcx_mx_sel[1:0] = fwd_int_fp_pcx_mx_sel_tmp[1:0] & ~{2{rst_tri_en}} ;
assign fwd_int_fp_pcx_mx_sel[2] = fwd_int_fp_pcx_mx_sel_tmp[2] | rst_tri_en ;
//*************************************************************************************************
// PCX REQUEST GENERATION (BEGIN)
//=================================================================================================
// PCX REQUEST SELECTION CONTROL
//=================================================================================================
// LOAD
// fpops have to squash other rqs in the 2nd cycle also.
//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick
assign ld0_pcx_rq_vld =
(|(queue_write[4:0] & ld0_l2bnk_dest[4:0])) &
ld0_pkt_vld & ~ld0_rawp_disabled;
//ld0_pkt_vld & ~ld0_rawp_disabled & ~mcycle_squash_d1;
//ld0_pkt_vld & ~ld0_rawp_disabled & ~st_atom_rq_d1 ;
assign ld1_pcx_rq_vld =
(|(queue_write[4:0] & ld1_l2bnk_dest[4:0])) &
ld1_pkt_vld & ~ld1_rawp_disabled;
//ld1_pkt_vld & ~ld1_rawp_disabled & ~mcycle_squash_d1;
//ld1_pkt_vld & ~ld1_rawp_disabled & ~st_atom_rq_d1 ;
assign ld2_pcx_rq_vld =
(|(queue_write[4:0] & ld2_l2bnk_dest[4:0])) &
ld2_pkt_vld & ~ld2_rawp_disabled ;
//ld2_pkt_vld & ~ld2_rawp_disabled & ~mcycle_squash_d1;
//ld2_pkt_vld & ~ld2_rawp_disabled & ~st_atom_rq_d1 ;
assign ld3_pcx_rq_vld =
(|(queue_write[4:0] & ld3_l2bnk_dest[4:0])) &
ld3_pkt_vld & ~ld3_rawp_disabled;
//ld3_pkt_vld & ~ld3_rawp_disabled & ~mcycle_squash_d1;
//ld3_pkt_vld & ~ld3_rawp_disabled & ~st_atom_rq_d1 ;
//assign ld_pcx_rq_vld = ld0_pcx_rq_vld | ld1_pcx_rq_vld
// | ld2_pcx_rq_vld | ld3_pcx_rq_vld ;
wire st0_atomic_pend_d1, st1_atomic_pend_d1, st2_atomic_pend_d1, st3_atomic_pend_d1 ;
assign st0_q_wr[4:0] = st0_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ;
assign st1_q_wr[4:0] = st1_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ;
assign st2_q_wr[4:0] = st2_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ;
assign st3_q_wr[4:0] = st3_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ;
assign st0_atom_rq = (st0_pcx_rq_sel & st0_atomic_vld) ;
assign st1_atom_rq = (st1_pcx_rq_sel & st1_atomic_vld) ;
assign st2_atom_rq = (st2_pcx_rq_sel & st2_atomic_vld) ;
assign st3_atom_rq = (st3_pcx_rq_sel & st3_atomic_vld) ;
dff_s #(8) avlds_d1 (
.din ({st0_atom_rq,st1_atom_rq,st2_atom_rq,st3_atom_rq,
st0_cas_vld,st1_cas_vld,st2_cas_vld,st3_cas_vld}),
.q ({st0_atom_rq_d1,st1_atom_rq_d1,st2_atom_rq_d1,st3_atom_rq_d1,
st0_cas_vld_d1,st1_cas_vld_d1,st2_cas_vld_d1,st3_cas_vld_d1}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(8) avlds_d2 (
.din ({st0_atom_rq_d1,st1_atom_rq_d1,st2_atom_rq_d1,st3_atom_rq_d1,
st0_cas_vld_d1,st1_cas_vld_d1,st2_cas_vld_d1,st3_cas_vld_d1}),
.q ({st0_atom_rq_d2,st1_atom_rq_d2,st2_atom_rq_d2,st3_atom_rq_d2,
st0_cas_vld_d2,st1_cas_vld_d2,st2_cas_vld_d2,st3_cas_vld_d2}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//timing fix : 7/28/03 - move the OR before flop
assign st_atom_rq = st0_atom_rq | st1_atom_rq | st2_atom_rq | st3_atom_rq ;
//assign st_atom_rq_d1 = st0_atom_rq_d1 | st1_atom_rq_d1 | st2_atom_rq_d1 | st3_atom_rq_d1 ;
// timing fix: 7/28/03 - move the OR before flop
dff_s #(1) ff_st_atom_pq (
.din (st_atom_rq),
.q (st_atom_rq_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign st_cas_rq_d2 =
(st0_atom_rq_d2 & st0_cas_vld_d2) |
(st1_atom_rq_d2 & st1_cas_vld_d2) |
(st2_atom_rq_d2 & st2_cas_vld_d2) |
(st3_atom_rq_d2 & st3_cas_vld_d2) ;
//assign st_quad_rq_d2 =
// (st0_atom_rq_d2 & ~st0_cas_vld_d2) |
// (st1_atom_rq_d2 & ~st1_cas_vld_d2) |
// (st2_atom_rq_d2 & ~st2_cas_vld_d2) |
// (st3_atom_rq_d2 & ~st3_cas_vld_d2) ;
//timing fix: 9/17/03 - move the OR to previous cycle and add flop for spc_pcx_atom_pq
// instantiate buf30 for flop output
//assign spc_pcx_atom_pq =
// st_atom_rq_d1 |
// fpop_atom_rq_pq ;
wire spc_pcx_atom_w, spc_pcx_atom_pq_tmp ;
assign spc_pcx_atom_w = st_atom_rq | fpop_atom_req ;
dff_s #(1) ff_spc_pcx_atom_pq (
.din (spc_pcx_atom_w),
.q (spc_pcx_atom_pq_tmp),
.clk (clk),
.se (1'b0), .si (), .so ()
);
bw_u1_buf_30x UZfix_spc_pcx_atom_pq_buf1 ( .a(spc_pcx_atom_pq_tmp), .z(spc_pcx_atom_pq) );
bw_u1_buf_30x UZsize_spc_pcx_atom_pq_buf2 ( .a(spc_pcx_atom_pq_tmp), .z(spc_pcx_atom_pq_buf2) );
// STORE
// st will wait in pcx bypass until previous st in chain is acked !!!!
//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick
assign st0_pcx_rq_vld =
(|(st0_q_wr[4:0] & st0_l2bnk_dest[4:0])) & st0_pkt_vld ;
//(|(st0_q_wr[4:0] & st0_l2bnk_dest[4:0])) & st0_pkt_vld & ~mcycle_squash_d1;
//(|(st0_q_wr[4:0] & st0_l2bnk_dest[4:0])) & st0_pkt_vld & ~st_atom_rq_d1 ;
assign st1_pcx_rq_vld =
(|(st1_q_wr[4:0] & st1_l2bnk_dest[4:0])) & st1_pkt_vld ;
//(|(st1_q_wr[4:0] & st1_l2bnk_dest[4:0])) & st1_pkt_vld & ~mcycle_squash_d1;
//(|(st1_q_wr[4:0] & st1_l2bnk_dest[4:0])) & st1_pkt_vld & ~st_atom_rq_d1 ;
assign st2_pcx_rq_vld =
(|(st2_q_wr[4:0] & st2_l2bnk_dest[4:0])) & st2_pkt_vld ;
//(|(st2_q_wr[4:0] & st2_l2bnk_dest[4:0])) & st2_pkt_vld & ~mcycle_squash_d1;
//(|(st2_q_wr[4:0] & st2_l2bnk_dest[4:0])) & st2_pkt_vld & ~st_atom_rq_d1 ;
assign st3_pcx_rq_vld =
(|(st3_q_wr[4:0] & st3_l2bnk_dest[4:0])) & st3_pkt_vld ;
//(|(st3_q_wr[4:0] & st3_l2bnk_dest[4:0])) & st3_pkt_vld & ~mcycle_squash_d1;
//(|(st3_q_wr[4:0] & st3_l2bnk_dest[4:0])) & st3_pkt_vld & ~st_atom_rq_d1 ;
// IMISS
// imiss requests will not speculate - ** change !!!
//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick
assign imiss_pcx_rq_vld =
(|(queue_write[4:0] & imiss_l2bnk_dest[4:0])) & imiss_pkt_vld ;
//(|(queue_write[4:0] & imiss_l2bnk_dest[4:0])) & imiss_pkt_vld & ~mcycle_squash_d1;
//(|((queue_write[4:0] & (sel_qentry0[4:0] | (~sel_qentry0[4:0] & ~spc_pcx_req_update_w2[4:0]))) & imiss_l2bnk_dest[4:0])) & imiss_pkt_vld & ~mcycle_squash_d1;
// SPU
//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick
assign strm_pcx_rq_vld =
(|(queue_write[4:0] & strm_l2bnk_dest[4:0])) & strm_pkt_vld ;
//(|(queue_write[4:0] & strm_l2bnk_dest[4:0])) & strm_pkt_vld & ~mcycle_squash_d1;
wire lsu_fwdpkt_vld_d1 ;
wire [4:0] fwdpkt_dest_d1 ;
// This delay is to compensate for the 1-cycle delay for internal rd/wr.
dff_s #(6) fvld_stgd1 (
.din ({lsu_fwdpkt_vld,lsu_fwdpkt_dest[4:0]}),
.q ({lsu_fwdpkt_vld_d1,fwdpkt_dest_d1[4:0]}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// FWD PKT
//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick
assign fwdpkt_rq_vld =
(|(queue_write[4:0] & fwdpkt_dest_d1[4:0])) &
lsu_fwdpkt_vld_d1 &
~(fwdpkt_pcx_rq_sel_d1 | fwdpkt_pcx_rq_sel_d2 | // screen vld until reset can be sent.
fwdpkt_pcx_rq_sel_d3) ; // extra cycle since fwdpkt_vld is now flop delayed.
//~mcycle_squash_d1;
// This to reset state. It must thus take into account speculative requests.
assign lsu_fwdpkt_pcx_rq_sel = fwdpkt_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
// INTERRUPT
//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick
assign intrpt_pcx_rq_vld =
(|(queue_write[4:0] & intrpt_l2bnk_dest[4:0])) & intrpt_pkt_vld ;
//(|(queue_write[4:0] & intrpt_l2bnk_dest[4:0])) & intrpt_pkt_vld & ~mcycle_squash_d1;
// FFU
// fpop will never get squashed.
// ** Should be able to simplify equation.
//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick
//for fpop pre_qwr is good enough to qual 'cos there are no ld/st atomics to IOB
wire [4:0] fpop_q_wr ;
assign fpop_pcx_rq_vld =
//sel_qentry0[4] & fpop_l2bnk_dest[4] & fpop_pkt_vld ;
//(|(queue_write[4:0] & fpop_l2bnk_dest[4:0])) &
//(|(pre_qwr[4:0] & fpop_l2bnk_dest[4:0])) &
(|(fpop_q_wr[4:0] & fpop_l2bnk_dest[4:0])) &
// change sel_qentry0[5] to sel_qentry0[4] for fpio merge
fpop_pkt_vld ;
//fpop_pkt_vld & ((sel_qentry0[4] & fpop_pkt1) | ~fpop_pkt1) ;
//~mcycle_squash_d1 ;
//=================================================================================================
// HIERARCHICAL PICKER FOR PCX REQ GENERATION
//=================================================================================================
// 13 requests to choose from :
// - imiss, 4 ld, 4 st, (intrpt,strm,fpop,fwdpkt).
// - 4 categories are thus formed, each with equal weight.
// - As a consequence, imiss has the highest priority (because it is one vs. 4 in others)
// - Fair scheduling thru round-robin is ensured between and within categories.
// - Starvation for 2-cycle b2b ops (cas/fpop) is prevented.
// - strm requests, even though they lie in the misc category, will get good
// thruput as the other misc requests will be infrequent.
// LEVEL ONE - PICK WITHIN CATEGORIES
// Note : picker defaults to 1-hot.
wire [3:0] all_pcx_rq_pick ;
wire [3:0] ld_events_raw ;
//wire [3:0] ld_events_final ;
wire ld3_pcx_rq_pick,ld2_pcx_rq_pick,ld1_pcx_rq_pick,ld0_pcx_rq_pick ;
//bug6807 - kill load events raw when partial raw is detected.
assign ld_events_raw[0] = (ld0_pkt_vld_unmasked & ~ld0_rawp_disabled) | ld0_pcx_rq_sel_d1 | ld0_pcx_rq_sel_d2 ;
assign ld_events_raw[1] = (ld1_pkt_vld_unmasked & ~ld1_rawp_disabled) | ld1_pcx_rq_sel_d1 | ld1_pcx_rq_sel_d2 ;
assign ld_events_raw[2] = (ld2_pkt_vld_unmasked & ~ld2_rawp_disabled) | ld2_pcx_rq_sel_d1 | ld2_pcx_rq_sel_d2 ;
assign ld_events_raw[3] = (ld3_pkt_vld_unmasked & ~ld3_rawp_disabled) | ld3_pcx_rq_sel_d1 | ld3_pcx_rq_sel_d2 ;
//bug4814 - change rrobin_picker1 to rrobin_picker2
// Choose one among 4 loads.
//lsu_rrobin_picker1 ld4_rrobin (
// .events ({ld3_pcx_rq_vld,ld2_pcx_rq_vld,
// ld1_pcx_rq_vld,ld0_pcx_rq_vld}),
// .events_raw ({ld3_pkt_vld_unmasked,ld2_pkt_vld_unmasked,
// ld1_pkt_vld_unmasked,ld0_pkt_vld_unmasked}),
// .pick_one_hot ({ld3_pcx_rq_pick,ld2_pcx_rq_pick,
// ld1_pcx_rq_pick,ld0_pcx_rq_pick}),
// .events_final (ld_events_final[3:0]),
// .rclk (rclk),
// .grst_l (grst_l),
// .arst_l (arst_l),
// .si(),
// .se(se),
// .so()
// );
lsu_rrobin_picker2 ld4_rrobin (
.events ({ld3_pcx_rq_vld,ld2_pcx_rq_vld,ld1_pcx_rq_vld,ld0_pcx_rq_vld}),
.thread_force (ld_thrd_force_vld[3:0]),
.pick_one_hot ({ld3_pcx_rq_pick,ld2_pcx_rq_pick,ld1_pcx_rq_pick,ld0_pcx_rq_pick}),
.events_picked({ld3_pcx_rq_sel,ld2_pcx_rq_sel,ld1_pcx_rq_sel,ld0_pcx_rq_sel}),
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.si(),
.se(se),
.so()
);
//timing fix: 05/20/03 - move mcycle_squash_d1 after pick instead of before pick
//assign ld3_pcx_rq_sel = ld3_pcx_rq_pick & ld3_pcx_rq_vld & all_pcx_rq_pick[1] ;
//assign ld2_pcx_rq_sel = ld2_pcx_rq_pick & ld2_pcx_rq_vld & all_pcx_rq_pick[1] ;
//assign ld1_pcx_rq_sel = ld1_pcx_rq_pick & ld1_pcx_rq_vld & all_pcx_rq_pick[1] ;
//assign ld0_pcx_rq_sel = ld0_pcx_rq_pick & ld0_pcx_rq_vld & all_pcx_rq_pick[1] ;
//bug2705 - add spec valid qualification
//assign ld3_pcx_rq_sel = ld3_pcx_rq_pick & ld3_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
//timing fix: 08/06/03 - tag_rdata->gen tag_parity_err->lsu_ld_miss_g arrives @625 in qctl1
// cache_way_hit ->lsu_ld_miss_g arrives @525 in qctl1
// cache_way_hit ->lsu_way_hit_or arrives @510 in qctl1
// 625ps + ld?_l2cache_rq_g (130ps) + urq_stgpq flop logic(100ps) (slack=-100ps)
//assign ld0_spec_pick_vld_g = ld0_spec_vld_g & ld0_l2cache_rq_g & ld0_pcx_rq_pick & ld0_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
wire ld0_nspec_pick_vld ,
ld1_nspec_pick_vld ,
ld2_nspec_pick_vld ,
ld3_nspec_pick_vld ;
assign ld0_spec_pick_vld_g = ld0_spec_vld_g & ~lsu_way_hit_or & ld0_pcx_rq_pick & ld0_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
assign ld0_nspec_pick_vld = ~ld0_spec_vld_g & ld0_pcx_rq_pick & ld0_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
assign ld1_spec_pick_vld_g = ld1_spec_vld_g & ~lsu_way_hit_or & ld1_pcx_rq_pick & ld1_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
assign ld1_nspec_pick_vld = ~ld1_spec_vld_g & ld1_pcx_rq_pick & ld1_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
assign ld2_spec_pick_vld_g = ld2_spec_vld_g & ~lsu_way_hit_or & ld2_pcx_rq_pick & ld2_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
assign ld2_nspec_pick_vld = ~ld2_spec_vld_g & ld2_pcx_rq_pick & ld2_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
assign ld3_spec_pick_vld_g = ld3_spec_vld_g & ~lsu_way_hit_or & ld3_pcx_rq_pick & ld3_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
assign ld3_nspec_pick_vld = ~ld3_spec_vld_g & ld3_pcx_rq_pick & ld3_pcx_rq_vld & all_pcx_rq_pick[1] & ~mcycle_squash_d1 ;
assign ld0_pcx_rq_sel = (ld0_spec_pick_vld_g | ld0_nspec_pick_vld) ;
assign ld1_pcx_rq_sel = (ld1_spec_pick_vld_g | ld1_nspec_pick_vld) ;
assign ld2_pcx_rq_sel = (ld2_spec_pick_vld_g | ld2_nspec_pick_vld) ;
assign ld3_pcx_rq_sel = (ld3_spec_pick_vld_g | ld3_nspec_pick_vld) ;
//bug3506: set mask in the level1 pick in w3-cycle if picked by pcx
//assign ld_events_final[3] = ld3_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
//assign ld_events_final[2] = ld2_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
//assign ld_events_final[1] = ld1_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
//assign ld_events_final[0] = ld0_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
wire st3_pcx_rq_pick,st2_pcx_rq_pick,st1_pcx_rq_pick,st0_pcx_rq_pick ;
// Choose one among 4 st.
wire pcx_rq_for_stb_en;
//wire [3:0] st_events_final ;
wire [3:0] st_events_raw ;
//8/20/03: bug3506 fix is incomplete - vld may not be held until d2 cycle
assign st_events_raw[0] = stb0_rd_for_pcx | st0_pcx_rq_sel_d1 | st0_pcx_rq_sel_d2 ;
assign st_events_raw[1] = stb1_rd_for_pcx | st1_pcx_rq_sel_d1 | st1_pcx_rq_sel_d2 ;
assign st_events_raw[2] = stb2_rd_for_pcx | st2_pcx_rq_sel_d1 | st2_pcx_rq_sel_d2 ;
assign st_events_raw[3] = stb3_rd_for_pcx | st3_pcx_rq_sel_d1 | st3_pcx_rq_sel_d2 ;
//bug4814 - change rrobin_picker1 to rrobin_picker2
//lsu_rrobin_picker1 st4_rrobin (
// .events ({st3_pcx_rq_vld,st2_pcx_rq_vld,
// st1_pcx_rq_vld,st0_pcx_rq_vld}),
// .events_raw (st_events_raw[3:0]),
// .pick_one_hot ({st3_pcx_rq_pick,st2_pcx_rq_pick,
// st1_pcx_rq_pick,st0_pcx_rq_pick}),
// //.en (pcx_rq_for_stb_en),
// .events_final (st_events_final[3:0]),
// .rclk (rclk),
// .grst_l (grst_l),
// .arst_l (arst_l),
// .si(),
// .se(se),
// .so()
//
// );
lsu_rrobin_picker2 st4_rrobin (
.events ({st3_pcx_rq_vld,st2_pcx_rq_vld,st1_pcx_rq_vld,st0_pcx_rq_vld}),
.thread_force(st_thrd_force_vld[3:0]),
.pick_one_hot ({st3_pcx_rq_pick,st2_pcx_rq_pick,st1_pcx_rq_pick,st0_pcx_rq_pick}),
.events_picked(pcx_rq_for_stb[3:0]),
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.si(),
.se(se),
.so()
);
assign lsu_st_pcx_rq_pick[3:0] = {st3_pcx_rq_pick,st2_pcx_rq_pick,st1_pcx_rq_pick,st0_pcx_rq_pick};
//timing fix: 9/2/03 - reduce fanout in stb_rwctl for lsu_st_pcx_rq_pick - gen separate signal for
// stb_cam_rptr_vld and stb_data_rptr_vld
assign lsu_st_pcx_rq_vld = st0_pcx_rq_vld | st1_pcx_rq_vld | st2_pcx_rq_vld | st3_pcx_rq_vld ;
//wire st0_pcx_rq_sel_tmp, st1_pcx_rq_sel_tmp;
//wire st2_pcx_rq_sel_tmp, st3_pcx_rq_sel_tmp;
wire stb_cam_hit_w;
//bug3503
assign stb_cam_hit_w = stb_cam_hit_bf & lsu_inst_vld_w ;
dff_s #(1) stb_cam_hit_stg_w2 (
.din (stb_cam_hit_w),
.q (stb_cam_hit_w2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//RAW read STB at W3 (not W2), so stb_cam_hit_w2 isn't critical
//assign pcx_rq_for_stb_en = ~(|lsu_st_ack_rq_stb[3:0]) & ~stb_cam_hit_w2 & ~stb_cam_wptr_vld;
//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick
assign pcx_rq_for_stb_en = ~stb_cam_hit_w2 & ~stb_cam_wr_no_ivld_m & ~mcycle_squash_d1 ;
//timing fix : 5/6 - move kill_w2 after store pick
//assign pcx_rq_for_stb[3] = st3_pcx_rq_pick & st3_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en;
//assign pcx_rq_for_stb[2] = st2_pcx_rq_pick & st2_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en;
//assign pcx_rq_for_stb[1] = st1_pcx_rq_pick & st1_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en;
//assign pcx_rq_for_stb[0] = st0_pcx_rq_pick & st0_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en;
//timing fix: 05/20/03 - move mcycle_squash_d1 after pick instead of before pick
//bug4513 - kill pcx_rq_for_stb if atomic request is picked and 2 entries to the l2bank are not available
wire [3:0] pcx_rq_for_stb_tmp ;
wire st0_qmon_2entry_avail,st1_qmon_2entry_avail,st2_qmon_2entry_avail,st3_qmon_2entry_avail ;
assign pcx_rq_for_stb_tmp[3] =
st3_pcx_rq_pick & st3_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[3] & ~mcycle_squash_d1 ;
//st3_pcx_rq_pick & st3_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[3];
assign pcx_rq_for_stb_tmp[2] =
st2_pcx_rq_pick & st2_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[2] & ~mcycle_squash_d1 ;
//st2_pcx_rq_pick & st2_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[2];
assign pcx_rq_for_stb_tmp[1] =
st1_pcx_rq_pick & st1_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[1] & ~mcycle_squash_d1 ;
//st1_pcx_rq_pick & st1_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[1];
assign pcx_rq_for_stb_tmp[0] =
st0_pcx_rq_pick & st0_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[0] & ~mcycle_squash_d1 ;
//st0_pcx_rq_pick & st0_pcx_rq_vld & all_pcx_rq_pick[2] & pcx_rq_for_stb_en & ~lsu_st_pcx_rq_kill_w2[0];
//bug4513 - kill pcx_rq_for_stb if atomic request is picked and 2 entries to the l2bank are not available
assign pcx_rq_for_stb[3] = ((st3_atomic_vld & st3_qmon_2entry_avail) | ~st3_atomic_vld) & pcx_rq_for_stb_tmp[3] ;
assign pcx_rq_for_stb[2] = ((st2_atomic_vld & st2_qmon_2entry_avail) | ~st2_atomic_vld) & pcx_rq_for_stb_tmp[2] ;
assign pcx_rq_for_stb[1] = ((st1_atomic_vld & st1_qmon_2entry_avail) | ~st1_atomic_vld) & pcx_rq_for_stb_tmp[1] ;
assign pcx_rq_for_stb[0] = ((st0_atomic_vld & st0_qmon_2entry_avail) | ~st0_atomic_vld) & pcx_rq_for_stb_tmp[0] ;
//assign st3_pcx_rq_sel_tmp = st3_pcx_rq_pick & st3_pcx_rq_vld & all_pcx_rq_pick[2] ;
//assign st2_pcx_rq_sel_tmp = st2_pcx_rq_pick & st2_pcx_rq_vld & all_pcx_rq_pick[2] ;
//assign st1_pcx_rq_sel_tmp = st1_pcx_rq_pick & st1_pcx_rq_vld & all_pcx_rq_pick[2] ;
//assign st0_pcx_rq_sel_tmp = st0_pcx_rq_pick & st0_pcx_rq_vld & all_pcx_rq_pick[2] ;
//bug3506: set mask in the level1 pick in w3-cycle if picked by pcx
//assign st_events_final[3] = st3_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
//assign st_events_final[2] = st2_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
//assign st_events_final[1] = st1_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
//assign st_events_final[0] = st0_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
wire strm_pcx_rq_pick,fpop_pcx_rq_pick,intrpt_pcx_rq_pick,fwdpkt_pcx_rq_pick;
//wire [3:0] misc_events_final ;
wire [3:0] misc_events_raw ;
//8/20/03: bug3506 fix is incomplete - vld may not be held until d2 cycle
assign misc_events_raw[0] = lsu_fwdpkt_vld_d1 | fwdpkt_pcx_rq_sel_d1 | fwdpkt_pcx_rq_sel_d2 ;
//bug6807 - kill interrupt events raw when store buffer is not empty i.e. interrupt clear=0
assign misc_events_raw[1] = (intrpt_pkt_vld_unmasked & intrpt_clr_d1) | intrpt_pcx_rq_sel_d1 | intrpt_pcx_rq_sel_d2 ;
assign misc_events_raw[2] = fpop_pkt_vld_unmasked | fpop_pcx_rq_sel_d1 | fpop_pcx_rq_sel_d2 ;
assign misc_events_raw[3] = strm_pkt_vld_unmasked | strm_pcx_rq_sel_d1 | strm_pcx_rq_sel_d2 ;
//bug4814 - change rrobin_picker1 to rrobin_picker2
//lsu_rrobin_picker1 misc4_rrobin (
// .events ({strm_pcx_rq_vld,fpop_pcx_rq_vld,
// intrpt_pcx_rq_vld,fwdpkt_rq_vld}),
// .events_raw (misc_events_raw[3:0]),
// .pick_one_hot ({strm_pcx_rq_pick,fpop_pcx_rq_pick,
// intrpt_pcx_rq_pick,fwdpkt_pcx_rq_pick}),
// .events_final (misc_events_final[3:0]),
// .rclk (rclk),
// .grst_l (grst_l),
// .arst_l (arst_l),
// .si(),
// .se(se),
// .so()
// );
lsu_rrobin_picker2 misc4_rrobin (
.events ({strm_pcx_rq_vld,fpop_pcx_rq_vld,intrpt_pcx_rq_vld,fwdpkt_rq_vld}),
.thread_force(misc_thrd_force_vld[3:0]),
.pick_one_hot ({strm_pcx_rq_pick,fpop_pcx_rq_pick,intrpt_pcx_rq_pick,fwdpkt_pcx_rq_pick}),
.events_picked({strm_pcx_rq_sel,fpop_pcx_rq_sel,intrpt_pcx_rq_sel,fwdpkt_pcx_rq_sel}),
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.si(),
.se(se),
.so()
);
//timing fix: 05/20/03 - move mcycle_squash_d1 after pick instead of before pick
//assign strm_pcx_rq_sel = strm_pcx_rq_pick & strm_pcx_rq_vld & all_pcx_rq_pick[3] ;
//assign fpop_pcx_rq_sel = fpop_pcx_rq_pick & fpop_pcx_rq_vld & all_pcx_rq_pick[3] ;
//assign intrpt_pcx_rq_sel = intrpt_pcx_rq_pick & intrpt_pcx_rq_vld & all_pcx_rq_pick[3] ;
//assign fwdpkt_pcx_rq_sel = fwdpkt_pcx_rq_pick & fwdpkt_rq_vld & all_pcx_rq_pick[3] ;
assign strm_pcx_rq_sel = strm_pcx_rq_pick & strm_pcx_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ;
//11/15/03 - change fpop atomic to be same as store atomic (bug4513)
//assign fpop_pcx_rq_sel = fpop_pcx_rq_pick & fpop_pcx_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ;
wire fpop_qmon_2entry_avail ;
assign fpop_pcx_rq_sel_tmp = fpop_pcx_rq_pick & fpop_pcx_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ;
assign fpop_pcx_rq_sel = fpop_pcx_rq_sel_tmp & fpop_qmon_2entry_avail ;
assign intrpt_pcx_rq_sel = intrpt_pcx_rq_pick & intrpt_pcx_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ;
assign fwdpkt_pcx_rq_sel = fwdpkt_pcx_rq_pick & fwdpkt_rq_vld & all_pcx_rq_pick[3] & ~mcycle_squash_d1 ;
//bug3506: set mask in the level1 pick in w3-cycle if picked by pcx
//assign misc_events_final[3] = lsu_spu_ldst_ack ;
//assign misc_events_final[2] = lsu_tlu_pcxpkt_ack ;
//assign misc_events_final[1] = lsu_fwdpkt_pcx_rq_sel ;
//assign misc_events_final[0] = fpop_pcx_rq_sel_d2 & ~pcx_req_squash_d1 ;
// LEVEL TWO - PICK AMONG CATEGORIES
// In parallel with level one
wire ld_pcx_rq_all, st_pcx_rq_all, misc_pcx_rq_all ;
assign ld_pcx_rq_all = ld3_pcx_rq_vld | ld2_pcx_rq_vld | ld1_pcx_rq_vld | ld0_pcx_rq_vld ;
assign st_pcx_rq_all = st3_pcx_rq_vld | st2_pcx_rq_vld | st1_pcx_rq_vld | st0_pcx_rq_vld ;
assign misc_pcx_rq_all = strm_pcx_rq_vld | fpop_pcx_rq_vld | intrpt_pcx_rq_vld | fwdpkt_rq_vld ;
//bug3506- raw valid used in resetting pick status
//8/20/03: bug3506 fix is incomplete - vld may not be held until d2 cycle
//wire all4_rrobin_en;
//timing fix: 5/20/03 - pcx_rq_for_stb will be independent of ifu_lsu_pcxreq_d
//assign all4_rrobin_en = ~(all_pcx_rq_pick[2] & ~pcx_rq_for_stb_en) ;
//timing fix: 05/20/03 - move mycle_squash_d1 after pick instead of before pick
//assign all4_rrobin_en = ~((all_pcx_rq_pick[2] & ~pcx_rq_for_stb_en) | imiss_pcx_rq_vld );
//bug3348 - setting history moved from w-stage to w3-stage(1-cycle after spc_pcx_req_pq)
// and hence there are no cases to disable logging of history
//assign all4_rrobin_en = ~((all_pcx_rq_pick[2] & ~pcx_rq_for_stb_en) | imiss_pcx_rq_vld | mcycle_squash_d1);
//wire spc_pcx_req_vld_pq1 ;
//assign all4_rrobin_en = spc_pcx_req_vld_pq1 ;
//wire [3:1] all_pcx_rq_pick_no_iqual;
wire [3:0] all_pcx_rq_pick_no_iqual;
//wire [3:0] all_pcx_pick_status_d2; // bug 3348
//wire [3:0] all_pick_status_rst_d2; //bug 3506
wire [3:0] all_pick_status_set;
//bug3506: set pick status in the same cycle
assign all_pick_status_set[3] = |{ strm_pcx_rq_sel, intrpt_pcx_rq_sel,fpop_pcx_rq_sel, fwdpkt_pcx_rq_sel} ;
assign all_pick_status_set[2] = |pcx_rq_for_stb[3:0] ;
assign all_pick_status_set[1] = |{ld0_pcx_rq_sel,ld1_pcx_rq_sel,ld2_pcx_rq_sel,ld3_pcx_rq_sel} ;
assign all_pick_status_set[0] = 1'b0 ;
lsu_rrobin_picker2 all4_rrobin (
.events ({misc_pcx_rq_all,st_pcx_rq_all,ld_pcx_rq_all,1'b0}),
.thread_force(all_thrd_force_vld[3:0]),
.pick_one_hot (all_pcx_rq_pick_no_iqual[3:0]),
.events_picked(all_pick_status_set[3:0]),
//.en (all4_rrobin_en), // bug 3348
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.si(),
.se(se),
.so()
);
// 5/22/03: cmp1_regr fail - qual all pick w/ ~mcycle_squash_d1; not doing this causes multi-hot select to
// pcx_pkt mux
assign all_pcx_rq_pick[0] = imiss_pcx_rq_vld & ~mcycle_squash_d1;
assign all_pcx_rq_pick[3:1] = all_pcx_rq_pick_no_iqual[3:1] & ~{3{imiss_pcx_rq_vld | mcycle_squash_d1}};
wire all_pcx_rq_dest_sel3 ;
assign all_pcx_rq_dest_sel3 = ~|all_pcx_rq_pick[2:0];
//timing fix: 5/20/03 - pcx_rq_for_stb will be independent of ifu_lsu_pcxreq_d
//assign imiss_pcx_rq_sel = imiss_pcx_rq_vld & all_pcx_rq_pick[0] ;
//timing fix: 05/20/03 - move mcycle_squash_d1 after pick instead of before pick
//assign imiss_pcx_rq_sel = imiss_pcx_rq_vld;
assign imiss_pcx_rq_sel = imiss_pcx_rq_vld & ~mcycle_squash_d1 ;
//=================================================================================================
// Select appr. load. Need a scheme which allows threads to
// make fwd progress.
/*assign ld0_pcx_rq_sel = ld0_pcx_rq_vld ;
assign ld1_pcx_rq_sel = ld1_pcx_rq_vld & ~ld0_pcx_rq_vld ;
assign ld2_pcx_rq_sel = ld2_pcx_rq_vld & ~(ld0_pcx_rq_vld | ld1_pcx_rq_vld);
assign ld3_pcx_rq_sel = ld3_pcx_rq_vld & ~(ld0_pcx_rq_vld | ld1_pcx_rq_vld | ld2_pcx_rq_vld) ; */
dff_s #(4) lrsel_stgd1 (
.din ({ld0_pcx_rq_sel, ld1_pcx_rq_sel, ld2_pcx_rq_sel, ld3_pcx_rq_sel}),
.q ({ld0_pcx_rq_sel_d1, ld1_pcx_rq_sel_d1, ld2_pcx_rq_sel_d1, ld3_pcx_rq_sel_d1}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug2705- kill pcx pick if spec vld kill is set
assign lsu_ld0_pcx_rq_sel_d1 = ld0_pcx_rq_sel_d1 & ~lsu_ld0_spec_vld_kill_w2 ;
assign lsu_ld1_pcx_rq_sel_d1 = ld1_pcx_rq_sel_d1 & ~lsu_ld1_spec_vld_kill_w2 ;
assign lsu_ld2_pcx_rq_sel_d1 = ld2_pcx_rq_sel_d1 & ~lsu_ld2_spec_vld_kill_w2 ;
assign lsu_ld3_pcx_rq_sel_d1 = ld3_pcx_rq_sel_d1 & ~lsu_ld3_spec_vld_kill_w2 ;
dff_s #(4) lrsel_stgd2 (
.din ({lsu_ld0_pcx_rq_sel_d1, lsu_ld1_pcx_rq_sel_d1, lsu_ld2_pcx_rq_sel_d1, lsu_ld3_pcx_rq_sel_d1}),
.q ({ld0_pcx_rq_sel_d2, ld1_pcx_rq_sel_d2, ld2_pcx_rq_sel_d2, ld3_pcx_rq_sel_d2}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Used to complete prefetch. Be careful ! ld could be squashed. Add pcx_req_squash.
assign lsu_ld_pcx_rq_sel_d2[3] = ld3_pcx_rq_sel_d2 ;
assign lsu_ld_pcx_rq_sel_d2[2] = ld2_pcx_rq_sel_d2 ;
assign lsu_ld_pcx_rq_sel_d2[1] = ld1_pcx_rq_sel_d2 ;
assign lsu_ld_pcx_rq_sel_d2[0] = ld0_pcx_rq_sel_d2 ;
//bug2705- kill pcx pick if spec vld kill is set
wire ld_pcxpkt_vld ;
assign ld_pcxpkt_vld =
lsu_ld0_pcx_rq_sel_d1 | lsu_ld1_pcx_rq_sel_d1 | lsu_ld2_pcx_rq_sel_d1 | lsu_ld3_pcx_rq_sel_d1 ;
//ld0_pcx_rq_sel_d1 | ld1_pcx_rq_sel_d1 | ld2_pcx_rq_sel_d1 | ld3_pcx_rq_sel_d1 ;
dff_s #(1) icindx_stgd1 (
.din (ld_pcxpkt_vld),
.q (lsu_ifu_ld_pcxpkt_vld),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire [3:0] ld_pcx_rq_sel ;
assign ld_pcx_rq_sel[0] = ld0_pcx_rq_sel_d1 | st0_atom_rq_d2 ;
assign ld_pcx_rq_sel[1] = ld1_pcx_rq_sel_d1 | st1_atom_rq_d2 ;
assign ld_pcx_rq_sel[2] = ld2_pcx_rq_sel_d1 | st2_atom_rq_d2 ;
assign ld_pcx_rq_sel[3] = ld3_pcx_rq_sel_d1 | st3_atom_rq_d2 ;
//11/7/03: add rst_tri_en
assign lsu_ld_pcx_rq_mxsel[2:0] = ld_pcx_rq_sel[2:0] & {3{~rst_tri_en}} ;
assign lsu_ld_pcx_rq_mxsel[3] = (~|ld_pcx_rq_sel[2:0]) | rst_tri_en ;
assign ld_pcx_thrd[0] = ld_pcx_rq_sel[1] | ld_pcx_rq_sel[3] ;
assign ld_pcx_thrd[1] = ld_pcx_rq_sel[2] | ld_pcx_rq_sel[3] ;
// Assume a simple priority based scheme for now.
// This should not be prioritized at this point.
//assign st_pcx_rq_mhot_sel[0] = st0_pcx_rq_sel_tmp ;
//assign st_pcx_rq_mhot_sel[1] = st1_pcx_rq_sel_tmp ;
//assign st_pcx_rq_mhot_sel[2] = st2_pcx_rq_sel_tmp ;
//assign st_pcx_rq_mhot_sel[3] = st3_pcx_rq_sel_tmp ;
/*assign st_pcx_rq_mhot_sel[0] =
~ld_pcx_rq_vld & st0_pcx_rq_vld ;
assign st_pcx_rq_mhot_sel[1] =
~ld_pcx_rq_vld & st1_pcx_rq_vld ;
assign st_pcx_rq_mhot_sel[2] =
~ld_pcx_rq_vld & st2_pcx_rq_vld ;
assign st_pcx_rq_mhot_sel[3] =
~ld_pcx_rq_vld & st3_pcx_rq_vld ;*/
assign st0_pcx_rq_sel = pcx_rq_for_stb[0] ;
assign st1_pcx_rq_sel = pcx_rq_for_stb[1] ;
assign st2_pcx_rq_sel = pcx_rq_for_stb[2] ;
assign st3_pcx_rq_sel = pcx_rq_for_stb[3] ;
//assign st_pcx_rq_vld = (|pcx_rq_for_stb[3:0]);
// Temporary.
//assign st0_pcx_rq_sel = stb_rd_for_pcx_sel[0] ;
//assign st1_pcx_rq_sel = stb_rd_for_pcx_sel[1] ;
//assign st2_pcx_rq_sel = stb_rd_for_pcx_sel[2] ;
//assign st3_pcx_rq_sel = stb_rd_for_pcx_sel[3] ;
// This will be on a critical path. Massage !!!
// Allows for speculative requests.
//assign st_pcx_rq_vld =
// (st0_pcx_rq_sel & stb_rd_for_pcx_sel[0]) |
// (st1_pcx_rq_sel & stb_rd_for_pcx_sel[1]) |
// (st2_pcx_rq_sel & stb_rd_for_pcx_sel[2]) |
// (st3_pcx_rq_sel & stb_rd_for_pcx_sel[3]) ;
/*assign imiss_pcx_rq_sel =
imiss_pcx_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld) ;
assign strm_pcx_rq_sel =
strm_pcx_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_sel) ;
assign fpop_pcx_rq_sel =
fpop_pcx_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld) ;
assign intrpt_pcx_rq_sel =
intrpt_pcx_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld | fpop_pcx_rq_sel) ;
assign fwdpkt_pcx_rq_sel =
fwdpkt_rq_vld & ~(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld | intrpt_pcx_rq_vld
| fpop_pcx_rq_sel) ; */
//assign imiss_strm_pcx_rq_sel = imiss_pcx_rq_sel | strm_pcx_rq_sel ;
// request was made with the queues full but not grant.
assign pcx_req_squash =
(|(spc_pcx_req_pq_buf2[4:0] & ~pre_qwr[4:0] & ~pcx_spc_grant_px[4:0])) ;
//(|(spc_pcx_req_pq[4:0] & ~queue_write[4:0] & ~pcx_spc_grant_px[4:0])) ;
// (|lsu_error_rst[3:0]) | // dtag parity error requires two ld pkts
// (st_atom_rq_d1) ; // cas,stq - 2 pkt requests
//bug:2877 - dtag parity error 2nd packet request;
//wire error_rst ;
//assign error_rst =
// (ld0_pcx_rq_sel_d1 & lsu_dtag_perror_w2[0]) |
// (ld1_pcx_rq_sel_d1 & lsu_dtag_perror_w2[1]) |
// (ld2_pcx_rq_sel_d1 & lsu_dtag_perror_w2[2]) |
// (ld3_pcx_rq_sel_d1 & lsu_dtag_perror_w2[3]) ;
//wire error_rst_d1 ;
//dff #(1) erst_stgd1 (
// .din (error_rst),
// .q (error_rst_d1),
// .clk (clk),
// .se (1'b0), .si (), .so ()
// );
wire [3:0] dtag_perr_pkt2_vld ;
assign dtag_perr_pkt2_vld[0] = lsu_ld0_pcx_rq_sel_d1 & lsu_dtag_perror_w2[0];
assign dtag_perr_pkt2_vld[1] = lsu_ld1_pcx_rq_sel_d1 & lsu_dtag_perror_w2[1];
assign dtag_perr_pkt2_vld[2] = lsu_ld2_pcx_rq_sel_d1 & lsu_dtag_perror_w2[2];
assign dtag_perr_pkt2_vld[3] = lsu_ld3_pcx_rq_sel_d1 & lsu_dtag_perror_w2[3];
//bug:2877 - dtag parity error 2nd packet request; flop to sync w/ ld?_pcx_rq_sel_d2
dff_s #(4) ff_dtag_perr_pkt2_vld_d1 (
.din (dtag_perr_pkt2_vld[3:0]),
.q (dtag_perr_pkt2_vld_d1[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug:2877 - dtag parity error 2nd packet request; error_rst can be removed from mcycle_mask_d1 since
// it does not behave like an atomic i.e. it is sent as 2 separate packets.
assign mcycle_squash_d1 =
// error_rst | // dtag parity error requires two ld pkts
//(|lsu_error_rst[3:0]) | // dtag parity error requires two ld pkts
spc_pcx_atom_pq_buf2 ; // cas/fpop
dff_s #(1) sqsh_stgd1 (
.din (pcx_req_squash),
.q (pcx_req_squash_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(1) sqsh_stgd2 (
.din (pcx_req_squash_d1),
.q (pcx_req_squash_d2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//timing fix: 9/19/03 - split the lsu_pcx_req_squash to 4 signals to stb_ctl[0-3] to reduce loading
assign lsu_pcx_req_squash = pcx_req_squash & ~st_atom_rq_d1 ;
assign lsu_pcx_req_squash0 = lsu_pcx_req_squash ;
assign lsu_pcx_req_squash1 = lsu_pcx_req_squash ;
assign lsu_pcx_req_squash2 = lsu_pcx_req_squash ;
assign lsu_pcx_req_squash3 = lsu_pcx_req_squash ;
assign lsu_pcx_req_squash_d1 = pcx_req_squash_d1 ;
dff_s #(5) rsel_stgd1 (
//.din ({imiss_strm_pcx_rq_sel,
.din ({
imiss_pcx_rq_sel, strm_pcx_rq_sel, intrpt_pcx_rq_sel, fpop_pcx_rq_sel,
fwdpkt_pcx_rq_sel}),
//.q ({imiss_strm_pcx_rq_sel_d1,
.q ({
imiss_pcx_rq_sel_d1, strm_pcx_rq_sel_d1, intrpt_pcx_rq_sel_d1,fpop_pcx_rq_sel_d1,
fwdpkt_pcx_rq_sel_d1}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign lsu_imiss_pcx_rq_sel_d1 = imiss_pcx_rq_sel_d1;
dff_s imrqs_stgd2 (
.din (imiss_pcx_rq_sel_d1),
.q (imiss_pcx_rq_sel_d2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s fwdrqs_stgd2 (
.din (fwdpkt_pcx_rq_sel_d1),
.q (fwdpkt_pcx_rq_sel_d2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s fwdrqs_stgd3 (
.din (fwdpkt_pcx_rq_sel_d2),
.q (fwdpkt_pcx_rq_sel_d3),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s fpop_stgd2 (
.din (fpop_pcx_rq_sel_d1), .q (fpop_pcx_rq_sel_d2),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug4665: add sehold to pcx_pkt_src_sel[1]
//wire ld_pcx_rq_sel_d1,st_pcx_rq_sel_d1,misc_pcx_rq_sel_d1;
wire ld_pcx_rq_sel_d1,st_pcx_rq_sel_d1;
wire all_pcx_rq_pick_b2 ;
assign all_pcx_rq_pick_b2 = sehold ? st_pcx_rq_sel_d1 : all_pcx_rq_pick[2] ;
dff_s #(2) pick_stgd1 (
.din ({all_pcx_rq_pick_b2, all_pcx_rq_pick[1]}),
.q ({st_pcx_rq_sel_d1,ld_pcx_rq_sel_d1}),
//.din ({all_pcx_rq_pick[3], all_pcx_rq_pick_b2, all_pcx_rq_pick[1]}),
//.q ({misc_pcx_rq_sel_d1,st_pcx_rq_sel_d1,ld_pcx_rq_sel_d1}),
//.din (all_pcx_rq_pick[2:1]), .q ({st_pcx_rq_sel_d1,ld_pcx_rq_sel_d1}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// add other sources in such as interrupt and fpop.
//bug:2877 - dtag parity error 2nd packet request; remove error_rst_d1 since dtag parity error does not
// behave as an atomic
//assign pcx_pkt_src_sel[0] = ld_pcx_rq_sel_d1 | st_cas_rq_d2 | error_rst_d1 ;
//11/7/03 - add rst_tri_en
wire [3:0] pcx_pkt_src_sel_tmp ;
assign pcx_pkt_src_sel_tmp[0] = ld_pcx_rq_sel_d1 | st_cas_rq_d2 ;
assign pcx_pkt_src_sel_tmp[1] = st_pcx_rq_sel_d1 ;
assign pcx_pkt_src_sel_tmp[2] = ~|{pcx_pkt_src_sel[3],pcx_pkt_src_sel[1:0]};
//imiss_strm_pcx_rq_sel_d1 ;
assign pcx_pkt_src_sel_tmp[3] = fpop_pcx_rq_sel_d1 | fpop_pcx_rq_sel_d2 |
fwdpkt_pcx_rq_sel_d1 | intrpt_pcx_rq_sel_d1 ;
//bug4888 - change rst_tri_en to select b[1] instead of b[3]
assign pcx_pkt_src_sel[3:2] = pcx_pkt_src_sel_tmp[3:2] & {2{~rst_tri_en}} ;
assign pcx_pkt_src_sel[1] = pcx_pkt_src_sel_tmp[1] | rst_tri_en ;
assign pcx_pkt_src_sel[0] = pcx_pkt_src_sel_tmp[0] & ~rst_tri_en ;
//assign dest_pkt_sel[0] = ld_pcx_rq_vld ;
//assign dest_pkt_sel[1] = st_pcx_rq_vld ;
//assign dest_pkt_sel[2] = ~(ld_pcx_rq_vld | st_pcx_rq_vld);
//=================================================================================================
// SELECT DESTINATION
//=================================================================================================
// Select dest for load.
mux4ds #(5) ldsel_dest (
.in0 (ld0_l2bnk_dest[4:0]),
.in1 (ld1_l2bnk_dest[4:0]),
.in2 (ld2_l2bnk_dest[4:0]),
.in3 (ld3_l2bnk_dest[4:0]),
.sel0 (ld0_pcx_rq_pick),
.sel1 (ld1_pcx_rq_pick),
.sel2 (ld2_pcx_rq_pick),
.sel3 (ld3_pcx_rq_pick),
.dout (ld_pkt_dest[4:0])
);
// Select dest for store
mux4ds #(5) stsel_dest (
.in0 (st0_l2bnk_dest[4:0]),
.in1 (st1_l2bnk_dest[4:0]),
.in2 (st2_l2bnk_dest[4:0]),
.in3 (st3_l2bnk_dest[4:0]),
.sel0 (st0_pcx_rq_pick),
.sel1 (st1_pcx_rq_pick),
.sel2 (st2_pcx_rq_pick),
.sel3 (st3_pcx_rq_pick),
.dout (st_pkt_dest[4:0])
);
wire [4:0] misc_pkt_dest ;
mux4ds #(5) miscsel_dest (
.in0 (strm_l2bnk_dest[4:0]),
.in1 (fpop_l2bnk_dest[4:0]),
.in2 (intrpt_l2bnk_dest[4:0]),
.in3 (fwdpkt_dest_d1[4:0]),
.sel0 (strm_pcx_rq_pick),
.sel1 (fpop_pcx_rq_pick),
.sel2 (intrpt_pcx_rq_pick),
.sel3 (fwdpkt_pcx_rq_pick),
.dout (misc_pkt_dest[4:0])
);
// This is temporary until the req/ack path is restructured
/*assign imiss_strm_pkt_dest[4:0] =
imiss_pcx_rq_sel ? imiss_l2bnk_dest[4:0] :
strm_pcx_rq_sel ? strm_l2bnk_dest[4:0] :
fpop_pcx_rq_sel ? fpop_l2bnk_dest[4:0] :
intrpt_pcx_rq_sel ? intrpt_l2bnk_dest[4:0] :
lsu_fwdpkt_dest[4:0] ; */
/*
// This needs to be replaced with structural mux once rq/ack resolved.
mux4ds #(5) istrmsel_dest (
.in0 (imiss_l2bnk_dest[4:0]),
.in1 (strm_l2bnk_dest[4:0]),
.in2 (fpop_l2bnk_dest[4:0]),
.in3 (intrpt_l2bnk_dest[4:0]),
.sel0 (imiss_pcx_rq_sel),
.sel1 (strm_pcx_rq_sel),
.sel2 (fpop_pcx_rq_sel),
.sel3 (intrpt_pcx_rq_sel),
.dout (imiss_strm_pkt_dest[4:0])
);
*/
mux4ds #(5) sel_final_dest (
.in0 (imiss_l2bnk_dest[4:0]),
.in1 (ld_pkt_dest[4:0]),
.in2 (st_pkt_dest[4:0]),
.in3 (misc_pkt_dest[4:0]),
.sel0 (all_pcx_rq_pick[0]),
.sel1 (all_pcx_rq_pick[1]),
.sel2 (all_pcx_rq_pick[2]),
.sel3 (all_pcx_rq_dest_sel3),
//.sel3 (all_pcx_rq_pick[3]),
.dout (current_pkt_dest[4:0])
);
/*mux3ds #(5) sel_dest (
.in0 (ld_pkt_dest[4:0]),
.in1 (st_pkt_dest[4:0]),
.in2 (imiss_strm_pkt_dest[4:0]),
.sel0 (dest_pkt_sel[0]),
.sel1 (dest_pkt_sel[1]),
.sel2 (dest_pkt_sel[2]),
.dout (current_pkt_dest[4:0])
);*/
wire pcx_rq_sel ;
assign pcx_rq_sel =
ld0_pcx_rq_sel | ld1_pcx_rq_sel | ld2_pcx_rq_sel | ld3_pcx_rq_sel |
st0_pcx_rq_sel | st1_pcx_rq_sel | st2_pcx_rq_sel | st3_pcx_rq_sel |
imiss_pcx_rq_sel | strm_pcx_rq_sel | fpop_pcx_rq_sel | intrpt_pcx_rq_sel |
fwdpkt_pcx_rq_sel ;
assign spc_pcx_req_g[4:0] =
(current_pkt_dest[4:0] & {5{pcx_rq_sel}}) ;
//(current_pkt_dest[4:0] &
//{5{(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld | intrpt_pcx_rq_vld | fpop_atom_req | fwdpkt_rq_vld)}}) ;
//timing fix: 9/19/03 - instantiate buffer for spc_pcx_req_pq
wire [4:0] spc_pcx_req_pq_tmp ;
dff_s #(5) rq_stgpq (
.din (spc_pcx_req_g[4:0]), .q (spc_pcx_req_pq_tmp[4:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
bw_u1_buf_30x UZfix_spc_pcx_req_pq0_buf1 ( .a(spc_pcx_req_pq_tmp[0]), .z(spc_pcx_req_pq[0]) );
bw_u1_buf_30x UZfix_spc_pcx_req_pq1_buf1 ( .a(spc_pcx_req_pq_tmp[1]), .z(spc_pcx_req_pq[1]) );
bw_u1_buf_30x UZfix_spc_pcx_req_pq2_buf1 ( .a(spc_pcx_req_pq_tmp[2]), .z(spc_pcx_req_pq[2]) );
bw_u1_buf_30x UZfix_spc_pcx_req_pq3_buf1 ( .a(spc_pcx_req_pq_tmp[3]), .z(spc_pcx_req_pq[3]) );
bw_u1_buf_30x UZfix_spc_pcx_req_pq4_buf1 ( .a(spc_pcx_req_pq_tmp[4]), .z(spc_pcx_req_pq[4]) );
bw_u1_buf_30x UZsize_spc_pcx_req_pq0_buf2 ( .a(spc_pcx_req_pq_tmp[0]), .z(spc_pcx_req_pq_buf2[0]) );
bw_u1_buf_30x UZsize_spc_pcx_req_pq1_buf2 ( .a(spc_pcx_req_pq_tmp[1]), .z(spc_pcx_req_pq_buf2[1]) );
bw_u1_buf_30x UZsize_spc_pcx_req_pq2_buf2 ( .a(spc_pcx_req_pq_tmp[2]), .z(spc_pcx_req_pq_buf2[2]) );
bw_u1_buf_30x UZsize_spc_pcx_req_pq3_buf2 ( .a(spc_pcx_req_pq_tmp[3]), .z(spc_pcx_req_pq_buf2[3]) );
bw_u1_buf_30x UZsize_spc_pcx_req_pq4_buf2 ( .a(spc_pcx_req_pq_tmp[4]), .z(spc_pcx_req_pq_buf2[4]) );
//bug3348 - not needed
//wire spc_pcx_req_vld_pq ;
//assign spc_pcx_req_vld_pq = |spc_pcx_req_pq[4:0];
//
//dff #(1) rq_stgpq1 (
// .din (spc_pcx_req_vld_pq), .q (spc_pcx_req_vld_pq1),
// .clk (clk),
// .se (1'b0), .si (), .so ()
// );
assign spc_pcx_req_update_g[4:0] =
(st_atom_rq_d1 | fpop_atom_rq_pq) ?
spc_pcx_req_pq_buf2[4:0] : // Recirculate same request if back to back case - stda, cas etc
(current_pkt_dest[4:0] &
{5{pcx_rq_sel}}) ;
//{5{(ld_pcx_rq_vld | st_pcx_rq_vld | imiss_pcx_rq_vld | strm_pcx_rq_vld | intrpt_pcx_rq_vld | fpop_pcx_rq_vld | fwdpkt_rq_vld)}}) ;
// Standard request
dff_s #(5) urq_stgpq (
.din (spc_pcx_req_update_g[4:0]), .q (spc_pcx_req_update_w2[4:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//=================================================================================================
// 2-CYCLE OP HANDLING
//=================================================================================================
// cas,fpop,dtag-error pkt. dtag-error pkt does not have to be b2b.
// prevent starvation, ensure requests are b2b.
// fpop can only request to fpu.(bit4) cas can only request to L2 (b3:0)
// ** error rst needs to be handled correctly.
// ** This needs to be massaged for timing.
// timing fix: 5/7/03 - delay the mask 1 cycle for stores.
wire [3:0] mcycle_mask_qwr ;
wire [4:0] mcycle_mask_qwr_d1 ;
//assign mcycle_mask_qwr[3:0] =
// ({4{(stb0_rd_for_pcx & st0_atomic_vld)}} & st0_l2bnk_dest[3:0]) |
// ({4{(stb1_rd_for_pcx & st1_atomic_vld)}} & st1_l2bnk_dest[3:0]) |
// ({4{(stb2_rd_for_pcx & st2_atomic_vld)}} & st2_l2bnk_dest[3:0]) |
// ({4{(stb3_rd_for_pcx & st3_atomic_vld)}} & st3_l2bnk_dest[3:0]) ;
//bug4513- kill the atomic store pcx req in this cycle if only 1 entry is available -
// atomic packets have to be sent b2bto pcx.
//
// ex. thread0 to l2 bank0 atomic store - w/ only 1 bank0 entry available
//---------------------------------------------------------------------------------
// 1 2 3 4 5 6 7
//---------------------------------------------------------------------------------
// st0_atomic_vld-------------->1
// pcx_rq_for_stb_tmp[0]------->1
// pcx_rq_for_stb[0]----------->0 1
// st0_qmon_2entry_avail------->0 1
//---------------------------------------------------------------------------------
// st0_atomic_pend------------->1 0
// st0_atomic_pend_d1------------------>1 0
// mcycle_mask_qwr_d1[0]--------------->1 0
//---------------------------------------------------------------------------------
assign st0_qmon_2entry_avail = |(st0_l2bnk_dest[3:0] & sel_qentry0[3:0]) ;
assign st1_qmon_2entry_avail = |(st1_l2bnk_dest[3:0] & sel_qentry0[3:0]) ;
assign st2_qmon_2entry_avail = |(st2_l2bnk_dest[3:0] & sel_qentry0[3:0]) ;
assign st3_qmon_2entry_avail = |(st3_l2bnk_dest[3:0] & sel_qentry0[3:0]) ;
assign fpop_qmon_2entry_avail = fpop_l2bnk_dest[4] & sel_qentry0[4] ;
//bug4513 - when atomic is picked, if 2 entries are not free, kill all requests until 2entries are free
wire st0_atomic_pend, st1_atomic_pend, st2_atomic_pend, st3_atomic_pend ;
assign st0_atomic_pend = (pcx_rq_for_stb_tmp[0] & st0_atomic_vld & ~st0_qmon_2entry_avail) | //set
(st0_atomic_pend_d1 & ~st0_qmon_2entry_avail) ; //recycle/reset
assign st1_atomic_pend = (pcx_rq_for_stb_tmp[1] & st1_atomic_vld & ~st1_qmon_2entry_avail) | //set
(st1_atomic_pend_d1 & ~st1_qmon_2entry_avail) ; //recycle/reset
assign st2_atomic_pend = (pcx_rq_for_stb_tmp[2] & st2_atomic_vld & ~st2_qmon_2entry_avail) | //set
(st2_atomic_pend_d1 & ~st2_qmon_2entry_avail) ; //recycle/reset
assign st3_atomic_pend = (pcx_rq_for_stb_tmp[3] & st3_atomic_vld & ~st3_qmon_2entry_avail) | //set
(st3_atomic_pend_d1 & ~st3_qmon_2entry_avail) ; //recycle/reset
dff_s #(4) ff_st0to3_atomic_pend_d1 (
.din ({st3_atomic_pend,st2_atomic_pend,st1_atomic_pend,st0_atomic_pend}),
.q ({st3_atomic_pend_d1,st2_atomic_pend_d1,st1_atomic_pend_d1,st0_atomic_pend_d1}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//bug4513 - kill all requests after atomic if 2 entries to the bank are not available
assign mcycle_mask_qwr[3:0] =
({4{st0_atomic_pend}} & st0_l2bnk_dest[3:0]) |
({4{st1_atomic_pend}} & st1_l2bnk_dest[3:0]) |
({4{st2_atomic_pend}} & st2_l2bnk_dest[3:0]) |
({4{st3_atomic_pend}} & st3_l2bnk_dest[3:0]) ;
//11/15/03 - change fpop atomic to be same as store atomic (bug4513)
//assign mcycle_mask_qwr[4] = fpop_pkt_vld | fpop_pcx_rq_sel_d1 ;
wire fpop_atomic_pend, fpop_atomic_pend_d1 ;
assign fpop_atomic_pend = (fpop_pcx_rq_sel_tmp & ~fpop_qmon_2entry_avail) |
(fpop_atomic_pend_d1 & ~fpop_qmon_2entry_avail) ;
assign fpop_q_wr[4:0] = fpop_atomic_pend_d1 ? pre_qwr[4:0] : queue_write[4:0] ;
dff_s #(1) ff_fpop_atomic_pend_d1 (
.din (fpop_atomic_pend),
.q (fpop_atomic_pend_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(5) ff_mcycle_mask_qwr_b4to0 (
.din ({fpop_atomic_pend,mcycle_mask_qwr[3:0]}),
.q (mcycle_mask_qwr_d1[4:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// PCX REQUEST GENERATION (END)
//*************************************************************************************************
//=================================================================================================
//
// CPX Packet Processing
//
//=================================================================================================
// D-SIDE PROCESSING
/*input [3:0] lsu_cpx_pkt_rqtype ;
input lsu_cpx_pkt_vld ;*/
// non-cacheables are processed at the head of the dfq.
// cpx_ld_type may not have to factor in strm load.
//=================================================================================================
//
// PCX Queue Control
//
//=================================================================================================
//timing fix: 5/7/03 - delay mask 1 cycle for stores
//11/15/03 - change fpop atomic to be same as store atomic (bug4513)
//assign queue_write[4:0] = pre_qwr[4:0] & ~{mcycle_mask_qwr[4],mcycle_mask_qwr_d1[3:0]} ;
assign queue_write[4:0] = pre_qwr[4:0] & ~mcycle_mask_qwr_d1[4:0] ;
//bug4513 - mcycle_mask_qwr will kill all requests other than stores. stores can be killed
// by fpop atomics
//11/14/03- fox for bug4513 was incorrect ; st_queue_write[3:0] not needed 'cos st[0-3]_q_wr
// has been changed to use st0_atomic_pend instead of st0_atomic_vld
//assign st_queue_write[4] = pre_qwr[4] & ~mcycle_mask_qwr[4] ;
//assign st_queue_write[3:0] = pre_qwr[3:0] ;
//assign queue_write[4:0] = pre_qwr[4:0] & ~mcycle_mask_qwr[4:0] ; // timing fix
// assign queue_write[4:0] = pre_qwr[4:0] ;
// PCX Queue Control
// - qctl tracks 2-input queue state for each of 6 destinations
// through grant signals available from pcx.
// L2 Bank0 Queue Monitor
lsu_pcx_qmon l2bank0_qmon (
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.si(),
.se(se),
.so(),
.send_by_pcx (pcx_spc_grant_px[0]),
.send_to_pcx (spc_pcx_req_update_w2[0]),
//.qwrite (queue_write[0]),
.qwrite (pre_qwr[0]),
.sel_qentry0 (sel_qentry0[0])
);
// L2 Bank1 Queue Monitor
lsu_pcx_qmon l2bank1_qmon (
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.si(),
.se(se),
.so(),
.send_by_pcx (pcx_spc_grant_px[1]),
.send_to_pcx (spc_pcx_req_update_w2[1]),
//.qwrite (queue_write[1]),
.qwrite (pre_qwr[1]),
.sel_qentry0 (sel_qentry0[1])
);
// L2 Bank2 Queue Monitor
lsu_pcx_qmon l2bank2_qmon (
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.si(),
.se(se),
.so(),
.send_by_pcx (pcx_spc_grant_px[2]),
.send_to_pcx (spc_pcx_req_update_w2[2]),
//.qwrite (queue_write[2]),
.qwrite (pre_qwr[2]),
.sel_qentry0 (sel_qentry0[2])
);
// L2 Bank3 Queue Monitor
lsu_pcx_qmon l2bank3_qmon (
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.si(),
.se(se),
.so(),
.send_by_pcx (pcx_spc_grant_px[3]),
.send_to_pcx (spc_pcx_req_update_w2[3]),
//.qwrite (queue_write[3]),
.qwrite (pre_qwr[3]),
.sel_qentry0 (sel_qentry0[3])
);
// FP/IO Bridge Queue Monitor
lsu_pcx_qmon fpiobridge_qmon (
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.si(),
.se(se),
.so(),
.send_by_pcx (pcx_spc_grant_px[4]),
.send_to_pcx (spc_pcx_req_update_w2[4]),
//.qwrite (queue_write[4]),
.qwrite (pre_qwr[4]),
.sel_qentry0 (sel_qentry0[4])
);
// 5/13/03: timing fix for lsu_dtag_perror_w2 thru st_pick
wire [3:0] error_en;
wire [3:0] error_rst_thrd;
//assign error_en[0] = lmq_enable[0] | (lsu_cpx_pkt_atm_st_cmplt & dcfill_active_e & dfq_byp_sel[0]);
assign error_en[0] = lsu_ld_inst_vld_g[0];
assign error_en[1] = lsu_ld_inst_vld_g[1];
assign error_en[2] = lsu_ld_inst_vld_g[2];
assign error_en[3] = lsu_ld_inst_vld_g[3];
//assign error_rst_thrd[0] = reset | (lsu_ld0_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ;
//assign error_rst_thrd[1] = reset | (lsu_ld1_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ;
//assign error_rst_thrd[2] = reset | (lsu_ld2_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ;
//assign error_rst_thrd[3] = reset | (lsu_ld3_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ;
// reset moved to d2 'cos if 1st pkt is speculative and grant=0, error should not be reset.
//bug4512 - stb_full_raw has to be qual w/ ld[0-3] inst_vld_w2
// also, need to qualify stb_full_raw w/ fp loads i.e. dont reset error if full raw is for fp double loads
assign error_rst_thrd[0] = reset | (ld0_pcx_rq_sel_d2 & ~pcx_req_squash_d1)
| (ld0_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 & thread0_w2) ; // Bug4512
//| (ld_stb_full_raw_w2 & thread0_w2) ; // Bug 4361
assign error_rst_thrd[1] = reset | (ld1_pcx_rq_sel_d2 & ~pcx_req_squash_d1)
| (ld1_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 & thread1_w2) ;
assign error_rst_thrd[2] = reset | (ld2_pcx_rq_sel_d2 & ~pcx_req_squash_d1)
| (ld2_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 & thread2_w2) ;
assign error_rst_thrd[3] = reset | (ld3_pcx_rq_sel_d2 & ~pcx_req_squash_d1)
| (ld3_inst_vld_w2 & ld_stb_full_raw_w2 & ~dbl_force_l2access_w2 & thread3_w2) ;
//assign lsu_error_rst[3:0] = error_rst[3:0];
wire dtag_perror3,dtag_perror2,dtag_perror1,dtag_perror0;
// Thread 0
dffre_s #(1) error_t0 (
.din (lsu_dcache_tag_perror_g),
.q (dtag_perror0),
.rst (error_rst_thrd[0]), .en (error_en[0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread 1
dffre_s #(1) error_t1 (
.din (lsu_dcache_tag_perror_g),
.q (dtag_perror1),
.rst (error_rst_thrd[1]), .en (error_en[1]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread 2
dffre_s #(1) error_t2 (
.din (lsu_dcache_tag_perror_g),
.q (dtag_perror2),
.rst (error_rst_thrd[2]), .en (error_en[2]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread 3
dffre_s #(1) error_t3 (
.din (lsu_dcache_tag_perror_g),
.q (dtag_perror3),
.rst (error_rst_thrd[3]), .en (error_en[3]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign lsu_dtag_perror_w2[3] = dtag_perror3 ;
assign lsu_dtag_perror_w2[2] = dtag_perror2 ;
assign lsu_dtag_perror_w2[1] = dtag_perror1 ;
assign lsu_dtag_perror_w2[0] = dtag_perror0 ;
// Determine if ld pkt requires correction due to dtag parity error.
assign lsu_pcx_ld_dtag_perror_w2 =
ld_pcx_rq_sel[0] ? dtag_perror0 :
ld_pcx_rq_sel[1] ? dtag_perror1 :
ld_pcx_rq_sel[2] ? dtag_perror2 : dtag_perror3 ;
//=================================================================================================
//
// THREAD RETRY DETECTION (picker related logic)
//
//=================================================================================================
//bug4814 - move pick_staus out of picker and reset pick status when all 12 valid requests have
// is picked and not squashed.
assign ld_thrd_pick_din[0] = ld_thrd_pick_status[0] | (ld0_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ;
assign ld_thrd_pick_din[1] = ld_thrd_pick_status[1] | (ld1_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ;
assign ld_thrd_pick_din[2] = ld_thrd_pick_status[2] | (ld2_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ;
assign ld_thrd_pick_din[3] = ld_thrd_pick_status[3] | (ld3_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ;
assign ld_thrd_pick_rst = ~|(ld_events_raw[3:0] & ~ld_thrd_pick_din[3:0]) ;
assign ld_thrd_pick_status_din[3:0] = ld_thrd_pick_din[3:0] & ~{4{all_thrd_pick_rst}} ;
//assign ld_thrd_pick_status_din[3:0] = ld_thrd_pick_din[3:0] & ~{4{ld_thrd_pick_rst}} ;
assign st_thrd_pick_din[0] = st_thrd_pick_status[0] | (st0_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ;
assign st_thrd_pick_din[1] = st_thrd_pick_status[1] | (st1_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ;
assign st_thrd_pick_din[2] = st_thrd_pick_status[2] | (st2_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ;
assign st_thrd_pick_din[3] = st_thrd_pick_status[3] | (st3_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ;
assign st_thrd_pick_rst = ~|(st_events_raw[3:0] & ~st_thrd_pick_din[3:0]) ;
assign st_thrd_pick_status_din[3:0] = st_thrd_pick_din[3:0] & ~{4{all_thrd_pick_rst}} ;
//assign st_thrd_pick_status_din[3:0] = st_thrd_pick_din[3:0] & ~{4{st_thrd_pick_rst}} ;
assign misc_thrd_pick_din[3] = misc_thrd_pick_status[3] | lsu_spu_ldst_ack ;
assign misc_thrd_pick_din[2] = misc_thrd_pick_status[2] | (fpop_pcx_rq_sel_d2 & ~pcx_req_squash_d1) ;
assign misc_thrd_pick_din[1] = misc_thrd_pick_status[1] | lsu_tlu_pcxpkt_ack ;
assign misc_thrd_pick_din[0] = misc_thrd_pick_status[0] | lsu_fwdpkt_pcx_rq_sel ;
assign misc_thrd_pick_rst = ~|(misc_events_raw[3:0] & ~misc_thrd_pick_din[3:0]) ;
assign misc_thrd_pick_status_din[3:0] = misc_thrd_pick_din[3:0] & ~{4{all_thrd_pick_rst}} ;
//assign misc_thrd_pick_status_din[3:0] = misc_thrd_pick_din[3:0] & ~{4{misc_thrd_pick_rst}} ;
assign all_thrd_pick_rst = ld_thrd_pick_rst & st_thrd_pick_rst & misc_thrd_pick_rst ;
dff_s #(4) ff_ld_thrd_force(
.din (ld_thrd_pick_status_din[3:0]),
.q (ld_thrd_pick_status[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(4) ff_st_thrd_force(
.din (st_thrd_pick_status_din[3:0]),
.q (st_thrd_pick_status[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(4) ff_misc_thrd_force(
.din (misc_thrd_pick_status_din[3:0]),
.q (misc_thrd_pick_status[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign ld_thrd_force_d1[3:0] = ~ld_thrd_pick_status[3:0] ;
assign st_thrd_force_d1[3:0] = ~st_thrd_pick_status[3:0] ;
assign misc_thrd_force_d1[3:0] = ~misc_thrd_pick_status[3:0] ;
assign ld_thrd_force_vld[0] = ld_thrd_force_d1[0] &
~(ld0_pcx_rq_sel_d1 | ld0_pcx_rq_sel_d2) ;
assign ld_thrd_force_vld[1] = ld_thrd_force_d1[1] &
~(ld1_pcx_rq_sel_d1 | ld1_pcx_rq_sel_d2) ;
assign ld_thrd_force_vld[2] = ld_thrd_force_d1[2] &
~(ld2_pcx_rq_sel_d1 | ld2_pcx_rq_sel_d2) ;
assign ld_thrd_force_vld[3] = ld_thrd_force_d1[3] &
~(ld3_pcx_rq_sel_d1 | ld3_pcx_rq_sel_d2) ;
// force valid to store picker if 1 entry is free and if it not picked in d1/d2
assign st_thrd_force_vld[0] = st_thrd_force_d1[0] &
~(st0_pcx_rq_sel_d1 | st0_pcx_rq_sel_d2) ;
assign st_thrd_force_vld[1] = st_thrd_force_d1[1] &
~(st1_pcx_rq_sel_d1 | st1_pcx_rq_sel_d2) ;
assign st_thrd_force_vld[2] = st_thrd_force_d1[2] &
~(st2_pcx_rq_sel_d1 | st2_pcx_rq_sel_d2) ;
assign st_thrd_force_vld[3] = st_thrd_force_d1[3] &
~(st3_pcx_rq_sel_d1 | st3_pcx_rq_sel_d2) ;
// force valid to misc picker if 1 entry is free and if it is not picked in d1/d2
assign misc_thrd_force_vld[0] = misc_thrd_force_d1[0] &
~(fwdpkt_pcx_rq_sel_d1 | fwdpkt_pcx_rq_sel_d2) ;
assign misc_thrd_force_vld[1] = misc_thrd_force_d1[1] &
~(intrpt_pcx_rq_sel_d1 | intrpt_pcx_rq_sel_d2);
assign misc_thrd_force_vld[2] = misc_thrd_force_d1[2] &
~(fpop_pcx_rq_sel_d1 | fpop_pcx_rq_sel_d2) ;
assign misc_thrd_force_vld[3] = misc_thrd_force_d1[3] &
~(strm_pcx_rq_sel_d1 | strm_pcx_rq_sel_d2) ;
//2nd level pick thread force - force only req are valid and l2bnk is free
assign all_thrd_force_vld[0] = 1'b0 ;
assign all_thrd_force_vld[1] =
|(ld_thrd_force_vld[3:0] &
{ld3_pcx_rq_vld,ld2_pcx_rq_vld,ld1_pcx_rq_vld,ld0_pcx_rq_vld}) ;
assign all_thrd_force_vld[2] =
|(st_thrd_force_vld[3:0] &
{st3_pcx_rq_vld,st2_pcx_rq_vld,st1_pcx_rq_vld,st0_pcx_rq_vld}) ;
assign all_thrd_force_vld[3] =
|(misc_thrd_force_vld[3:0] &
{strm_pcx_rq_vld,fpop_pcx_rq_vld,intrpt_pcx_rq_vld,fwdpkt_rq_vld}) ;
endmodule |
module para2ser(
input clk,
input rst_n,
input trans_start, // indicate tansform begin, level signal
input [8:0] data, // signal:0-9 max coding length:9
input [3:0] data_len, // 9 - 1
output wire output_data, // MSB first
output wire output_start,
output wire output_done
);
reg [3:0] data_cnt;
reg [8:0] data_reg;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
data_cnt <= 4'b0;
data_reg <= 9'b0;
end
else if(trans_start) begin
data_cnt <= (data_cnt == 4'b0) ? data_len-1 : data_cnt-1;
data_reg <= data;
end
end
reg trans_start_q1;
reg trans_start_q2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
trans_start_q1 <= 1'b0;
trans_start_q2 <= 1'b0;
end
else begin
trans_start_q1 <= trans_start;
trans_start_q2 <= trans_start_q1;
end
end
assign output_start = trans_start & ~trans_start_q1;
assign output_done = ~trans_start_q1 & trans_start_q2;
assign output_data = (data_reg >> data_cnt) & 1'b1;
endmodule |
module ik_swift (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire hps_io_hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_hps_io_spim0_inst_CLK, // .hps_io_spim0_inst_CLK
output wire hps_io_hps_io_spim0_inst_MOSI, // .hps_io_spim0_inst_MOSI
input wire hps_io_hps_io_spim0_inst_MISO, // .hps_io_spim0_inst_MISO
output wire hps_io_hps_io_spim0_inst_SS0, // .hps_io_spim0_inst_SS0
output wire hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
output wire [7:0] ik_R, // ik.R
output wire [7:0] ik_G, // .G
output wire [7:0] ik_B, // .B
output wire ik_CLK, // .CLK
output wire ik_HS, // .HS
output wire ik_VS, // .VS
output wire ik_BLANK_n, // .BLANK_n
output wire ik_SYNC_n // .SYNC_n
);
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awvalid
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arsize
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlock
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awcache
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arid
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_rready
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_bready
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awsize
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awprot
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arvalid
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arprot
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlen
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awid
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wid
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlock
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awburst
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arburst
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_araddr
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arcache
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlen
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awaddr
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wvalid
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wlast
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire [31:0] mm_interconnect_0_ik_driver_0_avalon_slave_0_writedata; // mm_interconnect_0:ik_driver_0_avalon_slave_0_writedata -> ik_driver_0:writedata
wire [4:0] mm_interconnect_0_ik_driver_0_avalon_slave_0_address; // mm_interconnect_0:ik_driver_0_avalon_slave_0_address -> ik_driver_0:address
wire mm_interconnect_0_ik_driver_0_avalon_slave_0_chipselect; // mm_interconnect_0:ik_driver_0_avalon_slave_0_chipselect -> ik_driver_0:chipselect
wire mm_interconnect_0_ik_driver_0_avalon_slave_0_write; // mm_interconnect_0:ik_driver_0_avalon_slave_0_write -> ik_driver_0:write
wire master_0_master_waitrequest; // mm_interconnect_0:master_0_master_waitrequest -> master_0:master_waitrequest
wire [31:0] master_0_master_writedata; // master_0:master_writedata -> mm_interconnect_0:master_0_master_writedata
wire [31:0] master_0_master_address; // master_0:master_address -> mm_interconnect_0:master_0_master_address
wire master_0_master_write; // master_0:master_write -> mm_interconnect_0:master_0_master_write
wire master_0_master_read; // master_0:master_read -> mm_interconnect_0:master_0_master_read
wire [31:0] master_0_master_readdata; // mm_interconnect_0:master_0_master_readdata -> master_0:master_readdata
wire [3:0] master_0_master_byteenable; // master_0:master_byteenable -> mm_interconnect_0:master_0_master_byteenable
wire master_0_master_readdatavalid; // mm_interconnect_0:master_0_master_readdatavalid -> master_0:master_readdatavalid
wire [31:0] hps_0_f2h_irq0_irq; // irq_mapper:sender_irq -> hps_0:f2h_irq_p0
wire [31:0] hps_0_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps_0:f2h_irq_p1
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [ik_driver_0:reset, mm_interconnect_0:ik_driver_0_reset_sink_reset_bridge_in_reset_reset, mm_interconnect_0:master_0_clk_reset_reset_bridge_in_reset_reset]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
wire hps_0_h2f_reset_reset; // hps_0:h2f_rst_n -> rst_controller_001:reset_in0
ik_swift_hps_0 #(
.F2S_Width (2),
.S2F_Width (2)
) hps_0 (
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim0_inst_CLK (hps_io_hps_io_spim0_inst_CLK), // .hps_io_spim0_inst_CLK
.hps_io_spim0_inst_MOSI (hps_io_hps_io_spim0_inst_MOSI), // .hps_io_spim0_inst_MOSI
.hps_io_spim0_inst_MISO (hps_io_hps_io_spim0_inst_MISO), // .hps_io_spim0_inst_MISO
.hps_io_spim0_inst_SS0 (hps_io_hps_io_spim0_inst_SS0), // .hps_io_spim0_inst_SS0
.hps_io_spim1_inst_CLK (hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.h2f_rst_n (hps_0_h2f_reset_reset), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (), // h2f_axi_master.awid
.h2f_AWADDR (), // .awaddr
.h2f_AWLEN (), // .awlen
.h2f_AWSIZE (), // .awsize
.h2f_AWBURST (), // .awburst
.h2f_AWLOCK (), // .awlock
.h2f_AWCACHE (), // .awcache
.h2f_AWPROT (), // .awprot
.h2f_AWVALID (), // .awvalid
.h2f_AWREADY (), // .awready
.h2f_WID (), // .wid
.h2f_WDATA (), // .wdata
.h2f_WSTRB (), // .wstrb
.h2f_WLAST (), // .wlast
.h2f_WVALID (), // .wvalid
.h2f_WREADY (), // .wready
.h2f_BID (), // .bid
.h2f_BRESP (), // .bresp
.h2f_BVALID (), // .bvalid
.h2f_BREADY (), // .bready
.h2f_ARID (), // .arid
.h2f_ARADDR (), // .araddr
.h2f_ARLEN (), // .arlen
.h2f_ARSIZE (), // .arsize
.h2f_ARBURST (), // .arburst
.h2f_ARLOCK (), // .arlock
.h2f_ARCACHE (), // .arcache
.h2f_ARPROT (), // .arprot
.h2f_ARVALID (), // .arvalid
.h2f_ARREADY (), // .arready
.h2f_RID (), // .rid
.h2f_RDATA (), // .rdata
.h2f_RRESP (), // .rresp
.h2f_RLAST (), // .rlast
.h2f_RVALID (), // .rvalid
.h2f_RREADY (), // .rready
.f2h_axi_clk (clk_clk), // f2h_axi_clock.clk
.f2h_AWID (), // f2h_axi_slave.awid
.f2h_AWADDR (), // .awaddr
.f2h_AWLEN (), // .awlen
.f2h_AWSIZE (), // .awsize
.f2h_AWBURST (), // .awburst
.f2h_AWLOCK (), // .awlock
.f2h_AWCACHE (), // .awcache
.f2h_AWPROT (), // .awprot
.f2h_AWVALID (), // .awvalid
.f2h_AWREADY (), // .awready
.f2h_AWUSER (), // .awuser
.f2h_WID (), // .wid
.f2h_WDATA (), // .wdata
.f2h_WSTRB (), // .wstrb
.f2h_WLAST (), // .wlast
.f2h_WVALID (), // .wvalid
.f2h_WREADY (), // .wready
.f2h_BID (), // .bid
.f2h_BRESP (), // .bresp
.f2h_BVALID (), // .bvalid
.f2h_BREADY (), // .bready
.f2h_ARID (), // .arid
.f2h_ARADDR (), // .araddr
.f2h_ARLEN (), // .arlen
.f2h_ARSIZE (), // .arsize
.f2h_ARBURST (), // .arburst
.f2h_ARLOCK (), // .arlock
.f2h_ARCACHE (), // .arcache
.f2h_ARPROT (), // .arprot
.f2h_ARVALID (), // .arvalid
.f2h_ARREADY (), // .arready
.f2h_ARUSER (), // .aruser
.f2h_RID (), // .rid
.f2h_RDATA (), // .rdata
.f2h_RRESP (), // .rresp
.f2h_RLAST (), // .rlast
.f2h_RVALID (), // .rvalid
.f2h_RREADY (), // .rready
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_0_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_0_f2h_irq1_irq) // f2h_irq1.irq
);
ik_swift_master_0 #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) master_0 (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (master_0_master_address), // master.address
.master_readdata (master_0_master_readdata), // .readdata
.master_read (master_0_master_read), // .read
.master_write (master_0_master_write), // .write
.master_writedata (master_0_master_writedata), // .writedata
.master_waitrequest (master_0_master_waitrequest), // .waitrequest
.master_readdatavalid (master_0_master_readdatavalid), // .readdatavalid
.master_byteenable (master_0_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
IK_DRIVER ik_driver_0 (
.clk (clk_clk), // clock.clk
.writedata (mm_interconnect_0_ik_driver_0_avalon_slave_0_writedata), // avalon_slave_0.writedata
.write (mm_interconnect_0_ik_driver_0_avalon_slave_0_write), // .write
.chipselect (mm_interconnect_0_ik_driver_0_avalon_slave_0_chipselect), // .chipselect
.address (mm_interconnect_0_ik_driver_0_avalon_slave_0_address), // .address
.reset (rst_controller_reset_out_reset), // reset_sink.reset
.VGA_R (ik_R), // conduit_end.export
.VGA_G (ik_G), // .export
.VGA_B (ik_B), // .export
.VGA_CLK (ik_CLK), // .export
.VGA_HS (ik_HS), // .export
.VGA_VS (ik_VS), // .export
.VGA_BLANK_n (ik_BLANK_n), // .export
.VGA_SYNC_n (ik_SYNC_n) // .export
);
ik_swift_mm_interconnect_0 mm_interconnect_0 (
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.ik_driver_0_reset_sink_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // ik_driver_0_reset_sink_reset_bridge_in_reset.reset
.master_0_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // master_0_clk_reset_reset_bridge_in_reset.reset
.master_0_master_address (master_0_master_address), // master_0_master.address
.master_0_master_waitrequest (master_0_master_waitrequest), // .waitrequest
.master_0_master_byteenable (master_0_master_byteenable), // .byteenable
.master_0_master_read (master_0_master_read), // .read
.master_0_master_readdata (master_0_master_readdata), // .readdata
.master_0_master_readdatavalid (master_0_master_readdatavalid), // .readdatavalid
.master_0_master_write (master_0_master_write), // .write
.master_0_master_writedata (master_0_master_writedata), // .writedata
.ik_driver_0_avalon_slave_0_address (mm_interconnect_0_ik_driver_0_avalon_slave_0_address), // ik_driver_0_avalon_slave_0.address
.ik_driver_0_avalon_slave_0_write (mm_interconnect_0_ik_driver_0_avalon_slave_0_write), // .write
.ik_driver_0_avalon_slave_0_writedata (mm_interconnect_0_ik_driver_0_avalon_slave_0_writedata), // .writedata
.ik_driver_0_avalon_slave_0_chipselect (mm_interconnect_0_ik_driver_0_avalon_slave_0_chipselect) // .chipselect
);
ik_swift_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_0_f2h_irq0_irq) // sender.irq
);
ik_swift_irq_mapper irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_0_f2h_irq1_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~hps_0_h2f_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module dff#(
parameter WIDTH = 1
) (
input wire clk,
input wire rst,
input wire [WIDTH-1:0] inp,
output reg [WIDTH-1:0] outp
);
always @(posedge clk) begin
outp <= rst ? 0 : inp;
end
endmodule |
module sky130_fd_sc_ms__o2111a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module processor(
input wire mclk,
// For Physical EPP Memory Interface
/*input wire epp_astb,
input wire epp_dstb,
input wire epp_wr,
output wire epp_wait,
inout wire[7:0] epp_data,*/
// For Simulated Memory Interface
input wire core_stall,
output wire memory_read,
output wire memory_write,
output wire[31:0] memory_address,
output wire[31:0] memory_din,
input wire[31:0] memory_dout,
input wire[7:0] switch,
input wire[3:0] button,
output wire[7:0] seg,
output wire[3:0] digit,
output wire hsync,
output wire vsync,
output wire[7:0] color
);
// Combinational
assign seg[7] = 1'b1;
// State
wire[3:0] enable = 4'b1111;
// For Physical EPP Memory Interface
/*wire core_stall;
wire memory_read;
wire memory_write;
wire[31:0] memory_address;
wire[31:0] memory_din;
wire[31:0] memory_dout;*/
// Displays
wire[15:0] digit_values;
wire[11:0] vga_write_address;
wire[7:0] vga_write_data;
wire vga_write_enable;
// Modules
core core_inst(
.mclk(mclk),
.stall(core_stall),
.dbg(digit_values),
.mem_address(memory_address),
.mem_din(memory_din),
.mem_dout(memory_dout),
.mem_re(memory_read),
.mem_we(memory_write),
.vga_address(vga_write_address),
.vga_data(vga_write_data),
.vga_we(vga_write_enable)
);
// For Physical EPP Memory Interface
/*memory memory_inst(
.mclk(mclk),
.epp_astb(epp_astb),
.epp_dstb(epp_dstb),
.epp_wr(epp_wr),
.epp_wait(epp_wait),
.epp_data(epp_data),
.core_stall(core_stall),
.read(memory_read),
.write(memory_write),
.address(memory_address),
.din(memory_din),
.dout(memory_dout)
);*/
digits digits_inst(
.seg(seg[6:0]),
.digit(digit),
.mclk(mclk),
.enable(enable),
.values(digit_values)
);
vga vga_inst(
.mclk(mclk),
.hsync(hsync),
.vsync(vsync),
.standard(switch[7:4]),
.emphasized(switch[3:0]),
.background(button),
.write_address(vga_write_address),
.write_data(vga_write_data),
.write_enable(vga_write_enable),
.color(color)
);
endmodule |
module outputs
wire [193 : 0] csr_trap_actions;
wire [129 : 0] csr_ret_actions;
wire [128 : 0] mav_csr_write;
wire [64 : 0] mav_read_csr, read_csr, read_csr_port2;
wire [63 : 0] csr_mip_read,
read_csr_mcycle,
read_csr_minstret,
read_csr_mtime,
read_mstatus,
read_satp,
read_ustatus;
wire [27 : 0] read_misa;
wire [4 : 0] interrupt_pending;
wire RDY_csr_ret_actions,
RDY_csr_trap_actions,
RDY_debug,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
access_permitted_1,
access_permitted_2,
csr_counter_read_fault,
nmi_pending,
wfi_resume;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register csr_mstatus_rg_mstatus
reg [63 : 0] csr_mstatus_rg_mstatus;
reg [63 : 0] csr_mstatus_rg_mstatus$D_IN;
wire csr_mstatus_rg_mstatus$EN;
// register rg_dcsr
reg [31 : 0] rg_dcsr;
wire [31 : 0] rg_dcsr$D_IN;
wire rg_dcsr$EN;
// register rg_dpc
reg [63 : 0] rg_dpc;
wire [63 : 0] rg_dpc$D_IN;
wire rg_dpc$EN;
// register rg_dscratch0
reg [63 : 0] rg_dscratch0;
wire [63 : 0] rg_dscratch0$D_IN;
wire rg_dscratch0$EN;
// register rg_dscratch1
reg [63 : 0] rg_dscratch1;
wire [63 : 0] rg_dscratch1$D_IN;
wire rg_dscratch1$EN;
// register rg_mcause
reg [4 : 0] rg_mcause;
reg [4 : 0] rg_mcause$D_IN;
wire rg_mcause$EN;
// register rg_mcounteren
reg [2 : 0] rg_mcounteren;
wire [2 : 0] rg_mcounteren$D_IN;
wire rg_mcounteren$EN;
// register rg_mcycle
reg [63 : 0] rg_mcycle;
wire [63 : 0] rg_mcycle$D_IN;
wire rg_mcycle$EN;
// register rg_mepc
reg [63 : 0] rg_mepc;
wire [63 : 0] rg_mepc$D_IN;
wire rg_mepc$EN;
// register rg_minstret
reg [63 : 0] rg_minstret;
wire [63 : 0] rg_minstret$D_IN;
wire rg_minstret$EN;
// register rg_mscratch
reg [63 : 0] rg_mscratch;
wire [63 : 0] rg_mscratch$D_IN;
wire rg_mscratch$EN;
// register rg_mtval
reg [63 : 0] rg_mtval;
wire [63 : 0] rg_mtval$D_IN;
wire rg_mtval$EN;
// register rg_mtvec
reg [62 : 0] rg_mtvec;
wire [62 : 0] rg_mtvec$D_IN;
wire rg_mtvec$EN;
// register rg_nmi
reg rg_nmi;
wire rg_nmi$D_IN, rg_nmi$EN;
// register rg_nmi_vector
reg [63 : 0] rg_nmi_vector;
wire [63 : 0] rg_nmi_vector$D_IN;
wire rg_nmi_vector$EN;
// register rg_state
reg rg_state;
wire rg_state$D_IN, rg_state$EN;
// register rg_tdata1
reg [63 : 0] rg_tdata1;
wire [63 : 0] rg_tdata1$D_IN;
wire rg_tdata1$EN;
// register rg_tdata2
reg [63 : 0] rg_tdata2;
wire [63 : 0] rg_tdata2$D_IN;
wire rg_tdata2$EN;
// register rg_tdata3
reg [63 : 0] rg_tdata3;
wire [63 : 0] rg_tdata3$D_IN;
wire rg_tdata3$EN;
// register rg_tselect
reg [63 : 0] rg_tselect;
wire [63 : 0] rg_tselect$D_IN;
wire rg_tselect$EN;
// ports of submodule csr_mie
wire [63 : 0] csr_mie$mav_write, csr_mie$mav_write_wordxl, csr_mie$mv_read;
wire [27 : 0] csr_mie$mav_write_misa;
wire csr_mie$EN_mav_write, csr_mie$EN_reset;
// ports of submodule csr_mip
wire [63 : 0] csr_mip$mav_write, csr_mip$mav_write_wordxl, csr_mip$mv_read;
wire [27 : 0] csr_mip$mav_write_misa;
wire csr_mip$EN_mav_write,
csr_mip$EN_reset,
csr_mip$m_external_interrupt_req_req,
csr_mip$s_external_interrupt_req_req,
csr_mip$software_interrupt_req_req,
csr_mip$timer_interrupt_req_req;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_mtvec_reset_value,
soc_map$m_nmivec_reset_value;
// rule scheduling signals
wire CAN_FIRE_RL_rl_mcycle_incr,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_RL_rl_upd_minstret_csrrx,
CAN_FIRE_RL_rl_upd_minstret_incr,
CAN_FIRE_csr_minstret_incr,
CAN_FIRE_csr_ret_actions,
CAN_FIRE_csr_trap_actions,
CAN_FIRE_debug,
CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_mav_csr_write,
CAN_FIRE_mav_read_csr,
CAN_FIRE_nmi_req,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_RL_rl_mcycle_incr,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_RL_rl_upd_minstret_csrrx,
WILL_FIRE_RL_rl_upd_minstret_incr,
WILL_FIRE_csr_minstret_incr,
WILL_FIRE_csr_ret_actions,
WILL_FIRE_csr_trap_actions,
WILL_FIRE_debug,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_mav_csr_write,
WILL_FIRE_mav_read_csr,
WILL_FIRE_nmi_req,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// inputs to muxes for submodule ports
wire [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_3,
MUX_rg_minstret$write_1__VAL_1,
MUX_rg_minstret$write_1__VAL_2;
wire [62 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2;
wire [4 : 0] MUX_rg_mcause$write_1__VAL_2, MUX_rg_mcause$write_1__VAL_3;
wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_2,
MUX_rg_mcause$write_1__SEL_2,
MUX_rg_mcounteren$write_1__SEL_1,
MUX_rg_mepc$write_1__SEL_1,
MUX_rg_mtval$write_1__SEL_1,
MUX_rg_mtvec$write_1__SEL_1,
MUX_rg_state$write_1__SEL_2,
MUX_rg_tdata1$write_1__SEL_1,
MUX_rw_minstret$wset_1__SEL_1;
// remaining internal signals
reg [63 : 0] IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584,
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440,
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170,
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305;
wire [65 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d883;
wire [63 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d865,
_theResult___fst__h8317,
_theResult___fst__h8518,
csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d858,
exc_pc___1__h7305,
exc_pc__h7041,
exc_pc__h7252,
mask__h8338,
mask__h8355,
new_csr_value__h4626,
new_csr_value__h5354,
v__h4434,
v__h4496,
v__h4667,
val__h8356,
vector_offset__h7253,
wordxl1__h3934,
x__h3755,
x__h5823,
x__h8146,
x__h8147,
x__h8337,
x__h8350,
x__h8367,
y__h8351,
y__h8368;
wire [22 : 0] fixed_up_val_23__h3975,
fixed_up_val_23__h6451,
fixed_up_val_23__h8209;
wire [5 : 0] ie_from_x__h8301, pie_from_x__h8302;
wire [3 : 0] IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1140,
IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1142,
IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1144,
IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1146,
exc_code__h7988;
wire [1 : 0] mpp__h7346, to_y__h8517;
wire NOT_access_permitted_1_csr_addr_ULT_0xC03_84_8_ETC___d950,
NOT_access_permitted_2_csr_addr_ULT_0xC03_55_5_ETC___d1020,
NOT_cfg_verbosity_read__51_ULE_1_52___d553,
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1104,
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1109,
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1114,
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1119,
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1124,
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1129,
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1134,
NOT_csr_trap_actions_nmi_13_AND_csr_trap_actio_ETC___d790,
b__h8354,
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1058,
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1063,
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1068,
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1073,
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1078,
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1083,
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1088,
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1093,
csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d841,
mav_csr_write_csr_addr_ULE_0x33F___d448,
mav_csr_write_csr_addr_ULE_0xB1F___d444,
mav_csr_write_csr_addr_ULT_0x323_47_OR_NOT_mav_ETC___d549,
mav_csr_write_csr_addr_ULT_0x323___d447,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d467,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d477,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d483,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d490,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d494,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d498,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d502,
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d504,
mav_csr_write_csr_addr_ULT_0xB03___d443;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_csr
assign read_csr =
{ read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F ||
read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F ||
read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F ||
read_csr_csr_addr == 12'hC00 ||
read_csr_csr_addr == 12'hC02 ||
read_csr_csr_addr == 12'hF11 ||
read_csr_csr_addr == 12'hF12 ||
read_csr_csr_addr == 12'hF13 ||
read_csr_csr_addr == 12'hF14 ||
read_csr_csr_addr == 12'h300 ||
read_csr_csr_addr == 12'h301 ||
read_csr_csr_addr == 12'h304 ||
read_csr_csr_addr == 12'h305 ||
read_csr_csr_addr == 12'h306 ||
read_csr_csr_addr == 12'h340 ||
read_csr_csr_addr == 12'h341 ||
read_csr_csr_addr == 12'h342 ||
read_csr_csr_addr == 12'h343 ||
read_csr_csr_addr == 12'h344 ||
read_csr_csr_addr == 12'hB00 ||
read_csr_csr_addr == 12'hB02 ||
read_csr_csr_addr == 12'h7A0 ||
read_csr_csr_addr == 12'h7A1 ||
read_csr_csr_addr == 12'h7A2 ||
read_csr_csr_addr == 12'h7A3,
(read_csr_csr_addr >= 12'hC03 &&
read_csr_csr_addr <= 12'hC1F ||
read_csr_csr_addr >= 12'hB03 &&
read_csr_csr_addr <= 12'hB1F ||
read_csr_csr_addr >= 12'h323 &&
read_csr_csr_addr <= 12'h33F) ?
64'd0 :
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 } ;
// value method read_csr_port2
assign read_csr_port2 =
{ read_csr_port2_csr_addr >= 12'hC03 &&
read_csr_port2_csr_addr <= 12'hC1F ||
read_csr_port2_csr_addr >= 12'hB03 &&
read_csr_port2_csr_addr <= 12'hB1F ||
read_csr_port2_csr_addr >= 12'h323 &&
read_csr_port2_csr_addr <= 12'h33F ||
read_csr_port2_csr_addr == 12'hC00 ||
read_csr_port2_csr_addr == 12'hC02 ||
read_csr_port2_csr_addr == 12'hF11 ||
read_csr_port2_csr_addr == 12'hF12 ||
read_csr_port2_csr_addr == 12'hF13 ||
read_csr_port2_csr_addr == 12'hF14 ||
read_csr_port2_csr_addr == 12'h300 ||
read_csr_port2_csr_addr == 12'h301 ||
read_csr_port2_csr_addr == 12'h304 ||
read_csr_port2_csr_addr == 12'h305 ||
read_csr_port2_csr_addr == 12'h306 ||
read_csr_port2_csr_addr == 12'h340 ||
read_csr_port2_csr_addr == 12'h341 ||
read_csr_port2_csr_addr == 12'h342 ||
read_csr_port2_csr_addr == 12'h343 ||
read_csr_port2_csr_addr == 12'h344 ||
read_csr_port2_csr_addr == 12'hB00 ||
read_csr_port2_csr_addr == 12'hB02 ||
read_csr_port2_csr_addr == 12'h7A0 ||
read_csr_port2_csr_addr == 12'h7A1 ||
read_csr_port2_csr_addr == 12'h7A2 ||
read_csr_port2_csr_addr == 12'h7A3,
(read_csr_port2_csr_addr >= 12'hC03 &&
read_csr_port2_csr_addr <= 12'hC1F ||
read_csr_port2_csr_addr >= 12'hB03 &&
read_csr_port2_csr_addr <= 12'hB1F ||
read_csr_port2_csr_addr >= 12'h323 &&
read_csr_port2_csr_addr <= 12'h33F) ?
64'd0 :
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 } ;
// actionvalue method mav_read_csr
assign mav_read_csr =
{ mav_read_csr_csr_addr >= 12'hC03 &&
mav_read_csr_csr_addr <= 12'hC1F ||
mav_read_csr_csr_addr >= 12'hB03 &&
mav_read_csr_csr_addr <= 12'hB1F ||
mav_read_csr_csr_addr >= 12'h323 &&
mav_read_csr_csr_addr <= 12'h33F ||
mav_read_csr_csr_addr == 12'hC00 ||
mav_read_csr_csr_addr == 12'hC02 ||
mav_read_csr_csr_addr == 12'hF11 ||
mav_read_csr_csr_addr == 12'hF12 ||
mav_read_csr_csr_addr == 12'hF13 ||
mav_read_csr_csr_addr == 12'hF14 ||
mav_read_csr_csr_addr == 12'h300 ||
mav_read_csr_csr_addr == 12'h301 ||
mav_read_csr_csr_addr == 12'h304 ||
mav_read_csr_csr_addr == 12'h305 ||
mav_read_csr_csr_addr == 12'h306 ||
mav_read_csr_csr_addr == 12'h340 ||
mav_read_csr_csr_addr == 12'h341 ||
mav_read_csr_csr_addr == 12'h342 ||
mav_read_csr_csr_addr == 12'h343 ||
mav_read_csr_csr_addr == 12'h344 ||
mav_read_csr_csr_addr == 12'hB00 ||
mav_read_csr_csr_addr == 12'hB02 ||
mav_read_csr_csr_addr == 12'h7A0 ||
mav_read_csr_csr_addr == 12'h7A1 ||
mav_read_csr_csr_addr == 12'h7A2 ||
mav_read_csr_csr_addr == 12'h7A3,
(mav_read_csr_csr_addr >= 12'hC03 &&
mav_read_csr_csr_addr <= 12'hC1F ||
mav_read_csr_csr_addr >= 12'hB03 &&
mav_read_csr_csr_addr <= 12'hB1F ||
mav_read_csr_csr_addr >= 12'h323 &&
mav_read_csr_csr_addr <= 12'h33F) ?
64'd0 :
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 } ;
assign CAN_FIRE_mav_read_csr = 1'd1 ;
assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ;
// actionvalue method mav_csr_write
assign mav_csr_write = { x__h3755, 65'h0AAAAAAAAAAAAAAAA } ;
assign CAN_FIRE_mav_csr_write = 1'd1 ;
assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ;
// value method read_misa
assign read_misa = 28'd135270661 ;
// value method read_mstatus
assign read_mstatus = csr_mstatus_rg_mstatus ;
// value method read_ustatus
assign read_ustatus =
{ 59'd0,
csr_mstatus_rg_mstatus[4],
3'd0,
csr_mstatus_rg_mstatus[0] } ;
// value method read_satp
assign read_satp = 64'hAAAAAAAAAAAAAAAA ;
// actionvalue method csr_trap_actions
assign csr_trap_actions = { x__h5823, x__h8146, x__h8147, 2'b11 } ;
assign RDY_csr_trap_actions = 1'd1 ;
assign CAN_FIRE_csr_trap_actions = 1'd1 ;
assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ;
// actionvalue method csr_ret_actions
assign csr_ret_actions =
{ rg_mepc,
IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d883 } ;
assign RDY_csr_ret_actions = 1'd1 ;
assign CAN_FIRE_csr_ret_actions = 1'd1 ;
assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ;
// value method read_csr_minstret
assign read_csr_minstret = rg_minstret ;
// action method csr_minstret_incr
assign CAN_FIRE_csr_minstret_incr = 1'd1 ;
assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ;
// value method read_csr_mcycle
assign read_csr_mcycle = rg_mcycle ;
// value method read_csr_mtime
assign read_csr_mtime = rg_mcycle ;
// value method access_permitted_1
assign access_permitted_1 =
NOT_access_permitted_1_csr_addr_ULT_0xC03_84_8_ETC___d950 &&
(access_permitted_1_read_not_write ||
access_permitted_1_csr_addr[11:10] != 2'b11) ;
// value method access_permitted_2
assign access_permitted_2 =
NOT_access_permitted_2_csr_addr_ULT_0xC03_55_5_ETC___d1020 &&
(access_permitted_2_read_not_write ||
access_permitted_2_csr_addr[11:10] != 2'b11) ;
// value method csr_counter_read_fault
assign csr_counter_read_fault =
(csr_counter_read_fault_priv == 2'b01 ||
csr_counter_read_fault_priv == 2'b0) &&
(csr_counter_read_fault_csr_addr == 12'hC00 &&
!rg_mcounteren[0] ||
csr_counter_read_fault_csr_addr == 12'hC01 &&
!rg_mcounteren[1] ||
csr_counter_read_fault_csr_addr == 12'hC02 &&
!rg_mcounteren[2] ||
csr_counter_read_fault_csr_addr >= 12'hC03 &&
csr_counter_read_fault_csr_addr <= 12'hC1F) ;
// value method csr_mip_read
assign csr_mip_read = csr_mip$mv_read ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// value method interrupt_pending
assign interrupt_pending =
{ csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1093,
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1134 ?
4'd4 :
IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1146 } ;
// value method wfi_resume
assign wfi_resume = (csr_mip$mv_read & csr_mie$mv_read) != 64'd0 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// value method nmi_pending
assign nmi_pending = rg_nmi ;
// action method debug
assign RDY_debug = 1'd1 ;
assign CAN_FIRE_debug = 1'd1 ;
assign WILL_FIRE_debug = EN_debug ;
// submodule csr_mie
mkCSR_MIE csr_mie(.CLK(CLK),
.RST_N(RST_N),
.mav_write_misa(csr_mie$mav_write_misa),
.mav_write_wordxl(csr_mie$mav_write_wordxl),
.EN_reset(csr_mie$EN_reset),
.EN_mav_write(csr_mie$EN_mav_write),
.mv_read(csr_mie$mv_read),
.mav_write(csr_mie$mav_write));
// submodule csr_mip
mkCSR_MIP csr_mip(.CLK(CLK),
.RST_N(RST_N),
.m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req),
.mav_write_misa(csr_mip$mav_write_misa),
.mav_write_wordxl(csr_mip$mav_write_wordxl),
.s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req),
.software_interrupt_req_req(csr_mip$software_interrupt_req_req),
.timer_interrupt_req_req(csr_mip$timer_interrupt_req_req),
.EN_reset(csr_mip$EN_reset),
.EN_mav_write(csr_mip$EN_mav_write),
.mv_read(csr_mip$mv_read),
.mav_write(csr_mip$mav_write));
// submodule f_reset_rsps
FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(soc_map$m_mtvec_reset_value),
.m_nmivec_reset_value(soc_map$m_nmivec_reset_value));
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = !rg_state ;
assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_mcycle_incr
assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ;
assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ;
// rule RL_rl_upd_minstret_csrrx
assign CAN_FIRE_RL_rl_upd_minstret_csrrx =
MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ;
assign WILL_FIRE_RL_rl_upd_minstret_csrrx =
CAN_FIRE_RL_rl_upd_minstret_csrrx ;
// rule RL_rl_upd_minstret_incr
assign CAN_FIRE_RL_rl_upd_minstret_incr =
!CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ;
assign WILL_FIRE_RL_rl_upd_minstret_incr =
CAN_FIRE_RL_rl_upd_minstret_incr ;
// inputs to muxes for submodule ports
assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453 ;
assign MUX_rg_mcause$write_1__SEL_2 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d483 ;
assign MUX_rg_mcounteren$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474 ;
assign MUX_rg_mepc$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479 ;
assign MUX_rg_mtval$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488 ;
assign MUX_rg_mtvec$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469 ;
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ;
assign MUX_rg_tdata1$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d498 ;
assign MUX_rw_minstret$wset_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d494 ;
assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 =
{ 41'd1024, fixed_up_val_23__h8209 } ;
assign MUX_rg_mcause$write_1__VAL_2 =
{ mav_csr_write_word[63], mav_csr_write_word[3:0] } ;
assign MUX_rg_mcause$write_1__VAL_3 =
{ !csr_trap_actions_nmi && csr_trap_actions_interrupt,
exc_code__h7988 } ;
assign MUX_rg_minstret$write_1__VAL_1 =
MUX_rw_minstret$wset_1__SEL_1 ? mav_csr_write_word : 64'd0 ;
assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ;
assign MUX_rg_mtvec$write_1__VAL_1 =
{ mav_csr_write_word[63:2], mav_csr_write_word[0] } ;
assign MUX_rg_mtvec$write_1__VAL_2 =
{ soc_map$m_mtvec_reset_value[63:2],
soc_map$m_mtvec_reset_value[0] } ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = 4'h0 ;
assign cfg_verbosity$EN = 1'b0 ;
// register csr_mstatus_rg_mstatus
always@(WILL_FIRE_RL_rl_reset_start or
MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 or
wordxl1__h3934 or
EN_csr_ret_actions or
MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 or
EN_csr_trap_actions or x__h8146)
case (1'b1)
WILL_FIRE_RL_rl_reset_start:
csr_mstatus_rg_mstatus$D_IN = 64'h0000000200000000;
MUX_csr_mstatus_rg_mstatus$write_1__SEL_2:
csr_mstatus_rg_mstatus$D_IN = wordxl1__h3934;
EN_csr_ret_actions:
csr_mstatus_rg_mstatus$D_IN =
MUX_csr_mstatus_rg_mstatus$write_1__VAL_3;
EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = x__h8146;
default: csr_mstatus_rg_mstatus$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csr_mstatus_rg_mstatus$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453 ||
EN_csr_trap_actions ||
EN_csr_ret_actions ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_dcsr
assign rg_dcsr$D_IN = 32'h0 ;
assign rg_dcsr$EN = 1'b0 ;
// register rg_dpc
assign rg_dpc$D_IN = 64'h0 ;
assign rg_dpc$EN = 1'b0 ;
// register rg_dscratch0
assign rg_dscratch0$D_IN = 64'h0 ;
assign rg_dscratch0$EN = 1'b0 ;
// register rg_dscratch1
assign rg_dscratch1$D_IN = 64'h0 ;
assign rg_dscratch1$EN = 1'b0 ;
// register rg_mcause
always@(WILL_FIRE_RL_rl_reset_start or
MUX_rg_mcause$write_1__SEL_2 or
MUX_rg_mcause$write_1__VAL_2 or
EN_csr_trap_actions or MUX_rg_mcause$write_1__VAL_3)
case (1'b1)
WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0;
MUX_rg_mcause$write_1__SEL_2:
rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2;
EN_csr_trap_actions: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3;
default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign rg_mcause$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d483 ||
EN_csr_trap_actions ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mcounteren
assign rg_mcounteren$D_IN =
MUX_rg_mcounteren$write_1__SEL_1 ?
mav_csr_write_word[2:0] :
3'd0 ;
assign rg_mcounteren$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mcycle
assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ;
assign rg_mcycle$EN = 1'd1 ;
// register rg_mepc
assign rg_mepc$D_IN =
MUX_rg_mepc$write_1__SEL_1 ?
new_csr_value__h4626 :
csr_trap_actions_pc ;
assign rg_mepc$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479 ||
EN_csr_trap_actions ;
// register rg_minstret
assign rg_minstret$D_IN =
WILL_FIRE_RL_rl_upd_minstret_csrrx ?
MUX_rg_minstret$write_1__VAL_1 :
MUX_rg_minstret$write_1__VAL_2 ;
assign rg_minstret$EN =
WILL_FIRE_RL_rl_upd_minstret_csrrx ||
WILL_FIRE_RL_rl_upd_minstret_incr ;
// register rg_mscratch
assign rg_mscratch$D_IN = mav_csr_write_word ;
assign rg_mscratch$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d477 ;
// register rg_mtval
assign rg_mtval$D_IN =
MUX_rg_mtval$write_1__SEL_1 ?
mav_csr_write_word :
csr_trap_actions_xtval ;
assign rg_mtval$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488 ||
EN_csr_trap_actions ;
// register rg_mtvec
assign rg_mtvec$D_IN =
MUX_rg_mtvec$write_1__SEL_1 ?
MUX_rg_mtvec$write_1__VAL_1 :
MUX_rg_mtvec$write_1__VAL_2 ;
assign rg_mtvec$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_nmi
assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ;
assign rg_nmi$EN = 1'b1 ;
// register rg_nmi_vector
assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value ;
assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ;
// register rg_state
assign rg_state$D_IN = !EN_server_reset_request_put ;
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ;
// register rg_tdata1
assign rg_tdata1$D_IN =
MUX_rg_tdata1$write_1__SEL_1 ? new_csr_value__h5354 : 64'd0 ;
assign rg_tdata1$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d498 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_tdata2
assign rg_tdata2$D_IN = mav_csr_write_word ;
assign rg_tdata2$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d502 ;
// register rg_tdata3
assign rg_tdata3$D_IN = mav_csr_write_word ;
assign rg_tdata3$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d504 ;
// register rg_tselect
assign rg_tselect$D_IN = 64'd0 ;
assign rg_tselect$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496 ||
WILL_FIRE_RL_rl_reset_start ;
// submodule csr_mie
assign csr_mie$mav_write_misa = 28'd135270661 ;
assign csr_mie$mav_write_wordxl = mav_csr_write_word ;
assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ;
assign csr_mie$EN_mav_write =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d467 ;
// submodule csr_mip
assign csr_mip$m_external_interrupt_req_req =
m_external_interrupt_req_set_not_clear ;
assign csr_mip$mav_write_misa = 28'd135270661 ;
assign csr_mip$mav_write_wordxl = mav_csr_write_word ;
assign csr_mip$s_external_interrupt_req_req =
s_external_interrupt_req_set_not_clear ;
assign csr_mip$software_interrupt_req_req =
software_interrupt_req_set_not_clear ;
assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ;
assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ;
assign csr_mip$EN_mav_write =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d490 ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1140 =
(!csr_mip$mv_read[11] || !csr_mie$mv_read[11] ||
interrupt_pending_cur_priv == 2'b11 &&
!csr_mstatus_rg_mstatus[3]) ?
4'd3 :
4'd11 ;
assign IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1142 =
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1109 ?
4'd9 :
(NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1104 ?
4'd7 :
IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1140) ;
assign IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1144 =
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1119 ?
4'd5 :
(NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1114 ?
4'd1 :
IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1142) ;
assign IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1146 =
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1129 ?
4'd0 :
(NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1124 ?
4'd8 :
IF_NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_N_ETC___d1144) ;
assign IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d865 =
(csr_ret_actions_from_priv == 2'b11) ?
_theResult___fst__h8317 :
_theResult___fst__h8518 ;
assign IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d883 =
(csr_ret_actions_from_priv == 2'b11) ?
{ csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d858[12:11],
_theResult___fst__h8317 } :
{ to_y__h8517, _theResult___fst__h8518 } ;
assign NOT_access_permitted_1_csr_addr_ULT_0xC03_84_8_ETC___d950 =
(access_permitted_1_csr_addr >= 12'hC03 &&
access_permitted_1_csr_addr <= 12'hC1F ||
access_permitted_1_csr_addr >= 12'hB03 &&
access_permitted_1_csr_addr <= 12'hB1F ||
access_permitted_1_csr_addr >= 12'h323 &&
access_permitted_1_csr_addr <= 12'h33F ||
access_permitted_1_csr_addr == 12'hC00 ||
access_permitted_1_csr_addr == 12'hC02 ||
access_permitted_1_csr_addr == 12'hF11 ||
access_permitted_1_csr_addr == 12'hF12 ||
access_permitted_1_csr_addr == 12'hF13 ||
access_permitted_1_csr_addr == 12'hF14 ||
access_permitted_1_csr_addr == 12'h300 ||
access_permitted_1_csr_addr == 12'h301 ||
access_permitted_1_csr_addr == 12'h304 ||
access_permitted_1_csr_addr == 12'h305 ||
access_permitted_1_csr_addr == 12'h306 ||
access_permitted_1_csr_addr == 12'h340 ||
access_permitted_1_csr_addr == 12'h341 ||
access_permitted_1_csr_addr == 12'h342 ||
access_permitted_1_csr_addr == 12'h343 ||
access_permitted_1_csr_addr == 12'h344 ||
access_permitted_1_csr_addr == 12'hB00 ||
access_permitted_1_csr_addr == 12'hB02 ||
access_permitted_1_csr_addr == 12'h7A0 ||
access_permitted_1_csr_addr == 12'h7A1 ||
access_permitted_1_csr_addr == 12'h7A2 ||
access_permitted_1_csr_addr == 12'h7A3) &&
access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] &&
(access_permitted_1_csr_addr != 12'h180 ||
!csr_mstatus_rg_mstatus[20]) ;
assign NOT_access_permitted_2_csr_addr_ULT_0xC03_55_5_ETC___d1020 =
(access_permitted_2_csr_addr >= 12'hC03 &&
access_permitted_2_csr_addr <= 12'hC1F ||
access_permitted_2_csr_addr >= 12'hB03 &&
access_permitted_2_csr_addr <= 12'hB1F ||
access_permitted_2_csr_addr >= 12'h323 &&
access_permitted_2_csr_addr <= 12'h33F ||
access_permitted_2_csr_addr == 12'hC00 ||
access_permitted_2_csr_addr == 12'hC02 ||
access_permitted_2_csr_addr == 12'hF11 ||
access_permitted_2_csr_addr == 12'hF12 ||
access_permitted_2_csr_addr == 12'hF13 ||
access_permitted_2_csr_addr == 12'hF14 ||
access_permitted_2_csr_addr == 12'h300 ||
access_permitted_2_csr_addr == 12'h301 ||
access_permitted_2_csr_addr == 12'h304 ||
access_permitted_2_csr_addr == 12'h305 ||
access_permitted_2_csr_addr == 12'h306 ||
access_permitted_2_csr_addr == 12'h340 ||
access_permitted_2_csr_addr == 12'h341 ||
access_permitted_2_csr_addr == 12'h342 ||
access_permitted_2_csr_addr == 12'h343 ||
access_permitted_2_csr_addr == 12'h344 ||
access_permitted_2_csr_addr == 12'hB00 ||
access_permitted_2_csr_addr == 12'hB02 ||
access_permitted_2_csr_addr == 12'h7A0 ||
access_permitted_2_csr_addr == 12'h7A1 ||
access_permitted_2_csr_addr == 12'h7A2 ||
access_permitted_2_csr_addr == 12'h7A3) &&
access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] &&
(access_permitted_2_csr_addr != 12'h180 ||
!csr_mstatus_rg_mstatus[20]) ;
assign NOT_cfg_verbosity_read__51_ULE_1_52___d553 = cfg_verbosity > 4'd1 ;
assign NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1104 =
(!csr_mip$mv_read[11] || !csr_mie$mv_read[11] ||
interrupt_pending_cur_priv == 2'b11 &&
!csr_mstatus_rg_mstatus[3]) &&
(!csr_mip$mv_read[3] || !csr_mie$mv_read[3] ||
interrupt_pending_cur_priv == 2'b11 &&
!csr_mstatus_rg_mstatus[3]) ;
assign NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1109 =
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1104 &&
(!csr_mip$mv_read[7] || !csr_mie$mv_read[7] ||
interrupt_pending_cur_priv == 2'b11 &&
!csr_mstatus_rg_mstatus[3]) ;
assign NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1114 =
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1109 &&
(!csr_mip$mv_read[9] || !csr_mie$mv_read[9] ||
interrupt_pending_cur_priv == 2'b11 &&
!csr_mstatus_rg_mstatus[3]) ;
assign NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1119 =
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1114 &&
(!csr_mip$mv_read[1] || !csr_mie$mv_read[1] ||
interrupt_pending_cur_priv == 2'b11 &&
!csr_mstatus_rg_mstatus[3]) ;
assign NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1124 =
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1119 &&
(!csr_mip$mv_read[5] || !csr_mie$mv_read[5] ||
interrupt_pending_cur_priv == 2'b11 &&
!csr_mstatus_rg_mstatus[3]) ;
assign NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1129 =
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1124 &&
(!csr_mip$mv_read[8] || !csr_mie$mv_read[8] ||
interrupt_pending_cur_priv == 2'b11 &&
!csr_mstatus_rg_mstatus[3]) ;
assign NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1134 =
NOT_csr_mip_mv_read__48_BIT_11_047_094_OR_NOT__ETC___d1129 &&
(!csr_mip$mv_read[0] || !csr_mie$mv_read[0] ||
interrupt_pending_cur_priv == 2'b11 &&
!csr_mstatus_rg_mstatus[3]) ;
assign NOT_csr_trap_actions_nmi_13_AND_csr_trap_actio_ETC___d790 =
!csr_trap_actions_nmi && csr_trap_actions_interrupt &&
exc_code__h7988 != 4'd0 &&
exc_code__h7988 != 4'd1 &&
exc_code__h7988 != 4'd2 &&
exc_code__h7988 != 4'd3 &&
exc_code__h7988 != 4'd4 &&
exc_code__h7988 != 4'd5 &&
exc_code__h7988 != 4'd6 &&
exc_code__h7988 != 4'd7 &&
exc_code__h7988 != 4'd8 &&
exc_code__h7988 != 4'd9 &&
exc_code__h7988 != 4'd10 &&
exc_code__h7988 != 4'd11 ;
assign _theResult___fst__h8317 =
{ csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d858[63:13],
2'd0,
csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d858[10:0] } ;
assign _theResult___fst__h8518 =
{ csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d858[63:9],
1'd0,
csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d858[7:0] } ;
assign b__h8354 = csr_mstatus_rg_mstatus[pie_from_x__h8302] ;
assign csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1058 =
csr_mip$mv_read[11] && csr_mie$mv_read[11] &&
(interrupt_pending_cur_priv != 2'b11 ||
csr_mstatus_rg_mstatus[3]) ||
csr_mip$mv_read[3] && csr_mie$mv_read[3] &&
(interrupt_pending_cur_priv != 2'b11 ||
csr_mstatus_rg_mstatus[3]) ;
assign csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1063 =
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1058 ||
csr_mip$mv_read[7] && csr_mie$mv_read[7] &&
(interrupt_pending_cur_priv != 2'b11 ||
csr_mstatus_rg_mstatus[3]) ;
assign csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1068 =
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1063 ||
csr_mip$mv_read[9] && csr_mie$mv_read[9] &&
(interrupt_pending_cur_priv != 2'b11 ||
csr_mstatus_rg_mstatus[3]) ;
assign csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1073 =
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1068 ||
csr_mip$mv_read[1] && csr_mie$mv_read[1] &&
(interrupt_pending_cur_priv != 2'b11 ||
csr_mstatus_rg_mstatus[3]) ;
assign csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1078 =
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1073 ||
csr_mip$mv_read[5] && csr_mie$mv_read[5] &&
(interrupt_pending_cur_priv != 2'b11 ||
csr_mstatus_rg_mstatus[3]) ;
assign csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1083 =
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1078 ||
csr_mip$mv_read[8] && csr_mie$mv_read[8] &&
(interrupt_pending_cur_priv != 2'b11 ||
csr_mstatus_rg_mstatus[3]) ;
assign csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1088 =
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1083 ||
csr_mip$mv_read[0] && csr_mie$mv_read[0] &&
(interrupt_pending_cur_priv != 2'b11 ||
csr_mstatus_rg_mstatus[3]) ;
assign csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1093 =
csr_mip_mv_read__48_BIT_11_047_AND_csr_mie_mv__ETC___d1088 ||
csr_mip$mv_read[4] && csr_mie$mv_read[4] &&
(interrupt_pending_cur_priv != 2'b11 ||
csr_mstatus_rg_mstatus[3]) ;
assign csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d858 =
x__h8350 | mask__h8338 ;
assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d841 =
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 != 4'd0 &&
exc_code__h7988 != 4'd1 &&
exc_code__h7988 != 4'd2 &&
exc_code__h7988 != 4'd3 &&
exc_code__h7988 != 4'd4 &&
exc_code__h7988 != 4'd5 &&
exc_code__h7988 != 4'd6 &&
exc_code__h7988 != 4'd7 &&
exc_code__h7988 != 4'd8 &&
exc_code__h7988 != 4'd9 &&
exc_code__h7988 != 4'd11 &&
exc_code__h7988 != 4'd12 &&
exc_code__h7988 != 4'd13 &&
exc_code__h7988 != 4'd15 ;
assign exc_code__h7988 =
csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ;
assign exc_pc___1__h7305 = exc_pc__h7252 + vector_offset__h7253 ;
assign exc_pc__h7041 = { rg_mtvec[62:1], 2'd0 } ;
assign exc_pc__h7252 =
csr_trap_actions_nmi ? rg_nmi_vector : exc_pc__h7041 ;
assign fixed_up_val_23__h3975 =
{ mav_csr_write_word[22:17],
4'd0,
(mav_csr_write_word[12:11] == 2'b11) ?
mav_csr_write_word[12:11] :
2'b0,
mav_csr_write_word[10:9],
1'd0,
mav_csr_write_word[7:6],
2'd0,
mav_csr_write_word[3:2],
2'd0 } ;
assign fixed_up_val_23__h6451 =
{ csr_mstatus_rg_mstatus[22:17],
4'd0,
mpp__h7346,
csr_mstatus_rg_mstatus[10:9],
1'd0,
csr_mstatus_rg_mstatus[3],
csr_mstatus_rg_mstatus[6],
3'd0,
csr_mstatus_rg_mstatus[2],
2'd0 } ;
assign fixed_up_val_23__h8209 =
{ IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d865[22:17],
4'd0,
(IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d865[12:11] ==
2'b11) ?
IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d865[12:11] :
2'b0,
IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d865[10:9],
1'd0,
IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d865[7:6],
2'd0,
IF_csr_ret_actions_from_priv_EQ_0b11_45_THEN_c_ETC___d865[3:2],
2'd0 } ;
assign ie_from_x__h8301 = { 4'd0, csr_ret_actions_from_priv } ;
assign mask__h8338 = 64'd1 << pie_from_x__h8302 ;
assign mask__h8355 = 64'd1 << ie_from_x__h8301 ;
assign mav_csr_write_csr_addr_ULE_0x33F___d448 =
mav_csr_write_csr_addr <= 12'h33F ;
assign mav_csr_write_csr_addr_ULE_0xB1F___d444 =
mav_csr_write_csr_addr <= 12'hB1F ;
assign mav_csr_write_csr_addr_ULT_0x323_47_OR_NOT_mav_ETC___d549 =
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr != 12'hF11 &&
mav_csr_write_csr_addr != 12'hF12 &&
mav_csr_write_csr_addr != 12'hF13 &&
mav_csr_write_csr_addr != 12'hF14 &&
mav_csr_write_csr_addr != 12'h300 &&
mav_csr_write_csr_addr != 12'h301 &&
mav_csr_write_csr_addr != 12'h304 &&
mav_csr_write_csr_addr != 12'h305 &&
mav_csr_write_csr_addr != 12'h306 &&
mav_csr_write_csr_addr != 12'h340 &&
mav_csr_write_csr_addr != 12'h341 &&
mav_csr_write_csr_addr != 12'h342 &&
mav_csr_write_csr_addr != 12'h343 &&
mav_csr_write_csr_addr != 12'h344 &&
mav_csr_write_csr_addr != 12'hB00 &&
mav_csr_write_csr_addr != 12'hB02 &&
mav_csr_write_csr_addr != 12'h7A0 &&
mav_csr_write_csr_addr != 12'h7A1 &&
mav_csr_write_csr_addr != 12'h7A2 &&
mav_csr_write_csr_addr != 12'h7A3 ;
assign mav_csr_write_csr_addr_ULT_0x323___d447 =
mav_csr_write_csr_addr < 12'h323 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h300 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d467 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h304 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h305 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h306 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d477 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h340 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h341 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d483 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h342 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h343 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d490 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h344 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d494 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'hB02 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h7A0 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d498 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h7A1 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d502 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h7A2 ;
assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d504 =
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
(mav_csr_write_csr_addr_ULT_0x323___d447 ||
!mav_csr_write_csr_addr_ULE_0x33F___d448) &&
mav_csr_write_csr_addr == 12'h7A3 ;
assign mav_csr_write_csr_addr_ULT_0xB03___d443 =
mav_csr_write_csr_addr < 12'hB03 ;
assign mpp__h7346 =
(csr_trap_actions_from_priv == 2'b11) ?
csr_trap_actions_from_priv :
2'b0 ;
assign new_csr_value__h4626 = { mav_csr_write_word[63:1], 1'd0 } ;
assign new_csr_value__h5354 = { 4'd0, mav_csr_write_word[59:0] } ;
assign pie_from_x__h8302 = { 4'd1, csr_ret_actions_from_priv } ;
assign to_y__h8517 =
{ 1'b0,
csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d858[8] } ;
assign v__h4434 =
{ mav_csr_write_word[63:2], 1'b0, mav_csr_write_word[0] } ;
assign v__h4496 = { 61'd0, mav_csr_write_word[2:0] } ;
assign v__h4667 =
{ mav_csr_write_word[63], 59'd0, mav_csr_write_word[3:0] } ;
assign val__h8356 = { 63'd0, b__h8354 } << ie_from_x__h8301 ;
assign vector_offset__h7253 = { 58'd0, csr_trap_actions_exc_code, 2'd0 } ;
assign wordxl1__h3934 = { 41'd1024, fixed_up_val_23__h3975 } ;
assign x__h3755 =
(!mav_csr_write_csr_addr_ULT_0xB03___d443 &&
mav_csr_write_csr_addr_ULE_0xB1F___d444 ||
!mav_csr_write_csr_addr_ULT_0x323___d447 &&
mav_csr_write_csr_addr_ULE_0x33F___d448 ||
mav_csr_write_csr_addr == 12'hF11 ||
mav_csr_write_csr_addr == 12'hF12 ||
mav_csr_write_csr_addr == 12'hF13 ||
mav_csr_write_csr_addr == 12'hF14) ?
64'd0 :
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 ;
assign x__h5823 =
(csr_trap_actions_interrupt && !csr_trap_actions_nmi &&
rg_mtvec[0]) ?
exc_pc___1__h7305 :
exc_pc__h7252 ;
assign x__h8146 = { 41'd1024, fixed_up_val_23__h6451 } ;
assign x__h8147 =
{ !csr_trap_actions_nmi && csr_trap_actions_interrupt,
59'd0,
exc_code__h7988 } ;
assign x__h8337 = x__h8367 | val__h8356 ;
assign x__h8350 = x__h8337 & y__h8351 ;
assign x__h8367 = csr_mstatus_rg_mstatus & y__h8368 ;
assign y__h8351 = ~mask__h8338 ;
assign y__h8368 = ~mask__h8355 ;
always@(mav_csr_write_csr_addr or
mav_csr_write_word or
wordxl1__h3934 or
csr_mie$mav_write or
v__h4434 or
v__h4496 or
new_csr_value__h4626 or
v__h4667 or csr_mip$mav_write or new_csr_value__h5354)
begin
case (mav_csr_write_csr_addr)
12'h300:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
wordxl1__h3934;
12'h301:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
64'h8000000000101105;
12'h304:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
csr_mie$mav_write;
12'h305:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
v__h4434;
12'h306:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
v__h4496;
12'h340, 12'h343, 12'hB00, 12'hB02:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
mav_csr_write_word;
12'h341:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
new_csr_value__h4626;
12'h342:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
v__h4667;
12'h344:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
csr_mip$mav_write;
12'h7A0:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 = 64'd0;
12'h7A1:
IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
new_csr_value__h5354;
default: IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d584 =
mav_csr_write_word;
endcase
end
always@(read_csr_csr_addr or
rg_tdata3 or
csr_mstatus_rg_mstatus or
csr_mie$mv_read or
rg_mtvec or
rg_mcounteren or
rg_mscratch or
rg_mepc or
rg_mcause or
rg_mtval or
csr_mip$mv_read or
rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret)
begin
case (read_csr_csr_addr)
12'h300:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
csr_mstatus_rg_mstatus;
12'h301:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
64'h8000000000101105;
12'h304:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
csr_mie$mv_read;
12'h305:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
{ rg_mtvec[62:1], 1'b0, rg_mtvec[0] };
12'h306:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
{ 61'd0, rg_mcounteren };
12'h340:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
rg_mscratch;
12'h341:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = rg_mepc;
12'h342:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
{ rg_mcause[4], 59'd0, rg_mcause[3:0] };
12'h343:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
rg_mtval;
12'h344:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
csr_mip$mv_read;
12'h7A0:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
rg_tselect;
12'h7A1:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
rg_tdata1;
12'h7A2:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
rg_tdata2;
12'hB00, 12'hC00:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
rg_mcycle;
12'hB02, 12'hC02:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
rg_minstret;
12'hF11, 12'hF12, 12'hF13, 12'hF14:
IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = 64'd0;
default: IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 =
rg_tdata3;
endcase
end
always@(read_csr_port2_csr_addr or
rg_tdata3 or
csr_mstatus_rg_mstatus or
csr_mie$mv_read or
rg_mtvec or
rg_mcounteren or
rg_mscratch or
rg_mepc or
rg_mcause or
rg_mtval or
csr_mip$mv_read or
rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret)
begin
case (read_csr_port2_csr_addr)
12'h300:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
csr_mstatus_rg_mstatus;
12'h301:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
64'h8000000000101105;
12'h304:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
csr_mie$mv_read;
12'h305:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
{ rg_mtvec[62:1], 1'b0, rg_mtvec[0] };
12'h306:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
{ 61'd0, rg_mcounteren };
12'h340:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
rg_mscratch;
12'h341:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = rg_mepc;
12'h342:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
{ rg_mcause[4], 59'd0, rg_mcause[3:0] };
12'h343:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
rg_mtval;
12'h344:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
csr_mip$mv_read;
12'h7A0:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
rg_tselect;
12'h7A1:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
rg_tdata1;
12'h7A2:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
rg_tdata2;
12'hB00, 12'hC00:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
rg_mcycle;
12'hB02, 12'hC02:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
rg_minstret;
12'hF11, 12'hF12, 12'hF13, 12'hF14:
IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = 64'd0;
default: IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 =
rg_tdata3;
endcase
end
always@(mav_read_csr_csr_addr or
rg_tdata3 or
csr_mstatus_rg_mstatus or
csr_mie$mv_read or
rg_mtvec or
rg_mcounteren or
rg_mscratch or
rg_mepc or
rg_mcause or
rg_mtval or
csr_mip$mv_read or
rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret)
begin
case (mav_read_csr_csr_addr)
12'h300:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
csr_mstatus_rg_mstatus;
12'h301:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
64'h8000000000101105;
12'h304:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
csr_mie$mv_read;
12'h305:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
{ rg_mtvec[62:1], 1'b0, rg_mtvec[0] };
12'h306:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
{ 61'd0, rg_mcounteren };
12'h340:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
rg_mscratch;
12'h341:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = rg_mepc;
12'h342:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
{ rg_mcause[4], 59'd0, rg_mcause[3:0] };
12'h343:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
rg_mtval;
12'h344:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
csr_mip$mv_read;
12'h7A0:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
rg_tselect;
12'h7A1:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
rg_tdata1;
12'h7A2:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
rg_tdata2;
12'hB00, 12'hC00:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
rg_mcycle;
12'hB02, 12'hC02:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
rg_minstret;
12'hF11, 12'hF12, 12'hF13, 12'hF14:
IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = 64'd0;
default: IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 =
rg_tdata3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 64'h0000000200000000;
rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0;
rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0;
rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (csr_mstatus_rg_mstatus$EN)
csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY
csr_mstatus_rg_mstatus$D_IN;
if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN;
if (rg_minstret$EN)
rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN;
if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN;
if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN;
if (rg_dscratch0$EN)
rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN;
if (rg_dscratch1$EN)
rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN;
if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN;
if (rg_mcounteren$EN)
rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN;
if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN;
if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN;
if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN;
if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN;
if (rg_nmi_vector$EN)
rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN;
if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN;
if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN;
if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN;
if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
csr_mstatus_rg_mstatus = 64'hAAAAAAAAAAAAAAAA;
rg_dcsr = 32'hAAAAAAAA;
rg_dpc = 64'hAAAAAAAAAAAAAAAA;
rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA;
rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA;
rg_mcause = 5'h0A;
rg_mcounteren = 3'h2;
rg_mcycle = 64'hAAAAAAAAAAAAAAAA;
rg_mepc = 64'hAAAAAAAAAAAAAAAA;
rg_minstret = 64'hAAAAAAAAAAAAAAAA;
rg_mscratch = 64'hAAAAAAAAAAAAAAAA;
rg_mtval = 64'hAAAAAAAAAAAAAAAA;
rg_mtvec = 63'h2AAAAAAAAAAAAAAA;
rg_nmi = 1'h0;
rg_nmi_vector = 64'hAAAAAAAAAAAAAAAA;
rg_state = 1'h0;
rg_tdata1 = 64'hAAAAAAAAAAAAAAAA;
rg_tdata2 = 64'hAAAAAAAAAAAAAAAA;
rg_tdata3 = 64'hAAAAAAAAAAAAAAAA;
rg_tselect = 64'hAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus);
if (RST_N != `BSV_RESET_VALUE)
if (EN_debug) $display("mip = 0x%0h", csr_mip$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_debug) $display("mie = 0x%0h", csr_mie$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h",
csr_trap_actions_from_priv,
csr_trap_actions_pc,
csr_trap_actions_interrupt,
csr_trap_actions_exc_code,
csr_trap_actions_xtval);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" priv %0d: ", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" ip: 0x%0h", csr_mip$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" ie: 0x%0h", csr_mie$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" edeleg: 0x%0h", 16'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" ideleg: 0x%0h", 12'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" cause:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd0)
$write("USER_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd1)
$write("SUPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd2)
$write("HYPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd3)
$write("MACHINE_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd4)
$write("USER_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd5)
$write("SUPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd6)
$write("HYPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd7)
$write("MACHINE_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd8)
$write("USER_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd9)
$write("SUPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd10)
$write("HYPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd11)
$write("MACHINE_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
rg_mcause[4] &&
rg_mcause[3:0] != 4'd0 &&
rg_mcause[3:0] != 4'd1 &&
rg_mcause[3:0] != 4'd2 &&
rg_mcause[3:0] != 4'd3 &&
rg_mcause[3:0] != 4'd4 &&
rg_mcause[3:0] != 4'd5 &&
rg_mcause[3:0] != 4'd6 &&
rg_mcause[3:0] != 4'd7 &&
rg_mcause[3:0] != 4'd8 &&
rg_mcause[3:0] != 4'd9 &&
rg_mcause[3:0] != 4'd10 &&
rg_mcause[3:0] != 4'd11)
$write("unknown interrupt Exc_Code %d", rg_mcause[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!rg_mcause[4] &&
rg_mcause[3:0] != 4'd0 &&
rg_mcause[3:0] != 4'd1 &&
rg_mcause[3:0] != 4'd2 &&
rg_mcause[3:0] != 4'd3 &&
rg_mcause[3:0] != 4'd4 &&
rg_mcause[3:0] != 4'd5 &&
rg_mcause[3:0] != 4'd6 &&
rg_mcause[3:0] != 4'd7 &&
rg_mcause[3:0] != 4'd8 &&
rg_mcause[3:0] != 4'd9 &&
rg_mcause[3:0] != 4'd11 &&
rg_mcause[3:0] != 4'd12 &&
rg_mcause[3:0] != 4'd13 &&
rg_mcause[3:0] != 4'd15)
$write("unknown trap Exc_Code %d", rg_mcause[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" status: 0x%0h", csr_mstatus_rg_mstatus);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" tvec: 0x%0h", { rg_mtvec[62:1], 1'b0, rg_mtvec[0] });
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" epc: 0x%0h", rg_mepc);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" tval: 0x%0h", rg_mtval);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" Return: new pc 0x%0h ", x__h5823);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" new mstatus:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write("MStatus{", "sd:%0d", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" sxl:%0d uxl:%0d", 2'd0, 2'd2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" tsr:%0d", csr_mstatus_rg_mstatus[22]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" tw:%0d", csr_mstatus_rg_mstatus[21]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" tvm:%0d", csr_mstatus_rg_mstatus[20]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" mxr:%0d", csr_mstatus_rg_mstatus[19]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" sum:%0d", csr_mstatus_rg_mstatus[18]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" mprv:%0d", csr_mstatus_rg_mstatus[17]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" xs:%0d", 2'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" fs:%0d", 2'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" mpp:%0d", mpp__h7346);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" spp:%0d", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" pies:%0d_%0d%0d", csr_mstatus_rg_mstatus[3], 1'd0, 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" ies:%0d_%0d%0d", 1'd0, 1'd0, 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" new xcause:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd0)
$write("USER_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd1)
$write("SUPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd2)
$write("HYPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd3)
$write("MACHINE_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd4)
$write("USER_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd5)
$write("SUPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd6)
$write("HYPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd7)
$write("MACHINE_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd8)
$write("USER_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd9)
$write("SUPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd10)
$write("HYPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h7988 == 4'd11)
$write("MACHINE_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
NOT_csr_trap_actions_nmi_13_AND_csr_trap_actio_ETC___d790)
$write("unknown interrupt Exc_Code %d", exc_code__h7988);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h7988 == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553 &&
csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d841)
$write("unknown trap Exc_Code %d", exc_code__h7988);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$write(" new priv %0d", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_mav_csr_write &&
(mav_csr_write_csr_addr_ULT_0xB03___d443 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d444) &&
mav_csr_write_csr_addr_ULT_0x323_47_OR_NOT_mav_ETC___d549 &&
NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful",
rg_mcycle,
mav_csr_write_csr_addr,
mav_csr_write_word);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display("%0d: CSR_RegFile: m_external_interrupt_req: %x",
rg_mcycle,
m_external_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display("%0d: CSR_RegFile: s_external_interrupt_req: %x",
rg_mcycle,
s_external_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display("%0d: CSR_RegFile: software_interrupt_req: %x",
rg_mcycle,
software_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_cfg_verbosity_read__51_ULE_1_52___d553)
$display("%0d: CSR_RegFile: timer_interrupt_req: %x",
rg_mcycle,
timer_interrupt_req_set_not_clear);
end
// synopsys translate_on
endmodule |
module up_hdmi_rx #(
parameter ID = 0) (
// hdmi interface
input hdmi_clk,
output hdmi_rst,
output hdmi_edge_sel,
output hdmi_bgr,
output hdmi_packed,
output hdmi_csc_bypass,
output [15:0] hdmi_vs_count,
output [15:0] hdmi_hs_count,
input hdmi_dma_ovf,
input hdmi_dma_unf,
input hdmi_tpm_oos,
input hdmi_vs_oos,
input hdmi_hs_oos,
input hdmi_vs_mismatch,
input hdmi_hs_mismatch,
input [15:0] hdmi_vs,
input [15:0] hdmi_hs,
input [31:0] hdmi_clk_ratio,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
localparam PCORE_VERSION = 32'h00040063;
// internal registers
reg up_core_preset = 'd0;
reg up_resetn = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_edge_sel = 'd0;
reg up_bgr = 'd0;
reg up_packed = 'd0;
reg up_csc_bypass = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf = 'd0;
reg up_tpm_oos = 'd0;
reg up_vs_oos = 'd0;
reg up_hs_oos = 'd0;
reg up_vs_mismatch = 'd0;
reg up_hs_mismatch = 'd0;
reg [15:0] up_vs_count = 'd0;
reg [15:0] up_hs_count = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_dma_ovf_s;
wire up_dma_unf_s;
wire up_vs_oos_s;
wire up_hs_oos_s;
wire up_vs_mismatch_s;
wire up_hs_mismatch_s;
wire [15:0] up_vs_s;
wire [15:0] up_hs_s;
wire [31:0] up_clk_count_s;
// decode block select
assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_core_preset <= 1'd1;
up_resetn <= 'd0;
up_wack <= 'd0;
up_scratch <= 'd0;
up_edge_sel <= 'd0;
up_bgr <= 'd0;
up_packed <= 'd0;
up_csc_bypass <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf <= 'd0;
up_tpm_oos <= 'd0;
up_vs_oos <= 'd0;
up_hs_oos <= 'd0;
up_vs_mismatch <= 'd0;
up_hs_mismatch <= 'd0;
up_vs_count <= 'd0;
up_hs_count <= 'd0;
end else begin
up_wack <= up_wreq_s;
up_core_preset <= ~up_resetn;
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
up_edge_sel <= up_wdata[3];
up_bgr <= up_wdata[2];
up_packed <= up_wdata[1];
up_csc_bypass <= up_wdata[0];
end
if (up_dma_ovf_s == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[1];
end
if (up_dma_unf_s == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[0];
end
if (up_tpm_oos_s == 1'b1) begin
up_tpm_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_tpm_oos <= up_tpm_oos & ~up_wdata[1];
end
if (up_vs_oos_s == 1'b1) begin
up_vs_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_vs_oos <= up_vs_oos & ~up_wdata[3];
end
if (up_hs_oos_s == 1'b1) begin
up_hs_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_hs_oos <= up_hs_oos & ~up_wdata[2];
end
if (up_vs_mismatch_s == 1'b1) begin
up_vs_mismatch <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_vs_mismatch <= up_vs_mismatch & ~up_wdata[1];
end
if (up_hs_mismatch_s == 1'b1) begin
up_hs_mismatch <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_hs_mismatch <= up_hs_mismatch & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
up_vs_count <= up_wdata[31:16];
up_hs_count <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if(up_rreq_s == 1'b1) begin
case (up_raddr[11:0])
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch;
12'h010: up_rdata <= {31'h0, up_resetn};
12'h011: up_rdata <= {28'h0, up_edge_sel, up_bgr, up_packed, up_csc_bypass};
12'h015: up_rdata <= up_clk_count_s;
12'h016: up_rdata <= hdmi_clk_ratio;
12'h018: up_rdata <= {30'h0, up_dma_ovf, up_dma_unf};
12'h019: up_rdata <= {30'h0, up_tpm_oos, 1'b0};
12'h020: up_rdata <= {28'h0, up_vs_oos, up_hs_oos,
up_vs_mismatch, up_hs_mismatch};
12'h100: up_rdata <= {up_vs_count, up_hs_count};
12'h101: up_rdata <= {up_vs_s, up_hs_s};
default: up_rdata <= 0;
endcase
end
end
end
// resets
ad_rst i_hdmi_rst_reg (
.rst_async (up_core_preset),
.clk (hdmi_clk),
.rstn (),
.rst (hdmi_rst));
// hdmi control & status
up_xfer_cntrl #(.DATA_WIDTH(36)) i_hdmi_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_edge_sel,
up_bgr,
up_packed,
up_csc_bypass,
up_vs_count,
up_hs_count}),
.up_xfer_done (),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_cntrl ({ hdmi_edge_sel,
hdmi_bgr,
hdmi_packed,
hdmi_csc_bypass,
hdmi_vs_count,
hdmi_hs_count}));
up_xfer_status #(.DATA_WIDTH(39)) i_hdmi_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({ up_dma_ovf_s,
up_dma_unf_s,
up_tpm_oos_s,
up_vs_oos_s,
up_hs_oos_s,
up_vs_mismatch_s,
up_hs_mismatch_s,
up_vs_s,
up_hs_s}),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_status ({ hdmi_dma_ovf,
hdmi_dma_unf,
hdmi_tpm_oos,
hdmi_vs_oos,
hdmi_hs_oos,
hdmi_vs_mismatch,
hdmi_hs_mismatch,
hdmi_vs,
hdmi_hs}));
up_clock_mon i_hdmi_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_clk_count_s),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk));
endmodule |
module ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output reg[3:0] CU, input MFC, Reset,Clk, input [31:0] IR,input [3:0] SR);
reg [4:0] State, NextState;
always @ (negedge Clk, posedge Reset)
if (Reset) begin
State <= 5'b00001;ALUSTORE = 0 ; IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;CU=0; opcode=5'b10010;end
else
State <= NextState;
/*
STATUS REGISTER FLAGS
WE FETCH INSTRUCTIONS 8BITS AT A TIME 8BIT DATAPATH
31. Negative, N = (ADD)&&(A[31]==B[31])&&(A[31]!=OUT[31]) || (SUB)
30. Zero, Z = OUT == 0
29. Carry, C = CARRY
28. Overflow, V = OVERFLOW
END
*/
always @ (State, MFC)
case (State)
5'b00000 : NextState = 5'b00000;
5'b00001 : if(MFC) NextState = 5'b10001 ; else NextState = 5'b00010;// goto stall cycle if not ready
5'b00010 : NextState = 5'b00011;
5'b00011 : if(MFC)NextState = 5'b00100; else NextState = 5'b00011;
5'b00100 : NextState = 5'b00101;
5'b00101 : case(IR[31:28])//Decode Begin
4'b0000: if(SR[2]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0001: if(SR[2]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b0010: if(SR[1]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0011: if(SR[1]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b0100: if(SR[3]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0101: if(SR[3]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b0110: if(SR[0]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b0111: if(SR[0]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b1000: if(SR[1]==1&SR[2]==0) NextState = 5'b00110; else NextState = 5'b00001;
4'b1001: if(SR[1]==0|SR[2]==1) NextState = 5'b00110; else NextState = 5'b00001;
4'b1010: if(SR[3]==SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1011: if(SR[3]!=SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1100: if(SR[2]==0&SR[3]==SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1101: if(SR[2]==1|SR[3]!=SR[0]) NextState = 5'b00110; else NextState = 5'b00001;
4'b1110: NextState = 5'b00110;
endcase
5'b00110 : case(IR[27:25])
3'b000,3'b001:NextState = 5'b00111;
3'b010,3'b011:NextState = 5'b01000;//Load/Store operation 1
3'b101:NextState = 5'b01110;//Branch operation 1
default:NextState = 5'b0001;
endcase
5'b00111 : NextState = 5'b00001; // Data operation 1
5'b01000 : if(IR[24] == 0 & IR[0] ==0 ) NextState = 5'b01001; else if(IR[20]) NextState = 5'b01010;else NextState = 5'b01011; //Load/Store operation 1
5'b01001 : if(IR[20]) NextState = 5'b01010;else NextState = 5'b01011; //Load/Store operation 2
5'b01010 : if(MFC) NextState = 5'b01100; else NextState = 5'b01010; //Load operation 1
5'b01011 : NextState = 5'b01101; //Store operation 1
5'b01100 : NextState = 5'b00001; //Load operation 2
5'b01101 : if(!MFC) NextState = 5'b00001 ; else NextState = 5'b01101; //Store operation 2
5'b01110 : NextState = 5'b00001;//Branch operation 1
5'b01111 : NextState = 5'b10000; // Empty state
5'b10000 : NextState = 5'b00001; // Empty state
5'b10001 : if(MFC) NextState = 5'b10001 ; else NextState = 5'b00010; // Stall State MFC Already Up
endcase
always @ (State, MFC)
case (State)
5'b00000 : begin end
5'b00001 : begin ALUSTORE = 1 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 1 ; CU=4'hf;opcode=5'b10010;end // send pc to mar: ircu = 1 cu = 1111,MARLOAD = 1
5'b00010 : begin ALUSTORE = 1 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 1 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 1 ; WORD_BYTE= 1 ;READ_WRITE= 1 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10001;end // increment pc : loadpc = 1 ircu = 1 cu = 1111 op = 17
5'b00011 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 1 ; WORD_BYTE= 1 ;READ_WRITE= 1 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10010;end // wait for MFC: MFA = 1 LOADIR = 1 read_write = 1 word_byte = 1
5'b00100 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 1 ;MBRLOAD= 0 ;MBRSTORE= 1 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10010;end // transfer data to IR
5'b00101 : begin ALUSTORE = 1 ;IR_CU= 1 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'h0;end // Check status codes
5'b00110 : begin ALUSTORE = 0 ;IR_CU= 1 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;end // Decode instruction type and set out signals
5'b00111 : begin ALUSTORE = 1 ;IR_CU= 1 ; RFLOAD= IR[24:21]>=4'b1011 || IR[24:21]<=4'b1000 ? 1 : 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;opcode = {1'b0,IR[24:21]};end //Data Operation 1
5'b01000 : begin ALUSTORE = 1 ;IR_CU= 1 ; RFLOAD= IR[21]==1&IR[24]==1 ? 1 : 0; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 1 ;opcode = IR[24] == 0 & IR[0] ==0 ? 5'b10010 : IR[23] ? 5'b00100/*add*/:5'b00010 ; end //Load/Store operation 1
5'b01001 : begin ALUSTORE = 1 ;IR_CU= 1 ; RFLOAD=1; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= !IR[22] ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;opcode = IR[23] ? 5'b00100/*add*/:5'b00010 ; end //Load/Store operation 1
5'b01010 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 1 ; WORD_BYTE= !IR[22] ;READ_WRITE= 1 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;end //Load operation 1
5'b01011 : begin ALUSTORE = 1 ;IR_CU= 1 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= !IR[22] ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 1 ;MBRSTORE= 0 ;MARLOAD = 0 ; opcode=5'b10010; end //Store operation 1
5'b01100 : begin ALUSTORE = 0 ;IR_CU= 1 ; RFLOAD= 1 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= !IR[22] ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 1 ;MARLOAD = 0 ;end //Load operation 2
5'b01101 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 1 ; #1 MFA= 0 ; WORD_BYTE= IR[22] ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;end //Store Operation 2
5'b01110 : begin ALUSTORE = 1 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 1 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b00100;end //Branch operation 1
5'b01111 : begin end
5'b10000 : begin end
5'b10001 : begin ALUSTORE = 0 ;IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ; CU=4'hf;opcode=5'b10001;end // Stall State Purpusely Left Empty MFC Already Up
/*branch and load_store instruction*/
default : begin end
endcase
endmodule |
module dex_smlablt
(
input de_clk,
input de_rstn,
input goblt,
input stpl_pk_1,
input apat_1,
input mcrdy,
input cache_rdy,
input signx,
input signy,
input yeqz,
input xeqz,
input [2:0] clp_status,
input apat32_2,
input rmw,
input read_2,
input mw_fip,
input local_eol,
output reg [21:0] lab_op,
output reg [4:0] lab_ksel,
output reg lab_set_busy,
output reg lab_clr_busy,
output reg lab_ld_wcnt,
output reg lab_mem_req,
output reg lab_mem_rd,
output reg lab_dchgy,
output reg lab_rstn_wad,
output reg lab_ld_rad,
output reg lab_set_sol,
output reg lab_set_eol,
output reg lab_ld_msk,
output reg lab_mul,
output reg lab_set_local_eol,
output reg lab_clr_local_eol,
output reg lab_rst_cr
);
// These parameters were formerly included by de_param.h
//`include "de_param.h"
parameter one = 5'h1,
LAB_WAIT = 5'h0,
LABS1 = 5'h1,
LABS2 = 5'h2,
LABS3 = 5'h3,
LABS4 = 5'h4,
LABS5 = 5'h5,
LABR1 = 5'h6,
LABR2 = 5'h7,
LABR3 = 5'h8,
LABW1 = 5'h9,
LABW2 = 5'ha,
LABW3 = 5'hb,
LABW4 = 5'hc,
LABNL1 = 5'hd,
LABNL2 = 5'he,
LABNL3 = 5'hf,
LABNL4 = 5'h10,
LABS2B = 5'h11,
LABS2C = 5'h12,
LABS2D = 5'h13,
LABS2E = 5'h14,
LABS2F = 5'h15,
LABS2G = 5'h16,
noop = 5'h0, // noop address.
pline = 5'h10, // pipeline address
sorgl = 5'he, // src org address low nibble.
dorgl = 5'hf, // src org address low nibble.
src = 5'h0, // source/start point register
dst = 5'h1, // destination/end point
mov = 5'hd, // bx--> fx, by--> fy
pix_dstx = 5'h5, // wrk3x
wrhi = 2'b01, // define write enables
wrlo = 2'b10, // define write enables
wrhl = 2'b00, // define write enables
wrno = 2'b11, // define write enables
addnib = 5'h2, // ax + bx(nibble)
dst_sav = 5'h9, // dst & wrk1y
add = 5'h1, // ax + bx, ay + by
size = 5'h2, // wrk0x and wrk0y
sav_dst = 5'h4,
xend_pc = 5'h09,
xmin_pc = 5'h0a,
xmax_pc = 5'h0b,
sub = 5'h12, // ax - bx, ay - by
amcn = 5'h4, // ax-k, ay-k
amcn_d = 5'h14, // {ax - const,ax - const}
zero = 5'h0,
four = 5'h4,
div16 = 5'ha, // bx/16 + wadj.
wr_wrds_sav = 5'hc, // wrk4x & wrk6x
mov_k = 5'he, // move constant.
eight = 5'h6,
wr_wrds = 5'h6, // wrk4x
sav_src_dst = 5'h3, // wrk1x & wrk1y
movx = 5'hf, // bx--> fy, by--> fx
apcn = 5'h6, // ax+k, ay+k
D64 = 5'h11,
D128 = 5'h15,
sav_wr_wrds = 5'h8; // wrk6x
/****************************************************************/
/* DEFINE PARAMETERS */
/****************************************************************/
/* define internal wires and make assignments */
reg [4:0] lab_cs;
reg [4:0] lab_ns;
/* create the state register */
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)lab_cs <= 0;
else lab_cs <= lab_ns;
end
always @*
begin
lab_op = 22'b00000_00000_00000_00000_11;
lab_ksel = one;
lab_set_busy = 1'b0;
lab_clr_busy = 1'b0;
lab_ld_wcnt = 1'b0;
lab_mem_req = 1'b0;
lab_mem_rd = 1'b0;
lab_dchgy = 1'b0;
lab_rstn_wad = 1'b0;
lab_ld_rad = 1'b0;
lab_set_sol = 1'b0;
lab_set_eol = 1'b0;
lab_mem_req = 1'b0;
lab_mem_rd = 1'b0;
lab_ld_msk = 1'b0;
lab_mul = 1'b0;
lab_set_local_eol = 1'b0;
lab_clr_local_eol = 1'b0;
lab_rst_cr = 1'b0;
case(lab_cs) /* synopsys full_case parallel_case */
/* if goblt and stipple and area pattern begin. */
/* ELSE wait. */
LAB_WAIT:if(goblt && (stpl_pk_1 && apat_1))
begin
lab_ns=LABS1;
lab_op={noop,dst,mov,pix_dstx,wrhi};
lab_set_busy = 1'b1;
lab_mul = 1'b1;
end
else lab_ns= LAB_WAIT;
/* multiply the src, dst, and size by 2 for 16BPP, or 4 for 32BPP. */
/* add org low nibble to destination point */
/* save the original destination X, to use on the next scan line. */
LABS1: begin
lab_ns=LABS2;
lab_op={dorgl,dst,addnib,dst_sav,wrhl};
end
LABS2: begin
lab_ns=LABS2B;
lab_op={sorgl,src,add,src,wrhi};
end
LABS2B: begin
lab_ns=LABS2C;
lab_op={noop,size,mov,sav_dst,wrlo};
end
LABS2C: begin
if(clp_status[2]) // trivial reject.
begin
lab_clr_busy = 1'b1;
lab_rst_cr = 1'b1;
lab_ns=LAB_WAIT;
end
else if(clp_status==3'b000)lab_ns=LABS3; // No clipping.
else if(clp_status==3'b011)
begin
lab_op={xend_pc,xmax_pc,sub,noop,wrno};
lab_ns=LABS2F;
end
else begin
lab_op={xmin_pc,dst,sub,noop,wrno};
lab_ns=LABS2D;
end
end
LABS2D: begin
lab_op={size,pline,sub,size,wrhi};
if(clp_status==3'b001)lab_ns=LABS2G;
else lab_ns=LABS2E;
end
LABS2E: begin
lab_op={xend_pc,xmax_pc,sub,noop,wrno};
lab_ns=LABS2F;
end
LABS2F: begin
lab_op={size,pline,sub,size,wrhi};
if(clp_status==3'b011)lab_ns=LABS3;
else lab_ns=LABS2G;
end
LABS2G: begin
lab_op={xmin_pc,noop,amcn_d,dst_sav,wrhl};
lab_ksel=zero;
lab_ns=LABS3;
end
/* calculate the write words per line adjusted X size. */
LABS3: begin
lab_ns=LABS4;
lab_set_sol=1'b1;
if(clp_status==3'b000)lab_op={dst,size,div16,wr_wrds_sav,wrhi};
else if(clp_status==3'b011) lab_op={dst,pline,div16,wr_wrds_sav,wrhi};
else lab_op={pline,size,div16,wr_wrds_sav,wrhi};
end
/* generate the start and end mask to be loaded in LABS5. */
LABS4: begin
lab_ns=LABS5;
lab_op={dst,size,add,noop,wrno};
lab_rstn_wad = 1'b1;
end
/* source minus destination nibble mode. for FIFO ADDRESS read = write, read = write-1. */
/* this will set the first read 8 flag if source nibble is less than destination nibble.*/
LABS5: begin
lab_ns=LABR1;
lab_ld_msk=1'b1; /* load the mask generated in LABS4. */
lab_op={noop,pix_dstx,mov,noop,wrno};
lab_ld_rad = 1'b1;
end
/* load the one and only read page count. */
LABR1: begin
lab_ld_wcnt=1'b1; /* this signal is externally delayed one clock. */
lab_op={noop,noop,mov_k,noop,wrno};
if(apat32_2)lab_ksel=eight;
else lab_ksel=one;
lab_ns=LABR2;
end
LABR2: lab_ns=LABR3;
/* request the read cycles. */
LABR3: begin
lab_op={wr_wrds,noop,amcn,noop,wrno};
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
/* if source fetch disable skip the read. */
if(!read_2)lab_ns=LABW1;
else if(mcrdy && !mw_fip)
begin
lab_mem_req=1'b1;
lab_mem_rd=1'b1;
lab_ns=LABW1;
end
else lab_ns=LABR3;
end
/* wait for the pipeline. */
LABW1: begin
lab_ns=LABW2;
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
lab_op={wr_wrds,noop,amcn,wr_wrds,wrhi};
end
/* Begin the write portion of the stretch bit blt state machine. */
LABW2: begin
lab_ld_wcnt=1'b1;
lab_ns=LABW3;
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
if(signx | xeqz)begin
lab_op={noop,wr_wrds,mov,noop,wrno};
lab_set_eol=1'b1;
lab_set_local_eol=1'b1;
end
else lab_op={noop,noop,mov_k,noop,wrno};
end
/* add 128 to the destination x pointer. */
LABW3: begin
if(local_eol && mcrdy && cache_rdy)
begin
lab_op={noop,sav_src_dst,movx,dst,wrhi};
lab_ns=LABW4;
end
else if(mcrdy && cache_rdy)
begin
lab_op={dst,noop,apcn,dst,wrhi};
lab_ns=LABW4;
end
else lab_ns=LABW3;
if(rmw)lab_ksel=D64;
else lab_ksel=D128;
end
LABW4: begin
if(local_eol)
begin
lab_op={noop,sav_src_dst,movx,dst,wrhi};
lab_mem_req=1'b1;
lab_clr_local_eol=1'b1;
lab_ns=LABNL1;
end
else
begin
lab_op={wr_wrds,noop,amcn,noop,wrno};
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
lab_mem_req=1'b1;
lab_ns=LABW1;
end
end
/* decrement the Y size register. */
LABNL1: begin
lab_op={size,noop,amcn,size,wrlo};
lab_set_sol=1'b1;
lab_dchgy = 1'b1;
lab_ns=LABNL2;
end
/* restore the write words per line. */
LABNL2: begin
lab_op={noop,sav_wr_wrds,mov,wr_wrds,wrhi};
lab_ns=LABNL3;
end
/* If Y size register goes to zero the bit blt is all done. */
/* Restore the original X destination registers. */
LABNL3: begin
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
if(yeqz)
begin
lab_clr_busy = 1'b1;
lab_rst_cr = 1'b1;
lab_ns=LAB_WAIT;
end
else begin
lab_ns=LABW1;
lab_op={pline,noop,amcn,noop,wrno};
end
end
LABNL4:
begin
lab_op={dst,pline,sub,dst,wrlo};
lab_ns=LABS3;
end
endcase
end
endmodule |
module omsp_gpio (
// OUTPUTs
irq_port1, // Port 1 interrupt
irq_port2, // Port 2 interrupt
p1_dout, // Port 1 data output
p1_dout_en, // Port 1 data output enable
p1_sel, // Port 1 function select
p2_dout, // Port 2 data output
p2_dout_en, // Port 2 data output enable
p2_sel, // Port 2 function select
p3_dout, // Port 3 data output
p3_dout_en, // Port 3 data output enable
p3_sel, // Port 3 function select
p4_dout, // Port 4 data output
p4_dout_en, // Port 4 data output enable
p4_sel, // Port 4 function select
p5_dout, // Port 5 data output
p5_dout_en, // Port 5 data output enable
p5_sel, // Port 5 function select
p6_dout, // Port 6 data output
p6_dout_en, // Port 6 data output enable
p6_sel, // Port 6 function select
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
p1_din, // Port 1 data input
p2_din, // Port 2 data input
p3_din, // Port 3 data input
p4_din, // Port 4 data input
p5_din, // Port 5 data input
p6_din, // Port 6 data input
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// PARAMETERs
//============
parameter P1_EN = 1'b1; // Enable Port 1
parameter P2_EN = 1'b1; // Enable Port 2
parameter P3_EN = 1'b0; // Enable Port 3
parameter P4_EN = 1'b0; // Enable Port 4
parameter P5_EN = 1'b0; // Enable Port 5
parameter P6_EN = 1'b0; // Enable Port 6
// OUTPUTs
//=========
output irq_port1; // Port 1 interrupt
output irq_port2; // Port 2 interrupt
output [7:0] p1_dout; // Port 1 data output
output [7:0] p1_dout_en; // Port 1 data output enable
output [7:0] p1_sel; // Port 1 function select
output [7:0] p2_dout; // Port 2 data output
output [7:0] p2_dout_en; // Port 2 data output enable
output [7:0] p2_sel; // Port 2 function select
output [7:0] p3_dout; // Port 3 data output
output [7:0] p3_dout_en; // Port 3 data output enable
output [7:0] p3_sel; // Port 3 function select
output [7:0] p4_dout; // Port 4 data output
output [7:0] p4_dout_en; // Port 4 data output enable
output [7:0] p4_sel; // Port 4 function select
output [7:0] p5_dout; // Port 5 data output
output [7:0] p5_dout_en; // Port 5 data output enable
output [7:0] p5_sel; // Port 5 function select
output [7:0] p6_dout; // Port 6 data output
output [7:0] p6_dout_en; // Port 6 data output enable
output [7:0] p6_sel; // Port 6 function select
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [7:0] p1_din; // Port 1 data input
input [7:0] p2_din; // Port 2 data input
input [7:0] p3_din; // Port 3 data input
input [7:0] p4_din; // Port 4 data input
input [7:0] p5_din; // Port 5 data input
input [7:0] p6_din; // Port 6 data input
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Masks
parameter P1_EN_MSK = {8{P1_EN[0]}};
parameter P2_EN_MSK = {8{P2_EN[0]}};
parameter P3_EN_MSK = {8{P3_EN[0]}};
parameter P4_EN_MSK = {8{P4_EN[0]}};
parameter P5_EN_MSK = {8{P5_EN[0]}};
parameter P6_EN_MSK = {8{P6_EN[0]}};
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0000;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 6;
// Register addresses offset
parameter [DEC_WD-1:0] P1IN = 'h20, // Port 1
P1OUT = 'h21,
P1DIR = 'h22,
P1IFG = 'h23,
P1IES = 'h24,
P1IE = 'h25,
P1SEL = 'h26,
P2IN = 'h28, // Port 2
P2OUT = 'h29,
P2DIR = 'h2A,
P2IFG = 'h2B,
P2IES = 'h2C,
P2IE = 'h2D,
P2SEL = 'h2E,
P3IN = 'h18, // Port 3
P3OUT = 'h19,
P3DIR = 'h1A,
P3SEL = 'h1B,
P4IN = 'h1C, // Port 4
P4OUT = 'h1D,
P4DIR = 'h1E,
P4SEL = 'h1F,
P5IN = 'h30, // Port 5
P5OUT = 'h31,
P5DIR = 'h32,
P5SEL = 'h33,
P6IN = 'h34, // Port 6
P6OUT = 'h35,
P6DIR = 'h36,
P6SEL = 'h37;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] P1IN_D = (BASE_REG << P1IN), // Port 1
P1OUT_D = (BASE_REG << P1OUT),
P1DIR_D = (BASE_REG << P1DIR),
P1IFG_D = (BASE_REG << P1IFG),
P1IES_D = (BASE_REG << P1IES),
P1IE_D = (BASE_REG << P1IE),
P1SEL_D = (BASE_REG << P1SEL),
P2IN_D = (BASE_REG << P2IN), // Port 2
P2OUT_D = (BASE_REG << P2OUT),
P2DIR_D = (BASE_REG << P2DIR),
P2IFG_D = (BASE_REG << P2IFG),
P2IES_D = (BASE_REG << P2IES),
P2IE_D = (BASE_REG << P2IE),
P2SEL_D = (BASE_REG << P2SEL),
P3IN_D = (BASE_REG << P3IN), // Port 3
P3OUT_D = (BASE_REG << P3OUT),
P3DIR_D = (BASE_REG << P3DIR),
P3SEL_D = (BASE_REG << P3SEL),
P4IN_D = (BASE_REG << P4IN), // Port 4
P4OUT_D = (BASE_REG << P4OUT),
P4DIR_D = (BASE_REG << P4DIR),
P4SEL_D = (BASE_REG << P4SEL),
P5IN_D = (BASE_REG << P5IN), // Port 5
P5OUT_D = (BASE_REG << P5OUT),
P5DIR_D = (BASE_REG << P5DIR),
P5SEL_D = (BASE_REG << P5SEL),
P6IN_D = (BASE_REG << P6IN), // Port 6
P6OUT_D = (BASE_REG << P6OUT),
P6DIR_D = (BASE_REG << P6DIR),
P6SEL_D = (BASE_REG << P6SEL);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (P1IN_D & {DEC_SZ{(reg_addr==(P1IN >>1)) & P1_EN[0]}}) |
(P1OUT_D & {DEC_SZ{(reg_addr==(P1OUT >>1)) & P1_EN[0]}}) |
(P1DIR_D & {DEC_SZ{(reg_addr==(P1DIR >>1)) & P1_EN[0]}}) |
(P1IFG_D & {DEC_SZ{(reg_addr==(P1IFG >>1)) & P1_EN[0]}}) |
(P1IES_D & {DEC_SZ{(reg_addr==(P1IES >>1)) & P1_EN[0]}}) |
(P1IE_D & {DEC_SZ{(reg_addr==(P1IE >>1)) & P1_EN[0]}}) |
(P1SEL_D & {DEC_SZ{(reg_addr==(P1SEL >>1)) & P1_EN[0]}}) |
(P2IN_D & {DEC_SZ{(reg_addr==(P2IN >>1)) & P2_EN[0]}}) |
(P2OUT_D & {DEC_SZ{(reg_addr==(P2OUT >>1)) & P2_EN[0]}}) |
(P2DIR_D & {DEC_SZ{(reg_addr==(P2DIR >>1)) & P2_EN[0]}}) |
(P2IFG_D & {DEC_SZ{(reg_addr==(P2IFG >>1)) & P2_EN[0]}}) |
(P2IES_D & {DEC_SZ{(reg_addr==(P2IES >>1)) & P2_EN[0]}}) |
(P2IE_D & {DEC_SZ{(reg_addr==(P2IE >>1)) & P2_EN[0]}}) |
(P2SEL_D & {DEC_SZ{(reg_addr==(P2SEL >>1)) & P2_EN[0]}}) |
(P3IN_D & {DEC_SZ{(reg_addr==(P3IN >>1)) & P3_EN[0]}}) |
(P3OUT_D & {DEC_SZ{(reg_addr==(P3OUT >>1)) & P3_EN[0]}}) |
(P3DIR_D & {DEC_SZ{(reg_addr==(P3DIR >>1)) & P3_EN[0]}}) |
(P3SEL_D & {DEC_SZ{(reg_addr==(P3SEL >>1)) & P3_EN[0]}}) |
(P4IN_D & {DEC_SZ{(reg_addr==(P4IN >>1)) & P4_EN[0]}}) |
(P4OUT_D & {DEC_SZ{(reg_addr==(P4OUT >>1)) & P4_EN[0]}}) |
(P4DIR_D & {DEC_SZ{(reg_addr==(P4DIR >>1)) & P4_EN[0]}}) |
(P4SEL_D & {DEC_SZ{(reg_addr==(P4SEL >>1)) & P4_EN[0]}}) |
(P5IN_D & {DEC_SZ{(reg_addr==(P5IN >>1)) & P5_EN[0]}}) |
(P5OUT_D & {DEC_SZ{(reg_addr==(P5OUT >>1)) & P5_EN[0]}}) |
(P5DIR_D & {DEC_SZ{(reg_addr==(P5DIR >>1)) & P5_EN[0]}}) |
(P5SEL_D & {DEC_SZ{(reg_addr==(P5SEL >>1)) & P5_EN[0]}}) |
(P6IN_D & {DEC_SZ{(reg_addr==(P6IN >>1)) & P6_EN[0]}}) |
(P6OUT_D & {DEC_SZ{(reg_addr==(P6OUT >>1)) & P6_EN[0]}}) |
(P6DIR_D & {DEC_SZ{(reg_addr==(P6DIR >>1)) & P6_EN[0]}}) |
(P6SEL_D & {DEC_SZ{(reg_addr==(P6SEL >>1)) & P6_EN[0]}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// P1IN Register
//---------------
wire [7:0] p1in;
omsp_sync_cell sync_cell_p1in_0 (.data_out(p1in[0]), .data_in(p1_din[0] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_1 (.data_out(p1in[1]), .data_in(p1_din[1] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_2 (.data_out(p1in[2]), .data_in(p1_din[2] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_3 (.data_out(p1in[3]), .data_in(p1_din[3] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_4 (.data_out(p1in[4]), .data_in(p1_din[4] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_5 (.data_out(p1in[5]), .data_in(p1_din[5] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_6 (.data_out(p1in[6]), .data_in(p1_din[6] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p1in_7 (.data_out(p1in[7]), .data_in(p1_din[7] & P1_EN[0]), .clk(mclk), .rst(puc_rst));
// P1OUT Register
//----------------
reg [7:0] p1out;
wire p1out_wr = P1OUT[0] ? reg_hi_wr[P1OUT] : reg_lo_wr[P1OUT];
wire [7:0] p1out_nxt = P1OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1out <= 8'h00;
else if (p1out_wr) p1out <= p1out_nxt & P1_EN_MSK;
assign p1_dout = p1out;
// P1DIR Register
//----------------
reg [7:0] p1dir;
wire p1dir_wr = P1DIR[0] ? reg_hi_wr[P1DIR] : reg_lo_wr[P1DIR];
wire [7:0] p1dir_nxt = P1DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1dir <= 8'h00;
else if (p1dir_wr) p1dir <= p1dir_nxt & P1_EN_MSK;
assign p1_dout_en = p1dir;
// P1IFG Register
//----------------
reg [7:0] p1ifg;
wire p1ifg_wr = P1IFG[0] ? reg_hi_wr[P1IFG] : reg_lo_wr[P1IFG];
wire [7:0] p1ifg_nxt = P1IFG[0] ? per_din[15:8] : per_din[7:0];
wire [7:0] p1ifg_set;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1ifg <= 8'h00;
else if (p1ifg_wr) p1ifg <= (p1ifg_nxt | p1ifg_set) & P1_EN_MSK;
else p1ifg <= (p1ifg | p1ifg_set) & P1_EN_MSK;
// P1IES Register
//----------------
reg [7:0] p1ies;
wire p1ies_wr = P1IES[0] ? reg_hi_wr[P1IES] : reg_lo_wr[P1IES];
wire [7:0] p1ies_nxt = P1IES[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1ies <= 8'h00;
else if (p1ies_wr) p1ies <= p1ies_nxt & P1_EN_MSK;
// P1IE Register
//----------------
reg [7:0] p1ie;
wire p1ie_wr = P1IE[0] ? reg_hi_wr[P1IE] : reg_lo_wr[P1IE];
wire [7:0] p1ie_nxt = P1IE[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1ie <= 8'h00;
else if (p1ie_wr) p1ie <= p1ie_nxt & P1_EN_MSK;
// P1SEL Register
//----------------
reg [7:0] p1sel;
wire p1sel_wr = P1SEL[0] ? reg_hi_wr[P1SEL] : reg_lo_wr[P1SEL];
wire [7:0] p1sel_nxt = P1SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1sel <= 8'h00;
else if (p1sel_wr) p1sel <= p1sel_nxt & P1_EN_MSK;
assign p1_sel = p1sel;
// P2IN Register
//---------------
wire [7:0] p2in;
omsp_sync_cell sync_cell_p2in_0 (.data_out(p2in[0]), .data_in(p2_din[0] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_1 (.data_out(p2in[1]), .data_in(p2_din[1] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_2 (.data_out(p2in[2]), .data_in(p2_din[2] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_3 (.data_out(p2in[3]), .data_in(p2_din[3] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_4 (.data_out(p2in[4]), .data_in(p2_din[4] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_5 (.data_out(p2in[5]), .data_in(p2_din[5] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_6 (.data_out(p2in[6]), .data_in(p2_din[6] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p2in_7 (.data_out(p2in[7]), .data_in(p2_din[7] & P2_EN[0]), .clk(mclk), .rst(puc_rst));
// P2OUT Register
//----------------
reg [7:0] p2out;
wire p2out_wr = P2OUT[0] ? reg_hi_wr[P2OUT] : reg_lo_wr[P2OUT];
wire [7:0] p2out_nxt = P2OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2out <= 8'h00;
else if (p2out_wr) p2out <= p2out_nxt & P2_EN_MSK;
assign p2_dout = p2out;
// P2DIR Register
//----------------
reg [7:0] p2dir;
wire p2dir_wr = P2DIR[0] ? reg_hi_wr[P2DIR] : reg_lo_wr[P2DIR];
wire [7:0] p2dir_nxt = P2DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2dir <= 8'h00;
else if (p2dir_wr) p2dir <= p2dir_nxt & P2_EN_MSK;
assign p2_dout_en = p2dir;
// P2IFG Register
//----------------
reg [7:0] p2ifg;
wire p2ifg_wr = P2IFG[0] ? reg_hi_wr[P2IFG] : reg_lo_wr[P2IFG];
wire [7:0] p2ifg_nxt = P2IFG[0] ? per_din[15:8] : per_din[7:0];
wire [7:0] p2ifg_set;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2ifg <= 8'h00;
else if (p2ifg_wr) p2ifg <= (p2ifg_nxt | p2ifg_set) & P2_EN_MSK;
else p2ifg <= (p2ifg | p2ifg_set) & P2_EN_MSK;
// P2IES Register
//----------------
reg [7:0] p2ies;
wire p2ies_wr = P2IES[0] ? reg_hi_wr[P2IES] : reg_lo_wr[P2IES];
wire [7:0] p2ies_nxt = P2IES[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2ies <= 8'h00;
else if (p2ies_wr) p2ies <= p2ies_nxt & P2_EN_MSK;
// P2IE Register
//----------------
reg [7:0] p2ie;
wire p2ie_wr = P2IE[0] ? reg_hi_wr[P2IE] : reg_lo_wr[P2IE];
wire [7:0] p2ie_nxt = P2IE[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2ie <= 8'h00;
else if (p2ie_wr) p2ie <= p2ie_nxt & P2_EN_MSK;
// P2SEL Register
//----------------
reg [7:0] p2sel;
wire p2sel_wr = P2SEL[0] ? reg_hi_wr[P2SEL] : reg_lo_wr[P2SEL];
wire [7:0] p2sel_nxt = P2SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2sel <= 8'h00;
else if (p2sel_wr) p2sel <= p2sel_nxt & P2_EN_MSK;
assign p2_sel = p2sel;
// P3IN Register
//---------------
wire [7:0] p3in;
omsp_sync_cell sync_cell_p3in_0 (.data_out(p3in[0]), .data_in(p3_din[0] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_1 (.data_out(p3in[1]), .data_in(p3_din[1] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_2 (.data_out(p3in[2]), .data_in(p3_din[2] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_3 (.data_out(p3in[3]), .data_in(p3_din[3] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_4 (.data_out(p3in[4]), .data_in(p3_din[4] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_5 (.data_out(p3in[5]), .data_in(p3_din[5] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_6 (.data_out(p3in[6]), .data_in(p3_din[6] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p3in_7 (.data_out(p3in[7]), .data_in(p3_din[7] & P3_EN[0]), .clk(mclk), .rst(puc_rst));
// P3OUT Register
//----------------
reg [7:0] p3out;
wire p3out_wr = P3OUT[0] ? reg_hi_wr[P3OUT] : reg_lo_wr[P3OUT];
wire [7:0] p3out_nxt = P3OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p3out <= 8'h00;
else if (p3out_wr) p3out <= p3out_nxt & P3_EN_MSK;
assign p3_dout = p3out;
// P3DIR Register
//----------------
reg [7:0] p3dir;
wire p3dir_wr = P3DIR[0] ? reg_hi_wr[P3DIR] : reg_lo_wr[P3DIR];
wire [7:0] p3dir_nxt = P3DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p3dir <= 8'h00;
else if (p3dir_wr) p3dir <= p3dir_nxt & P3_EN_MSK;
assign p3_dout_en = p3dir;
// P3SEL Register
//----------------
reg [7:0] p3sel;
wire p3sel_wr = P3SEL[0] ? reg_hi_wr[P3SEL] : reg_lo_wr[P3SEL];
wire [7:0] p3sel_nxt = P3SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p3sel <= 8'h00;
else if (p3sel_wr) p3sel <= p3sel_nxt & P3_EN_MSK;
assign p3_sel = p3sel;
// P4IN Register
//---------------
wire [7:0] p4in;
omsp_sync_cell sync_cell_p4in_0 (.data_out(p4in[0]), .data_in(p4_din[0] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_1 (.data_out(p4in[1]), .data_in(p4_din[1] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_2 (.data_out(p4in[2]), .data_in(p4_din[2] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_3 (.data_out(p4in[3]), .data_in(p4_din[3] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_4 (.data_out(p4in[4]), .data_in(p4_din[4] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_5 (.data_out(p4in[5]), .data_in(p4_din[5] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_6 (.data_out(p4in[6]), .data_in(p4_din[6] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p4in_7 (.data_out(p4in[7]), .data_in(p4_din[7] & P4_EN[0]), .clk(mclk), .rst(puc_rst));
// P4OUT Register
//----------------
reg [7:0] p4out;
wire p4out_wr = P4OUT[0] ? reg_hi_wr[P4OUT] : reg_lo_wr[P4OUT];
wire [7:0] p4out_nxt = P4OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p4out <= 8'h00;
else if (p4out_wr) p4out <= p4out_nxt & P4_EN_MSK;
assign p4_dout = p4out;
// P4DIR Register
//----------------
reg [7:0] p4dir;
wire p4dir_wr = P4DIR[0] ? reg_hi_wr[P4DIR] : reg_lo_wr[P4DIR];
wire [7:0] p4dir_nxt = P4DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p4dir <= 8'h00;
else if (p4dir_wr) p4dir <= p4dir_nxt & P4_EN_MSK;
assign p4_dout_en = p4dir;
// P4SEL Register
//----------------
reg [7:0] p4sel;
wire p4sel_wr = P4SEL[0] ? reg_hi_wr[P4SEL] : reg_lo_wr[P4SEL];
wire [7:0] p4sel_nxt = P4SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p4sel <= 8'h00;
else if (p4sel_wr) p4sel <= p4sel_nxt & P4_EN_MSK;
assign p4_sel = p4sel;
// P5IN Register
//---------------
wire [7:0] p5in;
omsp_sync_cell sync_cell_p5in_0 (.data_out(p5in[0]), .data_in(p5_din[0] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_1 (.data_out(p5in[1]), .data_in(p5_din[1] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_2 (.data_out(p5in[2]), .data_in(p5_din[2] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_3 (.data_out(p5in[3]), .data_in(p5_din[3] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_4 (.data_out(p5in[4]), .data_in(p5_din[4] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_5 (.data_out(p5in[5]), .data_in(p5_din[5] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_6 (.data_out(p5in[6]), .data_in(p5_din[6] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p5in_7 (.data_out(p5in[7]), .data_in(p5_din[7] & P5_EN[0]), .clk(mclk), .rst(puc_rst));
// P5OUT Register
//----------------
reg [7:0] p5out;
wire p5out_wr = P5OUT[0] ? reg_hi_wr[P5OUT] : reg_lo_wr[P5OUT];
wire [7:0] p5out_nxt = P5OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p5out <= 8'h00;
else if (p5out_wr) p5out <= p5out_nxt & P5_EN_MSK;
assign p5_dout = p5out;
// P5DIR Register
//----------------
reg [7:0] p5dir;
wire p5dir_wr = P5DIR[0] ? reg_hi_wr[P5DIR] : reg_lo_wr[P5DIR];
wire [7:0] p5dir_nxt = P5DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p5dir <= 8'h00;
else if (p5dir_wr) p5dir <= p5dir_nxt & P5_EN_MSK;
assign p5_dout_en = p5dir;
// P5SEL Register
//----------------
reg [7:0] p5sel;
wire p5sel_wr = P5SEL[0] ? reg_hi_wr[P5SEL] : reg_lo_wr[P5SEL];
wire [7:0] p5sel_nxt = P5SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p5sel <= 8'h00;
else if (p5sel_wr) p5sel <= p5sel_nxt & P5_EN_MSK;
assign p5_sel = p5sel;
// P6IN Register
//---------------
wire [7:0] p6in;
omsp_sync_cell sync_cell_p6in_0 (.data_out(p6in[0]), .data_in(p6_din[0] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_1 (.data_out(p6in[1]), .data_in(p6_din[1] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_2 (.data_out(p6in[2]), .data_in(p6_din[2] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_3 (.data_out(p6in[3]), .data_in(p6_din[3] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_4 (.data_out(p6in[4]), .data_in(p6_din[4] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_5 (.data_out(p6in[5]), .data_in(p6_din[5] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_6 (.data_out(p6in[6]), .data_in(p6_din[6] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
omsp_sync_cell sync_cell_p6in_7 (.data_out(p6in[7]), .data_in(p6_din[7] & P6_EN[0]), .clk(mclk), .rst(puc_rst));
// P6OUT Register
//----------------
reg [7:0] p6out;
wire p6out_wr = P6OUT[0] ? reg_hi_wr[P6OUT] : reg_lo_wr[P6OUT];
wire [7:0] p6out_nxt = P6OUT[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p6out <= 8'h00;
else if (p6out_wr) p6out <= p6out_nxt & P6_EN_MSK;
assign p6_dout = p6out;
// P6DIR Register
//----------------
reg [7:0] p6dir;
wire p6dir_wr = P6DIR[0] ? reg_hi_wr[P6DIR] : reg_lo_wr[P6DIR];
wire [7:0] p6dir_nxt = P6DIR[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p6dir <= 8'h00;
else if (p6dir_wr) p6dir <= p6dir_nxt & P6_EN_MSK;
assign p6_dout_en = p6dir;
// P6SEL Register
//----------------
reg [7:0] p6sel;
wire p6sel_wr = P6SEL[0] ? reg_hi_wr[P6SEL] : reg_lo_wr[P6SEL];
wire [7:0] p6sel_nxt = P6SEL[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p6sel <= 8'h00;
else if (p6sel_wr) p6sel <= p6sel_nxt & P6_EN_MSK;
assign p6_sel = p6sel;
//============================================================================
// 4) INTERRUPT GENERATION
//============================================================================
// Port 1 interrupt
//------------------
// Delay input
reg [7:0] p1in_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p1in_dly <= 8'h00;
else p1in_dly <= p1in & P1_EN_MSK;
// Edge detection
wire [7:0] p1in_re = p1in & ~p1in_dly;
wire [7:0] p1in_fe = ~p1in & p1in_dly;
// Set interrupt flag
assign p1ifg_set = {p1ies[7] ? p1in_fe[7] : p1in_re[7],
p1ies[6] ? p1in_fe[6] : p1in_re[6],
p1ies[5] ? p1in_fe[5] : p1in_re[5],
p1ies[4] ? p1in_fe[4] : p1in_re[4],
p1ies[3] ? p1in_fe[3] : p1in_re[3],
p1ies[2] ? p1in_fe[2] : p1in_re[2],
p1ies[1] ? p1in_fe[1] : p1in_re[1],
p1ies[0] ? p1in_fe[0] : p1in_re[0]} & P1_EN_MSK;
// Generate CPU interrupt
assign irq_port1 = |(p1ie & p1ifg) & P1_EN[0];
// Port 1 interrupt
//------------------
// Delay input
reg [7:0] p2in_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) p2in_dly <= 8'h00;
else p2in_dly <= p2in & P2_EN_MSK;
// Edge detection
wire [7:0] p2in_re = p2in & ~p2in_dly;
wire [7:0] p2in_fe = ~p2in & p2in_dly;
// Set interrupt flag
assign p2ifg_set = {p2ies[7] ? p2in_fe[7] : p2in_re[7],
p2ies[6] ? p2in_fe[6] : p2in_re[6],
p2ies[5] ? p2in_fe[5] : p2in_re[5],
p2ies[4] ? p2in_fe[4] : p2in_re[4],
p2ies[3] ? p2in_fe[3] : p2in_re[3],
p2ies[2] ? p2in_fe[2] : p2in_re[2],
p2ies[1] ? p2in_fe[1] : p2in_re[1],
p2ies[0] ? p2in_fe[0] : p2in_re[0]} & P2_EN_MSK;
// Generate CPU interrupt
assign irq_port2 = |(p2ie & p2ifg) & P2_EN[0];
//============================================================================
// 5) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] p1in_rd = {8'h00, (p1in & {8{reg_rd[P1IN]}})} << (8 & {4{P1IN[0]}});
wire [15:0] p1out_rd = {8'h00, (p1out & {8{reg_rd[P1OUT]}})} << (8 & {4{P1OUT[0]}});
wire [15:0] p1dir_rd = {8'h00, (p1dir & {8{reg_rd[P1DIR]}})} << (8 & {4{P1DIR[0]}});
wire [15:0] p1ifg_rd = {8'h00, (p1ifg & {8{reg_rd[P1IFG]}})} << (8 & {4{P1IFG[0]}});
wire [15:0] p1ies_rd = {8'h00, (p1ies & {8{reg_rd[P1IES]}})} << (8 & {4{P1IES[0]}});
wire [15:0] p1ie_rd = {8'h00, (p1ie & {8{reg_rd[P1IE]}})} << (8 & {4{P1IE[0]}});
wire [15:0] p1sel_rd = {8'h00, (p1sel & {8{reg_rd[P1SEL]}})} << (8 & {4{P1SEL[0]}});
wire [15:0] p2in_rd = {8'h00, (p2in & {8{reg_rd[P2IN]}})} << (8 & {4{P2IN[0]}});
wire [15:0] p2out_rd = {8'h00, (p2out & {8{reg_rd[P2OUT]}})} << (8 & {4{P2OUT[0]}});
wire [15:0] p2dir_rd = {8'h00, (p2dir & {8{reg_rd[P2DIR]}})} << (8 & {4{P2DIR[0]}});
wire [15:0] p2ifg_rd = {8'h00, (p2ifg & {8{reg_rd[P2IFG]}})} << (8 & {4{P2IFG[0]}});
wire [15:0] p2ies_rd = {8'h00, (p2ies & {8{reg_rd[P2IES]}})} << (8 & {4{P2IES[0]}});
wire [15:0] p2ie_rd = {8'h00, (p2ie & {8{reg_rd[P2IE]}})} << (8 & {4{P2IE[0]}});
wire [15:0] p2sel_rd = {8'h00, (p2sel & {8{reg_rd[P2SEL]}})} << (8 & {4{P2SEL[0]}});
wire [15:0] p3in_rd = {8'h00, (p3in & {8{reg_rd[P3IN]}})} << (8 & {4{P3IN[0]}});
wire [15:0] p3out_rd = {8'h00, (p3out & {8{reg_rd[P3OUT]}})} << (8 & {4{P3OUT[0]}});
wire [15:0] p3dir_rd = {8'h00, (p3dir & {8{reg_rd[P3DIR]}})} << (8 & {4{P3DIR[0]}});
wire [15:0] p3sel_rd = {8'h00, (p3sel & {8{reg_rd[P3SEL]}})} << (8 & {4{P3SEL[0]}});
wire [15:0] p4in_rd = {8'h00, (p4in & {8{reg_rd[P4IN]}})} << (8 & {4{P4IN[0]}});
wire [15:0] p4out_rd = {8'h00, (p4out & {8{reg_rd[P4OUT]}})} << (8 & {4{P4OUT[0]}});
wire [15:0] p4dir_rd = {8'h00, (p4dir & {8{reg_rd[P4DIR]}})} << (8 & {4{P4DIR[0]}});
wire [15:0] p4sel_rd = {8'h00, (p4sel & {8{reg_rd[P4SEL]}})} << (8 & {4{P4SEL[0]}});
wire [15:0] p5in_rd = {8'h00, (p5in & {8{reg_rd[P5IN]}})} << (8 & {4{P5IN[0]}});
wire [15:0] p5out_rd = {8'h00, (p5out & {8{reg_rd[P5OUT]}})} << (8 & {4{P5OUT[0]}});
wire [15:0] p5dir_rd = {8'h00, (p5dir & {8{reg_rd[P5DIR]}})} << (8 & {4{P5DIR[0]}});
wire [15:0] p5sel_rd = {8'h00, (p5sel & {8{reg_rd[P5SEL]}})} << (8 & {4{P5SEL[0]}});
wire [15:0] p6in_rd = {8'h00, (p6in & {8{reg_rd[P6IN]}})} << (8 & {4{P6IN[0]}});
wire [15:0] p6out_rd = {8'h00, (p6out & {8{reg_rd[P6OUT]}})} << (8 & {4{P6OUT[0]}});
wire [15:0] p6dir_rd = {8'h00, (p6dir & {8{reg_rd[P6DIR]}})} << (8 & {4{P6DIR[0]}});
wire [15:0] p6sel_rd = {8'h00, (p6sel & {8{reg_rd[P6SEL]}})} << (8 & {4{P6SEL[0]}});
wire [15:0] per_dout = p1in_rd |
p1out_rd |
p1dir_rd |
p1ifg_rd |
p1ies_rd |
p1ie_rd |
p1sel_rd |
p2in_rd |
p2out_rd |
p2dir_rd |
p2ifg_rd |
p2ies_rd |
p2ie_rd |
p2sel_rd |
p3in_rd |
p3out_rd |
p3dir_rd |
p3sel_rd |
p4in_rd |
p4out_rd |
p4dir_rd |
p4sel_rd |
p5in_rd |
p5out_rd |
p5dir_rd |
p5sel_rd |
p6in_rd |
p6out_rd |
p6dir_rd |
p6sel_rd;
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg CI;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT_N;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CI = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CI = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CI = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CI = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CI = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CI = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__fahcon dut (.A(A), .B(B), .CI(CI), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT_N(COUT_N), .SUM(SUM));
endmodule |
module pcie_7x_v1_3 # (
parameter CFG_VEND_ID = 16'h10EE,
parameter CFG_DEV_ID = 16'h4243,
parameter CFG_REV_ID = 8'h03,
parameter CFG_SUBSYS_VEND_ID = 16'h10EE,
parameter CFG_SUBSYS_ID = 16'h0007,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter PIPE_PIPELINE_STAGES = 1,
parameter [11:0] AER_BASE_PTR = 12'h000,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h000,
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_ON = "FALSE",
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "FALSE",
parameter [31:0] BAR0 = 32'hFF000000,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'h00000000,
parameter [31:0] BAR3 = 32'h00000000,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 128,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [23:0] CLASS_CODE = 24'h050000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'b00,
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_LANE_REVERSAL = "TRUE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h000,
parameter DSN_CAP_ON = "TRUE",
parameter [10:0] ENABLE_MSG_ROUTE = 11'b00000000000,
parameter ENABLE_RX_TD_ECRC_TRIM = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'h00000000,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [7:0] INTERRUPT_PIN = 8'h1,
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h2,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h04,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 1,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h04,
parameter MSI_CAP_MULTIMSGCAP = 0,
parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter MSI_CAP_ON = "TRUE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter MSIX_CAP_ON = "FALSE",
parameter MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h0,
parameter MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h0,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h0,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00,
parameter PM_CAP_DSI = "FALSE",
parameter PM_CAP_D1SUPPORT = "FALSE",
parameter PM_CAP_D2SUPPORT = "FALSE",
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [1:0] PM_DATA_SCALE0 = 2'h0,
parameter [1:0] PM_DATA_SCALE1 = 2'h0,
parameter [1:0] PM_DATA_SCALE2 = 2'h0,
parameter [1:0] PM_DATA_SCALE3 = 2'h0,
parameter [1:0] PM_DATA_SCALE4 = 2'h0,
parameter [1:0] PM_DATA_SCALE5 = 2'h0,
parameter [1:0] PM_DATA_SCALE6 = 2'h0,
parameter [1:0] PM_DATA_SCALE7 = 2'h0,
parameter [7:0] PM_DATA0 = 8'h00,
parameter [7:0] PM_DATA1 = 8'h00,
parameter [7:0] PM_DATA2 = 8'h00,
parameter [7:0] PM_DATA3 = 8'h00,
parameter [7:0] PM_DATA4 = 8'h00,
parameter [7:0] PM_DATA5 = 8'h00,
parameter [7:0] PM_DATA6 = 8'h00,
parameter [7:0] PM_DATA7 = 8'h00,
parameter [11:0] RBAR_BASE_PTR = 12'h000,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00001,
parameter [2:0] RBAR_NUM = 3'h0,
parameter RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter TL_RX_RAM_RADDR_LATENCY = 0,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TX_RAM_RADDR_LATENCY = 0,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_NP_FC = "TRUE",
parameter TRN_DW = "TRUE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "FALSE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK_FREQ = 3,
parameter USER_CLK2_DIV2 = "TRUE",
parameter [11:0] VC_BASE_PTR = 12'h000,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h7FF,
parameter VC0_TOTAL_CREDITS_CD = 461,
parameter VC0_TOTAL_CREDITS_CH = 36,
parameter VC0_TOTAL_CREDITS_NPH = 12,
parameter VC0_TOTAL_CREDITS_NPD = 24,
parameter VC0_TOTAL_CREDITS_PD = 437,
parameter VC0_TOTAL_CREDITS_PH = 32,
parameter VC0_TX_LASTPACKET = 29,
parameter [11:0] VSEC_BASE_PTR = 12'h000,
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter [4:0] INFER_EI = 5'h00,
parameter IS_SWITCH = "FALSE",
parameter LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_RSVD_23 = 0,
parameter LINK_CONTROL_RCB = 0,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR =8'h00,
parameter N_FTS_COMCLK_GEN1 = 255,
parameter N_FTS_COMCLK_GEN2 = 255,
parameter N_FTS_GEN1 = 255,
parameter N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter PCIE_CAP_ON = "TRUE",
parameter PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter PCIE_REVISION = 2,
parameter PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter PCIE_EXT_CLK = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter PM_CAP_AUXCURRENT = 0,
parameter [7:0] PM_CAP_ID = 8'h01,
parameter PM_CAP_ON = "TRUE",
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter PM_CAP_RSVD_04 = 0,
parameter PM_CAP_VERSION = 3,
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_B2B3 = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter SELECT_DLL_IF = "FALSE",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter TL_RBYPASS = "FALSE",
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter DEV_CAP_RSVD_14_12 = 0,
parameter DEV_CAP_RSVD_17_16 = 0,
parameter DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1,
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter MPS_FORCE = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter PM_MF = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SIM_VERSION = "1.0",
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter UR_CFG1 = "TRUE",
parameter USE_RID_PINS = "FALSE",
// New Parameters
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter PCIE_USE_MODE = "1.0"
)
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock Inputs //
//----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXUSRCLK_IN,
input PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk_out,
output reg user_reset_out,
output reg user_lnk_up,
// Tx
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
output s_axis_tx_tready,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
input tx_cfg_gnt,
// Rx
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
output wire cfg_pmcsr_pme_en,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_status,
output wire cfg_received_func_lvl_rst,
// Management Interface
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_en,
input wire cfg_mgmt_rd_en,
input wire cfg_mgmt_wr_readonly,
// Error Reporting Interface
input wire cfg_err_ecrc,
input wire cfg_err_ur,
input wire cfg_err_cpl_timeout,
input wire cfg_err_cpl_unexpect,
input wire cfg_err_cpl_abort,
input wire cfg_err_posted,
input wire cfg_err_cor,
input wire cfg_err_atomic_egress_blocked,
input wire cfg_err_internal_cor,
input wire cfg_err_malformed,
input wire cfg_err_mc_blocked,
input wire cfg_err_poisoned,
input wire cfg_err_norecovery,
input wire [47:0] cfg_err_tlp_cpl_header,
output wire cfg_err_cpl_rdy,
input wire cfg_err_locked,
input wire cfg_err_acs,
input wire cfg_err_internal_uncor,
input wire cfg_trn_pending,
input wire cfg_pm_halt_aspm_l0s,
input wire cfg_pm_halt_aspm_l1,
input wire cfg_pm_force_state_en,
input wire [1:0] cfg_pm_force_state,
input wire [63:0] cfg_dsn,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
// Interrupt Interface Signals
input wire cfg_interrupt,
output wire cfg_interrupt_rdy,
input wire cfg_interrupt_assert,
input wire [7:0] cfg_interrupt_di,
output wire [7:0] cfg_interrupt_do,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
input wire cfg_interrupt_stat,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
output cfg_to_turnoff,
input wire cfg_turnoff_ok,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
input wire cfg_pm_wake,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire cfg_pm_send_pme_to,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire cfg_mgmt_wr_rw1c_as_rw,
output cfg_msg_received,
output [15:0] cfg_msg_data,
output wire cfg_bridge_serr_en,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_setslotpowerlimit,
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
output wire pl_received_hot_rst,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire pl_transmit_hot_rst,
input wire pl_downstream_deemph_source,
//----------------------------------------------------------------------------------------------------------------//
// 6. AER interface //
//----------------------------------------------------------------------------------------------------------------//
input wire [127:0] cfg_err_aer_headerlog,
input wire [4:0] cfg_aer_interrupt_msgnum,
output wire cfg_err_aer_headerlog_set,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
output wire [6:0] cfg_vc_tcvc_map,
//----------------------------------------------------------------------------------------------------------------//
// 8. System(SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire sys_clk,
input wire sys_reset
);
wire user_clk;
wire user_clk2;
wire [15:0] cfg_vend_id = CFG_VEND_ID;
wire [15:0] cfg_dev_id = CFG_DEV_ID;
wire [7:0] cfg_rev_id = CFG_REV_ID;
wire [15:0] cfg_subsys_vend_id = CFG_SUBSYS_VEND_ID;
wire [15:0] cfg_subsys_id = CFG_SUBSYS_ID;
// PIPE Interface Wires
wire phy_rdy_n;
wire pipe_rx0_polarity_gt;
wire pipe_rx1_polarity_gt;
wire pipe_rx2_polarity_gt;
wire pipe_rx3_polarity_gt;
wire pipe_rx4_polarity_gt;
wire pipe_rx5_polarity_gt;
wire pipe_rx6_polarity_gt;
wire pipe_rx7_polarity_gt;
wire pipe_tx_deemph_gt;
wire [2:0] pipe_tx_margin_gt;
wire pipe_tx_rate_gt;
wire pipe_tx_rcvr_det_gt;
wire [1:0] pipe_tx0_char_is_k_gt;
wire pipe_tx0_compliance_gt;
wire [15:0] pipe_tx0_data_gt;
wire pipe_tx0_elec_idle_gt;
wire [1:0] pipe_tx0_powerdown_gt;
wire [1:0] pipe_tx1_char_is_k_gt;
wire pipe_tx1_compliance_gt;
wire [15:0] pipe_tx1_data_gt;
wire pipe_tx1_elec_idle_gt;
wire [1:0] pipe_tx1_powerdown_gt;
wire [1:0] pipe_tx2_char_is_k_gt;
wire pipe_tx2_compliance_gt;
wire [15:0] pipe_tx2_data_gt;
wire pipe_tx2_elec_idle_gt;
wire [1:0] pipe_tx2_powerdown_gt;
wire [1:0] pipe_tx3_char_is_k_gt;
wire pipe_tx3_compliance_gt;
wire [15:0] pipe_tx3_data_gt;
wire pipe_tx3_elec_idle_gt;
wire [1:0] pipe_tx3_powerdown_gt;
wire [1:0] pipe_tx4_char_is_k_gt;
wire pipe_tx4_compliance_gt;
wire [15:0] pipe_tx4_data_gt;
wire pipe_tx4_elec_idle_gt;
wire [1:0] pipe_tx4_powerdown_gt;
wire [1:0] pipe_tx5_char_is_k_gt;
wire pipe_tx5_compliance_gt;
wire [15:0] pipe_tx5_data_gt;
wire pipe_tx5_elec_idle_gt;
wire [1:0] pipe_tx5_powerdown_gt;
wire [1:0] pipe_tx6_char_is_k_gt;
wire pipe_tx6_compliance_gt;
wire [15:0] pipe_tx6_data_gt;
wire pipe_tx6_elec_idle_gt;
wire [1:0] pipe_tx6_powerdown_gt;
wire [1:0] pipe_tx7_char_is_k_gt;
wire pipe_tx7_compliance_gt;
wire [15:0] pipe_tx7_data_gt;
wire pipe_tx7_elec_idle_gt;
wire [1:0] pipe_tx7_powerdown_gt;
wire pipe_rx0_chanisaligned_gt;
wire [1:0] pipe_rx0_char_is_k_gt;
wire [15:0] pipe_rx0_data_gt;
wire pipe_rx0_elec_idle_gt;
wire pipe_rx0_phy_status_gt;
wire [2:0] pipe_rx0_status_gt;
wire pipe_rx0_valid_gt;
wire pipe_rx1_chanisaligned_gt;
wire [1:0] pipe_rx1_char_is_k_gt;
wire [15:0] pipe_rx1_data_gt;
wire pipe_rx1_elec_idle_gt;
wire pipe_rx1_phy_status_gt;
wire [2:0] pipe_rx1_status_gt;
wire pipe_rx1_valid_gt;
wire pipe_rx2_chanisaligned_gt;
wire [1:0] pipe_rx2_char_is_k_gt;
wire [15:0] pipe_rx2_data_gt;
wire pipe_rx2_elec_idle_gt;
wire pipe_rx2_phy_status_gt;
wire [2:0] pipe_rx2_status_gt;
wire pipe_rx2_valid_gt;
wire pipe_rx3_chanisaligned_gt;
wire [1:0] pipe_rx3_char_is_k_gt;
wire [15:0] pipe_rx3_data_gt;
wire pipe_rx3_elec_idle_gt;
wire pipe_rx3_phy_status_gt;
wire [2:0] pipe_rx3_status_gt;
wire pipe_rx3_valid_gt;
wire pipe_rx4_chanisaligned_gt;
wire [1:0] pipe_rx4_char_is_k_gt;
wire [15:0] pipe_rx4_data_gt;
wire pipe_rx4_elec_idle_gt;
wire pipe_rx4_phy_status_gt;
wire [2:0] pipe_rx4_status_gt;
wire pipe_rx4_valid_gt;
wire pipe_rx5_chanisaligned_gt;
wire [1:0] pipe_rx5_char_is_k_gt;
wire [15:0] pipe_rx5_data_gt;
wire pipe_rx5_elec_idle_gt;
wire pipe_rx5_phy_status_gt;
wire [2:0] pipe_rx5_status_gt;
wire pipe_rx5_valid_gt;
wire pipe_rx6_chanisaligned_gt;
wire [1:0] pipe_rx6_char_is_k_gt;
wire [15:0] pipe_rx6_data_gt;
wire pipe_rx6_elec_idle_gt;
wire pipe_rx6_phy_status_gt;
wire [2:0] pipe_rx6_status_gt;
wire pipe_rx6_valid_gt;
wire pipe_rx7_chanisaligned_gt;
wire [1:0] pipe_rx7_char_is_k_gt;
wire [15:0] pipe_rx7_data_gt;
wire pipe_rx7_elec_idle_gt;
wire pipe_rx7_phy_status_gt;
wire [2:0] pipe_rx7_status_gt;
wire pipe_rx7_valid_gt;
reg user_lnk_up_int;
reg user_reset_int;
wire user_rst_n;
reg pl_received_hot_rst_q;
wire pl_received_hot_rst_wire;
reg pl_phy_lnk_up_q;
wire pl_phy_lnk_up_wire;
wire sys_or_hot_rst;
wire trn_lnk_up;
wire sys_rst_n;
wire [5:0] pl_ltssm_state_int;
localparam TCQ = 100;
// Assign outputs
assign pl_ltssm_state = pl_ltssm_state_int;
assign pl_received_hot_rst = pl_received_hot_rst_q;
assign pl_phy_lnk_up = pl_phy_lnk_up_q;
// Register block outputs pl_received_hot_rst and phy_lnk_up to ease timing on block output
assign sys_or_hot_rst = !sys_rst_n || pl_received_hot_rst_q;
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
pl_received_hot_rst_q <= #TCQ 1'b0;
pl_phy_lnk_up_q <= #TCQ 1'b0;
end else begin
pl_received_hot_rst_q <= #TCQ pl_received_hot_rst_wire;
pl_phy_lnk_up_q <= #TCQ pl_phy_lnk_up_wire;
end
end
//------------------------------------------------------------------------------------------------------------------//
// Convert incomign reset from AXI required active High //
// to active low as that is what is required by GT and PCIe Block //
//------------------------------------------------------------------------------------------------------------------//
assign sys_rst_n = ~sys_reset;
// Generate user_lnk_up
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up <= #TCQ 1'b0;
end else begin
user_lnk_up <= #TCQ user_lnk_up_int;
end
end
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up_int <= #TCQ 1'b0;
end else begin
user_lnk_up_int <= #TCQ trn_lnk_up;
end
end
//------------------------------------------------------------------------------------------------------------------//
// Generate user_reset_out //
// Once user reset output of PCIE and Phy Layer is active, de-assert reset //
// Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise //
//------------------------------------------------------------------------------------------------------------------//
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
user_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_out <= #TCQ 1'b1;
end else begin
user_reset_out <= #TCQ user_reset_int;
end
end
//------------------------------------------------------------------------------------------------------------------//
// **** PCI Express Core Wrapper **** //
// The PCI Express Core Wrapper includes the following: //
// 1) AXI Streaming Bridge //
// 2) PCIE 2_1 Hard Block //
// 3) PCIE PIPE Interface Pipeline //
//------------------------------------------------------------------------------------------------------------------//
pcie_7x_v1_3_pcie_top # (
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS ( USE_RID_PINS ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
// I/O
) pcie_top_i (
// AXI Interface
.user_clk_out ( user_clk_out ),
.user_reset ( user_reset_out ),
.user_lnk_up ( user_lnk_up ),
.user_rst_n ( user_rst_n ),
.trn_lnk_up ( trn_lnk_up ),
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cm_rst_n ( 1'b1 ),
.func_lvl_rst_n ( 1'b1 ),
.cfg_dev_id ( cfg_dev_id ),
.cfg_vend_id ( cfg_vend_id ),
.cfg_rev_id ( cfg_rev_id ),
.cfg_subsys_id ( cfg_subsys_id ),
.cfg_subsys_vend_id ( cfg_subsys_vend_id ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_bridge_serr_en ( cfg_bridge_serr_en ),
.cfg_command_bus_master_enable ( ),
.cfg_command_interrupt_disable ( ),
.cfg_command_io_enable ( ),
.cfg_command_mem_enable ( ),
.cfg_command_serr_en ( ),
.cfg_dev_control_aux_power_en ( ),
.cfg_dev_control_corr_err_reporting_en ( ),
.cfg_dev_control_enable_ro ( ),
.cfg_dev_control_ext_tag_en ( ),
.cfg_dev_control_fatal_err_reporting_en ( ),
.cfg_dev_control_max_payload ( ),
.cfg_dev_control_max_read_req ( ),
.cfg_dev_control_non_fatal_reporting_en ( ),
.cfg_dev_control_no_snoop_en ( ),
.cfg_dev_control_phantom_en ( ),
.cfg_dev_control_ur_err_reporting_en ( ),
.cfg_dev_control2_cpl_timeout_dis ( ),
.cfg_dev_control2_cpl_timeout_val ( ),
.cfg_dev_control2_ari_forward_en ( ),
.cfg_dev_control2_atomic_requester_en ( ),
.cfg_dev_control2_atomic_egress_block ( ),
.cfg_dev_control2_ido_req_en ( ),
.cfg_dev_control2_ido_cpl_en ( ),
.cfg_dev_control2_ltr_en ( ),
.cfg_dev_control2_tlp_prefix_block ( ),
.cfg_dev_status_corr_err_detected ( ),
.cfg_dev_status_fatal_err_detected ( ),
.cfg_dev_status_non_fatal_err_detected ( ),
.cfg_dev_status_ur_detected ( ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_link_control_rcb ( ),
.cfg_link_control_aspm_control ( ),
.cfg_link_control_auto_bandwidth_int_en ( ),
.cfg_link_control_bandwidth_int_en ( ),
.cfg_link_control_clock_pm_en ( ),
.cfg_link_control_common_clock ( ),
.cfg_link_control_extended_sync ( ),
.cfg_link_control_hw_auto_width_dis ( ),
.cfg_link_control_link_disable ( ),
.cfg_link_control_retrain_link ( ),
.cfg_link_status_auto_bandwidth_status ( ),
.cfg_link_status_bandwidth_status ( ),
.cfg_link_status_current_speed ( ),
.cfg_link_status_dll_active ( ),
.cfg_link_status_link_training ( ),
.cfg_link_status_negotiated_width ( ),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a ),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b ),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c ),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d ),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a ),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b ),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c ),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d ),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor ),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal ),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal ),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak ),
.cfg_msg_received_pme_to ( ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack ),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme ),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit ),
.cfg_msg_received_unlock ( ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_pm_rcv_as_req_l1_n ( ),
.cfg_pm_rcv_enter_l1_n ( ),
.cfg_pm_rcv_enter_l23_n ( ),
.cfg_pm_rcv_req_ack_n ( ),
.cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ),
.cfg_slot_control_electromech_il_ctl_pulse ( cfg_slot_control_electromech_il_ctl_pulse ),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en ),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en ),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en ),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( cfg_aer_rooterr_non_fatal_err_reporting_en ),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en ),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received ),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received ),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( ),
.cfg_transaction_addr ( ),
.cfg_transaction_type ( ),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map ),
.cfg_mgmt_byte_en_n ( ~cfg_mgmt_byte_en ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( ~cfg_err_cor ),
.cfg_err_cpl_abort_n ( ~cfg_err_cpl_abort ),
.cfg_err_cpl_timeout_n ( ~cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect_n ( ~cfg_err_cpl_unexpect ),
.cfg_err_ecrc_n ( ~cfg_err_ecrc ),
.cfg_err_locked_n ( ~cfg_err_locked ),
.cfg_err_posted_n ( ~cfg_err_posted ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( ~cfg_err_ur ),
.cfg_err_malformed_n ( ~cfg_err_malformed ),
.cfg_err_poisoned_n ( ~cfg_err_poisoned ),
.cfg_err_atomic_egress_blocked_n ( ~cfg_err_atomic_egress_blocked ),
.cfg_err_mc_blocked_n ( ~cfg_err_mc_blocked ),
.cfg_err_internal_uncor_n ( ~cfg_err_internal_uncor ),
.cfg_err_internal_cor_n ( ~cfg_err_internal_cor ),
.cfg_err_norecovery_n ( ~cfg_err_norecovery ),
.cfg_interrupt_assert_n ( ~cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( ~cfg_interrupt ),
.cfg_interrupt_stat_n ( ~cfg_interrupt_stat ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_pm_send_pme_to_n ( 1'b1 ),
.cfg_pm_wake_n ( ~cfg_pm_wake ),
.cfg_pm_halt_aspm_l0s_n ( ~cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1_n ( ~cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en_n ( ~cfg_pm_force_state_en),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( 3'b0 ),
.cfg_force_common_clock_off ( 1'b0 ),
.cfg_force_extended_sync_on ( 1'b0 ),
.cfg_port_number ( 8'b0 ),
.cfg_mgmt_rd_en_n ( ~cfg_mgmt_rd_en ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( ~cfg_mgmt_wr_en ),
.cfg_mgmt_wr_readonly_n ( ~cfg_mgmt_wr_readonly ),
.cfg_mgmt_wr_rw1c_as_rw_n ( ~cfg_mgmt_wr_rw1c_as_rw ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state_int ),
.pl_phy_lnk_up ( pl_phy_lnk_up_wire ),
.pl_received_hot_rst ( pl_received_hot_rst_wire ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( 1'b0 ),
.pl_directed_ltssm_new ( 6'b0 ),
.pl_directed_ltssm_stall ( 1'b0 ),
.pl_directed_change_done ( pl_directed_change_done ),
.phy_rdy_n ( phy_rdy_n ),
.dbg_sclr_a ( ),
.dbg_sclr_b ( ),
.dbg_sclr_c ( ),
.dbg_sclr_d ( ),
.dbg_sclr_e ( ),
.dbg_sclr_f ( ),
.dbg_sclr_g ( ),
.dbg_sclr_h ( ),
.dbg_sclr_i ( ),
.dbg_sclr_j ( ),
.dbg_sclr_k ( ),
.dbg_vec_a ( ),
.dbg_vec_b ( ),
.dbg_vec_c ( ),
.pl_dbg_vec ( ),
.trn_rdllp_data ( ),
.trn_rdllp_src_rdy ( ),
.dbg_mode ( ),
.dbg_sub_mode ( ),
.pl_dbg_mode ( ),
.drp_clk ( 1'b0 ),
.drp_do ( ),
.drp_rdy ( ),
.drp_addr ( 9'b0 ),
.drp_en ( 1'b0 ),
.drp_di ( 16'b0 ),
.drp_we ( 1'b0 ),
// Pipe Interface
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.pipe_rx0_polarity_gt ( pipe_rx0_polarity_gt ),
.pipe_rx1_polarity_gt ( pipe_rx1_polarity_gt ),
.pipe_rx2_polarity_gt ( pipe_rx2_polarity_gt ),
.pipe_rx3_polarity_gt ( pipe_rx3_polarity_gt ),
.pipe_rx4_polarity_gt ( pipe_rx4_polarity_gt ),
.pipe_rx5_polarity_gt ( pipe_rx5_polarity_gt ),
.pipe_rx6_polarity_gt ( pipe_rx6_polarity_gt ),
.pipe_rx7_polarity_gt ( pipe_rx7_polarity_gt ),
.pipe_tx_deemph_gt ( pipe_tx_deemph_gt ),
.pipe_tx_margin_gt ( pipe_tx_margin_gt ),
.pipe_tx_rate_gt ( pipe_tx_rate_gt ),
.pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det_gt ),
.pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_compliance_gt ( pipe_tx0_compliance_gt ),
.pipe_tx0_data_gt ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_gt ( pipe_tx0_powerdown_gt ),
.pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_compliance_gt ( pipe_tx1_compliance_gt ),
.pipe_tx1_data_gt ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_gt ( pipe_tx1_powerdown_gt ),
.pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_compliance_gt ( pipe_tx2_compliance_gt ),
.pipe_tx2_data_gt ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_gt ( pipe_tx2_powerdown_gt ),
.pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_compliance_gt ( pipe_tx3_compliance_gt ),
.pipe_tx3_data_gt ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_gt ( pipe_tx3_powerdown_gt ),
.pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_compliance_gt ( pipe_tx4_compliance_gt ),
.pipe_tx4_data_gt ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_gt ( pipe_tx4_powerdown_gt ),
.pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_compliance_gt ( pipe_tx5_compliance_gt ),
.pipe_tx5_data_gt ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_gt ( pipe_tx5_powerdown_gt ),
.pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_compliance_gt ( pipe_tx6_compliance_gt ),
.pipe_tx6_data_gt ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_gt ( pipe_tx6_powerdown_gt ),
.pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_compliance_gt ( pipe_tx7_compliance_gt ),
.pipe_tx7_data_gt ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_gt ( pipe_tx7_powerdown_gt ),
.pipe_rx0_chanisaligned_gt ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_gt ( pipe_rx0_data_gt ),
.pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_phy_status_gt ( pipe_rx0_phy_status_gt ),
.pipe_rx0_status_gt ( pipe_rx0_status_gt ),
.pipe_rx0_valid_gt ( pipe_rx0_valid_gt ),
.pipe_rx1_chanisaligned_gt ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_gt ( pipe_rx1_data_gt ),
.pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_phy_status_gt ( pipe_rx1_phy_status_gt ),
.pipe_rx1_status_gt ( pipe_rx1_status_gt ),
.pipe_rx1_valid_gt ( pipe_rx1_valid_gt ),
.pipe_rx2_chanisaligned_gt ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_gt ( pipe_rx2_data_gt ),
.pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_phy_status_gt ( pipe_rx2_phy_status_gt ),
.pipe_rx2_status_gt ( pipe_rx2_status_gt ),
.pipe_rx2_valid_gt ( pipe_rx2_valid_gt ),
.pipe_rx3_chanisaligned_gt ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_gt ( pipe_rx3_data_gt ),
.pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_phy_status_gt ( pipe_rx3_phy_status_gt ),
.pipe_rx3_status_gt ( pipe_rx3_status_gt ),
.pipe_rx3_valid_gt ( pipe_rx3_valid_gt ),
.pipe_rx4_chanisaligned_gt ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_gt ( pipe_rx4_data_gt ),
.pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_phy_status_gt ( pipe_rx4_phy_status_gt ),
.pipe_rx4_status_gt ( pipe_rx4_status_gt ),
.pipe_rx4_valid_gt ( pipe_rx4_valid_gt ),
.pipe_rx5_chanisaligned_gt ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_gt ( pipe_rx5_data_gt ),
.pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_phy_status_gt ( pipe_rx5_phy_status_gt ),
.pipe_rx5_status_gt ( pipe_rx5_status_gt ),
.pipe_rx5_valid_gt ( pipe_rx5_valid_gt ),
.pipe_rx6_chanisaligned_gt ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_gt ( pipe_rx6_data_gt ),
.pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_phy_status_gt ( pipe_rx6_phy_status_gt ),
.pipe_rx6_status_gt ( pipe_rx6_status_gt ),
.pipe_rx6_valid_gt ( pipe_rx6_valid_gt ),
.pipe_rx7_chanisaligned_gt ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_gt ( pipe_rx7_data_gt ),
.pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_phy_status_gt ( pipe_rx7_phy_status_gt ),
.pipe_rx7_status_gt ( pipe_rx7_status_gt ),
.pipe_rx7_valid_gt ( pipe_rx7_valid_gt )
);
//------------------------------------------------------------------------------------------------------------------//
// **** Virtex7 GTX Wrapper **** //
// The Virtex7 GTX Wrapper includes the following: //
// 1) Virtex-7 GTX //
//------------------------------------------------------------------------------------------------------------------//
pcie_7x_v1_3_gt_top #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_USE_MODE ( PCIE_USE_MODE )
) gt_top_i (
// pl ltssm
.pl_ltssm_state ( pl_ltssm_state_int ),
// Pipe Common Signals
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset ( 1'b0 ),
.pipe_tx_rate ( pipe_tx_rate_gt ),
.pipe_tx_deemph ( pipe_tx_deemph_gt ),
.pipe_tx_margin ( pipe_tx_margin_gt ),
.pipe_tx_swing ( 1'b0 ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt),
.pipe_rx0_data ( pipe_rx0_data_gt ),
.pipe_rx0_valid ( pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_status ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity ( pipe_rx0_polarity_gt ),
.pipe_tx0_compliance ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt),
.pipe_rx1_data ( pipe_rx1_data_gt ),
.pipe_rx1_valid ( pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_status ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity ( pipe_rx1_polarity_gt ),
.pipe_tx1_compliance ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt),
.pipe_rx2_data ( pipe_rx2_data_gt ),
.pipe_rx2_valid ( pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_status ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity ( pipe_rx2_polarity_gt ),
.pipe_tx2_compliance ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt),
.pipe_rx3_data ( pipe_rx3_data_gt ),
.pipe_rx3_valid ( pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_status ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity ( pipe_rx3_polarity_gt ),
.pipe_tx3_compliance ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt),
.pipe_rx4_data ( pipe_rx4_data_gt ),
.pipe_rx4_valid ( pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_status ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity ( pipe_rx4_polarity_gt ),
.pipe_tx4_compliance ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt),
.pipe_rx5_data ( pipe_rx5_data_gt ),
.pipe_rx5_valid ( pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_status ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity ( pipe_rx5_polarity_gt ),
.pipe_tx5_compliance ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt),
.pipe_rx6_data ( pipe_rx6_data_gt ),
.pipe_rx6_valid ( pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_status ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity ( pipe_rx6_polarity_gt ),
.pipe_tx6_compliance ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt),
.pipe_rx7_data ( pipe_rx7_data_gt ),
.pipe_rx7_valid ( pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_status ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity ( pipe_rx7_polarity_gt ),
.pipe_tx7_compliance ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ),
// PCI Express Signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
// Non PIPE Signals
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.phy_rdy_n ( phy_rdy_n ),
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT )
);
endmodule |
module video
// memory clock domain
(input memory_clock
,input fb_waitrequest
,input [31:0] fb_readdata
,input fb_readdatavalid
,output reg [29:0] fb_address
,output reg fb_read = 0
,output reg [31:0] vsynccnt = 0
// video clock domain
,input video_clock
,output oVGA_CLOCK
,output reg [ 9:0] oVGA_R = 0
,output reg [ 9:0] oVGA_B = 0
,output reg [ 9:0] oVGA_G = 0
,output reg oVGA_BLANK_N = 0
,output reg oVGA_HS = 0
,output reg oVGA_VS = 0
,output oVGA_SYNC_N
);
parameter FB_BEGIN = 1024*1024/4;
parameter FB_SIZE = 1024*768/4;
parameter FB_MASK = ~0;
parameter M1 = 12'd1280;
parameter M2 = 12'd1328;
parameter M3 = 12'd1440;
parameter M4 = 12'd1688;
parameter M5 = 12'd1024;
parameter M6 = 12'd1025;
parameter M7 = 12'd1028;
parameter M8 = 12'd1066;
parameter HS_NEG = 1'd0;
parameter VS_NEG = 1'd0;
// Make the counters big enough for any conceivable situation
// 13:0 -> [-2**13; 2**13-1] == [-8192;8191]
parameter MSB = 13;
wire [MSB:0] video_x0_init = M1-10'd1;
wire [MSB:0] video_x1_init = M2-10'd1;
wire [MSB:0] video_x2_init = M3-10'd1;
wire [MSB:0] video_x3_init = M4-10'd2; // Yes, -2
wire [MSB:0] video_y0_init = M5-10'd1;
wire [MSB:0] video_y1_init = M6-10'd1;
wire [MSB:0] video_y2_init = M7-10'd1;
wire [MSB:0] video_y3_init = M8-10'd2; // Yes, -2
reg [MSB:0] video_x0, video_x1, video_x2, video_x3;
reg [MSB:0] video_y0, video_y1, video_y2, video_y3;
reg video_vsync;
assign oVGA_CLOCK = video_clock;
assign oVGA_SYNC_N = 1;
reg video_fifo_read = 0;
wire [7:0] video_fifo_read_data, video_fifo_read_data_really;
wire video_fifo_empty;
reg vsync_ = 1'd0;
wire fifo_write = fb_readdatavalid;
wire [31:0] fifo_write_data = fb_readdata;
wire fifo_full;
wire [6:0] fifo_used;
reg [24:0] vsync_count_down = 0;
reg vsync = 1'd0, vsync_next = 1'd0;
always @(posedge memory_clock) vsync_next <= video_vsync; // Clock domain crossing!
always @(posedge memory_clock) vsync <= vsync_next;
always @(posedge memory_clock) vsync_ <= vsync;
video_fifo video_fifo_inst
// Memory domain
(.wrclk (memory_clock)
,.wrreq (fifo_write)
// Argh, Quartus FIFO assumes little endian
,.data ({fifo_write_data[7:0],fifo_write_data[15:8],fifo_write_data[23:16],fifo_write_data[31:24]})
,.aclr (vsync)
,.wrfull (fifo_full)
,.wrusedw(fifo_used)
// Video domain
,.rdclk (video_clock)
,.rdreq (video_fifo_read)
,.q (video_fifo_read_data)
,.rdempty(video_fifo_empty)
);
// Pixel DMA - memory domain
// Pixel pump (really: very simply master that issues reads to the frame buffer)
reg [29:0] next = 1'd0;
always @(posedge memory_clock) begin
if (!fb_waitrequest) begin
fb_read <= 0;
if (vsync & !vsync_) begin
next <= FB_BEGIN;
vsync_count_down <= FB_SIZE - 2;
end else if (!vsync & !fifo_full & !fifo_used[5]) begin
fb_read <= 1;
fb_address <= next;
next <= (next + 4) & FB_MASK; // useful for looping around
end
end
// Crap, this doesn't appear to work at all!
if (vsync_count_down[24]) begin
vsynccnt <= vsynccnt + 1;
vsync_count_down <= FB_SIZE - 2;
end else
vsync_count_down <= vsync_count_down - 1;
end
// Video generation - dot clock domain
always @(posedge video_clock) begin
// Sadly we can only (barely) afford 8 bits pr pixel
// Pack as RGB332 / RRRGGGBB (the eye is least sensive to blue apparently)
// XXX spend the 7680 bytes and add a palette
// v * (1023 / 7)
case (video_fifo_read_data[7:5])
0: oVGA_R <= 10'd0;
1: oVGA_R <= 10'd146;
2: oVGA_R <= 10'd292;
3: oVGA_R <= 10'd438;
4: oVGA_R <= 10'd585;
5: oVGA_R <= 10'd732;
6: oVGA_R <= 10'd877;
7: oVGA_R <= 10'd1023;
endcase
case (video_fifo_read_data[4:2])
0: oVGA_G <= 10'd0;
1: oVGA_G <= 10'd146;
2: oVGA_G <= 10'd292;
3: oVGA_G <= 10'd438;
4: oVGA_G <= 10'd585;
5: oVGA_G <= 10'd732;
6: oVGA_G <= 10'd877;
7: oVGA_G <= 10'd1023;
endcase
// v * (1023 / 3)
case (video_fifo_read_data[1:0])
0: oVGA_B <= 10'd0;
1: oVGA_B <= 10'd341;
2: oVGA_B <= 10'd682;
3: oVGA_B <= 10'd1023;
endcase
// Hacks below to provide reference point
`ifdef HACK
if (video_x0 == video_x0_init || video_x0 == 0 || video_y0 == video_y0_init || video_y0 == 0)
{oVGA_R[9:2], oVGA_G[9:2], oVGA_B[9:2]} <= 24'hFFFFFF; // White frame
else if (video_x0 == video_y0)
{oVGA_R[9:2], oVGA_G[9:2], oVGA_B[9:2]} <= 24'h0000FF; // Blue lineppp
`endif
if (video_fifo_empty)
{oVGA_R,oVGA_G,oVGA_B} <= {10'h3FF,10'd0,10'd0}; // RED!
oVGA_BLANK_N <= ~(video_x0[MSB] | video_y0[MSB]);
oVGA_HS <= HS_NEG ^ video_x1[MSB] ^ video_x2[MSB];
oVGA_VS <= VS_NEG ^ video_y1[MSB] ^ video_y2[MSB];
video_vsync <= video_y1[MSB] ^ video_y2[MSB];
video_fifo_read <= ~(video_x0[MSB] | video_y0[MSB]);
if (!video_x3[MSB]) begin
video_x0 <= video_x0 - 1'd1;
video_x1 <= video_x1 - 1'd1;
video_x2 <= video_x2 - 1'd1;
video_x3 <= video_x3 - 1'd1;
end else begin
video_x0 <= video_x0_init;
video_x1 <= video_x1_init;
video_x2 <= video_x2_init;
video_x3 <= video_x3_init;
if (!video_y3[MSB]) begin
video_y0 <= video_y0 - 1'd1;
video_y1 <= video_y1 - 1'd1;
video_y2 <= video_y2 - 1'd1;
video_y3 <= video_y3 - 1'd1;
end else begin
video_y0 <= video_y0_init;
video_y1 <= video_y1_init;
video_y2 <= video_y2_init;
video_y3 <= video_y3_init;
end
end
end
endmodule |
module pm_clk_real(
input clk,
input rst,
input real_speed,
input rst_counter,
input irq_n, // the pm counter does not count when irq_n is low
input uart_speed,
output reg ym_pm,
output reg [31:0] pm_counter
);
parameter stop=5'd07;
reg [4:0] div_cnt, cambio0, cambio1;
always @(posedge clk or posedge rst) begin : speed_mux
if( rst ) begin
cambio0 <= 5'd2;
cambio1 <= 5'd4;
end
else begin
if( real_speed ) begin
cambio0 <= 5'd2;
cambio1 <= 5'd4;
end
else begin // con 8/16 he visto fallar el STATUS del YM una vez
if( uart_speed ) begin
cambio0 <= 5'd4;
cambio1 <= 5'd8;
end else begin
cambio0 <= 5'd7;
cambio1 <= 5'd15;
end
end
end
end
always @(posedge clk or posedge rst) begin : ym_pm_ff
if( rst ) begin
div_cnt <= 5'd0;
ym_pm <= 1'b0;
end
else begin
if(div_cnt>=cambio1) begin // =5'd4 tiempo real del YM
ym_pm <= 1'b1;
div_cnt <= 5'd0;
end
else begin
if( div_cnt==cambio0 ) ym_pm <= 1'b0; // =5'd2 tiempo real
div_cnt <= div_cnt + 1'b1;
end
end
end
reg ultpm;
always @(posedge clk or posedge rst) begin : pm_counter_ff
if( rst ) begin
pm_counter <= 32'd0;
ultpm <= 1'b0;
end
else begin
ultpm <= ym_pm;
if(rst_counter)
pm_counter <= 32'd0;
else
if( irq_n && ym_pm && !ultpm )
pm_counter <= pm_counter + 1'd1;
end
end
endmodule |
module sky130_fd_sc_hd__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module udp_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* UDP frame inputs
*/
input wire [S_COUNT-1:0] s_udp_hdr_valid,
output wire [S_COUNT-1:0] s_udp_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*4-1:0] s_ip_version,
input wire [S_COUNT*4-1:0] s_ip_ihl,
input wire [S_COUNT*6-1:0] s_ip_dscp,
input wire [S_COUNT*2-1:0] s_ip_ecn,
input wire [S_COUNT*16-1:0] s_ip_length,
input wire [S_COUNT*16-1:0] s_ip_identification,
input wire [S_COUNT*3-1:0] s_ip_flags,
input wire [S_COUNT*13-1:0] s_ip_fragment_offset,
input wire [S_COUNT*8-1:0] s_ip_ttl,
input wire [S_COUNT*8-1:0] s_ip_protocol,
input wire [S_COUNT*16-1:0] s_ip_header_checksum,
input wire [S_COUNT*32-1:0] s_ip_source_ip,
input wire [S_COUNT*32-1:0] s_ip_dest_ip,
input wire [S_COUNT*16-1:0] s_udp_source_port,
input wire [S_COUNT*16-1:0] s_udp_dest_port,
input wire [S_COUNT*16-1:0] s_udp_length,
input wire [S_COUNT*16-1:0] s_udp_checksum,
input wire [S_COUNT*DATA_WIDTH-1:0] s_udp_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_udp_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_udp_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_udp_payload_axis_tready,
input wire [S_COUNT-1:0] s_udp_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_udp_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_udp_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_udp_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [DATA_WIDTH-1:0] m_udp_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_udp_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_udp_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_udp_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_udp_hdr_ready_reg = 0, s_udp_hdr_ready_next;
reg [S_COUNT-1:0] s_udp_payload_axis_tready_reg = 0, s_udp_payload_axis_tready_next;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg [3:0] m_ip_version_reg = 4'd0, m_ip_version_next;
reg [3:0] m_ip_ihl_reg = 4'd0, m_ip_ihl_next;
reg [5:0] m_ip_dscp_reg = 6'd0, m_ip_dscp_next;
reg [1:0] m_ip_ecn_reg = 2'd0, m_ip_ecn_next;
reg [15:0] m_ip_length_reg = 16'd0, m_ip_length_next;
reg [15:0] m_ip_identification_reg = 16'd0, m_ip_identification_next;
reg [2:0] m_ip_flags_reg = 3'd0, m_ip_flags_next;
reg [12:0] m_ip_fragment_offset_reg = 13'd0, m_ip_fragment_offset_next;
reg [7:0] m_ip_ttl_reg = 8'd0, m_ip_ttl_next;
reg [7:0] m_ip_protocol_reg = 8'd0, m_ip_protocol_next;
reg [15:0] m_ip_header_checksum_reg = 16'd0, m_ip_header_checksum_next;
reg [31:0] m_ip_source_ip_reg = 32'd0, m_ip_source_ip_next;
reg [31:0] m_ip_dest_ip_reg = 32'd0, m_ip_dest_ip_next;
reg [15:0] m_udp_source_port_reg = 16'd0, m_udp_source_port_next;
reg [15:0] m_udp_dest_port_reg = 16'd0, m_udp_dest_port_next;
reg [15:0] m_udp_length_reg = 16'd0, m_udp_length_next;
reg [15:0] m_udp_checksum_reg = 16'd0, m_udp_checksum_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_udp_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep_int;
reg m_udp_payload_axis_tvalid_int;
reg m_udp_payload_axis_tready_int_reg = 1'b0;
reg m_udp_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_udp_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_udp_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_udp_payload_axis_tuser_int;
wire m_udp_payload_axis_tready_int_early;
assign s_udp_hdr_ready = s_udp_hdr_ready_reg;
assign s_udp_payload_axis_tready = s_udp_payload_axis_tready_reg;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_udp_payload_axis_tdata[select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_udp_payload_axis_tkeep[select_reg*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_udp_payload_axis_tvalid[select_reg];
wire current_s_tready = s_udp_payload_axis_tready[select_reg];
wire current_s_tlast = s_udp_payload_axis_tlast[select_reg];
wire [ID_WIDTH-1:0] current_s_tid = s_udp_payload_axis_tid[select_reg*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_udp_payload_axis_tdest[select_reg*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_udp_payload_axis_tuser[select_reg*USER_WIDTH +: USER_WIDTH];
always @* begin
select_next = select_reg;
frame_next = frame_reg;
s_udp_hdr_ready_next = 0;
s_udp_payload_axis_tready_next = 0;
m_udp_hdr_valid_next = m_udp_hdr_valid_reg && !m_udp_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
m_ip_version_next = m_ip_version_reg;
m_ip_ihl_next = m_ip_ihl_reg;
m_ip_dscp_next = m_ip_dscp_reg;
m_ip_ecn_next = m_ip_ecn_reg;
m_ip_length_next = m_ip_length_reg;
m_ip_identification_next = m_ip_identification_reg;
m_ip_flags_next = m_ip_flags_reg;
m_ip_fragment_offset_next = m_ip_fragment_offset_reg;
m_ip_ttl_next = m_ip_ttl_reg;
m_ip_protocol_next = m_ip_protocol_reg;
m_ip_header_checksum_next = m_ip_header_checksum_reg;
m_ip_source_ip_next = m_ip_source_ip_reg;
m_ip_dest_ip_next = m_ip_dest_ip_reg;
m_udp_source_port_next = m_udp_source_port_reg;
m_udp_dest_port_next = m_udp_dest_port_reg;
m_udp_length_next = m_udp_length_reg;
m_udp_checksum_next = m_udp_checksum_reg;
if (current_s_tvalid & current_s_tready) begin
// end of frame detection
if (current_s_tlast) begin
frame_next = 1'b0;
end
end
if (!frame_reg && enable && !m_udp_hdr_valid && (s_udp_hdr_valid & (1 << select))) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
s_udp_hdr_ready_next = (1 << select);
m_udp_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[select*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[select*48 +: 48];
m_eth_type_next = s_eth_type[select*16 +: 16];
m_ip_version_next = s_ip_version[select*4 +: 4];
m_ip_ihl_next = s_ip_ihl[select*4 +: 4];
m_ip_dscp_next = s_ip_dscp[select*6 +: 6];
m_ip_ecn_next = s_ip_ecn[select*2 +: 2];
m_ip_length_next = s_ip_length[select*16 +: 16];
m_ip_identification_next = s_ip_identification[select*16 +: 16];
m_ip_flags_next = s_ip_flags[select*3 +: 3];
m_ip_fragment_offset_next = s_ip_fragment_offset[select*13 +: 13];
m_ip_ttl_next = s_ip_ttl[select*8 +: 8];
m_ip_protocol_next = s_ip_protocol[select*8 +: 8];
m_ip_header_checksum_next = s_ip_header_checksum[select*16 +: 16];
m_ip_source_ip_next = s_ip_source_ip[select*32 +: 32];
m_ip_dest_ip_next = s_ip_dest_ip[select*32 +: 32];
m_udp_source_port_next = s_udp_source_port[select*16 +: 16];
m_udp_dest_port_next = s_udp_dest_port[select*16 +: 16];
m_udp_length_next = s_udp_length[select*16 +: 16];
m_udp_checksum_next = s_udp_checksum[select*16 +: 16];
end
// generate ready signal on selected port
s_udp_payload_axis_tready_next = (m_udp_payload_axis_tready_int_early && frame_next) << select_next;
// pass through selected packet data
m_udp_payload_axis_tdata_int = current_s_tdata;
m_udp_payload_axis_tkeep_int = current_s_tkeep;
m_udp_payload_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
m_udp_payload_axis_tlast_int = current_s_tlast;
m_udp_payload_axis_tid_int = current_s_tid;
m_udp_payload_axis_tdest_int = current_s_tdest;
m_udp_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 1'b0;
s_udp_hdr_ready_reg <= 0;
s_udp_payload_axis_tready_reg <= 0;
m_udp_hdr_valid_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
s_udp_hdr_ready_reg <= s_udp_hdr_ready_next;
s_udp_payload_axis_tready_reg <= s_udp_payload_axis_tready_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
m_ip_version_reg <= m_ip_version_next;
m_ip_ihl_reg <= m_ip_ihl_next;
m_ip_dscp_reg <= m_ip_dscp_next;
m_ip_ecn_reg <= m_ip_ecn_next;
m_ip_length_reg <= m_ip_length_next;
m_ip_identification_reg <= m_ip_identification_next;
m_ip_flags_reg <= m_ip_flags_next;
m_ip_fragment_offset_reg <= m_ip_fragment_offset_next;
m_ip_ttl_reg <= m_ip_ttl_next;
m_ip_protocol_reg <= m_ip_protocol_next;
m_ip_header_checksum_reg <= m_ip_header_checksum_next;
m_ip_source_ip_reg <= m_ip_source_ip_next;
m_ip_dest_ip_reg <= m_ip_dest_ip_next;
m_udp_source_port_reg <= m_udp_source_port_next;
m_udp_dest_port_reg <= m_udp_dest_port_next;
m_udp_length_reg <= m_udp_length_next;
m_udp_checksum_reg <= m_udp_checksum_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_udp_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_udp_payload_axis_tvalid_reg = 1'b0, m_udp_payload_axis_tvalid_next;
reg m_udp_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_udp_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_udp_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_udp_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_udp_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_udp_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_udp_payload_axis_tvalid_reg = 1'b0, temp_m_udp_payload_axis_tvalid_next;
reg temp_m_udp_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_udp_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_udp_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_udp_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_udp_payload_axis_tdata = m_udp_payload_axis_tdata_reg;
assign m_udp_payload_axis_tkeep = KEEP_ENABLE ? m_udp_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
assign m_udp_payload_axis_tid = ID_ENABLE ? m_udp_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_udp_payload_axis_tdest = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_udp_payload_axis_tuser = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_udp_payload_axis_tready_int_reg) begin
// input is ready
if (m_udp_payload_axis_tready || !m_udp_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_udp_payload_axis_tready) begin
// input is not ready, but output is ready
m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_udp_payload_axis_tvalid_reg <= 1'b0;
m_udp_payload_axis_tready_int_reg <= 1'b0;
temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
m_udp_payload_axis_tid_reg <= m_udp_payload_axis_tid_int;
m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_udp_payload_axis_tdata_reg <= temp_m_udp_payload_axis_tdata_reg;
m_udp_payload_axis_tkeep_reg <= temp_m_udp_payload_axis_tkeep_reg;
m_udp_payload_axis_tlast_reg <= temp_m_udp_payload_axis_tlast_reg;
m_udp_payload_axis_tid_reg <= temp_m_udp_payload_axis_tid_reg;
m_udp_payload_axis_tdest_reg <= temp_m_udp_payload_axis_tdest_reg;
m_udp_payload_axis_tuser_reg <= temp_m_udp_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
temp_m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
temp_m_udp_payload_axis_tid_reg <= m_udp_payload_axis_tid_int;
temp_m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end
end
endmodule |
module nonrestore_div #(
parameter NUMERATOR_WIDTH = 64,
parameter DENOMINATOR_WIDTH = 64
)(
input clk,
input clr,
input [NUMERATOR_WIDTH - 1 : 0] numer_in,
input [DENOMINATOR_WIDTH - 1 : 0] denom_in,
output reg [NUMERATOR_WIDTH - 1 : 0] quot_out,
output reg [DENOMINATOR_WIDTH - 1 : 0] rem_out,
output reg rdy_out
);
localparam s0 = 4'b0001;
localparam s1 = 4'b0010;
localparam s2 = 4'b0100;
localparam s3 = 4'b1000;
localparam TMPVAR_WIDTH = NUMERATOR_WIDTH + DENOMINATOR_WIDTH;
localparam REM_ITER_MSB = DENOMINATOR_WIDTH;
localparam QUOT_MSB = NUMERATOR_WIDTH - 1;
reg [3 : 0] state;
reg [NUMERATOR_WIDTH - 1 : 0] numer;
reg [DENOMINATOR_WIDTH - 1 : 0] denom;
reg [DENOMINATOR_WIDTH : 0] denom_neg;
reg [NUMERATOR_WIDTH - 1 : 0] quot;
reg [DENOMINATOR_WIDTH - 1 : 0] rem;
reg [DENOMINATOR_WIDTH : 0] rem_iter;
reg [7 : 0] count;
wire [DENOMINATOR_WIDTH : 0] rem_iter_shift;
wire [NUMERATOR_WIDTH - 1 : 0] quot_shift;
wire [DENOMINATOR_WIDTH : 0] rem_iter_sum;
assign {rem_iter_shift, quot_shift} = {rem_iter, quot} << 1;
assign rem_iter_sum = rem_iter_shift + (rem_iter[REM_ITER_MSB]) ? denom : denom_neg;
always @ (posedge clk or posedge clr)
begin
if (clr) begin
state <= s0;
rdy_out <= 1'b0;
numer <= 0;
denom <= 0;
denom_neg <= 0;
quot <= 0;
rem_iter <= 0;
rem <= 0;
count <= 0;
end
else begin
case (state)
s0 : begin
numer <= numer_in;
denom <= denom_in;
denom_neg <= {1'b1,~denom_in} + 1;
quot <= numer_in;
rem_iter <= 0;
count <= 0;
state <= s1;
end
s1 : begin
count <= count + 1;
quot[QUOT_MSB : 1] <= quot_shift[QUOT_MSB : 1];
rem_iter <= rem_iter_sum;
if (rem_iter_sum[REM_ITER_MSB]) begin
quot[0] <= 0;
end
else begin
quot[0] <= 1;
end
if (count == NUMERATOR_WIDTH - 1) begin
state <= s2;
end
end
s2 : begin
if (rem_iter[REM_ITER_MSB]) begin // rem < 0
rem <= rem_iter + denom;
end
else begin
rem <= rem_iter;
end
state <= s3;
end
s3 : begin
quot_out <= quot;
rem_out <= rem;
rdy_out <= 1'b1;
end
default : begin
state <= s0;
end
endcase
end
end
endmodule |
module sky130_fd_sc_ls__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module sky130_fd_sc_hs__and4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule |
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module altera_onchip_flash (
// To/From System
clock,
reset_n,
// To/From Avalon_MM data slave interface
avmm_data_read,
avmm_data_write,
avmm_data_addr,
avmm_data_writedata,
avmm_data_burstcount,
avmm_data_waitrequest,
avmm_data_readdatavalid,
avmm_data_readdata,
// To/From Avalon_MM csr slave interface
avmm_csr_read,
avmm_csr_write,
avmm_csr_addr,
avmm_csr_writedata,
avmm_csr_readdata
);
parameter DEVICE_FAMILY = "MAX 10";
parameter PART_NAME = "Unknown";
parameter IS_DUAL_BOOT = "False";
parameter IS_ERAM_SKIP = "False";
parameter IS_COMPRESSED_IMAGE = "False";
parameter INIT_FILENAME = "";
// simulation only start
parameter DEVICE_ID = "08";
parameter INIT_FILENAME_SIM = "";
// simulation only end
parameter PARALLEL_MODE = 0;
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter AVMM_CSR_DATA_WIDTH = 32;
parameter AVMM_DATA_DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 13;
parameter FLASH_DATA_WIDTH = 32;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read. only need in parallel mode.
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read. only need in parallel mode.
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment. only need in parallel mode.
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (960ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter MIN_UFM_VALID_ADDR = 1;
parameter MAX_UFM_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
// To/From System
input clock;
input reset_n;
// To/From Avalon_MM data slave interface
input avmm_data_read;
input avmm_data_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_data_addr;
input [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_data_burstcount;
output avmm_data_waitrequest;
output avmm_data_readdatavalid;
output [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata;
// To/From Avalon_MM csr slave interface
input avmm_csr_read;
input avmm_csr_write;
input avmm_csr_addr;
input [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_writedata;
output [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata;
wire [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata_wire;
wire [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata_wire;
wire [31:0] csr_control_wire;
wire [9:0] csr_status_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_ardin_wire;
wire [FLASH_DATA_WIDTH-1:0] flash_drdout_wire;
wire flash_busy;
wire flash_se_pass;
wire flash_sp_pass;
wire flash_osc;
wire flash_xe_ye;
wire flash_se;
wire flash_arclk;
wire flash_arshft;
wire flash_drclk;
wire flash_drshft;
wire flash_drdin;
wire flash_nprogram;
wire flash_nerase;
wire flash_par_en;
wire flash_xe_ye_wire;
wire flash_se_wire;
assign avmm_data_readdata = avmm_data_readdata_wire;
generate
if (READ_AND_WRITE_MODE == 0) begin
assign avmm_csr_readdata = 32'hffffffff;
assign csr_control_wire = 32'h3fffffff;
end
else begin
assign avmm_csr_readdata = avmm_csr_readdata_wire;
end
endgenerate
generate
if (DEVICE_ID == "02" || DEVICE_ID == "01") begin
assign flash_par_en = 1'b1;
assign flash_xe_ye = 1'b1;
assign flash_se = 1'b1;
end
else begin
assign flash_par_en = PARALLEL_MODE[0];
assign flash_xe_ye = flash_xe_ye_wire;
assign flash_se = flash_se_wire;
end
endgenerate
generate
if (READ_AND_WRITE_MODE) begin
// -------------------------------------------------------------------
// Instantiate a Avalon_MM csr slave controller
// -------------------------------------------------------------------
altera_onchip_flash_avmm_csr_controller avmm_csr_controller (
// To/From System
.clock(clock),
.reset_n(reset_n),
// To/From Avalon_MM csr slave interface
.avmm_read(avmm_csr_read),
.avmm_write(avmm_csr_write),
.avmm_addr(avmm_csr_addr),
.avmm_writedata(avmm_csr_writedata),
.avmm_readdata(avmm_csr_readdata_wire),
// To/From Avalon_MM data slave interface
.csr_control(csr_control_wire),
.csr_status(csr_status_wire)
);
end
endgenerate
// -------------------------------------------------------------------
// Instantiate a Avalon_MM data slave controller
// -------------------------------------------------------------------
altera_onchip_flash_avmm_data_controller # (
.READ_AND_WRITE_MODE (READ_AND_WRITE_MODE),
.WRAPPING_BURST_MODE (WRAPPING_BURST_MODE),
.AVMM_DATA_ADDR_WIDTH (AVMM_DATA_ADDR_WIDTH),
.AVMM_DATA_BURSTCOUNT_WIDTH (AVMM_DATA_BURSTCOUNT_WIDTH),
.FLASH_SEQ_READ_DATA_COUNT (FLASH_SEQ_READ_DATA_COUNT),
.FLASH_READ_CYCLE_MAX_INDEX (FLASH_READ_CYCLE_MAX_INDEX),
.FLASH_ADDR_ALIGNMENT_BITS (FLASH_ADDR_ALIGNMENT_BITS),
.FLASH_RESET_CYCLE_MAX_INDEX (FLASH_RESET_CYCLE_MAX_INDEX),
.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX (FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX),
.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX),
.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX),
.MIN_VALID_ADDR (MIN_VALID_ADDR),
.MAX_VALID_ADDR (MAX_VALID_ADDR),
.SECTOR1_START_ADDR (SECTOR1_START_ADDR),
.SECTOR1_END_ADDR (SECTOR1_END_ADDR),
.SECTOR2_START_ADDR (SECTOR2_START_ADDR),
.SECTOR2_END_ADDR (SECTOR2_END_ADDR),
.SECTOR3_START_ADDR (SECTOR3_START_ADDR),
.SECTOR3_END_ADDR (SECTOR3_END_ADDR),
.SECTOR4_START_ADDR (SECTOR4_START_ADDR),
.SECTOR4_END_ADDR (SECTOR4_END_ADDR),
.SECTOR5_START_ADDR (SECTOR5_START_ADDR),
.SECTOR5_END_ADDR (SECTOR5_END_ADDR),
.SECTOR_READ_PROTECTION_MODE (SECTOR_READ_PROTECTION_MODE),
.SECTOR1_MAP (SECTOR1_MAP),
.SECTOR2_MAP (SECTOR2_MAP),
.SECTOR3_MAP (SECTOR3_MAP),
.SECTOR4_MAP (SECTOR4_MAP),
.SECTOR5_MAP (SECTOR5_MAP),
.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET)
) avmm_data_controller (
// To/From System
.clock(clock),
.reset_n(reset_n),
// To/From Flash IP interface
.flash_busy(flash_busy),
.flash_se_pass(flash_se_pass),
.flash_sp_pass(flash_sp_pass),
.flash_osc(flash_osc),
.flash_drdout(flash_drdout_wire),
.flash_xe_ye(flash_xe_ye_wire),
.flash_se(flash_se_wire),
.flash_arclk(flash_arclk),
.flash_arshft(flash_arshft),
.flash_drclk(flash_drclk),
.flash_drshft(flash_drshft),
.flash_drdin(flash_drdin),
.flash_nprogram(flash_nprogram),
.flash_nerase(flash_nerase),
.flash_ardin(flash_ardin_wire),
// To/From Avalon_MM data slave interface
.avmm_read(avmm_data_read),
.avmm_write(avmm_data_write),
.avmm_addr(avmm_data_addr),
.avmm_writedata(avmm_data_writedata),
.avmm_burstcount(avmm_data_burstcount),
.avmm_waitrequest(avmm_data_waitrequest),
.avmm_readdatavalid(avmm_data_readdatavalid),
.avmm_readdata(avmm_data_readdata_wire),
// To/From Avalon_MM csr slave interface
.csr_control(csr_control_wire),
.csr_status(csr_status_wire)
);
// -------------------------------------------------------------------
// Instantiate wysiwyg for onchip flash block
// -------------------------------------------------------------------
altera_onchip_flash_block # (
.DEVICE_FAMILY (DEVICE_FAMILY),
.PART_NAME (PART_NAME),
.IS_DUAL_BOOT (IS_DUAL_BOOT),
.IS_ERAM_SKIP (IS_ERAM_SKIP),
.IS_COMPRESSED_IMAGE (IS_COMPRESSED_IMAGE),
.INIT_FILENAME (INIT_FILENAME),
.MIN_VALID_ADDR (MIN_VALID_ADDR),
.MAX_VALID_ADDR (MAX_VALID_ADDR),
.MIN_UFM_VALID_ADDR (MIN_UFM_VALID_ADDR),
.MAX_UFM_VALID_ADDR (MAX_UFM_VALID_ADDR),
.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET),
// simulation only start
.DEVICE_ID (DEVICE_ID),
.INIT_FILENAME_SIM (INIT_FILENAME_SIM)
// simulation only end
) altera_onchip_flash_block (
.xe_ye(flash_xe_ye),
.se(flash_se),
.arclk(flash_arclk),
.arshft(flash_arshft),
.ardin(flash_ardin_wire),
.drclk(flash_drclk),
.drshft(flash_drshft),
.drdin(flash_drdin),
.nprogram(flash_nprogram),
.nerase(flash_nerase),
.nosc_ena(1'b0),
.par_en(flash_par_en),
.drdout(flash_drdout_wire),
.busy(flash_busy),
.se_pass(flash_se_pass),
.sp_pass(flash_sp_pass),
.osc(flash_osc)
);
endmodule |
module serdes_test #
(
parameter DATA_WIDTH = 8,
parameter DATA_RATE = "DDR"
)
(
input wire SYSCLK,
input wire CLKDIV,
input wire RST,
input wire I_DAT,
output wire O_DAT,
output wire T_DAT,
input wire [7:0] INPUTS,
output wire [7:0] OUTPUTS
);
// ============================================================================
// CLKDIV generation using a BUFR
wire i_rstdiv;
// ISERDES reset generator
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLKDIV)
if (RST) rst_sr <= 4'hF;
else rst_sr <= rst_sr >> 1;
assign i_rstdiv = rst_sr[0];
// OSERDES
OSERDESE2 #(
.DATA_RATE_OQ (DATA_RATE),
.DATA_WIDTH (DATA_WIDTH),
.DATA_RATE_TQ ((DATA_RATE == "DDR" && DATA_WIDTH == 4) ? "DDR" : "BUF"),
.TRISTATE_WIDTH ((DATA_RATE == "DDR" && DATA_WIDTH == 4) ? 4 : 1)
)
oserdes
(
.CLK (SYSCLK),
.CLKDIV (CLKDIV),
.RST (i_rstdiv),
.OCE (1'b1),
.D1 (INPUTS[0]),
.D2 (INPUTS[1]),
.D3 (INPUTS[2]),
.D4 (INPUTS[3]),
.D5 (INPUTS[4]),
.D6 (INPUTS[5]),
.D7 (INPUTS[6]),
.D8 (INPUTS[7]),
.OQ (O_DAT),
.TCE (1'b1),
.T1 (1'b0), // All 0 to keep OBUFT always on.
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TQ (T_DAT)
);
// ============================================================================
// ISERDES
ISERDESE2 #
(
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (DATA_WIDTH),
.INTERFACE_TYPE ("NETWORKING"),
.NUM_CE (2)
)
iserdes
(
.CLK (SYSCLK),
.CLKB (SYSCLK),
.CLKDIV (CLKDIV),
.CE1 (1'b1),
.CE2 (1'b1),
.RST (i_rstdiv),
.D (I_DAT),
.Q1 (OUTPUTS[7]),
.Q2 (OUTPUTS[6]),
.Q3 (OUTPUTS[5]),
.Q4 (OUTPUTS[4]),
.Q5 (OUTPUTS[3]),
.Q6 (OUTPUTS[2]),
.Q7 (OUTPUTS[1]),
.Q8 (OUTPUTS[0])
);
endmodule |
module flt_fx_uv
(
input clk,
input [31:0] float,
output reg [31:0] fixed_out
);
reg [31:0] fixed;
wire [30:0] fixed_pos;
reg [30:0] fixed_pos_bar;
wire [31:0] fixed_pos_2;
wire [31:0] fixed_pos_3;
wire [8:0] shift;
wire big,tiny;
wire cin;
reg cin_bar;
wire cout;
reg neg_ovfl_mask;
/*
* Rounding accomplished as follows:
* b = a + r
* -b = -(a + r)
* -b = -a -r
* -b = ~a +1 -r
* -b = ~a + (1-r)
* but 1-r = ~r, when r is one bit, so...
* -b = ~a + ~r
*/
/*
* determine amount to shift mantissa, and if this float fits into 23.9TC
* note: h7e+h22=h94
*/
assign shift = 8'h94 - float[30:23];
assign big = shift[8];
assign tiny = |(shift[7:5]);
/*
* shift the mantissa
*/
assign {fixed_pos, cin} = lsr32({1'b1, float[22:0],8'b0}, shift[4:0]);
/*
* round the result, and convert to two's complement
*/
always @(fixed_pos or cin or big or tiny or float) begin
cin_bar = ~cin;
fixed_pos_bar = ~fixed_pos;
casex ({float[31],big,tiny}) /* synopsys full_case parallel_case */
3'b000: begin // positive, in range
fixed = fixed_pos + cin;
if (fixed[31])
fixed = 32'h7fffffff;
end // case: 3'b000
3'b100: begin // negative, in range
fixed = fixed_pos_bar + cin_bar;
fixed[31] = ~fixed[31];
end // case: 3'b100
3'b01x: // positive big
fixed = 32'h7fffffff;
3'b11x: // negative big
fixed = 32'h80000000;
3'bxx1: // tiny
fixed = 32'h0;
endcase // casex ({float[31],big,tiny})
end // always @ (fixed_pos or cin or big or tiny or float)
always @(posedge clk) fixed_out <= fixed;
function [31:0] lsr32;
// shift a 32-bit input vector to the right, by 0 to 31 places.
// fill in zeros's from the left
input [31:0] a;
input [4:0] s;
reg [4:0] s1;
reg [31:0] a1;
reg [31:0] a2;
reg [31:0] a4;
reg [31:0] a8;
reg [31:0] a16;
begin
if (s[0])
a1 = {1'b0, a[31:1]};
else
a1 = a;
if (s[1])
a2 = {{2{1'b0}}, a1[31:2]};
else
a2 = a1;
if (s[2])
a4 = {{4{1'b0}}, a2[31:4]};
else
a4 = a2;
if (s[3])
a8 = {{8{1'b0}}, a4[31:8]};
else
a8 = a4;
if (s[4])
a16 = {{16{1'b0}}, a8[31:16]};
else
a16 = a8;
lsr32 = a16;
end
endfunction // lsr32
endmodule |
module wasca (
altpll_0_areset_conduit_export,
altpll_0_locked_conduit_export,
altpll_0_phasedone_conduit_export,
clk_clk,
clock_116_mhz_clk,
external_sdram_controller_wire_addr,
external_sdram_controller_wire_ba,
external_sdram_controller_wire_cas_n,
external_sdram_controller_wire_cke,
external_sdram_controller_wire_cs_n,
external_sdram_controller_wire_dq,
external_sdram_controller_wire_dqm,
external_sdram_controller_wire_ras_n,
external_sdram_controller_wire_we_n,
sega_saturn_abus_slave_0_abus_address,
sega_saturn_abus_slave_0_abus_chipselect,
sega_saturn_abus_slave_0_abus_read,
sega_saturn_abus_slave_0_abus_write,
sega_saturn_abus_slave_0_abus_waitrequest,
sega_saturn_abus_slave_0_abus_interrupt,
sega_saturn_abus_slave_0_abus_addressdata,
sega_saturn_abus_slave_0_abus_direction,
sega_saturn_abus_slave_0_abus_muxing,
sega_saturn_abus_slave_0_abus_disableout,
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset,
spi_sd_card_MISO,
spi_sd_card_MOSI,
spi_sd_card_SCLK,
spi_sd_card_SS_n,
uart_0_external_connection_rxd,
uart_0_external_connection_txd,
spi_stm32_MISO,
spi_stm32_MOSI,
spi_stm32_SCLK,
spi_stm32_SS_n,
audio_out_BCLK,
audio_out_DACDAT,
audio_out_DACLRCK);
input altpll_0_areset_conduit_export;
output altpll_0_locked_conduit_export;
output altpll_0_phasedone_conduit_export;
input clk_clk;
output clock_116_mhz_clk;
output [12:0] external_sdram_controller_wire_addr;
output [1:0] external_sdram_controller_wire_ba;
output external_sdram_controller_wire_cas_n;
output external_sdram_controller_wire_cke;
output external_sdram_controller_wire_cs_n;
inout [15:0] external_sdram_controller_wire_dq;
output [1:0] external_sdram_controller_wire_dqm;
output external_sdram_controller_wire_ras_n;
output external_sdram_controller_wire_we_n;
input [9:0] sega_saturn_abus_slave_0_abus_address;
input [2:0] sega_saturn_abus_slave_0_abus_chipselect;
input sega_saturn_abus_slave_0_abus_read;
input [1:0] sega_saturn_abus_slave_0_abus_write;
output sega_saturn_abus_slave_0_abus_waitrequest;
output sega_saturn_abus_slave_0_abus_interrupt;
inout [15:0] sega_saturn_abus_slave_0_abus_addressdata;
output sega_saturn_abus_slave_0_abus_direction;
output [1:0] sega_saturn_abus_slave_0_abus_muxing;
output sega_saturn_abus_slave_0_abus_disableout;
input sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset;
input spi_sd_card_MISO;
output spi_sd_card_MOSI;
output spi_sd_card_SCLK;
output spi_sd_card_SS_n;
input uart_0_external_connection_rxd;
output uart_0_external_connection_txd;
output spi_stm32_MISO;
input spi_stm32_MOSI;
input spi_stm32_SCLK;
input spi_stm32_SS_n;
input audio_out_BCLK;
output audio_out_DACDAT;
input audio_out_DACLRCK;
endmodule |
module PCIEBus_pipe_eq #
(
parameter PCIE_SIM_MODE = "FALSE",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_RXEQ_MODE_GEN3 = 1
)
(
//---------- Input -------------------------------------
input EQ_CLK,
input EQ_RST_N,
input EQ_GEN3,
input [ 1:0] EQ_TXEQ_CONTROL,
input [ 3:0] EQ_TXEQ_PRESET,
input [ 3:0] EQ_TXEQ_PRESET_DEFAULT,
input [ 5:0] EQ_TXEQ_DEEMPH_IN,
input [ 1:0] EQ_RXEQ_CONTROL,
input [ 2:0] EQ_RXEQ_PRESET,
input [ 5:0] EQ_RXEQ_LFFS,
input [ 3:0] EQ_RXEQ_TXPRESET,
input EQ_RXEQ_USER_EN,
input [17:0] EQ_RXEQ_USER_TXCOEFF,
input EQ_RXEQ_USER_MODE,
//---------- Output ------------------------------------
output EQ_TXEQ_DEEMPH,
output [ 4:0] EQ_TXEQ_PRECURSOR,
output [ 6:0] EQ_TXEQ_MAINCURSOR,
output [ 4:0] EQ_TXEQ_POSTCURSOR,
output [17:0] EQ_TXEQ_DEEMPH_OUT,
output EQ_TXEQ_DONE,
output [ 5:0] EQ_TXEQ_FSM,
output [17:0] EQ_RXEQ_NEW_TXCOEFF,
output EQ_RXEQ_LFFS_SEL,
output EQ_RXEQ_ADAPT_DONE,
output EQ_RXEQ_DONE,
output [ 5:0] EQ_RXEQ_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg2;
//---------- Internal Signals --------------------------
reg [18:0] txeq_preset = 19'd0;
reg txeq_preset_done = 1'd0;
reg [ 1:0] txeq_txcoeff_cnt = 2'd0;
reg [ 2:0] rxeq_preset = 3'd0;
reg rxeq_preset_valid = 1'd0;
reg [ 3:0] rxeq_txpreset = 4'd0;
reg [17:0] rxeq_txcoeff = 18'd0;
reg [ 2:0] rxeq_cnt = 3'd0;
reg [ 5:0] rxeq_fs = 6'd0;
reg [ 5:0] rxeq_lf = 6'd0;
reg rxeq_new_txcoeff_req = 1'd0;
//---------- Output Registers --------------------------
reg [18:0] txeq_txcoeff = 19'd0;
reg txeq_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg [17:0] rxeq_new_txcoeff = 18'd0;
reg rxeq_lffs_sel = 1'd0;
reg rxeq_adapt_done_reg = 1'd0;
reg rxeq_adapt_done = 1'd0;
reg rxeq_done = 1'd0;
reg [ 5:0] fsm_rx = 6'd0;
//---------- RXEQ Eye Scan Module Output ---------------
wire rxeqscan_lffs_sel;
wire rxeqscan_preset_done;
wire [17:0] rxeqscan_new_txcoeff;
wire rxeqscan_new_txcoeff_done;
wire rxeqscan_adapt_done;
//---------- FSM ---------------------------------------
localparam FSM_TXEQ_IDLE = 6'b000001;
localparam FSM_TXEQ_PRESET = 6'b000010;
localparam FSM_TXEQ_TXCOEFF = 6'b000100;
localparam FSM_TXEQ_REMAP = 6'b001000;
localparam FSM_TXEQ_QUERY = 6'b010000;
localparam FSM_TXEQ_DONE = 6'b100000;
localparam FSM_RXEQ_IDLE = 6'b000001;
localparam FSM_RXEQ_PRESET = 6'b000010;
localparam FSM_RXEQ_TXCOEFF = 6'b000100;
localparam FSM_RXEQ_LF = 6'b001000;
localparam FSM_RXEQ_NEW_TXCOEFF_REQ = 6'b010000;
localparam FSM_RXEQ_DONE = 6'b100000;
//---------- TXEQ Presets Look-up Table ----------------
// TXPRECURSOR = Coefficient range between 0 and 20 units
// TXMAINCURSOR = Coefficient range between 29 and 80 units
// TXPOSTCURSOR = Coefficient range between 0 and 31 units
//------------------------------------------------------
// Actual Full Swing (FS) = 80
// Actual Low Frequency (LF) = 29
// Advertise Full Swing (FS) = 40
// Advertise Low Frequency (LF) = 15
//------------------------------------------------------
// Pre-emphasis = 20 log [80 - (2 * TXPRECURSOR)] / 80], assuming no de-emphasis
// Main-emphasis = 80 - (TXPRECURSOR + TXPOSTCURSOR)
// De-emphasis = 20 log [80 - (2 * TXPOSTCURSOR)] / 80], assuming no pre-emphasis
//------------------------------------------------------
// Note: TXMAINCURSOR calculated internally in GT
//------------------------------------------------------
localparam TXPRECURSOR_00 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_00 = 7'd60;
localparam TXPOSTCURSOR_00 = 6'd20; // -6.0 +/- 1 dB
localparam TXPRECURSOR_01 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_01 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_01 = 6'd13; // -3.5 +/- 1 dB
localparam TXPRECURSOR_02 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_02 = 7'd64;
localparam TXPOSTCURSOR_02 = 6'd16; // -4.4 +/- 1.5 dB
localparam TXPRECURSOR_03 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_03 = 7'd70;
localparam TXPOSTCURSOR_03 = 6'd10; // -2.5 +/- 1 dB
localparam TXPRECURSOR_04 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_04 = 7'd80;
localparam TXPOSTCURSOR_04 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_05 = 6'd8; // -1.9 +/- 1 dB
localparam TXMAINCURSOR_05 = 7'd72;
localparam TXPOSTCURSOR_05 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_06 = 6'd10; // -2.5 +/- 1 dB
localparam TXMAINCURSOR_06 = 7'd70;
localparam TXPOSTCURSOR_06 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_07 = 6'd8; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_07 = 7'd56;
localparam TXPOSTCURSOR_07 = 6'd16; // -6.0 +/- 1 dB
localparam TXPRECURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_08 = 7'd60;
localparam TXPOSTCURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXPRECURSOR_09 = 6'd13; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_09 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_09 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_10 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_10 = 7'd56; // added 1 to compensate decimal
localparam TXPOSTCURSOR_10 = 6'd25; // 9.5 +/- 1 dB, updated for coefficient rules
//---------- Input FF ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
txeq_control_reg1 <= 2'd0;
txeq_preset_reg1 <= 4'd0;
txeq_deemph_reg1 <= 6'd1;
rxeq_control_reg1 <= 2'd0;
rxeq_preset_reg1 <= 3'd0;
rxeq_lffs_reg1 <= 6'd0;
rxeq_txpreset_reg1 <= 4'd0;
rxeq_user_en_reg1 <= 1'd0;
rxeq_user_txcoeff_reg1 <= 18'd0;
rxeq_user_mode_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
txeq_control_reg2 <= 2'd0;
txeq_preset_reg2 <= 4'd0;
txeq_deemph_reg2 <= 6'd1;
rxeq_control_reg2 <= 2'd0;
rxeq_preset_reg2 <= 3'd0;
rxeq_lffs_reg2 <= 6'd0;
rxeq_txpreset_reg2 <= 4'd0;
rxeq_user_en_reg2 <= 1'd0;
rxeq_user_txcoeff_reg2 <= 18'd0;
rxeq_user_mode_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= EQ_GEN3;
txeq_control_reg1 <= EQ_TXEQ_CONTROL;
txeq_preset_reg1 <= EQ_TXEQ_PRESET;
txeq_deemph_reg1 <= EQ_TXEQ_DEEMPH_IN;
rxeq_control_reg1 <= EQ_RXEQ_CONTROL;
rxeq_preset_reg1 <= EQ_RXEQ_PRESET;
rxeq_lffs_reg1 <= EQ_RXEQ_LFFS;
rxeq_txpreset_reg1 <= EQ_RXEQ_TXPRESET;
rxeq_user_en_reg1 <= EQ_RXEQ_USER_EN;
rxeq_user_txcoeff_reg1 <= EQ_RXEQ_USER_TXCOEFF;
rxeq_user_mode_reg1 <= EQ_RXEQ_USER_MODE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
txeq_control_reg2 <= txeq_control_reg1;
txeq_preset_reg2 <= txeq_preset_reg1;
txeq_deemph_reg2 <= txeq_deemph_reg1;
rxeq_control_reg2 <= rxeq_control_reg1;
rxeq_preset_reg2 <= rxeq_preset_reg1;
rxeq_lffs_reg2 <= rxeq_lffs_reg1;
rxeq_txpreset_reg2 <= rxeq_txpreset_reg1;
rxeq_user_en_reg2 <= rxeq_user_en_reg1;
rxeq_user_txcoeff_reg2 <= rxeq_user_txcoeff_reg1;
rxeq_user_mode_reg2 <= rxeq_user_mode_reg1;
end
end
//---------- TXEQ Preset -------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- Select TXEQ Preset ----------------
case (EQ_TXEQ_PRESET_DEFAULT)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd0;
end
else
begin
if (fsm_tx == FSM_TXEQ_PRESET)
begin
//---------- Select TXEQ Preset ----------------
case (txeq_preset_reg2)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd1;
end
else
begin
txeq_preset <= txeq_preset;
txeq_preset_done <= 1'd0;
end
end
end
//---------- TXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ----------------------------
FSM_TXEQ_IDLE :
begin
case (txeq_control_reg2)
//---------- Idle ------------------------------
2'd0 :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Process TXEQ Preset ---------------
2'd1 :
begin
fsm_tx <= FSM_TXEQ_PRESET;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Coefficient -----------------------
2'd2 :
begin
fsm_tx <= FSM_TXEQ_TXCOEFF;
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= 2'd1;
txeq_done <= 1'd0;
end
//---------- Query -----------------------------
2'd3 :
begin
fsm_tx <= FSM_TXEQ_QUERY;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
//---------- Process TXEQ Preset -------------------
FSM_TXEQ_PRESET :
begin
fsm_tx <= (txeq_preset_done ? FSM_TXEQ_DONE : FSM_TXEQ_PRESET);
txeq_txcoeff <= txeq_preset;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Latch Link Partner TX Coefficient -----
FSM_TXEQ_TXCOEFF :
begin
fsm_tx <= ((txeq_txcoeff_cnt == 2'd2) ? FSM_TXEQ_REMAP : FSM_TXEQ_TXCOEFF);
//---------- Shift in extra bit for TXMAINCURSOR
if (txeq_txcoeff_cnt == 2'd1)
txeq_txcoeff <= {1'd0, txeq_deemph_reg2, txeq_txcoeff[18:7]};
else
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= txeq_txcoeff_cnt + 2'd1;
txeq_done <= 1'd0;
end
//---------- Remap to GT TX Coefficient ------------
FSM_TXEQ_REMAP :
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff << 1; // Multiply by 2x
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Query TXEQ Coefficient ----------------
FSM_TXEQ_QUERY:
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Done ----------------------------------
FSM_TXEQ_DONE :
begin
fsm_tx <= ((txeq_control_reg2 == 2'd0) ? FSM_TXEQ_IDLE : FSM_TXEQ_DONE);
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ----------------------------
FSM_RXEQ_IDLE :
begin
case (rxeq_control_reg2)
//---------- Process RXEQ Preset ---------------
2'd1 :
begin
fsm_rx <= FSM_RXEQ_PRESET;
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient --------
2'd2 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Phase2/3 Bypass (reuse logic from rxeq_control = 2 ----
2'd3 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
//---------- Process RXEQ Preset -------------------
FSM_RXEQ_PRESET :
begin
fsm_rx <= (rxeqscan_preset_done ? FSM_RXEQ_DONE : FSM_RXEQ_PRESET);
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd1;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Shift-in Link Partner TX Coefficient and Preset
FSM_RXEQ_TXCOEFF :
begin
fsm_rx <= ((rxeq_cnt == 3'd2) ? FSM_RXEQ_LF : FSM_RXEQ_TXCOEFF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Read Low Frequency (LF) Value ---------
FSM_RXEQ_LF :
begin
fsm_rx <= ((rxeq_cnt == 3'd7) ? FSM_RXEQ_NEW_TXCOEFF_REQ : FSM_RXEQ_LF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= ((rxeq_cnt == 3'd7) ? rxeq_lffs_reg2 : rxeq_lf);
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient ------------
FSM_RXEQ_NEW_TXCOEFF_REQ :
begin
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
if (rxeqscan_new_txcoeff_done)
begin
fsm_rx <= FSM_RXEQ_DONE;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeqscan_lffs_sel ? {14'd0, rxeqscan_new_txcoeff[3:0]} : rxeqscan_new_txcoeff;
rxeq_lffs_sel <= rxeqscan_lffs_sel;
rxeq_adapt_done_reg <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXEQ_NEW_TXCOEFF_REQ;
rxeq_new_txcoeff_req <= 1'd1;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
end
//---------- RXEQ Done -----------------------------
FSM_RXEQ_DONE :
begin
fsm_rx <= ((rxeq_control_reg2 == 2'd0) ? FSM_RXEQ_IDLE : FSM_RXEQ_DONE);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= rxeq_lffs_sel;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeq_adapt_done;
rxeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Module ----------------------------------------------
PCIEBus_rxeq_scan #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE),
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3)
)
rxeq_scan_i
(
//---------- Input -------------------------------------
.RXEQSCAN_CLK (EQ_CLK),
.RXEQSCAN_RST_N (EQ_RST_N),
.RXEQSCAN_CONTROL (rxeq_control_reg2),
.RXEQSCAN_FS (rxeq_fs),
.RXEQSCAN_LF (rxeq_lf),
.RXEQSCAN_PRESET (rxeq_preset),
.RXEQSCAN_PRESET_VALID (rxeq_preset_valid),
.RXEQSCAN_TXPRESET (rxeq_txpreset),
.RXEQSCAN_TXCOEFF (rxeq_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_REQ (rxeq_new_txcoeff_req),
//---------- Output ------------------------------------
.RXEQSCAN_PRESET_DONE (rxeqscan_preset_done),
.RXEQSCAN_NEW_TXCOEFF (rxeqscan_new_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_DONE (rxeqscan_new_txcoeff_done),
.RXEQSCAN_LFFS_SEL (rxeqscan_lffs_sel),
.RXEQSCAN_ADAPT_DONE (rxeqscan_adapt_done)
);
//---------- PIPE EQ Output ----------------------------------------------------
assign EQ_TXEQ_DEEMPH = txeq_txcoeff[0];
assign EQ_TXEQ_PRECURSOR = gen3_reg2 ? txeq_txcoeff[ 4: 0] : 5'h00;
assign EQ_TXEQ_MAINCURSOR = gen3_reg2 ? txeq_txcoeff[12: 6] : 7'h00;
assign EQ_TXEQ_POSTCURSOR = gen3_reg2 ? txeq_txcoeff[17:13] : 5'h00;
assign EQ_TXEQ_DEEMPH_OUT = {1'd0, txeq_txcoeff[18:14], txeq_txcoeff[12:7], 1'd0, txeq_txcoeff[5:1]}; // Divide by 2x
assign EQ_TXEQ_DONE = txeq_done;
assign EQ_TXEQ_FSM = fsm_tx;
assign EQ_RXEQ_NEW_TXCOEFF = rxeq_user_en_reg2 ? rxeq_user_txcoeff_reg2 : rxeq_new_txcoeff;
assign EQ_RXEQ_LFFS_SEL = rxeq_user_en_reg2 ? rxeq_user_mode_reg2 : rxeq_lffs_sel;
assign EQ_RXEQ_ADAPT_DONE = rxeq_adapt_done;
assign EQ_RXEQ_DONE = rxeq_done;
assign EQ_RXEQ_FSM = fsm_rx;
endmodule |
module sky130_fd_sc_ms__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module sky130_fd_sc_hd__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(IPCORE_CLK, IPCORE_RESETN, AXI4_Lite_ACLK,
AXI4_Lite_ARESETN, AXI4_Lite_AWADDR, AXI4_Lite_AWVALID, AXI4_Lite_WDATA, AXI4_Lite_WSTRB,
AXI4_Lite_WVALID, AXI4_Lite_BREADY, AXI4_Lite_ARADDR, AXI4_Lite_ARVALID,
AXI4_Lite_RREADY, AXI4_Lite_AWREADY, AXI4_Lite_WREADY, AXI4_Lite_BRESP, AXI4_Lite_BVALID,
AXI4_Lite_ARREADY, AXI4_Lite_RDATA, AXI4_Lite_RRESP, AXI4_Lite_RVALID)
/* synthesis syn_black_box black_box_pad_pin="IPCORE_CLK,IPCORE_RESETN,AXI4_Lite_ACLK,AXI4_Lite_ARESETN,AXI4_Lite_AWADDR[15:0],AXI4_Lite_AWVALID,AXI4_Lite_WDATA[31:0],AXI4_Lite_WSTRB[3:0],AXI4_Lite_WVALID,AXI4_Lite_BREADY,AXI4_Lite_ARADDR[15:0],AXI4_Lite_ARVALID,AXI4_Lite_RREADY,AXI4_Lite_AWREADY,AXI4_Lite_WREADY,AXI4_Lite_BRESP[1:0],AXI4_Lite_BVALID,AXI4_Lite_ARREADY,AXI4_Lite_RDATA[31:0],AXI4_Lite_RRESP[1:0],AXI4_Lite_RVALID" */;
input IPCORE_CLK;
input IPCORE_RESETN;
input AXI4_Lite_ACLK;
input AXI4_Lite_ARESETN;
input [15:0]AXI4_Lite_AWADDR;
input AXI4_Lite_AWVALID;
input [31:0]AXI4_Lite_WDATA;
input [3:0]AXI4_Lite_WSTRB;
input AXI4_Lite_WVALID;
input AXI4_Lite_BREADY;
input [15:0]AXI4_Lite_ARADDR;
input AXI4_Lite_ARVALID;
input AXI4_Lite_RREADY;
output AXI4_Lite_AWREADY;
output AXI4_Lite_WREADY;
output [1:0]AXI4_Lite_BRESP;
output AXI4_Lite_BVALID;
output AXI4_Lite_ARREADY;
output [31:0]AXI4_Lite_RDATA;
output [1:0]AXI4_Lite_RRESP;
output AXI4_Lite_RVALID;
endmodule |
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule |
module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule |
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule |
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule |
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule |
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule |
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule |
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule |
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule |
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule |
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule |
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule |
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule |
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule |
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule |
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule |
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule |
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule |
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule |
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule |
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule |
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule |
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule |
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule |
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule |
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule |
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule |
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule |
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule |
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule |
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule |
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule |
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule |
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule |
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule |
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule |
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule |
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