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module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule |
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule |
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule |
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule |
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule |
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule |
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule |
module sky130_fd_sc_hd__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module sky130_fd_sc_ms__dfstp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115,
n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170,
n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203,
n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236,
n237, n238, n239, n240, n241, n242, n243, n244, n245, n246, n247,
n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258,
n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269,
n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280,
n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313,
n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324,
n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335,
n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346,
n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357,
n358;
XNOR2X1TS U42 ( .A(n227), .B(n226), .Y(res[29]) );
NAND2X1TS U43 ( .A(n59), .B(n237), .Y(n238) );
NAND2X1TS U44 ( .A(n233), .B(n232), .Y(n234) );
NAND2XLTS U45 ( .A(n58), .B(n296), .Y(n298) );
NAND2X1TS U46 ( .A(n64), .B(n210), .Y(n207) );
NAND2X1TS U47 ( .A(n225), .B(n224), .Y(n226) );
NAND2X1TS U48 ( .A(n241), .B(n240), .Y(n242) );
NAND2XLTS U49 ( .A(n61), .B(n282), .Y(n283) );
NAND2XLTS U50 ( .A(n286), .B(n285), .Y(n287) );
NAND2XLTS U51 ( .A(n269), .B(n268), .Y(n270) );
NAND2XLTS U52 ( .A(n278), .B(n277), .Y(n279) );
NAND2X1TS U53 ( .A(n258), .B(n257), .Y(n259) );
NAND2X1TS U54 ( .A(n265), .B(n264), .Y(n266) );
NAND2XLTS U55 ( .A(n251), .B(n250), .Y(n252) );
NAND2X6TS U56 ( .A(n222), .B(n11), .Y(n56) );
OAI21X1TS U57 ( .A0(n9), .A1(n310), .B0(n311), .Y(n309) );
OAI21X1TS U58 ( .A0(n288), .A1(n275), .B0(n274), .Y(n280) );
OA21XLTS U59 ( .A0(n314), .A1(n111), .B0(n44), .Y(n9) );
INVX4TS U60 ( .A(n244), .Y(n271) );
INVX2TS U61 ( .A(n290), .Y(n297) );
NAND2X2TS U62 ( .A(n219), .B(in1[31]), .Y(n221) );
CLKBUFX2TS U63 ( .A(n289), .Y(n290) );
CLKMX2X2TS U64 ( .A(in2[31]), .B(n218), .S0(n217), .Y(n219) );
NOR2X1TS U65 ( .A(n215), .B(in2[30]), .Y(n216) );
NOR2X4TS U66 ( .A(n230), .B(n231), .Y(n198) );
NAND2X1TS U67 ( .A(n178), .B(in1[25]), .Y(n250) );
NAND2X2TS U68 ( .A(n176), .B(in1[23]), .Y(n264) );
NAND2X2TS U69 ( .A(n177), .B(in1[24]), .Y(n257) );
CLKMX2X2TS U70 ( .A(in2[29]), .B(n202), .S0(n201), .Y(n203) );
NAND2X2TS U71 ( .A(n194), .B(in1[27]), .Y(n237) );
OR2X4TS U72 ( .A(n154), .B(in1[20]), .Y(n61) );
NAND2BX2TS U73 ( .AN(in2[29]), .B(n204), .Y(n215) );
XNOR2X1TS U74 ( .A(n200), .B(in2[24]), .Y(n165) );
INVX2TS U75 ( .A(in2[23]), .Y(n168) );
OR2X1TS U76 ( .A(n190), .B(in2[27]), .Y(n199) );
NOR2X2TS U77 ( .A(n171), .B(n170), .Y(n172) );
NOR2X2TS U78 ( .A(n200), .B(n190), .Y(n188) );
XNOR2X1TS U79 ( .A(n131), .B(in2[17]), .Y(n132) );
NAND2X1TS U80 ( .A(n187), .B(n186), .Y(n190) );
NAND2X1TS U81 ( .A(n143), .B(in2[19]), .Y(n144) );
XNOR2X1TS U82 ( .A(n141), .B(in2[18]), .Y(n133) );
XOR2X2TS U83 ( .A(n171), .B(n149), .Y(n148) );
INVX2TS U84 ( .A(in2[26]), .Y(n186) );
NOR2X2TS U85 ( .A(in2[25]), .B(in2[24]), .Y(n187) );
NAND2X6TS U86 ( .A(n161), .B(n160), .Y(n200) );
INVX12TS U87 ( .A(n18), .Y(n160) );
OR2X6TS U88 ( .A(n107), .B(in1[11]), .Y(n62) );
INVX2TS U89 ( .A(n316), .Y(n109) );
INVX2TS U90 ( .A(n110), .Y(n317) );
NOR2X4TS U91 ( .A(n320), .B(n110), .Y(n45) );
NAND2X2TS U92 ( .A(n91), .B(in1[9]), .Y(n330) );
NOR2X6TS U93 ( .A(n117), .B(in1[14]), .Y(n305) );
NAND2X6TS U94 ( .A(n107), .B(in1[11]), .Y(n320) );
NAND2X2TS U95 ( .A(n108), .B(in1[12]), .Y(n316) );
OR2X2TS U96 ( .A(in2[21]), .B(in2[20]), .Y(n170) );
NAND2X4TS U97 ( .A(n33), .B(n32), .Y(n60) );
AND2X2TS U98 ( .A(n119), .B(n124), .Y(n12) );
NOR2X1TS U99 ( .A(in2[19]), .B(in2[18]), .Y(n146) );
XNOR2X2TS U100 ( .A(n104), .B(in2[10]), .Y(n87) );
NOR2X2TS U101 ( .A(in2[17]), .B(in2[16]), .Y(n147) );
CLKINVX6TS U102 ( .A(n77), .Y(n33) );
BUFX12TS U103 ( .A(n217), .Y(n201) );
INVX2TS U104 ( .A(in2[14]), .Y(n119) );
NOR2X2TS U105 ( .A(n95), .B(in2[8]), .Y(n88) );
INVX4TS U106 ( .A(n46), .Y(n70) );
NAND2X2TS U107 ( .A(n10), .B(n113), .Y(n114) );
NOR2X4TS U108 ( .A(n104), .B(in2[10]), .Y(n105) );
NAND2X4TS U109 ( .A(n46), .B(n31), .Y(n30) );
INVX6TS U110 ( .A(n143), .Y(n217) );
AO22X2TS U111 ( .A0(add_sub), .A1(n69), .B0(n67), .B1(in2[5]), .Y(n68) );
NAND3X2TS U112 ( .A(n37), .B(n72), .C(n348), .Y(n65) );
INVX4TS U113 ( .A(add_sub), .Y(n83) );
INVX4TS U114 ( .A(in2[8]), .Y(n86) );
NAND2X4TS U115 ( .A(n41), .B(n69), .Y(n79) );
INVX4TS U116 ( .A(n118), .Y(n28) );
CLKINVX3TS U117 ( .A(in2[9]), .Y(n90) );
NOR2X4TS U118 ( .A(n28), .B(n111), .Y(n27) );
MXI2X2TS U119 ( .A(n127), .B(n126), .S0(n201), .Y(n128) );
MXI2X2TS U120 ( .A(n152), .B(n151), .S0(n143), .Y(n157) );
INVX2TS U121 ( .A(n240), .Y(n196) );
NAND2X2TS U122 ( .A(n154), .B(in1[20]), .Y(n282) );
NAND2X1TS U123 ( .A(n197), .B(in1[28]), .Y(n232) );
INVX4TS U124 ( .A(add_sub), .Y(n143) );
OAI21XLTS U125 ( .A0(n333), .A1(n329), .B0(n330), .Y(n328) );
NAND2X1TS U126 ( .A(n293), .B(n292), .Y(n294) );
NOR2X4TS U127 ( .A(n25), .B(n24), .Y(n23) );
NAND2X4TS U128 ( .A(n317), .B(n62), .Y(n111) );
MX2X2TS U129 ( .A(in2[15]), .B(n122), .S0(add_sub), .Y(n123) );
XNOR2X2TS U130 ( .A(n65), .B(in2[6]), .Y(n66) );
NOR4X2TS U131 ( .A(n159), .B(n170), .C(in2[23]), .D(in2[22]), .Y(n161) );
NOR2X4TS U132 ( .A(n197), .B(in1[28]), .Y(n231) );
NAND2X1TS U133 ( .A(n63), .B(n299), .Y(n300) );
NOR2X4TS U134 ( .A(n141), .B(in2[18]), .Y(n142) );
NOR3X4TS U135 ( .A(n200), .B(in2[28]), .C(n199), .Y(n204) );
NOR2X2TS U136 ( .A(n200), .B(n199), .Y(n191) );
NAND2X1TS U137 ( .A(n307), .B(n306), .Y(n308) );
NAND2X1TS U138 ( .A(n317), .B(n316), .Y(n318) );
NAND2X1TS U139 ( .A(n16), .B(n303), .Y(n304) );
NAND2X6TS U140 ( .A(n19), .B(n12), .Y(n18) );
NOR2X4TS U141 ( .A(n108), .B(in1[12]), .Y(n110) );
INVX6TS U142 ( .A(n125), .Y(n19) );
INVX2TS U143 ( .A(in1[6]), .Y(n31) );
INVX2TS U144 ( .A(in1[7]), .Y(n32) );
INVX4TS U145 ( .A(n236), .Y(n241) );
OR2X4TS U146 ( .A(n219), .B(in1[31]), .Y(n11) );
INVX2TS U147 ( .A(n263), .Y(n265) );
INVX2TS U148 ( .A(n249), .Y(n251) );
NAND2X4TS U149 ( .A(n193), .B(in1[26]), .Y(n240) );
OR2X4TS U150 ( .A(n206), .B(in1[30]), .Y(n64) );
NOR2X4TS U151 ( .A(n157), .B(in1[21]), .Y(n276) );
NAND2X4TS U152 ( .A(n153), .B(in1[19]), .Y(n285) );
INVX2TS U153 ( .A(n292), .Y(n137) );
NOR2X4TS U154 ( .A(n178), .B(in1[25]), .Y(n249) );
NAND2X4TS U155 ( .A(n135), .B(in1[17]), .Y(n296) );
XNOR2X1TS U156 ( .A(n216), .B(in2[31]), .Y(n218) );
XOR2X2TS U157 ( .A(n150), .B(in2[21]), .Y(n152) );
OR2X4TS U158 ( .A(n128), .B(in1[16]), .Y(n63) );
XOR2X2TS U159 ( .A(n163), .B(n162), .Y(n164) );
INVX2TS U160 ( .A(n305), .Y(n307) );
NAND2X4TS U161 ( .A(n116), .B(in1[13]), .Y(n311) );
NAND2X4TS U162 ( .A(n123), .B(in1[15]), .Y(n303) );
NAND2X4TS U163 ( .A(n92), .B(in1[10]), .Y(n325) );
NAND2X4TS U164 ( .A(n353), .B(n69), .Y(n47) );
NOR2X4TS U165 ( .A(in2[13]), .B(in2[12]), .Y(n120) );
XOR2X1TS U166 ( .A(n295), .B(n294), .Y(res[18]) );
INVX4TS U167 ( .A(n198), .Y(n8) );
NAND2X4TS U168 ( .A(n241), .B(n59), .Y(n230) );
NAND2X2TS U169 ( .A(n11), .B(n221), .Y(n220) );
AOI21X2TS U170 ( .A0(n64), .A1(n212), .B0(n211), .Y(n213) );
XOR2X1TS U171 ( .A(n302), .B(n304), .Y(res[15]) );
NAND2X4TS U172 ( .A(n64), .B(n225), .Y(n214) );
INVX2TS U173 ( .A(n237), .Y(n195) );
OAI21X2TS U174 ( .A0(n249), .A1(n257), .B0(n250), .Y(n179) );
NOR2X4TS U175 ( .A(n249), .B(n256), .Y(n180) );
NAND2X4TS U176 ( .A(n58), .B(n293), .Y(n140) );
XOR2X1TS U177 ( .A(n319), .B(n318), .Y(res[12]) );
NAND2X2TS U178 ( .A(n206), .B(in1[30]), .Y(n210) );
NAND2X4TS U179 ( .A(n203), .B(in1[29]), .Y(n224) );
NAND2X4TS U180 ( .A(n175), .B(in1[22]), .Y(n268) );
INVX2TS U181 ( .A(n256), .Y(n258) );
NAND2X2TS U182 ( .A(n157), .B(in1[21]), .Y(n277) );
XOR2X1TS U183 ( .A(n9), .B(n313), .Y(res[13]) );
MX2X2TS U184 ( .A(in2[30]), .B(n205), .S0(n217), .Y(n206) );
NOR2X4TS U185 ( .A(n203), .B(in1[29]), .Y(n209) );
OR2X6TS U186 ( .A(n135), .B(in1[17]), .Y(n58) );
OR2X6TS U187 ( .A(n194), .B(in1[27]), .Y(n59) );
MX2X2TS U188 ( .A(in2[27]), .B(n189), .S0(n217), .Y(n194) );
XNOR2X2TS U189 ( .A(n184), .B(in2[26]), .Y(n185) );
MX2X2TS U190 ( .A(in2[25]), .B(n164), .S0(n201), .Y(n178) );
XOR2X1TS U191 ( .A(n333), .B(n332), .Y(res[9]) );
XNOR2X2TS U192 ( .A(n188), .B(in2[27]), .Y(n189) );
INVX2TS U193 ( .A(n200), .Y(n183) );
NOR2X2TS U194 ( .A(n130), .B(in2[16]), .Y(n131) );
INVX4TS U195 ( .A(n339), .Y(n78) );
NAND2X6TS U196 ( .A(n29), .B(n342), .Y(n340) );
NOR2X4TS U197 ( .A(n91), .B(in1[9]), .Y(n329) );
NAND2X6TS U198 ( .A(n343), .B(n30), .Y(n29) );
NAND3X6TS U199 ( .A(n68), .B(n48), .C(n47), .Y(n46) );
OAI21XLTS U200 ( .A0(n355), .A1(n83), .B0(n354), .Y(res[5]) );
MXI2X4TS U201 ( .A(n66), .B(n71), .S0(n83), .Y(n343) );
OAI21XLTS U202 ( .A0(n358), .A1(n83), .B0(n357), .Y(res[4]) );
OAI21XLTS U203 ( .A0(n350), .A1(n83), .B0(n349), .Y(res[2]) );
OAI21XLTS U204 ( .A0(n347), .A1(n83), .B0(n346), .Y(res[3]) );
AND2X4TS U205 ( .A(n100), .B(n99), .Y(n101) );
OAI21XLTS U206 ( .A0(n352), .A1(n143), .B0(n351), .Y(res[1]) );
NAND2X2TS U207 ( .A(n147), .B(n146), .Y(n159) );
AND2X4TS U208 ( .A(n98), .B(n97), .Y(n99) );
NAND2X4TS U209 ( .A(n86), .B(n90), .Y(n96) );
OR2X1TS U210 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
INVX8TS U211 ( .A(n356), .Y(n82) );
AND2X6TS U212 ( .A(n60), .B(n340), .Y(n13) );
NOR2X8TS U213 ( .A(n85), .B(in1[8]), .Y(n334) );
NOR2X6TS U214 ( .A(n263), .B(n261), .Y(n255) );
INVX6TS U215 ( .A(n79), .Y(n37) );
INVX6TS U216 ( .A(n273), .Y(n288) );
NOR2X4TS U217 ( .A(n324), .B(n329), .Y(n94) );
NOR2X4TS U218 ( .A(n153), .B(in1[19]), .Y(n281) );
XNOR2X4TS U219 ( .A(n142), .B(in2[19]), .Y(n145) );
NOR2X4TS U220 ( .A(n356), .B(in2[4]), .Y(n353) );
AOI21X2TS U221 ( .A0(n356), .A1(n15), .B0(n49), .Y(n48) );
MXI2X4TS U222 ( .A(n134), .B(n133), .S0(n201), .Y(n136) );
NOR2X8TS U223 ( .A(n50), .B(n57), .Y(n223) );
MXI2X4TS U224 ( .A(n86), .B(n84), .S0(n217), .Y(n85) );
NOR2X4TS U225 ( .A(n200), .B(in2[24]), .Y(n163) );
INVX16TS U226 ( .A(in2[5]), .Y(n69) );
NAND2BX4TS U227 ( .AN(n159), .B(n160), .Y(n171) );
NOR2X4TS U228 ( .A(n175), .B(in1[22]), .Y(n261) );
MXI2X4TS U229 ( .A(n90), .B(n89), .S0(n201), .Y(n91) );
XOR2X4TS U230 ( .A(n88), .B(in2[9]), .Y(n89) );
CLKINVX12TS U231 ( .A(n95), .Y(n102) );
NOR2X4TS U232 ( .A(n171), .B(in2[20]), .Y(n150) );
NAND2X4TS U233 ( .A(n160), .B(n147), .Y(n141) );
NOR2X2TS U234 ( .A(n275), .B(n276), .Y(n158) );
OAI21X2TS U235 ( .A0(n274), .A1(n276), .B0(n277), .Y(n36) );
NAND3X4TS U236 ( .A(n72), .B(n14), .C(n71), .Y(n73) );
INVX2TS U237 ( .A(in2[6]), .Y(n71) );
XOR2X1TS U238 ( .A(n86), .B(n95), .Y(n84) );
MXI2X4TS U239 ( .A(n97), .B(n87), .S0(n201), .Y(n92) );
MX2X4TS U240 ( .A(in2[17]), .B(n132), .S0(add_sub), .Y(n135) );
NAND2X4TS U241 ( .A(n85), .B(in1[8]), .Y(n335) );
INVX2TS U242 ( .A(n323), .Y(n333) );
INVX2TS U243 ( .A(n314), .Y(n322) );
NAND2X4TS U244 ( .A(n128), .B(in1[16]), .Y(n299) );
NOR2X4TS U245 ( .A(n176), .B(in1[23]), .Y(n263) );
NOR2X4TS U246 ( .A(n177), .B(in1[24]), .Y(n256) );
NOR2X4TS U247 ( .A(n193), .B(in1[26]), .Y(n236) );
INVX2TS U248 ( .A(n209), .Y(n225) );
NAND2X4TS U249 ( .A(n198), .B(n54), .Y(n51) );
INVX2TS U250 ( .A(n96), .Y(n100) );
INVX2TS U251 ( .A(in2[15]), .Y(n124) );
CLKINVX6TS U252 ( .A(in2[4]), .Y(n41) );
CLKAND2X2TS U253 ( .A(in2[5]), .B(add_sub), .Y(n15) );
INVX2TS U254 ( .A(in1[5]), .Y(n49) );
NAND2X1TS U255 ( .A(in2[4]), .B(add_sub), .Y(n67) );
INVX2TS U256 ( .A(in2[10]), .Y(n97) );
NAND2X2TS U257 ( .A(n180), .B(n255), .Y(n182) );
NAND2X4TS U258 ( .A(n34), .B(n76), .Y(n77) );
NAND2X1TS U259 ( .A(n83), .B(in2[7]), .Y(n76) );
NAND2X4TS U260 ( .A(n75), .B(n74), .Y(n34) );
MXI2X4TS U261 ( .A(n119), .B(n112), .S0(n201), .Y(n117) );
INVX4TS U262 ( .A(n44), .Y(n43) );
NOR2X2TS U263 ( .A(n305), .B(n311), .Y(n25) );
INVX2TS U264 ( .A(n306), .Y(n24) );
NOR2X4TS U265 ( .A(n136), .B(in1[18]), .Y(n138) );
INVX2TS U266 ( .A(n299), .Y(n129) );
INVX2TS U267 ( .A(n182), .Y(n54) );
INVX2TS U268 ( .A(n224), .Y(n212) );
INVX2TS U269 ( .A(n210), .Y(n211) );
NOR2X2TS U270 ( .A(n214), .B(n8), .Y(n55) );
INVX2TS U271 ( .A(n57), .Y(n20) );
NAND2X2TS U272 ( .A(n77), .B(in1[7]), .Y(n339) );
NAND2X2TS U273 ( .A(n117), .B(in1[14]), .Y(n306) );
NAND2X2TS U274 ( .A(n136), .B(in1[18]), .Y(n292) );
INVX2TS U275 ( .A(n138), .Y(n293) );
INVX2TS U276 ( .A(n281), .Y(n286) );
INVX2TS U277 ( .A(n282), .Y(n155) );
INVX2TS U278 ( .A(n285), .Y(n156) );
NAND2X2TS U279 ( .A(n286), .B(n61), .Y(n275) );
CLKBUFX2TS U280 ( .A(n272), .Y(n273) );
INVX2TS U281 ( .A(n261), .Y(n269) );
INVX2TS U282 ( .A(n268), .Y(n262) );
OAI21X1TS U283 ( .A0(n246), .A1(n256), .B0(n257), .Y(n247) );
NOR2X1TS U284 ( .A(n245), .B(n256), .Y(n248) );
INVX2TS U285 ( .A(n255), .Y(n245) );
NOR2XLTS U286 ( .A(n38), .B(in2[2]), .Y(n345) );
NAND2X1TS U287 ( .A(n30), .B(n342), .Y(n344) );
XNOR2X1TS U288 ( .A(n341), .B(n340), .Y(res[7]) );
NAND2X1TS U289 ( .A(n60), .B(n339), .Y(n341) );
NAND2X1TS U290 ( .A(n336), .B(n335), .Y(n337) );
INVX2TS U291 ( .A(n334), .Y(n336) );
NAND2X1TS U292 ( .A(n331), .B(n330), .Y(n332) );
INVX2TS U293 ( .A(n329), .Y(n331) );
NAND2X1TS U294 ( .A(n326), .B(n325), .Y(n327) );
INVX2TS U295 ( .A(n324), .Y(n326) );
NAND2X1TS U296 ( .A(n62), .B(n320), .Y(n321) );
AOI21X1TS U297 ( .A0(n322), .A1(n62), .B0(n315), .Y(n319) );
INVX2TS U298 ( .A(n320), .Y(n315) );
NAND2X1TS U299 ( .A(n312), .B(n311), .Y(n313) );
INVX2TS U300 ( .A(n310), .Y(n312) );
AOI21X1TS U301 ( .A0(n58), .A1(n297), .B0(n291), .Y(n295) );
INVX2TS U302 ( .A(n296), .Y(n291) );
XOR2XLTS U303 ( .A(n288), .B(n287), .Y(res[19]) );
XNOR2X1TS U304 ( .A(n284), .B(n283), .Y(res[20]) );
OAI21X1TS U305 ( .A0(n288), .A1(n281), .B0(n285), .Y(n284) );
XNOR2X1TS U306 ( .A(n280), .B(n279), .Y(res[21]) );
INVX2TS U307 ( .A(n276), .Y(n278) );
XNOR2X1TS U308 ( .A(n271), .B(n270), .Y(res[22]) );
XOR2X1TS U309 ( .A(n243), .B(n242), .Y(res[26]) );
INVX2TS U310 ( .A(n231), .Y(n233) );
NAND2X8TS U311 ( .A(n40), .B(n39), .Y(n38) );
OR2X4TS U312 ( .A(n95), .B(n96), .Y(n104) );
OR2X8TS U313 ( .A(n244), .B(n182), .Y(n35) );
AND2X4TS U314 ( .A(n37), .B(n348), .Y(n14) );
INVX12TS U315 ( .A(n38), .Y(n348) );
OAI21X4TS U316 ( .A0(n223), .A1(n209), .B0(n224), .Y(n208) );
AND2X8TS U317 ( .A(n102), .B(n101), .Y(n10) );
INVX2TS U318 ( .A(n22), .Y(n302) );
INVX2TS U319 ( .A(n42), .Y(n314) );
OR2X4TS U320 ( .A(n123), .B(in1[15]), .Y(n16) );
NAND3X8TS U321 ( .A(n17), .B(n23), .C(n26), .Y(n22) );
NAND2X8TS U322 ( .A(n27), .B(n42), .Y(n17) );
MX2X4TS U323 ( .A(in2[13]), .B(n115), .S0(add_sub), .Y(n116) );
OA21X4TS U324 ( .A0(n20), .A1(n214), .B0(n213), .Y(n52) );
NAND2X8TS U325 ( .A(n21), .B(n303), .Y(n301) );
NAND2X8TS U326 ( .A(n16), .B(n22), .Y(n21) );
NAND2X4TS U327 ( .A(n43), .B(n118), .Y(n26) );
NOR2X8TS U328 ( .A(n78), .B(n13), .Y(n338) );
NAND2X8TS U329 ( .A(n35), .B(n181), .Y(n228) );
AOI21X4TS U330 ( .A0(n272), .A1(n158), .B0(n36), .Y(n244) );
OAI21X4TS U331 ( .A0(n289), .A1(n140), .B0(n139), .Y(n272) );
INVX16TS U332 ( .A(in2[1]), .Y(n39) );
INVX16TS U333 ( .A(in2[0]), .Y(n40) );
NAND2X4TS U334 ( .A(n56), .B(n221), .Y(res[32]) );
NOR2X4TS U335 ( .A(in2[7]), .B(in2[6]), .Y(n80) );
MX2X4TS U336 ( .A(in2[11]), .B(n106), .S0(n201), .Y(n107) );
XOR2X4TS U337 ( .A(n172), .B(in2[22]), .Y(n173) );
XNOR2X4TS U338 ( .A(n167), .B(n168), .Y(n169) );
MXI2X4TS U339 ( .A(n166), .B(n165), .S0(n217), .Y(n177) );
AO21X4TS U340 ( .A0(n323), .A1(n94), .B0(n93), .Y(n42) );
NOR2X8TS U341 ( .A(n45), .B(n109), .Y(n44) );
NAND2X8TS U342 ( .A(n348), .B(n72), .Y(n356) );
NOR2X8TS U343 ( .A(in2[3]), .B(in2[2]), .Y(n72) );
OAI22X4TS U344 ( .A0(n51), .A1(n244), .B0(n181), .B1(n8), .Y(n50) );
NAND2X8TS U345 ( .A(n53), .B(n52), .Y(n222) );
NAND2X8TS U346 ( .A(n228), .B(n55), .Y(n53) );
OAI21X4TS U347 ( .A0(n229), .A1(n231), .B0(n232), .Y(n57) );
XOR2X1TS U348 ( .A(n253), .B(n252), .Y(res[25]) );
XOR2X1TS U349 ( .A(n267), .B(n266), .Y(res[23]) );
XOR2X1TS U350 ( .A(n260), .B(n259), .Y(res[24]) );
XNOR2X1TS U351 ( .A(n344), .B(n343), .Y(res[6]) );
XNOR2X4TS U352 ( .A(in2[14]), .B(n125), .Y(n112) );
XNOR2X1TS U353 ( .A(n301), .B(n300), .Y(res[16]) );
XNOR2X4TS U354 ( .A(n105), .B(in2[11]), .Y(n106) );
XOR2XLTS U355 ( .A(n338), .B(n337), .Y(res[8]) );
XOR2X4TS U356 ( .A(n10), .B(in2[12]), .Y(n103) );
NAND2X4TS U357 ( .A(n70), .B(in1[6]), .Y(n342) );
INVX2TS U358 ( .A(n83), .Y(n74) );
XOR2X4TS U359 ( .A(n73), .B(in2[7]), .Y(n75) );
NOR2BX4TS U360 ( .AN(n80), .B(n79), .Y(n81) );
NAND2X8TS U361 ( .A(n82), .B(n81), .Y(n95) );
OAI21X4TS U362 ( .A0(n338), .A1(n334), .B0(n335), .Y(n323) );
NOR2X8TS U363 ( .A(n92), .B(in1[10]), .Y(n324) );
OAI21X4TS U364 ( .A0(n324), .A1(n330), .B0(n325), .Y(n93) );
INVX2TS U365 ( .A(in2[11]), .Y(n98) );
INVX2TS U366 ( .A(in2[12]), .Y(n113) );
MXI2X4TS U367 ( .A(n103), .B(n113), .S0(n83), .Y(n108) );
NAND2X8TS U368 ( .A(n10), .B(n120), .Y(n125) );
XOR2X4TS U369 ( .A(n114), .B(in2[13]), .Y(n115) );
NOR2X8TS U370 ( .A(n116), .B(in1[13]), .Y(n310) );
NOR2X8TS U371 ( .A(n305), .B(n310), .Y(n118) );
NAND3X1TS U372 ( .A(n120), .B(n10), .C(n119), .Y(n121) );
XOR2X1TS U373 ( .A(n121), .B(in2[15]), .Y(n122) );
INVX2TS U374 ( .A(in2[16]), .Y(n127) );
XOR2X1TS U375 ( .A(in2[16]), .B(n160), .Y(n126) );
AOI21X4TS U376 ( .A0(n301), .A1(n63), .B0(n129), .Y(n289) );
INVX2TS U377 ( .A(n160), .Y(n130) );
INVX2TS U378 ( .A(in2[18]), .Y(n134) );
AOI2BB1X4TS U379 ( .A0N(n296), .A1N(n138), .B0(n137), .Y(n139) );
OAI2BB1X4TS U380 ( .A0N(add_sub), .A1N(n145), .B0(n144), .Y(n153) );
INVX2TS U381 ( .A(in2[20]), .Y(n149) );
MXI2X4TS U382 ( .A(n149), .B(n148), .S0(n217), .Y(n154) );
INVX2TS U383 ( .A(in2[21]), .Y(n151) );
AOI21X4TS U384 ( .A0(n156), .A1(n61), .B0(n155), .Y(n274) );
INVX2TS U385 ( .A(in2[25]), .Y(n162) );
INVX2TS U386 ( .A(in2[24]), .Y(n166) );
NOR3X4TS U387 ( .A(n171), .B(in2[22]), .C(n170), .Y(n167) );
MXI2X4TS U388 ( .A(n169), .B(n168), .S0(n83), .Y(n176) );
INVX2TS U389 ( .A(in2[22]), .Y(n174) );
MXI2X4TS U390 ( .A(n174), .B(n173), .S0(n201), .Y(n175) );
OAI21X4TS U391 ( .A0(n263), .A1(n268), .B0(n264), .Y(n254) );
AOI21X4TS U392 ( .A0(n254), .A1(n180), .B0(n179), .Y(n181) );
NAND2X2TS U393 ( .A(n183), .B(n187), .Y(n184) );
MXI2X4TS U394 ( .A(n186), .B(n185), .S0(n201), .Y(n193) );
XNOR2X1TS U395 ( .A(n191), .B(in2[28]), .Y(n192) );
MX2X4TS U396 ( .A(in2[28]), .B(n192), .S0(n217), .Y(n197) );
AOI21X4TS U397 ( .A0(n196), .A1(n59), .B0(n195), .Y(n229) );
XNOR2X1TS U398 ( .A(n204), .B(in2[29]), .Y(n202) );
XOR2X1TS U399 ( .A(n215), .B(in2[30]), .Y(n205) );
XNOR2X2TS U400 ( .A(n208), .B(n207), .Y(res[30]) );
XNOR2X4TS U401 ( .A(n222), .B(n220), .Y(res[31]) );
INVX2TS U402 ( .A(n223), .Y(n227) );
INVX12TS U403 ( .A(n228), .Y(n243) );
OAI21X4TS U404 ( .A0(n243), .A1(n230), .B0(n229), .Y(n235) );
XNOR2X4TS U405 ( .A(n235), .B(n234), .Y(res[28]) );
OAI21X4TS U406 ( .A0(n243), .A1(n236), .B0(n240), .Y(n239) );
XNOR2X4TS U407 ( .A(n239), .B(n238), .Y(res[27]) );
INVX2TS U408 ( .A(n254), .Y(n246) );
AOI21X4TS U409 ( .A0(n271), .A1(n248), .B0(n247), .Y(n253) );
AOI21X4TS U410 ( .A0(n271), .A1(n255), .B0(n254), .Y(n260) );
AOI21X4TS U411 ( .A0(n271), .A1(n269), .B0(n262), .Y(n267) );
XNOR2X1TS U412 ( .A(n298), .B(n297), .Y(res[17]) );
XNOR2X1TS U413 ( .A(n309), .B(n308), .Y(res[14]) );
XNOR2X1TS U414 ( .A(n322), .B(n321), .Y(res[11]) );
XNOR2X1TS U415 ( .A(n328), .B(n327), .Y(res[10]) );
XOR2X1TS U416 ( .A(n345), .B(in2[3]), .Y(n347) );
AOI21X1TS U417 ( .A0(n143), .A1(in2[3]), .B0(in1[3]), .Y(n346) );
XOR2X1TS U418 ( .A(in2[2]), .B(n348), .Y(n350) );
AOI21X1TS U419 ( .A0(n143), .A1(in2[2]), .B0(in1[2]), .Y(n349) );
XNOR2X1TS U420 ( .A(in2[0]), .B(in2[1]), .Y(n352) );
AOI21X1TS U421 ( .A0(n83), .A1(in2[1]), .B0(in1[1]), .Y(n351) );
XOR2X1TS U422 ( .A(n353), .B(in2[5]), .Y(n355) );
AOI21X1TS U423 ( .A0(n143), .A1(in2[5]), .B0(in1[5]), .Y(n354) );
XNOR2X1TS U424 ( .A(in2[4]), .B(n356), .Y(n358) );
AOI21X1TS U425 ( .A0(n143), .A1(in2[4]), .B0(in1[4]), .Y(n357) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL6_syn.sdf");
endmodule |
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule |
module NormaliseSum(
input [1:0] idle_AddState,
input [31:0] sout_AddState,
input [1:0] modeout_AddState,
input operationout_AddState,
input NatLogFlagout_AddState,
input [27:0] sum_AddState,
input [7:0] InsTag_AddState,
input clock,
output reg [1:0] idle_NormaliseSum,
output reg [31:0] sout_NormaliseSum,
output reg [1:0] modeout_NormaliseSum,
output reg operationout_NormaliseSum,
output reg NatLogFlagout_NormaliseSum,
output reg [27:0] sum_NormaliseSum,
output reg [7:0] InsTag_NormaliseSum
);
parameter mode_circular =2'b01,
mode_linear =2'b00,
mode_hyperbolic=2'b11;
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
wire [7:0] s_exponent;
assign s_exponent = sout_AddState[30:23];
always @ (posedge clock)
begin
InsTag_NormaliseSum <= InsTag_AddState;
idle_NormaliseSum <= idle_AddState;
modeout_NormaliseSum <= modeout_AddState;
operationout_NormaliseSum <= operationout_AddState;
NatLogFlagout_NormaliseSum <= NatLogFlagout_AddState;
if (idle_AddState != put_idle) begin
sout_NormaliseSum[31] <= sout_AddState[31];
sout_NormaliseSum[22:0] <= sout_AddState[22:0];
if (sum_AddState[27] == 1'b1) begin
sout_NormaliseSum[30:23] <= s_exponent + 1;
sum_NormaliseSum <= sum_AddState >> 1;
end
else if(sum_AddState[26:3] == 24'h000000) begin
sout_NormaliseSum[30:23] <= 10'h382;
end
else if (sum_AddState[26:4] == 23'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 23;
sum_NormaliseSum <= sum_AddState << 23;
end
else if (sum_AddState[26:5] == 22'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 22;
sum_NormaliseSum <= sum_AddState << 22;
end
else if (sum_AddState[26:6] == 21'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 21;
sum_NormaliseSum <= sum_AddState << 21;
end
else if (sum_AddState[26:7] == 20'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 20;
sum_NormaliseSum <= sum_AddState << 20;
end
else if (sum_AddState[26:8] == 19'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 19;
sum_NormaliseSum <= sum_AddState << 19;
end
else if (sum_AddState[26:9] == 18'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 18;
sum_NormaliseSum <= sum_AddState << 18;
end
else if (sum_AddState[26:10] == 17'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 17;
sum_NormaliseSum <= sum_AddState << 17;
end
else if (sum_AddState[26:11] == 16'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 16;
sum_NormaliseSum <= sum_AddState << 16;
end
else if (sum_AddState[26:12] == 15'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 15;
sum_NormaliseSum <= sum_AddState << 15;
end
else if (sum_AddState[26:13] == 14'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 14;
sum_NormaliseSum <= sum_AddState << 14;
end
else if (sum_AddState[26:14] == 13'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 13;
sum_NormaliseSum <= sum_AddState << 13;
end
else if (sum_AddState[26:15] == 12'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 12;
sum_NormaliseSum <= sum_AddState << 12;
end
else if (sum_AddState[26:16] == 11'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 11;
sum_NormaliseSum <= sum_AddState << 11;
end
else if (sum_AddState[26:17] == 10'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 10;
sum_NormaliseSum <= sum_AddState << 10;
end
else if (sum_AddState[26:18] == 9'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 9;
sum_NormaliseSum <= sum_AddState << 9;
end
else if (sum_AddState[26:19] == 8'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 8;
sum_NormaliseSum <= sum_AddState << 8;
end
else if (sum_AddState[26:20] == 7'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 7;
sum_NormaliseSum <= sum_AddState << 7;
end
else if (sum_AddState[26:21] == 6'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 6;
sum_NormaliseSum <= sum_AddState << 6;
end
else if (sum_AddState[26:22] == 5'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 5;
sum_NormaliseSum <= sum_AddState << 5;
end
else if (sum_AddState[26:23] == 4'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 4;
sum_NormaliseSum <= sum_AddState << 4;
end
else if (sum_AddState[26:24] == 3'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 3;
sum_NormaliseSum <= sum_AddState << 3;
end
else if (sum_AddState[26:25] == 2'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 2;
sum_NormaliseSum <= sum_AddState << 2;
end
else if (sum_AddState[26] == 1'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 1;
sum_NormaliseSum <= sum_AddState << 1;
end
else begin
sout_NormaliseSum[30:23] <= s_exponent;
sum_NormaliseSum <= sum_AddState;
end
end
else begin
sout_NormaliseSum <= sout_AddState;
sum_NormaliseSum <= 0;
end
end
endmodule |
module sky130_fd_sc_hs__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule |
module sky130_fd_sc_ms__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule |
module sky130_fd_sc_lp__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module bsg_dff_reset #(width_p=-1, harden_p=1)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
`bsg_dff_reset_macro(90)
else `bsg_dff_reset_macro(89)
else `bsg_dff_reset_macro(88)
else `bsg_dff_reset_macro(87)
else `bsg_dff_reset_macro(86)
else `bsg_dff_reset_macro(85)
else `bsg_dff_reset_macro(84)
else `bsg_dff_reset_macro(83)
else `bsg_dff_reset_macro(82)
else `bsg_dff_reset_macro(81)
else `bsg_dff_reset_macro(80)
else `bsg_dff_reset_macro(79)
else `bsg_dff_reset_macro(78)
else `bsg_dff_reset_macro(77)
else `bsg_dff_reset_macro(76)
else `bsg_dff_reset_macro(75)
else `bsg_dff_reset_macro(74)
else `bsg_dff_reset_macro(73)
else `bsg_dff_reset_macro(72)
else `bsg_dff_reset_macro(71)
else `bsg_dff_reset_macro(70)
else `bsg_dff_reset_macro(69)
else `bsg_dff_reset_macro(68)
else `bsg_dff_reset_macro(67)
else `bsg_dff_reset_macro(66)
else `bsg_dff_reset_macro(65)
else `bsg_dff_reset_macro(64)
else `bsg_dff_reset_macro(63)
else `bsg_dff_reset_macro(62)
else `bsg_dff_reset_macro(61)
else `bsg_dff_reset_macro(60)
else `bsg_dff_reset_macro(59)
else `bsg_dff_reset_macro(58)
else `bsg_dff_reset_macro(57)
else `bsg_dff_reset_macro(56)
else `bsg_dff_reset_macro(55)
else `bsg_dff_reset_macro(54)
else `bsg_dff_reset_macro(53)
else `bsg_dff_reset_macro(52)
else `bsg_dff_reset_macro(51)
else `bsg_dff_reset_macro(50)
else `bsg_dff_reset_macro(49)
else `bsg_dff_reset_macro(48)
else `bsg_dff_reset_macro(47)
else `bsg_dff_reset_macro(46)
else `bsg_dff_reset_macro(45)
else `bsg_dff_reset_macro(44)
else `bsg_dff_reset_macro(43)
else `bsg_dff_reset_macro(42)
else `bsg_dff_reset_macro(41)
else `bsg_dff_reset_macro(40)
else `bsg_dff_reset_macro(39)
else `bsg_dff_reset_macro(38)
else `bsg_dff_reset_macro(37)
else `bsg_dff_reset_macro(36)
else `bsg_dff_reset_macro(35)
else `bsg_dff_reset_macro(34)
else `bsg_dff_reset_macro(33)
else `bsg_dff_reset_macro(32)
else `bsg_dff_reset_macro(31)
else `bsg_dff_reset_macro(30)
else `bsg_dff_reset_macro(29)
else `bsg_dff_reset_macro(28)
else `bsg_dff_reset_macro(27)
else `bsg_dff_reset_macro(26)
else `bsg_dff_reset_macro(25)
else `bsg_dff_reset_macro(24)
else `bsg_dff_reset_macro(23)
else `bsg_dff_reset_macro(22)
else `bsg_dff_reset_macro(21)
else `bsg_dff_reset_macro(20)
else `bsg_dff_reset_macro(19)
else `bsg_dff_reset_macro(18)
else `bsg_dff_reset_macro(17)
else `bsg_dff_reset_macro(16)
else `bsg_dff_reset_macro(15)
else `bsg_dff_reset_macro(14)
else `bsg_dff_reset_macro(13)
else `bsg_dff_reset_macro(12)
else `bsg_dff_reset_macro(11)
else `bsg_dff_reset_macro(10)
else `bsg_dff_reset_macro(9)
else `bsg_dff_reset_macro(8)
else `bsg_dff_reset_macro(7)
else `bsg_dff_reset_macro(6)
else `bsg_dff_reset_macro(5)
else `bsg_dff_reset_macro(4)
else `bsg_dff_reset_macro(3)
else
begin: notmacro_dff_reset
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(posedge clk_i)
begin
if (reset_i)
data_r <= width_p ' (0);
else
data_r <= data_i;
end
end
endmodule |
module.
BOTTOM_MUX mux(.a(a), .b(b), .sel(sel), .y(y));
initial begin
a = 5'b01010;
b = 5'b10101;
sel = 1'b1;
#100;
a = 5'b00000;
#10;
sel = 1'b1;
#10;
b = 5'b11111;
#5;
a = 5'b00101;
#5;
sel = 1'b0;
b = 5'b11101;
#5;
sel = 1'bx;
end
always @ *
#1 $display("t = %0d sel =%b a = %b b = %b y = %b",
$time, sel, a, b, y);
endmodule |
module sky130_fd_sc_ls__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module instr_decoder_tb();
//Instructions
localparam ADDI = 0;
localparam ORI = 1;
localparam XORI = 2;
localparam ANDI = 3;
localparam SLTI = 4;
localparam SLTUI = 5;
localparam SLLI = 6;
localparam SRLI = 7;
localparam SRAI = 8;
localparam LUI = 9;
localparam AUIPC = 10;
localparam ADD = 11;
localparam SUB = 12;
localparam OR = 13;
localparam XOR = 14;
localparam AND = 15;
localparam SLT = 16;
localparam SLTU = 17;
localparam SLL = 18;
localparam SRL = 19;
localparam SRA = 20;
localparam JALR = 21;
localparam JAL = 22;
localparam SB = 23;
localparam SH = 24;
localparam SW = 25;
localparam LB = 26;
localparam LH = 27;
localparam LW = 28;
localparam LBU = 29;
localparam LHU = 30;
localparam BEQ = 31;
localparam BNE = 32;
localparam BLT = 33;
localparam BLTU = 34;
localparam BGE = 35;
localparam BGEU = 36;
localparam NUM_INSTRS = 37;
localparam OPCODE_IMM = 7'b0010011;
localparam OPCODE_LUI = 7'b0110111;
localparam OPCODE_AUIPC = 7'b0010111;
localparam OPCODE_OP = 7'b0110011;
localparam OPCODE_JAL = 7'b1101111;
localparam OPCODE_JALR = 7'b1100111;
localparam OPCODE_BRANCH = 7'b1100011;
localparam OPCODE_LOAD = 7'b0000011;
localparam OPCODE_STORE = 7'b0100011;
localparam OPCODE_MISC_MEM = 7'b0001111;
localparam OPCODE_SYSTEM = 7'b1110011;
localparam INSTR_ADD = 10'b0000000000;
localparam INSTR_SUB = 10'b0100000000;
localparam INSTR_OR = 10'b0000000110;
localparam INSTR_XOR = 10'b0000000100;
localparam INSTR_AND = 10'b0000000111;
localparam INSTR_SLT = 10'b0000000010;
localparam INSTR_SLTU = 10'b0000000011;
localparam INSTR_SLL = 10'b0000000001;
localparam INSTR_SRL = 10'b0000000101;
localparam INSTR_SRA = 10'b0100000101;
//MEM
localparam INSTR_LB = 3'b000;
localparam INSTR_LH = 3'b001;
localparam INSTR_LW = 3'b010;
localparam INSTR_LBU = 3'b100;
localparam INSTR_LHU = 3'b101;
localparam INSTR_SB = 3'b000;
localparam INSTR_SH = 3'b001;
localparam INSTR_SW = 3'b010;
//Branch
localparam INSTR_BEQ = 3'b000;
localparam INSTR_BNE = 3'b001;
localparam INSTR_BLT = 3'b100;
localparam INSTR_BGE = 3'b101;
localparam INSTR_BLTU = 3'b110;
localparam INSTR_BGEU = 3'b111;
//JALR
localparam INSTR_JALR = 3'b000;
task get_function_and_opcode(input integer instr_enum,
output [9:0] funct,
output [6:0] opcode);
begin
case (instr_enum)
ADDI : {funct, opcode} = {INSTR_ADD, OPCODE_IMM};
ORI : {funct, opcode} = {INSTR_OR, OPCODE_IMM};
XORI : {funct, opcode} = {INSTR_XOR, OPCODE_IMM};
ANDI : {funct, opcode} = {INSTR_AND, OPCODE_IMM};
SLTI : {funct, opcode} = {INSTR_SLT, OPCODE_IMM};
SLTUI: {funct, opcode} = {INSTR_SLTU, OPCODE_IMM};
SLLI : {funct, opcode} = {INSTR_SLL, OPCODE_IMM};
SRLI : {funct, opcode} = {INSTR_SRL, OPCODE_IMM};
SRAI : {funct, opcode} = {INSTR_SRA, OPCODE_IMM};
LUI : {funct, opcode} = {10'b0, OPCODE_LUI};
AUIPC: {funct, opcode} = {10'b0, OPCODE_AUIPC};
ADD : {funct, opcode} = {INSTR_ADD, OPCODE_OP};
SUB : {funct, opcode} = {INSTR_SUB, OPCODE_OP};
OR : {funct, opcode} = {INSTR_OR, OPCODE_OP};
XOR : {funct, opcode} = {INSTR_XOR, OPCODE_OP};
AND : {funct, opcode} = {INSTR_AND, OPCODE_OP};
SLT : {funct, opcode} = {INSTR_SLT, OPCODE_OP};
SLTU : {funct, opcode} = {INSTR_SLTU, OPCODE_OP};
SLL : {funct, opcode} = {INSTR_SLL, OPCODE_OP};
SRL : {funct, opcode} = {INSTR_SRL, OPCODE_OP};
SRA : {funct, opcode} = {INSTR_SRA, OPCODE_OP};
JALR : {funct, opcode} = {INSTR_JALR, OPCODE_JALR};
JAL : {funct, opcode} = {10'b0, OPCODE_JAL};
SB : {funct, opcode} = {INSTR_SB , OPCODE_STORE};
SH : {funct, opcode} = {INSTR_SH , OPCODE_STORE};
SW : {funct, opcode} = {INSTR_SW , OPCODE_STORE};
LB : {funct, opcode} = {INSTR_LB , OPCODE_LOAD};
LH : {funct, opcode} = {INSTR_LH , OPCODE_LOAD};
LW : {funct, opcode} = {INSTR_LW , OPCODE_LOAD};
LBU : {funct, opcode} = {INSTR_LBU , OPCODE_LOAD};
LHU : {funct, opcode} = {INSTR_LHU , OPCODE_LOAD};
BEQ : {funct, opcode} = {INSTR_BEQ , OPCODE_BRANCH};
BNE : {funct, opcode} = {INSTR_BNE , OPCODE_BRANCH};
BLT : {funct, opcode} = {INSTR_BLT , OPCODE_BRANCH};
BLTU : {funct, opcode} = {INSTR_BLTU, OPCODE_BRANCH};
BGE : {funct, opcode} = {INSTR_BGE , OPCODE_BRANCH};
BGEU : {funct, opcode} = {INSTR_BGEU, OPCODE_BRANCH};
endcase
end
endtask
function [31:0] sign_extend_imm (input integer high, low, input [31:0] data);
integer i;
reg sign_bit;
begin
sign_bit = data[high];
for (i = 0; i < 32; i = i + 1) begin
if (i < low)
sign_extend_imm[i] = 0;
else if (i > high)
sign_extend_imm[i] = sign_bit;
else
sign_extend_imm[i] = data[i];
end
end
endfunction
task generate_instruction(output [31:0] instr,
output integer instr_enum,
output [4:0] rsj, rsk, rsd,
output [31:0] immediate);
reg [31:0] rand_val;
reg [7:0] opcode;
reg [9:0] funct_l;
integer instr_enum_l;
reg [31:0] imm;
begin
rsj = 0;
rsk = 0;
rsd = 0;
immediate = 0;
instr_enum_l = $urandom % NUM_INSTRS;
get_function_and_opcode(instr_enum_l, funct_l, opcode);
instr_enum = instr_enum_l;
//rand_val = $urandom;
instr[6:0] = opcode;
case (opcode)
OPCODE_IMM : begin
rsj = $urandom % (1<<5);
rsd = $urandom % (1<<5);
imm = $urandom % (1<<12);
instr[11:7] = rsd;
instr[19:15] = rsj;
if (instr_enum_l == SRLI || instr_enum_l == SRAI || instr_enum_l == SRLI) begin
imm = imm & 'h1f;
instr[14:12] = funct_l[2:0];
instr[24:20] = imm[4:0];
instr[31:25] = funct_l[9:3];
end
else begin
instr[14:12] = funct_l[2:0];
instr[31:20] = imm[11:0];
end
immediate = sign_extend_imm(11, 0, imm);
end
OPCODE_LUI,
OPCODE_AUIPC : begin
rsd = $urandom % (1<<5);
imm = $urandom % (1<<20);
instr[11:7] = rsd;
instr[31:12] = imm[19:0];
immediate = sign_extend_imm(31, 12, imm);
end
OPCODE_OP : begin
rsk = $urandom % (1<<5);
rsj = $urandom % (1<<5);
rsd = $urandom % (1<<5);
instr[11:7] = rsd;
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[24:20] = rsk;
instr[31:25] = funct_l[9:3];
end
OPCODE_JAL : begin
rsd = $urandom % (1<<5);
imm = $urandom % (1<<20);
imm = imm << 1;
instr[11:7] = rsd;
instr[19:12] = imm[19:12];
instr[20] = imm[11];
instr[30:21] = imm[10:1];
instr[31] = imm[20];
immediate = sign_extend_imm(20, 1, imm);
end
OPCODE_JALR : begin
rsd = $urandom % (1<<5);
rsj = $urandom % (1<<5);
imm = $urandom % (1<<12);
instr[11:7] = rsd;
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[31:20] = imm[11:0];
immediate = sign_extend_imm(11, 0, imm);
end
OPCODE_BRANCH : begin
rsk = $urandom % (1<<5);
rsj = $urandom % (1<<5);
imm = $urandom % (1<<11);
imm = imm << 1;
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[24:20] = rsk;
instr[7] = imm[11];
instr[11:8] = imm[4:1];
instr[30:25] = imm[10:5];
instr[31] = imm[12];
immediate = sign_extend_imm(12, 1, imm);
end
OPCODE_LOAD : begin
rsd = $urandom % (1<<5);
rsj = $urandom % (1<<5);
imm = $urandom % (1<<12);
instr[11:7] = rsd;
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[31:20] = imm[11:0];
immediate = sign_extend_imm(11, 0, imm);
end
OPCODE_STORE : begin
rsk = $urandom % (1<<5);
rsj = $urandom % (1<<5);
imm = $urandom % (1<<12);
instr[11:7] = imm[4:0];
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[24:20] = rsj;
instr[31:25] = imm[11:5];
immediate = sign_extend_imm(11, 0, imm);
end
endcase
end
endtask
reg [31:0] instr;
integer instr_enum;
reg [4:0] rsj, rsk, rsd;
reg [31:0] immediate;
initial begin
repeat (100) begin
generate_instruction(instr, instr_enum, rsj, rsk, rsd, immediate);
$display("instr : %x instr_enum : %x rsj :%x rsk :%x rsd : %x immediate : %x",
instr, instr_enum, rsj, rsk, rsd, immediate);
end
end
endmodule |
module RAM32M #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output [1:0] DOA,
output [1:0] DOB,
output [1:0] DOC,
output [1:0] DOD,
input [4:0] ADDRA,
input [4:0] ADDRB,
input [4:0] ADDRC,
input [4:0] ADDRD,
input [1:0] DIA,
input [1:0] DIB,
input [1:0] DIC,
input [1:0] DID,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM32M";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire [4:0] ADDRD_in;
wire [1:0] DIA_in;
wire [1:0] DIB_in;
wire [1:0] DIC_in;
wire [1:0] DID_in;
wire WCLK_in;
wire WE_in;
`ifdef XIL_TIMING
wire [4:0] ADDRD_dly;
wire [1:0] DIA_dly;
wire [1:0] DIB_dly;
wire [1:0] DIC_dly;
wire [1:0] DID_dly;
wire WCLK_dly;
wire WE_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign ADDRD_in = ADDRD_dly;
assign DIA_in = DIA_dly;
assign DIB_in = DIB_dly;
assign DIC_in = DIC_dly;
assign DID_in = DID_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign ADDRD_in = ADDRD;
assign DIA_in = DIA;
assign DIB_in = DIB;
assign DIC_in = DIC;
assign DID_in = DID;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((INIT_A < 64'h0000000000000000) || (INIT_A > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-101] INIT_A attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_A);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_B < 64'h0000000000000000) || (INIT_B > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-102] INIT_B attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_B);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_C < 64'h0000000000000000) || (INIT_C > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-103] INIT_C attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_C);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_D < 64'h0000000000000000) || (INIT_D > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-104] INIT_D attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_D);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_WCLK_INVERTED !== 1'b0) && (IS_WCLK_INVERTED !== 1'b1))) begin
$display("Error: [Unisim %s-109] IS_WCLK_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_WCLK_INVERTED);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
reg [63:0] mem_a, mem_b, mem_c, mem_d;
reg [5:0] addr_in2, addr_in1;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
end
always @(ADDRD_in) begin
addr_in2 = 2 * ADDRD_in;
addr_in1 = 2 * ADDRD_in + 1;
end
always @(posedge WCLK_in)
if (WE_in) begin
mem_a[addr_in2] <= #100 DIA_in[0];
mem_a[addr_in1] <= #100 DIA_in[1];
mem_b[addr_in2] <= #100 DIB_in[0];
mem_b[addr_in1] <= #100 DIB_in[1];
mem_c[addr_in2] <= #100 DIC_in[0];
mem_c[addr_in1] <= #100 DIC_in[1];
mem_d[addr_in2] <= #100 DID_in[0];
mem_d[addr_in1] <= #100 DID_in[1];
end
assign DOA[0] = mem_a[2*ADDRA];
assign DOA[1] = mem_a[2*ADDRA + 1];
assign DOB[0] = mem_b[2*ADDRB];
assign DOB[1] = mem_b[2*ADDRB + 1];
assign DOC[0] = mem_c[2*ADDRC];
assign DOC[1] = mem_c[2*ADDRC + 1];
assign DOD[0] = mem_d[2*ADDRD_in];
assign DOD[1] = mem_d[2*ADDRD_in + 1];
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[addr_in2] <= 1'bx;
mem_a[addr_in1] <= 1'bx;
mem_b[addr_in2] <= 1'bx;
mem_b[addr_in1] <= 1'bx;
mem_c[addr_in2] <= 1'bx;
mem_c[addr_in1] <= 1'bx;
mem_d[addr_in2] <= 1'bx;
mem_d[addr_in1] <= 1'bx;
end
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => DOA[0]) = (0:0:0, 0:0:0);
(WCLK => DOA[1]) = (0:0:0, 0:0:0);
(WCLK => DOB[0]) = (0:0:0, 0:0:0);
(WCLK => DOB[1]) = (0:0:0, 0:0:0);
(WCLK => DOC[0]) = (0:0:0, 0:0:0);
(WCLK => DOC[1]) = (0:0:0, 0:0:0);
(WCLK => DOD[0]) = (0:0:0, 0:0:0);
(WCLK => DOD[1]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[0]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[1]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[0]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[1]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[0]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[1]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[0]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[1]) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule |
module mcm(
clk,rst,
i_valid,
inverse,
i_transize,
tq_sel_i,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_valid,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rst;
input i_valid;
input inverse;
input [1:0] i_transize;
input [1:0] tq_sel_i;
input signed [18:0] i_0;
input signed [18:0] i_1;
input signed [18:0] i_2;
input signed [18:0] i_3;
input signed [18:0] i_4;
input signed [18:0] i_5;
input signed [18:0] i_6;
input signed [18:0] i_7;
input signed [18:0] i_8;
input signed [18:0] i_9;
input signed [18:0] i_10;
input signed [18:0] i_11;
input signed [18:0] i_12;
input signed [18:0] i_13;
input signed [18:0] i_14;
input signed [18:0] i_15;
input signed [18:0] i_16;
input signed [18:0] i_17;
input signed [18:0] i_18;
input signed [18:0] i_19;
input signed [18:0] i_20;
input signed [18:0] i_21;
input signed [18:0] i_22;
input signed [18:0] i_23;
input signed [18:0] i_24;
input signed [18:0] i_25;
input signed [18:0] i_26;
input signed [18:0] i_27;
input signed [18:0] i_28;
input signed [18:0] i_29;
input signed [18:0] i_30;
input signed [18:0] i_31;
output reg o_valid;
output reg signed [27:0] o_0;
output reg signed [27:0] o_1;
output reg signed [27:0] o_2;
output reg signed [27:0] o_3;
output reg signed [27:0] o_4;
output reg signed [27:0] o_5;
output reg signed [27:0] o_6;
output reg signed [27:0] o_7;
output reg signed [27:0] o_8;
output reg signed [27:0] o_9;
output reg signed [27:0] o_10;
output reg signed [27:0] o_11;
output reg signed [27:0] o_12;
output reg signed [27:0] o_13;
output reg signed [27:0] o_14;
output reg signed [27:0] o_15;
output reg signed [27:0] o_16;
output reg signed [27:0] o_17;
output reg signed [27:0] o_18;
output reg signed [27:0] o_19;
output reg signed [27:0] o_20;
output reg signed [27:0] o_21;
output reg signed [27:0] o_22;
output reg signed [27:0] o_23;
output reg signed [27:0] o_24;
output reg signed [27:0] o_25;
output reg signed [27:0] o_26;
output reg signed [27:0] o_27;
output reg signed [27:0] o_28;
output reg signed [27:0] o_29;
output reg signed [27:0] o_30;
output reg signed [27:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [18:0] in_0;
wire signed [18:0] in_1;
wire signed [18:0] in_2;
wire signed [18:0] in_3;
wire signed [18:0] in_4;
wire signed [18:0] in_5;
wire signed [18:0] in_6;
wire signed [18:0] in_7;
wire signed [18:0] in_8;
wire signed [18:0] in_9;
wire signed [18:0] in_10;
wire signed [18:0] in_11;
wire signed [18:0] in_12;
wire signed [18:0] in_13;
wire signed [18:0] in_14;
wire signed [18:0] in_15;
wire signed [18:0] in_16;
wire signed [18:0] in_17;
wire signed [18:0] in_18;
wire signed [18:0] in_19;
wire signed [18:0] in_20;
wire signed [18:0] in_21;
wire signed [18:0] in_22;
wire signed [18:0] in_23;
wire signed [18:0] in_24;
wire signed [18:0] in_25;
wire signed [18:0] in_26;
wire signed [18:0] in_27;
wire signed [18:0] in_28;
wire signed [18:0] in_29;
wire signed [18:0] in_30;
wire signed [18:0] in_31;
wire signed [27:0] oms00_0;
wire signed [27:0] oms00_1;
wire signed [27:0] oms00_2;
wire signed [27:0] oms00_3;
wire signed [27:0] oms01_0;
wire signed [27:0] oms01_1;
wire signed [27:0] oms01_2;
wire signed [27:0] oms01_3;
wire signed [27:0] oms02_0;
wire signed [27:0] oms02_1;
wire signed [27:0] oms02_2;
wire signed [27:0] oms02_3;
wire signed [27:0] oms03_0;
wire signed [27:0] oms03_1;
wire signed [27:0] oms03_2;
wire signed [27:0] oms03_3;
wire signed [27:0] om00_0;
wire signed [27:0] om00_1;
wire signed [27:0] om00_2;
wire signed [27:0] om00_3;
wire signed [27:0] om01_0;
wire signed [27:0] om01_1;
wire signed [27:0] om01_2;
wire signed [27:0] om01_3;
wire signed [27:0] om02_0;
wire signed [27:0] om02_1;
wire signed [27:0] om02_2;
wire signed [27:0] om02_3;
wire signed [27:0] om03_0;
wire signed [27:0] om03_1;
wire signed [27:0] om03_2;
wire signed [27:0] om03_3;
wire signed [27:0] om40_0;
wire signed [27:0] om40_1;
wire signed [27:0] om40_2;
wire signed [27:0] om40_3;
wire signed [27:0] om41_0;
wire signed [27:0] om41_1;
wire signed [27:0] om41_2;
wire signed [27:0] om41_3;
wire signed [27:0] om42_0;
wire signed [27:0] om42_1;
wire signed [27:0] om42_2;
wire signed [27:0] om42_3;
wire signed [27:0] om43_0;
wire signed [27:0] om43_1;
wire signed [27:0] om43_2;
wire signed [27:0] om43_3;
wire signed [27:0] om80_0;
wire signed [27:0] om80_1;
wire signed [27:0] om80_2;
wire signed [27:0] om80_3;
wire signed [27:0] om80_4;
wire signed [27:0] om80_5;
wire signed [27:0] om80_6;
wire signed [27:0] om80_7;
wire signed [27:0] om81_0;
wire signed [27:0] om81_1;
wire signed [27:0] om81_2;
wire signed [27:0] om81_3;
wire signed [27:0] om81_4;
wire signed [27:0] om81_5;
wire signed [27:0] om81_6;
wire signed [27:0] om81_7;
wire signed [27:0] om160_0 ;
wire signed [27:0] om160_1 ;
wire signed [27:0] om160_2 ;
wire signed [27:0] om160_3 ;
wire signed [27:0] om160_4 ;
wire signed [27:0] om160_5 ;
wire signed [27:0] om160_6 ;
wire signed [27:0] om160_7 ;
wire signed [27:0] om160_8 ;
wire signed [27:0] om160_9 ;
wire signed [27:0] om160_10;
wire signed [27:0] om160_11;
wire signed [27:0] om160_12;
wire signed [27:0] om160_13;
wire signed [27:0] om160_14;
wire signed [27:0] om160_15;
// *********************************************
//
// REG DECLARATION
//
// **********************************************
reg i_valid_1;
reg signed [18:0] ims00_0;
reg signed [18:0] ims00_1;
reg signed [18:0] ims00_2;
reg signed [18:0] ims00_3;
reg signed [18:0] ims01_0;
reg signed [18:0] ims01_1;
reg signed [18:0] ims01_2;
reg signed [18:0] ims01_3;
reg signed [18:0] ims02_0;
reg signed [18:0] ims02_1;
reg signed [18:0] ims02_2;
reg signed [18:0] ims02_3;
reg signed [18:0] ims03_0;
reg signed [18:0] ims03_1;
reg signed [18:0] ims03_2;
reg signed [18:0] ims03_3;
reg signed [18:0] im00_0;
reg signed [18:0] im00_1;
reg signed [18:0] im00_2;
reg signed [18:0] im00_3;
reg signed [18:0] im01_0;
reg signed [18:0] im01_1;
reg signed [18:0] im01_2;
reg signed [18:0] im01_3;
reg signed [18:0] im02_0;
reg signed [18:0] im02_1;
reg signed [18:0] im02_2;
reg signed [18:0] im02_3;
reg signed [18:0] im03_0;
reg signed [18:0] im03_1;
reg signed [18:0] im03_2;
reg signed [18:0] im03_3;
reg signed [18:0] im40_0;
reg signed [18:0] im40_1;
reg signed [18:0] im40_2;
reg signed [18:0] im40_3;
reg signed [18:0] im41_0;
reg signed [18:0] im41_1;
reg signed [18:0] im41_2;
reg signed [18:0] im41_3;
reg signed [18:0] im42_0;
reg signed [18:0] im42_1;
reg signed [18:0] im42_2;
reg signed [18:0] im42_3;
reg signed [18:0] im43_0;
reg signed [18:0] im43_1;
reg signed [18:0] im43_2;
reg signed [18:0] im43_3;
reg signed [17:0] im80_0;
reg signed [17:0] im80_1;
reg signed [17:0] im80_2;
reg signed [17:0] im80_3;
reg signed [17:0] im80_4;
reg signed [17:0] im80_5;
reg signed [17:0] im80_6;
reg signed [17:0] im80_7;
reg signed [17:0] im81_0;
reg signed [17:0] im81_1;
reg signed [17:0] im81_2;
reg signed [17:0] im81_3;
reg signed [17:0] im81_4;
reg signed [17:0] im81_5;
reg signed [17:0] im81_6;
reg signed [17:0] im81_7;
reg signed [16:0] im160_0 ;
reg signed [16:0] im160_1 ;
reg signed [16:0] im160_2 ;
reg signed [16:0] im160_3 ;
reg signed [16:0] im160_4 ;
reg signed [16:0] im160_5 ;
reg signed [16:0] im160_6 ;
reg signed [16:0] im160_7 ;
reg signed [16:0] im160_8 ;
reg signed [16:0] im160_9 ;
reg signed [16:0] im160_10;
reg signed [16:0] im160_11;
reg signed [16:0] im160_12;
reg signed [16:0] im160_13;
reg signed [16:0] im160_14;
reg signed [16:0] im160_15;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign in_0=i_valid?i_0:'b0;
assign in_1=i_valid?i_1:'b0;
assign in_2=i_valid?i_2:'b0;
assign in_3=i_valid?i_3:'b0;
assign in_4=i_valid?i_4:'b0;
assign in_5=i_valid?i_5:'b0;
assign in_6=i_valid?i_6:'b0;
assign in_7=i_valid?i_7:'b0;
assign in_8=i_valid?i_8:'b0;
assign in_9=i_valid?i_9:'b0;
assign in_10=i_valid?i_10:'b0;
assign in_11=i_valid?i_11:'b0;
assign in_12=i_valid?i_12:'b0;
assign in_13=i_valid?i_13:'b0;
assign in_14=i_valid?i_14:'b0;
assign in_15=i_valid?i_15:'b0;
assign in_16=i_valid?i_16:'b0;
assign in_17=i_valid?i_17:'b0;
assign in_18=i_valid?i_18:'b0;
assign in_19=i_valid?i_19:'b0;
assign in_20=i_valid?i_20:'b0;
assign in_21=i_valid?i_21:'b0;
assign in_22=i_valid?i_22:'b0;
assign in_23=i_valid?i_23:'b0;
assign in_24=i_valid?i_24:'b0;
assign in_25=i_valid?i_25:'b0;
assign in_26=i_valid?i_26:'b0;
assign in_27=i_valid?i_27:'b0;
assign in_28=i_valid?i_28:'b0;
assign in_29=i_valid?i_29:'b0;
assign in_30=i_valid?i_30:'b0;
assign in_31=i_valid?i_31:'b0;
always@(*)
case(i_transize)
2'b00: if(!tq_sel_i[1])
begin
im00_0='b0;im00_1='b0;im00_2='b0;im00_3='b0;
im01_0='b0;im01_1='b0;im01_2='b0;im01_3='b0;
im02_0='b0;im02_1='b0;im02_2='b0;im02_3='b0;
im03_0='b0;im03_1='b0;im03_2='b0;im03_3='b0;
im40_0='b0;im40_1='b0;im40_2='b0;im40_3='b0;
im41_0='b0;im41_1='b0;im41_2='b0;im41_3='b0;
im42_0='b0;im42_1='b0;im42_2='b0;im42_3='b0;
im43_0='b0;im43_1='b0;im43_2='b0;im43_3='b0;
im80_0='b0;im80_1='b0;im80_2='b0;im80_3='b0;
im80_4='b0;im80_5='b0;im80_6='b0;im80_7='b0;
im81_0='b0;im81_1='b0;im81_2='b0;im81_3='b0;
im81_4='b0;im81_5='b0;im81_6='b0;im81_7='b0;
im160_0 ='b0;im160_1 ='b0;im160_2 ='b0;im160_3 ='b0;
im160_4 ='b0;im160_5 ='b0;im160_6 ='b0;im160_7 ='b0;
im160_8 ='b0;im160_9 ='b0;im160_10='b0;im160_11='b0;
im160_12='b0;im160_13='b0;im160_14='b0;im160_15='b0;
ims00_0=in_0 ;
ims00_1=in_1 ;
ims00_2=in_2 ;
ims00_3=in_3 ;
ims01_0=in_8 ;
ims01_1=in_9 ;
ims01_2=in_10;
ims01_3=in_11;
ims02_0=in_16;
ims02_1=in_17;
ims02_2=in_18;
ims02_3=in_19;
ims03_0=in_24;
ims03_1=in_25;
ims03_2=in_26;
ims03_3=in_27;
o_0 =oms00_0;
o_1 =oms00_1;
o_2 =oms00_2;
o_3 =oms00_3;
o_4=28'b0;
o_5=28'b0;
o_6=28'b0;
o_7=28'b0;
o_8 =oms01_0;
o_9 =oms01_1;
o_10 =oms01_2;
o_11 =oms01_3;
o_12=28'b0;
o_13=28'b0;
o_14=28'b0;
o_15=28'b0;
o_16=oms02_0;
o_17=oms02_1;
o_18=oms02_2;
o_19=oms02_3;
o_20=28'b0;
o_21=28'b0;
o_22=28'b0;
o_23=28'b0;
o_24=oms03_0;
o_25=oms03_1;
o_26=oms03_2;
o_27=oms03_3;
o_28=28'b0;
o_29=28'b0;
o_30=28'b0;
o_31=28'b0;
end
else begin
ims00_0='b0;ims00_1='b0;ims00_2='b0;ims00_3='b0;
ims01_0='b0;ims01_1='b0;ims01_2='b0;ims01_3='b0;
ims02_0='b0;ims02_1='b0;ims02_2='b0;ims02_3='b0;
ims03_0='b0;ims03_1='b0;ims03_2='b0;ims03_3='b0;
im40_0='b0;im40_1='b0;im40_2='b0;im40_3='b0;
im41_0='b0;im41_1='b0;im41_2='b0;im41_3='b0;
im42_0='b0;im42_1='b0;im42_2='b0;im42_3='b0;
im43_0='b0;im43_1='b0;im43_2='b0;im43_3='b0;
im80_0='b0;im80_1='b0;im80_2='b0;im80_3='b0;
im80_4='b0;im80_5='b0;im80_6='b0;im80_7='b0;
im81_0='b0;im81_1='b0;im81_2='b0;im81_3='b0;
im81_4='b0;im81_5='b0;im81_6='b0;im81_7='b0;
im160_0 ='b0;im160_1 ='b0;im160_2 ='b0;im160_3 ='b0;
im160_4 ='b0;im160_5 ='b0;im160_6 ='b0;im160_7 ='b0;
im160_8 ='b0;im160_9 ='b0;im160_10='b0;im160_11='b0;
im160_12='b0;im160_13='b0;im160_14='b0;im160_15='b0;
im00_0=in_0 ;
im00_1=in_1 ;
im00_2=in_2 ;
im00_3=in_3 ;
im01_0=in_8 ;
im01_1=in_9 ;
im01_2=in_10;
im01_3=in_11;
im02_0=in_16;
im02_1=in_17;
im02_2=in_18;
im02_3=in_19;
im03_0=in_24;
im03_1=in_25;
im03_2=in_26;
im03_3=in_27;
o_0 =om00_0;
o_1 =om00_1;
o_2 =om00_2;
o_3 =om00_3;
o_4=28'b0;
o_5=28'b0;
o_6=28'b0;
o_7=28'b0;
o_8 =om01_0;
o_9 =om01_1;
o_10 =om01_2;
o_11 =om01_3;
o_12=28'b0;
o_13=28'b0;
o_14=28'b0;
o_15=28'b0;
o_16=om02_0;
o_17=om02_1;
o_18=om02_2;
o_19=om02_3;
o_20=28'b0;
o_21=28'b0;
o_22=28'b0;
o_23=28'b0;
o_24=om03_0;
o_25=om03_1;
o_26=om03_2;
o_27=om03_3;
o_28=28'b0;
o_29=28'b0;
o_30=28'b0;
o_31=28'b0;
end
2'b01:begin
im00_0=in_0;
im00_1=in_1;
im00_2=in_2;
im00_3=in_3;
im40_0=in_4;
im40_1=in_5;
im40_2=in_6;
im40_3=in_7;
im01_0=in_8 ;
im01_1=in_9 ;
im01_2=in_10;
im01_3=in_11;
im41_0=in_12;
im41_1=in_13;
im41_2=in_14;
im41_3=in_15;
im02_0=in_16;
im02_1=in_17;
im02_2=in_18;
im02_3=in_19;
im42_0=in_20;
im42_1=in_21;
im42_2=in_22;
im42_3=in_23;
im03_0=in_24;
im03_1=in_25;
im03_2=in_26;
im03_3=in_27;
im43_0=in_28;
im43_1=in_29;
im43_2=in_30;
im43_3=in_31;
ims00_0='b0;ims00_1='b0;ims00_2='b0;ims00_3='b0;
ims01_0='b0;ims01_1='b0;ims01_2='b0;ims01_3='b0;
ims02_0='b0;ims02_1='b0;ims02_2='b0;ims02_3='b0;
ims03_0='b0;ims03_1='b0;ims03_2='b0;ims03_3='b0;
im80_0='b0;im80_1='b0;im80_2='b0;im80_3='b0;
im80_4='b0;im80_5='b0;im80_6='b0;im80_7='b0;
im81_0='b0;im81_1='b0;im81_2='b0;im81_3='b0;
im81_4='b0;im81_5='b0;im81_6='b0;im81_7='b0;
im160_0 ='b0;im160_1 ='b0;im160_2 ='b0;im160_3 ='b0;
im160_4 ='b0;im160_5 ='b0;im160_6 ='b0;im160_7 ='b0;
im160_8 ='b0;im160_9 ='b0;im160_10='b0;im160_11='b0;
im160_12='b0;im160_13='b0;im160_14='b0;im160_15='b0;
o_0=om00_0;
o_1=om00_1;
o_2=om00_2;
o_3=om00_3;
o_4=om40_0;
o_5=om40_1;
o_6=om40_2;
o_7=om40_3;
o_8 =om01_0;
o_9 =om01_1;
o_10=om01_2;
o_11=om01_3;
o_12=om41_0;
o_13=om41_1;
o_14=om41_2;
o_15=om41_3;
o_16=om02_0;
o_17=om02_1;
o_18=om02_2;
o_19=om02_3;
o_20=om42_0;
o_21=om42_1;
o_22=om42_2;
o_23=om42_3;
o_24=om03_0;
o_25=om03_1;
o_26=om03_2;
o_27=om03_3;
o_28=om43_0;
o_29=om43_1;
o_30=om43_2;
o_31=om43_3;
end
2'b10:begin
ims00_0='b0;ims00_1='b0;ims00_2='b0;ims00_3='b0;
ims01_0='b0;ims01_1='b0;ims01_2='b0;ims01_3='b0;
ims02_0='b0;ims02_1='b0;ims02_2='b0;ims02_3='b0;
ims03_0='b0;ims03_1='b0;ims03_2='b0;ims03_3='b0;
im02_0='b0;im02_1='b0;im02_2='b0;im02_3='b0;
im03_0='b0;im03_1='b0;im03_2='b0;im03_3='b0;
im42_0='b0;im42_1='b0;im42_2='b0;im42_3='b0;
im43_0='b0;im43_1='b0;im43_2='b0;im43_3='b0;
im160_0 ='b0;im160_1 ='b0;im160_2 ='b0;im160_3 ='b0;
im160_4 ='b0;im160_5 ='b0;im160_6 ='b0;im160_7 ='b0;
im160_8 ='b0;im160_9 ='b0;im160_10='b0;im160_11='b0;
im160_12='b0;im160_13='b0;im160_14='b0;im160_15='b0;
im00_0=in_0 ;
im00_1=in_1 ;
im00_2=in_2 ;
im00_3=in_3 ;
im40_0=in_4 ;
im40_1=in_5 ;
im40_2=in_6 ;
im40_3=in_7 ;
im80_0=in_8 ;
im80_1=in_9 ;
im80_2=in_10;
im80_3=in_11;
im80_4=in_12;
im80_5=in_13;
im80_6=in_14;
im80_7=in_15;
im01_0=in_16;
im01_1=in_17;
im01_2=in_18;
im01_3=in_19;
im41_0=in_20;
im41_1=in_21;
im41_2=in_22;
im41_3=in_23;
im81_0=in_24;
im81_1=in_25;
im81_2=in_26;
im81_3=in_27;
im81_4=in_28;
im81_5=in_29;
im81_6=in_30;
im81_7=in_31;
o_0 =om00_0;
o_1 =om00_1;
o_2 =om00_2;
o_3 =om00_3;
o_4 =om40_0;
o_5 =om40_1;
o_6 =om40_2;
o_7 =om40_3;
o_8 =om80_0;
o_9 =om80_1;
o_10=om80_2;
o_11=om80_3;
o_12=om80_4;
o_13=om80_5;
o_14=om80_6;
o_15=om80_7;
o_16=om01_0;
o_17=om01_1;
o_18=om01_2;
o_19=om01_3;
o_20=om41_0;
o_21=om41_1;
o_22=om41_2;
o_23=om41_3;
o_24=om81_0;
o_25=om81_1;
o_26=om81_2;
o_27=om81_3;
o_28=om81_4;
o_29=om81_5;
o_30=om81_6;
o_31=om81_7;
end
2'b11:begin
ims00_0='b0;ims00_1='b0;ims00_2='b0;ims00_3='b0;
ims01_0='b0;ims01_1='b0;ims01_2='b0;ims01_3='b0;
ims02_0='b0;ims02_1='b0;ims02_2='b0;ims02_3='b0;
ims03_0='b0;ims03_1='b0;ims03_2='b0;ims03_3='b0;
im01_0='b0;im01_1='b0;im01_2='b0;im01_3='b0;
im02_0='b0;im02_1='b0;im02_2='b0;im02_3='b0;
im03_0='b0;im03_1='b0;im03_2='b0;im03_3='b0;
im41_0='b0;im41_1='b0;im41_2='b0;im41_3='b0;
im42_0='b0;im42_1='b0;im42_2='b0;im42_3='b0;
im43_0='b0;im43_1='b0;im43_2='b0;im43_3='b0;
im81_0='b0;im81_1='b0;im81_2='b0;im81_3='b0;
im81_4='b0;im81_5='b0;im81_6='b0;im81_7='b0;
im00_0=in_0 ;
im00_1=in_1 ;
im00_2=in_2 ;
im00_3=in_3 ;
im40_0=in_4 ;
im40_1=in_5 ;
im40_2=in_6 ;
im40_3=in_7 ;
im80_0=in_8 ;
im80_1=in_9 ;
im80_2=in_10;
im80_3=in_11;
im80_4=in_12;
im80_5=in_13;
im80_6=in_14;
im80_7=in_15;
im160_0=in_16;
im160_1=in_17;
im160_2=in_18;
im160_3=in_19;
im160_4=in_20;
im160_5=in_21;
im160_6=in_22;
im160_7=in_23;
im160_8=in_24;
im160_9=in_25;
im160_10=in_26;
im160_11=in_27;
im160_12=in_28;
im160_13=in_29;
im160_14=in_30;
im160_15=in_31;
o_0 =om00_0;
o_1 =om00_1;
o_2 =om00_2;
o_3 =om00_3;
o_4 =om40_0;
o_5 =om40_1;
o_6 =om40_2;
o_7 =om40_3;
o_8 =om80_0;
o_9 =om80_1;
o_10=om80_2;
o_11=om80_3;
o_12=om80_4;
o_13=om80_5;
o_14=om80_6;
o_15=om80_7;
o_16=om160_0 ;
o_17=om160_1 ;
o_18=om160_2 ;
o_19=om160_3 ;
o_20=om160_4 ;
o_21=om160_5 ;
o_22=om160_6 ;
o_23=om160_7 ;
o_24=om160_8 ;
o_25=om160_9 ;
o_26=om160_10;
o_27=om160_11;
o_28=om160_12;
o_29=om160_13;
o_30=om160_14;
o_31=om160_15;
end
endcase
// ********************************************
//
// Sequence Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
i_valid_1<=1'b0;
else
i_valid_1<=i_valid;
always@(posedge clk or negedge rst)
if(!rst)
o_valid<=1'b0;
else
o_valid<=i_valid_1;
// ********************************************
//
// Sub Modules
//
// ********************************************
dst dst_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(ims00_0),
.i_1(ims00_1),
.i_2(ims00_2),
.i_3(ims00_3),
.o_0(oms00_0),
.o_1(oms00_1),
.o_2(oms00_2),
.o_3(oms00_3)
);
dst dst_1(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(ims01_0),
.i_1(ims01_1),
.i_2(ims01_2),
.i_3(ims01_3),
.o_0(oms01_0),
.o_1(oms01_1),
.o_2(oms01_2),
.o_3(oms01_3)
);
dst dst_2(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(ims02_0),
.i_1(ims02_1),
.i_2(ims02_2),
.i_3(ims02_3),
.o_0(oms02_0),
.o_1(oms02_1),
.o_2(oms02_2),
.o_3(oms02_3)
);
dst dst_3(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(ims03_0),
.i_1(ims03_1),
.i_2(ims03_2),
.i_3(ims03_3),
.o_0(oms03_0),
.o_1(oms03_1),
.o_2(oms03_2),
.o_3(oms03_3)
);
mcm_0 m0_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im00_0),
.i_1(im00_1),
.i_2(im00_2),
.i_3(im00_3),
.o_0(om00_0),
.o_1(om00_1),
.o_2(om00_2),
.o_3(om00_3)
);
mcm_0 m0_1(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im01_0),
.i_1(im01_1),
.i_2(im01_2),
.i_3(im01_3),
.o_0(om01_0),
.o_1(om01_1),
.o_2(om01_2),
.o_3(om01_3)
);
mcm_0 m0_2(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im02_0),
.i_1(im02_1),
.i_2(im02_2),
.i_3(im02_3),
.o_0(om02_0),
.o_1(om02_1),
.o_2(om02_2),
.o_3(om02_3)
);
mcm_0 m0_3(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im03_0),
.i_1(im03_1),
.i_2(im03_2),
.i_3(im03_3),
.o_0(om03_0),
.o_1(om03_1),
.o_2(om03_2),
.o_3(om03_3)
);
mcm_4 m4_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im40_0),
.i_1(im40_1),
.i_2(im40_2),
.i_3(im40_3),
.m1_0(om40_0),
.m1_1(om40_1),
.m1_2(om40_2),
.m1_3(om40_3)
);
mcm_4 m4_1(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im41_0),
.i_1(im41_1),
.i_2(im41_2),
.i_3(im41_3),
.m1_0(om41_0),
.m1_1(om41_1),
.m1_2(om41_2),
.m1_3(om41_3)
);
mcm_4 m4_2(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im42_0),
.i_1(im42_1),
.i_2(im42_2),
.i_3(im42_3),
.m1_0(om42_0),
.m1_1(om42_1),
.m1_2(om42_2),
.m1_3(om42_3)
);
mcm_4 m4_3(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im43_0),
.i_1(im43_1),
.i_2(im43_2),
.i_3(im43_3),
.m1_0(om43_0),
.m1_1(om43_1),
.m1_2(om43_2),
.m1_3(om43_3)
);
mcm_8 m8_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im80_0),
.i_1(im80_1),
.i_2(im80_2),
.i_3(im80_3),
.i_4(im80_4),
.i_5(im80_5),
.i_6(im80_6),
.i_7(im80_7),
.m2_0(om80_0),
.m2_1(om80_1),
.m2_2(om80_2),
.m2_3(om80_3),
.m2_4(om80_4),
.m2_5(om80_5),
.m2_6(om80_6),
.m2_7(om80_7)
);
mcm_8 m8_1(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im81_0),
.i_1(im81_1),
.i_2(im81_2),
.i_3(im81_3),
.i_4(im81_4),
.i_5(im81_5),
.i_6(im81_6),
.i_7(im81_7),
.m2_0(om81_0),
.m2_1(om81_1),
.m2_2(om81_2),
.m2_3(om81_3),
.m2_4(om81_4),
.m2_5(om81_5),
.m2_6(om81_6),
.m2_7(om81_7)
);
mcm_16 m16_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im160_0),
.i_1(im160_1),
.i_2(im160_2),
.i_3(im160_3),
.i_4(im160_4),
.i_5(im160_5),
.i_6(im160_6),
.i_7(im160_7),
.i_8(im160_8),
.i_9(im160_9),
.i_10(im160_10),
.i_11(im160_11),
.i_12(im160_12),
.i_13(im160_13),
.i_14(im160_14),
.i_15(im160_15),
.m3_0(om160_0),
.m3_1(om160_1),
.m3_2(om160_2),
.m3_3(om160_3),
.m3_4(om160_4),
.m3_5(om160_5),
.m3_6(om160_6),
.m3_7(om160_7),
.m3_8(om160_8),
.m3_9(om160_9),
.m3_10(om160_10),
.m3_11(om160_11),
.m3_12(om160_12),
.m3_13(om160_13),
.m3_14(om160_14),
.m3_15(om160_15)
);
endmodule |
module mem_ctrl (
// -- Clock & Reset
input sdram_clk,
input sdram_rst_,
// -- dwrite
input wr_req,
output wr_valid,
input [31:0] wr_addr,
input [15:0] wr_data,
// -- dread
input rd_req,
output rd_valid,
input [31:0] rd_addr,
output rd_rdy,
output [15:0] rd_data,
output sd_init_done,
// -- SDRAM Signals
output [12:0] sdram_addr,
output [1:0] sdram_ba,
inout [15:0] sdram_dq,
output sdram_ras_,
output sdram_cas_,
output sdram_we_,
output sdram_dqml,
output sdram_dqmh,
output sdram_cke,
output sdram_cs_
);
// --
// internal signals definition
// --
wire [15:0] sdram_dqo;
wire [15:0] sdram_dqi;
wire [15:0] sdram_dq_oe;
wire STOP_CLK;
wire PAA;
wire SET_MODE;
wire [2:0] BLK_SIZE; // Burst Length
// 3'b000: 1, 3'b001: 2, 3'b010: 4, 3'b011: 8
// if IS_SEQ == 1'b0, 3'b111: full page
wire IS_SEQ; // Burst Type
// 1'b0: Sequential, 1'b1: Interleaved
wire MODULE_BK_NUM; // Not Used
wire [1:0] ROW_SIZE; // 2'b00 : A0-A10, 2'b01 : A0-A11, 2'b10 : A0-A12
wire [1:0] BIT_SIZE; // 2'b00 : 4, 2'b01 : 8, 2'b10 : 16, 2'b11 : 32
wire BK_SIZE; // 1'b0 : B0, 1'b1 : B0-B1
wire [2:0] COL_SIZE; // 3'b000: A0-A7 3'b001: A0-A8 3'b010: A0-A9
// 3'b011: A0-A9,A11 3'b100: A0-A9, A11, A12
wire [1:0] tRCD;
wire [1:0] tCAS;
wire [1:0] tRP;
wire [2:0] tRAS;
wire [11:0] tREF;
wire [3:0] tRC;
wire [31:0] sys_addr;
wire sys_rd;
wire sys_wr;
wire [15:0] sys_wdata;
wire [15:0] sys_rdata;
wire sys_rd_rdy;
wire sys_burst_rdy;
wire [12:0] isdram_addr;
wire [1:0] isdram_ba;
wire [15:0] isdram_dqi;
wire [15:0] isdram_dqo;
wire isdram_dq_oe;
wire isdram_ras_;
wire isdram_cas_;
wire isdram_we_;
wire isdram_dqm;
wire isdram_cke;
wire isdram_cs_;
assign sd_init_done = PAA;
// --
// dwrite/dread access mux
// --
assign sys_addr = wr_req ? wr_addr : rd_addr;
assign sys_rd = rd_req;
assign sys_wr = wr_req;
assign sys_wdata = wr_data;
assign rd_data = sys_rdata;
assign wr_valid = wr_req & sys_burst_rdy;
assign rd_valid = rd_req & sys_burst_rdy;
assign rd_rdy = sys_rd_rdy;
// --
// sdram_clk output
// --
assign sdram_dq[0] = sdram_dq_oe[0] ? sdram_dqo[0] : 1'Hz;
assign sdram_dq[1] = sdram_dq_oe[1] ? sdram_dqo[1] : 1'Hz;
assign sdram_dq[2] = sdram_dq_oe[2] ? sdram_dqo[2] : 1'Hz;
assign sdram_dq[3] = sdram_dq_oe[3] ? sdram_dqo[3] : 1'Hz;
assign sdram_dq[4] = sdram_dq_oe[4] ? sdram_dqo[4] : 1'Hz;
assign sdram_dq[5] = sdram_dq_oe[5] ? sdram_dqo[5] : 1'Hz;
assign sdram_dq[6] = sdram_dq_oe[6] ? sdram_dqo[6] : 1'Hz;
assign sdram_dq[7] = sdram_dq_oe[7] ? sdram_dqo[7] : 1'Hz;
assign sdram_dq[8] = sdram_dq_oe[8] ? sdram_dqo[8] : 1'Hz;
assign sdram_dq[9] = sdram_dq_oe[9] ? sdram_dqo[9] : 1'Hz;
assign sdram_dq[10] = sdram_dq_oe[10] ? sdram_dqo[10] : 1'Hz;
assign sdram_dq[11] = sdram_dq_oe[11] ? sdram_dqo[11] : 1'Hz;
assign sdram_dq[12] = sdram_dq_oe[12] ? sdram_dqo[12] : 1'Hz;
assign sdram_dq[13] = sdram_dq_oe[13] ? sdram_dqo[13] : 1'Hz;
assign sdram_dq[14] = sdram_dq_oe[14] ? sdram_dqo[14] : 1'Hz;
assign sdram_dq[15] = sdram_dq_oe[15] ? sdram_dqo[15] : 1'Hz;
assign sdram_dqi = sdram_dq;
// --
// sdram parameter
// --
assign STOP_CLK = 1'b0; // Never Stop Clock
assign BLK_SIZE = 3'b000; // Burst length = 8
assign IS_SEQ = 1'b0; // Sequential
assign MODULE_BK_NUM = 1'b1;
assign ROW_SIZE = 2'b10; // A0-A12
assign BIT_SIZE = 2'b10; // 16
assign BK_SIZE = 1'b1; // B0-B1
assign COL_SIZE = 3'b001; // A0-A8
assign tRCD = 2'b10; // tRCD - 1
assign tCAS = 2'b11;
assign tRP = 2'b11;
assign tRAS = 3'b110;
assign tREF = 12'd257;
assign tRC = 4'b1000;
// --
// instant
// --
sdram_init sdram_init_x(
.sdram_clk(sdram_clk), .sdram_rst_(sdram_rst_),
//.CKE_IN(CKE), .CKE_OUT(CKE_OUT),
.PAA(PAA), .SET_MODE(SET_MODE)
);
sdram_ctl sdram_ctl(
.CLK(sdram_clk), .RST_(sdram_rst_),
// REG interface
.STOP_CLK(STOP_CLK), .PAA(PAA), .SET_MODE(SET_MODE), .BLK_SIZE(BLK_SIZE), .IS_SEQ(IS_SEQ),
.MODULE_BK_NUM(MODULE_BK_NUM), .ROW_SIZE(ROW_SIZE), .COL_SIZE(COL_SIZE[1:0]), .BK_SIZE(BK_SIZE), .BIT_SIZE(BIT_SIZE),
.tRCD(tRCD), .tCAS(tCAS), .tRAS(tRAS), .tRP(tRP),
.tREF(tREF), .tRC(tRC), //note: tRC minus 1
// from/to host side
.ADDR(sys_addr), .RD(sys_rd), .WR(sys_wr), .DAT_I(sys_wdata), .DAT_O(sys_rdata),
.RD_DAT_RDY(sys_rd_rdy), .BURST_RDY(sys_burst_rdy), .RW(),
.CPU_GNT_(1'b0), .MUX_EN(),
// from/to DIMM
.CKE(isdram_cke), .CS_(isdram_cs_),
.RAS_(isdram_ras_), .CAS_(isdram_cas_), .WE_(isdram_we_), .DQM(isdram_dqm),
.BA(isdram_ba), .DIMM_ADDR(isdram_addr),
.DQ_I(isdram_dqi), .DQ_O(isdram_dqo), .DQ_OE(isdram_dq_oe)
// .CKE(sdram_cke), .CS_(sdram_cs_),
// .RAS_(sdram_ras_), .CAS_(sdram_cas_), .WE_(sdram_we_), .DQM(sdram_dqm),
// .BA(sdram_ba), .DIMM_ADDR(sdram_addr),
// .DQ_I(sdram_dqi), .DQ_O(sdram_dqo), .DQ_OE(sdram_dq_oe)
);
sdram_io sdram_io(
// -- Clock
.sdram_clk(sdram_clk),
// -- From/to Internal Signals
.sdram_addr(isdram_addr), .sdram_ba(isdram_ba), .sdram_dqo(isdram_dqo),
.sdram_dqi(isdram_dqi), .sdram_dq_oe(isdram_dq_oe), .sdram_ras_(isdram_ras_),
.sdram_cas_(isdram_cas_), .sdram_we_(isdram_we_), .sdram_dqm(isdram_dqm),
.sdram_cke(isdram_cke), .sdram_cs_(isdram_cs_),
// -- From/to SDRAM Signals
.pad_addr(sdram_addr), .pad_ba(sdram_ba), .pad_dqo(sdram_dqo),
.pad_dqi(sdram_dqi), .pad_dq_oe(sdram_dq_oe), .pad_ras_(sdram_ras_),
.pad_cas_(sdram_cas_), .pad_we_(sdram_we_), .pad_dqml(sdram_dqml), .pad_dqmh(sdram_dqmh),
.pad_cke(sdram_cke), .pad_cs_(sdram_cs_)
);
endmodule |
module test();
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
localparam integer C_REALDATA = 1;
localparam integer C_PIXEL_WIDTH = (C_REALDATA ? 8 : 16);
localparam integer C_SH_WIDTH = 12;
localparam integer C_SW_WIDTH = 12;
localparam integer C_MH_WIDTH = 12;
localparam integer C_MW_WIDTH = 12;
localparam integer C_CH0_WIDTH = 8;
localparam integer C_CH1_WIDTH = 0;
localparam integer C_CH2_WIDTH = 0;
/// 10ms / 5ns
localparam integer C_FSYNC_INTERVAL = 10 * 1000 * 1000 / 5;
wire[C_PIXEL_WIDTH-1:0] m_axis_tdata_tb ;
wire m_axis_tlast_tb ;
reg m_axis_tready_tb;
wire m_axis_tuser_tb ;
wire m_axis_tvalid_tb;
wire[C_PIXEL_WIDTH-1:0] s_axis_tdata_tb ;
wire s_axis_tlast_tb ;
wire s_axis_tready_tb;
wire s_axis_tuser_tb ;
reg s_axis_tvalid_tb;
reg[C_SH_WIDTH-1:0] s_height_tb = 10;
reg[C_SW_WIDTH-1:0] s_width_tb = 10;
reg resetn_tb;
reg[C_MH_WIDTH-1:0] m_height_tb = 240;
reg[C_MW_WIDTH-1:0] m_width_tb = 320;
integer fileR, picType, dataPosition, grayDepth;
reg[80*8:0] outputFileName;
reg[11:0] outputFileIdx = 0;
integer fileW = 0;
initial begin
if (C_REALDATA) begin
fileR=$fopen("a.pgm", "r");
$fscanf(fileR, "P%d\n%d %d\n%d\n", picType, s_width_tb, s_height_tb, grayDepth);
dataPosition=$ftell(fileR);
$display("header: %dx%d, %d", s_width_tb, s_height_tb, grayDepth);
m_height_tb = s_height_tb / 2;
m_width_tb = s_width_tb / 2;
$display("header: %dx%d, %d, %0dx%0d", s_width_tb, s_height_tb, grayDepth, m_width_tb, m_height_tb);
end
else begin
s_width_tb = 10;
s_height_tb = 10;
m_height_tb = 60;
m_width_tb = 60;
end
end
reg clk;
reg fsync_tb = 0;
initial begin
clk <= 1'b1;
forever #2.5 clk <= ~clk;
end
initial begin
m_axis_tready_tb <= 1'b0;
#0.2 m_axis_tready_tb <= 1'b1;
forever begin
#5 m_axis_tready_tb <= (RANDOMOUTPUT ? {$random}%2 : 1);
end
end
initial begin
resetn_tb <= 1'b0;
repeat (5) #5 resetn_tb <= 1'b0;
forever #5 resetn_tb <= 1'b1;
end
initial begin
fsync_tb <= 0;
repeat (10) #5 fsync_tb <= 0;
forever begin
repeat (1) #5 fsync_tb <= 1;
repeat (C_FSYNC_INTERVAL - 1) #5 fsync_tb <= 0;
end
end
reg[23:0] outcnt = 0;
reg[11:0] outline = 0;
////////////////////////////////////////////////////////////////////////// input
reg [C_SH_WIDTH-1:0] s_ridx;
reg [C_SW_WIDTH-1:0] s_cidx;
wire s_rlast;
wire s_clast;
assign s_rlast = (s_ridx == s_height_tb - 1);
assign s_clast = (s_cidx == s_width_tb - 1);
assign s_axis_tuser_tb = (s_ridx == 0 && s_cidx == 0);
assign s_axis_tlast_tb = (s_cidx == s_width_tb - 1);
always @ (posedge clk) begin
if (resetn_tb == 1'b0) begin
s_ridx <= 0;
s_cidx <= 0;
end
else if (s_axis_tvalid_tb && s_axis_tready_tb) begin
if (~s_clast) begin
s_cidx <= s_cidx + 1;
s_ridx <= s_ridx;
end
else if (~s_rlast) begin
s_cidx <= 0;
s_ridx <= s_ridx + 1;
end
else begin
s_cidx <= 0;
s_ridx <= 0;
end
end
end
////////////////////////// enable input ////////////////////////////////////////
reg frm_done;
wire en_input;
wire trans_frm_last;
assign trans_frm_last = (s_ridx == (s_height_tb - 1)
&& s_cidx == s_width_tb - 1
&& s_axis_tvalid_tb);
always @ (posedge clk) begin
if (resetn_tb == 0)
frm_done <= 1;
else if (trans_frm_last)
frm_done <= 1;
else if (fsync_tb)
frm_done <= 0;
end
reg randomresult;
always @ (posedge clk) begin
randomresult <= (RANDOMINPUT ? {$random}%2 : 1);
end
assign en_input = (~trans_frm_last && ~frm_done && randomresult);
always @ (posedge clk) begin
if (resetn_tb == 1'b0)
s_axis_tvalid_tb <= 1'b0;
else if (~s_axis_tvalid_tb || s_axis_tready_tb) begin
s_axis_tvalid_tb <= en_input;
end
end
generate
if (C_REALDATA) begin
reg [C_PIXEL_WIDTH-1:0] s_axis_tdata_tb_r ;
assign s_axis_tdata_tb = s_axis_tdata_tb_r;
always @ (posedge clk) begin
if (fsync_tb)
$fseek(fileR, dataPosition, 0);
end
always @ (posedge clk) begin
if (resetn_tb == 1'b0) begin
s_axis_tdata_tb_r <= 0;
end
else if ((~s_axis_tvalid_tb || s_axis_tready_tb)
&& en_input) begin
s_axis_tdata_tb_r <= $fgetc(fileR);
end
end
end
else begin
assign s_axis_tdata_tb = (s_ridx * 256 + s_cidx);
end
endgenerate
///////////////////////////////////////////////////// output
always @(posedge clk) begin
if (resetn_tb == 1'b0 || (outcnt >= m_height_tb * m_width_tb && m_axis_tready_tb)) begin
if (fileW == 0) begin
outputFileIdx <= outputFileIdx + 1;
$sformat(outputFileName, "output%0d.pgm", outputFileIdx);
fileW=$fopen(outputFileName, "w");
$display("outputFileName: %s - %0d", outputFileName, fileW);
$fwrite(fileW, "P%0d\n%0d %0d\n%0d\n", picType, m_width_tb, m_height_tb, grayDepth);
end
if (outcnt > 0) $display ("new output!");
outcnt <= 0;
outline <= 0;
end
else if (m_axis_tready_tb && m_axis_tvalid_tb) begin
//$display("output data to %s", outputFileName);
$fwrite(fileW, "%c", m_axis_tdata_tb);
if (m_axis_tuser_tb != (outcnt == 0)) begin
$display("error sof %t", $time);
end
if (m_axis_tlast_tb != ((outcnt+1) % m_width_tb == 0)) begin
$display("error eol %t", $time);
end
$write("%h ", m_axis_tdata_tb);
if (m_axis_tlast_tb) begin
$write(outline+1, " time: %t\n", $time);
outline <= outline + 1;
end
outcnt <= outcnt + 1;
if (outcnt == m_height_tb * m_width_tb - 1) begin
$fclose(fileW);
fileW = 0;
end
end
end
axis_scaler # (
.C_PIXEL_WIDTH(C_PIXEL_WIDTH),
.C_SH_WIDTH (C_SH_WIDTH ),
.C_SW_WIDTH (C_SW_WIDTH ),
.C_MH_WIDTH (C_MH_WIDTH ),
.C_MW_WIDTH (C_MW_WIDTH ),
.C_CH0_WIDTH (C_CH0_WIDTH ),
.C_CH1_WIDTH (C_CH1_WIDTH ),
.C_CH2_WIDTH (C_CH2_WIDTH )
) uut (
.m_axis_tdata(m_axis_tdata_tb),
.m_axis_tlast(m_axis_tlast_tb),
.m_axis_tready(m_axis_tready_tb),
.m_axis_tuser(m_axis_tuser_tb),
.m_axis_tvalid(m_axis_tvalid_tb),
.s_axis_tdata(s_axis_tdata_tb),
.s_axis_tlast(s_axis_tlast_tb),
.s_axis_tready(s_axis_tready_tb),
.s_axis_tuser(s_axis_tuser_tb),
.s_axis_tvalid(s_axis_tvalid_tb),
.clk(clk),
.resetn(resetn_tb),
.fsync(fsync_tb),
.s_height(s_height_tb),
.s_width(s_width_tb),
.m_height(m_height_tb),
.m_width(m_width_tb)
);
endmodule |
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module pcie_ingress (
input clk,
input rst,
//AXI Stream Host 2 Device
output reg o_axi_ingress_ready,
input [31:0] i_axi_ingress_data,
input [3:0] i_axi_ingress_keep,
input i_axi_ingress_last,
input i_axi_ingress_valid,
//Parsed out control data
output reg [31:0] o_write_a_addr,
output reg [31:0] o_write_b_addr,
output reg [31:0] o_read_a_addr,
output reg [31:0] o_read_b_addr,
output reg [31:0] o_status_addr,
output reg [31:0] o_buffer_size,
output reg [31:0] o_ping_value,
output reg o_update_buf_stb,
output reg [1:0] o_update_buf,
output reg [31:0] o_dev_addr,
//Bar Hit
input [6:0] i_bar_hit,
input [31:0] i_control_addr_base,
output reg o_enable_config_read,
input i_finished_config_read,
//Ingress Data Path
output reg o_reg_write_stb,
//Commands
output reg o_cmd_rst_stb,
output reg o_cmd_wr_stb,
output reg o_cmd_rd_stb,
output reg o_cmd_ping_stb,
output reg o_cmd_rd_cfg_stb,
output reg o_cmd_unknown_stb,
output reg o_cmd_flg_fifo_stb,
output reg o_cmd_flg_sel_per_stb,
output reg o_cmd_flg_sel_mem_stb,
output reg o_cmd_flg_sel_dma_stb,
//Command Interface
output reg [31:0] o_cmd_data_count,
output reg [31:0] o_cmd_data_address,
//Flow Control
output reg o_cplt_pkt_stb,
output reg [9:0] o_cplt_pkt_cnt,
//Buffer Manager
//output reg [7:0] o_cplt_pkt_tag,
output [7:0] o_cplt_pkt_tag,
//output reg [6:0] o_cplt_pkt_lwr_addr,
output [6:0] o_cplt_pkt_lwr_addr,
//Buffer Interface
input [12:0] i_buf_offset,
output reg o_buf_we,
output reg [10:0] o_buf_addr,
output reg [31:0] o_buf_data,
output [3:0] o_state,
output reg [7:0] o_ingress_count,
output reg [7:0] o_ingress_ri_count,
output reg [7:0] o_ingress_ci_count,
output reg [31:0] o_ingress_addr,
output reg [31:0] o_ingress_cmplt_count,
output reg [2:0] o_cplt_sts,
output reg o_unknown_tlp_stb,
output reg o_unexpected_end_stb
);
//local parameters
localparam IDLE = 4'h0;
localparam READY = 4'h1;
localparam READ_HDR = 4'h2;
localparam WRITE_REG_CMD = 4'h3;
localparam READ_ADDR = 4'h4;
localparam READ_CMPLT = 4'h5;
localparam READ_CMPLT_DATA = 4'h6;
localparam GET_CMPLT_ADDR = 4'h7;
localparam SEND_DATA = 4'h8;
localparam READ_BAR_ADDR = 4'h9;
localparam FLUSH = 4'hA;
//Commands
localparam CMD_MEM_READ = 8'h00;
localparam CMD_MEM_READ_LOCK = 8'h01;
localparam CMD_MEM_WRITE = 8'h02;
localparam CMD_IO_READ = 8'h03;
localparam CMD_IO_WRITE = 8'h04;
localparam CMD_CONFIG_READD0 = 8'h05;
localparam CMD_CONFIG_WRITE0 = 8'h06;
localparam CMD_CONFIG_READ1 = 8'h07;
localparam CMD_CONFIG_WRITE1 = 8'h08;
localparam CMD_TCFGRD = 8'h09;
localparam CMD_TCFGWR = 8'h0A;
localparam CMD_MESSAGE = 8'h0B;
localparam CMD_MESSAGE_DATA = 8'h0C;
localparam CMD_COMPLETE = 8'h0D;
localparam CMD_COMPLETE_DATA = 8'h0E;
localparam CMD_COMPLETE_LOCK = 8'h0F;
localparam CMD_COMPLETE_DATA_LOCK = 8'h10;
localparam CMD_FETCH_ADD = 8'h11;
localparam CMD_SWAP = 8'h12;
localparam CMD_COMPARE_AND_SWAP = 8'h13;
localparam CMD_LPRF = 8'h14;
localparam CMD_EPRF = 8'h15;
localparam CMD_UNKNOWN = 8'h16;
//registes/wires
reg [3:0] state;
reg [23:0] r_data_count;
reg [3:0] r_hdr_index;
reg [31:0] r_hdr [0:3];
reg [2:0] r_hdr_size;
reg [7:0] r_hdr_cmd;
wire [9:0] w_pkt_data_size;
wire [31:0] w_pkt_addr;
wire [31:0] w_buf_pkt_addr_base;
wire [31:0] w_reg_addr;
wire w_cmd_en;
reg [31:0] r_buf_cnt;
wire [6:0] w_cmplt_lower_addr;
reg r_config_space_done;
wire [7:0] w_cplt_pkt_tag;
wire [6:0] w_cplt_pkt_lwr_addr;
wire [31:0] w_hdr0;
wire [31:0] w_hdr1;
wire [31:0] w_hdr2;
wire [31:0] w_hdr3;
assign w_hdr0 = r_hdr[0];
assign w_hdr1 = r_hdr[1];
assign w_hdr2 = r_hdr[2];
assign w_hdr3 = r_hdr[3];
assign o_state = state;
//submodules
//asynchronous logic
//Get Header Size
always @ (*) begin
case (r_hdr[0][`PCIE_FMT_RANGE])
`PCIE_FMT_3DW_NO_DATA: r_hdr_size = 3;
`PCIE_FMT_4DW_NO_DATA: r_hdr_size = 4;
`PCIE_FMT_3DW_DATA: r_hdr_size = 3;
`PCIE_FMT_4DW_DATA: r_hdr_size = 4;
default: r_hdr_size = 0;
endcase
end
always @ (*) begin
casex (r_hdr[0][`PCIE_TYPE_RANGE])
`PCIE_MRD: r_hdr_cmd = CMD_MEM_READ;
`PCIE_MRDLK: r_hdr_cmd = CMD_MEM_READ_LOCK;
`PCIE_MWR: r_hdr_cmd = CMD_MEM_WRITE;
`PCIE_IORD: r_hdr_cmd = CMD_IO_READ;
`PCIE_IOWR: r_hdr_cmd = CMD_IO_WRITE;
`PCIE_CFGRD0: r_hdr_cmd = CMD_CONFIG_READD0;
`PCIE_CFGWR0: r_hdr_cmd = CMD_CONFIG_WRITE0;
`PCIE_CFGRD1: r_hdr_cmd = CMD_CONFIG_READ1;
`PCIE_CFGWR1: r_hdr_cmd = CMD_CONFIG_WRITE1;
`PCIE_TCFGRD: r_hdr_cmd = CMD_TCFGRD;
`PCIE_TCFGWR: r_hdr_cmd = CMD_TCFGWR;
`PCIE_MSG: r_hdr_cmd = CMD_MESSAGE;
`PCIE_MSG_D: r_hdr_cmd = CMD_MESSAGE_DATA;
`PCIE_CPL: r_hdr_cmd = CMD_COMPLETE;
`PCIE_CPL_D: r_hdr_cmd = CMD_COMPLETE_DATA;
`PCIE_CPLLK: r_hdr_cmd = CMD_COMPLETE_LOCK;
`PCIE_CPLDLK: r_hdr_cmd = CMD_COMPLETE_DATA_LOCK;
`PCIE_FETCH_ADD: r_hdr_cmd = CMD_FETCH_ADD;
`PCIE_SWAP: r_hdr_cmd = CMD_SWAP;
`PCIE_CAS: r_hdr_cmd = CMD_COMPARE_AND_SWAP;
`PCIE_LPRF: r_hdr_cmd = CMD_LPRF;
`PCIE_EPRF: r_hdr_cmd = CMD_EPRF;
default: r_hdr_cmd = CMD_UNKNOWN;
endcase
end
assign w_pkt_data_size = r_hdr[0][`PCIE_DWORD_PKT_CNT_RANGE];
assign w_pkt_addr = {r_hdr[2][31:2], 2'b00};
assign w_cmplt_lower_addr = r_hdr[2][`CMPLT_LOWER_ADDR_RANGE];
assign w_reg_addr = (i_control_addr_base >= 0) ? ((w_pkt_addr - i_control_addr_base) >> 2): 32'h00;
assign w_cmd_en = (w_reg_addr >= `CMD_OFFSET);
//assign w_buf_pkt_addr_base = i_buf_offset - (w_pkt_addr + w_cmplt_lower_addr);
//assign w_buf_pkt_addr_base = i_buf_offset - w_cmplt_lower_addr;
assign w_buf_pkt_addr_base = i_buf_offset;
assign w_cplt_pkt_tag = (r_hdr_cmd == CMD_COMPLETE_DATA) ? r_hdr[2][15:8] : 8'h00;
//assign o_cplt_pkt_byte_count = (r_hdr_cmd == CMD_COMPLETE_DATA) ? r_hdr[1][11:0] : 12'h00;
assign w_cplt_pkt_lwr_addr = (r_hdr_cmd == CMD_COMPLETE_DATA) ? r_hdr[2][6:0] : 7'h0;
assign w_cplt_sts = r_hdr[1][15:13];
assign o_cplt_pkt_tag = w_cplt_pkt_tag;
assign o_cplt_pkt_lwr_addr = w_cplt_pkt_lwr_addr;
integer i;
//synchronous logic
always @ (posedge clk) begin
o_reg_write_stb <= 0;
o_buf_we <= 0;
o_cmd_rst_stb <= 0;
o_cmd_wr_stb <= 0;
o_cmd_rd_stb <= 0;
o_cmd_ping_stb <= 0;
o_cmd_rd_cfg_stb <= 0;
o_cmd_unknown_stb <= 0;
o_cmd_flg_fifo_stb <= 0;
o_cmd_flg_sel_per_stb <= 0;
o_cmd_flg_sel_mem_stb <= 0;
o_cmd_flg_sel_dma_stb <= 0;
o_update_buf_stb <= 0;
o_cplt_pkt_stb <= 0;
o_unknown_tlp_stb <= 0;
o_unexpected_end_stb <= 0;
if (rst) begin
state <= IDLE;
//Registers
o_write_a_addr <= 0;
o_write_b_addr <= 0;
o_read_a_addr <= 0;
o_read_b_addr <= 0;
o_status_addr <= 0;
o_update_buf <= 0;
o_ping_value <= 0;
o_buffer_size <= 0;
o_dev_addr <= 0;
//Command Registers
o_cmd_data_count <= 0;
o_cmd_data_address <= 0;
//Counts
r_data_count <= 0;
r_hdr_index <= 0;
//Buffer Interface
r_buf_cnt <= 0;
o_buf_addr <= 0;
o_buf_data <= 0;
o_axi_ingress_ready <= 0;
o_enable_config_read <= 0;
r_config_space_done <= 0;
o_ingress_count <= 0;
o_ingress_ri_count <= 0;
o_ingress_ci_count <= 0;
o_ingress_cmplt_count <= 0;
o_ingress_addr <= 0;
//o_cplt_pkt_tag <= 0;
//o_cplt_pkt_lwr_addr <= 0;
//Complete
o_cplt_pkt_cnt <= 0;
o_cplt_sts <= 0;
for (i = 0; i < 4; i = i + 1) begin
r_hdr[i] <= 0;
end
end
else begin
case (state)
IDLE: begin
r_buf_cnt <= 0;
o_buf_addr <= 0;
r_data_count <= 0;
r_hdr_index <= 0;
o_enable_config_read <= 0;
if (i_axi_ingress_valid) begin
if (!r_config_space_done && (i_bar_hit != 0)) begin
state <= READ_BAR_ADDR;
end
else begin
//This is a config register or a new command
state <= READY;
end
end
end
READY: begin
o_ingress_count <= o_ingress_count + 1;
o_axi_ingress_ready <= 1;
//r_hdr[r_hdr_index] <= i_axi_ingress_data;
//r_hdr_index <= r_hdr_index + 1;
state <= READ_HDR;
end
READ_HDR: begin
r_hdr[r_hdr_index] <= i_axi_ingress_data;
r_hdr_index <= r_hdr_index + 1;
if (r_hdr_index + 1 >= r_hdr_size) begin
case (r_hdr_cmd)
CMD_MEM_WRITE: begin
state <= WRITE_REG_CMD;
end
CMD_COMPLETE: begin
state <= READ_CMPLT;
end
CMD_COMPLETE_DATA: begin
o_cplt_pkt_cnt <= w_pkt_data_size;
state <= READ_CMPLT_DATA;
end
default: begin
o_unknown_tlp_stb <= 1;
state <= FLUSH;
end
endcase
end
end
WRITE_REG_CMD: begin
o_ingress_addr <= w_reg_addr;
if (w_cmd_en) begin
o_update_buf <= 2'b00;
//o_update_buf_stb <= 1;
o_cmd_data_count <= i_axi_ingress_data;
o_cmd_flg_sel_per_stb <= 0;
o_cmd_flg_sel_mem_stb <= 0;
o_cmd_flg_sel_dma_stb <= 0;
case (w_reg_addr)
`PCIE_COMMAND_RESET: begin
r_config_space_done <= 0;
o_cmd_rst_stb <= 1;
end
`PERIPHERAL_WRITE: begin
o_ingress_cmplt_count <= 0;
o_cplt_sts <= 0;
o_cmd_flg_sel_per_stb <= 1;
o_cmd_wr_stb <= 1;
end
`PERIPHERAL_WRITE_FIFO: begin
o_cmd_flg_sel_per_stb <= 1;
o_cmd_wr_stb <= 1;
o_cmd_flg_fifo_stb <= 1;
end
`PERIPHERAL_READ: begin
o_cmd_flg_sel_per_stb <= 1;
o_cmd_rd_stb <= 1;
end
`PERIPHERAL_READ_FIFO: begin
o_cmd_flg_sel_per_stb <= 1;
o_cmd_rd_stb <= 1;
o_cmd_flg_fifo_stb <= 1;
end
`MEMORY_WRITE: begin
o_cmd_flg_sel_mem_stb <= 1;
o_cmd_wr_stb <= 1;
end
`MEMORY_READ: begin
o_cmd_flg_sel_mem_stb <= 1;
o_cmd_rd_stb <= 1;
end
`DMA_WRITE: begin
o_cmd_flg_sel_dma_stb <= 1;
o_cmd_wr_stb <= 1;
end
`DMA_READ: begin
o_cmd_flg_sel_dma_stb <= 1;
o_cmd_rd_stb <= 1;
end
`PING: begin
o_cmd_ping_stb <= 1;
o_ping_value <= i_axi_ingress_data;
end
`READ_CONFIG: begin
o_cmd_rd_cfg_stb <= 1;
end
default: begin
o_cmd_unknown_stb <= 1;
o_ingress_ci_count <= o_ingress_ci_count + 1;
end
endcase
end
else begin
case (w_reg_addr)
`HDR_STATUS_BUF_ADDR: begin
o_status_addr <= i_axi_ingress_data;
end
`HDR_BUFFER_READY: begin
o_update_buf <= i_axi_ingress_data[1:0];
o_update_buf_stb <= 1;
end
`HDR_AUX_BUFFER_READY: begin
o_update_buf <= i_axi_ingress_data[1:0];
o_update_buf_stb <= 1;
end
`HDR_WRITE_BUF_A_ADDR: begin
o_write_a_addr <= i_axi_ingress_data;
end
`HDR_WRITE_BUF_B_ADDR: begin
o_write_b_addr <= i_axi_ingress_data;
end
`HDR_READ_BUF_A_ADDR: begin
o_read_a_addr <= i_axi_ingress_data;
end
`HDR_READ_BUF_B_ADDR: begin
o_read_b_addr <= i_axi_ingress_data;
end
`HDR_BUFFER_SIZE: begin
o_buffer_size <= i_axi_ingress_data;
end
`HDR_DEV_ADDR: begin
o_dev_addr <= i_axi_ingress_data;
o_cmd_data_address <= i_axi_ingress_data;
end
default: begin
o_ingress_ri_count <= o_ingress_ri_count + 1;
end
endcase
o_reg_write_stb <= 1;
end
state <= FLUSH;
end
READ_ADDR: begin
o_cmd_data_address <= i_axi_ingress_data;
state <= FLUSH;
end
READ_CMPLT: begin
if (w_cplt_sts != 0) begin
o_cplt_sts <= w_cplt_sts;
end
state <= FLUSH;
end
READ_CMPLT_DATA: begin
o_buf_addr <= w_buf_pkt_addr_base;
if (w_cplt_sts != 0) begin
o_cplt_sts <= w_cplt_sts;
end
o_buf_we <= 1;
o_buf_data <= i_axi_ingress_data;
r_buf_cnt <= r_buf_cnt + 1;
o_ingress_cmplt_count <= o_ingress_cmplt_count + 1;
//o_cplt_pkt_tag <= w_cplt_pkt_tag;
//o_cplt_pkt_lwr_addr <= w_cplt_pkt_lwr_addr;
//state <= GET_CMPLT_ADDR;
state <= SEND_DATA;
end
GET_CMPLT_ADDR: begin
state <= SEND_DATA;
end
SEND_DATA: begin
//The Buffer is available
if (r_buf_cnt < w_pkt_data_size) begin
//o_buf_addr <= w_buf_pkt_addr_base + r_buf_cnt;
o_buf_addr <= o_buf_addr + 1;
r_buf_cnt <= r_buf_cnt + 1;
o_buf_data <= i_axi_ingress_data;
o_buf_we <= 1;
end
else begin
o_cplt_pkt_stb <= 1;
state <= FLUSH;
end
//Sort of an out of band signal... but need to see if this is a problem
if ((r_buf_cnt < w_pkt_data_size) && !o_axi_ingress_ready) begin
o_unexpected_end_stb <= 1;
state <= IDLE;
end
end
FLUSH: begin
if (!o_axi_ingress_ready) begin
state <= IDLE;
end
if (!i_axi_ingress_valid) begin
o_axi_ingress_ready <= 0;
end
end
READ_BAR_ADDR: begin
o_enable_config_read <= 1;
if (i_finished_config_read) begin
r_config_space_done <= 1;
o_enable_config_read <= 0;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
//if (i_axi_ingress_last) begin
// o_axi_ingress_ready <= 0;
//end
end
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [7:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [15:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *) output [15:0]P;
wire [7:0]A;
wire [15:0]B;
wire CLK;
wire [15:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "8" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "8" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [7:0]A;
input [15:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [15:0]P;
output [47:0]PCASC;
wire \<const0> ;
wire [7:0]A;
wire [15:0]B;
wire CLK;
wire [15:0]P;
wire [47:0]NLW_i_mult_PCASC_UNCONNECTED;
wire [1:0]NLW_i_mult_ZERO_DETECT_UNCONNECTED;
assign PCASC[47] = \<const0> ;
assign PCASC[46] = \<const0> ;
assign PCASC[45] = \<const0> ;
assign PCASC[44] = \<const0> ;
assign PCASC[43] = \<const0> ;
assign PCASC[42] = \<const0> ;
assign PCASC[41] = \<const0> ;
assign PCASC[40] = \<const0> ;
assign PCASC[39] = \<const0> ;
assign PCASC[38] = \<const0> ;
assign PCASC[37] = \<const0> ;
assign PCASC[36] = \<const0> ;
assign PCASC[35] = \<const0> ;
assign PCASC[34] = \<const0> ;
assign PCASC[33] = \<const0> ;
assign PCASC[32] = \<const0> ;
assign PCASC[31] = \<const0> ;
assign PCASC[30] = \<const0> ;
assign PCASC[29] = \<const0> ;
assign PCASC[28] = \<const0> ;
assign PCASC[27] = \<const0> ;
assign PCASC[26] = \<const0> ;
assign PCASC[25] = \<const0> ;
assign PCASC[24] = \<const0> ;
assign PCASC[23] = \<const0> ;
assign PCASC[22] = \<const0> ;
assign PCASC[21] = \<const0> ;
assign PCASC[20] = \<const0> ;
assign PCASC[19] = \<const0> ;
assign PCASC[18] = \<const0> ;
assign PCASC[17] = \<const0> ;
assign PCASC[16] = \<const0> ;
assign PCASC[15] = \<const0> ;
assign PCASC[14] = \<const0> ;
assign PCASC[13] = \<const0> ;
assign PCASC[12] = \<const0> ;
assign PCASC[11] = \<const0> ;
assign PCASC[10] = \<const0> ;
assign PCASC[9] = \<const0> ;
assign PCASC[8] = \<const0> ;
assign PCASC[7] = \<const0> ;
assign PCASC[6] = \<const0> ;
assign PCASC[5] = \<const0> ;
assign PCASC[4] = \<const0> ;
assign PCASC[3] = \<const0> ;
assign PCASC[2] = \<const0> ;
assign PCASC[1] = \<const0> ;
assign PCASC[0] = \<const0> ;
assign ZERO_DETECT[1] = \<const0> ;
assign ZERO_DETECT[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "8" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "8" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv i_mult
(.A(A),
.B(B),
.CE(1'b0),
.CLK(CLK),
.P(P),
.PCASC(NLW_i_mult_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_i_mult_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module bsg_reduce #(parameter `BSG_INV_PARAM(width_p )
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter harden_p = 0
)
(input [width_p-1:0] i
, output o
);
// synopsys translate_off
initial
assert( $countones({xor_p & 1'b1, and_p & 1'b1, or_p & 1'b1}) == 1)
else $error("bsg_scan: only one function may be selected\n");
// synopsys translate_on
if (xor_p)
begin: xorr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = ^i;
end:xorr
else if (and_p)
begin: andr
if (width_p < 4)
begin: notmacro
assign o = &i;
end else
`bsg_andr_macro(4) else
`bsg_andr_macro(6) else
`bsg_andr_macro(8) else
`bsg_andr_macro(9) else
`bsg_andr_macro(12) else
`bsg_andr_macro(16) else
begin: notmacro
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = &i;
end
end
else if (or_p)
begin: orr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = |i;
end
endmodule |
module bsg_fsb_node_trace_replay
#(parameter ring_width_p=80
, parameter rom_addr_width_p=6
, parameter counter_width_p=`BSG_MIN(ring_width_p,16)
, parameter uptime_p=0
)
(input clk_i
, input reset_i
, input en_i
// input channel
, input v_i
, input [ring_width_p-1:0] data_i
, output logic ready_o
// output channel
, output logic v_o
, output logic [ring_width_p-1:0] data_o
, input yumi_i
// connection to rom
// note: asynchronous reads
, output [rom_addr_width_p-1:0] rom_addr_o
, input [ring_width_p+4-1:0] rom_data_i
// true outputs
, output logic done_o
, output logic error_o
);
initial
begin
$display("## WARNING: bsg_fsb_node_trace_replay will be DEPRECATED soon; please discontinue use (%m).");
end
// 0: wait one cycle
// 1: send data
// 2: receive data (and check its value)
// 3: assert done_o; test complete.
// 4: end test; call $finish
// 5: decrement cycle counter; wait for cycle_counter == 0
// 6: initialized cycle counter with 16 bits
// in theory, we could add branching, etc.
// before we know it, we have a processor =)
typedef enum logic [3:0] {
eNop=4'd0,
eSend=4'd1,
eReceive=4'd2,
eDone=4'd3,
eFinish=4'd4,
eCycleDec=4'd5,
eCycleInit=4'd6
} eOp;
logic [counter_width_p-1:0] cycle_ctr_r, cycle_ctr_n;
logic [rom_addr_width_p-1:0] addr_r, addr_n;
logic done_r, done_n;
logic error_r, error_n;
assign rom_addr_o = addr_r;
assign data_o = rom_data_i[0+:ring_width_p];
assign done_o = done_r;
assign error_o = error_r;
always_ff @(posedge clk_i)
begin
if (reset_i)
begin
addr_r <= 0;
done_r <= 0;
error_r <= 0;
cycle_ctr_r <= 16'b1;
end
else
begin
addr_r <= addr_n;
done_r <= done_n;
error_r <= error_n;
cycle_ctr_r <= cycle_ctr_n;
end
end // always_ff @
logic [3:0] op;
assign op = rom_data_i[ring_width_p+:4];
logic instr_completed;
assign addr_n = instr_completed ? (addr_r+1'b1) : addr_r;
// handle outputs
always_comb
begin
// defaults; not sending and not receiving unless done
v_o = 1'b0;
ready_o = done_r;
done_n = done_r;
if (!done_r & en_i & ~reset_i)
begin
case (op)
eSend: v_o = 1'b1;
eReceive: ready_o = 1'b1;
eDone: done_n = 1'b1;
default:
begin
end
endcase
end
end // always_comb
// next instruction logic
always_comb
begin
instr_completed = 1'b0;
error_n = error_r;
cycle_ctr_n = cycle_ctr_r;
if (!done_r & en_i & ~reset_i)
begin
case (op)
eNop: instr_completed = 1'b1;
eSend:
begin
if (yumi_i)
instr_completed = 1'b1;
end
eReceive:
begin
if (v_i)
begin
instr_completed = 1'b1;
if (error_r == 0)
error_n = data_i != data_o;
end
end
eDone: instr_completed = 1'b1;
eFinish: instr_completed = 1'b1;
eCycleDec:
begin
cycle_ctr_n = cycle_ctr_r - 1'b1;
instr_completed = ~(|cycle_ctr_r);
end
eCycleInit:
begin
cycle_ctr_n = rom_data_i[counter_width_p-1:0];
instr_completed = 1;
end
default:
begin
end
endcase // case (op)
end
end
// non-synthesizeable components
always @(negedge clk_i)
begin
if (instr_completed & ~reset_i & ~done_r)
begin
case(op)
eSend:
begin
string localtime;
if (uptime_p)
begin
int fd;
fd=$fopen("/proc/uptime","r");
void'($fscanf(fd,"%s",localtime));
$fclose(fd);
end
else
localtime = "";
$display("### bsg_fsb_node_trace_replay SEND %d'b%b (%m), time=%t uptime=%s", ring_width_p,data_o,$time,localtime);
end
eReceive:
begin
if (data_i !== data_o)
begin
$display("############################################################################");
$display("### bsg_fsb_node_trace_replay RECEIVE unmatched (%m) ");
$display("### ");
$display("### FAIL (trace mismatch) = %h", data_i);
$display("### expected = %h\n", data_o);
$display("### diff = %h\n", data_o ^ data_i);
$display("############################################################################");
$finish();
end
else
begin
$display("### bsg_fsb_node_trace_replay RECEIVE matched %h (%m)", data_o);
end // else: !if(data_i != data_o)
end
eDone:
begin
$display("############################################################################");
$display("###### bsg_fsb_node_trace_replay DONE done_o=1 (trace finished addr=%x) (%m)",rom_addr_o);
$display("############################################################################");
end
eFinish:
begin
$display("############################################################################");
$display("###### bsg_fsb_node_trace_replay FINISH (trace finished; CALLING $finish) (%m)");
$display("############################################################################");
$finish;
end
eCycleDec:
begin
$display("### bsg_fsb_node_trace_replay CYCLE DEC cycle_ctr_r = %x (%m)",cycle_ctr_r);
end
eCycleInit:
begin
$display("### bsg_fsb_node_trace_replay CYCLE INIT = %x (%m)",cycle_ctr_n);
end
default:
begin
end
endcase // case (op)
case (op)
eNop, eSend, eReceive, eDone, eFinish, eCycleDec, eCycleInit:
begin
end
default: $display("### bsg_fsb_node_trace_replay UNKNOWN op %x (%m)\n", op);
endcase // case (op)
end // if (instr_completed & ~reset_i & ~done_r)
end // always @ (negedge clk_i)
endmodule |
module Main_Test;
parameter ADDR_WIDTH=16;
parameter DATA_WIDTH=8;
reg clk; // System clock
reg reset; // System reset
reg rd; // Read enable
reg wr; // Write enable
reg ale; // Address latch enable.
reg [ADDR_WIDTH-1:0] addr; // Address bus
reg [DATA_WIDTH-1:0] data_in; // Data in bus
reg data_valid; // Indicates data-in is valid.
wire [DATA_WIDTH-1:0] data_out; // Data out bus
wire [DATA_WIDTH-1:0] ad;
MainAVR main_avr(._reset(~reset), .clk(clk),
._mpu_rd(~rd), ._mpu_wr(~wr), .mpu_ale(ale),
.mpu_ah(addr[ADDR_WIDTH-1:DATA_WIDTH]), .mpu_ad(ad));
assign data_out = (rd & ~wr & ~ale) ? ad : 'bx;
assign ad = ale ? addr[DATA_WIDTH-1:0] : (data_valid ? data_in : 'bz);
// Generate clock.
always
#1 clk = ~clk;
integer i;
reg [4:0] stage = 0;
initial begin
clk = 0;
reset = 0;
rd = 0;
wr = 0;
addr = 0;
data_in = 0;
data_valid = 0;
// Reset
#5 stage = 1;
#1 reset = 1;
#5 reset = 0;
#1 addr = 'bx;
// Test some writes
#5 stage = 2;
#1 write16(0, 'hdead);
#1 write16(2, 'hbeef);
#1 write16(4, 'hcafe);
#1 write16(8, 'hface);
#1 write16(16, 'hbead);
#1 write16(18, 'hfade);
#1 write16(24, 'hdeaf);
#1 write16(26, 'hface);
#1 write16(28, 'hface);
#1 write16(30, 'hface);
#1 addr = 'bx;
// Test some reads
#5 stage = 3;
#1 read_test();
#1 addr = 'bx;
// Test some byte writes
#5 stage = 4;
for (i = 0; i < 16; i = i + 1)
begin
#1 write8(i * 2, 'h0000);
#1 write8(i * 2 + 1, 'hffff);
end
// Test some reads
#5 stage = 5;
#1 read_test();
// Test some tile reg writes
#5 stage = 6;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 write16((`TILE_REG_ADDR_BASE + i) * 2, ~i);
end
#5 stage = 7;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 read8((`TILE_REG_ADDR_BASE + i) * 2);
#1 read8((`TILE_REG_ADDR_BASE + i) * 2 + 1);
end
// Test some palette writes
#5 stage = 8;
for (i = 0; i < 16; i = i + 1)
begin
#1 write16('h1000 + i * 2, ~i);
end
#5 stage = 9;
for (i = 0; i < 32; i = i + 1)
begin
#1 read8('h1000 + i);
end
end
// Task to write a byte.
task write8;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH-1:0] data_arg;
begin
addr = addr_arg;
data_in = data_arg;
#2 rd = 0; wr = 0; ale = 1; data_valid = 0;
#2 rd = 0; wr = 1; ale = 0; data_valid = 1;
#2 rd = 0; wr = 0; ale = 0; data_valid = 1;
#2 data_valid = 0;
end
endtask
// Task to write a word.
task write16;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH*2-1:0] data_arg;
begin
write8(addr_arg, data_arg[DATA_WIDTH-1:0]);
write8(addr_arg + 1, data_arg[DATA_WIDTH*2-1:DATA_WIDTH]);
end
endtask
// Task to read a byte.
task read8;
input [ADDR_WIDTH-1:0] addr_arg;
begin
addr = addr_arg;
#2 rd = 0; wr = 0; ale = 1;
#2 rd = 1; wr = 0; ale = 0;
#2 rd = 0; wr = 0; ale = 0;
end
endtask
// Readback test for the register
task read_test;
integer i;
begin
// Test some reads
#5
for (i = 0; i < 30; i = i + 1) begin
#1 read8(i);
end
end
endtask
endmodule |
module tx_port_channel_gate_128
#(parameter C_DATA_WIDTH = 9'd128,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH + 1)
(input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN); // Channel write data has been recieved
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE128_IDLE, _rState=`S_TXPORTGATE128_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
reg rOpen=0, _rOpen=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rOpen & !wFifoFull); // S_TXPORTGATE128_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo
#(.C_WIDTH(C_FIFO_DATA_WIDTH),
.C_DEPTH(C_FIFO_DEPTH))
fifo
(.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY));
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE128_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
rOpen <= #1 (RST ? 1'd0 : _rOpen);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
_rOpen = rOpen;
case (rState)
`S_TXPORTGATE128_IDLE: begin // Write the len, off, last
_rPause = 0;
_rClosed = 0;
_rOpen = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, 64'd0, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE128_OPENING;
end
end
`S_TXPORTGATE128_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
// rClosed catches a transfer that opens and subsequently closes
// without writing data
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
else begin
_rState = `S_TXPORTGATE128_OPEN;
_rOpen = CHNL_TX & rChnlTx;
end
end
end
`S_TXPORTGATE128_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
// CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
// but the VALID+REN model seem to make this difficult.
_rFifoWen = CHNL_TX_DATA_VALID;
_rFifoData = {1'd0, CHNL_TX_DATA};
end
if (!rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
_rOpen = CHNL_TX & rChnlTx;
end
`S_TXPORTGATE128_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE128_IDLE;
end
end
endcase
end
endmodule |
module checker (input clk);
parameter DATASIZE = 8;
parameter BUFFSIZE = 1024;
parameter ADDRSIZE = 10;
parameter STRRSIZE = 8*50;
parameter NOTFULL = 0;
parameter FULL = 1;
parameter ALMOSTFULL = 2;
parameter FILLINGUP = 3;
reg [DATASIZE : 0] got [BUFFSIZE - 1 : 0];
reg [DATASIZE : 0] exp [BUFFSIZE - 1 : 0];
integer nGot;
integer nExp;
reg [ADDRSIZE - 1 : 0] gotRdPtr;
reg [ADDRSIZE - 1 : 0] gotWrPtr;
reg [ADDRSIZE - 1 : 0] expRdPtr;
reg [ADDRSIZE - 1 : 0] expWrPtr;
reg[STRRSIZE : 1] name;
task new(input reg[STRRSIZE : 1] inName);
begin
name = inName;
nGot = 0;
nExp = 0;
gotRdPtr = 0;
gotWrPtr = 0;
expRdPtr = 0;
expWrPtr = 0;
end
endtask
function [1:0] addGot(input reg [DATASIZE - 1 : 0] data);
if(nGot == 1024) begin
addGot = FULL;
end
else if(nGot == 1023) begin
addGot = ALMOSTFULL;
end
else if (nGot == 1014) begin
addGot = FILLINGUP;
end
else begin
got[nGot] = data;
nGot = nGot + 1;
gotWrPtr = gotWrPtr + 1;
addGot = NOTFULL;
end
endfunction
function [1:0] addExp(input reg [DATASIZE - 1 : 0] data);
if(nExp == 1024) begin
addExp = FULL;
end
else if(nExp == 1023) begin
addExp = ALMOSTFULL;
end
else if (nExp == 1014) begin
addExp = FILLINGUP;
end
else begin
exp[nExp] = data;
nExp = nExp + 1;
expWrPtr = expWrPtr + 1;
addExp = NOTFULL;
end
endfunction
task checkAll;
integer i;
begin
if(nGot !== nExp) begin
$write("ERROR: %0s: Count Mismatch Got %0d bytes. Expected $0d\n", name, nGot, nExp);
end
else begin
for(i = 0; i < nGot; i = 0) begin
if(got[i] !== exp[i]) begin
$write("ERROR: %0s: Byte mismatch at index: %0d Got: %0h Expected: %0h", name, i, got[i], exp[i]);
end
end
nGot = 0;
nExp = 0;
gotRdPtr = 0;
gotWrPtr = 0;
expRdPtr = 0;
expWrPtr = 0;
end
end
endtask
task check;
while(1) begin
if(nGot > 0 && nExp > 0) begin
end
end
endtask
endmodule |
module joypad_snes_adapter(
input wire clock,
input wire reset,
// to gameboy
input wire [1:0] button_sel,
output wire [3:0] button_data,
output reg [15:0] button_state,
// to controller
input wire controller_data,
output wire controller_latch,
output wire controller_clock
);
////////////////////////////////////////////////////////
// http://www.gamefaqs.com/snes/916396-snes/faqs/5395
//
// Note: This implementation does *not* match the
// timings specified in the documentation above.
// Instead, it uses a much simpler and slower 1KHz
// clock which provides pretty good responsiveness
// to button presses. Also note that the Atlys board
// only provides a 3.3V Vcc instead of the spec'd 5V.
//
// Note: Color of wires on my controller ext. cable
// Vcc (+5V) - Green
// Clock - Blue
// Latch - Yellow
// Data - Red
// Ground - Brown
////////////////////////////////////////////////////////
parameter WAIT_STATE = 0;
parameter LATCH_STATE = 1;
parameter READ_STATE = 2;
reg [1:0] state;
reg [3:0] button_index;
//reg [15:0] button_state;
/**
* State transitions occur on the clock's positive edge.
*/
always @(posedge clock) begin
if (reset)
state <= WAIT_STATE;
else begin
if (state == WAIT_STATE)
state <= LATCH_STATE;
else if (state == LATCH_STATE)
state <= READ_STATE;
else if (state == READ_STATE) begin
if (button_index == 15)
state <= WAIT_STATE;
end
end
end
/**
* Button reading occurs on the negative edge to give
* values from the controller time to settle.
*/
always @(negedge clock) begin
if (reset) begin
button_index <= 4'b0;
button_state <= 16'hFFFF;
end else begin
if (state == WAIT_STATE)
button_index <= 4'b0;
else if (state == READ_STATE) begin
button_state[button_index] <= controller_data;
button_index <= button_index + 1;
end
end
end
assign controller_latch = (state == LATCH_STATE) ? 1'b1 : 1'b0;
assign controller_clock = (state == READ_STATE) ? clock : 1'b1;
// button order is
// B Y SELECT START UP DOWN LEFT RIGHT A X L R - - - -
assign button_data =
button_sel[0] == 1'b0 ? { button_state[7], button_state[6], button_state[4], button_state[5] } :
button_sel[1] == 1'b0 ? { button_state[8], button_state[0], button_state[2], button_state[3] } : 4'b1111;
endmodule |
module sky130_fd_sc_hs__o32ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 nor0_out ;
wire B1 nor1_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule |
module or1200_rfram_generic(
// Clock and reset
clk, rst,
// Port A
ce_a, addr_a, do_a,
// Port B
ce_b, addr_b, do_b,
// Port W
ce_w, we_w, addr_w, di_w
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Port A
//
input ce_a;
input [aw-1:0] addr_a;
output [dw-1:0] do_a;
//
// Port B
//
input ce_b;
input [aw-1:0] addr_b;
output [dw-1:0] do_b;
//
// Port W
//
input ce_w;
input we_w;
input [aw-1:0] addr_w;
input [dw-1:0] di_w;
//
// Internal wires and regs
//
reg [aw-1:0] intaddr_a;
reg [aw-1:0] intaddr_b;
reg [32*dw-1:0] mem;
reg [dw-1:0] do_a;
reg [dw-1:0] do_b;
//
// Write port
//
always @(posedge clk or posedge rst)
if (rst) begin
mem <= #1 {512'h0, 512'h0};
end
else if (ce_w & we_w)
case (addr_w) // synopsys parallel_case
5'd00: mem[32*0+31:32*0] <= #1 32'h0000_0000;
5'd01: mem[32*1+31:32*1] <= #1 di_w;
5'd02: mem[32*2+31:32*2] <= #1 di_w;
5'd03: mem[32*3+31:32*3] <= #1 di_w;
5'd04: mem[32*4+31:32*4] <= #1 di_w;
5'd05: mem[32*5+31:32*5] <= #1 di_w;
5'd06: mem[32*6+31:32*6] <= #1 di_w;
5'd07: mem[32*7+31:32*7] <= #1 di_w;
5'd08: mem[32*8+31:32*8] <= #1 di_w;
5'd09: mem[32*9+31:32*9] <= #1 di_w;
5'd10: mem[32*10+31:32*10] <= #1 di_w;
5'd11: mem[32*11+31:32*11] <= #1 di_w;
5'd12: mem[32*12+31:32*12] <= #1 di_w;
5'd13: mem[32*13+31:32*13] <= #1 di_w;
5'd14: mem[32*14+31:32*14] <= #1 di_w;
5'd15: mem[32*15+31:32*15] <= #1 di_w;
5'd16: mem[32*16+31:32*16] <= #1 di_w;
5'd17: mem[32*17+31:32*17] <= #1 di_w;
5'd18: mem[32*18+31:32*18] <= #1 di_w;
5'd19: mem[32*19+31:32*19] <= #1 di_w;
5'd20: mem[32*20+31:32*20] <= #1 di_w;
5'd21: mem[32*21+31:32*21] <= #1 di_w;
5'd22: mem[32*22+31:32*22] <= #1 di_w;
5'd23: mem[32*23+31:32*23] <= #1 di_w;
5'd24: mem[32*24+31:32*24] <= #1 di_w;
5'd25: mem[32*25+31:32*25] <= #1 di_w;
5'd26: mem[32*26+31:32*26] <= #1 di_w;
5'd27: mem[32*27+31:32*27] <= #1 di_w;
5'd28: mem[32*28+31:32*28] <= #1 di_w;
5'd29: mem[32*29+31:32*29] <= #1 di_w;
5'd30: mem[32*30+31:32*30] <= #1 di_w;
default: mem[32*31+31:32*31] <= #1 di_w;
endcase
//
// Read port A
//
always @(posedge clk or posedge rst)
if (rst) begin
intaddr_a <= #1 5'h00;
end
else if (ce_a)
intaddr_a <= #1 addr_a;
always @(mem or intaddr_a)
case (intaddr_a) // synopsys parallel_case
5'd00: do_a = 32'h0000_0000;
5'd01: do_a = mem[32*1+31:32*1];
5'd02: do_a = mem[32*2+31:32*2];
5'd03: do_a = mem[32*3+31:32*3];
5'd04: do_a = mem[32*4+31:32*4];
5'd05: do_a = mem[32*5+31:32*5];
5'd06: do_a = mem[32*6+31:32*6];
5'd07: do_a = mem[32*7+31:32*7];
5'd08: do_a = mem[32*8+31:32*8];
5'd09: do_a = mem[32*9+31:32*9];
5'd10: do_a = mem[32*10+31:32*10];
5'd11: do_a = mem[32*11+31:32*11];
5'd12: do_a = mem[32*12+31:32*12];
5'd13: do_a = mem[32*13+31:32*13];
5'd14: do_a = mem[32*14+31:32*14];
5'd15: do_a = mem[32*15+31:32*15];
5'd16: do_a = mem[32*16+31:32*16];
5'd17: do_a = mem[32*17+31:32*17];
5'd18: do_a = mem[32*18+31:32*18];
5'd19: do_a = mem[32*19+31:32*19];
5'd20: do_a = mem[32*20+31:32*20];
5'd21: do_a = mem[32*21+31:32*21];
5'd22: do_a = mem[32*22+31:32*22];
5'd23: do_a = mem[32*23+31:32*23];
5'd24: do_a = mem[32*24+31:32*24];
5'd25: do_a = mem[32*25+31:32*25];
5'd26: do_a = mem[32*26+31:32*26];
5'd27: do_a = mem[32*27+31:32*27];
5'd28: do_a = mem[32*28+31:32*28];
5'd29: do_a = mem[32*29+31:32*29];
5'd30: do_a = mem[32*30+31:32*30];
default: do_a = mem[32*31+31:32*31];
endcase
//
// Read port B
//
always @(posedge clk or posedge rst)
if (rst) begin
intaddr_b <= #1 5'h00;
end
else if (ce_b)
intaddr_b <= #1 addr_b;
always @(mem or intaddr_b)
case (intaddr_b) // synopsys parallel_case
5'd00: do_b = 32'h0000_0000;
5'd01: do_b = mem[32*1+31:32*1];
5'd02: do_b = mem[32*2+31:32*2];
5'd03: do_b = mem[32*3+31:32*3];
5'd04: do_b = mem[32*4+31:32*4];
5'd05: do_b = mem[32*5+31:32*5];
5'd06: do_b = mem[32*6+31:32*6];
5'd07: do_b = mem[32*7+31:32*7];
5'd08: do_b = mem[32*8+31:32*8];
5'd09: do_b = mem[32*9+31:32*9];
5'd10: do_b = mem[32*10+31:32*10];
5'd11: do_b = mem[32*11+31:32*11];
5'd12: do_b = mem[32*12+31:32*12];
5'd13: do_b = mem[32*13+31:32*13];
5'd14: do_b = mem[32*14+31:32*14];
5'd15: do_b = mem[32*15+31:32*15];
5'd16: do_b = mem[32*16+31:32*16];
5'd17: do_b = mem[32*17+31:32*17];
5'd18: do_b = mem[32*18+31:32*18];
5'd19: do_b = mem[32*19+31:32*19];
5'd20: do_b = mem[32*20+31:32*20];
5'd21: do_b = mem[32*21+31:32*21];
5'd22: do_b = mem[32*22+31:32*22];
5'd23: do_b = mem[32*23+31:32*23];
5'd24: do_b = mem[32*24+31:32*24];
5'd25: do_b = mem[32*25+31:32*25];
5'd26: do_b = mem[32*26+31:32*26];
5'd27: do_b = mem[32*27+31:32*27];
5'd28: do_b = mem[32*28+31:32*28];
5'd29: do_b = mem[32*29+31:32*29];
5'd30: do_b = mem[32*30+31:32*30];
default: do_b = mem[32*31+31:32*31];
endcase
endmodule |
module sky130_fd_sc_hs__sdlclkp (
VPWR,
VGND,
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
input VPWR;
input VGND;
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire SCE_GATE ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (m0 , SCE_GATE, clkn, VPWR, VGND);
and and0 (GCLK , m0n, CLK );
endmodule |
module timer #(
parameter res = 33, // bit resolution (default: 33 bits)
parameter phase = 12507 // phase value for the counter
)
(
input wb_clk_i, // Wishbone slave interface
input wb_rst_i,
output reg wb_tgc_o // Interrupt output
);
reg [res-1:0] cnt;
reg old_clk2;
wire clk2;
// Continuous assignments
assign clk2 = cnt[res-1];
// Behaviour
always @(posedge wb_clk_i)
cnt <= wb_rst_i ? 0 : (cnt + phase);
always @(posedge wb_clk_i)
old_clk2 <= wb_rst_i ? 1'b0 : clk2;
always @(posedge wb_clk_i)
wb_tgc_o <= wb_rst_i ? 1'b0 : (!old_clk2 & clk2);
// --------------------------------------------------------------------
endmodule |
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_103 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W17_102 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_8 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire enable_Pipeline_input, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5,
OP_FLAG_INIT, SIGN_FLAG_INIT, ZERO_FLAG_INIT, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, ADD_OVRFLW_NRM, n_7_net_, left_right_SHT2,
bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, n_21_net_, SIGN_FLAG_SFG, OP_FLAG_SFG,
ZERO_FLAG_SFG, N94, N95, ADD_OVRFLW_SGF,
inst_ShiftRegister_net3955607, SFT2FRMT_STAGE_VARS_net3955517,
FRMT_STAGE_DATAOUT_net3955445, SGF_STAGE_DMP_net3955499,
NRM_STAGE_Raw_mant_net3955481, INPUT_STAGE_OPERANDY_net3955445,
EXP_STAGE_DMP_net3955499, SHT1_STAGE_DMP_net3955499,
SHT2_STAGE_DMP_net3955499, SHT2_SHIFT_DATA_net3955481,
array_comparators_GTComparator_N0, n830, n831, n832,
DP_OP_15J206_122_2221_n22, DP_OP_15J206_122_2221_n21,
DP_OP_15J206_122_2221_n20, DP_OP_15J206_122_2221_n19,
DP_OP_15J206_122_2221_n18, DP_OP_15J206_122_2221_n17,
DP_OP_15J206_122_2221_n11, DP_OP_15J206_122_2221_n10,
DP_OP_15J206_122_2221_n9, DP_OP_15J206_122_2221_n8,
DP_OP_15J206_122_2221_n7, DP_OP_15J206_122_2221_n6,
DP_OP_15J206_122_2221_n5, DP_OP_15J206_122_2221_n4,
DP_OP_15J206_122_2221_n3, DP_OP_15J206_122_2221_n2,
DP_OP_15J206_122_2221_n1, intadd_470_CI, intadd_470_SUM_3_,
intadd_470_SUM_2_, intadd_470_SUM_1_, intadd_470_SUM_0_,
intadd_470_n4, intadd_470_n3, intadd_470_n2, intadd_470_n1, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857,
n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868,
n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811,
n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861,
n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871,
n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881,
n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891,
n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901,
n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911,
n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921,
n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931,
n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971,
n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981,
n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991,
n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001,
n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011,
n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021,
n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031,
n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041,
n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051,
n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061,
n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071,
n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081,
n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091,
n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401,
n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411,
n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [62:0] intDY_EWSW;
wire [62:0] DMP_INIT_EWSW;
wire [57:0] DmP_INIT_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [5:0] Shift_amount_EXP_EW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [5:0] LZD_raw_out_EWR;
wire [5:2] shft_value_mux_o_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [89:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [54:0] sftr_odat_SHT2_SWR;
wire [5:0] LZD_output_NRM2_EW;
wire [10:0] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [54:2] DmP_mant_SFG_SWR;
wire [54:1] Raw_mant_SGF;
wire [63:0] formatted_number_W;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_103 inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n832), .ENCLK(inst_ShiftRegister_net3955607), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W17_102 SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[1]), .ENCLK(
SFT2FRMT_STAGE_VARS_net3955517), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_6 FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[0]), .ENCLK(
FRMT_STAGE_DATAOUT_net3955445), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_5 SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(n_21_net_), .ENCLK(SGF_STAGE_DMP_net3955499), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_0_1 NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[2]), .ENCLK(
NRM_STAGE_Raw_mant_net3955481), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_7 INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(enable_Pipeline_input), .ENCLK(
INPUT_STAGE_OPERANDY_net3955445), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_9 EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_6), .ENCLK(EXP_STAGE_DMP_net3955499),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_8 SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_5), .ENCLK(SHT1_STAGE_DMP_net3955499),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_7 SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(SHT2_STAGE_DMP_net3955499), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_0_4 SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(n_7_net_), .ENCLK(SHT2_SHIFT_DATA_net3955481), .TE(1'b0) );
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n2536), .CK(
inst_ShiftRegister_net3955607), .RN(n2503), .Q(Shift_reg_FLAGS_7_6) );
DFFRXLTS inst_ShiftRegister_Q_reg_5_ ( .D(Shift_reg_FLAGS_7_6), .CK(
inst_ShiftRegister_net3955607), .RN(n2487), .Q(Shift_reg_FLAGS_7_5) );
DFFRXLTS inst_ShiftRegister_Q_reg_4_ ( .D(Shift_reg_FLAGS_7_5), .CK(
inst_ShiftRegister_net3955607), .RN(n2488), .QN(n852) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
inst_ShiftRegister_net3955607), .RN(n2504), .Q(Shift_reg_FLAGS_7[3])
);
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(Shift_reg_FLAGS_7[3]), .CK(
inst_ShiftRegister_net3955607), .RN(n2488), .Q(Shift_reg_FLAGS_7[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(Shift_amount_EXP_EW[0]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2490), .Q(Shift_amount_SHT1_EWR[0])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(Shift_amount_EXP_EW[1]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(Shift_amount_SHT1_EWR[1])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(Shift_amount_EXP_EW[2]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2494), .Q(Shift_amount_SHT1_EWR[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(Shift_amount_EXP_EW[3]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(Shift_amount_SHT1_EWR[3])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(Shift_amount_EXP_EW[4]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(Shift_amount_SHT1_EWR[4])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(Shift_amount_EXP_EW[5]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2494), .Q(Shift_amount_SHT1_EWR[5])
);
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n2498),
.Q(ready) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(formatted_number_W[52]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[52])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(formatted_number_W[53]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2506), .Q(final_result_ieee[53])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(formatted_number_W[54]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2506), .Q(final_result_ieee[54])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(formatted_number_W[55]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2512), .Q(final_result_ieee[55])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(formatted_number_W[56]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2524), .Q(final_result_ieee[56])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(formatted_number_W[57]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2528), .Q(final_result_ieee[57])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(formatted_number_W[58]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2511), .Q(final_result_ieee[58])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(formatted_number_W[59]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2520), .Q(final_result_ieee[59])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(formatted_number_W[60]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2515), .Q(final_result_ieee[60])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(formatted_number_W[61]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2527), .Q(final_result_ieee[61])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(formatted_number_W[62]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2512), .Q(final_result_ieee[62])
);
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n2484), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2490), .Q(underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(array_comparators_GTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3955445), .RN(n2504), .Q(overflow_flag) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(Data_X[18]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDX_EWSW[18]), .QN(
n2404) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(DmP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(DmP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(DmP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(DmP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2505), .Q(DmP_mant_SHT1_SW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(DmP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(DmP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2495), .Q(DmP_mant_SHT1_SW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(DmP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(DmP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_mant_SHT1_SW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(DmP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(DmP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(DmP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(DmP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(DmP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(DmP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2489), .Q(DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(DmP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(DmP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(DmP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2488), .Q(DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(DmP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(DmP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(DmP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2487), .Q(DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(DmP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(DmP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(DmP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2487), .Q(DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(DmP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(DmP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(DmP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(DmP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(DmP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2489), .Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(DmP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(DmP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(DmP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(DmP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2492), .Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(DmP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(DmP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(DmP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(DmP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(DmP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(DmP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(DmP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(DmP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(DmP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(DmP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(DmP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(DmP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(DmP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(DmP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_mant_SHT1_SW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(DmP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_EXP_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(DmP_EXP_EWSW[23]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_mant_SHT1_SW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(DmP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_EXP_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(DmP_EXP_EWSW[24]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_mant_SHT1_SW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(DmP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_EXP_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(DmP_EXP_EWSW[25]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_mant_SHT1_SW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(DmP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_EXP_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(DmP_EXP_EWSW[26]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_mant_SHT1_SW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(DmP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_EXP_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(DmP_EXP_EWSW[27]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_mant_SHT1_SW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(DmP_INIT_EWSW[28]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2494), .Q(DmP_EXP_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(DmP_EXP_EWSW[28]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2488), .Q(DmP_mant_SHT1_SW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(DmP_INIT_EWSW[29]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(DmP_EXP_EWSW[29]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2488), .Q(DmP_mant_SHT1_SW[29]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(DmP_INIT_EWSW[30]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_EXP_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(DmP_EXP_EWSW[30]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2494), .Q(DmP_mant_SHT1_SW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(DmP_INIT_EWSW[31]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_EXP_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(DmP_EXP_EWSW[31]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2488), .Q(DmP_mant_SHT1_SW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(DmP_INIT_EWSW[32]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_EXP_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(DmP_EXP_EWSW[32]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_mant_SHT1_SW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(DmP_INIT_EWSW[33]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_EXP_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(DmP_EXP_EWSW[33]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_mant_SHT1_SW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(DmP_INIT_EWSW[34]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_EXP_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(DmP_EXP_EWSW[34]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_mant_SHT1_SW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(DmP_INIT_EWSW[35]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_EXP_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(DmP_EXP_EWSW[35]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_mant_SHT1_SW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(DmP_INIT_EWSW[36]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(DmP_EXP_EWSW[36]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[36]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(DmP_INIT_EWSW[37]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(DmP_EXP_EWSW[37]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_mant_SHT1_SW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(DmP_INIT_EWSW[38]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_EXP_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(DmP_EXP_EWSW[38]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_mant_SHT1_SW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(DmP_INIT_EWSW[39]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(DmP_EXP_EWSW[39]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(DmP_INIT_EWSW[40]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(DmP_EXP_EWSW[40]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_mant_SHT1_SW[40]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(DmP_INIT_EWSW[41]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(DmP_EXP_EWSW[41]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_mant_SHT1_SW[41]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(DmP_INIT_EWSW[42]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_EXP_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(DmP_EXP_EWSW[42]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_mant_SHT1_SW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(DmP_INIT_EWSW[43]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_EXP_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(DmP_EXP_EWSW[43]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_mant_SHT1_SW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(DmP_INIT_EWSW[44]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(DmP_EXP_EWSW[44]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_mant_SHT1_SW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(DmP_INIT_EWSW[45]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_EXP_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(DmP_EXP_EWSW[45]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_mant_SHT1_SW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(DmP_INIT_EWSW[46]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(DmP_EXP_EWSW[46]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[46]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(DmP_INIT_EWSW[47]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(DmP_EXP_EWSW[47]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_mant_SHT1_SW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(DmP_INIT_EWSW[48]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(DmP_EXP_EWSW[48]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_mant_SHT1_SW[48]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(DmP_INIT_EWSW[49]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_EXP_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(DmP_EXP_EWSW[49]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_mant_SHT1_SW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(DmP_INIT_EWSW[50]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_EXP_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(DmP_EXP_EWSW[50]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(DmP_INIT_EWSW[51]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_EXP_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(DmP_EXP_EWSW[51]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_mant_SHT1_SW[51]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_52_ ( .D(DmP_INIT_EWSW[52]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[52]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_53_ ( .D(DmP_INIT_EWSW[53]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_EXP_EWSW[53]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_54_ ( .D(DmP_INIT_EWSW[54]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[54]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_55_ ( .D(DmP_INIT_EWSW[55]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_EXP_EWSW[55]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_56_ ( .D(DmP_INIT_EWSW[56]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[56]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_57_ ( .D(DmP_INIT_EWSW[57]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_EXP_EWSW[57]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(DMP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(DMP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(DMP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(DMP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(DMP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(DMP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(DMP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(DMP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(DMP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(DMP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(DMP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2490), .Q(DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(DMP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(DMP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(DMP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(DMP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(DMP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(DMP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(DMP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2503), .Q(DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(DMP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(DMP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(DMP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(DMP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2504), .Q(DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(DMP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(DMP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(DMP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(DMP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(DMP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(DMP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(DMP_INIT_EWSW[28]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(DMP_INIT_EWSW[29]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(DMP_INIT_EWSW[30]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2512), .Q(DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(DMP_INIT_EWSW[31]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(DMP_INIT_EWSW[32]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(DMP_INIT_EWSW[33]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(DMP_INIT_EWSW[34]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(DMP_INIT_EWSW[35]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(DMP_INIT_EWSW[36]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(DMP_INIT_EWSW[37]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(DMP_INIT_EWSW[38]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(DMP_INIT_EWSW[39]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2512), .Q(DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(DMP_INIT_EWSW[40]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(DMP_INIT_EWSW[41]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(DMP_INIT_EWSW[42]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n839), .Q(DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(DMP_INIT_EWSW[43]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2516), .Q(DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(DMP_INIT_EWSW[44]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(DMP_INIT_EWSW[45]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(DMP_INIT_EWSW[46]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(DMP_INIT_EWSW[47]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(DMP_INIT_EWSW[48]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(DMP_INIT_EWSW[49]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(DMP_INIT_EWSW[50]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(DMP_INIT_EWSW[51]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2516), .Q(DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(DMP_INIT_EWSW[52]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_EXP_EWSW[52]), .QN(n920)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_53_ ( .D(DMP_INIT_EWSW[53]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_EXP_EWSW[53]), .QN(n2424) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_54_ ( .D(DMP_INIT_EWSW[54]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_EXP_EWSW[54]), .QN(n2474) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_55_ ( .D(DMP_INIT_EWSW[55]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_EXP_EWSW[55]), .QN(n2473) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_56_ ( .D(DMP_INIT_EWSW[56]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_EXP_EWSW[56]), .QN(n2482) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_57_ ( .D(DMP_INIT_EWSW[57]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_EXP_EWSW[57]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(DMP_INIT_EWSW[58]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(DMP_INIT_EWSW[59]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(DMP_INIT_EWSW[60]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(DMP_INIT_EWSW[61]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(DMP_INIT_EWSW[62]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2519), .Q(ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2515), .Q(OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2522), .Q(SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(DMP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(DMP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(DMP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(DMP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(DMP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(DMP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(DMP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(DMP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(DMP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(DMP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(DMP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(DMP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2516), .Q(DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(DMP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(DMP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(DMP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(DMP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(DMP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(DMP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(DMP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(DMP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2496), .Q(DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(DMP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(DMP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(DMP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(DMP_EXP_EWSW[23]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(DMP_EXP_EWSW[24]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(DMP_EXP_EWSW[25]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(DMP_EXP_EWSW[26]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(DMP_EXP_EWSW[27]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(DMP_EXP_EWSW[28]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(DMP_EXP_EWSW[29]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2521), .Q(DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(DMP_EXP_EWSW[30]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2488), .Q(DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(DMP_EXP_EWSW[31]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2521), .Q(DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(DMP_EXP_EWSW[32]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(DMP_EXP_EWSW[33]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(DMP_EXP_EWSW[34]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(DMP_EXP_EWSW[35]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2504), .Q(DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(DMP_EXP_EWSW[36]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2521), .Q(DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(DMP_EXP_EWSW[37]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(DMP_EXP_EWSW[38]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(DMP_EXP_EWSW[39]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(DMP_EXP_EWSW[40]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(DMP_EXP_EWSW[41]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(DMP_EXP_EWSW[42]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n838), .Q(DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(DMP_EXP_EWSW[43]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(DMP_EXP_EWSW[44]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(DMP_EXP_EWSW[45]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(DMP_EXP_EWSW[46]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2485), .Q(DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(DMP_EXP_EWSW[47]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(DMP_EXP_EWSW[48]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(DMP_EXP_EWSW[49]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(DMP_EXP_EWSW[50]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(DMP_EXP_EWSW[51]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(DMP_EXP_EWSW[52]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(DMP_EXP_EWSW[53]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(DMP_EXP_EWSW[54]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(DMP_EXP_EWSW[55]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n839), .Q(DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(DMP_EXP_EWSW[56]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(DMP_EXP_EWSW[57]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(DMP_EXP_EWSW[58]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(DMP_EXP_EWSW[59]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(DMP_EXP_EWSW[60]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(DMP_EXP_EWSW[61]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n839), .Q(DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(DMP_EXP_EWSW[62]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2524), .Q(ZERO_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2511), .Q(OP_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2523), .Q(SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT1_EWSW[0]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT1_EWSW[1]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT1_EWSW[2]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT1_EWSW[3]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2496), .Q(DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT1_EWSW[4]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT1_EWSW[5]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT1_EWSW[6]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT1_EWSW[7]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT1_EWSW[8]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT1_EWSW[9]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT1_EWSW[10]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT1_EWSW[11]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2503), .Q(DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT1_EWSW[12]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT1_EWSW[13]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT1_EWSW[14]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT1_EWSW[15]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT1_EWSW[16]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT1_EWSW[17]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2530), .Q(DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT1_EWSW[18]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT1_EWSW[19]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT1_EWSW[20]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2512), .Q(DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT1_EWSW[21]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2530), .Q(DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT1_EWSW[22]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT1_EWSW[23]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SHT2_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT1_EWSW[24]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT2_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT1_EWSW[25]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2494), .Q(DMP_SHT2_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT1_EWSW[26]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2531), .Q(DMP_SHT2_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT1_EWSW[27]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT2_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT1_EWSW[28]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT2_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT1_EWSW[29]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT2_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT1_EWSW[30]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT2_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(DMP_SHT1_EWSW[31]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_SHT2_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(DMP_SHT1_EWSW[32]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT2_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(DMP_SHT1_EWSW[33]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SHT2_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(DMP_SHT1_EWSW[34]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT2_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(DMP_SHT1_EWSW[35]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2502), .Q(DMP_SHT2_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(DMP_SHT1_EWSW[36]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT2_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(DMP_SHT1_EWSW[37]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(DMP_SHT1_EWSW[38]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(DMP_SHT1_EWSW[39]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(DMP_SHT1_EWSW[40]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(DMP_SHT1_EWSW[41]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(DMP_SHT1_EWSW[42]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(DMP_SHT1_EWSW[43]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(DMP_SHT1_EWSW[44]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(DMP_SHT1_EWSW[45]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(DMP_SHT1_EWSW[46]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(DMP_SHT1_EWSW[47]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(DMP_SHT1_EWSW[48]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2494), .Q(DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(DMP_SHT1_EWSW[49]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2503), .Q(DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(DMP_SHT1_EWSW[50]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2531), .Q(DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(DMP_SHT1_EWSW[51]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2501), .Q(DMP_SHT2_EWSW[51]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_51_ ( .D(DMP_SHT2_EWSW[51]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2496), .QN(n870) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(DMP_SHT1_EWSW[52]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(DMP_SHT2_EWSW[52]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(DMP_SFG[52]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2515), .Q(DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(DMP_exp_NRM_EW[0]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2523), .Q(DMP_exp_NRM2_EW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(DMP_SHT1_EWSW[53]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(DMP_SHT2_EWSW[53]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(DMP_SFG[53]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(DMP_exp_NRM_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(DMP_exp_NRM_EW[1]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2520), .Q(DMP_exp_NRM2_EW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(DMP_SHT1_EWSW[54]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(DMP_SHT2_EWSW[54]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(DMP_SFG[54]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2514), .Q(DMP_exp_NRM_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(DMP_exp_NRM_EW[2]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2499), .Q(DMP_exp_NRM2_EW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(DMP_SHT1_EWSW[55]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(DMP_SHT2_EWSW[55]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(DMP_SFG[55]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(DMP_exp_NRM_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(DMP_exp_NRM_EW[3]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2491), .Q(DMP_exp_NRM2_EW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(DMP_SHT1_EWSW[56]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2531), .Q(DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(DMP_SHT2_EWSW[56]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(DMP_SFG[56]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(DMP_exp_NRM_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(DMP_exp_NRM_EW[4]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2531), .Q(DMP_exp_NRM2_EW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(DMP_SHT1_EWSW[57]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(DMP_SHT2_EWSW[57]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(DMP_SFG[57]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2501), .Q(DMP_exp_NRM_EW[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(DMP_exp_NRM_EW[5]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2509), .Q(DMP_exp_NRM2_EW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(DMP_SHT1_EWSW[58]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(DMP_SHT2_EWSW[58]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(DMP_SFG[58]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(DMP_exp_NRM_EW[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(DMP_exp_NRM_EW[6]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2488), .Q(DMP_exp_NRM2_EW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(DMP_SHT1_EWSW[59]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2531), .Q(DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(DMP_SHT2_EWSW[59]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(DMP_SFG[59]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2505), .Q(DMP_exp_NRM_EW[7]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(DMP_exp_NRM_EW[7]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2516), .Q(DMP_exp_NRM2_EW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(DMP_SHT1_EWSW[60]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(DMP_SHT2_EWSW[60]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(DMP_SFG[60]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(DMP_exp_NRM_EW[8]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(DMP_exp_NRM_EW[8]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2529), .Q(DMP_exp_NRM2_EW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(DMP_SHT1_EWSW[61]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(DMP_SHT2_EWSW[61]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2496), .Q(DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(DMP_SFG[61]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2489), .Q(DMP_exp_NRM_EW[9]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(DMP_exp_NRM_EW[9]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2528), .Q(DMP_exp_NRM2_EW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(DMP_SHT1_EWSW[62]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(DMP_SHT2_EWSW[62]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(DMP_SFG[62]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(DMP_exp_NRM_EW[10]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(DMP_exp_NRM_EW[10]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2521), .Q(DMP_exp_NRM2_EW[10])
);
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2504), .Q(ZERO_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n840), .Q(OP_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2499), .Q(SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2490), .Q(ZERO_FLAG_SFG) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2490), .Q(OP_FLAG_SFG) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(Raw_mant_SGF[2]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .QN(n854) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(Raw_mant_SGF[22]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2531), .QN(n851) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(Raw_mant_SGF[27]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2530), .QN(n850) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(Raw_mant_SGF[44]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2527), .QN(n849) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(Raw_mant_SGF[53]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2506), .QN(n842) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(Raw_mant_SGF[54]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2492), .Q(Raw_mant_NRM_SWR[54]),
.QN(n2421) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(LZD_raw_out_EWR[2]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2515), .Q(LZD_output_NRM2_EW[2])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(LZD_raw_out_EWR[3]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n839), .Q(LZD_output_NRM2_EW[3])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(LZD_raw_out_EWR[1]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2520), .Q(LZD_output_NRM2_EW[1])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(LZD_raw_out_EWR[4]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2511), .Q(LZD_output_NRM2_EW[4])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(LZD_raw_out_EWR[0]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n839), .Q(LZD_output_NRM2_EW[0])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(LZD_raw_out_EWR[5]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2515), .Q(LZD_output_NRM2_EW[5])
);
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2511), .Q(ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2524), .Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1SHT2), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2528), .Q(zero_flag) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2492), .Q(SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2492), .Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(formatted_number_W[63]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[63])
);
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(Data_array_SWR[51]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2492), .QN(n867) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(Data_array_SWR[49]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n838), .QN(n861) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(Data_array_SWR[48]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2526), .QN(n844) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(Data_array_SWR[46]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2514), .QN(n845) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(Data_array_SWR[44]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2513), .QN(n864) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(Data_array_SWR[41]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2513), .QN(n841) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(Data_array_SWR[40]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2525), .QN(n863) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(Data_array_SWR[38]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2525), .QN(n865) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(Data_array_SWR[37]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2511), .QN(n858) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(Data_array_SWR[36]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2521), .QN(n847) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(Data_array_SWR[34]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2499), .QN(n846) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(Data_array_SWR[28]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2529), .QN(n866) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(Data_array_SWR[23]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2522), .QN(n848) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(Data_array_SWR[22]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .QN(n843) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(Data_array_SWR[21]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .QN(n859) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(Data_array_SWR[18]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .QN(n856) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(Data_array_SWR[12]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .QN(n862) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(Data_array_SWR[11]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .QN(n871) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(Data_array_SWR[10]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .QN(n869) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(Data_array_SWR[9]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .QN(n868) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(Data_array_SWR[3]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .Q(Data_array_SWR[58]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(Data_array_SWR[2]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2531), .Q(Data_array_SWR[57]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(Data_array_SWR[1]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .Q(Data_array_SWR[56]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(Data_array_SWR[0]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .Q(Data_array_SWR[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(formatted_number_W[25]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[25])
);
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2534), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2528), .Q(left_right_SHT2) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(sftr_odat_SHT2_SWR[1]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(N95) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(sftr_odat_SHT2_SWR[54]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2521), .Q(DmP_mant_SFG_SWR[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(formatted_number_W[0]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[0])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(formatted_number_W[1]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2512), .Q(final_result_ieee[1])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(formatted_number_W[2]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2515), .Q(final_result_ieee[2])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(formatted_number_W[3]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2518), .Q(final_result_ieee[3])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(formatted_number_W[4]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2520), .Q(final_result_ieee[4])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(formatted_number_W[5]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[5])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(formatted_number_W[6]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[6])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(formatted_number_W[7]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[7])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(formatted_number_W[8]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[8])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(formatted_number_W[9]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(formatted_number_W[10]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[10])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(formatted_number_W[11]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[11])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(formatted_number_W[12]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[12])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(formatted_number_W[13]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[13])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(formatted_number_W[14]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[14])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(formatted_number_W[15]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[15])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(formatted_number_W[16]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[16])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(formatted_number_W[17]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[17])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(formatted_number_W[18]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[18])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(formatted_number_W[19]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[19])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(formatted_number_W[20]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[20])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(formatted_number_W[21]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[21])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(formatted_number_W[22]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[22])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(formatted_number_W[23]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[23])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(formatted_number_W[24]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[24])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(formatted_number_W[26]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[26])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(formatted_number_W[27]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[27])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(formatted_number_W[28]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[28])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(formatted_number_W[29]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[29])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(formatted_number_W[30]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2510), .Q(final_result_ieee[30])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(formatted_number_W[31]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2529), .Q(final_result_ieee[31])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(formatted_number_W[32]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2501), .Q(final_result_ieee[32])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(formatted_number_W[33]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2517), .Q(final_result_ieee[33])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(formatted_number_W[34]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2529), .Q(final_result_ieee[34])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(formatted_number_W[35]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2528), .Q(final_result_ieee[35])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(formatted_number_W[36]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2486), .Q(final_result_ieee[36])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(formatted_number_W[37]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n840), .Q(final_result_ieee[37])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(formatted_number_W[38]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2510), .Q(final_result_ieee[38])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(formatted_number_W[39]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2529), .Q(final_result_ieee[39])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(formatted_number_W[40]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2499), .Q(final_result_ieee[40])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(formatted_number_W[41]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2529), .Q(final_result_ieee[41])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(formatted_number_W[42]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2519), .Q(final_result_ieee[42])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(formatted_number_W[43]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2519), .Q(final_result_ieee[43])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(formatted_number_W[44]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[44])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(formatted_number_W[45]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2512), .Q(final_result_ieee[45])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(formatted_number_W[46]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2507), .Q(final_result_ieee[46])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(formatted_number_W[47]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2506), .Q(final_result_ieee[47])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(formatted_number_W[48]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2524), .Q(final_result_ieee[48])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(formatted_number_W[49]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2507), .Q(final_result_ieee[49])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(formatted_number_W[50]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2524), .Q(final_result_ieee[50])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(formatted_number_W[51]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2523), .Q(final_result_ieee[51])
);
CMPR32X2TS DP_OP_15J206_122_2221_U12 ( .A(DMP_exp_NRM2_EW[0]), .B(n2244),
.C(DP_OP_15J206_122_2221_n22), .CO(DP_OP_15J206_122_2221_n11), .S(
exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_15J206_122_2221_U11 ( .A(DP_OP_15J206_122_2221_n21), .B(
DMP_exp_NRM2_EW[1]), .C(DP_OP_15J206_122_2221_n11), .CO(
DP_OP_15J206_122_2221_n10), .S(exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J206_122_2221_U10 ( .A(DP_OP_15J206_122_2221_n20), .B(
DMP_exp_NRM2_EW[2]), .C(DP_OP_15J206_122_2221_n10), .CO(
DP_OP_15J206_122_2221_n9), .S(exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J206_122_2221_U9 ( .A(DP_OP_15J206_122_2221_n19), .B(
DMP_exp_NRM2_EW[3]), .C(DP_OP_15J206_122_2221_n9), .CO(
DP_OP_15J206_122_2221_n8), .S(exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_15J206_122_2221_U8 ( .A(DP_OP_15J206_122_2221_n18), .B(
DMP_exp_NRM2_EW[4]), .C(DP_OP_15J206_122_2221_n8), .CO(
DP_OP_15J206_122_2221_n7), .S(exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_15J206_122_2221_U7 ( .A(DP_OP_15J206_122_2221_n17), .B(
DMP_exp_NRM2_EW[5]), .C(DP_OP_15J206_122_2221_n7), .CO(
DP_OP_15J206_122_2221_n6), .S(exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS intadd_470_U5 ( .A(DmP_EXP_EWSW[53]), .B(n2424), .C(intadd_470_CI), .CO(intadd_470_n4), .S(intadd_470_SUM_0_) );
CMPR32X2TS intadd_470_U4 ( .A(DmP_EXP_EWSW[54]), .B(n2474), .C(intadd_470_n4), .CO(intadd_470_n3), .S(intadd_470_SUM_1_) );
CMPR32X2TS intadd_470_U3 ( .A(DmP_EXP_EWSW[55]), .B(n2473), .C(intadd_470_n3), .CO(intadd_470_n2), .S(intadd_470_SUM_2_) );
CMPR32X2TS intadd_470_U2 ( .A(DmP_EXP_EWSW[56]), .B(n2482), .C(intadd_470_n2), .CO(intadd_470_n1), .S(intadd_470_SUM_3_) );
DFFSX2TS R_0 ( .D(n2483), .CK(INPUT_STAGE_OPERANDY_net3955445), .SN(n2486),
.Q(n2535) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(Data_Y[47]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDY_EWSW[47]), .QN(
n2481) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(Data_Y[19]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .Q(intDY_EWSW[19]), .QN(
n2480) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(Data_Y[0]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[0]), .QN(
n2479) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(Data_Y[1]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2492), .Q(intDY_EWSW[1]), .QN(
n2478) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(Data_Y[38]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDY_EWSW[38]), .QN(
n2477) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(Data_Y[37]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[37]), .QN(
n2476) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(Data_Y[18]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDY_EWSW[18]), .QN(
n2475) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(Raw_mant_SGF[9]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n839), .Q(Raw_mant_NRM_SWR[9]),
.QN(n2472) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(Data_Y[46]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDY_EWSW[46]), .QN(
n2471) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n830), .CK(clk), .RN(
n2485), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n2470) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(Data_Y[32]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[32]), .QN(
n2469) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(Data_Y[51]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDY_EWSW[51]), .QN(
n2468) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(Data_Y[52]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDY_EWSW[52]), .QN(
n2467) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(Data_Y[48]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDY_EWSW[48]), .QN(
n2466) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(Data_Y[10]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDY_EWSW[10]), .QN(
n2465) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(Data_Y[44]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDY_EWSW[44]), .QN(
n2464) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(Data_Y[9]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDY_EWSW[9]), .QN(
n2463) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(Data_Y[40]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[40]), .QN(
n2462) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(Data_Y[2]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2493), .Q(intDY_EWSW[2]), .QN(
n2461) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(Data_Y[56]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDY_EWSW[56]), .QN(
n2460) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(Data_Y[34]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[34]), .QN(
n2459) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(Data_Y[30]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDY_EWSW[30]), .QN(
n2458) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(Data_Y[22]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[22]), .QN(
n2457) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(Data_Y[14]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .Q(intDY_EWSW[14]), .QN(
n2456) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(Data_Y[27]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[27]), .QN(
n2455) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(Data_Y[57]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2502), .Q(intDY_EWSW[57]), .QN(
n2454) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(Data_Y[45]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[45]), .QN(
n2453) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(Data_Y[42]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[42]), .QN(
n2452) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(Data_Y[54]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDY_EWSW[54]), .QN(
n2451) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(Data_Y[8]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDY_EWSW[8]), .QN(
n2450) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(Data_Y[49]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2502), .Q(intDY_EWSW[49]), .QN(
n2449) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(Data_Y[11]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[11]), .QN(
n2448) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(Data_Y[24]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n838), .Q(intDY_EWSW[24]), .QN(
n2447) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(Data_Y[17]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2502), .Q(intDY_EWSW[17]), .QN(
n2446) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(Data_Y[16]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDY_EWSW[16]), .QN(
n2445) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(Data_Y[25]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n1123), .Q(intDY_EWSW[25]), .QN(
n2444) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(Data_Y[26]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[26]), .QN(
n2443) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(Data_Y[36]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDY_EWSW[36]), .QN(
n2442) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(Data_Y[28]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDY_EWSW[28]), .QN(
n2441) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(Data_Y[20]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n839), .Q(intDY_EWSW[20]), .QN(
n2440) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(Data_Y[12]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDY_EWSW[12]), .QN(
n2439) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(Data_Y[50]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDY_EWSW[50]), .QN(
n2438) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(sftr_odat_SHT2_SWR[51]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_mant_SFG_SWR[51]), .QN(
n2423) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_49_ ( .D(DMP_SHT2_EWSW[49]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2521), .Q(DMP_SFG[49]), .QN(n2422) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_50_ ( .D(DMP_SHT2_EWSW[50]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SFG[50]), .QN(n2420) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(sftr_odat_SHT2_SWR[52]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2509), .Q(DmP_mant_SFG_SWR[52]), .QN(
n2419) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(Data_array_SWR[29]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2505), .Q(Data_array_SWR[75]), .QN(
n2418) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(sftr_odat_SHT2_SWR[49]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DmP_mant_SFG_SWR[49]), .QN(
n2417) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_47_ ( .D(DMP_SHT2_EWSW[47]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SFG[47]), .QN(n2416) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_48_ ( .D(DMP_SHT2_EWSW[48]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SFG[48]), .QN(n2415) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(Data_array_SWR[43]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2514), .Q(Data_array_SWR[83]), .QN(
n2414) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(Data_X[60]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[60]), .QN(
n2413) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(Data_X[58]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDX_EWSW[58]), .QN(
n2412) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(Data_array_SWR[54]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2493), .Q(Data_array_SWR[89]), .QN(
n2411) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(Data_X[62]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[62]), .QN(
n2410) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(Data_array_SWR[45]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2514), .Q(Data_array_SWR[84]), .QN(
n2409) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(Data_array_SWR[52]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .Q(Data_array_SWR[87]), .QN(
n2408) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(Data_array_SWR[24]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2524), .Q(Data_array_SWR[71]), .QN(
n2407) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(Data_X[61]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[61]), .QN(
n2406) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(Data_Y[39]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDY_EWSW[39]), .QN(
n2405) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(Data_X[52]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .Q(intDX_EWSW[52]), .QN(
n2401) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(Data_X[48]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .Q(intDX_EWSW[48]), .QN(
n2400) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(Data_X[10]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[10]), .QN(
n2399) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(Data_X[57]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .QN(n2398) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(Data_X[45]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .QN(n2397) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(Data_X[33]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2489), .QN(n2396) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(Data_X[8]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .QN(n2395) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(Data_X[44]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2502), .Q(intDX_EWSW[44]), .QN(
n2393) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(Data_X[53]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .QN(n2392) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(Data_X[49]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .QN(n2391) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(Data_X[11]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .QN(n2390) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(Data_X[38]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDX_EWSW[38]), .QN(
n2388) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(Data_X[37]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDX_EWSW[37]), .QN(
n2387) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(Data_X[16]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[16]), .QN(
n2383) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(Data_X[35]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2495), .QN(n2381) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(Data_X[31]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2505), .QN(n2380) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(Data_X[25]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .QN(n2379) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(Data_X[15]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .QN(n2378) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(Data_X[3]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .QN(n2377) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(Data_X[6]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDX_EWSW[6]), .QN(
n2371) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(Data_X[4]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDX_EWSW[4]), .QN(
n2370) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(Data_X[1]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDX_EWSW[1]), .QN(
n2369) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(Data_X[36]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2505), .Q(intDX_EWSW[36]), .QN(
n2368) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(Data_X[17]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[17]), .QN(
n2367) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(sftr_odat_SHT2_SWR[47]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DmP_mant_SFG_SWR[47]), .QN(
n2366) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_45_ ( .D(DMP_SHT2_EWSW[45]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SFG[45]), .QN(n2365) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(Data_X[5]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[5]), .QN(
n2364) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(sftr_odat_SHT2_SWR[45]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(DmP_mant_SFG_SWR[45]), .QN(
n2363) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(sftr_odat_SHT2_SWR[43]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2524), .Q(DmP_mant_SFG_SWR[43]), .QN(
n2362) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_43_ ( .D(DMP_SHT2_EWSW[43]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_SFG[43]), .QN(n2361) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_41_ ( .D(DMP_SHT2_EWSW[41]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SFG[41]), .QN(n2360) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(sftr_odat_SHT2_SWR[48]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DmP_mant_SFG_SWR[48]), .QN(
n2359) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(sftr_odat_SHT2_SWR[41]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DmP_mant_SFG_SWR[41]), .QN(
n2358) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_39_ ( .D(DMP_SHT2_EWSW[39]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SFG[39]), .QN(n2357) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(Raw_mant_SGF[35]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(Raw_mant_NRM_SWR[35]),
.QN(n2356) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_44_ ( .D(DMP_SHT2_EWSW[44]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SFG[44]), .QN(n2355) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(Raw_mant_SGF[4]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(Raw_mant_NRM_SWR[4]),
.QN(n2354) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(shft_value_mux_o_EWR[5]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2523), .Q(shift_value_SHT2_EWR[5]),
.QN(n2353) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(sftr_odat_SHT2_SWR[39]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2507), .Q(DmP_mant_SFG_SWR[39]), .QN(
n2352) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_37_ ( .D(DMP_SHT2_EWSW[37]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SFG[37]), .QN(n2351) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(Raw_mant_SGF[17]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2510), .Q(Raw_mant_NRM_SWR[17]),
.QN(n2350) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(shft_value_mux_o_EWR[3]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2518), .Q(shift_value_SHT2_EWR[3]),
.QN(n2349) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(sftr_odat_SHT2_SWR[37]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2530), .Q(DmP_mant_SFG_SWR[37]), .QN(
n2348) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(sftr_odat_SHT2_SWR[35]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2516), .Q(DmP_mant_SFG_SWR[35]), .QN(
n2347) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_35_ ( .D(DMP_SHT2_EWSW[35]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SFG[35]), .QN(n2346) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_33_ ( .D(DMP_SHT2_EWSW[33]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_SFG[33]), .QN(n2345) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(Raw_mant_SGF[41]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2508), .Q(Raw_mant_NRM_SWR[41]),
.QN(n2344) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_42_ ( .D(DMP_SHT2_EWSW[42]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SFG[42]), .QN(n2343) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(Raw_mant_SGF[31]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n1123), .Q(Raw_mant_NRM_SWR[31]),
.QN(n2342) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(Raw_mant_SGF[23]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2516), .Q(Raw_mant_NRM_SWR[23]),
.QN(n2341) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(sftr_odat_SHT2_SWR[33]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DmP_mant_SFG_SWR[33]), .QN(
n2340) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_31_ ( .D(DMP_SHT2_EWSW[31]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SFG[31]), .QN(n2339) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(Raw_mant_SGF[33]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2525), .Q(Raw_mant_NRM_SWR[33]),
.QN(n2338) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(Data_Y[61]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2493), .Q(intDY_EWSW[61]), .QN(
n2337) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(Raw_mant_SGF[6]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2512), .Q(Raw_mant_NRM_SWR[6]),
.QN(n2336) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(sftr_odat_SHT2_SWR[31]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_mant_SFG_SWR[31]), .QN(
n2332) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT2_EWSW[29]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SFG[29]), .QN(n2331) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(sftr_odat_SHT2_SWR[42]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2507), .Q(DmP_mant_SFG_SWR[42]), .QN(
n2330) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(Raw_mant_SGF[11]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2511), .Q(Raw_mant_NRM_SWR[11]),
.QN(n2328) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(sftr_odat_SHT2_SWR[29]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DmP_mant_SFG_SWR[29]), .QN(
n2327) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(sftr_odat_SHT2_SWR[27]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_mant_SFG_SWR[27]), .QN(
n2326) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT2_EWSW[27]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SFG[27]), .QN(n2325) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT2_EWSW[25]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[25]), .QN(n2324) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_38_ ( .D(DMP_SHT2_EWSW[38]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SFG[38]), .QN(n2323) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(sftr_odat_SHT2_SWR[25]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2525), .Q(DmP_mant_SFG_SWR[25]), .QN(
n2322) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT2_EWSW[23]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SFG[23]), .QN(n2321) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(Raw_mant_SGF[15]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(Raw_mant_NRM_SWR[15]),
.QN(n2320) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(sftr_odat_SHT2_SWR[23]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DmP_mant_SFG_SWR[23]), .QN(
n2319) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT2_EWSW[21]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_SFG[21]), .QN(n2318) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_36_ ( .D(DMP_SHT2_EWSW[36]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SFG[36]), .QN(n2317) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(sftr_odat_SHT2_SWR[21]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DmP_mant_SFG_SWR[21]), .QN(
n2316) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(sftr_odat_SHT2_SWR[19]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2512), .Q(DmP_mant_SFG_SWR[19]), .QN(
n2315) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT2_EWSW[19]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SFG[19]), .QN(n2314) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT2_EWSW[17]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SFG[17]), .QN(n2313) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(Raw_mant_SGF[20]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2516), .Q(Raw_mant_NRM_SWR[20]),
.QN(n2312) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(sftr_odat_SHT2_SWR[17]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DmP_mant_SFG_SWR[17]), .QN(
n2311) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT2_EWSW[15]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SFG[15]), .QN(n2310) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(sftr_odat_SHT2_SWR[36]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DmP_mant_SFG_SWR[36]), .QN(
n2309) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(sftr_odat_SHT2_SWR[15]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_mant_SFG_SWR[15]), .QN(
n2308) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT2_EWSW[13]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SFG[13]), .QN(n2307) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_32_ ( .D(DMP_SHT2_EWSW[32]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[32]), .QN(n2306) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(sftr_odat_SHT2_SWR[13]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2507), .Q(DmP_mant_SFG_SWR[13]), .QN(
n2305) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT2_EWSW[11]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SFG[11]), .QN(n2303) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT2_EWSW[30]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[30]), .QN(n2299) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(sftr_odat_SHT2_SWR[30]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DmP_mant_SFG_SWR[30]), .QN(
n2293) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT2_EWSW[26]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SFG[26]), .QN(n2290) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(Raw_mant_SGF[34]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2519), .Q(Raw_mant_NRM_SWR[34]),
.QN(n2289) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT2_EWSW[24]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SFG[24]), .QN(n2288) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(sftr_odat_SHT2_SWR[24]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2528), .Q(DmP_mant_SFG_SWR[24]), .QN(
n2287) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT2_EWSW[20]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SFG[20]), .QN(n2286) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(Raw_mant_SGF[42]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2508), .Q(Raw_mant_NRM_SWR[42]),
.QN(n2285) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT2_EWSW[18]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SFG[18]), .QN(n2284) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(sftr_odat_SHT2_SWR[18]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2523), .Q(DmP_mant_SFG_SWR[18]), .QN(
n2283) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT2_EWSW[14]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SFG[14]), .QN(n2282) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT2_EWSW[12]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2512), .Q(DMP_SFG[12]), .QN(n2281) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(sftr_odat_SHT2_SWR[12]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2509), .Q(DmP_mant_SFG_SWR[12]), .QN(
n2280) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(Data_Y[6]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2505), .Q(intDY_EWSW[6]), .QN(
n2275) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(Data_Y[4]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2489), .Q(intDY_EWSW[4]), .QN(
n2274) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(Data_X[59]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDX_EWSW[59]), .QN(
n2273) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(Data_X[39]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2489), .Q(intDX_EWSW[39]), .QN(
n2272) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(Data_X[19]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDX_EWSW[19]), .QN(
n2271) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(Data_X[47]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDX_EWSW[47]), .QN(
n2270) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(Data_X[56]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[56]), .QN(
n2269) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(Data_X[32]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2495), .Q(intDX_EWSW[32]), .QN(
n2268) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(Data_X[55]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[55]), .QN(
n2267) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(Data_X[9]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDX_EWSW[9]), .QN(
n2266) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(Data_X[50]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDX_EWSW[50]), .QN(
n2265) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(Data_X[43]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDX_EWSW[43]), .QN(
n2264) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(Data_X[0]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDX_EWSW[0]), .QN(
n2263) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(Data_X[40]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDX_EWSW[40]), .QN(
n2262) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(Data_X[24]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDX_EWSW[24]), .QN(
n2259) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(Data_X[2]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[2]), .QN(
n2257) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(Data_X[26]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDX_EWSW[26]), .QN(
n2256) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(Data_X[23]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[23]), .QN(
n2255) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(sftr_odat_SHT2_SWR[50]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2521), .Q(DmP_mant_SFG_SWR[50]), .QN(
n2254) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_46_ ( .D(DMP_SHT2_EWSW[46]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SFG[46]), .QN(n2253) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(Data_X[7]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[7]), .QN(
n2252) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(sftr_odat_SHT2_SWR[46]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DmP_mant_SFG_SWR[46]), .QN(
n2251) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(sftr_odat_SHT2_SWR[44]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DmP_mant_SFG_SWR[44]), .QN(
n2250) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(Raw_mant_SGF[3]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(Raw_mant_NRM_SWR[3]),
.QN(n2249) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_40_ ( .D(DMP_SHT2_EWSW[40]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SFG[40]), .QN(n2248) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(Raw_mant_SGF[39]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2514), .Q(Raw_mant_NRM_SWR[39]),
.QN(n2247) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(sftr_odat_SHT2_SWR[40]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2524), .Q(DmP_mant_SFG_SWR[40]), .QN(
n2245) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(sftr_odat_SHT2_SWR[38]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2515), .Q(DmP_mant_SFG_SWR[38]), .QN(
n2243) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_34_ ( .D(DMP_SHT2_EWSW[34]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SFG[34]), .QN(n2242) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(sftr_odat_SHT2_SWR[34]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2514), .Q(DmP_mant_SFG_SWR[34]), .QN(
n2241) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(sftr_odat_SHT2_SWR[32]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DmP_mant_SFG_SWR[32]), .QN(
n2240) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT2_EWSW[28]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2491), .Q(DMP_SFG[28]), .QN(n2239) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(sftr_odat_SHT2_SWR[28]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DmP_mant_SFG_SWR[28]), .QN(
n2238) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(sftr_odat_SHT2_SWR[26]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2525), .Q(DmP_mant_SFG_SWR[26]), .QN(
n2237) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT2_EWSW[22]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SFG[22]), .QN(n2236) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(sftr_odat_SHT2_SWR[22]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DmP_mant_SFG_SWR[22]), .QN(
n2235) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(sftr_odat_SHT2_SWR[20]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2518), .Q(DmP_mant_SFG_SWR[20]), .QN(
n2234) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT2_EWSW[16]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SFG[16]), .QN(n2233) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(sftr_odat_SHT2_SWR[16]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_mant_SFG_SWR[16]), .QN(
n2232) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(sftr_odat_SHT2_SWR[14]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_mant_SFG_SWR[14]), .QN(
n2231) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT2_EWSW[10]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2530), .Q(DMP_SFG[10]), .QN(n2230) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(sftr_odat_SHT2_SWR[8]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_mant_SFG_SWR[8]), .QN(
n2228) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT2_EWSW[4]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SFG[4]), .QN(n2227) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n831), .CK(clk), .RN(
n2487), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2225) );
CMPR32X2TS DP_OP_15J206_122_2221_U6 ( .A(n2244), .B(DMP_exp_NRM2_EW[6]), .C(
DP_OP_15J206_122_2221_n6), .CO(DP_OP_15J206_122_2221_n5), .S(
exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_15J206_122_2221_U5 ( .A(n2244), .B(DMP_exp_NRM2_EW[7]), .C(
DP_OP_15J206_122_2221_n5), .CO(DP_OP_15J206_122_2221_n4), .S(
exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS DP_OP_15J206_122_2221_U4 ( .A(n2244), .B(DMP_exp_NRM2_EW[8]), .C(
DP_OP_15J206_122_2221_n4), .CO(DP_OP_15J206_122_2221_n3), .S(
exp_rslt_NRM2_EW1[8]) );
CMPR32X2TS DP_OP_15J206_122_2221_U3 ( .A(n2244), .B(DMP_exp_NRM2_EW[9]), .C(
DP_OP_15J206_122_2221_n3), .CO(DP_OP_15J206_122_2221_n2), .S(
exp_rslt_NRM2_EW1[9]) );
CMPR32X2TS DP_OP_15J206_122_2221_U2 ( .A(n2244), .B(DMP_exp_NRM2_EW[10]),
.C(DP_OP_15J206_122_2221_n2), .CO(DP_OP_15J206_122_2221_n1), .S(
exp_rslt_NRM2_EW1[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT2_EWSW[9]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SFG[9]), .QN(n2302) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT2_EWSW[8]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SFG[8]), .QN(n2279) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT2_EWSW[7]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_SFG[7]), .QN(n2300) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT2_EWSW[6]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SFG[6]), .QN(n2278) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT2_EWSW[5]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SFG[5]), .QN(n2297) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT2_EWSW[3]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SFG[3]), .QN(n2294) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT2_EWSW[2]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SFG[2]), .QN(n2276) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT2_EWSW[1]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2500), .Q(DMP_SFG[1]), .QN(n2296) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT2_EWSW[0]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SFG[0]), .QN(n2292) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n2536), .CK(clk), .RN(
n2488), .Q(inst_FSM_INPUT_ENABLE_state_reg[1]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(sftr_odat_SHT2_SWR[6]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2529), .Q(DmP_mant_SFG_SWR[6]), .QN(
n2277) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(sftr_odat_SHT2_SWR[7]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_mant_SFG_SWR[7]), .QN(
n2298) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(sftr_odat_SHT2_SWR[9]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2529), .Q(DmP_mant_SFG_SWR[9]), .QN(
n2301) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(sftr_odat_SHT2_SWR[2]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2530), .Q(DmP_mant_SFG_SWR[2]), .QN(
n2291) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(sftr_odat_SHT2_SWR[4]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2510), .Q(DmP_mant_SFG_SWR[4]), .QN(
n2226) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(sftr_odat_SHT2_SWR[5]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2530), .Q(DmP_mant_SFG_SWR[5]), .QN(
n2295) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(sftr_odat_SHT2_SWR[10]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DmP_mant_SFG_SWR[10]), .QN(
n2229) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(sftr_odat_SHT2_SWR[11]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_mant_SFG_SWR[11]), .QN(
n2304) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(Data_Y[23]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .QN(n2433) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(Data_Y[7]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2495), .Q(intDY_EWSW[7]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(Data_Y[5]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .Q(intDY_EWSW[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(Raw_mant_SGF[29]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n1123), .Q(Raw_mant_NRM_SWR[29]),
.QN(n2246) );
DFFRX1TS inst_ShiftRegister_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[1]), .CK(
inst_ShiftRegister_net3955607), .RN(n2487), .Q(Shift_reg_FLAGS_7[0])
);
DFFRX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(ADD_OVRFLW_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2519), .Q(ADD_OVRFLW_NRM2), .QN(
n2244) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(ADD_OVRFLW_SGF), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2525), .Q(ADD_OVRFLW_NRM) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(shft_value_mux_o_EWR[4]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2528), .Q(shift_value_SHT2_EWR[4])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(Raw_mant_SGF[14]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2515), .Q(Raw_mant_NRM_SWR[14])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(Raw_mant_SGF[1]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2514), .Q(Raw_mant_NRM_SWR[1]) );
DFFRX2TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2533), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2522), .Q(bit_shift_SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(Raw_mant_SGF[45]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2524), .Q(Raw_mant_NRM_SWR[45])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(Raw_mant_SGF[7]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2489), .Q(Raw_mant_NRM_SWR[7]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(Raw_mant_SGF[12]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2517), .Q(Raw_mant_NRM_SWR[12])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(Raw_mant_SGF[28]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n1123), .Q(Raw_mant_NRM_SWR[28])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(Raw_mant_SGF[51]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2511), .Q(Raw_mant_NRM_SWR[51])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(Raw_mant_SGF[52]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2520), .Q(Raw_mant_NRM_SWR[52])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(Raw_mant_SGF[38]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2507), .Q(Raw_mant_NRM_SWR[38])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(Data_Y[58]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2505), .Q(intDY_EWSW[58]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(Raw_mant_SGF[25]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2531), .Q(Raw_mant_NRM_SWR[25])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(Data_Y[60]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2489), .Q(intDY_EWSW[60]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(Raw_mant_SGF[32]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2525), .Q(Raw_mant_NRM_SWR[32])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(Raw_mant_SGF[43]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2493), .Q(Raw_mant_NRM_SWR[43])
);
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(sftr_odat_SHT2_SWR[53]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DmP_mant_SFG_SWR[53]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(Raw_mant_SGF[21]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2531), .Q(Raw_mant_NRM_SWR[21])
);
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(Data_array_SWR[16]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[67]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(Data_array_SWR[13]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[64]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(Data_array_SWR[14]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[65]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(Data_array_SWR[15]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[66]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(Data_array_SWR[17]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[68]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(Data_array_SWR[39]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2526), .Q(Data_array_SWR[81]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(Data_array_SWR[42]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2513), .Q(Data_array_SWR[82]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(Raw_mant_SGF[5]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2489), .Q(Raw_mant_NRM_SWR[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(Raw_mant_SGF[19]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2492), .Q(Raw_mant_NRM_SWR[19])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(Raw_mant_SGF[48]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2507), .Q(Raw_mant_NRM_SWR[48])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(Raw_mant_SGF[30]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2525), .Q(Raw_mant_NRM_SWR[30])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(Raw_mant_SGF[50]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2523), .Q(Raw_mant_NRM_SWR[50]),
.QN(n2329) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(Raw_mant_SGF[10]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2529), .Q(Raw_mant_NRM_SWR[10])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(Raw_mant_SGF[36]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2493), .Q(Raw_mant_NRM_SWR[36])
);
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(Data_array_SWR[8]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2531), .Q(Data_array_SWR[63]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(N94), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(Raw_mant_NRM_SWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(sftr_odat_SHT2_SWR[0]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2524), .Q(N94) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(shft_value_mux_o_EWR[2]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .Q(shift_value_SHT2_EWR[2])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(Data_Y[3]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDY_EWSW[3]), .QN(
n2425) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(Data_Y[55]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[55]), .QN(
n2427) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(Data_Y[15]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDY_EWSW[15]), .QN(
n2429) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(Data_Y[31]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDY_EWSW[31]), .QN(
n2430) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(Data_Y[35]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[35]), .QN(
n2431) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(Data_Y[43]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n838), .Q(intDY_EWSW[43]), .QN(
n2432) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(Data_Y[13]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[13]), .QN(
n2434) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(Data_Y[21]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[21]), .QN(
n2435) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(Data_Y[29]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDY_EWSW[29]), .QN(
n2436) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(Data_Y[53]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDY_EWSW[53]), .QN(
n2426) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(Data_Y[33]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[33]), .QN(
n2428) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(Data_Y[41]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n1123), .Q(intDY_EWSW[41]), .QN(
n2437) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(Data_array_SWR[33]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2509), .Q(Data_array_SWR[79]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(sftr_odat_SHT2_SWR[3]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2521), .Q(DmP_mant_SFG_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(Data_array_SWR[30]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2521), .Q(Data_array_SWR[76]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(Data_array_SWR[6]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2531), .Q(Data_array_SWR[61]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(Data_array_SWR[7]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .Q(Data_array_SWR[62]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(Data_X[63]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .Q(intDX_EWSW[63]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(Data_X[51]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDX_EWSW[51]), .QN(
n2394) );
DFFRX2TS inst_ShiftRegister_Q_reg_1_ ( .D(Shift_reg_FLAGS_7[2]), .CK(
inst_ShiftRegister_net3955607), .RN(n2488), .Q(Shift_reg_FLAGS_7[1]),
.QN(n2532) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(Raw_mant_SGF[16]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2529), .Q(Raw_mant_NRM_SWR[16])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(Raw_mant_SGF[18]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2530), .Q(Raw_mant_NRM_SWR[18])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(Raw_mant_SGF[40]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2526), .Q(Raw_mant_NRM_SWR[40])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(Raw_mant_SGF[49]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2515), .Q(Raw_mant_NRM_SWR[49])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(Raw_mant_SGF[13]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2517), .Q(Raw_mant_NRM_SWR[13])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(Raw_mant_SGF[37]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2514), .Q(Raw_mant_NRM_SWR[37])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(Data_Y[62]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2495), .Q(intDY_EWSW[62]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(Raw_mant_SGF[46]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2528), .Q(Raw_mant_NRM_SWR[46]),
.QN(n2335) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(Data_Y[59]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[59]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(Data_array_SWR[25]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2517), .Q(Data_array_SWR[72]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(Data_array_SWR[47]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n838), .Q(Data_array_SWR[85]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(Data_array_SWR[35]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2525), .Q(Data_array_SWR[80]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(Data_array_SWR[31]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n840), .Q(Data_array_SWR[77]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(Data_array_SWR[19]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[69]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(Data_array_SWR[27]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n838), .Q(Data_array_SWR[74]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(Data_array_SWR[53]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n838), .Q(Data_array_SWR[88]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(Data_array_SWR[32]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2509), .Q(Data_array_SWR[78]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(Data_array_SWR[20]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[70]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(Data_array_SWR[26]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2522), .Q(Data_array_SWR[73]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(Raw_mant_SGF[24]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2530), .Q(Raw_mant_NRM_SWR[24])
);
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(Data_X[41]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDX_EWSW[41]), .QN(
n2376) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(Data_X[29]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2493), .Q(intDX_EWSW[29]), .QN(
n2386) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(Data_X[21]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[21]), .QN(
n2384) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(Data_X[13]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .Q(intDX_EWSW[13]), .QN(
n2382) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(Raw_mant_SGF[47]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2515), .Q(Raw_mant_NRM_SWR[47])
);
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(Raw_mant_SGF[8]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2504), .Q(Raw_mant_NRM_SWR[8]),
.QN(n2333) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(Data_X[27]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[27]), .QN(
n2385) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(Data_X[28]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .Q(intDX_EWSW[28]), .QN(
n2375) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(Data_X[20]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[20]), .QN(
n2373) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(Data_X[12]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[12]), .QN(
n2372) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(Data_X[14]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[14]), .QN(
n2258) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(Data_X[54]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDX_EWSW[54]), .QN(
n2402) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(Data_X[34]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2492), .Q(intDX_EWSW[34]), .QN(
n2261) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(Data_X[30]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2493), .Q(intDX_EWSW[30]), .QN(
n2260) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(Data_X[22]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[22]), .QN(
n2374) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(Data_X[42]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDX_EWSW[42]), .QN(
n2389) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(Raw_mant_SGF[26]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2493), .Q(Raw_mant_NRM_SWR[26]),
.QN(n2334) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(Data_array_SWR[50]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n1123), .Q(Data_array_SWR[86]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(Data_X[46]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDX_EWSW[46]), .QN(
n2403) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(Data_array_SWR[5]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2531), .Q(Data_array_SWR[60]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(Data_array_SWR[4]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .Q(Data_array_SWR[59]) );
BUFX6TS U1206 ( .A(n1123), .Y(n2498) );
AOI222X4TS U1207 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[36]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[16]), .C0(Raw_mant_NRM_SWR[38]), .C1(n1342), .Y(n1427) );
AOI222X4TS U1208 ( .A0(n915), .A1(DmP_mant_SHT1_SW[0]), .B0(n2221), .B1(
Raw_mant_NRM_SWR[52]), .C0(n914), .C1(n2533), .Y(n1460) );
AOI2BB1X1TS U1209 ( .A0N(n1602), .A1N(n1601), .B0(n1600), .Y(n1607) );
OAI21X2TS U1210 ( .A0(DmP_mant_SFG_SWR[50]), .A1(DMP_SFG[48]), .B0(n1627),
.Y(n1569) );
AOI21X1TS U1211 ( .A0(n1690), .A1(n1693), .B0(n1694), .Y(n1684) );
OAI21X1TS U1212 ( .A0(n1697), .A1(n1699), .B0(n1591), .Y(n1690) );
OAI21X2TS U1213 ( .A0(DmP_mant_SFG_SWR[46]), .A1(DMP_SFG[44]), .B0(n1653),
.Y(n1565) );
AOI21X1TS U1214 ( .A0(n1618), .A1(n1621), .B0(n1622), .Y(n1697) );
OAI21X1TS U1215 ( .A0(n1716), .A1(n1718), .B0(n1589), .Y(n1709) );
OAI21X1TS U1216 ( .A0(n1729), .A1(n1731), .B0(n1588), .Y(n1722) );
AOI21X1TS U1217 ( .A0(n1735), .A1(n1738), .B0(n1739), .Y(n1729) );
OAI21X1TS U1218 ( .A0(n1742), .A1(n1744), .B0(n1587), .Y(n1735) );
AOI21X1TS U1219 ( .A0(n1748), .A1(n1751), .B0(n1752), .Y(n1742) );
OAI21X1TS U1220 ( .A0(n1755), .A1(n1757), .B0(n1586), .Y(n1748) );
AOI21X1TS U1221 ( .A0(n1761), .A1(n1764), .B0(n1765), .Y(n1755) );
OAI21X1TS U1222 ( .A0(n1769), .A1(n1771), .B0(n1585), .Y(n1761) );
AOI21X1TS U1223 ( .A0(n1775), .A1(n1778), .B0(n1779), .Y(n1769) );
OAI21X1TS U1224 ( .A0(n1782), .A1(n1784), .B0(n1584), .Y(n1775) );
AOI21X1TS U1225 ( .A0(n1788), .A1(n1791), .B0(n1792), .Y(n1782) );
OAI21X1TS U1226 ( .A0(n1795), .A1(n1797), .B0(n1583), .Y(n1788) );
AOI21X1TS U1227 ( .A0(n1801), .A1(n1804), .B0(n1805), .Y(n1795) );
AOI21X1TS U1228 ( .A0(n1814), .A1(n1817), .B0(n1818), .Y(n1808) );
OAI21X1TS U1229 ( .A0(n1703), .A1(n1705), .B0(n1590), .Y(n1618) );
AOI21X1TS U1230 ( .A0(n1709), .A1(n1712), .B0(n1713), .Y(n1703) );
AOI21X1TS U1231 ( .A0(n1722), .A1(n1725), .B0(n1726), .Y(n1716) );
AOI21X1TS U1232 ( .A0(DMP_SFG[37]), .A1(DmP_mant_SFG_SWR[39]), .B0(n1698),
.Y(n1558) );
AOI21X1TS U1233 ( .A0(DMP_SFG[33]), .A1(DmP_mant_SFG_SWR[35]), .B0(n1717),
.Y(n1554) );
OAI21X2TS U1234 ( .A0(n2306), .A1(n2241), .B0(n1553), .Y(n1717) );
OAI21X1TS U1235 ( .A0(DmP_mant_SFG_SWR[34]), .A1(DMP_SFG[32]), .B0(n1724),
.Y(n1553) );
AOI21X1TS U1236 ( .A0(DMP_SFG[31]), .A1(DmP_mant_SFG_SWR[33]), .B0(n1730),
.Y(n1552) );
NOR2X1TS U1237 ( .A(n1638), .B(n1934), .Y(n1639) );
OAI21XLTS U1238 ( .A0(n1402), .A1(n1495), .B0(n1401), .Y(Data_array_SWR[50])
);
OAI21XLTS U1239 ( .A0(n1497), .A1(n2195), .B0(n1478), .Y(Data_array_SWR[11])
);
OAI21XLTS U1240 ( .A0(n2182), .A1(n1453), .B0(n1415), .Y(Data_array_SWR[51])
);
OAI21XLTS U1241 ( .A0(n1397), .A1(n1445), .B0(n1394), .Y(Data_array_SWR[49])
);
OAI21XLTS U1242 ( .A0(n1502), .A1(n2199), .B0(n1501), .Y(Data_array_SWR[10])
);
OAI21XLTS U1243 ( .A0(n1497), .A1(n2199), .B0(n1345), .Y(Data_array_SWR[12])
);
OAI21XLTS U1244 ( .A0(n2188), .A1(n1495), .B0(n1360), .Y(Data_array_SWR[28])
);
OAI21XLTS U1245 ( .A0(n1454), .A1(n2195), .B0(n1424), .Y(Data_array_SWR[31])
);
OAI21XLTS U1246 ( .A0(n1469), .A1(n1495), .B0(n1374), .Y(Data_array_SWR[20])
);
OAI21XLTS U1247 ( .A0(n1484), .A1(n2199), .B0(n1476), .Y(Data_array_SWR[5])
);
OAI21XLTS U1248 ( .A0(n1427), .A1(n1445), .B0(n1392), .Y(Data_array_SWR[38])
);
OAI21XLTS U1249 ( .A0(n1469), .A1(n2195), .B0(n1426), .Y(Data_array_SWR[19])
);
OAI21XLTS U1250 ( .A0(n1440), .A1(n2195), .B0(n1429), .Y(Data_array_SWR[35])
);
OAI21XLTS U1251 ( .A0(n1441), .A1(n1445), .B0(n1389), .Y(Data_array_SWR[37])
);
OAI21XLTS U1252 ( .A0(n1408), .A1(n1445), .B0(n1399), .Y(Data_array_SWR[46])
);
OAI21XLTS U1253 ( .A0(n1454), .A1(n1495), .B0(n1368), .Y(Data_array_SWR[32])
);
OAI21XLTS U1254 ( .A0(n1403), .A1(n2195), .B0(n1384), .Y(Data_array_SWR[47])
);
OAI21XLTS U1255 ( .A0(n2190), .A1(n1495), .B0(n1457), .Y(Data_array_SWR[29])
);
OAI21XLTS U1256 ( .A0(n1489), .A1(n2199), .B0(n1348), .Y(Data_array_SWR[4])
);
OAI21XLTS U1257 ( .A0(n1447), .A1(n1445), .B0(n1387), .Y(Data_array_SWR[41])
);
OAI21XLTS U1258 ( .A0(n1446), .A1(n1445), .B0(n1444), .Y(Data_array_SWR[34])
);
OAI21XLTS U1259 ( .A0(n1452), .A1(n1445), .B0(n1377), .Y(Data_array_SWR[40])
);
OAI21XLTS U1260 ( .A0(n1412), .A1(n1445), .B0(n1364), .Y(Data_array_SWR[44])
);
OAI21XLTS U1261 ( .A0(n1403), .A1(n1445), .B0(n1371), .Y(Data_array_SWR[48])
);
OAI21XLTS U1262 ( .A0(n1479), .A1(n2195), .B0(n1464), .Y(Data_array_SWR[7])
);
OAI21XLTS U1263 ( .A0(n1489), .A1(n2195), .B0(n1487), .Y(Data_array_SWR[3])
);
OAI21XLTS U1264 ( .A0(n1440), .A1(n1445), .B0(n1382), .Y(Data_array_SWR[36])
);
OAI21XLTS U1265 ( .A0(n1480), .A1(n2199), .B0(n1462), .Y(Data_array_SWR[9])
);
OAI21XLTS U1266 ( .A0(n1432), .A1(n1445), .B0(n1420), .Y(Data_array_SWR[33])
);
OAI21XLTS U1267 ( .A0(n1485), .A1(n2199), .B0(n1483), .Y(Data_array_SWR[6])
);
OAI21XLTS U1268 ( .A0(n1460), .A1(n2199), .B0(n1459), .Y(Data_array_SWR[2])
);
OAI21XLTS U1269 ( .A0(n2184), .A1(n1495), .B0(n1434), .Y(Data_array_SWR[30])
);
OAI21XLTS U1270 ( .A0(n1448), .A1(n1445), .B0(n1396), .Y(Data_array_SWR[42])
);
OAI21XLTS U1271 ( .A0(n1407), .A1(n1445), .B0(n1406), .Y(Data_array_SWR[45])
);
OAI21XLTS U1272 ( .A0(n1479), .A1(n2199), .B0(n1354), .Y(Data_array_SWR[8])
);
OAI21XLTS U1273 ( .A0(n1452), .A1(n2195), .B0(n1451), .Y(Data_array_SWR[39])
);
OAI21XLTS U1274 ( .A0(n1412), .A1(n2195), .B0(n1411), .Y(Data_array_SWR[43])
);
OAI21XLTS U1275 ( .A0(n1490), .A1(n2195), .B0(n1467), .Y(Data_array_SWR[15])
);
CLKINVX6TS U1276 ( .A(n1373), .Y(n835) );
OR3X1TS U1277 ( .A(n1110), .B(Raw_mant_NRM_SWR[3]), .C(Raw_mant_NRM_SWR[4]),
.Y(n1336) );
NAND2X1TS U1278 ( .A(n1312), .B(n1313), .Y(n1110) );
NAND3BX1TS U1279 ( .AN(Raw_mant_NRM_SWR[10]), .B(n2328), .C(n1308), .Y(n1320) );
NAND2X1TS U1280 ( .A(n1308), .B(Raw_mant_NRM_SWR[10]), .Y(n2214) );
NAND2X1TS U1281 ( .A(n963), .B(n2320), .Y(n976) );
NOR2BX2TS U1282 ( .AN(n950), .B(Raw_mant_NRM_SWR[16]), .Y(n963) );
NOR3X1TS U1283 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .C(
n1310), .Y(n950) );
NAND3BX1TS U1284 ( .AN(Raw_mant_NRM_SWR[19]), .B(n947), .C(n2312), .Y(n1310)
);
NAND2X1TS U1285 ( .A(Raw_mant_NRM_SWR[21]), .B(n971), .Y(n1321) );
NOR3X1TS U1286 ( .A(Raw_mant_NRM_SWR[23]), .B(n894), .C(n1112), .Y(n971) );
NAND2BX1TS U1287 ( .AN(Raw_mant_NRM_SWR[24]), .B(n941), .Y(n1112) );
NOR3BX1TS U1288 ( .AN(n2211), .B(Raw_mant_NRM_SWR[26]), .C(
Raw_mant_NRM_SWR[25]), .Y(n941) );
NOR2X1TS U1289 ( .A(Raw_mant_NRM_SWR[31]), .B(n969), .Y(n1324) );
NAND2X1TS U1290 ( .A(n1117), .B(n2289), .Y(n970) );
NOR2X1TS U1291 ( .A(Raw_mant_NRM_SWR[35]), .B(n1325), .Y(n1117) );
NAND2BX1TS U1292 ( .AN(Raw_mant_NRM_SWR[36]), .B(n943), .Y(n1325) );
NOR3X1TS U1293 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .C(
n1326), .Y(n943) );
NOR2X1TS U1294 ( .A(Raw_mant_NRM_SWR[41]), .B(n968), .Y(n936) );
NAND2X1TS U1295 ( .A(n1107), .B(n2285), .Y(n968) );
OAI21X1TS U1296 ( .A0(DmP_mant_SFG_SWR[6]), .A1(DMP_SFG[4]), .B0(n1906), .Y(
n1525) );
CLKINVX6TS U1297 ( .A(n1125), .Y(n1177) );
INVX2TS U1298 ( .A(n955), .Y(n935) );
BUFX6TS U1299 ( .A(OP_FLAG_SFG), .Y(n1768) );
AOI2BB1X2TS U1300 ( .A0N(n893), .A1N(DmP_mant_SFG_SWR[53]), .B0(n1572), .Y(
n1609) );
OAI21X1TS U1301 ( .A0(n1613), .A1(n1821), .B0(n1612), .Y(n1617) );
AOI2BB1X2TS U1302 ( .A0N(DMP_SFG[49]), .A1N(DmP_mant_SFG_SWR[51]), .B0(n1570), .Y(n1603) );
XOR2X1TS U1303 ( .A(n1637), .B(n1636), .Y(Raw_mant_SGF[49]) );
XOR2X1TS U1304 ( .A(n1650), .B(n1649), .Y(Raw_mant_SGF[47]) );
XOR2X1TS U1305 ( .A(n1663), .B(n1662), .Y(Raw_mant_SGF[45]) );
AOI21X2TS U1306 ( .A0(DMP_SFG[43]), .A1(DmP_mant_SFG_SWR[45]), .B0(n1659),
.Y(n1564) );
XOR2X1TS U1307 ( .A(n1676), .B(n1675), .Y(Raw_mant_SGF[43]) );
AOI21X2TS U1308 ( .A0(DMP_SFG[39]), .A1(DmP_mant_SFG_SWR[41]), .B0(n1685),
.Y(n1560) );
OAI21X2TS U1309 ( .A0(DmP_mant_SFG_SWR[40]), .A1(DMP_SFG[38]), .B0(n1692),
.Y(n1559) );
OAI21X2TS U1310 ( .A0(n2299), .A1(n2240), .B0(n1551), .Y(n1730) );
OAI21X1TS U1311 ( .A0(DmP_mant_SFG_SWR[32]), .A1(DMP_SFG[30]), .B0(n1737),
.Y(n1551) );
AOI21X1TS U1312 ( .A0(DMP_SFG[29]), .A1(DmP_mant_SFG_SWR[31]), .B0(n1743),
.Y(n1550) );
OAI21X2TS U1313 ( .A0(n2239), .A1(n2293), .B0(n1549), .Y(n1743) );
AOI2BB1X2TS U1314 ( .A0N(DMP_SFG[25]), .A1N(DmP_mant_SFG_SWR[27]), .B0(n1546), .Y(n1763) );
OAI21X1TS U1315 ( .A0(n2288), .A1(n2237), .B0(n1545), .Y(n1770) );
OAI21X1TS U1316 ( .A0(DmP_mant_SFG_SWR[26]), .A1(DMP_SFG[24]), .B0(n1777),
.Y(n1545) );
AOI2BB1X2TS U1317 ( .A0N(DMP_SFG[21]), .A1N(DmP_mant_SFG_SWR[23]), .B0(n1542), .Y(n1790) );
OAI21X1TS U1318 ( .A0(DmP_mant_SFG_SWR[22]), .A1(DMP_SFG[20]), .B0(n1803),
.Y(n1541) );
OAI21X1TS U1319 ( .A0(DmP_mant_SFG_SWR[20]), .A1(DMP_SFG[18]), .B0(n1816),
.Y(n1539) );
OAI32X1TS U1320 ( .A0(n939), .A1(n882), .A2(Raw_mant_NRM_SWR[7]), .B0(n2217),
.B1(n939), .Y(n940) );
AOI2BB1X2TS U1321 ( .A0N(DMP_SFG[15]), .A1N(DmP_mant_SFG_SWR[17]), .B0(n1536), .Y(n1830) );
INVX2TS U1322 ( .A(n976), .Y(n1118) );
OAI21X1TS U1323 ( .A0(n2282), .A1(n2232), .B0(n1535), .Y(n1836) );
OAI21X1TS U1324 ( .A0(DmP_mant_SFG_SWR[16]), .A1(DMP_SFG[14]), .B0(n1843),
.Y(n1535) );
AOI2BB1X2TS U1325 ( .A0N(DMP_SFG[11]), .A1N(DmP_mant_SFG_SWR[13]), .B0(n1532), .Y(n1856) );
NAND2XLTS U1326 ( .A(n1867), .B(n1919), .Y(n1868) );
OAI21X1TS U1327 ( .A0(DmP_mant_SFG_SWR[12]), .A1(DMP_SFG[10]), .B0(n1867),
.Y(n1531) );
NAND2XLTS U1328 ( .A(n1880), .B(n1922), .Y(n1881) );
OAI21X1TS U1329 ( .A0(DmP_mant_SFG_SWR[10]), .A1(DMP_SFG[8]), .B0(n1880),
.Y(n1529) );
BUFX4TS U1330 ( .A(n2162), .Y(n2175) );
NAND2XLTS U1331 ( .A(n1893), .B(n1934), .Y(n1894) );
AOI2BB1X2TS U1332 ( .A0N(DMP_SFG[5]), .A1N(DmP_mant_SFG_SWR[7]), .B0(n1526),
.Y(n1893) );
NAND2XLTS U1333 ( .A(n1906), .B(n1919), .Y(n1907) );
NAND2XLTS U1334 ( .A(n1920), .B(n1919), .Y(n1921) );
OR2X4TS U1335 ( .A(n1519), .B(n1102), .Y(n1303) );
BUFX6TS U1336 ( .A(n838), .Y(n2486) );
CLKBUFX2TS U1337 ( .A(n2384), .Y(n889) );
CLKBUFX2TS U1338 ( .A(n2374), .Y(n875) );
CLKBUFX2TS U1339 ( .A(n2258), .Y(n880) );
CLKBUFX2TS U1340 ( .A(n2382), .Y(n888) );
CLKBUFX2TS U1341 ( .A(n2389), .Y(n874) );
CLKBUFX2TS U1342 ( .A(n2376), .Y(n891) );
CLKBUFX2TS U1343 ( .A(n2260), .Y(n876) );
CLKBUFX2TS U1344 ( .A(n2385), .Y(n881) );
CLKBUFX2TS U1345 ( .A(n2386), .Y(n890) );
CLKBUFX2TS U1346 ( .A(n2261), .Y(n877) );
OR2X2TS U1347 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1021) );
BUFX6TS U1348 ( .A(n2532), .Y(n915) );
CLKBUFX2TS U1349 ( .A(Raw_mant_NRM_SWR[8]), .Y(n882) );
CLKBUFX2TS U1350 ( .A(Raw_mant_NRM_SWR[54]), .Y(n886) );
CLKINVX6TS U1351 ( .A(rst), .Y(n1123) );
XOR2X1TS U1352 ( .A(n1599), .B(n1598), .Y(Raw_mant_SGF[51]) );
OAI21X2TS U1353 ( .A0(DmP_mant_SFG_SWR[42]), .A1(DMP_SFG[40]), .B0(n1679),
.Y(n1561) );
OAI21X1TS U1354 ( .A0(DmP_mant_SFG_SWR[30]), .A1(DMP_SFG[28]), .B0(n1750),
.Y(n1549) );
OAI21X1TS U1355 ( .A0(n2290), .A1(n2238), .B0(n1547), .Y(n1756) );
NOR2X1TS U1356 ( .A(n1625), .B(n1934), .Y(n1626) );
OAI21X1TS U1357 ( .A0(DmP_mant_SFG_SWR[28]), .A1(DMP_SFG[26]), .B0(n1763),
.Y(n1547) );
AOI2BB1X2TS U1358 ( .A0N(DMP_SFG[23]), .A1N(DmP_mant_SFG_SWR[25]), .B0(n1544), .Y(n1777) );
OAI211X1TS U1359 ( .A0(n1460), .A1(n2189), .B0(n1418), .C0(n1341), .Y(
Data_array_SWR[0]) );
OAI222X1TS U1360 ( .A0(n2199), .A1(n2194), .B0(n2193), .B1(n2196), .C0(n2195), .C1(n2192), .Y(Data_array_SWR[25]) );
OAI21X1TS U1361 ( .A0(n2236), .A1(n2287), .B0(n1543), .Y(n1783) );
INVX3TS U1362 ( .A(n1466), .Y(n2199) );
OAI21X1TS U1363 ( .A0(DmP_mant_SFG_SWR[24]), .A1(DMP_SFG[22]), .B0(n1790),
.Y(n1543) );
INVX3TS U1364 ( .A(n1466), .Y(n1495) );
AND2X4TS U1365 ( .A(n2187), .B(n2191), .Y(n1373) );
AND2X4TS U1366 ( .A(n2191), .B(n2185), .Y(n1385) );
INVX3TS U1367 ( .A(n1466), .Y(n1445) );
AND2X4TS U1368 ( .A(n2196), .B(n2187), .Y(n1390) );
AND2X4TS U1369 ( .A(n2196), .B(n2185), .Y(n1466) );
AOI2BB1X2TS U1370 ( .A0N(DMP_SFG[19]), .A1N(DmP_mant_SFG_SWR[21]), .B0(n1540), .Y(n1803) );
AOI2BB1X2TS U1371 ( .A0N(DMP_SFG[17]), .A1N(DmP_mant_SFG_SWR[19]), .B0(n1538), .Y(n1816) );
OAI21X1TS U1372 ( .A0(n2233), .A1(n2283), .B0(n1537), .Y(n1823) );
OAI21X1TS U1373 ( .A0(DmP_mant_SFG_SWR[18]), .A1(DMP_SFG[16]), .B0(n1830),
.Y(n1537) );
NAND3BX1TS U1374 ( .AN(Raw_mant_NRM_SWR[14]), .B(n1118), .C(
Raw_mant_NRM_SWR[13]), .Y(n1309) );
AOI21X1TS U1375 ( .A0(DMP_SFG[15]), .A1(DmP_mant_SFG_SWR[17]), .B0(n1836),
.Y(n1536) );
AOI2BB1X2TS U1376 ( .A0N(DMP_SFG[13]), .A1N(DmP_mant_SFG_SWR[15]), .B0(n1534), .Y(n1843) );
AOI21X1TS U1377 ( .A0(DMP_SFG[13]), .A1(DmP_mant_SFG_SWR[15]), .B0(n1849),
.Y(n1534) );
OAI21X1TS U1378 ( .A0(n2281), .A1(n2231), .B0(n1533), .Y(n1849) );
OAI21X1TS U1379 ( .A0(DmP_mant_SFG_SWR[14]), .A1(DMP_SFG[12]), .B0(n1856),
.Y(n1533) );
OAI211X1TS U1380 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n975), .B0(n945), .C0(n944), .Y(n946) );
AOI21X1TS U1381 ( .A0(DMP_SFG[11]), .A1(DmP_mant_SFG_SWR[13]), .B0(n1862),
.Y(n1532) );
AOI2BB1X2TS U1382 ( .A0N(DMP_SFG[9]), .A1N(DmP_mant_SFG_SWR[11]), .B0(n1530),
.Y(n1867) );
NOR2X2TS U1383 ( .A(array_comparators_GTComparator_N0), .B(n2484), .Y(n2200)
);
NAND2BX1TS U1384 ( .AN(Raw_mant_NRM_SWR[32]), .B(n1113), .Y(n969) );
AOI2BB1X2TS U1385 ( .A0N(DMP_SFG[7]), .A1N(DmP_mant_SFG_SWR[9]), .B0(n1528),
.Y(n1880) );
AOI21X1TS U1386 ( .A0(DMP_SFG[7]), .A1(DmP_mant_SFG_SWR[9]), .B0(n1887), .Y(
n1528) );
INVX6TS U1387 ( .A(n2157), .Y(n2162) );
OAI21X1TS U1388 ( .A0(n2278), .A1(n2228), .B0(n1527), .Y(n1887) );
OAI21X1TS U1389 ( .A0(DmP_mant_SFG_SWR[8]), .A1(DMP_SFG[6]), .B0(n1893), .Y(
n1527) );
OAI32X4TS U1390 ( .A0(n968), .A1(Raw_mant_NRM_SWR[40]), .A2(n2247), .B0(
n2344), .B1(n968), .Y(n2205) );
OAI21X2TS U1391 ( .A0(n2249), .A1(n1366), .B0(n1340), .Y(n860) );
AOI2BB1X2TS U1392 ( .A0N(DMP_SFG[3]), .A1N(DmP_mant_SFG_SWR[5]), .B0(n1524),
.Y(n1906) );
OAI21X1TS U1393 ( .A0(n1179), .A1(n2418), .B0(n1178), .Y(n857) );
AO21XLTS U1394 ( .A0(n1928), .A1(n1930), .B0(n1929), .Y(n1923) );
OR2X4TS U1395 ( .A(n1508), .B(n1217), .Y(n1510) );
INVX4TS U1396 ( .A(n2534), .Y(n836) );
NOR2X6TS U1397 ( .A(n1217), .B(n1125), .Y(n983) );
NOR2X6TS U1398 ( .A(n1217), .B(n1021), .Y(n982) );
OAI21X1TS U1399 ( .A0(DmP_mant_SFG_SWR[4]), .A1(DMP_SFG[2]), .B0(n1920), .Y(
n1523) );
NAND2X2TS U1400 ( .A(shift_value_SHT2_EWR[4]), .B(n1257), .Y(n992) );
BUFX4TS U1401 ( .A(n1008), .Y(n837) );
INVX2TS U1402 ( .A(n1772), .Y(n1585) );
INVX2TS U1403 ( .A(n1758), .Y(n1586) );
INVX2TS U1404 ( .A(n1745), .Y(n1587) );
INVX2TS U1405 ( .A(n1661), .Y(n1594) );
INVX2TS U1406 ( .A(n1648), .Y(n1595) );
INVX2TS U1407 ( .A(n1635), .Y(n1596) );
CLKINVX3TS U1408 ( .A(n1194), .Y(n986) );
INVX2TS U1409 ( .A(n1700), .Y(n1591) );
INVX2TS U1410 ( .A(n1706), .Y(n1590) );
INVX6TS U1411 ( .A(n1366), .Y(n1342) );
INVX2TS U1412 ( .A(n1719), .Y(n1589) );
INVX2TS U1413 ( .A(n1687), .Y(n1592) );
INVX2TS U1414 ( .A(n1674), .Y(n1593) );
INVX2TS U1415 ( .A(n1732), .Y(n1588) );
INVX2TS U1416 ( .A(n1785), .Y(n1584) );
NAND2X1TS U1417 ( .A(DmP_mant_SFG_SWR[26]), .B(n2288), .Y(n1778) );
XOR2XLTS U1418 ( .A(DmP_mant_SFG_SWR[52]), .B(DMP_SFG[50]), .Y(n1604) );
NOR2X6TS U1419 ( .A(shift_value_SHT2_EWR[4]), .B(n2353), .Y(n989) );
NOR2X1TS U1420 ( .A(Raw_mant_NRM_SWR[51]), .B(Raw_mant_NRM_SWR[52]), .Y(n932) );
NAND2X1TS U1421 ( .A(DmP_mant_SFG_SWR[30]), .B(n2239), .Y(n1751) );
INVX1TS U1422 ( .A(n851), .Y(n894) );
NAND2X1TS U1423 ( .A(DmP_mant_SFG_SWR[32]), .B(n2299), .Y(n1738) );
NAND2X1TS U1424 ( .A(DmP_mant_SFG_SWR[44]), .B(n2343), .Y(n1667) );
NAND2X1TS U1425 ( .A(DmP_mant_SFG_SWR[42]), .B(n2248), .Y(n1680) );
NAND2X1TS U1426 ( .A(DmP_mant_SFG_SWR[34]), .B(n2306), .Y(n1725) );
NAND2X1TS U1427 ( .A(DmP_mant_SFG_SWR[40]), .B(n2323), .Y(n1693) );
NAND2X1TS U1428 ( .A(DmP_mant_SFG_SWR[38]), .B(n2317), .Y(n1621) );
NAND2X1TS U1429 ( .A(DmP_mant_SFG_SWR[36]), .B(n2242), .Y(n1712) );
NOR3X1TS U1430 ( .A(Raw_mant_NRM_SWR[48]), .B(Raw_mant_NRM_SWR[49]), .C(
Raw_mant_NRM_SWR[50]), .Y(n1114) );
NAND2X1TS U1431 ( .A(DmP_mant_SFG_SWR[46]), .B(n2355), .Y(n1654) );
NAND2X1TS U1432 ( .A(DmP_mant_SFG_SWR[48]), .B(n2253), .Y(n1641) );
NAND2X1TS U1433 ( .A(DmP_mant_SFG_SWR[28]), .B(n2290), .Y(n1764) );
NAND2X1TS U1434 ( .A(DmP_mant_SFG_SWR[50]), .B(n2415), .Y(n1628) );
NAND2X1TS U1435 ( .A(n2419), .B(DMP_SFG[50]), .Y(n1606) );
BUFX6TS U1436 ( .A(n2518), .Y(n838) );
BUFX6TS U1437 ( .A(n2530), .Y(n2522) );
BUFX6TS U1438 ( .A(n2512), .Y(n839) );
BUFX6TS U1439 ( .A(n2498), .Y(n2492) );
BUFX6TS U1440 ( .A(n1123), .Y(n2493) );
BUFX6TS U1441 ( .A(n1123), .Y(n2530) );
BUFX6TS U1442 ( .A(n2498), .Y(n840) );
AOI2BB1X4TS U1443 ( .A0N(DMP_SFG[43]), .A1N(DmP_mant_SFG_SWR[45]), .B0(n1564), .Y(n1653) );
OAI21X4TS U1444 ( .A0(n2323), .A1(n2245), .B0(n1559), .Y(n1685) );
OAI21X4TS U1445 ( .A0(n2317), .A1(n2243), .B0(n1557), .Y(n1698) );
OAI21X4TS U1446 ( .A0(n2415), .A1(n2254), .B0(n1569), .Y(n1597) );
OAI21X4TS U1447 ( .A0(n2355), .A1(n2251), .B0(n1565), .Y(n1646) );
OAI21X4TS U1448 ( .A0(n2248), .A1(n2330), .B0(n1561), .Y(n1672) );
AOI2BB1X4TS U1449 ( .A0N(DMP_SFG[47]), .A1N(DmP_mant_SFG_SWR[49]), .B0(n1568), .Y(n1627) );
AOI2BB1X4TS U1450 ( .A0N(DMP_SFG[37]), .A1N(DmP_mant_SFG_SWR[39]), .B0(n1558), .Y(n1692) );
OAI21X4TS U1451 ( .A0(n2253), .A1(n2359), .B0(n1567), .Y(n1633) );
OAI21X4TS U1452 ( .A0(n2343), .A1(n2250), .B0(n1563), .Y(n1659) );
XOR2X1TS U1453 ( .A(n1610), .B(DmP_mant_SFG_SWR[54]), .Y(Raw_mant_SGF[54])
);
OAI2BB2XLTS U1454 ( .B0(intDX_EWSW[12]), .B1(n2042), .A0N(intDY_EWSW[13]),
.A1N(n888), .Y(n2054) );
NAND2BXLTS U1455 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2029) );
NAND2BXLTS U1456 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2028) );
OAI2BB2XLTS U1457 ( .B0(intDX_EWSW[40]), .B1(n2100), .A0N(intDY_EWSW[41]),
.A1N(n891), .Y(n2105) );
AOI221X1TS U1458 ( .A0(n888), .A1(intDY_EWSW[13]), .B0(intDY_EWSW[2]), .B1(
n2257), .C0(n1995), .Y(n2000) );
AOI221X1TS U1459 ( .A0(n2264), .A1(intDY_EWSW[43]), .B0(n872), .B1(n2255),
.C0(n1989), .Y(n1991) );
AOI221X1TS U1460 ( .A0(n2380), .A1(intDY_EWSW[31]), .B0(intDY_EWSW[30]),
.B1(n876), .C0(n1988), .Y(n1992) );
NAND2BXLTS U1461 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2086) );
OAI32X1TS U1462 ( .A0(n2069), .A1(n2068), .A2(n2067), .B0(n2066), .B1(n2068),
.Y(n2073) );
OAI2BB2XLTS U1463 ( .B0(intDX_EWSW[20]), .B1(n2062), .A0N(intDY_EWSW[21]),
.A1N(n889), .Y(n2074) );
OAI2BB2XLTS U1464 ( .B0(intDX_EWSW[28]), .B1(n2017), .A0N(intDY_EWSW[29]),
.A1N(n890), .Y(n2026) );
NAND2BXLTS U1465 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2018) );
CLKAND2X2TS U1466 ( .A(bit_shift_SHT2), .B(n1021), .Y(n1199) );
NAND2X1TS U1467 ( .A(n934), .B(n1362), .Y(n951) );
CLKAND2X2TS U1468 ( .A(n933), .B(n932), .Y(n1115) );
AOI221X1TS U1469 ( .A0(n2381), .A1(intDY_EWSW[35]), .B0(intDY_EWSW[34]),
.B1(n877), .C0(n1945), .Y(n1948) );
AOI221X1TS U1470 ( .A0(n874), .A1(intDY_EWSW[42]), .B0(intDY_EWSW[41]), .B1(
n891), .C0(n1946), .Y(n1947) );
AOI221X1TS U1471 ( .A0(n2388), .A1(intDY_EWSW[38]), .B0(intDY_EWSW[22]),
.B1(n875), .C0(n1940), .Y(n1941) );
NAND2BXLTS U1472 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2014) );
NAND2BXLTS U1473 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2094) );
AO22XLTS U1474 ( .A0(n2187), .A1(n2188), .B0(n2185), .B1(n2186), .Y(n2193)
);
OAI21X1TS U1475 ( .A0(n2230), .A1(n2280), .B0(n1531), .Y(n1862) );
OAI21X1TS U1476 ( .A0(n2276), .A1(n2226), .B0(n1523), .Y(n1913) );
OAI21X1TS U1477 ( .A0(n2284), .A1(n2234), .B0(n1539), .Y(n1809) );
OAI21X1TS U1478 ( .A0(n2227), .A1(n2277), .B0(n1525), .Y(n1900) );
NAND2BXLTS U1479 ( .AN(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n1930) );
OAI21X1TS U1480 ( .A0(n2279), .A1(n2229), .B0(n1529), .Y(n1874) );
AOI21X1TS U1481 ( .A0(DMP_SFG[3]), .A1(DmP_mant_SFG_SWR[5]), .B0(n1913), .Y(
n1524) );
OAI21X1TS U1482 ( .A0(n2286), .A1(n2235), .B0(n1541), .Y(n1796) );
AO22XLTS U1483 ( .A0(n2187), .A1(n2186), .B0(n2185), .B1(n2192), .Y(n2197)
);
INVX6TS U1484 ( .A(n836), .Y(n1379) );
NAND2X1TS U1485 ( .A(n955), .B(n936), .Y(n1326) );
NAND2BXLTS U1486 ( .AN(n951), .B(Raw_mant_NRM_SWR[43]), .Y(n965) );
OAI211XLTS U1487 ( .A0(n2354), .A1(n1110), .B0(n1109), .C0(n1108), .Y(n1111)
);
NAND2BXLTS U1488 ( .AN(n893), .B(DmP_mant_SFG_SWR[53]), .Y(n1614) );
NAND2BXLTS U1489 ( .AN(n1779), .B(n1778), .Y(n1780) );
NOR2XLTS U1490 ( .A(n1648), .B(n1647), .Y(n1649) );
NAND2BXLTS U1491 ( .AN(n1792), .B(n1791), .Y(n1793) );
OAI222X1TS U1492 ( .A0(n2193), .A1(n2191), .B0(n835), .B1(n2184), .C0(n2183),
.C1(n2190), .Y(Data_array_SWR[27]) );
NAND2BXLTS U1493 ( .AN(n1655), .B(n1654), .Y(n1656) );
NOR2XLTS U1494 ( .A(n1651), .B(n1919), .Y(n1652) );
XOR2XLTS U1495 ( .A(n1708), .B(n1707), .Y(Raw_mant_SGF[37]) );
NOR2XLTS U1496 ( .A(n1635), .B(n1634), .Y(n1636) );
NAND2BXLTS U1497 ( .AN(n1694), .B(n1693), .Y(n1695) );
NOR2XLTS U1498 ( .A(n1690), .B(n1919), .Y(n1691) );
NAND2BXLTS U1499 ( .AN(n1832), .B(n1831), .Y(n1833) );
NAND2BXLTS U1500 ( .AN(n1845), .B(n1844), .Y(n1846) );
NAND2BXLTS U1501 ( .AN(n1713), .B(n1712), .Y(n1714) );
NOR2XLTS U1502 ( .A(n1709), .B(n1919), .Y(n1710) );
NAND2BXLTS U1503 ( .AN(n1629), .B(n1628), .Y(n1630) );
NAND2BXLTS U1504 ( .AN(n1752), .B(n1751), .Y(n1753) );
NAND2BXLTS U1505 ( .AN(n1642), .B(n1641), .Y(n1643) );
OAI21XLTS U1506 ( .A0(n1490), .A1(n1495), .B0(n1351), .Y(Data_array_SWR[16])
);
NAND2BXLTS U1507 ( .AN(n1739), .B(n1738), .Y(n1740) );
NAND2BXLTS U1508 ( .AN(n1622), .B(n1621), .Y(n1623) );
NOR2XLTS U1509 ( .A(n1618), .B(n1919), .Y(n1619) );
NOR2XLTS U1510 ( .A(n1600), .B(n1601), .Y(n1598) );
NAND2BXLTS U1511 ( .AN(n1765), .B(n1764), .Y(n1766) );
NAND2BXLTS U1512 ( .AN(n1858), .B(n1857), .Y(n1859) );
XOR2XLTS U1513 ( .A(n1702), .B(n1701), .Y(Raw_mant_SGF[39]) );
NAND2BXLTS U1514 ( .AN(n1681), .B(n1680), .Y(n1682) );
NOR2XLTS U1515 ( .A(n1677), .B(n1919), .Y(n1678) );
NAND2BXLTS U1516 ( .AN(n1726), .B(n1725), .Y(n1727) );
NOR2XLTS U1517 ( .A(n1722), .B(n1919), .Y(n1723) );
NAND2BXLTS U1518 ( .AN(n1818), .B(n1817), .Y(n1819) );
XOR2XLTS U1519 ( .A(n1734), .B(n1733), .Y(Raw_mant_SGF[33]) );
XOR2XLTS U1520 ( .A(n1689), .B(n1688), .Y(Raw_mant_SGF[41]) );
XOR2XLTS U1521 ( .A(n1721), .B(n1720), .Y(Raw_mant_SGF[35]) );
OAI21XLTS U1522 ( .A0(n2182), .A1(n2199), .B0(n1366), .Y(Data_array_SWR[54])
);
OAI21XLTS U1523 ( .A0(n1418), .A1(n1495), .B0(n1417), .Y(Data_array_SWR[1])
);
OAI21XLTS U1524 ( .A0(n1468), .A1(n1495), .B0(n1431), .Y(Data_array_SWR[18])
);
OAI21XLTS U1525 ( .A0(n1439), .A1(n1495), .B0(n1438), .Y(Data_array_SWR[21])
);
OAI21XLTS U1526 ( .A0(n2192), .A1(n835), .B0(n1357), .Y(Data_array_SWR[23])
);
NAND3XLTS U1527 ( .A(n2220), .B(n2219), .C(n2218), .Y(LZD_raw_out_EWR[3]) );
NAND2BXLTS U1528 ( .AN(n1615), .B(n1614), .Y(n1616) );
NAND2BXLTS U1529 ( .AN(n1668), .B(n1667), .Y(n1669) );
NOR2XLTS U1530 ( .A(n1664), .B(n1919), .Y(n1665) );
NAND2BXLTS U1531 ( .AN(n1805), .B(n1804), .Y(n1806) );
AO22XLTS U1532 ( .A0(n2178), .A1(intDX_EWSW[60]), .B0(n2177), .B1(
intDY_EWSW[60]), .Y(DMP_INIT_EWSW[60]) );
AO22XLTS U1533 ( .A0(n2178), .A1(intDX_EWSW[59]), .B0(n2167), .B1(
intDY_EWSW[59]), .Y(DMP_INIT_EWSW[59]) );
AO22XLTS U1534 ( .A0(n2178), .A1(intDX_EWSW[58]), .B0(n2162), .B1(
intDY_EWSW[58]), .Y(DMP_INIT_EWSW[58]) );
OR2X1TS U1535 ( .A(n916), .B(n917), .Y(n853) );
OR2X1TS U1536 ( .A(n918), .B(n919), .Y(n855) );
OAI21X1TS U1537 ( .A0(n1125), .A1(n2411), .B0(n1124), .Y(n998) );
OAI21X1TS U1538 ( .A0(n1125), .A1(n2407), .B0(n1085), .Y(n1086) );
OAI21X1TS U1539 ( .A0(n1125), .A1(n2408), .B0(n1124), .Y(n1126) );
NAND2X2TS U1540 ( .A(bit_shift_SHT2), .B(shift_value_SHT2_EWR[3]), .Y(n1124)
);
INVX1TS U1541 ( .A(n1154), .Y(n1145) );
INVX1TS U1542 ( .A(n1235), .Y(n1265) );
INVX1TS U1543 ( .A(n1241), .Y(n1250) );
INVX1TS U1544 ( .A(n1238), .Y(n1256) );
NOR4X2TS U1545 ( .A(n2011), .B(n2084), .C(n2096), .D(n2088), .Y(n2144) );
BUFX4TS U1546 ( .A(n2500), .Y(n2501) );
BUFX4TS U1547 ( .A(n1123), .Y(n2531) );
BUFX4TS U1548 ( .A(n1123), .Y(n2516) );
BUFX4TS U1549 ( .A(n1123), .Y(n2500) );
BUFX4TS U1550 ( .A(n838), .Y(n2521) );
BUFX4TS U1551 ( .A(n2522), .Y(n2509) );
BUFX4TS U1552 ( .A(n2516), .Y(n2511) );
BUFX4TS U1553 ( .A(n2531), .Y(n2507) );
BUFX4TS U1554 ( .A(n2530), .Y(n2524) );
BUFX4TS U1555 ( .A(n2531), .Y(n2515) );
OAI32X1TS U1556 ( .A0(n1317), .A1(Raw_mant_NRM_SWR[0]), .A2(
Raw_mant_NRM_SWR[1]), .B0(n1316), .B1(n1317), .Y(n1318) );
AOI211X1TS U1557 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n950), .B0(n1317), .C0(
n1333), .Y(n952) );
AOI32X4TS U1558 ( .A0(n2249), .A1(n940), .A2(n2354), .B0(n1110), .B1(n940),
.Y(n1317) );
BUFX4TS U1559 ( .A(n2500), .Y(n2499) );
BUFX4TS U1560 ( .A(n838), .Y(n2490) );
BUFX4TS U1561 ( .A(n2500), .Y(n2496) );
BUFX4TS U1562 ( .A(n839), .Y(n2489) );
BUFX4TS U1563 ( .A(n840), .Y(n2505) );
BUFX4TS U1564 ( .A(n2498), .Y(n2504) );
BUFX4TS U1565 ( .A(n838), .Y(n2503) );
BUFX4TS U1566 ( .A(n2516), .Y(n2519) );
BUFX4TS U1567 ( .A(n2530), .Y(n2520) );
BUFX4TS U1568 ( .A(n2516), .Y(n2528) );
BUFX4TS U1569 ( .A(n2531), .Y(n2506) );
BUFX4TS U1570 ( .A(n1123), .Y(n2491) );
BUFX4TS U1571 ( .A(n838), .Y(n2485) );
BUFX4TS U1572 ( .A(n2500), .Y(n2494) );
BUFX4TS U1573 ( .A(n2486), .Y(n2488) );
BUFX4TS U1574 ( .A(n2492), .Y(n2508) );
BUFX4TS U1575 ( .A(n838), .Y(n2525) );
BUFX4TS U1576 ( .A(n2522), .Y(n2514) );
BUFX6TS U1577 ( .A(n2492), .Y(n2529) );
BUFX4TS U1578 ( .A(n2492), .Y(n2517) );
AOI21X2TS U1579 ( .A0(n1206), .A1(Data_array_SWR[87]), .B0(n1199), .Y(n1511)
);
INVX4TS U1580 ( .A(n1021), .Y(n1206) );
INVX2TS U1581 ( .A(n2433), .Y(n872) );
NOR2X4TS U1582 ( .A(n1508), .B(n1216), .Y(n1231) );
INVX2TS U1583 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n873) );
AOI222X4TS U1584 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[26]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[26]), .C0(Raw_mant_NRM_SWR[28]), .C1(n2533), .Y(n2188) );
AOI222X4TS U1585 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[24]), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2533), .C0(Raw_mant_NRM_SWR[28]), .C1(
n2221), .Y(n2192) );
AOI211XLTS U1586 ( .A0(Raw_mant_NRM_SWR[26]), .A1(n2211), .B0(n2210), .C0(
n2209), .Y(n2212) );
INVX2TS U1587 ( .A(intDY_EWSW[7]), .Y(n878) );
INVX2TS U1588 ( .A(intDY_EWSW[5]), .Y(n879) );
OAI221X1TS U1589 ( .A0(n2391), .A1(intDY_EWSW[49]), .B0(n2402), .B1(
intDY_EWSW[54]), .C0(n1966), .Y(n1967) );
OAI211X2TS U1590 ( .A0(intDY_EWSW[12]), .A1(n2372), .B0(n2055), .C0(n2029),
.Y(n2059) );
AOI221X1TS U1591 ( .A0(n2378), .A1(intDY_EWSW[15]), .B0(intDY_EWSW[12]),
.B1(n2372), .C0(n1971), .Y(n1978) );
OAI211X2TS U1592 ( .A0(intDY_EWSW[20]), .A1(n2373), .B0(n2075), .C0(n2028),
.Y(n2068) );
AOI221X1TS U1593 ( .A0(n889), .A1(intDY_EWSW[21]), .B0(intDY_EWSW[20]), .B1(
n2373), .C0(n1997), .Y(n1998) );
OAI211X2TS U1594 ( .A0(intDY_EWSW[28]), .A1(n2375), .B0(n2027), .C0(n2018),
.Y(n2078) );
AOI221X1TS U1595 ( .A0(n890), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[28]), .B1(
n2375), .C0(n1996), .Y(n1999) );
CLKINVX6TS U1596 ( .A(n1768), .Y(n1919) );
INVX2TS U1597 ( .A(n868), .Y(n883) );
INVX2TS U1598 ( .A(n869), .Y(n884) );
INVX2TS U1599 ( .A(n871), .Y(n885) );
AOI211XLTS U1600 ( .A0(n929), .A1(n913), .B0(Raw_mant_NRM_SWR[48]), .C0(
Raw_mant_NRM_SWR[47]), .Y(n930) );
OAI21X2TS U1601 ( .A0(n2356), .A1(n1366), .B0(n1365), .Y(n1443) );
OAI21X2TS U1602 ( .A0(n2328), .A1(n1366), .B0(n1352), .Y(n1500) );
OAI21X2TS U1603 ( .A0(n1362), .A1(n1366), .B0(n1361), .Y(n1405) );
INVX2TS U1604 ( .A(n850), .Y(n887) );
OAI21X2TS U1605 ( .A0(n1305), .A1(shift_value_SHT2_EWR[4]), .B0(n1257), .Y(
n1292) );
CLKINVX3TS U1606 ( .A(n1521), .Y(n1257) );
CLKINVX6TS U1607 ( .A(n1385), .Y(n2183) );
OAI211X2TS U1608 ( .A0(n2414), .A1(n1021), .B0(n1020), .C0(n1033), .Y(n1517)
);
INVX6TS U1609 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1380) );
BUFX4TS U1610 ( .A(n2162), .Y(n2166) );
BUFX6TS U1611 ( .A(n2162), .Y(n2173) );
CLKINVX6TS U1612 ( .A(n1390), .Y(n1488) );
CLKINVX6TS U1613 ( .A(n1390), .Y(n2195) );
OAI21X2TS U1614 ( .A0(n836), .A1(n2249), .B0(n1369), .Y(n1414) );
OAI21X2TS U1615 ( .A0(n836), .A1(n2342), .B0(n1355), .Y(n1437) );
OAI21X2TS U1616 ( .A0(n836), .A1(n2328), .B0(n1375), .Y(n1410) );
OAI21X2TS U1617 ( .A0(n836), .A1(n2341), .B0(n1358), .Y(n1456) );
OAI21X2TS U1618 ( .A0(n836), .A1(n2356), .B0(n1349), .Y(n1471) );
OAI21X2TS U1619 ( .A0(n836), .A1(n1362), .B0(n1346), .Y(n1482) );
OAI21X2TS U1620 ( .A0(n836), .A1(n2320), .B0(n1378), .Y(n1450) );
INVX6TS U1621 ( .A(n836), .Y(n2221) );
NOR2X2TS U1622 ( .A(ADD_OVRFLW_NRM), .B(n915), .Y(n2534) );
BUFX4TS U1623 ( .A(n985), .Y(n1200) );
CLKINVX6TS U1624 ( .A(n2162), .Y(n2170) );
CLKINVX6TS U1625 ( .A(n2162), .Y(n2169) );
BUFX6TS U1626 ( .A(n1342), .Y(n2533) );
INVX3TS U1627 ( .A(n1098), .Y(n1260) );
CLKINVX6TS U1628 ( .A(n1510), .Y(n1262) );
INVX3TS U1629 ( .A(n1169), .Y(n1129) );
INVX4TS U1630 ( .A(n2176), .Y(n2161) );
BUFX3TS U1631 ( .A(n2162), .Y(n2176) );
CLKINVX6TS U1632 ( .A(n2162), .Y(n2174) );
CLKINVX3TS U1633 ( .A(n2162), .Y(n2171) );
INVX6TS U1634 ( .A(n1305), .Y(n1508) );
BUFX6TS U1635 ( .A(left_right_SHT2), .Y(n1305) );
NAND2X2TS U1636 ( .A(bit_shift_SHT2), .B(n1208), .Y(n1033) );
BUFX6TS U1637 ( .A(n1073), .Y(n1208) );
INVX2TS U1638 ( .A(n852), .Y(busy) );
INVX2TS U1639 ( .A(n870), .Y(n893) );
INVX2TS U1640 ( .A(n842), .Y(n895) );
AOI222X4TS U1641 ( .A0(n1208), .A1(n896), .B0(n1206), .B1(Data_array_SWR[67]), .C0(n1177), .C1(Data_array_SWR[70]), .Y(n1218) );
INVX2TS U1642 ( .A(n866), .Y(n896) );
AOI21X2TS U1643 ( .A0(n1208), .A1(Data_array_SWR[78]), .B0(n1086), .Y(n1195)
);
AOI21X2TS U1644 ( .A0(n1206), .A1(Data_array_SWR[86]), .B0(n998), .Y(n1506)
);
INVX2TS U1645 ( .A(n867), .Y(n897) );
AOI21X2TS U1646 ( .A0(n1206), .A1(Data_array_SWR[88]), .B0(n1199), .Y(n1214)
);
INVX2TS U1647 ( .A(n856), .Y(n898) );
INVX2TS U1648 ( .A(n859), .Y(n899) );
INVX2TS U1649 ( .A(n843), .Y(n900) );
INVX2TS U1650 ( .A(n848), .Y(n901) );
INVX2TS U1651 ( .A(n846), .Y(n902) );
INVX2TS U1652 ( .A(n847), .Y(n903) );
INVX2TS U1653 ( .A(n858), .Y(n904) );
INVX2TS U1654 ( .A(n865), .Y(n905) );
INVX2TS U1655 ( .A(n863), .Y(n906) );
INVX2TS U1656 ( .A(n864), .Y(n907) );
INVX2TS U1657 ( .A(n862), .Y(n908) );
INVX2TS U1658 ( .A(n845), .Y(n909) );
INVX2TS U1659 ( .A(n861), .Y(n910) );
INVX2TS U1660 ( .A(n844), .Y(n911) );
INVX2TS U1661 ( .A(n841), .Y(n912) );
AOI32X1TS U1662 ( .A0(n2412), .A1(n2086), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n2273), .Y(n2087) );
OAI221XLTS U1663 ( .A0(n2412), .A1(intDY_EWSW[58]), .B0(n2273), .B1(
intDY_EWSW[59]), .C0(n1942), .Y(n1953) );
NOR4X1TS U1664 ( .A(n913), .B(Raw_mant_NRM_SWR[45]), .C(Raw_mant_NRM_SWR[46]), .D(n2207), .Y(n934) );
NOR3X1TS U1665 ( .A(n913), .B(Raw_mant_NRM_SWR[45]), .C(Raw_mant_NRM_SWR[46]), .Y(n2208) );
OAI221X1TS U1666 ( .A0(n2410), .A1(intDY_EWSW[62]), .B0(n2413), .B1(
intDY_EWSW[60]), .C0(n1955), .Y(n1962) );
NOR4X2TS U1667 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[12]), .C(
Raw_mant_NRM_SWR[13]), .D(n976), .Y(n1308) );
INVX2TS U1668 ( .A(n849), .Y(n913) );
NOR2X2TS U1669 ( .A(Raw_mant_NRM_SWR[39]), .B(Raw_mant_NRM_SWR[40]), .Y(n955) );
NOR4X1TS U1670 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[18]), .C(
Raw_mant_NRM_SWR[17]), .D(Raw_mant_NRM_SWR[14]), .Y(n1311) );
INVX2TS U1671 ( .A(n854), .Y(n914) );
OAI221X1TS U1672 ( .A0(n2394), .A1(intDY_EWSW[51]), .B0(n2400), .B1(
intDY_EWSW[48]), .C0(n1957), .Y(n1960) );
AOI211X1TS U1673 ( .A0(n1117), .A1(Raw_mant_NRM_SWR[34]), .B0(n1334), .C0(
n1116), .Y(n1121) );
OAI221X1TS U1674 ( .A0(intDX_EWSW[39]), .A1(n2405), .B0(n2272), .B1(
intDY_EWSW[39]), .C0(n1941), .Y(n1954) );
INVX1TS U1675 ( .A(n1307), .Y(enable_Pipeline_input) );
NOR2XLTS U1676 ( .A(Data_array_SWR[76]), .B(n1002), .Y(n916) );
NOR2XLTS U1677 ( .A(n1208), .B(n1002), .Y(n917) );
AOI21X2TS U1678 ( .A0(n1207), .A1(Data_array_SWR[72]), .B0(n857), .Y(n1288)
);
AOI211XLTS U1679 ( .A0(intDX_EWSW[16]), .A1(n2445), .B0(n2063), .C0(n2069),
.Y(n2060) );
OAI21X2TS U1680 ( .A0(intDY_EWSW[18]), .A1(n2172), .B0(n2065), .Y(n2069) );
NOR2XLTS U1681 ( .A(Data_array_SWR[79]), .B(n1037), .Y(n918) );
NOR2XLTS U1682 ( .A(n1208), .B(n1037), .Y(n919) );
OAI21X1TS U1683 ( .A0(n1169), .A1(n2418), .B0(n1036), .Y(n1037) );
OAI221X1TS U1684 ( .A0(n2268), .A1(intDY_EWSW[32]), .B0(n2396), .B1(
intDY_EWSW[33]), .C0(n1943), .Y(n1952) );
OAI221XLTS U1685 ( .A0(n2392), .A1(intDY_EWSW[53]), .B0(n2399), .B1(
intDY_EWSW[10]), .C0(n1956), .Y(n1961) );
NOR2X4TS U1686 ( .A(n1305), .B(n1216), .Y(n1279) );
OAI221X1TS U1687 ( .A0(n2267), .A1(intDY_EWSW[55]), .B0(n2401), .B1(
intDY_EWSW[52]), .C0(n1963), .Y(n1970) );
NAND2X2TS U1688 ( .A(n2349), .B(shift_value_SHT2_EWR[2]), .Y(n1125) );
AOI211X2TS U1689 ( .A0(intDX_EWSW[44]), .A1(n2464), .B0(n2098), .C0(n2108),
.Y(n2106) );
OAI21X2TS U1690 ( .A0(intDY_EWSW[46]), .A1(n2403), .B0(n2097), .Y(n2108) );
OAI21X2TS U1691 ( .A0(n836), .A1(n2247), .B0(n1343), .Y(n1493) );
CLKINVX6TS U1692 ( .A(n1385), .Y(n2189) );
OAI21XLTS U1693 ( .A0(n1491), .A1(n1495), .B0(n1472), .Y(Data_array_SWR[17])
);
OAI21XLTS U1694 ( .A0(n1496), .A1(n1495), .B0(n1494), .Y(Data_array_SWR[14])
);
OAI21XLTS U1695 ( .A0(n1498), .A1(n1495), .B0(n1474), .Y(Data_array_SWR[13])
);
CLKINVX6TS U1696 ( .A(n1021), .Y(n1133) );
CLKINVX6TS U1697 ( .A(n1768), .Y(n1922) );
AOI31XLTS U1698 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2211), .A2(n2334), .B0(
n964), .Y(n966) );
OAI31X4TS U1699 ( .A0(Raw_mant_NRM_SWR[51]), .A1(Raw_mant_NRM_SWR[52]), .A2(
n931), .B0(n933), .Y(n954) );
NOR2BX2TS U1700 ( .AN(Raw_mant_NRM_SWR[28]), .B(n1329), .Y(n1334) );
OAI32X1TS U1701 ( .A0(n1119), .A1(Raw_mant_NRM_SWR[12]), .A2(
Raw_mant_NRM_SWR[14]), .B0(n1118), .B1(n1119), .Y(n1120) );
NOR2X2TS U1702 ( .A(shift_value_SHT2_EWR[5]), .B(shift_value_SHT2_EWR[4]),
.Y(n1519) );
NAND2X2TS U1703 ( .A(shift_value_SHT2_EWR[4]), .B(n2353), .Y(n1194) );
NAND2X2TS U1704 ( .A(shift_value_SHT2_EWR[5]), .B(shift_value_SHT2_EWR[4]),
.Y(n1203) );
OAI21X2TS U1705 ( .A0(shift_value_SHT2_EWR[4]), .A1(n1508), .B0(n1257), .Y(
n1228) );
OAI21XLTS U1706 ( .A0(intDX_EWSW[1]), .A1(n2478), .B0(intDX_EWSW[0]), .Y(
n2032) );
OAI21XLTS U1707 ( .A0(intDY_EWSW[35]), .A1(n2381), .B0(intDY_EWSW[34]), .Y(
n2118) );
NOR2XLTS U1708 ( .A(n2135), .B(intDX_EWSW[48]), .Y(n2136) );
NOR2XLTS U1709 ( .A(n2098), .B(intDX_EWSW[44]), .Y(n2099) );
OAI21XLTS U1710 ( .A0(intDY_EWSW[55]), .A1(n2142), .B0(intDY_EWSW[54]), .Y(
n2143) );
NOR2XLTS U1711 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[13]), .Y(n937) );
AOI21X1TS U1712 ( .A0(DMP_SFG[5]), .A1(DmP_mant_SFG_SWR[7]), .B0(n1900), .Y(
n1526) );
OAI211XLTS U1713 ( .A0(n1203), .A1(n1214), .B0(n1041), .C0(n1040), .Y(n1042)
);
AOI21X1TS U1714 ( .A0(DMP_SFG[9]), .A1(DmP_mant_SFG_SWR[11]), .B0(n1874),
.Y(n1530) );
AOI21X1TS U1715 ( .A0(DMP_SFG[17]), .A1(DmP_mant_SFG_SWR[19]), .B0(n1823),
.Y(n1538) );
NOR2XLTS U1716 ( .A(n1508), .B(n1194), .Y(n1081) );
NOR2XLTS U1717 ( .A(n1775), .B(n1919), .Y(n1776) );
OR2X1TS U1718 ( .A(n1379), .B(n2421), .Y(n1339) );
NOR2XLTS U1719 ( .A(Raw_mant_NRM_SWR[4]), .B(n2249), .Y(n977) );
OAI2BB1X1TS U1720 ( .A0N(DmP_mant_SFG_SWR[52]), .A1N(DMP_SFG[50]), .B0(n1571), .Y(n1613) );
NOR2XLTS U1721 ( .A(n1735), .B(n1919), .Y(n1736) );
NOR2XLTS U1722 ( .A(n1841), .B(n1934), .Y(n1842) );
OAI211XLTS U1723 ( .A0(n873), .A1(n1939), .B0(n2222), .C0(beg_OP), .Y(n1307)
);
NOR2XLTS U1724 ( .A(n1877), .B(n1876), .Y(n1878) );
NOR2XLTS U1725 ( .A(n1798), .B(n1797), .Y(n1799) );
OAI21XLTS U1726 ( .A0(n1923), .A1(n1922), .B0(n1921), .Y(n1927) );
NOR2XLTS U1727 ( .A(n1661), .B(n1660), .Y(n1662) );
NOR2XLTS U1728 ( .A(n1811), .B(n1810), .Y(n1812) );
OAI21XLTS U1729 ( .A0(n1882), .A1(n1922), .B0(n1881), .Y(n1886) );
OAI21XLTS U1730 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(n2222), .B0(
n1939), .Y(n830) );
OAI211XLTS U1731 ( .A0(n1305), .A1(n1176), .B0(n1175), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[0]) );
OAI21XLTS U1732 ( .A0(n1435), .A1(n1495), .B0(n1422), .Y(Data_array_SWR[22])
);
OR2X1TS U1733 ( .A(n2484), .B(exp_rslt_NRM2_EW1[3]), .Y(
formatted_number_W[55]) );
XNOR2X1TS U1734 ( .A(DP_OP_15J206_122_2221_n1), .B(ADD_OVRFLW_NRM2), .Y(n926) );
AND4X1TS U1735 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[0]), .D(exp_rslt_NRM2_EW1[1]), .Y(n921) );
AND4X1TS U1736 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n921), .Y(n922) );
AND4X1TS U1737 ( .A(exp_rslt_NRM2_EW1[9]), .B(exp_rslt_NRM2_EW1[8]), .C(
exp_rslt_NRM2_EW1[7]), .D(n922), .Y(n923) );
AND3X1TS U1738 ( .A(n926), .B(exp_rslt_NRM2_EW1[10]), .C(n923), .Y(
array_comparators_GTComparator_N0) );
OR4X2TS U1739 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[0]), .D(exp_rslt_NRM2_EW1[1]), .Y(n924) );
OR4X2TS U1740 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n924), .Y(n925) );
NOR4X1TS U1741 ( .A(exp_rslt_NRM2_EW1[9]), .B(exp_rslt_NRM2_EW1[8]), .C(
exp_rslt_NRM2_EW1[7]), .D(n925), .Y(n927) );
NOR3BX1TS U1742 ( .AN(n927), .B(n926), .C(exp_rslt_NRM2_EW1[10]), .Y(n928)
);
BUFX3TS U1743 ( .A(n928), .Y(n2484) );
NOR2XLTS U1744 ( .A(Raw_mant_NRM_SWR[45]), .B(Raw_mant_NRM_SWR[46]), .Y(n929) );
NOR3XLTS U1745 ( .A(Raw_mant_NRM_SWR[49]), .B(Raw_mant_NRM_SWR[50]), .C(n930), .Y(n931) );
NOR2X1TS U1746 ( .A(n886), .B(n895), .Y(n933) );
NAND2X2TS U1747 ( .A(n1114), .B(n1115), .Y(n2207) );
INVX2TS U1748 ( .A(Raw_mant_NRM_SWR[47]), .Y(n1362) );
NOR2X2TS U1749 ( .A(Raw_mant_NRM_SWR[43]), .B(n951), .Y(n1107) );
NOR2X2TS U1750 ( .A(Raw_mant_NRM_SWR[33]), .B(n970), .Y(n1113) );
NAND2BX2TS U1751 ( .AN(Raw_mant_NRM_SWR[30]), .B(n1324), .Y(n1329) );
AOI22X1TS U1752 ( .A0(n1334), .A1(n2246), .B0(n936), .B1(n935), .Y(n953) );
NOR4X2TS U1753 ( .A(Raw_mant_NRM_SWR[28]), .B(n887), .C(Raw_mant_NRM_SWR[29]), .D(n1329), .Y(n2211) );
NOR2BX2TS U1754 ( .AN(n971), .B(Raw_mant_NRM_SWR[21]), .Y(n947) );
AOI32X1TS U1755 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n963), .A2(n937), .B0(
Raw_mant_NRM_SWR[15]), .B1(n963), .Y(n938) );
NAND2X1TS U1756 ( .A(n1308), .B(Raw_mant_NRM_SWR[11]), .Y(n978) );
NAND2X1TS U1757 ( .A(n938), .B(n978), .Y(n939) );
NOR2X2TS U1758 ( .A(Raw_mant_NRM_SWR[9]), .B(n1320), .Y(n2217) );
NOR2X1TS U1759 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n1312)
);
NOR3BX2TS U1760 ( .AN(n2217), .B(n882), .C(Raw_mant_NRM_SWR[7]), .Y(n1313)
);
NOR2X2TS U1761 ( .A(n914), .B(n1336), .Y(n1316) );
NAND2X1TS U1762 ( .A(n1316), .B(Raw_mant_NRM_SWR[0]), .Y(n949) );
NOR2X1TS U1763 ( .A(n1112), .B(n2341), .Y(n964) );
NAND2X1TS U1764 ( .A(n947), .B(Raw_mant_NRM_SWR[19]), .Y(n972) );
OAI2BB1X1TS U1765 ( .A0N(n941), .A1N(Raw_mant_NRM_SWR[24]), .B0(n972), .Y(
n2210) );
NOR2XLTS U1766 ( .A(Raw_mant_NRM_SWR[28]), .B(n1329), .Y(n942) );
NAND2X1TS U1767 ( .A(n942), .B(n887), .Y(n975) );
OAI21XLTS U1768 ( .A0(Raw_mant_NRM_SWR[31]), .A1(Raw_mant_NRM_SWR[32]), .B0(
n1113), .Y(n945) );
OAI21XLTS U1769 ( .A0(Raw_mant_NRM_SWR[35]), .A1(Raw_mant_NRM_SWR[36]), .B0(
n943), .Y(n944) );
NOR3X1TS U1770 ( .A(n964), .B(n2210), .C(n946), .Y(n948) );
NAND2X1TS U1771 ( .A(n947), .B(Raw_mant_NRM_SWR[20]), .Y(n1109) );
OAI211X1TS U1772 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n949), .B0(n948), .C0(n1109), .Y(n1333) );
NAND4X1TS U1773 ( .A(n954), .B(n953), .C(n952), .D(n965), .Y(
LZD_raw_out_EWR[1]) );
INVX2TS U1774 ( .A(n2207), .Y(n960) );
NAND4XLTS U1775 ( .A(n955), .B(n1107), .C(Raw_mant_NRM_SWR[37]), .D(n2285),
.Y(n958) );
AOI21X1TS U1776 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n2329), .B0(
Raw_mant_NRM_SWR[51]), .Y(n956) );
AOI2BB1XLTS U1777 ( .A0N(Raw_mant_NRM_SWR[52]), .A1N(n956), .B0(n895), .Y(
n957) );
OAI22X1TS U1778 ( .A0(n958), .A1(Raw_mant_NRM_SWR[38]), .B0(n886), .B1(n957),
.Y(n959) );
AOI31XLTS U1779 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n960), .A2(n2335), .B0(n959), .Y(n961) );
OAI31X1TS U1780 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2350), .A2(n1310), .B0(
n961), .Y(n962) );
AOI21X1TS U1781 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n963), .B0(n962), .Y(n981)
);
AOI21X1TS U1782 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2333), .B0(
Raw_mant_NRM_SWR[9]), .Y(n967) );
OAI211X1TS U1783 ( .A0(n967), .A1(n1320), .B0(n966), .C0(n965), .Y(n2216) );
OAI22X1TS U1784 ( .A0(n2342), .A1(n969), .B0(n2207), .B1(n1362), .Y(n974) );
OA22X1TS U1785 ( .A0(n2338), .A1(n970), .B0(n1329), .B1(n2246), .Y(n1328) );
OAI211X1TS U1786 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n972), .B0(n1328), .C0(
n1321), .Y(n973) );
NOR4BX1TS U1787 ( .AN(n975), .B(n2205), .C(n974), .D(n973), .Y(n979) );
OAI211X1TS U1788 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n977), .B0(n1313), .C0(
n2336), .Y(n2218) );
NAND4X1TS U1789 ( .A(n979), .B(n978), .C(n1309), .D(n2218), .Y(n1119) );
AOI211X1TS U1790 ( .A0(n1316), .A1(Raw_mant_NRM_SWR[1]), .B0(n2216), .C0(
n1119), .Y(n980) );
OAI211X1TS U1791 ( .A0(n2356), .A1(n1325), .B0(n981), .C0(n980), .Y(
LZD_raw_out_EWR[0]) );
NAND2X2TS U1792 ( .A(Shift_reg_FLAGS_7[1]), .B(ADD_OVRFLW_NRM), .Y(n1366) );
AOI33XLTS U1793 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n2470), .B1(n873), .B2(n2225),
.Y(n832) );
INVX2TS U1794 ( .A(n1519), .Y(n1217) );
NAND3XLTS U1795 ( .A(bit_shift_SHT2), .B(n1508), .C(n1217), .Y(n1008) );
AOI22X1TS U1796 ( .A0(Data_array_SWR[63]), .A1(n982), .B0(n908), .B1(n983),
.Y(n995) );
OR2X2TS U1797 ( .A(shift_value_SHT2_EWR[2]), .B(n2349), .Y(n1169) );
NOR2XLTS U1798 ( .A(n1217), .B(n1169), .Y(n984) );
BUFX4TS U1799 ( .A(n984), .Y(n1215) );
NAND2X1TS U1800 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1179) );
NOR2XLTS U1801 ( .A(n1217), .B(n1179), .Y(n985) );
AOI22X1TS U1802 ( .A0(Data_array_SWR[67]), .A1(n1215), .B0(
Data_array_SWR[70]), .B1(n1200), .Y(n994) );
BUFX3TS U1803 ( .A(n1177), .Y(n1130) );
AOI22X1TS U1804 ( .A0(n896), .A1(n1130), .B0(n1206), .B1(Data_array_SWR[71]),
.Y(n988) );
INVX2TS U1805 ( .A(n1179), .Y(n1073) );
INVX4TS U1806 ( .A(n1169), .Y(n1207) );
AOI22X1TS U1807 ( .A0(n1208), .A1(n903), .B0(n1207), .B1(Data_array_SWR[78]),
.Y(n987) );
NAND2X1TS U1808 ( .A(n988), .B(n987), .Y(n1259) );
AOI22X1TS U1809 ( .A0(n1133), .A1(n906), .B0(n1129), .B1(n911), .Y(n991) );
AOI22X1TS U1810 ( .A0(n1208), .A1(Data_array_SWR[87]), .B0(n1130), .B1(n907),
.Y(n990) );
NAND2X1TS U1811 ( .A(n991), .B(n990), .Y(n1235) );
AOI22X1TS U1812 ( .A0(n986), .A1(n1259), .B0(n989), .B1(n1235), .Y(n993) );
NAND2X1TS U1813 ( .A(shift_value_SHT2_EWR[5]), .B(bit_shift_SHT2), .Y(n1521)
);
NAND4XLTS U1814 ( .A(n995), .B(n994), .C(n993), .D(n992), .Y(n1105) );
OR2X2TS U1815 ( .A(n1305), .B(n1217), .Y(n1287) );
CLKBUFX2TS U1816 ( .A(n1287), .Y(n1098) );
INVX4TS U1817 ( .A(n1098), .Y(n1222) );
AOI22X1TS U1818 ( .A0(n1133), .A1(n909), .B0(n1177), .B1(Data_array_SWR[86]),
.Y(n996) );
OAI211X2TS U1819 ( .A0(n2411), .A1(n1169), .B0(n996), .C0(n1033), .Y(n1258)
);
AOI22X1TS U1820 ( .A0(n1305), .A1(n1105), .B0(n1222), .B1(n1258), .Y(n997)
);
NAND2X1TS U1821 ( .A(n837), .B(n997), .Y(sftr_odat_SHT2_SWR[46]) );
AOI22X1TS U1822 ( .A0(n1133), .A1(n902), .B0(n1177), .B1(n905), .Y(n1000) );
AOI22X1TS U1823 ( .A0(n1208), .A1(n909), .B0(n1207), .B1(Data_array_SWR[82]),
.Y(n999) );
NAND2X1TS U1824 ( .A(n1000), .B(n999), .Y(n1084) );
AOI22X1TS U1825 ( .A0(n1133), .A1(n898), .B0(n1177), .B1(n900), .Y(n1001) );
OAI2BB1X1TS U1826 ( .A0N(n1207), .A1N(Data_array_SWR[73]), .B0(n1001), .Y(
n1002) );
AOI22X1TS U1827 ( .A0(n982), .A1(Data_array_SWR[57]), .B0(n1200), .B1(
Data_array_SWR[65]), .Y(n1004) );
AOI22X1TS U1828 ( .A0(n1215), .A1(n884), .B0(n983), .B1(Data_array_SWR[61]),
.Y(n1003) );
OAI211XLTS U1829 ( .A0(n853), .A1(n1194), .B0(n1004), .C0(n1003), .Y(n1005)
);
AOI21X1TS U1830 ( .A0(n989), .A1(n1084), .B0(n1005), .Y(n1006) );
OAI21X1TS U1831 ( .A0(n1506), .A1(n1203), .B0(n1006), .Y(n1507) );
INVX2TS U1832 ( .A(n1511), .Y(n1272) );
AOI22X1TS U1833 ( .A0(n1305), .A1(n1507), .B0(n1260), .B1(n1272), .Y(n1007)
);
NAND2X1TS U1834 ( .A(n837), .B(n1007), .Y(sftr_odat_SHT2_SWR[52]) );
AOI22X1TS U1835 ( .A0(n982), .A1(n883), .B0(n983), .B1(Data_array_SWR[64]),
.Y(n1015) );
AOI22X1TS U1836 ( .A0(n1215), .A1(Data_array_SWR[68]), .B0(n1200), .B1(n899),
.Y(n1014) );
AOI22X1TS U1837 ( .A0(n1133), .A1(Data_array_SWR[72]), .B0(n1130), .B1(
Data_array_SWR[75]), .Y(n1010) );
AOI22X1TS U1838 ( .A0(n1208), .A1(n904), .B0(n1129), .B1(Data_array_SWR[79]),
.Y(n1009) );
NAND2X1TS U1839 ( .A(n1010), .B(n1009), .Y(n1251) );
AOI22X1TS U1840 ( .A0(n1133), .A1(n912), .B0(n1129), .B1(n910), .Y(n1012) );
AOI22X1TS U1841 ( .A0(n1208), .A1(Data_array_SWR[88]), .B0(n1177), .B1(
Data_array_SWR[84]), .Y(n1011) );
NAND2X1TS U1842 ( .A(n1012), .B(n1011), .Y(n1238) );
AOI22X1TS U1843 ( .A0(n986), .A1(n1251), .B0(n989), .B1(n1238), .Y(n1013) );
NAND4XLTS U1844 ( .A(n1015), .B(n1014), .C(n1013), .D(n992), .Y(n1103) );
AOI22X1TS U1845 ( .A0(n1130), .A1(n910), .B0(n1129), .B1(Data_array_SWR[88]),
.Y(n1016) );
OAI211X2TS U1846 ( .A0(n2409), .A1(n1021), .B0(n1016), .C0(n1033), .Y(n1253)
);
AOI22X1TS U1847 ( .A0(n1305), .A1(n1103), .B0(n1222), .B1(n1253), .Y(n1017)
);
NAND2X1TS U1848 ( .A(n837), .B(n1017), .Y(sftr_odat_SHT2_SWR[45]) );
AOI22X1TS U1849 ( .A0(n1215), .A1(Data_array_SWR[69]), .B0(n983), .B1(
Data_array_SWR[66]), .Y(n1024) );
AOI22X1TS U1850 ( .A0(n982), .A1(n885), .B0(n1200), .B1(n901), .Y(n1023) );
AOI22X1TS U1851 ( .A0(n1133), .A1(Data_array_SWR[74]), .B0(n1130), .B1(
Data_array_SWR[77]), .Y(n1019) );
AOI22X1TS U1852 ( .A0(n1208), .A1(Data_array_SWR[81]), .B0(n1129), .B1(
Data_array_SWR[80]), .Y(n1018) );
NAND2X1TS U1853 ( .A(n1019), .B(n1018), .Y(n1518) );
AOI22X1TS U1854 ( .A0(n1130), .A1(Data_array_SWR[85]), .B0(n1129), .B1(n897),
.Y(n1020) );
AOI22X1TS U1855 ( .A0(n986), .A1(n1518), .B0(n989), .B1(n1517), .Y(n1022) );
NAND4XLTS U1856 ( .A(n1024), .B(n1023), .C(n1022), .D(n992), .Y(n1162) );
AOI22X1TS U1857 ( .A0(n1305), .A1(n1162), .B0(n1222), .B1(n1517), .Y(n1025)
);
NAND2X1TS U1858 ( .A(n837), .B(n1025), .Y(sftr_odat_SHT2_SWR[43]) );
AOI22X1TS U1859 ( .A0(n982), .A1(n884), .B0(n983), .B1(Data_array_SWR[65]),
.Y(n1032) );
AOI22X1TS U1860 ( .A0(n1215), .A1(n898), .B0(n1200), .B1(n900), .Y(n1031) );
AOI22X1TS U1861 ( .A0(n1133), .A1(Data_array_SWR[73]), .B0(n1130), .B1(
Data_array_SWR[76]), .Y(n1027) );
AOI22X1TS U1862 ( .A0(n1208), .A1(n905), .B0(n1129), .B1(n902), .Y(n1026) );
NAND2X1TS U1863 ( .A(n1027), .B(n1026), .Y(n1246) );
AOI22X1TS U1864 ( .A0(n1208), .A1(Data_array_SWR[89]), .B0(n1206), .B1(
Data_array_SWR[82]), .Y(n1029) );
AOI22X1TS U1865 ( .A0(n1130), .A1(n909), .B0(n1129), .B1(Data_array_SWR[86]),
.Y(n1028) );
NAND2X1TS U1866 ( .A(n1029), .B(n1028), .Y(n1241) );
AOI22X1TS U1867 ( .A0(n986), .A1(n1246), .B0(n989), .B1(n1241), .Y(n1030) );
NAND4XLTS U1868 ( .A(n1032), .B(n1031), .C(n1030), .D(n992), .Y(n1164) );
AOI22X1TS U1869 ( .A0(n1133), .A1(n907), .B0(n1130), .B1(n911), .Y(n1034) );
OAI211X2TS U1870 ( .A0(n2408), .A1(n1169), .B0(n1034), .C0(n1033), .Y(n1245)
);
AOI22X1TS U1871 ( .A0(n1305), .A1(n1164), .B0(n1222), .B1(n1245), .Y(n1035)
);
NAND2X1TS U1872 ( .A(n837), .B(n1035), .Y(sftr_odat_SHT2_SWR[44]) );
AOI22X1TS U1873 ( .A0(n1133), .A1(n899), .B0(n1177), .B1(Data_array_SWR[72]),
.Y(n1036) );
AOI22X1TS U1874 ( .A0(n1133), .A1(n904), .B0(n1177), .B1(n912), .Y(n1039) );
AOI22X1TS U1875 ( .A0(n1208), .A1(n910), .B0(n1207), .B1(Data_array_SWR[84]),
.Y(n1038) );
NAND2X2TS U1876 ( .A(n1039), .B(n1038), .Y(n1285) );
AOI22X1TS U1877 ( .A0(n982), .A1(Data_array_SWR[60]), .B0(n1200), .B1(
Data_array_SWR[68]), .Y(n1041) );
AOI22X1TS U1878 ( .A0(n1215), .A1(Data_array_SWR[64]), .B0(n983), .B1(n883),
.Y(n1040) );
AOI21X1TS U1879 ( .A0(n989), .A1(n1285), .B0(n1042), .Y(n1043) );
OAI21X1TS U1880 ( .A0(n855), .A1(n1194), .B0(n1043), .Y(n1166) );
AOI22X1TS U1881 ( .A0(n1133), .A1(n910), .B0(n1177), .B1(Data_array_SWR[88]),
.Y(n1044) );
NAND2X2TS U1882 ( .A(n1044), .B(n1124), .Y(n1278) );
AOI22X1TS U1883 ( .A0(n1305), .A1(n1166), .B0(n1222), .B1(n1278), .Y(n1045)
);
NAND2X1TS U1884 ( .A(n837), .B(n1045), .Y(sftr_odat_SHT2_SWR[49]) );
AOI22X1TS U1885 ( .A0(n982), .A1(Data_array_SWR[62]), .B0(n1200), .B1(
Data_array_SWR[69]), .Y(n1052) );
AOI22X1TS U1886 ( .A0(n1215), .A1(Data_array_SWR[66]), .B0(n983), .B1(n885),
.Y(n1051) );
AOI22X1TS U1887 ( .A0(n1133), .A1(n901), .B0(n1177), .B1(Data_array_SWR[74]),
.Y(n1047) );
AOI22X1TS U1888 ( .A0(n1208), .A1(Data_array_SWR[80]), .B0(n1207), .B1(
Data_array_SWR[77]), .Y(n1046) );
NAND2X1TS U1889 ( .A(n1047), .B(n1046), .Y(n1141) );
AOI22X1TS U1890 ( .A0(n1208), .A1(n897), .B0(n1206), .B1(Data_array_SWR[81]),
.Y(n1049) );
AOI22X1TS U1891 ( .A0(n1130), .A1(Data_array_SWR[83]), .B0(n1207), .B1(
Data_array_SWR[85]), .Y(n1048) );
NAND2X2TS U1892 ( .A(n1049), .B(n1048), .Y(n1151) );
AOI22X1TS U1893 ( .A0(n986), .A1(n1141), .B0(n989), .B1(n1151), .Y(n1050) );
NAND4XLTS U1894 ( .A(n1052), .B(n1051), .C(n1050), .D(n992), .Y(n1153) );
AOI22X1TS U1895 ( .A0(n1133), .A1(Data_array_SWR[85]), .B0(n1177), .B1(n897),
.Y(n1053) );
NAND2X1TS U1896 ( .A(n1053), .B(n1124), .Y(n1154) );
AOI22X1TS U1897 ( .A0(n1305), .A1(n1153), .B0(n1222), .B1(n1154), .Y(n1054)
);
NAND2X1TS U1898 ( .A(n837), .B(n1054), .Y(sftr_odat_SHT2_SWR[47]) );
AOI22X1TS U1899 ( .A0(n1215), .A1(n899), .B0(n983), .B1(Data_array_SWR[68]),
.Y(n1059) );
AOI22X1TS U1900 ( .A0(n982), .A1(Data_array_SWR[64]), .B0(n1200), .B1(
Data_array_SWR[72]), .Y(n1058) );
AOI22X1TS U1901 ( .A0(n1133), .A1(Data_array_SWR[75]), .B0(n1130), .B1(
Data_array_SWR[79]), .Y(n1056) );
AOI22X1TS U1902 ( .A0(n1073), .A1(n912), .B0(n1129), .B1(n904), .Y(n1055) );
NAND2X1TS U1903 ( .A(n1056), .B(n1055), .Y(n1252) );
AOI22X1TS U1904 ( .A0(n986), .A1(n1252), .B0(n989), .B1(n1253), .Y(n1057) );
NAND4XLTS U1905 ( .A(n1059), .B(n1058), .C(n1057), .D(n992), .Y(n1158) );
AOI22X1TS U1906 ( .A0(n1305), .A1(n1158), .B0(n1222), .B1(n1238), .Y(n1060)
);
NAND2X1TS U1907 ( .A(n837), .B(n1060), .Y(sftr_odat_SHT2_SWR[41]) );
AOI22X1TS U1908 ( .A0(n1215), .A1(n900), .B0(n983), .B1(n898), .Y(n1065) );
AOI22X1TS U1909 ( .A0(n982), .A1(Data_array_SWR[65]), .B0(n1200), .B1(
Data_array_SWR[73]), .Y(n1064) );
AOI22X1TS U1910 ( .A0(n1133), .A1(Data_array_SWR[76]), .B0(n1130), .B1(n902),
.Y(n1062) );
AOI22X1TS U1911 ( .A0(n1208), .A1(Data_array_SWR[82]), .B0(n1129), .B1(n905),
.Y(n1061) );
NAND2X1TS U1912 ( .A(n1062), .B(n1061), .Y(n1261) );
AOI22X1TS U1913 ( .A0(n986), .A1(n1261), .B0(n989), .B1(n1258), .Y(n1063) );
NAND4XLTS U1914 ( .A(n1065), .B(n1064), .C(n1063), .D(n992), .Y(n1156) );
AOI22X1TS U1915 ( .A0(n1305), .A1(n1156), .B0(n1222), .B1(n1235), .Y(n1066)
);
NAND2X1TS U1916 ( .A(n837), .B(n1066), .Y(sftr_odat_SHT2_SWR[40]) );
AOI22X1TS U1917 ( .A0(n982), .A1(Data_array_SWR[66]), .B0(n983), .B1(
Data_array_SWR[69]), .Y(n1071) );
AOI22X1TS U1918 ( .A0(n1215), .A1(n901), .B0(n1200), .B1(Data_array_SWR[74]),
.Y(n1070) );
AOI22X1TS U1919 ( .A0(n1133), .A1(Data_array_SWR[77]), .B0(n1177), .B1(
Data_array_SWR[80]), .Y(n1068) );
AOI22X1TS U1920 ( .A0(n1208), .A1(Data_array_SWR[83]), .B0(n1207), .B1(
Data_array_SWR[81]), .Y(n1067) );
NAND2X1TS U1921 ( .A(n1068), .B(n1067), .Y(n1142) );
AOI22X1TS U1922 ( .A0(n986), .A1(n1142), .B0(n989), .B1(n1154), .Y(n1069) );
NAND4XLTS U1923 ( .A(n1071), .B(n1070), .C(n1069), .D(n992), .Y(n1150) );
AOI22X1TS U1924 ( .A0(n1305), .A1(n1150), .B0(n1222), .B1(n1151), .Y(n1072)
);
NAND2X1TS U1925 ( .A(n837), .B(n1072), .Y(sftr_odat_SHT2_SWR[39]) );
AOI22X1TS U1926 ( .A0(Data_array_SWR[67]), .A1(n983), .B0(n982), .B1(n908),
.Y(n1078) );
AOI22X1TS U1927 ( .A0(Data_array_SWR[70]), .A1(n1215), .B0(
Data_array_SWR[71]), .B1(n1200), .Y(n1077) );
AOI22X1TS U1928 ( .A0(n896), .A1(n1133), .B0(n1177), .B1(Data_array_SWR[78]),
.Y(n1075) );
AOI22X1TS U1929 ( .A0(n1073), .A1(n906), .B0(n1129), .B1(n903), .Y(n1074) );
NAND2X1TS U1930 ( .A(n1075), .B(n1074), .Y(n1247) );
AOI22X1TS U1931 ( .A0(n986), .A1(n1247), .B0(n989), .B1(n1245), .Y(n1076) );
NAND4XLTS U1932 ( .A(n1078), .B(n1077), .C(n1076), .D(n992), .Y(n1160) );
AOI22X1TS U1933 ( .A0(n1305), .A1(n1160), .B0(n1222), .B1(n1241), .Y(n1079)
);
NAND2X1TS U1934 ( .A(n837), .B(n1079), .Y(sftr_odat_SHT2_SWR[42]) );
INVX2TS U1935 ( .A(n989), .Y(n1216) );
NOR2XLTS U1936 ( .A(n1305), .B(n1194), .Y(n1080) );
BUFX4TS U1937 ( .A(n1080), .Y(n1300) );
INVX2TS U1938 ( .A(n1506), .Y(n1271) );
AOI22X1TS U1939 ( .A0(n1231), .A1(n1272), .B0(n1300), .B1(n1271), .Y(n1089)
);
BUFX4TS U1940 ( .A(n1081), .Y(n1290) );
AOI22X1TS U1941 ( .A0(n1133), .A1(n903), .B0(n1177), .B1(n906), .Y(n1083) );
AOI22X1TS U1942 ( .A0(n1208), .A1(n911), .B0(n1207), .B1(n907), .Y(n1082) );
NAND2X2TS U1943 ( .A(n1083), .B(n1082), .Y(n1276) );
INVX2TS U1944 ( .A(n1228), .Y(n1232) );
INVX2TS U1945 ( .A(n1084), .Y(n1274) );
AOI22X1TS U1946 ( .A0(n896), .A1(n1129), .B0(n1206), .B1(Data_array_SWR[70]),
.Y(n1085) );
OAI22X1TS U1947 ( .A0(n1274), .A1(n1287), .B0(n1195), .B1(n1510), .Y(n1087)
);
AOI211X1TS U1948 ( .A0(n1290), .A1(n1276), .B0(n1232), .C0(n1087), .Y(n1088)
);
NAND2X1TS U1949 ( .A(n1089), .B(n1088), .Y(sftr_odat_SHT2_SWR[34]) );
INVX2TS U1950 ( .A(n1214), .Y(n1280) );
AOI22X1TS U1951 ( .A0(n1300), .A1(n1278), .B0(n1280), .B1(n1231), .Y(n1094)
);
AOI22X1TS U1952 ( .A0(n1206), .A1(Data_array_SWR[79]), .B0(n1177), .B1(n904),
.Y(n1090) );
OAI21X1TS U1953 ( .A0(n1179), .A1(n2409), .B0(n1090), .Y(n1091) );
AOI21X2TS U1954 ( .A0(n1207), .A1(n912), .B0(n1091), .Y(n1283) );
OAI22X1TS U1955 ( .A0(n855), .A1(n1510), .B0(n1283), .B1(n1098), .Y(n1092)
);
AOI211X1TS U1956 ( .A0(n1290), .A1(n1285), .B0(n1232), .C0(n1092), .Y(n1093)
);
NAND2X1TS U1957 ( .A(n1094), .B(n1093), .Y(sftr_odat_SHT2_SWR[33]) );
AOI22X1TS U1958 ( .A0(n1280), .A1(n1279), .B0(n1290), .B1(n1278), .Y(n1097)
);
INVX2TS U1959 ( .A(n1292), .Y(n1266) );
OAI22X1TS U1960 ( .A0(n855), .A1(n1287), .B0(n1283), .B1(n1510), .Y(n1095)
);
AOI211X1TS U1961 ( .A0(n1300), .A1(n1285), .B0(n1266), .C0(n1095), .Y(n1096)
);
NAND2X1TS U1962 ( .A(n1097), .B(n1096), .Y(sftr_odat_SHT2_SWR[21]) );
AOI22X1TS U1963 ( .A0(n1279), .A1(n1272), .B0(n1290), .B1(n1271), .Y(n1101)
);
OAI22X1TS U1964 ( .A0(n1274), .A1(n1510), .B0(n1195), .B1(n1098), .Y(n1099)
);
AOI211X1TS U1965 ( .A0(n1300), .A1(n1276), .B0(n1266), .C0(n1099), .Y(n1100)
);
NAND2X1TS U1966 ( .A(n1101), .B(n1100), .Y(sftr_odat_SHT2_SWR[20]) );
NAND2X1TS U1967 ( .A(bit_shift_SHT2), .B(n1305), .Y(n1102) );
INVX2TS U1968 ( .A(n1510), .Y(n1302) );
AOI22X1TS U1969 ( .A0(n1262), .A1(n1253), .B0(n1508), .B1(n1103), .Y(n1104)
);
NAND2X1TS U1970 ( .A(n1303), .B(n1104), .Y(sftr_odat_SHT2_SWR[9]) );
AOI22X1TS U1971 ( .A0(n1262), .A1(n1258), .B0(n1508), .B1(n1105), .Y(n1106)
);
NAND2X1TS U1972 ( .A(n1303), .B(n1106), .Y(sftr_odat_SHT2_SWR[8]) );
OAI21XLTS U1973 ( .A0(Raw_mant_NRM_SWR[40]), .A1(Raw_mant_NRM_SWR[42]), .B0(
n1107), .Y(n1108) );
AOI21X1TS U1974 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1313), .B0(n1111), .Y(n2220) );
NOR2BX1TS U1975 ( .AN(n894), .B(n1112), .Y(n1322) );
AOI22X1TS U1976 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n1113), .B0(n1322), .B1(
n2341), .Y(n1122) );
NOR2BX1TS U1977 ( .AN(n1115), .B(n1114), .Y(n1116) );
NAND4XLTS U1978 ( .A(n2220), .B(n1122), .C(n1121), .D(n1120), .Y(
LZD_raw_out_EWR[2]) );
BUFX3TS U1979 ( .A(n2492), .Y(n2510) );
BUFX3TS U1980 ( .A(n838), .Y(n2513) );
BUFX3TS U1981 ( .A(n2516), .Y(n2512) );
BUFX3TS U1982 ( .A(n2492), .Y(n2526) );
BUFX3TS U1983 ( .A(n2531), .Y(n2527) );
BUFX3TS U1984 ( .A(n2531), .Y(n2518) );
BUFX3TS U1985 ( .A(n2516), .Y(n2523) );
BUFX3TS U1986 ( .A(n1123), .Y(n2487) );
BUFX3TS U1987 ( .A(n2500), .Y(n2495) );
BUFX3TS U1988 ( .A(n838), .Y(n2502) );
AO21X2TS U1989 ( .A0(n1206), .A1(Data_array_SWR[89]), .B0(n1199), .Y(n1291)
);
AOI21X2TS U1990 ( .A0(n1206), .A1(n911), .B0(n1126), .Y(n1298) );
INVX2TS U1991 ( .A(n1298), .Y(n1146) );
AOI22X1TS U1992 ( .A0(n1231), .A1(n1291), .B0(n1300), .B1(n1146), .Y(n1138)
);
AOI22X1TS U1993 ( .A0(n1206), .A1(n900), .B0(n1177), .B1(Data_array_SWR[73]),
.Y(n1128) );
AOI22X1TS U1994 ( .A0(n1208), .A1(n902), .B0(n1207), .B1(Data_array_SWR[76]),
.Y(n1127) );
NAND2X1TS U1995 ( .A(n1128), .B(n1127), .Y(n1296) );
AOI22X1TS U1996 ( .A0(n1133), .A1(Data_array_SWR[78]), .B0(n1129), .B1(n906),
.Y(n1132) );
AOI22X1TS U1997 ( .A0(n1208), .A1(n907), .B0(n1130), .B1(n903), .Y(n1131) );
NAND2X1TS U1998 ( .A(n1132), .B(n1131), .Y(n1221) );
AOI22X1TS U1999 ( .A0(n1302), .A1(n1296), .B0(n1260), .B1(n1221), .Y(n1137)
);
AOI22X1TS U2000 ( .A0(n1133), .A1(n905), .B0(n1207), .B1(n909), .Y(n1135) );
AOI22X1TS U2001 ( .A0(n1208), .A1(Data_array_SWR[86]), .B0(n1177), .B1(
Data_array_SWR[82]), .Y(n1134) );
NAND2X2TS U2002 ( .A(n1135), .B(n1134), .Y(n1289) );
NAND2X1TS U2003 ( .A(n1290), .B(n1289), .Y(n1136) );
NAND4XLTS U2004 ( .A(n1228), .B(n1138), .C(n1137), .D(n1136), .Y(
sftr_odat_SHT2_SWR[32]) );
INVX2TS U2005 ( .A(n1300), .Y(n1282) );
AOI22X1TS U2006 ( .A0(n1262), .A1(n1141), .B0(n1260), .B1(n1142), .Y(n1140)
);
AOI21X1TS U2007 ( .A0(n1290), .A1(n1151), .B0(n1257), .Y(n1139) );
OAI211X1TS U2008 ( .A0(n1145), .A1(n1282), .B0(n1140), .C0(n1139), .Y(
sftr_odat_SHT2_SWR[31]) );
INVX2TS U2009 ( .A(n1290), .Y(n1244) );
AOI22X1TS U2010 ( .A0(n1262), .A1(n1142), .B0(n1260), .B1(n1141), .Y(n1144)
);
AOI21X1TS U2011 ( .A0(n1300), .A1(n1151), .B0(n1257), .Y(n1143) );
OAI211X1TS U2012 ( .A0(n1244), .A1(n1145), .B0(n1144), .C0(n1143), .Y(
sftr_odat_SHT2_SWR[23]) );
AOI22X1TS U2013 ( .A0(n1279), .A1(n1291), .B0(n1290), .B1(n1146), .Y(n1149)
);
AOI22X1TS U2014 ( .A0(n1222), .A1(n1296), .B0(n1302), .B1(n1221), .Y(n1148)
);
AOI21X1TS U2015 ( .A0(n1300), .A1(n1289), .B0(n1266), .Y(n1147) );
NAND3XLTS U2016 ( .A(n1149), .B(n1148), .C(n1147), .Y(sftr_odat_SHT2_SWR[22]) );
AOI22X1TS U2017 ( .A0(n1262), .A1(n1151), .B0(n1508), .B1(n1150), .Y(n1152)
);
NAND2X1TS U2018 ( .A(n1303), .B(n1152), .Y(sftr_odat_SHT2_SWR[15]) );
AOI22X1TS U2019 ( .A0(n1262), .A1(n1154), .B0(n1508), .B1(n1153), .Y(n1155)
);
NAND2X1TS U2020 ( .A(n1303), .B(n1155), .Y(sftr_odat_SHT2_SWR[7]) );
AOI22X1TS U2021 ( .A0(n1262), .A1(n1235), .B0(n1508), .B1(n1156), .Y(n1157)
);
NAND2X1TS U2022 ( .A(n1303), .B(n1157), .Y(sftr_odat_SHT2_SWR[14]) );
AOI22X1TS U2023 ( .A0(n1262), .A1(n1238), .B0(n1508), .B1(n1158), .Y(n1159)
);
NAND2X1TS U2024 ( .A(n1303), .B(n1159), .Y(sftr_odat_SHT2_SWR[13]) );
AOI22X1TS U2025 ( .A0(n1302), .A1(n1241), .B0(n1508), .B1(n1160), .Y(n1161)
);
NAND2X1TS U2026 ( .A(n1303), .B(n1161), .Y(sftr_odat_SHT2_SWR[12]) );
AOI22X1TS U2027 ( .A0(n1302), .A1(n1517), .B0(n1508), .B1(n1162), .Y(n1163)
);
NAND2X1TS U2028 ( .A(n1303), .B(n1163), .Y(sftr_odat_SHT2_SWR[11]) );
AOI22X1TS U2029 ( .A0(n1262), .A1(n1245), .B0(n1508), .B1(n1164), .Y(n1165)
);
NAND2X1TS U2030 ( .A(n1303), .B(n1165), .Y(sftr_odat_SHT2_SWR[10]) );
AOI22X1TS U2031 ( .A0(n1262), .A1(n1278), .B0(n1508), .B1(n1166), .Y(n1167)
);
NAND2X1TS U2032 ( .A(n1303), .B(n1167), .Y(sftr_odat_SHT2_SWR[5]) );
OR2X1TS U2033 ( .A(busy), .B(Shift_reg_FLAGS_7[1]), .Y(n_7_net_) );
NAND2X1TS U2034 ( .A(DmP_EXP_EWSW[52]), .B(n920), .Y(n1168) );
OAI21XLTS U2035 ( .A0(DmP_EXP_EWSW[52]), .A1(n920), .B0(n1168), .Y(
Shift_amount_EXP_EW[0]) );
NAND2X1TS U2036 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n873), .Y(n2222) );
NOR2X1TS U2037 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2225), .Y(n2224) );
INVX2TS U2038 ( .A(n2224), .Y(n1939) );
INVX2TS U2039 ( .A(intadd_470_SUM_0_), .Y(Shift_amount_EXP_EW[1]) );
INVX2TS U2040 ( .A(intadd_470_SUM_1_), .Y(Shift_amount_EXP_EW[2]) );
INVX2TS U2041 ( .A(intadd_470_SUM_2_), .Y(Shift_amount_EXP_EW[3]) );
INVX2TS U2042 ( .A(intadd_470_SUM_3_), .Y(Shift_amount_EXP_EW[4]) );
INVX2TS U2043 ( .A(n1168), .Y(intadd_470_CI) );
OAI32X1TS U2044 ( .A0(n1194), .A1(n1169), .A2(n2407), .B0(n1218), .B1(n1194),
.Y(n1173) );
AOI22X1TS U2045 ( .A0(n1200), .A1(n908), .B0(n983), .B1(Data_array_SWR[59]),
.Y(n1171) );
AOI22X1TS U2046 ( .A0(n1215), .A1(Data_array_SWR[63]), .B0(n982), .B1(
Data_array_SWR[55]), .Y(n1170) );
OAI211XLTS U2047 ( .A0(n1298), .A1(n1203), .B0(n1171), .C0(n1170), .Y(n1172)
);
AOI211X1TS U2048 ( .A0(n989), .A1(n1221), .B0(n1173), .C0(n1172), .Y(n1176)
);
NAND2X1TS U2049 ( .A(n1291), .B(n1222), .Y(n1174) );
OAI211XLTS U2050 ( .A0(n1176), .A1(n1508), .B0(n837), .C0(n1174), .Y(
sftr_odat_SHT2_SWR[54]) );
NAND2X1TS U2051 ( .A(n1291), .B(n1262), .Y(n1175) );
AOI22X1TS U2052 ( .A0(n1206), .A1(Data_array_SWR[68]), .B0(n1177), .B1(n899),
.Y(n1178) );
INVX2TS U2053 ( .A(n1203), .Y(n1185) );
AOI22X1TS U2054 ( .A0(n982), .A1(Data_array_SWR[56]), .B0(n1200), .B1(
Data_array_SWR[64]), .Y(n1181) );
AOI22X1TS U2055 ( .A0(n1215), .A1(n883), .B0(n983), .B1(Data_array_SWR[60]),
.Y(n1180) );
OAI211XLTS U2056 ( .A0(n1283), .A1(n1216), .B0(n1181), .C0(n1180), .Y(n1182)
);
AOI21X1TS U2057 ( .A0(n1185), .A1(n1278), .B0(n1182), .Y(n1183) );
OAI21X1TS U2058 ( .A0(n1288), .A1(n1194), .B0(n1183), .Y(n1212) );
NAND2X1TS U2059 ( .A(n1508), .B(n1212), .Y(n1184) );
OAI211XLTS U2060 ( .A0(n1510), .A1(n1214), .B0(n1303), .C0(n1184), .Y(
sftr_odat_SHT2_SWR[1]) );
OR2X1TS U2061 ( .A(n2484), .B(exp_rslt_NRM2_EW1[0]), .Y(
formatted_number_W[52]) );
OR2X1TS U2062 ( .A(n2484), .B(exp_rslt_NRM2_EW1[8]), .Y(
formatted_number_W[60]) );
OR2X1TS U2063 ( .A(n2484), .B(exp_rslt_NRM2_EW1[7]), .Y(
formatted_number_W[59]) );
OR2X1TS U2064 ( .A(n2484), .B(exp_rslt_NRM2_EW1[4]), .Y(
formatted_number_W[56]) );
OR2X1TS U2065 ( .A(n2484), .B(exp_rslt_NRM2_EW1[9]), .Y(
formatted_number_W[61]) );
OR2X1TS U2066 ( .A(n2484), .B(exp_rslt_NRM2_EW1[1]), .Y(
formatted_number_W[53]) );
OR2X1TS U2067 ( .A(n2484), .B(exp_rslt_NRM2_EW1[5]), .Y(
formatted_number_W[57]) );
OR2X1TS U2068 ( .A(n2484), .B(exp_rslt_NRM2_EW1[6]), .Y(
formatted_number_W[58]) );
OR2X1TS U2069 ( .A(n2484), .B(exp_rslt_NRM2_EW1[2]), .Y(
formatted_number_W[54]) );
AOI22X1TS U2070 ( .A0(n1215), .A1(Data_array_SWR[65]), .B0(n1200), .B1(n898),
.Y(n1188) );
AOI22X1TS U2071 ( .A0(n982), .A1(Data_array_SWR[61]), .B0(n983), .B1(n884),
.Y(n1187) );
AOI22X1TS U2072 ( .A0(n989), .A1(n1289), .B0(n1185), .B1(n1291), .Y(n1186)
);
NAND3XLTS U2073 ( .A(n1188), .B(n1187), .C(n1186), .Y(n1295) );
AOI22X1TS U2074 ( .A0(n1305), .A1(n1295), .B0(n1290), .B1(n1296), .Y(n1189)
);
OAI211X1TS U2075 ( .A0(n1298), .A1(n1287), .B0(n1189), .C0(n837), .Y(
sftr_odat_SHT2_SWR[48]) );
AOI22X1TS U2076 ( .A0(Data_array_SWR[67]), .A1(n1200), .B0(n982), .B1(
Data_array_SWR[59]), .Y(n1191) );
AOI22X1TS U2077 ( .A0(n1215), .A1(n908), .B0(Data_array_SWR[63]), .B1(n983),
.Y(n1190) );
OAI211XLTS U2078 ( .A0(n1203), .A1(n1511), .B0(n1191), .C0(n1190), .Y(n1192)
);
AOI21X1TS U2079 ( .A0(n989), .A1(n1276), .B0(n1192), .Y(n1193) );
OAI21X1TS U2080 ( .A0(n1195), .A1(n1194), .B0(n1193), .Y(n1504) );
NAND2X1TS U2081 ( .A(n1305), .B(n1504), .Y(n1196) );
OAI211X1TS U2082 ( .A0(n1506), .A1(n1287), .B0(n1196), .C0(n837), .Y(
sftr_odat_SHT2_SWR[50]) );
AOI22X1TS U2083 ( .A0(n1206), .A1(Data_array_SWR[80]), .B0(n1207), .B1(
Data_array_SWR[83]), .Y(n1198) );
AOI22X1TS U2084 ( .A0(n1208), .A1(Data_array_SWR[85]), .B0(n1177), .B1(
Data_array_SWR[81]), .Y(n1197) );
NAND2X1TS U2085 ( .A(n1198), .B(n1197), .Y(n1267) );
AOI21X1TS U2086 ( .A0(n1206), .A1(n897), .B0(n1199), .Y(n1205) );
AOI22X1TS U2087 ( .A0(n1215), .A1(n885), .B0(n1200), .B1(Data_array_SWR[66]),
.Y(n1202) );
AOI22X1TS U2088 ( .A0(n982), .A1(Data_array_SWR[58]), .B0(n983), .B1(
Data_array_SWR[62]), .Y(n1201) );
OAI211XLTS U2089 ( .A0(n1203), .A1(n1205), .B0(n1202), .C0(n1201), .Y(n1204)
);
AOI21X1TS U2090 ( .A0(n989), .A1(n1267), .B0(n1204), .Y(n1306) );
INVX2TS U2091 ( .A(n1205), .Y(n1301) );
AOI22X1TS U2092 ( .A0(n1206), .A1(Data_array_SWR[69]), .B0(n1177), .B1(n901),
.Y(n1210) );
AOI22X1TS U2093 ( .A0(n1208), .A1(Data_array_SWR[77]), .B0(n1207), .B1(
Data_array_SWR[74]), .Y(n1209) );
NAND2X1TS U2094 ( .A(n1210), .B(n1209), .Y(n1299) );
AOI22X1TS U2095 ( .A0(n1222), .A1(n1301), .B0(n1290), .B1(n1299), .Y(n1211)
);
OAI211X1TS U2096 ( .A0(n1306), .A1(n1508), .B0(n837), .C0(n1211), .Y(
sftr_odat_SHT2_SWR[51]) );
NAND2X1TS U2097 ( .A(n1305), .B(n1212), .Y(n1213) );
OAI211X1TS U2098 ( .A0(n1214), .A1(n1287), .B0(n1213), .C0(n837), .Y(
sftr_odat_SHT2_SWR[53]) );
CLKAND2X2TS U2099 ( .A(n1215), .B(Data_array_SWR[71]), .Y(n1220) );
OAI22X1TS U2100 ( .A0(n1218), .A1(n1217), .B0(n1298), .B1(n1216), .Y(n1219)
);
AOI211X1TS U2101 ( .A0(n986), .A1(n1221), .B0(n1220), .C0(n1219), .Y(n1294)
);
AOI22X1TS U2102 ( .A0(n1291), .A1(n1300), .B0(n1222), .B1(n1289), .Y(n1223)
);
OAI211X1TS U2103 ( .A0(n1294), .A1(n1508), .B0(n1228), .C0(n1223), .Y(
sftr_odat_SHT2_SWR[38]) );
AOI22X1TS U2104 ( .A0(n1300), .A1(n1280), .B0(n1231), .B1(n1278), .Y(n1224)
);
OAI211XLTS U2105 ( .A0(n1283), .A1(n1244), .B0(n1228), .C0(n1224), .Y(n1225)
);
AOI21X1TS U2106 ( .A0(n1260), .A1(n1285), .B0(n1225), .Y(n1226) );
OAI21X1TS U2107 ( .A0(n1288), .A1(n1510), .B0(n1226), .Y(
sftr_odat_SHT2_SWR[37]) );
AOI22X1TS U2108 ( .A0(n1300), .A1(n1272), .B0(n1231), .B1(n1271), .Y(n1227)
);
OAI211XLTS U2109 ( .A0(n1274), .A1(n1244), .B0(n1228), .C0(n1227), .Y(n1229)
);
AOI21X1TS U2110 ( .A0(n1260), .A1(n1276), .B0(n1229), .Y(n1230) );
OAI21X1TS U2111 ( .A0(n853), .A1(n1510), .B0(n1230), .Y(
sftr_odat_SHT2_SWR[36]) );
INVX2TS U2112 ( .A(n1299), .Y(n1270) );
OAI32X1TS U2113 ( .A0(n1232), .A1(n1300), .A2(n1231), .B0(n1301), .B1(n1232),
.Y(n1234) );
OAI21XLTS U2114 ( .A0(n1260), .A1(n1290), .B0(n1267), .Y(n1233) );
OAI211X1TS U2115 ( .A0(n1510), .A1(n1270), .B0(n1234), .C0(n1233), .Y(
sftr_odat_SHT2_SWR[35]) );
AOI21X1TS U2116 ( .A0(n1300), .A1(n1258), .B0(n1257), .Y(n1237) );
AOI22X1TS U2117 ( .A0(n1262), .A1(n1259), .B0(n1260), .B1(n1261), .Y(n1236)
);
OAI211X1TS U2118 ( .A0(n1244), .A1(n1265), .B0(n1237), .C0(n1236), .Y(
sftr_odat_SHT2_SWR[30]) );
AOI22X1TS U2119 ( .A0(n1262), .A1(n1251), .B0(n1260), .B1(n1252), .Y(n1240)
);
AOI21X1TS U2120 ( .A0(n1300), .A1(n1253), .B0(n1257), .Y(n1239) );
OAI211X1TS U2121 ( .A0(n1244), .A1(n1256), .B0(n1240), .C0(n1239), .Y(
sftr_odat_SHT2_SWR[29]) );
AOI21X1TS U2122 ( .A0(n1300), .A1(n1245), .B0(n1257), .Y(n1243) );
AOI22X1TS U2123 ( .A0(n1262), .A1(n1246), .B0(n1260), .B1(n1247), .Y(n1242)
);
OAI211X1TS U2124 ( .A0(n1244), .A1(n1250), .B0(n1243), .C0(n1242), .Y(
sftr_odat_SHT2_SWR[28]) );
AOI21X1TS U2125 ( .A0(n1290), .A1(n1245), .B0(n1257), .Y(n1249) );
AOI22X1TS U2126 ( .A0(n1262), .A1(n1247), .B0(n1260), .B1(n1246), .Y(n1248)
);
OAI211X1TS U2127 ( .A0(n1250), .A1(n1282), .B0(n1249), .C0(n1248), .Y(
sftr_odat_SHT2_SWR[26]) );
AOI22X1TS U2128 ( .A0(n1262), .A1(n1252), .B0(n1260), .B1(n1251), .Y(n1255)
);
AOI21X1TS U2129 ( .A0(n1290), .A1(n1253), .B0(n1257), .Y(n1254) );
OAI211X1TS U2130 ( .A0(n1256), .A1(n1282), .B0(n1255), .C0(n1254), .Y(
sftr_odat_SHT2_SWR[25]) );
AOI21X1TS U2131 ( .A0(n1290), .A1(n1258), .B0(n1257), .Y(n1264) );
AOI22X1TS U2132 ( .A0(n1262), .A1(n1261), .B0(n1260), .B1(n1259), .Y(n1263)
);
OAI211X1TS U2133 ( .A0(n1265), .A1(n1282), .B0(n1264), .C0(n1263), .Y(
sftr_odat_SHT2_SWR[24]) );
OAI32X1TS U2134 ( .A0(n1266), .A1(n1290), .A2(n1279), .B0(n1301), .B1(n1266),
.Y(n1269) );
OAI21XLTS U2135 ( .A0(n1302), .A1(n1300), .B0(n1267), .Y(n1268) );
OAI211X1TS U2136 ( .A0(n1287), .A1(n1270), .B0(n1269), .C0(n1268), .Y(
sftr_odat_SHT2_SWR[19]) );
AOI22X1TS U2137 ( .A0(n1290), .A1(n1272), .B0(n1279), .B1(n1271), .Y(n1273)
);
OAI211XLTS U2138 ( .A0(n1274), .A1(n1282), .B0(n1292), .C0(n1273), .Y(n1275)
);
AOI21X1TS U2139 ( .A0(n1302), .A1(n1276), .B0(n1275), .Y(n1277) );
OAI21X1TS U2140 ( .A0(n853), .A1(n1287), .B0(n1277), .Y(
sftr_odat_SHT2_SWR[18]) );
AOI22X1TS U2141 ( .A0(n1280), .A1(n1290), .B0(n1279), .B1(n1278), .Y(n1281)
);
OAI211XLTS U2142 ( .A0(n1283), .A1(n1282), .B0(n1292), .C0(n1281), .Y(n1284)
);
AOI21X1TS U2143 ( .A0(n1302), .A1(n1285), .B0(n1284), .Y(n1286) );
OAI21X1TS U2144 ( .A0(n1288), .A1(n1287), .B0(n1286), .Y(
sftr_odat_SHT2_SWR[17]) );
AOI22X1TS U2145 ( .A0(n1291), .A1(n1290), .B0(n1302), .B1(n1289), .Y(n1293)
);
OAI211X1TS U2146 ( .A0(n1294), .A1(n1305), .B0(n1293), .C0(n1292), .Y(
sftr_odat_SHT2_SWR[16]) );
AOI22X1TS U2147 ( .A0(n1300), .A1(n1296), .B0(n1508), .B1(n1295), .Y(n1297)
);
OAI211X1TS U2148 ( .A0(n1298), .A1(n1510), .B0(n1297), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[6]) );
AOI22X1TS U2149 ( .A0(n1302), .A1(n1301), .B0(n1300), .B1(n1299), .Y(n1304)
);
OAI211X1TS U2150 ( .A0(n1306), .A1(n1305), .B0(n1304), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[3]) );
OAI211X1TS U2151 ( .A0(n1311), .A1(n1310), .B0(n2214), .C0(n1309), .Y(n1315)
);
INVX2TS U2152 ( .A(n1312), .Y(n1314) );
OAI32X1TS U2153 ( .A0(n1315), .A1(n914), .A2(n1314), .B0(n1313), .B1(n1315),
.Y(n1319) );
OAI211X1TS U2154 ( .A0(n2472), .A1(n1320), .B0(n1319), .C0(n1318), .Y(
LZD_raw_out_EWR[5]) );
NOR2XLTS U2155 ( .A(n914), .B(Raw_mant_NRM_SWR[1]), .Y(n1337) );
INVX2TS U2156 ( .A(n1321), .Y(n1323) );
AOI211X1TS U2157 ( .A0(n1324), .A1(Raw_mant_NRM_SWR[30]), .B0(n1323), .C0(
n1322), .Y(n2213) );
NOR2XLTS U2158 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .Y(
n1327) );
OAI22X1TS U2159 ( .A0(n1327), .A1(n1326), .B0(n2289), .B1(n1325), .Y(n1332)
);
NOR2XLTS U2160 ( .A(Raw_mant_NRM_SWR[26]), .B(Raw_mant_NRM_SWR[25]), .Y(
n1330) );
OAI21XLTS U2161 ( .A0(n1330), .A1(n1329), .B0(n1328), .Y(n1331) );
NOR4X1TS U2162 ( .A(n1334), .B(n1333), .C(n1332), .D(n1331), .Y(n1335) );
OAI211X1TS U2163 ( .A0(n1337), .A1(n1336), .B0(n2213), .C0(n1335), .Y(
LZD_raw_out_EWR[4]) );
NAND2X1TS U2164 ( .A(n1379), .B(Raw_mant_NRM_SWR[0]), .Y(n1338) );
AND3X1TS U2165 ( .A(n1339), .B(Shift_reg_FLAGS_7[1]), .C(n1338), .Y(n2182)
);
AOI22X2TS U2166 ( .A0(n1379), .A1(LZD_raw_out_EWR[1]), .B0(
Shift_amount_SHT1_EWR[1]), .B1(n915), .Y(n2196) );
OAI22X2TS U2167 ( .A0(Shift_reg_FLAGS_7[1]), .A1(Shift_amount_SHT1_EWR[0]),
.B0(LZD_raw_out_EWR[0]), .B1(n836), .Y(n2185) );
INVX2TS U2168 ( .A(n2196), .Y(n2191) );
AOI22X1TS U2169 ( .A0(n1379), .A1(n895), .B0(Raw_mant_NRM_SWR[1]), .B1(n1342), .Y(n1418) );
AOI22X1TS U2170 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n1379), .B0(
DmP_mant_SHT1_SW[1]), .B1(n915), .Y(n1340) );
INVX2TS U2171 ( .A(n2185), .Y(n2187) );
AOI22X1TS U2172 ( .A0(n860), .A1(n1373), .B0(n886), .B1(n1379), .Y(n1341) );
AOI222X4TS U2173 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[10]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[42]), .C0(Raw_mant_NRM_SWR[12]), .C1(n2533), .Y(n1497) );
AOI22X1TS U2174 ( .A0(n2533), .A1(Raw_mant_NRM_SWR[15]), .B0(
DmP_mant_SHT1_SW[13]), .B1(n915), .Y(n1343) );
AOI222X4TS U2175 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[12]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[40]), .C0(Raw_mant_NRM_SWR[14]), .C1(n2533), .Y(n1496) );
AOI222X4TS U2176 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[11]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[41]), .C0(Raw_mant_NRM_SWR[13]), .C1(n1342), .Y(n1498) );
OAI22X1TS U2177 ( .A0(n1496), .A1(n2183), .B0(n1498), .B1(n2195), .Y(n1344)
);
AOI21X1TS U2178 ( .A0(n1373), .A1(n1493), .B0(n1344), .Y(n1345) );
AOI222X4TS U2179 ( .A0(n915), .A1(DmP_mant_SHT1_SW[2]), .B0(n2221), .B1(
Raw_mant_NRM_SWR[50]), .C0(Raw_mant_NRM_SWR[4]), .C1(n1342), .Y(n1489)
);
AOI22X1TS U2180 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[7]), .B0(
DmP_mant_SHT1_SW[5]), .B1(n2532), .Y(n1346) );
AOI222X4TS U2181 ( .A0(n2532), .A1(DmP_mant_SHT1_SW[4]), .B0(
Raw_mant_NRM_SWR[6]), .B1(n1342), .C0(Raw_mant_NRM_SWR[48]), .C1(n2221), .Y(n1485) );
AOI222X4TS U2182 ( .A0(n915), .A1(DmP_mant_SHT1_SW[3]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2533), .C0(Raw_mant_NRM_SWR[49]), .C1(n2221), .Y(n1484) );
OAI22X1TS U2183 ( .A0(n1485), .A1(n2183), .B0(n1484), .B1(n2195), .Y(n1347)
);
AOI21X1TS U2184 ( .A0(n1373), .A1(n1482), .B0(n1347), .Y(n1348) );
AOI222X4TS U2185 ( .A0(n915), .A1(DmP_mant_SHT1_SW[14]), .B0(
Raw_mant_NRM_SWR[16]), .B1(n2533), .C0(Raw_mant_NRM_SWR[38]), .C1(
n2221), .Y(n1490) );
AOI22X1TS U2186 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[19]), .B0(
DmP_mant_SHT1_SW[17]), .B1(n2532), .Y(n1349) );
AOI222X4TS U2187 ( .A0(n2532), .A1(DmP_mant_SHT1_SW[16]), .B0(
Raw_mant_NRM_SWR[18]), .B1(n2533), .C0(Raw_mant_NRM_SWR[36]), .C1(
n2221), .Y(n1468) );
AOI222X4TS U2188 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[15]), .B0(
Raw_mant_NRM_SWR[17]), .B1(n1342), .C0(Raw_mant_NRM_SWR[37]), .C1(
n2221), .Y(n1491) );
OAI22X1TS U2189 ( .A0(n1468), .A1(n2189), .B0(n1491), .B1(n2195), .Y(n1350)
);
AOI21X1TS U2190 ( .A0(n1373), .A1(n1471), .B0(n1350), .Y(n1351) );
AOI222X4TS U2191 ( .A0(n915), .A1(DmP_mant_SHT1_SW[6]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[46]), .C0(n882), .C1(n2533), .Y(n1479) );
AOI22X1TS U2192 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n1379), .B0(
DmP_mant_SHT1_SW[9]), .B1(n915), .Y(n1352) );
AOI222X4TS U2193 ( .A0(n915), .A1(DmP_mant_SHT1_SW[8]), .B0(n2221), .B1(n913), .C0(Raw_mant_NRM_SWR[10]), .C1(n1342), .Y(n1502) );
AOI222X4TS U2194 ( .A0(n915), .A1(DmP_mant_SHT1_SW[7]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1342), .C0(Raw_mant_NRM_SWR[45]), .C1(n2221), .Y(n1480) );
OAI22X1TS U2195 ( .A0(n1502), .A1(n2189), .B0(n1480), .B1(n1488), .Y(n1353)
);
AOI21X1TS U2196 ( .A0(n1373), .A1(n1500), .B0(n1353), .Y(n1354) );
AOI22X1TS U2197 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[23]), .B0(
DmP_mant_SHT1_SW[21]), .B1(n2532), .Y(n1355) );
AOI222X4TS U2198 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[23]), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1342), .C0(Raw_mant_NRM_SWR[29]), .C1(
n2221), .Y(n2194) );
AOI222X4TS U2199 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[22]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1342), .C0(Raw_mant_NRM_SWR[30]), .C1(
n2221), .Y(n2198) );
OAI22X1TS U2200 ( .A0(n2194), .A1(n2189), .B0(n2198), .B1(n1488), .Y(n1356)
);
AOI21X1TS U2201 ( .A0(n1466), .A1(n1437), .B0(n1356), .Y(n1357) );
AOI22X1TS U2202 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[31]), .B0(
DmP_mant_SHT1_SW[29]), .B1(n915), .Y(n1358) );
AOI222X4TS U2203 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[28]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[24]), .C0(Raw_mant_NRM_SWR[30]), .C1(n2533), .Y(n2184) );
AOI222X4TS U2204 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[27]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[25]), .C0(Raw_mant_NRM_SWR[29]), .C1(n2533), .Y(n2190) );
OAI22X1TS U2205 ( .A0(n2184), .A1(n2183), .B0(n2190), .B1(n1488), .Y(n1359)
);
AOI21X1TS U2206 ( .A0(n1373), .A1(n1456), .B0(n1359), .Y(n1360) );
AOI222X4TS U2207 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[42]), .B0(n913), .B1(
n2533), .C0(Raw_mant_NRM_SWR[10]), .C1(n2221), .Y(n1412) );
AOI22X1TS U2208 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1379), .B0(
DmP_mant_SHT1_SW[45]), .B1(n915), .Y(n1361) );
AOI222X4TS U2209 ( .A0(n915), .A1(DmP_mant_SHT1_SW[44]), .B0(
Raw_mant_NRM_SWR[46]), .B1(n2533), .C0(n882), .C1(n2221), .Y(n1408) );
AOI222X4TS U2210 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[43]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[9]), .C0(Raw_mant_NRM_SWR[45]), .C1(n1342), .Y(n1407)
);
OAI22X1TS U2211 ( .A0(n1408), .A1(n2183), .B0(n1407), .B1(n1488), .Y(n1363)
);
AOI21X1TS U2212 ( .A0(n1373), .A1(n1405), .B0(n1363), .Y(n1364) );
AOI222X4TS U2213 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[30]), .B0(
Raw_mant_NRM_SWR[32]), .B1(n2533), .C0(n894), .C1(n2221), .Y(n1454) );
AOI22X1TS U2214 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1379), .B0(
DmP_mant_SHT1_SW[33]), .B1(n2532), .Y(n1365) );
AOI222X4TS U2215 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[32]), .B0(
Raw_mant_NRM_SWR[34]), .B1(n1342), .C0(Raw_mant_NRM_SWR[20]), .C1(
n2221), .Y(n1446) );
AOI222X4TS U2216 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[31]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[21]), .C0(Raw_mant_NRM_SWR[33]), .C1(n2533), .Y(n1432) );
OAI22X1TS U2217 ( .A0(n1446), .A1(n2183), .B0(n1432), .B1(n1488), .Y(n1367)
);
AOI21X1TS U2218 ( .A0(n1373), .A1(n1443), .B0(n1367), .Y(n1368) );
AOI222X4TS U2219 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[46]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[6]), .C0(Raw_mant_NRM_SWR[48]), .C1(n1342), .Y(n1403)
);
AOI22X1TS U2220 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[51]), .B0(
DmP_mant_SHT1_SW[49]), .B1(n915), .Y(n1369) );
AOI222X4TS U2221 ( .A0(n915), .A1(DmP_mant_SHT1_SW[48]), .B0(
Raw_mant_NRM_SWR[50]), .B1(n2533), .C0(Raw_mant_NRM_SWR[4]), .C1(n2221), .Y(n1402) );
AOI222X4TS U2222 ( .A0(n915), .A1(DmP_mant_SHT1_SW[47]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[5]), .C0(Raw_mant_NRM_SWR[49]), .C1(n1342), .Y(n1397)
);
OAI22X1TS U2223 ( .A0(n1402), .A1(n2189), .B0(n1397), .B1(n1488), .Y(n1370)
);
AOI21X1TS U2224 ( .A0(n1373), .A1(n1414), .B0(n1370), .Y(n1371) );
AOI222X4TS U2225 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[18]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[34]), .C0(Raw_mant_NRM_SWR[20]), .C1(n2533), .Y(n1469) );
AOI222X4TS U2226 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[20]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[32]), .C0(n894), .C1(n1342), .Y(n1435) );
AOI222X4TS U2227 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[19]), .B0(
Raw_mant_NRM_SWR[21]), .B1(n1342), .C0(Raw_mant_NRM_SWR[33]), .C1(
n2221), .Y(n1439) );
OAI22X1TS U2228 ( .A0(n1435), .A1(n2189), .B0(n1439), .B1(n1488), .Y(n1372)
);
AOI21X1TS U2229 ( .A0(n1373), .A1(n1437), .B0(n1372), .Y(n1374) );
AOI222X4TS U2230 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[38]), .B0(
Raw_mant_NRM_SWR[40]), .B1(n1342), .C0(Raw_mant_NRM_SWR[14]), .C1(
n2221), .Y(n1452) );
AOI22X1TS U2231 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[43]), .B0(
DmP_mant_SHT1_SW[41]), .B1(n2532), .Y(n1375) );
AOI222X4TS U2232 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[40]), .B0(
Raw_mant_NRM_SWR[42]), .B1(n2533), .C0(Raw_mant_NRM_SWR[12]), .C1(
n2221), .Y(n1448) );
AOI222X4TS U2233 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[39]), .B0(
Raw_mant_NRM_SWR[41]), .B1(n2533), .C0(Raw_mant_NRM_SWR[13]), .C1(
n2221), .Y(n1447) );
OAI22X1TS U2234 ( .A0(n1448), .A1(n2189), .B0(n1447), .B1(n1488), .Y(n1376)
);
AOI21X1TS U2235 ( .A0(n1373), .A1(n1410), .B0(n1376), .Y(n1377) );
AOI222X4TS U2236 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[34]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[18]), .C0(Raw_mant_NRM_SWR[36]), .C1(n2533), .Y(n1440) );
AOI22X1TS U2237 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[39]), .B0(
DmP_mant_SHT1_SW[37]), .B1(n2532), .Y(n1378) );
AOI222X4TS U2238 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[35]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[17]), .C0(Raw_mant_NRM_SWR[37]), .C1(n2533), .Y(n1441) );
OAI22X1TS U2239 ( .A0(n1427), .A1(n2189), .B0(n1441), .B1(n1488), .Y(n1381)
);
AOI21X1TS U2240 ( .A0(n1373), .A1(n1450), .B0(n1381), .Y(n1382) );
OAI22X1TS U2241 ( .A0(n1402), .A1(n835), .B0(n1397), .B1(n2183), .Y(n1383)
);
AOI21X1TS U2242 ( .A0(n1466), .A1(n1405), .B0(n1383), .Y(n1384) );
OAI22X1TS U2243 ( .A0(n1412), .A1(n835), .B0(n1448), .B1(n2195), .Y(n1386)
);
AOI21X1TS U2244 ( .A0(n1385), .A1(n1410), .B0(n1386), .Y(n1387) );
OAI22X1TS U2245 ( .A0(n1452), .A1(n835), .B0(n1427), .B1(n1488), .Y(n1388)
);
AOI21X1TS U2246 ( .A0(n1385), .A1(n1450), .B0(n1388), .Y(n1389) );
OAI22X1TS U2247 ( .A0(n1447), .A1(n835), .B0(n1452), .B1(n2183), .Y(n1391)
);
AOI21X1TS U2248 ( .A0(n1390), .A1(n1450), .B0(n1391), .Y(n1392) );
AOI222X4TS U2249 ( .A0(n915), .A1(DmP_mant_SHT1_SW[50]), .B0(
Raw_mant_NRM_SWR[52]), .B1(n2533), .C0(n914), .C1(n2221), .Y(n2180) );
OAI22X1TS U2250 ( .A0(n2180), .A1(n835), .B0(n1402), .B1(n2195), .Y(n1393)
);
AOI21X1TS U2251 ( .A0(n1385), .A1(n1414), .B0(n1393), .Y(n1394) );
OAI22X1TS U2252 ( .A0(n1407), .A1(n835), .B0(n1412), .B1(n2183), .Y(n1395)
);
AOI21X1TS U2253 ( .A0(n1390), .A1(n1410), .B0(n1395), .Y(n1396) );
OAI22X1TS U2254 ( .A0(n1397), .A1(n835), .B0(n1403), .B1(n2183), .Y(n1398)
);
AOI21X1TS U2255 ( .A0(n1390), .A1(n1405), .B0(n1398), .Y(n1399) );
AOI222X4TS U2256 ( .A0(n915), .A1(DmP_mant_SHT1_SW[51]), .B0(n895), .B1(
n2533), .C0(Raw_mant_NRM_SWR[1]), .C1(n2221), .Y(n2181) );
OAI22X1TS U2257 ( .A0(n2181), .A1(n835), .B0(n2180), .B1(n2183), .Y(n1400)
);
AOI21X1TS U2258 ( .A0(n1390), .A1(n1414), .B0(n1400), .Y(n1401) );
OAI22X1TS U2259 ( .A0(n1403), .A1(n835), .B0(n1408), .B1(n1488), .Y(n1404)
);
AOI21X1TS U2260 ( .A0(n1385), .A1(n1405), .B0(n1404), .Y(n1406) );
OAI22X1TS U2261 ( .A0(n1408), .A1(n835), .B0(n1407), .B1(n2183), .Y(n1409)
);
AOI21X1TS U2262 ( .A0(n1466), .A1(n1410), .B0(n1409), .Y(n1411) );
INVX4TS U2263 ( .A(n1373), .Y(n1453) );
OAI22X1TS U2264 ( .A0(n2180), .A1(n2195), .B0(n2181), .B1(n2189), .Y(n1413)
);
AOI21X1TS U2265 ( .A0(n1466), .A1(n1414), .B0(n1413), .Y(n1415) );
OAI22X1TS U2266 ( .A0(n1489), .A1(n1453), .B0(n1460), .B1(n1488), .Y(n1416)
);
AOI21X1TS U2267 ( .A0(n1385), .A1(n860), .B0(n1416), .Y(n1417) );
OAI22X1TS U2268 ( .A0(n1440), .A1(n1453), .B0(n1446), .B1(n1488), .Y(n1419)
);
AOI21X1TS U2269 ( .A0(n1385), .A1(n1443), .B0(n1419), .Y(n1420) );
OAI22X1TS U2270 ( .A0(n2194), .A1(n1453), .B0(n2198), .B1(n2183), .Y(n1421)
);
AOI21X1TS U2271 ( .A0(n1390), .A1(n1437), .B0(n1421), .Y(n1422) );
OAI22X1TS U2272 ( .A0(n1446), .A1(n835), .B0(n1432), .B1(n2183), .Y(n1423)
);
AOI21X1TS U2273 ( .A0(n1466), .A1(n1456), .B0(n1423), .Y(n1424) );
OAI22X1TS U2274 ( .A0(n1435), .A1(n1453), .B0(n1439), .B1(n2183), .Y(n1425)
);
AOI21X1TS U2275 ( .A0(n1466), .A1(n1471), .B0(n1425), .Y(n1426) );
OAI22X1TS U2276 ( .A0(n1427), .A1(n835), .B0(n1441), .B1(n2183), .Y(n1428)
);
AOI21X1TS U2277 ( .A0(n1466), .A1(n1443), .B0(n1428), .Y(n1429) );
OAI22X1TS U2278 ( .A0(n1439), .A1(n1453), .B0(n1469), .B1(n2189), .Y(n1430)
);
AOI21X1TS U2279 ( .A0(n1390), .A1(n1471), .B0(n1430), .Y(n1431) );
OAI22X1TS U2280 ( .A0(n1432), .A1(n1453), .B0(n1454), .B1(n2183), .Y(n1433)
);
AOI21X1TS U2281 ( .A0(n1390), .A1(n1456), .B0(n1433), .Y(n1434) );
OAI22X1TS U2282 ( .A0(n2198), .A1(n1453), .B0(n1435), .B1(n1488), .Y(n1436)
);
AOI21X1TS U2283 ( .A0(n1385), .A1(n1437), .B0(n1436), .Y(n1438) );
OAI22X1TS U2284 ( .A0(n1441), .A1(n1453), .B0(n1440), .B1(n2183), .Y(n1442)
);
AOI21X1TS U2285 ( .A0(n1390), .A1(n1443), .B0(n1442), .Y(n1444) );
OAI22X1TS U2286 ( .A0(n1448), .A1(n1453), .B0(n1447), .B1(n2183), .Y(n1449)
);
AOI21X1TS U2287 ( .A0(n1466), .A1(n1450), .B0(n1449), .Y(n1451) );
OAI22X1TS U2288 ( .A0(n1454), .A1(n1453), .B0(n2184), .B1(n1488), .Y(n1455)
);
AOI21X1TS U2289 ( .A0(n1385), .A1(n1456), .B0(n1455), .Y(n1457) );
OAI22X1TS U2290 ( .A0(n1484), .A1(n1453), .B0(n1489), .B1(n2189), .Y(n1458)
);
AOI21X1TS U2291 ( .A0(n1390), .A1(n860), .B0(n1458), .Y(n1459) );
OAI22X1TS U2292 ( .A0(n1497), .A1(n835), .B0(n1502), .B1(n1488), .Y(n1461)
);
AOI21X1TS U2293 ( .A0(n1385), .A1(n1500), .B0(n1461), .Y(n1462) );
OAI22X1TS U2294 ( .A0(n1502), .A1(n835), .B0(n1480), .B1(n2189), .Y(n1463)
);
AOI21X1TS U2295 ( .A0(n1466), .A1(n1482), .B0(n1463), .Y(n1464) );
OAI22X1TS U2296 ( .A0(n1468), .A1(n835), .B0(n1491), .B1(n2189), .Y(n1465)
);
AOI21X1TS U2297 ( .A0(n1466), .A1(n1493), .B0(n1465), .Y(n1467) );
OAI22X1TS U2298 ( .A0(n1469), .A1(n835), .B0(n1468), .B1(n1488), .Y(n1470)
);
AOI21X1TS U2299 ( .A0(n1385), .A1(n1471), .B0(n1470), .Y(n1472) );
OAI22X1TS U2300 ( .A0(n1490), .A1(n835), .B0(n1496), .B1(n1488), .Y(n1473)
);
AOI21X1TS U2301 ( .A0(n1385), .A1(n1493), .B0(n1473), .Y(n1474) );
OAI22X1TS U2302 ( .A0(n1479), .A1(n1453), .B0(n1485), .B1(n2195), .Y(n1475)
);
AOI21X1TS U2303 ( .A0(n1385), .A1(n1482), .B0(n1475), .Y(n1476) );
OAI22X1TS U2304 ( .A0(n1496), .A1(n1453), .B0(n1498), .B1(n2189), .Y(n1477)
);
AOI21X1TS U2305 ( .A0(n1466), .A1(n1500), .B0(n1477), .Y(n1478) );
OAI22X1TS U2306 ( .A0(n1480), .A1(n835), .B0(n1479), .B1(n2189), .Y(n1481)
);
AOI21X1TS U2307 ( .A0(n1390), .A1(n1482), .B0(n1481), .Y(n1483) );
OAI22X1TS U2308 ( .A0(n1485), .A1(n1453), .B0(n1484), .B1(n2189), .Y(n1486)
);
AOI21X1TS U2309 ( .A0(n1466), .A1(n860), .B0(n1486), .Y(n1487) );
OAI22X1TS U2310 ( .A0(n1491), .A1(n835), .B0(n1490), .B1(n2189), .Y(n1492)
);
AOI21X1TS U2311 ( .A0(n1390), .A1(n1493), .B0(n1492), .Y(n1494) );
OAI22X1TS U2312 ( .A0(n1498), .A1(n1453), .B0(n1497), .B1(n2189), .Y(n1499)
);
AOI21X1TS U2313 ( .A0(n1390), .A1(n1500), .B0(n1499), .Y(n1501) );
NOR2BX1TS U2314 ( .AN(LZD_output_NRM2_EW[5]), .B(ADD_OVRFLW_NRM2), .Y(n1503)
);
XOR2X1TS U2315 ( .A(n2244), .B(n1503), .Y(DP_OP_15J206_122_2221_n17) );
NAND2X1TS U2316 ( .A(n1508), .B(n1504), .Y(n1505) );
OAI211X1TS U2317 ( .A0(n1506), .A1(n1510), .B0(n1505), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[4]) );
NAND2X1TS U2318 ( .A(n1508), .B(n1507), .Y(n1509) );
OAI211X1TS U2319 ( .A0(n1511), .A1(n1510), .B0(n1509), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[2]) );
NOR2BX1TS U2320 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n1512)
);
XOR2X1TS U2321 ( .A(n2244), .B(n1512), .Y(DP_OP_15J206_122_2221_n18) );
NOR2BX1TS U2322 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n1513)
);
XOR2X1TS U2323 ( .A(n2244), .B(n1513), .Y(DP_OP_15J206_122_2221_n19) );
NOR2BX1TS U2324 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n1514)
);
XOR2X1TS U2325 ( .A(n2244), .B(n1514), .Y(DP_OP_15J206_122_2221_n20) );
NOR2BX1TS U2326 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n1515)
);
XOR2X1TS U2327 ( .A(n2244), .B(n1515), .Y(DP_OP_15J206_122_2221_n21) );
OR2X1TS U2328 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n1516) );
XOR2X1TS U2329 ( .A(n2244), .B(n1516), .Y(DP_OP_15J206_122_2221_n22) );
AOI22X1TS U2330 ( .A0(n1519), .A1(n1518), .B0(n986), .B1(n1517), .Y(n1520)
);
NAND2X1TS U2331 ( .A(n1521), .B(n1520), .Y(sftr_odat_SHT2_SWR[27]) );
NAND2X1TS U2332 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n1935) );
NAND2X1TS U2333 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n1522) );
AOI2BB2X1TS U2334 ( .B0(n1935), .B1(n1522), .A0N(DMP_SFG[1]), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1920) );
AOI21X1TS U2335 ( .A0(DMP_SFG[19]), .A1(DmP_mant_SFG_SWR[21]), .B0(n1809),
.Y(n1540) );
AOI21X1TS U2336 ( .A0(DMP_SFG[21]), .A1(DmP_mant_SFG_SWR[23]), .B0(n1796),
.Y(n1542) );
AOI21X1TS U2337 ( .A0(DMP_SFG[23]), .A1(DmP_mant_SFG_SWR[25]), .B0(n1783),
.Y(n1544) );
AOI21X1TS U2338 ( .A0(DMP_SFG[25]), .A1(DmP_mant_SFG_SWR[27]), .B0(n1770),
.Y(n1546) );
AOI21X1TS U2339 ( .A0(DMP_SFG[27]), .A1(DmP_mant_SFG_SWR[29]), .B0(n1756),
.Y(n1548) );
AOI2BB1X2TS U2340 ( .A0N(DMP_SFG[27]), .A1N(DmP_mant_SFG_SWR[29]), .B0(n1548), .Y(n1750) );
AOI2BB1X2TS U2341 ( .A0N(DMP_SFG[29]), .A1N(DmP_mant_SFG_SWR[31]), .B0(n1550), .Y(n1737) );
AOI2BB1X2TS U2342 ( .A0N(DMP_SFG[31]), .A1N(DmP_mant_SFG_SWR[33]), .B0(n1552), .Y(n1724) );
AOI2BB1X2TS U2343 ( .A0N(DMP_SFG[33]), .A1N(DmP_mant_SFG_SWR[35]), .B0(n1554), .Y(n1711) );
OAI21X2TS U2344 ( .A0(DmP_mant_SFG_SWR[36]), .A1(DMP_SFG[34]), .B0(n1711),
.Y(n1555) );
OAI21X2TS U2345 ( .A0(n2242), .A1(n2309), .B0(n1555), .Y(n1704) );
AOI21X1TS U2346 ( .A0(DMP_SFG[35]), .A1(DmP_mant_SFG_SWR[37]), .B0(n1704),
.Y(n1556) );
AOI2BB1X2TS U2347 ( .A0N(DMP_SFG[35]), .A1N(DmP_mant_SFG_SWR[37]), .B0(n1556), .Y(n1620) );
OAI21X2TS U2348 ( .A0(DmP_mant_SFG_SWR[38]), .A1(DMP_SFG[36]), .B0(n1620),
.Y(n1557) );
AOI2BB1X2TS U2349 ( .A0N(DMP_SFG[39]), .A1N(DmP_mant_SFG_SWR[41]), .B0(n1560), .Y(n1679) );
AOI21X2TS U2350 ( .A0(DMP_SFG[41]), .A1(DmP_mant_SFG_SWR[43]), .B0(n1672),
.Y(n1562) );
AOI2BB1X2TS U2351 ( .A0N(DMP_SFG[41]), .A1N(DmP_mant_SFG_SWR[43]), .B0(n1562), .Y(n1666) );
OAI21X2TS U2352 ( .A0(DmP_mant_SFG_SWR[44]), .A1(DMP_SFG[42]), .B0(n1666),
.Y(n1563) );
AOI21X2TS U2353 ( .A0(DMP_SFG[45]), .A1(DmP_mant_SFG_SWR[47]), .B0(n1646),
.Y(n1566) );
AOI2BB1X2TS U2354 ( .A0N(DMP_SFG[45]), .A1N(DmP_mant_SFG_SWR[47]), .B0(n1566), .Y(n1640) );
OAI21X2TS U2355 ( .A0(DmP_mant_SFG_SWR[48]), .A1(DMP_SFG[46]), .B0(n1640),
.Y(n1567) );
AOI21X2TS U2356 ( .A0(DMP_SFG[47]), .A1(DmP_mant_SFG_SWR[49]), .B0(n1633),
.Y(n1568) );
AOI21X1TS U2357 ( .A0(DMP_SFG[49]), .A1(DmP_mant_SFG_SWR[51]), .B0(n1597),
.Y(n1570) );
OAI21X1TS U2358 ( .A0(DmP_mant_SFG_SWR[52]), .A1(DMP_SFG[50]), .B0(n1603),
.Y(n1571) );
AOI21X1TS U2359 ( .A0(DmP_mant_SFG_SWR[53]), .A1(n893), .B0(n1613), .Y(n1572) );
OA21XLTS U2360 ( .A0(n1609), .A1(DmP_mant_SFG_SWR[54]), .B0(n1922), .Y(
ADD_OVRFLW_SGF) );
NOR2X1TS U2361 ( .A(N94), .B(N95), .Y(n1933) );
AOI21X1TS U2362 ( .A0(DMP_SFG[0]), .A1(n2291), .B0(n1933), .Y(n1573) );
AOI21X1TS U2363 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n2292), .B0(n1573), .Y(n1928) );
NOR2X1TS U2364 ( .A(n2296), .B(DmP_mant_SFG_SWR[3]), .Y(n1929) );
NAND2X1TS U2365 ( .A(DmP_mant_SFG_SWR[4]), .B(n2276), .Y(n1925) );
NOR2X1TS U2366 ( .A(DmP_mant_SFG_SWR[4]), .B(n2276), .Y(n1924) );
AOI21X1TS U2367 ( .A0(n1923), .A1(n1925), .B0(n1924), .Y(n1914) );
NOR2X1TS U2368 ( .A(n2295), .B(DMP_SFG[3]), .Y(n1915) );
NOR2X1TS U2369 ( .A(n2294), .B(DmP_mant_SFG_SWR[5]), .Y(n1916) );
INVX2TS U2370 ( .A(n1916), .Y(n1574) );
OAI21X1TS U2371 ( .A0(n1914), .A1(n1915), .B0(n1574), .Y(n1908) );
NAND2X1TS U2372 ( .A(DmP_mant_SFG_SWR[6]), .B(n2227), .Y(n1910) );
NOR2X1TS U2373 ( .A(DmP_mant_SFG_SWR[6]), .B(n2227), .Y(n1909) );
AOI21X1TS U2374 ( .A0(n1908), .A1(n1910), .B0(n1909), .Y(n1901) );
NOR2X1TS U2375 ( .A(n2298), .B(DMP_SFG[5]), .Y(n1902) );
NOR2X1TS U2376 ( .A(n2297), .B(DmP_mant_SFG_SWR[7]), .Y(n1903) );
INVX2TS U2377 ( .A(n1903), .Y(n1575) );
OAI21X1TS U2378 ( .A0(n1901), .A1(n1902), .B0(n1575), .Y(n1895) );
NAND2X1TS U2379 ( .A(DmP_mant_SFG_SWR[8]), .B(n2278), .Y(n1897) );
NOR2X1TS U2380 ( .A(DmP_mant_SFG_SWR[8]), .B(n2278), .Y(n1896) );
AOI21X1TS U2381 ( .A0(n1895), .A1(n1897), .B0(n1896), .Y(n1888) );
NOR2X1TS U2382 ( .A(n2301), .B(DMP_SFG[7]), .Y(n1889) );
NOR2X1TS U2383 ( .A(n2300), .B(DmP_mant_SFG_SWR[9]), .Y(n1890) );
INVX2TS U2384 ( .A(n1890), .Y(n1576) );
OAI21X1TS U2385 ( .A0(n1888), .A1(n1889), .B0(n1576), .Y(n1882) );
NAND2X1TS U2386 ( .A(DmP_mant_SFG_SWR[10]), .B(n2279), .Y(n1884) );
NOR2X1TS U2387 ( .A(DmP_mant_SFG_SWR[10]), .B(n2279), .Y(n1883) );
AOI21X1TS U2388 ( .A0(n1882), .A1(n1884), .B0(n1883), .Y(n1875) );
NOR2X1TS U2389 ( .A(n2304), .B(DMP_SFG[9]), .Y(n1876) );
NOR2X1TS U2390 ( .A(n2302), .B(DmP_mant_SFG_SWR[11]), .Y(n1877) );
INVX2TS U2391 ( .A(n1877), .Y(n1577) );
OAI21X1TS U2392 ( .A0(n1875), .A1(n1876), .B0(n1577), .Y(n1869) );
NAND2X1TS U2393 ( .A(DmP_mant_SFG_SWR[12]), .B(n2230), .Y(n1871) );
NOR2X1TS U2394 ( .A(DmP_mant_SFG_SWR[12]), .B(n2230), .Y(n1870) );
AOI21X1TS U2395 ( .A0(n1869), .A1(n1871), .B0(n1870), .Y(n1861) );
NOR2X1TS U2396 ( .A(n2305), .B(DMP_SFG[11]), .Y(n1863) );
NOR2X1TS U2397 ( .A(n2303), .B(DmP_mant_SFG_SWR[13]), .Y(n1864) );
INVX2TS U2398 ( .A(n1864), .Y(n1578) );
OAI21X1TS U2399 ( .A0(n1861), .A1(n1863), .B0(n1578), .Y(n1854) );
NAND2X1TS U2400 ( .A(DmP_mant_SFG_SWR[14]), .B(n2281), .Y(n1857) );
NOR2X1TS U2401 ( .A(DmP_mant_SFG_SWR[14]), .B(n2281), .Y(n1858) );
AOI21X1TS U2402 ( .A0(n1854), .A1(n1857), .B0(n1858), .Y(n1848) );
NOR2X1TS U2403 ( .A(n2308), .B(DMP_SFG[13]), .Y(n1850) );
NOR2X1TS U2404 ( .A(n2307), .B(DmP_mant_SFG_SWR[15]), .Y(n1851) );
INVX2TS U2405 ( .A(n1851), .Y(n1579) );
OAI21X1TS U2406 ( .A0(n1848), .A1(n1850), .B0(n1579), .Y(n1841) );
NAND2X1TS U2407 ( .A(DmP_mant_SFG_SWR[16]), .B(n2282), .Y(n1844) );
NOR2X1TS U2408 ( .A(DmP_mant_SFG_SWR[16]), .B(n2282), .Y(n1845) );
AOI21X1TS U2409 ( .A0(n1841), .A1(n1844), .B0(n1845), .Y(n1835) );
NOR2X1TS U2410 ( .A(n2311), .B(DMP_SFG[15]), .Y(n1837) );
NOR2X1TS U2411 ( .A(n2310), .B(DmP_mant_SFG_SWR[17]), .Y(n1838) );
INVX2TS U2412 ( .A(n1838), .Y(n1580) );
OAI21X1TS U2413 ( .A0(n1835), .A1(n1837), .B0(n1580), .Y(n1828) );
NAND2X1TS U2414 ( .A(DmP_mant_SFG_SWR[18]), .B(n2233), .Y(n1831) );
NOR2X1TS U2415 ( .A(DmP_mant_SFG_SWR[18]), .B(n2233), .Y(n1832) );
AOI21X1TS U2416 ( .A0(n1828), .A1(n1831), .B0(n1832), .Y(n1822) );
NOR2X1TS U2417 ( .A(n2315), .B(DMP_SFG[17]), .Y(n1824) );
NOR2X1TS U2418 ( .A(n2313), .B(DmP_mant_SFG_SWR[19]), .Y(n1825) );
INVX2TS U2419 ( .A(n1825), .Y(n1581) );
OAI21X1TS U2420 ( .A0(n1822), .A1(n1824), .B0(n1581), .Y(n1814) );
NAND2X1TS U2421 ( .A(DmP_mant_SFG_SWR[20]), .B(n2284), .Y(n1817) );
NOR2X1TS U2422 ( .A(DmP_mant_SFG_SWR[20]), .B(n2284), .Y(n1818) );
NOR2X1TS U2423 ( .A(n2316), .B(DMP_SFG[19]), .Y(n1810) );
NOR2X1TS U2424 ( .A(n2314), .B(DmP_mant_SFG_SWR[21]), .Y(n1811) );
INVX2TS U2425 ( .A(n1811), .Y(n1582) );
OAI21X1TS U2426 ( .A0(n1808), .A1(n1810), .B0(n1582), .Y(n1801) );
NAND2X1TS U2427 ( .A(DmP_mant_SFG_SWR[22]), .B(n2286), .Y(n1804) );
NOR2X1TS U2428 ( .A(DmP_mant_SFG_SWR[22]), .B(n2286), .Y(n1805) );
NOR2X1TS U2429 ( .A(n2319), .B(DMP_SFG[21]), .Y(n1797) );
NOR2X1TS U2430 ( .A(n2318), .B(DmP_mant_SFG_SWR[23]), .Y(n1798) );
INVX2TS U2431 ( .A(n1798), .Y(n1583) );
NAND2X1TS U2432 ( .A(DmP_mant_SFG_SWR[24]), .B(n2236), .Y(n1791) );
NOR2X1TS U2433 ( .A(DmP_mant_SFG_SWR[24]), .B(n2236), .Y(n1792) );
NOR2X1TS U2434 ( .A(n2322), .B(DMP_SFG[23]), .Y(n1784) );
NOR2X1TS U2435 ( .A(n2321), .B(DmP_mant_SFG_SWR[25]), .Y(n1785) );
NOR2X1TS U2436 ( .A(DmP_mant_SFG_SWR[26]), .B(n2288), .Y(n1779) );
NOR2X1TS U2437 ( .A(n2326), .B(DMP_SFG[25]), .Y(n1771) );
NOR2X1TS U2438 ( .A(n2324), .B(DmP_mant_SFG_SWR[27]), .Y(n1772) );
NOR2X1TS U2439 ( .A(DmP_mant_SFG_SWR[28]), .B(n2290), .Y(n1765) );
NOR2X1TS U2440 ( .A(n2327), .B(DMP_SFG[27]), .Y(n1757) );
NOR2X1TS U2441 ( .A(n2325), .B(DmP_mant_SFG_SWR[29]), .Y(n1758) );
NOR2X1TS U2442 ( .A(DmP_mant_SFG_SWR[30]), .B(n2239), .Y(n1752) );
NOR2X1TS U2443 ( .A(n2332), .B(DMP_SFG[29]), .Y(n1744) );
NOR2X1TS U2444 ( .A(n2331), .B(DmP_mant_SFG_SWR[31]), .Y(n1745) );
NOR2X1TS U2445 ( .A(DmP_mant_SFG_SWR[32]), .B(n2299), .Y(n1739) );
NOR2X1TS U2446 ( .A(n2340), .B(DMP_SFG[31]), .Y(n1731) );
NOR2X1TS U2447 ( .A(n2339), .B(DmP_mant_SFG_SWR[33]), .Y(n1732) );
NOR2X1TS U2448 ( .A(DmP_mant_SFG_SWR[34]), .B(n2306), .Y(n1726) );
NOR2X1TS U2449 ( .A(n2347), .B(DMP_SFG[33]), .Y(n1718) );
NOR2X1TS U2450 ( .A(n2345), .B(DmP_mant_SFG_SWR[35]), .Y(n1719) );
NOR2X1TS U2451 ( .A(DmP_mant_SFG_SWR[36]), .B(n2242), .Y(n1713) );
NOR2X1TS U2452 ( .A(n2348), .B(DMP_SFG[35]), .Y(n1705) );
NOR2X1TS U2453 ( .A(n2346), .B(DmP_mant_SFG_SWR[37]), .Y(n1706) );
NOR2X1TS U2454 ( .A(DmP_mant_SFG_SWR[38]), .B(n2317), .Y(n1622) );
NOR2X1TS U2455 ( .A(n2352), .B(DMP_SFG[37]), .Y(n1699) );
NOR2X1TS U2456 ( .A(n2351), .B(DmP_mant_SFG_SWR[39]), .Y(n1700) );
NOR2X1TS U2457 ( .A(DmP_mant_SFG_SWR[40]), .B(n2323), .Y(n1694) );
NOR2X1TS U2458 ( .A(n2358), .B(DMP_SFG[39]), .Y(n1686) );
NOR2X1TS U2459 ( .A(n2357), .B(DmP_mant_SFG_SWR[41]), .Y(n1687) );
OAI21X1TS U2460 ( .A0(n1684), .A1(n1686), .B0(n1592), .Y(n1677) );
NOR2X1TS U2461 ( .A(DmP_mant_SFG_SWR[42]), .B(n2248), .Y(n1681) );
AOI21X1TS U2462 ( .A0(n1677), .A1(n1680), .B0(n1681), .Y(n1671) );
NOR2X1TS U2463 ( .A(n2362), .B(DMP_SFG[41]), .Y(n1673) );
NOR2X1TS U2464 ( .A(n2360), .B(DmP_mant_SFG_SWR[43]), .Y(n1674) );
OAI21X1TS U2465 ( .A0(n1671), .A1(n1673), .B0(n1593), .Y(n1664) );
NOR2X1TS U2466 ( .A(DmP_mant_SFG_SWR[44]), .B(n2343), .Y(n1668) );
AOI21X1TS U2467 ( .A0(n1664), .A1(n1667), .B0(n1668), .Y(n1658) );
NOR2X1TS U2468 ( .A(n2363), .B(DMP_SFG[43]), .Y(n1660) );
NOR2X1TS U2469 ( .A(n2361), .B(DmP_mant_SFG_SWR[45]), .Y(n1661) );
OAI21X1TS U2470 ( .A0(n1658), .A1(n1660), .B0(n1594), .Y(n1651) );
NOR2X1TS U2471 ( .A(DmP_mant_SFG_SWR[46]), .B(n2355), .Y(n1655) );
AOI21X1TS U2472 ( .A0(n1651), .A1(n1654), .B0(n1655), .Y(n1645) );
NOR2X1TS U2473 ( .A(n2366), .B(DMP_SFG[45]), .Y(n1647) );
NOR2X1TS U2474 ( .A(n2365), .B(DmP_mant_SFG_SWR[47]), .Y(n1648) );
OAI21X1TS U2475 ( .A0(n1645), .A1(n1647), .B0(n1595), .Y(n1638) );
NOR2X1TS U2476 ( .A(DmP_mant_SFG_SWR[48]), .B(n2253), .Y(n1642) );
AOI21X1TS U2477 ( .A0(n1638), .A1(n1641), .B0(n1642), .Y(n1632) );
NOR2X1TS U2478 ( .A(n2417), .B(DMP_SFG[47]), .Y(n1634) );
NOR2X1TS U2479 ( .A(n2416), .B(DmP_mant_SFG_SWR[49]), .Y(n1635) );
OAI21X1TS U2480 ( .A0(n1632), .A1(n1634), .B0(n1596), .Y(n1625) );
NOR2X1TS U2481 ( .A(DmP_mant_SFG_SWR[50]), .B(n2415), .Y(n1629) );
AOI21X1TS U2482 ( .A0(n1625), .A1(n1628), .B0(n1629), .Y(n1602) );
MXI2X1TS U2483 ( .A(n1597), .B(n1602), .S0(n1768), .Y(n1599) );
NOR2X1TS U2484 ( .A(n2422), .B(DmP_mant_SFG_SWR[51]), .Y(n1600) );
NOR2X1TS U2485 ( .A(n2423), .B(DMP_SFG[49]), .Y(n1601) );
MXI2X1TS U2486 ( .A(n1603), .B(n1607), .S0(n1768), .Y(n1605) );
XNOR2X1TS U2487 ( .A(n1605), .B(n1604), .Y(Raw_mant_SGF[52]) );
AOI22X1TS U2488 ( .A0(n1607), .A1(n1606), .B0(DmP_mant_SFG_SWR[52]), .B1(
n2420), .Y(n1611) );
NOR2BX1TS U2489 ( .AN(n893), .B(DmP_mant_SFG_SWR[53]), .Y(n1615) );
AOI211X1TS U2490 ( .A0(n1611), .A1(n1614), .B0(n1615), .C0(n1922), .Y(n1608)
);
AOI21X1TS U2491 ( .A0(n1609), .A1(n1922), .B0(n1608), .Y(n1610) );
CLKBUFX2TS U2492 ( .A(n1768), .Y(n1821) );
NAND2X1TS U2493 ( .A(n1611), .B(n1768), .Y(n1612) );
XNOR2X1TS U2494 ( .A(n1617), .B(n1616), .Y(Raw_mant_SGF[53]) );
AOI21X1TS U2495 ( .A0(n1620), .A1(n1922), .B0(n1619), .Y(n1624) );
XNOR2X1TS U2496 ( .A(n1624), .B(n1623), .Y(Raw_mant_SGF[38]) );
NOR2BX1TS U2497 ( .AN(exp_rslt_NRM2_EW1[10]), .B(
array_comparators_GTComparator_N0), .Y(formatted_number_W[62]) );
INVX4TS U2498 ( .A(n1768), .Y(n1934) );
AOI21X1TS U2499 ( .A0(n1627), .A1(n1922), .B0(n1626), .Y(n1631) );
XNOR2X1TS U2500 ( .A(n1631), .B(n1630), .Y(Raw_mant_SGF[50]) );
MXI2X1TS U2501 ( .A(n1633), .B(n1632), .S0(n1768), .Y(n1637) );
AOI21X1TS U2502 ( .A0(n1640), .A1(n1922), .B0(n1639), .Y(n1644) );
XNOR2X1TS U2503 ( .A(n1644), .B(n1643), .Y(Raw_mant_SGF[48]) );
MXI2X1TS U2504 ( .A(n1646), .B(n1645), .S0(n1768), .Y(n1650) );
AOI21X1TS U2505 ( .A0(n1653), .A1(n1922), .B0(n1652), .Y(n1657) );
XNOR2X1TS U2506 ( .A(n1657), .B(n1656), .Y(Raw_mant_SGF[46]) );
MXI2X1TS U2507 ( .A(n1659), .B(n1658), .S0(n1768), .Y(n1663) );
AOI21X1TS U2508 ( .A0(n1666), .A1(n1922), .B0(n1665), .Y(n1670) );
XNOR2X1TS U2509 ( .A(n1670), .B(n1669), .Y(Raw_mant_SGF[44]) );
MXI2X1TS U2510 ( .A(n1672), .B(n1671), .S0(n1768), .Y(n1676) );
NOR2XLTS U2511 ( .A(n1674), .B(n1673), .Y(n1675) );
AOI21X1TS U2512 ( .A0(n1679), .A1(n1922), .B0(n1678), .Y(n1683) );
XNOR2X1TS U2513 ( .A(n1683), .B(n1682), .Y(Raw_mant_SGF[42]) );
MXI2X1TS U2514 ( .A(n1685), .B(n1684), .S0(n1821), .Y(n1689) );
NOR2XLTS U2515 ( .A(n1687), .B(n1686), .Y(n1688) );
AOI21X1TS U2516 ( .A0(n1692), .A1(n1922), .B0(n1691), .Y(n1696) );
XNOR2X1TS U2517 ( .A(n1696), .B(n1695), .Y(Raw_mant_SGF[40]) );
MXI2X1TS U2518 ( .A(n1698), .B(n1697), .S0(n1768), .Y(n1702) );
NOR2XLTS U2519 ( .A(n1700), .B(n1699), .Y(n1701) );
MXI2X1TS U2520 ( .A(n1704), .B(n1703), .S0(n1768), .Y(n1708) );
NOR2XLTS U2521 ( .A(n1706), .B(n1705), .Y(n1707) );
AOI21X1TS U2522 ( .A0(n1711), .A1(n1919), .B0(n1710), .Y(n1715) );
XNOR2X1TS U2523 ( .A(n1715), .B(n1714), .Y(Raw_mant_SGF[36]) );
MXI2X1TS U2524 ( .A(n1717), .B(n1716), .S0(n1821), .Y(n1721) );
NOR2XLTS U2525 ( .A(n1719), .B(n1718), .Y(n1720) );
AOI21X1TS U2526 ( .A0(n1724), .A1(n1922), .B0(n1723), .Y(n1728) );
XNOR2X1TS U2527 ( .A(n1728), .B(n1727), .Y(Raw_mant_SGF[34]) );
MXI2X1TS U2528 ( .A(n1730), .B(n1729), .S0(n1768), .Y(n1734) );
NOR2XLTS U2529 ( .A(n1732), .B(n1731), .Y(n1733) );
AOI21X1TS U2530 ( .A0(n1737), .A1(n1919), .B0(n1736), .Y(n1741) );
XNOR2X1TS U2531 ( .A(n1741), .B(n1740), .Y(Raw_mant_SGF[32]) );
MXI2X1TS U2532 ( .A(n1743), .B(n1742), .S0(n1768), .Y(n1747) );
NOR2XLTS U2533 ( .A(n1745), .B(n1744), .Y(n1746) );
XOR2XLTS U2534 ( .A(n1747), .B(n1746), .Y(Raw_mant_SGF[31]) );
NOR2XLTS U2535 ( .A(n1748), .B(n1919), .Y(n1749) );
AOI21X1TS U2536 ( .A0(n1750), .A1(n1934), .B0(n1749), .Y(n1754) );
XNOR2X1TS U2537 ( .A(n1754), .B(n1753), .Y(Raw_mant_SGF[30]) );
MXI2X1TS U2538 ( .A(n1756), .B(n1755), .S0(n1768), .Y(n1760) );
NOR2XLTS U2539 ( .A(n1758), .B(n1757), .Y(n1759) );
XOR2XLTS U2540 ( .A(n1760), .B(n1759), .Y(Raw_mant_SGF[29]) );
NOR2XLTS U2541 ( .A(n1761), .B(n1919), .Y(n1762) );
AOI21X1TS U2542 ( .A0(n1763), .A1(n1922), .B0(n1762), .Y(n1767) );
XNOR2X1TS U2543 ( .A(n1767), .B(n1766), .Y(Raw_mant_SGF[28]) );
MXI2X1TS U2544 ( .A(n1770), .B(n1769), .S0(n1768), .Y(n1774) );
NOR2XLTS U2545 ( .A(n1772), .B(n1771), .Y(n1773) );
XOR2XLTS U2546 ( .A(n1774), .B(n1773), .Y(Raw_mant_SGF[27]) );
AOI21X1TS U2547 ( .A0(n1777), .A1(n1922), .B0(n1776), .Y(n1781) );
XNOR2X1TS U2548 ( .A(n1781), .B(n1780), .Y(Raw_mant_SGF[26]) );
MXI2X1TS U2549 ( .A(n1783), .B(n1782), .S0(n1768), .Y(n1787) );
NOR2XLTS U2550 ( .A(n1785), .B(n1784), .Y(n1786) );
XOR2XLTS U2551 ( .A(n1787), .B(n1786), .Y(Raw_mant_SGF[25]) );
NOR2XLTS U2552 ( .A(n1788), .B(n1919), .Y(n1789) );
AOI21X1TS U2553 ( .A0(n1790), .A1(n1919), .B0(n1789), .Y(n1794) );
XNOR2X1TS U2554 ( .A(n1794), .B(n1793), .Y(Raw_mant_SGF[24]) );
MXI2X1TS U2555 ( .A(n1796), .B(n1795), .S0(n1821), .Y(n1800) );
XOR2XLTS U2556 ( .A(n1800), .B(n1799), .Y(Raw_mant_SGF[23]) );
NOR2XLTS U2557 ( .A(n1801), .B(n1934), .Y(n1802) );
AOI21X1TS U2558 ( .A0(n1803), .A1(n1922), .B0(n1802), .Y(n1807) );
XNOR2X1TS U2559 ( .A(n1807), .B(n1806), .Y(Raw_mant_SGF[22]) );
MXI2X1TS U2560 ( .A(n1809), .B(n1808), .S0(n1821), .Y(n1813) );
XOR2XLTS U2561 ( .A(n1813), .B(n1812), .Y(Raw_mant_SGF[21]) );
NOR2XLTS U2562 ( .A(n1814), .B(n1934), .Y(n1815) );
AOI21X1TS U2563 ( .A0(n1816), .A1(n1934), .B0(n1815), .Y(n1820) );
XNOR2X1TS U2564 ( .A(n1820), .B(n1819), .Y(Raw_mant_SGF[20]) );
MXI2X1TS U2565 ( .A(n1823), .B(n1822), .S0(n1821), .Y(n1827) );
NOR2XLTS U2566 ( .A(n1825), .B(n1824), .Y(n1826) );
XOR2XLTS U2567 ( .A(n1827), .B(n1826), .Y(Raw_mant_SGF[19]) );
NOR2XLTS U2568 ( .A(n1828), .B(n1919), .Y(n1829) );
AOI21X1TS U2569 ( .A0(n1830), .A1(n1922), .B0(n1829), .Y(n1834) );
XNOR2X1TS U2570 ( .A(n1834), .B(n1833), .Y(Raw_mant_SGF[18]) );
MXI2X1TS U2571 ( .A(n1836), .B(n1835), .S0(n1768), .Y(n1840) );
NOR2XLTS U2572 ( .A(n1838), .B(n1837), .Y(n1839) );
XOR2XLTS U2573 ( .A(n1840), .B(n1839), .Y(Raw_mant_SGF[17]) );
AOI21X1TS U2574 ( .A0(n1843), .A1(n1922), .B0(n1842), .Y(n1847) );
XNOR2X1TS U2575 ( .A(n1847), .B(n1846), .Y(Raw_mant_SGF[16]) );
MXI2X1TS U2576 ( .A(n1849), .B(n1848), .S0(n1768), .Y(n1853) );
NOR2XLTS U2577 ( .A(n1851), .B(n1850), .Y(n1852) );
XOR2XLTS U2578 ( .A(n1853), .B(n1852), .Y(Raw_mant_SGF[15]) );
NOR2XLTS U2579 ( .A(n1854), .B(n1934), .Y(n1855) );
AOI21X1TS U2580 ( .A0(n1856), .A1(n1922), .B0(n1855), .Y(n1860) );
XNOR2X1TS U2581 ( .A(n1860), .B(n1859), .Y(Raw_mant_SGF[14]) );
MXI2X1TS U2582 ( .A(n1862), .B(n1861), .S0(n1768), .Y(n1866) );
NOR2XLTS U2583 ( .A(n1864), .B(n1863), .Y(n1865) );
XOR2XLTS U2584 ( .A(n1866), .B(n1865), .Y(Raw_mant_SGF[13]) );
OAI21XLTS U2585 ( .A0(n1934), .A1(n1869), .B0(n1868), .Y(n1873) );
NOR2BX1TS U2586 ( .AN(n1871), .B(n1870), .Y(n1872) );
XNOR2X1TS U2587 ( .A(n1873), .B(n1872), .Y(Raw_mant_SGF[12]) );
MXI2X1TS U2588 ( .A(n1875), .B(n1874), .S0(n1934), .Y(n1879) );
XOR2XLTS U2589 ( .A(n1879), .B(n1878), .Y(Raw_mant_SGF[11]) );
NOR2BX1TS U2590 ( .AN(n1884), .B(n1883), .Y(n1885) );
XNOR2X1TS U2591 ( .A(n1886), .B(n1885), .Y(Raw_mant_SGF[10]) );
MXI2X1TS U2592 ( .A(n1888), .B(n1887), .S0(n1934), .Y(n1892) );
NOR2XLTS U2593 ( .A(n1890), .B(n1889), .Y(n1891) );
XOR2XLTS U2594 ( .A(n1892), .B(n1891), .Y(Raw_mant_SGF[9]) );
OAI21XLTS U2595 ( .A0(n1895), .A1(n1922), .B0(n1894), .Y(n1899) );
NOR2BX1TS U2596 ( .AN(n1897), .B(n1896), .Y(n1898) );
XNOR2X1TS U2597 ( .A(n1899), .B(n1898), .Y(Raw_mant_SGF[8]) );
MXI2X1TS U2598 ( .A(n1901), .B(n1900), .S0(n1934), .Y(n1905) );
NOR2XLTS U2599 ( .A(n1903), .B(n1902), .Y(n1904) );
XOR2XLTS U2600 ( .A(n1905), .B(n1904), .Y(Raw_mant_SGF[7]) );
OAI21XLTS U2601 ( .A0(n1908), .A1(n1922), .B0(n1907), .Y(n1912) );
NOR2BX1TS U2602 ( .AN(n1910), .B(n1909), .Y(n1911) );
XNOR2X1TS U2603 ( .A(n1912), .B(n1911), .Y(Raw_mant_SGF[6]) );
MXI2X1TS U2604 ( .A(n1914), .B(n1913), .S0(n1934), .Y(n1918) );
NOR2XLTS U2605 ( .A(n1916), .B(n1915), .Y(n1917) );
XOR2XLTS U2606 ( .A(n1918), .B(n1917), .Y(Raw_mant_SGF[5]) );
NOR2BX1TS U2607 ( .AN(n1925), .B(n1924), .Y(n1926) );
XNOR2X1TS U2608 ( .A(n1927), .B(n1926), .Y(Raw_mant_SGF[4]) );
MXI2X1TS U2609 ( .A(n1928), .B(n1935), .S0(n1934), .Y(n1932) );
NOR2BX1TS U2610 ( .AN(n1930), .B(n1929), .Y(n1931) );
XNOR2X1TS U2611 ( .A(n1932), .B(n1931), .Y(Raw_mant_SGF[3]) );
NOR2XLTS U2612 ( .A(n1934), .B(n1933), .Y(n1937) );
OAI21XLTS U2613 ( .A0(DMP_SFG[0]), .A1(DmP_mant_SFG_SWR[2]), .B0(n1935), .Y(
n1936) );
XNOR2X1TS U2614 ( .A(n1937), .B(n1936), .Y(Raw_mant_SGF[2]) );
XOR2XLTS U2615 ( .A(DMP_EXP_EWSW[57]), .B(DmP_EXP_EWSW[57]), .Y(n1938) );
XOR2XLTS U2616 ( .A(intadd_470_n1), .B(n1938), .Y(Shift_amount_EXP_EW[5]) );
AOI22X1TS U2617 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1939), .B1(n873), .Y(n2536)
);
XNOR2X1TS U2618 ( .A(add_subt), .B(Data_Y[63]), .Y(n2483) );
XNOR2X1TS U2619 ( .A(intDX_EWSW[63]), .B(n2535), .Y(OP_FLAG_INIT) );
OAI22X1TS U2620 ( .A0(n2388), .A1(intDY_EWSW[38]), .B0(n875), .B1(
intDY_EWSW[22]), .Y(n1940) );
AOI22X1TS U2621 ( .A0(n2412), .A1(intDY_EWSW[58]), .B0(n2273), .B1(
intDY_EWSW[59]), .Y(n1942) );
AOI22X1TS U2622 ( .A0(n2268), .A1(intDY_EWSW[32]), .B0(n2396), .B1(
intDY_EWSW[33]), .Y(n1943) );
NAND2BXLTS U2623 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2097) );
AOI221X1TS U2624 ( .A0(n2270), .A1(intDY_EWSW[47]), .B0(intDY_EWSW[46]),
.B1(n2403), .C0(n2108), .Y(n1950) );
INVX2TS U2625 ( .A(intDX_EWSW[36]), .Y(n2114) );
OAI22X1TS U2626 ( .A0(n2387), .A1(intDY_EWSW[37]), .B0(n2368), .B1(
intDY_EWSW[36]), .Y(n1944) );
AOI221X1TS U2627 ( .A0(n2387), .A1(intDY_EWSW[37]), .B0(intDY_EWSW[36]),
.B1(n2114), .C0(n1944), .Y(n1949) );
OAI22X1TS U2628 ( .A0(n2381), .A1(intDY_EWSW[35]), .B0(n877), .B1(
intDY_EWSW[34]), .Y(n1945) );
OAI22X1TS U2629 ( .A0(n874), .A1(intDY_EWSW[42]), .B0(n891), .B1(
intDY_EWSW[41]), .Y(n1946) );
NAND4XLTS U2630 ( .A(n1950), .B(n1949), .C(n1948), .D(n1947), .Y(n1951) );
NOR4X1TS U2631 ( .A(n1954), .B(n1953), .C(n1952), .D(n1951), .Y(n2009) );
AOI22X1TS U2632 ( .A0(n2410), .A1(intDY_EWSW[62]), .B0(n2413), .B1(
intDY_EWSW[60]), .Y(n1955) );
AOI22X1TS U2633 ( .A0(n2392), .A1(intDY_EWSW[53]), .B0(n2399), .B1(
intDY_EWSW[10]), .Y(n1956) );
AOI22X1TS U2634 ( .A0(n2394), .A1(intDY_EWSW[51]), .B0(n2400), .B1(
intDY_EWSW[48]), .Y(n1957) );
AOI22X1TS U2635 ( .A0(n2269), .A1(intDY_EWSW[56]), .B0(n2398), .B1(
intDY_EWSW[57]), .Y(n1958) );
OAI221XLTS U2636 ( .A0(n2269), .A1(intDY_EWSW[56]), .B0(n2398), .B1(
intDY_EWSW[57]), .C0(n1958), .Y(n1959) );
NOR4X1TS U2637 ( .A(n1962), .B(n1961), .C(n1960), .D(n1959), .Y(n2008) );
AOI22X1TS U2638 ( .A0(n2267), .A1(intDY_EWSW[55]), .B0(n2401), .B1(
intDY_EWSW[52]), .Y(n1963) );
AOI22X1TS U2639 ( .A0(n2393), .A1(intDY_EWSW[44]), .B0(n2397), .B1(
intDY_EWSW[45]), .Y(n1964) );
OAI221XLTS U2640 ( .A0(n2393), .A1(intDY_EWSW[44]), .B0(n2397), .B1(
intDY_EWSW[45]), .C0(n1964), .Y(n1969) );
AOI22X1TS U2641 ( .A0(n2390), .A1(intDY_EWSW[11]), .B0(n2395), .B1(
intDY_EWSW[8]), .Y(n1965) );
OAI221XLTS U2642 ( .A0(n2390), .A1(intDY_EWSW[11]), .B0(n2395), .B1(
intDY_EWSW[8]), .C0(n1965), .Y(n1968) );
AOI22X1TS U2643 ( .A0(n2391), .A1(intDY_EWSW[49]), .B0(n2402), .B1(
intDY_EWSW[54]), .Y(n1966) );
NOR4X1TS U2644 ( .A(n1970), .B(n1969), .C(n1967), .D(n1968), .Y(n2007) );
OAI22X1TS U2645 ( .A0(n2378), .A1(intDY_EWSW[15]), .B0(n2372), .B1(
intDY_EWSW[12]), .Y(n1971) );
INVX2TS U2646 ( .A(intDX_EWSW[26]), .Y(n2165) );
OAI22X1TS U2647 ( .A0(n2364), .A1(intDY_EWSW[5]), .B0(n2256), .B1(
intDY_EWSW[26]), .Y(n1972) );
AOI221X1TS U2648 ( .A0(n2364), .A1(intDY_EWSW[5]), .B0(intDY_EWSW[26]), .B1(
n2165), .C0(n1972), .Y(n1977) );
OAI22X1TS U2649 ( .A0(n2377), .A1(intDY_EWSW[3]), .B0(n2371), .B1(
intDY_EWSW[6]), .Y(n1973) );
AOI221X1TS U2650 ( .A0(n2377), .A1(intDY_EWSW[3]), .B0(intDY_EWSW[6]), .B1(
n2371), .C0(n1973), .Y(n1976) );
OAI22X1TS U2651 ( .A0(n2266), .A1(intDY_EWSW[9]), .B0(n880), .B1(
intDY_EWSW[14]), .Y(n1974) );
AOI221X1TS U2652 ( .A0(n2266), .A1(intDY_EWSW[9]), .B0(intDY_EWSW[14]), .B1(
n880), .C0(n1974), .Y(n1975) );
NAND4XLTS U2653 ( .A(n1978), .B(n1977), .C(n1976), .D(n1975), .Y(n2005) );
OAI22X1TS U2654 ( .A0(n2252), .A1(intDY_EWSW[7]), .B0(n2370), .B1(
intDY_EWSW[4]), .Y(n1979) );
AOI221X1TS U2655 ( .A0(n2252), .A1(intDY_EWSW[7]), .B0(intDY_EWSW[4]), .B1(
n2370), .C0(n1979), .Y(n1986) );
INVX2TS U2656 ( .A(intDX_EWSW[50]), .Y(n2168) );
OAI22X1TS U2657 ( .A0(n2265), .A1(intDY_EWSW[50]), .B0(n2406), .B1(
intDY_EWSW[61]), .Y(n1980) );
AOI221X1TS U2658 ( .A0(n2168), .A1(intDY_EWSW[50]), .B0(intDY_EWSW[61]),
.B1(n2406), .C0(n1980), .Y(n1985) );
OAI22X1TS U2659 ( .A0(n881), .A1(intDY_EWSW[27]), .B0(n2262), .B1(
intDY_EWSW[40]), .Y(n1981) );
AOI221X1TS U2660 ( .A0(n881), .A1(intDY_EWSW[27]), .B0(intDY_EWSW[40]), .B1(
n2262), .C0(n1981), .Y(n1984) );
OAI22X1TS U2661 ( .A0(n2263), .A1(intDY_EWSW[0]), .B0(n2369), .B1(
intDY_EWSW[1]), .Y(n1982) );
AOI221X1TS U2662 ( .A0(n2263), .A1(intDY_EWSW[0]), .B0(intDY_EWSW[1]), .B1(
n2369), .C0(n1982), .Y(n1983) );
NAND4XLTS U2663 ( .A(n1986), .B(n1985), .C(n1984), .D(n1983), .Y(n2004) );
INVX2TS U2664 ( .A(intDX_EWSW[17]), .Y(n2163) );
OAI22X1TS U2665 ( .A0(n2383), .A1(intDY_EWSW[16]), .B0(n2367), .B1(
intDY_EWSW[17]), .Y(n1987) );
AOI221X1TS U2666 ( .A0(n2383), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]),
.B1(n2163), .C0(n1987), .Y(n1993) );
OAI22X1TS U2667 ( .A0(n2380), .A1(intDY_EWSW[31]), .B0(n876), .B1(
intDY_EWSW[30]), .Y(n1988) );
OAI22X1TS U2668 ( .A0(n2264), .A1(intDY_EWSW[43]), .B0(n2255), .B1(n872),
.Y(n1989) );
INVX2TS U2669 ( .A(intDX_EWSW[18]), .Y(n2172) );
NAND2BXLTS U2670 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2065) );
AOI221X1TS U2671 ( .A0(n2404), .A1(intDY_EWSW[18]), .B0(intDY_EWSW[19]),
.B1(n2271), .C0(n2069), .Y(n1990) );
NAND4XLTS U2672 ( .A(n1993), .B(n1992), .C(n1991), .D(n1990), .Y(n2003) );
OAI22X1TS U2673 ( .A0(n2379), .A1(intDY_EWSW[25]), .B0(n2259), .B1(
intDY_EWSW[24]), .Y(n1994) );
AOI221X1TS U2674 ( .A0(n2379), .A1(intDY_EWSW[25]), .B0(intDY_EWSW[24]),
.B1(n2259), .C0(n1994), .Y(n2001) );
OAI22X1TS U2675 ( .A0(n888), .A1(intDY_EWSW[13]), .B0(n2257), .B1(
intDY_EWSW[2]), .Y(n1995) );
OAI22X1TS U2676 ( .A0(n890), .A1(intDY_EWSW[29]), .B0(n2375), .B1(
intDY_EWSW[28]), .Y(n1996) );
OAI22X1TS U2677 ( .A0(n889), .A1(intDY_EWSW[21]), .B0(n2373), .B1(
intDY_EWSW[20]), .Y(n1997) );
NAND4XLTS U2678 ( .A(n2001), .B(n2000), .C(n1999), .D(n1998), .Y(n2002) );
NOR4X1TS U2679 ( .A(n2005), .B(n2004), .C(n2003), .D(n2002), .Y(n2006) );
NAND4XLTS U2680 ( .A(n2009), .B(n2008), .C(n2007), .D(n2006), .Y(n2158) );
NOR2BX1TS U2681 ( .AN(OP_FLAG_INIT), .B(n2158), .Y(ZERO_FLAG_INIT) );
NOR2BX1TS U2682 ( .AN(Shift_reg_FLAGS_7[3]), .B(Shift_reg_FLAGS_7[0]), .Y(
n_21_net_) );
NOR2XLTS U2683 ( .A(n2392), .B(intDY_EWSW[53]), .Y(n2010) );
INVX2TS U2684 ( .A(intDX_EWSW[55]), .Y(n2142) );
OAI22X1TS U2685 ( .A0(n2142), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n2402), .Y(n2132) );
AOI211X1TS U2686 ( .A0(intDX_EWSW[52]), .A1(n2467), .B0(n2010), .C0(n2132),
.Y(n2134) );
NOR2BX1TS U2687 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2011) );
NOR2X1TS U2688 ( .A(n2398), .B(intDY_EWSW[57]), .Y(n2084) );
NAND2X1TS U2689 ( .A(n2337), .B(intDX_EWSW[61]), .Y(n2090) );
OAI211X1TS U2690 ( .A0(intDY_EWSW[60]), .A1(n2413), .B0(n2094), .C0(n2090),
.Y(n2096) );
OAI21X1TS U2691 ( .A0(intDY_EWSW[58]), .A1(n2412), .B0(n2086), .Y(n2088) );
NOR2X1TS U2692 ( .A(n2391), .B(intDY_EWSW[49]), .Y(n2135) );
NAND2BXLTS U2693 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2137) );
OAI21X1TS U2694 ( .A0(intDY_EWSW[50]), .A1(n2168), .B0(n2137), .Y(n2141) );
AOI211X1TS U2695 ( .A0(intDX_EWSW[48]), .A1(n2466), .B0(n2135), .C0(n2141),
.Y(n2012) );
NAND3X1TS U2696 ( .A(n2134), .B(n2144), .C(n2012), .Y(n2152) );
NOR2BX1TS U2697 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2126) );
AOI21X1TS U2698 ( .A0(intDX_EWSW[38]), .A1(n2477), .B0(n2126), .Y(n2125) );
NAND2X1TS U2699 ( .A(n2476), .B(intDX_EWSW[37]), .Y(n2113) );
OAI211X1TS U2700 ( .A0(intDY_EWSW[36]), .A1(n2114), .B0(n2125), .C0(n2113),
.Y(n2116) );
NOR2X1TS U2701 ( .A(n2397), .B(intDY_EWSW[45]), .Y(n2098) );
INVX2TS U2702 ( .A(intDX_EWSW[43]), .Y(n2101) );
OA22X1TS U2703 ( .A0(n874), .A1(intDY_EWSW[42]), .B0(n2101), .B1(
intDY_EWSW[43]), .Y(n2104) );
NAND2BXLTS U2704 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2013) );
NAND4XLTS U2705 ( .A(n2106), .B(n2104), .C(n2014), .D(n2013), .Y(n2150) );
NAND2BXLTS U2706 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2015) );
OA22X1TS U2707 ( .A0(n877), .A1(intDY_EWSW[34]), .B0(n2381), .B1(
intDY_EWSW[35]), .Y(n2120) );
OAI211XLTS U2708 ( .A0(n2396), .A1(intDY_EWSW[33]), .B0(n2015), .C0(n2120),
.Y(n2016) );
NOR4X1TS U2709 ( .A(n2152), .B(n2116), .C(n2150), .D(n2016), .Y(n2156) );
OA22X1TS U2710 ( .A0(n876), .A1(intDY_EWSW[30]), .B0(n2380), .B1(
intDY_EWSW[31]), .Y(n2027) );
OAI21XLTS U2711 ( .A0(intDY_EWSW[29]), .A1(n890), .B0(intDY_EWSW[28]), .Y(
n2017) );
NAND2BXLTS U2712 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2020) );
OAI21X1TS U2713 ( .A0(intDY_EWSW[26]), .A1(n2165), .B0(n2020), .Y(n2079) );
NOR2X1TS U2714 ( .A(n2379), .B(intDY_EWSW[25]), .Y(n2076) );
NOR2XLTS U2715 ( .A(n2076), .B(intDX_EWSW[24]), .Y(n2019) );
AOI22X1TS U2716 ( .A0(n2019), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n2379), .Y(n2022) );
AOI32X1TS U2717 ( .A0(n2165), .A1(n2020), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n881), .Y(n2021) );
OAI32X1TS U2718 ( .A0(n2079), .A1(n2078), .A2(n2022), .B0(n2021), .B1(n2078),
.Y(n2025) );
OAI21XLTS U2719 ( .A0(intDY_EWSW[31]), .A1(n2380), .B0(intDY_EWSW[30]), .Y(
n2023) );
OAI2BB2XLTS U2720 ( .B0(intDX_EWSW[30]), .B1(n2023), .A0N(intDY_EWSW[31]),
.A1N(n2380), .Y(n2024) );
AOI211X1TS U2721 ( .A0(n2027), .A1(n2026), .B0(n2025), .C0(n2024), .Y(n2083)
);
INVX2TS U2722 ( .A(intDX_EWSW[23]), .Y(n2070) );
OA22X1TS U2723 ( .A0(n875), .A1(intDY_EWSW[22]), .B0(n2070), .B1(n872), .Y(
n2075) );
OA22X1TS U2724 ( .A0(n880), .A1(intDY_EWSW[14]), .B0(n2378), .B1(
intDY_EWSW[15]), .Y(n2055) );
OAI2BB1X1TS U2725 ( .A0N(n879), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]), .Y(
n2030) );
OAI22X1TS U2726 ( .A0(intDX_EWSW[4]), .A1(n2030), .B0(n879), .B1(
intDX_EWSW[5]), .Y(n2041) );
OAI2BB1X1TS U2727 ( .A0N(n878), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]), .Y(
n2031) );
OAI22X1TS U2728 ( .A0(intDX_EWSW[6]), .A1(n2031), .B0(n878), .B1(
intDX_EWSW[7]), .Y(n2040) );
NAND2BXLTS U2729 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2034) );
AOI2BB2XLTS U2730 ( .B0(intDX_EWSW[1]), .B1(n2478), .A0N(intDY_EWSW[0]),
.A1N(n2032), .Y(n2033) );
OAI211XLTS U2731 ( .A0(n2377), .A1(intDY_EWSW[3]), .B0(n2034), .C0(n2033),
.Y(n2037) );
OAI21XLTS U2732 ( .A0(intDY_EWSW[3]), .A1(n2377), .B0(intDY_EWSW[2]), .Y(
n2035) );
AOI2BB2XLTS U2733 ( .B0(intDY_EWSW[3]), .B1(n2377), .A0N(intDX_EWSW[2]),
.A1N(n2035), .Y(n2036) );
AOI222X1TS U2734 ( .A0(intDX_EWSW[4]), .A1(n2274), .B0(intDX_EWSW[5]), .B1(
n879), .C0(n2037), .C1(n2036), .Y(n2039) );
AOI22X1TS U2735 ( .A0(intDX_EWSW[7]), .A1(n878), .B0(intDX_EWSW[6]), .B1(
n2275), .Y(n2038) );
OAI32X1TS U2736 ( .A0(n2041), .A1(n2040), .A2(n2039), .B0(n2038), .B1(n2040),
.Y(n2058) );
NAND2BXLTS U2737 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2045) );
NOR2X1TS U2738 ( .A(n2390), .B(intDY_EWSW[11]), .Y(n2043) );
AOI21X1TS U2739 ( .A0(intDX_EWSW[10]), .A1(n2465), .B0(n2043), .Y(n2048) );
OAI211XLTS U2740 ( .A0(intDY_EWSW[8]), .A1(n2395), .B0(n2045), .C0(n2048),
.Y(n2057) );
OAI21XLTS U2741 ( .A0(intDY_EWSW[13]), .A1(n888), .B0(intDY_EWSW[12]), .Y(
n2042) );
NOR2XLTS U2742 ( .A(n2043), .B(intDX_EWSW[10]), .Y(n2044) );
AOI22X1TS U2743 ( .A0(intDY_EWSW[11]), .A1(n2390), .B0(intDY_EWSW[10]), .B1(
n2044), .Y(n2050) );
NAND3XLTS U2744 ( .A(n2395), .B(n2045), .C(intDY_EWSW[8]), .Y(n2047) );
NAND2BXLTS U2745 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2046) );
AOI21X1TS U2746 ( .A0(n2047), .A1(n2046), .B0(n2059), .Y(n2049) );
OAI2BB2XLTS U2747 ( .B0(n2050), .B1(n2059), .A0N(n2049), .A1N(n2048), .Y(
n2053) );
OAI21XLTS U2748 ( .A0(intDY_EWSW[15]), .A1(n2378), .B0(intDY_EWSW[14]), .Y(
n2051) );
OAI2BB2XLTS U2749 ( .B0(intDX_EWSW[14]), .B1(n2051), .A0N(intDY_EWSW[15]),
.A1N(n2378), .Y(n2052) );
AOI211X1TS U2750 ( .A0(n2055), .A1(n2054), .B0(n2053), .C0(n2052), .Y(n2056)
);
OAI31X1TS U2751 ( .A0(n2059), .A1(n2058), .A2(n2057), .B0(n2056), .Y(n2061)
);
NOR2X1TS U2752 ( .A(n2163), .B(intDY_EWSW[17]), .Y(n2063) );
NAND3BXLTS U2753 ( .AN(n2068), .B(n2061), .C(n2060), .Y(n2082) );
OAI21XLTS U2754 ( .A0(intDY_EWSW[21]), .A1(n889), .B0(intDY_EWSW[20]), .Y(
n2062) );
NOR2XLTS U2755 ( .A(n2063), .B(intDX_EWSW[16]), .Y(n2064) );
AOI22X1TS U2756 ( .A0(n2064), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n2163), .Y(n2067) );
AOI32X1TS U2757 ( .A0(n2172), .A1(n2065), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n2271), .Y(n2066) );
OAI21XLTS U2758 ( .A0(n872), .A1(n2070), .B0(intDY_EWSW[22]), .Y(n2071) );
OAI2BB2XLTS U2759 ( .B0(intDX_EWSW[22]), .B1(n2071), .A0N(n872), .A1N(n2070),
.Y(n2072) );
AOI211X1TS U2760 ( .A0(n2075), .A1(n2074), .B0(n2073), .C0(n2072), .Y(n2081)
);
NOR2BX1TS U2761 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2077) );
OR4X2TS U2762 ( .A(n2079), .B(n2078), .C(n2077), .D(n2076), .Y(n2080) );
AOI32X1TS U2763 ( .A0(n2083), .A1(n2082), .A2(n2081), .B0(n2080), .B1(n2083),
.Y(n2155) );
NOR2XLTS U2764 ( .A(n2084), .B(intDX_EWSW[56]), .Y(n2085) );
AOI22X1TS U2765 ( .A0(intDY_EWSW[57]), .A1(n2398), .B0(intDY_EWSW[56]), .B1(
n2085), .Y(n2089) );
OA21XLTS U2766 ( .A0(n2089), .A1(n2088), .B0(n2087), .Y(n2095) );
NAND2BXLTS U2767 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2092) );
NAND3XLTS U2768 ( .A(n2413), .B(n2090), .C(intDY_EWSW[60]), .Y(n2091) );
OAI211XLTS U2769 ( .A0(intDX_EWSW[61]), .A1(n2337), .B0(n2092), .C0(n2091),
.Y(n2093) );
OAI2BB2XLTS U2770 ( .B0(n2096), .B1(n2095), .A0N(n2094), .A1N(n2093), .Y(
n2154) );
NOR2BX1TS U2771 ( .AN(n2097), .B(intDX_EWSW[46]), .Y(n2112) );
AOI22X1TS U2772 ( .A0(intDY_EWSW[45]), .A1(n2397), .B0(intDY_EWSW[44]), .B1(
n2099), .Y(n2109) );
OAI21XLTS U2773 ( .A0(intDY_EWSW[41]), .A1(n891), .B0(intDY_EWSW[40]), .Y(
n2100) );
OAI21XLTS U2774 ( .A0(intDY_EWSW[43]), .A1(n2101), .B0(intDY_EWSW[42]), .Y(
n2102) );
OAI2BB2XLTS U2775 ( .B0(intDX_EWSW[42]), .B1(n2102), .A0N(intDY_EWSW[43]),
.A1N(n2101), .Y(n2103) );
AOI32X1TS U2776 ( .A0(n2106), .A1(n2105), .A2(n2104), .B0(n2103), .B1(n2106),
.Y(n2107) );
OAI21XLTS U2777 ( .A0(n2109), .A1(n2108), .B0(n2107), .Y(n2111) );
NOR2BX1TS U2778 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2110) );
AOI211XLTS U2779 ( .A0(intDY_EWSW[46]), .A1(n2112), .B0(n2111), .C0(n2110),
.Y(n2151) );
NAND3XLTS U2780 ( .A(n2114), .B(n2113), .C(intDY_EWSW[36]), .Y(n2115) );
OAI21XLTS U2781 ( .A0(intDX_EWSW[37]), .A1(n2476), .B0(n2115), .Y(n2124) );
INVX2TS U2782 ( .A(n2116), .Y(n2122) );
OAI21XLTS U2783 ( .A0(intDY_EWSW[33]), .A1(n2396), .B0(intDY_EWSW[32]), .Y(
n2117) );
OAI2BB2XLTS U2784 ( .B0(intDX_EWSW[32]), .B1(n2117), .A0N(intDY_EWSW[33]),
.A1N(n2396), .Y(n2121) );
OAI2BB2XLTS U2785 ( .B0(intDX_EWSW[34]), .B1(n2118), .A0N(intDY_EWSW[35]),
.A1N(n2381), .Y(n2119) );
AOI32X1TS U2786 ( .A0(n2122), .A1(n2121), .A2(n2120), .B0(n2119), .B1(n2122),
.Y(n2123) );
OAI2BB1X1TS U2787 ( .A0N(n2125), .A1N(n2124), .B0(n2123), .Y(n2130) );
NOR2BX1TS U2788 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2129) );
NOR3X1TS U2789 ( .A(n2477), .B(n2126), .C(intDX_EWSW[38]), .Y(n2128) );
INVX2TS U2790 ( .A(n2152), .Y(n2127) );
OAI31X1TS U2791 ( .A0(n2130), .A1(n2129), .A2(n2128), .B0(n2127), .Y(n2149)
);
OAI21XLTS U2792 ( .A0(intDY_EWSW[53]), .A1(n2392), .B0(intDY_EWSW[52]), .Y(
n2131) );
AOI2BB2XLTS U2793 ( .B0(intDY_EWSW[53]), .B1(n2392), .A0N(intDX_EWSW[52]),
.A1N(n2131), .Y(n2133) );
NOR2XLTS U2794 ( .A(n2133), .B(n2132), .Y(n2147) );
INVX2TS U2795 ( .A(n2134), .Y(n2140) );
AOI22X1TS U2796 ( .A0(intDY_EWSW[49]), .A1(n2391), .B0(intDY_EWSW[48]), .B1(
n2136), .Y(n2139) );
AOI32X1TS U2797 ( .A0(n2168), .A1(n2137), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n2394), .Y(n2138) );
OAI32X1TS U2798 ( .A0(n2141), .A1(n2140), .A2(n2139), .B0(n2138), .B1(n2140),
.Y(n2146) );
OAI2BB2XLTS U2799 ( .B0(intDX_EWSW[54]), .B1(n2143), .A0N(intDY_EWSW[55]),
.A1N(n2142), .Y(n2145) );
OAI31X1TS U2800 ( .A0(n2147), .A1(n2146), .A2(n2145), .B0(n2144), .Y(n2148)
);
OAI221XLTS U2801 ( .A0(n2152), .A1(n2151), .B0(n2150), .B1(n2149), .C0(n2148), .Y(n2153) );
AOI211X1TS U2802 ( .A0(n2156), .A1(n2155), .B0(n2154), .C0(n2153), .Y(n2157)
);
BUFX3TS U2803 ( .A(n2162), .Y(n2167) );
AOI21X1TS U2804 ( .A0(n2158), .A1(n2167), .B0(intDX_EWSW[63]), .Y(n2159) );
AOI21X1TS U2805 ( .A0(n2535), .A1(n2173), .B0(n2159), .Y(SIGN_FLAG_INIT) );
AOI2BB1XLTS U2806 ( .A0N(n2484), .A1N(SIGN_FLAG_SHT1SHT2), .B0(
array_comparators_GTComparator_N0), .Y(formatted_number_W[63]) );
NAND2X1TS U2807 ( .A(N94), .B(n1768), .Y(n2160) );
XNOR2X1TS U2808 ( .A(n2160), .B(N95), .Y(Raw_mant_SGF[1]) );
BUFX3TS U2809 ( .A(n2162), .Y(n2164) );
AOI22X1TS U2810 ( .A0(n2161), .A1(n2479), .B0(n2263), .B1(n2164), .Y(
DmP_INIT_EWSW[0]) );
AOI22X1TS U2811 ( .A0(n2161), .A1(n2478), .B0(n2369), .B1(n2166), .Y(
DmP_INIT_EWSW[1]) );
AOI22X1TS U2812 ( .A0(n2161), .A1(n2461), .B0(n2257), .B1(n2173), .Y(
DmP_INIT_EWSW[2]) );
AOI22X1TS U2813 ( .A0(n2161), .A1(n2425), .B0(n2377), .B1(n2173), .Y(
DmP_INIT_EWSW[3]) );
BUFX3TS U2814 ( .A(n2162), .Y(n2177) );
AOI22X1TS U2815 ( .A0(n2161), .A1(n2274), .B0(n2370), .B1(n2177), .Y(
DmP_INIT_EWSW[4]) );
AOI22X1TS U2816 ( .A0(n2161), .A1(n879), .B0(n2364), .B1(n2166), .Y(
DmP_INIT_EWSW[5]) );
AOI22X1TS U2817 ( .A0(n2161), .A1(n2275), .B0(n2371), .B1(n2166), .Y(
DmP_INIT_EWSW[6]) );
AOI22X1TS U2818 ( .A0(n2161), .A1(n878), .B0(n2252), .B1(n2176), .Y(
DmP_INIT_EWSW[7]) );
AOI22X1TS U2819 ( .A0(n2161), .A1(n2450), .B0(n2395), .B1(n2164), .Y(
DmP_INIT_EWSW[8]) );
AOI22X1TS U2820 ( .A0(n2161), .A1(n2463), .B0(n2266), .B1(n2164), .Y(
DmP_INIT_EWSW[9]) );
AOI22X1TS U2821 ( .A0(n2161), .A1(n2465), .B0(n2399), .B1(n2164), .Y(
DmP_INIT_EWSW[10]) );
AOI22X1TS U2822 ( .A0(n2161), .A1(n2448), .B0(n2390), .B1(n2164), .Y(
DmP_INIT_EWSW[11]) );
AOI22X1TS U2823 ( .A0(n2161), .A1(n2439), .B0(n2372), .B1(n2164), .Y(
DmP_INIT_EWSW[12]) );
AOI22X1TS U2824 ( .A0(n2170), .A1(n2434), .B0(n888), .B1(n2164), .Y(
DmP_INIT_EWSW[13]) );
AOI22X1TS U2825 ( .A0(n2170), .A1(n2456), .B0(n880), .B1(n2164), .Y(
DmP_INIT_EWSW[14]) );
AOI22X1TS U2826 ( .A0(n2170), .A1(n2429), .B0(n2378), .B1(n2164), .Y(
DmP_INIT_EWSW[15]) );
AOI22X1TS U2827 ( .A0(n2170), .A1(n2445), .B0(n2383), .B1(n2164), .Y(
DmP_INIT_EWSW[16]) );
AOI22X1TS U2828 ( .A0(n2170), .A1(n2446), .B0(n2163), .B1(n2164), .Y(
DmP_INIT_EWSW[17]) );
AOI22X1TS U2829 ( .A0(n2170), .A1(n2475), .B0(n2172), .B1(n2166), .Y(
DmP_INIT_EWSW[18]) );
AOI22X1TS U2830 ( .A0(n2170), .A1(n2480), .B0(n2271), .B1(n2164), .Y(
DmP_INIT_EWSW[19]) );
AOI22X1TS U2831 ( .A0(n2170), .A1(n2440), .B0(n2373), .B1(n2173), .Y(
DmP_INIT_EWSW[20]) );
AOI22X1TS U2832 ( .A0(n2170), .A1(n2435), .B0(n889), .B1(n2173), .Y(
DmP_INIT_EWSW[21]) );
AOI22X1TS U2833 ( .A0(n2170), .A1(n2457), .B0(n875), .B1(n2166), .Y(
DmP_INIT_EWSW[22]) );
AOI22X1TS U2834 ( .A0(n2170), .A1(n2433), .B0(n2255), .B1(n2173), .Y(
DmP_INIT_EWSW[23]) );
AOI22X1TS U2835 ( .A0(n2170), .A1(n2447), .B0(n2259), .B1(n2173), .Y(
DmP_INIT_EWSW[24]) );
AOI22X1TS U2836 ( .A0(n2170), .A1(n2444), .B0(n2379), .B1(n2166), .Y(
DmP_INIT_EWSW[25]) );
AOI22X1TS U2837 ( .A0(n2169), .A1(n2443), .B0(n2165), .B1(n2173), .Y(
DmP_INIT_EWSW[26]) );
AOI22X1TS U2838 ( .A0(n2169), .A1(n2455), .B0(n881), .B1(n2166), .Y(
DmP_INIT_EWSW[27]) );
AOI22X1TS U2839 ( .A0(n2169), .A1(n2441), .B0(n2375), .B1(n2173), .Y(
DmP_INIT_EWSW[28]) );
AOI22X1TS U2840 ( .A0(n2169), .A1(n2436), .B0(n890), .B1(n2167), .Y(
DmP_INIT_EWSW[29]) );
AOI22X1TS U2841 ( .A0(n2169), .A1(n2458), .B0(n876), .B1(n2167), .Y(
DmP_INIT_EWSW[30]) );
AOI22X1TS U2842 ( .A0(n2169), .A1(n2430), .B0(n2380), .B1(n2167), .Y(
DmP_INIT_EWSW[31]) );
AOI22X1TS U2843 ( .A0(n2169), .A1(n2469), .B0(n2268), .B1(n2167), .Y(
DmP_INIT_EWSW[32]) );
AOI22X1TS U2844 ( .A0(n2169), .A1(n2428), .B0(n2396), .B1(n2167), .Y(
DmP_INIT_EWSW[33]) );
AOI22X1TS U2845 ( .A0(n2169), .A1(n2459), .B0(n877), .B1(n2167), .Y(
DmP_INIT_EWSW[34]) );
AOI22X1TS U2846 ( .A0(n2169), .A1(n2431), .B0(n2381), .B1(n2167), .Y(
DmP_INIT_EWSW[35]) );
AOI22X1TS U2847 ( .A0(n2169), .A1(n2442), .B0(n2368), .B1(n2167), .Y(
DmP_INIT_EWSW[36]) );
AOI22X1TS U2848 ( .A0(n2169), .A1(n2476), .B0(n2387), .B1(n2167), .Y(
DmP_INIT_EWSW[37]) );
AOI22X1TS U2849 ( .A0(n2169), .A1(n2477), .B0(n2388), .B1(n2167), .Y(
DmP_INIT_EWSW[38]) );
AOI22X1TS U2850 ( .A0(n2170), .A1(n2405), .B0(n2272), .B1(n2164), .Y(
DmP_INIT_EWSW[39]) );
AOI22X1TS U2851 ( .A0(n2169), .A1(n2462), .B0(n2262), .B1(n2175), .Y(
DmP_INIT_EWSW[40]) );
AOI22X1TS U2852 ( .A0(n2170), .A1(n2437), .B0(n891), .B1(n2175), .Y(
DmP_INIT_EWSW[41]) );
AOI22X1TS U2853 ( .A0(n2169), .A1(n2452), .B0(n874), .B1(n2173), .Y(
DmP_INIT_EWSW[42]) );
AOI22X1TS U2854 ( .A0(n2170), .A1(n2432), .B0(n2264), .B1(n2173), .Y(
DmP_INIT_EWSW[43]) );
AOI22X1TS U2855 ( .A0(n2169), .A1(n2464), .B0(n2393), .B1(n2175), .Y(
DmP_INIT_EWSW[44]) );
AOI22X1TS U2856 ( .A0(n2170), .A1(n2453), .B0(n2397), .B1(n2167), .Y(
DmP_INIT_EWSW[45]) );
AOI22X1TS U2857 ( .A0(n2169), .A1(n2471), .B0(n2403), .B1(n2173), .Y(
DmP_INIT_EWSW[46]) );
AOI22X1TS U2858 ( .A0(n2170), .A1(n2481), .B0(n2270), .B1(n2166), .Y(
DmP_INIT_EWSW[47]) );
AOI22X1TS U2859 ( .A0(n2169), .A1(n2466), .B0(n2400), .B1(n2173), .Y(
DmP_INIT_EWSW[48]) );
AOI22X1TS U2860 ( .A0(n2170), .A1(n2449), .B0(n2391), .B1(n2175), .Y(
DmP_INIT_EWSW[49]) );
AOI22X1TS U2861 ( .A0(n2169), .A1(n2438), .B0(n2168), .B1(n2162), .Y(
DmP_INIT_EWSW[50]) );
AOI22X1TS U2862 ( .A0(n2169), .A1(n2468), .B0(n2394), .B1(n2166), .Y(
DmP_INIT_EWSW[51]) );
AOI22X1TS U2863 ( .A0(n2178), .A1(n2467), .B0(n2401), .B1(n2176), .Y(
DmP_INIT_EWSW[52]) );
AOI22X1TS U2864 ( .A0(n2170), .A1(n2426), .B0(n2392), .B1(n2166), .Y(
DmP_INIT_EWSW[53]) );
AOI22X1TS U2865 ( .A0(n2179), .A1(n2451), .B0(n2402), .B1(n2162), .Y(
DmP_INIT_EWSW[54]) );
AOI22X1TS U2866 ( .A0(n2161), .A1(n2427), .B0(n2267), .B1(n2162), .Y(
DmP_INIT_EWSW[55]) );
AOI22X1TS U2867 ( .A0(n2174), .A1(n2460), .B0(n2269), .B1(n2177), .Y(
DmP_INIT_EWSW[56]) );
AOI22X1TS U2868 ( .A0(n2161), .A1(n2454), .B0(n2398), .B1(n2175), .Y(
DmP_INIT_EWSW[57]) );
AOI22X1TS U2869 ( .A0(n2161), .A1(n2263), .B0(n2479), .B1(n2177), .Y(
DMP_INIT_EWSW[0]) );
AOI22X1TS U2870 ( .A0(n2174), .A1(n2369), .B0(n2478), .B1(n2177), .Y(
DMP_INIT_EWSW[1]) );
AOI22X1TS U2871 ( .A0(n2169), .A1(n2257), .B0(n2461), .B1(n2177), .Y(
DMP_INIT_EWSW[2]) );
AOI22X1TS U2872 ( .A0(n2170), .A1(n2377), .B0(n2425), .B1(n2177), .Y(
DMP_INIT_EWSW[3]) );
AOI22X1TS U2873 ( .A0(n2171), .A1(n2370), .B0(n2274), .B1(n2177), .Y(
DMP_INIT_EWSW[4]) );
AOI22X1TS U2874 ( .A0(n2174), .A1(n2364), .B0(n879), .B1(n2177), .Y(
DMP_INIT_EWSW[5]) );
AOI22X1TS U2875 ( .A0(n2174), .A1(n2371), .B0(n2275), .B1(n2177), .Y(
DMP_INIT_EWSW[6]) );
AOI22X1TS U2876 ( .A0(n2174), .A1(n2252), .B0(n878), .B1(n2177), .Y(
DMP_INIT_EWSW[7]) );
AOI22X1TS U2877 ( .A0(n2171), .A1(n2395), .B0(n2450), .B1(n2177), .Y(
DMP_INIT_EWSW[8]) );
AOI22X1TS U2878 ( .A0(n2174), .A1(n2266), .B0(n2463), .B1(n2177), .Y(
DMP_INIT_EWSW[9]) );
AOI22X1TS U2879 ( .A0(n2171), .A1(n2399), .B0(n2465), .B1(n2166), .Y(
DMP_INIT_EWSW[10]) );
AOI22X1TS U2880 ( .A0(n2174), .A1(n2390), .B0(n2448), .B1(n2173), .Y(
DMP_INIT_EWSW[11]) );
AOI22X1TS U2881 ( .A0(n2174), .A1(n2372), .B0(n2439), .B1(n2166), .Y(
DMP_INIT_EWSW[12]) );
AOI22X1TS U2882 ( .A0(n2171), .A1(n888), .B0(n2434), .B1(n2173), .Y(
DMP_INIT_EWSW[13]) );
AOI22X1TS U2883 ( .A0(n2174), .A1(n880), .B0(n2456), .B1(n2166), .Y(
DMP_INIT_EWSW[14]) );
AOI22X1TS U2884 ( .A0(n2174), .A1(n2378), .B0(n2429), .B1(n2173), .Y(
DMP_INIT_EWSW[15]) );
AOI22X1TS U2885 ( .A0(n2171), .A1(n2383), .B0(n2445), .B1(n2173), .Y(
DMP_INIT_EWSW[16]) );
AOI22X1TS U2886 ( .A0(n2174), .A1(n2367), .B0(n2446), .B1(n2166), .Y(
DMP_INIT_EWSW[17]) );
AOI22X1TS U2887 ( .A0(n2174), .A1(n2172), .B0(n2475), .B1(n2173), .Y(
DMP_INIT_EWSW[18]) );
AOI22X1TS U2888 ( .A0(n2171), .A1(n2271), .B0(n2480), .B1(n2166), .Y(
DMP_INIT_EWSW[19]) );
AOI22X1TS U2889 ( .A0(n2174), .A1(n2373), .B0(n2440), .B1(n2173), .Y(
DMP_INIT_EWSW[20]) );
AOI22X1TS U2890 ( .A0(n2174), .A1(n889), .B0(n2435), .B1(n2173), .Y(
DMP_INIT_EWSW[21]) );
AOI22X1TS U2891 ( .A0(n2174), .A1(n875), .B0(n2457), .B1(n2166), .Y(
DMP_INIT_EWSW[22]) );
AOI22X1TS U2892 ( .A0(n2174), .A1(n2255), .B0(n2433), .B1(n2173), .Y(
DMP_INIT_EWSW[23]) );
AOI22X1TS U2893 ( .A0(n2174), .A1(n2259), .B0(n2447), .B1(n2166), .Y(
DMP_INIT_EWSW[24]) );
AOI22X1TS U2894 ( .A0(n2171), .A1(n2379), .B0(n2444), .B1(n2166), .Y(
DMP_INIT_EWSW[25]) );
AOI22X1TS U2895 ( .A0(n2174), .A1(n2256), .B0(n2443), .B1(n2173), .Y(
DMP_INIT_EWSW[26]) );
AOI22X1TS U2896 ( .A0(n2174), .A1(n881), .B0(n2455), .B1(n2173), .Y(
DMP_INIT_EWSW[27]) );
AOI22X1TS U2897 ( .A0(n2171), .A1(n2375), .B0(n2441), .B1(n2173), .Y(
DMP_INIT_EWSW[28]) );
AOI22X1TS U2898 ( .A0(n2171), .A1(n890), .B0(n2436), .B1(n2173), .Y(
DMP_INIT_EWSW[29]) );
AOI22X1TS U2899 ( .A0(n2174), .A1(n876), .B0(n2458), .B1(n2175), .Y(
DMP_INIT_EWSW[30]) );
AOI22X1TS U2900 ( .A0(n2174), .A1(n2380), .B0(n2430), .B1(n2175), .Y(
DMP_INIT_EWSW[31]) );
AOI22X1TS U2901 ( .A0(n2171), .A1(n2268), .B0(n2469), .B1(n2175), .Y(
DMP_INIT_EWSW[32]) );
INVX4TS U2902 ( .A(n2175), .Y(n2179) );
AOI22X1TS U2903 ( .A0(n2179), .A1(n2396), .B0(n2428), .B1(n2175), .Y(
DMP_INIT_EWSW[33]) );
AOI22X1TS U2904 ( .A0(n2179), .A1(n877), .B0(n2459), .B1(n2175), .Y(
DMP_INIT_EWSW[34]) );
AOI22X1TS U2905 ( .A0(n2179), .A1(n2381), .B0(n2431), .B1(n2175), .Y(
DMP_INIT_EWSW[35]) );
AOI22X1TS U2906 ( .A0(n2179), .A1(n2368), .B0(n2442), .B1(n2175), .Y(
DMP_INIT_EWSW[36]) );
AOI22X1TS U2907 ( .A0(n2179), .A1(n2387), .B0(n2476), .B1(n2175), .Y(
DMP_INIT_EWSW[37]) );
AOI22X1TS U2908 ( .A0(n2179), .A1(n2388), .B0(n2477), .B1(n2175), .Y(
DMP_INIT_EWSW[38]) );
AOI22X1TS U2909 ( .A0(n2179), .A1(n2272), .B0(n2405), .B1(n2175), .Y(
DMP_INIT_EWSW[39]) );
AOI22X1TS U2910 ( .A0(n2179), .A1(n2262), .B0(n2462), .B1(n2175), .Y(
DMP_INIT_EWSW[40]) );
AOI22X1TS U2911 ( .A0(n2179), .A1(n891), .B0(n2437), .B1(n2162), .Y(
DMP_INIT_EWSW[41]) );
AOI22X1TS U2912 ( .A0(n2179), .A1(n874), .B0(n2452), .B1(n2162), .Y(
DMP_INIT_EWSW[42]) );
AOI22X1TS U2913 ( .A0(n2179), .A1(n2264), .B0(n2432), .B1(n2162), .Y(
DMP_INIT_EWSW[43]) );
AOI22X1TS U2914 ( .A0(n2179), .A1(n2393), .B0(n2464), .B1(n2162), .Y(
DMP_INIT_EWSW[44]) );
AOI22X1TS U2915 ( .A0(n2179), .A1(n2397), .B0(n2453), .B1(n2162), .Y(
DMP_INIT_EWSW[45]) );
INVX4TS U2916 ( .A(n2175), .Y(n2178) );
AOI22X1TS U2917 ( .A0(n2178), .A1(n2403), .B0(n2471), .B1(n2176), .Y(
DMP_INIT_EWSW[46]) );
AOI22X1TS U2918 ( .A0(n2178), .A1(n2270), .B0(n2481), .B1(n2176), .Y(
DMP_INIT_EWSW[47]) );
AOI22X1TS U2919 ( .A0(n2178), .A1(n2400), .B0(n2466), .B1(n2162), .Y(
DMP_INIT_EWSW[48]) );
AOI22X1TS U2920 ( .A0(n2178), .A1(n2391), .B0(n2449), .B1(n2162), .Y(
DMP_INIT_EWSW[49]) );
AOI22X1TS U2921 ( .A0(n2178), .A1(n2265), .B0(n2438), .B1(n2162), .Y(
DMP_INIT_EWSW[50]) );
AOI22X1TS U2922 ( .A0(n2178), .A1(n2394), .B0(n2468), .B1(n2176), .Y(
DMP_INIT_EWSW[51]) );
AOI22X1TS U2923 ( .A0(n2178), .A1(n2401), .B0(n2467), .B1(n2176), .Y(
DMP_INIT_EWSW[52]) );
AOI22X1TS U2924 ( .A0(n2178), .A1(n2392), .B0(n2426), .B1(n2176), .Y(
DMP_INIT_EWSW[53]) );
AOI22X1TS U2925 ( .A0(n2178), .A1(n2402), .B0(n2451), .B1(n2176), .Y(
DMP_INIT_EWSW[54]) );
AOI22X1TS U2926 ( .A0(n2178), .A1(n2267), .B0(n2427), .B1(n2176), .Y(
DMP_INIT_EWSW[55]) );
AOI22X1TS U2927 ( .A0(n2178), .A1(n2269), .B0(n2460), .B1(n2176), .Y(
DMP_INIT_EWSW[56]) );
AOI22X1TS U2928 ( .A0(n2178), .A1(n2398), .B0(n2454), .B1(n2176), .Y(
DMP_INIT_EWSW[57]) );
AO22XLTS U2929 ( .A0(n2179), .A1(intDX_EWSW[61]), .B0(n2162), .B1(
intDY_EWSW[61]), .Y(DMP_INIT_EWSW[61]) );
OR2X1TS U2930 ( .A(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(DMP_INIT_EWSW[62]) );
OAI22X1TS U2931 ( .A0(n2182), .A1(n2195), .B0(n2181), .B1(n2199), .Y(
Data_array_SWR[53]) );
OAI222X1TS U2932 ( .A0(n2189), .A1(n2182), .B0(n2195), .B1(n2181), .C0(n2199), .C1(n2180), .Y(Data_array_SWR[52]) );
AOI22X1TS U2933 ( .A0(Shift_reg_FLAGS_7[1]), .A1(n887), .B0(
DmP_mant_SHT1_SW[25]), .B1(n915), .Y(n2186) );
OAI222X1TS U2934 ( .A0(n2197), .A1(n2191), .B0(n835), .B1(n2190), .C0(n2189),
.C1(n2188), .Y(Data_array_SWR[26]) );
OAI222X1TS U2935 ( .A0(n2199), .A1(n2198), .B0(n2197), .B1(n2196), .C0(n2195), .C1(n2194), .Y(Data_array_SWR[24]) );
BUFX3TS U2936 ( .A(n2200), .Y(n2201) );
CLKAND2X2TS U2937 ( .A(n2201), .B(sftr_odat_SHT2_SWR[2]), .Y(
formatted_number_W[0]) );
CLKAND2X2TS U2938 ( .A(n2201), .B(sftr_odat_SHT2_SWR[3]), .Y(
formatted_number_W[1]) );
CLKAND2X2TS U2939 ( .A(n2201), .B(sftr_odat_SHT2_SWR[4]), .Y(
formatted_number_W[2]) );
CLKAND2X2TS U2940 ( .A(n2201), .B(sftr_odat_SHT2_SWR[5]), .Y(
formatted_number_W[3]) );
CLKAND2X2TS U2941 ( .A(n2201), .B(sftr_odat_SHT2_SWR[6]), .Y(
formatted_number_W[4]) );
CLKAND2X2TS U2942 ( .A(n2201), .B(sftr_odat_SHT2_SWR[7]), .Y(
formatted_number_W[5]) );
CLKAND2X2TS U2943 ( .A(n2201), .B(sftr_odat_SHT2_SWR[8]), .Y(
formatted_number_W[6]) );
CLKAND2X2TS U2944 ( .A(n2201), .B(sftr_odat_SHT2_SWR[9]), .Y(
formatted_number_W[7]) );
CLKAND2X2TS U2945 ( .A(n2201), .B(sftr_odat_SHT2_SWR[10]), .Y(
formatted_number_W[8]) );
CLKAND2X2TS U2946 ( .A(n2201), .B(sftr_odat_SHT2_SWR[11]), .Y(
formatted_number_W[9]) );
CLKAND2X2TS U2947 ( .A(n2201), .B(sftr_odat_SHT2_SWR[12]), .Y(
formatted_number_W[10]) );
CLKAND2X2TS U2948 ( .A(n2201), .B(sftr_odat_SHT2_SWR[13]), .Y(
formatted_number_W[11]) );
BUFX3TS U2949 ( .A(n2200), .Y(n2203) );
CLKAND2X2TS U2950 ( .A(n2203), .B(sftr_odat_SHT2_SWR[14]), .Y(
formatted_number_W[12]) );
CLKAND2X2TS U2951 ( .A(n2203), .B(sftr_odat_SHT2_SWR[15]), .Y(
formatted_number_W[13]) );
CLKAND2X2TS U2952 ( .A(n2203), .B(sftr_odat_SHT2_SWR[16]), .Y(
formatted_number_W[14]) );
CLKAND2X2TS U2953 ( .A(n2203), .B(sftr_odat_SHT2_SWR[17]), .Y(
formatted_number_W[15]) );
CLKAND2X2TS U2954 ( .A(n2203), .B(sftr_odat_SHT2_SWR[18]), .Y(
formatted_number_W[16]) );
CLKAND2X2TS U2955 ( .A(n2203), .B(sftr_odat_SHT2_SWR[19]), .Y(
formatted_number_W[17]) );
CLKAND2X2TS U2956 ( .A(n2203), .B(sftr_odat_SHT2_SWR[20]), .Y(
formatted_number_W[18]) );
CLKAND2X2TS U2957 ( .A(n2203), .B(sftr_odat_SHT2_SWR[21]), .Y(
formatted_number_W[19]) );
CLKAND2X2TS U2958 ( .A(n2203), .B(sftr_odat_SHT2_SWR[22]), .Y(
formatted_number_W[20]) );
CLKAND2X2TS U2959 ( .A(n2203), .B(sftr_odat_SHT2_SWR[23]), .Y(
formatted_number_W[21]) );
CLKAND2X2TS U2960 ( .A(n2203), .B(sftr_odat_SHT2_SWR[24]), .Y(
formatted_number_W[22]) );
CLKAND2X2TS U2961 ( .A(n2203), .B(sftr_odat_SHT2_SWR[25]), .Y(
formatted_number_W[23]) );
BUFX3TS U2962 ( .A(n2200), .Y(n2204) );
CLKAND2X2TS U2963 ( .A(n2204), .B(sftr_odat_SHT2_SWR[26]), .Y(
formatted_number_W[24]) );
CLKAND2X2TS U2964 ( .A(n2204), .B(sftr_odat_SHT2_SWR[27]), .Y(
formatted_number_W[25]) );
CLKAND2X2TS U2965 ( .A(n2204), .B(sftr_odat_SHT2_SWR[28]), .Y(
formatted_number_W[26]) );
CLKAND2X2TS U2966 ( .A(n2204), .B(sftr_odat_SHT2_SWR[29]), .Y(
formatted_number_W[27]) );
CLKAND2X2TS U2967 ( .A(n2204), .B(sftr_odat_SHT2_SWR[30]), .Y(
formatted_number_W[28]) );
CLKAND2X2TS U2968 ( .A(n2204), .B(sftr_odat_SHT2_SWR[31]), .Y(
formatted_number_W[29]) );
CLKAND2X2TS U2969 ( .A(n2204), .B(sftr_odat_SHT2_SWR[32]), .Y(
formatted_number_W[30]) );
CLKAND2X2TS U2970 ( .A(n2204), .B(sftr_odat_SHT2_SWR[33]), .Y(
formatted_number_W[31]) );
CLKAND2X2TS U2971 ( .A(n2204), .B(sftr_odat_SHT2_SWR[34]), .Y(
formatted_number_W[32]) );
CLKAND2X2TS U2972 ( .A(n2204), .B(sftr_odat_SHT2_SWR[35]), .Y(
formatted_number_W[33]) );
CLKAND2X2TS U2973 ( .A(n2204), .B(sftr_odat_SHT2_SWR[36]), .Y(
formatted_number_W[34]) );
CLKAND2X2TS U2974 ( .A(n2204), .B(sftr_odat_SHT2_SWR[37]), .Y(
formatted_number_W[35]) );
BUFX3TS U2975 ( .A(n2200), .Y(n2202) );
CLKAND2X2TS U2976 ( .A(n2202), .B(sftr_odat_SHT2_SWR[38]), .Y(
formatted_number_W[36]) );
CLKAND2X2TS U2977 ( .A(n2202), .B(sftr_odat_SHT2_SWR[39]), .Y(
formatted_number_W[37]) );
CLKAND2X2TS U2978 ( .A(n2202), .B(sftr_odat_SHT2_SWR[40]), .Y(
formatted_number_W[38]) );
CLKAND2X2TS U2979 ( .A(n2202), .B(sftr_odat_SHT2_SWR[41]), .Y(
formatted_number_W[39]) );
CLKAND2X2TS U2980 ( .A(n2202), .B(sftr_odat_SHT2_SWR[42]), .Y(
formatted_number_W[40]) );
CLKAND2X2TS U2981 ( .A(n2202), .B(sftr_odat_SHT2_SWR[43]), .Y(
formatted_number_W[41]) );
CLKAND2X2TS U2982 ( .A(n2202), .B(sftr_odat_SHT2_SWR[44]), .Y(
formatted_number_W[42]) );
CLKAND2X2TS U2983 ( .A(n2202), .B(sftr_odat_SHT2_SWR[45]), .Y(
formatted_number_W[43]) );
CLKAND2X2TS U2984 ( .A(n2202), .B(sftr_odat_SHT2_SWR[46]), .Y(
formatted_number_W[44]) );
CLKAND2X2TS U2985 ( .A(n2202), .B(sftr_odat_SHT2_SWR[47]), .Y(
formatted_number_W[45]) );
CLKAND2X2TS U2986 ( .A(n2202), .B(sftr_odat_SHT2_SWR[48]), .Y(
formatted_number_W[46]) );
CLKAND2X2TS U2987 ( .A(n2202), .B(sftr_odat_SHT2_SWR[49]), .Y(
formatted_number_W[47]) );
CLKAND2X2TS U2988 ( .A(n2201), .B(sftr_odat_SHT2_SWR[50]), .Y(
formatted_number_W[48]) );
CLKAND2X2TS U2989 ( .A(n2202), .B(sftr_odat_SHT2_SWR[51]), .Y(
formatted_number_W[49]) );
CLKAND2X2TS U2990 ( .A(n2203), .B(sftr_odat_SHT2_SWR[52]), .Y(
formatted_number_W[50]) );
CLKAND2X2TS U2991 ( .A(n2204), .B(sftr_odat_SHT2_SWR[53]), .Y(
formatted_number_W[51]) );
AO22XLTS U2992 ( .A0(n2221), .A1(LZD_raw_out_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n915), .Y(shft_value_mux_o_EWR[2]) );
INVX2TS U2993 ( .A(n2205), .Y(n2206) );
OAI31X1TS U2994 ( .A0(n2208), .A1(Raw_mant_NRM_SWR[47]), .A2(n2207), .B0(
n2206), .Y(n2209) );
OAI211XLTS U2995 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n2214), .B0(n2213), .C0(
n2212), .Y(n2215) );
AOI211XLTS U2996 ( .A0(n2217), .A1(n882), .B0(n2216), .C0(n2215), .Y(n2219)
);
AO22XLTS U2997 ( .A0(n2534), .A1(LZD_raw_out_EWR[3]), .B0(
Shift_amount_SHT1_EWR[3]), .B1(n915), .Y(shft_value_mux_o_EWR[3]) );
AO22XLTS U2998 ( .A0(n2221), .A1(LZD_raw_out_EWR[4]), .B0(
Shift_amount_SHT1_EWR[4]), .B1(n915), .Y(shft_value_mux_o_EWR[4]) );
AO22XLTS U2999 ( .A0(n2534), .A1(LZD_raw_out_EWR[5]), .B0(
Shift_amount_SHT1_EWR[5]), .B1(n915), .Y(shft_value_mux_o_EWR[5]) );
AOI22X1TS U3001 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n2470), .B0(
beg_OP), .B1(n873), .Y(n2223) );
OAI22X1TS U3002 ( .A0(n2224), .A1(n2223), .B0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n2222), .Y(n831) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule |
module MemFaces(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[799:0]" */;
input clka;
input [9:0]addra;
output [799:0]douta;
endmodule |
module sky130_fd_sc_hd__and4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module tmu2_hinterp(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input diff_x_positive,
input [16:0] diff_x_q,
input [16:0] diff_x_r,
input diff_y_positive,
input [16:0] diff_y_q,
input [16:0] diff_y_r,
input [10:0] dst_squarew,
output pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] dx,
output reg signed [11:0] dy,
output signed [17:0] tx,
output signed [17:0] ty
);
reg load;
reg next_point;
/* Interpolators */
tmu2_geninterp18 i_tx(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(tsx),
.positive(diff_x_positive),
.q(diff_x_q),
.r(diff_x_r),
.divisor({6'd0, dst_squarew}),
.o(tx)
);
tmu2_geninterp18 i_ty(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(tsy),
.positive(diff_y_positive),
.q(diff_y_q),
.r(diff_y_r),
.divisor({6'd0, dst_squarew}),
.o(ty)
);
always @(posedge sys_clk) begin
if(load) begin
dx <= x;
dy <= y;
end else if(next_point)
dx <= dx + 12'd1;
end
/* Controller */
reg [10:0] remaining_points;
always @(posedge sys_clk) begin
if(load)
remaining_points <= dst_squarew - 11'd1;
else if(next_point)
remaining_points <= remaining_points - 11'd1;
end
wire last_point = remaining_points == 11'd0;
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter BUSY = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
assign busy = state;
assign pipe_ack_o = ~state;
assign pipe_stb_o = state;
always @(*) begin
next_state = state;
load = 1'b0;
next_point = 1'b0;
case(state)
IDLE: begin
if(pipe_stb_i) begin
load = 1'b1;
next_state = BUSY;
end
end
BUSY: begin
if(pipe_ack_i) begin
if(last_point)
next_state = IDLE;
else
next_point = 1'b1;
end
end
endcase
end
endmodule |
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module prio_enc #(
parameter WIDTH_LOG = 4
) (x, msb);
localparam WIDTH = 1 << WIDTH_LOG;
localparam HI = WIDTH - 1;
input [HI:0] x;
`define FAST_1
//`define FAST_2
//`define SLOW
`ifdef FAST_1
// This seems to compile to most cost-efficient
// implementation across all toolchains.
output reg [WIDTH_LOG - 1:0] msb;
integer i, width;
reg [HI:0] part;
always @* begin
msb = 0;
part = x;
for (i = WIDTH_LOG - 1; i >= 0; i = i - 1) begin
width = 1 << i;
if (|(part >> width))
msb[i] = 1;
// Hopefully synthesizer understands that 'part' is shrinking...
part = msb[i] ? part >> width : part & ((1'd1 << width) - 1'd1);
end
end
`endif
`ifdef FAST_2
// The most low-level implementation. Surprinsingly it's not always
// the fastest...
output [WIDTH_LOG - 1:0] msb;
wire [WIDTH_LOG*WIDTH - 1:0] ors;
assign ors[WIDTH_LOG*WIDTH - 1:(WIDTH_LOG - 1)*WIDTH] = x;
genvar w, i;
integer j;
generate
for (w = WIDTH_LOG - 1; w >= 0; w = w - 1) begin
assign msb[w] = |ors[w*WIDTH + 2*(1 << w) - 1:w*WIDTH + (1 << w)];
if (w > 0) begin
assign ors[(w - 1)*WIDTH + (1 << w) - 1:(w - 1)*WIDTH] = msb[w] ? ors[w*WIDTH + 2*(1 << w) - 1:w*WIDTH + (1 << w)] : ors[w*WIDTH + (1 << w) - 1:w*WIDTH];
end
end
endgenerate
`endif
`ifdef SLOW
// Slow but simple. Some synthesizers are able
// to generate good RTL from this but not all.
output reg [WIDTH_LOG - 1:0] msb;
integer i;
always @* begin
msb = 0;
for (i = HI; i >= 0; i = i - 1)
if (!msb && x[i])
msb = i;
end
`endif
`ifdef SIM
// initial
// $monitor("%t: x=%b, msb=%b, ors=%b", $time, x, msb, ors);
`endif
endmodule |
module sky130_fd_sc_ls__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM, A, B, ci );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule |
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule |
module outputs)
wire amode; // From mio_regs of mio_regs.v
wire clkchange; // From mio_regs of mio_regs.v
wire [7:0] clkdiv; // From mio_regs of mio_regs.v
wire [15:0] clkphase0; // From mio_regs of mio_regs.v
wire [15:0] clkphase1; // From mio_regs of mio_regs.v
wire [4:0] ctrlmode; // From mio_regs of mio_regs.v
wire [7:0] datasize; // From mio_regs of mio_regs.v
wire ddr_mode; // From mio_regs of mio_regs.v
wire [AW-1:0] dstaddr; // From mio_regs of mio_regs.v
wire emode; // From mio_regs of mio_regs.v
wire framepol; // From mio_regs of mio_regs.v
wire io_clk; // From oh_clockdiv of oh_clockdiv.v
wire lsbfirst; // From mio_regs of mio_regs.v
wire rx_access_io2c; // From mio_dp of mio_dp.v
wire rx_empty; // From mio_dp of mio_dp.v
wire rx_en; // From mio_regs of mio_regs.v
wire rx_full; // From mio_dp of mio_dp.v
wire [MPW-1:0] rx_packet_io2c; // From mio_dp of mio_dp.v
wire rx_prog_full; // From mio_dp of mio_dp.v
wire rx_wait_c2io; // From mio_if of mio_if.v
wire tx_access_c2io; // From mio_if of mio_if.v
wire tx_empty; // From mio_dp of mio_dp.v
wire tx_en; // From mio_regs of mio_regs.v
wire tx_full; // From mio_dp of mio_dp.v
wire [MPW-1:0] tx_packet_c2io; // From mio_if of mio_if.v
wire tx_prog_full; // From mio_dp of mio_dp.v
wire tx_wait_io2c; // From mio_dp of mio_dp.v
// End of automatics
//################################
//# CONFIGURATION REGISTERS
//################################
/*mio_regs AUTO_TEMPLATE (.\(.*\)_out (reg_\1_out[]),
.\(.*\)_in (reg_\1_in[]),
);
*/
mio_regs #(.AW(AW),
.PW(PW),
.DEF_CFG(DEF_CFG),
.DEF_CLK(DEF_CLK))
mio_regs (.dmode (),
/*AUTOINST*/
// Outputs
.wait_out (reg_wait_out), // Templated
.access_out (reg_access_out), // Templated
.packet_out (reg_packet_out[PW-1:0]), // Templated
.tx_en (tx_en),
.rx_en (rx_en),
.ddr_mode (ddr_mode),
.emode (emode),
.amode (amode),
.datasize (datasize[7:0]),
.lsbfirst (lsbfirst),
.framepol (framepol),
.ctrlmode (ctrlmode[4:0]),
.dstaddr (dstaddr[AW-1:0]),
.clkchange (clkchange),
.clkdiv (clkdiv[7:0]),
.clkphase0 (clkphase0[15:0]),
.clkphase1 (clkphase1[15:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.access_in (reg_access_in), // Templated
.packet_in (reg_packet_in[PW-1:0]), // Templated
.wait_in (reg_wait_in), // Templated
.tx_full (tx_full),
.tx_prog_full (tx_prog_full),
.tx_empty (tx_empty),
.rx_full (rx_full),
.rx_prog_full (rx_prog_full),
.rx_empty (rx_empty));
//################################
//# TX CLOCK DRIVER
//################################
/*oh_clockdiv AUTO_TEMPLATE (
.clkout0 (io_clk),
.clkout1 (tx_clk),
.clken (tx_en),
);
*/
oh_clockdiv oh_clockdiv(.clkrise0 (),
.clkfall0 (),
.clkrise1 (),
.clkfall1 (),
.clkstable (),
/*AUTOINST*/
// Outputs
.clkout0 (io_clk), // Templated
.clkout1 (tx_clk), // Templated
// Inputs
.clk (clk),
.nreset (nreset),
.clkchange (clkchange),
.clken (tx_en), // Templated
.clkdiv (clkdiv[7:0]),
.clkphase0 (clkphase0[15:0]),
.clkphase1 (clkphase1[15:0]));
//################################
//# DATAPATH
//################################
/*mio_dp AUTO_TEMPLATE (.wait_in (rx_wait_c2io),
.wait_out (tx_wait_io2c),
.packet_out (rx_packet_io2c[MPW-1:0]),
.packet_in (tx_packet_c2io[MPW-1:0]),
.access_in (tx_access_c2io),
.\(.*\)_out (rx_\1_io2c[]),
);
*/
mio_dp #(.TARGET(TARGET),
.NMIO(NMIO),
.PW(MPW))
mio_dp(/*AUTOINST*/
// Outputs
.tx_full (tx_full),
.tx_prog_full (tx_prog_full),
.tx_empty (tx_empty),
.rx_full (rx_full),
.rx_prog_full (rx_prog_full),
.rx_empty (rx_empty),
.tx_access (tx_access),
.tx_packet (tx_packet[NMIO-1:0]),
.rx_wait (rx_wait),
.wait_out (tx_wait_io2c), // Templated
.access_out (rx_access_io2c), // Templated
.packet_out (rx_packet_io2c[MPW-1:0]), // Templated
// Inputs
.clk (clk),
.io_clk (io_clk),
.nreset (nreset),
.datasize (datasize[7:0]),
.ddr_mode (ddr_mode),
.lsbfirst (lsbfirst),
.framepol (framepol),
.tx_en (tx_en),
.rx_en (rx_en),
.tx_wait (tx_wait),
.rx_clk (rx_clk),
.rx_access (rx_access),
.rx_packet (rx_packet[NMIO-1:0]),
.access_in (tx_access_c2io), // Templated
.packet_in (tx_packet_c2io[MPW-1:0]), // Templated
.wait_in (rx_wait_c2io)); // Templated
//################################
//# MIO INTERFACE
//################################
/*mio_if AUTO_TEMPLATE (
.\(.*\)_\(.*\)_out (\1_\2_c2io[]),
.\(.*\)_\(.*\)_in (\1_\2_io2c[]),
);
*/
mio_if #(.AW(AW),
.PW(PW),
.MPW(MPW))
mio_if (
/*AUTOINST*/
// Outputs
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
.wait_out (wait_out),
.rx_wait_out (rx_wait_c2io), // Templated
.tx_access_out (tx_access_c2io), // Templated
.tx_packet_out (tx_packet_c2io[MPW-1:0]), // Templated
// Inputs
.clk (clk),
.nreset (nreset),
.amode (amode),
.emode (emode),
.lsbfirst (lsbfirst),
.datasize (datasize[7:0]),
.ctrlmode (ctrlmode[4:0]),
.dstaddr (dstaddr[AW-1:0]),
.wait_in (wait_in),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.rx_access_in (rx_access_io2c), // Templated
.rx_packet_in (rx_packet_io2c[MPW-1:0]), // Templated
.tx_wait_in (tx_wait_io2c)); // Templated
endmodule |
module ram_8x512_hi(
addr,
clk,
din,
dout,
en,
we);
input [8 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;
// synthesis translate_off
BLKMEMSP_V6_2 #(
.c_addr_width(9),
.c_default_data("0"),
.c_depth(512),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_din(1),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(0),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(0),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.EN(en),
.WE(we),
.ND(),
.RFD(),
.RDY(),
.SINIT());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of ram_8x512_hi is "black_box"
endmodule |
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ms__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module test_axis_srl_fifo;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
count);
// dump file
$dumpfile("test_axis_srl_fifo.lxt");
$dumpvars(0, test_axis_srl_fifo);
end
axis_srl_fifo #(
.DEPTH(4),
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Status
.count(count)
);
endmodule |
module IBUFDS_DPHY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter SIM_DEVICE = "ULTRASCALE_PLUS"
)(
output HSRX_O,
output LPRX_O_N,
output LPRX_O_P,
input HSRX_DISABLE,
input I,
input IB,
input LPRX_DISABLE
);
// define constants
localparam MODULE_NAME = "IBUFDS_DPHY";
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 1;
localparam DIFF_TERM_TRUE = 0;
localparam IOSTANDARD_DEFAULT = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IBUFDS_DPHY_dr.v"
`else
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
`endif
wire DIFF_TERM_BIN;
wire IOSTANDARD_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire HSRX_O_out;
wire LPRX_O_N_out;
wire LPRX_O_P_out;
wire HSRX_DISABLE_in;
wire IB_in;
wire I_in;
wire LPRX_DISABLE_in;
assign HSRX_O = HSRX_O_out;
assign LPRX_O_N = LPRX_O_N_out;
assign LPRX_O_P = LPRX_O_P_out;
assign HSRX_DISABLE_in = HSRX_DISABLE;
assign IB_in = IB;
assign I_in = I;
assign LPRX_DISABLE_in = LPRX_DISABLE;
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_TRUE;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DIFF_TERM_REG != "TRUE") &&
(DIFF_TERM_REG != "FALSE"))) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE != "ULTRASCALE_PLUS") &&
(SIM_DEVICE != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE != "ULTRASCALE_PLUS_ES2") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2"))) begin
$display("Error: [Unisim %s-102] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
attr_err = 1'b1;
end
// no check
// if ((attr_test == 1'b1) ||
// ((IOSTANDARD_REG != "DEFAULT"))) begin
// $display("Error: [Unisim %s-102] IOSTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, IOSTANDARD_REG);
// attr_err = 1'b1;
// end
if (attr_err == 1'b1) #1 $finish;
end
reg o_out;
wire [1:0] lp_out;
wire sim_mode;
wire lp_mode;
wire lp_rx_disable;
wire hs_mode;
wire hs_out;
reg [3*8:1] strP,strN;
always @(*)
begin
$sformat(strP, "%v", I);
$sformat(strN, "%v", IB);
end
assign lp_mode = (strP[24:17] == "S") & (strN[24:17] == "S"); // For LP strength type Strong
//assign sim_mode = (SIM_DEVICE == "ULTRASCALE_PLUS" || SIM_DEVICE== "ULTRASCALE_PLUS_ES1" || SIM_DEVICE== "ULTRASCALE_PLUS_ES2") ? 1'b0 : 1'b0;
assign sim_mode = 1'b0;
assign #1 lp_out[0] = lp_mode === 1'b1 ? I_in : 1'b0;
assign #1 lp_out[1] = lp_mode === 1'b1 ? IB_in : 1'b0;
assign HSRX_O_out = (HSRX_DISABLE_in === 1'b0) ? o_out : (HSRX_DISABLE_in === 1'bx || HSRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0;
assign LPRX_O_N_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[1] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : sim_mode;
assign LPRX_O_P_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[0] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : sim_mode;
always @ (I_in or IB_in) begin
if (I_in == 1'b1 && IB_in == 1'b0)
o_out <= 1'b1;
else if (I_in == 1'b0 && IB_in == 1'b1)
o_out <= 1'b0;
else if ((I_in === 1'bx) || (IB_in === 1'bx) || I_in === 1'bz || IB_in === 1'bz )
o_out <= 1'bx;
end
endmodule |
module nukv_Predicate_Eval_Pipeline_v2 #(
parameter MEMORY_WIDTH = 512,
parameter META_WIDTH = 96,
parameter GENERATE_COMMANDS = 1,
parameter SUPPORT_SCANS = 0,
parameter PIPE_DEPTH = 1
)
(
// Clock
input wire clk,
input wire rst,
input wire [META_WIDTH+MEMORY_WIDTH-1:0] pred_data,
input wire pred_valid,
input wire pred_scan,
output wire pred_ready,
input wire [MEMORY_WIDTH-1:0] value_data,
input wire value_valid,
input wire value_last,
input wire value_drop,
output wire value_ready,
output wire [MEMORY_WIDTH-1:0] output_data,
output wire output_valid,
output wire output_last,
output wire output_drop,
input wire output_ready,
input scan_on_outside,
output wire cmd_valid,
output wire[15:0] cmd_length,
output wire[META_WIDTH-1:0] cmd_meta,
input wire cmd_ready,
output wire error_input
);
localparam MAX_DEPTH = 9;
wire[META_WIDTH+MEMORY_WIDTH-1:0] prarr_data [0:MAX_DEPTH-1];
wire[MAX_DEPTH-1:0] prarr_valid ;
wire[MAX_DEPTH-1:0] prarr_scan ;
wire[MAX_DEPTH-1:0] prarr_ready ;
wire[MAX_DEPTH-1:0] prarr_in_ready ;
wire [MEMORY_WIDTH-1:0] varr_data [0:MAX_DEPTH];
wire [MAX_DEPTH:0] varr_valid;
wire [MAX_DEPTH:0] varr_last;
wire [MAX_DEPTH:0] varr_drop;
wire [MAX_DEPTH:0] varr_ready;
assign varr_data[0] = value_data;
assign varr_valid[0] = value_valid;
assign varr_last[0] = value_last;
assign varr_drop[0] = value_drop;
assign value_ready = varr_ready[0];
assign output_data = varr_data[MAX_DEPTH];
assign output_valid = varr_valid[MAX_DEPTH];
assign output_last = varr_last[MAX_DEPTH];
assign output_drop = varr_drop[MAX_DEPTH];
assign varr_ready[MAX_DEPTH] = output_ready;
assign pred_ready = &prarr_in_ready;
generate
genvar i;
for (i=0; i<MAX_DEPTH; i=i+1) begin
if (i<PIPE_DEPTH-1) begin
nukv_fifogen #(
.DATA_SIZE(48+96+1),
.ADDR_BITS(7)
) fifo_predconfig (
.clk(clk),
.rst(rst),
.s_axis_tdata({pred_data[META_WIDTH+i*48 +: 48],pred_data[META_WIDTH-1:0], pred_scan}),
.s_axis_tvalid(pred_valid & pred_ready),
.s_axis_tready(prarr_in_ready[i]),
.m_axis_tdata({prarr_data[i],prarr_scan[i]}),
.m_axis_tvalid(prarr_valid[i]),
.m_axis_tready(prarr_ready[i])
);
nukv_Predicate_Eval #(.SUPPORT_SCANS(SUPPORT_SCANS))
pred_eval
(
.clk(clk),
.rst(rst),
.pred_data(prarr_data[i]),
.pred_valid(prarr_valid[i]),
.pred_ready(prarr_ready[i]),
.pred_scan((SUPPORT_SCANS==1) ? prarr_scan[i] : 0),
.value_data(varr_data[i]),
.value_last(varr_last[i]),
.value_drop(varr_drop[i]),
.value_valid(varr_valid[i]),
.value_ready(varr_ready[i]),
.output_valid(varr_valid[i+1]),
.output_ready(varr_ready[i+1]),
.output_data(varr_data[i+1]),
.output_last(varr_last[i+1]),
.output_drop(varr_drop[i+1]),
.scan_on_outside(scan_on_outside)
);
end else if (i==PIPE_DEPTH-1) begin
nukv_fifogen #(
.DATA_SIZE(48+96+1),
.ADDR_BITS(7)
) fifo_predconfig (
.clk(clk),
.rst(rst),
.s_axis_tdata({pred_data[META_WIDTH+i*48 +: 48],pred_data[META_WIDTH-1:0], pred_scan}),
.s_axis_tvalid(pred_valid & pred_ready),
.s_axis_tready(prarr_in_ready[i]),
.m_axis_tdata({prarr_data[i],prarr_scan[i]}),
.m_axis_tvalid(prarr_valid[i]),
.m_axis_tready(prarr_ready[i])
);
nukv_Predicate_Eval #(.SUPPORT_SCANS(SUPPORT_SCANS))
pred_eval
(
.clk(clk),
.rst(rst),
.pred_data(prarr_data[i]),
.pred_valid(prarr_valid[i]),
.pred_ready(prarr_ready[i]),
.pred_scan((SUPPORT_SCANS==1) ? prarr_scan[i] : 0),
.value_data(varr_data[i]),
.value_last(varr_last[i]),
.value_drop(varr_drop[i]),
.value_valid(varr_valid[i]),
.value_ready(varr_ready[i]),
.output_valid(varr_valid[i+1]),
.output_ready(varr_ready[i+1]),
.output_data(varr_data[i+1]),
.output_last(varr_last[i+1]),
.output_drop(varr_drop[i+1]),
.scan_on_outside(scan_on_outside),
.error_input (error_input),
.cmd_valid (cmd_valid),
.cmd_length (cmd_length),
.cmd_meta (cmd_meta),
.cmd_ready (cmd_ready)
);
end else begin
assign prarr_in_ready[i] = 1;
assign varr_data[i+1] = varr_data[i];
assign varr_valid[i+1] = varr_valid[i];
assign varr_last[i+1] = varr_last[i];
assign varr_drop[i+1] = varr_drop[i];
assign varr_ready[i] = varr_ready[i+1];
end
end
endgenerate
endmodule |
module CORDIC_Arch3
(clk,
rst,
beg_fsm_cordic,
ack_cordic,
operation,
data_in,
shift_region_flag,
ready_cordic,
overflow_flag,
underflow_flag,
zero_flag,
busy,
data_output);
input clk;
input rst;
input beg_fsm_cordic;
input ack_cordic;
input operation;
input [31:0]data_in;
input [1:0]shift_region_flag;
output ready_cordic;
output overflow_flag;
output underflow_flag;
output zero_flag;
output busy;
output [31:0]data_output;
wire [7:0]A;
wire ITER_CONT_n_10;
wire ITER_CONT_n_100;
wire ITER_CONT_n_104;
wire ITER_CONT_n_107;
wire ITER_CONT_n_108;
wire ITER_CONT_n_109;
wire ITER_CONT_n_11;
wire ITER_CONT_n_118;
wire ITER_CONT_n_119;
wire ITER_CONT_n_12;
wire ITER_CONT_n_13;
wire ITER_CONT_n_14;
wire ITER_CONT_n_15;
wire ITER_CONT_n_16;
wire ITER_CONT_n_17;
wire ITER_CONT_n_18;
wire ITER_CONT_n_19;
wire ITER_CONT_n_20;
wire ITER_CONT_n_21;
wire ITER_CONT_n_22;
wire ITER_CONT_n_23;
wire ITER_CONT_n_24;
wire ITER_CONT_n_25;
wire ITER_CONT_n_26;
wire ITER_CONT_n_27;
wire ITER_CONT_n_28;
wire ITER_CONT_n_29;
wire ITER_CONT_n_30;
wire ITER_CONT_n_31;
wire ITER_CONT_n_32;
wire ITER_CONT_n_33;
wire ITER_CONT_n_34;
wire ITER_CONT_n_35;
wire ITER_CONT_n_36;
wire ITER_CONT_n_37;
wire ITER_CONT_n_38;
wire ITER_CONT_n_39;
wire ITER_CONT_n_40;
wire ITER_CONT_n_41;
wire ITER_CONT_n_42;
wire ITER_CONT_n_43;
wire ITER_CONT_n_44;
wire ITER_CONT_n_45;
wire ITER_CONT_n_46;
wire ITER_CONT_n_47;
wire ITER_CONT_n_48;
wire ITER_CONT_n_49;
wire ITER_CONT_n_5;
wire ITER_CONT_n_50;
wire ITER_CONT_n_51;
wire ITER_CONT_n_52;
wire ITER_CONT_n_53;
wire ITER_CONT_n_54;
wire ITER_CONT_n_55;
wire ITER_CONT_n_56;
wire ITER_CONT_n_57;
wire ITER_CONT_n_58;
wire ITER_CONT_n_59;
wire ITER_CONT_n_6;
wire ITER_CONT_n_60;
wire ITER_CONT_n_61;
wire ITER_CONT_n_62;
wire ITER_CONT_n_63;
wire ITER_CONT_n_64;
wire ITER_CONT_n_65;
wire ITER_CONT_n_66;
wire ITER_CONT_n_67;
wire ITER_CONT_n_68;
wire ITER_CONT_n_69;
wire ITER_CONT_n_7;
wire ITER_CONT_n_70;
wire ITER_CONT_n_71;
wire ITER_CONT_n_72;
wire ITER_CONT_n_73;
wire ITER_CONT_n_74;
wire ITER_CONT_n_75;
wire ITER_CONT_n_76;
wire ITER_CONT_n_77;
wire ITER_CONT_n_78;
wire ITER_CONT_n_79;
wire ITER_CONT_n_8;
wire ITER_CONT_n_80;
wire ITER_CONT_n_81;
wire ITER_CONT_n_82;
wire ITER_CONT_n_83;
wire ITER_CONT_n_84;
wire ITER_CONT_n_85;
wire ITER_CONT_n_86;
wire ITER_CONT_n_87;
wire ITER_CONT_n_88;
wire ITER_CONT_n_89;
wire ITER_CONT_n_9;
wire ITER_CONT_n_90;
wire ITER_CONT_n_91;
wire ITER_CONT_n_92;
wire ITER_CONT_n_93;
wire ITER_CONT_n_94;
wire ITER_CONT_n_95;
wire ITER_CONT_n_96;
wire ITER_CONT_n_97;
wire ITER_CONT_n_98;
wire ITER_CONT_n_99;
wire VAR_CONT_n_10;
wire VAR_CONT_n_11;
wire VAR_CONT_n_12;
wire VAR_CONT_n_13;
wire VAR_CONT_n_14;
wire VAR_CONT_n_15;
wire VAR_CONT_n_16;
wire VAR_CONT_n_17;
wire VAR_CONT_n_18;
wire VAR_CONT_n_19;
wire VAR_CONT_n_20;
wire VAR_CONT_n_21;
wire VAR_CONT_n_22;
wire VAR_CONT_n_23;
wire VAR_CONT_n_24;
wire VAR_CONT_n_25;
wire VAR_CONT_n_26;
wire VAR_CONT_n_27;
wire VAR_CONT_n_28;
wire VAR_CONT_n_29;
wire VAR_CONT_n_3;
wire VAR_CONT_n_30;
wire VAR_CONT_n_31;
wire VAR_CONT_n_32;
wire VAR_CONT_n_33;
wire VAR_CONT_n_34;
wire VAR_CONT_n_35;
wire VAR_CONT_n_36;
wire VAR_CONT_n_37;
wire VAR_CONT_n_38;
wire VAR_CONT_n_39;
wire VAR_CONT_n_40;
wire VAR_CONT_n_41;
wire VAR_CONT_n_42;
wire VAR_CONT_n_43;
wire VAR_CONT_n_44;
wire VAR_CONT_n_45;
wire VAR_CONT_n_46;
wire VAR_CONT_n_47;
wire VAR_CONT_n_48;
wire VAR_CONT_n_49;
wire VAR_CONT_n_5;
wire VAR_CONT_n_50;
wire VAR_CONT_n_51;
wire VAR_CONT_n_52;
wire VAR_CONT_n_53;
wire VAR_CONT_n_54;
wire VAR_CONT_n_55;
wire VAR_CONT_n_56;
wire VAR_CONT_n_57;
wire VAR_CONT_n_58;
wire VAR_CONT_n_59;
wire VAR_CONT_n_6;
wire VAR_CONT_n_60;
wire VAR_CONT_n_61;
wire VAR_CONT_n_62;
wire VAR_CONT_n_63;
wire VAR_CONT_n_64;
wire VAR_CONT_n_65;
wire VAR_CONT_n_66;
wire VAR_CONT_n_67;
wire VAR_CONT_n_68;
wire VAR_CONT_n_7;
wire VAR_CONT_n_8;
wire VAR_CONT_n_9;
wire [7:0]Y;
wire ack_cordic;
wire ack_cordic_IBUF;
wire beg_fsm_cordic;
wire beg_fsm_cordic_IBUF;
wire busy;
wire busy_OBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire [3:0]cont_iter_out;
wire [1:0]cont_var_out;
wire d_ff1_operation_out;
wire [31:31]d_ff2_Y;
wire [31:31]d_ff2_Z;
wire d_ff3_sign_out;
wire d_ff4_Xn_n_0;
wire d_ff4_Xn_n_1;
wire d_ff4_Xn_n_10;
wire d_ff4_Xn_n_11;
wire d_ff4_Xn_n_12;
wire d_ff4_Xn_n_13;
wire d_ff4_Xn_n_14;
wire d_ff4_Xn_n_15;
wire d_ff4_Xn_n_16;
wire d_ff4_Xn_n_17;
wire d_ff4_Xn_n_18;
wire d_ff4_Xn_n_19;
wire d_ff4_Xn_n_2;
wire d_ff4_Xn_n_20;
wire d_ff4_Xn_n_21;
wire d_ff4_Xn_n_22;
wire d_ff4_Xn_n_23;
wire d_ff4_Xn_n_24;
wire d_ff4_Xn_n_25;
wire d_ff4_Xn_n_26;
wire d_ff4_Xn_n_27;
wire d_ff4_Xn_n_28;
wire d_ff4_Xn_n_29;
wire d_ff4_Xn_n_3;
wire d_ff4_Xn_n_30;
wire d_ff4_Xn_n_31;
wire d_ff4_Xn_n_4;
wire d_ff4_Xn_n_5;
wire d_ff4_Xn_n_6;
wire d_ff4_Xn_n_7;
wire d_ff4_Xn_n_8;
wire d_ff4_Xn_n_9;
wire d_ff4_Yn_n_0;
wire d_ff4_Yn_n_1;
wire d_ff4_Yn_n_10;
wire d_ff4_Yn_n_11;
wire d_ff4_Yn_n_12;
wire d_ff4_Yn_n_13;
wire d_ff4_Yn_n_14;
wire d_ff4_Yn_n_15;
wire d_ff4_Yn_n_16;
wire d_ff4_Yn_n_17;
wire d_ff4_Yn_n_18;
wire d_ff4_Yn_n_19;
wire d_ff4_Yn_n_2;
wire d_ff4_Yn_n_20;
wire d_ff4_Yn_n_21;
wire d_ff4_Yn_n_22;
wire d_ff4_Yn_n_23;
wire d_ff4_Yn_n_24;
wire d_ff4_Yn_n_25;
wire d_ff4_Yn_n_26;
wire d_ff4_Yn_n_27;
wire d_ff4_Yn_n_28;
wire d_ff4_Yn_n_29;
wire d_ff4_Yn_n_3;
wire d_ff4_Yn_n_30;
wire d_ff4_Yn_n_31;
wire d_ff4_Yn_n_4;
wire d_ff4_Yn_n_5;
wire d_ff4_Yn_n_6;
wire d_ff4_Yn_n_7;
wire d_ff4_Yn_n_8;
wire d_ff4_Yn_n_9;
wire d_ff4_Zn_n_0;
wire d_ff4_Zn_n_1;
wire d_ff4_Zn_n_10;
wire d_ff4_Zn_n_11;
wire d_ff4_Zn_n_12;
wire d_ff4_Zn_n_13;
wire d_ff4_Zn_n_14;
wire d_ff4_Zn_n_15;
wire d_ff4_Zn_n_16;
wire d_ff4_Zn_n_17;
wire d_ff4_Zn_n_18;
wire d_ff4_Zn_n_19;
wire d_ff4_Zn_n_2;
wire d_ff4_Zn_n_20;
wire d_ff4_Zn_n_21;
wire d_ff4_Zn_n_22;
wire d_ff4_Zn_n_23;
wire d_ff4_Zn_n_24;
wire d_ff4_Zn_n_25;
wire d_ff4_Zn_n_26;
wire d_ff4_Zn_n_27;
wire d_ff4_Zn_n_28;
wire d_ff4_Zn_n_29;
wire d_ff4_Zn_n_3;
wire d_ff4_Zn_n_30;
wire d_ff4_Zn_n_31;
wire d_ff4_Zn_n_4;
wire d_ff4_Zn_n_5;
wire d_ff4_Zn_n_6;
wire d_ff4_Zn_n_7;
wire d_ff4_Zn_n_8;
wire d_ff4_Zn_n_9;
wire [31:0]data_in;
wire [31:0]data_in_IBUF;
wire [26:0]data_out_LUT;
wire [31:0]data_output;
wire [31:0]data_output_OBUF;
wire enab_RB3;
wire enab_cont_iter;
wire enab_d_ff4_Yn;
wire enab_d_ff4_Zn;
wire enab_d_ff5_data_out;
wire enab_d_ff_RB1;
wire inst_CORDIC_FSM_v3_n_0;
wire inst_CORDIC_FSM_v3_n_1;
wire inst_CORDIC_FSM_v3_n_3;
wire inst_CORDIC_FSM_v3_n_4;
wire inst_CORDIC_FSM_v3_n_5;
wire inst_CORDIC_FSM_v3_n_6;
wire inst_CORDIC_FSM_v3_n_7;
wire inst_CORDIC_FSM_v3_n_8;
wire inst_CORDIC_FSM_v3_n_9;
wire inst_FPU_PIPELINED_FPADDSUB_n_10;
wire inst_FPU_PIPELINED_FPADDSUB_n_11;
wire inst_FPU_PIPELINED_FPADDSUB_n_12;
wire inst_FPU_PIPELINED_FPADDSUB_n_13;
wire inst_FPU_PIPELINED_FPADDSUB_n_14;
wire inst_FPU_PIPELINED_FPADDSUB_n_15;
wire inst_FPU_PIPELINED_FPADDSUB_n_16;
wire inst_FPU_PIPELINED_FPADDSUB_n_17;
wire inst_FPU_PIPELINED_FPADDSUB_n_18;
wire inst_FPU_PIPELINED_FPADDSUB_n_19;
wire inst_FPU_PIPELINED_FPADDSUB_n_2;
wire inst_FPU_PIPELINED_FPADDSUB_n_20;
wire inst_FPU_PIPELINED_FPADDSUB_n_21;
wire inst_FPU_PIPELINED_FPADDSUB_n_22;
wire inst_FPU_PIPELINED_FPADDSUB_n_23;
wire inst_FPU_PIPELINED_FPADDSUB_n_24;
wire inst_FPU_PIPELINED_FPADDSUB_n_25;
wire inst_FPU_PIPELINED_FPADDSUB_n_26;
wire inst_FPU_PIPELINED_FPADDSUB_n_27;
wire inst_FPU_PIPELINED_FPADDSUB_n_28;
wire inst_FPU_PIPELINED_FPADDSUB_n_29;
wire inst_FPU_PIPELINED_FPADDSUB_n_3;
wire inst_FPU_PIPELINED_FPADDSUB_n_30;
wire inst_FPU_PIPELINED_FPADDSUB_n_31;
wire inst_FPU_PIPELINED_FPADDSUB_n_32;
wire inst_FPU_PIPELINED_FPADDSUB_n_33;
wire inst_FPU_PIPELINED_FPADDSUB_n_37;
wire inst_FPU_PIPELINED_FPADDSUB_n_4;
wire inst_FPU_PIPELINED_FPADDSUB_n_5;
wire inst_FPU_PIPELINED_FPADDSUB_n_6;
wire inst_FPU_PIPELINED_FPADDSUB_n_7;
wire inst_FPU_PIPELINED_FPADDSUB_n_8;
wire inst_FPU_PIPELINED_FPADDSUB_n_9;
wire max_tick_iter;
wire op_add_subt;
wire operation;
wire operation_IBUF;
wire overflow_flag;
wire overflow_flag_OBUF;
wire [2:2]p_1_out;
wire ready_add_subt;
wire ready_cordic;
wire ready_cordic_OBUF;
wire reg_LUT_n_0;
wire reg_LUT_n_1;
wire reg_LUT_n_10;
wire reg_LUT_n_11;
wire reg_LUT_n_12;
wire reg_LUT_n_13;
wire reg_LUT_n_14;
wire reg_LUT_n_15;
wire reg_LUT_n_16;
wire reg_LUT_n_17;
wire reg_LUT_n_18;
wire reg_LUT_n_19;
wire reg_LUT_n_2;
wire reg_LUT_n_20;
wire reg_LUT_n_3;
wire reg_LUT_n_4;
wire reg_LUT_n_5;
wire reg_LUT_n_6;
wire reg_LUT_n_7;
wire reg_LUT_n_8;
wire reg_LUT_n_9;
wire reg_Z0_n_0;
wire reg_Z0_n_1;
wire reg_Z0_n_10;
wire reg_Z0_n_11;
wire reg_Z0_n_12;
wire reg_Z0_n_13;
wire reg_Z0_n_14;
wire reg_Z0_n_15;
wire reg_Z0_n_16;
wire reg_Z0_n_17;
wire reg_Z0_n_18;
wire reg_Z0_n_19;
wire reg_Z0_n_2;
wire reg_Z0_n_20;
wire reg_Z0_n_21;
wire reg_Z0_n_22;
wire reg_Z0_n_23;
wire reg_Z0_n_24;
wire reg_Z0_n_25;
wire reg_Z0_n_26;
wire reg_Z0_n_27;
wire reg_Z0_n_28;
wire reg_Z0_n_29;
wire reg_Z0_n_3;
wire reg_Z0_n_30;
wire reg_Z0_n_31;
wire reg_Z0_n_4;
wire reg_Z0_n_5;
wire reg_Z0_n_6;
wire reg_Z0_n_7;
wire reg_Z0_n_8;
wire reg_Z0_n_9;
wire reg_region_flag_n_0;
wire reg_region_flag_n_1;
wire reg_region_flag_n_10;
wire reg_region_flag_n_11;
wire reg_region_flag_n_12;
wire reg_region_flag_n_13;
wire reg_region_flag_n_14;
wire reg_region_flag_n_15;
wire reg_region_flag_n_16;
wire reg_region_flag_n_17;
wire reg_region_flag_n_18;
wire reg_region_flag_n_19;
wire reg_region_flag_n_2;
wire reg_region_flag_n_20;
wire reg_region_flag_n_21;
wire reg_region_flag_n_22;
wire reg_region_flag_n_23;
wire reg_region_flag_n_24;
wire reg_region_flag_n_25;
wire reg_region_flag_n_26;
wire reg_region_flag_n_27;
wire reg_region_flag_n_28;
wire reg_region_flag_n_29;
wire reg_region_flag_n_3;
wire reg_region_flag_n_30;
wire reg_region_flag_n_31;
wire reg_region_flag_n_4;
wire reg_region_flag_n_5;
wire reg_region_flag_n_6;
wire reg_region_flag_n_7;
wire reg_region_flag_n_8;
wire reg_region_flag_n_9;
wire reg_shift_x_n_0;
wire reg_shift_x_n_1;
wire reg_shift_x_n_10;
wire reg_shift_x_n_11;
wire reg_shift_x_n_12;
wire reg_shift_x_n_13;
wire reg_shift_x_n_14;
wire reg_shift_x_n_15;
wire reg_shift_x_n_16;
wire reg_shift_x_n_17;
wire reg_shift_x_n_18;
wire reg_shift_x_n_19;
wire reg_shift_x_n_2;
wire reg_shift_x_n_20;
wire reg_shift_x_n_21;
wire reg_shift_x_n_22;
wire reg_shift_x_n_23;
wire reg_shift_x_n_24;
wire reg_shift_x_n_25;
wire reg_shift_x_n_26;
wire reg_shift_x_n_27;
wire reg_shift_x_n_28;
wire reg_shift_x_n_29;
wire reg_shift_x_n_3;
wire reg_shift_x_n_30;
wire reg_shift_x_n_31;
wire reg_shift_x_n_4;
wire reg_shift_x_n_5;
wire reg_shift_x_n_6;
wire reg_shift_x_n_7;
wire reg_shift_x_n_8;
wire reg_shift_x_n_9;
wire reg_shift_y_n_0;
wire reg_shift_y_n_1;
wire reg_shift_y_n_10;
wire reg_shift_y_n_11;
wire reg_shift_y_n_12;
wire reg_shift_y_n_13;
wire reg_shift_y_n_14;
wire reg_shift_y_n_15;
wire reg_shift_y_n_16;
wire reg_shift_y_n_17;
wire reg_shift_y_n_18;
wire reg_shift_y_n_19;
wire reg_shift_y_n_2;
wire reg_shift_y_n_20;
wire reg_shift_y_n_21;
wire reg_shift_y_n_22;
wire reg_shift_y_n_23;
wire reg_shift_y_n_24;
wire reg_shift_y_n_25;
wire reg_shift_y_n_26;
wire reg_shift_y_n_27;
wire reg_shift_y_n_28;
wire reg_shift_y_n_29;
wire reg_shift_y_n_3;
wire reg_shift_y_n_30;
wire reg_shift_y_n_31;
wire reg_shift_y_n_4;
wire reg_shift_y_n_5;
wire reg_shift_y_n_6;
wire reg_shift_y_n_7;
wire reg_shift_y_n_8;
wire reg_shift_y_n_9;
wire reg_val_muxX_2stage_n_0;
wire reg_val_muxX_2stage_n_1;
wire reg_val_muxX_2stage_n_13;
wire reg_val_muxX_2stage_n_14;
wire reg_val_muxX_2stage_n_15;
wire reg_val_muxX_2stage_n_16;
wire reg_val_muxX_2stage_n_17;
wire reg_val_muxX_2stage_n_18;
wire reg_val_muxX_2stage_n_19;
wire reg_val_muxX_2stage_n_2;
wire reg_val_muxX_2stage_n_20;
wire reg_val_muxX_2stage_n_21;
wire reg_val_muxX_2stage_n_22;
wire reg_val_muxX_2stage_n_23;
wire reg_val_muxX_2stage_n_24;
wire reg_val_muxX_2stage_n_25;
wire reg_val_muxX_2stage_n_26;
wire reg_val_muxX_2stage_n_27;
wire reg_val_muxX_2stage_n_28;
wire reg_val_muxX_2stage_n_29;
wire reg_val_muxX_2stage_n_3;
wire reg_val_muxX_2stage_n_30;
wire reg_val_muxX_2stage_n_31;
wire reg_val_muxX_2stage_n_32;
wire reg_val_muxX_2stage_n_33;
wire reg_val_muxX_2stage_n_34;
wire reg_val_muxX_2stage_n_35;
wire reg_val_muxX_2stage_n_36;
wire reg_val_muxX_2stage_n_37;
wire reg_val_muxX_2stage_n_38;
wire reg_val_muxX_2stage_n_39;
wire reg_val_muxX_2stage_n_4;
wire reg_val_muxY_2stage_n_1;
wire reg_val_muxY_2stage_n_10;
wire reg_val_muxY_2stage_n_11;
wire reg_val_muxY_2stage_n_12;
wire reg_val_muxY_2stage_n_13;
wire reg_val_muxY_2stage_n_14;
wire reg_val_muxY_2stage_n_15;
wire reg_val_muxY_2stage_n_16;
wire reg_val_muxY_2stage_n_17;
wire reg_val_muxY_2stage_n_18;
wire reg_val_muxY_2stage_n_19;
wire reg_val_muxY_2stage_n_2;
wire reg_val_muxY_2stage_n_20;
wire reg_val_muxY_2stage_n_21;
wire reg_val_muxY_2stage_n_22;
wire reg_val_muxY_2stage_n_23;
wire reg_val_muxY_2stage_n_24;
wire reg_val_muxY_2stage_n_25;
wire reg_val_muxY_2stage_n_26;
wire reg_val_muxY_2stage_n_27;
wire reg_val_muxY_2stage_n_28;
wire reg_val_muxY_2stage_n_29;
wire reg_val_muxY_2stage_n_3;
wire reg_val_muxY_2stage_n_30;
wire reg_val_muxY_2stage_n_31;
wire reg_val_muxY_2stage_n_32;
wire reg_val_muxY_2stage_n_33;
wire reg_val_muxY_2stage_n_34;
wire reg_val_muxY_2stage_n_35;
wire reg_val_muxY_2stage_n_36;
wire reg_val_muxY_2stage_n_37;
wire reg_val_muxY_2stage_n_38;
wire reg_val_muxY_2stage_n_39;
wire reg_val_muxY_2stage_n_4;
wire reg_val_muxY_2stage_n_5;
wire reg_val_muxY_2stage_n_6;
wire reg_val_muxY_2stage_n_7;
wire reg_val_muxY_2stage_n_8;
wire reg_val_muxY_2stage_n_9;
wire reg_val_muxZ_2stage_n_1;
wire reg_val_muxZ_2stage_n_10;
wire reg_val_muxZ_2stage_n_11;
wire reg_val_muxZ_2stage_n_12;
wire reg_val_muxZ_2stage_n_13;
wire reg_val_muxZ_2stage_n_14;
wire reg_val_muxZ_2stage_n_15;
wire reg_val_muxZ_2stage_n_16;
wire reg_val_muxZ_2stage_n_17;
wire reg_val_muxZ_2stage_n_18;
wire reg_val_muxZ_2stage_n_19;
wire reg_val_muxZ_2stage_n_2;
wire reg_val_muxZ_2stage_n_20;
wire reg_val_muxZ_2stage_n_21;
wire reg_val_muxZ_2stage_n_22;
wire reg_val_muxZ_2stage_n_23;
wire reg_val_muxZ_2stage_n_24;
wire reg_val_muxZ_2stage_n_25;
wire reg_val_muxZ_2stage_n_26;
wire reg_val_muxZ_2stage_n_27;
wire reg_val_muxZ_2stage_n_28;
wire reg_val_muxZ_2stage_n_29;
wire reg_val_muxZ_2stage_n_3;
wire reg_val_muxZ_2stage_n_30;
wire reg_val_muxZ_2stage_n_31;
wire reg_val_muxZ_2stage_n_4;
wire reg_val_muxZ_2stage_n_5;
wire reg_val_muxZ_2stage_n_6;
wire reg_val_muxZ_2stage_n_7;
wire reg_val_muxZ_2stage_n_8;
wire reg_val_muxZ_2stage_n_9;
wire reset_reg_cordic;
wire rst;
wire rst0;
wire rst_IBUF;
wire [1:0]shift_region_flag;
wire [1:0]shift_region_flag_IBUF;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
wire zero_flag_OBUF;
initial begin
$sdf_annotate("testbench_CORDIC_Arch3_time_synth.sdf",,,,"tool_control");
end
Up_counter ITER_CONT
(.CLK(clk_IBUF_BUFG),
.D({ITER_CONT_n_5,ITER_CONT_n_6,ITER_CONT_n_7,ITER_CONT_n_8,ITER_CONT_n_9,ITER_CONT_n_10,ITER_CONT_n_11,ITER_CONT_n_12,ITER_CONT_n_13,ITER_CONT_n_14,ITER_CONT_n_15,ITER_CONT_n_16,ITER_CONT_n_17,ITER_CONT_n_18,ITER_CONT_n_19,ITER_CONT_n_20,ITER_CONT_n_21,ITER_CONT_n_22,ITER_CONT_n_23,ITER_CONT_n_24,ITER_CONT_n_25,ITER_CONT_n_26,ITER_CONT_n_27,ITER_CONT_n_28,ITER_CONT_n_29,ITER_CONT_n_30,ITER_CONT_n_31,ITER_CONT_n_32,ITER_CONT_n_33,ITER_CONT_n_34,ITER_CONT_n_35,ITER_CONT_n_36}),
.E(enab_cont_iter),
.Q(cont_iter_out),
.\Q_reg[26] ({data_out_LUT[26:24],ITER_CONT_n_104,data_out_LUT[22:21],ITER_CONT_n_107,ITER_CONT_n_108,ITER_CONT_n_109,data_out_LUT[14],data_out_LUT[12:9],p_1_out,data_out_LUT[6],data_out_LUT[4],ITER_CONT_n_118,ITER_CONT_n_119,data_out_LUT[0]}),
.\Q_reg[31] ({ITER_CONT_n_37,ITER_CONT_n_38,ITER_CONT_n_39,ITER_CONT_n_40,ITER_CONT_n_41,ITER_CONT_n_42,ITER_CONT_n_43,ITER_CONT_n_44,ITER_CONT_n_45,ITER_CONT_n_46,ITER_CONT_n_47,ITER_CONT_n_48,ITER_CONT_n_49,ITER_CONT_n_50,ITER_CONT_n_51,ITER_CONT_n_52,ITER_CONT_n_53,ITER_CONT_n_54,ITER_CONT_n_55,ITER_CONT_n_56,ITER_CONT_n_57,ITER_CONT_n_58,ITER_CONT_n_59,ITER_CONT_n_60,ITER_CONT_n_61,ITER_CONT_n_62,ITER_CONT_n_63,ITER_CONT_n_64,ITER_CONT_n_65,ITER_CONT_n_66,ITER_CONT_n_67,ITER_CONT_n_68}),
.\Q_reg[31]_0 ({ITER_CONT_n_69,ITER_CONT_n_70,ITER_CONT_n_71,ITER_CONT_n_72,ITER_CONT_n_73,ITER_CONT_n_74,ITER_CONT_n_75,ITER_CONT_n_76,ITER_CONT_n_77,ITER_CONT_n_78,ITER_CONT_n_79,ITER_CONT_n_80,ITER_CONT_n_81,ITER_CONT_n_82,ITER_CONT_n_83,ITER_CONT_n_84,ITER_CONT_n_85,ITER_CONT_n_86,ITER_CONT_n_87,ITER_CONT_n_88,ITER_CONT_n_89,ITER_CONT_n_90,ITER_CONT_n_91,ITER_CONT_n_92,ITER_CONT_n_93,ITER_CONT_n_94,ITER_CONT_n_95,ITER_CONT_n_96,ITER_CONT_n_97,ITER_CONT_n_98,ITER_CONT_n_99,ITER_CONT_n_100}),
.\Q_reg[31]_1 ({d_ff4_Zn_n_0,d_ff4_Zn_n_1,d_ff4_Zn_n_2,d_ff4_Zn_n_3,d_ff4_Zn_n_4,d_ff4_Zn_n_5,d_ff4_Zn_n_6,d_ff4_Zn_n_7,d_ff4_Zn_n_8,d_ff4_Zn_n_9,d_ff4_Zn_n_10,d_ff4_Zn_n_11,d_ff4_Zn_n_12,d_ff4_Zn_n_13,d_ff4_Zn_n_14,d_ff4_Zn_n_15,d_ff4_Zn_n_16,d_ff4_Zn_n_17,d_ff4_Zn_n_18,d_ff4_Zn_n_19,d_ff4_Zn_n_20,d_ff4_Zn_n_21,d_ff4_Zn_n_22,d_ff4_Zn_n_23,d_ff4_Zn_n_24,d_ff4_Zn_n_25,d_ff4_Zn_n_26,d_ff4_Zn_n_27,d_ff4_Zn_n_28,d_ff4_Zn_n_29,d_ff4_Zn_n_30,d_ff4_Zn_n_31}),
.\Q_reg[31]_2 ({reg_Z0_n_0,reg_Z0_n_1,reg_Z0_n_2,reg_Z0_n_3,reg_Z0_n_4,reg_Z0_n_5,reg_Z0_n_6,reg_Z0_n_7,reg_Z0_n_8,reg_Z0_n_9,reg_Z0_n_10,reg_Z0_n_11,reg_Z0_n_12,reg_Z0_n_13,reg_Z0_n_14,reg_Z0_n_15,reg_Z0_n_16,reg_Z0_n_17,reg_Z0_n_18,reg_Z0_n_19,reg_Z0_n_20,reg_Z0_n_21,reg_Z0_n_22,reg_Z0_n_23,reg_Z0_n_24,reg_Z0_n_25,reg_Z0_n_26,reg_Z0_n_27,reg_Z0_n_28,reg_Z0_n_29,reg_Z0_n_30,reg_Z0_n_31}),
.\Q_reg[31]_3 ({d_ff4_Xn_n_0,d_ff4_Xn_n_1,d_ff4_Xn_n_2,d_ff4_Xn_n_3,d_ff4_Xn_n_4,d_ff4_Xn_n_5,d_ff4_Xn_n_6,d_ff4_Xn_n_7,d_ff4_Xn_n_8,d_ff4_Xn_n_9,d_ff4_Xn_n_10,d_ff4_Xn_n_11,d_ff4_Xn_n_12,d_ff4_Xn_n_13,d_ff4_Xn_n_14,d_ff4_Xn_n_15,d_ff4_Xn_n_16,d_ff4_Xn_n_17,d_ff4_Xn_n_18,d_ff4_Xn_n_19,d_ff4_Xn_n_20,d_ff4_Xn_n_21,d_ff4_Xn_n_22,d_ff4_Xn_n_23,d_ff4_Xn_n_24,d_ff4_Xn_n_25,d_ff4_Xn_n_26,d_ff4_Xn_n_27,d_ff4_Xn_n_28,d_ff4_Xn_n_29,d_ff4_Xn_n_30,d_ff4_Xn_n_31}),
.\Q_reg[31]_4 ({d_ff4_Yn_n_0,d_ff4_Yn_n_1,d_ff4_Yn_n_2,d_ff4_Yn_n_3,d_ff4_Yn_n_4,d_ff4_Yn_n_5,d_ff4_Yn_n_6,d_ff4_Yn_n_7,d_ff4_Yn_n_8,d_ff4_Yn_n_9,d_ff4_Yn_n_10,d_ff4_Yn_n_11,d_ff4_Yn_n_12,d_ff4_Yn_n_13,d_ff4_Yn_n_14,d_ff4_Yn_n_15,d_ff4_Yn_n_16,d_ff4_Yn_n_17,d_ff4_Yn_n_18,d_ff4_Yn_n_19,d_ff4_Yn_n_20,d_ff4_Yn_n_21,d_ff4_Yn_n_22,d_ff4_Yn_n_23,d_ff4_Yn_n_24,d_ff4_Yn_n_25,d_ff4_Yn_n_26,d_ff4_Yn_n_27,d_ff4_Yn_n_28,d_ff4_Yn_n_29,d_ff4_Yn_n_30,d_ff4_Yn_n_31}),
.SR(reset_reg_cordic),
.max_tick_iter(max_tick_iter));
Up_counter__parameterized0 VAR_CONT
(.CLK(clk_IBUF_BUFG),
.D({VAR_CONT_n_5,VAR_CONT_n_6,VAR_CONT_n_7,VAR_CONT_n_8,VAR_CONT_n_9,VAR_CONT_n_10,VAR_CONT_n_11,VAR_CONT_n_12,VAR_CONT_n_13,VAR_CONT_n_14,VAR_CONT_n_15,VAR_CONT_n_16,VAR_CONT_n_17,VAR_CONT_n_18,VAR_CONT_n_19,VAR_CONT_n_20,VAR_CONT_n_21,VAR_CONT_n_22,VAR_CONT_n_23,VAR_CONT_n_24,VAR_CONT_n_25,VAR_CONT_n_26,VAR_CONT_n_27,VAR_CONT_n_28,VAR_CONT_n_29,VAR_CONT_n_30,VAR_CONT_n_31,VAR_CONT_n_32,VAR_CONT_n_33,VAR_CONT_n_34,VAR_CONT_n_35,VAR_CONT_n_36}),
.E(enab_d_ff4_Zn),
.Q({reg_shift_y_n_0,reg_shift_y_n_1,reg_shift_y_n_2,reg_shift_y_n_3,reg_shift_y_n_4,reg_shift_y_n_5,reg_shift_y_n_6,reg_shift_y_n_7,reg_shift_y_n_8,reg_shift_y_n_9,reg_shift_y_n_10,reg_shift_y_n_11,reg_shift_y_n_12,reg_shift_y_n_13,reg_shift_y_n_14,reg_shift_y_n_15,reg_shift_y_n_16,reg_shift_y_n_17,reg_shift_y_n_18,reg_shift_y_n_19,reg_shift_y_n_20,reg_shift_y_n_21,reg_shift_y_n_22,reg_shift_y_n_23,reg_shift_y_n_24,reg_shift_y_n_25,reg_shift_y_n_26,reg_shift_y_n_27,reg_shift_y_n_28,reg_shift_y_n_29,reg_shift_y_n_30,reg_shift_y_n_31}),
.\Q_reg[29] ({reg_LUT_n_0,reg_LUT_n_1,reg_LUT_n_2,reg_LUT_n_3,reg_LUT_n_4,reg_LUT_n_5,reg_LUT_n_6,reg_LUT_n_7,reg_LUT_n_8,reg_LUT_n_9,reg_LUT_n_10,reg_LUT_n_11,reg_LUT_n_12,reg_LUT_n_13,reg_LUT_n_14,reg_LUT_n_15,reg_LUT_n_16,reg_LUT_n_17,reg_LUT_n_18,reg_LUT_n_19,reg_LUT_n_20}),
.\Q_reg[31] (VAR_CONT_n_3),
.\Q_reg[31]_0 (enab_d_ff4_Yn),
.\Q_reg[31]_1 ({VAR_CONT_n_37,VAR_CONT_n_38,VAR_CONT_n_39,VAR_CONT_n_40,VAR_CONT_n_41,VAR_CONT_n_42,VAR_CONT_n_43,VAR_CONT_n_44,VAR_CONT_n_45,VAR_CONT_n_46,VAR_CONT_n_47,VAR_CONT_n_48,VAR_CONT_n_49,VAR_CONT_n_50,VAR_CONT_n_51,VAR_CONT_n_52,VAR_CONT_n_53,VAR_CONT_n_54,VAR_CONT_n_55,VAR_CONT_n_56,VAR_CONT_n_57,VAR_CONT_n_58,VAR_CONT_n_59,VAR_CONT_n_60,VAR_CONT_n_61,VAR_CONT_n_62,VAR_CONT_n_63,VAR_CONT_n_64,VAR_CONT_n_65,VAR_CONT_n_66,VAR_CONT_n_67,VAR_CONT_n_68}),
.\Q_reg[31]_2 ({reg_shift_x_n_0,reg_shift_x_n_1,reg_shift_x_n_2,reg_shift_x_n_3,reg_shift_x_n_4,reg_shift_x_n_5,reg_shift_x_n_6,reg_shift_x_n_7,reg_shift_x_n_8,reg_shift_x_n_9,reg_shift_x_n_10,reg_shift_x_n_11,reg_shift_x_n_12,reg_shift_x_n_13,reg_shift_x_n_14,reg_shift_x_n_15,reg_shift_x_n_16,reg_shift_x_n_17,reg_shift_x_n_18,reg_shift_x_n_19,reg_shift_x_n_20,reg_shift_x_n_21,reg_shift_x_n_22,reg_shift_x_n_23,reg_shift_x_n_24,reg_shift_x_n_25,reg_shift_x_n_26,reg_shift_x_n_27,reg_shift_x_n_28,reg_shift_x_n_29,reg_shift_x_n_30,reg_shift_x_n_31}),
.\Q_reg[31]_3 ({d_ff2_Z,reg_val_muxZ_2stage_n_1,reg_val_muxZ_2stage_n_2,reg_val_muxZ_2stage_n_3,reg_val_muxZ_2stage_n_4,reg_val_muxZ_2stage_n_5,reg_val_muxZ_2stage_n_6,reg_val_muxZ_2stage_n_7,reg_val_muxZ_2stage_n_8,reg_val_muxZ_2stage_n_9,reg_val_muxZ_2stage_n_10,reg_val_muxZ_2stage_n_11,reg_val_muxZ_2stage_n_12,reg_val_muxZ_2stage_n_13,reg_val_muxZ_2stage_n_14,reg_val_muxZ_2stage_n_15,reg_val_muxZ_2stage_n_16,reg_val_muxZ_2stage_n_17,reg_val_muxZ_2stage_n_18,reg_val_muxZ_2stage_n_19,reg_val_muxZ_2stage_n_20,reg_val_muxZ_2stage_n_21,reg_val_muxZ_2stage_n_22,reg_val_muxZ_2stage_n_23,reg_val_muxZ_2stage_n_24,reg_val_muxZ_2stage_n_25,reg_val_muxZ_2stage_n_26,reg_val_muxZ_2stage_n_27,reg_val_muxZ_2stage_n_28,reg_val_muxZ_2stage_n_29,reg_val_muxZ_2stage_n_30,reg_val_muxZ_2stage_n_31}),
.\Q_reg[31]_4 ({reg_val_muxX_2stage_n_4,A,reg_val_muxX_2stage_n_13,reg_val_muxX_2stage_n_14,reg_val_muxX_2stage_n_15,reg_val_muxX_2stage_n_16,reg_val_muxX_2stage_n_17,reg_val_muxX_2stage_n_18,reg_val_muxX_2stage_n_19,reg_val_muxX_2stage_n_20,reg_val_muxX_2stage_n_21,reg_val_muxX_2stage_n_22,reg_val_muxX_2stage_n_23,reg_val_muxX_2stage_n_24,reg_val_muxX_2stage_n_25,reg_val_muxX_2stage_n_26,reg_val_muxX_2stage_n_27,reg_val_muxX_2stage_n_28,reg_val_muxX_2stage_n_29,reg_val_muxX_2stage_n_30,reg_val_muxX_2stage_n_31,reg_val_muxX_2stage_n_32,reg_val_muxX_2stage_n_33,reg_val_muxX_2stage_n_34,reg_val_muxX_2stage_n_35}),
.\Q_reg[31]_5 ({d_ff2_Y,reg_val_muxY_2stage_n_1,reg_val_muxY_2stage_n_2,reg_val_muxY_2stage_n_3,reg_val_muxY_2stage_n_4,reg_val_muxY_2stage_n_5,reg_val_muxY_2stage_n_6,reg_val_muxY_2stage_n_7,reg_val_muxY_2stage_n_8,reg_val_muxY_2stage_n_9,reg_val_muxY_2stage_n_10,reg_val_muxY_2stage_n_11,reg_val_muxY_2stage_n_12,reg_val_muxY_2stage_n_13,reg_val_muxY_2stage_n_14,reg_val_muxY_2stage_n_15,reg_val_muxY_2stage_n_16,reg_val_muxY_2stage_n_17,reg_val_muxY_2stage_n_18,reg_val_muxY_2stage_n_19,reg_val_muxY_2stage_n_20,reg_val_muxY_2stage_n_21,reg_val_muxY_2stage_n_22,reg_val_muxY_2stage_n_23,reg_val_muxY_2stage_n_24,reg_val_muxY_2stage_n_25,reg_val_muxY_2stage_n_26,reg_val_muxY_2stage_n_27,reg_val_muxY_2stage_n_28,reg_val_muxY_2stage_n_29,reg_val_muxY_2stage_n_30,reg_val_muxY_2stage_n_31}),
.cont_var_out(cont_var_out),
.d_ff3_sign_out(d_ff3_sign_out),
.op_add_subt(op_add_subt),
.out({inst_CORDIC_FSM_v3_n_4,inst_CORDIC_FSM_v3_n_6}),
.ready_add_subt(ready_add_subt),
.rst_IBUF(rst_IBUF));
IBUF ack_cordic_IBUF_inst
(.I(ack_cordic),
.O(ack_cordic_IBUF));
IBUF beg_fsm_cordic_IBUF_inst
(.I(beg_fsm_cordic),
.O(beg_fsm_cordic_IBUF));
OBUF busy_OBUF_inst
(.I(busy_OBUF),
.O(busy));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
d_ff_en__parameterized8 d_ff4_Xn
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.E(VAR_CONT_n_3),
.Q({d_ff4_Xn_n_0,d_ff4_Xn_n_1,d_ff4_Xn_n_2,d_ff4_Xn_n_3,d_ff4_Xn_n_4,d_ff4_Xn_n_5,d_ff4_Xn_n_6,d_ff4_Xn_n_7,d_ff4_Xn_n_8,d_ff4_Xn_n_9,d_ff4_Xn_n_10,d_ff4_Xn_n_11,d_ff4_Xn_n_12,d_ff4_Xn_n_13,d_ff4_Xn_n_14,d_ff4_Xn_n_15,d_ff4_Xn_n_16,d_ff4_Xn_n_17,d_ff4_Xn_n_18,d_ff4_Xn_n_19,d_ff4_Xn_n_20,d_ff4_Xn_n_21,d_ff4_Xn_n_22,d_ff4_Xn_n_23,d_ff4_Xn_n_24,d_ff4_Xn_n_25,d_ff4_Xn_n_26,d_ff4_Xn_n_27,d_ff4_Xn_n_28,d_ff4_Xn_n_29,d_ff4_Xn_n_30,d_ff4_Xn_n_31}),
.\Q_reg[31]_0 ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}));
d_ff_en__parameterized9 d_ff4_Yn
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.E(enab_d_ff4_Yn),
.Q({d_ff4_Yn_n_0,d_ff4_Yn_n_1,d_ff4_Yn_n_2,d_ff4_Yn_n_3,d_ff4_Yn_n_4,d_ff4_Yn_n_5,d_ff4_Yn_n_6,d_ff4_Yn_n_7,d_ff4_Yn_n_8,d_ff4_Yn_n_9,d_ff4_Yn_n_10,d_ff4_Yn_n_11,d_ff4_Yn_n_12,d_ff4_Yn_n_13,d_ff4_Yn_n_14,d_ff4_Yn_n_15,d_ff4_Yn_n_16,d_ff4_Yn_n_17,d_ff4_Yn_n_18,d_ff4_Yn_n_19,d_ff4_Yn_n_20,d_ff4_Yn_n_21,d_ff4_Yn_n_22,d_ff4_Yn_n_23,d_ff4_Yn_n_24,d_ff4_Yn_n_25,d_ff4_Yn_n_26,d_ff4_Yn_n_27,d_ff4_Yn_n_28,d_ff4_Yn_n_29,d_ff4_Yn_n_30,d_ff4_Yn_n_31}),
.\Q_reg[31]_0 ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}));
d_ff_en__parameterized10 d_ff4_Zn
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.E(enab_d_ff4_Zn),
.Q({d_ff4_Zn_n_0,d_ff4_Zn_n_1,d_ff4_Zn_n_2,d_ff4_Zn_n_3,d_ff4_Zn_n_4,d_ff4_Zn_n_5,d_ff4_Zn_n_6,d_ff4_Zn_n_7,d_ff4_Zn_n_8,d_ff4_Zn_n_9,d_ff4_Zn_n_10,d_ff4_Zn_n_11,d_ff4_Zn_n_12,d_ff4_Zn_n_13,d_ff4_Zn_n_14,d_ff4_Zn_n_15,d_ff4_Zn_n_16,d_ff4_Zn_n_17,d_ff4_Zn_n_18,d_ff4_Zn_n_19,d_ff4_Zn_n_20,d_ff4_Zn_n_21,d_ff4_Zn_n_22,d_ff4_Zn_n_23,d_ff4_Zn_n_24,d_ff4_Zn_n_25,d_ff4_Zn_n_26,d_ff4_Zn_n_27,d_ff4_Zn_n_28,d_ff4_Zn_n_29,d_ff4_Zn_n_30,d_ff4_Zn_n_31}),
.\Q_reg[31]_0 ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}));
d_ff_en__parameterized11 d_ff5_data_out
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.D({reg_region_flag_n_0,reg_region_flag_n_1,reg_region_flag_n_2,reg_region_flag_n_3,reg_region_flag_n_4,reg_region_flag_n_5,reg_region_flag_n_6,reg_region_flag_n_7,reg_region_flag_n_8,reg_region_flag_n_9,reg_region_flag_n_10,reg_region_flag_n_11,reg_region_flag_n_12,reg_region_flag_n_13,reg_region_flag_n_14,reg_region_flag_n_15,reg_region_flag_n_16,reg_region_flag_n_17,reg_region_flag_n_18,reg_region_flag_n_19,reg_region_flag_n_20,reg_region_flag_n_21,reg_region_flag_n_22,reg_region_flag_n_23,reg_region_flag_n_24,reg_region_flag_n_25,reg_region_flag_n_26,reg_region_flag_n_27,reg_region_flag_n_28,reg_region_flag_n_29,reg_region_flag_n_30,reg_region_flag_n_31}),
.E(enab_d_ff5_data_out),
.Q(data_output_OBUF));
IBUF \data_in_IBUF[0]_inst
(.I(data_in[0]),
.O(data_in_IBUF[0]));
IBUF \data_in_IBUF[10]_inst
(.I(data_in[10]),
.O(data_in_IBUF[10]));
IBUF \data_in_IBUF[11]_inst
(.I(data_in[11]),
.O(data_in_IBUF[11]));
IBUF \data_in_IBUF[12]_inst
(.I(data_in[12]),
.O(data_in_IBUF[12]));
IBUF \data_in_IBUF[13]_inst
(.I(data_in[13]),
.O(data_in_IBUF[13]));
IBUF \data_in_IBUF[14]_inst
(.I(data_in[14]),
.O(data_in_IBUF[14]));
IBUF \data_in_IBUF[15]_inst
(.I(data_in[15]),
.O(data_in_IBUF[15]));
IBUF \data_in_IBUF[16]_inst
(.I(data_in[16]),
.O(data_in_IBUF[16]));
IBUF \data_in_IBUF[17]_inst
(.I(data_in[17]),
.O(data_in_IBUF[17]));
IBUF \data_in_IBUF[18]_inst
(.I(data_in[18]),
.O(data_in_IBUF[18]));
IBUF \data_in_IBUF[19]_inst
(.I(data_in[19]),
.O(data_in_IBUF[19]));
IBUF \data_in_IBUF[1]_inst
(.I(data_in[1]),
.O(data_in_IBUF[1]));
IBUF \data_in_IBUF[20]_inst
(.I(data_in[20]),
.O(data_in_IBUF[20]));
IBUF \data_in_IBUF[21]_inst
(.I(data_in[21]),
.O(data_in_IBUF[21]));
IBUF \data_in_IBUF[22]_inst
(.I(data_in[22]),
.O(data_in_IBUF[22]));
IBUF \data_in_IBUF[23]_inst
(.I(data_in[23]),
.O(data_in_IBUF[23]));
IBUF \data_in_IBUF[24]_inst
(.I(data_in[24]),
.O(data_in_IBUF[24]));
IBUF \data_in_IBUF[25]_inst
(.I(data_in[25]),
.O(data_in_IBUF[25]));
IBUF \data_in_IBUF[26]_inst
(.I(data_in[26]),
.O(data_in_IBUF[26]));
IBUF \data_in_IBUF[27]_inst
(.I(data_in[27]),
.O(data_in_IBUF[27]));
IBUF \data_in_IBUF[28]_inst
(.I(data_in[28]),
.O(data_in_IBUF[28]));
IBUF \data_in_IBUF[29]_inst
(.I(data_in[29]),
.O(data_in_IBUF[29]));
IBUF \data_in_IBUF[2]_inst
(.I(data_in[2]),
.O(data_in_IBUF[2]));
IBUF \data_in_IBUF[30]_inst
(.I(data_in[30]),
.O(data_in_IBUF[30]));
IBUF \data_in_IBUF[31]_inst
(.I(data_in[31]),
.O(data_in_IBUF[31]));
IBUF \data_in_IBUF[3]_inst
(.I(data_in[3]),
.O(data_in_IBUF[3]));
IBUF \data_in_IBUF[4]_inst
(.I(data_in[4]),
.O(data_in_IBUF[4]));
IBUF \data_in_IBUF[5]_inst
(.I(data_in[5]),
.O(data_in_IBUF[5]));
IBUF \data_in_IBUF[6]_inst
(.I(data_in[6]),
.O(data_in_IBUF[6]));
IBUF \data_in_IBUF[7]_inst
(.I(data_in[7]),
.O(data_in_IBUF[7]));
IBUF \data_in_IBUF[8]_inst
(.I(data_in[8]),
.O(data_in_IBUF[8]));
IBUF \data_in_IBUF[9]_inst
(.I(data_in[9]),
.O(data_in_IBUF[9]));
OBUF \data_output_OBUF[0]_inst
(.I(data_output_OBUF[0]),
.O(data_output[0]));
OBUF \data_output_OBUF[10]_inst
(.I(data_output_OBUF[10]),
.O(data_output[10]));
OBUF \data_output_OBUF[11]_inst
(.I(data_output_OBUF[11]),
.O(data_output[11]));
OBUF \data_output_OBUF[12]_inst
(.I(data_output_OBUF[12]),
.O(data_output[12]));
OBUF \data_output_OBUF[13]_inst
(.I(data_output_OBUF[13]),
.O(data_output[13]));
OBUF \data_output_OBUF[14]_inst
(.I(data_output_OBUF[14]),
.O(data_output[14]));
OBUF \data_output_OBUF[15]_inst
(.I(data_output_OBUF[15]),
.O(data_output[15]));
OBUF \data_output_OBUF[16]_inst
(.I(data_output_OBUF[16]),
.O(data_output[16]));
OBUF \data_output_OBUF[17]_inst
(.I(data_output_OBUF[17]),
.O(data_output[17]));
OBUF \data_output_OBUF[18]_inst
(.I(data_output_OBUF[18]),
.O(data_output[18]));
OBUF \data_output_OBUF[19]_inst
(.I(data_output_OBUF[19]),
.O(data_output[19]));
OBUF \data_output_OBUF[1]_inst
(.I(data_output_OBUF[1]),
.O(data_output[1]));
OBUF \data_output_OBUF[20]_inst
(.I(data_output_OBUF[20]),
.O(data_output[20]));
OBUF \data_output_OBUF[21]_inst
(.I(data_output_OBUF[21]),
.O(data_output[21]));
OBUF \data_output_OBUF[22]_inst
(.I(data_output_OBUF[22]),
.O(data_output[22]));
OBUF \data_output_OBUF[23]_inst
(.I(data_output_OBUF[23]),
.O(data_output[23]));
OBUF \data_output_OBUF[24]_inst
(.I(data_output_OBUF[24]),
.O(data_output[24]));
OBUF \data_output_OBUF[25]_inst
(.I(data_output_OBUF[25]),
.O(data_output[25]));
OBUF \data_output_OBUF[26]_inst
(.I(data_output_OBUF[26]),
.O(data_output[26]));
OBUF \data_output_OBUF[27]_inst
(.I(data_output_OBUF[27]),
.O(data_output[27]));
OBUF \data_output_OBUF[28]_inst
(.I(data_output_OBUF[28]),
.O(data_output[28]));
OBUF \data_output_OBUF[29]_inst
(.I(data_output_OBUF[29]),
.O(data_output[29]));
OBUF \data_output_OBUF[2]_inst
(.I(data_output_OBUF[2]),
.O(data_output[2]));
OBUF \data_output_OBUF[30]_inst
(.I(data_output_OBUF[30]),
.O(data_output[30]));
OBUF \data_output_OBUF[31]_inst
(.I(data_output_OBUF[31]),
.O(data_output[31]));
OBUF \data_output_OBUF[3]_inst
(.I(data_output_OBUF[3]),
.O(data_output[3]));
OBUF \data_output_OBUF[4]_inst
(.I(data_output_OBUF[4]),
.O(data_output[4]));
OBUF \data_output_OBUF[5]_inst
(.I(data_output_OBUF[5]),
.O(data_output[5]));
OBUF \data_output_OBUF[6]_inst
(.I(data_output_OBUF[6]),
.O(data_output[6]));
OBUF \data_output_OBUF[7]_inst
(.I(data_output_OBUF[7]),
.O(data_output[7]));
OBUF \data_output_OBUF[8]_inst
(.I(data_output_OBUF[8]),
.O(data_output[8]));
OBUF \data_output_OBUF[9]_inst
(.I(data_output_OBUF[9]),
.O(data_output[9]));
CORDIC_FSM_v3 inst_CORDIC_FSM_v3
(.AR({inst_CORDIC_FSM_v3_n_0,inst_CORDIC_FSM_v3_n_1,rst0,inst_CORDIC_FSM_v3_n_3}),
.CLK(clk_IBUF_BUFG),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[0]_0 (inst_CORDIC_FSM_v3_n_7),
.\FSM_sequential_state_reg_reg[2]_0 (inst_FPU_PIPELINED_FPADDSUB_n_37),
.\Q_reg[0] (enab_RB3),
.\Q_reg[1] (enab_d_ff_RB1),
.\Q_reg[31] (inst_CORDIC_FSM_v3_n_9),
.\Q_reg[31]_0 (enab_d_ff5_data_out),
.\Q_reg[31]_1 (reset_reg_cordic),
.ack_cordic_IBUF(ack_cordic_IBUF),
.beg_fsm_cordic_IBUF(beg_fsm_cordic_IBUF),
.cont_var_out(cont_var_out),
.max_tick_iter(max_tick_iter),
.out({inst_CORDIC_FSM_v3_n_4,inst_CORDIC_FSM_v3_n_5,inst_CORDIC_FSM_v3_n_6}),
.ready_cordic_OBUF(ready_cordic_OBUF),
.rst_IBUF(rst_IBUF),
.\temp_reg[0] (enab_cont_iter),
.\temp_reg[1] (enab_d_ff4_Zn));
FPU_PIPELINED_FPADDSUB inst_FPU_PIPELINED_FPADDSUB
(.AR({inst_CORDIC_FSM_v3_n_0,inst_CORDIC_FSM_v3_n_1,rst0,inst_CORDIC_FSM_v3_n_3}),
.CLK(clk_IBUF_BUFG),
.D({VAR_CONT_n_5,VAR_CONT_n_6,VAR_CONT_n_7,VAR_CONT_n_8,VAR_CONT_n_9,VAR_CONT_n_10,VAR_CONT_n_11,VAR_CONT_n_12,VAR_CONT_n_13,VAR_CONT_n_14,VAR_CONT_n_15,VAR_CONT_n_16,VAR_CONT_n_17,VAR_CONT_n_18,VAR_CONT_n_19,VAR_CONT_n_20,VAR_CONT_n_21,VAR_CONT_n_22,VAR_CONT_n_23,VAR_CONT_n_24,VAR_CONT_n_25,VAR_CONT_n_26,VAR_CONT_n_27,VAR_CONT_n_28,VAR_CONT_n_29,VAR_CONT_n_30,VAR_CONT_n_31,VAR_CONT_n_32,VAR_CONT_n_33,VAR_CONT_n_34,VAR_CONT_n_35,VAR_CONT_n_36}),
.E(inst_CORDIC_FSM_v3_n_9),
.\FSM_sequential_state_reg_reg[1] (inst_CORDIC_FSM_v3_n_7),
.\FSM_sequential_state_reg_reg[2] ({inst_CORDIC_FSM_v3_n_4,inst_CORDIC_FSM_v3_n_5}),
.Q(busy_OBUF),
.\Q_reg[31] ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}),
.\Q_reg[31]_0 ({VAR_CONT_n_37,VAR_CONT_n_38,VAR_CONT_n_39,VAR_CONT_n_40,VAR_CONT_n_41,VAR_CONT_n_42,VAR_CONT_n_43,VAR_CONT_n_44,VAR_CONT_n_45,VAR_CONT_n_46,VAR_CONT_n_47,VAR_CONT_n_48,VAR_CONT_n_49,VAR_CONT_n_50,VAR_CONT_n_51,VAR_CONT_n_52,VAR_CONT_n_53,VAR_CONT_n_54,VAR_CONT_n_55,VAR_CONT_n_56,VAR_CONT_n_57,VAR_CONT_n_58,VAR_CONT_n_59,VAR_CONT_n_60,VAR_CONT_n_61,VAR_CONT_n_62,VAR_CONT_n_63,VAR_CONT_n_64,VAR_CONT_n_65,VAR_CONT_n_66,VAR_CONT_n_67,VAR_CONT_n_68}),
.op_add_subt(op_add_subt),
.out(inst_FPU_PIPELINED_FPADDSUB_n_37),
.overflow_flag({overflow_flag_OBUF,underflow_flag_OBUF,zero_flag_OBUF}),
.ready_add_subt(ready_add_subt));
IBUF operation_IBUF_inst
(.I(operation),
.O(operation_IBUF));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
OBUF ready_cordic_OBUF_inst
(.I(ready_cordic_OBUF),
.O(ready_cordic));
d_ff_en__parameterized7 reg_LUT
(.CLK(clk_IBUF_BUFG),
.D({data_out_LUT[26:24],ITER_CONT_n_104,data_out_LUT[22:21],ITER_CONT_n_107,ITER_CONT_n_108,ITER_CONT_n_109,data_out_LUT[14],data_out_LUT[12:9],p_1_out,data_out_LUT[6],data_out_LUT[4],ITER_CONT_n_118,ITER_CONT_n_119,data_out_LUT[0]}),
.E(enab_RB3),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_LUT_n_0,reg_LUT_n_1,reg_LUT_n_2,reg_LUT_n_3,reg_LUT_n_4,reg_LUT_n_5,reg_LUT_n_6,reg_LUT_n_7,reg_LUT_n_8,reg_LUT_n_9,reg_LUT_n_10,reg_LUT_n_11,reg_LUT_n_12,reg_LUT_n_13,reg_LUT_n_14,reg_LUT_n_15,reg_LUT_n_16,reg_LUT_n_17,reg_LUT_n_18,reg_LUT_n_19,reg_LUT_n_20}));
d_ff_en__parameterized1 reg_Z0
(.CLK(clk_IBUF_BUFG),
.D(data_in_IBUF),
.E(enab_d_ff_RB1),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_Z0_n_0,reg_Z0_n_1,reg_Z0_n_2,reg_Z0_n_3,reg_Z0_n_4,reg_Z0_n_5,reg_Z0_n_6,reg_Z0_n_7,reg_Z0_n_8,reg_Z0_n_9,reg_Z0_n_10,reg_Z0_n_11,reg_Z0_n_12,reg_Z0_n_13,reg_Z0_n_14,reg_Z0_n_15,reg_Z0_n_16,reg_Z0_n_17,reg_Z0_n_18,reg_Z0_n_19,reg_Z0_n_20,reg_Z0_n_21,reg_Z0_n_22,reg_Z0_n_23,reg_Z0_n_24,reg_Z0_n_25,reg_Z0_n_26,reg_Z0_n_27,reg_Z0_n_28,reg_Z0_n_29,reg_Z0_n_30,reg_Z0_n_31}));
d_ff_en reg_operation
(.CLK(clk_IBUF_BUFG),
.E(enab_d_ff_RB1),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.d_ff1_operation_out(d_ff1_operation_out),
.operation_IBUF(operation_IBUF));
d_ff_en__parameterized0 reg_region_flag
(.CLK(clk_IBUF_BUFG),
.D({reg_region_flag_n_0,reg_region_flag_n_1,reg_region_flag_n_2,reg_region_flag_n_3,reg_region_flag_n_4,reg_region_flag_n_5,reg_region_flag_n_6,reg_region_flag_n_7,reg_region_flag_n_8,reg_region_flag_n_9,reg_region_flag_n_10,reg_region_flag_n_11,reg_region_flag_n_12,reg_region_flag_n_13,reg_region_flag_n_14,reg_region_flag_n_15,reg_region_flag_n_16,reg_region_flag_n_17,reg_region_flag_n_18,reg_region_flag_n_19,reg_region_flag_n_20,reg_region_flag_n_21,reg_region_flag_n_22,reg_region_flag_n_23,reg_region_flag_n_24,reg_region_flag_n_25,reg_region_flag_n_26,reg_region_flag_n_27,reg_region_flag_n_28,reg_region_flag_n_29,reg_region_flag_n_30,reg_region_flag_n_31}),
.E(enab_d_ff_RB1),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({d_ff4_Yn_n_0,d_ff4_Yn_n_1,d_ff4_Yn_n_2,d_ff4_Yn_n_3,d_ff4_Yn_n_4,d_ff4_Yn_n_5,d_ff4_Yn_n_6,d_ff4_Yn_n_7,d_ff4_Yn_n_8,d_ff4_Yn_n_9,d_ff4_Yn_n_10,d_ff4_Yn_n_11,d_ff4_Yn_n_12,d_ff4_Yn_n_13,d_ff4_Yn_n_14,d_ff4_Yn_n_15,d_ff4_Yn_n_16,d_ff4_Yn_n_17,d_ff4_Yn_n_18,d_ff4_Yn_n_19,d_ff4_Yn_n_20,d_ff4_Yn_n_21,d_ff4_Yn_n_22,d_ff4_Yn_n_23,d_ff4_Yn_n_24,d_ff4_Yn_n_25,d_ff4_Yn_n_26,d_ff4_Yn_n_27,d_ff4_Yn_n_28,d_ff4_Yn_n_29,d_ff4_Yn_n_30,d_ff4_Yn_n_31}),
.\Q_reg[31] ({d_ff4_Xn_n_0,d_ff4_Xn_n_1,d_ff4_Xn_n_2,d_ff4_Xn_n_3,d_ff4_Xn_n_4,d_ff4_Xn_n_5,d_ff4_Xn_n_6,d_ff4_Xn_n_7,d_ff4_Xn_n_8,d_ff4_Xn_n_9,d_ff4_Xn_n_10,d_ff4_Xn_n_11,d_ff4_Xn_n_12,d_ff4_Xn_n_13,d_ff4_Xn_n_14,d_ff4_Xn_n_15,d_ff4_Xn_n_16,d_ff4_Xn_n_17,d_ff4_Xn_n_18,d_ff4_Xn_n_19,d_ff4_Xn_n_20,d_ff4_Xn_n_21,d_ff4_Xn_n_22,d_ff4_Xn_n_23,d_ff4_Xn_n_24,d_ff4_Xn_n_25,d_ff4_Xn_n_26,d_ff4_Xn_n_27,d_ff4_Xn_n_28,d_ff4_Xn_n_29,d_ff4_Xn_n_30,d_ff4_Xn_n_31}),
.d_ff1_operation_out(d_ff1_operation_out),
.\shift_region_flag[1] (shift_region_flag_IBUF));
d_ff_en__parameterized5 reg_shift_x
(.CLK(clk_IBUF_BUFG),
.D({reg_val_muxX_2stage_n_4,Y,reg_val_muxX_2stage_n_13,reg_val_muxX_2stage_n_14,reg_val_muxX_2stage_n_15,reg_val_muxX_2stage_n_16,reg_val_muxX_2stage_n_17,reg_val_muxX_2stage_n_18,reg_val_muxX_2stage_n_19,reg_val_muxX_2stage_n_20,reg_val_muxX_2stage_n_21,reg_val_muxX_2stage_n_22,reg_val_muxX_2stage_n_23,reg_val_muxX_2stage_n_24,reg_val_muxX_2stage_n_25,reg_val_muxX_2stage_n_26,reg_val_muxX_2stage_n_27,reg_val_muxX_2stage_n_28,reg_val_muxX_2stage_n_29,reg_val_muxX_2stage_n_30,reg_val_muxX_2stage_n_31,reg_val_muxX_2stage_n_32,reg_val_muxX_2stage_n_33,reg_val_muxX_2stage_n_34,reg_val_muxX_2stage_n_35}),
.E(enab_RB3),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_shift_x_n_0,reg_shift_x_n_1,reg_shift_x_n_2,reg_shift_x_n_3,reg_shift_x_n_4,reg_shift_x_n_5,reg_shift_x_n_6,reg_shift_x_n_7,reg_shift_x_n_8,reg_shift_x_n_9,reg_shift_x_n_10,reg_shift_x_n_11,reg_shift_x_n_12,reg_shift_x_n_13,reg_shift_x_n_14,reg_shift_x_n_15,reg_shift_x_n_16,reg_shift_x_n_17,reg_shift_x_n_18,reg_shift_x_n_19,reg_shift_x_n_20,reg_shift_x_n_21,reg_shift_x_n_22,reg_shift_x_n_23,reg_shift_x_n_24,reg_shift_x_n_25,reg_shift_x_n_26,reg_shift_x_n_27,reg_shift_x_n_28,reg_shift_x_n_29,reg_shift_x_n_30,reg_shift_x_n_31}));
d_ff_en__parameterized6 reg_shift_y
(.CLK(clk_IBUF_BUFG),
.D({d_ff2_Y,reg_val_muxY_2stage_n_32,reg_val_muxY_2stage_n_33,reg_val_muxY_2stage_n_34,reg_val_muxY_2stage_n_35,reg_val_muxY_2stage_n_36,reg_val_muxY_2stage_n_37,reg_val_muxY_2stage_n_38,reg_val_muxY_2stage_n_39,reg_val_muxY_2stage_n_9,reg_val_muxY_2stage_n_10,reg_val_muxY_2stage_n_11,reg_val_muxY_2stage_n_12,reg_val_muxY_2stage_n_13,reg_val_muxY_2stage_n_14,reg_val_muxY_2stage_n_15,reg_val_muxY_2stage_n_16,reg_val_muxY_2stage_n_17,reg_val_muxY_2stage_n_18,reg_val_muxY_2stage_n_19,reg_val_muxY_2stage_n_20,reg_val_muxY_2stage_n_21,reg_val_muxY_2stage_n_22,reg_val_muxY_2stage_n_23,reg_val_muxY_2stage_n_24,reg_val_muxY_2stage_n_25,reg_val_muxY_2stage_n_26,reg_val_muxY_2stage_n_27,reg_val_muxY_2stage_n_28,reg_val_muxY_2stage_n_29,reg_val_muxY_2stage_n_30,reg_val_muxY_2stage_n_31}),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.\FSM_sequential_state_reg_reg[2] (enab_RB3),
.Q({reg_shift_y_n_0,reg_shift_y_n_1,reg_shift_y_n_2,reg_shift_y_n_3,reg_shift_y_n_4,reg_shift_y_n_5,reg_shift_y_n_6,reg_shift_y_n_7,reg_shift_y_n_8,reg_shift_y_n_9,reg_shift_y_n_10,reg_shift_y_n_11,reg_shift_y_n_12,reg_shift_y_n_13,reg_shift_y_n_14,reg_shift_y_n_15,reg_shift_y_n_16,reg_shift_y_n_17,reg_shift_y_n_18,reg_shift_y_n_19,reg_shift_y_n_20,reg_shift_y_n_21,reg_shift_y_n_22,reg_shift_y_n_23,reg_shift_y_n_24,reg_shift_y_n_25,reg_shift_y_n_26,reg_shift_y_n_27,reg_shift_y_n_28,reg_shift_y_n_29,reg_shift_y_n_30,reg_shift_y_n_31}));
d_ff_en_0 reg_sign
(.CLK(clk_IBUF_BUFG),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.\FSM_sequential_state_reg_reg[2] (enab_RB3),
.Q(d_ff2_Z),
.d_ff3_sign_out(d_ff3_sign_out));
d_ff_en__parameterized2 reg_val_muxX_2stage
(.CLK(clk_IBUF_BUFG),
.D({ITER_CONT_n_37,ITER_CONT_n_38,ITER_CONT_n_39,ITER_CONT_n_40,ITER_CONT_n_41,ITER_CONT_n_42,ITER_CONT_n_43,ITER_CONT_n_44,ITER_CONT_n_45,ITER_CONT_n_46,ITER_CONT_n_47,ITER_CONT_n_48,ITER_CONT_n_49,ITER_CONT_n_50,ITER_CONT_n_51,ITER_CONT_n_52,ITER_CONT_n_53,ITER_CONT_n_54,ITER_CONT_n_55,ITER_CONT_n_56,ITER_CONT_n_57,ITER_CONT_n_58,ITER_CONT_n_59,ITER_CONT_n_60,ITER_CONT_n_61,ITER_CONT_n_62,ITER_CONT_n_63,ITER_CONT_n_64,ITER_CONT_n_65,ITER_CONT_n_66,ITER_CONT_n_67,ITER_CONT_n_68}),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_val_muxX_2stage_n_4,A,reg_val_muxX_2stage_n_13,reg_val_muxX_2stage_n_14,reg_val_muxX_2stage_n_15,reg_val_muxX_2stage_n_16,reg_val_muxX_2stage_n_17,reg_val_muxX_2stage_n_18,reg_val_muxX_2stage_n_19,reg_val_muxX_2stage_n_20,reg_val_muxX_2stage_n_21,reg_val_muxX_2stage_n_22,reg_val_muxX_2stage_n_23,reg_val_muxX_2stage_n_24,reg_val_muxX_2stage_n_25,reg_val_muxX_2stage_n_26,reg_val_muxX_2stage_n_27,reg_val_muxX_2stage_n_28,reg_val_muxX_2stage_n_29,reg_val_muxX_2stage_n_30,reg_val_muxX_2stage_n_31,reg_val_muxX_2stage_n_32,reg_val_muxX_2stage_n_33,reg_val_muxX_2stage_n_34,reg_val_muxX_2stage_n_35}),
.\Q_reg[26]_0 ({reg_val_muxX_2stage_n_36,reg_val_muxX_2stage_n_37,reg_val_muxX_2stage_n_38,reg_val_muxX_2stage_n_39}),
.S({reg_val_muxX_2stage_n_0,reg_val_muxX_2stage_n_1,reg_val_muxX_2stage_n_2,reg_val_muxX_2stage_n_3}),
.\temp_reg[3] (cont_iter_out));
d_ff_en__parameterized3 reg_val_muxY_2stage
(.CLK(clk_IBUF_BUFG),
.D({reg_val_muxY_2stage_n_32,reg_val_muxY_2stage_n_33,reg_val_muxY_2stage_n_34,reg_val_muxY_2stage_n_35,reg_val_muxY_2stage_n_36,reg_val_muxY_2stage_n_37,reg_val_muxY_2stage_n_38,reg_val_muxY_2stage_n_39}),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({d_ff2_Y,reg_val_muxY_2stage_n_1,reg_val_muxY_2stage_n_2,reg_val_muxY_2stage_n_3,reg_val_muxY_2stage_n_4,reg_val_muxY_2stage_n_5,reg_val_muxY_2stage_n_6,reg_val_muxY_2stage_n_7,reg_val_muxY_2stage_n_8,reg_val_muxY_2stage_n_9,reg_val_muxY_2stage_n_10,reg_val_muxY_2stage_n_11,reg_val_muxY_2stage_n_12,reg_val_muxY_2stage_n_13,reg_val_muxY_2stage_n_14,reg_val_muxY_2stage_n_15,reg_val_muxY_2stage_n_16,reg_val_muxY_2stage_n_17,reg_val_muxY_2stage_n_18,reg_val_muxY_2stage_n_19,reg_val_muxY_2stage_n_20,reg_val_muxY_2stage_n_21,reg_val_muxY_2stage_n_22,reg_val_muxY_2stage_n_23,reg_val_muxY_2stage_n_24,reg_val_muxY_2stage_n_25,reg_val_muxY_2stage_n_26,reg_val_muxY_2stage_n_27,reg_val_muxY_2stage_n_28,reg_val_muxY_2stage_n_29,reg_val_muxY_2stage_n_30,reg_val_muxY_2stage_n_31}),
.\temp_reg[3] (cont_iter_out),
.\temp_reg[3]_0 ({ITER_CONT_n_69,ITER_CONT_n_70,ITER_CONT_n_71,ITER_CONT_n_72,ITER_CONT_n_73,ITER_CONT_n_74,ITER_CONT_n_75,ITER_CONT_n_76,ITER_CONT_n_77,ITER_CONT_n_78,ITER_CONT_n_79,ITER_CONT_n_80,ITER_CONT_n_81,ITER_CONT_n_82,ITER_CONT_n_83,ITER_CONT_n_84,ITER_CONT_n_85,ITER_CONT_n_86,ITER_CONT_n_87,ITER_CONT_n_88,ITER_CONT_n_89,ITER_CONT_n_90,ITER_CONT_n_91,ITER_CONT_n_92,ITER_CONT_n_93,ITER_CONT_n_94,ITER_CONT_n_95,ITER_CONT_n_96,ITER_CONT_n_97,ITER_CONT_n_98,ITER_CONT_n_99,ITER_CONT_n_100}));
d_ff_en__parameterized4 reg_val_muxZ_2stage
(.CLK(clk_IBUF_BUFG),
.D({ITER_CONT_n_5,ITER_CONT_n_6,ITER_CONT_n_7,ITER_CONT_n_8,ITER_CONT_n_9,ITER_CONT_n_10,ITER_CONT_n_11,ITER_CONT_n_12,ITER_CONT_n_13,ITER_CONT_n_14,ITER_CONT_n_15,ITER_CONT_n_16,ITER_CONT_n_17,ITER_CONT_n_18,ITER_CONT_n_19,ITER_CONT_n_20,ITER_CONT_n_21,ITER_CONT_n_22,ITER_CONT_n_23,ITER_CONT_n_24,ITER_CONT_n_25,ITER_CONT_n_26,ITER_CONT_n_27,ITER_CONT_n_28,ITER_CONT_n_29,ITER_CONT_n_30,ITER_CONT_n_31,ITER_CONT_n_32,ITER_CONT_n_33,ITER_CONT_n_34,ITER_CONT_n_35,ITER_CONT_n_36}),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({d_ff2_Z,reg_val_muxZ_2stage_n_1,reg_val_muxZ_2stage_n_2,reg_val_muxZ_2stage_n_3,reg_val_muxZ_2stage_n_4,reg_val_muxZ_2stage_n_5,reg_val_muxZ_2stage_n_6,reg_val_muxZ_2stage_n_7,reg_val_muxZ_2stage_n_8,reg_val_muxZ_2stage_n_9,reg_val_muxZ_2stage_n_10,reg_val_muxZ_2stage_n_11,reg_val_muxZ_2stage_n_12,reg_val_muxZ_2stage_n_13,reg_val_muxZ_2stage_n_14,reg_val_muxZ_2stage_n_15,reg_val_muxZ_2stage_n_16,reg_val_muxZ_2stage_n_17,reg_val_muxZ_2stage_n_18,reg_val_muxZ_2stage_n_19,reg_val_muxZ_2stage_n_20,reg_val_muxZ_2stage_n_21,reg_val_muxZ_2stage_n_22,reg_val_muxZ_2stage_n_23,reg_val_muxZ_2stage_n_24,reg_val_muxZ_2stage_n_25,reg_val_muxZ_2stage_n_26,reg_val_muxZ_2stage_n_27,reg_val_muxZ_2stage_n_28,reg_val_muxZ_2stage_n_29,reg_val_muxZ_2stage_n_30,reg_val_muxZ_2stage_n_31}));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
IBUF \shift_region_flag_IBUF[0]_inst
(.I(shift_region_flag[0]),
.O(shift_region_flag_IBUF[0]));
IBUF \shift_region_flag_IBUF[1]_inst
(.I(shift_region_flag[1]),
.O(shift_region_flag_IBUF[1]));
Simple_Subt shift_x
(.D(Y),
.Q(A[6:0]),
.\Q_reg[26] ({reg_val_muxX_2stage_n_36,reg_val_muxX_2stage_n_37,reg_val_muxX_2stage_n_38,reg_val_muxX_2stage_n_39}),
.S({reg_val_muxX_2stage_n_0,reg_val_muxX_2stage_n_1,reg_val_muxX_2stage_n_2,reg_val_muxX_2stage_n_3}));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
OBUF zero_flag_OBUF_inst
(.I(zero_flag_OBUF),
.O(zero_flag));
endmodule |
module CORDIC_FSM_v3
(AR,
out,
\FSM_sequential_state_reg_reg[0]_0 ,
E,
\Q_reg[31] ,
\Q_reg[31]_0 ,
\Q_reg[0] ,
\Q_reg[1] ,
\temp_reg[0] ,
ready_cordic_OBUF,
\Q_reg[31]_1 ,
rst_IBUF,
\FSM_sequential_state_reg_reg[2]_0 ,
CLK,
max_tick_iter,
\temp_reg[1] ,
ack_cordic_IBUF,
cont_var_out,
beg_fsm_cordic_IBUF);
output [3:0]AR;
output [2:0]out;
output [0:0]\FSM_sequential_state_reg_reg[0]_0 ;
output [0:0]E;
output [0:0]\Q_reg[31] ;
output [0:0]\Q_reg[31]_0 ;
output [0:0]\Q_reg[0] ;
output [0:0]\Q_reg[1] ;
output [0:0]\temp_reg[0] ;
output ready_cordic_OBUF;
output [0:0]\Q_reg[31]_1 ;
input rst_IBUF;
input [0:0]\FSM_sequential_state_reg_reg[2]_0 ;
input CLK;
input max_tick_iter;
input [0:0]\temp_reg[1] ;
input ack_cordic_IBUF;
input [1:0]cont_var_out;
input beg_fsm_cordic_IBUF;
wire [3:0]AR;
wire CLK;
wire [0:0]E;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[0]_i_2_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire [0:0]\FSM_sequential_state_reg_reg[0]_0 ;
wire [0:0]\FSM_sequential_state_reg_reg[2]_0 ;
wire [0:0]\Q_reg[0] ;
wire [0:0]\Q_reg[1] ;
wire [0:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [0:0]\Q_reg[31]_1 ;
wire ack_cordic_IBUF;
wire beg_fsm_cordic_IBUF;
wire [1:0]cont_var_out;
wire max_tick_iter;
(* RTL_KEEP = "yes" *) wire [2:0]out;
wire ready_cordic_OBUF;
wire rst_IBUF;
wire [0:0]\temp_reg[0] ;
wire [0:0]\temp_reg[1] ;
LUT6 #(
.INIT(64'h02A2FFFF02A20000))
\FSM_sequential_state_reg[0]_i_1
(.I0(out[2]),
.I1(\temp_reg[1] ),
.I2(out[1]),
.I3(ack_cordic_IBUF),
.I4(out[0]),
.I5(\FSM_sequential_state_reg[0]_i_2_n_0 ),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB888FFFFB888CCCC))
\FSM_sequential_state_reg[0]_i_2
(.I0(max_tick_iter),
.I1(out[1]),
.I2(cont_var_out[1]),
.I3(cont_var_out[0]),
.I4(out[2]),
.I5(beg_fsm_cordic_IBUF),
.O(\FSM_sequential_state_reg[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h7C3C4C3C))
\FSM_sequential_state_reg[1]_i_1
(.I0(ack_cordic_IBUF),
.I1(out[1]),
.I2(out[0]),
.I3(out[2]),
.I4(\temp_reg[1] ),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'h74FFCC00))
\FSM_sequential_state_reg[2]_i_1
(.I0(ack_cordic_IBUF),
.I1(out[0]),
.I2(max_tick_iter),
.I3(out[1]),
.I4(out[2]),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFF08))
\FSM_sequential_state_reg[2]_i_2__0
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(\FSM_sequential_state_reg_reg[0]_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(rst_IBUF),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(out[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(rst_IBUF),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(out[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(rst_IBUF),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(out[2]));
LUT4 #(
.INIT(16'hFF08))
\Q[0]_i_1__7
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[2]));
LUT4 #(
.INIT(16'hFF08))
\Q[14]_i_2
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[3]));
LUT3 #(
.INIT(8'h02))
\Q[1]_i_1
(.I0(out[0]),
.I1(out[2]),
.I2(out[1]),
.O(\Q_reg[1] ));
LUT3 #(
.INIT(8'h01))
\Q[1]_i_2
(.I0(out[1]),
.I1(out[0]),
.I2(out[2]),
.O(\Q_reg[31]_1 ));
LUT3 #(
.INIT(8'h40))
\Q[29]_i_1
(.I0(out[2]),
.I1(out[0]),
.I2(out[1]),
.O(\Q_reg[0] ));
LUT4 #(
.INIT(16'hA800))
\Q[31]_i_1
(.I0(out[2]),
.I1(out[0]),
.I2(max_tick_iter),
.I3(out[1]),
.O(\Q_reg[31]_0 ));
LUT3 #(
.INIT(8'h02))
\Q[31]_i_1__7
(.I0(out[1]),
.I1(out[0]),
.I2(out[2]),
.O(E));
LUT3 #(
.INIT(8'h04))
\Q[31]_i_1__8
(.I0(out[1]),
.I1(out[2]),
.I2(\FSM_sequential_state_reg_reg[2]_0 ),
.O(\Q_reg[31] ));
LUT4 #(
.INIT(16'hFF08))
\Q[31]_i_2
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[1]));
LUT4 #(
.INIT(16'hFF08))
\Q[6]_i_2
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[0]));
LUT3 #(
.INIT(8'h80))
ready_cordic_OBUF_inst_i_1
(.I0(out[1]),
.I1(out[0]),
.I2(out[2]),
.O(ready_cordic_OBUF));
LUT3 #(
.INIT(8'h40))
\temp[3]_i_1
(.I0(out[0]),
.I1(out[2]),
.I2(out[1]),
.O(\temp_reg[0] ));
endmodule |
module Comparator
(CO,
\Q_reg[2] ,
\Q_reg[6] ,
S,
\Q_reg[14] ,
\Q_reg[14]_0 ,
\Q_reg[22] ,
\Q_reg[22]_0 ,
DI,
\Q_reg[30] ,
\Q_reg[9] ,
\Q_reg[21] ,
\Q_reg[30]_0 );
output [0:0]CO;
output [0:0]\Q_reg[2] ;
input [3:0]\Q_reg[6] ;
input [3:0]S;
input [3:0]\Q_reg[14] ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[22] ;
input [3:0]\Q_reg[22]_0 ;
input [3:0]DI;
input [3:0]\Q_reg[30] ;
input [3:0]\Q_reg[9] ;
input [3:0]\Q_reg[21] ;
input [2:0]\Q_reg[30]_0 ;
wire [0:0]CO;
wire [3:0]DI;
wire [3:0]\Q_reg[14] ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[21] ;
wire [3:0]\Q_reg[22] ;
wire [3:0]\Q_reg[22]_0 ;
wire [0:0]\Q_reg[2] ;
wire [3:0]\Q_reg[30] ;
wire [2:0]\Q_reg[30]_0 ;
wire [3:0]\Q_reg[6] ;
wire [3:0]\Q_reg[9] ;
wire [3:0]S;
wire eqXY_o_carry__0_n_0;
wire eqXY_o_carry__0_n_1;
wire eqXY_o_carry__0_n_2;
wire eqXY_o_carry__0_n_3;
wire eqXY_o_carry__1_n_2;
wire eqXY_o_carry__1_n_3;
wire eqXY_o_carry_n_0;
wire eqXY_o_carry_n_1;
wire eqXY_o_carry_n_2;
wire eqXY_o_carry_n_3;
wire gtXY_o_carry__0_n_0;
wire gtXY_o_carry__0_n_1;
wire gtXY_o_carry__0_n_2;
wire gtXY_o_carry__0_n_3;
wire gtXY_o_carry__1_n_0;
wire gtXY_o_carry__1_n_1;
wire gtXY_o_carry__1_n_2;
wire gtXY_o_carry__1_n_3;
wire gtXY_o_carry__2_n_1;
wire gtXY_o_carry__2_n_2;
wire gtXY_o_carry__2_n_3;
wire gtXY_o_carry_n_0;
wire gtXY_o_carry_n_1;
wire gtXY_o_carry_n_2;
wire gtXY_o_carry_n_3;
wire [3:0]NLW_eqXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__0_O_UNCONNECTED;
wire [3:3]NLW_eqXY_o_carry__1_CO_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__0_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__2_O_UNCONNECTED;
CARRY4 eqXY_o_carry
(.CI(1'b0),
.CO({eqXY_o_carry_n_0,eqXY_o_carry_n_1,eqXY_o_carry_n_2,eqXY_o_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry_O_UNCONNECTED[3:0]),
.S(\Q_reg[9] ));
CARRY4 eqXY_o_carry__0
(.CI(eqXY_o_carry_n_0),
.CO({eqXY_o_carry__0_n_0,eqXY_o_carry__0_n_1,eqXY_o_carry__0_n_2,eqXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[21] ));
CARRY4 eqXY_o_carry__1
(.CI(eqXY_o_carry__0_n_0),
.CO({NLW_eqXY_o_carry__1_CO_UNCONNECTED[3],\Q_reg[2] ,eqXY_o_carry__1_n_2,eqXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__1_O_UNCONNECTED[3:0]),
.S({1'b0,\Q_reg[30]_0 }));
CARRY4 gtXY_o_carry
(.CI(1'b0),
.CO({gtXY_o_carry_n_0,gtXY_o_carry_n_1,gtXY_o_carry_n_2,gtXY_o_carry_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[6] ),
.O(NLW_gtXY_o_carry_O_UNCONNECTED[3:0]),
.S(S));
CARRY4 gtXY_o_carry__0
(.CI(gtXY_o_carry_n_0),
.CO({gtXY_o_carry__0_n_0,gtXY_o_carry__0_n_1,gtXY_o_carry__0_n_2,gtXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[14] ),
.O(NLW_gtXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[14]_0 ));
CARRY4 gtXY_o_carry__1
(.CI(gtXY_o_carry__0_n_0),
.CO({gtXY_o_carry__1_n_0,gtXY_o_carry__1_n_1,gtXY_o_carry__1_n_2,gtXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[22] ),
.O(NLW_gtXY_o_carry__1_O_UNCONNECTED[3:0]),
.S(\Q_reg[22]_0 ));
CARRY4 gtXY_o_carry__2
(.CI(gtXY_o_carry__1_n_0),
.CO({CO,gtXY_o_carry__2_n_1,gtXY_o_carry__2_n_2,gtXY_o_carry__2_n_3}),
.CYINIT(1'b0),
.DI(DI),
.O(NLW_gtXY_o_carry__2_O_UNCONNECTED[3:0]),
.S(\Q_reg[30] ));
endmodule |
module FPU_PIPELINED_FPADDSUB
(ready_add_subt,
Q,
\Q_reg[31] ,
overflow_flag,
out,
CLK,
AR,
E,
op_add_subt,
\FSM_sequential_state_reg_reg[1] ,
D,
\Q_reg[31]_0 ,
\FSM_sequential_state_reg_reg[2] );
output ready_add_subt;
output [0:0]Q;
output [31:0]\Q_reg[31] ;
output [2:0]overflow_flag;
output [0:0]out;
input CLK;
input [3:0]AR;
input [0:0]E;
input op_add_subt;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [31:0]D;
input [31:0]\Q_reg[31]_0 ;
input [1:0]\FSM_sequential_state_reg_reg[2] ;
wire ADD_OVRFLW_NRM;
wire ADD_OVRFLW_NRM2;
wire [3:0]AR;
wire CLK;
wire [31:0]D;
wire [24:2]DMP_mant_SFG_SWR;
wire [25:0]\Data_array_SWR[2]_1 ;
wire [25:18]\Data_array_SWR[3]_0 ;
wire [15:14]\Data_array_SWR[4]_4 ;
wire [17:2]\Data_array_SWR[5]_2 ;
wire [25:1]\Data_array_SWR[6]_3 ;
wire [0:0]E;
wire EXP_STAGE_DMP_n_1;
wire EXP_STAGE_DMP_n_10;
wire EXP_STAGE_DMP_n_11;
wire EXP_STAGE_DMP_n_12;
wire EXP_STAGE_DMP_n_13;
wire EXP_STAGE_DMP_n_14;
wire EXP_STAGE_DMP_n_15;
wire EXP_STAGE_DMP_n_16;
wire EXP_STAGE_DMP_n_17;
wire EXP_STAGE_DMP_n_18;
wire EXP_STAGE_DMP_n_19;
wire EXP_STAGE_DMP_n_2;
wire EXP_STAGE_DMP_n_20;
wire EXP_STAGE_DMP_n_21;
wire EXP_STAGE_DMP_n_22;
wire EXP_STAGE_DMP_n_23;
wire EXP_STAGE_DMP_n_24;
wire EXP_STAGE_DMP_n_25;
wire EXP_STAGE_DMP_n_26;
wire EXP_STAGE_DMP_n_27;
wire EXP_STAGE_DMP_n_28;
wire EXP_STAGE_DMP_n_29;
wire EXP_STAGE_DMP_n_3;
wire EXP_STAGE_DMP_n_30;
wire EXP_STAGE_DMP_n_31;
wire EXP_STAGE_DMP_n_32;
wire EXP_STAGE_DMP_n_4;
wire EXP_STAGE_DMP_n_5;
wire EXP_STAGE_DMP_n_6;
wire EXP_STAGE_DMP_n_7;
wire EXP_STAGE_DMP_n_8;
wire EXP_STAGE_DMP_n_9;
wire EXP_STAGE_DmP_n_10;
wire EXP_STAGE_DmP_n_11;
wire EXP_STAGE_DmP_n_12;
wire EXP_STAGE_DmP_n_13;
wire EXP_STAGE_DmP_n_14;
wire EXP_STAGE_DmP_n_15;
wire EXP_STAGE_DmP_n_16;
wire EXP_STAGE_DmP_n_17;
wire EXP_STAGE_DmP_n_18;
wire EXP_STAGE_DmP_n_19;
wire EXP_STAGE_DmP_n_20;
wire EXP_STAGE_DmP_n_21;
wire EXP_STAGE_DmP_n_22;
wire EXP_STAGE_DmP_n_23;
wire EXP_STAGE_DmP_n_24;
wire EXP_STAGE_DmP_n_25;
wire EXP_STAGE_DmP_n_26;
wire EXP_STAGE_DmP_n_27;
wire EXP_STAGE_DmP_n_28;
wire EXP_STAGE_DmP_n_3;
wire EXP_STAGE_DmP_n_4;
wire EXP_STAGE_DmP_n_5;
wire EXP_STAGE_DmP_n_6;
wire EXP_STAGE_DmP_n_7;
wire EXP_STAGE_DmP_n_8;
wire EXP_STAGE_DmP_n_9;
wire EXP_STAGE_FLAGS_n_0;
wire EXP_STAGE_FLAGS_n_1;
wire EXP_STAGE_FLAGS_n_2;
wire FSM_enable_input_internal;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [1:0]\FSM_sequential_state_reg_reg[2] ;
wire INPUT_STAGE_FLAGS_n_1;
wire INPUT_STAGE_OPERANDX_n_0;
wire INPUT_STAGE_OPERANDX_n_1;
wire INPUT_STAGE_OPERANDX_n_10;
wire INPUT_STAGE_OPERANDX_n_11;
wire INPUT_STAGE_OPERANDX_n_12;
wire INPUT_STAGE_OPERANDX_n_13;
wire INPUT_STAGE_OPERANDX_n_14;
wire INPUT_STAGE_OPERANDX_n_15;
wire INPUT_STAGE_OPERANDX_n_16;
wire INPUT_STAGE_OPERANDX_n_17;
wire INPUT_STAGE_OPERANDX_n_18;
wire INPUT_STAGE_OPERANDX_n_19;
wire INPUT_STAGE_OPERANDX_n_2;
wire INPUT_STAGE_OPERANDX_n_20;
wire INPUT_STAGE_OPERANDX_n_21;
wire INPUT_STAGE_OPERANDX_n_22;
wire INPUT_STAGE_OPERANDX_n_23;
wire INPUT_STAGE_OPERANDX_n_24;
wire INPUT_STAGE_OPERANDX_n_25;
wire INPUT_STAGE_OPERANDX_n_26;
wire INPUT_STAGE_OPERANDX_n_27;
wire INPUT_STAGE_OPERANDX_n_28;
wire INPUT_STAGE_OPERANDX_n_29;
wire INPUT_STAGE_OPERANDX_n_3;
wire INPUT_STAGE_OPERANDX_n_30;
wire INPUT_STAGE_OPERANDX_n_31;
wire INPUT_STAGE_OPERANDX_n_32;
wire INPUT_STAGE_OPERANDX_n_33;
wire INPUT_STAGE_OPERANDX_n_34;
wire INPUT_STAGE_OPERANDX_n_35;
wire INPUT_STAGE_OPERANDX_n_36;
wire INPUT_STAGE_OPERANDX_n_37;
wire INPUT_STAGE_OPERANDX_n_38;
wire INPUT_STAGE_OPERANDX_n_39;
wire INPUT_STAGE_OPERANDX_n_40;
wire INPUT_STAGE_OPERANDX_n_41;
wire INPUT_STAGE_OPERANDX_n_42;
wire INPUT_STAGE_OPERANDX_n_43;
wire INPUT_STAGE_OPERANDX_n_44;
wire INPUT_STAGE_OPERANDX_n_45;
wire INPUT_STAGE_OPERANDX_n_46;
wire INPUT_STAGE_OPERANDX_n_47;
wire INPUT_STAGE_OPERANDX_n_48;
wire INPUT_STAGE_OPERANDX_n_49;
wire INPUT_STAGE_OPERANDX_n_5;
wire INPUT_STAGE_OPERANDX_n_50;
wire INPUT_STAGE_OPERANDX_n_51;
wire INPUT_STAGE_OPERANDX_n_52;
wire INPUT_STAGE_OPERANDX_n_53;
wire INPUT_STAGE_OPERANDX_n_54;
wire INPUT_STAGE_OPERANDX_n_55;
wire INPUT_STAGE_OPERANDX_n_56;
wire INPUT_STAGE_OPERANDX_n_57;
wire INPUT_STAGE_OPERANDX_n_58;
wire INPUT_STAGE_OPERANDX_n_59;
wire INPUT_STAGE_OPERANDX_n_6;
wire INPUT_STAGE_OPERANDX_n_60;
wire INPUT_STAGE_OPERANDX_n_61;
wire INPUT_STAGE_OPERANDX_n_62;
wire INPUT_STAGE_OPERANDX_n_63;
wire INPUT_STAGE_OPERANDX_n_64;
wire INPUT_STAGE_OPERANDX_n_65;
wire INPUT_STAGE_OPERANDX_n_66;
wire INPUT_STAGE_OPERANDX_n_67;
wire INPUT_STAGE_OPERANDX_n_68;
wire INPUT_STAGE_OPERANDX_n_69;
wire INPUT_STAGE_OPERANDX_n_7;
wire INPUT_STAGE_OPERANDX_n_70;
wire INPUT_STAGE_OPERANDX_n_71;
wire INPUT_STAGE_OPERANDX_n_72;
wire INPUT_STAGE_OPERANDX_n_8;
wire INPUT_STAGE_OPERANDX_n_9;
wire INPUT_STAGE_OPERANDY_n_0;
wire INPUT_STAGE_OPERANDY_n_10;
wire INPUT_STAGE_OPERANDY_n_11;
wire INPUT_STAGE_OPERANDY_n_12;
wire INPUT_STAGE_OPERANDY_n_13;
wire INPUT_STAGE_OPERANDY_n_14;
wire INPUT_STAGE_OPERANDY_n_15;
wire INPUT_STAGE_OPERANDY_n_16;
wire INPUT_STAGE_OPERANDY_n_17;
wire INPUT_STAGE_OPERANDY_n_18;
wire INPUT_STAGE_OPERANDY_n_19;
wire INPUT_STAGE_OPERANDY_n_2;
wire INPUT_STAGE_OPERANDY_n_20;
wire INPUT_STAGE_OPERANDY_n_21;
wire INPUT_STAGE_OPERANDY_n_22;
wire INPUT_STAGE_OPERANDY_n_23;
wire INPUT_STAGE_OPERANDY_n_24;
wire INPUT_STAGE_OPERANDY_n_25;
wire INPUT_STAGE_OPERANDY_n_26;
wire INPUT_STAGE_OPERANDY_n_27;
wire INPUT_STAGE_OPERANDY_n_28;
wire INPUT_STAGE_OPERANDY_n_29;
wire INPUT_STAGE_OPERANDY_n_3;
wire INPUT_STAGE_OPERANDY_n_30;
wire INPUT_STAGE_OPERANDY_n_31;
wire INPUT_STAGE_OPERANDY_n_32;
wire INPUT_STAGE_OPERANDY_n_33;
wire INPUT_STAGE_OPERANDY_n_4;
wire INPUT_STAGE_OPERANDY_n_5;
wire INPUT_STAGE_OPERANDY_n_6;
wire INPUT_STAGE_OPERANDY_n_7;
wire INPUT_STAGE_OPERANDY_n_8;
wire INPUT_STAGE_OPERANDY_n_9;
wire [4:0]LZD_raw_out_EWR;
wire MuxXY_n_0;
wire MuxXY_n_1;
wire MuxXY_n_10;
wire MuxXY_n_11;
wire MuxXY_n_12;
wire MuxXY_n_13;
wire MuxXY_n_14;
wire MuxXY_n_15;
wire MuxXY_n_16;
wire MuxXY_n_17;
wire MuxXY_n_18;
wire MuxXY_n_19;
wire MuxXY_n_2;
wire MuxXY_n_20;
wire MuxXY_n_21;
wire MuxXY_n_22;
wire MuxXY_n_23;
wire MuxXY_n_24;
wire MuxXY_n_25;
wire MuxXY_n_26;
wire MuxXY_n_27;
wire MuxXY_n_28;
wire MuxXY_n_29;
wire MuxXY_n_3;
wire MuxXY_n_30;
wire MuxXY_n_31;
wire MuxXY_n_32;
wire MuxXY_n_33;
wire MuxXY_n_34;
wire MuxXY_n_35;
wire MuxXY_n_36;
wire MuxXY_n_37;
wire MuxXY_n_38;
wire MuxXY_n_39;
wire MuxXY_n_4;
wire MuxXY_n_40;
wire MuxXY_n_41;
wire MuxXY_n_42;
wire MuxXY_n_43;
wire MuxXY_n_44;
wire MuxXY_n_45;
wire MuxXY_n_46;
wire MuxXY_n_47;
wire MuxXY_n_48;
wire MuxXY_n_49;
wire MuxXY_n_5;
wire MuxXY_n_50;
wire MuxXY_n_51;
wire MuxXY_n_52;
wire MuxXY_n_53;
wire MuxXY_n_54;
wire MuxXY_n_55;
wire MuxXY_n_56;
wire MuxXY_n_57;
wire MuxXY_n_58;
wire MuxXY_n_6;
wire MuxXY_n_7;
wire MuxXY_n_8;
wire MuxXY_n_9;
wire NRM_STAGE_DMP_exp_n_0;
wire NRM_STAGE_DMP_exp_n_1;
wire NRM_STAGE_DMP_exp_n_2;
wire NRM_STAGE_DMP_exp_n_3;
wire NRM_STAGE_DMP_exp_n_4;
wire NRM_STAGE_DMP_exp_n_5;
wire NRM_STAGE_DMP_exp_n_6;
wire NRM_STAGE_DMP_exp_n_7;
wire NRM_STAGE_FLAGS_n_2;
wire NRM_STAGE_FLAGS_n_3;
wire NRM_STAGE_FLAGS_n_4;
wire NRM_STAGE_Raw_mant_n_30;
wire OP_FLAG_INIT;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire \Q[12]_i_10_n_0 ;
wire \Q[12]_i_11_n_0 ;
wire \Q[12]_i_8_n_0 ;
wire \Q[12]_i_9_n_0 ;
wire \Q[16]_i_10_n_0 ;
wire \Q[16]_i_11_n_0 ;
wire \Q[16]_i_8_n_0 ;
wire \Q[16]_i_9_n_0 ;
wire \Q[20]_i_10_n_0 ;
wire \Q[20]_i_11_n_0 ;
wire \Q[20]_i_8_n_0 ;
wire \Q[20]_i_9_n_0 ;
wire \Q[24]_i_10_n_0 ;
wire \Q[24]_i_11_n_0 ;
wire \Q[24]_i_8_n_0 ;
wire \Q[24]_i_9_n_0 ;
wire \Q[4]_i_10_n_0 ;
wire \Q[4]_i_11_n_0 ;
wire \Q[4]_i_9_n_0 ;
wire \Q[8]_i_10_n_0 ;
wire \Q[8]_i_11_n_0 ;
wire \Q[8]_i_8__0_n_0 ;
wire \Q[8]_i_9__0_n_0 ;
wire [31:0]\Q_reg[31] ;
wire [31:0]\Q_reg[31]_0 ;
wire [25:0]Raw_mant_SGF;
wire SFT2FRMT_STAGE_FLAGS_n_1;
wire SFT2FRMT_STAGE_FLAGS_n_3;
wire SFT2FRMT_STAGE_VARS_n_0;
wire SFT2FRMT_STAGE_VARS_n_1;
wire SFT2FRMT_STAGE_VARS_n_10;
wire SFT2FRMT_STAGE_VARS_n_11;
wire SFT2FRMT_STAGE_VARS_n_12;
wire SFT2FRMT_STAGE_VARS_n_13;
wire SFT2FRMT_STAGE_VARS_n_14;
wire SFT2FRMT_STAGE_VARS_n_15;
wire SFT2FRMT_STAGE_VARS_n_16;
wire SFT2FRMT_STAGE_VARS_n_17;
wire SFT2FRMT_STAGE_VARS_n_18;
wire SFT2FRMT_STAGE_VARS_n_19;
wire SFT2FRMT_STAGE_VARS_n_2;
wire SFT2FRMT_STAGE_VARS_n_20;
wire SFT2FRMT_STAGE_VARS_n_21;
wire SFT2FRMT_STAGE_VARS_n_22;
wire SFT2FRMT_STAGE_VARS_n_23;
wire SFT2FRMT_STAGE_VARS_n_3;
wire SFT2FRMT_STAGE_VARS_n_4;
wire SFT2FRMT_STAGE_VARS_n_5;
wire SFT2FRMT_STAGE_VARS_n_6;
wire SFT2FRMT_STAGE_VARS_n_7;
wire SFT2FRMT_STAGE_VARS_n_8;
wire SFT2FRMT_STAGE_VARS_n_9;
wire SGF_STAGE_DMP_n_0;
wire SGF_STAGE_DMP_n_1;
wire SGF_STAGE_DMP_n_10;
wire SGF_STAGE_DMP_n_11;
wire SGF_STAGE_DMP_n_2;
wire SGF_STAGE_DMP_n_3;
wire SGF_STAGE_DMP_n_35;
wire SGF_STAGE_DMP_n_36;
wire SGF_STAGE_DMP_n_37;
wire SGF_STAGE_DMP_n_38;
wire SGF_STAGE_DMP_n_39;
wire SGF_STAGE_DMP_n_4;
wire SGF_STAGE_DMP_n_40;
wire SGF_STAGE_DMP_n_41;
wire SGF_STAGE_DMP_n_42;
wire SGF_STAGE_DMP_n_43;
wire SGF_STAGE_DMP_n_44;
wire SGF_STAGE_DMP_n_45;
wire SGF_STAGE_DMP_n_46;
wire SGF_STAGE_DMP_n_47;
wire SGF_STAGE_DMP_n_48;
wire SGF_STAGE_DMP_n_49;
wire SGF_STAGE_DMP_n_5;
wire SGF_STAGE_DMP_n_50;
wire SGF_STAGE_DMP_n_51;
wire SGF_STAGE_DMP_n_52;
wire SGF_STAGE_DMP_n_53;
wire SGF_STAGE_DMP_n_54;
wire SGF_STAGE_DMP_n_55;
wire SGF_STAGE_DMP_n_6;
wire SGF_STAGE_DMP_n_7;
wire SGF_STAGE_DMP_n_8;
wire SGF_STAGE_DMP_n_9;
wire SGF_STAGE_DmP_mant_n_0;
wire SGF_STAGE_DmP_mant_n_1;
wire SGF_STAGE_DmP_mant_n_10;
wire SGF_STAGE_DmP_mant_n_11;
wire SGF_STAGE_DmP_mant_n_12;
wire SGF_STAGE_DmP_mant_n_13;
wire SGF_STAGE_DmP_mant_n_14;
wire SGF_STAGE_DmP_mant_n_15;
wire SGF_STAGE_DmP_mant_n_16;
wire SGF_STAGE_DmP_mant_n_17;
wire SGF_STAGE_DmP_mant_n_18;
wire SGF_STAGE_DmP_mant_n_19;
wire SGF_STAGE_DmP_mant_n_2;
wire SGF_STAGE_DmP_mant_n_20;
wire SGF_STAGE_DmP_mant_n_21;
wire SGF_STAGE_DmP_mant_n_22;
wire SGF_STAGE_DmP_mant_n_24;
wire SGF_STAGE_DmP_mant_n_25;
wire SGF_STAGE_DmP_mant_n_26;
wire SGF_STAGE_DmP_mant_n_27;
wire SGF_STAGE_DmP_mant_n_28;
wire SGF_STAGE_DmP_mant_n_29;
wire SGF_STAGE_DmP_mant_n_3;
wire SGF_STAGE_DmP_mant_n_30;
wire SGF_STAGE_DmP_mant_n_31;
wire SGF_STAGE_DmP_mant_n_32;
wire SGF_STAGE_DmP_mant_n_33;
wire SGF_STAGE_DmP_mant_n_34;
wire SGF_STAGE_DmP_mant_n_35;
wire SGF_STAGE_DmP_mant_n_36;
wire SGF_STAGE_DmP_mant_n_37;
wire SGF_STAGE_DmP_mant_n_38;
wire SGF_STAGE_DmP_mant_n_39;
wire SGF_STAGE_DmP_mant_n_4;
wire SGF_STAGE_DmP_mant_n_40;
wire SGF_STAGE_DmP_mant_n_41;
wire SGF_STAGE_DmP_mant_n_42;
wire SGF_STAGE_DmP_mant_n_43;
wire SGF_STAGE_DmP_mant_n_44;
wire SGF_STAGE_DmP_mant_n_45;
wire SGF_STAGE_DmP_mant_n_46;
wire SGF_STAGE_DmP_mant_n_47;
wire SGF_STAGE_DmP_mant_n_48;
wire SGF_STAGE_DmP_mant_n_49;
wire SGF_STAGE_DmP_mant_n_5;
wire SGF_STAGE_DmP_mant_n_51;
wire SGF_STAGE_DmP_mant_n_6;
wire SGF_STAGE_DmP_mant_n_7;
wire SGF_STAGE_DmP_mant_n_8;
wire SGF_STAGE_DmP_mant_n_9;
wire SGF_STAGE_FLAGS_n_0;
wire SGF_STAGE_FLAGS_n_1;
wire SHT1_STAGE_DMP_n_0;
wire SHT1_STAGE_DMP_n_1;
wire SHT1_STAGE_DMP_n_10;
wire SHT1_STAGE_DMP_n_11;
wire SHT1_STAGE_DMP_n_12;
wire SHT1_STAGE_DMP_n_13;
wire SHT1_STAGE_DMP_n_14;
wire SHT1_STAGE_DMP_n_15;
wire SHT1_STAGE_DMP_n_16;
wire SHT1_STAGE_DMP_n_17;
wire SHT1_STAGE_DMP_n_18;
wire SHT1_STAGE_DMP_n_19;
wire SHT1_STAGE_DMP_n_2;
wire SHT1_STAGE_DMP_n_20;
wire SHT1_STAGE_DMP_n_21;
wire SHT1_STAGE_DMP_n_22;
wire SHT1_STAGE_DMP_n_23;
wire SHT1_STAGE_DMP_n_24;
wire SHT1_STAGE_DMP_n_25;
wire SHT1_STAGE_DMP_n_26;
wire SHT1_STAGE_DMP_n_27;
wire SHT1_STAGE_DMP_n_28;
wire SHT1_STAGE_DMP_n_29;
wire SHT1_STAGE_DMP_n_3;
wire SHT1_STAGE_DMP_n_30;
wire SHT1_STAGE_DMP_n_4;
wire SHT1_STAGE_DMP_n_5;
wire SHT1_STAGE_DMP_n_6;
wire SHT1_STAGE_DMP_n_7;
wire SHT1_STAGE_DMP_n_8;
wire SHT1_STAGE_DMP_n_9;
wire SHT1_STAGE_DmP_mant_n_0;
wire SHT1_STAGE_DmP_mant_n_1;
wire SHT1_STAGE_DmP_mant_n_10;
wire SHT1_STAGE_DmP_mant_n_11;
wire SHT1_STAGE_DmP_mant_n_12;
wire SHT1_STAGE_DmP_mant_n_13;
wire SHT1_STAGE_DmP_mant_n_14;
wire SHT1_STAGE_DmP_mant_n_15;
wire SHT1_STAGE_DmP_mant_n_16;
wire SHT1_STAGE_DmP_mant_n_17;
wire SHT1_STAGE_DmP_mant_n_18;
wire SHT1_STAGE_DmP_mant_n_19;
wire SHT1_STAGE_DmP_mant_n_2;
wire SHT1_STAGE_DmP_mant_n_20;
wire SHT1_STAGE_DmP_mant_n_21;
wire SHT1_STAGE_DmP_mant_n_22;
wire SHT1_STAGE_DmP_mant_n_3;
wire SHT1_STAGE_DmP_mant_n_4;
wire SHT1_STAGE_DmP_mant_n_5;
wire SHT1_STAGE_DmP_mant_n_6;
wire SHT1_STAGE_DmP_mant_n_7;
wire SHT1_STAGE_DmP_mant_n_8;
wire SHT1_STAGE_DmP_mant_n_9;
wire SHT1_STAGE_FLAGS_n_0;
wire SHT1_STAGE_FLAGS_n_1;
wire SHT1_STAGE_FLAGS_n_2;
wire SHT1_STAGE_sft_amount_n_0;
wire SHT2_SHIFT_DATA_n_0;
wire SHT2_SHIFT_DATA_n_1;
wire SHT2_SHIFT_DATA_n_2;
wire SHT2_STAGE_DMP_n_0;
wire SHT2_STAGE_DMP_n_1;
wire SHT2_STAGE_DMP_n_10;
wire SHT2_STAGE_DMP_n_11;
wire SHT2_STAGE_DMP_n_12;
wire SHT2_STAGE_DMP_n_13;
wire SHT2_STAGE_DMP_n_14;
wire SHT2_STAGE_DMP_n_15;
wire SHT2_STAGE_DMP_n_16;
wire SHT2_STAGE_DMP_n_17;
wire SHT2_STAGE_DMP_n_18;
wire SHT2_STAGE_DMP_n_19;
wire SHT2_STAGE_DMP_n_2;
wire SHT2_STAGE_DMP_n_20;
wire SHT2_STAGE_DMP_n_21;
wire SHT2_STAGE_DMP_n_22;
wire SHT2_STAGE_DMP_n_23;
wire SHT2_STAGE_DMP_n_24;
wire SHT2_STAGE_DMP_n_25;
wire SHT2_STAGE_DMP_n_26;
wire SHT2_STAGE_DMP_n_27;
wire SHT2_STAGE_DMP_n_28;
wire SHT2_STAGE_DMP_n_29;
wire SHT2_STAGE_DMP_n_3;
wire SHT2_STAGE_DMP_n_30;
wire SHT2_STAGE_DMP_n_4;
wire SHT2_STAGE_DMP_n_5;
wire SHT2_STAGE_DMP_n_6;
wire SHT2_STAGE_DMP_n_7;
wire SHT2_STAGE_DMP_n_8;
wire SHT2_STAGE_DMP_n_9;
wire SHT2_STAGE_FLAGS_n_0;
wire SHT2_STAGE_FLAGS_n_1;
wire SHT2_STAGE_FLAGS_n_2;
wire SHT2_STAGE_SHFTVARS1_n_0;
wire SHT2_STAGE_SHFTVARS1_n_1;
wire SHT2_STAGE_SHFTVARS1_n_10;
wire SHT2_STAGE_SHFTVARS1_n_11;
wire SHT2_STAGE_SHFTVARS1_n_12;
wire SHT2_STAGE_SHFTVARS1_n_13;
wire SHT2_STAGE_SHFTVARS1_n_2;
wire SHT2_STAGE_SHFTVARS1_n_3;
wire SHT2_STAGE_SHFTVARS1_n_4;
wire SHT2_STAGE_SHFTVARS1_n_5;
wire SHT2_STAGE_SHFTVARS1_n_6;
wire SHT2_STAGE_SHFTVARS1_n_7;
wire SHT2_STAGE_SHFTVARS1_n_8;
wire SHT2_STAGE_SHFTVARS1_n_9;
wire SHT2_STAGE_SHFTVARS2_n_0;
wire SHT2_STAGE_SHFTVARS2_n_1;
wire SHT2_STAGE_SHFTVARS2_n_2;
wire SHT2_STAGE_SHFTVARS2_n_3;
wire SHT2_STAGE_SHFTVARS2_n_4;
wire SHT2_STAGE_SHFTVARS2_n_5;
wire SHT2_STAGE_SHFTVARS2_n_7;
wire SIGN_FLAG_INIT;
wire [4:1]Shift_amount_EXP_EW;
wire [2:0]Shift_amount_SHT1_EWR;
wire [1:1]Shift_reg_FLAGS_7;
wire UNDRFLW_FLAG_FRMT;
wire _inferred__1_carry__0_n_0;
wire _inferred__1_carry__0_n_1;
wire _inferred__1_carry__0_n_2;
wire _inferred__1_carry__0_n_3;
wire _inferred__1_carry_n_0;
wire _inferred__1_carry_n_1;
wire _inferred__1_carry_n_2;
wire _inferred__1_carry_n_3;
wire bit_shift_SHT1;
wire enable_shift_reg;
wire eqXY;
wire [8:0]exp_rslt_NRM2_EW1;
wire [31:31]formatted_number_W;
wire gtXY;
wire inst_ShiftRegister_n_1;
wire inst_ShiftRegister_n_2;
wire inst_ShiftRegister_n_4;
wire inst_ShiftRegister_n_6;
wire inst_ShiftRegister_n_7;
wire intAS;
wire [31:31]intDX_EWSW;
wire [31:31]intDY_EWSW;
wire left_right_SHT1;
wire left_right_SHT2;
wire load0;
wire op_add_subt;
wire [0:0]out;
wire [2:0]overflow_flag;
wire [1:0]p_0_in;
wire p_2_in;
wire ready_add_subt;
wire [25:0]sftr_odat_SHT2_SWR;
wire [4:2]shft_value_mux_o_EWR;
wire [4:2]shift_value_SHT2_EWR;
wire [3:0]NLW__inferred__1_carry__1_CO_UNCONNECTED;
wire [3:1]NLW__inferred__1_carry__1_O_UNCONNECTED;
RegisterAdd__parameterized1 EXP_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.D({Shift_amount_EXP_EW[2],EXP_STAGE_DMP_n_1}),
.Q({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.\Q_reg[25]_0 ({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5}),
.\Q_reg[30]_0 ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized2 EXP_STAGE_DmP
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({Shift_amount_EXP_EW[4:3],Shift_amount_EXP_EW[1]}),
.Q({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5,EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.\Q_reg[27]_0 ({EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9}),
.\Q_reg[27]_1 ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized3 EXP_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({SIGN_FLAG_INIT,OP_FLAG_INIT,INPUT_STAGE_FLAGS_n_1}),
.Q({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.\Q_reg[6] (inst_ShiftRegister_n_1));
RegisterAdd FRMT_STAGE_DATAOUT
(.AR({AR[3],AR[1]}),
.CLK(CLK),
.D({formatted_number_W,SFT2FRMT_STAGE_VARS_n_15,SFT2FRMT_STAGE_VARS_n_16,SFT2FRMT_STAGE_VARS_n_17,SFT2FRMT_STAGE_VARS_n_18,SFT2FRMT_STAGE_VARS_n_19,SFT2FRMT_STAGE_VARS_n_20,SFT2FRMT_STAGE_VARS_n_21,SFT2FRMT_STAGE_VARS_n_22,SHT2_SHIFT_DATA_n_0,SHT2_STAGE_SHFTVARS1_n_0,SHT2_STAGE_SHFTVARS1_n_1,SHT2_STAGE_SHFTVARS1_n_2,SHT2_STAGE_SHFTVARS1_n_3,SHT2_STAGE_SHFTVARS1_n_4,SHT2_STAGE_SHFTVARS1_n_5,SHT2_STAGE_SHFTVARS1_n_6,SHT2_STAGE_SHFTVARS1_n_7,SHT2_STAGE_SHFTVARS2_n_0,SHT2_STAGE_SHFTVARS2_n_1,SHT2_SHIFT_DATA_n_1,SHT2_SHIFT_DATA_n_2,SHT2_STAGE_SHFTVARS2_n_2,SHT2_STAGE_SHFTVARS2_n_3,SHT2_STAGE_SHFTVARS2_n_4,SHT2_STAGE_SHFTVARS2_n_5,SHT2_STAGE_SHFTVARS1_n_8,SHT2_STAGE_SHFTVARS1_n_9,SHT2_STAGE_SHFTVARS1_n_10,SHT2_STAGE_SHFTVARS1_n_11,SHT2_STAGE_SHFTVARS1_n_12,SHT2_STAGE_SHFTVARS1_n_13}),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q(inst_ShiftRegister_n_6),
.\Q_reg[31]_0 (\Q_reg[31] ),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT),
.exp_rslt_NRM2_EW1(exp_rslt_NRM2_EW1));
RegisterAdd__parameterized21 FRMT_STAGE_FLAGS
(.AR(AR[2:1]),
.CLK(CLK),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q(inst_ShiftRegister_n_6),
.\Q_reg[0]_0 (SFT2FRMT_STAGE_FLAGS_n_3),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT),
.overflow_flag(overflow_flag));
RegisterAdd__parameterized0 INPUT_STAGE_FLAGS
(.CLK(CLK),
.CO(eqXY),
.D(INPUT_STAGE_FLAGS_n_1),
.E(E),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.Q(intDY_EWSW),
.\Q_reg[31] (intDX_EWSW),
.intAS(intAS),
.op_add_subt(op_add_subt));
RegisterAdd_1 INPUT_STAGE_OPERANDX
(.AR(AR[0]),
.CLK(CLK),
.D(OP_FLAG_INIT),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.E(E),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.Q({intDX_EWSW,INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[2]_0 ({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.\Q_reg[2]_1 ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[2]_2 ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[2]_3 ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.\Q_reg[2]_4 ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[2]_5 ({INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62,INPUT_STAGE_OPERANDX_n_63}),
.\Q_reg[2]_6 ({INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66,INPUT_STAGE_OPERANDX_n_67}),
.\Q_reg[2]_7 ({INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[2]_8 ({INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[31]_0 ({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.\Q_reg[31]_1 (\Q_reg[31]_0 ),
.S({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}),
.intAS(intAS));
RegisterAdd_2 INPUT_STAGE_OPERANDY
(.CLK(CLK),
.D(D),
.E(E),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.Q({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.\Q_reg[2]_0 (INPUT_STAGE_OPERANDY_n_33),
.\Q_reg[30]_0 (INPUT_STAGE_OPERANDX_n_5),
.S(INPUT_STAGE_OPERANDY_n_0));
Comparator Magnitude_Comparator
(.CO(gtXY),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.\Q_reg[14] ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[14]_0 ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[21] ({INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62,INPUT_STAGE_OPERANDX_n_63}),
.\Q_reg[22] ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[22]_0 ({INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66,INPUT_STAGE_OPERANDX_n_67}),
.\Q_reg[2] (eqXY),
.\Q_reg[30] ({INPUT_STAGE_OPERANDY_n_33,INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_0,INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[6] ({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.\Q_reg[9] ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.S({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}));
MultiplexTxT MuxXY
(.CO(gtXY),
.Q({INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[27] ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[30] ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}));
RegisterAdd__parameterized19 NRM_STAGE_DMP_exp
(.AR(AR[0]),
.CLK(CLK),
.Q({NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.\Q_reg[2]_0 (inst_ShiftRegister_n_4),
.\Q_reg[30] ({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11}));
RegisterAdd__parameterized20 NRM_STAGE_FLAGS
(.AR(AR[0]),
.CLK(CLK),
.D(shft_value_mux_o_EWR[2]),
.Q({ADD_OVRFLW_NRM,NRM_STAGE_FLAGS_n_2,NRM_STAGE_FLAGS_n_3}),
.\Q_reg[0]_0 (NRM_STAGE_Raw_mant_n_30),
.\Q_reg[1]_0 (SHT1_STAGE_sft_amount_n_0),
.\Q_reg[1]_1 ({SGF_STAGE_FLAGS_n_0,SGF_STAGE_FLAGS_n_1,p_0_in[0]}),
.\Q_reg[22] ({LZD_raw_out_EWR[2],LZD_raw_out_EWR[0]}),
.\Q_reg[25] (NRM_STAGE_FLAGS_n_4),
.\Q_reg[25]_0 (\Data_array_SWR[2]_1 [25]),
.\Q_reg[2]_0 ({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}),
.\Q_reg[2]_1 ({Shift_amount_SHT1_EWR[2],Shift_amount_SHT1_EWR[0]}));
RegisterAdd__parameterized18 NRM_STAGE_Raw_mant
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D(\Data_array_SWR[2]_1 [24:0]),
.Q({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}),
.\Q_reg[12]_0 (LZD_raw_out_EWR),
.\Q_reg[12]_1 (NRM_STAGE_Raw_mant_n_30),
.\Q_reg[1]_0 (bit_shift_SHT1),
.\Q_reg[1]_1 (SHT1_STAGE_sft_amount_n_0),
.\Q_reg[1]_2 (Raw_mant_SGF),
.\Q_reg[22]_0 ({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[2]_0 (NRM_STAGE_FLAGS_n_4),
.\Q_reg[2]_1 (ADD_OVRFLW_NRM));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1
(.I0(SGF_STAGE_DmP_mant_n_35),
.I1(SGF_STAGE_DMP_n_41),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[10]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1
(.I0(SGF_STAGE_DmP_mant_n_34),
.I1(SGF_STAGE_DMP_n_40),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[11]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1
(.I0(SGF_STAGE_DmP_mant_n_33),
.I1(SGF_STAGE_DMP_n_39),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[12]));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_10
(.I0(DMP_mant_SFG_SWR[10]),
.I1(SGF_STAGE_DmP_mant_n_14),
.O(\Q[12]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_11
(.I0(DMP_mant_SFG_SWR[9]),
.I1(SGF_STAGE_DmP_mant_n_15),
.O(\Q[12]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_8
(.I0(DMP_mant_SFG_SWR[12]),
.I1(SGF_STAGE_DmP_mant_n_12),
.O(\Q[12]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_9
(.I0(DMP_mant_SFG_SWR[11]),
.I1(SGF_STAGE_DmP_mant_n_13),
.O(\Q[12]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1
(.I0(SGF_STAGE_DmP_mant_n_40),
.I1(SGF_STAGE_DMP_n_46),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[13]));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1
(.I0(SGF_STAGE_DmP_mant_n_39),
.I1(SGF_STAGE_DMP_n_45),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[14]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1
(.I0(SGF_STAGE_DmP_mant_n_38),
.I1(SGF_STAGE_DMP_n_44),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[15]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1
(.I0(SGF_STAGE_DmP_mant_n_37),
.I1(SGF_STAGE_DMP_n_43),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[16]));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_10
(.I0(DMP_mant_SFG_SWR[14]),
.I1(SGF_STAGE_DmP_mant_n_10),
.O(\Q[16]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_11
(.I0(DMP_mant_SFG_SWR[13]),
.I1(SGF_STAGE_DmP_mant_n_11),
.O(\Q[16]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_8
(.I0(DMP_mant_SFG_SWR[16]),
.I1(SGF_STAGE_DmP_mant_n_8),
.O(\Q[16]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_9
(.I0(DMP_mant_SFG_SWR[15]),
.I1(SGF_STAGE_DmP_mant_n_9),
.O(\Q[16]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1
(.I0(SGF_STAGE_DmP_mant_n_44),
.I1(SGF_STAGE_DMP_n_50),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[17]));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1
(.I0(SGF_STAGE_DmP_mant_n_43),
.I1(SGF_STAGE_DMP_n_49),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[18]));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1
(.I0(SGF_STAGE_DmP_mant_n_42),
.I1(SGF_STAGE_DMP_n_48),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[19]));
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1
(.I0(SGF_STAGE_DmP_mant_n_28),
.I1(SGF_STAGE_DMP_n_3),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[1]));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1
(.I0(SGF_STAGE_DmP_mant_n_41),
.I1(SGF_STAGE_DMP_n_47),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[20]));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_10
(.I0(DMP_mant_SFG_SWR[18]),
.I1(SGF_STAGE_DmP_mant_n_6),
.O(\Q[20]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_11
(.I0(DMP_mant_SFG_SWR[17]),
.I1(SGF_STAGE_DmP_mant_n_7),
.O(\Q[20]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_8
(.I0(DMP_mant_SFG_SWR[20]),
.I1(SGF_STAGE_DmP_mant_n_4),
.O(\Q[20]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_9
(.I0(DMP_mant_SFG_SWR[19]),
.I1(SGF_STAGE_DmP_mant_n_5),
.O(\Q[20]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1
(.I0(SGF_STAGE_DmP_mant_n_48),
.I1(SGF_STAGE_DMP_n_55),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[21]));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1
(.I0(SGF_STAGE_DmP_mant_n_47),
.I1(SGF_STAGE_DMP_n_54),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[22]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1
(.I0(SGF_STAGE_DmP_mant_n_46),
.I1(SGF_STAGE_DMP_n_53),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[23]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1
(.I0(SGF_STAGE_DmP_mant_n_45),
.I1(SGF_STAGE_DMP_n_52),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[24]));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_10
(.I0(DMP_mant_SFG_SWR[22]),
.I1(SGF_STAGE_DmP_mant_n_2),
.O(\Q[24]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_11
(.I0(DMP_mant_SFG_SWR[21]),
.I1(SGF_STAGE_DmP_mant_n_3),
.O(\Q[24]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_8
(.I0(DMP_mant_SFG_SWR[24]),
.I1(SGF_STAGE_DmP_mant_n_0),
.O(\Q[24]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_9
(.I0(DMP_mant_SFG_SWR[23]),
.I1(SGF_STAGE_DmP_mant_n_1),
.O(\Q[24]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1
(.I0(SGF_STAGE_DmP_mant_n_49),
.I1(SGF_STAGE_DmP_mant_n_51),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[25]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1
(.I0(SGF_STAGE_DmP_mant_n_27),
.I1(SGF_STAGE_DMP_n_2),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[2]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1
(.I0(SGF_STAGE_DmP_mant_n_26),
.I1(SGF_STAGE_DMP_n_1),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[3]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1
(.I0(SGF_STAGE_DmP_mant_n_25),
.I1(SGF_STAGE_DMP_n_0),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[4]));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_10
(.I0(DMP_mant_SFG_SWR[3]),
.I1(SGF_STAGE_DmP_mant_n_21),
.O(\Q[4]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_11
(.I0(DMP_mant_SFG_SWR[2]),
.I1(SGF_STAGE_DmP_mant_n_22),
.O(\Q[4]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_9
(.I0(DMP_mant_SFG_SWR[4]),
.I1(SGF_STAGE_DmP_mant_n_20),
.O(\Q[4]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1
(.I0(SGF_STAGE_DmP_mant_n_32),
.I1(SGF_STAGE_DMP_n_38),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[5]));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1
(.I0(SGF_STAGE_DmP_mant_n_31),
.I1(SGF_STAGE_DMP_n_37),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[6]));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1
(.I0(SGF_STAGE_DmP_mant_n_30),
.I1(SGF_STAGE_DMP_n_36),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[7]));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1
(.I0(SGF_STAGE_DmP_mant_n_29),
.I1(SGF_STAGE_DMP_n_35),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[8]));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_10
(.I0(DMP_mant_SFG_SWR[6]),
.I1(SGF_STAGE_DmP_mant_n_18),
.O(\Q[8]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_11
(.I0(DMP_mant_SFG_SWR[5]),
.I1(SGF_STAGE_DmP_mant_n_19),
.O(\Q[8]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_8__0
(.I0(DMP_mant_SFG_SWR[8]),
.I1(SGF_STAGE_DmP_mant_n_16),
.O(\Q[8]_i_8__0_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_9__0
(.I0(DMP_mant_SFG_SWR[7]),
.I1(SGF_STAGE_DmP_mant_n_17),
.O(\Q[8]_i_9__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1
(.I0(SGF_STAGE_DmP_mant_n_36),
.I1(SGF_STAGE_DMP_n_42),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[9]));
RegisterAdd__parameterized22 Ready_reg
(.AR(AR[1]),
.CLK(CLK),
.Q(inst_ShiftRegister_n_6),
.ready_add_subt(ready_add_subt));
RegisterAdd__parameterized14 SFT2FRMT_STAGE_FLAGS
(.AR(AR[2]),
.CLK(CLK),
.D(formatted_number_W),
.DI(SFT2FRMT_STAGE_FLAGS_n_1),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({ADD_OVRFLW_NRM2,SFT2FRMT_STAGE_FLAGS_n_3}),
.\Q_reg[1]_0 (Shift_reg_FLAGS_7),
.\Q_reg[2]_0 ({ADD_OVRFLW_NRM,NRM_STAGE_FLAGS_n_2,NRM_STAGE_FLAGS_n_3}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized13 SFT2FRMT_STAGE_VARS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({SFT2FRMT_STAGE_VARS_n_15,SFT2FRMT_STAGE_VARS_n_16,SFT2FRMT_STAGE_VARS_n_17,SFT2FRMT_STAGE_VARS_n_18,SFT2FRMT_STAGE_VARS_n_19,SFT2FRMT_STAGE_VARS_n_20,SFT2FRMT_STAGE_VARS_n_21,SFT2FRMT_STAGE_VARS_n_22}),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q(ADD_OVRFLW_NRM2),
.\Q_reg[1]_0 (SFT2FRMT_STAGE_VARS_n_23),
.\Q_reg[1]_1 (Shift_reg_FLAGS_7),
.\Q_reg[1]_2 ({LZD_raw_out_EWR,NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.\Q_reg[30] ({SFT2FRMT_STAGE_VARS_n_4,SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7}),
.\Q_reg[30]_0 ({SFT2FRMT_STAGE_VARS_n_8,SFT2FRMT_STAGE_VARS_n_9,SFT2FRMT_STAGE_VARS_n_10,SFT2FRMT_STAGE_VARS_n_11,SFT2FRMT_STAGE_VARS_n_12,SFT2FRMT_STAGE_VARS_n_13,SFT2FRMT_STAGE_VARS_n_14}),
.S({SFT2FRMT_STAGE_VARS_n_0,SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT),
.exp_rslt_NRM2_EW1(exp_rslt_NRM2_EW1[7:0]));
RegisterAdd__parameterized15 SGF_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.CO(SGF_STAGE_DMP_n_51),
.E(load0),
.O({SGF_STAGE_DMP_n_0,SGF_STAGE_DMP_n_1,SGF_STAGE_DMP_n_2,SGF_STAGE_DMP_n_3}),
.Q({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11,DMP_mant_SFG_SWR}),
.\Q_reg[10]_0 ({\Q[12]_i_8_n_0 ,\Q[12]_i_9_n_0 ,\Q[12]_i_10_n_0 ,\Q[12]_i_11_n_0 }),
.\Q_reg[12]_0 ({SGF_STAGE_DMP_n_39,SGF_STAGE_DMP_n_40,SGF_STAGE_DMP_n_41,SGF_STAGE_DMP_n_42}),
.\Q_reg[14]_0 ({\Q[16]_i_8_n_0 ,\Q[16]_i_9_n_0 ,\Q[16]_i_10_n_0 ,\Q[16]_i_11_n_0 }),
.\Q_reg[16]_0 ({SGF_STAGE_DMP_n_43,SGF_STAGE_DMP_n_44,SGF_STAGE_DMP_n_45,SGF_STAGE_DMP_n_46}),
.\Q_reg[18]_0 ({\Q[20]_i_8_n_0 ,\Q[20]_i_9_n_0 ,\Q[20]_i_10_n_0 ,\Q[20]_i_11_n_0 }),
.\Q_reg[20]_0 ({SGF_STAGE_DMP_n_47,SGF_STAGE_DMP_n_48,SGF_STAGE_DMP_n_49,SGF_STAGE_DMP_n_50}),
.\Q_reg[22]_0 ({\Q[24]_i_8_n_0 ,\Q[24]_i_9_n_0 ,\Q[24]_i_10_n_0 ,\Q[24]_i_11_n_0 }),
.\Q_reg[24]_0 ({SGF_STAGE_DMP_n_52,SGF_STAGE_DMP_n_53,SGF_STAGE_DMP_n_54,SGF_STAGE_DMP_n_55}),
.\Q_reg[30]_0 ({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[6]_0 ({\Q[8]_i_8__0_n_0 ,\Q[8]_i_9__0_n_0 ,\Q[8]_i_10_n_0 ,\Q[8]_i_11_n_0 }),
.\Q_reg[8]_0 ({SGF_STAGE_DMP_n_35,SGF_STAGE_DMP_n_36,SGF_STAGE_DMP_n_37,SGF_STAGE_DMP_n_38}),
.S({\Q[4]_i_9_n_0 ,\Q[4]_i_10_n_0 ,\Q[4]_i_11_n_0 ,SGF_STAGE_DmP_mant_n_24}));
RegisterAdd__parameterized16 SGF_STAGE_DmP_mant
(.AR(AR),
.CLK(CLK),
.CO(p_2_in),
.D(sftr_odat_SHT2_SWR),
.E(load0),
.O({SGF_STAGE_DmP_mant_n_25,SGF_STAGE_DmP_mant_n_26,SGF_STAGE_DmP_mant_n_27,SGF_STAGE_DmP_mant_n_28}),
.Q({SGF_STAGE_DmP_mant_n_0,SGF_STAGE_DmP_mant_n_1,SGF_STAGE_DmP_mant_n_2,SGF_STAGE_DmP_mant_n_3,SGF_STAGE_DmP_mant_n_4,SGF_STAGE_DmP_mant_n_5,SGF_STAGE_DmP_mant_n_6,SGF_STAGE_DmP_mant_n_7,SGF_STAGE_DmP_mant_n_8,SGF_STAGE_DmP_mant_n_9,SGF_STAGE_DmP_mant_n_10,SGF_STAGE_DmP_mant_n_11,SGF_STAGE_DmP_mant_n_12,SGF_STAGE_DmP_mant_n_13,SGF_STAGE_DmP_mant_n_14,SGF_STAGE_DmP_mant_n_15,SGF_STAGE_DmP_mant_n_16,SGF_STAGE_DmP_mant_n_17,SGF_STAGE_DmP_mant_n_18,SGF_STAGE_DmP_mant_n_19,SGF_STAGE_DmP_mant_n_20,SGF_STAGE_DmP_mant_n_21,SGF_STAGE_DmP_mant_n_22,Raw_mant_SGF[0]}),
.\Q_reg[12]_0 ({SGF_STAGE_DmP_mant_n_33,SGF_STAGE_DmP_mant_n_34,SGF_STAGE_DmP_mant_n_35,SGF_STAGE_DmP_mant_n_36}),
.\Q_reg[16]_0 ({SGF_STAGE_DmP_mant_n_37,SGF_STAGE_DmP_mant_n_38,SGF_STAGE_DmP_mant_n_39,SGF_STAGE_DmP_mant_n_40}),
.\Q_reg[20]_0 ({SGF_STAGE_DmP_mant_n_41,SGF_STAGE_DmP_mant_n_42,SGF_STAGE_DmP_mant_n_43,SGF_STAGE_DmP_mant_n_44}),
.\Q_reg[22]_0 (DMP_mant_SFG_SWR),
.\Q_reg[22]_1 (SGF_STAGE_DMP_n_51),
.\Q_reg[24]_0 ({SGF_STAGE_DmP_mant_n_45,SGF_STAGE_DmP_mant_n_46,SGF_STAGE_DmP_mant_n_47,SGF_STAGE_DmP_mant_n_48}),
.\Q_reg[25]_0 (SGF_STAGE_DmP_mant_n_49),
.\Q_reg[25]_1 (SGF_STAGE_DmP_mant_n_51),
.\Q_reg[8]_0 ({SGF_STAGE_DmP_mant_n_29,SGF_STAGE_DmP_mant_n_30,SGF_STAGE_DmP_mant_n_31,SGF_STAGE_DmP_mant_n_32}),
.S(SGF_STAGE_DmP_mant_n_24));
RegisterAdd__parameterized17 SGF_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.CO(p_2_in),
.E(load0),
.Q(p_0_in[1]),
.\Q_reg[2]_0 ({SGF_STAGE_FLAGS_n_0,SGF_STAGE_FLAGS_n_1,p_0_in[0]}),
.\Q_reg[2]_1 ({SHT2_STAGE_FLAGS_n_0,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}));
RegisterAdd__parameterized4 SHT1_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.D({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.Q({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized5 SHT1_STAGE_DmP_mant
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.Q({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized7 SHT1_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.Q({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,SHT1_STAGE_FLAGS_n_2}),
.\Q_reg[5] (inst_ShiftRegister_n_2));
RegisterAdd__parameterized6 SHT1_STAGE_sft_amount
(.AR(AR[2]),
.CLK(CLK),
.D(shft_value_mux_o_EWR[4:3]),
.Q({Shift_amount_SHT1_EWR[2],Shift_amount_SHT1_EWR[0]}),
.\Q_reg[1]_0 ({LZD_raw_out_EWR[4:3],LZD_raw_out_EWR[1]}),
.\Q_reg[23] (SHT1_STAGE_sft_amount_n_0),
.\Q_reg[26] ({Shift_amount_EXP_EW,EXP_STAGE_DMP_n_1}),
.\Q_reg[2]_0 (ADD_OVRFLW_NRM),
.\Q_reg[5] ({inst_ShiftRegister_n_2,Shift_reg_FLAGS_7}));
RegisterAdd__parameterized9 SHT2_SHIFT_DATA
(.CLK(CLK),
.D({SHT2_SHIFT_DATA_n_0,SHT2_SHIFT_DATA_n_1,SHT2_SHIFT_DATA_n_2}),
.\Data_array_SWR[4]_4 (\Data_array_SWR[4]_4 ),
.\Data_array_SWR[6]_3 (\Data_array_SWR[6]_3 [1]),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_7}),
.\Q_reg[13]_0 (\Data_array_SWR[3]_0 ),
.\Q_reg[25]_0 ({sftr_odat_SHT2_SWR[25:24],sftr_odat_SHT2_SWR[13:12],sftr_odat_SHT2_SWR[0]}),
.\Q_reg[2]_0 (\Data_array_SWR[2]_1 ),
.\Q_reg[4]_0 (\Data_array_SWR[6]_3 [25:24]),
.\Q_reg[4]_1 (shift_value_SHT2_EWR),
.\Q_reg[8]_0 ({\Data_array_SWR[5]_2 [17:16],\Data_array_SWR[5]_2 [11:2]}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized8 SHT2_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.D({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.Q({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[4]_0 (Q));
RegisterAdd__parameterized12 SHT2_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,SHT1_STAGE_FLAGS_n_2}),
.Q({SHT2_STAGE_FLAGS_n_0,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}),
.\Q_reg[4] (Q));
RegisterAdd__parameterized10 SHT2_STAGE_SHFTVARS1
(.CLK(CLK),
.D({SHT2_STAGE_SHFTVARS1_n_0,SHT2_STAGE_SHFTVARS1_n_1,SHT2_STAGE_SHFTVARS1_n_2,SHT2_STAGE_SHFTVARS1_n_3,SHT2_STAGE_SHFTVARS1_n_4,SHT2_STAGE_SHFTVARS1_n_5,SHT2_STAGE_SHFTVARS1_n_6,SHT2_STAGE_SHFTVARS1_n_7,SHT2_STAGE_SHFTVARS1_n_8,SHT2_STAGE_SHFTVARS1_n_9,SHT2_STAGE_SHFTVARS1_n_10,SHT2_STAGE_SHFTVARS1_n_11,SHT2_STAGE_SHFTVARS1_n_12,SHT2_STAGE_SHFTVARS1_n_13}),
.\Data_array_SWR[4]_4 (\Data_array_SWR[4]_4 ),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_7}),
.\Q_reg[0] ({\Data_array_SWR[5]_2 [17:16],\Data_array_SWR[5]_2 [9:2]}),
.\Q_reg[16] (shift_value_SHT2_EWR),
.\Q_reg[23] ({sftr_odat_SHT2_SWR[23:16],sftr_odat_SHT2_SWR[7:1]}),
.\Q_reg[25] ({\Data_array_SWR[6]_3 [25:24],\Data_array_SWR[6]_3 [15:14],\Data_array_SWR[6]_3 [9:8]}),
.\Q_reg[25]_0 (\Data_array_SWR[3]_0 ),
.\Q_reg[4]_0 (\Data_array_SWR[6]_3 [1]),
.\Q_reg[4]_1 (shft_value_mux_o_EWR),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized11 SHT2_STAGE_SHFTVARS2
(.CLK(CLK),
.D({SHT2_STAGE_SHFTVARS2_n_0,SHT2_STAGE_SHFTVARS2_n_1,SHT2_STAGE_SHFTVARS2_n_2,SHT2_STAGE_SHFTVARS2_n_3,SHT2_STAGE_SHFTVARS2_n_4,SHT2_STAGE_SHFTVARS2_n_5}),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_7}),
.\Q_reg[0]_0 ({\Data_array_SWR[5]_2 [17:16],\Data_array_SWR[5]_2 [11:10]}),
.\Q_reg[15] ({sftr_odat_SHT2_SWR[15:14],sftr_odat_SHT2_SWR[11:8]}),
.\Q_reg[1]_0 ({left_right_SHT1,bit_shift_SHT1}),
.\Q_reg[4] ({\Data_array_SWR[6]_3 [15:14],\Data_array_SWR[6]_3 [9:8]}),
.\Q_reg[4]_0 (shift_value_SHT2_EWR[4]),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _inferred__1_carry
(.CI(1'b0),
.CO({_inferred__1_carry_n_0,_inferred__1_carry_n_1,_inferred__1_carry_n_2,_inferred__1_carry_n_3}),
.CYINIT(SFT2FRMT_STAGE_VARS_n_14),
.DI({SFT2FRMT_STAGE_VARS_n_11,SFT2FRMT_STAGE_VARS_n_12,SFT2FRMT_STAGE_VARS_n_13,SFT2FRMT_STAGE_FLAGS_n_1}),
.O(exp_rslt_NRM2_EW1[3:0]),
.S({SFT2FRMT_STAGE_VARS_n_0,SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _inferred__1_carry__0
(.CI(_inferred__1_carry_n_0),
.CO({_inferred__1_carry__0_n_0,_inferred__1_carry__0_n_1,_inferred__1_carry__0_n_2,_inferred__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({SFT2FRMT_STAGE_VARS_n_8,SFT2FRMT_STAGE_VARS_n_9,ADD_OVRFLW_NRM2,SFT2FRMT_STAGE_VARS_n_10}),
.O(exp_rslt_NRM2_EW1[7:4]),
.S({SFT2FRMT_STAGE_VARS_n_4,SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _inferred__1_carry__1
(.CI(_inferred__1_carry__0_n_0),
.CO(NLW__inferred__1_carry__1_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW__inferred__1_carry__1_O_UNCONNECTED[3:1],exp_rslt_NRM2_EW1[8]}),
.S({1'b0,1'b0,1'b0,SFT2FRMT_STAGE_VARS_n_23}));
FSM_INPUT_ENABLE inst_FSM_INPUT_ENABLE
(.CLK(CLK),
.D(FSM_enable_input_internal),
.E(enable_shift_reg),
.\FSM_sequential_state_reg_reg[1]_0 (\FSM_sequential_state_reg_reg[1] ),
.\FSM_sequential_state_reg_reg[2]_0 (\FSM_sequential_state_reg_reg[2] ),
.out(out));
ShiftRegister inst_ShiftRegister
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D(FSM_enable_input_internal),
.E(load0),
.\FSM_sequential_state_reg_reg[0] (enable_shift_reg),
.Q({inst_ShiftRegister_n_1,inst_ShiftRegister_n_2,Q,inst_ShiftRegister_n_4,Shift_reg_FLAGS_7,inst_ShiftRegister_n_6}),
.\Q_reg[1]_0 (inst_ShiftRegister_n_7),
.\Q_reg[1]_1 ({left_right_SHT1,bit_shift_SHT1}),
.\Q_reg[2]_0 (ADD_OVRFLW_NRM));
sgn_result result_sign_bit
(.CO(gtXY),
.D(SIGN_FLAG_INIT),
.Q(intDY_EWSW),
.\Q_reg[30] (eqXY),
.\Q_reg[31] (intDX_EWSW),
.intAS(intAS));
endmodule |
module FSM_INPUT_ENABLE
(out,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1]_0 ,
\FSM_sequential_state_reg_reg[2]_0 );
output [0:0]out;
output [0:0]E;
output [0:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1]_0 ;
input [1:0]\FSM_sequential_state_reg_reg[2]_0 ;
wire CLK;
wire [0:0]D;
wire [0:0]E;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire [0:0]\FSM_sequential_state_reg_reg[1]_0 ;
wire [1:0]\FSM_sequential_state_reg_reg[2]_0 ;
(* RTL_KEEP = "yes" *) wire [0:0]out;
(* RTL_KEEP = "yes" *) wire [1:0]state_reg;
LUT5 #(
.INIT(32'h14145514))
\FSM_sequential_state_reg[0]_i_1
(.I0(state_reg[0]),
.I1(state_reg[1]),
.I2(out),
.I3(\FSM_sequential_state_reg_reg[2]_0 [1]),
.I4(\FSM_sequential_state_reg_reg[2]_0 [0]),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h26))
\FSM_sequential_state_reg[1]_i_1
(.I0(state_reg[0]),
.I1(state_reg[1]),
.I2(out),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'h38))
\FSM_sequential_state_reg[2]_i_1
(.I0(state_reg[0]),
.I1(state_reg[1]),
.I2(out),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[1]_0 ),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(state_reg[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[1]_0 ),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(state_reg[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[1]_0 ),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(out));
LUT1 #(
.INIT(2'h1))
\Q[6]_i_1__0
(.I0(out),
.O(D));
LUT3 #(
.INIT(8'h7E))
__0
(.I0(state_reg[0]),
.I1(out),
.I2(state_reg[1]),
.O(E));
endmodule |
module MultiplexTxT
(\Q_reg[30] ,
\Q_reg[27] ,
Q,
\Q_reg[30]_0 ,
CO);
output [30:0]\Q_reg[30] ;
output [27:0]\Q_reg[27] ;
input [30:0]Q;
input [30:0]\Q_reg[30]_0 ;
input [0:0]CO;
wire [0:0]CO;
wire [30:0]Q;
wire [27:0]\Q_reg[27] ;
wire [30:0]\Q_reg[30] ;
wire [30:0]\Q_reg[30]_0 ;
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1
(.I0(Q[0]),
.I1(\Q_reg[30]_0 [0]),
.I2(CO),
.O(\Q_reg[30] [0]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1__0
(.I0(\Q_reg[30]_0 [0]),
.I1(Q[0]),
.I2(CO),
.O(\Q_reg[27] [0]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1
(.I0(Q[10]),
.I1(\Q_reg[30]_0 [10]),
.I2(CO),
.O(\Q_reg[30] [10]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1__0
(.I0(\Q_reg[30]_0 [10]),
.I1(Q[10]),
.I2(CO),
.O(\Q_reg[27] [10]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1
(.I0(Q[11]),
.I1(\Q_reg[30]_0 [11]),
.I2(CO),
.O(\Q_reg[30] [11]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1__0
(.I0(\Q_reg[30]_0 [11]),
.I1(Q[11]),
.I2(CO),
.O(\Q_reg[27] [11]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1
(.I0(Q[12]),
.I1(\Q_reg[30]_0 [12]),
.I2(CO),
.O(\Q_reg[30] [12]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1__0
(.I0(\Q_reg[30]_0 [12]),
.I1(Q[12]),
.I2(CO),
.O(\Q_reg[27] [12]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1
(.I0(Q[13]),
.I1(\Q_reg[30]_0 [13]),
.I2(CO),
.O(\Q_reg[30] [13]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1__0
(.I0(\Q_reg[30]_0 [13]),
.I1(Q[13]),
.I2(CO),
.O(\Q_reg[27] [13]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1
(.I0(Q[14]),
.I1(\Q_reg[30]_0 [14]),
.I2(CO),
.O(\Q_reg[30] [14]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1__0
(.I0(\Q_reg[30]_0 [14]),
.I1(Q[14]),
.I2(CO),
.O(\Q_reg[27] [14]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1
(.I0(Q[15]),
.I1(\Q_reg[30]_0 [15]),
.I2(CO),
.O(\Q_reg[30] [15]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1__0
(.I0(\Q_reg[30]_0 [15]),
.I1(Q[15]),
.I2(CO),
.O(\Q_reg[27] [15]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1
(.I0(Q[16]),
.I1(\Q_reg[30]_0 [16]),
.I2(CO),
.O(\Q_reg[30] [16]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1__0
(.I0(\Q_reg[30]_0 [16]),
.I1(Q[16]),
.I2(CO),
.O(\Q_reg[27] [16]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1
(.I0(Q[17]),
.I1(\Q_reg[30]_0 [17]),
.I2(CO),
.O(\Q_reg[30] [17]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1__0
(.I0(\Q_reg[30]_0 [17]),
.I1(Q[17]),
.I2(CO),
.O(\Q_reg[27] [17]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1
(.I0(Q[18]),
.I1(\Q_reg[30]_0 [18]),
.I2(CO),
.O(\Q_reg[30] [18]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1__0
(.I0(\Q_reg[30]_0 [18]),
.I1(Q[18]),
.I2(CO),
.O(\Q_reg[27] [18]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1
(.I0(Q[19]),
.I1(\Q_reg[30]_0 [19]),
.I2(CO),
.O(\Q_reg[30] [19]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1__0
(.I0(\Q_reg[30]_0 [19]),
.I1(Q[19]),
.I2(CO),
.O(\Q_reg[27] [19]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1
(.I0(Q[1]),
.I1(\Q_reg[30]_0 [1]),
.I2(CO),
.O(\Q_reg[30] [1]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1__0
(.I0(\Q_reg[30]_0 [1]),
.I1(Q[1]),
.I2(CO),
.O(\Q_reg[27] [1]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1
(.I0(Q[20]),
.I1(\Q_reg[30]_0 [20]),
.I2(CO),
.O(\Q_reg[30] [20]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1__0
(.I0(\Q_reg[30]_0 [20]),
.I1(Q[20]),
.I2(CO),
.O(\Q_reg[27] [20]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1
(.I0(Q[21]),
.I1(\Q_reg[30]_0 [21]),
.I2(CO),
.O(\Q_reg[30] [21]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1__0
(.I0(\Q_reg[30]_0 [21]),
.I1(Q[21]),
.I2(CO),
.O(\Q_reg[27] [21]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1
(.I0(Q[22]),
.I1(\Q_reg[30]_0 [22]),
.I2(CO),
.O(\Q_reg[30] [22]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1__0
(.I0(\Q_reg[30]_0 [22]),
.I1(Q[22]),
.I2(CO),
.O(\Q_reg[27] [22]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1
(.I0(Q[23]),
.I1(\Q_reg[30]_0 [23]),
.I2(CO),
.O(\Q_reg[30] [23]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1__0
(.I0(\Q_reg[30]_0 [23]),
.I1(Q[23]),
.I2(CO),
.O(\Q_reg[27] [23]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1
(.I0(Q[24]),
.I1(\Q_reg[30]_0 [24]),
.I2(CO),
.O(\Q_reg[30] [24]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1__0
(.I0(\Q_reg[30]_0 [24]),
.I1(Q[24]),
.I2(CO),
.O(\Q_reg[27] [24]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1
(.I0(Q[25]),
.I1(\Q_reg[30]_0 [25]),
.I2(CO),
.O(\Q_reg[30] [25]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1__0
(.I0(\Q_reg[30]_0 [25]),
.I1(Q[25]),
.I2(CO),
.O(\Q_reg[27] [25]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1
(.I0(Q[26]),
.I1(\Q_reg[30]_0 [26]),
.I2(CO),
.O(\Q_reg[30] [26]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1__0
(.I0(\Q_reg[30]_0 [26]),
.I1(Q[26]),
.I2(CO),
.O(\Q_reg[27] [26]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1
(.I0(Q[27]),
.I1(\Q_reg[30]_0 [27]),
.I2(CO),
.O(\Q_reg[30] [27]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1__0
(.I0(\Q_reg[30]_0 [27]),
.I1(Q[27]),
.I2(CO),
.O(\Q_reg[27] [27]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hAC))
\Q[28]_i_1
(.I0(Q[28]),
.I1(\Q_reg[30]_0 [28]),
.I2(CO),
.O(\Q_reg[30] [28]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hAC))
\Q[29]_i_1
(.I0(Q[29]),
.I1(\Q_reg[30]_0 [29]),
.I2(CO),
.O(\Q_reg[30] [29]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1
(.I0(Q[2]),
.I1(\Q_reg[30]_0 [2]),
.I2(CO),
.O(\Q_reg[30] [2]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1__0
(.I0(\Q_reg[30]_0 [2]),
.I1(Q[2]),
.I2(CO),
.O(\Q_reg[27] [2]));
LUT3 #(
.INIT(8'hAC))
\Q[30]_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 [30]),
.I2(CO),
.O(\Q_reg[30] [30]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1
(.I0(Q[3]),
.I1(\Q_reg[30]_0 [3]),
.I2(CO),
.O(\Q_reg[30] [3]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1__0
(.I0(\Q_reg[30]_0 [3]),
.I1(Q[3]),
.I2(CO),
.O(\Q_reg[27] [3]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1
(.I0(Q[4]),
.I1(\Q_reg[30]_0 [4]),
.I2(CO),
.O(\Q_reg[30] [4]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1__0
(.I0(\Q_reg[30]_0 [4]),
.I1(Q[4]),
.I2(CO),
.O(\Q_reg[27] [4]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1
(.I0(Q[5]),
.I1(\Q_reg[30]_0 [5]),
.I2(CO),
.O(\Q_reg[30] [5]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1__0
(.I0(\Q_reg[30]_0 [5]),
.I1(Q[5]),
.I2(CO),
.O(\Q_reg[27] [5]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1
(.I0(Q[6]),
.I1(\Q_reg[30]_0 [6]),
.I2(CO),
.O(\Q_reg[30] [6]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1__0
(.I0(\Q_reg[30]_0 [6]),
.I1(Q[6]),
.I2(CO),
.O(\Q_reg[27] [6]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1
(.I0(Q[7]),
.I1(\Q_reg[30]_0 [7]),
.I2(CO),
.O(\Q_reg[30] [7]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1__0
(.I0(\Q_reg[30]_0 [7]),
.I1(Q[7]),
.I2(CO),
.O(\Q_reg[27] [7]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1
(.I0(Q[8]),
.I1(\Q_reg[30]_0 [8]),
.I2(CO),
.O(\Q_reg[30] [8]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1__0
(.I0(\Q_reg[30]_0 [8]),
.I1(Q[8]),
.I2(CO),
.O(\Q_reg[27] [8]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1
(.I0(Q[9]),
.I1(\Q_reg[30]_0 [9]),
.I2(CO),
.O(\Q_reg[30] [9]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1__0
(.I0(\Q_reg[30]_0 [9]),
.I1(Q[9]),
.I2(CO),
.O(\Q_reg[27] [9]));
endmodule |
module RegisterAdd
(UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[31]_0 ,
exp_rslt_NRM2_EW1,
Q,
D,
CLK,
AR);
output UNDRFLW_FLAG_FRMT;
output OVRFLW_FLAG_FRMT;
output [31:0]\Q_reg[31]_0 ;
input [8:0]exp_rslt_NRM2_EW1;
input [0:0]Q;
input [31:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [31:0]D;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire \Q[1]_i_2__1_n_0 ;
wire \Q[2]_i_2__0_n_0 ;
wire [31:0]\Q_reg[31]_0 ;
wire UNDRFLW_FLAG_FRMT;
wire [8:0]exp_rslt_NRM2_EW1;
LUT5 #(
.INIT(32'h00000001))
\Q[1]_i_1__9
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[6]),
.I2(exp_rslt_NRM2_EW1[8]),
.I3(exp_rslt_NRM2_EW1[7]),
.I4(\Q[1]_i_2__1_n_0 ),
.O(UNDRFLW_FLAG_FRMT));
LUT5 #(
.INIT(32'hFFFFFFFE))
\Q[1]_i_2__1
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(exp_rslt_NRM2_EW1[0]),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[4]),
.I4(exp_rslt_NRM2_EW1[3]),
.O(\Q[1]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hEAAAAAAAAAAAAAAA))
\Q[2]_i_1__7
(.I0(exp_rslt_NRM2_EW1[8]),
.I1(\Q[2]_i_2__0_n_0 ),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[0]),
.I4(exp_rslt_NRM2_EW1[3]),
.I5(exp_rslt_NRM2_EW1[2]),
.O(OVRFLW_FLAG_FRMT));
LUT4 #(
.INIT(16'h8000))
\Q[2]_i_2__0
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[4]),
.I2(exp_rslt_NRM2_EW1[6]),
.I3(exp_rslt_NRM2_EW1[7]),
.O(\Q[2]_i_2__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[0]),
.Q(\Q_reg[31]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[10]),
.Q(\Q_reg[31]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[11]),
.Q(\Q_reg[31]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[12]),
.Q(\Q_reg[31]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[13]),
.Q(\Q_reg[31]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[14]),
.Q(\Q_reg[31]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[15]),
.Q(\Q_reg[31]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[16]),
.Q(\Q_reg[31]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[17]),
.Q(\Q_reg[31]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[18]),
.Q(\Q_reg[31]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[19]),
.Q(\Q_reg[31]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[1]),
.Q(\Q_reg[31]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[20]),
.Q(\Q_reg[31]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[21]),
.Q(\Q_reg[31]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[22]),
.Q(\Q_reg[31]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[23]),
.Q(\Q_reg[31]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[24]),
.Q(\Q_reg[31]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[25]),
.Q(\Q_reg[31]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[26]),
.Q(\Q_reg[31]_0 [26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[27]),
.Q(\Q_reg[31]_0 [27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[28]),
.Q(\Q_reg[31]_0 [28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[29]),
.Q(\Q_reg[31]_0 [29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[2]),
.Q(\Q_reg[31]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[30]),
.Q(\Q_reg[31]_0 [30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[31]),
.Q(\Q_reg[31]_0 [31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[3]),
.Q(\Q_reg[31]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[4]),
.Q(\Q_reg[31]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[5]),
.Q(\Q_reg[31]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[6]),
.Q(\Q_reg[31]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[7]),
.Q(\Q_reg[31]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[8]),
.Q(\Q_reg[31]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[9]),
.Q(\Q_reg[31]_0 [9]));
endmodule |
module RegisterAdd_1
(DI,
Q,
\Q_reg[2]_0 ,
S,
\Q_reg[2]_1 ,
\Q_reg[2]_2 ,
\Q_reg[2]_3 ,
\Q_reg[2]_4 ,
\Q_reg[2]_5 ,
\Q_reg[2]_6 ,
\Q_reg[2]_7 ,
\Q_reg[2]_8 ,
D,
\Q_reg[31]_0 ,
intAS,
E,
\Q_reg[31]_1 ,
CLK,
\FSM_sequential_state_reg_reg[1] ,
AR);
output [3:0]DI;
output [31:0]Q;
output [3:0]\Q_reg[2]_0 ;
output [3:0]S;
output [3:0]\Q_reg[2]_1 ;
output [3:0]\Q_reg[2]_2 ;
output [3:0]\Q_reg[2]_3 ;
output [3:0]\Q_reg[2]_4 ;
output [3:0]\Q_reg[2]_5 ;
output [3:0]\Q_reg[2]_6 ;
output [2:0]\Q_reg[2]_7 ;
output [1:0]\Q_reg[2]_8 ;
output [0:0]D;
input [31:0]\Q_reg[31]_0 ;
input intAS;
input [0:0]E;
input [31:0]\Q_reg[31]_1 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [3:0]DI;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [3:0]\Q_reg[2]_0 ;
wire [3:0]\Q_reg[2]_1 ;
wire [3:0]\Q_reg[2]_2 ;
wire [3:0]\Q_reg[2]_3 ;
wire [3:0]\Q_reg[2]_4 ;
wire [3:0]\Q_reg[2]_5 ;
wire [3:0]\Q_reg[2]_6 ;
wire [2:0]\Q_reg[2]_7 ;
wire [1:0]\Q_reg[2]_8 ;
wire [31:0]\Q_reg[31]_0 ;
wire [31:0]\Q_reg[31]_1 ;
wire [3:0]S;
wire intAS;
LUT3 #(
.INIT(8'h96))
\Q[1]_i_1__8
(.I0(Q[31]),
.I1(\Q_reg[31]_0 [31]),
.I2(intAS),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [9]),
.Q(Q[9]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_1
(.I0(Q[21]),
.I1(\Q_reg[31]_0 [21]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.I4(\Q_reg[31]_0 [22]),
.I5(Q[22]),
.O(\Q_reg[2]_5 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_2
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [20]),
.I3(Q[20]),
.I4(\Q_reg[31]_0 [19]),
.I5(Q[19]),
.O(\Q_reg[2]_5 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_3
(.I0(Q[15]),
.I1(\Q_reg[31]_0 [15]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.I4(\Q_reg[31]_0 [16]),
.I5(Q[16]),
.O(\Q_reg[2]_5 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_4
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [14]),
.I3(Q[14]),
.I4(\Q_reg[31]_0 [13]),
.I5(Q[13]),
.O(\Q_reg[2]_5 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_2
(.I0(Q[27]),
.I1(\Q_reg[31]_0 [27]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.I4(\Q_reg[31]_0 [28]),
.I5(Q[28]),
.O(\Q_reg[2]_8 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_3
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [26]),
.I3(Q[26]),
.I4(\Q_reg[31]_0 [25]),
.I5(Q[25]),
.O(\Q_reg[2]_8 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_1
(.I0(Q[9]),
.I1(\Q_reg[31]_0 [9]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.I4(\Q_reg[31]_0 [10]),
.I5(Q[10]),
.O(\Q_reg[2]_3 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_2
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [8]),
.I3(Q[8]),
.I4(\Q_reg[31]_0 [7]),
.I5(Q[7]),
.O(\Q_reg[2]_3 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_3
(.I0(Q[3]),
.I1(\Q_reg[31]_0 [3]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.I4(\Q_reg[31]_0 [4]),
.I5(Q[4]),
.O(\Q_reg[2]_3 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [2]),
.I3(Q[2]),
.I4(\Q_reg[31]_0 [1]),
.I5(Q[1]),
.O(\Q_reg[2]_3 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_1
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(\Q_reg[31]_0 [15]),
.I3(Q[15]),
.O(\Q_reg[2]_1 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_2
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [13]),
.I3(Q[13]),
.O(\Q_reg[2]_1 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_3
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.O(\Q_reg[2]_1 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_4
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(\Q_reg[31]_0 [9]),
.I3(Q[9]),
.O(\Q_reg[2]_1 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_5
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(Q[15]),
.I3(\Q_reg[31]_0 [15]),
.O(\Q_reg[2]_2 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_6
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(Q[13]),
.I3(\Q_reg[31]_0 [13]),
.O(\Q_reg[2]_2 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_7
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(Q[11]),
.I3(\Q_reg[31]_0 [11]),
.O(\Q_reg[2]_2 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_8
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(Q[9]),
.I3(\Q_reg[31]_0 [9]),
.O(\Q_reg[2]_2 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_1
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.O(\Q_reg[2]_4 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_2
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(\Q_reg[31]_0 [21]),
.I3(Q[21]),
.O(\Q_reg[2]_4 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_3
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [19]),
.I3(Q[19]),
.O(\Q_reg[2]_4 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_4
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.O(\Q_reg[2]_4 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_5
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(Q[23]),
.I3(\Q_reg[31]_0 [23]),
.O(\Q_reg[2]_6 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_6
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(Q[21]),
.I3(\Q_reg[31]_0 [21]),
.O(\Q_reg[2]_6 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_7
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(Q[19]),
.I3(\Q_reg[31]_0 [19]),
.O(\Q_reg[2]_6 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_8
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(Q[17]),
.I3(\Q_reg[31]_0 [17]),
.O(\Q_reg[2]_6 [0]));
LUT2 #(
.INIT(4'h2))
gtXY_o_carry__2_i_1
(.I0(Q[30]),
.I1(\Q_reg[31]_0 [30]),
.O(DI[3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_2
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.O(DI[2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_3
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(\Q_reg[31]_0 [27]),
.I3(Q[27]),
.O(DI[1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_4
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [25]),
.I3(Q[25]),
.O(DI[0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_6
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(Q[29]),
.I3(\Q_reg[31]_0 [29]),
.O(\Q_reg[2]_7 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_7
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(Q[27]),
.I3(\Q_reg[31]_0 [27]),
.O(\Q_reg[2]_7 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_8
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(Q[25]),
.I3(\Q_reg[31]_0 [25]),
.O(\Q_reg[2]_7 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_1
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [7]),
.I3(Q[7]),
.O(\Q_reg[2]_0 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_2
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.O(\Q_reg[2]_0 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_3
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(\Q_reg[31]_0 [3]),
.I3(Q[3]),
.O(\Q_reg[2]_0 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [1]),
.I3(Q[1]),
.O(\Q_reg[2]_0 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_5
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(Q[7]),
.I3(\Q_reg[31]_0 [7]),
.O(S[3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_6
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(Q[5]),
.I3(\Q_reg[31]_0 [5]),
.O(S[2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_7
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(Q[3]),
.I3(\Q_reg[31]_0 [3]),
.O(S[1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_8
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(Q[1]),
.I3(\Q_reg[31]_0 [1]),
.O(S[0]));
endmodule |
module RegisterAdd_2
(S,
Q,
\Q_reg[2]_0 ,
\Q_reg[30]_0 ,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [0:0]S;
output [31:0]Q;
output [0:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[30]_0 ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [0:0]\Q_reg[30]_0 ;
wire [0:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
LUT2 #(
.INIT(4'h9))
eqXY_o_carry__1_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(S));
LUT2 #(
.INIT(4'h9))
gtXY_o_carry__2_i_5
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(\Q_reg[2]_0 ));
endmodule |
module RegisterAdd__parameterized0
(intAS,
D,
E,
op_add_subt,
CLK,
\FSM_sequential_state_reg_reg[1] ,
Q,
\Q_reg[31] ,
CO);
output intAS;
output [0:0]D;
input [0:0]E;
input op_add_subt;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [0:0]Q;
input [0:0]\Q_reg[31] ;
input [0:0]CO;
wire CLK;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [0:0]Q;
wire [0:0]\Q_reg[31] ;
wire intAS;
wire op_add_subt;
LUT4 #(
.INIT(16'h9600))
\Q[0]_i_1__10
(.I0(intAS),
.I1(Q),
.I2(\Q_reg[31] ),
.I3(CO),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(op_add_subt),
.Q(intAS));
endmodule |
module RegisterAdd__parameterized1
(D,
Q,
\Q_reg[25]_0 ,
\Q_reg[6]_0 ,
\Q_reg[30]_0 ,
CLK,
AR);
output [1:0]D;
output [30:0]Q;
input [2:0]\Q_reg[25]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [1:0]D;
wire [30:0]Q;
wire [2:0]\Q_reg[25]_0 ;
wire [30:0]\Q_reg[30]_0 ;
wire [0:0]\Q_reg[6]_0 ;
LUT2 #(
.INIT(4'h6))
\Q[0]_i_1__11
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.O(D[0]));
LUT6 #(
.INIT(64'h4F04B0FBB0FB4F04))
\Q[2]_i_1__9
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[25]_0 [1]),
.I4(\Q_reg[25]_0 [2]),
.I5(Q[25]),
.O(D[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule |
module RegisterAdd__parameterized10
(D,
\Q_reg[25] ,
\Q_reg[23] ,
\Q_reg[16] ,
\Q_reg[4]_0 ,
Q,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[0] ,
\Q_reg[25]_0 ,
\Data_array_SWR[4]_4 ,
E,
\Q_reg[4]_1 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [13:0]D;
output [5:0]\Q_reg[25] ;
output [14:0]\Q_reg[23] ;
output [2:0]\Q_reg[16] ;
input [0:0]\Q_reg[4]_0 ;
input [1:0]Q;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [9:0]\Q_reg[0] ;
input [7:0]\Q_reg[25]_0 ;
input [1:0]\Data_array_SWR[4]_4 ;
input [0:0]E;
input [2:0]\Q_reg[4]_1 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [13:0]D;
wire [1:0]\Data_array_SWR[4]_4 ;
wire [21:18]\Data_array_SWR[5]_2 ;
wire [23:2]\Data_array_SWR[6]_3 ;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [9:0]\Q_reg[0] ;
wire [2:0]\Q_reg[16] ;
wire [14:0]\Q_reg[23] ;
wire [5:0]\Q_reg[25] ;
wire [7:0]\Q_reg[25]_0 ;
wire [0:0]\Q_reg[4]_0 ;
wire [2:0]\Q_reg[4]_1 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[0]_i_1__12
(.I0(\Data_array_SWR[6]_3 [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [2]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[0]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[12]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4]_4 [0]),
.O(\Q_reg[25] [2]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[13]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4]_4 [1]),
.O(\Q_reg[25] [3]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'h02))
\Q[14]_i_1__7
(.I0(\Q_reg[23] [7]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'h02))
\Q[15]_i_1__6
(.I0(\Q_reg[23] [8]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[7]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[16]_i_1__6
(.I0(\Q_reg[25] [1]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0] [8]),
.O(\Q_reg[23] [7]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[16]_i_1__8
(.I0(\Data_array_SWR[6]_3 [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [18]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[8]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[16]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [5]),
.O(\Data_array_SWR[6]_3 [7]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[16]_i_2__1
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [7]),
.O(\Q_reg[25] [1]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[16]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[6]_3 [18]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[17]_i_1__6
(.I0(\Q_reg[25] [0]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0] [9]),
.O(\Q_reg[23] [8]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[17]_i_1__7
(.I0(\Data_array_SWR[6]_3 [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [19]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[9]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[17]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [4]),
.O(\Data_array_SWR[6]_3 [6]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[17]_i_2__1
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [6]),
.O(\Q_reg[25] [0]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[17]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[6]_3 [19]));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_1__6
(.I0(\Data_array_SWR[6]_3 [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [18]),
.O(\Q_reg[23] [9]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[18]_i_1__8
(.I0(\Data_array_SWR[6]_3 [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [20]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_2__0
(.I0(\Data_array_SWR[5]_2 [21]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [3]),
.O(\Data_array_SWR[6]_3 [5]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[18]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[6]_3 [20]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[18]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [7]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[5]_2 [21]));
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_1__6
(.I0(\Data_array_SWR[6]_3 [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [19]),
.O(\Q_reg[23] [10]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[19]_i_1__7
(.I0(\Data_array_SWR[6]_3 [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [21]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_2__0
(.I0(\Data_array_SWR[5]_2 [20]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [2]),
.O(\Data_array_SWR[6]_3 [4]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[19]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[6]_3 [21]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[19]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [6]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[5]_2 [20]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1__10
(.I0(\Q_reg[25] [4]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 ),
.O(\Q_reg[23] [0]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[1]_i_1__13
(.I0(\Data_array_SWR[6]_3 [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [3]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_1__6
(.I0(\Data_array_SWR[6]_3 [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [20]),
.O(\Q_reg[23] [11]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[20]_i_1__8
(.I0(\Data_array_SWR[6]_3 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [22]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_2__0
(.I0(\Data_array_SWR[5]_2 [19]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [1]),
.O(\Data_array_SWR[6]_3 [3]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[20]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [4]),
.O(\Data_array_SWR[6]_3 [22]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[20]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [5]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[5]_2 [19]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_1__7
(.I0(\Data_array_SWR[6]_3 [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [21]),
.O(\Q_reg[23] [12]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[21]_i_1__8
(.I0(\Data_array_SWR[6]_3 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [23]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_2__0
(.I0(\Data_array_SWR[5]_2 [18]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [0]),
.O(\Data_array_SWR[6]_3 [2]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[21]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [5]),
.O(\Data_array_SWR[6]_3 [23]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[21]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [4]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[5]_2 [18]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_1__7
(.I0(\Data_array_SWR[6]_3 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [22]),
.O(\Q_reg[23] [13]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[22]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [6]),
.O(\Q_reg[25] [4]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_1__7
(.I0(\Data_array_SWR[6]_3 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [23]),
.O(\Q_reg[23] [14]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[25]_i_4__0
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [7]),
.O(\Q_reg[25] [5]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[2]_i_1__12
(.I0(\Data_array_SWR[6]_3 [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [4]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\Q[2]_i_1__8
(.I0(\Data_array_SWR[6]_3 [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [2]),
.O(\Q_reg[23] [1]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_1__7
(.I0(\Data_array_SWR[6]_3 [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [3]),
.O(\Q_reg[23] [2]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[3]_i_1__9
(.I0(\Data_array_SWR[6]_3 [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [5]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[4]_i_1__10
(.I0(\Data_array_SWR[6]_3 [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [6]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\Q[4]_i_1__8
(.I0(\Data_array_SWR[6]_3 [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [4]),
.O(\Q_reg[23] [3]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\Q[5]_i_1__6
(.I0(\Data_array_SWR[6]_3 [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [5]),
.O(\Q_reg[23] [4]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[5]_i_1__7
(.I0(\Data_array_SWR[6]_3 [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [7]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\Q[6]_i_1__9
(.I0(\Data_array_SWR[6]_3 [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [6]),
.O(\Q_reg[23] [5]));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\Q[7]_i_1__7
(.I0(\Data_array_SWR[6]_3 [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [7]),
.O(\Q_reg[23] [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[4]_1 [0]),
.Q(\Q_reg[16] [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[4]_1 [1]),
.Q(\Q_reg[16] [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[4]_1 [2]),
.Q(\Q_reg[16] [2]));
endmodule |
module RegisterAdd__parameterized11
(D,
Q,
\Q_reg[15] ,
\Q_reg[4] ,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[4]_0 ,
\Q_reg[0]_0 ,
E,
\Q_reg[1]_0 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [5:0]D;
output [1:0]Q;
output [5:0]\Q_reg[15] ;
input [3:0]\Q_reg[4] ;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]\Q_reg[4]_0 ;
input [3:0]\Q_reg[0]_0 ;
input [0:0]E;
input [1:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [5:0]D;
wire [11:10]\Data_array_SWR[6]_3 ;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [3:0]\Q_reg[0]_0 ;
wire [5:0]\Q_reg[15] ;
wire [1:0]\Q_reg[1]_0 ;
wire [3:0]\Q_reg[4] ;
wire [0:0]\Q_reg[4]_0 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1__9
(.I0(\Q_reg[4] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [10]),
.O(\Q_reg[15] [2]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1__9
(.I0(\Q_reg[4] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [11]),
.O(\Q_reg[15] [3]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[12]_i_1__9
(.I0(\Data_array_SWR[6]_3 [11]),
.I1(Q[1]),
.I2(\Q_reg[4] [2]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_2__1
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [1]),
.O(\Data_array_SWR[6]_3 [11]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[13]_i_1__7
(.I0(\Data_array_SWR[6]_3 [10]),
.I1(Q[1]),
.I2(\Q_reg[4] [3]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [0]),
.O(\Data_array_SWR[6]_3 [10]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1__8
(.I0(\Data_array_SWR[6]_3 [11]),
.I1(Q[1]),
.I2(\Q_reg[4] [2]),
.O(\Q_reg[15] [4]));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1__7
(.I0(\Data_array_SWR[6]_3 [10]),
.I1(Q[1]),
.I2(\Q_reg[4] [3]),
.O(\Q_reg[15] [5]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'h02))
\Q[6]_i_1__8
(.I0(\Q_reg[15] [0]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'h02))
\Q[7]_i_1__6
(.I0(\Q_reg[15] [1]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[8]_i_1__8
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [3]),
.I3(Q[1]),
.I4(\Q_reg[4] [0]),
.O(\Q_reg[15] [0]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[8]_i_1__9
(.I0(\Q_reg[4] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [10]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[2]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[9]_i_1__8
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [2]),
.I3(Q[1]),
.I4(\Q_reg[4] [1]),
.O(\Q_reg[15] [1]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[9]_i_1__9
(.I0(\Q_reg[4] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [11]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[1]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[1]_0 [1]),
.Q(Q[1]));
endmodule |
module RegisterAdd__parameterized12
(Q,
\Q_reg[4] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[4] ;
input [2:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[4] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR[0]),
.D(D[2]),
.Q(Q[2]));
endmodule |
module RegisterAdd__parameterized13
(S,
\Q_reg[30] ,
\Q_reg[30]_0 ,
D,
\Q_reg[1]_0 ,
Q,
exp_rslt_NRM2_EW1,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[1]_1 ,
\Q_reg[1]_2 ,
CLK,
AR);
output [3:0]S;
output [3:0]\Q_reg[30] ;
output [6:0]\Q_reg[30]_0 ;
output [7:0]D;
output [0:0]\Q_reg[1]_0 ;
input [0:0]Q;
input [7:0]exp_rslt_NRM2_EW1;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]\Q_reg[1]_1 ;
input [12:0]\Q_reg[1]_2 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [7:0]D;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[1]_1 ;
wire [12:0]\Q_reg[1]_2 ;
wire [3:0]\Q_reg[30] ;
wire [6:0]\Q_reg[30]_0 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
wire [3:0]S;
wire UNDRFLW_FLAG_FRMT;
wire [7:0]exp_rslt_NRM2_EW1;
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hFE))
\Q[23]_i_1__6
(.I0(exp_rslt_NRM2_EW1[0]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hFE))
\Q[24]_i_1__7
(.I0(exp_rslt_NRM2_EW1[1]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hFE))
\Q[25]_i_1__7
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hFE))
\Q[26]_i_1__6
(.I0(exp_rslt_NRM2_EW1[3]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hFE))
\Q[27]_i_1__5
(.I0(exp_rslt_NRM2_EW1[4]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hFE))
\Q[28]_i_1__5
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hFE))
\Q[29]_i_1__6
(.I0(exp_rslt_NRM2_EW1[6]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hFE))
\Q[30]_i_1__5
(.I0(exp_rslt_NRM2_EW1[7]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [0]),
.Q(\Q_reg[30]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [1]),
.Q(\Q_reg[30]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [2]),
.Q(\Q_reg[30]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [3]),
.Q(\Q_reg[30]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [4]),
.Q(\Q_reg[30]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [5]),
.Q(\Q_reg[30]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [6]),
.Q(\Q_reg[30]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [9]),
.Q(\Q_reg_n_0_[9] ));
LUT2 #(
.INIT(4'h9))
_inferred__1_carry__0_i_1
(.I0(\Q_reg[30]_0 [6]),
.I1(\Q_reg_n_0_[7] ),
.O(\Q_reg[30] [3]));
LUT2 #(
.INIT(4'h9))
_inferred__1_carry__0_i_2
(.I0(\Q_reg[30]_0 [5]),
.I1(\Q_reg[30]_0 [6]),
.O(\Q_reg[30] [2]));
LUT2 #(
.INIT(4'h9))
_inferred__1_carry__0_i_3
(.I0(\Q_reg[30]_0 [5]),
.I1(Q),
.O(\Q_reg[30] [1]));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry__0_i_4
(.I0(Q),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q_reg[30]_0 [4]),
.O(\Q_reg[30] [0]));
LUT1 #(
.INIT(2'h1))
_inferred__1_carry__1_i_1
(.I0(\Q_reg_n_0_[7] ),
.O(\Q_reg[1]_0 ));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry_i_2
(.I0(Q),
.I1(\Q_reg_n_0_[11] ),
.I2(\Q_reg[30]_0 [3]),
.O(S[3]));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry_i_3
(.I0(Q),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg[30]_0 [2]),
.O(S[2]));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry_i_4
(.I0(Q),
.I1(\Q_reg_n_0_[9] ),
.I2(\Q_reg[30]_0 [1]),
.O(S[1]));
LUT2 #(
.INIT(4'hE))
_inferred__1_carry_i_5
(.I0(\Q_reg_n_0_[8] ),
.I1(Q),
.O(S[0]));
endmodule |
module RegisterAdd__parameterized14
(D,
DI,
Q,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[1]_0 ,
\Q_reg[2]_0 ,
CLK,
AR);
output [0:0]D;
output [0:0]DI;
output [1:0]Q;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]\Q_reg[1]_0 ;
input [2:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]DI;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [2:0]\Q_reg[2]_0 ;
wire SIGN_FLAG_SHT1SHT2;
wire UNDRFLW_FLAG_FRMT;
LUT3 #(
.INIT(8'h0E))
\Q[31]_i_1__6
(.I0(UNDRFLW_FLAG_FRMT),
.I1(SIGN_FLAG_SHT1SHT2),
.I2(OVRFLW_FLAG_FRMT),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[2]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[2]_0 [1]),
.Q(SIGN_FLAG_SHT1SHT2));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[2]_0 [2]),
.Q(Q[1]));
LUT1 #(
.INIT(2'h1))
_inferred__1_carry_i_1
(.I0(Q[1]),
.O(DI));
endmodule |
module RegisterAdd__parameterized15
(O,
Q,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
CO,
\Q_reg[24]_0 ,
S,
\Q_reg[6]_0 ,
\Q_reg[10]_0 ,
\Q_reg[14]_0 ,
\Q_reg[18]_0 ,
\Q_reg[22]_0 ,
E,
\Q_reg[30]_0 ,
CLK,
AR);
output [3:0]O;
output [30:0]Q;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [0:0]CO;
output [3:0]\Q_reg[24]_0 ;
input [3:0]S;
input [3:0]\Q_reg[6]_0 ;
input [3:0]\Q_reg[10]_0 ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[18]_0 ;
input [3:0]\Q_reg[22]_0 ;
input [0:0]E;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [3:0]O;
wire [30:0]Q;
wire [3:0]\Q_reg[10]_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_3_n_0 ;
wire \Q_reg[12]_i_3_n_1 ;
wire \Q_reg[12]_i_3_n_2 ;
wire \Q_reg[12]_i_3_n_3 ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_3_n_0 ;
wire \Q_reg[16]_i_3_n_1 ;
wire \Q_reg[16]_i_3_n_2 ;
wire \Q_reg[16]_i_3_n_3 ;
wire [3:0]\Q_reg[18]_0 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_3_n_0 ;
wire \Q_reg[20]_i_3_n_1 ;
wire \Q_reg[20]_i_3_n_2 ;
wire \Q_reg[20]_i_3_n_3 ;
wire [3:0]\Q_reg[22]_0 ;
wire [3:0]\Q_reg[24]_0 ;
wire \Q_reg[24]_i_3_n_1 ;
wire \Q_reg[24]_i_3_n_2 ;
wire \Q_reg[24]_i_3_n_3 ;
wire [30:0]\Q_reg[30]_0 ;
wire \Q_reg[4]_i_3_n_0 ;
wire \Q_reg[4]_i_3_n_1 ;
wire \Q_reg[4]_i_3_n_2 ;
wire \Q_reg[4]_i_3_n_3 ;
wire [3:0]\Q_reg[6]_0 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_3_n_0 ;
wire \Q_reg[8]_i_3_n_1 ;
wire \Q_reg[8]_i_3_n_2 ;
wire \Q_reg[8]_i_3_n_3 ;
wire [3:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
CARRY4 \Q_reg[12]_i_3
(.CI(\Q_reg[8]_i_3_n_0 ),
.CO({\Q_reg[12]_i_3_n_0 ,\Q_reg[12]_i_3_n_1 ,\Q_reg[12]_i_3_n_2 ,\Q_reg[12]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[10:7]),
.O(\Q_reg[12]_0 ),
.S(\Q_reg[10]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
CARRY4 \Q_reg[16]_i_3
(.CI(\Q_reg[12]_i_3_n_0 ),
.CO({\Q_reg[16]_i_3_n_0 ,\Q_reg[16]_i_3_n_1 ,\Q_reg[16]_i_3_n_2 ,\Q_reg[16]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[14:11]),
.O(\Q_reg[16]_0 ),
.S(\Q_reg[14]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
CARRY4 \Q_reg[20]_i_3
(.CI(\Q_reg[16]_i_3_n_0 ),
.CO({\Q_reg[20]_i_3_n_0 ,\Q_reg[20]_i_3_n_1 ,\Q_reg[20]_i_3_n_2 ,\Q_reg[20]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[18:15]),
.O(\Q_reg[20]_0 ),
.S(\Q_reg[18]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
CARRY4 \Q_reg[24]_i_3
(.CI(\Q_reg[20]_i_3_n_0 ),
.CO({CO,\Q_reg[24]_i_3_n_1 ,\Q_reg[24]_i_3_n_2 ,\Q_reg[24]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[22:19]),
.O(\Q_reg[24]_0 ),
.S(\Q_reg[22]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
CARRY4 \Q_reg[4]_i_3
(.CI(1'b0),
.CO({\Q_reg[4]_i_3_n_0 ,\Q_reg[4]_i_3_n_1 ,\Q_reg[4]_i_3_n_2 ,\Q_reg[4]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({Q[2:0],1'b0}),
.O(O),
.S(S));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
CARRY4 \Q_reg[8]_i_3
(.CI(\Q_reg[4]_i_3_n_0 ),
.CO({\Q_reg[8]_i_3_n_0 ,\Q_reg[8]_i_3_n_1 ,\Q_reg[8]_i_3_n_2 ,\Q_reg[8]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[6:3]),
.O(\Q_reg[8]_0 ),
.S(\Q_reg[6]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule |
module RegisterAdd__parameterized16
(Q,
S,
O,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
\Q_reg[24]_0 ,
\Q_reg[25]_0 ,
CO,
\Q_reg[25]_1 ,
\Q_reg[22]_0 ,
\Q_reg[22]_1 ,
E,
D,
CLK,
AR);
output [23:0]Q;
output [0:0]S;
output [3:0]O;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [3:0]\Q_reg[24]_0 ;
output [0:0]\Q_reg[25]_0 ;
output [0:0]CO;
output [0:0]\Q_reg[25]_1 ;
input [22:0]\Q_reg[22]_0 ;
input [0:0]\Q_reg[22]_1 ;
input [0:0]E;
input [25:0]D;
input CLK;
input [3:0]AR;
wire [3:0]AR;
wire CLK;
wire [0:0]CO;
wire [25:0]D;
wire [0:0]E;
wire [3:0]O;
wire [23:0]Q;
wire \Q[12]_i_4__1_n_0 ;
wire \Q[12]_i_5__1_n_0 ;
wire \Q[12]_i_6__0_n_0 ;
wire \Q[12]_i_7__0_n_0 ;
wire \Q[16]_i_4__0_n_0 ;
wire \Q[16]_i_5_n_0 ;
wire \Q[16]_i_6_n_0 ;
wire \Q[16]_i_7_n_0 ;
wire \Q[20]_i_4__0_n_0 ;
wire \Q[20]_i_5__0_n_0 ;
wire \Q[20]_i_6_n_0 ;
wire \Q[20]_i_7_n_0 ;
wire \Q[24]_i_4_n_0 ;
wire \Q[24]_i_5_n_0 ;
wire \Q[24]_i_6_n_0 ;
wire \Q[24]_i_7_n_0 ;
wire \Q[2]_i_3_n_0 ;
wire \Q[4]_i_4_n_0 ;
wire \Q[4]_i_5_n_0 ;
wire \Q[4]_i_6_n_0 ;
wire \Q[4]_i_7_n_0 ;
wire \Q[4]_i_8_n_0 ;
wire \Q[8]_i_4__0_n_0 ;
wire \Q[8]_i_5__0_n_0 ;
wire \Q[8]_i_6__0_n_0 ;
wire \Q[8]_i_7__0_n_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_2_n_0 ;
wire \Q_reg[12]_i_2_n_1 ;
wire \Q_reg[12]_i_2_n_2 ;
wire \Q_reg[12]_i_2_n_3 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_2_n_0 ;
wire \Q_reg[16]_i_2_n_1 ;
wire \Q_reg[16]_i_2_n_2 ;
wire \Q_reg[16]_i_2_n_3 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_2_n_0 ;
wire \Q_reg[20]_i_2_n_1 ;
wire \Q_reg[20]_i_2_n_2 ;
wire \Q_reg[20]_i_2_n_3 ;
wire [22:0]\Q_reg[22]_0 ;
wire [0:0]\Q_reg[22]_1 ;
wire [3:0]\Q_reg[24]_0 ;
wire \Q_reg[24]_i_2_n_0 ;
wire \Q_reg[24]_i_2_n_1 ;
wire \Q_reg[24]_i_2_n_2 ;
wire \Q_reg[24]_i_2_n_3 ;
wire [0:0]\Q_reg[25]_0 ;
wire [0:0]\Q_reg[25]_1 ;
wire \Q_reg[4]_i_2_n_0 ;
wire \Q_reg[4]_i_2_n_1 ;
wire \Q_reg[4]_i_2_n_2 ;
wire \Q_reg[4]_i_2_n_3 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_2_n_0 ;
wire \Q_reg[8]_i_2_n_1 ;
wire \Q_reg[8]_i_2_n_2 ;
wire \Q_reg[8]_i_2_n_3 ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[25] ;
wire [3:0]\NLW_Q_reg[25]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[25]_i_2_O_UNCONNECTED ;
wire [3:0]\NLW_Q_reg[2]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[2]_i_2_O_UNCONNECTED ;
assign S[0] = \Q_reg_n_0_[1] ;
LUT2 #(
.INIT(4'h9))
\Q[12]_i_4__1
(.I0(Q[11]),
.I1(\Q_reg[22]_0 [10]),
.O(\Q[12]_i_4__1_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_5__1
(.I0(Q[10]),
.I1(\Q_reg[22]_0 [9]),
.O(\Q[12]_i_5__1_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_6__0
(.I0(Q[9]),
.I1(\Q_reg[22]_0 [8]),
.O(\Q[12]_i_6__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_7__0
(.I0(Q[8]),
.I1(\Q_reg[22]_0 [7]),
.O(\Q[12]_i_7__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_4__0
(.I0(Q[15]),
.I1(\Q_reg[22]_0 [14]),
.O(\Q[16]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_5
(.I0(Q[14]),
.I1(\Q_reg[22]_0 [13]),
.O(\Q[16]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_6
(.I0(Q[13]),
.I1(\Q_reg[22]_0 [12]),
.O(\Q[16]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_7
(.I0(Q[12]),
.I1(\Q_reg[22]_0 [11]),
.O(\Q[16]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_4__0
(.I0(Q[19]),
.I1(\Q_reg[22]_0 [18]),
.O(\Q[20]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_5__0
(.I0(Q[18]),
.I1(\Q_reg[22]_0 [17]),
.O(\Q[20]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_6
(.I0(Q[17]),
.I1(\Q_reg[22]_0 [16]),
.O(\Q[20]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_7
(.I0(Q[16]),
.I1(\Q_reg[22]_0 [15]),
.O(\Q[20]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_4
(.I0(Q[23]),
.I1(\Q_reg[22]_0 [22]),
.O(\Q[24]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_5
(.I0(Q[22]),
.I1(\Q_reg[22]_0 [21]),
.O(\Q[24]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_6
(.I0(Q[21]),
.I1(\Q_reg[22]_0 [20]),
.O(\Q[24]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_7
(.I0(Q[20]),
.I1(\Q_reg[22]_0 [19]),
.O(\Q[24]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[2]_i_3
(.I0(\Q_reg_n_0_[25] ),
.O(\Q[2]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_4
(.I0(Q[0]),
.O(\Q[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_5
(.I0(Q[3]),
.I1(\Q_reg[22]_0 [2]),
.O(\Q[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_6
(.I0(Q[2]),
.I1(\Q_reg[22]_0 [1]),
.O(\Q[4]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_7
(.I0(Q[1]),
.I1(\Q_reg[22]_0 [0]),
.O(\Q[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_8
(.I0(\Q_reg_n_0_[1] ),
.O(\Q[4]_i_8_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_4__0
(.I0(Q[7]),
.I1(\Q_reg[22]_0 [6]),
.O(\Q[8]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_5__0
(.I0(Q[6]),
.I1(\Q_reg[22]_0 [5]),
.O(\Q[8]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_6__0
(.I0(Q[5]),
.I1(\Q_reg[22]_0 [4]),
.O(\Q[8]_i_6__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_7__0
(.I0(Q[4]),
.I1(\Q_reg[22]_0 [3]),
.O(\Q[8]_i_7__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[10]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[11]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[12]),
.Q(Q[11]));
CARRY4 \Q_reg[12]_i_2
(.CI(\Q_reg[8]_i_2_n_0 ),
.CO({\Q_reg[12]_i_2_n_0 ,\Q_reg[12]_i_2_n_1 ,\Q_reg[12]_i_2_n_2 ,\Q_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [10:7]),
.O(\Q_reg[12]_0 ),
.S({\Q[12]_i_4__1_n_0 ,\Q[12]_i_5__1_n_0 ,\Q[12]_i_6__0_n_0 ,\Q[12]_i_7__0_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[13]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[14]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[15]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[16]),
.Q(Q[15]));
CARRY4 \Q_reg[16]_i_2
(.CI(\Q_reg[12]_i_2_n_0 ),
.CO({\Q_reg[16]_i_2_n_0 ,\Q_reg[16]_i_2_n_1 ,\Q_reg[16]_i_2_n_2 ,\Q_reg[16]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [14:11]),
.O(\Q_reg[16]_0 ),
.S({\Q[16]_i_4__0_n_0 ,\Q[16]_i_5_n_0 ,\Q[16]_i_6_n_0 ,\Q[16]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[17]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[18]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[19]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(D[1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[20]),
.Q(Q[19]));
CARRY4 \Q_reg[20]_i_2
(.CI(\Q_reg[16]_i_2_n_0 ),
.CO({\Q_reg[20]_i_2_n_0 ,\Q_reg[20]_i_2_n_1 ,\Q_reg[20]_i_2_n_2 ,\Q_reg[20]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [18:15]),
.O(\Q_reg[20]_0 ),
.S({\Q[20]_i_4__0_n_0 ,\Q[20]_i_5__0_n_0 ,\Q[20]_i_6_n_0 ,\Q[20]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[21]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[22]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[23]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[24]),
.Q(Q[23]));
CARRY4 \Q_reg[24]_i_2
(.CI(\Q_reg[20]_i_2_n_0 ),
.CO({\Q_reg[24]_i_2_n_0 ,\Q_reg[24]_i_2_n_1 ,\Q_reg[24]_i_2_n_2 ,\Q_reg[24]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [22:19]),
.O(\Q_reg[24]_0 ),
.S({\Q[24]_i_4_n_0 ,\Q[24]_i_5_n_0 ,\Q[24]_i_6_n_0 ,\Q[24]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[25]),
.Q(\Q_reg_n_0_[25] ));
CARRY4 \Q_reg[25]_i_2
(.CI(\Q_reg[24]_i_2_n_0 ),
.CO(\NLW_Q_reg[25]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Q_reg[25]_i_2_O_UNCONNECTED [3:1],\Q_reg[25]_0 }),
.S({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[2]),
.Q(Q[1]));
CARRY4 \Q_reg[2]_i_2
(.CI(\Q_reg[22]_1 ),
.CO({\NLW_Q_reg[2]_i_2_CO_UNCONNECTED [3:2],CO,\NLW_Q_reg[2]_i_2_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }),
.O({\NLW_Q_reg[2]_i_2_O_UNCONNECTED [3:1],\Q_reg[25]_1 }),
.S({1'b0,1'b0,1'b1,\Q[2]_i_3_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[3]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[4]),
.Q(Q[3]));
CARRY4 \Q_reg[4]_i_2
(.CI(1'b0),
.CO({\Q_reg[4]_i_2_n_0 ,\Q_reg[4]_i_2_n_1 ,\Q_reg[4]_i_2_n_2 ,\Q_reg[4]_i_2_n_3 }),
.CYINIT(\Q[4]_i_4_n_0 ),
.DI({\Q_reg[22]_0 [2:0],1'b0}),
.O(O),
.S({\Q[4]_i_5_n_0 ,\Q[4]_i_6_n_0 ,\Q[4]_i_7_n_0 ,\Q[4]_i_8_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[5]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[6]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[7]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[8]),
.Q(Q[7]));
CARRY4 \Q_reg[8]_i_2
(.CI(\Q_reg[4]_i_2_n_0 ),
.CO({\Q_reg[8]_i_2_n_0 ,\Q_reg[8]_i_2_n_1 ,\Q_reg[8]_i_2_n_2 ,\Q_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [6:3]),
.O(\Q_reg[8]_0 ),
.S({\Q[8]_i_4__0_n_0 ,\Q[8]_i_5__0_n_0 ,\Q[8]_i_6__0_n_0 ,\Q[8]_i_7__0_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[9]),
.Q(Q[8]));
endmodule |
module RegisterAdd__parameterized17
(\Q_reg[2]_0 ,
Q,
CO,
E,
\Q_reg[2]_1 ,
CLK,
AR);
output [2:0]\Q_reg[2]_0 ;
output [0:0]Q;
input [0:0]CO;
input [0:0]E;
input [2:0]\Q_reg[2]_1 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [0:0]Q;
wire [2:0]\Q_reg[2]_0 ;
wire [2:0]\Q_reg[2]_1 ;
LUT2 #(
.INIT(4'h2))
\Q[2]_i_1__11
(.I0(CO),
.I1(Q),
.O(\Q_reg[2]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[2]_1 [0]),
.Q(\Q_reg[2]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[2]_1 [1]),
.Q(Q));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[2]_1 [2]),
.Q(\Q_reg[2]_0 [1]));
endmodule |
module RegisterAdd__parameterized18
(D,
\Q_reg[12]_0 ,
\Q_reg[12]_1 ,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
\Q_reg[2]_0 ,
Q,
\Q_reg[2]_1 ,
\Q_reg[22]_0 ,
\Q_reg[1]_2 ,
CLK,
AR);
output [24:0]D;
output [4:0]\Q_reg[12]_0 ;
output [0:0]\Q_reg[12]_1 ;
input [0:0]\Q_reg[1]_0 ;
input \Q_reg[1]_1 ;
input \Q_reg[2]_0 ;
input [1:0]Q;
input [0:0]\Q_reg[2]_1 ;
input [22:0]\Q_reg[22]_0 ;
input [25:0]\Q_reg[1]_2 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [24:0]D;
wire [1:0]Q;
wire \Q[0]_i_2_n_0 ;
wire \Q[10]_i_2__0_n_0 ;
wire \Q[10]_i_2_n_0 ;
wire \Q[10]_i_3_n_0 ;
wire \Q[10]_i_4_n_0 ;
wire \Q[11]_i_2_n_0 ;
wire \Q[12]_i_2__0_n_0 ;
wire \Q[12]_i_2_n_0 ;
wire \Q[12]_i_3_n_0 ;
wire \Q[12]_i_4_n_0 ;
wire \Q[12]_i_5_n_0 ;
wire \Q[12]_i_6_n_0 ;
wire \Q[12]_i_7_n_0 ;
wire \Q[13]_i_2_n_0 ;
wire \Q[14]_i_2__0_n_0 ;
wire \Q[15]_i_2_n_0 ;
wire \Q[16]_i_2_n_0 ;
wire \Q[17]_i_2_n_0 ;
wire \Q[18]_i_2_n_0 ;
wire \Q[19]_i_2_n_0 ;
wire \Q[1]_i_2__0_n_0 ;
wire \Q[20]_i_2_n_0 ;
wire \Q[21]_i_2_n_0 ;
wire \Q[22]_i_2_n_0 ;
wire \Q[23]_i_2_n_0 ;
wire \Q[24]_i_2_n_0 ;
wire \Q[24]_i_3_n_0 ;
wire \Q[2]_i_2_n_0 ;
wire \Q[3]_i_2_n_0 ;
wire \Q[4]_i_2_n_0 ;
wire \Q[5]_i_2_n_0 ;
wire \Q[6]_i_2__0_n_0 ;
wire \Q[7]_i_2_n_0 ;
wire \Q[8]_i_2__0_n_0 ;
wire \Q[8]_i_2_n_0 ;
wire \Q[8]_i_3_n_0 ;
wire \Q[8]_i_4_n_0 ;
wire \Q[8]_i_5_n_0 ;
wire \Q[8]_i_6_n_0 ;
wire \Q[8]_i_7_n_0 ;
wire \Q[8]_i_8_n_0 ;
wire \Q[8]_i_9_n_0 ;
wire \Q[9]_i_10_n_0 ;
wire \Q[9]_i_11_n_0 ;
wire \Q[9]_i_2__0_n_0 ;
wire \Q[9]_i_2_n_0 ;
wire \Q[9]_i_3_n_0 ;
wire \Q[9]_i_4_n_0 ;
wire \Q[9]_i_5_n_0 ;
wire \Q[9]_i_6_n_0 ;
wire \Q[9]_i_7_n_0 ;
wire \Q[9]_i_8_n_0 ;
wire \Q[9]_i_9_n_0 ;
wire [4:0]\Q_reg[12]_0 ;
wire [0:0]\Q_reg[12]_1 ;
wire [0:0]\Q_reg[1]_0 ;
wire \Q_reg[1]_1 ;
wire [25:0]\Q_reg[1]_2 ;
wire [22:0]\Q_reg[22]_0 ;
wire \Q_reg[2]_0 ;
wire [0:0]\Q_reg[2]_1 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[13] ;
wire \Q_reg_n_0_[14] ;
wire \Q_reg_n_0_[15] ;
wire \Q_reg_n_0_[16] ;
wire \Q_reg_n_0_[17] ;
wire \Q_reg_n_0_[18] ;
wire \Q_reg_n_0_[19] ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[20] ;
wire \Q_reg_n_0_[21] ;
wire \Q_reg_n_0_[22] ;
wire \Q_reg_n_0_[23] ;
wire \Q_reg_n_0_[24] ;
wire \Q_reg_n_0_[25] ;
wire \Q_reg_n_0_[2] ;
wire \Q_reg_n_0_[3] ;
wire \Q_reg_n_0_[4] ;
wire \Q_reg_n_0_[5] ;
wire \Q_reg_n_0_[6] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
LUT6 #(
.INIT(64'hFFFFFFC0FFA0FFC0))
\Q[0]_i_1__8
(.I0(\Q[3]_i_2_n_0 ),
.I1(\Q[2]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[0]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[1]_i_2__0_n_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'h20))
\Q[0]_i_2
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg[2]_1 ),
.I2(Q[0]),
.O(\Q[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[10]_i_1__6
(.I0(\Q[13]_i_2_n_0 ),
.I1(\Q[12]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[11]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[10]_i_2__0_n_0 ),
.O(D[10]));
LUT6 #(
.INIT(64'h0001000000010001))
\Q[10]_i_1__7
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[23] ),
.I2(\Q_reg_n_0_[24] ),
.I3(\Q_reg_n_0_[25] ),
.I4(\Q[10]_i_2_n_0 ),
.I5(\Q[10]_i_3_n_0 ),
.O(\Q_reg[12]_0 [2]));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
\Q[10]_i_2
(.I0(\Q[12]_i_6_n_0 ),
.I1(\Q[12]_i_3_n_0 ),
.I2(\Q_reg[12]_1 ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[12]_i_2_n_0 ),
.I5(\Q[10]_i_4_n_0 ),
.O(\Q[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[10]_i_2__0
(.I0(\Q_reg_n_0_[15] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[10] ),
.I4(\Q_reg[22]_0 [8]),
.O(\Q[10]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT4 #(
.INIT(16'h0001))
\Q[10]_i_3
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg_n_0_[20] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[10]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT4 #(
.INIT(16'h0001))
\Q[10]_i_4
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_1__6
(.I0(\Q[14]_i_2__0_n_0 ),
.I1(\Q[13]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[12]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[11]_i_2_n_0 ),
.O(D[11]));
LUT5 #(
.INIT(32'h8000AAAA))
\Q[11]_i_1__7
(.I0(\Q[12]_i_5_n_0 ),
.I1(\Q[12]_i_3_n_0 ),
.I2(\Q[12]_i_2_n_0 ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[12]_i_4_n_0 ),
.O(\Q_reg[12]_0 [3]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[11]_i_2
(.I0(\Q_reg_n_0_[14] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg[22]_0 [9]),
.O(\Q[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_1__6
(.I0(\Q[15]_i_2_n_0 ),
.I1(\Q[14]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[13]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[12]_i_2__0_n_0 ),
.O(D[12]));
LUT6 #(
.INIT(64'hFDFF000000000000))
\Q[12]_i_1__7
(.I0(\Q[12]_i_2_n_0 ),
.I1(\Q_reg_n_0_[1] ),
.I2(\Q_reg[12]_1 ),
.I3(\Q[12]_i_3_n_0 ),
.I4(\Q[12]_i_4_n_0 ),
.I5(\Q[12]_i_5_n_0 ),
.O(\Q_reg[12]_0 [4]));
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_2
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[4] ),
.O(\Q[12]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT5 #(
.INIT(32'hFB3BC808))
\Q[12]_i_2__0
(.I0(\Q_reg_n_0_[13] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[12] ),
.I4(\Q_reg[22]_0 [10]),
.O(\Q[12]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_3
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q_reg_n_0_[6] ),
.I3(\Q_reg_n_0_[7] ),
.O(\Q[12]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h00010000))
\Q[12]_i_4
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q[12]_i_6_n_0 ),
.O(\Q[12]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h00010000))
\Q[12]_i_5
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg_n_0_[19] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q[12]_i_7_n_0 ),
.O(\Q[12]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_6
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg_n_0_[16] ),
.I2(\Q_reg_n_0_[15] ),
.I3(\Q_reg_n_0_[14] ),
.O(\Q[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_7
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q_reg_n_0_[23] ),
.I3(\Q_reg_n_0_[22] ),
.O(\Q[12]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_1__5
(.I0(\Q[16]_i_2_n_0 ),
.I1(\Q[15]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[14]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[13]_i_2_n_0 ),
.O(D[13]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[13]_i_2
(.I0(\Q_reg_n_0_[12] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[13] ),
.I4(\Q_reg[22]_0 [11]),
.O(\Q[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_1__6
(.I0(\Q[17]_i_2_n_0 ),
.I1(\Q[16]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[15]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[14]_i_2__0_n_0 ),
.O(D[14]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[14]_i_2__0
(.I0(\Q_reg_n_0_[11] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[14] ),
.I4(\Q_reg[22]_0 [12]),
.O(\Q[14]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_1__5
(.I0(\Q[18]_i_2_n_0 ),
.I1(\Q[17]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[16]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[15]_i_2_n_0 ),
.O(D[15]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[15]_i_2
(.I0(\Q_reg_n_0_[10] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[15] ),
.I4(\Q_reg[22]_0 [13]),
.O(\Q[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_1__5
(.I0(\Q[19]_i_2_n_0 ),
.I1(\Q[18]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[17]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[16]_i_2_n_0 ),
.O(D[16]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[16]_i_2
(.I0(\Q_reg_n_0_[9] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[16] ),
.I4(\Q_reg[22]_0 [14]),
.O(\Q[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_1__5
(.I0(\Q[20]_i_2_n_0 ),
.I1(\Q[19]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[18]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[17]_i_2_n_0 ),
.O(D[17]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[17]_i_2
(.I0(\Q_reg_n_0_[8] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[17] ),
.I4(\Q_reg[22]_0 [15]),
.O(\Q[17]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_1__5
(.I0(\Q[21]_i_2_n_0 ),
.I1(\Q[20]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[19]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[18]_i_2_n_0 ),
.O(D[18]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[18]_i_2
(.I0(\Q_reg_n_0_[7] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[18] ),
.I4(\Q_reg[22]_0 [16]),
.O(\Q[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_1__5
(.I0(\Q[22]_i_2_n_0 ),
.I1(\Q[21]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[20]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[19]_i_2_n_0 ),
.O(D[19]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[19]_i_2
(.I0(\Q_reg_n_0_[6] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[19] ),
.I4(\Q_reg[22]_0 [17]),
.O(\Q[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[1]_i_1__6
(.I0(\Q[4]_i_2_n_0 ),
.I1(\Q[3]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[2]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[1]_i_2__0_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT4 #(
.INIT(16'h8C80))
\Q[1]_i_2__0
(.I0(\Q_reg_n_0_[1] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[24] ),
.O(\Q[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_1__5
(.I0(\Q[23]_i_2_n_0 ),
.I1(\Q[22]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[21]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[20]_i_2_n_0 ),
.O(D[20]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[20]_i_2
(.I0(\Q_reg_n_0_[5] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg[22]_0 [18]),
.O(\Q[20]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_1__6
(.I0(\Q[24]_i_2_n_0 ),
.I1(\Q[23]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[22]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[21]_i_2_n_0 ),
.O(D[21]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[21]_i_2
(.I0(\Q_reg_n_0_[4] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q_reg[22]_0 [19]),
.O(\Q[21]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_1__6
(.I0(\Q[24]_i_3_n_0 ),
.I1(\Q[24]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[23]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[22]_i_2_n_0 ),
.O(D[22]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[22]_i_2
(.I0(\Q_reg_n_0_[3] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[22] ),
.I4(\Q_reg[22]_0 [20]),
.O(\Q[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0EFEFAFA0E0E0))
\Q[23]_i_1__5
(.I0(\Q_reg[1]_0 ),
.I1(\Q[24]_i_3_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[24]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[23]_i_2_n_0 ),
.O(D[23]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[23]_i_2
(.I0(\Q_reg_n_0_[2] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[23] ),
.I4(\Q_reg[22]_0 [21]),
.O(\Q[23]_i_2_n_0 ));
LUT4 #(
.INIT(16'h00E2))
\Q[24]_i_1__6
(.I0(\Q[24]_i_2_n_0 ),
.I1(\Q_reg[2]_0 ),
.I2(\Q[24]_i_3_n_0 ),
.I3(\Q_reg[1]_1 ),
.O(D[24]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT5 #(
.INIT(32'hFB3BC808))
\Q[24]_i_2
(.I0(\Q_reg_n_0_[1] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[24] ),
.I4(\Q_reg[22]_0 [22]),
.O(\Q[24]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'hFB3B))
\Q[24]_i_3
(.I0(\Q_reg[12]_1 ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[25] ),
.O(\Q[24]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[2]_i_1__5
(.I0(\Q[5]_i_2_n_0 ),
.I1(\Q[4]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[3]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[2]_i_2_n_0 ),
.O(D[2]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[2]_i_2
(.I0(\Q_reg_n_0_[23] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg[22]_0 [0]),
.O(\Q[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[3]_i_1__5
(.I0(\Q[6]_i_2__0_n_0 ),
.I1(\Q[5]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[4]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[3]_i_2_n_0 ),
.O(D[3]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[3]_i_2
(.I0(\Q_reg_n_0_[22] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[3] ),
.I4(\Q_reg[22]_0 [1]),
.O(\Q[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[4]_i_1__6
(.I0(\Q[7]_i_2_n_0 ),
.I1(\Q[6]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[5]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[4]_i_2_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[4]_i_2
(.I0(\Q_reg_n_0_[21] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[4] ),
.I4(\Q_reg[22]_0 [2]),
.O(\Q[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[5]_i_1__5
(.I0(\Q[8]_i_2__0_n_0 ),
.I1(\Q[7]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[6]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[5]_i_2_n_0 ),
.O(D[5]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[5]_i_2
(.I0(\Q_reg_n_0_[20] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg[22]_0 [3]),
.O(\Q[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[6]_i_1__7
(.I0(\Q[9]_i_2__0_n_0 ),
.I1(\Q[8]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[7]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[6]_i_2__0_n_0 ),
.O(D[6]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[6]_i_2__0
(.I0(\Q_reg_n_0_[19] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q_reg[22]_0 [4]),
.O(\Q[6]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[7]_i_1__5
(.I0(\Q[10]_i_2__0_n_0 ),
.I1(\Q[9]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[8]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[7]_i_2_n_0 ),
.O(D[7]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[7]_i_2
(.I0(\Q_reg_n_0_[18] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[7] ),
.I4(\Q_reg[22]_0 [5]),
.O(\Q[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[8]_i_1__6
(.I0(\Q[11]_i_2_n_0 ),
.I1(\Q[10]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[9]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[8]_i_2__0_n_0 ),
.O(D[8]));
LUT6 #(
.INIT(64'h00000000FFFF00AE))
\Q[8]_i_1__7
(.I0(\Q[8]_i_2_n_0 ),
.I1(\Q[8]_i_3_n_0 ),
.I2(\Q[8]_i_4_n_0 ),
.I3(\Q[8]_i_5_n_0 ),
.I4(\Q_reg_n_0_[24] ),
.I5(\Q_reg_n_0_[25] ),
.O(\Q_reg[12]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[8]_i_2
(.I0(\Q[8]_i_6_n_0 ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[8]_i_2__0
(.I0(\Q_reg_n_0_[17] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[8] ),
.I4(\Q_reg[22]_0 [6]),
.O(\Q[8]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF55045555))
\Q[8]_i_3
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg_n_0_[4] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q[8]_i_7_n_0 ),
.I5(\Q[8]_i_8_n_0 ),
.O(\Q[8]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT4 #(
.INIT(16'hFEFF))
\Q[8]_i_4
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[17] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q[8]_i_9_n_0 ),
.O(\Q[8]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT5 #(
.INIT(32'hBABBBABA))
\Q[8]_i_5
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[21] ),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg_n_0_[19] ),
.O(\Q[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT4 #(
.INIT(16'h00F2))
\Q[8]_i_6
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.I2(\Q_reg_n_0_[16] ),
.I3(\Q_reg_n_0_[17] ),
.O(\Q[8]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFFBABB))
\Q[8]_i_7
(.I0(\Q_reg_n_0_[5] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[1] ),
.I3(\Q_reg[12]_1 ),
.I4(\Q_reg_n_0_[3] ),
.O(\Q[8]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'hEFEE))
\Q[8]_i_8
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[10] ),
.O(\Q[8]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'hFF0B))
\Q[8]_i_9
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[9] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[8]_i_9_n_0 ));
LUT2 #(
.INIT(4'h1))
\Q[9]_i_10
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[11] ),
.O(\Q[9]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_11
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.O(\Q[9]_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[9]_i_1__6
(.I0(\Q[12]_i_2__0_n_0 ),
.I1(\Q[11]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[10]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[9]_i_2__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'h1111111110001010))
\Q[9]_i_1__7
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q[9]_i_2_n_0 ),
.I3(\Q[9]_i_3_n_0 ),
.I4(\Q[9]_i_4_n_0 ),
.I5(\Q[9]_i_5_n_0 ),
.O(\Q_reg[12]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_2
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg_n_0_[21] ),
.O(\Q[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[9]_i_2__0
(.I0(\Q_reg_n_0_[16] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[9] ),
.I4(\Q_reg[22]_0 [7]),
.O(\Q[9]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
\Q[9]_i_3
(.I0(\Q[9]_i_6_n_0 ),
.I1(\Q[9]_i_7_n_0 ),
.I2(\Q[9]_i_8_n_0 ),
.I3(\Q[9]_i_9_n_0 ),
.I4(\Q[9]_i_10_n_0 ),
.I5(\Q[9]_i_11_n_0 ),
.O(\Q[9]_i_3_n_0 ));
LUT2 #(
.INIT(4'h1))
\Q[9]_i_4
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg_n_0_[19] ),
.O(\Q[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'hE))
\Q[9]_i_5
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[23] ),
.O(\Q[9]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\Q[9]_i_6
(.I0(\Q_reg_n_0_[16] ),
.I1(\Q_reg_n_0_[17] ),
.O(\Q[9]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_7
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.O(\Q[9]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_8
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[9] ),
.O(\Q[9]_i_8_n_0 ));
LUT6 #(
.INIT(64'h1110111011101111))
\Q[9]_i_9
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg_n_0_[7] ),
.I2(\Q_reg_n_0_[4] ),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg_n_0_[2] ),
.I5(\Q_reg_n_0_[3] ),
.O(\Q[9]_i_9_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [0]),
.Q(\Q_reg[12]_1 ));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [13]),
.Q(\Q_reg_n_0_[13] ));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [14]),
.Q(\Q_reg_n_0_[14] ));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [15]),
.Q(\Q_reg_n_0_[15] ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [16]),
.Q(\Q_reg_n_0_[16] ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [17]),
.Q(\Q_reg_n_0_[17] ));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [18]),
.Q(\Q_reg_n_0_[18] ));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [19]),
.Q(\Q_reg_n_0_[19] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [20]),
.Q(\Q_reg_n_0_[20] ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [21]),
.Q(\Q_reg_n_0_[21] ));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [22]),
.Q(\Q_reg_n_0_[22] ));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [23]),
.Q(\Q_reg_n_0_[23] ));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [24]),
.Q(\Q_reg_n_0_[24] ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [25]),
.Q(\Q_reg_n_0_[25] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [2]),
.Q(\Q_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [4]),
.Q(\Q_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [5]),
.Q(\Q_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [6]),
.Q(\Q_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [9]),
.Q(\Q_reg_n_0_[9] ));
endmodule |
module RegisterAdd__parameterized19
(Q,
\Q_reg[2]_0 ,
\Q_reg[30] ,
CLK,
AR);
output [7:0]Q;
input [0:0]\Q_reg[2]_0 ;
input [7:0]\Q_reg[30] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [7:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [7:0]\Q_reg[30] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [7]),
.Q(Q[7]));
endmodule |
module RegisterAdd__parameterized2
(D,
Q,
\Q_reg[27]_0 ,
\Q_reg[6]_0 ,
\Q_reg[27]_1 ,
CLK,
AR);
output [2:0]D;
output [25:0]Q;
input [4:0]\Q_reg[27]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [27:0]\Q_reg[27]_1 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [25:0]Q;
wire \Q[4]_i_2__0_n_0 ;
wire [4:0]\Q_reg[27]_0 ;
wire [27:0]\Q_reg[27]_1 ;
wire [0:0]\Q_reg[6]_0 ;
wire \Q_reg_n_0_[26] ;
wire \Q_reg_n_0_[27] ;
LUT4 #(
.INIT(16'h2DD2))
\Q[1]_i_1__11
(.I0(Q[23]),
.I1(\Q_reg[27]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[27]_0 [1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h69))
\Q[3]_i_1__8
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg_n_0_[26] ),
.I2(\Q_reg[27]_0 [3]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'h718E8E71))
\Q[4]_i_1__9
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg[27]_0 [3]),
.I2(\Q_reg_n_0_[26] ),
.I3(\Q_reg_n_0_[27] ),
.I4(\Q_reg[27]_0 [4]),
.O(D[2]));
LUT6 #(
.INIT(64'hD4DD4444DDDDD4DD))
\Q[4]_i_2__0
(.I0(Q[25]),
.I1(\Q_reg[27]_0 [2]),
.I2(\Q_reg[27]_0 [0]),
.I3(Q[23]),
.I4(\Q_reg[27]_0 [1]),
.I5(Q[24]),
.O(\Q[4]_i_2__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [26]),
.Q(\Q_reg_n_0_[26] ));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [27]),
.Q(\Q_reg_n_0_[27] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [9]),
.Q(Q[9]));
endmodule |
module RegisterAdd__parameterized20
(D,
Q,
\Q_reg[25] ,
\Q_reg[25]_0 ,
\Q_reg[22] ,
\Q_reg[2]_0 ,
\Q_reg[2]_1 ,
\Q_reg[0]_0 ,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
CLK,
AR);
output [0:0]D;
output [2:0]Q;
output \Q_reg[25] ;
output [0:0]\Q_reg[25]_0 ;
input [1:0]\Q_reg[22] ;
input [1:0]\Q_reg[2]_0 ;
input [1:0]\Q_reg[2]_1 ;
input [0:0]\Q_reg[0]_0 ;
input \Q_reg[1]_0 ;
input [2:0]\Q_reg[1]_1 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[1]_0 ;
wire [2:0]\Q_reg[1]_1 ;
wire [1:0]\Q_reg[22] ;
wire \Q_reg[25] ;
wire [0:0]\Q_reg[25]_0 ;
wire [1:0]\Q_reg[2]_0 ;
wire [1:0]\Q_reg[2]_1 ;
LUT5 #(
.INIT(32'h000088FB))
\Q[25]_i_2
(.I0(Q[2]),
.I1(\Q_reg[2]_0 [0]),
.I2(\Q_reg[0]_0 ),
.I3(\Q_reg[25] ),
.I4(\Q_reg[1]_0 ),
.O(\Q_reg[25]_0 ));
LUT4 #(
.INIT(16'hEEF0))
\Q[25]_i_3
(.I0(Q[2]),
.I1(\Q_reg[22] [0]),
.I2(\Q_reg[2]_1 [0]),
.I3(\Q_reg[2]_0 [0]),
.O(\Q_reg[25] ));
LUT4 #(
.INIT(16'h4F40))
\Q[2]_i_1__6
(.I0(Q[2]),
.I1(\Q_reg[22] [1]),
.I2(\Q_reg[2]_0 [0]),
.I3(\Q_reg[2]_1 [1]),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_1 [2]),
.Q(Q[2]));
endmodule |
module RegisterAdd__parameterized21
(overflow_flag,
Q,
OVRFLW_FLAG_FRMT,
CLK,
AR,
UNDRFLW_FLAG_FRMT,
\Q_reg[0]_0 );
output [2:0]overflow_flag;
input [0:0]Q;
input OVRFLW_FLAG_FRMT;
input CLK;
input [1:0]AR;
input UNDRFLW_FLAG_FRMT;
input [0:0]\Q_reg[0]_0 ;
wire [1:0]AR;
wire CLK;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire [0:0]\Q_reg[0]_0 ;
wire UNDRFLW_FLAG_FRMT;
wire [2:0]overflow_flag;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(\Q_reg[0]_0 ),
.Q(overflow_flag[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(UNDRFLW_FLAG_FRMT),
.Q(overflow_flag[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(OVRFLW_FLAG_FRMT),
.Q(overflow_flag[2]));
endmodule |
module RegisterAdd__parameterized22
(ready_add_subt,
Q,
CLK,
AR);
output ready_add_subt;
input [0:0]Q;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]Q;
wire ready_add_subt;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(Q),
.Q(ready_add_subt));
endmodule |
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