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module pcie_128_if #(
parameter TCQ = 100
)(
input rst_n_250,
input rst_n_500,
output [6:0] trn_rbar_hit_n_o,
output [127:0] trn_rd_o,
output trn_recrc_err_n_o,
output trn_rsof_n_o,
output trn_reof_n_o,
output trn_rerrfwd_n_o,
output [1:0] trn_rrem_n_o,
output trn_rsrc_dsc_n_o,
output trn_rsrc_rdy_n_o,
input trn_rdst_rdy_n_i,
input trn_rnpok_n_i,
output [5:0] trn_tbuf_av_o,
output trn_tdst_rdy_n_o,
output trn_terr_drop_n_o,
input [127:0] trn_td_i,
input trn_tecrc_gen_n_i,
input trn_terr_fwd_n_i,
input [1:0] trn_trem_n_i,
input trn_tsof_n_i,
input trn_teof_n_i,
input trn_tsrc_dsc_n_i,
input trn_tsrc_rdy_n_i,
input trn_tstr_n_i,
output [11:0] trn_fc_cpld_o,
output [7:0] trn_fc_cplh_o,
output [11:0] trn_fc_npd_o,
output [7:0] trn_fc_nph_o,
output [11:0] trn_fc_pd_o,
output [7:0] trn_fc_ph_o,
input [2:0] trn_fc_sel_i,
input [6:0] TRNRBARHITN_i,
input [63:0] TRNRD_i,
input TRNRECRCERRN_i,
input TRNRSOFN_i,
input TRNREOFN_i,
input TRNRERRFWDN_i,
input TRNRREMN_i,
input TRNRSRCDSCN_i,
input TRNRSRCRDYN_i,
output TRNRDSTRDYN_o,
output TRNRNPOKN_o,
input [5:0] TRNTBUFAV_i,
input TRNTCFGREQN_i,
input TRNTDSTRDYN_i,
input TRNTERRDROPN_i,
output TRNTCFGGNTN_o,
output [63:0] TRNTD_o,
output TRNTECRCGENN_o,
output TRNTERRFWDN_o,
output TRNTREMN_o,
output TRNTSOFN_o,
output TRNTEOFN_o,
output TRNTSRCDSCN_o,
output TRNTSRCRDYN_o,
output TRNTSTRN_o,
input [11:0] TRNFCCPLD_i,
input [7:0] TRNFCCPLH_i,
input [11:0] TRNFCNPD_i,
input [7:0] TRNFCNPH_i,
input [11:0] TRNFCPD_i,
input [7:0] TRNFCPH_i,
output [2:0] TRNFCSEL_o,
//--------------------------------------
input BLOCKCLK,
input USERCLK,
input CFGCOMMANDBUSMASTERENABLE_i,
input CFGCOMMANDINTERRUPTDISABLE_i,
input CFGCOMMANDIOENABLE_i,
input CFGCOMMANDMEMENABLE_i,
input CFGCOMMANDSERREN_i,
input CFGDEVCONTROLAUXPOWEREN_i,
input CFGDEVCONTROLCORRERRREPORTINGEN_i,
input CFGDEVCONTROLENABLERO_i,
input CFGDEVCONTROLEXTTAGEN_i,
input CFGDEVCONTROLFATALERRREPORTINGEN_i,
input [2:0] CFGDEVCONTROLMAXPAYLOAD_i,
input [2:0] CFGDEVCONTROLMAXREADREQ_i,
input CFGDEVCONTROLNONFATALREPORTINGEN_i,
input CFGDEVCONTROLNOSNOOPEN_i,
input CFGDEVCONTROLPHANTOMEN_i,
input CFGDEVCONTROLURERRREPORTINGEN_i,
input CFGDEVCONTROL2CPLTIMEOUTDIS_i,
input [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL_i,
input CFGDEVSTATUSCORRERRDETECTED_i,
input CFGDEVSTATUSFATALERRDETECTED_i,
input CFGDEVSTATUSNONFATALERRDETECTED_i,
input CFGDEVSTATUSURDETECTED_i,
input [31:0] CFGDO_i,
input CFGERRCPLRDYN_i,
input [7:0] CFGINTERRUPTDO_i,
input [2:0] CFGINTERRUPTMMENABLE_i,
input CFGINTERRUPTMSIENABLE_i,
input CFGINTERRUPTMSIXENABLE_i,
input CFGINTERRUPTMSIXFM_i,
input CFGINTERRUPTRDYN_i,
input CFGLINKCONTROLRCB_i,
input [1:0] CFGLINKCONTROLASPMCONTROL_i,
input CFGLINKCONTROLAUTOBANDWIDTHINTEN_i,
input CFGLINKCONTROLBANDWIDTHINTEN_i,
input CFGLINKCONTROLCLOCKPMEN_i,
input CFGLINKCONTROLCOMMONCLOCK_i,
input CFGLINKCONTROLEXTENDEDSYNC_i,
input CFGLINKCONTROLHWAUTOWIDTHDIS_i,
input CFGLINKCONTROLLINKDISABLE_i,
input CFGLINKCONTROLRETRAINLINK_i,
input CFGLINKSTATUSAUTOBANDWIDTHSTATUS_i,
input CFGLINKSTATUSBANDWITHSTATUS_i,
input [1:0] CFGLINKSTATUSCURRENTSPEED_i,
input CFGLINKSTATUSDLLACTIVE_i,
input CFGLINKSTATUSLINKTRAINING_i,
input [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH_i,
input [15:0] CFGMSGDATA_i,
input CFGMSGRECEIVED_i,
input CFGMSGRECEIVEDPMETO_i,
input [2:0] CFGPCIELINKSTATE_i,
input CFGPMCSRPMEEN_i,
input CFGPMCSRPMESTATUS_i,
input [1:0] CFGPMCSRPOWERSTATE_i,
input CFGRDWRDONEN_i,
input CFGMSGRECEIVEDSETSLOTPOWERLIMIT_i,
input CFGMSGRECEIVEDUNLOCK_i,
input CFGMSGRECEIVEDPMASNAK_i,
input CFGPMRCVREQACKN_i,
input CFGTRANSACTION_i,
input [6:0] CFGTRANSACTIONADDR_i,
input CFGTRANSACTIONTYPE_i,
output [3:0] CFGBYTEENN_o,
output [31:0] CFGDI_o,
output [63:0] CFGDSN_o,
output [9:0] CFGDWADDR_o,
output CFGERRACSN_o,
output CFGERRCORN_o,
output CFGERRCPLABORTN_o,
output CFGERRCPLTIMEOUTN_o,
output CFGERRCPLUNEXPECTN_o,
output CFGERRECRCN_o,
output CFGERRLOCKEDN_o,
output CFGERRPOSTEDN_o,
output [47:0] CFGERRTLPCPLHEADER_o,
output CFGERRURN_o,
output CFGINTERRUPTASSERTN_o,
output [7:0] CFGINTERRUPTDI_o,
output CFGINTERRUPTN_o,
output CFGPMDIRECTASPML1N_o,
output CFGPMSENDPMACKN_o,
output CFGPMSENDPMETON_o,
output CFGPMSENDPMNAKN_o,
output CFGPMTURNOFFOKN_o,
output CFGPMWAKEN_o,
output [7:0] CFGPORTNUMBER_o,
output CFGRDENN_o,
output CFGTRNPENDINGN_o,
output CFGWRENN_o,
output CFGWRREADONLYN_o,
output CFGWRRW1CASRWN_o,
//--------------------------------------------------------
output CFGCOMMANDBUSMASTERENABLE_o,
output CFGCOMMANDINTERRUPTDISABLE_o,
output CFGCOMMANDIOENABLE_o,
output CFGCOMMANDMEMENABLE_o,
output CFGCOMMANDSERREN_o,
output CFGDEVCONTROLAUXPOWEREN_o,
output CFGDEVCONTROLCORRERRREPORTINGEN_o,
output CFGDEVCONTROLENABLERO_o,
output CFGDEVCONTROLEXTTAGEN_o,
output CFGDEVCONTROLFATALERRREPORTINGEN_o,
output [2:0] CFGDEVCONTROLMAXPAYLOAD_o,
output [2:0] CFGDEVCONTROLMAXREADREQ_o,
output CFGDEVCONTROLNONFATALREPORTINGEN_o,
output CFGDEVCONTROLNOSNOOPEN_o,
output CFGDEVCONTROLPHANTOMEN_o,
output CFGDEVCONTROLURERRREPORTINGEN_o,
output CFGDEVCONTROL2CPLTIMEOUTDIS_o,
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL_o,
output CFGDEVSTATUSCORRERRDETECTED_o,
output CFGDEVSTATUSFATALERRDETECTED_o,
output CFGDEVSTATUSNONFATALERRDETECTED_o,
output CFGDEVSTATUSURDETECTED_o,
output [31:0] CFGDO_o,
output CFGERRCPLRDYN_o,
output [7:0] CFGINTERRUPTDO_o,
output [2:0] CFGINTERRUPTMMENABLE_o,
output CFGINTERRUPTMSIENABLE_o,
output CFGINTERRUPTMSIXENABLE_o,
output CFGINTERRUPTMSIXFM_o,
output CFGINTERRUPTRDYN_o,
output CFGLINKCONTROLRCB_o,
output [1:0] CFGLINKCONTROLASPMCONTROL_o,
output CFGLINKCONTROLAUTOBANDWIDTHINTEN_o,
output CFGLINKCONTROLBANDWIDTHINTEN_o,
output CFGLINKCONTROLCLOCKPMEN_o,
output CFGLINKCONTROLCOMMONCLOCK_o,
output CFGLINKCONTROLEXTENDEDSYNC_o,
output CFGLINKCONTROLHWAUTOWIDTHDIS_o,
output CFGLINKCONTROLLINKDISABLE_o,
output CFGLINKCONTROLRETRAINLINK_o,
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS_o,
output CFGLINKSTATUSBANDWITHSTATUS_o,
output [1:0] CFGLINKSTATUSCURRENTSPEED_o,
output CFGLINKSTATUSDLLACTIVE_o,
output CFGLINKSTATUSLINKTRAINING_o,
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH_o,
output [15:0] CFGMSGDATA_o,
output CFGMSGRECEIVED_o,
output CFGMSGRECEIVEDPMETO_o,
output [2:0] CFGPCIELINKSTATE_o,
output CFGPMCSRPMEEN_o,
output CFGPMCSRPMESTATUS_o,
output [1:0] CFGPMCSRPOWERSTATE_o,
output CFGRDWRDONEN_o,
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT_o,
output CFGMSGRECEIVEDUNLOCK_o,
output CFGMSGRECEIVEDPMASNAK_o,
output CFGPMRCVREQACKN_o,
output CFGTRANSACTION_o,
output [6:0] CFGTRANSACTIONADDR_o,
output CFGTRANSACTIONTYPE_o,
input [3:0] CFGBYTEENN_i,
input [31:0] CFGDI_i,
input [63:0] CFGDSN_i,
input [9:0] CFGDWADDR_i,
input CFGERRACSN_i,
input CFGERRCORN_i,
input CFGERRCPLABORTN_i,
input CFGERRCPLTIMEOUTN_i,
input CFGERRCPLUNEXPECTN_i,
input CFGERRECRCN_i,
input CFGERRLOCKEDN_i,
input CFGERRPOSTEDN_i,
input [47:0] CFGERRTLPCPLHEADER_i,
input CFGERRURN_i,
input CFGINTERRUPTASSERTN_i,
input [7:0] CFGINTERRUPTDI_i,
input CFGINTERRUPTN_i,
input CFGPMDIRECTASPML1N_i,
input CFGPMSENDPMACKN_i,
input CFGPMSENDPMETON_i,
input CFGPMSENDPMNAKN_i,
input CFGPMTURNOFFOKN_i,
input CFGPMWAKEN_i,
input [7:0] CFGPORTNUMBER_i,
input CFGRDENN_i,
input CFGTRNPENDINGN_i,
input CFGWRENN_i,
input CFGWRREADONLYN_i,
input CFGWRRW1CASRWN_i
);
pcie_trn_128 #(
.TCQ ( TCQ )
) pcie_trn_128_i (
.user_clk ( USERCLK ),
.block_clk ( BLOCKCLK ),
.rst_n_250 ( rst_n_250 ),
.rst_n_500 ( rst_n_500 ),
`ifdef SILICON_1_0
.cfgpmcsrpowerstate ( 2'h0 ),
`else
.cfgpmcsrpowerstate ( CFGPMCSRPOWERSTATE_o ),
`endif
//////////////////
// to/from user //
//////////////////
.trn_rbar_hit_n_o( trn_rbar_hit_n_o ),
.trn_rd_o( trn_rd_o ),
.trn_recrc_err_n_o( trn_recrc_err_n_o ),
.trn_rsof_n_o( trn_rsof_n_o ),
.trn_reof_n_o( trn_reof_n_o ),
.trn_rerrfwd_n_o( trn_rerrfwd_n_o ),
.trn_rrem_n_o( trn_rrem_n_o ),
.trn_rsrc_dsc_n_o( trn_rsrc_dsc_n_o ),
.trn_rsrc_rdy_n_o( trn_rsrc_rdy_n_o ),
.trn_rdst_rdy_n_i( trn_rdst_rdy_n_i ),
.trn_rnpok_n_i( trn_rnpok_n_i ),
.trn_tbuf_av_o( trn_tbuf_av_o ),
.trn_tdst_rdy_n_o( trn_tdst_rdy_n_o ),
.trn_terr_drop_n_o( trn_terr_drop_n_o ),
.trn_td_i( trn_td_i ),
.trn_tecrc_gen_n_i( trn_tecrc_gen_n_i ),
.trn_terr_fwd_n_i( trn_terr_fwd_n_i ),
.trn_trem_n_i( trn_trem_n_i ),
.trn_tsof_n_i( trn_tsof_n_i ),
.trn_teof_n_i( trn_teof_n_i ),
.trn_tsrc_dsc_n_i( trn_tsrc_dsc_n_i ),
.trn_tsrc_rdy_n_i( trn_tsrc_rdy_n_i ),
.trn_tstr_n_i( trn_tstr_n_i ),
.trn_fc_cpld_o( trn_fc_cpld_o ),
.trn_fc_cplh_o( trn_fc_cplh_o ),
.trn_fc_npd_o( trn_fc_npd_o ),
.trn_fc_nph_o( trn_fc_nph_o ),
.trn_fc_pd_o( trn_fc_pd_o ),
.trn_fc_ph_o( trn_fc_ph_o ),
.trn_fc_sel_i( trn_fc_sel_i ),
////////////////
// to/from EP //
////////////////
.TRNRBARHITN_i( TRNRBARHITN_i ),
.TRNRD_i( TRNRD_i ),
.TRNRECRCERRN_i( TRNRECRCERRN_i ),
.TRNRSOFN_i( TRNRSOFN_i ),
.TRNREOFN_i( TRNREOFN_i ),
.TRNRERRFWDN_i( TRNRERRFWDN_i ),
.TRNRREMN_i( TRNRREMN_i ),
.TRNRSRCDSCN_i( TRNRSRCDSCN_i ),
.TRNRSRCRDYN_i( TRNRSRCRDYN_i ),
.TRNRDSTRDYN_o( TRNRDSTRDYN_o ),
.TRNRNPOKN_o( TRNRNPOKN_o ),
.TRNTBUFAV_i( TRNTBUFAV_i ),
.TRNTCFGREQN_i( TRNTCFGREQN_i ),
.TRNTDSTRDYN_i( TRNTDSTRDYN_i ),
.TRNTERRDROPN_i( TRNTERRDROPN_i ),
.TRNTCFGGNTN_o( TRNTCFGGNTN_o ),
.TRNTD_o( TRNTD_o ),
.TRNTECRCGENN_o( TRNTECRCGENN_o ),
.TRNTERRFWDN_o( TRNTERRFWDN_o ),
.TRNTREMN_o( TRNTREMN_o ),
.TRNTSOFN_o( TRNTSOFN_o ),
.TRNTEOFN_o( TRNTEOFN_o ),
.TRNTSRCDSCN_o( TRNTSRCDSCN_o ),
.TRNTSRCRDYN_o( TRNTSRCRDYN_o ),
.TRNTSTRN_o( TRNTSTRN_o ),
.TRNFCCPLD_i( TRNFCCPLD_i ),
.TRNFCCPLH_i( TRNFCCPLH_i ),
.TRNFCNPD_i( TRNFCNPD_i ),
.TRNFCNPH_i( TRNFCNPH_i ),
.TRNFCPD_i( TRNFCPD_i ),
.TRNFCPH_i( TRNFCPH_i ),
.TRNFCSEL_o( TRNFCSEL_o )
);
pcie_cfg_128 #(
.TCQ( TCQ )
) pcie_cfg_128_i (
.user_clk ( USERCLK ),
.block_clk ( BLOCKCLK ),
.rst_n_500 ( rst_n_500 ),
.CFGCOMMANDBUSMASTERENABLE_i( CFGCOMMANDBUSMASTERENABLE_i ),
.CFGCOMMANDINTERRUPTDISABLE_i( CFGCOMMANDINTERRUPTDISABLE_i ),
.CFGCOMMANDIOENABLE_i( CFGCOMMANDIOENABLE_i ),
.CFGCOMMANDMEMENABLE_i( CFGCOMMANDMEMENABLE_i ),
.CFGCOMMANDSERREN_i( CFGCOMMANDSERREN_i ),
.CFGDEVCONTROLAUXPOWEREN_i( CFGDEVCONTROLAUXPOWEREN_i ),
.CFGDEVCONTROLCORRERRREPORTINGEN_i( CFGDEVCONTROLCORRERRREPORTINGEN_i ),
.CFGDEVCONTROLENABLERO_i( CFGDEVCONTROLENABLERO_i ),
.CFGDEVCONTROLEXTTAGEN_i( CFGDEVCONTROLEXTTAGEN_i ),
.CFGDEVCONTROLFATALERRREPORTINGEN_i( CFGDEVCONTROLFATALERRREPORTINGEN_i ),
.CFGDEVCONTROLMAXPAYLOAD_i( CFGDEVCONTROLMAXPAYLOAD_i ),
.CFGDEVCONTROLMAXREADREQ_i( CFGDEVCONTROLMAXREADREQ_i ),
.CFGDEVCONTROLNONFATALREPORTINGEN_i( CFGDEVCONTROLNONFATALREPORTINGEN_i ),
.CFGDEVCONTROLNOSNOOPEN_i( CFGDEVCONTROLNOSNOOPEN_i ),
.CFGDEVCONTROLPHANTOMEN_i( CFGDEVCONTROLPHANTOMEN_i ),
.CFGDEVCONTROLURERRREPORTINGEN_i( CFGDEVCONTROLURERRREPORTINGEN_i ),
.CFGDEVCONTROL2CPLTIMEOUTDIS_i( CFGDEVCONTROL2CPLTIMEOUTDIS_i ),
.CFGDEVCONTROL2CPLTIMEOUTVAL_i( CFGDEVCONTROL2CPLTIMEOUTVAL_i ),
.CFGDEVSTATUSCORRERRDETECTED_i( CFGDEVSTATUSCORRERRDETECTED_i ),
.CFGDEVSTATUSFATALERRDETECTED_i( CFGDEVSTATUSFATALERRDETECTED_i ),
.CFGDEVSTATUSNONFATALERRDETECTED_i( CFGDEVSTATUSNONFATALERRDETECTED_i ),
.CFGDEVSTATUSURDETECTED_i( CFGDEVSTATUSURDETECTED_i ),
.CFGDO_i( CFGDO_i ),
.CFGERRCPLRDYN_i( CFGERRCPLRDYN_i ),
.CFGINTERRUPTDO_i( CFGINTERRUPTDO_i ),
.CFGINTERRUPTMMENABLE_i( CFGINTERRUPTMMENABLE_i ),
.CFGINTERRUPTMSIENABLE_i( CFGINTERRUPTMSIENABLE_i ),
.CFGINTERRUPTMSIXENABLE_i( CFGINTERRUPTMSIXENABLE_i ),
.CFGINTERRUPTMSIXFM_i( CFGINTERRUPTMSIXFM_i ),
.CFGINTERRUPTRDYN_i( CFGINTERRUPTRDYN_i ),
.CFGLINKCONTROLRCB_i( CFGLINKCONTROLRCB_i ),
.CFGLINKCONTROLASPMCONTROL_i( CFGLINKCONTROLASPMCONTROL_i ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN_i( CFGLINKCONTROLAUTOBANDWIDTHINTEN_i ),
.CFGLINKCONTROLBANDWIDTHINTEN_i( CFGLINKCONTROLBANDWIDTHINTEN_i ),
.CFGLINKCONTROLCLOCKPMEN_i( CFGLINKCONTROLCLOCKPMEN_i ),
.CFGLINKCONTROLCOMMONCLOCK_i( CFGLINKCONTROLCOMMONCLOCK_i ),
.CFGLINKCONTROLEXTENDEDSYNC_i( CFGLINKCONTROLEXTENDEDSYNC_i ),
.CFGLINKCONTROLHWAUTOWIDTHDIS_i( CFGLINKCONTROLHWAUTOWIDTHDIS_i ),
.CFGLINKCONTROLLINKDISABLE_i( CFGLINKCONTROLLINKDISABLE_i ),
.CFGLINKCONTROLRETRAINLINK_i( CFGLINKCONTROLRETRAINLINK_i ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS_i( CFGLINKSTATUSAUTOBANDWIDTHSTATUS_i ),
.CFGLINKSTATUSBANDWITHSTATUS_i( CFGLINKSTATUSBANDWITHSTATUS_i ),
.CFGLINKSTATUSCURRENTSPEED_i( CFGLINKSTATUSCURRENTSPEED_i ),
.CFGLINKSTATUSDLLACTIVE_i( CFGLINKSTATUSDLLACTIVE_i ),
.CFGLINKSTATUSLINKTRAINING_i( CFGLINKSTATUSLINKTRAINING_i ),
.CFGLINKSTATUSNEGOTIATEDWIDTH_i( CFGLINKSTATUSNEGOTIATEDWIDTH_i ),
.CFGMSGDATA_i( CFGMSGDATA_i ),
.CFGMSGRECEIVED_i( CFGMSGRECEIVED_i ),
.CFGMSGRECEIVEDPMETO_i( CFGMSGRECEIVEDPMETO_i ),
.CFGPCIELINKSTATE_i( CFGPCIELINKSTATE_i ),
.CFGPMCSRPMEEN_i( CFGPMCSRPMEEN_i ),
.CFGPMCSRPMESTATUS_i( CFGPMCSRPMESTATUS_i ),
.CFGPMCSRPOWERSTATE_i( CFGPMCSRPOWERSTATE_i ),
.CFGRDWRDONEN_i( CFGRDWRDONEN_i ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT_i( CFGMSGRECEIVEDSETSLOTPOWERLIMIT_i ),
.CFGMSGRECEIVEDUNLOCK_i( CFGMSGRECEIVEDUNLOCK_i ),
.CFGMSGRECEIVEDPMASNAK_i( CFGMSGRECEIVEDPMASNAK_i ),
.CFGPMRCVREQACKN_i( CFGPMRCVREQACKN_i ),
.CFGTRANSACTION_i( CFGTRANSACTION_i ),
.CFGTRANSACTIONADDR_i( CFGTRANSACTIONADDR_i ),
.CFGTRANSACTIONTYPE_i( CFGTRANSACTIONTYPE_i ),
.CFGBYTEENN_o( CFGBYTEENN_o ),
.CFGDI_o( CFGDI_o ),
.CFGDSN_o( CFGDSN_o ),
.CFGDWADDR_o( CFGDWADDR_o ),
.CFGERRACSN_o( CFGERRACSN_o ),
.CFGERRCORN_o( CFGERRCORN_o ),
.CFGERRCPLABORTN_o( CFGERRCPLABORTN_o ),
.CFGERRCPLTIMEOUTN_o( CFGERRCPLTIMEOUTN_o ),
.CFGERRCPLUNEXPECTN_o( CFGERRCPLUNEXPECTN_o ),
.CFGERRECRCN_o( CFGERRECRCN_o ),
.CFGERRLOCKEDN_o( CFGERRLOCKEDN_o ),
.CFGERRPOSTEDN_o( CFGERRPOSTEDN_o ),
.CFGERRTLPCPLHEADER_o( CFGERRTLPCPLHEADER_o ),
.CFGERRURN_o( CFGERRURN_o ),
.CFGINTERRUPTASSERTN_o( CFGINTERRUPTASSERTN_o ),
.CFGINTERRUPTDI_o( CFGINTERRUPTDI_o ),
.CFGINTERRUPTN_o( CFGINTERRUPTN_o ),
.CFGPMDIRECTASPML1N_o( CFGPMDIRECTASPML1N_o ),
.CFGPMSENDPMACKN_o( CFGPMSENDPMACKN_o ),
.CFGPMSENDPMETON_o( CFGPMSENDPMETON_o ),
.CFGPMSENDPMNAKN_o( CFGPMSENDPMNAKN_o ),
.CFGPMTURNOFFOKN_o( CFGPMTURNOFFOKN_o ),
.CFGPMWAKEN_o( CFGPMWAKEN_o ),
.CFGPORTNUMBER_o( CFGPORTNUMBER_o ),
.CFGRDENN_o( CFGRDENN_o ),
.CFGTRNPENDINGN_o( CFGTRNPENDINGN_o ),
.CFGWRENN_o( CFGWRENN_o ),
.CFGWRREADONLYN_o( CFGWRREADONLYN_o ),
.CFGWRRW1CASRWN_o( CFGWRRW1CASRWN_o ),
//------------------
.CFGCOMMANDBUSMASTERENABLE_o( CFGCOMMANDBUSMASTERENABLE_o ),
.CFGCOMMANDINTERRUPTDISABLE_o( CFGCOMMANDINTERRUPTDISABLE_o ),
.CFGCOMMANDIOENABLE_o( CFGCOMMANDIOENABLE_o ),
.CFGCOMMANDMEMENABLE_o( CFGCOMMANDMEMENABLE_o ),
.CFGCOMMANDSERREN_o( CFGCOMMANDSERREN_o ),
.CFGDEVCONTROLAUXPOWEREN_o( CFGDEVCONTROLAUXPOWEREN_o ),
.CFGDEVCONTROLCORRERRREPORTINGEN_o( CFGDEVCONTROLCORRERRREPORTINGEN_o ),
.CFGDEVCONTROLENABLERO_o( CFGDEVCONTROLENABLERO_o ),
.CFGDEVCONTROLEXTTAGEN_o( CFGDEVCONTROLEXTTAGEN_o ),
.CFGDEVCONTROLFATALERRREPORTINGEN_o( CFGDEVCONTROLFATALERRREPORTINGEN_o ),
.CFGDEVCONTROLMAXPAYLOAD_o( CFGDEVCONTROLMAXPAYLOAD_o ),
.CFGDEVCONTROLMAXREADREQ_o( CFGDEVCONTROLMAXREADREQ_o ),
.CFGDEVCONTROLNONFATALREPORTINGEN_o( CFGDEVCONTROLNONFATALREPORTINGEN_o ),
.CFGDEVCONTROLNOSNOOPEN_o( CFGDEVCONTROLNOSNOOPEN_o ),
.CFGDEVCONTROLPHANTOMEN_o( CFGDEVCONTROLPHANTOMEN_o ),
.CFGDEVCONTROLURERRREPORTINGEN_o( CFGDEVCONTROLURERRREPORTINGEN_o ),
.CFGDEVCONTROL2CPLTIMEOUTDIS_o( CFGDEVCONTROL2CPLTIMEOUTDIS_o ),
.CFGDEVCONTROL2CPLTIMEOUTVAL_o( CFGDEVCONTROL2CPLTIMEOUTVAL_o ),
.CFGDEVSTATUSCORRERRDETECTED_o( CFGDEVSTATUSCORRERRDETECTED_o ),
.CFGDEVSTATUSFATALERRDETECTED_o( CFGDEVSTATUSFATALERRDETECTED_o ),
.CFGDEVSTATUSNONFATALERRDETECTED_o( CFGDEVSTATUSNONFATALERRDETECTED_o ),
.CFGDEVSTATUSURDETECTED_o( CFGDEVSTATUSURDETECTED_o ),
.CFGDO_o( CFGDO_o ),
.CFGERRCPLRDYN_o( CFGERRCPLRDYN_o ),
.CFGINTERRUPTDO_o( CFGINTERRUPTDO_o ),
.CFGINTERRUPTMMENABLE_o( CFGINTERRUPTMMENABLE_o ),
.CFGINTERRUPTMSIENABLE_o( CFGINTERRUPTMSIENABLE_o ),
.CFGINTERRUPTMSIXENABLE_o( CFGINTERRUPTMSIXENABLE_o ),
.CFGINTERRUPTMSIXFM_o( CFGINTERRUPTMSIXFM_o ),
.CFGINTERRUPTRDYN_o( CFGINTERRUPTRDYN_o ),
.CFGLINKCONTROLRCB_o( CFGLINKCONTROLRCB_o ),
.CFGLINKCONTROLASPMCONTROL_o( CFGLINKCONTROLASPMCONTROL_o ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN_o( CFGLINKCONTROLAUTOBANDWIDTHINTEN_o ),
.CFGLINKCONTROLBANDWIDTHINTEN_o( CFGLINKCONTROLBANDWIDTHINTEN_o ),
.CFGLINKCONTROLCLOCKPMEN_o( CFGLINKCONTROLCLOCKPMEN_o ),
.CFGLINKCONTROLCOMMONCLOCK_o( CFGLINKCONTROLCOMMONCLOCK_o ),
.CFGLINKCONTROLEXTENDEDSYNC_o( CFGLINKCONTROLEXTENDEDSYNC_o ),
.CFGLINKCONTROLHWAUTOWIDTHDIS_o( CFGLINKCONTROLHWAUTOWIDTHDIS_o ),
.CFGLINKCONTROLLINKDISABLE_o( CFGLINKCONTROLLINKDISABLE_o ),
.CFGLINKCONTROLRETRAINLINK_o( CFGLINKCONTROLRETRAINLINK_o ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS_o( CFGLINKSTATUSAUTOBANDWIDTHSTATUS_o ),
.CFGLINKSTATUSBANDWITHSTATUS_o( CFGLINKSTATUSBANDWITHSTATUS_o ),
.CFGLINKSTATUSCURRENTSPEED_o( CFGLINKSTATUSCURRENTSPEED_o ),
.CFGLINKSTATUSDLLACTIVE_o( CFGLINKSTATUSDLLACTIVE_o ),
.CFGLINKSTATUSLINKTRAINING_o( CFGLINKSTATUSLINKTRAINING_o ),
.CFGLINKSTATUSNEGOTIATEDWIDTH_o( CFGLINKSTATUSNEGOTIATEDWIDTH_o ),
.CFGMSGDATA_o( CFGMSGDATA_o ),
.CFGMSGRECEIVED_o( CFGMSGRECEIVED_o ),
.CFGMSGRECEIVEDPMETO_o( CFGMSGRECEIVEDPMETO_o ),
.CFGPCIELINKSTATE_o( CFGPCIELINKSTATE_o ),
.CFGPMCSRPMEEN_o( CFGPMCSRPMEEN_o ),
.CFGPMCSRPMESTATUS_o( CFGPMCSRPMESTATUS_o ),
.CFGPMCSRPOWERSTATE_o( CFGPMCSRPOWERSTATE_o ),
.CFGRDWRDONEN_o( CFGRDWRDONEN_o ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT_o( CFGMSGRECEIVEDSETSLOTPOWERLIMIT_o ),
.CFGMSGRECEIVEDUNLOCK_o( CFGMSGRECEIVEDUNLOCK_o ),
.CFGMSGRECEIVEDPMASNAK_o( CFGMSGRECEIVEDPMASNAK_o ),
.CFGPMRCVREQACKN_o( CFGPMRCVREQACKN_o ),
.CFGTRANSACTION_o( CFGTRANSACTION_o ),
.CFGTRANSACTIONADDR_o( CFGTRANSACTIONADDR_o ),
.CFGTRANSACTIONTYPE_o( CFGTRANSACTIONTYPE_o ),
.CFGBYTEENN_i( CFGBYTEENN_i ),
.CFGDI_i( CFGDI_i ),
.CFGDSN_i( CFGDSN_i ),
.CFGDWADDR_i( CFGDWADDR_i ),
.CFGERRACSN_i( CFGERRACSN_i ),
.CFGERRCORN_i( CFGERRCORN_i ),
.CFGERRCPLABORTN_i( CFGERRCPLABORTN_i ),
.CFGERRCPLTIMEOUTN_i( CFGERRCPLTIMEOUTN_i ),
.CFGERRCPLUNEXPECTN_i( CFGERRCPLUNEXPECTN_i ),
.CFGERRECRCN_i( CFGERRECRCN_i ),
.CFGERRLOCKEDN_i( CFGERRLOCKEDN_i ),
.CFGERRPOSTEDN_i( CFGERRPOSTEDN_i ),
.CFGERRTLPCPLHEADER_i( CFGERRTLPCPLHEADER_i ),
.CFGERRURN_i( CFGERRURN_i ),
.CFGINTERRUPTASSERTN_i( CFGINTERRUPTASSERTN_i ),
.CFGINTERRUPTDI_i( CFGINTERRUPTDI_i ),
.CFGINTERRUPTN_i( CFGINTERRUPTN_i ),
.CFGPMDIRECTASPML1N_i( CFGPMDIRECTASPML1N_i ),
.CFGPMSENDPMACKN_i( CFGPMSENDPMACKN_i ),
.CFGPMSENDPMETON_i( CFGPMSENDPMETON_i ),
.CFGPMSENDPMNAKN_i( CFGPMSENDPMNAKN_i ),
.CFGPMTURNOFFOKN_i( CFGPMTURNOFFOKN_i ),
.CFGPMWAKEN_i( CFGPMWAKEN_i ),
.CFGPORTNUMBER_i( CFGPORTNUMBER_i ),
.CFGRDENN_i( CFGRDENN_i ),
.CFGTRNPENDINGN_i( CFGTRNPENDINGN_i ),
.CFGWRENN_i( CFGWRENN_i ),
.CFGWRREADONLYN_i( CFGWRREADONLYN_i ),
.CFGWRRW1CASRWN_i( CFGWRRW1CASRWN_i )
);
endmodule |
module sky130_fd_sc_hdll__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_lp__inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module Sgf_Multiplication
#(parameter SW = 24)
//#(parameter SW = 54)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//wire [SW-1:0] Data_A_i;
//wire [SW-1:0] Data_B_i;
//wire [2*(SW/2)-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder;
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder;
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin : GEN1
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level1)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
multiplier #(.W(SW/2)/*,.level(level1)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right[2*(SW/2)-1:0])
);
// assign Q_left = Data_A_i[SW-1:SW-SW/2]*Data_B_i[SW-1:SW-SW/2];
// assign Q_right[2*(SW/2)-1:0] = Data_A_i[SW-SW/2-1:0]*Data_B_i[SW-SW/2-1:0];
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
//multiplication for middle
multiplier #(.W(SW/2+1)/*,.level(level1)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.Data_S_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
//assign Q_middle[2*(SW/2)+1:0] = result_A_adder[SW/2:0]*result_B_adder[SW/2:0];
//segmentation registers array
/*RegisterAdd #(.W(SW+2)) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult[2*(SW/2)+1:0]),
.Q(Q_middle[2*(SW/2)+1:0])
);//*/
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({{(2*SW-(SW+SW/2+2)){1'b0}},S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : GEN2
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level2)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(2*(SW/2))) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W((SW/2)+1)/*,.level(level2)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult*/Q_right)
);
/*RegisterAdd #(.W(2*((SW/2)+1))) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult),
.Q(Q_right)
);//*/
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//multiplication for middle
multiplier #(.W(SW/2+2)/*,.level(level2)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.Data_S_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule |
module setbit_tb;
//-- Cable para conectar al componente que pone
//-- el bit a uno
wire LED1;
//--Instanciar el componente. Conectado al cable A
setbit SB1 (
.LED1 (LED1)
);
//-- Comenzamos las pruebas
initial begin
//-- Definir el fichero donde volvar los datos
//-- para ver graficamente la salida
$dumpfile("T01-setbit_tb.vcd");
//-- Volcar todos los datos a ese fichero
$dumpvars(0, setbit_tb);
//-- Pasadas 10 unidades de tiempo comprobamos
//-- si el cable esta a 1
//-- En caso de no estar a 1, se informa del problema, pero la
//-- simulacion no se detiene
# 10 if (LED1 != 1)
$display("---->¡ERROR! Salida no esta a 1");
else
$display("Componente ok!");
//-- Terminar la simulacion 10 unidades de tiempo
//-- despues
# 10 $finish;
end
endmodule |
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_15"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_16"),
.ENUM_MEM_IF_TRC ("TRC_22"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_2"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (2800),
.INTG_MEM_IF_TRFC (30),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule |
module sh_dff(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C)
Q <= D;
endmodule |
module adder_carry(
output sumout,
output cout,
input p,
input g,
input cin
);
assign sumout = p ^ cin;
assign cout = p ? cin : g;
endmodule |
module adder_lut5(
output lut5_out,
(* abc9_carry *)
output cout,
input [0:4] in,
(* abc9_carry *)
input cin
);
parameter [0:15] LUT=0;
parameter IN2_IS_CIN = 0;
wire [0:4] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3], in[4]} : {in[0], in[1], in[2], in[3],in[4]};
// Output function
wire [0:15] s1 = li[0] ?
{LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14], LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30]}:
{LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15], LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31]};
wire [0:7] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6], s1[8], s1[10], s1[12], s1[14]} :
{s1[1], s1[3], s1[5], s1[7], s1[9], s1[11], s1[13], s1[15]};
wire [0:3] s3 = li[2] ? {s2[0], s2[2], s2[4], s2[6]} : {s2[1], s2[3], s2[5], s2[7]};
wire [0:1] s4 = li[3] ? {s3[0], s3[2]} : {s3[1], s3[3]};
assign lut5_out = li[4] ? s4[0] : s4[1];
// Carry out function
assign cout = (s3[2]) ? cin : s3[3];
endmodule |
module frac_lut6(
input [0:5] in,
output [0:3] lut4_out,
output [0:1] lut5_out,
output lut6_out
);
parameter [0:63] LUT = 0;
// Effective LUT input
wire [0:5] li = in;
// Output function
wire [0:31] s1 = li[0] ?
{LUT[0] , LUT[2] , LUT[4] , LUT[6] , LUT[8] , LUT[10], LUT[12], LUT[14],
LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30],
LUT[32], LUT[34], LUT[36], LUT[38], LUT[40], LUT[42], LUT[44], LUT[46],
LUT[48], LUT[50], LUT[52], LUT[54], LUT[56], LUT[58], LUT[60], LUT[62]}:
{LUT[1] , LUT[3] , LUT[5] , LUT[7] , LUT[9] , LUT[11], LUT[13], LUT[15],
LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31],
LUT[33], LUT[35], LUT[37], LUT[39], LUT[41], LUT[43], LUT[45], LUT[47],
LUT[49], LUT[51], LUT[53], LUT[55], LUT[57], LUT[59], LUT[61], LUT[63]};
wire [0:15] s2 = li[1] ?
{s1[0] , s1[2] , s1[4] , s1[6] , s1[8] , s1[10], s1[12], s1[14],
s1[16], s1[18], s1[20], s1[22], s1[24], s1[26], s1[28], s1[30]}:
{s1[1] , s1[3] , s1[5] , s1[7] , s1[9] , s1[11], s1[13], s1[15],
s1[17], s1[19], s1[21], s1[23], s1[25], s1[27], s1[29], s1[31]};
wire [0:7] s3 = li[2] ?
{s2[0], s2[2], s2[4], s2[6], s2[8], s2[10], s2[12], s2[14]}:
{s2[1], s2[3], s2[5], s2[7], s2[9], s2[11], s2[13], s2[15]};
wire [0:3] s4 = li[3] ? {s3[0], s3[2], s3[4], s3[6]}:
{s3[1], s3[3], s3[5], s3[7]};
wire [0:1] s5 = li[4] ? {s4[0], s4[2]} : {s4[1], s4[3]};
assign lut4_out[0] = s4[0];
assign lut4_out[1] = s4[1];
assign lut4_out[2] = s4[2];
assign lut4_out[3] = s4[3];
assign lut5_out[0] = s0[0];
assign lut5_out[1] = s5[1];
assign lut6_out = li[5] ? s5[0] : s5[1];
endmodule |
module dff(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
Q <= D;
1'b1:
always @(negedge C)
Q <= D;
endcase
endmodule |
module dffr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge R)
if (R)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or posedge R)
if (R)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule |
module dffre(
output reg Q,
input D,
input R,
input E,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge R)
if (R)
Q <= 1'b0;
else if(E)
Q <= D;
1'b1:
always @(negedge C or posedge R)
if (R)
Q <= 1'b0;
else if(E)
Q <= D;
endcase
endmodule |
module dffs(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input S
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge S)
if (S)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or negedge S)
if (S)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule |
module dffse(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input S,
input E,
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge S)
if (S)
Q <= 1'b1;
else if(E)
Q <= D;
1'b1:
always @(negedge C or negedge S)
if (S)
Q <= 1'b1;
else if(E)
Q <= D;
endcase
endmodule |
module dffsr(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge S or negedge R)
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or negedge S or negedge R)
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule |
module dffsre(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input E,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C or negedge S or negedge R)
if (!R)
Q <= 1'b0;
else if (!S)
Q <= 1'b1;
else if (E)
Q <= D;
endmodule |
module dffnsre(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input E,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C or negedge S or negedge R)
if (!R)
Q <= 1'b0;
else if (!S)
Q <= 1'b1;
else if (E)
Q <= D;
endmodule |
module latchsre (
output reg Q,
input S,
input R,
input D,
input G,
input E
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
begin
if (!R)
Q <= 1'b0;
else if (!S)
Q <= 1'b1;
else if (E && G)
Q <= D;
end
endmodule |
module latchnsre (
output reg Q,
input S,
input R,
input D,
input G,
input E
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
begin
if (!R)
Q <= 1'b0;
else if (!S)
Q <= 1'b1;
else if (E && !G)
Q <= D;
end
endmodule |
module scff(
output reg Q,
input D,
input clk
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge clk)
Q <= D;
endmodule |
module TDP_BRAM18 (
(* clkbuf_sink *)
input CLOCKA,
(* clkbuf_sink *)
input CLOCKB,
input READENABLEA,
input READENABLEB,
input [13:0] ADDRA,
input [13:0] ADDRB,
input [15:0] WRITEDATAA,
input [15:0] WRITEDATAB,
input [1:0] WRITEDATAAP,
input [1:0] WRITEDATABP,
input WRITEENABLEA,
input WRITEENABLEB,
input [1:0] BYTEENABLEA,
input [1:0] BYTEENABLEB,
//input [2:0] WRITEDATAWIDTHA,
//input [2:0] WRITEDATAWIDTHB,
//input [2:0] READDATAWIDTHA,
//input [2:0] READDATAWIDTHB,
output [15:0] READDATAA,
output [15:0] READDATAB,
output [1:0] READDATAAP,
output [1:0] READDATABP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
endmodule |
module TDP_BRAM36 (
(* clkbuf_sink *)
input CLOCKA,
(* clkbuf_sink *)
input CLOCKB,
input READENABLEA,
input READENABLEB,
input [14:0] ADDRA,
input [14:0] ADDRB,
input [31:0] WRITEDATAA,
input [31:0] WRITEDATAB,
input [3:0] WRITEDATAAP,
input [3:0] WRITEDATABP,
input WRITEENABLEA,
input WRITEENABLEB,
input [3:0] BYTEENABLEA,
input [3:0] BYTEENABLEB,
//input [2:0] WRITEDATAWIDTHA,
//input [2:0] WRITEDATAWIDTHB,
//input [2:0] READDATAWIDTHA,
//input [2:0] READDATAWIDTHB,
output [31:0] READDATAA,
output [31:0] READDATAB,
output [3:0] READDATAAP,
output [3:0] READDATABP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
endmodule |
module QL_DSP1 (
input [19:0] a,
input [17:0] b,
input clk0,
(* clkbuf_sink *)
input clk1,
(* clkbuf_sink *)
input [ 1:0] feedback0,
input [ 1:0] feedback1,
input load_acc0,
input load_acc1,
input reset0,
input reset1,
output reg [37:0] z
);
parameter MODE_BITS = 27'b00000000000000000000000000;
endmodule |
module sky130_fd_sc_ls__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module Lpm (input wire CLK, input wire nRST,
input wire request$enter__ENA,
input wire [31:0]request$enter$x,
output wire request$enter__RDY,
output wire outQ$enq__ENA,
output wire [31:0]outQ$enq$v,
input wire outQ$enq__RDY);
wire [2:0]RULE$recirc__ENA$agg_2e_tmp$state;
wire [15:0]RULE$recirc__ENA$y$IPA;
wire compBuf$tickIfc$allocateTicket__ENA;
wire compBuf$tickIfc$allocateTicket__RDY;
wire [3:0]compBuf$tickIfc$getTicket;
wire compBuf$tickIfc$getTicket__RDY;
wire [22:0]fifo$in$enq$v;
wire fifo$in$enq__ENA;
wire fifo$in$enq__RDY;
wire fifo$out$deq__ENA;
wire fifo$out$deq__RDY;
wire [22:0]fifo$out$first;
wire fifo$out$first__RDY;
wire inQ$in$enq__RDY;
wire inQ$out$deq__ENA;
wire inQ$out$deq__RDY;
wire [31:0]inQ$out$first;
wire inQ$out$first__RDY;
wire [31:0]mem$ifc$req$v;
wire mem$ifc$req__ENA;
wire mem$ifc$req__RDY;
wire mem$ifc$resAccept__ENA;
wire mem$ifc$resAccept__RDY;
wire [31:0]mem$ifc$resValue;
wire mem$ifc$resValue__RDY;
BufTicket compBuf (.CLK(CLK), .nRST(nRST),
.tickIfc$allocateTicket__ENA(compBuf$tickIfc$allocateTicket__ENA),
.tickIfc$allocateTicket__RDY(compBuf$tickIfc$allocateTicket__RDY),
.tickIfc$getTicket(compBuf$tickIfc$getTicket),
.tickIfc$getTicket__RDY(compBuf$tickIfc$getTicket__RDY));
Fifo1Base#(32) inQ (.CLK(CLK), .nRST(nRST),
.in$enq__ENA(request$enter__ENA),
.in$enq$v(request$enter$x),
.in$enq__RDY(inQ$in$enq__RDY),
.out$deq__ENA(inQ$out$deq__ENA),
.out$deq__RDY(inQ$out$deq__RDY),
.out$first(inQ$out$first),
.out$first__RDY(inQ$out$first__RDY));
FifoB1Base#(23) fifo (.CLK(CLK), .nRST(nRST),
.in$enq__ENA(fifo$in$enq__ENA),
.in$enq$v(fifo$in$enq$v),
.in$enq__RDY(fifo$in$enq__RDY),
.out$deq__ENA(fifo$out$deq__ENA),
.out$deq__RDY(fifo$out$deq__RDY),
.out$first(fifo$out$first),
.out$first__RDY(fifo$out$first__RDY));
LpmMemory mem (.CLK(CLK), .nRST(nRST),
.ifc$req__ENA(mem$ifc$req__ENA),
.ifc$req$v(mem$ifc$req$v),
.ifc$req__RDY(mem$ifc$req__RDY),
.ifc$resAccept__ENA(mem$ifc$resAccept__ENA),
.ifc$resAccept__RDY(mem$ifc$resAccept__RDY),
.ifc$resValue(mem$ifc$resValue),
.ifc$resValue__RDY(mem$ifc$resValue__RDY));
// There are still ERRORs in some of these conditions
assign compBuf$tickIfc$allocateTicket__ENA = ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY & mem$ifc$resAccept__RDY
& mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY & inQ$out$deq__RDY & fifo$in$enq__RDY & mem$ifc$req__RDY;
assign fifo$in$enq$v = ( ( ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & mem$ifc$req__RDY
& fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY
& inQ$out$deq__RDY & fifo$in$enq__RDY & mem$ifc$req__RDY )
? { 3'd0 , inQ$out$first[ 15 : 0 ] , compBuf$tickIfc$getTicket } : 23'd0 )
| ( ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY
& mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY )
? { RULE$recirc__ENA$agg_2e_tmp$state , fifo$out$first[ 19 : 4 ] , fifo$out$first[ 3 : 0 ] } : 23'd0 );
assign fifo$in$enq__ENA = ( ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY & inQ$out$deq__RDY & mem$ifc$req__RDY )
| ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY );
assign fifo$out$deq__ENA = ( ( mem$ifc$resValue == 32'd1 )
& ( !( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY
& mem$ifc$req__RDY & fifo$in$enq__RDY ) )
& mem$ifc$resValue__RDY & fifo$out$first__RDY & mem$ifc$resAccept__RDY & outQ$enq__RDY )
| ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$in$enq__RDY );
assign inQ$out$deq__ENA = ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY &
mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY & fifo$in$enq__RDY & mem$ifc$req__RDY;
assign mem$ifc$req$v = ( ( ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY & inQ$out$deq__RDY
& fifo$in$enq__RDY & mem$ifc$req__RDY )
? ( 32'd0 + inQ$out$first[ 31 : 16 ] inQ$out$first [ 18446744073709551615 ] ) : 32'd0 )
| ( ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY &
fifo$out$first__RDY & mem$ifc$resAccept__RDY
& mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY )
? ( ( ( mem$ifc$resValue + fifo$out$first[ 22 : 20 ] ) == 1 )
? RULE$recirc__ENA$y$IPA[ 15 : 8 ]
: RULE$recirc__ENA$y$IPA[ 7 : 0 ] )
: 8'd0 );
assign mem$ifc$req__ENA = ( ( ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY & inQ$out$deq__RDY )
| ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY & fifo$out$deq__RDY ) )
& fifo$in$enq__RDY;
assign mem$ifc$resAccept__ENA = ( ( mem$ifc$resValue == 32'd1 )
& ( !( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& mem$ifc$resValue__RDY & fifo$out$first__RDY & fifo$out$deq__RDY & outQ$enq__RDY )
| ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY );
assign outQ$enq$v = mem$ifc$resValue;
assign outQ$enq__ENA = ( mem$ifc$resValue == 32'd1 )
& ( !( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& mem$ifc$resValue__RDY & fifo$out$first__RDY & mem$ifc$resAccept__RDY & fifo$out$deq__RDY;
assign request$enter__RDY = inQ$in$enq__RDY;
// Extra assigments, not to output wires
assign RULE$recirc__ENA$agg_2e_tmp$state = fifo$out$first[ 22 : 20 ] + 3'd1;
assign RULE$recirc__ENA$y$IPA = fifo$out$first[ 19 : 4 ];
endmodule |
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule |
module sky130_fd_sc_hs__dlxtn (
VPWR ,
VGND ,
Q ,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input D ;
input GATE_N;
// Local signals
wire gate buf_Q ;
wire gate GATE_N_delayed;
wire gate D_delayed ;
wire GATE ;
// Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule |
module sky130_fd_sc_hs__einvp (
A ,
TE,
Z
);
input A ;
input TE;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module graph_core_stim;
`define DISPLAY_MODE 32'H0104_0101
`define BLOCK_MODE 32'h0
`include "../../stim/includes/stim_params_sh.h"
parameter
`ifdef BYTE4
BYTES = 4,
BYTE_BASE = 2,
`elsif BYTE8
BYTES = 8,
BYTE_BASE = 3,
`elsif BYTE16
BYTES = 16,
BYTE_BASE = 4,
`else
BYTES = 32,
BYTE_BASE = 5,
`endif
DE_ADDR = 32'h800,
`ifdef WIN_TEST XYW_ADDR = 32'h4000_0000,
`else XYW_ADDR = 32'h1000_0000,
`endif
id_width = 4,
addr_width = 29,
aresp_width = 2,
alen_width = 4,
asize_width = 3,
aburst_width = 2,
alock_width = 2,
acache_width = 4,
aprot_width = 3;
reg start_of_test = 0;
// Clock and reset signals
reg pclk; // host clock reg port
reg de_clk; // Drawing engine clock
reg pll_ref_clk; // 25Mhz Board clock
wire mclock; // Memory controller clock
reg bb_rstn; // Global soft reset
// Dual port ram interface for ded_ca_top.v
`ifdef BYTE16
wire [3:0] ca_enable;
`elsif BYTE8
wire [1:0] ca_enable;
`else
wire ca_enable;
`endif
wire de_push;
wire [(BYTES*8)-1:0] mc_read_data;
wire [4:0] ca_ram_addr0;
wire [4:0] ca_ram_addr1;
wire [(BYTES*8)-1:0] hb_dout_ram, hb_din;
reg [(BYTES*8)-1:0] hb_dout_ramc;
wire [(BYTES<<3)-1:0] ca_dout0;
wire [(BYTES<<3)-1:0] ca_dout1;
// Host interface signals
reg [31:2] paddr; // APB address.
reg [31:0] pwdata; // APA data.
reg pwrite; // Host write enable
reg psel; // Chip Select
reg penable; // Chip Select
wire [31:0] prdata; // host bus read back data
reg [31:0] pwcdata; // Cache swizzel data.
wire interrupt; // host interrupt active high.
// DLP signals
reg vb_int_tog; // Vertical interrupt
// DDR3 signals
tri [ 63: 0] mem_dq;
tri [ 7: 0] mem_dqs;
tri [ 7: 0] mem_dqsn;
wire [ 13: 0] mem_addr;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire mem_cke;
wire mem_clk;
wire mem_clk_n;
wire mem_cs_n;
wire [ 7: 0] mem_dm;
wire mem_odt;
wire mem_ras_n;
wire mem_rst_n;
wire mem_we_n;
// SIMULATION ENVIRONMENT REGISTERS.
reg enable_64;
reg [19:0] aw_mask;
reg [3:0] aw_size;
reg [31:0] config_reg;
reg [31:0] temp_config;
reg config_en;
reg [31:0] rbase_io;
reg [31:0] rbase_g; // holding register for the global base address.
reg [31:0] rbase_w; // holding register for the memory windows base addr
reg [31:0] rbase_a; // holding register for drawing engine A base addr
reg [31:0] rbase_aw; // holding reg for drawing engine A cache base addr
reg [31:0] rbase_b; // holding register for drawing engine B base addr
reg [31:0] rbase_bw; // holding reg for drawing engine B cache base addr
reg [31:0] rbase_i; // holding register for interrupt register address.
reg [31:0] rbase_e; // holding register for EPROM base address.
reg [31:0] rbase_mw0;
reg [31:0] rbase_mw1;
reg [31:0] test_reg; // holding register for read.
reg [15:0] h;
reg [15:0] i;
reg [15:0] j;
reg [15:0] k;
reg [15:0] l;
reg [15:0] m;
reg [15:0] n;
reg [15:0] o;
reg [15:0] p;
reg [15:0] w;
reg [15:0] xs;
reg [15:0] ys;
reg [15:0] xd;
reg [15:0] yd;
reg [15:0] xe;
reg [15:0] ye;
reg [15:0] xs_inc;
reg [15:0] ys_inc;
reg [15:0] xe_inc;
reg [15:0] ye_inc;
reg [15:0] zx;
reg [15:0] zy;
reg [14:0] mw0_mask;
reg [14:0] mw1_mask;
reg [31:12] mw0_ad_dout;
reg [31:12] mw1_ad_dout;
reg [3:0] mw0_sz_dout;
reg [3:0] mw1_sz_dout;
reg [31:0] mw0_org_dout;
reg [31:0] mw1_org_dout;
reg [31:0] mem_address;
reg [31:0] old_mem;
// hb port to the cache for sims
wire [4:0] hb_ram_addr;
reg [31:12] xyw_a_dout;
graph_core
#(
.BYTES (BYTES),
.DE_ADDR (DE_ADDR),
.XYW_ADDR (XYW_ADDR)
)
u_core
(
// Clock and reset signals
.de_clk (de_clk),
.mclock (mclock),
.pll_ref_clk (pll_ref_clk),
.bb_rstn (bb_rstn),
// Host interface signals
.pclk (pclk),
.paddr (paddr),
.pwdata (pwdata),
.pwrite (pwrite),
.psel (psel),
.penable (penable),
.prdata (prdata),
.pready (pready),
.pslverr (pslverr),
.interrupt (interrupt),
// Memory Window Flush in progress.
// Tie to zero if frame buffer is not cached.
.mw_de_fip (1'b0),
.mw_dlp_fip (1'b0),
// Dual port ram interface for ded_ca_top.v
.ca_enable (ca_enable),
.hb_ram_addr (hb_ram_addr),
.de_push (de_push),
.mc_read_data (mc_read_data),
.ca_ram_addr0 (ca_ram_addr0),
.ca_ram_addr1 (ca_ram_addr1),
.hb_dout_ram (hb_dout_ramc),
.ca_dout0 (ca_dout0),
.ca_dout1 (ca_dout1),
// DLP signals
.vb_int_tog (vb_int_tog),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (mem_cs_n),
.mem_dm (mem_dm),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_rst_n (mem_rst_n),
.mem_we_n (mem_we_n),
// outputs:
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqsn (mem_dqsn)
);
// Write swizzle.
always @* begin
case(u_core.U_DE.hdf_1)
3'b000: pwcdata = pwdata;
3'b001: pwcdata = {hdf_rot(pwdata[31:24]), hdf_rot(pwdata[23:16]), hdf_rot(pwdata[15:8]), hdf_rot(pwdata[7:0])};
3'b010: pwcdata = {pwdata[23:16], pwdata[31:24], pwdata[7:0], pwdata[15:8]};
3'b011: pwcdata = {hdf_rot(pwdata[23:16]), hdf_rot(pwdata[31:24]), hdf_rot(pwdata[7:0]), hdf_rot(pwdata[15:8])};
3'b100: pwcdata = {pwdata[15:8], pwdata[7:0], pwdata[31:24], pwdata[23:16]};
3'b101: pwcdata = {hdf_rot(pwdata[15:8]), hdf_rot(pwdata[7:0]), hdf_rot(pwdata[31:24]), hdf_rot(pwdata[23:16])};
3'b110: pwcdata = {pwdata[7:0], pwdata[15:8], pwdata[23:16], pwdata[31:24]};
3'b111: pwcdata = {hdf_rot(pwdata[7:0]), hdf_rot(pwdata[15:8]), hdf_rot(pwdata[23:16]), hdf_rot(pwdata[31:24])};
endcase
end
// Read swizzle.
always @* begin
if (BYTES == 16) begin
case(u_core.U_DE.hdf_1)
3'b000: hb_dout_ramc[127:64] = hb_dout_ram[127:64];
3'b001: hb_dout_ramc[127:64] =
{
hdf_rot(hb_dout_ram[127:120]),
hdf_rot(hb_dout_ram[119:112]),
hdf_rot(hb_dout_ram[111:104]),
hdf_rot(hb_dout_ram[103:96]),
hdf_rot(hb_dout_ram[95:88]),
hdf_rot(hb_dout_ram[87:80]),
hdf_rot(hb_dout_ram[79:72]),
hdf_rot(hb_dout_ram[71:64])
};
3'b010: hb_dout_ramc[127:64] =
{
hb_dout_ram[119:112],
hb_dout_ram[127:120],
hb_dout_ram[103:96],
hb_dout_ram[111:104],
hb_dout_ram[87:80],
hb_dout_ram[95:88],
hb_dout_ram[71:64],
hb_dout_ram[79:72]
};
3'b011: hb_dout_ramc[127:64] =
{
hdf_rot(hb_dout_ram[119:112]),
hdf_rot(hb_dout_ram[127:120]),
hdf_rot(hb_dout_ram[103:96]),
hdf_rot(hb_dout_ram[111:104]),
hdf_rot(hb_dout_ram[87:80]),
hdf_rot(hb_dout_ram[95:88]),
hdf_rot(hb_dout_ram[71:64]),
hdf_rot(hb_dout_ram[79:72])
};
3'b100: hb_dout_ramc[127:64] =
{
hb_dout_ram[111:104],
hb_dout_ram[103:96],
hb_dout_ram[127:120],
hb_dout_ram[119:112],
hb_dout_ram[79:72],
hb_dout_ram[71:64],
hb_dout_ram[95:88],
hb_dout_ram[87:80]
};
3'b101: hb_dout_ramc[127:64] =
{
hdf_rot(hb_dout_ram[111:104]),
hdf_rot(hb_dout_ram[103:96]),
hdf_rot(hb_dout_ram[127:120]),
hdf_rot(hb_dout_ram[119:112]),
hdf_rot(hb_dout_ram[79:72]),
hdf_rot(hb_dout_ram[71:64]),
hdf_rot(hb_dout_ram[95:88]),
hdf_rot(hb_dout_ram[87:80])
};
3'b110: hb_dout_ramc[127:64] =
{
hb_dout_ram[103:96],
hb_dout_ram[111:104],
hb_dout_ram[119:112],
hb_dout_ram[127:120],
hb_dout_ram[71:64],
hb_dout_ram[79:72],
hb_dout_ram[87:80],
hb_dout_ram[95:88]
};
3'b111: hb_dout_ramc[127:64] =
{
hdf_rot(hb_dout_ram[103:96]),
hdf_rot(hb_dout_ram[111:104]),
hdf_rot(hb_dout_ram[119:112]),
hdf_rot(hb_dout_ram[127:120]),
hdf_rot(hb_dout_ram[71:64]),
hdf_rot(hb_dout_ram[79:72]),
hdf_rot(hb_dout_ram[87:80]),
hdf_rot(hb_dout_ram[95:88])
};
endcase
end
if (BYTES == 16 || BYTES == 8) begin
case(u_core.U_DE.hdf_1)
3'b000: hb_dout_ramc[63:32] = hb_dout_ram[63:32];
3'b001: hb_dout_ramc[63:32] =
{
hdf_rot(hb_dout_ram[63:56]),
hdf_rot(hb_dout_ram[55:48]),
hdf_rot(hb_dout_ram[47:40]),
hdf_rot(hb_dout_ram[39:32])
};
3'b010: hb_dout_ramc[63:32] =
{
hb_dout_ram[55:48],
hb_dout_ram[63:56],
hb_dout_ram[39:32],
hb_dout_ram[47:40]
};
3'b011: hb_dout_ramc[63:32] =
{
hdf_rot(hb_dout_ram[55:48]),
hdf_rot(hb_dout_ram[63:56]),
hdf_rot(hb_dout_ram[39:32]),
hdf_rot(hb_dout_ram[47:40])
};
3'b100: hb_dout_ramc[63:32] =
{
hb_dout_ram[47:40],
hb_dout_ram[39:32],
hb_dout_ram[63:56],
hb_dout_ram[55:48]
};
3'b101: hb_dout_ramc[63:32] =
{
hdf_rot(hb_dout_ram[47:40]),
hdf_rot(hb_dout_ram[39:32]),
hdf_rot(hb_dout_ram[63:56]),
hdf_rot(hb_dout_ram[55:48])
};
3'b110: hb_dout_ramc[63:32] =
{
hb_dout_ram[39:32],
hb_dout_ram[47:40],
hb_dout_ram[55:48],
hb_dout_ram[63:56]
};
3'b111: hb_dout_ramc[63:32] =
{
hdf_rot(hb_dout_ram[39:32]),
hdf_rot(hb_dout_ram[47:40]),
hdf_rot(hb_dout_ram[55:48]),
hdf_rot(hb_dout_ram[63:56])
};
endcase
end
case(u_core.U_DE.hdf_1)
3'b000: hb_dout_ramc[31:0] = hb_dout_ram[31:0];
3'b001: hb_dout_ramc[31:0] =
{
hdf_rot(hb_dout_ram[31:24]),
hdf_rot(hb_dout_ram[23:16]),
hdf_rot(hb_dout_ram[15:8]),
hdf_rot(hb_dout_ram[7:0])
};
3'b010: hb_dout_ramc[31:0] =
{
hb_dout_ram[23:16],
hb_dout_ram[31:24],
hb_dout_ram[7:0],
hb_dout_ram[15:8]
};
3'b011: hb_dout_ramc[31:0] =
{
hdf_rot(hb_dout_ram[23:16]),
hdf_rot(hb_dout_ram[31:24]),
hdf_rot(hb_dout_ram[7:0]),
hdf_rot(hb_dout_ram[15:8])
};
3'b100: hb_dout_ramc[31:0] =
{
hb_dout_ram[15:8],
hb_dout_ram[7:0],
hb_dout_ram[31:24],
hb_dout_ram[23:16]
};
3'b101: hb_dout_ramc[31:0] =
{
hdf_rot(hb_dout_ram[15:8]),
hdf_rot(hb_dout_ram[7:0]),
hdf_rot(hb_dout_ram[31:24]),
hdf_rot(hb_dout_ram[23:16])
};
3'b110: hb_dout_ramc[31:0] =
{
hb_dout_ram[7:0],
hb_dout_ram[15:8],
hb_dout_ram[23:16],
hb_dout_ram[31:24]
};
3'b111: hb_dout_ramc[31:0] =
{
hdf_rot(hb_dout_ram[7:0]),
hdf_rot(hb_dout_ram[15:8]),
hdf_rot(hb_dout_ram[23:16]),
hdf_rot(hb_dout_ram[31:24])
};
endcase
end
// DE cache RAMs
// ram_32x32_dp_be u_ram0[`BYTES/4-1:0]
dual_port_sim u_ram0[BYTES/4-1:0]
(
.clock_a (pclk),
.data_a (pwcdata),
.wren_a (ca_enable),
.address_a (hb_ram_addr),
.clock_b (mclock),
.data_b (mc_read_data),
.address_b (ca_ram_addr0),
.wren_b (de_push),
.q_a (hb_dout_ram),
.q_b (ca_dout0)
);
// ram_32x32_dp_be u_ram4[`BYTES/4-1:0]
dual_port_sim u_ram4[BYTES/4-1:0]
(
.clock_a (pclk),
.data_a (pwcdata),
.wren_a (ca_enable),
.address_a (hb_ram_addr),
.clock_b (mclock),
.data_b (mc_read_data),
.address_b (ca_ram_addr1),
.wren_b (de_push),
.q_a (),
.q_b (ca_dout1)
);
ddr3_int_full_mem_model VR
(
// inputs:
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (mem_cs_n),
.mem_dm (mem_dm),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_rst_n (mem_rst_n),
.mem_we_n (mem_we_n),
// outputs:
.global_reset_n (),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqsn)
);
// CREATE CLOCKS.
always begin
#5 pclk = 0;
#5 pclk = 1;
end
always begin
#3 de_clk=0;
#3 de_clk=1;
end
always begin
#20 pll_ref_clk=0;
#20 pll_ref_clk=1;
end
task pci_burst_data;
input [31:0] address;
input [3:0] byte_enables;
input [31:0] data;
begin
// All APB Cycles are at least two cycles long.
if ((address[31:9] == rbase_a[31:9]) && (address[8:2] == 7'h04)) begin
xyw_a_dout[31:12] <= data[31:12];
end else if (address[31:9] == rbase_a[31:9]) begin
// Drawing engine register accesses
psel = 1'b1;
pwrite = 1'b1;
penable = 1'b0;
paddr = address[31:2];
pwdata = data;
@(posedge pclk);
#1;
penable = 1'b1;
#1;
while(pslverr | ~pready) begin
@(posedge pclk);
#1;
psel = 1'b1;
end
@(posedge pclk);
#1;
psel = 1'b0;
pwrite = 1'b0;
penable = 1'b0;
end else if (address[31:12] == xyw_a_dout) begin // if (address[31:9] == rbase_a[31:9])
// Drawing engine cache access
psel = 1'b1;
pwrite = 1'b1;
penable = 1'b0;
paddr = address[31:2];
pwdata = data;
@(posedge pclk);
#1;
penable = 1'b1;
@(posedge pclk);
#1;
psel = 1'b0;
pwrite = 1'b0;
penable = 1'b0;
end else if (address[31:8] == rbase_w[31:8]) begin // if (address[31:9] == rbase_a[31:9])
case (address[7:2])
// MW0_CTRL register (addr= {RBASE_W,x0000})
//6'h00: begin
//if (!byte_enables[0]) mw0_ctrl_dout_0 <= data[7:0];
//if (!byte_enables[2]) mw0_ctrl_dout_2 <= data[23:16];
//if (!byte_enables[3]) mw0_ctrl_dout_3 <= data[31:24];
//end
// MW0_AD register (addr= {RBASE_W,x0004})
6'h01: begin
if (!byte_enables[1]) mw0_ad_dout[15:12] <= data[15:12];
if (!byte_enables[2]) mw0_ad_dout[23:16] <= data[23:16];
if (!byte_enables[3]) mw0_ad_dout[31:24] <= data[31:24];
end
// MW0_SZ register (addr= {RBASE_W,x0008})
6'h02: begin
if (!byte_enables[0]) mw0_sz_dout <= data[3:0];
end //
// MW0_ORG register (addr= {RBASE_W,x0010 OR RBASE_W,x0014})
6'h04: begin
if (!byte_enables[1]) mw0_org_dout[15:12] <= data[15:12];
if (!byte_enables[2]) mw0_org_dout[23:16] <= data[23:16];
if (!byte_enables[3]) mw0_org_dout[26:24] <= data[26:24];
end
// MW1_CTRL register (addr= {RBASE_W,x0028})
//6'h0a: begin
//if (!byte_enables[0]) mw1_ctrl_dout_0 <= data[7:0];
//if (!byte_enables[2]) mw1_ctrl_dout_2 <= data[23:16];
//if (!byte_enables[3]) mw1_ctrl_dout_3 <= data[31:24];
//end
// MW1_AD register (addr= {RBASE_W,x002C})
6'h0b: begin
if (!byte_enables[1]) mw1_ad_dout[15:12] <= data[15:12];
if (!byte_enables[2]) mw1_ad_dout[23:16] <= data[23:16];
if (!byte_enables[3]) mw1_ad_dout[31:24] <= data[31:24];
end
// MW1_SZ register (addr= {RBASE_W,x0030})
6'h0c: begin
if (!byte_enables[0]) mw1_sz_dout <= data[3:0];
end //
// MW1_ORG register (addr= {RBASE_W,x0010 OR RBASE_W,x003C})
6'h0e: begin
if (!byte_enables[1]) mw1_org_dout[15:12] <= data[15:12];
if (!byte_enables[2]) mw1_org_dout[23:16] <= data[23:16];
if (!byte_enables[3]) mw1_org_dout[26:24] <= data[26:24];
end
endcase // case(hbi_addr_in[7:2])
case (mw0_sz_dout)
4'h0: mw0_mask = 15'b000000000000000; // 4K
4'h1: mw0_mask = 15'b000000000000001; // 8K
4'h2: mw0_mask = 15'b000000000000011; // 16K
4'h3: mw0_mask = 15'b000000000000111; // 32K
4'h4: mw0_mask = 15'b000000000001111; // 64K
4'h5: mw0_mask = 15'b000000000011111; // 128K
4'h6: mw0_mask = 15'b000000000111111; // 256K
4'h7: mw0_mask = 15'b000000001111111; // 512K
4'h8: mw0_mask = 15'b000000011111111; // 1M
4'h9: mw0_mask = 15'b000000111111111; // 2M
4'ha: mw0_mask = 15'b000001111111111; // 4M
4'hb: mw0_mask = 15'b000011111111111; // 8M
4'hc: mw0_mask = 15'b000111111111111; // 16M
4'hd: mw0_mask = 15'b001111111111111; // 32M
4'he: mw0_mask = 15'b011111111111111; // 64M
4'hf: mw0_mask = 15'b111111111111111; // 128M
endcase // case (mw0_sz_dout)
case (mw1_sz_dout)
4'h0: mw1_mask = 15'b000000000000000; // 4K
4'h1: mw1_mask = 15'b000000000000001; // 8K
4'h2: mw1_mask = 15'b000000000000011; // 16K
4'h3: mw1_mask = 15'b000000000000111; // 32K
4'h4: mw1_mask = 15'b000000000001111; // 64K
4'h5: mw1_mask = 15'b000000000011111; // 128K
4'h6: mw1_mask = 15'b000000000111111; // 256K
4'h7: mw1_mask = 15'b000000001111111; // 512K
4'h8: mw1_mask = 15'b000000011111111; // 1M
4'h9: mw1_mask = 15'b000000111111111; // 2M
4'ha: mw1_mask = 15'b000001111111111; // 4M
4'hb: mw1_mask = 15'b000011111111111; // 8M
4'hc: mw1_mask = 15'b000111111111111; // 16M
4'hd: mw1_mask = 15'b001111111111111; // 32M
4'he: mw1_mask = 15'b011111111111111; // 64M
4'hf: mw1_mask = 15'b111111111111111; // 128M
endcase // case (mw1_sz_dout)
@(posedge pclk);
end else if ((address[31:12] ~^ mw0_ad_dout[31:12] |
{7'h0,mw0_mask})==22'h3fffff) begin
// Direct memory access
$display("Write %h to %h ", data, mem_address);
mem_address = mw0_org_dout + {(address[26:12] & mw0_mask), address[11:0]};
if (BYTES == 4) begin
old_mem = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>2];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][31:24] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][23:16] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][15:8] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][7:0] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end else if (BYTES == 8) begin // if (BYTES == 4)
if (mem_address[2]) begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][63:56] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][55:48] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][47:40] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][39:32] = data[7:0];
end else begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][31:24] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][23:16] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][15:8] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][7:0] = data[7:0];
end
end else begin
old_mem = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>4];
case (mem_address[3:2])
2'h0: begin
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][31:24] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][23:16] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][15:8] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][7:0] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end // case: begin...
2'h1: begin
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][63:56] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][55:48] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][47:40] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][39:32] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end // case: begin...
2'h2: begin
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][95:88] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][87:80] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][79:72] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][71:64] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end // case: begin...
2'h3: begin
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][127:120] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][119:112] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][111:104] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][103:96] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end // case: begin...
endcase // case (mem_address[3:2])
end
$display("MW0 Access to %h", mem_address);
@(posedge pclk);
end else if ((address[31:12] ~^ mw1_ad_dout[31:12] |
{7'h0,mw1_mask})==22'h3fffff) begin
// Direct memory access
mem_address = mw1_org_dout + {(address[26:12] & mw1_mask), address[11:0]};
$display("Write %h to %h ", data, mem_address);
if (BYTES == 4) begin
old_mem = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>2];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][31:24] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][23:16] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][15:8] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][7:0] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end else if (BYTES == 8) begin // if (BYTES == 4)
if (mem_address[2]) begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][63:56] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][55:48] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][47:40] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][39:32] = data[7:0];
end else begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][31:24] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][23:16] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][15:8] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][7:0] = data[7:0];
end
end else begin
old_mem = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>4];
case (mem_address[3:2])
2'h0: begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][31:24] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][23:16] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][15:8] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][7:0] = data[7:0];
end // case: begin...
2'h1: begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][63:56] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][55:48] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][47:40] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][39:32] = data[7:0];
end // case: begin...
2'h2: begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][95:88] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][87:80] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][79:72] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][71:64] = data[7:0];
end // case: begin...
2'h3: begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][127:120] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][119:112] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][111:104] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][103:96] = data[7:0];
end // case: begin...
endcase // case (mem_address[3:2])
end
$display("MW1 Access to %h", mem_address);
@(posedge pclk);
end else // if ((address[31:12] ~^ mw1_ad_dout[31:12] |...
@(posedge pclk);
end
endtask // pci_burst_data
task mov_dw;
input [3:0] host_cycle_type;
input [31:0] address;
input [31:0] data;
input [3:0] byte_enables;
input [29:0] NO_OF_BEATS;
begin
if (host_cycle_type == MEM_WR ||
host_cycle_type == CONFIG_WR ||
host_cycle_type == IO_WR)
pci_burst_data(address, byte_enables, data);
end
endtask // mov_dw
task mov_burst;
input [3:0] host_cycle_type;
input [31:0] address;
input [3:0] byte_enables;
input [3:0] NO_OF_BEATS;
input [31:0] data1;
input [31:0] data2;
input [31:0] data3;
input [31:0] data4;
input [31:0] data5;
input [31:0] data6;
input [31:0] data7;
input [31:0] data8;
begin
if (NO_OF_BEATS >= 1) pci_burst_data(address, byte_enables, data1);
if (NO_OF_BEATS >= 2) pci_burst_data(address + 4, byte_enables, data2);
if (NO_OF_BEATS >= 3) pci_burst_data(address + 8, byte_enables, data3);
if (NO_OF_BEATS >= 4) pci_burst_data(address + 12, byte_enables, data4);
if (NO_OF_BEATS >= 5) pci_burst_data(address + 16, byte_enables, data5);
if (NO_OF_BEATS >= 6) pci_burst_data(address + 20, byte_enables, data6);
if (NO_OF_BEATS >= 7) pci_burst_data(address + 24, byte_enables, data7);
if (NO_OF_BEATS == 8) pci_burst_data(address + 28, byte_enables, data8);
end
endtask // mov_burst
task rd;
input [3:0] host_cycle_type;
input [31:0] address;
input [29:0] count; //number of beats in one burst cycle (max= 1G beats)
integer int_count, int_address;
begin
int_count = count; // Load a local copy of the counter
int_address= address;
psel = 1'b0;
while (int_count != 0) begin
if (int_address[31:9] == rbase_a[31:9]) begin
psel = 1'b1;
pwrite = 1'b0;
penable = 1'b0;
paddr = address[31:2];
@(posedge pclk);
#1;
penable = 1'b1;
@(posedge pclk);
test_reg = prdata;
#1;
psel = 1'b0;
penable = 1'b0;
end else if (address[31:12] == xyw_a_dout) begin
psel = 1'b1;
pwrite = 1'b0;
penable = 1'b0;
paddr = address[31:2];
@(posedge pclk);
#1;
penable = 1'b1;
@(posedge pclk);
@(posedge pclk);
test_reg = prdata;
#1;
psel = 1'b0;
penable = 1'b0;
end else if (int_address[31:8] == rbase_g[31:8]) begin
end else if (int_address[31:8] == rbase_i[31:8]) begin
end else if ((address[31:12] ~^ mw0_ad_dout[31:12] |
{7'h0,mw0_mask})==22'h3fffff) begin
// Direct memory access
mem_address = mw0_org_dout + (address[31:12] - mw0_ad_dout[31:12]);
if (BYTES == 4)
test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>2];
else if (BYTES == 8)
case (mem_address[2])
1'b0: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][31:0];
1'b1: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][63:32];
endcase
else
case (mem_address[2])
2'h0: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][31:0];
2'h1: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][63:32];
2'h2: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][95:64];
2'h3: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][127:96];
endcase
end else if ((address[31:12] ~^ mw1_ad_dout[31:12] |
{7'h0,mw1_mask})==22'h3fffff) begin
// Direct memory access
mem_address = mw1_org_dout + (address[31:12] - mw1_ad_dout[31:12]);
if (BYTES == 4)
test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>2];
else if (BYTES == 8)
case (mem_address[2])
1'b0: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][31:0];
1'b1: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][63:32];
endcase
else
case (mem_address[2])
2'h0: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][31:0];
2'h1: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][63:32];
2'h2: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][95:64];
2'h3: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][127:96];
endcase
end
int_address = int_address + 4;
int_count = int_count - 1;
end // while (int_count != 0)
end
endtask // rd
task cpu_mov_dw;
input[3:0] Access;
input[31:0] Address;
input[31:0] Data;
reg[31:0] shift_back, shift_forward;
reg[31:0] Address1, Address2;
reg[31:0] Data1, Data2;
reg[3:0] Mask1, Mask2;
reg[3:0] Strobe1, Strobe2;
reg[3:0] StandardMask ;
reg[3:0] Strobe;
begin
StandardMask = 4'b1111;
shift_back = (Address & 32'h0000_0003);
if (shift_back > 0)
begin
shift_forward = 4 - shift_back;
Address1 = Address - shift_back;
Data1 = Data << (shift_back * 8);
Mask1 = StandardMask << shift_back;
Strobe1 = ~Mask1;
Address2 = Address + shift_forward;
Data2 = Data >> (shift_forward * 8);
Mask2 = StandardMask >> shift_forward;
Strobe2 = ~Mask2;
mov_dw(Access, Address1, Data1, Strobe1, 1);
mov_dw(Access, Address2, Data2, Strobe2, 1);
end
else /* There is no need to shift data. */
begin
Strobe = ~StandardMask;
mov_dw(Access, Address, Data, Strobe, 1);
end
end
endtask // cpu_mov_dw
task cpu_mov_w;
input[3:0] Access;
input[31:0] Address;
input[15:0] Data;
reg[31:0] shift_back;
reg[31:0] Data2;
reg[3:0] StandardMask ;
reg[3:0] Strobe;
begin
StandardMask = 4'b0011;
shift_back = (Address & 32'h0000_0003);
if (shift_back > 2)
begin
mov_dw(Access, Address - 3, Data << 24, 4'b1000, 1);
mov_dw(Access, Address + 1, Data, 4'b0001, 1);
end
else /* Shift the data in the word */
begin
Strobe = ~(StandardMask << shift_back);
Data2 = Data << (shift_back << 3);
mov_dw(Access, Address - shift_back, Data2, Strobe, 1);
end
end
endtask // cpu_mov_w
task cpu_mov_b;
input[3:0] Access;
input[31:0] Address;
input[7:0] Data;
reg[31:0] shift_back, shift_forward;
reg[31:0] NewAddress;
reg[31:0] LongData;
reg[3:0] Mask;
reg[3:0] StandardMask;
reg[3:0] Strobe;
reg[31:0] Long_tmp;
reg[31:0] test_tmp;
begin
LongData = Data;
StandardMask = 4'b0001;
shift_back = (Address & 32'h0000_0003);
if (shift_back > 0)
begin
shift_forward = 4 - shift_back;
NewAddress = Address - shift_back;
LongData = LongData << (shift_back * 8);
Mask = StandardMask << shift_back;
Strobe = ~Mask;
rd(MEM_RD, NewAddress,1);
test_tmp = {test_reg[31:24] & {8{Strobe[3]}},
test_reg[23:16] & {8{Strobe[2]}},
test_reg[15:8] & {8{Strobe[1]}},
test_reg[7:0] & {8{Strobe[0]}}};
Long_tmp = {LongData[31:24] & {8{~Strobe[3]}},
LongData[23:16] & {8{~Strobe[2]}},
LongData[15:8] & {8{~Strobe[1]}},
LongData[7:0] & {8{~Strobe[0]}}};
mov_dw(Access, NewAddress, (Long_tmp | test_tmp), Strobe, 1);
end
else /* There is no need to shift data. */
begin
NewAddress = Address;
Strobe = ~StandardMask;
rd(MEM_RD, NewAddress,1);
test_tmp = {test_reg[31:24] & {8{Strobe[3]}},
test_reg[23:16] & {8{Strobe[2]}},
test_reg[15:8] & {8{Strobe[1]}},
test_reg[7:0] & {8{Strobe[0]}}};
Long_tmp = {LongData[31:24] & {8{~Strobe[3]}},
LongData[23:16] & {8{~Strobe[2]}},
LongData[15:8] & {8{~Strobe[1]}},
LongData[7:0] & {8{~Strobe[0]}}};
mov_dw(Access, NewAddress, (Long_tmp | test_tmp), Strobe, 1);
end
end
endtask // cpu_mov_b
task Verify;
input [31:0] address;
input [7:0] size;
input [31:0] data;
begin
$display("VERIFY ADDRESS %h Size %h", address, size);
$display("VERIFY EXPECTED %h", data);
rd(MEM_RD, address, 1);
$display("VERIFY DATA %h", test_reg);
end
endtask
task Verify_Io;
input [31:0] address;
input [7:0] size;
input [31:0] data;
integer long_addr;
integer byte_enables;
begin
long_addr = address & 32'hFFFFFFFC;
byte_enables = (1 << size) - 1;
byte_enables = byte_enables << (address & 3);
$display("VERIFY ADDRESS %h Size %h", address, size);
$display("VERIFY EXPECTED %h", data);
rd_byte(IO_RD, address, ~byte_enables, 1);
data = (test_reg >> (address & 3)) & ((1 << size) - 1);
$display("VERIFY DATA %h", data);
end
endtask
task initialize;
begin
@(posedge pclk);
bb_rstn = 0;
rbase_io = 32'h9000;
config_en = 1'b1;
repeat (12) @(posedge pclk);
config_en = 1'b0;
repeat (12) @(posedge pclk);
bb_rstn = 1;
// Enable all address decoding
load_base("G",32'h100);
load_base("W",32'h200);
load_base("A",32'h800);
load_base("B",32'h400);
load_base("I",32'h500);
load_base("E",32'h600);
end
endtask // initialize
/***************************************************************************/
/* TASK TO LOAD THE BASE ADDRESSES. */
/***************************************************************************/
task load_base;
input [7:0] reg_string;
input [31:0] reg_address;
begin
if(reg_string=="G") rbase_g = {reg_address[31:8],8'h0};
if(reg_string=="W") rbase_w = {reg_address[31:8],8'h0};
if(reg_string=="A") rbase_a = {reg_address[31:8],8'h0};
if(reg_string=="B") rbase_b = {reg_address[31:8],8'h0};
if(reg_string=="I") rbase_i = {reg_address[31:8],8'h0};
if(reg_string=="E") rbase_e = {reg_address[31:8],8'h0};
end
endtask
/**************************************************************************/
task redhat_wait;
begin
rd(MEM_RD, rbase_a+FLOW,1);
while (test_reg[3] || test_reg[1] || test_reg[0]) rd(MEM_RD, rbase_a+FLOW,1);
end
endtask
/**************************************************************************/
task wait_for_pipe_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+BUSY,1);
while (test_reg[0]) rd(MEM_RD, rbase_a+BUSY,1);
end
endtask
/**************************************************************************/
task wait_for_de_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+FLOW,1);
while (test_reg[0]) rd(MEM_RD, rbase_a+FLOW,1);
end
endtask
/**************************************************************************/
task wait_for_mc_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+FLOW,1);
while (test_reg[1]) rd(MEM_RD, rbase_a+FLOW,1);
repeat (6000) @(posedge pclk);
end
endtask
/**************************************************************************/
task wait_for_prev_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+FLOW,1);
while (test_reg[3]) rd(MEM_RD, rbase_a+FLOW,1);
end
endtask
/**************************************************************************/
task wait_for_crdy_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+BUF_CTRL,1);
while (test_reg[31]) rd(MEM_RD, rbase_a+BUF_CTRL,1);
end
endtask
task wait_for_dlp;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+32'hFC,1);
while (~test_reg[31]) rd(MEM_RD, rbase_a+32'hFC,1);
end
endtask
/*
task wait_for_eq;
input [31:0] address;
input [4:0] bit_select;
input value;
begin
rd(MEM_RD, address,1);
while ((test_reg[bit_select]) != value) rd(MEM_RD, address,1);
end
endtask
*/
/* Empty tasks to not break tests */
task wait_for_mw0;
begin
@(posedge pclk);
end
endtask
task wait_for_mw1;
begin
@(posedge pclk);
end
endtask
// Main task
initial begin
mw0_org_dout = 32'b0;
mw1_org_dout = 32'b0;
vb_int_tog = 1'b0;
paddr = 30'h0;
pwdata = 0;
pwrite = 1'b0;
psel = 1'b0;
penable = 1'b0;
initialize;
//set up the memory window addresses
pci_burst_data(rbase_a + XYC_AD, 4'h0, 32'h1000_0000); // 4 KBytes
mov_dw(MEM_WR, rbase_w + MW0_AD, 32'h4000_0000, 4'h0, 1);
mov_dw(MEM_WR, rbase_w + MW0_SZ, 32'h0000_000A, 4'h0, 1); // 4 MBytes
mov_dw(MEM_WR, rbase_w + MW1_AD, 32'hA000_0000, 4'h0, 1);
mov_dw(MEM_WR, rbase_w + MW1_SZ, 32'h0000_000A, 4'h0, 1); // 4 MBytes
/* clear interrupt register. */
pci_burst_data(rbase_a+INTP, 4'h0, 32'h0000_0000);
/* clear interrupt mask register. */
pci_burst_data(rbase_a+INTM, 4'h0, 32'h0000_0000);
/* set the buffer control register. */
pci_burst_data(rbase_a+BUF_CTRL, 4'h0, 32'h0000_0000);
/* set the buffer control register. */
pci_burst_data(rbase_a+XYW_AD, 4'h0, 32'h1000_0000);
/* Set the Drawing engine source origins equals zero. */
pci_burst_data(rbase_a+DE_SORG,4'h0,32'h0000_0000);
pci_burst_data(rbase_a+DE_DORG,4'h0,32'h0000_0000);
/* Drawing engine KEY equals zero. */
pci_burst_data(rbase_a+DE_KEY,4'h0,32'h0000_0000);
/* Set the Drawing engine pitches = 40h (64x16bytes=1024). */
pci_burst_data(rbase_a+DE_SPTCH,4'h0,32'h0000_0400);
pci_burst_data(rbase_a+DE_DPTCH,4'h0,32'h0000_0400);
/* Drawing engine foreground = ffff. */
pci_burst_data(rbase_a+FORE,4'h0,32'h9999_9999);
/* Drawing engine background = bbbb. */
pci_burst_data(rbase_a+BACK,4'h0,32'hbbbb_bbbb);
/* Drawing engine plane mask = ffffffff. */
pci_burst_data(rbase_a+MASK,4'h0,32'hffff_ffff);
/* Drawing engine line pattern register = ffffffff. */
pci_burst_data(rbase_a+LPAT,4'h0,32'hffff_ffff);
/* Drawing engine line pattern control register = 0. */
pci_burst_data(rbase_a+PCTRL,4'h0,32'h0000_0000);
/* Drawing engine clipping top left corner (0,0). */
pci_burst_data(rbase_a+CLPTL,4'h0,32'h0000_0000);
/* Drawing engine clipping bottom right corner (1024,1024). */
pci_burst_data(rbase_a+CLPBR,4'h0, 32'h03ff_03ff);
pci_burst_data(rbase_a + XYC_AD, 4'h0, 32'h1000_0400); // 4 KBytes
// Wait for the DDR2 Controller to come up
wait (u_core.init_done);
$display("DDR3 Contoller now up.");
`include "the_test.h"
$stop;
end
function [7:0] hdf_rot;
input [7:0] din;
hdf_rot = {din[0], din[1], din[2], din[3], din[4], din[5], din[6], din[7]};
endfunction //
endmodule |
module fpga_top
(
input wire RSTN,
input wire clk_sys,
input wire clk,
input wire SW4N,
input wire SW5N,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL_IK
);
parameter
N_IN = 7,
N_OUT = 90;
reg req;
reg [N_IN-1:0] n;
wire ack;
wire [N_OUT-1:0] result;
// detect falling edge
reg [1:0] ff_sw4 = 0;
reg [1:0] ff_sw5 = 0;
always @(posedge clk) begin
ff_sw4 <= {ff_sw4[0], SW4N};
ff_sw5 <= {ff_sw5[0], SW5N};
end
wire tri_sw4 = (ff_sw4 == 2'b10);
wire tri_sw5 = (ff_sw5 == 2'b10);
always @(posedge clk or negedge RSTN) begin
if(~RSTN)
req <= 0;
else if(tri_sw4) begin
req <= 1;
n <= 60;
end
else if(tri_sw5)
req <= 0;
end
fib
#(
.N_IN ( N_IN ) ,
.N_OUT ( N_OUT )
) fib_1
(
.rst_n ( RSTN ) ,
.clk ( clk ) ,
.req ( req ) ,
.n ( n ) ,
.ack ( ack ) ,
.result ( result )
);
/* 7SEG LED
+--------+--------+--------+--------+
| data0 | data1 | data2 | data3 |
+--------+--------+--------+--------+
| data4 | data5 | data6 | data7 |
+--------+--------+--------+--------+
| data8 | data9 | data10 | data11 |
+--------+--------+--------+--------+
| data12 | data13 | data14 | data15 |
+--------+--------+--------+--------+
*/
displayIK_7seg_16
_displayIK_7seg_16
(
.RSTN ( RSTN ),
.CLK ( clk_sys ),
.data0 ( {3'h0, clk, 3'h0, RSTN, 8'h00} ),
.data1 ( {3'h0, SW4N, 3'h0, SW5N, 3'h0, req, 3'h0, ack} ),
.data2 ( 0 ) ,
.data3 ( n ) ,
.data4 ( result[89:64] ) ,
.data5 ( result[63:48] ) ,
.data6 ( result[47:32] ) ,
.data7 ( result[31:16] ) ,
.data8 ( result[15: 0] ) ,
.data9 ( 0 ) ,
.data10 ( 0 ) ,
.data11 ( 0 ) ,
.data12 ( 0 ) ,
.data13 ( 0 ) ,
.data14 ( 0 ) ,
.data15 ( 0 ) ,
.SEG_A ( SEG_A ) ,
.SEG_B ( SEG_B ) ,
.SEG_C ( SEG_C ) ,
.SEG_D ( SEG_D ) ,
.SEG_E ( SEG_E ) ,
.SEG_F ( SEG_F ) ,
.SEG_G ( SEG_G ) ,
.SEG_H ( SEG_H ) ,
.SEG_SEL ( SEG_SEL_IK )
);
endmodule |
module test_arbiter_rr;
// parameters
localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "REQUEST";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;
// Outputs
wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
request,
acknowledge);
$to_myhdl(grant,
grant_valid,
grant_encoded);
// dump file
$dumpfile("test_arbiter_rr.lxt");
$dumpvars(0, test_arbiter_rr);
end
arbiter #(
.PORTS(PORTS),
.TYPE(TYPE),
.BLOCK(BLOCK)
)
UUT (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule |
module reconocedor_cursor(
input [2:0] visor_x,
input [1:0] visor_y,
output reg [7:0] valor,
output reg is_number
);
always @(*) begin
case ({visor_x,visor_y})
{3'd0 ,2'd0}: {valor,is_number}={8'b0,1'b1};
{3'd1 ,2'd0}: {valor,is_number}={8'b1,1'b1};
{3'd2 ,2'd0}: {valor,is_number}={8'd2,1'b1};
{3'd3 ,2'd0}: {valor,is_number}={8'd3,1'b1};
{3'd4 ,2'd0}: {valor,is_number}={8'd16,1'b0}; //suma
{3'd5 ,2'd0}: {valor,is_number}={8'd17,1'b0}; //resta
{3'd0 ,2'd1}: {valor,is_number}={8'd4,1'b1};
{3'd1 ,2'd1}: {valor,is_number}={8'd5,1'b1};
{3'd2 ,2'd1}: {valor,is_number}={8'd6,1'b1};
{3'd3 ,2'd1}: {valor,is_number}={8'd7,1'b1};
{3'd4 ,2'd1}: {valor,is_number}={8'd18,1'b0}; //mul
{3'd5 ,2'd1}: {valor,is_number}={8'd19,1'b0}; //or
{3'd0 ,2'd2}: {valor,is_number}={8'd8,1'b1};
{3'd1 ,2'd2}: {valor,is_number}={8'd9,1'b1};
{3'd2 ,2'd2}: {valor,is_number}={8'h0a,1'b1};
{3'd3 ,2'd2}: {valor,is_number}={8'h0b,1'b1};
{3'd4 ,2'd2}: {valor,is_number}={8'd20,1'b0}; //and
{3'd5 ,2'd2}: {valor,is_number}={8'd21,1'b0}; //CE
{3'd0 ,2'd3}: {valor,is_number}={8'h0c,1'b1};
{3'd1 ,2'd3}: {valor,is_number}={8'h0d,1'b1};
{3'd2 ,2'd3}: {valor,is_number}={8'h0e,1'b1};
{3'd3 ,2'd3}: {valor,is_number}={8'h0f,1'b1};
{3'd4 ,2'd3}: {valor,is_number}={8'd22,1'b0}; //EXE
default: {valor,is_number}={8'd28,1'b0};
endcase
end
endmodule |
module _InternalTestRam(input wire clk,
// Write enable
input wire we,
// Address
input wire [`TR_ADDR_MSB_POS:0] addr,
// Data in
input wire [`TR_DATA_MSB_POS:0] data_in,
// Data out
output reg [`TR_DATA_MSB_POS:0] data_out);
`include "src/inc/cpu_debug_params.v"
reg [`TR_DATA_MSB_POS:0] __mem[0:`_ARR_SIZE_THING(`_TR_ADDR_WIDTH)];
initial $readmemh("readmemh_input.txt.ignore", __mem);
always @ (posedge clk)
begin
//$display("In _InternalTestRam: %h\t\t%h\t\t%h, %h",
// we,
// addr,
// data_in, data_out);
$display("In _InternalTestRam: %h\t\t%h, %h, %h\t\t%h",
we,
__mem[__debug_addr_0], __mem[__debug_addr_1],
__mem[__debug_addr_2],
data_out);
if (we)
begin
__mem[addr] <= data_in;
end
data_out <= __mem[addr];
end
endmodule |
module TestRam(input wire clk,
input wire req_rdwr,
// Write enable
input wire we,
// Address
input wire [`TR_ADDR_MSB_POS:0] addr,
// Data in
input wire [`TR_DATA_MSB_POS:0] data_in,
// Data out
output wire [`TR_DATA_MSB_POS:0] data_out,
// data_ready goes high when data is ready
output reg data_ready);
`include "src/inc/generic_params.v"
reg __can_rdwr;
//reg [1:0] __can_rdwr;
// "pt" is short for "passthrough"
wire __pt_we;
wire [`TR_ADDR_MSB_POS:0] __pt_addr;
wire [`TR_DATA_MSB_POS:0] __pt_data_in, __pt_data_out;
// Inputs to internal_test_ram
assign __pt_we = we;
assign __pt_addr = addr;
assign __pt_data_in = data_in;
// Outputs from internal_test_ram
assign data_out = __pt_data_out;
_InternalTestRam internal_test_ram(.clk(clk), .we(__pt_we),
.addr(__pt_addr), .data_in(__pt_data_in),
.data_out(__pt_data_out));
initial data_ready = __false;
initial __can_rdwr = __false;
always @ (posedge clk)
begin
//__can_rdwr <= !__can_rdwr;
if (!req_rdwr)
begin
data_ready <= __false;
__can_rdwr <= __false;
end
else // if (req_rdwr)
begin
__can_rdwr <= !__can_rdwr;
data_ready <= __can_rdwr;
end
end
endmodule |
module Hydra ( ready , data_out ,
clk , rst_n ,
inst_cur , inst_nxt ,
data_in_1 , data_in_2 ,
hy_exe
);
//====parameter Declaration====//
parameter inst_num = 31;
parameter nop = 5'h0;
parameter setrn = 5'h1;
parameter mul = 5'h2;
parameter add = 5'h3;
parameter sub = 5'h4;
parameter mod = 5'h5;
parameter pol_add = 5'h6;
parameter mov = 5'h7;
parameter shuffle = 5'h8;
parameter stall = 3'h7;
parameter mode_i = 1'b0;
parameter mode_q = 1'b1;
parameter state_idle = 4'h0 ;
parameter state_load_N = 4'h1 ;
parameter state_p_m_0 = 4'h2 ;
parameter state_p_m_1 = 4'h3 ;
parameter state_p_m_2 = 4'h4 ;
parameter state_p_m_3 = 4'h5 ;
parameter state_p_a_1 = 4'h6 ;
parameter state_p_s_N = 4'h7 ;
parameter state_p_s_1 = 4'h8 ;
parameter state_p_a_N = 4'h9 ;
parameter state_write = 4'hf ;
integer i;
//====I/O Declaration====//
output ready ;
reg ready ;
output [255:0] data_out;
reg [255:0] data_out;
input clk , hy_exe , rst_n;
input [255:0] data_in_1 , data_in_2;
input [inst_num-1:0] inst_cur , inst_nxt;
//====Register Declaration====//
reg [15:0] A [15:0];
reg [15:0] A_next [15:0];
reg [15:0] X [15:0];
reg [15:0] X_next [15:0];
reg [15:0] N [15:0];
reg [15:0] N_next [15:0];
reg [18:0] Y [16:0];
reg [18:0] Y_next [16:0];
reg [15:0] temp , temp_next , np , np_next;
reg [3: 0] curstate , nextstate;
reg [4: 0] counter , counter_next;
//====Wire Declaration====//
reg [15:0] mul_in1 [15:0];
reg [15:0] mul_in2 [15:0];
reg [31:0] mul_o [15:0];
reg [17:0] add1_in1 [15:0];
reg [17:0] add1_in2 [15:0];
reg [18:0] add1_o [15:0];
reg [17:0] add2_in1 [15:0];
reg [17:0] add2_in2 [15:0];
reg [18:0] add2_o [15:0];
//====Connection Wire====//
reg [15:0] buf_44 [43:0];
reg [15:0] vec_inA [15:0];
reg [15:0] vec_inX [15:0];
reg [15:0] vec_out [15:0];
//====Define Wire====//
wire [4:0] comp_type_nxt = inst_nxt[30:26];
wire [4:0] comp_type = inst_cur[30:26];
wire [1:0] shift = inst_cur[17:16];
wire mode = inst_cur[9];
wire rstY = inst_cur[8];
wire accuY = inst_cur[7];
wire WB = inst_cur[6];
wire expand = inst_cur[18];
wire load_A = inst_nxt[24];
wire load_X = inst_nxt[15];
wire [31:0] pol_det = { N[1] , N[0] };
//====Vector Connection====//
always @ (*) begin
data_out = { vec_out[15], vec_out[14], vec_out[13], vec_out[12], vec_out[11], vec_out[10], vec_out[9], vec_out[8],
vec_out[ 7], vec_out[ 6], vec_out[ 5], vec_out[ 4], vec_out[ 3], vec_out[ 2], vec_out[1], vec_out[0] };
{ vec_inA[15], vec_inA[14], vec_inA[13], vec_inA[12], vec_inA[11], vec_inA[10], vec_inA[9], vec_inA[8],
vec_inA[ 7], vec_inA[ 6], vec_inA[ 5], vec_inA[ 4], vec_inA[ 3], vec_inA[ 2], vec_inA[1], vec_inA[0] } = data_in_1;
{ vec_inX[15], vec_inX[14], vec_inX[13], vec_inX[12], vec_inX[11], vec_inX[10], vec_inX[9], vec_inX[8],
vec_inX[ 7], vec_inX[ 6], vec_inX[ 5], vec_inX[ 4], vec_inX[ 3], vec_inX[ 2], vec_inX[1], vec_inX[0] } = data_in_2;
buf_44[ 0] = N[ 0];buf_44[ 1] = N[ 1];buf_44[ 2] = N[ 2];buf_44[ 3] = N[ 3];buf_44[ 4] = N[ 4];buf_44[ 5] = N[ 5];
buf_44[ 6] = N[ 6];buf_44[ 7] = N[ 7];buf_44[ 8] = N[ 8];buf_44[ 9] = N[ 9];buf_44[10] = N[10];buf_44[11] = N[11];
buf_44[12] = N[12];buf_44[13] = N[13];buf_44[14] = N[14];buf_44[15] = N[15];buf_44[16] = X[ 0];buf_44[17] = X[ 1];
buf_44[18] = X[ 2];buf_44[19] = X[ 3];buf_44[20] = X[ 4];buf_44[21] = X[ 5];buf_44[22] = X[ 6];buf_44[23] = X[ 7];
buf_44[24] = X[ 8];buf_44[25] = X[ 9];buf_44[26] = X[10];buf_44[27] = X[11];buf_44[28] = X[12];buf_44[29] = X[13];
buf_44[30] = X[14];buf_44[31] = X[15];buf_44[32] = Y[ 0];buf_44[33] = Y[ 1];buf_44[34] = Y[ 2];buf_44[35] = Y[ 3];
buf_44[36] = Y[ 4];buf_44[37] = Y[ 5];buf_44[38] = Y[ 6];buf_44[39] = Y[ 7];buf_44[40] = Y[ 8];buf_44[41] = Y[ 9];
buf_44[42] = Y[10];buf_44[43] = Y[11];
end
//===============================Sequential Logic===============================//
always @ ( posedge clk or negedge rst_n ) begin
if ( rst_n == 1'b0 ) begin
curstate <= 4'd0;
counter <= 5'd0;
temp <=16'd0;
np <=16'd0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
A[i] <= 16'd0;
X[i] <= 16'd0;
N[i] <= 16'd0;
Y[i] <= 19'd0;
end
Y[16] <= 19'd0;
end
else begin
curstate <= nextstate;
counter <= counter_next;
temp <= temp_next;
np <= np_next;
for ( i=0 ; i!=16 ; i=i+1 ) begin
A[i] <= A_next[i];
X[i] <= X_next[i];
N[i] <= N_next[i];
Y[i] <= Y_next[i];
end
Y[16] <= Y_next[16];
end
end
//===============================NextState Logic===============================//
always @ (*)
begin
case (curstate)
state_idle :
case (comp_type)
mul :
nextstate = state_p_m_0;
add :
nextstate = state_p_a_1;
sub :
nextstate = state_p_s_1;
default :
nextstate = state_idle;
endcase
state_p_m_0 :
nextstate = state_p_m_1;
state_p_m_1 :
nextstate = state_p_m_2;
state_p_m_2 :
nextstate = state_p_m_3;
state_p_m_3 :
if ( counter==5'd17 )
nextstate = state_write;
else
nextstate = state_p_m_1;
state_p_a_1 :
if ( add2_o[15]<N[15] && add2_o[15][16]==1'b0 )
nextstate = state_write;
else
nextstate = state_p_s_N;
state_p_s_N :
nextstate = state_write;
state_p_s_1 :
if (add2_o[15][16]==1'b0 )
nextstate = state_write;
else
nextstate = state_p_a_N;
state_p_a_N :
nextstate = state_write;
state_write :
nextstate = state_idle;
default :
nextstate = state_idle;
endcase
end
//===============================Output Logic===============================//
always @ ( * ) begin
temp_next = temp;
//-------------------------------------------
//--********Write back strategy************--
//-------------------------------------------
for ( i=0 ; i!=16 ; i=i+1 ) begin //vec_out
if (WB)
vec_out[i] = add2_o[i];
else
vec_out[i] = 16'd0;
end
//----------------------------------------
//--********Loading strategy************--
//----------------------------------------
if (ready==1'b1) begin //A & X
if (load_A==1'b1) begin
if (expand==1'b1) begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = vec_inA[0];
end // end expand
else if (shift==2'd1) begin
for ( i=0 ; i!=15 ; i=i+1 )
A_next[i] = vec_inA[i+1];
A_next[15] = 16'd0;
end // end shift 1
else if (shift==2'd2) begin
for ( i=0 ; i!=14 ; i=i+1 )
A_next[i] = vec_inA[i+2];
A_next[14] = 16'd0;
A_next[15] = 16'd0;
end // end shift 2
else begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = vec_inA[i];
end // end normal load
end // end load_A == 1
else if (shift==2'd1) begin
for ( i=0 ; i!=15 ; i=i+1 )
A_next[i] = A[i+1];
A_next[15] = 16'd0;
end // end shift 1
else if (shift==2'd2) begin
for ( i=0 ; i!=14 ; i=i+1 )
A_next[i] = A[i+2];
A_next[14] = 16'd0;
A_next[15] = 16'd0;
end // end shift 2
else begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = A[i];
end
end
else begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = A[i];
end
for ( i=0 ; i!=16 ; i=i+1 ) begin
if ( ready==1'b1 && load_X==1'b1 )
X_next[i] = vec_inX[i];
else
X_next[i] = X[i];
end
//---------------------------------------------
//--********Accumulation strategy************--
//---------------------------------------------
for ( i=0 ; i!=16 ; i=i+1 ) begin //Y
if (accuY==1'b1)
Y_next[i] = add2_o[i];
else if (rstY==1'b1)
Y_next[i] = 19'd0;
else
Y_next[i] = Y[i];
end
if (rstY==1'b1)
Y_next[16] = 19'd0;
else
Y_next[16] = Y[16];
//----------------------------------------
//--********Default strategy************--
//----------------------------------------
np_next = (comp_type==setrn) ? 16'h15c1/*A[0]*/ : np;
// for ( i=0 ; i!=16 ; i=i+1 ) begin
// N_next[i] = (comp_type==setrn) ? X[i] : N[i];
// end
ready = hy_exe;
for ( i=0 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = 16'd0;
mul_in2[i] = 16'd0;
add1_in1[i] = 18'd0;
add1_in2[i] = 18'd0;
add2_in1[i] = 18'd0;
add2_in2[i] = 18'd0;
N_next[i] = N[i];
end
counter_next = 5'd0;
//--------------------------------------------
//--********Instruction strategy************--
//--------------------------------------------
if (hy_exe==1'b0) begin
counter_next = counter;
for ( i=0 ; i!=16 ; i=i+1 ) begin
N_next[i] = N[i];
X_next[i] = X[i];
A_next[i] = A[i];
Y_next[i] = Y[i];
end
Y_next[16] = Y[16];
end
else if (mode==mode_q) begin
case (comp_type)
nop : begin
counter_next = 5'd0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = 16'd0;
mul_in2[i] = 16'd0;
add1_in1[i] = A[i];
add1_in2[i] = mul_o[i];
add2_in1[i] = (accuY) ? Y[i] : 16'd0;
add2_in2[i] = add1_o[i];
end
end
setrn : begin
if (comp_type_nxt==pol_add)
counter_next = 5'd0;
else
counter_next = 5'd0;
//XXXXXXXXXXXXXXXXXXXXXXXXXX TO BE CONFIRMED XXXXXXXXXXXXXXXXXXXXXXXXXX
for ( i=0 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = 16'd0;
mul_in2[i] = 16'd0;
add1_in1[i] = A[i];
add1_in2[i] = mul_o[i];
add2_in1[i] = (accuY) ? Y[i] : 18'd0;
add2_in2[i] = add1_o[i];
// X_next [i] = vec_inX[i];
N_next [i] = A[i];
end
// ready = (counter==5'd1) ? 1'b1 : 1'b0;
//XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
end
pol_add : begin
counter_next = (counter>5'd6) ? 5'd0 : counter +5'd1;
ready = (counter==5'd7) ? 1'b1 : 1'b0;
//computation part
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = (N[0][i]==1'b1 && counter<5'd8 ) ? A[0] : 18'd0 ;
add2_in1[i] = (accuY) ? Y[i] : 18'd0;
add2_in2[i] = add1_o[i];
end
for ( i=0 ; i!=15 ; i=i+1 ) begin
add1_in2[i] = (N[0][i+1]==1'b1 && counter<5'd8 ) ? A[1] : 18'd0 ;
end
add1_in2[15] = (N[1][0]==1'b1 && counter<5'd8 ) ? A[1] : 18'd0 ;
if ( counter < 5'd8 ) begin
for ( i=0 ; i!=15 ; i=i+1 )
N_next[i] = { N[i+1][1:0] , N[i][15:2] };
N_next[15] = { X[0][1:0] , N[15][15:2] };
for ( i=0 ; i!=8 ; i=i+1 )
X_next[i] = { X[i+1][1:0] , X[i][15:2] };
X_next[8] = { 3'd0 , N[0][1:0] , X[8][12:2] };
for ( i=9 ; i!=16 ; i=i+1 )
X_next[i] = X[i] ;
end
else begin
for ( i=0 ; i!=16 ; i=i+1 ) begin
N_next[i] = N[i];
X_next[i] = X[i];
end
end
if ( counter>5'd6 ) begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = vec_inA[i];
end
else begin
for ( i=0 ; i!=14 ; i=i+1 )
A_next[i] = A[i+2];
A_next[14] = 16'd0;
A_next[15] = 16'd0;
end
end
mul : begin
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
if (expand==1'b1)
mul_in1[i] = A[0];
else
mul_in1[i] = A[i];
mul_in2[i] = X[i];
add1_in1[i] = 16'd0;
add1_in2[i] = mul_o[i];
add2_in1[i] = (accuY) ? Y[i][17:0] : 18'd0;
add2_in2[i] = add1_o[i][17:0];
end
end
add : begin
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = A[i];
add1_in2[i] = X[i];
add2_in1[i] = (accuY) ? Y[i][17:0] : 18'd0;
add2_in2[i] = add1_o[i];
end
end
sub : begin //Should be modified
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = A[i];
add1_in2[i] = ~X[i]+16'd1;
add2_in1[i] = (accuY) ? Y[i][17:0] : 18'd0;
add2_in2[i] = add1_o[i];
end
end
mod : begin
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = 18'd0;
add1_in2[i] = 18'd0;
add2_in1[i] = Y[i] % {inst_cur[23:19] , inst_cur[14:10]};
add2_in2[i] = add1_o[i];
end
//rotation control
for ( i=0 ; i!=15 ; i=i+1 )
N_next[i] = { N[i+1][12:0] , N[i][15:13] };
N_next[15] = { X[0][12:0] , N[15][15:13] };
for ( i=0 ; i!=7 ; i=i+1 )
X_next[i] = { X[i+1][12:0] , X[i][15:13] };
X_next[7] = { X[8][12:0] , X[7][15:13]};
X_next[8] = { 3'd0 , N[0][12:0] } ;
for ( i=9 ; i!=16 ; i=i+1 )
X_next[i] = X[i] ;
end
shuffle : begin
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = buf_44[A[i]];
add1_in2[i] = 18'd0;
add2_in1[i] = 18'd0;
add2_in2[i] = add1_o[i];
end
end
endcase
end
else begin
if ( comp_type==nop || comp_type==mov || comp_type[4:2]==stall ) begin
ready = hy_exe;
end
else begin
case (curstate)
state_p_a_1 : begin
counter_next = 5'd1;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = A[i];
add1_in2[i] = X[i];
add2_in1[i] = add1_o[i][15:0];
Y_next[i] = add2_o[i][16:0];
end
for ( i=1 ; i!=16 ; i=i+1 )
add2_in2[i] = add1_o[i-1][16];
add2_in2[0] = 18'd0;
end
state_p_s_N : begin
counter_next = 5'd1;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = Y[i][17:0];
add1_in2[i] = { 2'b11 , ~N[i] };
Y_next[i] = add2_o[i][15:0];
end
for ( i=1 ; i!=16 ; i=i+1 ) begin
add2_in1[i] = add1_o[i][17:0];
if (add1_o[i-1][17]==1'b1 && add1_o[i-1]!=-18'd1 )
add2_in2[i] = 18'd0;
else
add2_in2[i] = 18'd1;
end
add2_in1[0] = add1_o[0][17:0];
add2_in2[0] = 18'd1;
end
state_p_s_1 : begin
counter_next = 5'd1;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = A[i];
add1_in2[i] = { 2'b11 , ~X[i] };
Y_next[i] = add2_o[i][15:0];
end
for ( i=1 ; i!=16 ; i=i+1 ) begin
add2_in1[i] = add1_o[i][17:0];
if (add1_o[i-1][17]==1'b1 && add1_o[i-1][17:0]!=-18'd1 )
add2_in2[i] = 18'd0;
else
add2_in2[i] = 18'd1;
end
add2_in1[0] = add1_o[0][17:0];
add2_in2[0] = 18'd1;
end
state_p_a_N : begin
counter_next = 5'd1;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = Y[i][17:0];
add1_in2[i] = N[i];
add2_in1[i] = add1_o[i][15:0];
Y_next[i] = add2_o[i][16:0];
end
for ( i=1 ; i!=16 ; i=i+1 )
add2_in2[i] = add1_o[i-1][16];
add2_in2[0] = 18'd0;
end
state_p_m_0 : begin
counter_next = counter;
ready = 1'b0;
mul_in1[0] = A[0];
mul_in2[0] = X[0];
temp_next = mul_o[0][15:0];
Y_next[0] = { 1'b0 , mul_o[0][15:0] };
Y_next[1] = { 1'b0 , mul_o[0][31:16]};
end
state_p_m_1 : begin
counter_next = counter + 5'd1;
ready = 1'b0;
mul_in1[0] = temp;
mul_in2[0] = np;
for ( i=1 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = A[0];
mul_in2[i] = X[i];
add1_in1[i] = { 1'b0 , Y[i][16:0] };
add1_in2[i] = { 2'd0 , mul_o[i][15:0] };
add2_in1[i] = add1_o[i][17:0];
end
for ( i=2 ; i!=16 ; i=i+1 )
add2_in2[i] = { 2'd0 , mul_o[i-1][31:16] };
add2_in2[1] = 18'd0;
for ( i=1 ; i!=16 ; i=i+1 ) begin
Y_next[i] = add2_o[i];
end
Y_next[ 0] = Y[0];
Y_next[16] = mul_o[15][31:16];
temp_next = mul_o[0][15:0];
end
state_p_m_2 : begin
counter_next = counter;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = temp;
mul_in2[i] = N[i];
add1_in1[i] = Y[i][17:0];
add1_in2[i] = { 2'd0 , mul_o[i][15:0] };
end
add2_in1[0] = Y[16][17:0];
add2_in2[0] = { 2'd0 , mul_o[15][31:16] };
for ( i=1 ; i!=16 ; i=i+1 ) begin
add2_in1[i] = add1_o[i][17:0];
add2_in2[i] = { 2'd0 , mul_o[i-1][31:16] };
Y_next[i] = add2_o[i];
end
Y_next[ 0] = add1_o[0];
Y_next[16] = add2_o[0];
for( i=0 ; i!=15 ; i=i+1 )
A_next[i] = A[i+1];
A_next[15] = 16'd0;
end
state_p_m_3 : begin
counter_next = counter;
ready = 1'b0;
mul_in1[0] = A[0];
mul_in2[0] = X[0];
for ( i=1 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = { 2'd0 , Y[i][15:0]};
add1_in2[i] = { 15'd0 , Y[i-1][18:16]};
end
add1_in1[0] = { 2'd0 , Y[16][15:0]};
add1_in2[0] = { 15'd0 , Y[15][18:16]};
add2_in1[1] = add1_o[1][17:0];
add2_in2[1] = { 2'd0 , mul_o[0][15:0] };
add2_in1[2] = add1_o[2][17:0];
add2_in2[2] = { 2'd0 , mul_o[0][31:16] };
//should be mpdified to Y_next[i] = add2_o[i] for regular
for ( i=2 ; i!=15 ; i=i+1 )
Y_next[i] = add1_o[i+1];
Y_next[ 0] = add2_o[1];
Y_next[ 1] = add2_o[2];
Y_next[15] = add1_o[0];
Y_next[16] = 19'd0;
temp_next = add2_o[1][15:0];
end
state_write : begin
counter_next = 5'd0 ;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1) begin
vec_out[i] = Y[i][15:0];
Y_next[i] = (accuY) ? Y[i] : 19'd0;
// A_next[i] = vec_inA[i];
// X_next[i] = vec_inX[i];
end
end
default : begin
counter_next = 5'd0;
ready = 1'b0;
// ready = hy_exe;
for ( i=0 ; i!=16 ; i=i+1) begin
vec_out[i] = 16'd0;
// Y_next[i] = 19'd0;
// A_next[i] = 16'd0;
// X_next[i] = 16'd0;
end
end
endcase
end
end
end
//===============================Combinational Logic===============================//
always @ (*) begin
for (i=0 ; i<=15 ; i=i+1) begin
mul_o[i] = mul_in1[i] * mul_in2[i] ;
add1_o[i] = add1_in1[i] + add1_in2[i] ;
add2_o[i] = add2_in1[i] + add2_in2[i] ;
end
end
endmodule |
module which instantiates the sub-modules responsible for master controller operation:
counter=frequency counter (really, a period counter with inversion) for
determining the RF frequency from the square-wave input on "sig"
lut=look-up-table for mapping from a frequency to a capacitor state.
Currently, the same state number is assigned to both the series and parallel outputs
driver=responsible for mapping from look-up-table output to encoded
signal for decoder boards (in present implementation, no adjustment
needs to be made to lut output), and also determines whether the state
has settled and the cap boards may act on the change.
PIN ASSIGNMENT FOR EPM2210F256C5N (MANY MACROCELL CPLD)
To arrive at this pin assignment,
(1) consult pin assignment for CapBoardDecoder (for tuning code pins) OR "BurkeCPLDBoardConfigurationTemplate.doc" (for signal input)
(2) map to pins on standard 84-pin CPLD
(3) consult Bill Parkin's 84-256-pin adapter schematic to map to 256-pin pin values.
Ok clk Location PIN_H5 Yes
Ok sig Location PIN_K1 Yes (PIN_04 on socket - see Willy Burke's doc and note we are using Slot 1 for sync input on board front panel)
Ok enableSer Location PIN_F1 Yes AC24 on backplane
Ok enablePar Location PIN_G1 Yes AC25
Ok codeSer[0] Location PIN_R16 Yes AC3
Ok codeSer[1] Location PIN_L16 Yes AC6
Ok codeSer[2] Location PIN_E16 Yes AC9
Ok codeSer[3] Location PIN_A13 Yes AC12
Ok codeSer[4] Location PIN_A8 Yes AC15
Ok codeSer[5] Location PIN_A5 Yes AC18
Ok codeSer[6] Location PIN_B1 Yes AC21
Ok codePar[0] Location PIN_N16 Yes AC4
Ok codePar[1] Location PIN_G16 Yes AC7
Ok codePar[2] Location PIN_D16 Yes AC10
Ok codePar[3] Location PIN_A12 Yes AC13
Ok codePar[4] Location PIN_A7 Yes AC16
Ok codePar[5] Location PIN_A4 Yes AC19
Ok codePar[6] Location PIN_D1 Yes AC22
Ok ioPowerEnable Location PIN_T12 Yes Connects to I/O 27. This needs a signal - e.g. clock divided down - to demonstrate CPLD is working. But really should go to Pin56 out of CPLD - this is not connected to 256-pin CPLD, so need to make a jumper wire on board.
Ok clkEnable Location PIN_T15 Yes Connects to I/O 28. The clock needs Pin73 out of CPLD to be high to work, but Pin73 is not connected to 256-pin CPLD, so need to make a hardware jumper on the board.
Ok serCodeOutput Location PIN_N1 Yes Encodes the logic state for the series capacitors into a time series going out on LEMO I/O 4
Ok parCodeOutput Location PIN_T2 Yes Encodes the logic state for the series capacitors into a time series going out on LEMO I/O 4
Ok nclkOutput Location PIN_T4 Yes Encodes n_clk - the number of clock counts in a signal count period. Goes out on I/O #6 - J16 on 84-pin footprint, and connected to PIN_T4 on 256 pin adapter.
Ted Golfinopoulos, pin assignment made on 24 Oct 2011
Revised 9 January 2012
*/
input clk, sig; //1 bit inputs corresponding to clk and RF signal.
output wire [6:0] codeSer, codePar; //Capacitor state encoded in a number which is interpreted by CapBoardDecoder to determine which caps to turn on.
output enableSer, enablePar; //"Ready" bits indicating codes are ready for decoding.
output ioPowerEnable; //Bit which receives clock-like signal and allows IO circuitry to receive power on LH timing board.
output clkEnable; //Bit which, when high, enables clock.
output serCodeOutput; //Bit containing encoded version of serial cap code.
output parCodeOutput; //Bit containing encoded version of parallel cap code.
output nclkOutput; //Bit containing (time)-encoded version of clock counts per M signal count period.
//wire [13:0] f; //Frequency of sig IN HUNDREDS OF Hz, need 4 significant decimal figures.
wire [13:0] n_clk; //Frequency of sig IN HUNDREDS OF Hz, need 4 significant decimal figures.
wire [6:0] stateSer; //Intermediate variable to hold lut output for series levels.
wire [6:0] statePar; //Intermediate variable to hold lut output for parallel levels.
reg [4:0] clkCntr; //Divide clock signal down.
initial begin
#0
clkCntr=4'b0; //Initialize clock counter.
end
//Instantiate frequency counter object.
//counter c(clk, sig, f); //Use period counter instead of frequency counter.
//fcounter c(clk, sig, f); //Use frequency counter instead of period counter.
counter_n c(clk, sig, n_clk); //Use period counter, but don't use division step. Instead, pass number of clock counts.
//10 August 2012 double clock speed and halve number of signal edges so that matching
//network can respond faster to frequency chances.
defparam c.M=25; //Number of signal edges counted inside period counter.
defparam c.F_CLK=80000; //Clock frequency in hundreds of Hz.
//79 corner frequencies in HUNDREDS OF Hz,
//from about 50 kHz (500 hundred Hz) to 300 kHz (3000 hundred Hz)
//Instantiate look-up table which determines state from frequency.
//lut tab(clk,f,state);
lut_n tabSer(clk,n_clk,stateSer); //Tell series lut to use table 1
lut_n tabPar(clk,n_clk,statePar); //Tell parallel lut to use table 2
defparam tabSer.LOOKUP_ID=1; //Tell series lut to use table 1
defparam tabPar.LOOKUP_ID=2; //Tell parallel lut to use table 2
//defparam tabSer.OFFSET=4'b1000;
//defparam tabPar.OFFSET=4'b0111;
//lut_n tabSer(clk,n_clk,stateSer);
//lut_n tabPar(clk,n_clk,statePar);
//At this point, the look-up table outputs a state in the same format required for the encoded cap states, and
//the cap index for the series board is the same as for the parallel board.
assign codeSer=stateSer;
assign codePar=statePar;
//Instantiate drivers for serial and parallel states - primarily, this determines when the states are ready for decoding by CapBoardDecoder.
driver dSer(clk, codeSer, enableSer);
driver dPar(clk, codePar, enablePar);
//Instantiate encoders to put out the series and parallel codes in a pulse sequence on the LEMO outputs.
//Give a slower version of clock so that the digitizer, with 2.5 MHz sample rate, can resolve the pulses.
stateEncoder seriesStateEncoder(clkCntr[4], codeSer, enableSer, serCodeOutput);
stateEncoder parallelStateEncoder(clkCntr[4], codePar, enablePar, parCodeOutput);
defparam nclkEncoder.STATE_LENGTH=4'b1110; //Need to redefine the parameter dictating the size of the bit pattern to encode.
stateEncoder nclkEncoder(clkCntr[4], n_clk, enableSer, nclkOutput); //Instantiate encoder for n_clk
always @(posedge clk) begin
clkCntr=clkCntr+4'b1; //Increment clock counter.
end
//Give ioPowerEnable bit a divided version of the clock. The rationale behind this is
//that (a) the ioPowerEnable bit needs a clock-like signal and (b) you should do an operation
//on the clock to prove that the CPLD is working (otherwise synthesis can just connect a wire,
//and so passing the clock to the ioPowerEnable bit may not demonstrate functionality). This
//is in accordance with the new version of the LH Timing Board. Pin 56 on the CPLD must receive
//the ioPowerEnable bit.
assign ioPowerEnable=clkCntr[1];
assign clkEnable=1'b1;
endmodule |
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule |
module sky130_fd_sc_ls__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module altpcie_pcie_reconfig_bridge (
input [ 7: 0] avs_pcie_reconfig_address,
input avs_pcie_reconfig_chipselect,
input avs_pcie_reconfig_write,
input [ 15: 0] avs_pcie_reconfig_writedata,
output reg avs_pcie_reconfig_waitrequest,
input avs_pcie_reconfig_read,
output reg [15: 0] avs_pcie_reconfig_readdata,
output reg avs_pcie_reconfig_readdatavalid,
input avs_pcie_reconfig_clk, // 50 MHz
input avs_pcie_reconfig_rstn,
// DPRIO Interface
output reg dpriodisable,
output reg dprioin,
output reg dprioload,
output dpclk,
input dprioout
);
parameter device_address=0;
parameter port_address =0;
parameter base_address =0;
parameter implement_address_checking =1;
localparam IDLE_ST =0,
CHECK_ADDR_ST =1,
MDIO_START_ST =2,
CTRL_WR_ST =3,
CTRL_RD_ST =4,
ERR_ST =5,
MDIO_CLR_ST =6,
MDIO_PRE_ST =7,
MDIO_FRAME_ST =8,
CLEAR_WAITREQ_ST =9;
localparam MDIO_ADDR =2'b00,
MDIO_WRITE =2'b01,
MDIO_READ =2'b10,
MDIO_END =2'b11;
reg [3:0] cstate;
reg [3:0] nstate;
reg [1:0] error_status;
reg [4:0] hip_dev_addr;
reg [4:0] hip_port_addr;
reg [7:0] hip_base_addr;
reg [31:0] shift_dprioin;
reg [15:0] shift_dprioout;
reg [6:0] count_mdio_st;
reg [1:0] mdio_cycle;
reg read_cycle;
reg write_cycle;
wire valid_address;
reg valid_addrreg;
reg extended_dprio_access;
assign dpclk = avs_pcie_reconfig_clk;
// state machine
always @*
case (cstate)
//TODO : Confirm that Avalon-MM read and write at the same time is illegal
//TODO : Confirm that read or write, chipselect can not be de-asserted until
// waitrequest is de-asserted
IDLE_ST: begin
if ((avs_pcie_reconfig_readdatavalid==1'b0)&&(avs_pcie_reconfig_chipselect==1'b1))
nstate <= CHECK_ADDR_ST;
else
nstate <= IDLE_ST;
end
CHECK_ADDR_ST:
begin
if (valid_address==1'b0)
nstate <= ERR_ST;
else if (avs_pcie_reconfig_address[7] == 1'b1)
nstate <= MDIO_START_ST;
else if (write_cycle==1'b1)
nstate <= CTRL_WR_ST;
else if (read_cycle==1'b1)
nstate <= CTRL_RD_ST;
else
nstate <= IDLE_ST;
end
MDIO_START_ST:
nstate <= MDIO_CLR_ST;
CTRL_WR_ST:
nstate <= CLEAR_WAITREQ_ST;
CTRL_RD_ST:
nstate <= CLEAR_WAITREQ_ST;
ERR_ST:
nstate <= CLEAR_WAITREQ_ST;
MDIO_CLR_ST:
//send 16 zero's to clear the MDIO state machine
//TODO : Check if it's necessary for every read/write transaction or if it's only
// necessary after the first reset
if (count_mdio_st==0) begin
if (mdio_cycle==MDIO_END)
nstate <= CLEAR_WAITREQ_ST;
else
nstate <= MDIO_PRE_ST;
end
else
nstate <= MDIO_CLR_ST;
MDIO_PRE_ST:
// Preamble 32-bit 1's
if (count_mdio_st==0)
nstate <= MDIO_FRAME_ST;
else
nstate <= MDIO_PRE_ST;
MDIO_FRAME_ST:
if (count_mdio_st==0) begin
if (mdio_cycle==MDIO_END)
nstate <= MDIO_CLR_ST;
else
nstate <= MDIO_PRE_ST;
end
else
nstate <= MDIO_FRAME_ST;
CLEAR_WAITREQ_ST:
nstate <= IDLE_ST;
default:
nstate <= IDLE_ST;
endcase
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
cstate <= IDLE_ST;
else
cstate <= nstate;
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
mdio_cycle <= MDIO_ADDR;
else if (cstate==MDIO_START_ST)
mdio_cycle <= MDIO_ADDR;
else if ((cstate==MDIO_FRAME_ST) && (count_mdio_st==6'h1F)) begin
if ((mdio_cycle==MDIO_ADDR) && (write_cycle==1'b1))
mdio_cycle <= MDIO_WRITE;
else if ((mdio_cycle==MDIO_ADDR) && (read_cycle==1'b1))
mdio_cycle <= MDIO_READ;
else if ((mdio_cycle==MDIO_WRITE) || (mdio_cycle==MDIO_READ))
mdio_cycle <= MDIO_END;
end
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
//TODO Use multiple counter if speed is an issue
if (avs_pcie_reconfig_rstn==1'b0)
count_mdio_st <= 0;
else if (cstate==MDIO_START_ST)
count_mdio_st <= 6'hF;
else if (cstate==MDIO_CLR_ST) begin
if (count_mdio_st>0)
count_mdio_st<=count_mdio_st-1;
else
count_mdio_st<=6'h1F;
end
else if ((cstate==MDIO_PRE_ST)||(cstate==MDIO_FRAME_ST)) begin
if (count_mdio_st>0)
count_mdio_st<=count_mdio_st-1;
else if (mdio_cycle==MDIO_END)
count_mdio_st <= 6'hF;
else
count_mdio_st<=6'h1F;
end
else
count_mdio_st <= 0;
end
// MDIO dprioin, dprioload
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
shift_dprioin <= 32'h0;
else if (cstate==MDIO_PRE_ST) begin
// ST bits - Start of frame
shift_dprioin[31:30]<=2'b00;
// OP bits - Op Codes
if (mdio_cycle==MDIO_ADDR)
shift_dprioin[29:28]<=2'b00;
else if (mdio_cycle == MDIO_WRITE)
shift_dprioin[29:28]<=2'b01;
else // READ
shift_dprioin[29:28]=2'b11;
// Port, Device address
shift_dprioin[27:18] <= {port_address[4:0], device_address[4:0]};
// TA Bits Turnaround
// TODO : Check TA bit 0 which supposed to be Z for read?
shift_dprioin[17:16] <= 2'b10;
if (mdio_cycle==MDIO_ADDR)
// 0x80 is the range for vendor specific (altera) registers according to XAUI spec
shift_dprioin[15:0] = {8'h80,1'b0,avs_pcie_reconfig_address[6:0]};
else if (mdio_cycle==MDIO_WRITE)
shift_dprioin[15:0] = avs_pcie_reconfig_writedata[15:0];
else if (mdio_cycle==MDIO_READ)
shift_dprioin[15:0] = avs_pcie_reconfig_writedata[15:0];
end
else if (cstate==MDIO_FRAME_ST)
shift_dprioin[31:0] <= {shift_dprioin[30:0],1'b0};
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0) begin
dprioin <= 1'b0;
end
else if (cstate==MDIO_CLR_ST) begin
if (count_mdio_st>0)
dprioin <= 1'b0;
else if (mdio_cycle==MDIO_END)
dprioin <= 1'b0;
else
dprioin <= 1'b1;
end
else if (cstate==MDIO_PRE_ST) begin
if (count_mdio_st>0)
dprioin <= 1'b1;
else
dprioin <= shift_dprioin[31];
end
else if (cstate==MDIO_FRAME_ST) begin
// MDIO : MSB first
if (count_mdio_st>0)
dprioin <= shift_dprioin[30];
else if (mdio_cycle==MDIO_END)
dprioin <=1'b0;
else
dprioin <=1'b1;
end
else
dprioin <= 1'b0;
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
shift_dprioout <= 16'h0;
else
shift_dprioout[15:0] <= {shift_dprioout[14:0],dprioout};
end
// MDIO and status registers dpriodisable , dprioload
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0) begin
dpriodisable <= 1'b1;
dprioload <= 1'b0;
extended_dprio_access <=1'b0;
end
else if ((cstate==CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h00 )) begin
dpriodisable <= avs_pcie_reconfig_writedata[0];
dprioload <= ~avs_pcie_reconfig_writedata[0];
end
else if ((cstate==CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h03 )) begin
extended_dprio_access <= (avs_pcie_reconfig_writedata==16'hED10)?1'b1:1'b0;
end
end
// Avalon-MM Wait request
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
avs_pcie_reconfig_waitrequest <= 1'b1;
else if (nstate == CLEAR_WAITREQ_ST)
avs_pcie_reconfig_waitrequest <= 1'b0;
else
avs_pcie_reconfig_waitrequest <= 1'b1;
end
// Error Status registers
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
error_status[1:0] <= 2'b00;
else if (cstate==ERR_ST) begin
if (write_cycle==1'b1)
error_status[0] <= 1'b1;
if (read_cycle==1'b1)
error_status[1] <= 1'b1;
end
else if ((cstate == CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h00))
// Clear error status registers
error_status[1:0] <= avs_pcie_reconfig_writedata[3:2];
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0) begin
// Default parameter
hip_dev_addr <= device_address;
hip_port_addr <= port_address;
end
else if ((cstate==CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h01 )) begin
hip_dev_addr <= avs_pcie_reconfig_writedata[4:0];
hip_port_addr <= avs_pcie_reconfig_writedata[9:5];
end
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
// Default parameter
hip_base_addr <= base_address;
else if ((cstate==CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h02 ))
hip_base_addr <= avs_pcie_reconfig_writedata[7:0];
end
always @ (posedge avs_pcie_reconfig_clk) begin
if (cstate==IDLE_ST)
avs_pcie_reconfig_readdata <= 16'hFFFF;
else if (cstate==CTRL_RD_ST)
case (avs_pcie_reconfig_address[6:0])
7'h0 : avs_pcie_reconfig_readdata <= {12'h0,error_status[1:0], 1'b0, dpriodisable};
7'h1 : avs_pcie_reconfig_readdata <= {6'h0,hip_dev_addr[4:0], hip_port_addr[4:0]};
7'h2 : avs_pcie_reconfig_readdata <= {8'h0,hip_base_addr[7:0]};
7'h3 : avs_pcie_reconfig_readdata <= 16'hFADE;
default : avs_pcie_reconfig_readdata <= 16'hFFFF;
endcase
else if ((cstate==MDIO_CLR_ST)&&(count_mdio_st==6'hF))
avs_pcie_reconfig_readdata <= shift_dprioout;
end
always @ (posedge avs_pcie_reconfig_clk) begin
if ((cstate==CLEAR_WAITREQ_ST)&&(read_cycle==1'b1))
avs_pcie_reconfig_readdatavalid <=1'b1;
else
avs_pcie_reconfig_readdatavalid <=1'b0;
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0) begin
read_cycle <= 1'b0;
write_cycle <= 1'b0;
end
else if ((cstate==IDLE_ST) && (avs_pcie_reconfig_chipselect==1'b1)) begin
read_cycle <= avs_pcie_reconfig_read;
write_cycle <= avs_pcie_reconfig_write;
end
end
assign valid_address = (implement_address_checking==0)?1'b1:valid_addrreg;
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
valid_addrreg <= 1'b1;
else if (cstate==IDLE_ST) begin
if (avs_pcie_reconfig_address[7]==1'b0) begin
// Control register address space
if (avs_pcie_reconfig_address[6:0] > 7'h4)
valid_addrreg <=1'b0;
else
valid_addrreg <=1'b1;
end
else begin
// MDIO register HIP address space
if ((avs_pcie_reconfig_address[6:0] < 7'h9) && (extended_dprio_access==1'b0))
valid_addrreg <=1'b0;
else if ((avs_pcie_reconfig_address[6:0] > 7'h5E) && (extended_dprio_access==1'b0))
valid_addrreg <=1'b0;
else if ((avs_pcie_reconfig_address[6:0]>7'h40)&&(avs_pcie_reconfig_address[6:0]<7'h59) && (extended_dprio_access==1'b0))
valid_addrreg <=1'b0;
else
valid_addrreg <=1'b1;
end
end
end
endmodule |
module system_vga_pll_0_0(clk_100, clk_50, clk_25, clk_12_5, clk_6_25)
/* synthesis syn_black_box black_box_pad_pin="clk_100,clk_50,clk_25,clk_12_5,clk_6_25" */;
input clk_100;
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
endmodule |
module sky130_fd_sc_hs__nand2b_4 (
Y ,
A_N ,
B ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__nand2b_4 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule |
module! */
parameter ethernet = 1'b0;
/* Bus cycles from the ep9302 processor come in to the FPGA multiplexed by
* the MAX2 CPLD on the TS-7300. Any access on the ep9302 for addresses
* 0x72000000 - 0x72ffffff are routed to the FPGA. The ep9302 CS7 SMCBCR register
* at 0x8008001c physical should be set to 0x10004508 -- 16-bit,
* ~120 nS bus cycle. The FPGA must be loaded and sending 75Mhz to the MAX2
* on clk_75mhz_pad before any bus cycles are attempted.
*
* Since the native multiplexed bus is a little unfriendly to deal with
* and non-standard, as our first order of business we translate it into
* something more easily understood and better documented: a 16 bit WISHBONE bus.
*/
reg epwbm_done, epwbm_done32;
reg isa_add1_pad_q;
reg [23:0] ep93xx_address;
reg epwbm_we_o, epwbm_stb_o;
wire [23:0] epwbm_adr_o;
reg [15:0] epwbm_dat_o;
reg [15:0] epwbm_dat_i;
reg [15:0] ep93xx_dat_latch;
reg epwbm_ack_i;
wire epwbm_clk_o = clk_75mhz_pad;
wire epwbm_cyc_o = start_cycle_posedge_q;
wire ep93xx_databus_oe = !epwbm_we_o && start_cycle_posedge && !bd_oe_pad;
wire pll_locked, clk_150mhz;
wire epwbm_rst_o = !pll_locked;
assign fl_d_pad[7:0] = ep93xx_databus_oe ?ep93xx_dat_latch[7:0] : 8'hzz;
assign bd_pad[7:0] = ep93xx_databus_oe ?ep93xx_dat_latch[15:8] : 8'hzz;
assign isa_wait_pad = start_cycle_negedge ? epwbm_done : 1'bz;
assign epwbm_adr_o[23:2] = ep93xx_address[23:2];
reg ep93xx_address1_q;
assign epwbm_adr_o[0] = ep93xx_address[0];
assign epwbm_adr_o[1] = ep93xx_address1_q;
/* Use Altera's PLL to multiply 25Mhz from the ethernet PHY to 75Mhz */
pll clkgencore(
.inclk0(clk_25mhz_pad),
.c0(clk_150mhz),
.c1(clk_75mhz_pad),
.locked(pll_locked)
);
reg ep93xx_end, ep93xx_end_q;
reg start_cycle_negedge, start_cycle_posedge, bd_oe_negedge,
bd_oe_posedge;
reg start_cycle_negedge_q, start_cycle_posedge_q;
reg bd_oe_negedge_q, bd_oe_posedge_q;
always @(posedge clk_75mhz_pad)
begin
start_cycle_negedge_q <= start_cycle_negedge;
start_cycle_posedge_q <= start_cycle_posedge;
bd_oe_negedge_q <= bd_oe_negedge;
bd_oe_posedge_q <= bd_oe_posedge;
isa_add1_pad_q <= isa_add1_pad;
if ((bd_oe_negedge_q && epwbm_we_o) ||
(start_cycle_posedge_q && !epwbm_we_o) && !epwbm_done)
begin
epwbm_stb_o <= 1'b1;
ep93xx_address1_q <= isa_add1_pad_q;
epwbm_dat_o <= {bd_pad[7:0], fl_d_pad[7:0]};
end
if (epwbm_stb_o && epwbm_ack_i)
begin
epwbm_stb_o <= 1'b0;
epwbm_done <= 1'b1;
ep93xx_dat_latch <= epwbm_dat_i;
end
if (epwbm_done && !epwbm_done32 &&
(ep93xx_address[1] !=isa_add1_pad_q))
begin
epwbm_done <= 1'b0;
epwbm_done32 <= 1'b1;
end
ep93xx_end_q <= 1'b0;
if ((start_cycle_negedge_q && start_cycle_posedge_q &&
bd_oe_negedge_q && bd_oe_posedge) || !pll_locked)
begin
ep93xx_end <= 1'b1;
ep93xx_end_q <= 1'b0;
end
if (ep93xx_end)
begin
ep93xx_end <= 1'b0;
ep93xx_end_q <= 1'b1;
epwbm_done32 <= 1'b0;
epwbm_stb_o <= 1'b0;
epwbm_done <= 1'b0;
start_cycle_negedge_q <= 1'b0;
start_cycle_posedge_q <= 1'b0;
bd_oe_negedge_q <= 1'b0;
bd_oe_posedge_q <= 1'b0;
end
end
wire start_cycle_negedge_aset = !start_cycle_pad && pll_locked;
always @(posedge ep93xx_end_q or posedge start_cycle_negedge_aset)
begin
if (start_cycle_negedge_aset)
start_cycle_negedge <= 1'b1;
else start_cycle_negedge <= 1'b0;
end
always @(posedge start_cycle_pad or posedge ep93xx_end_q)
begin
if (ep93xx_end_q)
start_cycle_posedge <= 1'b0;
else
if (start_cycle_negedge)
start_cycle_posedge <= 1'b1;
end
always @(posedge start_cycle_pad)
begin
epwbm_we_o <= fl_d_pad[7];
ep93xx_address[23] <= fl_d_pad[0];
ep93xx_address[22] <= fl_d_pad[1];
ep93xx_address[21] <= fl_d_pad[2];
ep93xx_address[20:17] <= add_pad[3:0];
ep93xx_address[16] <= fl_d_pad[3];
ep93xx_address[15] <= isa_add15_pad;
ep93xx_address[14] <= isa_add14_pad;
ep93xx_address[13] <= fl_d_pad[4];
ep93xx_address[12] <= isa_add12_pad;
ep93xx_address[11] <= isa_add11_pad;
ep93xx_address[10] <= bd_pad[0];
ep93xx_address[9] <= bd_pad[1];
ep93xx_address[8] <= bd_pad[2];
ep93xx_address[7] <= bd_pad[3];
ep93xx_address[6] <= bd_pad[4];
ep93xx_address[5] <= bd_pad[5];
ep93xx_address[4] <= bd_pad[6];
ep93xx_address[3] <= bd_pad[7];
ep93xx_address[2] <= fl_d_pad[5];
ep93xx_address[1] <= isa_add1_pad;
ep93xx_address[0] <= fl_d_pad[6];
end
always @(negedge bd_oe_pad or posedge ep93xx_end_q)
begin
if (ep93xx_end_q)
bd_oe_negedge <= 1'b0;
else
if (start_cycle_posedge)
bd_oe_negedge <= 1'b1;
end
always @(posedge bd_oe_pad or posedge ep93xx_end_q)
begin
if (ep93xx_end_q)
bd_oe_posedge <= 1'b0;
else
if (bd_oe_negedge)
bd_oe_posedge <= 1'b1;
end
wire [15:0] epwbm_wb32m_bridgecore_dat;
wire epwbm_wb32m_bridgecore_ack;
wire [31:0] wb32m_dat_o;
reg [31:0] wb32m_dat_i;
wire [21:0] wb32m_adr_o;
wire [3:0] wb32m_sel_o;
wire wb32m_cyc_o, wb32m_stb_o, wb32m_we_o;
reg wb32m_ack_i;
wire wb32m_clk_o = epwbm_clk_o;
wire wb32m_rst_o = epwbm_rst_o;
wb32_bridge epwbm_wb32m_bridgecore
(
.wb_clk_i(epwbm_clk_o),
.wb_rst_i(epwbm_rst_o),
.wb16_adr_i(epwbm_adr_o[23:1]),
.wb16_dat_i(epwbm_dat_o),
.wb16_dat_o(epwbm_wb32m_bridgecore_dat),
.wb16_cyc_i(epwbm_cyc_o),
.wb16_stb_i(epwbm_stb_o),
.wb16_we_i(epwbm_we_o),
.wb16_ack_o(epwbm_wb32m_bridgecore_ack),
.wbm_adr_o(wb32m_adr_o),
.wbm_dat_o(wb32m_dat_o),
.wbm_dat_i(wb32m_dat_i),
.wbm_cyc_o(wb32m_cyc_o),
.wbm_stb_o(wb32m_stb_o),
.wbm_we_o(wb32m_we_o),
.wbm_ack_i(wb32m_ack_i),
.wbm_sel_o(wb32m_sel_o)
);
/* At this point we have turned the multiplexed ep93xx bus cycle into a
* WISHBONE master bus cycle with the local regs/wires:
*
* [15:0] epwbm_dat_i -- WISHBONE master 16-bit databus input
* [15:0] epwbm_dat_o -- WISHBONE master 16-bit databus output
* epwbm_clk_o -- WISHBONE master clock output (75 Mhz)
* epwbm_rst_o -- WISHBONE master reset output
* [23:0] epwbm_adr_o -- WISHBONE byte address output
* epwbm_we_o -- WISHBONE master write enable output
* epwbm_stb_o -- WISHBONE master strobe output
* epwbm_cyc_o -- WISHBONE master cycle output
* epwbm_ack_i -- WISHBONE master ack input
*
* The WISHBONE slave or WISHBONE interconnect can withhold the bus cycle ack
* as long as necessary as the above logic will ensure the processor will be
* halted until the cycle is complete. In that regard, it is possible
* to lock up the processor if nothing acks the WISHBONE bus cycle. (!)
*
* Note that the above is only a 16-bit WISHBONE bus. A special WISHBONE
* to WISHBONE bridge is used to combine two back-to-back 16 bit reads or
* writes into a single atomic 32-bit WISHBONE bus cycle. Care should be
* taken to never issue a byte or halfword ARM insn (ldrh, strh, ldrb, strb) to
* address space handled here. This bridge is presented as a secondary
* WISHBONE master bus prefixed with wb32m_:
*
* [31:0] wb32m_dat_i -- WISHBONE master 32-bit databus input
* [31:0] wb32m_dat_o -- WISHBONE master 32-bit databus output
* wb32m_clk_o -- WISHBONE master clock output (75 Mhz)
* wb32m_rst_o -- WISHBONE master reset output
* [21:0] wb32m_adr_o -- WISHBONE master word address
* wb32m_we_o -- WISHBONE master write enable output
* wb32m_stb_o -- WISHBONE master strobe output
* wb32m_cyc_o -- WISHBONE master cycle output
* wb32m_ack_i -- WISHBONE master ack input
* wb32m_sel_o -- WISHBONE master select output -- always 4'b1111
*/
/******************************************************************
* blue_pad, green_pad etc, etc are the physical pin I/Os.
* headerpin_o is the data to be output.
* headerpin_oe should be the tristate control.
* headerpin_i should be the incoming data
* This is a hacked version to try and get the I/O tristate
* control to synthesise properly :(
*******************************************************/
wire [31:0] usercore_dat;
wire usercore_ack;
reg usercore_stb;
wire [40:1] headerpin_i;
reg [40:1] temp_reg;
wire [40:1] headerpin_oe, headerpin_o;
integer i;
// grab the current inputs
assign headerpin_i[1] = blue_pad[0];
assign headerpin_i[3] = blue_pad[1];
assign headerpin_i[5] = blue_pad[2];
assign headerpin_i[7] = blue_pad[3];
assign headerpin_i[9] = blue_pad[4];
assign headerpin_i[11] = green_pad[0];
assign headerpin_i[13] = green_pad[1];
assign headerpin_i[15] = green_pad[2];
assign headerpin_i[17] = green_pad[3];
assign headerpin_i[19] = green_pad[4];
assign headerpin_i[4] = red_pad[0];
assign headerpin_i[6] = red_pad[1];
assign headerpin_i[8] = red_pad[2];
assign headerpin_i[10] = red_pad[3];
assign headerpin_i[12] = red_pad[4];
assign headerpin_i[21] = dio0to8_pad[0];
assign headerpin_i[23] = dio0to8_pad[1];
assign headerpin_i[25] = dio0to8_pad[2];
assign headerpin_i[27] = dio0to8_pad[3];
assign headerpin_i[29] = dio0to8_pad[4];
assign headerpin_i[31] = dio0to8_pad[5];
assign headerpin_i[33] = dio0to8_pad[6];
assign headerpin_i[35] = dio0to8_pad[7];
assign headerpin_i[37] = dio0to8_pad[8];
assign headerpin_i[24] = dio10to17_pad[0];
assign headerpin_i[26] = dio10to17_pad[1];
assign headerpin_i[28] = dio10to17_pad[2];
assign headerpin_i[30] = dio10to17_pad[3];
assign headerpin_i[32] = dio10to17_pad[4];
assign headerpin_i[34] = dio10to17_pad[5];
assign headerpin_i[36] = dio10to17_pad[6];
assign headerpin_i[38] = dio10to17_pad[7];
assign headerpin_i[39] = dio9_pad;
assign headerpin_i[14] = hsync_pad;
assign headerpin_i[16] = vsync_pad;
// misc fixed values
assign headerpin_i[22] = 1'b0;
assign headerpin_i[40] = 1'b1;
assign headerpin_i[2] = 1'b0;
assign headerpin_i[20] = 1'b1;
assign headerpin_i[18] = 1'b0;
// assign outputs or tristates
assign blue_pad[0] = temp_reg[1];
assign blue_pad[1] = temp_reg[3];
assign blue_pad[2] = temp_reg[5];
assign blue_pad[3] = temp_reg[7];
assign blue_pad[4] = temp_reg[9];
assign green_pad[0] = temp_reg[11];
assign green_pad[1] = temp_reg[13];
assign green_pad[2] = temp_reg[15];
assign green_pad[3] = temp_reg[17];
assign green_pad[4] = temp_reg[19];
assign red_pad[0] = temp_reg[4];
assign red_pad[1] = temp_reg[6];
assign red_pad[2] = temp_reg[8];
assign red_pad[3] = temp_reg[10];
assign red_pad[4] = temp_reg[12];
assign vsync_pad = temp_reg[16];
assign hsync_pad = temp_reg[14];
assign dio0to8_pad[0] = temp_reg[21];
assign dio0to8_pad[1] = temp_reg[23];
assign dio0to8_pad[2] = temp_reg[25];
assign dio0to8_pad[3] = temp_reg[27];
assign dio0to8_pad[4] = temp_reg[29];
assign dio0to8_pad[5] = temp_reg[31];
assign dio0to8_pad[6] = temp_reg[33];
assign dio0to8_pad[7] = temp_reg[35];
assign dio0to8_pad[8] = temp_reg[37];
assign dio10to17_pad[0] = temp_reg[24];
assign dio10to17_pad[1] = temp_reg[26];
assign dio10to17_pad[2] = temp_reg[28];
assign dio10to17_pad[3] = temp_reg[30];
assign dio10to17_pad[4] = temp_reg[32];
assign dio10to17_pad[5] = temp_reg[34];
assign dio10to17_pad[6] = temp_reg[36];
assign dio10to17_pad[7] = temp_reg[38];
always @( headerpin_o or headerpin_oe )
begin
for (i = 0; i < 5; i = i + 1)
begin
if (headerpin_oe[1 + (i * 2)])
temp_reg[1+(i*2)] =headerpin_o[1 + (i * 2)];
else
temp_reg[1 + (i * 2)] = 1'bz;
if (headerpin_oe[11 + (i * 2)])
temp_reg[11 + (i * 2)] = headerpin_o[11 + (i * 2)];
else
temp_reg[11 + (i * 2)] = 1'bz;
if (headerpin_oe[4 + (i * 2)])
temp_reg[4 + (i * 2)] = headerpin_o[4 + (i * 2)];
else
temp_reg[4 + (i * 2)] = 1'bz;
end
for (i = 0; i < 8; i = i + 1)
begin
if (headerpin_oe[24 + (i * 2)])
temp_reg[24 + (i * 2)] = headerpin_o[24 + (i * 2)];
else
temp_reg[24 + (i * 2)] = 1'bz;
if (headerpin_oe[21 + (i * 2)])
temp_reg[21 + (i * 2)] = headerpin_o[21 + (i * 2)];
else
temp_reg[21 + (i * 2)] = 1'bz;
end
if (headerpin_oe[14])
temp_reg[14] = headerpin_o[14];
else
temp_reg[14] = 1'bz;
if (headerpin_oe[16])
temp_reg[16] = headerpin_o[16];
else
temp_reg[16] = 1'bz;
if (headerpin_oe[37])
temp_reg[37] = headerpin_o[37];
else
temp_reg[37] = 1'bz;
end
wire usercore_drq, usercore_irq;
// SDRAM
wire [12:0] uc_sdram_add_pad;
wire uc_sdram_ras_pad;
wire uc_sdram_cas_pad;
wire uc_sdram_we_pad;
wire [1:0] uc_sdram_ba_pad;
wire [15:0] uc_sdram_data_pad_i;
wire [15:0] uc_sdram_data_pad_o;
reg uc_sdram_data_pad_oe;
////////////////////////////////////////////////////////////////////////
// this is the interface to your component. It shouldn't need changing//
////////////////////////////////////////////////////////////////////////
ts7300_usercore usercore
(
.wb_clk_i(wb32m_clk_o),
.wb_rst_i(wb32m_rst_o),
.wb_cyc_i(wb32m_cyc_o),
.wb_stb_i(usercore_stb),
.wb_we_i(wb32m_we_o),
.wb_ack_o(usercore_ack),
.wb_dat_o(usercore_dat),
.wb_dat_i(wb32m_dat_o),
.wb_adr_i(wb32m_adr_o),
.headerpin_i(headerpin_i[40:1]),
.headerpin_o(headerpin_o[40:1]),
.headerpin_oe_o(headerpin_oe[40:1]),
.irq_o(usercore_irq),
.sdram_ras_o( sdram_ras_pad ),
.sdram_cas_o( sdram_cas_pad ),
.sdram_we_n_o( sdram_we_pad ),
.sdram_ba_o( sdram_ba_pad ),
.sdram_saddr_o( sdram_add_pad ),
.sdram_sdata_i( uc_sdram_data_pad_i ),
.sdram_sdata_o( uc_sdram_data_pad_o ),
.sdram_sdata_oe( uc_sdram_data_pad_oe )
);
/* IRQ7 is actually ep9302 VIC IRQ #40 */
assign irq7_pad = ( usercore_irq ) ? 1'b1 : 1'bz;
//assign sdram_add_pad = uc_sdram_add_pad;
//assign sdram_ba_pad = uc_sdram_ba_pad;
//assign sdram_cas_pad = uc_sdram_cas_pad;
//assign sdram_ras_pad = uc_sdram_ras_pad;
//assign sdram_we_pad = uc_sdram_we_pad;
assign sdram_clk_pad = clk_75mhz_pad & pll_locked;
assign sdram_data_pad = uc_sdram_data_pad_oe ? uc_sdram_data_pad_o :
16'bz;
assign uc_sdram_data_pad_i = uc_sdram_data_pad_oe ?
uc_sdram_data_pad_i : sdram_data_pad;
/* Now we set up the address decode and the return WISHBONE master
* databus and ack signal multiplexors. This is very simple, on the native
* WISHBONE bus (epwbm_*) if the address is >= 0x72100000, the 16 to 32 bit
* bridge is selected. The 32 bit wishbone bus contains 3 wishbone
* slaves: the ethernet core, the ethernet packet RAM, and the usercore. If the
* address >= 0x72a00000 the usercore is strobed and expected to ack, for
* address >= 0x72102000 the ethernet core is strobed and expected to ack
* otherwise the bus cycle goes to the ethernet RAM core.
*/
always @(epwbm_adr_o or epwbm_wb32m_bridgecore_dat or
epwbm_wb32m_bridgecore_ack or usercore_dat or usercore_ack or
wb32m_adr_o or wb32m_stb_o)
begin
epwbm_dat_i = 16'hxxxx;
epwbm_ack_i = 1'bx;
if (epwbm_adr_o >= 24'h100000)
begin
epwbm_dat_i = epwbm_wb32m_bridgecore_dat;
epwbm_ack_i = epwbm_wb32m_bridgecore_ack;
end
usercore_stb = 1'b0;
// ethcore_stb = 1'b0;
// ethramcore_stb = 1'b0;
// if (wb32m_adr_o >= 22'h280000) begin
usercore_stb = wb32m_stb_o;
wb32m_dat_i = usercore_dat;
wb32m_ack_i = usercore_ack;
// end
end
/* Various defaults for signals not used in this boilerplate project: */
/* No use for DMA -- used by TS-SDCORE on shipped bitstream */
assign dma_req_pad = 1'bz;
/* PHY always on */
assign eth_pd_pad = 1'b1;
/* SDRAM signals outputing 0's -- used by TS-VIDCORE in shipped
bitstream */
/*
assign sdram_add_pad = 12'd0;
assign sdram_ba_pad = 2'd0;
assign sdram_cas_pad = 1'b0;
assign sdram_ras_pad = 1'b0;
assign sdram_we_pad = 1'b0;
assign sdram_clk_pad = 1'b0;
assign sdram_data_pad = 16'd0;
*/
/* serial (RS232) mux signals safely "parked" -- used by TS-UART */
assign rd_mux_pad = 1'b1;
assign mux_cntrl_pad = 1'b0;
assign wr_232_pad = 1'b1;
assign mux_pad = 4'hz;
/* SD flash card signals "parked" -- used by TS-SDCORE */
assign sd_soft_power_pad = 1'b0;
assign sd_hard_power_pad = 1'b1;
assign sd_dat_pad = 4'hz;
assign sd_clk_pad = 1'b0;
assign sd_cmd_pad = 1'bz;
endmodule |
module main(
input _cpuClock,
input [15:0] sw,
input btnC,
input btnU,
input btnD,
input btnL,
input btnR,
output [15:0] led,
output [6:0] seg,
output dp,
output [3:0] an,
input SD_MISO, SD_CD, SD_WP,
output SD_CLK, SD_MOSI, SD_CS
,
input [31:0] UBDI, // Data In from MB
output [31:0] UBDO, // Data Out to MB
output UBEO, // Error Out to MB (Active HIGH)
output UBRRI, // ReadReadyInterrupt to MB (Active HIGH)
input UBRRA, // ReadReadyAcknowledge from MB (Active HIGH)
input UBRM, // read mode
input UBWM, // write mode
input [31:0] UBADDR // Block Address
);
// CPU CLOCK PRESCALER //
localparam PRESCALE = 8; // Use to slowdown CPU CLOCK
wire cpuClock;
//clockDiv #(PRESCALE) c00 (_cpuClock, cpuClock); // Slowed (Debugging)
assign cpuClock = _cpuClock; // Not Slowed (Normal Operation)
// RESET BUTTON //
wire globalReset;
assign globalReset = btnU || btnC;
// ERROR REGISTER //
reg [7:0] _errorState = 0; // Last state before error occured
wire _errorNoti;
// COMMANDS //
reg [5:0] CMD_INDEX; // Command Index (CMD0 - CMD63)
reg [31:0] CMD_ARG; // 32-bit Command Argument
reg CMD_TRANSMIT; // 0 => Receiver, 1 => Transmitter
// Communication Master (CM) //
reg CM_EN = 0; // Enable
reg CM_RST = 1; // Reset
reg cmSpiClkEn = 1; // Enable SPI Clock Output
reg CMClkBS = 0; // 0 = not activate, 1 = activate byte sync mode
wire CM_EINT; // Error Interrupt
wire [3:0] CM_ETYPE; // Error Type
wire [3:0] CM_EST; // Errored State
reg [1:0] CM_RM = 2'b00; // Read Mode
wire [39:0] CM_RR; // Read Response (Read Data Buffer)
reg CM_STA = 0; // Start
wire CM_FIN; // Finished
wire CM_MISO, CM_CD, CM_WP; // => From SD
wire CM_SCLK, CM_MOSI, CM_CS; // <= To SD
spiCommMaster CMM (cpuClock, CM_EN, CM_RST, cmSpiClkEn, CMClkBS,
CM_EINT, CM_ETYPE, CM_EST,
CMD_TRANSMIT, CMD_INDEX, CMD_ARG,
CM_RM, CM_RR,
CM_STA, CM_FIN,
CM_MISO, CM_CD, CM_WP, CM_SCLK, CM_MOSI, CM_CS);
// INTERNAL //
reg spiClockEn = 0;
reg INTL_MOSI = 1, INTL_CS = 1;
reg INTLTM_RST = 1; // Internal Timer Reset
wire [9:0] INTLTM_OUT;
wire INTLTM_OV; // Internal Timer Overflow
counter #(10) INTLTM (CM_SCLK, INTLTM_RST, INTLTM_OUT, INTLTM_OV);
reg [39:0] INTL_RR = 0; // Internal Read Response
reg trySDv1 = 1;
// SPI PROTOCOL PORT CONNECTION //
assign CM_MISO = SD_MISO;
assign CM_CD = SD_CD;
assign CM_WP = SD_WP;
assign SD_CLK = (spiClockEn ? CM_SCLK : 1'b1) ; // also controlled by cmSpiClkEn
assign SD_MOSI = (CM_EN ? CM_MOSI : INTL_MOSI);
assign SD_CS = (CM_EN ? CM_CS : INTL_CS);
//// Outsize Communication Ports (UB - MicroBlaze)
//wire [31:0] UBDI; // Data In from MB
//wire [31:0] UBDO; // Data Out to MB
//wire UBEO; // Error Out to MB (Active HIGH)
//wire UBRRI; // ReadReadyInterrupt to MB (Active HIGH)
//wire UBRRA; // ReadReadyAcknowledge from MB (Active HIGH)
//wire UBRM; // read mode
//wire UBWM; // write mode
//wire UBADDR;
//assign UBRM = btnR;
//assign UBWM = btnL;
//assign UBRRA = btnD;
//assign UBADDR = 32'h0;
// Data Read //
reg [6:0] _yb = 0; // vertical SD reading (128)
// Single Read (8-bit)
reg INTLRS_ST = 0;
wire INTLRS_FIN;
reg [7:0] INTLRS_BUFF;
wire [7:0] INTLRS_OUT;
reg INTLRS_WFBI = 1;
spiRead #(1) INTLRSM (CM_SCLK, INTLRS_ST, SD_MISO, INTLRS_FIN, INTLRS_OUT, INTLRS_WFBI);
// Double Read (16-bit)
reg INTLRD_ST = 0;
wire INTLRD_FIN;
reg [15:0] INTLRD_BUFF;
wire [15:0] INTLRD_OUT;
reg INTLRD_WFBI = 0;
spiRead #(2) INTLRDM (CM_SCLK, INTLRD_ST, SD_MISO, INTLRD_FIN, INTLRD_OUT, INTLRD_WFBI);
// Quad read (32-bit)
reg INTLRQ_ST = 0;
wire INTLRQ_FIN;
reg [31:0] INTLRQ_BUFF;
wire [31:0] INTLRQ_OUT;
reg INTLRQ_WFBI = 0;
spiRead #(4) INTLRQM (CM_SCLK, INTLRQ_ST, SD_MISO, INTLRQ_FIN, INTLRQ_OUT, INTLRQ_WFBI);
// CRC-16 For Data (CRCD) //
// uses CPU CLOCK
wire CRCD_IN;
reg CRCD_CLR = 1;
reg CRCD_EN = 0;
wire [15:0] CRCD_OUT;
reg [15:0] CRCD_OUT_BUFF;
crcGenerator #(.LEN(16)) CRCDM (CRCD_IN, CM_SCLK, CRCD_CLR, CRCD_EN, 17'b1_00010000_00100001, CRCD_OUT);
assign CRCD_IN = SD_MISO;
// Data Reader (DR) //
reg DR_DRI = 0; // <= Data Ready Interrupt
wire DR_DACK; // => Data Ready Acknowledge
reg DREO = 0; // <= Data Reader Error Out
wire [31:0] DR_OUT; // Data Read output
assign DR_OUT = (DR_DRI) ? INTLRQ_BUFF : 32'bZ;
assign UBDO = DR_OUT; // Data Out to MB
assign UBEO = DREO;
assign UBRRI = DR_DRI; // ReadReadyInterrupt to MB (Active HIGH)
assign DR_DACK = UBRRA; // ReadReadyAcknowledge from MB (Active HIGH)
// STATES //
// 0x0- : error states
// 0x1- : power sequence states
// 0x2- : initialization states (1)
// 0x3- : initialization states (2)
// 0x40 : data transfer standby
// 0x6- : read
// 0xA- : write
reg [7:0] state = 8'h10;
reg [7:0] nstate = 8'h10;
assign _errorNoti = state[7:4] == 4'b0;
// main loop //
always @ (negedge cpuClock) begin
if(globalReset) begin
_errorState <= 8'h0;
nstate <= 8'h10;
INTLTM_RST <= 1; // Stop Internal Timer
CM_RST <= 1; // Reset Communication Master
DREO <= 0;
end else begin
case (state)
8'h07: begin // card locked error
if (SD_WP) begin
nstate <= 8'h10;
end
end
8'h10: begin // wait for card
CM_RST <= 0; // Start Communication Master (Use CM_CLK)
CM_EN <= 0; // Disable Communication Master (Use Internal CS and Timer)
if (!SD_CD) begin
INTLTM_RST <= 0; // Start Internal Timer With SPI Clock from CMM
nstate <= 8'h11;
end
end
8'h11: begin // wait >= 1ms
if (INTLTM_OUT > 200) begin
spiClockEn <= 1; // Main Enable SPI Clock Set for the rest of operation
INTL_CS <= 1; // Set CS HIGH per SD specification
INTLTM_RST <= 1; // Stop Internal Timer
nstate <= 8'h12;
end
end
8'h12: begin // ctrReset sync
if (INTLTM_OUT == 0) begin // wait until counter is set to 0 at SPI Clock
INTLTM_RST <= 0; // Start Inter Internal Timer With SPI Clock from CMM
nstate <= 8'h13;
end
end
8'h13: begin // wait for at least 74 SPI clocks
if (INTLTM_OUT > 74) begin
CM_EN <= 1;
nstate <= 8'h14;
end
end
8'h14: begin // [CMD0] Set CMD
INTLTM_RST <= 1; // reset Internal Timer
CMD_INDEX <= 0; // CMD 0
CMD_ARG <= 0;
CMD_TRANSMIT <= 1;
CM_STA <= 1; // Start Communication Master
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h15;
end
8'h15: begin // [CMD0] wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR = CM_RR;
nstate <= 8'h16;
end
end
8'h16: begin // [CMD0] check response
if (INTL_RR[7:0] == 8'b1) nstate <= 8'h20;
else begin // init response error (unknown device)
_errorState <= state;
nstate <= 8'h02; // response error
end
end
8'h20: begin // standby (card idle state)
//if (check?)
nstate <= 8'h24; // Check Voltage range
end
8'h24: begin // [CMD8] Set CMD
CMD_INDEX <= 6'h08; // CMD8: Send Interface Condition Command
CMD_ARG <= {24'h000001, 8'hAA}; // AA = 8-bit check pattern
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 2;
nstate <= 8'h25;
end
8'h25: begin // [CMD8] wait for CM
if (CM_EINT) begin
if(CM_ETYPE == 4'b0010) begin // timeout => Might be SDv1
trySDv1 <= 0;
CM_RST <= 1;
nstate <= 8'h28; // goto 'set CMD55' state
end else begin
nstate <= 8'h05; // CM Error
end
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h26;
end
end
8'h26: begin // [CMD8] check response
if (INTL_RR[11:0] == 12'h1AA) begin
nstate <= 8'h28; // SDv2
end else if(INTL_RR[39:32] == 8'h05) begin
trySDv1 <= 0;
nstate <= 8'h28; // SDv1? => try SDv1
end else begin
_errorState = state;
nstate <= 8'h03; // Unknown Card Error
end
end
8'h28: begin // [CMD55] set CMD (SDv1 & SDv2)
CMD_INDEX <= 55; // CMD55: Application Specific Command (APP_CMD)
CMD_ARG <= 0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h29;
end
8'h29: begin // [CMD55] wait for CM (SDv1 & SDv2)
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h2A; // delay check response to next clock for safety
end
end
8'h2A: begin // [CMD55] check response (SDv1 & SDv2)
if (INTL_RR[7:0] == 8'h01) begin // Definitely SDv2
nstate <= 8'h2C;
end else if (INTL_RR[7:0] == 8'h05) begin // Is it SD v1?
if (trySDv1) begin // Have we tried SD v1?
trySDv1 <= 0;
nstate <= 8'h28; // goto 'Set CMD55' State
end else begin // Not SD v1 and SD v2
nstate <= 8'h03; // Unknown Card Error
end
end else begin
_errorState <= state;
nstate <= 8'h03; // Unknown Card Error
end
end
8'h2C: begin // [ACMD41] Set CMD (SDv1 & SDv2 -- different in ACMD41_ARG)
CMD_INDEX <= 41; // ACMD41
CMD_ARG <= {(trySDv1 ? 4'h4 : 4'h0), 28'h0};
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h2D;
end
8'h2D: begin // [ACMD41] wait for reading (SDv1 & SDv2)
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h2E;
end
end
8'h2E: begin // [ACMD41] check response (SDv1 & SDv2)
if (INTL_RR[7:0] == 8'h01) begin // Not finished
nstate <= 8'h28; // Set CMD 58
end else if (INTL_RR[7:0] == 8'h00) begin // finished
if (trySDv1) begin // SDv2
nstate <= 8'h30; // goto `Set CMD58` State
end else begin // SDv1
nstate <= 8'h38; // goto `Set CMD16` State
end
end else if (INTL_RR[7:0] == 8'h05) begin // 'invalid command'
if (trySDv1) begin // Have we tried SD v1?
trySDv1 <= 0;
nstate <= 8'h28; // goto 'Set CMD55' State
end else begin // Not SD v1 and SD v2
_errorState = state;
nstate <= 8'h03; // Unknown Card Error
end
end else begin
_errorState = state;
nstate <= 8'h03; // Unknown Card Error
end
end
8'h30: begin // [CMD58] set CMD
CMD_INDEX <= 58; // CMD58 - gen_crc
CMD_ARG <= 32'h0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 2;
nstate <= 8'h31;
end
8'h31: begin // [CMD58] wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h32; // delay check response to next clock for safety
end
end
8'h32: begin // [CMD58] check response
if (INTL_RR[30] == 1) begin // CSS bit: determines whether High Capacity (HC) Card or not
// HC => Finish Initialize
nstate <= 8'h40;
end else begin
// Standard Capacity => force block size
nstate <= 8'h34;
end
end
8'h34: begin // [CMD16] Set CMD
CMD_INDEX <= 16; // CMD16
CMD_ARG <= 32'h00000200; // Force Block Size = 512 bytes for FAT filesystem
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h35;
end
8'h35: begin // [CMD16] wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h36;
end
end
8'h36: begin // [CMD16] Check response
if (INTL_RR[7:0] == 8'h01) begin
nstate <= 8'h40;
end else begin
nstate <= 8'h02;
_errorState <= state;
end
end
8'h40: begin
// finished initialization
if (SD_CD) begin
nstate <= 8'h10;
end
if (UBRM) begin
nstate <= 8'h60;
end else if (UBWM) begin
nstate <= 8'hA0;
end
end
8'h60: begin // [CMD17] Set CMD
CMD_INDEX <= 17; // CMD17 (Read Single Block)
CMD_ARG <= UBADDR; // Address = 0
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h61;
end
8'h61: begin // [CMD17] Wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h62;
end
end
8'h62: begin // [CMD17] Check Response
if (INTL_RR[7:0] == 8'h00) begin
CM_EN <= 0; // Disable CM
INTL_MOSI <= 1;
INTL_CS <= 0;
INTLTM_RST <= 0;
spiClockEn <= 0;
nstate <= 8'h64; // goto ' wait for reading //
end else begin
_errorState <= state;
nstate <= 8'h02; // Response Error
end
end
8'h64: begin // Start Reading into INTLRS (Data Token Receive)
if (INTLRS_FIN == 0) begin // check whether previous reading `stop` has been acknowledged
INTLRS_ST <= 1; // start reading
INTLRS_WFBI <= 0;
spiClockEn <= 1;
nstate <= 8'h65;
end
end
8'h65: begin // wait for INTLRS reading
if (INTLRS_FIN) begin
nstate <= 8'h66;
INTLRS_ST <= 0;
INTLRS_WFBI <= 1;
INTLRS_BUFF <= INTLRS_OUT;
end
end
8'h66: begin // check response of INTLRS (Data Token)
if (INTLRS_BUFF == 8'hFE) begin // received data token for CMD17/18/24
INTLTM_RST <= 1;
nstate <= 8'h67;
end else if (INTLRS_BUFF == 8'hFC) begin // received data token for CMD25
_errorState <= state;
nstate <= 8'h02;
end else if (INTLRS_BUFF == 8'hFD) begin // Stop trans token for CMD25
_errorState <= state;
nstate <= 8'h02;
end else if (INTLRS_BUFF == 8'hFF) begin
if (INTLTM_OUT > 200) begin
INTLTM_RST <= 1;
_errorState <= state;
nstate <= 8'h01;
end else begin
spiClockEn <= 0;
nstate <= 8'h64; // go back
end
end else begin
_errorState <= state;
nstate <= 8'h02; // illegal response
end
end
8'h67: begin // Start Reading Loop (y) - 32 bit
_yb <= 0;
CRCD_CLR <= 0;
nstate <= 8'h68;
end
8'h68: begin // Read Data Loop body (1)
INTLRQ_ST <= 1;
spiClockEn <= 1;
DR_DRI <= 0;
CRCD_EN <= 1;
nstate <= 8'h69;
end
8'h69: begin // Wait for Reading
if (INTLRQ_FIN) begin
spiClockEn <= 0;
INTLRQ_BUFF <= INTLRQ_OUT;
INTLRQ_ST <= 0;
DR_DRI <= 1;
CRCD_OUT_BUFF <= CRCD_OUT;
CRCD_EN <= 0;
nstate <= 8'h6A;
end else begin
spiClockEn <= 1;
end
end
8'h6A: begin // Check data
if (!INTLRQ_FIN && DR_DACK) begin
if (_yb == 7'h7F) begin // loop condition
_yb <= 0;
nstate <= 8'h70;
end else begin
_yb <= _yb + 1; // loop increment
nstate <= 8'h68;
end
end
end
8'h70: begin // Finish Reading Data => read CRC-16
INTLRD_ST <= 1;
spiClockEn <= 1;
nstate <= 8'h71;
end
8'h71: begin
if (INTLRD_FIN) begin
INTLRD_BUFF <= INTLRD_OUT;
INTLRD_ST <= 0;
nstate <= 8'h72;
end
end
8'h72: begin
if (INTLRD_BUFF == CRCD_OUT_BUFF) begin
DREO <= 0;
nstate <= 8'h74;
end else begin
DREO <= 1;
nstate <= 8'h08; // crc error
end
end
8'h74: begin //wait for data transfer to UB (Microblaze) complete.
CM_EN <= 1; // Enable CM
nstate <= 8'h40; // go back
end
8'h80: begin // [CMD18] Set CMD
CMD_INDEX <= 18; // CMD17 (Read Multi Block)
CMD_ARG <= UBADDR; // Address
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h81;
end
8'h81: begin // [CMD18] Wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h82;
end
end
8'h82: begin // [CMD18] Check Response
if (INTL_RR[7:0] == 8'h00) begin
CM_EN <= 0; // Disable CM
INTL_MOSI <= 1;
INTL_CS <= 0;
INTLTM_RST <= 0;
spiClockEn <= 0;
nstate <= 8'h84; // goto ' wait for reading //
end else begin
_errorState <= state;
nstate <= 8'h02; // Response Error
end
end
8'h84: begin
end
8'hA0: begin // <single write>
end
default: begin
if(state[7:4] != 4'b0) begin
_errorState = state;
nstate = 8'h04;
end
end
endcase
end
end
always @ (posedge cpuClock) begin
if (nstate != state && nstate != state + 1 && nstate[1:0] != 2'b00 && nstate[7:4] != 4'h0) begin
state <= 8'h06; //Invalid state sequence
end else begin
state <= nstate;
end
end
// History of states //
// LSB = newest, MSB = oldest
reg [63:0] history = 0;
always @ (posedge cpuClock) begin
if (globalReset)begin
history = 0;
end else if (nstate != state) begin
history = {history[55:0], nstate};
end
end
// Seven Segment //
wire [2:0] historySel;
assign historySel = sw[10:8];
wire [15:0] numSegment;
wire segClock;
wire [3:0] aen;
assign numSegment = sw[11] ? {CM_EST, CM_ETYPE} : historySel == 0 ? {_errorState, state} : history[historySel * 8 +:7];
assign aen = ~sw[15:12];
clockDiv #(10) seg0 (cpuClock, segClock);
segMaster seg1 (segClock, numSegment, aen, seg, an, dp);
// debug
reg [255:0] historyBuff = 0;
always @ (posedge cpuClock) begin
if (globalReset)begin
historyBuff = 0;
end else if (INTLRQ_BUFF != historyBuff[31:0]) begin
historyBuff = {historyBuff[223:0], INTLRQ_BUFF};
end
end
wire [1:0] layer;
assign layer = sw[1:0];
wire cl0, cl1, cl2;
clockDiv #(12) d0 (cpuClock, cl0);
assign led = (sw[1] ? historyBuff[historySel * 32 + 16 +:15] : historyBuff[historySel * 32 +:15]);
endmodule |
module asyn_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk_125mhz,
input wire clk90_125mhz,
input wire rst_125mhz,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign ledu = 0;
assign ledl = 0;
assign ledd = 0;
assign ledr = 0;
assign ledc = 0;
assign led = led_reg;
assign phy_reset_n = !rst_125mhz;
assign uart_rxd = 0;
assign uart_cts = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk_125mhz),
.gtx_clk90(clk90_125mhz),
.gtx_rst(rst_125mhz),
.logic_clk(clk_125mhz),
.logic_rst(rst_125mhz),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule |
module shadow_pixel
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "11" *)
(* C_ADDRB_WIDTH = "11" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.5913 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "shadow_pixel.mem" *)
(* C_INIT_FILE_NAME = "shadow_pixel.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1080" *)
(* C_READ_DEPTH_B = "1080" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1080" *)
(* C_WRITE_DEPTH_B = "1080" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
shadow_pixel_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule |
module shadow_pixel_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
shadow_pixel_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule |
module shadow_pixel_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
shadow_pixel_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule |
module shadow_pixel_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h1330133013301330133013301330133013301330133013301330133013301330),
.INIT_01(256'h1330000013300000133000001330000013301330133013301330133013301330),
.INIT_02(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_03(256'h1330133013301330133013301330133013301330133013301330133013300000),
.INIT_04(256'h1330133013301330133013301330133013301330133013301330133013301330),
.INIT_05(256'h0000133000001330000013300000133000001330133013301330133013301330),
.INIT_06(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_07(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_08(256'h1330133013301330133013301330133013301330133013301330133000001330),
.INIT_09(256'h1330000013300000133000001330133013301330133013301330133013301330),
.INIT_0A(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_0B(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_0C(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_0D(256'h0000133013301330133013301330133013301330133013301330133013301330),
.INIT_0E(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_0F(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_10(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_11(256'h1330133013301330133013300000133000001330000013300000133000001330),
.INIT_12(256'h1330000013300000133000001330000013300000133000001330133013301330),
.INIT_13(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_14(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_15(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_16(256'h0000133000001330000013300000133013301330133000001330000013300000),
.INIT_17(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_18(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_19(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_1A(256'h1330133000001330000013300000133000001330000013300000133000001330),
.INIT_1B(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_1C(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_1D(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_1E(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_1F(256'h0000133000001330000013300000133013300000133000001330000013300000),
.INIT_20(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_21(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_22(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_23(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_24(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_25(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_26(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_27(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_28(256'h0000133000001330000013300000133013300000133000001330000013300000),
.INIT_29(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_2A(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_2B(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_2C(256'h1330133000001330000013300000133000001330000013300000133000001330),
.INIT_2D(256'h1330000013300000133000001330000013300000133000001330133013301330),
.INIT_2E(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_2F(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_30(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_31(256'h0000133000001330133013301330133013301330133000001330000013300000),
.INIT_32(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_33(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_34(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_35(256'h1330133013301330133013300000133000001330000013300000133000001330),
.INIT_36(256'h1330000013300000133000001330133013301330133013301330133013301330),
.INIT_37(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_38(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_39(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_3A(256'h1330133013301330133013301330133013301330133013301330133013301330),
.INIT_3B(256'h0000133000001330000013300000133000001330133013301330133013301330),
.INIT_3C(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_3D(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_3E(256'h1330133013301330133013301330133013301330133013301330133000001330),
.INIT_3F(256'h1330133013301330133013301330133013301330133013301330133013301330),
.INIT_40(256'h1330000013300000133000001330000013301330133013301330133013301330),
.INIT_41(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_42(256'h1330133013301330133013301330133013301330133013301330133013300000),
.INIT_43(256'h0000000000000000000000000000000013301330133013301330133013301330),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[11:6],1'b0,1'b0,dina[5:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,douta[11:6],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,douta[5:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module shadow_pixel_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
shadow_pixel_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule |
module shadow_pixel_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [10:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [10:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [10:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [10:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
shadow_pixel_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule |
module shadow_pixel_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
shadow_pixel_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module OBUFDS_DPHY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter IOSTANDARD = "DEFAULT"
)(
output O,
output OB,
input HSTX_I,
input HSTX_T,
input LPTX_I_N,
input LPTX_I_P,
input LPTX_T
);
// define constants
localparam MODULE_NAME = "OBUFDS_DPHY";
// Parameter encodings and registers
localparam IOSTANDARD_DEFAULT = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_DPHY_dr.v"
`else
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
`endif
wire IOSTANDARD_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg OB_out;
reg O_out;
wire HSTX_I_in;
wire HSTX_T_in;
wire LPTX_I_N_in;
wire LPTX_I_P_in;
wire LPTX_T_in;
reg hs_mode = 1'b1;
assign (strong1,strong0) O = (hs_mode === 1'b0) ? O_out : 1'bz;
assign (strong1, strong0) OB = (hs_mode === 1'b0) ? OB_out : 1'bz;
assign (supply1,supply0) O = (hs_mode === 1'b1) ? O_out : 1'bz;
assign (supply1,supply0) OB = (hs_mode === 1'b1) ? OB_out : 1'bz;
assign HSTX_I_in = HSTX_I;
assign HSTX_T_in = HSTX_T;
assign LPTX_I_N_in = LPTX_I_N;
assign LPTX_I_P_in = LPTX_I_P;
assign LPTX_T_in = LPTX_T;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
//Commenting out the DRC check for IOSTANDARD attribute as it is not required as per IOTST.
/* initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((IOSTANDARD_REG != "DEFAULT"))) begin
$display("Error: [Unisim %s-101] IOSTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
*/
always @ (LPTX_T_in or HSTX_T_in or LPTX_I_P_in or LPTX_I_N_in or HSTX_I_in) begin
if (LPTX_T_in === 1'b0) begin
O_out <= LPTX_I_P_in;
OB_out <= LPTX_I_N_in;
hs_mode <= 1'b0;
end else if (LPTX_T_in === 1'b1 && HSTX_T_in === 1'b0) begin
O_out <= HSTX_I_in;
OB_out <= ~HSTX_I_in;
hs_mode <= 1'b1;
end else begin
O_out <= 1'bz;
OB_out <= 1'bz;
hs_mode <= 1'bx;
end
end
specify
(HSTX_I => O) = (0:0:0, 0:0:0);
(HSTX_I => OB) = (0:0:0, 0:0:0);
(HSTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(HSTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(LPTX_I_N => OB) = (0:0:0, 0:0:0);
(LPTX_I_P => O) = (0:0:0, 0:0:0);
(LPTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(LPTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule |
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND);
endmodule |
module ElbertV2_FPGA_Board(
input[5:0] BTN,
input clk,
output[7:0] LED,
output [7:0] SevenSegment,
output [2:0] SevenSegment_Enable,
output IO_P1_1,
output IO_P1_3,
inout IO_P1_5
);
wire rst_n;
wire inc_n_btn;
wire btn2_n;
wire dht11_dat;
reg [1:0] state_func;
wire inc_n_debounced;
wire btn2_n_debounced;
wire btn6_debounced;
wire select_onehot;
wire rst_debounced;
wire clk_div_1Hz;
wire clk_div_1MHZ;
wire clk_div_1kHZ;
wire [9:0] counter_4bit_out;
wire [9:0] counter_10bit_out;
wire dummy;
wire [9:0]humid;
wire [9:0]temp;
wire [3:0]status;
wire [3:0] HUNDREDS;
wire [3:0] TENS;
wire [3:0] ONES;
wire start_dht11_capture;
reg auto_capture;
reg [3:0] auto_capture_counter;
reg auto_capture_start;
reg auto_capture_rst_n;
wire [3:0] data0a;
wire [3:0] data1a;
wire [3:0] data2a;
wire [3:0] data0b;
wire [3:0] data1b;
wire [3:0] data2b;
reg [3:0] LCD_3;
reg [3:0] LCD_2;
reg [3:0] LCD_1;
wire dht11_start;
wire rst_n_dht11;
assign rst_n = BTN[4];
assign inc_n_btn = ~BTN[0];
assign btn2_n = ~BTN[1];
assign LED[7] = counter_4bit_out[0];
assign LED[6] = counter_4bit_out[1];
assign LED[5] = btn2_n_debounced;
assign LED[4] = inc_n_debounced;
assign LED[3] = status[0];
assign LED[2] = status[1];
assign LED[1] = status[2];
assign LED[0] = status[3];
assign SevenSegment[0] = ~clk_div_1Hz;
assign IO_P1_1 = 1'b0;
assign IO_P1_3 = 1'b1;
assign IO_P1_5 = dht11_dat;
assign start_dht11_capture = auto_capture? auto_capture_start:btn2_n_debounced;
assign rst_n_dht11 = btn6_debounced;//auto_capture? auto_capture_rst_n:btn6_debounced;
assign humid[9:8] = 2'b0;
assign temp[9:8] = 2'b0;
//assign SevenSegment = counter_10bit_out[7:0];
always@(posedge clk or negedge rst_debounced)
begin
if(~rst_debounced)
begin
state_func <=2'b0;
auto_capture<=1'b0;
end
else
begin
if(select_onehot==1'b1)
state_func <=state_func +1;
case(counter_4bit_out[1:0])
2'b0:
begin
LCD_1 <= ONES;
LCD_2 <= TENS;
LCD_3 <= HUNDREDS;
auto_capture<=1'b0;
end
2'b1:
begin
LCD_1 <= data0a;
LCD_2 <= data1a;
LCD_3 <= data2a;
auto_capture<=1'b0;
end
2'b10:
begin
LCD_1 <= data0b;
LCD_2 <= data1b;
LCD_3 <= data2b;
auto_capture<=1'b0;
end
2'b11:
begin
LCD_1 <= data0a;
LCD_2 <= data1a;
LCD_3 <= data2a;
auto_capture<=1'b1;
end
endcase
end
end
/*
always@(posedge clk_div_1Hz or negedge rst_n)
begin
if(~rst_n)
auto_capture_counter<=4'b0;
else
begin
auto_capture_counter<=auto_capture_counter+1;
if (auto_capture_counter == 4'b1101)
begin
auto_capture_rst_n <=1'b0;
end
else
begin
auto_capture_rst_n <=1'b1;
if(auto_capture_counter[2:0] == 3'b111)
begin
auto_capture_start<=1'b1;
end
else
begin
auto_capture_start<=1'b0;
end
end
end
end
*/
always@(posedge clk_div_1Hz or negedge rst_n)
begin
if(~rst_n)
begin
auto_capture_counter<=4'b0;
auto_capture_start<=1'b0;
end
else
begin
auto_capture_counter<=auto_capture_counter+1;
if(auto_capture_counter[2:0] == 3'b111)
auto_capture_start<=1'b1;
else
auto_capture_start<=1'b0;
end
end
freqdiv freqdiv1(clk,rst_n,clk_div_1Hz,2'b01);
freqdiv freqdiv2(clk,rst_n,clk_div_1MHZ,2'b00);
freqdiv freqdiv3(clk,rst_n,clk_div_1kHZ,2'b10);
debounce debounce_inc(clk_div_1kHZ,inc_n_btn,inc_n_debounced);
debounce debounce_start(clk_div_1kHZ,btn2_n,btn2_n_debounced);
debounce debounce_dht11_rst(clk_div_1kHZ,BTN[5],btn6_debounced);
debounce debounce_rst(clk_div_1kHZ,rst_n,rst_debounced);
new_counter theNewCounter(rst_n,inc_n_debounced,counter_4bit_out);
new_counter the10bitCounter(rst_n,clk_div_1Hz,counter_10bit_out);
mySevenSegment sevenSegementDec(clk,rst_debounced,LCD_1,LCD_2,LCD_3,SevenSegment[7:1],SevenSegment_Enable);
BINARY_TO_BCD theBinary2BCD(counter_10bit_out, HUNDREDS,TENS,ONES);
BINARY_TO_BCD theBinary2BCDhumid(humid, data2a,data1a,data0a);
BINARY_TO_BCD theBinary2BCDtemp(temp, data2b,data1b,data0b);
dht11_driver dht11_driver(clk_div_1MHZ,rst_n_dht11,start_dht11_capture,dht11_dat,humid[7:0],temp[7:0],status);
endmodule |
module debounce(
clk,
PB,
PB_state
);
input clk;
input PB;
output PB_state;
reg init_state = 1'b0;
reg PB_state = 1'b0;
// Next declare a 16-bits counter
reg [11:0] PB_cnt = 12'd0;
wire PB_cnt_max = &PB_cnt;
wire PB_idle = (PB_cnt == 12'd0);
wire PB_changed = (PB != init_state);
always @(posedge clk)
if(PB_idle & PB_changed)
begin
init_state = PB;
PB_cnt = 12'd1;
end
else if(PB_cnt_max)
begin
PB_state = init_state;
PB_cnt = 12'd0;
end
else if(~PB_idle)
PB_cnt = PB_cnt + 12'd1;
endmodule |
module sky130_fd_sc_hs__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sky130_fd_sc_hs__sdfrtp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_r_no_pg u_df_p_r_no_pg0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule |
module jbi_mout (/*AUTOARG*/
// Outputs
mout_pio_req_adv, mout_pio_pop, mout_mondo_pop, jbi_io_j_adtype,
jbi_io_j_adtype_en, jbi_io_j_ad, jbi_io_j_ad_en, jbi_io_j_adp,
jbi_io_j_adp_en, jbi_io_j_req0_out_l, jbi_io_j_req0_out_en, jbi_io_j_pack0,
jbi_io_j_pack0_en, jbi_io_j_pack1, jbi_io_j_pack1_en,
mout_dsbl_sampling, mout_trans_yid, mout_trans_valid,
mout_scb0_jbus_wr_ack, mout_scb1_jbus_wr_ack, mout_scb2_jbus_wr_ack,
mout_scb3_jbus_wr_ack, mout_scb0_jbus_rd_ack, mout_scb1_jbus_rd_ack,
mout_scb2_jbus_rd_ack, mout_scb3_jbus_rd_ack, mout_nack, mout_nack_buf_id,
mout_nack_thr_id, mout_min_inject_err_done, mout_csr_inject_output_done, mout_min_jbus_owner,
mout_port_4_present, mout_port_5_present, mout_csr_err_cpar, mout_csr_jbi_log_par_jpar,
mout_csr_jbi_log_par_jpack0, mout_csr_jbi_log_par_jpack1, mout_csr_jbi_log_par_jpack4,
mout_csr_jbi_log_par_jpack5, mout_csr_jbi_log_par_jreq, mout_csr_err_arb_to,
jbi_log_arb_myreq, jbi_log_arb_reqtype, jbi_log_arb_aok, jbi_log_arb_dok, jbi_log_arb_jreq,
mout_csr_err_fatal, mout_csr_err_read_to,
mout_perf_aok_off, mout_perf_dok_off, mout_dbg_pop,
// Inputs
scbuf0_jbi_data, scbuf0_jbi_ctag_vld, scbuf0_jbi_ue_err,
sctag0_jbi_por_req_buf, scbuf1_jbi_data, scbuf1_jbi_ctag_vld,
scbuf1_jbi_ue_err, sctag1_jbi_por_req_buf, scbuf2_jbi_data,
scbuf2_jbi_ctag_vld, scbuf2_jbi_ue_err, sctag2_jbi_por_req_buf,
scbuf3_jbi_data, scbuf3_jbi_ctag_vld, scbuf3_jbi_ue_err,
sctag3_jbi_por_req_buf, ncio_pio_req, ncio_pio_req_rw, ncio_pio_req_dest,
ncio_pio_ad, ncio_pio_ue, ncio_pio_be, ncio_yid, ncio_mondo_req,
ncio_mondo_ack, ncio_mondo_agnt_id, ncio_mondo_cpu_id, ncio_prqq_level,
ncio_makq_level, io_jbi_j_pack4, io_jbi_j_pack5, io_jbi_j_req4_in_l,
io_jbi_j_req5_in_l, io_jbi_j_par, min_free, min_free_jid, min_trans_jid,
min_aok_on, min_aok_off, min_snp_launch, ncio_mout_nack_pop, min_mout_inject_err,
csr_jbi_config_arb_mode, csr_jbi_arb_timeout_timeval,
csr_jbi_trans_timeout_timeval,
csr_jbi_err_inject_errtype, csr_jbi_err_inject_xormask,
csr_jbi_debug_info_enb, csr_dok_on,
csr_jbi_debug_arb_aggr_arb, csr_jbi_error_config_fe_enb, csr_jbi_log_enb_read_to, dbg_req_transparent,
dbg_req_arbitrate, dbg_req_priority, dbg_data, testmux_sel, hold, rst_tri_en,
cclk, crst_l, clk, rst_l, tx_en_local_m1, arst_l
);
`include "jbi_mout.h"
// SCTAG0.
input [31:0] scbuf0_jbi_data;
input scbuf0_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf0_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag0_jbi_por_req_buf; // Request for DOK_FATAL.
// SCTAG1.
input [31:0] scbuf1_jbi_data;
input scbuf1_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf1_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag1_jbi_por_req_buf; // Request for DOK_FATAL.
// SCTAG2.
input [31:0] scbuf2_jbi_data;
input scbuf2_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf2_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag2_jbi_por_req_buf; // Request for DOK_FATAL.
// SCTAG3.
input [31:0] scbuf3_jbi_data;
input scbuf3_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf3_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag3_jbi_por_req_buf; // Request for DOK_FATAL.
// Non-Cache IO (ncio).
input ncio_pio_req;
input ncio_pio_req_rw;
input [1:0] ncio_pio_req_dest;
output mout_pio_req_adv;
input [63:0] ncio_pio_ad;
input ncio_pio_ue;
input [15:0] ncio_pio_be;
input [`JBI_YID_WIDTH-1:0] ncio_yid;
output mout_pio_pop;
//
input ncio_mondo_req;
input ncio_mondo_ack; // 1=ack; 0=nack
input [`JBI_AD_INT_AGTID_WIDTH-1:0] ncio_mondo_agnt_id;
input [`JBI_AD_INT_CPUID_WIDTH-1:0] ncio_mondo_cpu_id;
output mout_mondo_pop;
input [`JBI_PRQQ_ADDR_WIDTH:0] ncio_prqq_level; // Number of received PIO requests in queue
input [`JBI_MAKQ_ADDR_WIDTH:0] ncio_makq_level; // Number of INTACK/NACK transmit requests in queue.
// IO.
output [7:0] jbi_io_j_adtype;
output jbi_io_j_adtype_en;
output [127:0] jbi_io_j_ad;
output [3:0] jbi_io_j_ad_en;
input [2:0] io_jbi_j_pack4;
input [2:0] io_jbi_j_pack5;
output [3:0] jbi_io_j_adp;
output jbi_io_j_adp_en;
input io_jbi_j_req4_in_l;
input io_jbi_j_req5_in_l;
output jbi_io_j_req0_out_l;
output jbi_io_j_req0_out_en;
output [2:0] jbi_io_j_pack0;
output jbi_io_j_pack0_en;
output [2:0] jbi_io_j_pack1;
output jbi_io_j_pack1_en;
input io_jbi_j_par;
// DTL Control.
output mout_dsbl_sampling;
// Memory In (jbi_min).
input min_free; // Free an assignment to ...
input [3:0] min_free_jid; // 'min_free_jid[]'.
input [`JBI_JID_WIDTH-1:0] min_trans_jid; // Translate this JID to a YID.
output [`JBI_YID_WIDTH-1:0] mout_trans_yid; // Translated 'min_trans_jid[]'.
output mout_trans_valid; // Translation is valid qualifier.
output mout_scb0_jbus_wr_ack; // Inform when L2 sends Write Ack to JBus. (cmp clock)
output mout_scb1_jbus_wr_ack;
output mout_scb2_jbus_wr_ack;
output mout_scb3_jbus_wr_ack;
output mout_scb0_jbus_rd_ack; // Inform when we put read return data on JBus. (jbus clock)
output mout_scb1_jbus_rd_ack;
output mout_scb2_jbus_rd_ack;
output mout_scb3_jbus_rd_ack;
input min_aok_on; // Requests for AOK Flow Control.
input min_aok_off;
input min_snp_launch; // Issue COHACK.
input ncio_mout_nack_pop; // YID recovery from Timedout JBus read request.
output mout_nack;
output [1:0] mout_nack_buf_id;
output [5:0] mout_nack_thr_id;
input min_mout_inject_err; // J_AD error injection request.
output mout_min_inject_err_done;
output mout_csr_inject_output_done;
output [5:0] mout_min_jbus_owner; // JBus owner (logged by min block into JBI_LOG_CTRL[OWNER] as source of data return).
// CSRs (jbi_csr).
input [1:0] csr_jbi_config_arb_mode; // "Arbiter Mode" control from JBI_CONFIG register.
output mout_port_4_present; // "Port Present" in JBI_CONFIG register.
output mout_port_5_present; //
output mout_csr_err_cpar; // "JBus Control Parity Error" to Error Handling registers:
output mout_csr_jbi_log_par_jpar; // log J_PAR
output [2:0] mout_csr_jbi_log_par_jpack0; // log J_PACK0
output [2:0] mout_csr_jbi_log_par_jpack1; // log J_PACK1
output [2:0] mout_csr_jbi_log_par_jpack4; // log J_PACK4
output [2:0] mout_csr_jbi_log_par_jpack5; // log J_PACK5
output [6:0] mout_csr_jbi_log_par_jreq; // log J_REQ[6:0]
output mout_csr_err_arb_to; // "Arbitration Timeout Error" to Error Handling registers:
input [31:0] csr_jbi_arb_timeout_timeval; // "Arbitration Timeout Error" timeout interval.
output [2:0] jbi_log_arb_myreq; // log MYREQ.
output [2:0] jbi_log_arb_reqtype; // log REQTYPE.
output [6:0] jbi_log_arb_aok; // log AOK
output [6:0] jbi_log_arb_dok; // log DOK
output [6:0] jbi_log_arb_jreq; // log J_REQs
output [5:4] mout_csr_err_fatal; // "Reported Fatal Error" to Error Handling registers.
output mout_csr_err_read_to; // "Transaction Timeout - Read Req" to Error Handling registers.
input [31:0] csr_jbi_trans_timeout_timeval; // Interval counter wraparound value.
input csr_jbi_err_inject_errtype; //
input [3:0] csr_jbi_err_inject_xormask; //
output mout_perf_aok_off; // Performance Counter events - AOK OFF
output mout_perf_dok_off; // DOK OFF
input csr_jbi_debug_info_enb; // Put Debug Info in high half of JBus Address Cycles.
input csr_dok_on; // CSR request for DOK_FATAL.
input csr_jbi_debug_arb_aggr_arb; // AGGR_ARB bit of JBI_DEBUG_ARB register.
input csr_jbi_error_config_fe_enb; // Enable DOK Fatal for non-JBI fatal errors.
input csr_jbi_log_enb_read_to; // When negated, do not report Read Timeout errors.
// Dbg.
input dbg_req_transparent; // The Debug Info queue a valid request and wants it sent without impacting the JBus flow.
input dbg_req_arbitrate; // The Debug Info queue a valid request and want fair round robin arbitration.
input dbg_req_priority; // The Debug Info queue a valid request and needs it sent right away.
input [127:0] dbg_data; // Data to put on the JBus.
output mout_dbg_pop; // When asserted, pop the transaction header from the Debug Info queue.
// Misc.
input testmux_sel; // Memory and ATPG test mode signal.
input hold;
input rst_tri_en;
// Clock and reset.
input cclk; // CMP clock.
input crst_l; // CMP clock domain reset.
input clk; // JBus clock.
input rst_l; // JBus clock domain reset.
input tx_en_local_m1; // CMP to JBI clock domain crossing synchronization pulse.
input arst_l; // Asynch reset.
// Wires and Regs.
wire [3:0] int_req_type;
wire [6:0] int_requestors;
wire [127:0] jbi_io_j_ad;
wire [3:0] jbi_io_j_adp;
wire [7:0] jbi_io_j_adtype;
wire [3:0] sel_j_adbus;
wire [3:0] unused_jid;
wire [31:0] scbuf0_jbi_data, scbuf1_jbi_data, scbuf2_jbi_data, scbuf3_jbi_data;
wire [3:0] sct0rdq_trans_count, sct1rdq_trans_count, sct2rdq_trans_count, sct3rdq_trans_count;
wire [5:0] sct0rdq_jid, sct1rdq_jid, sct2rdq_jid, sct3rdq_jid;
wire [127:0] sct0rdq_data, sct1rdq_data, sct2rdq_data, sct3rdq_data;
wire [2:0] sel_queue;
wire [3:0] inj_err_j_ad;
wire [`JBI_YID_WIDTH-1:0] mout_trans_yid;
wire [3:0] nack_error_id;
wire [1:0] ignored;
// SCT0 Outbound Request Queues.
jbi_sct_out_queues sct0_out_queues (
// SCTAG/BUF Outbound Requests and Return Data.
.scbuf_jbi_data (scbuf0_jbi_data),
.scbuf_jbi_ctag_vld (scbuf0_jbi_ctag_vld),
.scbuf_jbi_ue_err (scbuf0_jbi_ue_err),
// JBI Outbound Interface.
.sctrdq_trans_count (sct0rdq_trans_count),
.sctrdq_data1_4 (sct0rdq_data1_4),
.sctrdq_install_state (sct0rdq_install_state),
.sctrdq_unmapped_error (sct0rdq_unmapped_error),
.sctrdq_jid (sct0rdq_jid),
.sctrdq_data (sct0rdq_data),
.sctrdq_ue_err (sct0rdq_ue_err),
.sctrdq_dec_count (sct0rdq_dec_count),
.sctrdq_dequeue (sct0rdq_dequeue),
// Memory In (jbi_min).
.mout_scb_jbus_wr_ack (mout_scb0_jbus_wr_ack),
// Misc.
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
// Clock and reset.
.cclk (cclk),
.crst_l (crst_l),
.clk (clk),
.rst_l (rst_l),
.tx_en_local_m1 (tx_en_local_m1),
.arst_l (arst_l)
);
// SCT1 Outbound Request Queues.
jbi_sct_out_queues sct1_out_queues (
// Outbound Requests and Return Data.
.scbuf_jbi_data (scbuf1_jbi_data),
.scbuf_jbi_ctag_vld (scbuf1_jbi_ctag_vld),
.scbuf_jbi_ue_err (scbuf1_jbi_ue_err),
// JBI Outbound Interface.
.sctrdq_trans_count (sct1rdq_trans_count),
.sctrdq_data1_4 (sct1rdq_data1_4),
.sctrdq_install_state (sct1rdq_install_state),
.sctrdq_unmapped_error (sct1rdq_unmapped_error),
.sctrdq_jid (sct1rdq_jid),
.sctrdq_data (sct1rdq_data),
.sctrdq_ue_err (sct1rdq_ue_err),
.sctrdq_dec_count (sct1rdq_dec_count),
.sctrdq_dequeue (sct1rdq_dequeue),
// Memory In (jbi_min).
.mout_scb_jbus_wr_ack (mout_scb1_jbus_wr_ack),
// Misc.
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
// Clock and reset.
.cclk (cclk),
.crst_l (crst_l),
.clk (clk),
.rst_l (rst_l),
.tx_en_local_m1 (tx_en_local_m1),
.arst_l (arst_l)
);
// SCT2 Outbound Request Queues.
jbi_sct_out_queues sct2_out_queues (
// Outbound Requests and Return Data.
.scbuf_jbi_data (scbuf2_jbi_data),
.scbuf_jbi_ctag_vld (scbuf2_jbi_ctag_vld),
.scbuf_jbi_ue_err (scbuf2_jbi_ue_err),
// JBI Outbound Interface.
.sctrdq_trans_count (sct2rdq_trans_count),
.sctrdq_data1_4 (sct2rdq_data1_4),
.sctrdq_install_state (sct2rdq_install_state),
.sctrdq_unmapped_error (sct2rdq_unmapped_error),
.sctrdq_jid (sct2rdq_jid),
.sctrdq_data (sct2rdq_data),
.sctrdq_ue_err (sct2rdq_ue_err),
.sctrdq_dec_count (sct2rdq_dec_count),
.sctrdq_dequeue (sct2rdq_dequeue),
// Memory In (jbi_min).
.mout_scb_jbus_wr_ack (mout_scb2_jbus_wr_ack),
// Misc.
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
// Clock and reset.
.cclk (cclk),
.crst_l (crst_l),
.clk (clk),
.rst_l (rst_l),
.tx_en_local_m1 (tx_en_local_m1),
.arst_l (arst_l)
);
// SCT3 Outbound Request Queues.
jbi_sct_out_queues sct3_out_queues (
// Outbound Requests and Return Data.
.scbuf_jbi_data (scbuf3_jbi_data),
.scbuf_jbi_ctag_vld (scbuf3_jbi_ctag_vld),
.scbuf_jbi_ue_err (scbuf3_jbi_ue_err),
// JBI Outbound Interface.
.sctrdq_trans_count (sct3rdq_trans_count),
.sctrdq_data1_4 (sct3rdq_data1_4),
.sctrdq_install_state (sct3rdq_install_state),
.sctrdq_unmapped_error (sct3rdq_unmapped_error),
.sctrdq_jid (sct3rdq_jid),
.sctrdq_data (sct3rdq_data),
.sctrdq_ue_err (sct3rdq_ue_err),
.sctrdq_dec_count (sct3rdq_dec_count),
.sctrdq_dequeue (sct3rdq_dequeue),
// Memory In (jbi_min).
.mout_scb_jbus_wr_ack (mout_scb3_jbus_wr_ack),
// Misc.
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
// Clock and reset.
.cclk (cclk),
.crst_l (crst_l),
.clk (clk),
.rst_l (rst_l),
.tx_en_local_m1 (tx_en_local_m1),
.arst_l (arst_l)
);
// YID to JID Translator.
jbi_jid_to_yid jid_to_yid (
// Translation, port 0.
.trans_jid0 (min_trans_jid[3:0]),
.trans_yid0 (mout_trans_yid),
.trans_valid0 (mout_trans_valid),
// Translation, port 1.
.trans_jid1 (nack_error_id[3:0]),
.trans_yid1 ({ignored[1:0], mout_nack_thr_id[5:0], mout_nack_buf_id[1:0]}),
.trans_valid1 (),
// Allocating an assignment.
.alloc_stall (),
.alloc (alloc),
.alloc_yid (ncio_yid),
.alloc_jid (unused_jid),
// Freeing an assignment, port 0.
.free0 (min_free),
.free_jid0 (min_free_jid),
// Freeing an assignment, port 1.
.free1 (ncio_mout_nack_pop),
.free_jid1 (nack_error_id[3:0]),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// Internal Arbiter.
jbi_int_arb int_arb (
// SCT0 RDQ.
.sct0rdq_data1_4 (sct0rdq_data1_4),
.sct0rdq_trans_count (sct0rdq_trans_count),
.sct0rdq_dec_count (sct0rdq_dec_count),
.sct0rdq_ue_err (sct0rdq_ue_err),
.sct0rdq_unmapped_error (sct0rdq_unmapped_error),
// SCT1 RDQ.
.sct1rdq_data1_4 (sct1rdq_data1_4),
.sct1rdq_trans_count (sct1rdq_trans_count),
.sct1rdq_dec_count (sct1rdq_dec_count),
.sct1rdq_ue_err (sct1rdq_ue_err),
.sct1rdq_unmapped_error (sct1rdq_unmapped_error),
// SCT2 RDQ.
.sct2rdq_data1_4 (sct2rdq_data1_4),
.sct2rdq_trans_count (sct2rdq_trans_count),
.sct2rdq_dec_count (sct2rdq_dec_count),
.sct2rdq_ue_err (sct2rdq_ue_err),
.sct2rdq_unmapped_error (sct2rdq_unmapped_error),
// SCT3 RDQ.
.sct3rdq_data1_4 (sct3rdq_data1_4),
.sct3rdq_trans_count (sct3rdq_trans_count),
.sct3rdq_dec_count (sct3rdq_dec_count),
.sct3rdq_ue_err (sct3rdq_ue_err),
.sct3rdq_unmapped_error (sct3rdq_unmapped_error),
// PIO RQQ.
.piorqq_req (ncio_pio_req),
.piorqq_req_rw (ncio_pio_req_rw),
.piorqq_req_dest (ncio_pio_req_dest),
.piorqq_req_adv (mout_pio_req_adv),
// PIO ACKQ.
.pioackq_req (ncio_mondo_req),
.pioackq_ack_nack (ncio_mondo_ack),
.pioackq_req_adv (),
// DEBUG ACKQ.
.dbg_req_transparent (dbg_req_transparent),
.dbg_req_arbitrate (dbg_req_arbitrate),
.dbg_req_priority (dbg_req_priority),
.dbg_req_adv (),
// JBus Arbiter.
.int_req (int_req),
// Arb Timeout support.
.have_trans_waiting (have_trans_waiting),
// JBus Packet Controller.
.int_requestors (int_requestors),
.int_req_type (int_req_type),
.int_granted (int_granted),
.parked_on_us (parked_on_us),
// Flow Control.
.ok_send_address_pkt (ok_send_address_pkt),
.ok_send_data_pkt_to_4 (ok_send_data_pkt_to_4),
.ok_send_data_pkt_to_5 (ok_send_data_pkt_to_5),
// CSRs and errors.
.jbi_log_arb_myreq (jbi_log_arb_myreq),
.jbi_log_arb_reqtype (jbi_log_arb_reqtype),
.csr_jbi_debug_arb_aggr_arb (csr_jbi_debug_arb_aggr_arb),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// JBus Arbiter.
jbi_jbus_arb jbus_arb (
// Configuration.
.csr_jbi_config_arb_mode (csr_jbi_config_arb_mode),
// Internal requests.
.int_req (int_req),
.multiple_in_progress (multiple_in_progress),
.multiple_ok (multiple_ok),
.parked_on_us (parked_on_us),
// External requests.
.io_jbi_j_req4_in_l (io_jbi_j_req4_in_l),
.io_jbi_j_req5_in_l (io_jbi_j_req5_in_l),
.jbi_io_j_req0_out_l (jbi_io_j_req0_out_l),
.jbi_io_j_req0_out_en (jbi_io_j_req0_out_en),
// Grant.
.stream_break_point (stream_break_point),
.grant (grant),
// CSRs and errors.
.mout_csr_err_arb_to (mout_csr_err_arb_to),
.csr_jbi_arb_timeout_timeval(csr_jbi_arb_timeout_timeval),
.have_trans_waiting (have_trans_waiting),
.piorqq_req (ncio_pio_req),
.int_requestor_piorqq (int_requestors[LRQ_PIORQQ_BIT]),
.jbi_log_arb_jreq (jbi_log_arb_jreq),
.mout_min_jbus_owner (mout_min_jbus_owner),
// I/O buffer enable for J_ADTYPE[], J_AD[], J_ADP[].
.jbi_io_j_adtype_en (jbi_io_j_adtype_en),
.jbi_io_j_ad_en (jbi_io_j_ad_en),
.jbi_io_j_adp_en (jbi_io_j_adp_en),
.mout_dsbl_sampling (mout_dsbl_sampling),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// JBus Packet Controller.
jbi_pktout_ctlr pktout_ctlr (
// JBus Arbiter.
.grant (grant),
.multiple_in_progress (multiple_in_progress),
.stream_break_point (stream_break_point),
// Internal Arbiter.
.multiple_ok (multiple_ok),
.int_req_type (int_req_type),
.int_requestors (int_requestors),
.int_granted (int_granted),
// Flow Control.
.ok_send_address_pkt (ok_send_address_pkt),
.ok_send_data_pkt_to_4 (ok_send_data_pkt_to_4),
.ok_send_data_pkt_to_5 (ok_send_data_pkt_to_5),
// Queues.
.sct0rdq_dequeue (sct0rdq_dequeue),
.sct1rdq_dequeue (sct1rdq_dequeue),
.sct2rdq_dequeue (sct2rdq_dequeue),
.sct3rdq_dequeue (sct3rdq_dequeue),
.piorqq_dequeue (mout_pio_pop),
.pioackq_dequeue (mout_mondo_pop),
.dbg_dequeue (mout_dbg_pop),
// Status bits.
.mout_scb0_jbus_rd_ack (mout_scb0_jbus_rd_ack),
.mout_scb1_jbus_rd_ack (mout_scb1_jbus_rd_ack),
.mout_scb2_jbus_rd_ack (mout_scb2_jbus_rd_ack),
.mout_scb3_jbus_rd_ack (mout_scb3_jbus_rd_ack),
.jbus_out_addr_cycle (jbus_out_addr_cycle),
.jbus_out_data_cycle (jbus_out_data_cycle),
// JID to PIO ID map.
.alloc (alloc),
// J_ADTYPE, J_AD, J_ADP busses.
.sel_j_adbus (sel_j_adbus),
.sel_queue (sel_queue),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// JBus Packet Assembler and Driver.
jbi_pktout_asm pktout_asm (
// Outbound Packet Controller.
.sel_j_adbus (sel_j_adbus),
.sel_queue (sel_queue),
// Queues.
// SCT0 RDQ.
.sct0rdq_install_state (sct0rdq_install_state),
.sct0rdq_unmapped_error (sct0rdq_unmapped_error),
.sct0rdq_jid (sct0rdq_jid),
.sct0rdq_data (sct0rdq_data),
.sct0rdq_ue_err (sct0rdq_ue_err),
// SCT1 RDQ.
.sct1rdq_install_state (sct1rdq_install_state),
.sct1rdq_unmapped_error (sct1rdq_unmapped_error),
.sct1rdq_jid (sct1rdq_jid),
.sct1rdq_data (sct1rdq_data),
.sct1rdq_ue_err (sct1rdq_ue_err),
// SCT2 RDQ.
.sct2rdq_install_state (sct2rdq_install_state),
.sct2rdq_unmapped_error (sct2rdq_unmapped_error),
.sct2rdq_jid (sct2rdq_jid),
.sct2rdq_data (sct2rdq_data),
.sct2rdq_ue_err (sct2rdq_ue_err),
// SCT3 RDQ.
.sct3rdq_install_state (sct3rdq_install_state),
.sct3rdq_unmapped_error (sct3rdq_unmapped_error),
.sct3rdq_jid (sct3rdq_jid),
.sct3rdq_data (sct3rdq_data),
.sct3rdq_ue_err (sct3rdq_ue_err),
// PIO RQQ.
.ncio_pio_ue (ncio_pio_ue),
.ncio_pio_be (ncio_pio_be),
.ncio_pio_ad (ncio_pio_ad),
// PIO ACKQ.
.ncio_mondo_agnt_id (ncio_mondo_agnt_id),
.ncio_mondo_cpu_id (ncio_mondo_cpu_id),
// DBGQ.
.dbg_data (dbg_data),
// YID-to-JID Translation.
.unused_jid ({ 2'b00, unused_jid }),
// J_ADTYPE, J_AD, J_ADP busses.
.jbi_io_j_adtype (jbi_io_j_adtype),
.jbi_io_j_ad (jbi_io_j_ad),
.jbi_io_j_adp (jbi_io_j_adp),
// Error injection.
.inj_err_j_ad (inj_err_j_ad),
// Debug Info.
.csr_jbi_debug_info_enb (csr_jbi_debug_info_enb), // Put these data fields in high half of JBus Address Cycles.
.thread_id (ncio_yid[`JBI_YID_THR_HI-1:`JBI_YID_THR_LO]),
.sct0rdq_trans_count (sct0rdq_trans_count[3:0]),
.sct1rdq_trans_count (sct1rdq_trans_count[3:0]),
.sct2rdq_trans_count (sct2rdq_trans_count[3:0]),
.sct3rdq_trans_count (sct3rdq_trans_count[3:0]),
.ncio_prqq_level (ncio_prqq_level[4:0]),
.ncio_makq_level (ncio_makq_level[4:0]),
// Clock.
.clk (clk)
);
// AOK/DOK Flow Control Tracking.
jbi_aok_dok_tracking aok_dok_tracking (
// J_PACK signals.
.j_pack0_m1 (jbi_io_j_pack0),
.j_pack1_m1 (jbi_io_j_pack1),
.j_pack4_p1 (io_jbi_j_pack4),
.j_pack5_p1 (io_jbi_j_pack5),
// Flow control signals.
.ok_send_data_pkt_to_4 (ok_send_data_pkt_to_4),
.ok_send_data_pkt_to_5 (ok_send_data_pkt_to_5),
.ok_send_address_pkt (ok_send_address_pkt),
// CSR Interface.
.jbi_log_arb_aok (jbi_log_arb_aok),
.jbi_log_arb_dok (jbi_log_arb_dok),
.mout_csr_err_fatal (mout_csr_err_fatal),
// Performance Counter events.
.mout_perf_aok_off (mout_perf_aok_off),
.mout_perf_dok_off (mout_perf_dok_off),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// Outbound Snoop Response Generator.
jbi_j_pack_out_gen j_pack_out_gen (
// COHACK response requests.
.min_snp_launch (min_snp_launch),
// Flow Control.
.send_aok_off (min_aok_off),
.send_aok_on (min_aok_on),
.send_dok_off (1'b0),
.send_dok_on (1'b0),
// Fatal error control.
.dok_fatal_req_csr (csr_dok_on),
.dok_fatal_req_sctag ({ sctag0_jbi_por_req_buf, sctag1_jbi_por_req_buf, sctag2_jbi_por_req_buf, sctag3_jbi_por_req_buf }),
.csr_jbi_error_config_fe_enb(csr_jbi_error_config_fe_enb),
// JPack out.
.jbi_io_j_pack0 (jbi_io_j_pack0),
.jbi_io_j_pack0_en (jbi_io_j_pack0_en),
.jbi_io_j_pack1 (jbi_io_j_pack1),
.jbi_io_j_pack1_en (jbi_io_j_pack1_en),
// Clock and reset.
.clk (clk),
.rst_l (rst_l),
.cclk (cclk),
.crst_l (crst_l),
.tx_en_local_m1 (tx_en_local_m1)
);
// CSR interface for errors and logging.
jbi_mout_csr mout_csr (
// Port Present detection.
.mout_port_4_present (mout_port_4_present),
.mout_port_5_present (mout_port_5_present),
// Transaction Timeout error detection.
.alloc (alloc),
.unused_jid (unused_jid),
.min_free (min_free),
.min_free_jid (min_free_jid),
.trans_timeout_timeval (csr_jbi_trans_timeout_timeval),
.mout_csr_err_read_to (mout_csr_err_read_to),
.mout_nack (mout_nack),
.nack_error_id (nack_error_id),
.ncio_mout_nack_pop (ncio_mout_nack_pop),
.csr_jbi_log_enb_read_to (csr_jbi_log_enb_read_to),
// J_PAR Error detection.
.j_par (io_jbi_j_par),
.j_req4_in_l_p1 (io_jbi_j_req4_in_l),
.j_req5_in_l_p1 (io_jbi_j_req5_in_l),
.j_req0_out_l_m1 (jbi_io_j_req0_out_l),
.j_pack0_m1 (jbi_io_j_pack0),
.j_pack1_m1 (jbi_io_j_pack1),
.j_pack4_p1 (io_jbi_j_pack4),
.j_pack5_p1 (io_jbi_j_pack5),
.mout_csr_err_cpar (mout_csr_err_cpar),
.mout_csr_jbi_log_par_jpar (mout_csr_jbi_log_par_jpar),
.mout_csr_jbi_log_par_jpack0(mout_csr_jbi_log_par_jpack0),
.mout_csr_jbi_log_par_jpack1(mout_csr_jbi_log_par_jpack1),
.mout_csr_jbi_log_par_jpack4(mout_csr_jbi_log_par_jpack4),
.mout_csr_jbi_log_par_jpack5(mout_csr_jbi_log_par_jpack5),
.mout_csr_jbi_log_par_jreq (mout_csr_jbi_log_par_jreq),
// JBus Error Injection control from JBI_ERR_INJECT.
.min_mout_inject_err (min_mout_inject_err),
.jbi_err_inject_xormask (csr_jbi_err_inject_xormask),
.jbi_err_inject_errtype (csr_jbi_err_inject_errtype),
.jbus_out_addr_cycle (jbus_out_addr_cycle),
.jbus_out_data_cycle (jbus_out_data_cycle),
.inj_err_j_ad (inj_err_j_ad),
.mout_min_inject_err_done (mout_min_inject_err_done),
.mout_csr_inject_output_done(mout_csr_inject_output_done),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
endmodule |
module sky130_fd_sc_lp__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
break_on_reset <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr;
//NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram, which is an nios_sp_ram
NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram_module NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_ociram_default_contents.dat";
`else
defparam NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00200020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001616 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h00200000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000000001;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
end
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 19: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 21: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 21: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 21: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 21: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] excaddr;
wire instr_retired;
wire is_advanced_exception;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
wire sync_pending;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign is_advanced_exception = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign excaddr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_pending = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_pending;
assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | is_advanced_exception)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_frametype <= 4'b0010;
pending_excaddr <= excaddr;
if (is_fast_tlb_miss_exception)
pending_exctype <= 1'b1;
else
pending_exctype <= 1'b0;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (pending_frametype == 4'b0010))
itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype};
else if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 21: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_trc_ctrl_td_mode, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_td_mode NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
)
;
output [ 1: 0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_tm_count;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_tm_count = 0;
end // 3'b000
3'b001: begin
compute_tm_count = 1;
end // 3'b001
3'b010: begin
compute_tm_count = 1;
end // 3'b010
3'b011: begin
compute_tm_count = 2;
end // 3'b011
3'b100: begin
compute_tm_count = 1;
end // 3'b100
3'b101: begin
compute_tm_count = 2;
end // 3'b101
3'b110: begin
compute_tm_count = 2;
end // 3'b110
3'b111: begin
compute_tm_count = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
)
;
output [ 3: 0] fifowp_inc;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 3: 0] fifowp_inc;
always @(free2 or free3 or tm_count)
begin
if (free3 & (tm_count == 3))
fifowp_inc = 3;
else if (free2 & (tm_count >= 2))
fifowp_inc = 2;
else if (tm_count >= 1)
fifowp_inc = 1;
else
fifowp_inc = 0;
end
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
)
;
output [ 4: 0] fifocount_inc;
input empty;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 4: 0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)
begin
if (empty)
fifocount_inc = tm_count[1 : 0];
else if (free3 & (tm_count == 3))
fifocount_inc = 2;
else if (free2 & (tm_count >= 2))
fifocount_inc = 1;
else if (tm_count >= 1)
fifocount_inc = 0;
else
fifocount_inc = {5{1'b1}};
end
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_tm_count_tm_count;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
wire [ 35: 0] fifo_read_mux;
reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifocount_inc_fifocount;
wire [ 35: 0] fifohead;
reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifowp1;
wire [ 3: 0] fifowp2;
wire [ 3: 0] fifowp_inc_fifowp;
wire free2;
wire free3;
wire itm_valid;
reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] ovr_pending_atm;
wire [ 35: 0] ovr_pending_dtm;
wire [ 1: 0] tm_count;
wire tm_count_ge1;
wire tm_count_ge2;
wire tm_count_ge3;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign free2 = ~fifocount[4];
assign free3 = ~fifocount[4] & ~&fifocount[3 : 0];
assign empty = ~|fifocount;
assign fifowp1 = fifowp + 1;
assign fifowp2 = fifowp + 2;
//NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_compute_tm_count_tm_count, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_compute_tm_count NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_compute_tm_count_tm_count
(
.atm_valid (atm_valid),
.compute_tm_count (compute_tm_count_tm_count),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign tm_count = compute_tm_count_tm_count;
//NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifowp_inc_fifowp, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifowp_inc NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifowp_inc_fifowp
(
.fifowp_inc (fifowp_inc_fifowp),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifocount_inc_fifocount, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifocount_inc NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifocount_inc_fifocount
(
.empty (empty),
.fifocount_inc (fifocount_inc_fifocount),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//the_NIOS_SYSTEMV3_NIOS_CPU_oci_test_bench, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_oci_test_bench the_NIOS_SYSTEMV3_NIOS_CPU_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fiforp <= 0;
fifowp <= 0;
fifocount <= 0;
ovf_pending <= 1;
end
else
begin
fifowp <= fifowp + fifowp_inc_fifowp;
fifocount <= fifocount + fifocount_inc_fifocount;
if (~empty)
fiforp <= fiforp + 1;
if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count)))
ovf_pending <= 1;
else if (atm_valid | dtm_valid)
ovf_pending <= 0;
end
end
assign fifohead = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm;
assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm :
(((fifowp == 4'd0) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm :
(((fifowp == 4'd1) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm :
(((fifowp == 4'd2) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm :
(((fifowp == 4'd3) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm :
(((fifowp == 4'd4) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm :
(((fifowp == 4'd5) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm :
(((fifowp == 4'd6) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm :
(((fifowp == 4'd7) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm :
(((fifowp == 4'd8) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm :
(((fifowp == 4'd9) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm :
(((fifowp == 4'd10) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm :
(((fifowp == 4'd11) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm :
(((fifowp == 4'd12) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm :
(((fifowp == 4'd13) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm :
(((fifowp == 4'd14) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm :
(((fifowp == 4'd15) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign tm_count_ge1 = |tm_count;
assign tm_count_ge2 = tm_count[1];
assign tm_count_ge3 = &tm_count;
assign ovr_pending_atm = {ovf_pending, atm[34 : 0]};
assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]};
assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 :
(fiforp == 4'd1)? fifo_1 :
(fiforp == 4'd2)? fifo_2 :
(fiforp == 4'd3)? fifo_3 :
(fiforp == 4'd4)? fifo_4 :
(fiforp == 4'd5)? fifo_5 :
(fiforp == 4'd6)? fifo_6 :
(fiforp == 4'd7)? fifo_7 :
(fiforp == 4'd8)? fifo_8 :
(fiforp == 4'd9)? fifo_9 :
(fiforp == 4'd10)? fifo_10 :
(fiforp == 4'd11)? fifo_11 :
(fiforp == 4'd12)? fifo_12 :
(fiforp == 4'd13)? fifo_13 :
(fiforp == 4'd14)? fifo_14 :
fifo_15;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
assign tracemem_trcdata = 0;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_performance_monitors
;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
test_ending,
test_has_ended,
write_nxt,
writedata_nxt,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 19: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 21: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input test_ending;
input test_has_ended;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire clkx2;
wire [ 21: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_debug the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_ocimem the_NIOS_SYSTEMV3_NIOS_CPU_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_avalon_reg the_NIOS_SYSTEMV3_NIOS_CPU_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_break the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_xbrk the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dbrk the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_itrace the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dtrace the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifo the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_pib the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_im the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign jtag_debug_module_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_wrapper the_NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule |
module NIOS_SYSTEMV3_NIOS_CPU (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_read,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
jtag_debug_module_waitrequest,
no_ci_readra
)
;
output [ 21: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 21: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output jtag_debug_module_waitrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_read;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 19: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 21: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 19: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 19: 0] F_pc_no_crst_nxt;
wire [ 19: 0] F_pc_nxt;
wire [ 19: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 21: 0] F_pcb;
wire [ 21: 0] F_pcb_nxt;
wire [ 21: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 21: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 21: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
wire d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 21: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire jtag_debug_module_waitrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_NIOS_SYSTEMV3_NIOS_CPU_test_bench, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_test_bench the_NIOS_SYSTEMV3_NIOS_CPU_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.d_write_nxt (d_write_nxt),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000001;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 524296 :
(F_pc_sel_nxt == 2'b01)? 526856 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[21 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 524288;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//NIOS_SYSTEMV3_NIOS_CPU_register_bank_a, which is an nios_sdp_ram
NIOS_SYSTEMV3_NIOS_CPU_register_bank_a_module NIOS_SYSTEMV3_NIOS_CPU_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_a.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_a.dat";
`else
defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_a.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_a.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//NIOS_SYSTEMV3_NIOS_CPU_register_bank_b, which is an nios_sdp_ram
NIOS_SYSTEMV3_NIOS_CPU_register_bank_b_module NIOS_SYSTEMV3_NIOS_CPU_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_b.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_b.dat";
`else
defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_b.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_b.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[21 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
0;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[21 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000001;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000001;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (jtag_debug_module_byteenable),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess_nxt (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (jtag_debug_module_read),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.waitrequest (jtag_debug_module_waitrequest),
.write_nxt (jtag_debug_module_write),
.writedata_nxt (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule |
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule |
module decrypt_tb;
// Inputs
reg [63:0] message;
reg [63:0] DESkey;
reg clk;
reg reset;
reg enable;
reg ack;
integer clk_cnt;
parameter CLK_PERIOD = 10;
// Outputs
wire [63:0] decrypted;
wire done;
// Instantiate the Unit Under Test (UUT)
decrypt_dumb uut (
.message(message),
.DESkey(DESkey),
.decrypted(decrypted),
.done(done),
.clk(clk),
.reset(reset),
.enable(enable),
.ack(ack)
);
initial
begin : CLK_GENERATOR
clk = 0;
forever
begin
#(CLK_PERIOD/2) clk = ~clk;
end
end
initial
begin : RESET_GENERATOR
reset = 1;
#(10 * CLK_PERIOD) reset = 0;
end
initial
begin : CLK_COUNTER
clk_cnt = 0;
forever
begin
#(CLK_PERIOD) clk_cnt = clk_cnt + 1;
end
end
initial begin
// Initialize Inputs
message = 0;
DESkey = 0;
enable = 0;
ack = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
message = 64'b1110000010100110111110111111100010010010011001011010011101100101;
DESkey = 64'h133457799BBCDFF1;
enable = 1;
wait(done);
ack = 1;
# 100;
DESkey = 64'h133457799BBCDFF0;
wait(done);
ack = 1;
# 100;
DESkey = 64'hab01986231bc8d01;
//ack = 1;
# 10;
end
endmodule |
module blockram
(input wire clock
,input wire rst
,output mem_waitrequest
,input [1:0] mem_id
,input [29:0] mem_address
,input mem_read
,input mem_write
,input [31:0] mem_writedata
,input [3:0] mem_writedatamask
,output [31:0] mem_readdata
,output reg [1:0] mem_readdataid = 0
);
parameter burst_bits = 2;
parameter size = 18; // 4 * 2^18 = 1 MiB
parameter INIT_FILE = "";
parameter burst_length = 1 << burst_bits;
wire sel = mem_address[29:26] == 'h4;
reg [burst_bits:0] cnt = ~0;
reg [size-1:0] read_address = 0;
assign mem_waitrequest = !cnt[burst_bits];
dpram memory(.clock(clock),
.address_a(mem_waitrequest
? read_address
: mem_address[size-1:0]),
.byteena_a(mem_writedatamask),
.wrdata_a(mem_writedata),
.wren_a(!mem_waitrequest & sel & mem_write),
.rddata_a(mem_readdata),
.address_b(0),
.byteena_b(0),
.wrdata_b(0),
.wren_b(0),
.rddata_b());
defparam
memory.DATA_WIDTH = 32,
memory.ADDR_WIDTH = size,
memory.INIT_FILE = INIT_FILE;
always @(posedge clock)
if (mem_waitrequest) begin
cnt <= cnt - 1;
read_address <= read_address + 1;
end else begin
mem_readdataid <= 0;
if (sel & mem_read) begin
read_address <= mem_address[size-1:0] + 1;
mem_readdataid <= mem_id;
cnt <= burst_length - 2;
end
end
`define DEBUG_BLOCKRAM 1
`ifdef DEBUG_BLOCKRAM
always @(posedge clock) begin
if (!mem_waitrequest & sel & mem_read)
$display("%05d blockram[%x] -> ? for %d", $time,
{mem_address,2'd0}, mem_id);
if (!mem_waitrequest & sel & mem_write)
$display("%05d blockram[%x] <- %8x/%x", $time,
{mem_address,2'd0}, mem_writedata, mem_writedatamask);
if (mem_readdataid)
$display("%05d blockram[%x] -> %8x for %d", $time,
32'h3fff_fffc + (read_address << 2), mem_readdata, mem_readdataid);
end
`endif
endmodule |
module sky130_fd_sc_lp__buf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A)
);
endmodule |
module flow_classification
(// --- data path interface
output [63:0] out_data0,
output [23:0] out_pkt_route0,
output out_wr0,
output reg out_req0,
input out_ack0,
output out_bypass0,
output [63:0] out_data1,
output [23:0] out_pkt_route1,
output out_wr1,
output reg out_req1,
input out_ack1,
output out_bypass1,
input [63:0] in_data,
input [7:0] in_ctrl,
input in_wr,
output in_rdy,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [1:0] reg_src_out,
// --- Misc
input clk,
input reset
);
assign reg_req_out = reg_req_in;
assign reg_ack_out = reg_ack_in;
assign reg_rd_wr_L_out = reg_rd_wr_L_in;
assign reg_addr_out = reg_addr_in;
assign reg_data_out = reg_data_in;
assign reg_src_out = reg_src_in;
reg [63:0] out_data[1:0];
reg [23:0] out_pkt_route[1:0];
reg [1:0] out_wr;
reg [1:0] out_req;
reg [1:0] out_ack;
reg [1:0] out_bypass;
assign out_data0 = out_data[0];
assign out_data1 = out_data[1];
assign out_pkt_route0 = out_pkt_route[0];
assign out_pkt_route1 = out_pkt_route[1];
assign out_wr0 = out_wr[0];
assign out_wr1 = out_wr[1];
assign out_bypass0 = out_bypass[0];
assign out_bypass1 = out_bypass[1];
reg in_rdy_reg;
assign in_rdy = in_rdy_reg;
reg wr_curr;
reg wr_prev;
wire eop;
assign eop = ((wr_curr == 0) && (wr_prev != 0)) ? 1 : 0;
reg [2:0] state;
reg [2:0] state_next;
parameter FC_IDLE = 3'b001,
FC_LOOKUP_ROUTE = 3'b010,
FC_REQ = 3'b011,
FC_ACK = 3'b100,
FC_TX = 3'b101,
FC_CANCEL_REQ = 3'b110,
FC_WAIT_ACK = 3'b111;
reg [1:0] pkt_count;
wire [1:0] pkt_count_plus_1;
assign pkt_count_plus_1 = (pkt_count == 2'b00) ? 0 : pkt_count + 1;
reg curr_output;
//assign curr_output = pkt_count[1];
always @(*) begin
out_req = 0;
in_rdy_reg = 0;
state_next = state;
case(state)
FC_IDLE: begin
// curr_output = 0;
out_req = 0;
in_rdy_reg = 0;
state_next = FC_LOOKUP_ROUTE;
end
FC_LOOKUP_ROUTE: begin
curr_output = pkt_count[1];
if(pkt_count[0] == 1'b1) begin
out_pkt_route[curr_output] = 24'b000_000_000_000_000_000_111_011;
out_bypass[curr_output] = 0;
end else begin
out_pkt_route[curr_output] = 24'b000_000_000_000_000_000_011_111;
out_bypass[curr_output] = 1;
end
state_next = FC_REQ;
end
FC_REQ: begin
out_req[curr_output] = 1;
state_next = FC_ACK;
end
FC_ACK: begin
out_req[curr_output] = 1;
if(out_ack[curr_output]) begin
state_next = FC_TX;
end
end
FC_TX: begin
out_req[curr_output] = 1;
in_rdy_reg = 1;
if(eop) begin
in_rdy_reg = 0;
state_next = FC_CANCEL_REQ;
end
end
FC_CANCEL_REQ: begin
in_rdy_reg = 0;
out_req[curr_output] = 0;
state_next = FC_WAIT_ACK;
end
FC_WAIT_ACK: begin
if(!out_ack[curr_output]) begin
state_next = FC_IDLE;
end
end
default: begin
state_next = FC_IDLE;
end
endcase
end
always @(posedge clk) begin
if(reset) begin
state <= 0;
pkt_count <= 0;
end else begin
state <= state_next;
out_req0 <= out_req[0];
out_req1 <= out_req[1];
out_ack[0] <= out_ack0;
out_ack[1] <= out_ack1;
out_data[curr_output] <= in_data;
out_wr[curr_output] <= in_wr;
wr_prev <= wr_curr;
wr_curr <= in_wr;
if(state == FC_IDLE) begin
pkt_count <= pkt_count_plus_1;
end
end
end
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
/*
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_v1_02_a cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0)
);
assign TRIG0[63:0] = in_data;
assign TRIG0[71:64] = in_ctrl;
assign TRIG0[80] = in_wr;
assign TRIG0[81] = in_rdy;
assign TRIG0[89:82] = out_data1[7:0];
assign TRIG0[98:90] = out_pkt_route1[8:0];
assign TRIG0[163:100] = out_data0;
assign TRIG0[179:164] = out_pkt_route0;
assign TRIG0[180] = out_wr0;
assign TRIG0[181] = out_req0;
assign TRIG0[182] = out_ack0;
assign TRIG0[183] = out_bypass0;
assign TRIG0[184] = out_wr1;
assign TRIG0[185] = out_req1;
assign TRIG0[186] = out_ack1;
assign TRIG0[187] = out_bypass1;
assign TRIG0[202:200] = state;
assign TRIG0[205:203] = state_next;
assign TRIG0[206] = eop;
*/
endmodule |
module tx_reset_sm
(
input refclkdiv2,
input rst_n,
input tx_pll_lol_qd_s,
output reg tx_pcs_rst_ch_c, //TX Lane Reset (modified to have one bit)
output reg rst_qd_c // QUAD Reset
);
parameter count_index = 17;
// States of LSM
localparam QUAD_RESET = 0,
WAIT_FOR_TIMER1 = 1,
CHECK_PLOL = 2,
WAIT_FOR_TIMER2 = 3,
NORMAL = 4;
localparam STATEWIDTH =3;
// Flop variables
reg [STATEWIDTH-1:0] cs /*synthesis syn_encoding="safe, gray"*/; // current state of lsm
// Combinational logic variables
reg [STATEWIDTH-1:0] ns; // next state of lsm
reg tx_pll_lol_qd_s_int;
reg tx_pll_lol_qd_s_int1;
reg [3:0] tx_pcs_rst_ch_c_int; //TX Lane Reset
reg rst_qd_c_int; // QUAD Reset
//SEQUENTIAL
always @(posedge refclkdiv2 or negedge rst_n)
begin
if (rst_n == 1'b0)
begin
cs <= QUAD_RESET;
tx_pll_lol_qd_s_int <= 1;
tx_pll_lol_qd_s_int1 <= 1;
tx_pcs_rst_ch_c <= 1'b1;
rst_qd_c <= 1;
end
else
begin
cs <= ns;
tx_pll_lol_qd_s_int1 <= tx_pll_lol_qd_s;
tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s_int1;
tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int[0];
rst_qd_c <= rst_qd_c_int;
end
end
//
reg reset_timer1, reset_timer2;
//TIMER1 = 20ns;
//Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
// A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
localparam TIMER1WIDTH=3;
reg [TIMER1WIDTH-1:0] counter1;
reg TIMER1;
always @(posedge refclkdiv2 or posedge reset_timer1)
begin
if (reset_timer1)
begin
counter1 <= 0;
TIMER1 <= 0;
end
else
begin
if (counter1[2] == 1)
TIMER1 <=1;
else
begin
TIMER1 <=0;
counter1 <= counter1 + 1 ;
end
end
end
//TIMER2 = 1,400,000 UI;
//WORST CASE CYCLES is with smallest multipier factor.
// This would be with X8 clock multiplier in DIV2 mode
// IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
// SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
// An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
//localparam TIMER2WIDTH=19;
//1,400,000 * 400 ps / 20 ns = 28000
// so a 16 bit counter is enough
localparam TIMER2WIDTH=18;
reg [TIMER2WIDTH-1:0] counter2;
reg TIMER2;
always @(posedge refclkdiv2 or posedge reset_timer2)
begin
if (reset_timer2)
begin
counter2 <= 0;
TIMER2 <= 0;
end
else
begin
// `ifdef SIM //IF SIM parameter is set, define lower value
// //TO SAVE SIMULATION TIME
// if (counter2[4] == 1)
// `else
// if (counter2[18] == 1)
// `endif
if (counter2[count_index] == 1)
TIMER2 <=1;
else
begin
TIMER2 <=0;
counter2 <= counter2 + 1 ;
end
end
end
always @(*)
begin : NEXT_STATE
reset_timer1 = 0;
reset_timer2 = 0;
case (cs)
QUAD_RESET: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 1;
reset_timer1 = 1;
ns = WAIT_FOR_TIMER1;
end
WAIT_FOR_TIMER1: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 1;
if (TIMER1)
ns = CHECK_PLOL;
else
ns = WAIT_FOR_TIMER1;
end
CHECK_PLOL: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 0;
reset_timer2 = 1;
ns = WAIT_FOR_TIMER2;
end
WAIT_FOR_TIMER2: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 0;
if (TIMER2)
if (tx_pll_lol_qd_s_int)
ns = QUAD_RESET;
else
ns = NORMAL;
else
ns = WAIT_FOR_TIMER2;
end
NORMAL: begin
tx_pcs_rst_ch_c_int = 4'h0;
rst_qd_c_int = 0;
if (tx_pll_lol_qd_s_int)
ns = QUAD_RESET;
else
ns = NORMAL;
end
// prevent lockup in undefined state
default: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 1;
ns = QUAD_RESET;
end
endcase // case
end //NEXT_STATE
endmodule |
module system_acl_iface_acl_kernel_interface_mm_interconnect_1 (
input wire clk_reset_clk_clk, // clk_reset_clk.clk
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cntrl_reset_reset_bridge_in_reset_reset, // kernel_cntrl_reset_reset_bridge_in_reset.reset
input wire sw_reset_clk_reset_reset_bridge_in_reset_reset, // sw_reset_clk_reset_reset_bridge_in_reset.reset
input wire [13:0] kernel_cntrl_m0_address, // kernel_cntrl_m0.address
output wire kernel_cntrl_m0_waitrequest, // .waitrequest
input wire [0:0] kernel_cntrl_m0_burstcount, // .burstcount
input wire [3:0] kernel_cntrl_m0_byteenable, // .byteenable
input wire kernel_cntrl_m0_read, // .read
output wire [31:0] kernel_cntrl_m0_readdata, // .readdata
output wire kernel_cntrl_m0_readdatavalid, // .readdatavalid
input wire kernel_cntrl_m0_write, // .write
input wire [31:0] kernel_cntrl_m0_writedata, // .writedata
input wire kernel_cntrl_m0_debugaccess, // .debugaccess
output wire address_span_extender_0_cntl_write, // address_span_extender_0_cntl.write
output wire address_span_extender_0_cntl_read, // .read
input wire [63:0] address_span_extender_0_cntl_readdata, // .readdata
output wire [63:0] address_span_extender_0_cntl_writedata, // .writedata
output wire [7:0] address_span_extender_0_cntl_byteenable, // .byteenable
output wire [9:0] address_span_extender_0_windowed_slave_address, // address_span_extender_0_windowed_slave.address
output wire address_span_extender_0_windowed_slave_write, // .write
output wire address_span_extender_0_windowed_slave_read, // .read
input wire [31:0] address_span_extender_0_windowed_slave_readdata, // .readdata
output wire [31:0] address_span_extender_0_windowed_slave_writedata, // .writedata
output wire [0:0] address_span_extender_0_windowed_slave_burstcount, // .burstcount
output wire [3:0] address_span_extender_0_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_0_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_0_windowed_slave_waitrequest, // .waitrequest
output wire irq_ena_0_s_write, // irq_ena_0_s.write
output wire irq_ena_0_s_read, // .read
input wire [31:0] irq_ena_0_s_readdata, // .readdata
output wire [31:0] irq_ena_0_s_writedata, // .writedata
output wire [3:0] irq_ena_0_s_byteenable, // .byteenable
input wire irq_ena_0_s_waitrequest, // .waitrequest
output wire mem_org_mode_s_write, // mem_org_mode_s.write
output wire mem_org_mode_s_read, // .read
input wire [31:0] mem_org_mode_s_readdata, // .readdata
output wire [31:0] mem_org_mode_s_writedata, // .writedata
input wire mem_org_mode_s_waitrequest, // .waitrequest
output wire sw_reset_s_write, // sw_reset_s.write
output wire sw_reset_s_read, // .read
input wire [63:0] sw_reset_s_readdata, // .readdata
output wire [63:0] sw_reset_s_writedata, // .writedata
output wire [7:0] sw_reset_s_byteenable, // .byteenable
input wire sw_reset_s_waitrequest, // .waitrequest
output wire [8:0] sys_description_rom_s1_address, // sys_description_rom_s1.address
output wire sys_description_rom_s1_write, // .write
input wire [63:0] sys_description_rom_s1_readdata, // .readdata
output wire [63:0] sys_description_rom_s1_writedata, // .writedata
output wire [7:0] sys_description_rom_s1_byteenable, // .byteenable
output wire sys_description_rom_s1_chipselect, // .chipselect
output wire sys_description_rom_s1_clken, // .clken
output wire sys_description_rom_s1_debugaccess, // .debugaccess
output wire version_id_0_s_read, // version_id_0_s.read
input wire [31:0] version_id_0_s_readdata // .readdata
);
wire kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest; // kernel_cntrl_m0_agent:av_waitrequest -> kernel_cntrl_m0_translator:uav_waitrequest
wire [2:0] kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount; // kernel_cntrl_m0_translator:uav_burstcount -> kernel_cntrl_m0_agent:av_burstcount
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_writedata; // kernel_cntrl_m0_translator:uav_writedata -> kernel_cntrl_m0_agent:av_writedata
wire [13:0] kernel_cntrl_m0_translator_avalon_universal_master_0_address; // kernel_cntrl_m0_translator:uav_address -> kernel_cntrl_m0_agent:av_address
wire kernel_cntrl_m0_translator_avalon_universal_master_0_lock; // kernel_cntrl_m0_translator:uav_lock -> kernel_cntrl_m0_agent:av_lock
wire kernel_cntrl_m0_translator_avalon_universal_master_0_write; // kernel_cntrl_m0_translator:uav_write -> kernel_cntrl_m0_agent:av_write
wire kernel_cntrl_m0_translator_avalon_universal_master_0_read; // kernel_cntrl_m0_translator:uav_read -> kernel_cntrl_m0_agent:av_read
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_readdata; // kernel_cntrl_m0_agent:av_readdata -> kernel_cntrl_m0_translator:uav_readdata
wire kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess; // kernel_cntrl_m0_translator:uav_debugaccess -> kernel_cntrl_m0_agent:av_debugaccess
wire [3:0] kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable; // kernel_cntrl_m0_translator:uav_byteenable -> kernel_cntrl_m0_agent:av_byteenable
wire kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid; // kernel_cntrl_m0_agent:av_readdatavalid -> kernel_cntrl_m0_translator:uav_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_waitrequest; // address_span_extender_0_windowed_slave_translator:uav_waitrequest -> address_span_extender_0_windowed_slave_agent:m0_waitrequest
wire [2:0] address_span_extender_0_windowed_slave_agent_m0_burstcount; // address_span_extender_0_windowed_slave_agent:m0_burstcount -> address_span_extender_0_windowed_slave_translator:uav_burstcount
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_writedata; // address_span_extender_0_windowed_slave_agent:m0_writedata -> address_span_extender_0_windowed_slave_translator:uav_writedata
wire [13:0] address_span_extender_0_windowed_slave_agent_m0_address; // address_span_extender_0_windowed_slave_agent:m0_address -> address_span_extender_0_windowed_slave_translator:uav_address
wire address_span_extender_0_windowed_slave_agent_m0_write; // address_span_extender_0_windowed_slave_agent:m0_write -> address_span_extender_0_windowed_slave_translator:uav_write
wire address_span_extender_0_windowed_slave_agent_m0_lock; // address_span_extender_0_windowed_slave_agent:m0_lock -> address_span_extender_0_windowed_slave_translator:uav_lock
wire address_span_extender_0_windowed_slave_agent_m0_read; // address_span_extender_0_windowed_slave_agent:m0_read -> address_span_extender_0_windowed_slave_translator:uav_read
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_readdata; // address_span_extender_0_windowed_slave_translator:uav_readdata -> address_span_extender_0_windowed_slave_agent:m0_readdata
wire address_span_extender_0_windowed_slave_agent_m0_readdatavalid; // address_span_extender_0_windowed_slave_translator:uav_readdatavalid -> address_span_extender_0_windowed_slave_agent:m0_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_debugaccess; // address_span_extender_0_windowed_slave_agent:m0_debugaccess -> address_span_extender_0_windowed_slave_translator:uav_debugaccess
wire [3:0] address_span_extender_0_windowed_slave_agent_m0_byteenable; // address_span_extender_0_windowed_slave_agent:m0_byteenable -> address_span_extender_0_windowed_slave_translator:uav_byteenable
wire address_span_extender_0_windowed_slave_agent_rf_source_endofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_endofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_windowed_slave_agent_rf_source_valid; // address_span_extender_0_windowed_slave_agent:rf_source_valid -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_valid
wire address_span_extender_0_windowed_slave_agent_rf_source_startofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_startofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rf_source_data; // address_span_extender_0_windowed_slave_agent:rf_source_data -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rf_source_ready; // address_span_extender_0_windowed_slave_agent_rsp_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rf_source_ready
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rf_sink_valid
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rf_sink_data
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rf_sink_ready -> address_span_extender_0_windowed_slave_agent_rsp_fifo:out_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_valid -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_data -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready; // address_span_extender_0_windowed_slave_agent_rdata_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rdata_fifo_src_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_ready -> address_span_extender_0_windowed_slave_agent_rdata_fifo:out_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> address_span_extender_0_windowed_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> address_span_extender_0_windowed_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> address_span_extender_0_windowed_slave_agent:cp_startofpacket
wire [88:0] cmd_mux_src_data; // cmd_mux:src_data -> address_span_extender_0_windowed_slave_agent:cp_data
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> address_span_extender_0_windowed_slave_agent:cp_channel
wire cmd_mux_src_ready; // address_span_extender_0_windowed_slave_agent:cp_ready -> cmd_mux:src_ready
wire address_span_extender_0_cntl_agent_m0_waitrequest; // address_span_extender_0_cntl_translator:uav_waitrequest -> address_span_extender_0_cntl_agent:m0_waitrequest
wire [3:0] address_span_extender_0_cntl_agent_m0_burstcount; // address_span_extender_0_cntl_agent:m0_burstcount -> address_span_extender_0_cntl_translator:uav_burstcount
wire [63:0] address_span_extender_0_cntl_agent_m0_writedata; // address_span_extender_0_cntl_agent:m0_writedata -> address_span_extender_0_cntl_translator:uav_writedata
wire [13:0] address_span_extender_0_cntl_agent_m0_address; // address_span_extender_0_cntl_agent:m0_address -> address_span_extender_0_cntl_translator:uav_address
wire address_span_extender_0_cntl_agent_m0_write; // address_span_extender_0_cntl_agent:m0_write -> address_span_extender_0_cntl_translator:uav_write
wire address_span_extender_0_cntl_agent_m0_lock; // address_span_extender_0_cntl_agent:m0_lock -> address_span_extender_0_cntl_translator:uav_lock
wire address_span_extender_0_cntl_agent_m0_read; // address_span_extender_0_cntl_agent:m0_read -> address_span_extender_0_cntl_translator:uav_read
wire [63:0] address_span_extender_0_cntl_agent_m0_readdata; // address_span_extender_0_cntl_translator:uav_readdata -> address_span_extender_0_cntl_agent:m0_readdata
wire address_span_extender_0_cntl_agent_m0_readdatavalid; // address_span_extender_0_cntl_translator:uav_readdatavalid -> address_span_extender_0_cntl_agent:m0_readdatavalid
wire address_span_extender_0_cntl_agent_m0_debugaccess; // address_span_extender_0_cntl_agent:m0_debugaccess -> address_span_extender_0_cntl_translator:uav_debugaccess
wire [7:0] address_span_extender_0_cntl_agent_m0_byteenable; // address_span_extender_0_cntl_agent:m0_byteenable -> address_span_extender_0_cntl_translator:uav_byteenable
wire address_span_extender_0_cntl_agent_rf_source_endofpacket; // address_span_extender_0_cntl_agent:rf_source_endofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_cntl_agent_rf_source_valid; // address_span_extender_0_cntl_agent:rf_source_valid -> address_span_extender_0_cntl_agent_rsp_fifo:in_valid
wire address_span_extender_0_cntl_agent_rf_source_startofpacket; // address_span_extender_0_cntl_agent:rf_source_startofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rf_source_data; // address_span_extender_0_cntl_agent:rf_source_data -> address_span_extender_0_cntl_agent_rsp_fifo:in_data
wire address_span_extender_0_cntl_agent_rf_source_ready; // address_span_extender_0_cntl_agent_rsp_fifo:in_ready -> address_span_extender_0_cntl_agent:rf_source_ready
wire address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_cntl_agent:rf_sink_endofpacket
wire address_span_extender_0_cntl_agent_rsp_fifo_out_valid; // address_span_extender_0_cntl_agent_rsp_fifo:out_valid -> address_span_extender_0_cntl_agent:rf_sink_valid
wire address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_cntl_agent:rf_sink_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rsp_fifo_out_data; // address_span_extender_0_cntl_agent_rsp_fifo:out_data -> address_span_extender_0_cntl_agent:rf_sink_data
wire address_span_extender_0_cntl_agent_rsp_fifo_out_ready; // address_span_extender_0_cntl_agent:rf_sink_ready -> address_span_extender_0_cntl_agent_rsp_fifo:out_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_src_valid; // address_span_extender_0_cntl_agent:rdata_fifo_src_valid -> address_span_extender_0_cntl_agent_rdata_fifo:in_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_src_data; // address_span_extender_0_cntl_agent:rdata_fifo_src_data -> address_span_extender_0_cntl_agent_rdata_fifo:in_data
wire address_span_extender_0_cntl_agent_rdata_fifo_src_ready; // address_span_extender_0_cntl_agent_rdata_fifo:in_ready -> address_span_extender_0_cntl_agent:rdata_fifo_src_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_out_valid; // address_span_extender_0_cntl_agent_rdata_fifo:out_valid -> address_span_extender_0_cntl_agent:rdata_fifo_sink_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_out_data; // address_span_extender_0_cntl_agent_rdata_fifo:out_data -> address_span_extender_0_cntl_agent:rdata_fifo_sink_data
wire address_span_extender_0_cntl_agent_rdata_fifo_out_ready; // address_span_extender_0_cntl_agent:rdata_fifo_sink_ready -> address_span_extender_0_cntl_agent_rdata_fifo:out_ready
wire sys_description_rom_s1_agent_m0_waitrequest; // sys_description_rom_s1_translator:uav_waitrequest -> sys_description_rom_s1_agent:m0_waitrequest
wire [3:0] sys_description_rom_s1_agent_m0_burstcount; // sys_description_rom_s1_agent:m0_burstcount -> sys_description_rom_s1_translator:uav_burstcount
wire [63:0] sys_description_rom_s1_agent_m0_writedata; // sys_description_rom_s1_agent:m0_writedata -> sys_description_rom_s1_translator:uav_writedata
wire [13:0] sys_description_rom_s1_agent_m0_address; // sys_description_rom_s1_agent:m0_address -> sys_description_rom_s1_translator:uav_address
wire sys_description_rom_s1_agent_m0_write; // sys_description_rom_s1_agent:m0_write -> sys_description_rom_s1_translator:uav_write
wire sys_description_rom_s1_agent_m0_lock; // sys_description_rom_s1_agent:m0_lock -> sys_description_rom_s1_translator:uav_lock
wire sys_description_rom_s1_agent_m0_read; // sys_description_rom_s1_agent:m0_read -> sys_description_rom_s1_translator:uav_read
wire [63:0] sys_description_rom_s1_agent_m0_readdata; // sys_description_rom_s1_translator:uav_readdata -> sys_description_rom_s1_agent:m0_readdata
wire sys_description_rom_s1_agent_m0_readdatavalid; // sys_description_rom_s1_translator:uav_readdatavalid -> sys_description_rom_s1_agent:m0_readdatavalid
wire sys_description_rom_s1_agent_m0_debugaccess; // sys_description_rom_s1_agent:m0_debugaccess -> sys_description_rom_s1_translator:uav_debugaccess
wire [7:0] sys_description_rom_s1_agent_m0_byteenable; // sys_description_rom_s1_agent:m0_byteenable -> sys_description_rom_s1_translator:uav_byteenable
wire sys_description_rom_s1_agent_rf_source_endofpacket; // sys_description_rom_s1_agent:rf_source_endofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_endofpacket
wire sys_description_rom_s1_agent_rf_source_valid; // sys_description_rom_s1_agent:rf_source_valid -> sys_description_rom_s1_agent_rsp_fifo:in_valid
wire sys_description_rom_s1_agent_rf_source_startofpacket; // sys_description_rom_s1_agent:rf_source_startofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_startofpacket
wire [125:0] sys_description_rom_s1_agent_rf_source_data; // sys_description_rom_s1_agent:rf_source_data -> sys_description_rom_s1_agent_rsp_fifo:in_data
wire sys_description_rom_s1_agent_rf_source_ready; // sys_description_rom_s1_agent_rsp_fifo:in_ready -> sys_description_rom_s1_agent:rf_source_ready
wire sys_description_rom_s1_agent_rsp_fifo_out_endofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_endofpacket -> sys_description_rom_s1_agent:rf_sink_endofpacket
wire sys_description_rom_s1_agent_rsp_fifo_out_valid; // sys_description_rom_s1_agent_rsp_fifo:out_valid -> sys_description_rom_s1_agent:rf_sink_valid
wire sys_description_rom_s1_agent_rsp_fifo_out_startofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_startofpacket -> sys_description_rom_s1_agent:rf_sink_startofpacket
wire [125:0] sys_description_rom_s1_agent_rsp_fifo_out_data; // sys_description_rom_s1_agent_rsp_fifo:out_data -> sys_description_rom_s1_agent:rf_sink_data
wire sys_description_rom_s1_agent_rsp_fifo_out_ready; // sys_description_rom_s1_agent:rf_sink_ready -> sys_description_rom_s1_agent_rsp_fifo:out_ready
wire sys_description_rom_s1_agent_rdata_fifo_src_valid; // sys_description_rom_s1_agent:rdata_fifo_src_valid -> sys_description_rom_s1_agent:rdata_fifo_sink_valid
wire [65:0] sys_description_rom_s1_agent_rdata_fifo_src_data; // sys_description_rom_s1_agent:rdata_fifo_src_data -> sys_description_rom_s1_agent:rdata_fifo_sink_data
wire sys_description_rom_s1_agent_rdata_fifo_src_ready; // sys_description_rom_s1_agent:rdata_fifo_sink_ready -> sys_description_rom_s1_agent:rdata_fifo_src_ready
wire sw_reset_s_agent_m0_waitrequest; // sw_reset_s_translator:uav_waitrequest -> sw_reset_s_agent:m0_waitrequest
wire [3:0] sw_reset_s_agent_m0_burstcount; // sw_reset_s_agent:m0_burstcount -> sw_reset_s_translator:uav_burstcount
wire [63:0] sw_reset_s_agent_m0_writedata; // sw_reset_s_agent:m0_writedata -> sw_reset_s_translator:uav_writedata
wire [13:0] sw_reset_s_agent_m0_address; // sw_reset_s_agent:m0_address -> sw_reset_s_translator:uav_address
wire sw_reset_s_agent_m0_write; // sw_reset_s_agent:m0_write -> sw_reset_s_translator:uav_write
wire sw_reset_s_agent_m0_lock; // sw_reset_s_agent:m0_lock -> sw_reset_s_translator:uav_lock
wire sw_reset_s_agent_m0_read; // sw_reset_s_agent:m0_read -> sw_reset_s_translator:uav_read
wire [63:0] sw_reset_s_agent_m0_readdata; // sw_reset_s_translator:uav_readdata -> sw_reset_s_agent:m0_readdata
wire sw_reset_s_agent_m0_readdatavalid; // sw_reset_s_translator:uav_readdatavalid -> sw_reset_s_agent:m0_readdatavalid
wire sw_reset_s_agent_m0_debugaccess; // sw_reset_s_agent:m0_debugaccess -> sw_reset_s_translator:uav_debugaccess
wire [7:0] sw_reset_s_agent_m0_byteenable; // sw_reset_s_agent:m0_byteenable -> sw_reset_s_translator:uav_byteenable
wire sw_reset_s_agent_rf_source_endofpacket; // sw_reset_s_agent:rf_source_endofpacket -> sw_reset_s_agent_rsp_fifo:in_endofpacket
wire sw_reset_s_agent_rf_source_valid; // sw_reset_s_agent:rf_source_valid -> sw_reset_s_agent_rsp_fifo:in_valid
wire sw_reset_s_agent_rf_source_startofpacket; // sw_reset_s_agent:rf_source_startofpacket -> sw_reset_s_agent_rsp_fifo:in_startofpacket
wire [125:0] sw_reset_s_agent_rf_source_data; // sw_reset_s_agent:rf_source_data -> sw_reset_s_agent_rsp_fifo:in_data
wire sw_reset_s_agent_rf_source_ready; // sw_reset_s_agent_rsp_fifo:in_ready -> sw_reset_s_agent:rf_source_ready
wire sw_reset_s_agent_rsp_fifo_out_endofpacket; // sw_reset_s_agent_rsp_fifo:out_endofpacket -> sw_reset_s_agent:rf_sink_endofpacket
wire sw_reset_s_agent_rsp_fifo_out_valid; // sw_reset_s_agent_rsp_fifo:out_valid -> sw_reset_s_agent:rf_sink_valid
wire sw_reset_s_agent_rsp_fifo_out_startofpacket; // sw_reset_s_agent_rsp_fifo:out_startofpacket -> sw_reset_s_agent:rf_sink_startofpacket
wire [125:0] sw_reset_s_agent_rsp_fifo_out_data; // sw_reset_s_agent_rsp_fifo:out_data -> sw_reset_s_agent:rf_sink_data
wire sw_reset_s_agent_rsp_fifo_out_ready; // sw_reset_s_agent:rf_sink_ready -> sw_reset_s_agent_rsp_fifo:out_ready
wire sw_reset_s_agent_rdata_fifo_src_valid; // sw_reset_s_agent:rdata_fifo_src_valid -> sw_reset_s_agent:rdata_fifo_sink_valid
wire [65:0] sw_reset_s_agent_rdata_fifo_src_data; // sw_reset_s_agent:rdata_fifo_src_data -> sw_reset_s_agent:rdata_fifo_sink_data
wire sw_reset_s_agent_rdata_fifo_src_ready; // sw_reset_s_agent:rdata_fifo_sink_ready -> sw_reset_s_agent:rdata_fifo_src_ready
wire mem_org_mode_s_agent_m0_waitrequest; // mem_org_mode_s_translator:uav_waitrequest -> mem_org_mode_s_agent:m0_waitrequest
wire [2:0] mem_org_mode_s_agent_m0_burstcount; // mem_org_mode_s_agent:m0_burstcount -> mem_org_mode_s_translator:uav_burstcount
wire [31:0] mem_org_mode_s_agent_m0_writedata; // mem_org_mode_s_agent:m0_writedata -> mem_org_mode_s_translator:uav_writedata
wire [13:0] mem_org_mode_s_agent_m0_address; // mem_org_mode_s_agent:m0_address -> mem_org_mode_s_translator:uav_address
wire mem_org_mode_s_agent_m0_write; // mem_org_mode_s_agent:m0_write -> mem_org_mode_s_translator:uav_write
wire mem_org_mode_s_agent_m0_lock; // mem_org_mode_s_agent:m0_lock -> mem_org_mode_s_translator:uav_lock
wire mem_org_mode_s_agent_m0_read; // mem_org_mode_s_agent:m0_read -> mem_org_mode_s_translator:uav_read
wire [31:0] mem_org_mode_s_agent_m0_readdata; // mem_org_mode_s_translator:uav_readdata -> mem_org_mode_s_agent:m0_readdata
wire mem_org_mode_s_agent_m0_readdatavalid; // mem_org_mode_s_translator:uav_readdatavalid -> mem_org_mode_s_agent:m0_readdatavalid
wire mem_org_mode_s_agent_m0_debugaccess; // mem_org_mode_s_agent:m0_debugaccess -> mem_org_mode_s_translator:uav_debugaccess
wire [3:0] mem_org_mode_s_agent_m0_byteenable; // mem_org_mode_s_agent:m0_byteenable -> mem_org_mode_s_translator:uav_byteenable
wire mem_org_mode_s_agent_rf_source_endofpacket; // mem_org_mode_s_agent:rf_source_endofpacket -> mem_org_mode_s_agent_rsp_fifo:in_endofpacket
wire mem_org_mode_s_agent_rf_source_valid; // mem_org_mode_s_agent:rf_source_valid -> mem_org_mode_s_agent_rsp_fifo:in_valid
wire mem_org_mode_s_agent_rf_source_startofpacket; // mem_org_mode_s_agent:rf_source_startofpacket -> mem_org_mode_s_agent_rsp_fifo:in_startofpacket
wire [89:0] mem_org_mode_s_agent_rf_source_data; // mem_org_mode_s_agent:rf_source_data -> mem_org_mode_s_agent_rsp_fifo:in_data
wire mem_org_mode_s_agent_rf_source_ready; // mem_org_mode_s_agent_rsp_fifo:in_ready -> mem_org_mode_s_agent:rf_source_ready
wire mem_org_mode_s_agent_rsp_fifo_out_endofpacket; // mem_org_mode_s_agent_rsp_fifo:out_endofpacket -> mem_org_mode_s_agent:rf_sink_endofpacket
wire mem_org_mode_s_agent_rsp_fifo_out_valid; // mem_org_mode_s_agent_rsp_fifo:out_valid -> mem_org_mode_s_agent:rf_sink_valid
wire mem_org_mode_s_agent_rsp_fifo_out_startofpacket; // mem_org_mode_s_agent_rsp_fifo:out_startofpacket -> mem_org_mode_s_agent:rf_sink_startofpacket
wire [89:0] mem_org_mode_s_agent_rsp_fifo_out_data; // mem_org_mode_s_agent_rsp_fifo:out_data -> mem_org_mode_s_agent:rf_sink_data
wire mem_org_mode_s_agent_rsp_fifo_out_ready; // mem_org_mode_s_agent:rf_sink_ready -> mem_org_mode_s_agent_rsp_fifo:out_ready
wire mem_org_mode_s_agent_rdata_fifo_src_valid; // mem_org_mode_s_agent:rdata_fifo_src_valid -> mem_org_mode_s_agent:rdata_fifo_sink_valid
wire [33:0] mem_org_mode_s_agent_rdata_fifo_src_data; // mem_org_mode_s_agent:rdata_fifo_src_data -> mem_org_mode_s_agent:rdata_fifo_sink_data
wire mem_org_mode_s_agent_rdata_fifo_src_ready; // mem_org_mode_s_agent:rdata_fifo_sink_ready -> mem_org_mode_s_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> mem_org_mode_s_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> mem_org_mode_s_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> mem_org_mode_s_agent:cp_startofpacket
wire [88:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> mem_org_mode_s_agent:cp_data
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> mem_org_mode_s_agent:cp_channel
wire cmd_mux_004_src_ready; // mem_org_mode_s_agent:cp_ready -> cmd_mux_004:src_ready
wire version_id_0_s_agent_m0_waitrequest; // version_id_0_s_translator:uav_waitrequest -> version_id_0_s_agent:m0_waitrequest
wire [2:0] version_id_0_s_agent_m0_burstcount; // version_id_0_s_agent:m0_burstcount -> version_id_0_s_translator:uav_burstcount
wire [31:0] version_id_0_s_agent_m0_writedata; // version_id_0_s_agent:m0_writedata -> version_id_0_s_translator:uav_writedata
wire [13:0] version_id_0_s_agent_m0_address; // version_id_0_s_agent:m0_address -> version_id_0_s_translator:uav_address
wire version_id_0_s_agent_m0_write; // version_id_0_s_agent:m0_write -> version_id_0_s_translator:uav_write
wire version_id_0_s_agent_m0_lock; // version_id_0_s_agent:m0_lock -> version_id_0_s_translator:uav_lock
wire version_id_0_s_agent_m0_read; // version_id_0_s_agent:m0_read -> version_id_0_s_translator:uav_read
wire [31:0] version_id_0_s_agent_m0_readdata; // version_id_0_s_translator:uav_readdata -> version_id_0_s_agent:m0_readdata
wire version_id_0_s_agent_m0_readdatavalid; // version_id_0_s_translator:uav_readdatavalid -> version_id_0_s_agent:m0_readdatavalid
wire version_id_0_s_agent_m0_debugaccess; // version_id_0_s_agent:m0_debugaccess -> version_id_0_s_translator:uav_debugaccess
wire [3:0] version_id_0_s_agent_m0_byteenable; // version_id_0_s_agent:m0_byteenable -> version_id_0_s_translator:uav_byteenable
wire version_id_0_s_agent_rf_source_endofpacket; // version_id_0_s_agent:rf_source_endofpacket -> version_id_0_s_agent_rsp_fifo:in_endofpacket
wire version_id_0_s_agent_rf_source_valid; // version_id_0_s_agent:rf_source_valid -> version_id_0_s_agent_rsp_fifo:in_valid
wire version_id_0_s_agent_rf_source_startofpacket; // version_id_0_s_agent:rf_source_startofpacket -> version_id_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] version_id_0_s_agent_rf_source_data; // version_id_0_s_agent:rf_source_data -> version_id_0_s_agent_rsp_fifo:in_data
wire version_id_0_s_agent_rf_source_ready; // version_id_0_s_agent_rsp_fifo:in_ready -> version_id_0_s_agent:rf_source_ready
wire version_id_0_s_agent_rsp_fifo_out_endofpacket; // version_id_0_s_agent_rsp_fifo:out_endofpacket -> version_id_0_s_agent:rf_sink_endofpacket
wire version_id_0_s_agent_rsp_fifo_out_valid; // version_id_0_s_agent_rsp_fifo:out_valid -> version_id_0_s_agent:rf_sink_valid
wire version_id_0_s_agent_rsp_fifo_out_startofpacket; // version_id_0_s_agent_rsp_fifo:out_startofpacket -> version_id_0_s_agent:rf_sink_startofpacket
wire [89:0] version_id_0_s_agent_rsp_fifo_out_data; // version_id_0_s_agent_rsp_fifo:out_data -> version_id_0_s_agent:rf_sink_data
wire version_id_0_s_agent_rsp_fifo_out_ready; // version_id_0_s_agent:rf_sink_ready -> version_id_0_s_agent_rsp_fifo:out_ready
wire version_id_0_s_agent_rdata_fifo_src_valid; // version_id_0_s_agent:rdata_fifo_src_valid -> version_id_0_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_0_s_agent_rdata_fifo_src_data; // version_id_0_s_agent:rdata_fifo_src_data -> version_id_0_s_agent:rdata_fifo_sink_data
wire version_id_0_s_agent_rdata_fifo_src_ready; // version_id_0_s_agent:rdata_fifo_sink_ready -> version_id_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> version_id_0_s_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> version_id_0_s_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> version_id_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> version_id_0_s_agent:cp_data
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> version_id_0_s_agent:cp_channel
wire cmd_mux_005_src_ready; // version_id_0_s_agent:cp_ready -> cmd_mux_005:src_ready
wire irq_ena_0_s_agent_m0_waitrequest; // irq_ena_0_s_translator:uav_waitrequest -> irq_ena_0_s_agent:m0_waitrequest
wire [2:0] irq_ena_0_s_agent_m0_burstcount; // irq_ena_0_s_agent:m0_burstcount -> irq_ena_0_s_translator:uav_burstcount
wire [31:0] irq_ena_0_s_agent_m0_writedata; // irq_ena_0_s_agent:m0_writedata -> irq_ena_0_s_translator:uav_writedata
wire [13:0] irq_ena_0_s_agent_m0_address; // irq_ena_0_s_agent:m0_address -> irq_ena_0_s_translator:uav_address
wire irq_ena_0_s_agent_m0_write; // irq_ena_0_s_agent:m0_write -> irq_ena_0_s_translator:uav_write
wire irq_ena_0_s_agent_m0_lock; // irq_ena_0_s_agent:m0_lock -> irq_ena_0_s_translator:uav_lock
wire irq_ena_0_s_agent_m0_read; // irq_ena_0_s_agent:m0_read -> irq_ena_0_s_translator:uav_read
wire [31:0] irq_ena_0_s_agent_m0_readdata; // irq_ena_0_s_translator:uav_readdata -> irq_ena_0_s_agent:m0_readdata
wire irq_ena_0_s_agent_m0_readdatavalid; // irq_ena_0_s_translator:uav_readdatavalid -> irq_ena_0_s_agent:m0_readdatavalid
wire irq_ena_0_s_agent_m0_debugaccess; // irq_ena_0_s_agent:m0_debugaccess -> irq_ena_0_s_translator:uav_debugaccess
wire [3:0] irq_ena_0_s_agent_m0_byteenable; // irq_ena_0_s_agent:m0_byteenable -> irq_ena_0_s_translator:uav_byteenable
wire irq_ena_0_s_agent_rf_source_endofpacket; // irq_ena_0_s_agent:rf_source_endofpacket -> irq_ena_0_s_agent_rsp_fifo:in_endofpacket
wire irq_ena_0_s_agent_rf_source_valid; // irq_ena_0_s_agent:rf_source_valid -> irq_ena_0_s_agent_rsp_fifo:in_valid
wire irq_ena_0_s_agent_rf_source_startofpacket; // irq_ena_0_s_agent:rf_source_startofpacket -> irq_ena_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] irq_ena_0_s_agent_rf_source_data; // irq_ena_0_s_agent:rf_source_data -> irq_ena_0_s_agent_rsp_fifo:in_data
wire irq_ena_0_s_agent_rf_source_ready; // irq_ena_0_s_agent_rsp_fifo:in_ready -> irq_ena_0_s_agent:rf_source_ready
wire irq_ena_0_s_agent_rsp_fifo_out_endofpacket; // irq_ena_0_s_agent_rsp_fifo:out_endofpacket -> irq_ena_0_s_agent:rf_sink_endofpacket
wire irq_ena_0_s_agent_rsp_fifo_out_valid; // irq_ena_0_s_agent_rsp_fifo:out_valid -> irq_ena_0_s_agent:rf_sink_valid
wire irq_ena_0_s_agent_rsp_fifo_out_startofpacket; // irq_ena_0_s_agent_rsp_fifo:out_startofpacket -> irq_ena_0_s_agent:rf_sink_startofpacket
wire [89:0] irq_ena_0_s_agent_rsp_fifo_out_data; // irq_ena_0_s_agent_rsp_fifo:out_data -> irq_ena_0_s_agent:rf_sink_data
wire irq_ena_0_s_agent_rsp_fifo_out_ready; // irq_ena_0_s_agent:rf_sink_ready -> irq_ena_0_s_agent_rsp_fifo:out_ready
wire irq_ena_0_s_agent_rdata_fifo_src_valid; // irq_ena_0_s_agent:rdata_fifo_src_valid -> irq_ena_0_s_agent:rdata_fifo_sink_valid
wire [33:0] irq_ena_0_s_agent_rdata_fifo_src_data; // irq_ena_0_s_agent:rdata_fifo_src_data -> irq_ena_0_s_agent:rdata_fifo_sink_data
wire irq_ena_0_s_agent_rdata_fifo_src_ready; // irq_ena_0_s_agent:rdata_fifo_sink_ready -> irq_ena_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> irq_ena_0_s_agent:cp_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> irq_ena_0_s_agent:cp_valid
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> irq_ena_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> irq_ena_0_s_agent:cp_data
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> irq_ena_0_s_agent:cp_channel
wire cmd_mux_006_src_ready; // irq_ena_0_s_agent:cp_ready -> cmd_mux_006:src_ready
wire kernel_cntrl_m0_agent_cp_endofpacket; // kernel_cntrl_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire kernel_cntrl_m0_agent_cp_valid; // kernel_cntrl_m0_agent:cp_valid -> router:sink_valid
wire kernel_cntrl_m0_agent_cp_startofpacket; // kernel_cntrl_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire [88:0] kernel_cntrl_m0_agent_cp_data; // kernel_cntrl_m0_agent:cp_data -> router:sink_data
wire kernel_cntrl_m0_agent_cp_ready; // router:sink_ready -> kernel_cntrl_m0_agent:cp_ready
wire address_span_extender_0_windowed_slave_agent_rp_endofpacket; // address_span_extender_0_windowed_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rp_valid; // address_span_extender_0_windowed_slave_agent:rp_valid -> router_001:sink_valid
wire address_span_extender_0_windowed_slave_agent_rp_startofpacket; // address_span_extender_0_windowed_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [88:0] address_span_extender_0_windowed_slave_agent_rp_data; // address_span_extender_0_windowed_slave_agent:rp_data -> router_001:sink_data
wire address_span_extender_0_windowed_slave_agent_rp_ready; // router_001:sink_ready -> address_span_extender_0_windowed_slave_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [88:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [6:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire address_span_extender_0_cntl_agent_rp_endofpacket; // address_span_extender_0_cntl_agent:rp_endofpacket -> router_002:sink_endofpacket
wire address_span_extender_0_cntl_agent_rp_valid; // address_span_extender_0_cntl_agent:rp_valid -> router_002:sink_valid
wire address_span_extender_0_cntl_agent_rp_startofpacket; // address_span_extender_0_cntl_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [124:0] address_span_extender_0_cntl_agent_rp_data; // address_span_extender_0_cntl_agent:rp_data -> router_002:sink_data
wire address_span_extender_0_cntl_agent_rp_ready; // router_002:sink_ready -> address_span_extender_0_cntl_agent:rp_ready
wire sys_description_rom_s1_agent_rp_endofpacket; // sys_description_rom_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire sys_description_rom_s1_agent_rp_valid; // sys_description_rom_s1_agent:rp_valid -> router_003:sink_valid
wire sys_description_rom_s1_agent_rp_startofpacket; // sys_description_rom_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [124:0] sys_description_rom_s1_agent_rp_data; // sys_description_rom_s1_agent:rp_data -> router_003:sink_data
wire sys_description_rom_s1_agent_rp_ready; // router_003:sink_ready -> sys_description_rom_s1_agent:rp_ready
wire sw_reset_s_agent_rp_endofpacket; // sw_reset_s_agent:rp_endofpacket -> router_004:sink_endofpacket
wire sw_reset_s_agent_rp_valid; // sw_reset_s_agent:rp_valid -> router_004:sink_valid
wire sw_reset_s_agent_rp_startofpacket; // sw_reset_s_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [124:0] sw_reset_s_agent_rp_data; // sw_reset_s_agent:rp_data -> router_004:sink_data
wire sw_reset_s_agent_rp_ready; // router_004:sink_ready -> sw_reset_s_agent:rp_ready
wire mem_org_mode_s_agent_rp_endofpacket; // mem_org_mode_s_agent:rp_endofpacket -> router_005:sink_endofpacket
wire mem_org_mode_s_agent_rp_valid; // mem_org_mode_s_agent:rp_valid -> router_005:sink_valid
wire mem_org_mode_s_agent_rp_startofpacket; // mem_org_mode_s_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [88:0] mem_org_mode_s_agent_rp_data; // mem_org_mode_s_agent:rp_data -> router_005:sink_data
wire mem_org_mode_s_agent_rp_ready; // router_005:sink_ready -> mem_org_mode_s_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_004:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [88:0] router_005_src_data; // router_005:src_data -> rsp_demux_004:sink_data
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_004:sink_channel
wire router_005_src_ready; // rsp_demux_004:sink_ready -> router_005:src_ready
wire version_id_0_s_agent_rp_endofpacket; // version_id_0_s_agent:rp_endofpacket -> router_006:sink_endofpacket
wire version_id_0_s_agent_rp_valid; // version_id_0_s_agent:rp_valid -> router_006:sink_valid
wire version_id_0_s_agent_rp_startofpacket; // version_id_0_s_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [88:0] version_id_0_s_agent_rp_data; // version_id_0_s_agent:rp_data -> router_006:sink_data
wire version_id_0_s_agent_rp_ready; // router_006:sink_ready -> version_id_0_s_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_005:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [88:0] router_006_src_data; // router_006:src_data -> rsp_demux_005:sink_data
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_005:sink_channel
wire router_006_src_ready; // rsp_demux_005:sink_ready -> router_006:src_ready
wire irq_ena_0_s_agent_rp_endofpacket; // irq_ena_0_s_agent:rp_endofpacket -> router_007:sink_endofpacket
wire irq_ena_0_s_agent_rp_valid; // irq_ena_0_s_agent:rp_valid -> router_007:sink_valid
wire irq_ena_0_s_agent_rp_startofpacket; // irq_ena_0_s_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [88:0] irq_ena_0_s_agent_rp_data; // irq_ena_0_s_agent:rp_data -> router_007:sink_data
wire irq_ena_0_s_agent_rp_ready; // router_007:sink_ready -> irq_ena_0_s_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_006:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire [88:0] router_007_src_data; // router_007:src_data -> rsp_demux_006:sink_data
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_006:sink_channel
wire router_007_src_ready; // rsp_demux_006:sink_ready -> router_007:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> kernel_cntrl_m0_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> kernel_cntrl_m0_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> kernel_cntrl_m0_limiter:cmd_sink_startofpacket
wire [88:0] router_src_data; // router:src_data -> kernel_cntrl_m0_limiter:cmd_sink_data
wire [6:0] router_src_channel; // router:src_channel -> kernel_cntrl_m0_limiter:cmd_sink_channel
wire router_src_ready; // kernel_cntrl_m0_limiter:cmd_sink_ready -> router:src_ready
wire kernel_cntrl_m0_limiter_cmd_src_endofpacket; // kernel_cntrl_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire kernel_cntrl_m0_limiter_cmd_src_startofpacket; // kernel_cntrl_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_cmd_src_data; // kernel_cntrl_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire [6:0] kernel_cntrl_m0_limiter_cmd_src_channel; // kernel_cntrl_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire kernel_cntrl_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> kernel_cntrl_m0_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> kernel_cntrl_m0_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> kernel_cntrl_m0_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> kernel_cntrl_m0_limiter:rsp_sink_startofpacket
wire [88:0] rsp_mux_src_data; // rsp_mux:src_data -> kernel_cntrl_m0_limiter:rsp_sink_data
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> kernel_cntrl_m0_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // kernel_cntrl_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire kernel_cntrl_m0_limiter_rsp_src_endofpacket; // kernel_cntrl_m0_limiter:rsp_src_endofpacket -> kernel_cntrl_m0_agent:rp_endofpacket
wire kernel_cntrl_m0_limiter_rsp_src_valid; // kernel_cntrl_m0_limiter:rsp_src_valid -> kernel_cntrl_m0_agent:rp_valid
wire kernel_cntrl_m0_limiter_rsp_src_startofpacket; // kernel_cntrl_m0_limiter:rsp_src_startofpacket -> kernel_cntrl_m0_agent:rp_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_rsp_src_data; // kernel_cntrl_m0_limiter:rsp_src_data -> kernel_cntrl_m0_agent:rp_data
wire [6:0] kernel_cntrl_m0_limiter_rsp_src_channel; // kernel_cntrl_m0_limiter:rsp_src_channel -> kernel_cntrl_m0_agent:rp_channel
wire kernel_cntrl_m0_limiter_rsp_src_ready; // kernel_cntrl_m0_agent:rp_ready -> kernel_cntrl_m0_limiter:rsp_src_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [88:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [88:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [88:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [88:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire [88:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire [6:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [88:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [88:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [88:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire [88:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire [88:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> address_span_extender_0_cntl_cmd_width_adapter:in_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> address_span_extender_0_cntl_cmd_width_adapter:in_data
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> address_span_extender_0_cntl_cmd_width_adapter:in_channel
wire cmd_mux_001_src_ready; // address_span_extender_0_cntl_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_endofpacket -> address_span_extender_0_cntl_agent:cp_endofpacket
wire address_span_extender_0_cntl_cmd_width_adapter_src_valid; // address_span_extender_0_cntl_cmd_width_adapter:out_valid -> address_span_extender_0_cntl_agent:cp_valid
wire address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_startofpacket -> address_span_extender_0_cntl_agent:cp_startofpacket
wire [124:0] address_span_extender_0_cntl_cmd_width_adapter_src_data; // address_span_extender_0_cntl_cmd_width_adapter:out_data -> address_span_extender_0_cntl_agent:cp_data
wire address_span_extender_0_cntl_cmd_width_adapter_src_ready; // address_span_extender_0_cntl_agent:cp_ready -> address_span_extender_0_cntl_cmd_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_cmd_width_adapter_src_channel; // address_span_extender_0_cntl_cmd_width_adapter:out_channel -> address_span_extender_0_cntl_agent:cp_channel
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sys_description_rom_s1_cmd_width_adapter:in_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sys_description_rom_s1_cmd_width_adapter:in_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sys_description_rom_s1_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sys_description_rom_s1_cmd_width_adapter:in_data
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sys_description_rom_s1_cmd_width_adapter:in_channel
wire cmd_mux_002_src_ready; // sys_description_rom_s1_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire sys_description_rom_s1_cmd_width_adapter_src_endofpacket; // sys_description_rom_s1_cmd_width_adapter:out_endofpacket -> sys_description_rom_s1_agent:cp_endofpacket
wire sys_description_rom_s1_cmd_width_adapter_src_valid; // sys_description_rom_s1_cmd_width_adapter:out_valid -> sys_description_rom_s1_agent:cp_valid
wire sys_description_rom_s1_cmd_width_adapter_src_startofpacket; // sys_description_rom_s1_cmd_width_adapter:out_startofpacket -> sys_description_rom_s1_agent:cp_startofpacket
wire [124:0] sys_description_rom_s1_cmd_width_adapter_src_data; // sys_description_rom_s1_cmd_width_adapter:out_data -> sys_description_rom_s1_agent:cp_data
wire sys_description_rom_s1_cmd_width_adapter_src_ready; // sys_description_rom_s1_agent:cp_ready -> sys_description_rom_s1_cmd_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_cmd_width_adapter_src_channel; // sys_description_rom_s1_cmd_width_adapter:out_channel -> sys_description_rom_s1_agent:cp_channel
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sw_reset_s_cmd_width_adapter:in_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sw_reset_s_cmd_width_adapter:in_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sw_reset_s_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sw_reset_s_cmd_width_adapter:in_data
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sw_reset_s_cmd_width_adapter:in_channel
wire cmd_mux_003_src_ready; // sw_reset_s_cmd_width_adapter:in_ready -> cmd_mux_003:src_ready
wire sw_reset_s_cmd_width_adapter_src_endofpacket; // sw_reset_s_cmd_width_adapter:out_endofpacket -> sw_reset_s_agent:cp_endofpacket
wire sw_reset_s_cmd_width_adapter_src_valid; // sw_reset_s_cmd_width_adapter:out_valid -> sw_reset_s_agent:cp_valid
wire sw_reset_s_cmd_width_adapter_src_startofpacket; // sw_reset_s_cmd_width_adapter:out_startofpacket -> sw_reset_s_agent:cp_startofpacket
wire [124:0] sw_reset_s_cmd_width_adapter_src_data; // sw_reset_s_cmd_width_adapter:out_data -> sw_reset_s_agent:cp_data
wire sw_reset_s_cmd_width_adapter_src_ready; // sw_reset_s_agent:cp_ready -> sw_reset_s_cmd_width_adapter:out_ready
wire [6:0] sw_reset_s_cmd_width_adapter_src_channel; // sw_reset_s_cmd_width_adapter:out_channel -> sw_reset_s_agent:cp_channel
wire router_002_src_endofpacket; // router_002:src_endofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_endofpacket
wire router_002_src_valid; // router_002:src_valid -> address_span_extender_0_cntl_rsp_width_adapter:in_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_startofpacket
wire [124:0] router_002_src_data; // router_002:src_data -> address_span_extender_0_cntl_rsp_width_adapter:in_data
wire [6:0] router_002_src_channel; // router_002:src_channel -> address_span_extender_0_cntl_rsp_width_adapter:in_channel
wire router_002_src_ready; // address_span_extender_0_cntl_rsp_width_adapter:in_ready -> router_002:src_ready
wire address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire address_span_extender_0_cntl_rsp_width_adapter_src_valid; // address_span_extender_0_cntl_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire [88:0] address_span_extender_0_cntl_rsp_width_adapter_src_data; // address_span_extender_0_cntl_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire address_span_extender_0_cntl_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> address_span_extender_0_cntl_rsp_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_rsp_width_adapter_src_channel; // address_span_extender_0_cntl_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire router_003_src_endofpacket; // router_003:src_endofpacket -> sys_description_rom_s1_rsp_width_adapter:in_endofpacket
wire router_003_src_valid; // router_003:src_valid -> sys_description_rom_s1_rsp_width_adapter:in_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> sys_description_rom_s1_rsp_width_adapter:in_startofpacket
wire [124:0] router_003_src_data; // router_003:src_data -> sys_description_rom_s1_rsp_width_adapter:in_data
wire [6:0] router_003_src_channel; // router_003:src_channel -> sys_description_rom_s1_rsp_width_adapter:in_channel
wire router_003_src_ready; // sys_description_rom_s1_rsp_width_adapter:in_ready -> router_003:src_ready
wire sys_description_rom_s1_rsp_width_adapter_src_endofpacket; // sys_description_rom_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire sys_description_rom_s1_rsp_width_adapter_src_valid; // sys_description_rom_s1_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire sys_description_rom_s1_rsp_width_adapter_src_startofpacket; // sys_description_rom_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire [88:0] sys_description_rom_s1_rsp_width_adapter_src_data; // sys_description_rom_s1_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire sys_description_rom_s1_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> sys_description_rom_s1_rsp_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_rsp_width_adapter_src_channel; // sys_description_rom_s1_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire router_004_src_endofpacket; // router_004:src_endofpacket -> sw_reset_s_rsp_width_adapter:in_endofpacket
wire router_004_src_valid; // router_004:src_valid -> sw_reset_s_rsp_width_adapter:in_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> sw_reset_s_rsp_width_adapter:in_startofpacket
wire [124:0] router_004_src_data; // router_004:src_data -> sw_reset_s_rsp_width_adapter:in_data
wire [6:0] router_004_src_channel; // router_004:src_channel -> sw_reset_s_rsp_width_adapter:in_channel
wire router_004_src_ready; // sw_reset_s_rsp_width_adapter:in_ready -> router_004:src_ready
wire sw_reset_s_rsp_width_adapter_src_endofpacket; // sw_reset_s_rsp_width_adapter:out_endofpacket -> rsp_demux_003:sink_endofpacket
wire sw_reset_s_rsp_width_adapter_src_valid; // sw_reset_s_rsp_width_adapter:out_valid -> rsp_demux_003:sink_valid
wire sw_reset_s_rsp_width_adapter_src_startofpacket; // sw_reset_s_rsp_width_adapter:out_startofpacket -> rsp_demux_003:sink_startofpacket
wire [88:0] sw_reset_s_rsp_width_adapter_src_data; // sw_reset_s_rsp_width_adapter:out_data -> rsp_demux_003:sink_data
wire sw_reset_s_rsp_width_adapter_src_ready; // rsp_demux_003:sink_ready -> sw_reset_s_rsp_width_adapter:out_ready
wire [6:0] sw_reset_s_rsp_width_adapter_src_channel; // sw_reset_s_rsp_width_adapter:out_channel -> rsp_demux_003:sink_channel
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire [88:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire [88:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire [6:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> crosser_001:in_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> crosser_001:in_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> crosser_001:in_startofpacket
wire [88:0] cmd_demux_src1_data; // cmd_demux:src1_data -> crosser_001:in_data
wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> crosser_001:in_channel
wire cmd_demux_src1_ready; // crosser_001:in_ready -> cmd_demux:src1_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_001:sink0_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [88:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_001:sink0_data
wire [6:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_001:sink0_channel
wire crosser_001_out_ready; // cmd_mux_001:sink0_ready -> crosser_001:out_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_002:in_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_002:in_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_002:in_startofpacket
wire [88:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_002:in_data
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_002:in_channel
wire rsp_demux_src0_ready; // crosser_002:in_ready -> rsp_demux:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink0_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink0_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink0_startofpacket
wire [88:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink0_data
wire [6:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink0_channel
wire crosser_002_out_ready; // rsp_mux:sink0_ready -> crosser_002:out_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> crosser_003:in_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
wire [88:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> crosser_003:in_data
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> crosser_003:in_channel
wire rsp_demux_001_src0_ready; // crosser_003:in_ready -> rsp_demux_001:src0_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux:sink1_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux:sink1_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux:sink1_startofpacket
wire [88:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux:sink1_data
wire [6:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux:sink1_channel
wire crosser_003_out_ready; // rsp_mux:sink1_ready -> crosser_003:out_ready
wire [6:0] kernel_cntrl_m0_limiter_cmd_valid_data; // kernel_cntrl_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) kernel_cntrl_m0_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (kernel_cntrl_m0_address), // avalon_anti_master_0.address
.av_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.av_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.av_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.av_read (kernel_cntrl_m0_read), // .read
.av_readdata (kernel_cntrl_m0_readdata), // .readdata
.av_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.av_write (kernel_cntrl_m0_write), // .write
.av_writedata (kernel_cntrl_m0_writedata), // .writedata
.av_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_windowed_slave_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_windowed_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.uav_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_0_windowed_slave_write), // .write
.av_read (address_span_extender_0_windowed_slave_read), // .read
.av_readdata (address_span_extender_0_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_0_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_0_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_cntl_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_cntl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_cntl_agent_m0_read), // .read
.uav_write (address_span_extender_0_cntl_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.av_write (address_span_extender_0_cntl_write), // avalon_anti_slave_0.write
.av_read (address_span_extender_0_cntl_read), // .read
.av_readdata (address_span_extender_0_cntl_readdata), // .readdata
.av_writedata (address_span_extender_0_cntl_writedata), // .writedata
.av_byteenable (address_span_extender_0_cntl_byteenable), // .byteenable
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sys_description_rom_s1_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sys_description_rom_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.uav_read (sys_description_rom_s1_agent_m0_read), // .read
.uav_write (sys_description_rom_s1_agent_m0_write), // .write
.uav_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.uav_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.uav_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.uav_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sys_description_rom_s1_address), // avalon_anti_slave_0.address
.av_write (sys_description_rom_s1_write), // .write
.av_readdata (sys_description_rom_s1_readdata), // .readdata
.av_writedata (sys_description_rom_s1_writedata), // .writedata
.av_byteenable (sys_description_rom_s1_byteenable), // .byteenable
.av_chipselect (sys_description_rom_s1_chipselect), // .chipselect
.av_clken (sys_description_rom_s1_clken), // .clken
.av_debugaccess (sys_description_rom_s1_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_reset_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_reset_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.uav_read (sw_reset_s_agent_m0_read), // .read
.uav_write (sw_reset_s_agent_m0_write), // .write
.uav_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.uav_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.uav_lock (sw_reset_s_agent_m0_lock), // .lock
.uav_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.av_write (sw_reset_s_write), // avalon_anti_slave_0.write
.av_read (sw_reset_s_read), // .read
.av_readdata (sw_reset_s_readdata), // .readdata
.av_writedata (sw_reset_s_writedata), // .writedata
.av_byteenable (sw_reset_s_byteenable), // .byteenable
.av_waitrequest (sw_reset_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mem_org_mode_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem_org_mode_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.uav_read (mem_org_mode_s_agent_m0_read), // .read
.uav_write (mem_org_mode_s_agent_m0_write), // .write
.uav_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.uav_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.uav_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.uav_lock (mem_org_mode_s_agent_m0_lock), // .lock
.uav_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.av_write (mem_org_mode_s_write), // avalon_anti_slave_0.write
.av_read (mem_org_mode_s_read), // .read
.av_readdata (mem_org_mode_s_readdata), // .readdata
.av_writedata (mem_org_mode_s_writedata), // .writedata
.av_waitrequest (mem_org_mode_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_0_s_agent_m0_read), // .read
.uav_write (version_id_0_s_agent_m0_write), // .write
.uav_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_0_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_0_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) irq_ena_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (irq_ena_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.uav_read (irq_ena_0_s_agent_m0_read), // .read
.uav_write (irq_ena_0_s_agent_m0_write), // .write
.uav_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.uav_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.uav_lock (irq_ena_0_s_agent_m0_lock), // .lock
.uav_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.av_write (irq_ena_0_s_write), // avalon_anti_slave_0.write
.av_read (irq_ena_0_s_read), // .read
.av_readdata (irq_ena_0_s_readdata), // .readdata
.av_writedata (irq_ena_0_s_writedata), // .writedata
.av_byteenable (irq_ena_0_s_byteenable), // .byteenable
.av_waitrequest (irq_ena_0_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BEGIN_BURST (68),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_THREAD_ID_H (76),
.PKT_THREAD_ID_L (76),
.PKT_CACHE_H (83),
.PKT_CACHE_L (80),
.PKT_DATA_SIDEBAND_H (67),
.PKT_DATA_SIDEBAND_L (67),
.PKT_QOS_H (69),
.PKT_QOS_L (69),
.PKT_ADDR_SIDEBAND_H (66),
.PKT_ADDR_SIDEBAND_L (66),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cntrl_m0_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.av_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (kernel_cntrl_m0_agent_cp_valid), // cp.valid
.cp_data (kernel_cntrl_m0_agent_cp_data), // .data
.cp_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (kernel_cntrl_m0_agent_cp_ready), // .ready
.rp_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rp_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_windowed_slave_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_windowed_slave_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_cntl_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_cntl_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_cntl_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_cntl_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_cntl_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_cntl_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.cp_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.cp_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.cp_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_cntl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_cntl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sys_description_rom_s1_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sys_description_rom_s1_agent_m0_address), // m0.address
.m0_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.m0_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sys_description_rom_s1_agent_m0_read), // .read
.m0_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.m0_write (sys_description_rom_s1_agent_m0_write), // .write
.rp_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sys_description_rom_s1_agent_rp_ready), // .ready
.rp_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.rp_data (sys_description_rom_s1_agent_rp_data), // .data
.rp_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.cp_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sys_description_rom_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sys_description_rom_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sys_description_rom_s1_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sys_description_rom_s1_agent_rf_source_data), // in.data
.in_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.in_ready (sys_description_rom_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_reset_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_reset_s_agent_m0_address), // m0.address
.m0_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_reset_s_agent_m0_lock), // .lock
.m0_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_reset_s_agent_m0_read), // .read
.m0_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.m0_write (sw_reset_s_agent_m0_write), // .write
.rp_endofpacket (sw_reset_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_reset_s_agent_rp_ready), // .ready
.rp_valid (sw_reset_s_agent_rp_valid), // .valid
.rp_data (sw_reset_s_agent_rp_data), // .data
.rp_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (sw_reset_s_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.cp_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sw_reset_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_reset_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_reset_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_reset_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_reset_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_reset_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_reset_s_agent_rf_source_data), // in.data
.in_valid (sw_reset_s_agent_rf_source_valid), // .valid
.in_ready (sw_reset_s_agent_rf_source_ready), // .ready
.in_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_reset_s_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_reset_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mem_org_mode_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (mem_org_mode_s_agent_m0_address), // m0.address
.m0_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (mem_org_mode_s_agent_m0_lock), // .lock
.m0_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mem_org_mode_s_agent_m0_read), // .read
.m0_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.m0_write (mem_org_mode_s_agent_m0_write), // .write
.rp_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mem_org_mode_s_agent_rp_ready), // .ready
.rp_valid (mem_org_mode_s_agent_rp_valid), // .valid
.rp_data (mem_org_mode_s_agent_rp_data), // .data
.rp_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mem_org_mode_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mem_org_mode_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mem_org_mode_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mem_org_mode_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (mem_org_mode_s_agent_rf_source_data), // in.data
.in_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.in_ready (mem_org_mode_s_agent_rf_source_ready), // .ready
.in_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (mem_org_mode_s_agent_rsp_fifo_out_data), // out.data
.out_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_0_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_0_s_agent_m0_lock), // .lock
.m0_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_0_s_agent_m0_read), // .read
.m0_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.m0_write (version_id_0_s_agent_m0_write), // .write
.rp_endofpacket (version_id_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_0_s_agent_rp_ready), // .ready
.rp_valid (version_id_0_s_agent_rp_valid), // .valid
.rp_data (version_id_0_s_agent_rp_data), // .data
.rp_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (version_id_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_0_s_agent_rf_source_data), // in.data
.in_valid (version_id_0_s_agent_rf_source_valid), // .valid
.in_ready (version_id_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) irq_ena_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (irq_ena_0_s_agent_m0_address), // m0.address
.m0_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (irq_ena_0_s_agent_m0_lock), // .lock
.m0_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (irq_ena_0_s_agent_m0_read), // .read
.m0_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.m0_write (irq_ena_0_s_agent_m0_write), // .write
.rp_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (irq_ena_0_s_agent_rp_ready), // .ready
.rp_valid (irq_ena_0_s_agent_rp_valid), // .valid
.rp_data (irq_ena_0_s_agent_rp_data), // .data
.rp_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (irq_ena_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (irq_ena_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (irq_ena_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) irq_ena_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (irq_ena_0_s_agent_rf_source_data), // in.data
.in_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.in_ready (irq_ena_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (irq_ena_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router router (
.sink_ready (kernel_cntrl_m0_agent_cp_ready), // sink.ready
.sink_valid (kernel_cntrl_m0_agent_cp_valid), // .valid
.sink_data (kernel_cntrl_m0_agent_cp_data), // .data
.sink_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_001 (
.sink_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 router_002 (
.sink_ready (address_span_extender_0_cntl_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_cntl_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_003 (
.sink_ready (sys_description_rom_s1_agent_rp_ready), // sink.ready
.sink_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.sink_data (sys_description_rom_s1_agent_rp_data), // .data
.sink_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_004 (
.sink_ready (sw_reset_s_agent_rp_ready), // sink.ready
.sink_valid (sw_reset_s_agent_rp_valid), // .valid
.sink_data (sw_reset_s_agent_rp_data), // .data
.sink_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_005 (
.sink_ready (mem_org_mode_s_agent_rp_ready), // sink.ready
.sink_valid (mem_org_mode_s_agent_rp_valid), // .valid
.sink_data (mem_org_mode_s_agent_rp_data), // .data
.sink_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_006 (
.sink_ready (version_id_0_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_0_s_agent_rp_valid), // .valid
.sink_data (version_id_0_s_agent_rp_data), // .data
.sink_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_007 (
.sink_ready (irq_ena_0_s_agent_rp_ready), // sink.ready
.sink_valid (irq_ena_0_s_agent_rp_valid), // .valid
.sink_data (irq_ena_0_s_agent_rp_data), // .data
.sink_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) kernel_cntrl_m0_limiter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (kernel_cntrl_m0_limiter_cmd_valid_data) // cmd_valid.data
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.sink_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (kernel_cntrl_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.sink_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sw_reset_s_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.sink_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_003_src_valid), // sink.valid
.in_channel (cmd_mux_003_src_channel), // .channel
.in_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_003_src_ready), // .ready
.in_data (cmd_mux_003_src_data), // .data
.out_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.out_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_003_src_valid), // sink.valid
.in_channel (router_003_src_channel), // .channel
.in_startofpacket (router_003_src_startofpacket), // .startofpacket
.in_endofpacket (router_003_src_endofpacket), // .endofpacket
.in_ready (router_003_src_ready), // .ready
.in_data (router_003_src_data), // .data
.out_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_004_src_valid), // sink.valid
.in_channel (router_004_src_channel), // .channel
.in_startofpacket (router_004_src_startofpacket), // .startofpacket
.in_endofpacket (router_004_src_endofpacket), // .endofpacket
.in_ready (router_004_src_ready), // .ready
.in_data (router_004_src_data), // .data
.out_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.out_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src1_ready), // in.ready
.in_valid (cmd_demux_src1_valid), // .valid
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_src1_channel), // .channel
.in_data (cmd_demux_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src0_ready), // in.ready
.in_valid (rsp_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_data (rsp_demux_001_src0_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule |
module design_1_xbar_1 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *)
output wire [127 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *)
output wire [15 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *)
input wire [127 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_rready;
axi_crossbar_v2_1_9_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(4),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(256'H0000000043c100000000000043c0000000000000428000000000000040400000),
.C_M_AXI_ADDR_WIDTH(128'H00000010000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(128'H00000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(128'H00000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(128'H00000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(4'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(4'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(4'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(4'HF),
.m_axi_ruser(4'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module testbench;
reg clk;
reg rstn;
reg datain_ch0;
reg datain_ch1;
reg datain_ch2;
reg datain_ch3;
integer i;
wire serialout;
wire testout0;
wire testout1;
wire testout2;
wire testout3;
root test_root(
.clk(clk),
.rstn(rstn),
.datain_ch0(datain_ch0),
.datain_ch1(datain_ch1),
.datain_ch2(datain_ch2),
.datain_ch3(datain_ch3),
.serialout(serialout),
.testout0(testout0),
.testout1(testout1),
.testout2(testout2),
.testout3(testout3)
);
initial begin
$dumpvars(0, testbench);
clk = 0;
rstn = 0;
datain_ch0 = 0;
datain_ch1 = 0;
datain_ch2 = 0;
datain_ch3 = 0;
#10
rstn = 1;
#5000000
datain_ch1 = 1;
#1090
datain_ch0 = 1;
#610
datain_ch0 = 0;
#8300
datain_ch1 = 0;
//datain_ch0 = 1;
//#2
//datain_ch0 = 0;
#10000000 $finish;
end
always #5 clk = ~clk;
endmodule |
module test_uart;
// Inputs
reg [31:0] dat_i;
reg [31:0] adr_i;
reg we_i;
reg stb_i;
reg sys_clk;
reg sys_rst;
reg uart_rx;
// Outputs
wire [31:0] dat_o;
wire ack_o;
wire rx_irq;
wire tx_irq;
wire uart_tx;
// Instantiate the Unit Under Test (UUT)
uart uut (
.dat_i(dat_i),
.adr_i(adr_i),
.we_i(we_i),
.stb_i(stb_i),
.dat_o(dat_o),
.ack_o(ack_o),
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.rx_irq(rx_irq),
.tx_irq(tx_irq),
.uart_rx(uart_rx),
.uart_tx(uart_tx)
);
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
initial forever begin
sys_clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) sys_clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
initial begin
// Initialize Inputs
dat_i = 32'h0000_00ff;
adr_i = 0;
we_i = 0;
stb_i = 0;
//sys_clk = 0;
sys_rst = 0;
uart_rx = 0;
// Wait 100 ns for global reset to finish
#100 ;
#100 sys_rst = 1;
#100 sys_rst = 0;
//#100 we_i = 0;
#100 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#100 stb_i = 1;
// Add stimulus here
end
endmodule |
module pcx_buf_pdl_even(/*AUTOARG*/
// Outputs
arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l,
arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l,
arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa,
arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px,
// Inputs
arbpc0_pcxdp_grant_bufp1_pa_l, arbpc0_pcxdp_q0_hold_bufp1_pa,
arbpc0_pcxdp_qsel0_bufp1_pa_l, arbpc0_pcxdp_qsel1_bufp1_pa,
arbpc0_pcxdp_shift_bufp1_px_l, arbpc2_pcxdp_grant_bufp1_pa_l,
arbpc2_pcxdp_q0_hold_bufp1_pa, arbpc2_pcxdp_qsel0_bufp1_pa_l,
arbpc2_pcxdp_qsel1_bufp1_pa, arbpc2_pcxdp_shift_bufp1_px_l
);
output arbpc0_pcxdp_grant_pa ;
output arbpc0_pcxdp_q0_hold_pa_l ;
output arbpc0_pcxdp_qsel0_pa ;
output arbpc0_pcxdp_qsel1_pa_l ;
output arbpc0_pcxdp_shift_px ;
output arbpc2_pcxdp_grant_pa ;
output arbpc2_pcxdp_q0_hold_pa_l ;
output arbpc2_pcxdp_qsel0_pa ;
output arbpc2_pcxdp_qsel1_pa_l ;
output arbpc2_pcxdp_shift_px ;
input arbpc0_pcxdp_grant_bufp1_pa_l;
input arbpc0_pcxdp_q0_hold_bufp1_pa;
input arbpc0_pcxdp_qsel0_bufp1_pa_l;
input arbpc0_pcxdp_qsel1_bufp1_pa;
input arbpc0_pcxdp_shift_bufp1_px_l;
input arbpc2_pcxdp_grant_bufp1_pa_l;
input arbpc2_pcxdp_q0_hold_bufp1_pa;
input arbpc2_pcxdp_qsel0_bufp1_pa_l;
input arbpc2_pcxdp_qsel1_bufp1_pa;
input arbpc2_pcxdp_shift_bufp1_px_l;
assign arbpc0_pcxdp_grant_pa = ~arbpc0_pcxdp_grant_bufp1_pa_l;
assign arbpc0_pcxdp_q0_hold_pa_l = ~arbpc0_pcxdp_q0_hold_bufp1_pa;
assign arbpc0_pcxdp_qsel0_pa = ~arbpc0_pcxdp_qsel0_bufp1_pa_l;
assign arbpc0_pcxdp_qsel1_pa_l = ~arbpc0_pcxdp_qsel1_bufp1_pa;
assign arbpc0_pcxdp_shift_px = ~arbpc0_pcxdp_shift_bufp1_px_l;
assign arbpc2_pcxdp_grant_pa = ~arbpc2_pcxdp_grant_bufp1_pa_l;
assign arbpc2_pcxdp_q0_hold_pa_l = ~arbpc2_pcxdp_q0_hold_bufp1_pa;
assign arbpc2_pcxdp_qsel0_pa = ~arbpc2_pcxdp_qsel0_bufp1_pa_l;
assign arbpc2_pcxdp_qsel1_pa_l = ~arbpc2_pcxdp_qsel1_bufp1_pa;
assign arbpc2_pcxdp_shift_px = ~arbpc2_pcxdp_shift_bufp1_px_l;
endmodule |
module axis_xgmii_tx_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* XGMII output
*/
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
/*
* Status
*/
output wire [1:0] start_packet,
output wire error_underflow
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
localparam MIN_FL_NOCRC = MIN_FRAME_LENGTH-4;
localparam MIN_FL_NOCRC_MS = MIN_FL_NOCRC & 16'hfff8;
localparam MIN_FL_NOCRC_LS = MIN_FL_NOCRC & 16'h0007;
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_PAD = 3'd2,
STATE_FCS_1 = 3'd3,
STATE_FCS_2 = 3'd4,
STATE_IFG = 3'd5,
STATE_WAIT_END = 3'd6;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg swap_lanes;
reg unswap_lanes;
reg lanes_swapped = 1'b0;
reg [31:0] swap_txd = 32'd0;
reg [3:0] swap_txc = 4'd0;
reg [DATA_WIDTH-1:0] s_axis_tdata_masked;
reg [DATA_WIDTH-1:0] s_tdata_reg = {DATA_WIDTH{1'b0}}, s_tdata_next;
reg [KEEP_WIDTH-1:0] s_tkeep_reg = {KEEP_WIDTH{1'b0}}, s_tkeep_next;
reg [DATA_WIDTH-1:0] fcs_output_txd_0;
reg [DATA_WIDTH-1:0] fcs_output_txd_1;
reg [CTRL_WIDTH-1:0] fcs_output_txc_0;
reg [CTRL_WIDTH-1:0] fcs_output_txc_1;
reg [7:0] ifg_offset;
reg extra_cycle;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
reg [7:0] ifg_count_reg = 8'd0, ifg_count_next;
reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next;
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next;
reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next0;
wire [31:0] crc_next1;
wire [31:0] crc_next2;
wire [31:0] crc_next3;
wire [31:0] crc_next4;
wire [31:0] crc_next5;
wire [31:0] crc_next6;
wire [31:0] crc_next7;
reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next;
reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next;
reg start_packet_reg = 2'b00, start_packet_next;
reg error_underflow_reg = 1'b0, error_underflow_next;
assign s_axis_tready = s_axis_tready_reg;
assign xgmii_txd = xgmii_txd_reg;
assign xgmii_txc = xgmii_txc_reg;
assign m_axis_ptp_ts = PTP_TS_ENABLE ? m_axis_ptp_ts_reg : 0;
assign m_axis_ptp_ts_tag = PTP_TAG_ENABLE ? m_axis_ptp_ts_tag_reg : 0;
assign m_axis_ptp_ts_valid = PTP_TS_ENABLE || PTP_TAG_ENABLE ? m_axis_ptp_ts_valid_reg : 1'b0;
assign start_packet = start_packet_reg;
assign error_underflow = error_underflow_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(s_tdata_reg[7:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next0)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(16),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(s_tdata_reg[15:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next1)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(24),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(s_tdata_reg[23:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next2)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(s_tdata_reg[31:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next3)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(40),
.STYLE("AUTO")
)
eth_crc_40 (
.data_in(s_tdata_reg[39:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next4)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(48),
.STYLE("AUTO")
)
eth_crc_48 (
.data_in(s_tdata_reg[47:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next5)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(56),
.STYLE("AUTO")
)
eth_crc_56 (
.data_in(s_tdata_reg[55:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next6)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(s_tdata_reg[63:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next7)
);
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
// Mask input data
integer j;
always @* begin
for (j = 0; j < 8; j = j + 1) begin
s_axis_tdata_masked[j*8 +: 8] = s_axis_tkeep[j] ? s_axis_tdata[j*8 +: 8] : 8'd0;
end
end
// FCS cycle calculation
always @* begin
casez (s_tkeep_reg)
8'bzzzzzz01: begin
fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_next0[31:0], s_tdata_reg[7:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b11100000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd3;
extra_cycle = 1'b0;
end
8'bzzzzz011: begin
fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_next1[31:0], s_tdata_reg[15:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b11000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd2;
extra_cycle = 1'b0;
end
8'bzzzz0111: begin
fcs_output_txd_0 = {XGMII_TERM, ~crc_next2[31:0], s_tdata_reg[23:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b10000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd1;
extra_cycle = 1'b0;
end
8'bzzz01111: begin
fcs_output_txd_0 = {~crc_next3[31:0], s_tdata_reg[31:0]};
fcs_output_txd_1 = {{7{XGMII_IDLE}}, XGMII_TERM};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd8;
extra_cycle = 1'b1;
end
8'bzz011111: begin
fcs_output_txd_0 = {~crc_next4[23:0], s_tdata_reg[39:0]};
fcs_output_txd_1 = {{6{XGMII_IDLE}}, XGMII_TERM, ~crc_next4[31:24]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111110;
ifg_offset = 8'd7;
extra_cycle = 1'b1;
end
8'bz0111111: begin
fcs_output_txd_0 = {~crc_next5[15:0], s_tdata_reg[47:0]};
fcs_output_txd_1 = {{5{XGMII_IDLE}}, XGMII_TERM, ~crc_next5[31:16]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111100;
ifg_offset = 8'd6;
extra_cycle = 1'b1;
end
8'b01111111: begin
fcs_output_txd_0 = {~crc_next6[7:0], s_tdata_reg[55:0]};
fcs_output_txd_1 = {{4{XGMII_IDLE}}, XGMII_TERM, ~crc_next6[31:8]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111000;
ifg_offset = 8'd5;
extra_cycle = 1'b1;
end
8'b11111111: begin
fcs_output_txd_0 = s_tdata_reg;
fcs_output_txd_1 = {{3{XGMII_IDLE}}, XGMII_TERM, ~crc_next7[31:0]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11110000;
ifg_offset = 8'd4;
extra_cycle = 1'b1;
end
default: begin
fcs_output_txd_0 = {CTRL_WIDTH{XGMII_ERROR}};
fcs_output_txd_1 = {CTRL_WIDTH{XGMII_ERROR}};
fcs_output_txc_0 = {CTRL_WIDTH{1'b1}};
fcs_output_txc_1 = {CTRL_WIDTH{1'b1}};
ifg_offset = 8'd0;
extra_cycle = 1'b1;
end
endcase
end
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
swap_lanes = 1'b0;
unswap_lanes = 1'b0;
frame_ptr_next = frame_ptr_reg;
ifg_count_next = ifg_count_reg;
deficit_idle_count_next = deficit_idle_count_reg;
s_axis_tready_next = 1'b0;
s_tdata_next = s_tdata_reg;
s_tkeep_next = s_tkeep_reg;
m_axis_ptp_ts_next = m_axis_ptp_ts_reg;
m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg;
m_axis_ptp_ts_valid_next = 1'b0;
m_axis_ptp_ts_valid_int_next = 1'b0;
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
start_packet_next = 2'b00;
error_underflow_next = 1'b0;
if (m_axis_ptp_ts_valid_int_reg) begin
m_axis_ptp_ts_valid_next = 1'b1;
if (PTP_TS_WIDTH == 96 && $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000) > 0) begin
// ns field rollover
m_axis_ptp_ts_next[45:16] = $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
m_axis_ptp_ts_next[95:48] = m_axis_ptp_ts_reg[95:48] + 1;
end
end
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 16'd8;
reset_crc = 1'b1;
s_axis_tready_next = 1'b1;
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
s_tdata_next = s_axis_tdata_masked;
s_tkeep_next = s_axis_tkeep;
if (s_axis_tvalid) begin
// XGMII start and preamble
if (ifg_count_reg > 8'd0) begin
// need to send more idles - swap lanes
swap_lanes = 1'b1;
if (PTP_TS_WIDTH == 96) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
end
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_int_next = 1'b1;
start_packet_next = 2'b10;
end else begin
// no more idles - unswap
unswap_lanes = 1'b1;
if (PTP_TS_WIDTH == 96) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
end
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_int_next = 1'b1;
start_packet_next = 2'b01;
end
xgmii_txd_next = {ETH_SFD, {6{ETH_PRE}}, XGMII_START};
xgmii_txc_next = 8'b00000001;
s_axis_tready_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
ifg_count_next = 8'd0;
deficit_idle_count_next = 2'd0;
unswap_lanes = 1'b1;
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
update_crc = 1'b1;
s_axis_tready_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd8;
xgmii_txd_next = s_tdata_reg;
xgmii_txc_next = 8'b00000000;
s_tdata_next = s_axis_tdata_masked;
s_tkeep_next = s_axis_tkeep;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
frame_ptr_next = frame_ptr_reg + keep2count(s_axis_tkeep);
s_axis_tready_next = 1'b0;
if (s_axis_tuser[0]) begin
xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
xgmii_txc_next = 8'b11111111;
frame_ptr_next = 16'd0;
ifg_count_next = 8'd8;
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b0;
if (ENABLE_PADDING && (frame_ptr_reg < MIN_FL_NOCRC_MS || (frame_ptr_reg == MIN_FL_NOCRC_MS && keep2count(s_axis_tkeep) < MIN_FL_NOCRC_LS))) begin
s_tkeep_next = 8'hff;
frame_ptr_next = frame_ptr_reg + 16'd8;
if (frame_ptr_reg < (MIN_FL_NOCRC_LS > 0 ? MIN_FL_NOCRC_MS : MIN_FL_NOCRC_MS-8)) begin
state_next = STATE_PAD;
end else begin
s_tkeep_next = 8'hff >> ((8-MIN_FL_NOCRC_LS) % 8);
state_next = STATE_FCS_1;
end
end else begin
state_next = STATE_FCS_1;
end
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
// tvalid deassert, fail frame
xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
xgmii_txc_next = 8'b11111111;
frame_ptr_next = 16'd0;
ifg_count_next = 8'd8;
error_underflow_next = 1'b1;
state_next = STATE_WAIT_END;
end
end
STATE_PAD: begin
// pad frame to MIN_FRAME_LENGTH
s_axis_tready_next = 1'b0;
xgmii_txd_next = s_tdata_reg;
xgmii_txc_next = {CTRL_WIDTH{1'b0}};
s_tdata_next = 64'd0;
s_tkeep_next = 8'hff;
update_crc = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd8;
if (frame_ptr_reg < (MIN_FL_NOCRC_LS > 0 ? MIN_FL_NOCRC_MS : MIN_FL_NOCRC_MS-8)) begin
state_next = STATE_PAD;
end else begin
s_tkeep_next = 8'hff >> ((8-MIN_FL_NOCRC_LS) % 8);
state_next = STATE_FCS_1;
end
end
STATE_FCS_1: begin
// last cycle
s_axis_tready_next = 1'b0;
xgmii_txd_next = fcs_output_txd_0;
xgmii_txc_next = fcs_output_txc_0;
frame_ptr_next = 16'd0;
ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (lanes_swapped ? 8'd4 : 8'd0) + deficit_idle_count_reg;
if (extra_cycle) begin
state_next = STATE_FCS_2;
end else begin
state_next = STATE_IFG;
end
end
STATE_FCS_2: begin
// last cycle
s_axis_tready_next = 1'b0;
xgmii_txd_next = fcs_output_txd_1;
xgmii_txc_next = fcs_output_txc_1;
reset_crc = 1'b1;
frame_ptr_next = 16'd0;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end
STATE_IFG: begin
// send IFG
if (ifg_count_reg > 8'd8) begin
ifg_count_next = ifg_count_reg - 8'd8;
end else begin
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end
STATE_WAIT_END: begin
// wait for end of frame
s_axis_tready_next = 1'b1;
if (ifg_count_reg > 8'd8) begin
ifg_count_next = ifg_count_reg - 8'd8;
end else begin
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
s_axis_tready_next = 1'b0;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end else begin
state_next = STATE_WAIT_END;
end
end else begin
state_next = STATE_WAIT_END;
end
end
endcase
end
always @(posedge clk) begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
ifg_count_reg <= ifg_count_next;
deficit_idle_count_reg <= deficit_idle_count_next;
s_tdata_reg <= s_tdata_next;
s_tkeep_reg <= s_tkeep_next;
s_axis_tready_reg <= s_axis_tready_next;
m_axis_ptp_ts_reg <= m_axis_ptp_ts_next;
m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next;
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next;
m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next;
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next7;
end
swap_txd <= xgmii_txd_next[63:32];
swap_txc <= xgmii_txc_next[7:4];
if (swap_lanes || (lanes_swapped && !unswap_lanes)) begin
lanes_swapped <= 1'b1;
xgmii_txd_reg <= {xgmii_txd_next[31:0], swap_txd};
xgmii_txc_reg <= {xgmii_txc_next[3:0], swap_txc};
end else begin
lanes_swapped <= 1'b0;
xgmii_txd_reg <= xgmii_txd_next;
xgmii_txc_reg <= xgmii_txc_next;
end
start_packet_reg <= start_packet_next;
error_underflow_reg <= error_underflow_next;
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0;
s_axis_tready_reg <= 1'b0;
m_axis_ptp_ts_valid_reg <= 1'b0;
m_axis_ptp_ts_valid_int_reg <= 1'b0;
xgmii_txd_reg <= {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_reg <= {CTRL_WIDTH{1'b1}};
start_packet_reg <= 2'b00;
error_underflow_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
lanes_swapped <= 1'b0;
end
end
endmodule |
module scsiTarget (
output [7:0] DBx_out, // Active High, connected to SCSI bus via inverter
output REQ, // Active High, connected to SCSI bus via inverter
input nACK, // Active LOW, connected directly to SCSI bus.
input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus.
input nDBP, // Active LOW, connected directly to SCSI bus
input IO, // Active High, set by CPU via status register.
input nRST, // Active LOW, connected directly to SCSI bus.
input clk,
output tx_intr,
output rx_intr,
output parityErr
);
//`#start body` -- edit after this line, do not edit this line
/////////////////////////////////////////////////////////////////////////////
// Force Clock Sync
/////////////////////////////////////////////////////////////////////////////
// The udb_clock_enable primitive component is used to indicate that the input
// clock must always be synchronous and if not implement synchronizers to make
// it synchronous.
wire op_clk;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
(
.clock_in(clk),
.enable(1'b1),
.clock_out(op_clk)
);
/////////////////////////////////////////////////////////////////////////////
// CONSTANTS
/////////////////////////////////////////////////////////////////////////////
localparam IO_WRITE = 1'b1;
localparam IO_READ = 1'b0;
/////////////////////////////////////////////////////////////////////////////
// STATE MACHINE
/////////////////////////////////////////////////////////////////////////////
// TX States:
// IDLE
// Wait for the SCSI Initiator to be ready
// FIFOLOAD
// Load F0 into A0. Feed (old) A0 into the ALU SRCA.
// TX
// Load data register from PO. PO is fed by A0 going into the ALU via SRCA
// A0 must remain unchanged.
// DESKEW_INIT
// DBx output signals will be output in this state
// Load deskew clock count into A0 from D0
// DESKEW
// DBx output signals will be output in this state
// Wait for the SCSI deskew time of 55ns. (DEC A0).
// A1 must be fed into SRCA, so PO is now useless.
// READY
// REQ and DBx output signals will be output in this state
// Wait for acknowledgement from the SCSI initiator
// Wait for space in output fifo
// RX
// Dummy state for flow control.
// REQ signal will be output in this state
// PI enabled for input into ALU "PASS" operation, storing into F1.
//
// RX States:
// IDLE
// Wait for a dummy "enabling" entry in the input FIFO,
// and for the SCSI Initiator to be ready
// FIFOLOAD
// Load F0 into A0.
// The input FIFO is used to control the number of bytes we attempt to
// read from the SCSI bus.
// READY
// REQ signal will be output in this state
// Wait for the initiator to send a byte on the SCSI bus.
// Wait for space in output fifo
// RX
// REQ signal will be output in this state
// PI enabled for input into ALU "PASS" operation, storing into F1.
localparam STATE_IDLE = 3'b000;
localparam STATE_FIFOLOAD = 3'b001;
localparam STATE_TX = 3'b010;
localparam STATE_DESKEW_INIT = 3'b011;
localparam STATE_DESKEW = 3'b100;
localparam STATE_WAIT_TIL_READY = 3'b101;
localparam STATE_READY = 3'b110;
localparam STATE_RX = 3'b111;
// state selects the datapath register.
reg[2:0] state;
// Data being read/written from/to the SCSI bus
reg[7:0] data;
// Set by the datapath zero detector (z1). High when A1 counts down to zero.
wire deskewComplete;
// Parallel input to the datapath SRCA.
// Selected for input through to the ALU if CFB EN bit set for the datapath
// state and enabled by PI DYN bit in CFG15-14
wire[7:0] pi;
// Parallel output from the selected SRCA value (A0 or A1) to the ALU.
wire[7:0] po;
// Set true to trigger storing A1 into F1. Set while in STATE_RX
reg fifoStore;
// Set to true on detecting a parity input while reading
reg parityErrReg;
// Temp values in parity calcs. We need to do it in 2 steps to avoid
// timing issues and running-out-of resources
reg[2:0] genParity;
reg REQReg;
// Set Output Pins
assign REQ = REQReg; // STATE_READY & STATE_RX
assign DBx_out[7:0] = data;
assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus
assign parityErr = parityErrReg;
/////////////////////////////////////////////////////////////////////////////
// FIFO Status Register
/////////////////////////////////////////////////////////////////////////////
// Status Register: scsiTarget_StatusReg__STATUS_REG
// Bit 0: Tx FIFO not full
// Bit 1: Rx FIFO not empty
// Bit 2: Tx FIFO empty
// Bit 3: Rx FIFO full
// Bit 4: TX Complete. Fifos empty and idle.
//
// TX FIFO Register: scsiTarget_scsiTarget_u0__F0_REG
// RX FIFO Register: scsiTarget_scsiTarget_u0__F1_REG
// Use with CY_GET_REG8 and CY_SET_REG8
wire f0_bus_stat; // Tx FIFO not full
wire f0_blk_stat; // Tx FIFO empty
wire f1_bus_stat; // Rx FIFO not empty
wire f1_blk_stat; // Rx FIFO full
wire txComplete = f0_blk_stat && (state == STATE_IDLE) && nACK;
cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg
(
.clock(op_clk),
.status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})
);
// DMA outputs
//assign tx_intr = f0_bus_stat;
assign tx_intr = f0_blk_stat;
//assign rx_intr = f1_bus_stat;
assign rx_intr = f1_blk_stat;
/////////////////////////////////////////////////////////////////////////////
// State machine
/////////////////////////////////////////////////////////////////////////////
always @(posedge op_clk) begin
case (state)
STATE_IDLE:
begin
if (!nRST) state <= STATE_IDLE;
else if (!f0_blk_stat) // Input FIFO has some data
state <= STATE_FIFOLOAD;
else
state <= STATE_IDLE;
// Clear our output pins
data <= 8'b0;
REQReg <= 1'b0;
fifoStore <= 1'b0;
parityErrReg <= 1'b0;
end
STATE_FIFOLOAD:
if (!nRST) state <= STATE_IDLE;
else if (IO == IO_WRITE)
state <= STATE_TX;
// Check that SCSI initiator is ready, and output FIFO is not full.
else if (nACK && !f1_blk_stat) begin
state <= STATE_READY;
REQReg <= 1'b1;
end else begin
state <= STATE_WAIT_TIL_READY;
end
STATE_TX:
begin
if (!nRST) state <= STATE_IDLE;
else state <= STATE_DESKEW_INIT;
data <= po;
end
STATE_DESKEW_INIT:
if (!nRST) state <= STATE_IDLE;
else state <= STATE_DESKEW;
STATE_DESKEW:
if (!nRST) state <= STATE_IDLE;
else if(deskewComplete && nACK) begin
state <= STATE_READY;
REQReg <= 1'b1;
end else if (deskewComplete) begin
state <= STATE_WAIT_TIL_READY;
end else state <= STATE_DESKEW;
STATE_WAIT_TIL_READY:
if (!nRST) state <= STATE_IDLE;
// Check that SCSI initiator is ready, and output FIFO is not full.
// Note that output FIFO is unused in TX mode.
else if (nACK && ((IO == IO_WRITE) || !f1_blk_stat)) begin
state <= STATE_READY;
REQReg <= 1'b1;
end else begin
state <= STATE_WAIT_TIL_READY;
end
STATE_READY:
if (!nRST) state <= STATE_IDLE;
else if (~nACK) begin
state <= STATE_RX;
fifoStore <= 1'b1;
genParity[0] <= (~nDBP) ^ 1'b1 ^ ~nDBx_in[7] ^ ~nDBx_in[6];
genParity[1] <= ~nDBx_in[5] ^ ~nDBx_in[4] ^ ~nDBx_in[3];
genParity[2] <= ~nDBx_in[2] ^ ~nDBx_in[1] ^ ~nDBx_in[0];
end else state <= STATE_READY;
STATE_RX:
begin
state <= STATE_IDLE;
REQReg <= 1'b0;
fifoStore <= 1'b0;
parityErrReg <= 1'b0;
data <= 8'b0;
if (IO == IO_READ) begin
parityErrReg <= ^genParity[2:0];
end
end
default: state <= STATE_IDLE;
endcase
end
// D0 is used for the deskew count.
// The data output is valid during the DESKEW_INIT phase as well,
// so we subtract 1.
// SCSI-1 deskew + cable skew = 55ns
// D0 = [0.000000055 / (1 / clk)] - 1 = 2
// SCSI-2 FAST deskew + cable skew = 25ns
// D0 = [0.000000025 / (1 / clk)] - 1 = 0
cy_psoc3_dp #(.d0_init(2),
.cy_dpconfig(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: WAIT TIL READY*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN,
1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) datapath(
/* input */ .reset(1'b0),
/* input */ .clk(op_clk),
/* input [02:00] */ .cs_addr(state),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(fifoStore),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(deskewComplete),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(f0_bus_stat),
/* output */ .f0_blk_stat(f0_blk_stat),
/* output */ .f1_bus_stat(f1_bus_stat),
/* output */ .f1_blk_stat(f1_blk_stat),
/* input */ .ci(1'b0), // Carry in from previous stage
/* output */ .co(), // Carry out to next stage
/* input */ .sir(1'b0), // Shift in from right side
/* output */ .sor(), // Shift out to right side
/* input */ .sil(1'b0), // Shift in from left side
/* output */ .sol(), // Shift out to left side
/* input */ .msbi(1'b0), // MSB chain in
/* output */ .msbo(), // MSB chain out
/* input [01:00] */ .cei(2'b0), // Compare equal in from prev stage
/* output [01:00] */ .ceo(), // Compare equal out to next stage
/* input [01:00] */ .cli(2'b0), // Compare less than in from prv stage
/* output [01:00] */ .clo(), // Compare less than out to next stage
/* input [01:00] */ .zi(2'b0), // Zero detect in from previous stage
/* output [01:00] */ .zo(), // Zero detect out to next stage
/* input [01:00] */ .fi(2'b0), // 0xFF detect in from previous stage
/* output [01:00] */ .fo(), // 0xFF detect out to next stage
/* input [01:00] */ .capi(2'b0), // Software capture from previous stage
/* output [01:00] */ .capo(), // Software capture to next stage
/* input */ .cfbi(1'b0), // CRC Feedback in from previous stage
/* output */ .cfbo(), // CRC Feedback out to next stage
/* input [07:00] */ .pi(pi), // Parallel data port
/* output [07:00] */ .po(po) // Parallel data port
);
//`#end` -- edit above this line, do not edit this line
endmodule |
module support_dma (
input clk_i,
input enable_i, // When this goes high, it resets the state machine to first state
input d_avail_i, // Goes high when data is available
input [7:0] data_i,
output [15:0] adr_o, // DMA address
output [7:0] data_o,
output wr_o, // To memory
output rd_o, // To SPI
output n_reset_o // To clear the UART before starting
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [2:0] state = 3'd0;
reg [15:0] address = 0;
reg mem_wr = 0;
reg inbound_rd = 0, d_avail = 0;
reg n_reset = 1;
// Assignments ================================================================================
assign rd_o = inbound_rd;
assign data_o = data_i;
assign n_reset_o = n_reset;
//TESTING assign adr_o = {4'b1110,address[11:0]};
assign adr_o = address;
assign wr_o = mem_wr;
// Module connections =========================================================================
always @( posedge clk_i ) d_avail <= d_avail_i; // d_avail is set on negedge
// Simulation branches and control ============================================================
always @(negedge clk_i)
begin
case (state)
0 :begin
address <= 16'd0;
mem_wr <= 0;
inbound_rd <= 0;
if( enable_i ) state <= 3'd1;
end
1 :begin
n_reset <= 0;
state <= 3'd2;
end
2 :begin
n_reset <= 1; // Reset going high will update fifo counters, so wait another step
state <= 3'd3; // For the d_avail_i to be updated
end
3 :begin
if( !enable_i )
state <= 3'd0;
else
if( d_avail )
state <= 3'd4;
end
4 :begin
inbound_rd <= 1'b1; // read takes effect immediately
state <= 3'd5;
end
5 :begin
inbound_rd <= 1'b0;
mem_wr <= 1'b1; // Write only takes effect on next clock posedge
state <= 3'd6;
end
6 :begin
mem_wr <= 1'd0;
state <= 3'd7;
end
7 :begin
address <= address + 1'b1;
state <= 3'd3;
end
default:
state <= 3'd0;
endcase
end
// Other logic ================================================================================
endmodule |
module sky130_fd_sc_ms__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
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