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module RegisterAdd__parameterized3
(Q,
\Q_reg[6] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[6] ;
input [2:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[6] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR[0]),
.D(D[2]),
.Q(Q[2]));
endmodule |
module RegisterAdd__parameterized4
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [30:0]D;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[9]),
.Q(Q[9]));
endmodule |
module RegisterAdd__parameterized5
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [22:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [22:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [22:0]D;
wire [22:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[9]),
.Q(Q[9]));
endmodule |
module RegisterAdd__parameterized6
(\Q_reg[23] ,
Q,
D,
\Q_reg[5] ,
\Q_reg[2]_0 ,
\Q_reg[1]_0 ,
\Q_reg[26] ,
CLK,
AR);
output \Q_reg[23] ;
output [1:0]Q;
output [1:0]D;
input [1:0]\Q_reg[5] ;
input [0:0]\Q_reg[2]_0 ;
input [2:0]\Q_reg[1]_0 ;
input [4:0]\Q_reg[26] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [1:0]D;
wire [1:0]Q;
wire [2:0]\Q_reg[1]_0 ;
wire \Q_reg[23] ;
wire [4:0]\Q_reg[26] ;
wire [0:0]\Q_reg[2]_0 ;
wire [1:0]\Q_reg[5] ;
wire [4:1]Shift_amount_SHT1_EWR;
LUT4 #(
.INIT(16'h2E22))
\Q[25]_i_4
(.I0(Shift_amount_SHT1_EWR[1]),
.I1(\Q_reg[5] [0]),
.I2(\Q_reg[2]_0 ),
.I3(\Q_reg[1]_0 [0]),
.O(\Q_reg[23] ));
LUT4 #(
.INIT(16'h2E22))
\Q[3]_i_1__6
(.I0(Shift_amount_SHT1_EWR[3]),
.I1(\Q_reg[5] [0]),
.I2(\Q_reg[2]_0 ),
.I3(\Q_reg[1]_0 [1]),
.O(D[0]));
LUT4 #(
.INIT(16'h2E22))
\Q[4]_i_1__7
(.I0(Shift_amount_SHT1_EWR[4]),
.I1(\Q_reg[5] [0]),
.I2(\Q_reg[2]_0 ),
.I3(\Q_reg[1]_0 [2]),
.O(D[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [1]),
.Q(Shift_amount_SHT1_EWR[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [2]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [3]),
.Q(Shift_amount_SHT1_EWR[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [4]),
.Q(Shift_amount_SHT1_EWR[4]));
endmodule |
module RegisterAdd__parameterized7
(Q,
\Q_reg[5] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[5] ;
input [2:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[5] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR[0]),
.D(D[2]),
.Q(Q[2]));
endmodule |
module RegisterAdd__parameterized8
(Q,
\Q_reg[4]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[4]_0 ;
input [30:0]D;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[4]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[9]),
.Q(Q[9]));
endmodule |
module RegisterAdd__parameterized9
(D,
\Data_array_SWR[6]_3 ,
\Q_reg[25]_0 ,
\Q_reg[8]_0 ,
\Q_reg[13]_0 ,
\Data_array_SWR[4]_4 ,
Q,
\Q_reg[4]_0 ,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[4]_1 ,
E,
\Q_reg[2]_0 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [2:0]D;
output [0:0]\Data_array_SWR[6]_3 ;
output [4:0]\Q_reg[25]_0 ;
output [11:0]\Q_reg[8]_0 ;
output [7:0]\Q_reg[13]_0 ;
output [1:0]\Data_array_SWR[4]_4 ;
input [1:0]Q;
input [1:0]\Q_reg[4]_0 ;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [2:0]\Q_reg[4]_1 ;
input [0:0]E;
input [25:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [2:0]D;
wire [17:0]\Data_array_SWR[3]_0 ;
wire [1:0]\Data_array_SWR[4]_4 ;
wire [13:0]\Data_array_SWR[5]_2 ;
wire [0:0]\Data_array_SWR[6]_3 ;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [7:0]\Q_reg[13]_0 ;
wire [4:0]\Q_reg[25]_0 ;
wire [25:0]\Q_reg[2]_0 ;
wire [1:0]\Q_reg[4]_0 ;
wire [2:0]\Q_reg[4]_1 ;
wire [11:0]\Q_reg[8]_0 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hFF00B8B8))
\Q[0]_i_1__13
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_1 [2]),
.I2(\Data_array_SWR[5]_2 [0]),
.I3(\Q_reg[4]_0 [1]),
.I4(Q[1]),
.O(\Q_reg[25]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'h02))
\Q[10]_i_1__8
(.I0(\Q_reg[25]_0 [1]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'h02))
\Q[11]_i_1__8
(.I0(\Q_reg[25]_0 [2]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[12]_i_1__8
(.I0(\Data_array_SWR[5]_2 [13]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [2]),
.I4(\Data_array_SWR[5]_2 [12]),
.O(\Q_reg[25]_0 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_4__0
(.I0(\Q_reg[13]_0 [5]),
.I1(\Q_reg[13]_0 [1]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [15]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [11]),
.O(\Q_reg[8]_0 [9]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_5__0
(.I0(\Q_reg[13]_0 [0]),
.I1(\Q_reg[4]_1 [0]),
.I2(\Data_array_SWR[3]_0 [14]),
.O(\Data_array_SWR[4]_4 [0]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[13]_i_1__6
(.I0(\Data_array_SWR[5]_2 [12]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [2]),
.I4(\Data_array_SWR[5]_2 [13]),
.O(\Q_reg[25]_0 [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_2__1
(.I0(\Q_reg[13]_0 [6]),
.I1(\Q_reg[13]_0 [2]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [16]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [12]),
.O(\Data_array_SWR[5]_2 [12]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_3
(.I0(\Q_reg[13]_0 [7]),
.I1(\Q_reg[13]_0 [3]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [17]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [13]),
.O(\Data_array_SWR[5]_2 [13]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_4
(.I0(\Q_reg[13]_0 [4]),
.I1(\Q_reg[13]_0 [0]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [14]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [10]),
.O(\Q_reg[8]_0 [8]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_5
(.I0(\Q_reg[13]_0 [1]),
.I1(\Q_reg[4]_1 [0]),
.I2(\Data_array_SWR[3]_0 [15]),
.O(\Data_array_SWR[4]_4 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_3
(.I0(\Q_reg[13]_0 [3]),
.I1(\Data_array_SWR[3]_0 [17]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [13]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [9]),
.O(\Q_reg[8]_0 [7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_4
(.I0(\Q_reg[13]_0 [1]),
.I1(\Data_array_SWR[3]_0 [15]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [11]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [7]),
.O(\Q_reg[8]_0 [5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_3
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [7]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Q_reg[13]_0 [3]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [17]),
.O(\Q_reg[8]_0 [11]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_4
(.I0(\Q_reg[13]_0 [0]),
.I1(\Data_array_SWR[3]_0 [14]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [10]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [6]),
.O(\Q_reg[8]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_4__0
(.I0(\Q_reg[13]_0 [2]),
.I1(\Data_array_SWR[3]_0 [16]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [12]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [8]),
.O(\Q_reg[8]_0 [6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_5
(.I0(\Data_array_SWR[3]_0 [17]),
.I1(\Data_array_SWR[3]_0 [13]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [9]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [5]),
.O(\Q_reg[8]_0 [3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_5
(.I0(\Data_array_SWR[3]_0 [16]),
.I1(\Data_array_SWR[3]_0 [12]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [8]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [4]),
.O(\Q_reg[8]_0 [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_5
(.I0(\Data_array_SWR[3]_0 [15]),
.I1(\Data_array_SWR[3]_0 [11]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [7]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [3]),
.O(\Q_reg[8]_0 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_5
(.I0(\Data_array_SWR[3]_0 [14]),
.I1(\Data_array_SWR[3]_0 [10]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [6]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [2]),
.O(\Q_reg[8]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[22]_i_1__8
(.I0(\Data_array_SWR[6]_3 ),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [0]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[2]));
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_2__0
(.I0(\Q_reg[8]_0 [11]),
.I1(\Q_reg[4]_1 [2]),
.I2(\Data_array_SWR[5]_2 [1]),
.O(\Data_array_SWR[6]_3 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_4
(.I0(\Data_array_SWR[3]_0 [13]),
.I1(\Data_array_SWR[3]_0 [9]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [5]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [1]),
.O(\Data_array_SWR[5]_2 [1]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_1__8
(.I0(\Data_array_SWR[6]_3 ),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [0]),
.O(\Q_reg[25]_0 [3]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hB8FFB800))
\Q[25]_i_1__8
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_1 [2]),
.I2(\Data_array_SWR[5]_2 [0]),
.I3(Q[1]),
.I4(\Q_reg[4]_0 [1]),
.O(\Q_reg[25]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [6]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Q_reg[13]_0 [2]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [16]),
.O(\Q_reg[8]_0 [10]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_3__0
(.I0(\Data_array_SWR[3]_0 [12]),
.I1(\Data_array_SWR[3]_0 [8]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [4]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [0]),
.O(\Data_array_SWR[5]_2 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [0]),
.Q(\Data_array_SWR[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [10]),
.Q(\Data_array_SWR[3]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [11]),
.Q(\Data_array_SWR[3]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [12]),
.Q(\Data_array_SWR[3]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [13]),
.Q(\Data_array_SWR[3]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [14]),
.Q(\Data_array_SWR[3]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [15]),
.Q(\Data_array_SWR[3]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [16]),
.Q(\Data_array_SWR[3]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [17]),
.Q(\Data_array_SWR[3]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [18]),
.Q(\Q_reg[13]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [19]),
.Q(\Q_reg[13]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [1]),
.Q(\Data_array_SWR[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [20]),
.Q(\Q_reg[13]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [21]),
.Q(\Q_reg[13]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [22]),
.Q(\Q_reg[13]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [23]),
.Q(\Q_reg[13]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [24]),
.Q(\Q_reg[13]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [25]),
.Q(\Q_reg[13]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [2]),
.Q(\Data_array_SWR[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [3]),
.Q(\Data_array_SWR[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [4]),
.Q(\Data_array_SWR[3]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [5]),
.Q(\Data_array_SWR[3]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [6]),
.Q(\Data_array_SWR[3]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [7]),
.Q(\Data_array_SWR[3]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [8]),
.Q(\Data_array_SWR[3]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [9]),
.Q(\Data_array_SWR[3]_0 [9]));
endmodule |
module ShiftRegister
(E,
Q,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
\Q_reg[2]_0 ,
\FSM_sequential_state_reg_reg[0] ,
D,
CLK,
AR);
output [0:0]E;
output [5:0]Q;
output [0:0]\Q_reg[1]_0 ;
output [1:0]\Q_reg[1]_1 ;
input [0:0]\Q_reg[2]_0 ;
input [0:0]\FSM_sequential_state_reg_reg[0] ;
input [0:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[0] ;
wire [5:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [1:0]\Q_reg[1]_1 ;
wire [0:0]\Q_reg[2]_0 ;
wire \Q_reg_n_0_[3] ;
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT2 #(
.INIT(4'h8))
\Q[0]_i_1__9
(.I0(Q[1]),
.I1(\Q_reg[2]_0 ),
.O(\Q_reg[1]_1 [0]));
LUT2 #(
.INIT(4'h2))
\Q[1]_i_1__7
(.I0(Q[1]),
.I1(\Q_reg[2]_0 ),
.O(\Q_reg[1]_1 [1]));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT2 #(
.INIT(4'hE))
\Q[25]_i_1__6
(.I0(Q[1]),
.I1(Q[3]),
.O(\Q_reg[1]_0 ));
LUT2 #(
.INIT(4'h2))
\Q[30]_i_1__6
(.I0(\Q_reg_n_0_[3] ),
.I1(Q[0]),
.O(E));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[1]),
.D(Q[1]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[2]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(\Q_reg_n_0_[3] ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[4]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[5]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(D),
.Q(Q[5]));
endmodule |
module Simple_Subt
(D,
Q,
\Q_reg[26] ,
S);
output [7:0]D;
input [6:0]Q;
input [3:0]\Q_reg[26] ;
input [3:0]S;
wire [7:0]D;
wire [6:0]Q;
wire [3:0]\Q_reg[26] ;
wire [3:0]S;
wire Y_carry__0_n_1;
wire Y_carry__0_n_2;
wire Y_carry__0_n_3;
wire Y_carry_n_0;
wire Y_carry_n_1;
wire Y_carry_n_2;
wire Y_carry_n_3;
wire [3:3]NLW_Y_carry__0_CO_UNCONNECTED;
CARRY4 Y_carry
(.CI(1'b0),
.CO({Y_carry_n_0,Y_carry_n_1,Y_carry_n_2,Y_carry_n_3}),
.CYINIT(1'b1),
.DI(Q[3:0]),
.O(D[3:0]),
.S(\Q_reg[26] ));
CARRY4 Y_carry__0
(.CI(Y_carry_n_0),
.CO({NLW_Y_carry__0_CO_UNCONNECTED[3],Y_carry__0_n_1,Y_carry__0_n_2,Y_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Q[6:4]}),
.O(D[7:4]),
.S(S));
endmodule |
module Up_counter
(Q,
max_tick_iter,
D,
\Q_reg[31] ,
\Q_reg[31]_0 ,
\Q_reg[26] ,
\Q_reg[31]_1 ,
\Q_reg[31]_2 ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
SR,
E,
CLK);
output [3:0]Q;
output max_tick_iter;
output [31:0]D;
output [31:0]\Q_reg[31] ;
output [31:0]\Q_reg[31]_0 ;
output [19:0]\Q_reg[26] ;
input [31:0]\Q_reg[31]_1 ;
input [31:0]\Q_reg[31]_2 ;
input [31:0]\Q_reg[31]_3 ;
input [31:0]\Q_reg[31]_4 ;
input [0:0]SR;
input [0:0]E;
input CLK;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [19:0]\Q_reg[26] ;
wire [31:0]\Q_reg[31] ;
wire [31:0]\Q_reg[31]_0 ;
wire [31:0]\Q_reg[31]_1 ;
wire [31:0]\Q_reg[31]_2 ;
wire [31:0]\Q_reg[31]_3 ;
wire [31:0]\Q_reg[31]_4 ;
wire [0:0]SR;
wire max_tick_iter;
wire [3:0]p_0_in;
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h8000))
\FSM_sequential_state_reg[2]_i_2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(max_tick_iter));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7465))
\Q[0]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.O(\Q_reg[26] [0]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[0]_i_1__0
(.I0(\Q_reg[31]_1 [0]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [0]),
.O(D[0]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[0]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [0]),
.O(\Q_reg[31]_0 [0]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[0]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [0]),
.O(\Q_reg[31] [0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7445))
\Q[10]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[1]),
.O(\Q_reg[26] [7]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[10]_i_1__0
(.I0(\Q_reg[31]_1 [10]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [10]),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[10]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [10]),
.O(\Q_reg[31] [10]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[10]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [10]),
.O(\Q_reg[31]_0 [10]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h55EF))
\Q[11]_i_1
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[3]),
.O(\Q_reg[26] [8]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[11]_i_1__0
(.I0(\Q_reg[31]_1 [11]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [11]),
.O(D[11]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[11]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [11]),
.O(\Q_reg[31]_0 [11]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[11]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [11]),
.O(\Q_reg[31] [11]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6474))
\Q[12]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.O(\Q_reg[26] [9]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[12]_i_1__0
(.I0(\Q_reg[31]_1 [12]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [12]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[12]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [12]),
.O(\Q_reg[31] [12]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[12]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [12]),
.O(\Q_reg[31]_0 [12]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[13]_i_1
(.I0(\Q_reg[31]_1 [13]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [13]),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[13]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [13]),
.O(\Q_reg[31] [13]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[13]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [13]),
.O(\Q_reg[31]_0 [13]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h54BE))
\Q[14]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.O(\Q_reg[26] [10]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[14]_i_1__0
(.I0(\Q_reg[31]_1 [14]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [14]),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[14]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [14]),
.O(\Q_reg[31] [14]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[14]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [14]),
.O(\Q_reg[31]_0 [14]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[15]_i_1
(.I0(\Q_reg[31]_1 [15]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [15]),
.O(D[15]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[15]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [15]),
.O(\Q_reg[31]_0 [15]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[15]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [15]),
.O(\Q_reg[31] [15]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[16]_i_1
(.I0(\Q_reg[31]_1 [16]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [16]),
.O(D[16]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[16]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [16]),
.O(\Q_reg[31] [16]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[16]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [16]),
.O(\Q_reg[31]_0 [16]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h5B))
\Q[16]_i_1__7
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.O(\Q_reg[26] [11]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[17]_i_1
(.I0(\Q_reg[31]_1 [17]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [17]),
.O(D[17]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[17]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [17]),
.O(\Q_reg[31] [17]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[17]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [17]),
.O(\Q_reg[31]_0 [17]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[18]_i_1
(.I0(\Q_reg[31]_1 [18]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [18]),
.O(D[18]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[18]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [18]),
.O(\Q_reg[31]_0 [18]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[18]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [18]),
.O(\Q_reg[31] [18]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h5E))
\Q[18]_i_1__7
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.O(\Q_reg[26] [12]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[19]_i_1
(.I0(\Q_reg[31]_1 [19]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [19]),
.O(D[19]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[19]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [19]),
.O(\Q_reg[31] [19]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[19]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [19]),
.O(\Q_reg[31]_0 [19]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[1]_i_1__0
(.I0(\Q_reg[31]_1 [1]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[1]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [1]),
.O(\Q_reg[31] [1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h55AB))
\Q[1]_i_1__12
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.O(\Q_reg[26] [1]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[1]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [1]),
.O(\Q_reg[31]_0 [1]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[20]_i_1
(.I0(\Q_reg[31]_1 [20]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [20]),
.O(D[20]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[20]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [20]),
.O(\Q_reg[31] [20]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[20]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [20]),
.O(\Q_reg[31]_0 [20]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h5E))
\Q[20]_i_1__7
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.O(\Q_reg[26] [13]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h55FE))
\Q[21]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(\Q_reg[26] [14]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[21]_i_1__0
(.I0(\Q_reg[31]_1 [21]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [21]),
.O(D[21]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[21]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [21]),
.O(\Q_reg[31]_0 [21]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[21]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [21]),
.O(\Q_reg[31] [21]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h7))
\Q[22]_i_1
(.I0(Q[3]),
.I1(Q[2]),
.O(\Q_reg[26] [15]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[22]_i_1__0
(.I0(\Q_reg[31]_1 [22]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [22]),
.O(D[22]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[22]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [22]),
.O(\Q_reg[31]_0 [22]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[22]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [22]),
.O(\Q_reg[31] [22]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[23]_i_1
(.I0(\Q_reg[31]_1 [23]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [23]),
.O(D[23]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[23]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [23]),
.O(\Q_reg[31]_0 [23]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[23]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [23]),
.O(\Q_reg[31] [23]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h6A))
\Q[23]_i_1__8
(.I0(Q[0]),
.I1(Q[2]),
.I2(Q[3]),
.O(\Q_reg[26] [16]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h708F))
\Q[24]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[1]),
.O(\Q_reg[26] [17]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[24]_i_1__0
(.I0(\Q_reg[31]_1 [24]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [24]),
.O(D[24]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[24]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [24]),
.O(\Q_reg[31] [24]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[24]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [24]),
.O(\Q_reg[31]_0 [24]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h0787))
\Q[25]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\Q_reg[26] [18]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[25]_i_1__0
(.I0(\Q_reg[31]_1 [25]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [25]),
.O(D[25]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[25]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [25]),
.O(\Q_reg[31] [25]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[25]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [25]),
.O(\Q_reg[31]_0 [25]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h007F))
\Q[26]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[3]),
.O(\Q_reg[26] [19]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[26]_i_1__0
(.I0(\Q_reg[31]_1 [26]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [26]),
.O(D[26]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[26]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [26]),
.O(\Q_reg[31] [26]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[26]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [26]),
.O(\Q_reg[31]_0 [26]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[27]_i_1
(.I0(\Q_reg[31]_1 [27]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [27]),
.O(D[27]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[27]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [27]),
.O(\Q_reg[31] [27]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[27]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [27]),
.O(\Q_reg[31]_0 [27]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[28]_i_1
(.I0(\Q_reg[31]_1 [28]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [28]),
.O(D[28]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[28]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [28]),
.O(\Q_reg[31] [28]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[28]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [28]),
.O(\Q_reg[31]_0 [28]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[29]_i_1__0
(.I0(\Q_reg[31]_1 [29]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [29]),
.O(D[29]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[29]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [29]),
.O(\Q_reg[31] [29]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[29]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [29]),
.O(\Q_reg[31]_0 [29]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[2]_i_1
(.I0(\Q_reg[31]_1 [2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[2]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [2]),
.O(\Q_reg[31] [2]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[2]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [2]),
.O(\Q_reg[31]_0 [2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0858))
\Q[2]_i_1__10
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\Q_reg[26] [2]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[30]_i_1
(.I0(\Q_reg[31]_1 [30]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [30]),
.O(D[30]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[30]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [30]),
.O(\Q_reg[31]_0 [30]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[30]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [30]),
.O(\Q_reg[31] [30]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[31]_i_1__3
(.I0(\Q_reg[31]_1 [31]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [31]),
.O(D[31]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[31]_i_1__4
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(\Q_reg[31]_4 [31]),
.O(\Q_reg[31]_0 [31]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[31]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(\Q_reg[31]_3 [31]),
.O(\Q_reg[31] [31]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[3]_i_1
(.I0(\Q_reg[31]_1 [3]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[3]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [3]),
.O(\Q_reg[31] [3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[3]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [3]),
.O(\Q_reg[31]_0 [3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h01F3))
\Q[4]_i_1
(.I0(Q[0]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[2]),
.O(\Q_reg[26] [3]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[4]_i_1__0
(.I0(\Q_reg[31]_1 [4]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [4]),
.O(D[4]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[4]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [4]),
.O(\Q_reg[31]_0 [4]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[4]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [4]),
.O(\Q_reg[31] [4]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[5]_i_1
(.I0(\Q_reg[31]_1 [5]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[5]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [5]),
.O(\Q_reg[31] [5]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[5]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [5]),
.O(\Q_reg[31]_0 [5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h5443))
\Q[6]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(\Q_reg[26] [4]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[6]_i_1__1
(.I0(\Q_reg[31]_1 [6]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[6]_i_1__2
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [6]),
.O(\Q_reg[31] [6]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[6]_i_1__3
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [6]),
.O(\Q_reg[31]_0 [6]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[7]_i_1
(.I0(\Q_reg[31]_1 [7]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[7]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [7]),
.O(\Q_reg[31] [7]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[7]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [7]),
.O(\Q_reg[31]_0 [7]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT1 #(
.INIT(2'h1))
\Q[8]_i_1
(.I0(Q[2]),
.O(\Q_reg[26] [5]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[8]_i_1__0
(.I0(\Q_reg[31]_1 [8]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [8]),
.O(D[8]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[8]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [8]),
.O(\Q_reg[31]_0 [8]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[8]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [8]),
.O(\Q_reg[31] [8]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h55BF))
\Q[9]_i_1
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[3]),
.O(\Q_reg[26] [6]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[9]_i_1__0
(.I0(\Q_reg[31]_1 [9]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [9]),
.O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[9]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [9]),
.O(\Q_reg[31]_0 [9]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[9]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [9]),
.O(\Q_reg[31] [9]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT1 #(
.INIT(2'h1))
\temp[0]_i_1
(.I0(Q[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h6))
\temp[1]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h78))
\temp[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h6AAA))
\temp[3]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.O(p_0_in[3]));
FDRE #(
.INIT(1'b0))
\temp_reg[0]
(.C(CLK),
.CE(E),
.D(p_0_in[0]),
.Q(Q[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\temp_reg[1]
(.C(CLK),
.CE(E),
.D(p_0_in[1]),
.Q(Q[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\temp_reg[2]
(.C(CLK),
.CE(E),
.D(p_0_in[2]),
.Q(Q[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\temp_reg[3]
(.C(CLK),
.CE(E),
.D(p_0_in[3]),
.Q(Q[3]),
.R(SR));
endmodule |
module Up_counter__parameterized0
(E,
cont_var_out,
\Q_reg[31] ,
\Q_reg[31]_0 ,
D,
\Q_reg[31]_1 ,
op_add_subt,
ready_add_subt,
Q,
\Q_reg[31]_2 ,
\Q_reg[29] ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
\Q_reg[31]_5 ,
d_ff3_sign_out,
out,
rst_IBUF,
CLK);
output [0:0]E;
output [1:0]cont_var_out;
output [0:0]\Q_reg[31] ;
output [0:0]\Q_reg[31]_0 ;
output [31:0]D;
output [31:0]\Q_reg[31]_1 ;
output op_add_subt;
input ready_add_subt;
input [31:0]Q;
input [31:0]\Q_reg[31]_2 ;
input [20:0]\Q_reg[29] ;
input [31:0]\Q_reg[31]_3 ;
input [31:0]\Q_reg[31]_4 ;
input [31:0]\Q_reg[31]_5 ;
input d_ff3_sign_out;
input [1:0]out;
input rst_IBUF;
input CLK;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
wire [20:0]\Q_reg[29] ;
wire [0:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [31:0]\Q_reg[31]_1 ;
wire [31:0]\Q_reg[31]_2 ;
wire [31:0]\Q_reg[31]_3 ;
wire [31:0]\Q_reg[31]_4 ;
wire [31:0]\Q_reg[31]_5 ;
wire [1:0]cont_var_out;
wire d_ff3_sign_out;
wire op_add_subt;
wire [1:0]out;
wire ready_add_subt;
wire rst_IBUF;
wire \temp[0]_i_1_n_0 ;
wire \temp[1]_i_1_n_0 ;
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[0]_i_1__3
(.I0(\Q_reg[29] [0]),
.I1(Q[0]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [0]),
.I4(cont_var_out[1]),
.O(D[0]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[0]_i_1__4
(.I0(\Q_reg[31]_3 [0]),
.I1(\Q_reg[31]_4 [0]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [0]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [0]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h6))
\Q[0]_i_1__6
(.I0(cont_var_out[0]),
.I1(d_ff3_sign_out),
.O(op_add_subt));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[10]_i_1__3
(.I0(\Q_reg[29] [7]),
.I1(Q[10]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [10]),
.I4(cont_var_out[1]),
.O(D[10]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[10]_i_1__4
(.I0(\Q_reg[31]_3 [10]),
.I1(\Q_reg[31]_4 [10]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [10]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [10]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[11]_i_1__3
(.I0(\Q_reg[29] [8]),
.I1(Q[11]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [11]),
.I4(cont_var_out[1]),
.O(D[11]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[11]_i_1__4
(.I0(\Q_reg[31]_3 [11]),
.I1(\Q_reg[31]_4 [11]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [11]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [11]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[12]_i_1__3
(.I0(\Q_reg[29] [9]),
.I1(Q[12]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [12]),
.I4(cont_var_out[1]),
.O(D[12]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[12]_i_1__4
(.I0(\Q_reg[31]_3 [12]),
.I1(\Q_reg[31]_4 [12]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [12]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [12]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[13]_i_1__2
(.I0(\Q_reg[29] [12]),
.I1(Q[13]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [13]),
.I4(cont_var_out[1]),
.O(D[13]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[13]_i_1__3
(.I0(\Q_reg[31]_3 [13]),
.I1(\Q_reg[31]_4 [13]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [13]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [13]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[14]_i_1__3
(.I0(\Q_reg[29] [10]),
.I1(Q[14]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [14]),
.I4(cont_var_out[1]),
.O(D[14]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[14]_i_1__4
(.I0(\Q_reg[31]_3 [14]),
.I1(\Q_reg[31]_4 [14]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [14]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [14]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[15]_i_1__2
(.I0(\Q_reg[29] [13]),
.I1(Q[15]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [15]),
.I4(cont_var_out[1]),
.O(D[15]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[15]_i_1__3
(.I0(\Q_reg[31]_3 [15]),
.I1(\Q_reg[31]_4 [15]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [15]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [15]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[16]_i_1__2
(.I0(\Q_reg[29] [11]),
.I1(Q[16]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [16]),
.I4(cont_var_out[1]),
.O(D[16]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[16]_i_1__3
(.I0(\Q_reg[31]_3 [16]),
.I1(\Q_reg[31]_4 [16]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [16]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [16]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[17]_i_1__2
(.I0(\Q_reg[29] [13]),
.I1(Q[17]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [17]),
.I4(cont_var_out[1]),
.O(D[17]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[17]_i_1__3
(.I0(\Q_reg[31]_3 [17]),
.I1(\Q_reg[31]_4 [17]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [17]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [17]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[18]_i_1__2
(.I0(\Q_reg[29] [12]),
.I1(Q[18]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [18]),
.I4(cont_var_out[1]),
.O(D[18]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[18]_i_1__3
(.I0(\Q_reg[31]_3 [18]),
.I1(\Q_reg[31]_4 [18]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [18]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [18]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[19]_i_1__2
(.I0(\Q_reg[29] [15]),
.I1(Q[19]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [19]),
.I4(cont_var_out[1]),
.O(D[19]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[19]_i_1__3
(.I0(\Q_reg[31]_3 [19]),
.I1(\Q_reg[31]_4 [19]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [19]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [19]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[1]_i_1__3
(.I0(\Q_reg[29] [1]),
.I1(Q[1]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [1]),
.I4(cont_var_out[1]),
.O(D[1]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[1]_i_1__4
(.I0(\Q_reg[31]_3 [1]),
.I1(\Q_reg[31]_4 [1]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [1]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [1]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[20]_i_1__2
(.I0(\Q_reg[29] [13]),
.I1(Q[20]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [20]),
.I4(cont_var_out[1]),
.O(D[20]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[20]_i_1__3
(.I0(\Q_reg[31]_3 [20]),
.I1(\Q_reg[31]_4 [20]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [20]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [20]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[21]_i_1__3
(.I0(\Q_reg[29] [14]),
.I1(Q[21]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [21]),
.I4(cont_var_out[1]),
.O(D[21]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[21]_i_1__4
(.I0(\Q_reg[31]_3 [21]),
.I1(\Q_reg[31]_4 [21]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [21]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [21]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[22]_i_1__3
(.I0(\Q_reg[29] [15]),
.I1(Q[22]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [22]),
.I4(cont_var_out[1]),
.O(D[22]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[22]_i_1__4
(.I0(\Q_reg[31]_3 [22]),
.I1(\Q_reg[31]_4 [22]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [22]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [22]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[23]_i_1__2
(.I0(\Q_reg[29] [16]),
.I1(Q[23]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [23]),
.I4(cont_var_out[1]),
.O(D[23]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[23]_i_1__3
(.I0(\Q_reg[31]_3 [23]),
.I1(\Q_reg[31]_4 [23]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [23]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [23]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[24]_i_1__3
(.I0(\Q_reg[29] [17]),
.I1(Q[24]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [24]),
.I4(cont_var_out[1]),
.O(D[24]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[24]_i_1__4
(.I0(\Q_reg[31]_3 [24]),
.I1(\Q_reg[31]_4 [24]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [24]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [24]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[25]_i_1__3
(.I0(\Q_reg[29] [18]),
.I1(Q[25]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [25]),
.I4(cont_var_out[1]),
.O(D[25]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[25]_i_1__4
(.I0(\Q_reg[31]_3 [25]),
.I1(\Q_reg[31]_4 [25]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [25]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [25]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[26]_i_1__3
(.I0(\Q_reg[29] [19]),
.I1(Q[26]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [26]),
.I4(cont_var_out[1]),
.O(D[26]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[26]_i_1__4
(.I0(\Q_reg[31]_3 [26]),
.I1(\Q_reg[31]_4 [26]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [26]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [26]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[27]_i_1__2
(.I0(\Q_reg[29] [20]),
.I1(Q[27]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [27]),
.I4(cont_var_out[1]),
.O(D[27]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[27]_i_1__3
(.I0(\Q_reg[31]_3 [27]),
.I1(\Q_reg[31]_4 [27]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [27]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [27]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[28]_i_1__2
(.I0(\Q_reg[29] [20]),
.I1(Q[28]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [28]),
.I4(cont_var_out[1]),
.O(D[28]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[28]_i_1__3
(.I0(\Q_reg[31]_3 [28]),
.I1(\Q_reg[31]_4 [28]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [28]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [28]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[29]_i_1__3
(.I0(\Q_reg[29] [20]),
.I1(Q[29]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [29]),
.I4(cont_var_out[1]),
.O(D[29]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[29]_i_1__4
(.I0(\Q_reg[31]_3 [29]),
.I1(\Q_reg[31]_4 [29]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [29]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [29]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[2]_i_1__2
(.I0(\Q_reg[29] [2]),
.I1(Q[2]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [2]),
.I4(cont_var_out[1]),
.O(D[2]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[2]_i_1__3
(.I0(\Q_reg[31]_3 [2]),
.I1(\Q_reg[31]_4 [2]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [2]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [2]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h3088))
\Q[30]_i_1__2
(.I0(Q[30]),
.I1(cont_var_out[0]),
.I2(\Q_reg[31]_2 [30]),
.I3(cont_var_out[1]),
.O(D[30]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[30]_i_1__3
(.I0(\Q_reg[31]_3 [30]),
.I1(\Q_reg[31]_4 [30]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [30]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [30]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h08))
\Q[31]_i_1__0
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(cont_var_out[0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'h04))
\Q[31]_i_1__1
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(cont_var_out[0]),
.O(\Q_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'h40))
\Q[31]_i_1__2
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(cont_var_out[0]),
.O(\Q_reg[31]_0 ));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[31]_i_1__5
(.I0(\Q_reg[31]_3 [31]),
.I1(\Q_reg[31]_4 [31]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [31]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [31]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h3088))
\Q[31]_i_2__1
(.I0(Q[31]),
.I1(cont_var_out[0]),
.I2(\Q_reg[31]_2 [31]),
.I3(cont_var_out[1]),
.O(D[31]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[3]_i_1__2
(.I0(\Q_reg[29] [11]),
.I1(Q[3]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [3]),
.I4(cont_var_out[1]),
.O(D[3]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[3]_i_1__3
(.I0(\Q_reg[31]_3 [3]),
.I1(\Q_reg[31]_4 [3]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [3]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [3]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[4]_i_1__3
(.I0(\Q_reg[29] [3]),
.I1(Q[4]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [4]),
.I4(cont_var_out[1]),
.O(D[4]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[4]_i_1__4
(.I0(\Q_reg[31]_3 [4]),
.I1(\Q_reg[31]_4 [4]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [4]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [4]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[5]_i_1__2
(.I0(\Q_reg[29] [10]),
.I1(Q[5]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [5]),
.I4(cont_var_out[1]),
.O(D[5]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[5]_i_1__3
(.I0(\Q_reg[31]_3 [5]),
.I1(\Q_reg[31]_4 [5]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [5]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [5]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[6]_i_1__4
(.I0(\Q_reg[29] [4]),
.I1(Q[6]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [6]),
.I4(cont_var_out[1]),
.O(D[6]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[6]_i_1__5
(.I0(\Q_reg[31]_3 [6]),
.I1(\Q_reg[31]_4 [6]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [6]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [6]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[7]_i_1__2
(.I0(\Q_reg[29] [8]),
.I1(Q[7]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [7]),
.I4(cont_var_out[1]),
.O(D[7]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[7]_i_1__3
(.I0(\Q_reg[31]_3 [7]),
.I1(\Q_reg[31]_4 [7]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [7]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [7]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[8]_i_1__3
(.I0(\Q_reg[29] [5]),
.I1(Q[8]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [8]),
.I4(cont_var_out[1]),
.O(D[8]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[8]_i_1__4
(.I0(\Q_reg[31]_3 [8]),
.I1(\Q_reg[31]_4 [8]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [8]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [8]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[9]_i_1__3
(.I0(\Q_reg[29] [6]),
.I1(Q[9]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [9]),
.I4(cont_var_out[1]),
.O(D[9]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[9]_i_1__4
(.I0(\Q_reg[31]_3 [9]),
.I1(\Q_reg[31]_4 [9]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [9]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [9]));
LUT5 #(
.INIT(32'h0000559A))
\temp[0]_i_1
(.I0(cont_var_out[0]),
.I1(out[0]),
.I2(out[1]),
.I3(ready_add_subt),
.I4(rst_IBUF),
.O(\temp[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000006656AAAA))
\temp[1]_i_1
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(out[1]),
.I3(out[0]),
.I4(cont_var_out[0]),
.I5(rst_IBUF),
.O(\temp[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\temp_reg[0]
(.C(CLK),
.CE(1'b1),
.D(\temp[0]_i_1_n_0 ),
.Q(cont_var_out[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_reg[1]
(.C(CLK),
.CE(1'b1),
.D(\temp[1]_i_1_n_0 ),
.Q(cont_var_out[1]),
.R(1'b0));
endmodule |
module d_ff_en
(d_ff1_operation_out,
E,
operation_IBUF,
CLK,
\FSM_sequential_state_reg_reg[1] );
output d_ff1_operation_out;
input [0:0]E;
input operation_IBUF;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire d_ff1_operation_out;
wire operation_IBUF;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(operation_IBUF),
.Q(d_ff1_operation_out));
endmodule |
module d_ff_en_0
(d_ff3_sign_out,
\FSM_sequential_state_reg_reg[2] ,
Q,
CLK,
\FSM_sequential_state_reg_reg[1] );
output d_ff3_sign_out;
input [0:0]\FSM_sequential_state_reg_reg[2] ;
input [0:0]Q;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [0:0]\FSM_sequential_state_reg_reg[2] ;
wire [0:0]Q;
wire d_ff3_sign_out;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(Q),
.Q(d_ff3_sign_out));
endmodule |
module d_ff_en__parameterized0
(D,
d_ff1_operation_out,
Q,
\Q_reg[31] ,
E,
\shift_region_flag[1] ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]D;
input d_ff1_operation_out;
input [31:0]Q;
input [31:0]\Q_reg[31] ;
input [0:0]E;
input [1:0]\shift_region_flag[1] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [31:0]\Q_reg[31] ;
wire d_ff1_operation_out;
wire [1:0]d_ff1_shift_region_flag_out;
wire [1:0]\shift_region_flag[1] ;
LUT5 #(
.INIT(32'hACCACAAC))
\Q[0]_i_1__5
(.I0(Q[0]),
.I1(\Q_reg[31] [0]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[0]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[10]_i_1__5
(.I0(Q[10]),
.I1(\Q_reg[31] [10]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[10]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[11]_i_1__5
(.I0(Q[11]),
.I1(\Q_reg[31] [11]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[11]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[12]_i_1__5
(.I0(Q[12]),
.I1(\Q_reg[31] [12]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[12]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[13]_i_1__4
(.I0(Q[13]),
.I1(\Q_reg[31] [13]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[13]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[14]_i_1__5
(.I0(Q[14]),
.I1(\Q_reg[31] [14]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[14]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[15]_i_1__4
(.I0(Q[15]),
.I1(\Q_reg[31] [15]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[15]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[16]_i_1__4
(.I0(Q[16]),
.I1(\Q_reg[31] [16]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[16]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[17]_i_1__4
(.I0(Q[17]),
.I1(\Q_reg[31] [17]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[17]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[18]_i_1__4
(.I0(Q[18]),
.I1(\Q_reg[31] [18]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[18]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[19]_i_1__4
(.I0(Q[19]),
.I1(\Q_reg[31] [19]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[19]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[1]_i_1__5
(.I0(Q[1]),
.I1(\Q_reg[31] [1]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[1]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[20]_i_1__4
(.I0(Q[20]),
.I1(\Q_reg[31] [20]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[20]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[21]_i_1__5
(.I0(Q[21]),
.I1(\Q_reg[31] [21]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[21]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[22]_i_1__5
(.I0(Q[22]),
.I1(\Q_reg[31] [22]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[22]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[23]_i_1__4
(.I0(Q[23]),
.I1(\Q_reg[31] [23]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[23]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[24]_i_1__5
(.I0(Q[24]),
.I1(\Q_reg[31] [24]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[24]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[25]_i_1__5
(.I0(Q[25]),
.I1(\Q_reg[31] [25]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[25]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[26]_i_1__5
(.I0(Q[26]),
.I1(\Q_reg[31] [26]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[26]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[27]_i_1__4
(.I0(Q[27]),
.I1(\Q_reg[31] [27]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[27]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[28]_i_1__4
(.I0(Q[28]),
.I1(\Q_reg[31] [28]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[28]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[29]_i_1__5
(.I0(Q[29]),
.I1(\Q_reg[31] [29]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[29]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[2]_i_1__4
(.I0(Q[2]),
.I1(\Q_reg[31] [2]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[2]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[30]_i_1__4
(.I0(Q[30]),
.I1(\Q_reg[31] [30]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[30]));
LUT5 #(
.INIT(32'hE77181E8))
\Q[31]_i_2__2
(.I0(d_ff1_operation_out),
.I1(d_ff1_shift_region_flag_out[1]),
.I2(Q[31]),
.I3(d_ff1_shift_region_flag_out[0]),
.I4(\Q_reg[31] [31]),
.O(D[31]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[3]_i_1__4
(.I0(Q[3]),
.I1(\Q_reg[31] [3]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[3]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[4]_i_1__5
(.I0(Q[4]),
.I1(\Q_reg[31] [4]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[4]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[5]_i_1__4
(.I0(Q[5]),
.I1(\Q_reg[31] [5]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[5]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[6]_i_1__6
(.I0(Q[6]),
.I1(\Q_reg[31] [6]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[6]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[7]_i_1__4
(.I0(Q[7]),
.I1(\Q_reg[31] [7]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[7]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[8]_i_1__5
(.I0(Q[8]),
.I1(\Q_reg[31] [8]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[8]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[9]_i_1__5
(.I0(Q[9]),
.I1(\Q_reg[31] [9]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\shift_region_flag[1] [0]),
.Q(d_ff1_shift_region_flag_out[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\shift_region_flag[1] [1]),
.Q(d_ff1_shift_region_flag_out[1]));
endmodule |
module d_ff_en__parameterized1
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule |
module d_ff_en__parameterized10
(Q,
E,
\Q_reg[31]_0 ,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]\Q_reg[31]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [31:0]Q;
wire [31:0]\Q_reg[31]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [9]),
.Q(Q[9]));
endmodule |
module d_ff_en__parameterized11
(Q,
E,
D,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule |
module d_ff_en__parameterized2
(S,
Q,
\Q_reg[26]_0 ,
\temp_reg[3] ,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [3:0]S;
output [31:0]Q;
output [3:0]\Q_reg[26]_0 ;
input [3:0]\temp_reg[3] ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [3:0]\Q_reg[26]_0 ;
wire [3:0]S;
wire [3:0]\temp_reg[3] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_1
(.I0(Q[30]),
.O(S[3]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_2
(.I0(Q[29]),
.O(S[2]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_3
(.I0(Q[28]),
.O(S[1]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_4
(.I0(Q[27]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_1
(.I0(Q[26]),
.I1(\temp_reg[3] [3]),
.O(\Q_reg[26]_0 [3]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_2
(.I0(Q[25]),
.I1(\temp_reg[3] [2]),
.O(\Q_reg[26]_0 [2]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_3
(.I0(Q[24]),
.I1(\temp_reg[3] [1]),
.O(\Q_reg[26]_0 [1]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_4
(.I0(Q[23]),
.I1(\temp_reg[3] [0]),
.O(\Q_reg[26]_0 [0]));
endmodule |
module d_ff_en__parameterized3
(Q,
D,
\temp_reg[3] ,
E,
\temp_reg[3]_0 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
output [7:0]D;
input [3:0]\temp_reg[3] ;
input [0:0]E;
input [31:0]\temp_reg[3]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [7:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire \Q[26]_i_2_n_0 ;
wire \Q[26]_i_3_n_0 ;
wire \Q[26]_i_4_n_0 ;
wire \Q[26]_i_5_n_0 ;
wire \Q[30]_i_2_n_0 ;
wire \Q[30]_i_3_n_0 ;
wire \Q[30]_i_4_n_0 ;
wire \Q[30]_i_5_n_0 ;
wire \Q_reg[26]_i_1_n_0 ;
wire \Q_reg[26]_i_1_n_1 ;
wire \Q_reg[26]_i_1_n_2 ;
wire \Q_reg[26]_i_1_n_3 ;
wire \Q_reg[30]_i_1_n_1 ;
wire \Q_reg[30]_i_1_n_2 ;
wire \Q_reg[30]_i_1_n_3 ;
wire [3:0]\temp_reg[3] ;
wire [31:0]\temp_reg[3]_0 ;
wire [3:3]\NLW_Q_reg[30]_i_1_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h9))
\Q[26]_i_2
(.I0(Q[26]),
.I1(\temp_reg[3] [3]),
.O(\Q[26]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[26]_i_3
(.I0(Q[25]),
.I1(\temp_reg[3] [2]),
.O(\Q[26]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[26]_i_4
(.I0(Q[24]),
.I1(\temp_reg[3] [1]),
.O(\Q[26]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[26]_i_5
(.I0(Q[23]),
.I1(\temp_reg[3] [0]),
.O(\Q[26]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_2
(.I0(Q[30]),
.O(\Q[30]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_3
(.I0(Q[29]),
.O(\Q[30]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_4
(.I0(Q[28]),
.O(\Q[30]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_5
(.I0(Q[27]),
.O(\Q[30]_i_5_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [26]),
.Q(Q[26]));
CARRY4 \Q_reg[26]_i_1
(.CI(1'b0),
.CO({\Q_reg[26]_i_1_n_0 ,\Q_reg[26]_i_1_n_1 ,\Q_reg[26]_i_1_n_2 ,\Q_reg[26]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(Q[26:23]),
.O(D[3:0]),
.S({\Q[26]_i_2_n_0 ,\Q[26]_i_3_n_0 ,\Q[26]_i_4_n_0 ,\Q[26]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [30]),
.Q(Q[30]));
CARRY4 \Q_reg[30]_i_1
(.CI(\Q_reg[26]_i_1_n_0 ),
.CO({\NLW_Q_reg[30]_i_1_CO_UNCONNECTED [3],\Q_reg[30]_i_1_n_1 ,\Q_reg[30]_i_1_n_2 ,\Q_reg[30]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,Q[29:27]}),
.O(D[7:4]),
.S({\Q[30]_i_2_n_0 ,\Q[30]_i_3_n_0 ,\Q[30]_i_4_n_0 ,\Q[30]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [9]),
.Q(Q[9]));
endmodule |
module d_ff_en__parameterized4
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule |
module d_ff_en__parameterized5
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule |
module d_ff_en__parameterized6
(Q,
\FSM_sequential_state_reg_reg[2] ,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]\FSM_sequential_state_reg_reg[2] ;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [0:0]\FSM_sequential_state_reg_reg[2] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule |
module d_ff_en__parameterized7
(Q,
E,
CLK,
\FSM_sequential_state_reg_reg[1] ,
D);
output [20:0]Q;
input [0:0]E;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [19:0]D;
wire CLK;
wire [19:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [20:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(1'b1),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
endmodule |
module d_ff_en__parameterized8
(Q,
E,
\Q_reg[31]_0 ,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]\Q_reg[31]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [31:0]Q;
wire [31:0]\Q_reg[31]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [9]),
.Q(Q[9]));
endmodule |
module d_ff_en__parameterized9
(Q,
E,
\Q_reg[31]_0 ,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]\Q_reg[31]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [31:0]Q;
wire [31:0]\Q_reg[31]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [9]),
.Q(Q[9]));
endmodule |
module sgn_result
(D,
\Q_reg[30] ,
Q,
intAS,
CO,
\Q_reg[31] );
output [0:0]D;
input [0:0]\Q_reg[30] ;
input [0:0]Q;
input intAS;
input [0:0]CO;
input [0:0]\Q_reg[31] ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]Q;
wire [0:0]\Q_reg[30] ;
wire [0:0]\Q_reg[31] ;
wire intAS;
LUT5 #(
.INIT(32'hFF3C0014))
sgn_result_o
(.I0(\Q_reg[30] ),
.I1(Q),
.I2(intAS),
.I3(CO),
.I4(\Q_reg[31] ),
.O(D));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hvl__buf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hvl__buf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule |
module sky130_fd_sc_ls__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule |
module cpu(
input wire clk);
parameter NMEM = 20; // number in instruction memory
parameter IM_DATA = "im_data.txt";
// {{{ diagnostic outputs
initial begin
if (`DEBUG_CPU_STAGES) begin
$display("if_pc, if_instr, id_regrs, id_regrt, ex_alua, ex_alub, ex_aluctl, mem_memdata, mem_memread, mem_memwrite, wb_regdata, wb_regwrite");
$monitor("%x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x",
pc, /* if_pc */
inst, /* if_instr */
data1, /* id_regrs */
data2, /* id_regrt */
data1_s3, /* data1_s3 */
alusrc_data2, /* alusrc_data2 */
aluctl, /* ex_aluctl */
data2_s4, /* mem_memdata */
memread_s4, /* mem_memread */
memwrite_s4, /* mem_memwrite */
wrdata_s5, /* wb_regdata */
regwrite_s5 /* wb_regwrite */
);
end
end
// }}}
// {{{ flush control
reg flush_s1, flush_s2, flush_s3;
always @(*) begin
flush_s1 <= 1'b0;
flush_s2 <= 1'b0;
flush_s3 <= 1'b0;
if (pcsrc) begin
flush_s1 <= 1'b1;
flush_s2 <= 1'b1;
flush_s3 <= 1'b1;
end
end
// }}}
// {{{ stage 1, IF (fetch)
reg [31:0] pc;
initial begin
pc <= 32'd0;
end
wire [31:0] pc4; // PC + 4
assign pc4 = pc + 4;
always @(posedge clk) begin
if (stall_s1_s2)
pc <= pc;
else if (pcsrc == 1'b1)
pc <= baddr_s4;
else
pc <= pc4;
end
// pass PC + 4 to stage 2
wire [31:0] pc4_s2;
regr #(.N(32)) regr_pc4_s2(.clk(clk),
.hold(stall_s1_s2), .clear(flush_s1),
.in(pc4), .out(pc4_s2));
// instruction memory
wire [31:0] inst;
wire [31:0] inst_s2;
im #(.NMEM(NMEM), .IM_DATA(IM_DATA))
im1(.clk(clk), .addr(pc), .data(inst));
regr #(.N(32)) regr_im_s2(.clk(clk),
.hold(stall_s1_s2), .clear(flush_s1),
.in(inst), .out(inst_s2));
// }}}
// {{{ stage 2, ID (decode)
// decode instruction
wire [5:0] opcode;
wire [4:0] rs;
wire [4:0] rt;
wire [4:0] rd;
wire [15:0] imm;
wire [4:0] shamt;
wire [25:0] jimm; // jump, immediate
wire [31:0] seimm; // sign extended immediate
//
assign opcode = inst_s2[31:26];
assign rs = inst_s2[25:21];
assign rt = inst_s2[20:16];
assign rd = inst_s2[15:11];
assign imm = inst_s2[15:0];
assign shamt = inst_s2[10:6];
assign jimm = inst_s2[25:0];
assign seimm = {{16{inst_s2[15]}}, inst_s2[15:0]};
// register memory
wire [31:0] data1, data2;
regm regm1(.clk(clk), .read1(rs), .read2(rt),
.data1(data1), .data2(data2),
.regwrite(regwrite_s5), .wrreg(wrreg_s5),
.wrdata(wrdata_s5));
// pass rs to stage 3 (for forwarding)
wire [4:0] rs_s3;
regr #(.N(5)) regr_s2_rs(.clk(clk), .clear(1'b0), .hold(stall_s1_s2),
.in(rs), .out(rs_s3));
// transfer register data to stage 3
wire [31:0] data1_s3, data2_s3;
regr #(.N(64)) reg_s2_mem(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in({data1, data2}),
.out({data1_s3, data2_s3}));
// transfer seimm, rt, and rd to stage 3
wire [31:0] seimm_s3;
wire [4:0] rt_s3;
wire [4:0] rd_s3;
regr #(.N(32)) reg_s2_seimm(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in(seimm), .out(seimm_s3));
regr #(.N(10)) reg_s2_rt_rd(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in({rt, rd}), .out({rt_s3, rd_s3}));
// transfer PC + 4 to stage 3
wire [31:0] pc4_s3;
regr #(.N(32)) reg_pc4_s2(.clk(clk), .clear(1'b0), .hold(stall_s1_s2),
.in(pc4_s2), .out(pc4_s3));
// control (opcode -> ...)
wire regdst;
wire [1:0] branch_s2;
wire memread;
wire memwrite;
wire memtoreg;
wire [1:0] aluop;
wire regwrite;
wire alusrc;
//
control ctl1(.opcode(opcode), .regdst(regdst),
.branch(branch_s2), .memread(memread),
.memtoreg(memtoreg), .aluop(aluop),
.memwrite(memwrite), .alusrc(alusrc),
.regwrite(regwrite));
// shift left, seimm
wire [31:0] seimm_sl2;
assign seimm_sl2 = {seimm[29:0], 2'b0}; // shift left 2 bits
// branch address
wire [31:0] baddr_s2;
assign baddr_s2 = pc4_s2 + seimm_sl2;
// transfer the control signals to stage 3
wire regdst_s3;
wire memread_s3;
wire memwrite_s3;
wire memtoreg_s3;
wire [1:0] aluop_s3;
wire regwrite_s3;
wire alusrc_s3;
// A bubble is inserted by setting all the control signals
// to zero (stall_s1_s2).
regr #(.N(8)) reg_s2_control(.clk(clk), .clear(stall_s1_s2), .hold(1'b0),
.in({regdst, memread, memwrite,
memtoreg, aluop, regwrite, alusrc}),
.out({regdst_s3, memread_s3, memwrite_s3,
memtoreg_s3, aluop_s3, regwrite_s3, alusrc_s3}));
wire [1:0] branch_s3;
regr #(.N(2)) branch_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(branch_s2), .out(branch_s3));
wire [31:0] baddr_s3;
regr #(.N(32)) baddr_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(baddr_s2), .out(baddr_s3));
// }}}
// {{{ stage 3, EX (execute)
// pass through some control signals to stage 4
wire regwrite_s4;
wire memtoreg_s4;
wire memread_s4;
wire memwrite_s4;
regr #(.N(4)) reg_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in({regwrite_s3, memtoreg_s3, memread_s3,
memwrite_s3}),
.out({regwrite_s4, memtoreg_s4, memread_s4,
memwrite_s4}));
// ALU
// second ALU input can come from an immediate value or data
wire [31:0] alusrc_data2;
assign alusrc_data2 = (alusrc_s3) ? seimm_s3 : fw_data2_s3;
// ALU control
wire [3:0] aluctl;
wire [5:0] funct;
assign funct = seimm_s3[5:0];
alu_control alu_ctl1(.funct(funct), .aluop(aluop_s3), .aluctl(aluctl));
// ALU
wire [31:0] alurslt;
reg [31:0] fw_data1_s3;
always @(*)
case (forward_a)
2'd1: fw_data1_s3 = alurslt_s4;
2'd2: fw_data1_s3 = wrdata_s5;
default: fw_data1_s3 = data1_s3;
endcase
wire zero_s3;
alu alu1(.ctl(aluctl), .a(fw_data1_s3), .b(alusrc_data2), .out(alurslt),
.zero(zero_s3));
wire zero_s4;
regr #(.N(1)) reg_zero_s3_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(zero_s3), .out(zero_s4));
// pass ALU result and zero to stage 4
wire [31:0] alurslt_s4;
regr #(.N(32)) reg_alurslt(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in({alurslt}),
.out({alurslt_s4}));
// pass data2 to stage 4
wire [31:0] data2_s4;
reg [31:0] fw_data2_s3;
always @(*)
case (forward_b)
2'd1: fw_data2_s3 = alurslt_s4;
2'd2: fw_data2_s3 = wrdata_s5;
default: fw_data2_s3 = data2_s3;
endcase
regr #(.N(32)) reg_data2_s3(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(fw_data2_s3), .out(data2_s4));
// write register
wire [4:0] wrreg;
wire [4:0] wrreg_s4;
assign wrreg = (regdst_s3) ? rd_s3 : rt_s3;
// pass to stage 4
regr #(.N(5)) reg_wrreg(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(wrreg), .out(wrreg_s4));
wire [1:0] branch_s4;
regr #(.N(2)) branch_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(branch_s3), .out(branch_s4));
wire [31:0] baddr_s4;
regr #(.N(32)) baddr_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(baddr_s3), .out(baddr_s4));
// }}}
// {{{ stage 4, MEM (memory)
// pass regwrite and memtoreg to stage 5
wire regwrite_s5;
wire memtoreg_s5;
regr #(.N(2)) reg_regwrite_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in({regwrite_s4, memtoreg_s4}),
.out({regwrite_s5, memtoreg_s5}));
// data memory
wire [31:0] rdata;
dm dm1(.clk(clk), .addr(alurslt_s4[8:2]), .rd(memread_s4), .wr(memwrite_s4),
.wdata(data2_s4), .rdata(rdata));
// pass read data to stage 5
wire [31:0] rdata_s5;
regr #(.N(32)) reg_rdata_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(rdata),
.out(rdata_s5));
// pass alurslt to stage 5
wire [31:0] alurslt_s5;
regr #(.N(32)) reg_alurslt_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(alurslt_s4),
.out(alurslt_s5));
// pass wrreg to stage 5
wire [4:0] wrreg_s5;
regr #(.N(5)) reg_wrreg_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(wrreg_s4),
.out(wrreg_s5));
// branch
reg pcsrc;
always @(*) begin
case (1'b1)
branch_s4[`BRANCH_BEQ]: pcsrc <= zero_s4;
branch_s4[`BRANCH_BNE]: pcsrc <= ~(zero_s4);
default: pcsrc <= 1'b0;
endcase
end
// }}}
// {{{ stage 5, WB (write back)
wire [31:0] wrdata_s5;
assign wrdata_s5 = (memtoreg_s5 == 1'b1) ? rdata_s5 : alurslt_s5;
// }}}
// {{{ forwarding
// stage 3 (MEM) -> stage 2 (EX)
// stage 4 (WB) -> stage 2 (EX)
reg [1:0] forward_a;
reg [1:0] forward_b;
always @(*) begin
// If the previous instruction (stage 4) would write,
// and it is a value we want to read (stage 3), forward it.
// data1 input to ALU
if ((regwrite_s4 == 1'b1) && (wrreg_s4 == rs_s3)) begin
forward_a <= 2'd1; // stage 4
end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rs_s3)) begin
forward_a <= 2'd2; // stage 5
end else
forward_a <= 2'd0; // no forwarding
// data2 input to ALU
if ((regwrite_s4 == 1'b1) & (wrreg_s4 == rt_s3)) begin
forward_b <= 2'd1; // stage 5
end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rt_s3)) begin
forward_b <= 2'd2; // stage 5
end else
forward_b <= 2'd0; // no forwarding
end
// }}}
// {{{ load use data hazard detection, signal stall
/* If an operation in stage 4 (MEM) loads from memory (e.g. lw)
* and the operation in stage 3 (EX) depends on this value,
* a stall must be performed. The memory read cannot
* be forwarded because memory access is too slow. It can
* be forwarded from stage 5 (WB) after a stall.
*
* lw $1, 16($10) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $1, 32($12) ; I-type, rt_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $2, 32($1) ; I-type, rt_s2 = $2, rs_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* add $2, $1, $1 ; R-type, rs_s2 = $1, rt_s2 = $1, memread_s2 = 0
*/
reg stall_s1_s2;
always @(*) begin
if (memread_s3 == 1'b1 && ((rt == rt_s3) || (rs == rt_s3)) ) begin
stall_s1_s2 <= 1'b1; // perform a stall
end else
stall_s1_s2 <= 1'b0; // no stall
end
// }}}
endmodule |
module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
endmodule |
module async_counter_30(clk, count);
input clk;
output [29:0] count;
reg [14:0] count_a;
reg [14:0] count_b;
initial count_a = 15'b0;
initial count_b = 15'b0;
always @(negedge clk)
count_a <= count_a + 1'b1;
always @(negedge count_a[14])
count_b <= count_b + 1'b1;
assign count = {count_b, count_a};
endmodule |
module COMMAND_PAGE (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [7:0] rdaddress;
input [8:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule |
module sn7402 (P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14);
output reg P1, P4, P10, P13;
input P2, P3, P5, P6, P8, P9, P11, P12, P7, P14;
always @(P2, P3, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P1 = ~(P2 | P3);
end
end
always @(P5, P6, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P4 = ~(P5 | P6);
end
end
always @(P8, P9, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P10 = ~(P8 | P9);
end
end
always @(P11, P12, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P13 = ~(P11 | P12);
end
end
endmodule |
module sky130_fd_io__top_power_lvc_wpad (
//# {{data|Data Signals}}
inout P_PAD ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
//# {{power|Power}}
inout BDY2_B2B ,
inout VSWITCH ,
inout P_CORE ,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout DRN_LVC1 ,
inout DRN_LVC2 ,
inout OGC_LVC ,
inout SRC_BDY_LVC1,
inout SRC_BDY_LVC2,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule |
module MultiplexerTest;
wire [2:0] w_data;
wire w_error;
reg [3:0] r_select;
reg r_disable_error_check;
reg r_error;
Multiplexer4 #(.width(3)) mux(
.i_data0 (3'b001 ),
.i_data1 (3'b010 ),
.i_data2 (3'b011 ),
.i_data3 (3'b100 ),
.i_select0(r_select[0]),
.i_select1(r_select[1]),
.i_select2(r_select[2]),
.i_select3(r_select[3]),
.o_data (w_data ),
.o_error (w_error ));
always @ (w_error or r_error) begin
if (w_error & !r_disable_error_check) begin
$display("unexpected error");
end
if (r_error) begin
$display("wrong data is selected");
end
end
initial begin
//$dumpfile("Multiplexer.vcd");
//$dumpvars(0, mux);
r_disable_error_check <= 1'b0;
r_error <= 1'b0;
r_select <= 4'b0001;
#1
r_error <= w_data != 3'b001;
#1
r_select <= 4'b0010;
#1
r_error <= w_data != 3'b010;
#1
r_select <= 4'b0100;
#1
r_error <= w_data != 3'b011;
#1
r_select <= 4'b1000;
#1
r_error <= w_data != 3'b100;
#1
r_disable_error_check <= 1'b1;
#1
r_select <= 4'b0011;
#1
r_error <= w_error != 1'b1;
#1
r_select <= 4'b0000;
#1
r_error <= w_error != 1'b1;
#1
$finish;
end
endmodule |
module sky130_fd_sc_hd__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule |
module sky130_fd_sc_ms__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_lp__a41o_lp (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__a41o_lp (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule |
module ex(
input wire rst,
//Ë͵½Ö´Ðн׶εÄÐÅÏ¢
input wire[`AluOpBus] aluop_i,
input wire[`AluSelBus] alusel_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] inst_i,
input wire[31:0] excepttype_i,
input wire[`RegBus] current_inst_address_i,
//HI¡¢LO¼Ä´æÆ÷µÄÖµ
input wire[`RegBus] hi_i,
input wire[`RegBus] lo_i,
//»Øд½×¶ÎµÄÖ¸ÁîÊÇ·ñҪдHI¡¢LO£¬ÓÃÓÚ¼ì²âHI¡¢LOµÄÊý¾ÝÏà¹Ø
input wire[`RegBus] wb_hi_i,
input wire[`RegBus] wb_lo_i,
input wire wb_whilo_i,
//·Ã´æ½×¶ÎµÄÖ¸ÁîÊÇ·ñҪдHI¡¢LO£¬ÓÃÓÚ¼ì²âHI¡¢LOµÄÊý¾ÝÏà¹Ø
input wire[`RegBus] mem_hi_i,
input wire[`RegBus] mem_lo_i,
input wire mem_whilo_i,
input wire[`DoubleRegBus] hilo_temp_i,
input wire[1:0] cnt_i,
//Óë³ý·¨Ä£¿éÏàÁ¬
input wire[`DoubleRegBus] div_result_i,
input wire div_ready_i,
//ÊÇ·ñתÒÆ¡¢ÒÔ¼°link address
input wire[`RegBus] link_address_i,
input wire is_in_delayslot_i,
//·Ã´æ½×¶ÎµÄÖ¸ÁîÊÇ·ñҪдCP0£¬ÓÃÀ´¼ì²âÊý¾ÝÏà¹Ø
input wire mem_cp0_reg_we,
input wire[4:0] mem_cp0_reg_write_addr,
input wire[`RegBus] mem_cp0_reg_data,
//»Øд½×¶ÎµÄÖ¸ÁîÊÇ·ñҪдCP0£¬ÓÃÀ´¼ì²âÊý¾ÝÏà¹Ø
input wire wb_cp0_reg_we,
input wire[4:0] wb_cp0_reg_write_addr,
input wire[`RegBus] wb_cp0_reg_data,
//ÓëCP0ÏàÁ¬£¬¶ÁÈ¡ÆäÖÐCP0¼Ä´æÆ÷µÄÖµ
input wire[`RegBus] cp0_reg_data_i,
output reg[4:0] cp0_reg_read_addr_o,
//ÏòÏÂÒ»Á÷Ë®¼¶´«µÝ£¬ÓÃÓÚдCP0ÖеļĴæÆ÷
output reg cp0_reg_we_o,
output reg[4:0] cp0_reg_write_addr_o,
output reg[`RegBus] cp0_reg_data_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o,
output reg[`RegBus] hi_o,
output reg[`RegBus] lo_o,
output reg whilo_o,
output reg[`DoubleRegBus] hilo_temp_o,
output reg[1:0] cnt_o,
output reg[`RegBus] div_opdata1_o,
output reg[`RegBus] div_opdata2_o,
output reg div_start_o,
output reg signed_div_o,
//ÏÂÃæÐÂÔöµÄ¼¸¸öÊä³öÊÇΪ¼ÓÔØ¡¢´æ´¢Ö¸Áî×¼±¸µÄ
output wire[`AluOpBus] aluop_o,
output wire[`RegBus] mem_addr_o,
output wire[`RegBus] reg2_o,
output wire[31:0] excepttype_o,
output wire is_in_delayslot_o,
output wire[`RegBus] current_inst_address_o,
output reg stallreq
);
reg[`RegBus] logicout;
reg[`RegBus] shiftres;
reg[`RegBus] moveres;
reg[`RegBus] arithmeticres;
reg[`DoubleRegBus] mulres;
reg[`RegBus] HI;
reg[`RegBus] LO;
wire[`RegBus] reg2_i_mux;
wire[`RegBus] reg1_i_not;
wire[`RegBus] result_sum;
wire ov_sum;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
wire[`RegBus] opdata1_mult;
wire[`RegBus] opdata2_mult;
wire[`DoubleRegBus] hilo_temp;
reg[`DoubleRegBus] hilo_temp1;
reg stallreq_for_madd_msub;
reg stallreq_for_div;
reg trapassert;
reg breassert;
//aluop_o´«µÝµ½·Ã´æ½×¶Î£¬ÓÃÓÚ¼ÓÔØ¡¢´æ´¢Ö¸Áî
assign aluop_o = aluop_i;
//mem_addr´«µÝµ½·Ã´æ½×¶Î£¬ÊǼÓÔØ¡¢´æ´¢Ö¸Áî¶ÔÓ¦µÄ´æ´¢Æ÷µØÖ·
assign mem_addr_o = reg1_i + {{16{inst_i[15]}},inst_i[15:0]};
//½«Á½¸ö²Ù×÷ÊýÒ²´«µÝµ½·Ã´æ½×¶Î£¬Ò²ÊÇΪ¼ÇÔØ¡¢´æ´¢Ö¸Áî×¼±¸µÄ
assign reg2_o = reg2_i;
assign excepttype_o = {excepttype_i[31:12],breassert,trapassert,excepttype_i[9:8],8'h00};
assign is_in_delayslot_o = is_in_delayslot_i;
assign current_inst_address_o = current_inst_address_i;
always @ (*) begin
if(rst == `RstEnable) begin
logicout <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_NOR_OP: begin
logicout <= ~(reg1_i |reg2_i);
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
default: begin
logicout <= `ZeroWord;
end
endcase
end //if
end //always
always @ (*) begin
if(rst == `RstEnable) begin
shiftres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL_OP: begin
shiftres <= reg2_i << reg1_i[4:0] ;
end
`EXE_SRL_OP: begin
shiftres <= reg2_i >> reg1_i[4:0];
end
`EXE_SRA_OP: begin
shiftres <= ({32{reg2_i[31]}} << (6'd32-{1'b0, reg1_i[4:0]}))
| reg2_i >> reg1_i[4:0];
end
default: begin
shiftres <= `ZeroWord;
end
endcase
end //if
end //always
assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) || (aluop_i == `EXE_SUBU_OP) ||
(aluop_i == `EXE_SLT_OP)|| (aluop_i == `EXE_TLT_OP) ||
(aluop_i == `EXE_TLTI_OP) || (aluop_i == `EXE_TGE_OP) ||
(aluop_i == `EXE_TGEI_OP))
? (~reg2_i)+1 : reg2_i;
assign result_sum = reg1_i + reg2_i_mux;
/*assign ov_sum = ((!reg1_i[31] && !reg2_i_mux[31]) && result_sum[31]) ||
((reg1_i[31] && reg2_i_mux[31]) && (!result_sum[31])); */
assign reg1_lt_reg2 = ((aluop_i == `EXE_SLT_OP) || (aluop_i == `EXE_TLT_OP) ||
(aluop_i == `EXE_TLTI_OP) || (aluop_i == `EXE_TGE_OP) ||
(aluop_i == `EXE_TGEI_OP)) ?
((reg1_i[31] && !reg2_i[31]) ||
(!reg1_i[31] && !reg2_i[31] && result_sum[31])||
(reg1_i[31] && reg2_i[31] && result_sum[31]))
: (reg1_i < reg2_i);
assign reg1_i_not = ~reg1_i;
always @ (*) begin
if(rst == `RstEnable) begin
arithmeticres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLT_OP, `EXE_SLTU_OP: begin
arithmeticres <= reg1_lt_reg2 ;
end
`EXE_ADD_OP, `EXE_ADDU_OP, `EXE_ADDI_OP, `EXE_ADDIU_OP: begin
arithmeticres <= result_sum;
end
`EXE_SUB_OP, `EXE_SUBU_OP: begin
arithmeticres <= result_sum;
end
`EXE_CLZ_OP: begin
arithmeticres <= reg1_i[31] ? 0 : reg1_i[30] ? 1 : reg1_i[29] ? 2 :
reg1_i[28] ? 3 : reg1_i[27] ? 4 : reg1_i[26] ? 5 :
reg1_i[25] ? 6 : reg1_i[24] ? 7 : reg1_i[23] ? 8 :
reg1_i[22] ? 9 : reg1_i[21] ? 10 : reg1_i[20] ? 11 :
reg1_i[19] ? 12 : reg1_i[18] ? 13 : reg1_i[17] ? 14 :
reg1_i[16] ? 15 : reg1_i[15] ? 16 : reg1_i[14] ? 17 :
reg1_i[13] ? 18 : reg1_i[12] ? 19 : reg1_i[11] ? 20 :
reg1_i[10] ? 21 : reg1_i[9] ? 22 : reg1_i[8] ? 23 :
reg1_i[7] ? 24 : reg1_i[6] ? 25 : reg1_i[5] ? 26 :
reg1_i[4] ? 27 : reg1_i[3] ? 28 : reg1_i[2] ? 29 :
reg1_i[1] ? 30 : reg1_i[0] ? 31 : 32 ;
end
`EXE_CLO_OP: begin
arithmeticres <= (reg1_i_not[31] ? 0 : reg1_i_not[30] ? 1 : reg1_i_not[29] ? 2 :
reg1_i_not[28] ? 3 : reg1_i_not[27] ? 4 : reg1_i_not[26] ? 5 :
reg1_i_not[25] ? 6 : reg1_i_not[24] ? 7 : reg1_i_not[23] ? 8 :
reg1_i_not[22] ? 9 : reg1_i_not[21] ? 10 : reg1_i_not[20] ? 11 :
reg1_i_not[19] ? 12 : reg1_i_not[18] ? 13 : reg1_i_not[17] ? 14 :
reg1_i_not[16] ? 15 : reg1_i_not[15] ? 16 : reg1_i_not[14] ? 17 :
reg1_i_not[13] ? 18 : reg1_i_not[12] ? 19 : reg1_i_not[11] ? 20 :
reg1_i_not[10] ? 21 : reg1_i_not[9] ? 22 : reg1_i_not[8] ? 23 :
reg1_i_not[7] ? 24 : reg1_i_not[6] ? 25 : reg1_i_not[5] ? 26 :
reg1_i_not[4] ? 27 : reg1_i_not[3] ? 28 : reg1_i_not[2] ? 29 :
reg1_i_not[1] ? 30 : reg1_i_not[0] ? 31 : 32) ;
end
default: begin
arithmeticres <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
trapassert <= `TrapNotAssert;
end else begin
trapassert <= `TrapNotAssert;
case (aluop_i)
`EXE_TEQ_OP, `EXE_TEQI_OP: begin
if( reg1_i == reg2_i ) begin
trapassert <= `TrapAssert;
end
end
`EXE_TGE_OP, `EXE_TGEI_OP, `EXE_TGEIU_OP, `EXE_TGEU_OP: begin
if( ~reg1_lt_reg2 ) begin
trapassert <= `TrapAssert;
end
end
`EXE_TLT_OP, `EXE_TLTI_OP, `EXE_TLTIU_OP, `EXE_TLTU_OP: begin
if( reg1_lt_reg2 ) begin
trapassert <= `TrapAssert;
end
end
`EXE_TNE_OP, `EXE_TNEI_OP: begin
if( reg1_i != reg2_i ) begin
trapassert <= `TrapAssert;
end
end
default: begin
trapassert <= `TrapNotAssert;
end
endcase
end
end
always@ (*) begin
if(aluop_i == `EXE_BREAK_OP) begin
breassert <= 1'b1;
end else begin
breassert <= 1'b0;
end
end
//È¡µÃ³Ë·¨²Ù×÷µÄ²Ù×÷Êý£¬Èç¹ûÊÇÓзûºÅ³ý·¨ÇÒ²Ù×÷ÊýÊǸºÊý£¬ÄÇôȡ·´¼ÓÒ»
assign opdata1_mult = (((aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP) ||
(aluop_i == `EXE_MADD_OP) || (aluop_i == `EXE_MSUB_OP))
&& (reg1_i[31] == 1'b1)) ? (~reg1_i + 1) : reg1_i;
assign opdata2_mult = (((aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP) ||
(aluop_i == `EXE_MADD_OP) || (aluop_i == `EXE_MSUB_OP))
&& (reg2_i[31] == 1'b1)) ? (~reg2_i + 1) : reg2_i;
assign hilo_temp = opdata1_mult * opdata2_mult;
always @ (*) begin
if(rst == `RstEnable) begin
mulres <= {`ZeroWord,`ZeroWord};
end else if ((aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MUL_OP) ||
(aluop_i == `EXE_MADD_OP) || (aluop_i == `EXE_MSUB_OP))begin
if(reg1_i[31] ^ reg2_i[31] == 1'b1) begin
mulres <= ~hilo_temp + 1;
end else begin
mulres <= hilo_temp;
end
end else begin
mulres <= hilo_temp;
end
end
//µÃµ½×îеÄHI¡¢LO¼Ä´æÆ÷µÄÖµ£¬´Ë´¦Òª½â¾öÖ¸ÁîÊý¾ÝÏà¹ØÎÊÌâ
always @ (*) begin
if(rst == `RstEnable) begin
{HI,LO} <= {`ZeroWord,`ZeroWord};
end else if(mem_whilo_i == `WriteEnable) begin
{HI,LO} <= {mem_hi_i,mem_lo_i};
end else if(wb_whilo_i == `WriteEnable) begin
{HI,LO} <= {wb_hi_i,wb_lo_i};
end else begin
{HI,LO} <= {hi_i,lo_i};
end
end
always @ (*) begin
stallreq = stallreq_for_madd_msub || stallreq_for_div;
end
//MADD¡¢MADDU¡¢MSUB¡¢MSUBUÖ¸Áî
always @ (*) begin
if(rst == `RstEnable) begin
hilo_temp_o <= {`ZeroWord,`ZeroWord};
cnt_o <= 2'b00;
stallreq_for_madd_msub <= `NoStop;
end else begin
case (aluop_i)
`EXE_MADD_OP, `EXE_MADDU_OP: begin
if(cnt_i == 2'b00) begin
hilo_temp_o <= mulres;
cnt_o <= 2'b01;
stallreq_for_madd_msub <= `Stop;
hilo_temp1 <= {`ZeroWord,`ZeroWord};
end else if(cnt_i == 2'b01) begin
hilo_temp_o <= {`ZeroWord,`ZeroWord};
cnt_o <= 2'b10;
hilo_temp1 <= hilo_temp_i + {HI,LO};
stallreq_for_madd_msub <= `NoStop;
end
end
`EXE_MSUB_OP, `EXE_MSUBU_OP: begin
if(cnt_i == 2'b00) begin
hilo_temp_o <= ~mulres + 1 ;
cnt_o <= 2'b01;
stallreq_for_madd_msub <= `Stop;
end else if(cnt_i == 2'b01)begin
hilo_temp_o <= {`ZeroWord,`ZeroWord};
cnt_o <= 2'b10;
hilo_temp1 <= hilo_temp_i + {HI,LO};
stallreq_for_madd_msub <= `NoStop;
end
end
default: begin
hilo_temp_o <= {`ZeroWord,`ZeroWord};
cnt_o <= 2'b00;
stallreq_for_madd_msub <= `NoStop;
end
endcase
end
end
//DIV¡¢DIVUÖ¸Áî
always @ (*) begin
if(rst == `RstEnable) begin
stallreq_for_div <= `NoStop;
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
end else begin
stallreq_for_div <= `NoStop;
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
case (aluop_i)
`EXE_DIV_OP: begin
if(div_ready_i == `DivResultNotReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivStart;
signed_div_o <= 1'b1;
stallreq_for_div <= `Stop;
end else if(div_ready_i == `DivResultReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivStop;
signed_div_o <= 1'b1;
stallreq_for_div <= `NoStop;
end else begin
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
stallreq_for_div <= `NoStop;
end
end
`EXE_DIVU_OP: begin
if(div_ready_i == `DivResultNotReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivStart;
signed_div_o <= 1'b0;
stallreq_for_div <= `Stop;
end else if(div_ready_i == `DivResultReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
stallreq_for_div <= `NoStop;
end else begin
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
stallreq_for_div <= `NoStop;
end
end
default: begin
end
endcase
end
end
//MFHI¡¢MFLO¡¢MOVN¡¢MOVZÖ¸Áî
always @ (*) begin
if(rst == `RstEnable) begin
moveres <= `ZeroWord;
end else begin
moveres <= `ZeroWord;
case (aluop_i)
`EXE_MFHI_OP: begin
moveres <= HI;
end
`EXE_MFLO_OP: begin
moveres <= LO;
end
`EXE_MOVZ_OP: begin
moveres <= reg1_i;
end
`EXE_MOVN_OP: begin
moveres <= reg1_i;
end
`EXE_MFC0_OP: begin
cp0_reg_read_addr_o <= inst_i[15:11];
moveres <= cp0_reg_data_i;
if( mem_cp0_reg_we == `WriteEnable &&
mem_cp0_reg_write_addr == inst_i[15:11] ) begin
moveres <= mem_cp0_reg_data;
end else if( wb_cp0_reg_we == `WriteEnable &&
wb_cp0_reg_write_addr == inst_i[15:11] ) begin
moveres <= wb_cp0_reg_data;
end
end
default : begin
end
endcase
end
end
always @ (*) begin
wd_o <= wd_i;
wreg_o <= wreg_i;
case ( alusel_i )
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
`EXE_RES_SHIFT: begin
wdata_o <= shiftres;
end
`EXE_RES_MOVE: begin
wdata_o <= moveres;
end
`EXE_RES_ARITHMETIC: begin
wdata_o <= arithmeticres;
end
`EXE_RES_MUL: begin
wdata_o <= mulres[31:0];
end
`EXE_RES_JUMP_BRANCH: begin
wdata_o <= link_address_i;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
always @ (*) begin
if(rst == `RstEnable) begin
whilo_o <= `WriteDisable;
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end else if((aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MULTU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= mulres[63:32];
lo_o <= mulres[31:0];
end else if((aluop_i == `EXE_MADD_OP) || (aluop_i == `EXE_MADDU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= hilo_temp1[63:32];
lo_o <= hilo_temp1[31:0];
end else if((aluop_i == `EXE_MSUB_OP) || (aluop_i == `EXE_MSUBU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= hilo_temp1[63:32];
lo_o <= hilo_temp1[31:0];
end else if((aluop_i == `EXE_DIV_OP) || (aluop_i == `EXE_DIVU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= div_result_i[63:32];
lo_o <= div_result_i[31:0];
end else if(aluop_i == `EXE_MTHI_OP) begin
whilo_o <= `WriteEnable;
hi_o <= reg1_i;
lo_o <= LO;
end else if(aluop_i == `EXE_MTLO_OP) begin
whilo_o <= `WriteEnable;
hi_o <= HI;
lo_o <= reg1_i;
end else begin
whilo_o <= `WriteDisable;
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
cp0_reg_write_addr_o <= 5'b00000;
cp0_reg_we_o <= `WriteDisable;
cp0_reg_data_o <= `ZeroWord;
end else if(aluop_i == `EXE_MTC0_OP) begin
cp0_reg_write_addr_o <= inst_i[15:11];
cp0_reg_we_o <= `WriteEnable;
cp0_reg_data_o <= reg1_i;
end else begin
cp0_reg_write_addr_o <= 5'b00000;
cp0_reg_we_o <= `WriteDisable;
cp0_reg_data_o <= `ZeroWord;
end
end
endmodule |
module pcie_tlp (
// System
input pcie_clk,
input sys_rst,
// Management
input [6:0] rx_bar_hit,
input [7:0] bus_num,
input [4:0] dev_num,
input [2:0] func_num,
// Receive
input rx_st,
input rx_end,
input [15:0] rx_data,
input rx_malf,
// Transmit
output reg tx_req = 1'b0,
input tx_rdy,
output reg tx_st = 1'b0,
output tx_end,
output reg [15:0] tx_data,
input [8:0] tx_ca_ph,
input [12:0] tx_ca_pd,
input [8:0] tx_ca_nph,
input [12:0] tx_ca_npd,
input [8:0] tx_ca_cplh,
input [12:0] tx_ca_cpld,
input tx_ca_p_recheck,
input tx_ca_cpl_recheck,
// Receive credits
output reg [7:0] pd_num = 8'h0,
output reg ph_cr = 1'b0,
output reg pd_cr = 1'b0,
output reg nph_cr = 1'b0,
output reg npd_cr = 1'b0,
// Master FIFO
output reg mst_rd_en,
input mst_empty,
input [17:0] mst_dout,
output reg mst_wr_en,
input mst_full,
output reg [17:0] mst_din,
// Slave BUS
output reg [6:0] slv_bar_i,
output reg slv_ce_i,
output reg slv_we_i,
output reg [19:1] slv_adr_i,
output reg [15:0] slv_dat_i,
output reg [1:0] slv_sel_i,
input [15:0] slv_dat_o,
// Slave FIFO
output reg slv_rd_en,
input slv_empty,
input [17:0] slv_dout,
output reg slv_wr_en,
input slv_full,
output reg [17:0] slv_din,
// LED and Switches
input [7:0] dipsw,
output [7:0] led,
output [13:0] segled,
input btn
);
parameter [2:0]
TLP_MR = 3'h0,
TLP_MRdLk= 3'h1,
TLP_IO = 3'h2,
TLP_Cfg0 = 3'h3,
TLP_Cfg1 = 3'h4,
TLP_Msg = 3'h5,
TLP_Cpl = 3'h6,
TLP_CplLk= 3'h7;
reg [2:0] rx_comm = 3'h0;
//-----------------------------------------------------------------
// TLP receive
//-----------------------------------------------------------------
parameter [3:0]
RX_HEAD0 = 4'h0,
RX_HEAD1 = 4'h1,
RX_REQ2 = 4'h2,
RX_REQ3 = 4'h3,
RX_REQ4 = 4'h4,
RX_REQ5 = 4'h5,
RX_REQ6 = 4'h6,
RX_REQ7 = 4'h7,
RX_REQ = 4'h8,
RX_COMP2 = 4'h9,
RX_COMP3 = 4'ha,
RX_COMP4 = 4'hb,
RX_COMP5 = 4'hc,
RX_COMP6 = 4'hd,
RX_COMP7 = 4'he,
RX_COMP = 4'hf;
reg [3:0] rx_status = RX_HEAD0;
reg [1:0] rx_fmt = 2'b00;
reg [4:0] rx_type = 5'b00000;
reg [2:0] rx_tc = 2'b00;
reg rx_td = 1'b0, rx_ep = 1'b0;
reg [1:0] rx_attr = 2'b00;
reg [9:0] rx_length = 10'h0;
reg [15:0] rx_reqid = 16'h0;
reg [7:0] rx_tag = 8'h0;
reg [3:0] rx_lastbe = 4'h0, rx_firstbe = 4'h0;
reg [47:2] rx_addr = 46'h0000000000000000;
reg rx_tlph_valid = 1'b0;
reg [15:0] rx_data2 = 16'h0;
reg rx_end2 = 1'b0;
always @(posedge pcie_clk) begin
if (sys_rst) begin
rx_status <= RX_HEAD0;
rx_tlph_valid <= 1'b0;
pd_num <= 8'h0;
ph_cr <= 1'b0;
pd_cr <= 1'b0;
nph_cr <= 1'b0;
npd_cr <= 1'b0;
rx_data2[15:0] <= 16'h0;
rx_end2 <= 1'b0;
end else begin
rx_tlph_valid <= 1'b0;
pd_num <= 8'h0;
ph_cr <= 1'b0;
pd_cr <= 1'b0;
nph_cr <= 1'b0;
npd_cr <= 1'b0;
rx_data2 <= rx_data;
rx_end2 <= rx_end;
if ( rx_end == 1'b1 ) begin
case ( rx_comm )
TLP_MR, TLP_MRdLk: begin
`ifndef ENABLE_EXPROM
if ( rx_bar_hit[6:0] != 7'b0000000 ) begin
`endif
if ( rx_fmt[1] == 1'b0 ) begin
nph_cr <= 1'b1;
end else begin
ph_cr <= 1'b1;
pd_cr <= rx_fmt[1];
pd_num <= rx_length[1:0] == 2'b00 ? rx_length[9:2] : (rx_length[9:2] + 8'h1);
end
`ifndef ENABLE_EXPROM
end
`endif
end
TLP_IO, TLP_Cfg0, TLP_Cfg1: begin
nph_cr <= 1'b1;
npd_cr <= rx_fmt[1];
end
TLP_Msg: begin
ph_cr <= 1'b1;
if ( rx_fmt[1] == 1'b1 ) begin
pd_cr <= 1'b1;
pd_num <= rx_length[1:0] == 2'b00 ? rx_length[9:2] : (rx_length[9:2] + 8'h1);
end
end
TLP_Cpl: begin
end
TLP_CplLk: begin
end
endcase
rx_status <= RX_HEAD0;
end
case ( rx_status )
RX_HEAD0: begin
if ( rx_st == 1'b1 ) begin
rx_fmt [1:0] <= rx_data[14:13];
rx_type[4:0] <= rx_data[12: 8];
rx_tc [2:0] <= rx_data[ 6: 4];
if ( rx_data[12] == 1'b1 ) begin
rx_comm <= TLP_Msg;
end else begin
if ( rx_data[11] == 1'b0) begin
case ( rx_data[10:8] )
3'b000: rx_comm <= TLP_MR;
3'b001: rx_comm <= TLP_MRdLk;
3'b010: rx_comm <= TLP_IO;
3'b100: rx_comm <= TLP_Cfg0;
default:rx_comm <= TLP_Cfg1;
endcase
end else begin
if ( rx_data[8] == 1'b0 )
rx_comm <= TLP_Cpl;
else
rx_comm <= TLP_CplLk;
end
end
rx_status <= RX_HEAD1;
end
end
RX_HEAD1: begin
rx_td <= rx_data[15:15];
rx_ep <= rx_data[14:14];
rx_attr[1:0] <= rx_data[13:12];
rx_length[9:0] <= rx_data[ 9: 0];
if ( rx_type[3] == 1'b0 )
rx_status <= RX_REQ2;
else
rx_status <= RX_COMP2;
end
RX_REQ2: begin
rx_reqid[15:0] <= rx_data[15:0];
rx_status <= RX_REQ3;
end
RX_REQ3: begin
rx_tag[7:0] <= rx_data[15:8];
rx_lastbe[3:0] <= rx_data[7:4];
rx_firstbe[3:0] <= rx_data[3:0];
if ( rx_fmt[0] == 1'b0 ) begin // 64 or 32bit ??
rx_addr[47:32] <= 16'h0;
rx_status <= RX_REQ6;
end else
rx_status <= RX_REQ4;
end
RX_REQ4: begin
rx_status <= RX_REQ5;
end
RX_REQ5: begin
rx_addr[47:32] <= rx_data[15:0];
rx_status <= RX_REQ6;
end
RX_REQ6: begin
rx_addr[31:16] <= rx_data[15:0];
rx_tlph_valid <= 1'b1;
rx_status <= RX_REQ7;
end
RX_REQ7: begin
rx_addr[15: 2] <= rx_data[15:2];
if ( rx_end == 1'b0 )
rx_status <= RX_REQ;
end
RX_REQ: begin
end
endcase
end
end
//-----------------------------------------------------------------
// TLP transmit
//-----------------------------------------------------------------
parameter [4:0]
TX_IDLE = 5'h0,
TX_WAIT = 5'h1,
TX1_HEAD0= 5'h2,
TX1_HEAD1= 5'h3,
TX1_COMP2= 5'h4,
TX1_COMP3= 5'h5,
TX1_COMP4= 5'h6,
TX1_COMP5= 5'h7,
TX1_DATA = 5'h8,
TX2_HEAD0= 5'h9,
TX2_HEAD1= 5'hA,
TX2_COMP2= 5'hB,
TX2_COMP3= 5'hC,
TX2_COMP4= 5'hD,
TX2_COMP5= 5'hE,
TX2_COMP6= 5'hF,
TX2_COMP7= 5'h10,
TX2_DATA = 5'h11;
reg [4:0] tx_status = TX_IDLE;
reg tx_lastch = 1'b0;
reg [15:0] tx1_data;
reg tx1_tlph_valid = 1'b0;
reg tx1_tlpd_ready = 1'b0;
reg tx1_tlpd_done = 1'b0;
reg [1:0] tx1_fmt = 2'b00;
reg [4:0] tx1_type = 5'b00000;
reg [2:0] tx1_tc = 2'b00;
reg tx1_td = 1'b0, tx1_ep = 1'b0;
reg [1:0] tx1_attr = 2'b00;
reg [10:0] tx1_length = 11'h0;
reg [2:0] tx1_cplst = 3'h0;
reg tx1_bcm = 1'b0;
reg [11:0] tx1_bcount = 12'h0;
reg [15:0] tx1_reqid = 16'h0;
reg [7:0] tx1_tag = 8'h0;
reg [7:0] tx1_lowaddr = 8'h0;
reg [3:0] tx1_lastbe = 4'h0, tx1_firstbe = 4'h0;
reg [15:0] tx2_data;
reg tx2_tlph_valid = 1'b0;
reg tx2_tlpd_ready = 1'b0;
reg tx2_tlpd_done = 1'b0;
reg [1:0] tx2_fmt = 2'b00;
reg [4:0] tx2_type = 5'b00000;
reg [2:0] tx2_tc = 2'b00;
reg tx2_td = 1'b0, tx2_ep = 1'b0;
reg [1:0] tx2_attr = 2'b00;
reg [10:0] tx2_length = 11'h0;
reg [11:0] tx2_bcount = 12'h0;
reg [15:0] tx2_reqid = 16'h0;
reg [7:0] tx2_tag = 8'h0;
reg [7:0] tx2_lowaddr = 8'h0;
reg [3:0] tx2_lastbe = 4'h0, tx2_firstbe = 4'h0;
reg [47:2] tx2_addr = 46'h0000000000000000;
always @(posedge pcie_clk) begin
if (sys_rst) begin
tx_status <= TX_IDLE;
tx_data[15:0] <= 16'h0;
tx_req <= 1'b0;
tx_st <= 1'b0;
tx1_tlpd_ready <= 1'b0;
tx2_tlpd_ready <= 1'b0;
tx_lastch <= 1'b0;
end else begin
tx_st <= 1'b0;
case ( tx_status )
TX_IDLE: begin
if ( tx1_tlph_valid == 1'b1 || tx2_tlph_valid == 1'b1 ) begin
tx_lastch <= tx2_tlph_valid;
tx_req <= 1'b1;
tx_status <= TX_WAIT;
end
end
TX_WAIT: begin
if ( tx_rdy == 1'b1 ) begin
tx_req <= 1'b0;
if ( tx_lastch == 1'b1 )
tx_status <= TX2_HEAD0;
else
tx_status <= TX1_HEAD0;
end
end
TX1_HEAD0: begin
tx_data[15:0] <= {1'b0, tx1_fmt[1:0], tx1_type[4:0], 1'b0, tx1_tc[2:0], 4'b000};
tx_st <= 1'b1;
tx_status <= TX1_HEAD1;
end
TX1_HEAD1: begin
tx_data[15:0] <= {tx1_td, tx1_ep, tx1_attr[1:0], 2'b00, tx1_length[10:1]};
tx_status <= TX1_COMP2;
end
TX1_COMP2: begin
tx_data[15:0] <= {bus_num, dev_num, func_num}; // CplID
tx1_tlpd_ready <= 1'b1;
tx_status <= TX1_COMP3;
end
TX1_COMP3: begin
tx_data[15:0] <= { tx1_cplst[2:0], tx1_bcm, tx1_bcount[11:0] };
tx_status <= TX1_COMP4;
end
TX1_COMP4: begin
tx_data[15:0] <= tx1_reqid[15:0];
tx_status <= TX1_COMP5;
end
TX1_COMP5: begin
tx_data[15:0] <= { tx1_tag[7:0], 1'b0, tx1_lowaddr[6:0] };
tx_status <= TX1_DATA;
end
TX1_DATA: begin
tx_data[15:0] <= tx1_data[15:0];
if (tx1_tlpd_done == 1'b1) begin
tx_status <= TX_IDLE;
tx1_tlpd_ready <= 1'b0;
end
end
TX2_HEAD0: begin
tx_data[15:0] <= {1'b0, tx2_fmt[1:0], tx2_type[4:0], 1'b0, tx2_tc[2:0], 4'b000};
tx_st <= 1'b1;
tx_status <= TX2_HEAD1;
end
TX2_HEAD1: begin
tx_data[15:0] <= {tx2_td, tx2_ep, tx2_attr[1:0], 2'b00, tx2_length[10:1]};
tx_status <= TX2_COMP2;
end
TX2_COMP2: begin
tx_data[15:0] <= {bus_num, dev_num, func_num}; // Request ID
tx_status <= TX2_COMP3;
end
TX2_COMP3: begin
tx_data[15:0] <= { tx2_tag[7:0], tx2_lastbe[3:0], tx2_firstbe[3:0] };
if ( tx2_fmt[0] == 1'b0 ) begin // 64 or 32bit ??
tx2_tlpd_ready <= 1'b1;
tx_status <= TX2_COMP6;
end else
tx_status <= TX2_COMP4;
end
TX2_COMP4: begin
tx_data[15:0] <= 16'h0000;
tx2_tlpd_ready <= 1'b1;
tx_status <= TX2_COMP5;
end
TX2_COMP5: begin
tx_data[15:0] <= tx2_addr[47:32];
tx_status <= TX2_COMP6;
end
TX2_COMP6: begin
tx_data[15:0] <= tx2_addr[31:16];
tx_status <= TX2_COMP7;
end
TX2_COMP7: begin
tx_data[15:0] <= { tx2_addr[15: 2], 2'b00 };
tx_status <= TX2_DATA;
end
TX2_DATA: begin
tx_data[15:0] <= tx2_data[15:0];
if (tx2_tlpd_done == 1'b1) begin
tx_status <= TX_IDLE;
tx2_tlpd_ready <= 1'b0;
end
end
endcase
end
end
//-----------------------------------------------------------------
// Slave Seaquencer
//-----------------------------------------------------------------
parameter [3:0]
SLV_IDLE = 3'h0,
SLV_MREADH = 3'h1,
SLV_MREADD = 3'h2,
SLV_MWRITEH= 3'h3,
SLV_MWRITED= 3'h4,
SLV_COMP = 3'h7;
reg [3:0] slv_status = SLV_IDLE;
always @(posedge pcie_clk) begin
if (sys_rst) begin
tx1_tlph_valid <= 1'b0;
tx1_tlpd_done <= 1'b0;
slv_status <= SLV_IDLE;
slv_bar_i <= 7'h0;
slv_ce_i <= 1'b0;
slv_we_i <= 1'b0;
slv_adr_i <= 20'h0;
slv_dat_i <= 16'b0;
slv_sel_i <= 2'b00;
end else begin
tx1_tlpd_done <= 1'b0;
slv_ce_i <= 1'b0;
slv_we_i <= 1'b0;
case ( slv_status )
SLV_IDLE: begin
tx1_tlph_valid <= 1'b0;
slv_bar_i <= 7'h0;
if ( rx_tlph_valid == 1'b1 ) begin
case ( rx_comm )
TLP_MR: begin
`ifdef ENABLE_EXPROM
slv_bar_i <= rx_bar_hit == 7'h0 ? 7'b1000000 : rx_bar_hit;
`else
slv_bar_i <= rx_bar_hit;
`endif
if ( rx_fmt[1] == 1'b0 ) begin
slv_status <= SLV_MREADH;
end else begin
slv_status <= SLV_MWRITEH;
end
end
TLP_MRdLk: begin
end
TLP_IO: begin
end
TLP_Cfg0: begin
end
TLP_Cfg1: begin
end
TLP_Msg: begin
end
TLP_Cpl: begin
end
TLP_CplLk: begin
end
endcase
end
end
SLV_MREADH: begin
tx1_fmt[1:0] <= 2'b10; // 3DW with data
tx1_type[4:0] <= 5'b01010; // Cpl with data
tx1_tc[2:0] <= 3'b000;
tx1_td <= 1'b0;
tx1_ep <= 1'b0;
tx1_attr[1:0] <= 2'b00;
tx1_cplst[2:0] <= 3'b000;
tx1_bcm <= 1'b0;
casex( {rx_firstbe[3:0], rx_lastbe[3:0]} )
8'b1xx10000: tx1_bcount[11:0] <= 12'h004;
8'b01x10000: tx1_bcount[11:0] <= 12'h003;
8'b1x100000: tx1_bcount[11:0] <= 12'h003;
8'b00110000: tx1_bcount[11:0] <= 12'h002;
8'b01100000: tx1_bcount[11:0] <= 12'h002;
8'b11000000: tx1_bcount[11:0] <= 12'h002;
8'b00010000: tx1_bcount[11:0] <= 12'h001;
8'b00100000: tx1_bcount[11:0] <= 12'h001;
8'b01000000: tx1_bcount[11:0] <= 12'h001;
8'b10000000: tx1_bcount[11:0] <= 12'h001;
8'b00000000: tx1_bcount[11:0] <= 12'h001;
8'bxxx11xxx: tx1_bcount[11:0] <= (rx_length*4);
8'bxxx101xx: tx1_bcount[11:0] <= (rx_length*4) - 1;
8'bxxx1001x: tx1_bcount[11:0] <= (rx_length*4) - 2;
8'bxxx10001: tx1_bcount[11:0] <= (rx_length*4) - 3;
8'bxx101xxx: tx1_bcount[11:0] <= (rx_length*4) - 1;
8'bxx1001xx: tx1_bcount[11:0] <= (rx_length*4) - 2;
8'bxx10001x: tx1_bcount[11:0] <= (rx_length*4) - 3;
8'bxx100001: tx1_bcount[11:0] <= (rx_length*4) - 4;
8'bx1001xxx: tx1_bcount[11:0] <= (rx_length*4) - 2;
8'bx10001xx: tx1_bcount[11:0] <= (rx_length*4) - 3;
8'bx100001x: tx1_bcount[11:0] <= (rx_length*4) - 4;
8'bx1000001: tx1_bcount[11:0] <= (rx_length*4) - 5;
8'b10001xxx: tx1_bcount[11:0] <= (rx_length*4) - 3;
8'b100001xx: tx1_bcount[11:0] <= (rx_length*4) - 4;
8'b1000001x: tx1_bcount[11:0] <= (rx_length*4) - 5;
8'b10000001: tx1_bcount[11:0] <= (rx_length*4) - 6;
endcase
tx1_reqid[15:0] <= rx_reqid[15:0];
tx1_tag[7:0] <= rx_tag[7:0];
casex (rx_firstbe[3:0])
4'b0000: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b00};
4'bxxx1: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b00};
4'bxx10: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b01};
4'bx100: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b10};
4'b1000: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b11};
endcase
tx1_length[10:0] <= {rx_length[9:0], 1'b1};
slv_adr_i[19:1] <= ({rx_addr[19:2],1'b0} - 19'h1);
tx1_tlph_valid <= 1'b1;
slv_status <= SLV_MREADD;
end
SLV_MREADD: begin
if ( tx1_tlpd_ready == 1'b1 ) begin
tx1_tlph_valid <= 1'b0;
tx1_length <= tx1_length - 11'h1;
if ( tx1_length[10:1] != 10'h000)
slv_adr_i[19:1] <= slv_adr_i[19:1] + 19'h1;
if ( tx1_length == 11'h7ff ) begin
slv_status <= SLV_IDLE;
tx1_tlpd_done <= 1'b1;
end else
slv_ce_i <= 1'b1;
tx1_data[15:0] <= slv_dat_o[15:0];
end
end
SLV_MWRITEH: begin
tx1_length[10:0] <= 11'h0;
slv_adr_i[19:1] <= ({rx_addr[19:2],1'b0} - 19'h1);
slv_status <= SLV_MWRITED;
end
SLV_MWRITED: begin
tx1_length <= tx1_length + 11'h1;
slv_adr_i[19:1] <= slv_adr_i[19:1] + 19'h1;
slv_ce_i <= 1'b1;
slv_we_i <= 1'b1;
slv_dat_i <= rx_data2[15:0];
if ( tx1_length[10:1] == 10'h0 ) begin
if ( tx1_length[0] == 1'b0 ) begin
slv_sel_i[1:0] <= { rx_firstbe[0], rx_firstbe[1] };
end else begin
slv_sel_i[1:0] <= { rx_firstbe[2], rx_firstbe[3] };
end
end else if ( tx1_length[10:1] == (rx_length[9:0] - 10'h1) )
if ( tx1_length[0] == 1'b0 ) begin
slv_sel_i[1:0] <= { rx_lastbe[0], rx_lastbe[1] };
end else begin
slv_sel_i[1:0] <= { rx_lastbe[2], rx_lastbe[3] };
slv_status <= SLV_IDLE;
end
else begin
slv_sel_i[1:0] <= 2'b11;
end
if ( rx_end2 == 1'b1 )
slv_status <= SLV_IDLE;
end
endcase
end
end
//-----------------------------------------------------------------
// Master Seaquencer
//-----------------------------------------------------------------
parameter [3:0]
MST_IDLE = 3'h0,
MST_MWRITE64= 3'h1,
MST_MWRITE48= 3'h2,
MST_MWRITE32= 3'h3,
MST_MWRITE16= 3'h4,
MST_MWRITED = 3'h5,
MST_COMP = 3'h7;
reg [3:0] mst_status = MST_IDLE;
reg [47:1] mst_adr;
reg mst_rd_wait;
always @(posedge pcie_clk) begin
if (sys_rst) begin
tx2_tlph_valid <= 1'b0;
tx2_tlpd_done <= 1'b0;
mst_status <= MST_IDLE;
mst_rd_en <= 1'b0;
mst_rd_wait <= 1'b0;
end else begin
tx2_tlpd_done <= 1'b0;
mst_rd_en <= ~mst_empty & ~mst_rd_wait;
if ( ( mst_rd_en == 1'b1 && mst_empty == 1'b0 ) || ( mst_status == MST_MWRITED ) ) begin
case ( mst_status )
MST_IDLE: begin
tx2_tlph_valid <= 1'b0;
if ( mst_dout[17] == 1'b1 ) begin
tx2_addr[47:32] <= 14'h0;
tx2_length[10:0] <= {4'b0000, mst_dout[13:8], 1'b0};
{tx2_lastbe[3:0], tx2_firstbe[3:0]} <= mst_dout[7:0];
case ( mst_dout[15:14] )
2'b00: mst_status <= MST_MWRITE32;
2'b01: mst_status <= MST_MWRITE64;
2'b10: mst_status <= MST_MWRITE32;
2'b11: mst_status <= MST_MWRITE64;
endcase
end
end
MST_MWRITE64: begin
mst_status <= MST_MWRITE48;
end
MST_MWRITE48: begin
tx2_addr[47:32] <= mst_dout[15:0];
mst_status <= MST_MWRITE32;
end
MST_MWRITE32: begin
tx2_addr[31:16] <= mst_dout[15:0];
mst_status <= MST_MWRITE16;
end
MST_MWRITE16: begin
tx2_addr[15: 2] <= mst_dout[15:2];
tx2_fmt[1:0] <= 2'b11; // 4DW, with DATA
tx2_type[4:0] <= 5'b00000; // Memory write request
tx2_tc[2:0] <= 3'b000;
tx2_td <= 1'b0;
tx2_ep <= 1'b0;
tx2_attr[1:0] <= 2'b00;
tx2_tag[7:0] <= 8'h01;
mst_adr[47:1] <= {tx2_addr[47:16], mst_dout[15:2], 1'b0};
tx2_tlph_valid <= 1'b1;
mst_rd_en <= 1'b0;
mst_rd_wait <= 1'b1;
mst_status <= MST_MWRITED;
end
MST_MWRITED: begin
if ( tx2_tlpd_ready == 1'b1 ) begin
tx2_tlph_valid <= 1'b0;
tx2_length <= tx2_length - 11'h1;
if ( tx2_length[10:1] != 10'h000)
mst_adr[47:1] <= mst_adr[47:1] + 19'h1;
if ( tx2_length == 11'h7ff || tx2_length == 11'h7fe ) begin
mst_rd_en <= 1'b0;
end
if ( tx2_length == 11'h7fe ) begin
tx2_tlpd_done <= 1'b1;
mst_status <= MST_IDLE;
end
tx2_data[15:0] <= mst_dout[15:0];
mst_rd_wait <= 1'b0;
end
end
`ifdef NO
MST_MWRITEH: begin
tx2_length[10:0] <= 11'h0;
mst_adr[19:1] <= ({rx_addr[19:2],1'b0} - 19'h1);
mst_status <= MST_MWRITED;
end
MST_MWRITED: begin
tx2_length <= tx2_length + 11'h1;
mst_adr[19:1] <= mst_adr[19:1] + 19'h1;
mst_din <= rx_data2[15:0];
if ( tx2_length[10:1] == (rx_length[9:0] - 10'h1) )
if ( tx2_length[0] == 1'b1 ) begin
mst_status <= MST_IDLE;
end
if ( rx_end2 == 1'b1 )
mst_status <= MST_IDLE;
end
`endif
endcase
end
end
end
assign tx_end = tx1_tlpd_done | tx2_tlpd_done;
//assign tx_end = tx1_tlpd_done;
//assign led = 8'b11111111;
//assign led = ~(btn ? rx_addr[31:24] : rx_addr[23:16]);
assign led = ~(btn ? rx_length[7:0] : {rx_lastbe[3:0], rx_firstbe[3:0]} );
//assign segled = ~{12'b000000000000, rx_length[9:8] };
endmodule |
module fifo_267x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [266:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [266:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
endmodule |
module LAG_pl_allocator (req, output_port, // PL request, for which port?
pl_new, pl_new_valid, // newly allocated PL ids
pl_allocated, // which PLs were allocated on this cycle?
pl_alloc_status, // which PLs are free?
clk, rst_n);
parameter buf_len=4;
parameter xs=4;
parameter ys=4;
parameter np=5;
parameter nv=4;
parameter dynamic_priority_pl_alloc = 0;
parameter plalloc_unrestricted = 0;
parameter alloc_stages = 1;
parameter plselect_bydestinationnode = 0;
parameter plselect_leastfullbuffer = 0;
parameter plselect_arbstateupdate = 0;
parameter plselect_usepacketmask = 0;
//-----
input [np-1:0][nv-1:0] req;
input output_port_t output_port [np-1:0][nv-1:0];
output [np-1:0][nv-1:0][nv-1:0] pl_new;
output [np-1:0][nv-1:0] pl_new_valid;
// input pl_priority_t pl_sel_priority [np-1:0][nv-1:0][nv-1:0];
output [np-1:0][nv-1:0] pl_allocated;
input [np-1:0][nv-1:0] pl_alloc_status;
input clk, rst_n;
generate
LAG_pl_unrestricted_allocator
#(.np(np), .nv(nv), .xs(xs), .ys(ys), .buf_len(buf_len),
.alloc_stages(alloc_stages),
.dynamic_priority_pl_alloc(dynamic_priority_pl_alloc),
.plselect_bydestinationnode(plselect_bydestinationnode),
.plselect_leastfullbuffer(plselect_leastfullbuffer),
.plselect_arbstateupdate(plselect_arbstateupdate),
.plselect_usepacketmask(plselect_usepacketmask))
unrestricted
(
.req,
.output_port,
.pl_status(pl_alloc_status),
.pl_new,
.pl_new_valid,
.pl_allocated,
.clk, .rst_n
);
endgenerate
endmodule |
module altera_syscon_pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altera_syscon_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule |
module sky130_fd_sc_lp__xor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module sirv_tl_repeater_5(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [1:0] io_enq_bits_source,
input [29:0] io_enq_bits_address,
input [3:0] io_enq_bits_mask,
input [31:0] io_enq_bits_data,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [1:0] io_deq_bits_source,
output [29:0] io_deq_bits_address,
output [3:0] io_deq_bits_mask,
output [31:0] io_deq_bits_data
);
reg full;
reg [31:0] GEN_9;
reg [2:0] saved_opcode;
reg [31:0] GEN_10;
reg [2:0] saved_param;
reg [31:0] GEN_11;
reg [2:0] saved_size;
reg [31:0] GEN_12;
reg [1:0] saved_source;
reg [31:0] GEN_13;
reg [29:0] saved_address;
reg [31:0] GEN_14;
reg [3:0] saved_mask;
reg [31:0] GEN_15;
reg [31:0] saved_data;
reg [31:0] GEN_16;
wire T_77;
wire T_79;
wire T_80;
wire [2:0] T_81_opcode;
wire [2:0] T_81_param;
wire [2:0] T_81_size;
wire [1:0] T_81_source;
wire [29:0] T_81_address;
wire [3:0] T_81_mask;
wire [31:0] T_81_data;
wire T_89;
wire T_90;
wire GEN_0;
wire [2:0] GEN_1;
wire [2:0] GEN_2;
wire [2:0] GEN_3;
wire [1:0] GEN_4;
wire [29:0] GEN_5;
wire [3:0] GEN_6;
wire [31:0] GEN_7;
wire T_92;
wire T_94;
wire T_95;
wire GEN_8;
assign io_full = full;
assign io_enq_ready = T_80;
assign io_deq_valid = T_77;
assign io_deq_bits_opcode = T_81_opcode;
assign io_deq_bits_param = T_81_param;
assign io_deq_bits_size = T_81_size;
assign io_deq_bits_source = T_81_source;
assign io_deq_bits_address = T_81_address;
assign io_deq_bits_mask = T_81_mask;
assign io_deq_bits_data = T_81_data;
assign T_77 = io_enq_valid | full;
assign T_79 = full == 1'h0;
assign T_80 = io_deq_ready & T_79;
assign T_81_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign T_81_param = full ? saved_param : io_enq_bits_param;
assign T_81_size = full ? saved_size : io_enq_bits_size;
assign T_81_source = full ? saved_source : io_enq_bits_source;
assign T_81_address = full ? saved_address : io_enq_bits_address;
assign T_81_mask = full ? saved_mask : io_enq_bits_mask;
assign T_81_data = full ? saved_data : io_enq_bits_data;
assign T_89 = io_enq_ready & io_enq_valid;
assign T_90 = T_89 & io_repeat;
assign GEN_0 = T_90 ? 1'h1 : full;
assign GEN_1 = T_90 ? io_enq_bits_opcode : saved_opcode;
assign GEN_2 = T_90 ? io_enq_bits_param : saved_param;
assign GEN_3 = T_90 ? io_enq_bits_size : saved_size;
assign GEN_4 = T_90 ? io_enq_bits_source : saved_source;
assign GEN_5 = T_90 ? io_enq_bits_address : saved_address;
assign GEN_6 = T_90 ? io_enq_bits_mask : saved_mask;
assign GEN_7 = T_90 ? io_enq_bits_data : saved_data;
assign T_92 = io_deq_ready & io_deq_valid;
assign T_94 = io_repeat == 1'h0;
assign T_95 = T_92 & T_94;
assign GEN_8 = T_95 ? 1'h0 : GEN_0;
always @(posedge clock or posedge reset)
if (reset) begin
full <= 1'h0;
end else begin
if (T_95) begin
full <= 1'h0;
end else begin
if (T_90) begin
full <= 1'h1;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
saved_opcode <= 3'b0;
saved_param <= 3'b0;
saved_size <= 3'b0;
saved_source <= 2'b0;
saved_address <= 30'b0;
saved_mask <= 4'b0;
saved_data <= 32'b0;
end
else begin
if (T_90) begin
saved_opcode <= io_enq_bits_opcode;
end
if (T_90) begin
saved_param <= io_enq_bits_param;
end
if (T_90) begin
saved_size <= io_enq_bits_size;
end
if (T_90) begin
saved_source <= io_enq_bits_source;
end
if (T_90) begin
saved_address <= io_enq_bits_address;
end
if (T_90) begin
saved_mask <= io_enq_bits_mask;
end
if (T_90) begin
saved_data <= io_enq_bits_data;
end
end
endmodule |
module image_processing_2d_design
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
LINESCANNER0_DATA,
LINESCANNER0_END_ADC,
LINESCANNER0_LOAD_PULSE,
LINESCANNER0_LVAL,
LINESCANNER0_MAIN_CLOCK,
LINESCANNER0_N_RESET,
LINESCANNER0_PIXEL_CLOCK,
LINESCANNER0_RST_CDS,
LINESCANNER0_RST_CVC,
LINESCANNER0_SAMPLE,
LINESCANNER1_DATA,
LINESCANNER1_END_ADC,
LINESCANNER1_LOAD_PULSE,
LINESCANNER1_LVAL,
LINESCANNER1_MAIN_CLOCK,
LINESCANNER1_N_RESET,
LINESCANNER1_PIXEL_CLOCK,
LINESCANNER1_RST_CDS,
LINESCANNER1_RST_CVC,
LINESCANNER1_SAMPLE,
LINESCANNER_CLK,
LINESCANNER_CS,
LINESCANNER_MISO,
LINESCANNER_MOSI);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [7:0]LINESCANNER0_DATA;
input LINESCANNER0_END_ADC;
output LINESCANNER0_LOAD_PULSE;
input LINESCANNER0_LVAL;
output LINESCANNER0_MAIN_CLOCK;
output [0:0]LINESCANNER0_N_RESET;
input LINESCANNER0_PIXEL_CLOCK;
output LINESCANNER0_RST_CDS;
output LINESCANNER0_RST_CVC;
output LINESCANNER0_SAMPLE;
input [7:0]LINESCANNER1_DATA;
input LINESCANNER1_END_ADC;
output LINESCANNER1_LOAD_PULSE;
input LINESCANNER1_LVAL;
output LINESCANNER1_MAIN_CLOCK;
output [0:0]LINESCANNER1_N_RESET;
input LINESCANNER1_PIXEL_CLOCK;
output LINESCANNER1_RST_CDS;
output LINESCANNER1_RST_CVC;
output LINESCANNER1_SAMPLE;
output LINESCANNER_CLK;
output [1:0]LINESCANNER_CS;
input LINESCANNER_MISO;
output LINESCANNER_MOSI;
wire [7:0]LINESCANNER0_DATA_1;
wire LINESCANNER0_END_ADC_1;
wire LINESCANNER0_LVAL_1;
wire LINESCANNER0_PIXEL_CLOCK_1;
wire [7:0]LINESCANNER1_DATA_1;
wire LINESCANNER1_END_ADC_1;
wire LINESCANNER1_LVAL_1;
wire LINESCANNER1_PIXEL_CLOCK_1;
wire LINESCANNER_MISO_1;
wire [31:0]axi_interconnect_0_M01_AXI_ARADDR;
wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;
wire axi_interconnect_0_M01_AXI_ARREADY;
wire axi_interconnect_0_M01_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M01_AXI_AWADDR;
wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;
wire axi_interconnect_0_M01_AXI_AWREADY;
wire axi_interconnect_0_M01_AXI_AWVALID;
wire axi_interconnect_0_M01_AXI_BREADY;
wire [1:0]axi_interconnect_0_M01_AXI_BRESP;
wire axi_interconnect_0_M01_AXI_BVALID;
wire [31:0]axi_interconnect_0_M01_AXI_RDATA;
wire axi_interconnect_0_M01_AXI_RREADY;
wire [1:0]axi_interconnect_0_M01_AXI_RRESP;
wire axi_interconnect_0_M01_AXI_RVALID;
wire [31:0]axi_interconnect_0_M01_AXI_WDATA;
wire axi_interconnect_0_M01_AXI_WREADY;
wire [3:0]axi_interconnect_0_M01_AXI_WSTRB;
wire axi_interconnect_0_M01_AXI_WVALID;
wire [31:0]axi_interconnect_0_M02_AXI_ARADDR;
wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;
wire axi_interconnect_0_M02_AXI_ARREADY;
wire axi_interconnect_0_M02_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M02_AXI_AWADDR;
wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;
wire axi_interconnect_0_M02_AXI_AWREADY;
wire axi_interconnect_0_M02_AXI_AWVALID;
wire axi_interconnect_0_M02_AXI_BREADY;
wire [1:0]axi_interconnect_0_M02_AXI_BRESP;
wire axi_interconnect_0_M02_AXI_BVALID;
wire [31:0]axi_interconnect_0_M02_AXI_RDATA;
wire axi_interconnect_0_M02_AXI_RREADY;
wire [1:0]axi_interconnect_0_M02_AXI_RRESP;
wire axi_interconnect_0_M02_AXI_RVALID;
wire [31:0]axi_interconnect_0_M02_AXI_WDATA;
wire axi_interconnect_0_M02_AXI_WREADY;
wire [3:0]axi_interconnect_0_M02_AXI_WSTRB;
wire axi_interconnect_0_M02_AXI_WVALID;
wire [31:0]axi_interconnect_0_M03_AXI_ARADDR;
wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;
wire axi_interconnect_0_M03_AXI_ARREADY;
wire axi_interconnect_0_M03_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M03_AXI_AWADDR;
wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;
wire axi_interconnect_0_M03_AXI_AWREADY;
wire axi_interconnect_0_M03_AXI_AWVALID;
wire axi_interconnect_0_M03_AXI_BREADY;
wire [1:0]axi_interconnect_0_M03_AXI_BRESP;
wire axi_interconnect_0_M03_AXI_BVALID;
wire [31:0]axi_interconnect_0_M03_AXI_RDATA;
wire axi_interconnect_0_M03_AXI_RREADY;
wire [1:0]axi_interconnect_0_M03_AXI_RRESP;
wire axi_interconnect_0_M03_AXI_RVALID;
wire [31:0]axi_interconnect_0_M03_AXI_WDATA;
wire axi_interconnect_0_M03_AXI_WREADY;
wire [3:0]axi_interconnect_0_M03_AXI_WSTRB;
wire axi_interconnect_0_M03_AXI_WVALID;
wire [31:0]axi_interconnect_0_M04_AXI_ARADDR;
wire [1:0]axi_interconnect_0_M04_AXI_ARBURST;
wire [3:0]axi_interconnect_0_M04_AXI_ARCACHE;
wire [3:0]axi_interconnect_0_M04_AXI_ARLEN;
wire [1:0]axi_interconnect_0_M04_AXI_ARLOCK;
wire [2:0]axi_interconnect_0_M04_AXI_ARPROT;
wire [3:0]axi_interconnect_0_M04_AXI_ARQOS;
wire axi_interconnect_0_M04_AXI_ARREADY;
wire [2:0]axi_interconnect_0_M04_AXI_ARSIZE;
wire axi_interconnect_0_M04_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M04_AXI_AWADDR;
wire [1:0]axi_interconnect_0_M04_AXI_AWBURST;
wire [3:0]axi_interconnect_0_M04_AXI_AWCACHE;
wire [3:0]axi_interconnect_0_M04_AXI_AWLEN;
wire [1:0]axi_interconnect_0_M04_AXI_AWLOCK;
wire [2:0]axi_interconnect_0_M04_AXI_AWPROT;
wire [3:0]axi_interconnect_0_M04_AXI_AWQOS;
wire axi_interconnect_0_M04_AXI_AWREADY;
wire [2:0]axi_interconnect_0_M04_AXI_AWSIZE;
wire axi_interconnect_0_M04_AXI_AWVALID;
wire axi_interconnect_0_M04_AXI_BREADY;
wire [1:0]axi_interconnect_0_M04_AXI_BRESP;
wire axi_interconnect_0_M04_AXI_BVALID;
wire [31:0]axi_interconnect_0_M04_AXI_RDATA;
wire axi_interconnect_0_M04_AXI_RLAST;
wire axi_interconnect_0_M04_AXI_RREADY;
wire [1:0]axi_interconnect_0_M04_AXI_RRESP;
wire axi_interconnect_0_M04_AXI_RVALID;
wire [31:0]axi_interconnect_0_M04_AXI_WDATA;
wire axi_interconnect_0_M04_AXI_WLAST;
wire axi_interconnect_0_M04_AXI_WREADY;
wire [3:0]axi_interconnect_0_M04_AXI_WSTRB;
wire axi_interconnect_0_M04_AXI_WVALID;
wire dragster_configurator_0_mosi;
wire dragster_configurator_0_sclk;
wire [1:0]dragster_configurator_0_ss_n;
wire frequency_analyzer_manager_0_irq;
wire frequency_analyzer_manager_1_irq;
wire frequency_analyzer_synch_0_start_analyzer_0;
wire frequency_analyzer_synch_0_start_analyzer_1;
wire frequency_analyzer_synch_0_stop_analyzer_0;
wire frequency_analyzer_synch_0_stop_analyzer_1;
wire image_capture_manager_0_clear_memory;
wire image_capture_manager_0_image_capture_enabled;
wire image_capture_manager_0_reset;
wire linescanner_image_capture_unit_0_load_pulse;
wire linescanner_image_capture_unit_0_main_clock;
wire linescanner_image_capture_unit_0_pixel_captured;
(* MARK_DEBUG *) wire [7:0]linescanner_image_capture_unit_0_pixel_data;
wire linescanner_image_capture_unit_0_rst_cds;
wire linescanner_image_capture_unit_0_rst_cvc;
wire linescanner_image_capture_unit_0_sample;
wire linescanner_image_capture_unit_1_load_pulse;
wire linescanner_image_capture_unit_1_main_clock;
wire linescanner_image_capture_unit_1_pixel_captured;
wire [7:0]linescanner_image_capture_unit_1_pixel_data;
wire linescanner_image_capture_unit_1_rst_cds;
wire linescanner_image_capture_unit_1_rst_cvc;
wire linescanner_image_capture_unit_1_sample;
wire proc_sys_reset_0_peripheral_aresetn;
wire [0:0]proc_sys_reset_0_peripheral_reset;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_CLK1;
wire processing_system7_0_FCLK_CLK2;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [1:0]xlconcat_0_dout;
assign LINESCANNER0_DATA_1 = LINESCANNER0_DATA[7:0];
assign LINESCANNER0_END_ADC_1 = LINESCANNER0_END_ADC;
assign LINESCANNER0_LOAD_PULSE = linescanner_image_capture_unit_0_load_pulse;
assign LINESCANNER0_LVAL_1 = LINESCANNER0_LVAL;
assign LINESCANNER0_MAIN_CLOCK = linescanner_image_capture_unit_0_main_clock;
assign LINESCANNER0_N_RESET[0] = proc_sys_reset_0_peripheral_aresetn;
assign LINESCANNER0_PIXEL_CLOCK_1 = LINESCANNER0_PIXEL_CLOCK;
assign LINESCANNER0_RST_CDS = linescanner_image_capture_unit_0_rst_cds;
assign LINESCANNER0_RST_CVC = linescanner_image_capture_unit_0_rst_cvc;
assign LINESCANNER0_SAMPLE = linescanner_image_capture_unit_0_sample;
assign LINESCANNER1_DATA_1 = LINESCANNER1_DATA[7:0];
assign LINESCANNER1_END_ADC_1 = LINESCANNER1_END_ADC;
assign LINESCANNER1_LOAD_PULSE = linescanner_image_capture_unit_1_load_pulse;
assign LINESCANNER1_LVAL_1 = LINESCANNER1_LVAL;
assign LINESCANNER1_MAIN_CLOCK = linescanner_image_capture_unit_1_main_clock;
assign LINESCANNER1_N_RESET[0] = proc_sys_reset_0_peripheral_aresetn;
assign LINESCANNER1_PIXEL_CLOCK_1 = LINESCANNER1_PIXEL_CLOCK;
assign LINESCANNER1_RST_CDS = linescanner_image_capture_unit_1_rst_cds;
assign LINESCANNER1_RST_CVC = linescanner_image_capture_unit_1_rst_cvc;
assign LINESCANNER1_SAMPLE = linescanner_image_capture_unit_1_sample;
assign LINESCANNER_CLK = dragster_configurator_0_sclk;
assign LINESCANNER_CS[1:0] = dragster_configurator_0_ss_n;
assign LINESCANNER_MISO_1 = LINESCANNER_MISO;
assign LINESCANNER_MOSI = dragster_configurator_0_mosi;
image_processing_2d_design_axi_interconnect_0_0 axi_interconnect_0
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M00_AXI_arready(1'b0),
.M00_AXI_awready(1'b0),
.M00_AXI_bresp(1'b0),
.M00_AXI_bvalid(1'b0),
.M00_AXI_rdata(1'b0),
.M00_AXI_rlast(1'b0),
.M00_AXI_rresp(1'b0),
.M00_AXI_rvalid(1'b0),
.M00_AXI_wready(1'b0),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),
.M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),
.M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),
.M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),
.M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),
.M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),
.M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),
.M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),
.M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),
.M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),
.M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),
.M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),
.M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),
.M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),
.M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),
.M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),
.M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),
.M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),
.M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),
.M02_ACLK(processing_system7_0_FCLK_CLK0),
.M02_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),
.M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),
.M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),
.M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),
.M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),
.M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),
.M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),
.M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),
.M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),
.M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),
.M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),
.M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),
.M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),
.M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),
.M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),
.M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),
.M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),
.M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),
.M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),
.M03_ACLK(processing_system7_0_FCLK_CLK0),
.M03_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),
.M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),
.M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),
.M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),
.M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),
.M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),
.M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),
.M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),
.M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),
.M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),
.M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),
.M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),
.M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),
.M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),
.M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),
.M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),
.M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),
.M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),
.M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),
.M04_ACLK(processing_system7_0_FCLK_CLK0),
.M04_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M04_AXI_araddr(axi_interconnect_0_M04_AXI_ARADDR),
.M04_AXI_arburst(axi_interconnect_0_M04_AXI_ARBURST),
.M04_AXI_arcache(axi_interconnect_0_M04_AXI_ARCACHE),
.M04_AXI_arlen(axi_interconnect_0_M04_AXI_ARLEN),
.M04_AXI_arlock(axi_interconnect_0_M04_AXI_ARLOCK),
.M04_AXI_arprot(axi_interconnect_0_M04_AXI_ARPROT),
.M04_AXI_arqos(axi_interconnect_0_M04_AXI_ARQOS),
.M04_AXI_arready(axi_interconnect_0_M04_AXI_ARREADY),
.M04_AXI_arsize(axi_interconnect_0_M04_AXI_ARSIZE),
.M04_AXI_arvalid(axi_interconnect_0_M04_AXI_ARVALID),
.M04_AXI_awaddr(axi_interconnect_0_M04_AXI_AWADDR),
.M04_AXI_awburst(axi_interconnect_0_M04_AXI_AWBURST),
.M04_AXI_awcache(axi_interconnect_0_M04_AXI_AWCACHE),
.M04_AXI_awlen(axi_interconnect_0_M04_AXI_AWLEN),
.M04_AXI_awlock(axi_interconnect_0_M04_AXI_AWLOCK),
.M04_AXI_awprot(axi_interconnect_0_M04_AXI_AWPROT),
.M04_AXI_awqos(axi_interconnect_0_M04_AXI_AWQOS),
.M04_AXI_awready(axi_interconnect_0_M04_AXI_AWREADY),
.M04_AXI_awsize(axi_interconnect_0_M04_AXI_AWSIZE),
.M04_AXI_awvalid(axi_interconnect_0_M04_AXI_AWVALID),
.M04_AXI_bready(axi_interconnect_0_M04_AXI_BREADY),
.M04_AXI_bresp(axi_interconnect_0_M04_AXI_BRESP),
.M04_AXI_bvalid(axi_interconnect_0_M04_AXI_BVALID),
.M04_AXI_rdata(axi_interconnect_0_M04_AXI_RDATA),
.M04_AXI_rlast(axi_interconnect_0_M04_AXI_RLAST),
.M04_AXI_rready(axi_interconnect_0_M04_AXI_RREADY),
.M04_AXI_rresp(axi_interconnect_0_M04_AXI_RRESP),
.M04_AXI_rvalid(axi_interconnect_0_M04_AXI_RVALID),
.M04_AXI_wdata(axi_interconnect_0_M04_AXI_WDATA),
.M04_AXI_wlast(axi_interconnect_0_M04_AXI_WLAST),
.M04_AXI_wready(axi_interconnect_0_M04_AXI_WREADY),
.M04_AXI_wstrb(axi_interconnect_0_M04_AXI_WSTRB),
.M04_AXI_wvalid(axi_interconnect_0_M04_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID),
.S01_ACLK(processing_system7_0_FCLK_CLK0),
.S01_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.S01_AXI_araddr(1'b0),
.S01_AXI_arburst(1'b0),
.S01_AXI_arcache(1'b0),
.S01_AXI_arid(1'b0),
.S01_AXI_arlen(1'b0),
.S01_AXI_arlock(1'b0),
.S01_AXI_arprot(1'b0),
.S01_AXI_arqos(1'b0),
.S01_AXI_arsize(1'b0),
.S01_AXI_arvalid(1'b0),
.S01_AXI_awaddr(1'b0),
.S01_AXI_awburst(1'b0),
.S01_AXI_awcache(1'b0),
.S01_AXI_awid(1'b0),
.S01_AXI_awlen(1'b0),
.S01_AXI_awlock(1'b0),
.S01_AXI_awprot(1'b0),
.S01_AXI_awqos(1'b0),
.S01_AXI_awsize(1'b0),
.S01_AXI_awvalid(1'b0),
.S01_AXI_bready(1'b0),
.S01_AXI_rready(1'b0),
.S01_AXI_wdata(1'b0),
.S01_AXI_wlast(1'b0),
.S01_AXI_wstrb(1'b0),
.S01_AXI_wvalid(1'b0));
image_processing_2d_design_dragster_configurator_0_0 dragster_configurator_0
(.clk(processing_system7_0_FCLK_CLK2),
.miso(LINESCANNER_MISO_1),
.mosi(dragster_configurator_0_mosi),
.reset_n(proc_sys_reset_0_peripheral_aresetn),
.sclk(dragster_configurator_0_sclk),
.ss_n(dragster_configurator_0_ss_n));
image_processing_2d_design_frequency_analyzer_manager_0_1 frequency_analyzer_manager_0
(.clear(image_capture_manager_0_clear_memory),
.data(linescanner_image_capture_unit_0_pixel_data),
.irq(frequency_analyzer_manager_1_irq),
.pixel_clock(linescanner_image_capture_unit_0_pixel_captured),
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
.s00_axi_araddr(axi_interconnect_0_M02_AXI_ARADDR[9:0]),
.s00_axi_aresetn(proc_sys_reset_0_peripheral_aresetn),
.s00_axi_arprot(axi_interconnect_0_M02_AXI_ARPROT),
.s00_axi_arready(axi_interconnect_0_M02_AXI_ARREADY),
.s00_axi_arvalid(axi_interconnect_0_M02_AXI_ARVALID),
.s00_axi_awaddr(axi_interconnect_0_M02_AXI_AWADDR[9:0]),
.s00_axi_awprot(axi_interconnect_0_M02_AXI_AWPROT),
.s00_axi_awready(axi_interconnect_0_M02_AXI_AWREADY),
.s00_axi_awvalid(axi_interconnect_0_M02_AXI_AWVALID),
.s00_axi_bready(axi_interconnect_0_M02_AXI_BREADY),
.s00_axi_bresp(axi_interconnect_0_M02_AXI_BRESP),
.s00_axi_bvalid(axi_interconnect_0_M02_AXI_BVALID),
.s00_axi_rdata(axi_interconnect_0_M02_AXI_RDATA),
.s00_axi_rready(axi_interconnect_0_M02_AXI_RREADY),
.s00_axi_rresp(axi_interconnect_0_M02_AXI_RRESP),
.s00_axi_rvalid(axi_interconnect_0_M02_AXI_RVALID),
.s00_axi_wdata(axi_interconnect_0_M02_AXI_WDATA),
.s00_axi_wready(axi_interconnect_0_M02_AXI_WREADY),
.s00_axi_wstrb(axi_interconnect_0_M02_AXI_WSTRB),
.s00_axi_wvalid(axi_interconnect_0_M02_AXI_WVALID),
.start(frequency_analyzer_synch_0_start_analyzer_0),
.stop(frequency_analyzer_synch_0_stop_analyzer_0));
image_processing_2d_design_frequency_analyzer_manager_1_0 frequency_analyzer_manager_1
(.clear(image_capture_manager_0_clear_memory),
.data(linescanner_image_capture_unit_1_pixel_data),
.irq(frequency_analyzer_manager_0_irq),
.pixel_clock(linescanner_image_capture_unit_1_pixel_captured),
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
.s00_axi_araddr(axi_interconnect_0_M03_AXI_ARADDR[9:0]),
.s00_axi_aresetn(proc_sys_reset_0_peripheral_aresetn),
.s00_axi_arprot(axi_interconnect_0_M03_AXI_ARPROT),
.s00_axi_arready(axi_interconnect_0_M03_AXI_ARREADY),
.s00_axi_arvalid(axi_interconnect_0_M03_AXI_ARVALID),
.s00_axi_awaddr(axi_interconnect_0_M03_AXI_AWADDR[9:0]),
.s00_axi_awprot(axi_interconnect_0_M03_AXI_AWPROT),
.s00_axi_awready(axi_interconnect_0_M03_AXI_AWREADY),
.s00_axi_awvalid(axi_interconnect_0_M03_AXI_AWVALID),
.s00_axi_bready(axi_interconnect_0_M03_AXI_BREADY),
.s00_axi_bresp(axi_interconnect_0_M03_AXI_BRESP),
.s00_axi_bvalid(axi_interconnect_0_M03_AXI_BVALID),
.s00_axi_rdata(axi_interconnect_0_M03_AXI_RDATA),
.s00_axi_rready(axi_interconnect_0_M03_AXI_RREADY),
.s00_axi_rresp(axi_interconnect_0_M03_AXI_RRESP),
.s00_axi_rvalid(axi_interconnect_0_M03_AXI_RVALID),
.s00_axi_wdata(axi_interconnect_0_M03_AXI_WDATA),
.s00_axi_wready(axi_interconnect_0_M03_AXI_WREADY),
.s00_axi_wstrb(axi_interconnect_0_M03_AXI_WSTRB),
.s00_axi_wvalid(axi_interconnect_0_M03_AXI_WVALID),
.start(frequency_analyzer_synch_0_start_analyzer_1),
.stop(frequency_analyzer_synch_0_stop_analyzer_1));
image_processing_2d_design_frequency_analyzer_synch_0_0 frequency_analyzer_synch_0
(.clock(processing_system7_0_FCLK_CLK0),
.enable(image_capture_manager_0_image_capture_enabled),
.reset(proc_sys_reset_0_peripheral_aresetn),
.start_analyzer_0(frequency_analyzer_synch_0_start_analyzer_0),
.start_analyzer_1(frequency_analyzer_synch_0_start_analyzer_1),
.stop_analyzer_0(frequency_analyzer_synch_0_stop_analyzer_0),
.stop_analyzer_1(frequency_analyzer_synch_0_stop_analyzer_1));
image_processing_2d_design_image_capture_manager_0_0 image_capture_manager_0
(.clear_memory(image_capture_manager_0_clear_memory),
.image_capture_enabled(image_capture_manager_0_image_capture_enabled),
.reset(image_capture_manager_0_reset),
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
.s00_axi_araddr(axi_interconnect_0_M01_AXI_ARADDR[3:0]),
.s00_axi_aresetn(proc_sys_reset_0_peripheral_aresetn),
.s00_axi_arprot(axi_interconnect_0_M01_AXI_ARPROT),
.s00_axi_arready(axi_interconnect_0_M01_AXI_ARREADY),
.s00_axi_arvalid(axi_interconnect_0_M01_AXI_ARVALID),
.s00_axi_awaddr(axi_interconnect_0_M01_AXI_AWADDR[3:0]),
.s00_axi_awprot(axi_interconnect_0_M01_AXI_AWPROT),
.s00_axi_awready(axi_interconnect_0_M01_AXI_AWREADY),
.s00_axi_awvalid(axi_interconnect_0_M01_AXI_AWVALID),
.s00_axi_bready(axi_interconnect_0_M01_AXI_BREADY),
.s00_axi_bresp(axi_interconnect_0_M01_AXI_BRESP),
.s00_axi_bvalid(axi_interconnect_0_M01_AXI_BVALID),
.s00_axi_rdata(axi_interconnect_0_M01_AXI_RDATA),
.s00_axi_rready(axi_interconnect_0_M01_AXI_RREADY),
.s00_axi_rresp(axi_interconnect_0_M01_AXI_RRESP),
.s00_axi_rvalid(axi_interconnect_0_M01_AXI_RVALID),
.s00_axi_wdata(axi_interconnect_0_M01_AXI_WDATA),
.s00_axi_wready(axi_interconnect_0_M01_AXI_WREADY),
.s00_axi_wstrb(axi_interconnect_0_M01_AXI_WSTRB),
.s00_axi_wvalid(axi_interconnect_0_M01_AXI_WVALID));
image_processing_2d_design_linescanner_image_capture_unit_0_1 linescanner_image_capture_unit_0
(.data(LINESCANNER0_DATA_1),
.enable(image_capture_manager_0_image_capture_enabled),
.end_adc(LINESCANNER0_END_ADC_1),
.load_pulse(linescanner_image_capture_unit_0_load_pulse),
.lval(LINESCANNER0_LVAL_1),
.main_clock(linescanner_image_capture_unit_0_main_clock),
.main_clock_source(processing_system7_0_FCLK_CLK1),
.n_reset(proc_sys_reset_0_peripheral_aresetn),
.pixel_captured(linescanner_image_capture_unit_0_pixel_captured),
.pixel_clock(LINESCANNER0_PIXEL_CLOCK_1),
.pixel_data(linescanner_image_capture_unit_0_pixel_data),
.rst_cds(linescanner_image_capture_unit_0_rst_cds),
.rst_cvc(linescanner_image_capture_unit_0_rst_cvc),
.sample(linescanner_image_capture_unit_0_sample));
image_processing_2d_design_linescanner_image_capture_unit_1_1 linescanner_image_capture_unit_1
(.data(LINESCANNER1_DATA_1),
.enable(image_capture_manager_0_image_capture_enabled),
.end_adc(LINESCANNER1_END_ADC_1),
.load_pulse(linescanner_image_capture_unit_1_load_pulse),
.lval(LINESCANNER1_LVAL_1),
.main_clock(linescanner_image_capture_unit_1_main_clock),
.main_clock_source(processing_system7_0_FCLK_CLK1),
.n_reset(proc_sys_reset_0_peripheral_aresetn),
.pixel_captured(linescanner_image_capture_unit_1_pixel_captured),
.pixel_clock(LINESCANNER1_PIXEL_CLOCK_1),
.pixel_data(linescanner_image_capture_unit_1_pixel_data),
.rst_cds(linescanner_image_capture_unit_1_rst_cds),
.rst_cvc(linescanner_image_capture_unit_1_rst_cvc),
.sample(linescanner_image_capture_unit_1_sample));
image_processing_2d_design_not_1bit_0_0 not_1bit_0
(.inp(proc_sys_reset_0_peripheral_reset),
.outp(proc_sys_reset_0_peripheral_aresetn));
image_processing_2d_design_proc_sys_reset_0_1 proc_sys_reset_0
(.aux_reset_in(image_capture_manager_0_reset),
.dcm_locked(1'b1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.mb_debug_sys_rst(1'b0),
.peripheral_reset(proc_sys_reset_0_peripheral_reset),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
image_processing_2d_design_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_CLK1(processing_system7_0_FCLK_CLK1),
.FCLK_CLK2(processing_system7_0_FCLK_CLK2),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.GPIO_I({1'b0,1'b0,1'b0,1'b0}),
.IRQ_F2P(xlconcat_0_dout),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.S_AXI_HP0_ACLK(processing_system7_0_FCLK_CLK0),
.S_AXI_HP0_ARADDR(axi_interconnect_0_M04_AXI_ARADDR),
.S_AXI_HP0_ARBURST(axi_interconnect_0_M04_AXI_ARBURST),
.S_AXI_HP0_ARCACHE(axi_interconnect_0_M04_AXI_ARCACHE),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN(axi_interconnect_0_M04_AXI_ARLEN),
.S_AXI_HP0_ARLOCK(axi_interconnect_0_M04_AXI_ARLOCK),
.S_AXI_HP0_ARPROT(axi_interconnect_0_M04_AXI_ARPROT),
.S_AXI_HP0_ARQOS(axi_interconnect_0_M04_AXI_ARQOS),
.S_AXI_HP0_ARREADY(axi_interconnect_0_M04_AXI_ARREADY),
.S_AXI_HP0_ARSIZE(axi_interconnect_0_M04_AXI_ARSIZE),
.S_AXI_HP0_ARVALID(axi_interconnect_0_M04_AXI_ARVALID),
.S_AXI_HP0_AWADDR(axi_interconnect_0_M04_AXI_AWADDR),
.S_AXI_HP0_AWBURST(axi_interconnect_0_M04_AXI_AWBURST),
.S_AXI_HP0_AWCACHE(axi_interconnect_0_M04_AXI_AWCACHE),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN(axi_interconnect_0_M04_AXI_AWLEN),
.S_AXI_HP0_AWLOCK(axi_interconnect_0_M04_AXI_AWLOCK),
.S_AXI_HP0_AWPROT(axi_interconnect_0_M04_AXI_AWPROT),
.S_AXI_HP0_AWQOS(axi_interconnect_0_M04_AXI_AWQOS),
.S_AXI_HP0_AWREADY(axi_interconnect_0_M04_AXI_AWREADY),
.S_AXI_HP0_AWSIZE(axi_interconnect_0_M04_AXI_AWSIZE),
.S_AXI_HP0_AWVALID(axi_interconnect_0_M04_AXI_AWVALID),
.S_AXI_HP0_BREADY(axi_interconnect_0_M04_AXI_BREADY),
.S_AXI_HP0_BRESP(axi_interconnect_0_M04_AXI_BRESP),
.S_AXI_HP0_BVALID(axi_interconnect_0_M04_AXI_BVALID),
.S_AXI_HP0_RDATA(axi_interconnect_0_M04_AXI_RDATA),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RLAST(axi_interconnect_0_M04_AXI_RLAST),
.S_AXI_HP0_RREADY(axi_interconnect_0_M04_AXI_RREADY),
.S_AXI_HP0_RRESP(axi_interconnect_0_M04_AXI_RRESP),
.S_AXI_HP0_RVALID(axi_interconnect_0_M04_AXI_RVALID),
.S_AXI_HP0_WDATA(axi_interconnect_0_M04_AXI_WDATA),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(axi_interconnect_0_M04_AXI_WLAST),
.S_AXI_HP0_WREADY(axi_interconnect_0_M04_AXI_WREADY),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB(axi_interconnect_0_M04_AXI_WSTRB),
.S_AXI_HP0_WVALID(axi_interconnect_0_M04_AXI_WVALID));
image_processing_2d_design_xlconcat_0_0 xlconcat_0
(.In0(frequency_analyzer_manager_1_irq),
.In1(frequency_analyzer_manager_0_irq),
.dout(xlconcat_0_dout));
endmodule |
module image_processing_2d_design_axi_interconnect_0_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arregion,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awregion,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arprot,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awprot,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arprot,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awprot,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wstrb,
M02_AXI_wvalid,
M03_ACLK,
M03_ARESETN,
M03_AXI_araddr,
M03_AXI_arprot,
M03_AXI_arready,
M03_AXI_arvalid,
M03_AXI_awaddr,
M03_AXI_awprot,
M03_AXI_awready,
M03_AXI_awvalid,
M03_AXI_bready,
M03_AXI_bresp,
M03_AXI_bvalid,
M03_AXI_rdata,
M03_AXI_rready,
M03_AXI_rresp,
M03_AXI_rvalid,
M03_AXI_wdata,
M03_AXI_wready,
M03_AXI_wstrb,
M03_AXI_wvalid,
M04_ACLK,
M04_ARESETN,
M04_AXI_araddr,
M04_AXI_arburst,
M04_AXI_arcache,
M04_AXI_arlen,
M04_AXI_arlock,
M04_AXI_arprot,
M04_AXI_arqos,
M04_AXI_arready,
M04_AXI_arsize,
M04_AXI_arvalid,
M04_AXI_awaddr,
M04_AXI_awburst,
M04_AXI_awcache,
M04_AXI_awlen,
M04_AXI_awlock,
M04_AXI_awprot,
M04_AXI_awqos,
M04_AXI_awready,
M04_AXI_awsize,
M04_AXI_awvalid,
M04_AXI_bready,
M04_AXI_bresp,
M04_AXI_bvalid,
M04_AXI_rdata,
M04_AXI_rlast,
M04_AXI_rready,
M04_AXI_rresp,
M04_AXI_rvalid,
M04_AXI_wdata,
M04_AXI_wlast,
M04_AXI_wready,
M04_AXI_wstrb,
M04_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid,
S01_ACLK,
S01_ARESETN,
S01_AXI_araddr,
S01_AXI_arburst,
S01_AXI_arcache,
S01_AXI_arid,
S01_AXI_arlen,
S01_AXI_arlock,
S01_AXI_arprot,
S01_AXI_arqos,
S01_AXI_arready,
S01_AXI_arsize,
S01_AXI_arvalid,
S01_AXI_awaddr,
S01_AXI_awburst,
S01_AXI_awcache,
S01_AXI_awid,
S01_AXI_awlen,
S01_AXI_awlock,
S01_AXI_awprot,
S01_AXI_awqos,
S01_AXI_awready,
S01_AXI_awsize,
S01_AXI_awvalid,
S01_AXI_bid,
S01_AXI_bready,
S01_AXI_bresp,
S01_AXI_bvalid,
S01_AXI_rdata,
S01_AXI_rid,
S01_AXI_rlast,
S01_AXI_rready,
S01_AXI_rresp,
S01_AXI_rvalid,
S01_AXI_wdata,
S01_AXI_wlast,
S01_AXI_wready,
S01_AXI_wstrb,
S01_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output M00_AXI_araddr;
output M00_AXI_arburst;
output M00_AXI_arcache;
output M00_AXI_arlen;
output M00_AXI_arlock;
output M00_AXI_arprot;
output M00_AXI_arqos;
input M00_AXI_arready;
output M00_AXI_arregion;
output M00_AXI_arsize;
output M00_AXI_arvalid;
output M00_AXI_awaddr;
output M00_AXI_awburst;
output M00_AXI_awcache;
output M00_AXI_awlen;
output M00_AXI_awlock;
output M00_AXI_awprot;
output M00_AXI_awqos;
input M00_AXI_awready;
output M00_AXI_awregion;
output M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input M00_AXI_bresp;
input M00_AXI_bvalid;
input M00_AXI_rdata;
input M00_AXI_rlast;
output M00_AXI_rready;
input M00_AXI_rresp;
input M00_AXI_rvalid;
output M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output M00_AXI_wstrb;
output M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [31:0]M01_AXI_araddr;
output [2:0]M01_AXI_arprot;
input M01_AXI_arready;
output M01_AXI_arvalid;
output [31:0]M01_AXI_awaddr;
output [2:0]M01_AXI_awprot;
input M01_AXI_awready;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [31:0]M02_AXI_araddr;
output [2:0]M02_AXI_arprot;
input M02_AXI_arready;
output M02_AXI_arvalid;
output [31:0]M02_AXI_awaddr;
output [2:0]M02_AXI_awprot;
input M02_AXI_awready;
output M02_AXI_awvalid;
output M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input M02_AXI_wready;
output [3:0]M02_AXI_wstrb;
output M02_AXI_wvalid;
input M03_ACLK;
input [0:0]M03_ARESETN;
output [31:0]M03_AXI_araddr;
output [2:0]M03_AXI_arprot;
input M03_AXI_arready;
output M03_AXI_arvalid;
output [31:0]M03_AXI_awaddr;
output [2:0]M03_AXI_awprot;
input M03_AXI_awready;
output M03_AXI_awvalid;
output M03_AXI_bready;
input [1:0]M03_AXI_bresp;
input M03_AXI_bvalid;
input [31:0]M03_AXI_rdata;
output M03_AXI_rready;
input [1:0]M03_AXI_rresp;
input M03_AXI_rvalid;
output [31:0]M03_AXI_wdata;
input M03_AXI_wready;
output [3:0]M03_AXI_wstrb;
output M03_AXI_wvalid;
input M04_ACLK;
input [0:0]M04_ARESETN;
output [31:0]M04_AXI_araddr;
output [1:0]M04_AXI_arburst;
output [3:0]M04_AXI_arcache;
output [3:0]M04_AXI_arlen;
output [1:0]M04_AXI_arlock;
output [2:0]M04_AXI_arprot;
output [3:0]M04_AXI_arqos;
input M04_AXI_arready;
output [2:0]M04_AXI_arsize;
output M04_AXI_arvalid;
output [31:0]M04_AXI_awaddr;
output [1:0]M04_AXI_awburst;
output [3:0]M04_AXI_awcache;
output [3:0]M04_AXI_awlen;
output [1:0]M04_AXI_awlock;
output [2:0]M04_AXI_awprot;
output [3:0]M04_AXI_awqos;
input M04_AXI_awready;
output [2:0]M04_AXI_awsize;
output M04_AXI_awvalid;
output M04_AXI_bready;
input [1:0]M04_AXI_bresp;
input M04_AXI_bvalid;
input [31:0]M04_AXI_rdata;
input M04_AXI_rlast;
output M04_AXI_rready;
input [1:0]M04_AXI_rresp;
input M04_AXI_rvalid;
output [31:0]M04_AXI_wdata;
output M04_AXI_wlast;
input M04_AXI_wready;
output [3:0]M04_AXI_wstrb;
output M04_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
input S01_ACLK;
input [0:0]S01_ARESETN;
input S01_AXI_araddr;
input S01_AXI_arburst;
input S01_AXI_arcache;
input S01_AXI_arid;
input S01_AXI_arlen;
input S01_AXI_arlock;
input S01_AXI_arprot;
input S01_AXI_arqos;
output S01_AXI_arready;
input S01_AXI_arsize;
input S01_AXI_arvalid;
input S01_AXI_awaddr;
input S01_AXI_awburst;
input S01_AXI_awcache;
input S01_AXI_awid;
input S01_AXI_awlen;
input S01_AXI_awlock;
input S01_AXI_awprot;
input S01_AXI_awqos;
output S01_AXI_awready;
input S01_AXI_awsize;
input S01_AXI_awvalid;
output S01_AXI_bid;
input S01_AXI_bready;
output S01_AXI_bresp;
output S01_AXI_bvalid;
output S01_AXI_rdata;
output S01_AXI_rid;
output S01_AXI_rlast;
input S01_AXI_rready;
output S01_AXI_rresp;
output S01_AXI_rvalid;
input S01_AXI_wdata;
input S01_AXI_wlast;
output S01_AXI_wready;
input S01_AXI_wstrb;
input S01_AXI_wvalid;
wire axi_interconnect_0_ACLK_net;
wire [0:0]axi_interconnect_0_ARESETN_net;
wire [31:0]axi_interconnect_0_to_s00_couplers_ARADDR;
wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;
wire [11:0]axi_interconnect_0_to_s00_couplers_ARID;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARLEN;
wire [1:0]axi_interconnect_0_to_s00_couplers_ARLOCK;
wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;
wire axi_interconnect_0_to_s00_couplers_ARREADY;
wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;
wire axi_interconnect_0_to_s00_couplers_ARVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_AWADDR;
wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;
wire [11:0]axi_interconnect_0_to_s00_couplers_AWID;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWLEN;
wire [1:0]axi_interconnect_0_to_s00_couplers_AWLOCK;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;
wire axi_interconnect_0_to_s00_couplers_AWREADY;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;
wire axi_interconnect_0_to_s00_couplers_AWVALID;
wire [11:0]axi_interconnect_0_to_s00_couplers_BID;
wire axi_interconnect_0_to_s00_couplers_BREADY;
wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;
wire axi_interconnect_0_to_s00_couplers_BVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_RDATA;
wire [11:0]axi_interconnect_0_to_s00_couplers_RID;
wire axi_interconnect_0_to_s00_couplers_RLAST;
wire axi_interconnect_0_to_s00_couplers_RREADY;
wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;
wire axi_interconnect_0_to_s00_couplers_RVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_WDATA;
wire [11:0]axi_interconnect_0_to_s00_couplers_WID;
wire axi_interconnect_0_to_s00_couplers_WLAST;
wire axi_interconnect_0_to_s00_couplers_WREADY;
wire [3:0]axi_interconnect_0_to_s00_couplers_WSTRB;
wire axi_interconnect_0_to_s00_couplers_WVALID;
wire axi_interconnect_0_to_s01_couplers_ARADDR;
wire axi_interconnect_0_to_s01_couplers_ARBURST;
wire axi_interconnect_0_to_s01_couplers_ARCACHE;
wire axi_interconnect_0_to_s01_couplers_ARID;
wire axi_interconnect_0_to_s01_couplers_ARLEN;
wire axi_interconnect_0_to_s01_couplers_ARLOCK;
wire axi_interconnect_0_to_s01_couplers_ARPROT;
wire axi_interconnect_0_to_s01_couplers_ARQOS;
wire axi_interconnect_0_to_s01_couplers_ARREADY;
wire axi_interconnect_0_to_s01_couplers_ARSIZE;
wire axi_interconnect_0_to_s01_couplers_ARVALID;
wire axi_interconnect_0_to_s01_couplers_AWADDR;
wire axi_interconnect_0_to_s01_couplers_AWBURST;
wire axi_interconnect_0_to_s01_couplers_AWCACHE;
wire axi_interconnect_0_to_s01_couplers_AWID;
wire axi_interconnect_0_to_s01_couplers_AWLEN;
wire axi_interconnect_0_to_s01_couplers_AWLOCK;
wire axi_interconnect_0_to_s01_couplers_AWPROT;
wire axi_interconnect_0_to_s01_couplers_AWQOS;
wire axi_interconnect_0_to_s01_couplers_AWREADY;
wire axi_interconnect_0_to_s01_couplers_AWSIZE;
wire axi_interconnect_0_to_s01_couplers_AWVALID;
wire axi_interconnect_0_to_s01_couplers_BID;
wire axi_interconnect_0_to_s01_couplers_BREADY;
wire axi_interconnect_0_to_s01_couplers_BRESP;
wire axi_interconnect_0_to_s01_couplers_BVALID;
wire axi_interconnect_0_to_s01_couplers_RDATA;
wire axi_interconnect_0_to_s01_couplers_RID;
wire axi_interconnect_0_to_s01_couplers_RLAST;
wire axi_interconnect_0_to_s01_couplers_RREADY;
wire axi_interconnect_0_to_s01_couplers_RRESP;
wire axi_interconnect_0_to_s01_couplers_RVALID;
wire axi_interconnect_0_to_s01_couplers_WDATA;
wire axi_interconnect_0_to_s01_couplers_WLAST;
wire axi_interconnect_0_to_s01_couplers_WREADY;
wire axi_interconnect_0_to_s01_couplers_WSTRB;
wire axi_interconnect_0_to_s01_couplers_WVALID;
wire m00_couplers_to_axi_interconnect_0_ARADDR;
wire m00_couplers_to_axi_interconnect_0_ARBURST;
wire m00_couplers_to_axi_interconnect_0_ARCACHE;
wire m00_couplers_to_axi_interconnect_0_ARLEN;
wire m00_couplers_to_axi_interconnect_0_ARLOCK;
wire m00_couplers_to_axi_interconnect_0_ARPROT;
wire m00_couplers_to_axi_interconnect_0_ARQOS;
wire m00_couplers_to_axi_interconnect_0_ARREADY;
wire m00_couplers_to_axi_interconnect_0_ARREGION;
wire m00_couplers_to_axi_interconnect_0_ARSIZE;
wire m00_couplers_to_axi_interconnect_0_ARVALID;
wire m00_couplers_to_axi_interconnect_0_AWADDR;
wire m00_couplers_to_axi_interconnect_0_AWBURST;
wire m00_couplers_to_axi_interconnect_0_AWCACHE;
wire m00_couplers_to_axi_interconnect_0_AWLEN;
wire m00_couplers_to_axi_interconnect_0_AWLOCK;
wire m00_couplers_to_axi_interconnect_0_AWPROT;
wire m00_couplers_to_axi_interconnect_0_AWQOS;
wire m00_couplers_to_axi_interconnect_0_AWREADY;
wire m00_couplers_to_axi_interconnect_0_AWREGION;
wire m00_couplers_to_axi_interconnect_0_AWSIZE;
wire m00_couplers_to_axi_interconnect_0_AWVALID;
wire m00_couplers_to_axi_interconnect_0_BREADY;
wire m00_couplers_to_axi_interconnect_0_BRESP;
wire m00_couplers_to_axi_interconnect_0_BVALID;
wire m00_couplers_to_axi_interconnect_0_RDATA;
wire m00_couplers_to_axi_interconnect_0_RLAST;
wire m00_couplers_to_axi_interconnect_0_RREADY;
wire m00_couplers_to_axi_interconnect_0_RRESP;
wire m00_couplers_to_axi_interconnect_0_RVALID;
wire m00_couplers_to_axi_interconnect_0_WDATA;
wire m00_couplers_to_axi_interconnect_0_WLAST;
wire m00_couplers_to_axi_interconnect_0_WREADY;
wire m00_couplers_to_axi_interconnect_0_WSTRB;
wire m00_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]m01_couplers_to_axi_interconnect_0_ARADDR;
wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;
wire m01_couplers_to_axi_interconnect_0_ARREADY;
wire m01_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m01_couplers_to_axi_interconnect_0_AWADDR;
wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;
wire m01_couplers_to_axi_interconnect_0_AWREADY;
wire m01_couplers_to_axi_interconnect_0_AWVALID;
wire m01_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;
wire m01_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m01_couplers_to_axi_interconnect_0_RDATA;
wire m01_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;
wire m01_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m01_couplers_to_axi_interconnect_0_WDATA;
wire m01_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]m01_couplers_to_axi_interconnect_0_WSTRB;
wire m01_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_ARADDR;
wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;
wire m02_couplers_to_axi_interconnect_0_ARREADY;
wire m02_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_AWADDR;
wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;
wire m02_couplers_to_axi_interconnect_0_AWREADY;
wire m02_couplers_to_axi_interconnect_0_AWVALID;
wire m02_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;
wire m02_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_RDATA;
wire m02_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;
wire m02_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_WDATA;
wire m02_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]m02_couplers_to_axi_interconnect_0_WSTRB;
wire m02_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]m03_couplers_to_axi_interconnect_0_ARADDR;
wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;
wire m03_couplers_to_axi_interconnect_0_ARREADY;
wire m03_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m03_couplers_to_axi_interconnect_0_AWADDR;
wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;
wire m03_couplers_to_axi_interconnect_0_AWREADY;
wire m03_couplers_to_axi_interconnect_0_AWVALID;
wire m03_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;
wire m03_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m03_couplers_to_axi_interconnect_0_RDATA;
wire m03_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;
wire m03_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m03_couplers_to_axi_interconnect_0_WDATA;
wire m03_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]m03_couplers_to_axi_interconnect_0_WSTRB;
wire m03_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_ARADDR;
wire [1:0]m04_couplers_to_axi_interconnect_0_ARBURST;
wire [3:0]m04_couplers_to_axi_interconnect_0_ARCACHE;
wire [3:0]m04_couplers_to_axi_interconnect_0_ARLEN;
wire [1:0]m04_couplers_to_axi_interconnect_0_ARLOCK;
wire [2:0]m04_couplers_to_axi_interconnect_0_ARPROT;
wire [3:0]m04_couplers_to_axi_interconnect_0_ARQOS;
wire m04_couplers_to_axi_interconnect_0_ARREADY;
wire [2:0]m04_couplers_to_axi_interconnect_0_ARSIZE;
wire m04_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_AWADDR;
wire [1:0]m04_couplers_to_axi_interconnect_0_AWBURST;
wire [3:0]m04_couplers_to_axi_interconnect_0_AWCACHE;
wire [3:0]m04_couplers_to_axi_interconnect_0_AWLEN;
wire [1:0]m04_couplers_to_axi_interconnect_0_AWLOCK;
wire [2:0]m04_couplers_to_axi_interconnect_0_AWPROT;
wire [3:0]m04_couplers_to_axi_interconnect_0_AWQOS;
wire m04_couplers_to_axi_interconnect_0_AWREADY;
wire [2:0]m04_couplers_to_axi_interconnect_0_AWSIZE;
wire m04_couplers_to_axi_interconnect_0_AWVALID;
wire m04_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m04_couplers_to_axi_interconnect_0_BRESP;
wire m04_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_RDATA;
wire m04_couplers_to_axi_interconnect_0_RLAST;
wire m04_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m04_couplers_to_axi_interconnect_0_RRESP;
wire m04_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_WDATA;
wire m04_couplers_to_axi_interconnect_0_WLAST;
wire m04_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]m04_couplers_to_axi_interconnect_0_WSTRB;
wire m04_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [11:0]s00_couplers_to_xbar_ARID;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [0:0]s00_couplers_to_xbar_ARLOCK;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [3:0]s00_couplers_to_xbar_ARQOS;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [1:0]s00_couplers_to_xbar_AWBURST;
wire [3:0]s00_couplers_to_xbar_AWCACHE;
wire [11:0]s00_couplers_to_xbar_AWID;
wire [7:0]s00_couplers_to_xbar_AWLEN;
wire [0:0]s00_couplers_to_xbar_AWLOCK;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [3:0]s00_couplers_to_xbar_AWQOS;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire [2:0]s00_couplers_to_xbar_AWSIZE;
wire s00_couplers_to_xbar_AWVALID;
wire [12:0]s00_couplers_to_xbar_BID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire [12:0]s00_couplers_to_xbar_RID;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire s00_couplers_to_xbar_WLAST;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire s01_couplers_to_xbar_ARADDR;
wire s01_couplers_to_xbar_ARBURST;
wire s01_couplers_to_xbar_ARCACHE;
wire s01_couplers_to_xbar_ARID;
wire s01_couplers_to_xbar_ARLEN;
wire s01_couplers_to_xbar_ARLOCK;
wire s01_couplers_to_xbar_ARPROT;
wire s01_couplers_to_xbar_ARQOS;
wire [1:1]s01_couplers_to_xbar_ARREADY;
wire s01_couplers_to_xbar_ARSIZE;
wire s01_couplers_to_xbar_ARVALID;
wire s01_couplers_to_xbar_AWADDR;
wire s01_couplers_to_xbar_AWBURST;
wire s01_couplers_to_xbar_AWCACHE;
wire s01_couplers_to_xbar_AWID;
wire s01_couplers_to_xbar_AWLEN;
wire s01_couplers_to_xbar_AWLOCK;
wire s01_couplers_to_xbar_AWPROT;
wire s01_couplers_to_xbar_AWQOS;
wire [1:1]s01_couplers_to_xbar_AWREADY;
wire s01_couplers_to_xbar_AWSIZE;
wire s01_couplers_to_xbar_AWVALID;
wire [25:13]s01_couplers_to_xbar_BID;
wire s01_couplers_to_xbar_BREADY;
wire [3:2]s01_couplers_to_xbar_BRESP;
wire [1:1]s01_couplers_to_xbar_BVALID;
wire [63:32]s01_couplers_to_xbar_RDATA;
wire [25:13]s01_couplers_to_xbar_RID;
wire [1:1]s01_couplers_to_xbar_RLAST;
wire s01_couplers_to_xbar_RREADY;
wire [3:2]s01_couplers_to_xbar_RRESP;
wire [1:1]s01_couplers_to_xbar_RVALID;
wire s01_couplers_to_xbar_WDATA;
wire s01_couplers_to_xbar_WLAST;
wire [1:1]s01_couplers_to_xbar_WREADY;
wire s01_couplers_to_xbar_WSTRB;
wire s01_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire xbar_to_m00_couplers_RDATA;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire [3:2]xbar_to_m01_couplers_ARBURST;
wire [7:4]xbar_to_m01_couplers_ARCACHE;
wire [15:8]xbar_to_m01_couplers_ARLEN;
wire [1:1]xbar_to_m01_couplers_ARLOCK;
wire [5:3]xbar_to_m01_couplers_ARPROT;
wire [7:4]xbar_to_m01_couplers_ARQOS;
wire xbar_to_m01_couplers_ARREADY;
wire [7:4]xbar_to_m01_couplers_ARREGION;
wire [5:3]xbar_to_m01_couplers_ARSIZE;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire [3:2]xbar_to_m01_couplers_AWBURST;
wire [7:4]xbar_to_m01_couplers_AWCACHE;
wire [15:8]xbar_to_m01_couplers_AWLEN;
wire [1:1]xbar_to_m01_couplers_AWLOCK;
wire [5:3]xbar_to_m01_couplers_AWPROT;
wire [7:4]xbar_to_m01_couplers_AWQOS;
wire xbar_to_m01_couplers_AWREADY;
wire [7:4]xbar_to_m01_couplers_AWREGION;
wire [5:3]xbar_to_m01_couplers_AWSIZE;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire xbar_to_m01_couplers_RLAST;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire [1:1]xbar_to_m01_couplers_WLAST;
wire xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire [5:4]xbar_to_m02_couplers_ARBURST;
wire [11:8]xbar_to_m02_couplers_ARCACHE;
wire [23:16]xbar_to_m02_couplers_ARLEN;
wire [2:2]xbar_to_m02_couplers_ARLOCK;
wire [8:6]xbar_to_m02_couplers_ARPROT;
wire [11:8]xbar_to_m02_couplers_ARQOS;
wire xbar_to_m02_couplers_ARREADY;
wire [11:8]xbar_to_m02_couplers_ARREGION;
wire [8:6]xbar_to_m02_couplers_ARSIZE;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire [5:4]xbar_to_m02_couplers_AWBURST;
wire [11:8]xbar_to_m02_couplers_AWCACHE;
wire [23:16]xbar_to_m02_couplers_AWLEN;
wire [2:2]xbar_to_m02_couplers_AWLOCK;
wire [8:6]xbar_to_m02_couplers_AWPROT;
wire [11:8]xbar_to_m02_couplers_AWQOS;
wire xbar_to_m02_couplers_AWREADY;
wire [11:8]xbar_to_m02_couplers_AWREGION;
wire [8:6]xbar_to_m02_couplers_AWSIZE;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire xbar_to_m02_couplers_RLAST;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire [2:2]xbar_to_m02_couplers_WLAST;
wire xbar_to_m02_couplers_WREADY;
wire [11:8]xbar_to_m02_couplers_WSTRB;
wire [2:2]xbar_to_m02_couplers_WVALID;
wire [127:96]xbar_to_m03_couplers_ARADDR;
wire [7:6]xbar_to_m03_couplers_ARBURST;
wire [15:12]xbar_to_m03_couplers_ARCACHE;
wire [31:24]xbar_to_m03_couplers_ARLEN;
wire [3:3]xbar_to_m03_couplers_ARLOCK;
wire [11:9]xbar_to_m03_couplers_ARPROT;
wire [15:12]xbar_to_m03_couplers_ARQOS;
wire xbar_to_m03_couplers_ARREADY;
wire [15:12]xbar_to_m03_couplers_ARREGION;
wire [11:9]xbar_to_m03_couplers_ARSIZE;
wire [3:3]xbar_to_m03_couplers_ARVALID;
wire [127:96]xbar_to_m03_couplers_AWADDR;
wire [7:6]xbar_to_m03_couplers_AWBURST;
wire [15:12]xbar_to_m03_couplers_AWCACHE;
wire [31:24]xbar_to_m03_couplers_AWLEN;
wire [3:3]xbar_to_m03_couplers_AWLOCK;
wire [11:9]xbar_to_m03_couplers_AWPROT;
wire [15:12]xbar_to_m03_couplers_AWQOS;
wire xbar_to_m03_couplers_AWREADY;
wire [15:12]xbar_to_m03_couplers_AWREGION;
wire [11:9]xbar_to_m03_couplers_AWSIZE;
wire [3:3]xbar_to_m03_couplers_AWVALID;
wire [3:3]xbar_to_m03_couplers_BREADY;
wire [1:0]xbar_to_m03_couplers_BRESP;
wire xbar_to_m03_couplers_BVALID;
wire [31:0]xbar_to_m03_couplers_RDATA;
wire xbar_to_m03_couplers_RLAST;
wire [3:3]xbar_to_m03_couplers_RREADY;
wire [1:0]xbar_to_m03_couplers_RRESP;
wire xbar_to_m03_couplers_RVALID;
wire [127:96]xbar_to_m03_couplers_WDATA;
wire [3:3]xbar_to_m03_couplers_WLAST;
wire xbar_to_m03_couplers_WREADY;
wire [15:12]xbar_to_m03_couplers_WSTRB;
wire [3:3]xbar_to_m03_couplers_WVALID;
wire [159:128]xbar_to_m04_couplers_ARADDR;
wire [9:8]xbar_to_m04_couplers_ARBURST;
wire [19:16]xbar_to_m04_couplers_ARCACHE;
wire [39:32]xbar_to_m04_couplers_ARLEN;
wire [4:4]xbar_to_m04_couplers_ARLOCK;
wire [14:12]xbar_to_m04_couplers_ARPROT;
wire [19:16]xbar_to_m04_couplers_ARQOS;
wire xbar_to_m04_couplers_ARREADY;
wire [19:16]xbar_to_m04_couplers_ARREGION;
wire [14:12]xbar_to_m04_couplers_ARSIZE;
wire [4:4]xbar_to_m04_couplers_ARVALID;
wire [159:128]xbar_to_m04_couplers_AWADDR;
wire [9:8]xbar_to_m04_couplers_AWBURST;
wire [19:16]xbar_to_m04_couplers_AWCACHE;
wire [39:32]xbar_to_m04_couplers_AWLEN;
wire [4:4]xbar_to_m04_couplers_AWLOCK;
wire [14:12]xbar_to_m04_couplers_AWPROT;
wire [19:16]xbar_to_m04_couplers_AWQOS;
wire xbar_to_m04_couplers_AWREADY;
wire [19:16]xbar_to_m04_couplers_AWREGION;
wire [14:12]xbar_to_m04_couplers_AWSIZE;
wire [4:4]xbar_to_m04_couplers_AWVALID;
wire [4:4]xbar_to_m04_couplers_BREADY;
wire [1:0]xbar_to_m04_couplers_BRESP;
wire xbar_to_m04_couplers_BVALID;
wire [31:0]xbar_to_m04_couplers_RDATA;
wire xbar_to_m04_couplers_RLAST;
wire [4:4]xbar_to_m04_couplers_RREADY;
wire [1:0]xbar_to_m04_couplers_RRESP;
wire xbar_to_m04_couplers_RVALID;
wire [159:128]xbar_to_m04_couplers_WDATA;
wire [4:4]xbar_to_m04_couplers_WLAST;
wire xbar_to_m04_couplers_WREADY;
wire [19:16]xbar_to_m04_couplers_WSTRB;
wire [4:4]xbar_to_m04_couplers_WVALID;
assign M00_AXI_araddr = m00_couplers_to_axi_interconnect_0_ARADDR;
assign M00_AXI_arburst = m00_couplers_to_axi_interconnect_0_ARBURST;
assign M00_AXI_arcache = m00_couplers_to_axi_interconnect_0_ARCACHE;
assign M00_AXI_arlen = m00_couplers_to_axi_interconnect_0_ARLEN;
assign M00_AXI_arlock = m00_couplers_to_axi_interconnect_0_ARLOCK;
assign M00_AXI_arprot = m00_couplers_to_axi_interconnect_0_ARPROT;
assign M00_AXI_arqos = m00_couplers_to_axi_interconnect_0_ARQOS;
assign M00_AXI_arregion = m00_couplers_to_axi_interconnect_0_ARREGION;
assign M00_AXI_arsize = m00_couplers_to_axi_interconnect_0_ARSIZE;
assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;
assign M00_AXI_awaddr = m00_couplers_to_axi_interconnect_0_AWADDR;
assign M00_AXI_awburst = m00_couplers_to_axi_interconnect_0_AWBURST;
assign M00_AXI_awcache = m00_couplers_to_axi_interconnect_0_AWCACHE;
assign M00_AXI_awlen = m00_couplers_to_axi_interconnect_0_AWLEN;
assign M00_AXI_awlock = m00_couplers_to_axi_interconnect_0_AWLOCK;
assign M00_AXI_awprot = m00_couplers_to_axi_interconnect_0_AWPROT;
assign M00_AXI_awqos = m00_couplers_to_axi_interconnect_0_AWQOS;
assign M00_AXI_awregion = m00_couplers_to_axi_interconnect_0_AWREGION;
assign M00_AXI_awsize = m00_couplers_to_axi_interconnect_0_AWSIZE;
assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;
assign M00_AXI_wdata = m00_couplers_to_axi_interconnect_0_WDATA;
assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;
assign M00_AXI_wstrb = m00_couplers_to_axi_interconnect_0_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;
assign M01_AXI_araddr[31:0] = m01_couplers_to_axi_interconnect_0_ARADDR;
assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;
assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;
assign M01_AXI_awaddr[31:0] = m01_couplers_to_axi_interconnect_0_AWADDR;
assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;
assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;
assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;
assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_axi_interconnect_0_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_axi_interconnect_0_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;
assign M02_AXI_araddr[31:0] = m02_couplers_to_axi_interconnect_0_ARADDR;
assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;
assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;
assign M02_AXI_awaddr[31:0] = m02_couplers_to_axi_interconnect_0_AWADDR;
assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;
assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;
assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;
assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_axi_interconnect_0_WDATA;
assign M02_AXI_wstrb[3:0] = m02_couplers_to_axi_interconnect_0_WSTRB;
assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;
assign M03_AXI_araddr[31:0] = m03_couplers_to_axi_interconnect_0_ARADDR;
assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;
assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;
assign M03_AXI_awaddr[31:0] = m03_couplers_to_axi_interconnect_0_AWADDR;
assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;
assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;
assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;
assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;
assign M03_AXI_wdata[31:0] = m03_couplers_to_axi_interconnect_0_WDATA;
assign M03_AXI_wstrb[3:0] = m03_couplers_to_axi_interconnect_0_WSTRB;
assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;
assign M04_AXI_araddr[31:0] = m04_couplers_to_axi_interconnect_0_ARADDR;
assign M04_AXI_arburst[1:0] = m04_couplers_to_axi_interconnect_0_ARBURST;
assign M04_AXI_arcache[3:0] = m04_couplers_to_axi_interconnect_0_ARCACHE;
assign M04_AXI_arlen[3:0] = m04_couplers_to_axi_interconnect_0_ARLEN;
assign M04_AXI_arlock[1:0] = m04_couplers_to_axi_interconnect_0_ARLOCK;
assign M04_AXI_arprot[2:0] = m04_couplers_to_axi_interconnect_0_ARPROT;
assign M04_AXI_arqos[3:0] = m04_couplers_to_axi_interconnect_0_ARQOS;
assign M04_AXI_arsize[2:0] = m04_couplers_to_axi_interconnect_0_ARSIZE;
assign M04_AXI_arvalid = m04_couplers_to_axi_interconnect_0_ARVALID;
assign M04_AXI_awaddr[31:0] = m04_couplers_to_axi_interconnect_0_AWADDR;
assign M04_AXI_awburst[1:0] = m04_couplers_to_axi_interconnect_0_AWBURST;
assign M04_AXI_awcache[3:0] = m04_couplers_to_axi_interconnect_0_AWCACHE;
assign M04_AXI_awlen[3:0] = m04_couplers_to_axi_interconnect_0_AWLEN;
assign M04_AXI_awlock[1:0] = m04_couplers_to_axi_interconnect_0_AWLOCK;
assign M04_AXI_awprot[2:0] = m04_couplers_to_axi_interconnect_0_AWPROT;
assign M04_AXI_awqos[3:0] = m04_couplers_to_axi_interconnect_0_AWQOS;
assign M04_AXI_awsize[2:0] = m04_couplers_to_axi_interconnect_0_AWSIZE;
assign M04_AXI_awvalid = m04_couplers_to_axi_interconnect_0_AWVALID;
assign M04_AXI_bready = m04_couplers_to_axi_interconnect_0_BREADY;
assign M04_AXI_rready = m04_couplers_to_axi_interconnect_0_RREADY;
assign M04_AXI_wdata[31:0] = m04_couplers_to_axi_interconnect_0_WDATA;
assign M04_AXI_wlast = m04_couplers_to_axi_interconnect_0_WLAST;
assign M04_AXI_wstrb[3:0] = m04_couplers_to_axi_interconnect_0_WSTRB;
assign M04_AXI_wvalid = m04_couplers_to_axi_interconnect_0_WVALID;
assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = axi_interconnect_0_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_interconnect_0_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = axi_interconnect_0_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;
assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;
assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;
assign S01_AXI_bid = axi_interconnect_0_to_s01_couplers_BID;
assign S01_AXI_bresp = axi_interconnect_0_to_s01_couplers_BRESP;
assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;
assign S01_AXI_rdata = axi_interconnect_0_to_s01_couplers_RDATA;
assign S01_AXI_rid = axi_interconnect_0_to_s01_couplers_RID;
assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;
assign S01_AXI_rresp = axi_interconnect_0_to_s01_couplers_RRESP;
assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;
assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;
assign axi_interconnect_0_ACLK_net = ACLK;
assign axi_interconnect_0_ARESETN_net = ARESETN[0];
assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_interconnect_0_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr;
assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst;
assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache;
assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid;
assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen;
assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock;
assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot;
assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos;
assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize;
assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;
assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr;
assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst;
assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache;
assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid;
assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen;
assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock;
assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot;
assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos;
assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize;
assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;
assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;
assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;
assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata;
assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;
assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb;
assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;
assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp;
assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata;
assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;
assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp;
assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;
assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;
assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;
assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;
assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;
assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;
assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;
assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;
assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;
assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;
assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;
assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];
assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;
assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[31:0];
assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];
assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;
assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;
assign m04_couplers_to_axi_interconnect_0_ARREADY = M04_AXI_arready;
assign m04_couplers_to_axi_interconnect_0_AWREADY = M04_AXI_awready;
assign m04_couplers_to_axi_interconnect_0_BRESP = M04_AXI_bresp[1:0];
assign m04_couplers_to_axi_interconnect_0_BVALID = M04_AXI_bvalid;
assign m04_couplers_to_axi_interconnect_0_RDATA = M04_AXI_rdata[31:0];
assign m04_couplers_to_axi_interconnect_0_RLAST = M04_AXI_rlast;
assign m04_couplers_to_axi_interconnect_0_RRESP = M04_AXI_rresp[1:0];
assign m04_couplers_to_axi_interconnect_0_RVALID = M04_AXI_rvalid;
assign m04_couplers_to_axi_interconnect_0_WREADY = M04_AXI_wready;
m00_couplers_imp_J0QEI9 m00_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),
.M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),
.M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),
.M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),
.M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),
.M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),
.M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),
.M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),
.M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),
.M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),
.M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),
.M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),
.M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),
.M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),
.M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),
.M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),
.M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[0]),
.S_AXI_arburst(xbar_to_m00_couplers_ARBURST[0]),
.S_AXI_arcache(xbar_to_m00_couplers_ARCACHE[0]),
.S_AXI_arlen(xbar_to_m00_couplers_ARLEN[0]),
.S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT[0]),
.S_AXI_arqos(xbar_to_m00_couplers_ARQOS[0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m00_couplers_ARREGION[0]),
.S_AXI_arsize(xbar_to_m00_couplers_ARSIZE[0]),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[0]),
.S_AXI_awburst(xbar_to_m00_couplers_AWBURST[0]),
.S_AXI_awcache(xbar_to_m00_couplers_AWCACHE[0]),
.S_AXI_awlen(xbar_to_m00_couplers_AWLEN[0]),
.S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT[0]),
.S_AXI_awqos(xbar_to_m00_couplers_AWQOS[0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m00_couplers_AWREGION[0]),
.S_AXI_awsize(xbar_to_m00_couplers_AWSIZE[0]),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rlast(xbar_to_m00_couplers_RLAST),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA[0]),
.S_AXI_wlast(xbar_to_m00_couplers_WLAST),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB[0]),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_1M9HB38 m01_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m01_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m01_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m01_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m01_couplers_ARQOS),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m01_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m01_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m01_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m01_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m01_couplers_AWQOS),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m01_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rlast(xbar_to_m01_couplers_RLAST),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wlast(xbar_to_m01_couplers_WLAST),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_1E92BOA m02_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m02_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m02_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m02_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m02_couplers_ARQOS),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m02_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m02_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m02_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m02_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m02_couplers_AWQOS),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m02_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rlast(xbar_to_m02_couplers_RLAST),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wlast(xbar_to_m02_couplers_WLAST),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
m03_couplers_imp_8ZVH8V m03_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m03_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m03_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m03_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m03_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m03_couplers_ARQOS),
.S_AXI_arready(xbar_to_m03_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m03_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m03_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m03_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m03_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m03_couplers_AWQOS),
.S_AXI_awready(xbar_to_m03_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m03_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),
.S_AXI_bready(xbar_to_m03_couplers_BREADY),
.S_AXI_bresp(xbar_to_m03_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m03_couplers_BVALID),
.S_AXI_rdata(xbar_to_m03_couplers_RDATA),
.S_AXI_rlast(xbar_to_m03_couplers_RLAST),
.S_AXI_rready(xbar_to_m03_couplers_RREADY),
.S_AXI_rresp(xbar_to_m03_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m03_couplers_RVALID),
.S_AXI_wdata(xbar_to_m03_couplers_WDATA),
.S_AXI_wlast(xbar_to_m03_couplers_WLAST),
.S_AXI_wready(xbar_to_m03_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m03_couplers_WVALID));
m04_couplers_imp_YN7N1I m04_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m04_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arburst(m04_couplers_to_axi_interconnect_0_ARBURST),
.M_AXI_arcache(m04_couplers_to_axi_interconnect_0_ARCACHE),
.M_AXI_arlen(m04_couplers_to_axi_interconnect_0_ARLEN),
.M_AXI_arlock(m04_couplers_to_axi_interconnect_0_ARLOCK),
.M_AXI_arprot(m04_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arqos(m04_couplers_to_axi_interconnect_0_ARQOS),
.M_AXI_arready(m04_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arsize(m04_couplers_to_axi_interconnect_0_ARSIZE),
.M_AXI_arvalid(m04_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m04_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awburst(m04_couplers_to_axi_interconnect_0_AWBURST),
.M_AXI_awcache(m04_couplers_to_axi_interconnect_0_AWCACHE),
.M_AXI_awlen(m04_couplers_to_axi_interconnect_0_AWLEN),
.M_AXI_awlock(m04_couplers_to_axi_interconnect_0_AWLOCK),
.M_AXI_awprot(m04_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awqos(m04_couplers_to_axi_interconnect_0_AWQOS),
.M_AXI_awready(m04_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awsize(m04_couplers_to_axi_interconnect_0_AWSIZE),
.M_AXI_awvalid(m04_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m04_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m04_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m04_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m04_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rlast(m04_couplers_to_axi_interconnect_0_RLAST),
.M_AXI_rready(m04_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m04_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m04_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m04_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wlast(m04_couplers_to_axi_interconnect_0_WLAST),
.M_AXI_wready(m04_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m04_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m04_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m04_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m04_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m04_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m04_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m04_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m04_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m04_couplers_ARQOS),
.S_AXI_arready(xbar_to_m04_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m04_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m04_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m04_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m04_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m04_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m04_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m04_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m04_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m04_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m04_couplers_AWQOS),
.S_AXI_awready(xbar_to_m04_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m04_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m04_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m04_couplers_AWVALID),
.S_AXI_bready(xbar_to_m04_couplers_BREADY),
.S_AXI_bresp(xbar_to_m04_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m04_couplers_BVALID),
.S_AXI_rdata(xbar_to_m04_couplers_RDATA),
.S_AXI_rlast(xbar_to_m04_couplers_RLAST),
.S_AXI_rready(xbar_to_m04_couplers_RREADY),
.S_AXI_rresp(xbar_to_m04_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m04_couplers_RVALID),
.S_AXI_wdata(xbar_to_m04_couplers_WDATA),
.S_AXI_wlast(xbar_to_m04_couplers_WLAST),
.S_AXI_wready(xbar_to_m04_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m04_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m04_couplers_WVALID));
s00_couplers_imp_1PH4J44 s00_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s00_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),
.M_AXI_arid(s00_couplers_to_xbar_ARID),
.M_AXI_arlen(s00_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s00_couplers_to_xbar_ARQOS),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s00_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),
.M_AXI_awid(s00_couplers_to_xbar_AWID),
.M_AXI_awlen(s00_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s00_couplers_to_xbar_AWQOS),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bid(s00_couplers_to_xbar_BID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rid(s00_couplers_to_xbar_RID),
.M_AXI_rlast(s00_couplers_to_xbar_RLAST),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wlast(s00_couplers_to_xbar_WLAST),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),
.S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),
.S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),
.S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),
.S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),
.S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),
.S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),
.S_AXI_wid(axi_interconnect_0_to_s00_couplers_WID),
.S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),
.S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));
s01_couplers_imp_K956Q9 s01_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(s01_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s01_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),
.M_AXI_arid(s01_couplers_to_xbar_ARID),
.M_AXI_arlen(s01_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s01_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s01_couplers_to_xbar_ARQOS),
.M_AXI_arready(s01_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s01_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),
.M_AXI_awid(s01_couplers_to_xbar_AWID),
.M_AXI_awlen(s01_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s01_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s01_couplers_to_xbar_AWQOS),
.M_AXI_awready(s01_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),
.M_AXI_bid(s01_couplers_to_xbar_BID[13]),
.M_AXI_bready(s01_couplers_to_xbar_BREADY),
.M_AXI_bresp(s01_couplers_to_xbar_BRESP[2]),
.M_AXI_bvalid(s01_couplers_to_xbar_BVALID),
.M_AXI_rdata(s01_couplers_to_xbar_RDATA[32]),
.M_AXI_rid(s01_couplers_to_xbar_RID[13]),
.M_AXI_rlast(s01_couplers_to_xbar_RLAST),
.M_AXI_rready(s01_couplers_to_xbar_RREADY),
.M_AXI_rresp(s01_couplers_to_xbar_RRESP[2]),
.M_AXI_rvalid(s01_couplers_to_xbar_RVALID),
.M_AXI_wdata(s01_couplers_to_xbar_WDATA),
.M_AXI_wlast(s01_couplers_to_xbar_WLAST),
.M_AXI_wready(s01_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s01_couplers_to_xbar_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),
.S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),
.S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),
.S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),
.S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),
.S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),
.S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),
.S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),
.S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),
.S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),
.S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),
.S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),
.S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),
.S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),
.S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),
.S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),
.S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),
.S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),
.S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),
.S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),
.S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),
.S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),
.S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),
.S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),
.S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),
.S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),
.S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),
.S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),
.S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),
.S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),
.S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),
.S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),
.S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),
.S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),
.S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),
.S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),
.S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));
image_processing_2d_design_xbar_0 xbar
(.aclk(axi_interconnect_0_ACLK_net),
.aresetn(axi_interconnect_0_ARESETN_net),
.m_axi_araddr({xbar_to_m04_couplers_ARADDR,xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arburst({xbar_to_m04_couplers_ARBURST,xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),
.m_axi_arcache({xbar_to_m04_couplers_ARCACHE,xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),
.m_axi_arlen({xbar_to_m04_couplers_ARLEN,xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),
.m_axi_arlock({xbar_to_m04_couplers_ARLOCK,xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),
.m_axi_arprot({xbar_to_m04_couplers_ARPROT,xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),
.m_axi_arqos({xbar_to_m04_couplers_ARQOS,xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),
.m_axi_arready({xbar_to_m04_couplers_ARREADY,xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arregion({xbar_to_m04_couplers_ARREGION,xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),
.m_axi_arsize({xbar_to_m04_couplers_ARSIZE,xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),
.m_axi_arvalid({xbar_to_m04_couplers_ARVALID,xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m04_couplers_AWADDR,xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awburst({xbar_to_m04_couplers_AWBURST,xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),
.m_axi_awcache({xbar_to_m04_couplers_AWCACHE,xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),
.m_axi_awlen({xbar_to_m04_couplers_AWLEN,xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),
.m_axi_awlock({xbar_to_m04_couplers_AWLOCK,xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),
.m_axi_awprot({xbar_to_m04_couplers_AWPROT,xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),
.m_axi_awqos({xbar_to_m04_couplers_AWQOS,xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),
.m_axi_awready({xbar_to_m04_couplers_AWREADY,xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awregion({xbar_to_m04_couplers_AWREGION,xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),
.m_axi_awsize({xbar_to_m04_couplers_AWSIZE,xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),
.m_axi_awvalid({xbar_to_m04_couplers_AWVALID,xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m04_couplers_BREADY,xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m04_couplers_BRESP,xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m04_couplers_BVALID,xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m04_couplers_RDATA,xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rlast({xbar_to_m04_couplers_RLAST,xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),
.m_axi_rready({xbar_to_m04_couplers_RREADY,xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m04_couplers_RRESP,xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m04_couplers_RVALID,xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m04_couplers_WDATA,xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wlast({xbar_to_m04_couplers_WLAST,xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),
.m_axi_wready({xbar_to_m04_couplers_WREADY,xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m04_couplers_WSTRB,xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m04_couplers_WVALID,xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr({s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),
.s_axi_arburst({s01_couplers_to_xbar_ARBURST,s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),
.s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s01_couplers_to_xbar_ARCACHE,s01_couplers_to_xbar_ARCACHE,s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),
.s_axi_arid({s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),
.s_axi_arlen({s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),
.s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),
.s_axi_arprot({s01_couplers_to_xbar_ARPROT,s01_couplers_to_xbar_ARPROT,s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),
.s_axi_arqos({s01_couplers_to_xbar_ARQOS,s01_couplers_to_xbar_ARQOS,s01_couplers_to_xbar_ARQOS,s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),
.s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),
.s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s01_couplers_to_xbar_ARSIZE,s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),
.s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),
.s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),
.s_axi_awburst({s01_couplers_to_xbar_AWBURST,s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),
.s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s01_couplers_to_xbar_AWCACHE,s01_couplers_to_xbar_AWCACHE,s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),
.s_axi_awid({s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),
.s_axi_awlen({s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),
.s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),
.s_axi_awprot({s01_couplers_to_xbar_AWPROT,s01_couplers_to_xbar_AWPROT,s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),
.s_axi_awqos({s01_couplers_to_xbar_AWQOS,s01_couplers_to_xbar_AWQOS,s01_couplers_to_xbar_AWQOS,s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),
.s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),
.s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s01_couplers_to_xbar_AWSIZE,s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),
.s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),
.s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),
.s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),
.s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),
.s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),
.s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),
.s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),
.s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),
.s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),
.s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),
.s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),
.s_axi_wdata({s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),
.s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),
.s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),
.s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),
.s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));
endmodule |
module m00_couplers_imp_J0QEI9
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arregion,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awregion,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output M_AXI_araddr;
output M_AXI_arburst;
output M_AXI_arcache;
output M_AXI_arlen;
output M_AXI_arlock;
output M_AXI_arprot;
output M_AXI_arqos;
input M_AXI_arready;
output M_AXI_arregion;
output M_AXI_arsize;
output M_AXI_arvalid;
output M_AXI_awaddr;
output M_AXI_awburst;
output M_AXI_awcache;
output M_AXI_awlen;
output M_AXI_awlock;
output M_AXI_awprot;
output M_AXI_awqos;
input M_AXI_awready;
output M_AXI_awregion;
output M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input M_AXI_bresp;
input M_AXI_bvalid;
input M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input M_AXI_rresp;
input M_AXI_rvalid;
output M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input S_AXI_araddr;
input S_AXI_arburst;
input S_AXI_arcache;
input S_AXI_arlen;
input S_AXI_arlock;
input S_AXI_arprot;
input S_AXI_arqos;
output S_AXI_arready;
input S_AXI_arregion;
input S_AXI_arsize;
input S_AXI_arvalid;
input S_AXI_awaddr;
input S_AXI_awburst;
input S_AXI_awcache;
input S_AXI_awlen;
input S_AXI_awlock;
input S_AXI_awprot;
input S_AXI_awqos;
output S_AXI_awready;
input S_AXI_awregion;
input S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output S_AXI_bresp;
output S_AXI_bvalid;
output S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output S_AXI_rresp;
output S_AXI_rvalid;
input S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input S_AXI_wstrb;
input S_AXI_wvalid;
wire m00_couplers_to_m00_couplers_ARADDR;
wire m00_couplers_to_m00_couplers_ARBURST;
wire m00_couplers_to_m00_couplers_ARCACHE;
wire m00_couplers_to_m00_couplers_ARLEN;
wire m00_couplers_to_m00_couplers_ARLOCK;
wire m00_couplers_to_m00_couplers_ARPROT;
wire m00_couplers_to_m00_couplers_ARQOS;
wire m00_couplers_to_m00_couplers_ARREADY;
wire m00_couplers_to_m00_couplers_ARREGION;
wire m00_couplers_to_m00_couplers_ARSIZE;
wire m00_couplers_to_m00_couplers_ARVALID;
wire m00_couplers_to_m00_couplers_AWADDR;
wire m00_couplers_to_m00_couplers_AWBURST;
wire m00_couplers_to_m00_couplers_AWCACHE;
wire m00_couplers_to_m00_couplers_AWLEN;
wire m00_couplers_to_m00_couplers_AWLOCK;
wire m00_couplers_to_m00_couplers_AWPROT;
wire m00_couplers_to_m00_couplers_AWQOS;
wire m00_couplers_to_m00_couplers_AWREADY;
wire m00_couplers_to_m00_couplers_AWREGION;
wire m00_couplers_to_m00_couplers_AWSIZE;
wire m00_couplers_to_m00_couplers_AWVALID;
wire m00_couplers_to_m00_couplers_BREADY;
wire m00_couplers_to_m00_couplers_BRESP;
wire m00_couplers_to_m00_couplers_BVALID;
wire m00_couplers_to_m00_couplers_RDATA;
wire m00_couplers_to_m00_couplers_RLAST;
wire m00_couplers_to_m00_couplers_RREADY;
wire m00_couplers_to_m00_couplers_RRESP;
wire m00_couplers_to_m00_couplers_RVALID;
wire m00_couplers_to_m00_couplers_WDATA;
wire m00_couplers_to_m00_couplers_WLAST;
wire m00_couplers_to_m00_couplers_WREADY;
wire m00_couplers_to_m00_couplers_WSTRB;
wire m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arburst = m00_couplers_to_m00_couplers_ARBURST;
assign M_AXI_arcache = m00_couplers_to_m00_couplers_ARCACHE;
assign M_AXI_arlen = m00_couplers_to_m00_couplers_ARLEN;
assign M_AXI_arlock = m00_couplers_to_m00_couplers_ARLOCK;
assign M_AXI_arprot = m00_couplers_to_m00_couplers_ARPROT;
assign M_AXI_arqos = m00_couplers_to_m00_couplers_ARQOS;
assign M_AXI_arregion = m00_couplers_to_m00_couplers_ARREGION;
assign M_AXI_arsize = m00_couplers_to_m00_couplers_ARSIZE;
assign M_AXI_arvalid = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awburst = m00_couplers_to_m00_couplers_AWBURST;
assign M_AXI_awcache = m00_couplers_to_m00_couplers_AWCACHE;
assign M_AXI_awlen = m00_couplers_to_m00_couplers_AWLEN;
assign M_AXI_awlock = m00_couplers_to_m00_couplers_AWLOCK;
assign M_AXI_awprot = m00_couplers_to_m00_couplers_AWPROT;
assign M_AXI_awqos = m00_couplers_to_m00_couplers_AWQOS;
assign M_AXI_awregion = m00_couplers_to_m00_couplers_AWREGION;
assign M_AXI_awsize = m00_couplers_to_m00_couplers_AWSIZE;
assign M_AXI_awvalid = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wlast = m00_couplers_to_m00_couplers_WLAST;
assign M_AXI_wstrb = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rlast = m00_couplers_to_m00_couplers_RLAST;
assign S_AXI_rresp = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr;
assign m00_couplers_to_m00_couplers_ARBURST = S_AXI_arburst;
assign m00_couplers_to_m00_couplers_ARCACHE = S_AXI_arcache;
assign m00_couplers_to_m00_couplers_ARLEN = S_AXI_arlen;
assign m00_couplers_to_m00_couplers_ARLOCK = S_AXI_arlock;
assign m00_couplers_to_m00_couplers_ARPROT = S_AXI_arprot;
assign m00_couplers_to_m00_couplers_ARQOS = S_AXI_arqos;
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready;
assign m00_couplers_to_m00_couplers_ARREGION = S_AXI_arregion;
assign m00_couplers_to_m00_couplers_ARSIZE = S_AXI_arsize;
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr;
assign m00_couplers_to_m00_couplers_AWBURST = S_AXI_awburst;
assign m00_couplers_to_m00_couplers_AWCACHE = S_AXI_awcache;
assign m00_couplers_to_m00_couplers_AWLEN = S_AXI_awlen;
assign m00_couplers_to_m00_couplers_AWLOCK = S_AXI_awlock;
assign m00_couplers_to_m00_couplers_AWPROT = S_AXI_awprot;
assign m00_couplers_to_m00_couplers_AWQOS = S_AXI_awqos;
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready;
assign m00_couplers_to_m00_couplers_AWREGION = S_AXI_awregion;
assign m00_couplers_to_m00_couplers_AWSIZE = S_AXI_awsize;
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready;
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp;
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid;
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata;
assign m00_couplers_to_m00_couplers_RLAST = M_AXI_rlast;
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready;
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp;
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid;
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata;
assign m00_couplers_to_m00_couplers_WLAST = S_AXI_wlast;
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb;
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid;
endmodule |
module m01_couplers_imp_1M9HB38
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m01_couplers_ARADDR;
wire [2:0]auto_pc_to_m01_couplers_ARPROT;
wire auto_pc_to_m01_couplers_ARREADY;
wire auto_pc_to_m01_couplers_ARVALID;
wire [31:0]auto_pc_to_m01_couplers_AWADDR;
wire [2:0]auto_pc_to_m01_couplers_AWPROT;
wire auto_pc_to_m01_couplers_AWREADY;
wire auto_pc_to_m01_couplers_AWVALID;
wire auto_pc_to_m01_couplers_BREADY;
wire [1:0]auto_pc_to_m01_couplers_BRESP;
wire auto_pc_to_m01_couplers_BVALID;
wire [31:0]auto_pc_to_m01_couplers_RDATA;
wire auto_pc_to_m01_couplers_RREADY;
wire [1:0]auto_pc_to_m01_couplers_RRESP;
wire auto_pc_to_m01_couplers_RVALID;
wire [31:0]auto_pc_to_m01_couplers_WDATA;
wire auto_pc_to_m01_couplers_WREADY;
wire [3:0]auto_pc_to_m01_couplers_WSTRB;
wire auto_pc_to_m01_couplers_WVALID;
wire [31:0]m01_couplers_to_auto_pc_ARADDR;
wire [1:0]m01_couplers_to_auto_pc_ARBURST;
wire [3:0]m01_couplers_to_auto_pc_ARCACHE;
wire [7:0]m01_couplers_to_auto_pc_ARLEN;
wire [0:0]m01_couplers_to_auto_pc_ARLOCK;
wire [2:0]m01_couplers_to_auto_pc_ARPROT;
wire [3:0]m01_couplers_to_auto_pc_ARQOS;
wire m01_couplers_to_auto_pc_ARREADY;
wire [3:0]m01_couplers_to_auto_pc_ARREGION;
wire [2:0]m01_couplers_to_auto_pc_ARSIZE;
wire m01_couplers_to_auto_pc_ARVALID;
wire [31:0]m01_couplers_to_auto_pc_AWADDR;
wire [1:0]m01_couplers_to_auto_pc_AWBURST;
wire [3:0]m01_couplers_to_auto_pc_AWCACHE;
wire [7:0]m01_couplers_to_auto_pc_AWLEN;
wire [0:0]m01_couplers_to_auto_pc_AWLOCK;
wire [2:0]m01_couplers_to_auto_pc_AWPROT;
wire [3:0]m01_couplers_to_auto_pc_AWQOS;
wire m01_couplers_to_auto_pc_AWREADY;
wire [3:0]m01_couplers_to_auto_pc_AWREGION;
wire [2:0]m01_couplers_to_auto_pc_AWSIZE;
wire m01_couplers_to_auto_pc_AWVALID;
wire m01_couplers_to_auto_pc_BREADY;
wire [1:0]m01_couplers_to_auto_pc_BRESP;
wire m01_couplers_to_auto_pc_BVALID;
wire [31:0]m01_couplers_to_auto_pc_RDATA;
wire m01_couplers_to_auto_pc_RLAST;
wire m01_couplers_to_auto_pc_RREADY;
wire [1:0]m01_couplers_to_auto_pc_RRESP;
wire m01_couplers_to_auto_pc_RVALID;
wire [31:0]m01_couplers_to_auto_pc_WDATA;
wire m01_couplers_to_auto_pc_WLAST;
wire m01_couplers_to_auto_pc_WREADY;
wire [3:0]m01_couplers_to_auto_pc_WSTRB;
wire m01_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m01_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_m01_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m01_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_m01_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_m01_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m01_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m01_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m01_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m01_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m01_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m01_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m01_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m01_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m01_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m01_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m01_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m01_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m01_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m01_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m01_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m01_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m01_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m01_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m01_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m01_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m01_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m01_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m01_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m01_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m01_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m01_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m01_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m01_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m01_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m01_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m01_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m01_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m01_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m01_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m01_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_m01_couplers_ARPROT),
.m_axi_arready(auto_pc_to_m01_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_m01_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m01_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_m01_couplers_AWPROT),
.m_axi_awready(auto_pc_to_m01_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_m01_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m01_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m01_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m01_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m01_couplers_RDATA),
.m_axi_rready(auto_pc_to_m01_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m01_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m01_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m01_couplers_WDATA),
.m_axi_wready(auto_pc_to_m01_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m01_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m01_couplers_WVALID),
.s_axi_araddr(m01_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m01_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m01_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m01_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m01_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m01_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m01_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m01_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m01_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m01_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m01_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m01_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m01_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m01_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m01_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m01_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m01_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m01_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m01_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m01_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m01_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m01_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m01_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m01_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m01_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m01_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m01_couplers_to_auto_pc_RLAST),
.s_axi_rready(m01_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m01_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m01_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m01_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m01_couplers_to_auto_pc_WLAST),
.s_axi_wready(m01_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m01_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m01_couplers_to_auto_pc_WVALID));
endmodule |
module m02_couplers_imp_1E92BOA
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m02_couplers_ARADDR;
wire [2:0]auto_pc_to_m02_couplers_ARPROT;
wire auto_pc_to_m02_couplers_ARREADY;
wire auto_pc_to_m02_couplers_ARVALID;
wire [31:0]auto_pc_to_m02_couplers_AWADDR;
wire [2:0]auto_pc_to_m02_couplers_AWPROT;
wire auto_pc_to_m02_couplers_AWREADY;
wire auto_pc_to_m02_couplers_AWVALID;
wire auto_pc_to_m02_couplers_BREADY;
wire [1:0]auto_pc_to_m02_couplers_BRESP;
wire auto_pc_to_m02_couplers_BVALID;
wire [31:0]auto_pc_to_m02_couplers_RDATA;
wire auto_pc_to_m02_couplers_RREADY;
wire [1:0]auto_pc_to_m02_couplers_RRESP;
wire auto_pc_to_m02_couplers_RVALID;
wire [31:0]auto_pc_to_m02_couplers_WDATA;
wire auto_pc_to_m02_couplers_WREADY;
wire [3:0]auto_pc_to_m02_couplers_WSTRB;
wire auto_pc_to_m02_couplers_WVALID;
wire [31:0]m02_couplers_to_auto_pc_ARADDR;
wire [1:0]m02_couplers_to_auto_pc_ARBURST;
wire [3:0]m02_couplers_to_auto_pc_ARCACHE;
wire [7:0]m02_couplers_to_auto_pc_ARLEN;
wire [0:0]m02_couplers_to_auto_pc_ARLOCK;
wire [2:0]m02_couplers_to_auto_pc_ARPROT;
wire [3:0]m02_couplers_to_auto_pc_ARQOS;
wire m02_couplers_to_auto_pc_ARREADY;
wire [3:0]m02_couplers_to_auto_pc_ARREGION;
wire [2:0]m02_couplers_to_auto_pc_ARSIZE;
wire m02_couplers_to_auto_pc_ARVALID;
wire [31:0]m02_couplers_to_auto_pc_AWADDR;
wire [1:0]m02_couplers_to_auto_pc_AWBURST;
wire [3:0]m02_couplers_to_auto_pc_AWCACHE;
wire [7:0]m02_couplers_to_auto_pc_AWLEN;
wire [0:0]m02_couplers_to_auto_pc_AWLOCK;
wire [2:0]m02_couplers_to_auto_pc_AWPROT;
wire [3:0]m02_couplers_to_auto_pc_AWQOS;
wire m02_couplers_to_auto_pc_AWREADY;
wire [3:0]m02_couplers_to_auto_pc_AWREGION;
wire [2:0]m02_couplers_to_auto_pc_AWSIZE;
wire m02_couplers_to_auto_pc_AWVALID;
wire m02_couplers_to_auto_pc_BREADY;
wire [1:0]m02_couplers_to_auto_pc_BRESP;
wire m02_couplers_to_auto_pc_BVALID;
wire [31:0]m02_couplers_to_auto_pc_RDATA;
wire m02_couplers_to_auto_pc_RLAST;
wire m02_couplers_to_auto_pc_RREADY;
wire [1:0]m02_couplers_to_auto_pc_RRESP;
wire m02_couplers_to_auto_pc_RVALID;
wire [31:0]m02_couplers_to_auto_pc_WDATA;
wire m02_couplers_to_auto_pc_WLAST;
wire m02_couplers_to_auto_pc_WREADY;
wire [3:0]m02_couplers_to_auto_pc_WSTRB;
wire m02_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m02_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_m02_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m02_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_m02_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_m02_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m02_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_m02_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_m02_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m02_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m02_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m02_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m02_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m02_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m02_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m02_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m02_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m02_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m02_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m02_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m02_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m02_couplers_WREADY = M_AXI_wready;
assign m02_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m02_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m02_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m02_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m02_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m02_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m02_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m02_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m02_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m02_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m02_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m02_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m02_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m02_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m02_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m02_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m02_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m02_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m02_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m02_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m02_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m02_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m02_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m02_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign m02_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m02_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_m02_couplers_ARPROT),
.m_axi_arready(auto_pc_to_m02_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_m02_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m02_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_m02_couplers_AWPROT),
.m_axi_awready(auto_pc_to_m02_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_m02_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m02_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m02_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m02_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m02_couplers_RDATA),
.m_axi_rready(auto_pc_to_m02_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m02_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m02_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m02_couplers_WDATA),
.m_axi_wready(auto_pc_to_m02_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m02_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m02_couplers_WVALID),
.s_axi_araddr(m02_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m02_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m02_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m02_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m02_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m02_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m02_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m02_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m02_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m02_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m02_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m02_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m02_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m02_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m02_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m02_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m02_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m02_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m02_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m02_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m02_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m02_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m02_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m02_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m02_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m02_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m02_couplers_to_auto_pc_RLAST),
.s_axi_rready(m02_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m02_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m02_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m02_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m02_couplers_to_auto_pc_WLAST),
.s_axi_wready(m02_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m02_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m02_couplers_to_auto_pc_WVALID));
endmodule |
module m03_couplers_imp_8ZVH8V
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m03_couplers_ARADDR;
wire [2:0]auto_pc_to_m03_couplers_ARPROT;
wire auto_pc_to_m03_couplers_ARREADY;
wire auto_pc_to_m03_couplers_ARVALID;
wire [31:0]auto_pc_to_m03_couplers_AWADDR;
wire [2:0]auto_pc_to_m03_couplers_AWPROT;
wire auto_pc_to_m03_couplers_AWREADY;
wire auto_pc_to_m03_couplers_AWVALID;
wire auto_pc_to_m03_couplers_BREADY;
wire [1:0]auto_pc_to_m03_couplers_BRESP;
wire auto_pc_to_m03_couplers_BVALID;
wire [31:0]auto_pc_to_m03_couplers_RDATA;
wire auto_pc_to_m03_couplers_RREADY;
wire [1:0]auto_pc_to_m03_couplers_RRESP;
wire auto_pc_to_m03_couplers_RVALID;
wire [31:0]auto_pc_to_m03_couplers_WDATA;
wire auto_pc_to_m03_couplers_WREADY;
wire [3:0]auto_pc_to_m03_couplers_WSTRB;
wire auto_pc_to_m03_couplers_WVALID;
wire [31:0]m03_couplers_to_auto_pc_ARADDR;
wire [1:0]m03_couplers_to_auto_pc_ARBURST;
wire [3:0]m03_couplers_to_auto_pc_ARCACHE;
wire [7:0]m03_couplers_to_auto_pc_ARLEN;
wire [0:0]m03_couplers_to_auto_pc_ARLOCK;
wire [2:0]m03_couplers_to_auto_pc_ARPROT;
wire [3:0]m03_couplers_to_auto_pc_ARQOS;
wire m03_couplers_to_auto_pc_ARREADY;
wire [3:0]m03_couplers_to_auto_pc_ARREGION;
wire [2:0]m03_couplers_to_auto_pc_ARSIZE;
wire m03_couplers_to_auto_pc_ARVALID;
wire [31:0]m03_couplers_to_auto_pc_AWADDR;
wire [1:0]m03_couplers_to_auto_pc_AWBURST;
wire [3:0]m03_couplers_to_auto_pc_AWCACHE;
wire [7:0]m03_couplers_to_auto_pc_AWLEN;
wire [0:0]m03_couplers_to_auto_pc_AWLOCK;
wire [2:0]m03_couplers_to_auto_pc_AWPROT;
wire [3:0]m03_couplers_to_auto_pc_AWQOS;
wire m03_couplers_to_auto_pc_AWREADY;
wire [3:0]m03_couplers_to_auto_pc_AWREGION;
wire [2:0]m03_couplers_to_auto_pc_AWSIZE;
wire m03_couplers_to_auto_pc_AWVALID;
wire m03_couplers_to_auto_pc_BREADY;
wire [1:0]m03_couplers_to_auto_pc_BRESP;
wire m03_couplers_to_auto_pc_BVALID;
wire [31:0]m03_couplers_to_auto_pc_RDATA;
wire m03_couplers_to_auto_pc_RLAST;
wire m03_couplers_to_auto_pc_RREADY;
wire [1:0]m03_couplers_to_auto_pc_RRESP;
wire m03_couplers_to_auto_pc_RVALID;
wire [31:0]m03_couplers_to_auto_pc_WDATA;
wire m03_couplers_to_auto_pc_WLAST;
wire m03_couplers_to_auto_pc_WREADY;
wire [3:0]m03_couplers_to_auto_pc_WSTRB;
wire m03_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m03_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_m03_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_m03_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m03_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_m03_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_m03_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m03_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m03_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_m03_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_m03_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m03_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m03_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m03_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m03_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m03_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = m03_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m03_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m03_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m03_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m03_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m03_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m03_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m03_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m03_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m03_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_m03_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m03_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m03_couplers_WREADY = M_AXI_wready;
assign m03_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m03_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m03_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m03_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m03_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m03_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m03_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m03_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m03_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m03_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m03_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m03_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m03_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m03_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m03_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m03_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m03_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m03_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m03_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m03_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m03_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m03_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m03_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign m03_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m03_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign m03_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_2 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m03_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_m03_couplers_ARPROT),
.m_axi_arready(auto_pc_to_m03_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_m03_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m03_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_m03_couplers_AWPROT),
.m_axi_awready(auto_pc_to_m03_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_m03_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m03_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m03_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m03_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m03_couplers_RDATA),
.m_axi_rready(auto_pc_to_m03_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m03_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m03_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m03_couplers_WDATA),
.m_axi_wready(auto_pc_to_m03_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m03_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m03_couplers_WVALID),
.s_axi_araddr(m03_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m03_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m03_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m03_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m03_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m03_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m03_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m03_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m03_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m03_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m03_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m03_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m03_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m03_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m03_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m03_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m03_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m03_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m03_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m03_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m03_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m03_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m03_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m03_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m03_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m03_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m03_couplers_to_auto_pc_RLAST),
.s_axi_rready(m03_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m03_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m03_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m03_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m03_couplers_to_auto_pc_WLAST),
.s_axi_wready(m03_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m03_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m03_couplers_to_auto_pc_WVALID));
endmodule |
module m04_couplers_imp_YN7N1I
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [3:0]M_AXI_arlen;
output [1:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m04_couplers_ARADDR;
wire [1:0]auto_pc_to_m04_couplers_ARBURST;
wire [3:0]auto_pc_to_m04_couplers_ARCACHE;
wire [3:0]auto_pc_to_m04_couplers_ARLEN;
wire [1:0]auto_pc_to_m04_couplers_ARLOCK;
wire [2:0]auto_pc_to_m04_couplers_ARPROT;
wire [3:0]auto_pc_to_m04_couplers_ARQOS;
wire auto_pc_to_m04_couplers_ARREADY;
wire [2:0]auto_pc_to_m04_couplers_ARSIZE;
wire auto_pc_to_m04_couplers_ARVALID;
wire [31:0]auto_pc_to_m04_couplers_AWADDR;
wire [1:0]auto_pc_to_m04_couplers_AWBURST;
wire [3:0]auto_pc_to_m04_couplers_AWCACHE;
wire [3:0]auto_pc_to_m04_couplers_AWLEN;
wire [1:0]auto_pc_to_m04_couplers_AWLOCK;
wire [2:0]auto_pc_to_m04_couplers_AWPROT;
wire [3:0]auto_pc_to_m04_couplers_AWQOS;
wire auto_pc_to_m04_couplers_AWREADY;
wire [2:0]auto_pc_to_m04_couplers_AWSIZE;
wire auto_pc_to_m04_couplers_AWVALID;
wire auto_pc_to_m04_couplers_BREADY;
wire [1:0]auto_pc_to_m04_couplers_BRESP;
wire auto_pc_to_m04_couplers_BVALID;
wire [31:0]auto_pc_to_m04_couplers_RDATA;
wire auto_pc_to_m04_couplers_RLAST;
wire auto_pc_to_m04_couplers_RREADY;
wire [1:0]auto_pc_to_m04_couplers_RRESP;
wire auto_pc_to_m04_couplers_RVALID;
wire [31:0]auto_pc_to_m04_couplers_WDATA;
wire auto_pc_to_m04_couplers_WLAST;
wire auto_pc_to_m04_couplers_WREADY;
wire [3:0]auto_pc_to_m04_couplers_WSTRB;
wire auto_pc_to_m04_couplers_WVALID;
wire [31:0]m04_couplers_to_auto_pc_ARADDR;
wire [1:0]m04_couplers_to_auto_pc_ARBURST;
wire [3:0]m04_couplers_to_auto_pc_ARCACHE;
wire [7:0]m04_couplers_to_auto_pc_ARLEN;
wire [0:0]m04_couplers_to_auto_pc_ARLOCK;
wire [2:0]m04_couplers_to_auto_pc_ARPROT;
wire [3:0]m04_couplers_to_auto_pc_ARQOS;
wire m04_couplers_to_auto_pc_ARREADY;
wire [3:0]m04_couplers_to_auto_pc_ARREGION;
wire [2:0]m04_couplers_to_auto_pc_ARSIZE;
wire m04_couplers_to_auto_pc_ARVALID;
wire [31:0]m04_couplers_to_auto_pc_AWADDR;
wire [1:0]m04_couplers_to_auto_pc_AWBURST;
wire [3:0]m04_couplers_to_auto_pc_AWCACHE;
wire [7:0]m04_couplers_to_auto_pc_AWLEN;
wire [0:0]m04_couplers_to_auto_pc_AWLOCK;
wire [2:0]m04_couplers_to_auto_pc_AWPROT;
wire [3:0]m04_couplers_to_auto_pc_AWQOS;
wire m04_couplers_to_auto_pc_AWREADY;
wire [3:0]m04_couplers_to_auto_pc_AWREGION;
wire [2:0]m04_couplers_to_auto_pc_AWSIZE;
wire m04_couplers_to_auto_pc_AWVALID;
wire m04_couplers_to_auto_pc_BREADY;
wire [1:0]m04_couplers_to_auto_pc_BRESP;
wire m04_couplers_to_auto_pc_BVALID;
wire [31:0]m04_couplers_to_auto_pc_RDATA;
wire m04_couplers_to_auto_pc_RLAST;
wire m04_couplers_to_auto_pc_RREADY;
wire [1:0]m04_couplers_to_auto_pc_RRESP;
wire m04_couplers_to_auto_pc_RVALID;
wire [31:0]m04_couplers_to_auto_pc_WDATA;
wire m04_couplers_to_auto_pc_WLAST;
wire m04_couplers_to_auto_pc_WREADY;
wire [3:0]m04_couplers_to_auto_pc_WSTRB;
wire m04_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m04_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_m04_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_m04_couplers_ARCACHE;
assign M_AXI_arlen[3:0] = auto_pc_to_m04_couplers_ARLEN;
assign M_AXI_arlock[1:0] = auto_pc_to_m04_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_m04_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_m04_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_m04_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_m04_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m04_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_m04_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_m04_couplers_AWCACHE;
assign M_AXI_awlen[3:0] = auto_pc_to_m04_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_pc_to_m04_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_m04_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_m04_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_m04_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_m04_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m04_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m04_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_m04_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_m04_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_pc_to_m04_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m04_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m04_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m04_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m04_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m04_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = m04_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m04_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m04_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m04_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m04_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m04_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m04_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m04_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m04_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m04_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_m04_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_m04_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m04_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m04_couplers_WREADY = M_AXI_wready;
assign m04_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m04_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m04_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m04_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m04_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m04_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m04_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m04_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m04_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m04_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m04_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m04_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m04_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m04_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m04_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m04_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m04_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m04_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m04_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m04_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m04_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m04_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m04_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign m04_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m04_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign m04_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_3 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m04_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_m04_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_m04_couplers_ARCACHE),
.m_axi_arlen(auto_pc_to_m04_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_m04_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_m04_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_m04_couplers_ARQOS),
.m_axi_arready(auto_pc_to_m04_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_m04_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_m04_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m04_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_m04_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_m04_couplers_AWCACHE),
.m_axi_awlen(auto_pc_to_m04_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_m04_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_m04_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_m04_couplers_AWQOS),
.m_axi_awready(auto_pc_to_m04_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_m04_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_m04_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m04_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m04_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m04_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m04_couplers_RDATA),
.m_axi_rlast(auto_pc_to_m04_couplers_RLAST),
.m_axi_rready(auto_pc_to_m04_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m04_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m04_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m04_couplers_WDATA),
.m_axi_wlast(auto_pc_to_m04_couplers_WLAST),
.m_axi_wready(auto_pc_to_m04_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m04_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m04_couplers_WVALID),
.s_axi_araddr(m04_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m04_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m04_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m04_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m04_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m04_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m04_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m04_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m04_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m04_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m04_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m04_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m04_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m04_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m04_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m04_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m04_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m04_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m04_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m04_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m04_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m04_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m04_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m04_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m04_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m04_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m04_couplers_to_auto_pc_RLAST),
.s_axi_rready(m04_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m04_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m04_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m04_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m04_couplers_to_auto_pc_WLAST),
.s_axi_wready(m04_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m04_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m04_couplers_to_auto_pc_WVALID));
endmodule |
module s00_couplers_imp_1PH4J44
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [11:0]M_AXI_arid;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [11:0]M_AXI_awid;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [12:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input [12:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [1:0]auto_pc_to_s00_couplers_ARBURST;
wire [3:0]auto_pc_to_s00_couplers_ARCACHE;
wire [11:0]auto_pc_to_s00_couplers_ARID;
wire [7:0]auto_pc_to_s00_couplers_ARLEN;
wire [0:0]auto_pc_to_s00_couplers_ARLOCK;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire [3:0]auto_pc_to_s00_couplers_ARQOS;
wire auto_pc_to_s00_couplers_ARREADY;
wire [2:0]auto_pc_to_s00_couplers_ARSIZE;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [1:0]auto_pc_to_s00_couplers_AWBURST;
wire [3:0]auto_pc_to_s00_couplers_AWCACHE;
wire [11:0]auto_pc_to_s00_couplers_AWID;
wire [7:0]auto_pc_to_s00_couplers_AWLEN;
wire [0:0]auto_pc_to_s00_couplers_AWLOCK;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire [3:0]auto_pc_to_s00_couplers_AWQOS;
wire auto_pc_to_s00_couplers_AWREADY;
wire [2:0]auto_pc_to_s00_couplers_AWSIZE;
wire auto_pc_to_s00_couplers_AWVALID;
wire [12:0]auto_pc_to_s00_couplers_BID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire [12:0]auto_pc_to_s00_couplers_RID;
wire auto_pc_to_s00_couplers_RLAST;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WLAST;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_s00_couplers_ARCACHE;
assign M_AXI_arid[11:0] = auto_pc_to_s00_couplers_ARID;
assign M_AXI_arlen[7:0] = auto_pc_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_pc_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_s00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_s00_couplers_AWCACHE;
assign M_AXI_awid[11:0] = auto_pc_to_s00_couplers_AWID;
assign M_AXI_awlen[7:0] = auto_pc_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_pc_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_s00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_s00_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BID = M_AXI_bid[12:0];
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RID = M_AXI_rid[12:0];
assign auto_pc_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_4 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_s00_couplers_ARCACHE),
.m_axi_arid(auto_pc_to_s00_couplers_ARID),
.m_axi_arlen(auto_pc_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_s00_couplers_ARQOS),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_s00_couplers_AWCACHE),
.m_axi_awid(auto_pc_to_s00_couplers_AWID),
.m_axi_awlen(auto_pc_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_s00_couplers_AWQOS),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bid(auto_pc_to_s00_couplers_BID[11:0]),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rid(auto_pc_to_s00_couplers_RID[11:0]),
.m_axi_rlast(auto_pc_to_s00_couplers_RLAST),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wlast(auto_pc_to_s00_couplers_WLAST),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule |
module s01_couplers_imp_K956Q9
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output M_AXI_araddr;
output M_AXI_arburst;
output M_AXI_arcache;
output M_AXI_arid;
output M_AXI_arlen;
output M_AXI_arlock;
output M_AXI_arprot;
output M_AXI_arqos;
input M_AXI_arready;
output M_AXI_arsize;
output M_AXI_arvalid;
output M_AXI_awaddr;
output M_AXI_awburst;
output M_AXI_awcache;
output M_AXI_awid;
output M_AXI_awlen;
output M_AXI_awlock;
output M_AXI_awprot;
output M_AXI_awqos;
input M_AXI_awready;
output M_AXI_awsize;
output M_AXI_awvalid;
input M_AXI_bid;
output M_AXI_bready;
input M_AXI_bresp;
input M_AXI_bvalid;
input M_AXI_rdata;
input M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input M_AXI_rresp;
input M_AXI_rvalid;
output M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input S_AXI_araddr;
input S_AXI_arburst;
input S_AXI_arcache;
input S_AXI_arid;
input S_AXI_arlen;
input S_AXI_arlock;
input S_AXI_arprot;
input S_AXI_arqos;
output S_AXI_arready;
input S_AXI_arsize;
input S_AXI_arvalid;
input S_AXI_awaddr;
input S_AXI_awburst;
input S_AXI_awcache;
input S_AXI_awid;
input S_AXI_awlen;
input S_AXI_awlock;
input S_AXI_awprot;
input S_AXI_awqos;
output S_AXI_awready;
input S_AXI_awsize;
input S_AXI_awvalid;
output S_AXI_bid;
input S_AXI_bready;
output S_AXI_bresp;
output S_AXI_bvalid;
output S_AXI_rdata;
output S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output S_AXI_rresp;
output S_AXI_rvalid;
input S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input S_AXI_wstrb;
input S_AXI_wvalid;
wire s01_couplers_to_s01_couplers_ARADDR;
wire s01_couplers_to_s01_couplers_ARBURST;
wire s01_couplers_to_s01_couplers_ARCACHE;
wire s01_couplers_to_s01_couplers_ARID;
wire s01_couplers_to_s01_couplers_ARLEN;
wire s01_couplers_to_s01_couplers_ARLOCK;
wire s01_couplers_to_s01_couplers_ARPROT;
wire s01_couplers_to_s01_couplers_ARQOS;
wire s01_couplers_to_s01_couplers_ARREADY;
wire s01_couplers_to_s01_couplers_ARSIZE;
wire s01_couplers_to_s01_couplers_ARVALID;
wire s01_couplers_to_s01_couplers_AWADDR;
wire s01_couplers_to_s01_couplers_AWBURST;
wire s01_couplers_to_s01_couplers_AWCACHE;
wire s01_couplers_to_s01_couplers_AWID;
wire s01_couplers_to_s01_couplers_AWLEN;
wire s01_couplers_to_s01_couplers_AWLOCK;
wire s01_couplers_to_s01_couplers_AWPROT;
wire s01_couplers_to_s01_couplers_AWQOS;
wire s01_couplers_to_s01_couplers_AWREADY;
wire s01_couplers_to_s01_couplers_AWSIZE;
wire s01_couplers_to_s01_couplers_AWVALID;
wire s01_couplers_to_s01_couplers_BID;
wire s01_couplers_to_s01_couplers_BREADY;
wire s01_couplers_to_s01_couplers_BRESP;
wire s01_couplers_to_s01_couplers_BVALID;
wire s01_couplers_to_s01_couplers_RDATA;
wire s01_couplers_to_s01_couplers_RID;
wire s01_couplers_to_s01_couplers_RLAST;
wire s01_couplers_to_s01_couplers_RREADY;
wire s01_couplers_to_s01_couplers_RRESP;
wire s01_couplers_to_s01_couplers_RVALID;
wire s01_couplers_to_s01_couplers_WDATA;
wire s01_couplers_to_s01_couplers_WLAST;
wire s01_couplers_to_s01_couplers_WREADY;
wire s01_couplers_to_s01_couplers_WSTRB;
wire s01_couplers_to_s01_couplers_WVALID;
assign M_AXI_araddr = s01_couplers_to_s01_couplers_ARADDR;
assign M_AXI_arburst = s01_couplers_to_s01_couplers_ARBURST;
assign M_AXI_arcache = s01_couplers_to_s01_couplers_ARCACHE;
assign M_AXI_arid = s01_couplers_to_s01_couplers_ARID;
assign M_AXI_arlen = s01_couplers_to_s01_couplers_ARLEN;
assign M_AXI_arlock = s01_couplers_to_s01_couplers_ARLOCK;
assign M_AXI_arprot = s01_couplers_to_s01_couplers_ARPROT;
assign M_AXI_arqos = s01_couplers_to_s01_couplers_ARQOS;
assign M_AXI_arsize = s01_couplers_to_s01_couplers_ARSIZE;
assign M_AXI_arvalid = s01_couplers_to_s01_couplers_ARVALID;
assign M_AXI_awaddr = s01_couplers_to_s01_couplers_AWADDR;
assign M_AXI_awburst = s01_couplers_to_s01_couplers_AWBURST;
assign M_AXI_awcache = s01_couplers_to_s01_couplers_AWCACHE;
assign M_AXI_awid = s01_couplers_to_s01_couplers_AWID;
assign M_AXI_awlen = s01_couplers_to_s01_couplers_AWLEN;
assign M_AXI_awlock = s01_couplers_to_s01_couplers_AWLOCK;
assign M_AXI_awprot = s01_couplers_to_s01_couplers_AWPROT;
assign M_AXI_awqos = s01_couplers_to_s01_couplers_AWQOS;
assign M_AXI_awsize = s01_couplers_to_s01_couplers_AWSIZE;
assign M_AXI_awvalid = s01_couplers_to_s01_couplers_AWVALID;
assign M_AXI_bready = s01_couplers_to_s01_couplers_BREADY;
assign M_AXI_rready = s01_couplers_to_s01_couplers_RREADY;
assign M_AXI_wdata = s01_couplers_to_s01_couplers_WDATA;
assign M_AXI_wlast = s01_couplers_to_s01_couplers_WLAST;
assign M_AXI_wstrb = s01_couplers_to_s01_couplers_WSTRB;
assign M_AXI_wvalid = s01_couplers_to_s01_couplers_WVALID;
assign S_AXI_arready = s01_couplers_to_s01_couplers_ARREADY;
assign S_AXI_awready = s01_couplers_to_s01_couplers_AWREADY;
assign S_AXI_bid = s01_couplers_to_s01_couplers_BID;
assign S_AXI_bresp = s01_couplers_to_s01_couplers_BRESP;
assign S_AXI_bvalid = s01_couplers_to_s01_couplers_BVALID;
assign S_AXI_rdata = s01_couplers_to_s01_couplers_RDATA;
assign S_AXI_rid = s01_couplers_to_s01_couplers_RID;
assign S_AXI_rlast = s01_couplers_to_s01_couplers_RLAST;
assign S_AXI_rresp = s01_couplers_to_s01_couplers_RRESP;
assign S_AXI_rvalid = s01_couplers_to_s01_couplers_RVALID;
assign S_AXI_wready = s01_couplers_to_s01_couplers_WREADY;
assign s01_couplers_to_s01_couplers_ARADDR = S_AXI_araddr;
assign s01_couplers_to_s01_couplers_ARBURST = S_AXI_arburst;
assign s01_couplers_to_s01_couplers_ARCACHE = S_AXI_arcache;
assign s01_couplers_to_s01_couplers_ARID = S_AXI_arid;
assign s01_couplers_to_s01_couplers_ARLEN = S_AXI_arlen;
assign s01_couplers_to_s01_couplers_ARLOCK = S_AXI_arlock;
assign s01_couplers_to_s01_couplers_ARPROT = S_AXI_arprot;
assign s01_couplers_to_s01_couplers_ARQOS = S_AXI_arqos;
assign s01_couplers_to_s01_couplers_ARREADY = M_AXI_arready;
assign s01_couplers_to_s01_couplers_ARSIZE = S_AXI_arsize;
assign s01_couplers_to_s01_couplers_ARVALID = S_AXI_arvalid;
assign s01_couplers_to_s01_couplers_AWADDR = S_AXI_awaddr;
assign s01_couplers_to_s01_couplers_AWBURST = S_AXI_awburst;
assign s01_couplers_to_s01_couplers_AWCACHE = S_AXI_awcache;
assign s01_couplers_to_s01_couplers_AWID = S_AXI_awid;
assign s01_couplers_to_s01_couplers_AWLEN = S_AXI_awlen;
assign s01_couplers_to_s01_couplers_AWLOCK = S_AXI_awlock;
assign s01_couplers_to_s01_couplers_AWPROT = S_AXI_awprot;
assign s01_couplers_to_s01_couplers_AWQOS = S_AXI_awqos;
assign s01_couplers_to_s01_couplers_AWREADY = M_AXI_awready;
assign s01_couplers_to_s01_couplers_AWSIZE = S_AXI_awsize;
assign s01_couplers_to_s01_couplers_AWVALID = S_AXI_awvalid;
assign s01_couplers_to_s01_couplers_BID = M_AXI_bid;
assign s01_couplers_to_s01_couplers_BREADY = S_AXI_bready;
assign s01_couplers_to_s01_couplers_BRESP = M_AXI_bresp;
assign s01_couplers_to_s01_couplers_BVALID = M_AXI_bvalid;
assign s01_couplers_to_s01_couplers_RDATA = M_AXI_rdata;
assign s01_couplers_to_s01_couplers_RID = M_AXI_rid;
assign s01_couplers_to_s01_couplers_RLAST = M_AXI_rlast;
assign s01_couplers_to_s01_couplers_RREADY = S_AXI_rready;
assign s01_couplers_to_s01_couplers_RRESP = M_AXI_rresp;
assign s01_couplers_to_s01_couplers_RVALID = M_AXI_rvalid;
assign s01_couplers_to_s01_couplers_WDATA = S_AXI_wdata;
assign s01_couplers_to_s01_couplers_WLAST = S_AXI_wlast;
assign s01_couplers_to_s01_couplers_WREADY = M_AXI_wready;
assign s01_couplers_to_s01_couplers_WSTRB = S_AXI_wstrb;
assign s01_couplers_to_s01_couplers_WVALID = S_AXI_wvalid;
endmodule |
module de_PLL (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
endmodule |
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B_N = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B_N = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B_N = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B_N = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__or2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module sky130_fd_sc_lp__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module ym2610(
input PHI_M,
input nRESET,
inout [7:0] SDD,
input [1:0] SDA,
output nIRQ,
input nCS,
input nWR_RAW,
input nRD_RAW,
inout [7:0] SDRAD,
output [5:0] SDRA,
output SDRMPX, nSDROE,
inout [7:0] SDPAD,
output [3:0] SDPA,
output SDPMPX, nSDPOE,
output [5:0] ANA, // How many levels ?
output SH1, SH2, OP0, PHI_S // YM3016 output
);
wire nRD, nWR;
wire BUSY_MMR;
wire clr_run_A, set_run_A, clr_run_B, set_run_B;
// nCS gating - Not sure if it's that simple
assign nWR = nCS | nWR_RAW;
assign nRD = nCS | nRD_RAW;
// Internal
reg P1; // Internal clock
reg BUSY;
reg [1:0] BUSY_MMR_SR; // For edge detection
reg nWR_COPY;
reg [1:0] ADDR_COPY;
reg [7:0] DATA_COPY;
reg nWRITE_S;
reg [1:0] ADDR_S;
reg [7:0] DATA_S;
wire [15:0] ADPCM_OUT;
wire FLAG_A, FLAG_B;
reg [7:0] CLK_144_DIV;
wire TICK_144;
// Timer
wire [9:0] YMTIMER_TA_LOAD;
wire [7:0] YMTIMER_TB_LOAD;
wire [5:0] YMTIMER_CONFIG;
reg FLAG_A_S, FLAG_B_S;
// SSG
wire [11:0] SSG_FREQ_A;
wire [11:0] SSG_FREQ_B;
wire [11:0] SSG_FREQ_C;
wire [4:0] SSG_NOISE;
wire [5:0] SSG_EN;
wire [4:0] SSG_VOL_A;
wire [4:0] SSG_VOL_B;
wire [4:0] SSG_VOL_C;
wire [15:0] SSG_ENV_FREQ;
wire [3:0] SSG_ENV;
// FM
wire [3:0] FM_LFO;
wire [7:0] FM_KEYON;
wire [6:0] FM_DTMUL[3:0];
wire [6:0] FM_TL[3:0];
wire [7:0] FM_KSAR[3:0];
wire [7:0] FM_AMDR[3:0];
wire [4:0] FM_SR[3:0];
wire [7:0] FM_SLRR[3:0];
wire [3:0] FM_SSGEG[3:0];
wire [13:0] FM_FNUM13;
wire [13:0] FM_FNUM24;
wire [13:0] FM_2FNUM13;
wire [13:0] FM_2FNUM24;
wire [5:0] FM_FBALGO13;
wire [5:0] FM_FBALGO24;
wire [7:0] FM_PAN13;
wire [7:0] FM_PAN24;
// ADPCM-A
wire [7:0] PCMA_KEYON;
wire [7:0] PCMA_KEYOFF;
wire [5:0] PCMA_MVOL;
wire [7:0] PCMA_VOLPAN_A, PCMA_VOLPAN_B, PCMA_VOLPAN_C, PCMA_VOLPAN_D, PCMA_VOLPAN_E, PCMA_VOLPAN_F;
wire [15:0] PCMA_START_A, PCMA_START_B, PCMA_START_C, PCMA_START_D, PCMA_START_E, PCMA_START_F;
wire [15:0] PCMA_STOP_A, PCMA_STOP_B, PCMA_STOP_C, PCMA_STOP_D, PCMA_STOP_E, PCMA_STOP_F;
// ADPCM-B
wire [1:0] PCMB_PAN;
wire [15:0] PCMB_START_ADDR;
wire [15:0] PCMB_STOP_ADDR;
wire [15:0] PCMB_DELTA;
wire [7:0] PCMB_TL;
wire PCMB_RESET, PCMB_REPEAT, PCMB_START;
wire [7:0] ADPCM_FLAGS;
wire [5:0] PCMA_FLAGMASK;
wire PCMA_FLAGMASK_PCMB;
// Internal clock generation
always @(posedge PHI_M or negedge nRESET)
begin
if (!nRESET)
P1 <= 1'b0;
else
P1 <= ~P1;
end
assign TICK_144 = (CLK_144_DIV == 143) ? 1'b1 : 1'b0; // 143, not 0. Otherwise timers are goofy
// TICK_144 gen (CLK/144)
always @(posedge PHI_M)
begin
if (!nRESET)
CLK_144_DIV <= 0;
else
begin
if (CLK_144_DIV < 143) // / 12 / 12 = / 144
CLK_144_DIV <= CLK_144_DIV + 1'b1;
else
CLK_144_DIV <= 0;
end
end
// CPU interface
always @(posedge PHI_S)
begin
if (!nRESET)
begin
BUSY <= 1'b0;
end
else
begin
BUSY_MMR_SR <= {BUSY_MMR_SR[0], BUSY_MMR};
if (!nWR && !BUSY)
begin
// Do write
BUSY <= 1'b1;
nWR_COPY <= 1'b0;
ADDR_COPY <= SDA;
DATA_COPY <= SDD;
end
else
begin
if (BUSY_MMR) nWR_COPY <= 1'b1;
if (BUSY && BUSY_MMR_SR == 2'b10) BUSY <= 1'b0;
end
end
end
// Read registers
assign SDD = nRD ? 8'bzzzzzzzz : (SDA == 0) ? { BUSY, 5'h0, FLAG_B_S, FLAG_A_S } : // 4: Timer status
(SDA == 1) ? 8'h0 : // 5: SSG register data
(SDA == 2) ? ADPCM_FLAGS : // 6: ADPCM flags
8'h0; // 7: Nothing
always @(posedge PHI_M)
{ FLAG_B_S, FLAG_A_S } <= { FLAG_B, FLAG_A };
always @(posedge P1)
{nWRITE_S, ADDR_S, DATA_S} <= {nWR_COPY, ADDR_COPY, DATA_COPY};
ym_regs YMREGS(PHI_M, nRESET, nWRITE_S, ADDR_S, DATA_S, BUSY_MMR,
SSG_FREQ_A, SSG_FREQ_B, SSG_FREQ_C, SSG_NOISE, SSG_EN, SSG_VOL_A, SSG_VOL_B, SSG_VOL_C,
SSG_ENV_FREQ, SSG_ENV,
YMTIMER_TA_LOAD, YMTIMER_TB_LOAD, YMTIMER_CONFIG,
clr_run_A, set_run_A, clr_run_B, set_run_B,
PCMA_KEYON, PCMA_KEYOFF, PCMA_MVOL,
PCMA_VOLPAN_A, PCMA_VOLPAN_B, PCMA_VOLPAN_C, PCMA_VOLPAN_D, PCMA_VOLPAN_E, PCMA_VOLPAN_F,
PCMA_START_A, PCMA_START_B, PCMA_START_C, PCMA_START_D, PCMA_START_E, PCMA_START_F,
PCMA_STOP_A, PCMA_STOP_B, PCMA_STOP_C, PCMA_STOP_D, PCMA_STOP_E, PCMA_STOP_F,
PCMA_FLAGMASK, PCMA_FLAGMASK_PCMB,
PCMB_RESET, PCMB_REPEAT, PCMB_START,
PCMB_PAN, PCMB_START_ADDR, PCMB_STOP_ADDR, PCMB_DELTA, PCMB_TL
);
ym_timers YMTIMER(PHI_M, TICK_144, nRESET, YMTIMER_TA_LOAD, YMTIMER_TB_LOAD, YMTIMER_CONFIG,
clr_run_A, set_run_A, clr_run_B, set_run_B, FLAG_A, FLAG_B, nIRQ);
ym_ssg YMSSG(PHI_M, ANA, SSG_FREQ_A, SSG_FREQ_B, SSG_FREQ_C, SSG_NOISE, SSG_EN, SSG_VOL_A, SSG_VOL_B, SSG_VOL_C,
SSG_ENV_FREQ, SSG_ENV);
ym_fm YMFM(PHI_M);
ym_pcm YMPCM(PHI_M, TICK_144, nRESET,
PCMA_FLAGMASK, PCMA_FLAGMASK_PCMB,
ADPCM_FLAGS,
PCMA_KEYON, PCMA_KEYOFF,
PCMA_MVOL,
PCMA_VOLPAN_A, PCMA_VOLPAN_B, PCMA_VOLPAN_C, PCMA_VOLPAN_D, PCMA_VOLPAN_E, PCMA_VOLPAN_F,
PCMA_START_A, PCMA_STOP_A, PCMA_START_B, PCMA_STOP_B, PCMA_START_C, PCMA_STOP_C,
PCMA_START_D, PCMA_STOP_D, PCMA_START_E, PCMA_STOP_E, PCMA_START_F, PCMA_STOP_F,
SDRAD, SDRA, SDRMPX, nSDROE,
SDPAD, SDPA, SDPMPX, nSDPOE,
ADPCM_OUT,
PCMB_RESET, PCMB_REPEAT, PCMB_START,
PCMB_PAN, PCMB_START_ADDR, PCMB_STOP_ADDR, PCMB_DELTA, PCMB_TL);
endmodule |
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire pwrgood0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood0_out_A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
endmodule |
module sky130_fd_sc_ls__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule |
module alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result,wrbyteen);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Clock signal
//input clock;
// Control signal bits - ppp
input [0:2] ctrl_ppp;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'hfffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'h00112233445566778899aabbccddeeff1;
//parameter max_128_bits = 128'h123415678901234567890123456789012;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ppp or ctrl_ww or alu_op or wrbyteen)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ======================================================
// ======================================================
// SRA instruction >> mv to LSB >> bit 127
`aluwsra:
begin
case(ctrl_ww)
`w8: // sra AND `w8
begin
case(reg_B[5:7])
0:
begin
result[0:7]<=reg_A[0:7]>>0;
result[8:15]<=reg_A[8:15]>>0;
result[16:23]<=reg_A[16:23]>>0;
result[24:31]<=reg_A[24:31]>>0;
result[32:39]<=reg_A[32:39]>>0;
result[40:47]<=reg_A[40:47]>>0;
result[48:55]<=reg_A[48:55]>>0;
result[56:63]<=reg_A[56:63]>>0;
result[64:71]<=reg_A[64:71]>>0;
result[72:79]<=reg_A[72:79]>>0;
result[80:87]<=reg_A[80:87]>>0;
result[88:95]<=reg_A[88:95]>>0;
result[96:103]<=reg_A[96:103]>>0;
result[104:111]<=reg_A[104:111]>>0;
result[112:119]<=reg_A[112:119]>>0;
result[120:127]<=reg_A[120:127]>>0;
end
1:
begin
result[0:7]<=reg_A[0:7]>>1;
result[0]<=result[0];
result[8:15]<=reg_A[8:15]>>1;
result[8]<=result[8];
result[16:23]<=reg_A[16:23]>>1;
result[16]<=result[16];
result[24:31]<=reg_A[24:31]>>1;
result[24]<=result[24];
result[32:39]<=reg_A[32:39]>>1;
result[32]<=result[32];
result[40:47]<=reg_A[40:47]>>1;
result[40]<=result[40];
result[48:55]<=reg_A[48:55]>>1;
result[48]<=result[48];
result[56:63]<=reg_A[56:63]>>1;
result[56]<=result[56];
result[64:71]<=reg_A[64:71]>>1;
result[64]<=result[64];
result[72:79]<=reg_A[72:79]>>1;
result[72]<=result[72];
result[80:87]<=reg_A[80:87]>>1;
result[80]<=result[80];
result[88:95]<=reg_A[88:95]>>1;
result[88]<=result[88];
result[96:103]<=reg_A[96:103]>>1;
result[96]<=result[96];
result[104:111]<=reg_A[104:111]>>1;
result[104]<=result[104];
result[112:119]<=reg_A[112:119]>>1;
result[112]<=result[112];
result[120:127]<=reg_A[120:127]>>1;
result[120]<=result[120];
end
2:
begin
result[0:7]<=reg_A[0:7]>>2;
result[0]<=result[0];
result[1]<=result[0];
result[8:15]<=reg_A[8:15]>>2;
result[8]<=result[8];
result[9]<=result[8];
result[16:23]<=reg_A[16:23]>>2;
result[16]<=result[16];
result[17]<=result[16];
result[24:31]<=reg_A[24:31]>>2;
result[24]<=result[24];
result[25]<=result[24];
result[32:39]<=reg_A[32:39]>>2;
result[32]<=result[32];
result[33]<=result[32];
result[40:47]<=reg_A[40:47]>>2;
result[40]<=result[40];
result[41]<=result[40];
result[48:55]<=reg_A[48:55]>>2;
result[48]<=result[48];
result[49]<=result[48];
result[56:63]<=reg_A[56:63]>>2;
result[56]<=result[56];
result[57]<=result[56];
result[64:71]<=reg_A[64:71]>>2;
result[64]<=result[64];
result[65]<=result[64];
result[72:79]<=reg_A[72:79]>>2;
result[72]<=result[72];
result[73]<=result[72];
result[80:87]<=reg_A[80:87]>>2;
result[80]<=result[80];
result[81]<=result[80];
result[88:95]<=reg_A[88:95]>>2;
result[88]<=result[88];
result[89]<=result[88];
result[96:103]<=reg_A[96:103]>>2;
result[96]<=result[96];
result[97]<=result[96];
result[104:111]<=reg_A[104:111]>>2;
result[104]<=result[104];
result[105]<=result[104];
result[112:119]<=reg_A[112:119]>>2;
result[112]<=result[112];
result[113]<=result[112];
result[120:127]<=reg_A[120:127]>>2;
result[120]<=result[120];
result[121]<=result[120];
end
3:
begin
result[0:7]<=reg_A[0:7]>>3;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[8:15]<=reg_A[8:15]>>3;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[16:23]<=reg_A[16:23]>>3;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[24:31]<=reg_A[24:31]>>3;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[32:39]<=reg_A[32:39]>>3;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[40:47]<=reg_A[40:47]>>3;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[48:55]<=reg_A[48:55]>>3;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[56:63]<=reg_A[56:63]>>3;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[64:71]<=reg_A[64:71]>>3;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[72:79]<=reg_A[72:79]>>3;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[80:87]<=reg_A[80:87]>>3;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[88:95]<=reg_A[88:95]>>3;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[96:103]<=reg_A[96:103]>>3;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[104:111]<=reg_A[104:111]>>3;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[112:119]<=reg_A[112:119]>>3;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[120:127]<=reg_A[120:127]>>3;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
end
4:
begin
$display("entered 8 - shift 4");
result[0:7]<=reg_A[0:7]>>4;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[8:15]<=reg_A[8:15]>>4;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[16:23]<=reg_A[16:23]>>4;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[24:31]<=reg_A[24:31]>>4;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[32:39]<=reg_A[32:39]>>4;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[40:47]<=reg_A[40:47]>>4;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[48:55]<=reg_A[48:55]>>4;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[56:63]<=reg_A[56:63]>>4;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[64:71]<=reg_A[64:71]>>4;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[72:79]<=reg_A[72:79]>>4;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[80:87]<=reg_A[80:87]>>4;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[88:95]<=reg_A[88:95]>>4;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[96:103]<=reg_A[96:103]>>4;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[104:111]<=reg_A[104:111]>>4;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[112:119]<=reg_A[112:119]>>4;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[120:127]<=reg_A[120:127]>>4;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
end
5:
begin
result[0:7]<=reg_A[0:7]>>5;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[8:15]<=reg_A[8:15]>>5;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[12]<=result[8];
result[16:23]<=reg_A[16:23]>>5;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[24:31]<=reg_A[24:31]>>5;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[28]<=result[24];
result[32:39]<=reg_A[32:39]>>5;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[40:47]<=reg_A[40:47]>>5;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[44]<=result[40];
result[48:55]<=reg_A[48:55]>>5;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[56:63]<=reg_A[56:63]>>5;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[60]<=result[56];
result[64:71]<=reg_A[64:71]>>5;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[72:79]<=reg_A[72:79]>>5;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[76]<=result[72];
result[80:87]<=reg_A[80:87]>>5;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[88:95]<=reg_A[88:95]>>5;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[92]<=result[88];
result[96:103]<=reg_A[96:103]>>5;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[104:111]<=reg_A[104:111]>>5;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[108]<=result[104];
result[112:119]<=reg_A[112:119]>>5;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[120:127]<=reg_A[120:127]>>5;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
result[124]<=result[120];
end
6:
begin
result[0:7]<=reg_A[0:7]>>6;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[8:15]<=reg_A[8:15]>>6;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[12]<=result[8];
result[13]<=result[8];
result[16:23]<=reg_A[16:23]>>6;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[24:31]<=reg_A[24:31]>>6;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[28]<=result[24];
result[29]<=result[24];
result[32:39]<=reg_A[32:39]>>6;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[40:47]<=reg_A[40:47]>>6;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[44]<=result[40];
result[45]<=result[40];
result[48:55]<=reg_A[48:55]>>6;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[56:63]<=reg_A[56:63]>>6;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[60]<=result[56];
result[61]<=result[56];
result[64:71]<=reg_A[64:71]>>6;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[72:79]<=reg_A[72:79]>>6;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[76]<=result[72];
result[77]<=result[72];
result[80:87]<=reg_A[80:87]>>6;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[88:95]<=reg_A[88:95]>>6;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[92]<=result[88];
result[93]<=result[88];
result[96:103]<=reg_A[96:103]>>6;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[104:111]<=reg_A[104:111]>>6;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[108]<=result[104];
result[109]<=result[104];
result[112:119]<=reg_A[112:119]>>6;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[120:127]<=reg_A[120:127]>>6;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
result[124]<=result[120];
result[125]<=result[120];
end
default: // sra AND `w8 && 7
begin
result[0:7]<=reg_A[0:7]>>7;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[8:15]<=reg_A[8:15]>>7;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[12]<=result[8];
result[13]<=result[8];
result[14]<=result[8];
result[16:23]<=reg_A[16:23]>>7;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[24:31]<=reg_A[24:31]>>7;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[28]<=result[24];
result[29]<=result[24];
result[30]<=result[24];
result[32:39]<=reg_A[32:39]>>7;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[40:47]<=reg_A[40:47]>>7;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[44]<=result[40];
result[45]<=result[40];
result[46]<=result[40];
result[48:55]<=reg_A[48:55]>>7;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[56:63]<=reg_A[56:63]>>7;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[60]<=result[56];
result[61]<=result[56];
result[62]<=result[56];
result[64:71]<=reg_A[64:71]>>7;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[72:79]<=reg_A[72:79]>>7;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[76]<=result[72];
result[77]<=result[72];
result[78]<=result[72];
result[80:87]<=reg_A[80:87]>>7;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[88:95]<=reg_A[88:95]>>7;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[92]<=result[88];
result[93]<=result[88];
result[94]<=result[88];
result[96:103]<=reg_A[96:103]>>7;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[104:111]<=reg_A[104:111]>>7;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[108]<=result[104];
result[109]<=result[104];
result[110]<=result[104];
result[112:119]<=reg_A[112:119]>>7;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[120:127]<=reg_A[120:127]>>7;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
result[124]<=result[120];
result[125]<=result[120];
result[126]<=result[120];
end
endcase
end
`w16: // sra AND `w16
begin
case(reg_B[4:7])
0:
begin
result[0:15]<=reg_A[0:15]>>0;
result[16:31]<=reg_A[16:31]>>0;
result[32:47]<=reg_A[32:47]>>0;
result[48:63]<=reg_A[48:63]>>0;
result[64:79]<=reg_A[64:79]>>0;
result[80:95]<=reg_A[80:95]>>0;
result[96:111]<=reg_A[96:111]>>0;
result[112:127]<=reg_A[112:127]>>0;
end
1:
begin
result[0:15]<=reg_A[0:15]>>1;
result[0]<=result[0];
result[16:31]<=reg_A[16:31]>>1;
result[16]<=result[16];
result[32:47]<=reg_A[32:47]>>1;
result[32]<=result[32];
result[48:63]<=reg_A[48:63]>>1;
result[48]<=result[48];
result[64:79]<=reg_A[64:79]>>1;
result[64]<=result[64];
result[80:95]<=reg_A[80:95]>>1;
result[80]<=result[80];
result[96:111]<=reg_A[96:111]>>1;
result[96]<=result[96];
result[112:127]<=reg_A[112:127]>>1;
result[112]<=result[112];
end
2:
begin
result[0:15]<=reg_A[0:15]>>2;
result[0]<=result[0];
result[1]<=result[0];
result[16:31]<=reg_A[16:31]>>2;
result[16]<=result[16];
result[17]<=result[16];
result[32:47]<=reg_A[32:47]>>2;
result[32]<=result[32];
result[33]<=result[32];
result[48:63]<=reg_A[48:63]>>2;
result[48]<=result[48];
result[49]<=result[48];
result[64:79]<=reg_A[64:79]>>2;
result[64]<=result[64];
result[65]<=result[64];
result[80:95]<=reg_A[80:95]>>2;
result[80]<=result[80];
result[81]<=result[80];
result[96:111]<=reg_A[96:111]>>2;
result[96]<=result[96];
result[97]<=result[96];
result[112:127]<=reg_A[112:127]>>2;
result[112]<=result[112];
result[113]<=result[112];
end
3:
begin
result[0:15]<=reg_A[0:15]>>3;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[16:31]<=reg_A[16:31]>>3;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[32:47]<=reg_A[32:47]>>3;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[48:63]<=reg_A[48:63]>>3;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[64:79]<=reg_A[64:79]>>3;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[80:95]<=reg_A[80:95]>>3;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[96:111]<=reg_A[96:111]>>3;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[112:127]<=reg_A[112:127]>>3;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
end
4:
begin
$display("entered 16 - shift 4");
result[0:15]<=reg_A[0:15]>>4;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[16:31]<=reg_A[16:31]>>4;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[32:47]<=reg_A[32:47]>>4;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[48:63]<=reg_A[48:63]>>4;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[64:79]<=reg_A[64:79]>>4;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[80:95]<=reg_A[80:95]>>4;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[96:111]<=reg_A[96:111]>>4;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[112:127]<=reg_A[112:127]>>4;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
end
5:
begin
result[0:15]<=reg_A[0:15]>>5;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[16:31]<=reg_A[16:31]>>5;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[32:47]<=reg_A[32:47]>>5;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[48:63]<=reg_A[48:63]>>5;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[64:79]<=reg_A[64:79]>>5;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[80:95]<=reg_A[80:95]>>5;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[96:111]<=reg_A[96:111]>>5;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[112:127]<=reg_A[112:127]>>5;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
end
6:
begin
result[0:15]<=reg_A[0:15]>>6;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[16:31]<=reg_A[16:31]>>6;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[32:47]<=reg_A[32:47]>>6;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[48:63]<=reg_A[48:63]>>6;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[64:79]<=reg_A[64:79]>>6;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[80:95]<=reg_A[80:95]>>6;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[96:111]<=reg_A[96:111]>>6;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[112:127]<=reg_A[112:127]>>6;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
end
7:
begin
result[0:15]<=reg_A[0:15]>>7;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[16:31]<=reg_A[16:31]>>7;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[32:47]<=reg_A[32:47]>>7;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[48:63]<=reg_A[48:63]>>7;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[64:79]<=reg_A[64:79]>>7;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[80:95]<=reg_A[80:95]>>7;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[96:111]<=reg_A[96:111]>>7;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[112:127]<=reg_A[112:127]>>7;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
end
8:
begin
$display("entered 16 - shift 8");
result[0:15]<=reg_A[0:15]>>8;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[16:31]<=reg_A[16:31]>>8;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[32:47]<=reg_A[32:47]>>8;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[48:63]<=reg_A[48:63]>>8;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[64:79]<=reg_A[64:79]>>8;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[80:95]<=reg_A[80:95]>>8;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[96:111]<=reg_A[96:111]>>8;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[112:127]<=reg_A[112:127]>>8;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
end
9:
begin
result[0:15]<=reg_A[0:15]>>9;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[16:31]<=reg_A[16:31]>>9;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[32:47]<=reg_A[32:47]>>9;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[48:63]<=reg_A[48:63]>>9;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[64:79]<=reg_A[64:79]>>9;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[80:95]<=reg_A[80:95]>>9;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[96:111]<=reg_A[96:111]>>9;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[112:127]<=reg_A[112:127]>>9;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
end
10:
begin
result[0:15]<=reg_A[0:15]>>10;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[16:31]<=reg_A[16:31]>>10;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[32:47]<=reg_A[32:47]>>10;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[48:63]<=reg_A[48:63]>>10;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[64:79]<=reg_A[64:79]>>10;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[80:95]<=reg_A[80:95]>>10;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[96:111]<=reg_A[96:111]>>10;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[112:127]<=reg_A[112:127]>>10;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
end
11:
begin
result[0:15]<=reg_A[0:15]>>11;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[16:31]<=reg_A[16:31]>>11;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[32:47]<=reg_A[32:47]>>11;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[48:63]<=reg_A[48:63]>>11;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[64:79]<=reg_A[64:79]>>11;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[80:95]<=reg_A[80:95]>>11;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[96:111]<=reg_A[96:111]>>11;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[112:127]<=reg_A[112:127]>>11;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
end
12:
begin
result[0:15]<=reg_A[0:15]>>12;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[16:31]<=reg_A[16:31]>>12;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[32:47]<=reg_A[32:47]>>12;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[48:63]<=reg_A[48:63]>>12;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[64:79]<=reg_A[64:79]>>12;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[80:95]<=reg_A[80:95]>>12;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[96:111]<=reg_A[96:111]>>12;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[112:127]<=reg_A[112:127]>>12;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
end
13:
begin
result[0:15]<=reg_A[0:15]>>13;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[16:31]<=reg_A[16:31]>>13;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[28]<=result[16];
result[32:47]<=reg_A[32:47]>>13;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[48:63]<=reg_A[48:63]>>13;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[60]<=result[48];
result[64:79]<=reg_A[64:79]>>13;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[80:95]<=reg_A[80:95]>>13;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[92]<=result[80];
result[96:111]<=reg_A[96:111]>>13;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[112:127]<=reg_A[112:127]>>13;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
result[124]<=result[112];
end
14:
begin
$display("entered 16 - shift 14");
result[0:15]<=reg_A[0:15]>>14;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[16:31]<=reg_A[16:31]>>14;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[28]<=result[16];
result[29]<=result[16];
result[32:47]<=reg_A[32:47]>>14;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[48:63]<=reg_A[48:63]>>14;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[60]<=result[48];
result[61]<=result[48];
result[64:79]<=reg_A[64:79]>>14;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[80:95]<=reg_A[80:95]>>14;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[92]<=result[80];
result[93]<=result[80];
result[96:111]<=reg_A[96:111]>>14;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[112:127]<=reg_A[112:127]>>14;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
result[124]<=result[112];
result[125]<=result[112];
end
default: // sra AND `w16 && 15
begin
result[0:15]<=reg_A[0:15]>>15;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[16:31]<=reg_A[16:31]>>15;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[28]<=result[16];
result[29]<=result[16];
result[30]<=result[16];
result[32:47]<=reg_A[32:47]>>15;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[48:63]<=reg_A[48:63]>>15;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[60]<=result[48];
result[61]<=result[48];
result[62]<=result[48];
result[64:79]<=reg_A[64:79]>>15;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[80:95]<=reg_A[80:95]>>15;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[92]<=result[80];
result[93]<=result[80];
result[94]<=result[80];
result[96:111]<=reg_A[96:111]>>15;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[112:127]<=reg_A[112:127]>>15;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
result[124]<=result[112];
result[125]<=result[112];
result[126]<=result[112];
end
endcase
end
default: // sra AND `w32:
begin
case(reg_B[5:7])
0:
begin
result[0:31]<=reg_A[0:31]>>0;
result[32:63]<=reg_A[32:63]>>0;
result[64:95]<=reg_A[64:95]>>0;
result[96:127]<=reg_A[96:127]>>0;
end
1:
begin
result[0:31]<=reg_A[0:31]>>1;
result[0]<=result[0];
result[32:63]<=reg_A[32:63]>>1;
result[32]<=result[32];
result[64:95]<=reg_A[64:95]>>1;
result[64]<=result[64];
result[96:127]<=reg_A[96:127]>>1;
result[96]<=result[96];
end
2:
begin
result[0:31]<=reg_A[0:31]>>2;
result[0]<=result[0];
result[1]<=result[0];
result[32:63]<=reg_A[32:63]>>2;
result[32]<=result[32];
result[33]<=result[32];
result[64:95]<=reg_A[64:95]>>2;
result[64]<=result[64];
result[65]<=result[64];
result[96:127]<=reg_A[96:127]>>2;
result[96]<=result[96];
result[97]<=result[96];
end
3:
begin
result[0:31]<=reg_A[0:31]>>3;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[32:63]<=reg_A[32:63]>>3;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[64:95]<=reg_A[64:95]>>3;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[96:127]<=reg_A[96:127]>>3;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
end
4:
begin
result[0:31]<=reg_A[0:31]>>4;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[32:63]<=reg_A[32:63]>>4;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[64:95]<=reg_A[64:95]>>4;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[96:127]<=reg_A[96:127]>>4;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
end
5:
begin
result[0:31]<=reg_A[0:31]>>5;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[32:63]<=reg_A[32:63]>>5;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[64:95]<=reg_A[64:95]>>5;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[96:127]<=reg_A[96:127]>>5;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
end
6:
begin
result[0:31]<=reg_A[0:31]>>6;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[32:63]<=reg_A[32:63]>>6;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[64:95]<=reg_A[64:95]>>6;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[96:127]<=reg_A[96:127]>>6;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
end
7:
begin
result[0:31]<=reg_A[0:31]>>7;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[32:63]<=reg_A[32:63]>>7;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[64:95]<=reg_A[64:95]>>7;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[96:127]<=reg_A[96:127]>>7;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
end
8:
begin
$display("entered 32 - shift 8");
result[0:31]<=reg_A[0:31]>>8;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[32:63]<=reg_A[32:63]>>8;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[64:95]<=reg_A[64:95]>>8;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[96:127]<=reg_A[96:127]>>8;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
end
9:
begin
result[0:31]<=reg_A[0:31]>>9;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[32:63]<=reg_A[32:63]>>9;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[64:95]<=reg_A[64:95]>>9;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[96:127]<=reg_A[96:127]>>9;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
end
10:
begin
result[0:31]<=reg_A[0:31]>>10;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[32:63]<=reg_A[32:63]>>10;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[64:95]<=reg_A[64:95]>>10;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[96:127]<=reg_A[96:127]>>10;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
end
11:
begin
$display("entered 32 - shift 11");
result[0:31]<=reg_A[0:31]>>11;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[32:63]<=reg_A[32:63]>>11;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[64:95]<=reg_A[64:95]>>11;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[96:127]<=reg_A[96:127]>>11;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
end
12:
begin
$display("entered 32 - shift 12");
result[0:31]<=reg_A[0:31]>>12;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[32:63]<=reg_A[32:63]>>12;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[64:95]<=reg_A[64:95]>>12;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[96:127]<=reg_A[96:127]>>12;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
end
13:
begin
result[0:31]<=reg_A[0:31]>>13;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[32:63]<=reg_A[32:63]>>13;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[64:95]<=reg_A[64:95]>>13;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[96:127]<=reg_A[96:127]>>13;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
end
14:
begin
result[0:31]<=reg_A[0:31]>>14;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[32:63]<=reg_A[32:63]>>14;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[64:95]<=reg_A[64:95]>>14;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[96:127]<=reg_A[96:127]>>14;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
end
15:
begin
result[0:31]<=reg_A[0:31]>>15;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[32:63]<=reg_A[32:63]>>15;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[64:95]<=reg_A[64:95]>>15;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[96:127]<=reg_A[96:127]>>15;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
end
16:
begin
$display("entered 32 - shift 16");
result[0:31]<=reg_A[0:31]>>16;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[32:63]<=reg_A[32:63]>>16;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[64:95]<=reg_A[64:95]>>16;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[96:127]<=reg_A[96:127]>>16;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
end
17:
begin
result[0:31]<=reg_A[0:31]>>17;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[32:63]<=reg_A[32:63]>>17;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[64:95]<=reg_A[64:95]>>17;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[96:127]<=reg_A[96:127]>>17;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
end
18:
begin
result[0:31]<=reg_A[0:31]>>18;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[32:63]<=reg_A[32:63]>>18;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[64:95]<=reg_A[64:95]>>18;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[96:127]<=reg_A[96:127]>>18;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
end
19:
begin
result[0:31]<=reg_A[0:31]>>19;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[32:63]<=reg_A[32:63]>>19;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[64:95]<=reg_A[64:95]>>19;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[96:127]<=reg_A[96:127]>>19;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
end
20:
begin
result[0:31]<=reg_A[0:31]>>20;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[32:63]<=reg_A[32:63]>>20;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[64:95]<=reg_A[64:95]>>20;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[96:127]<=reg_A[96:127]>>20;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
end
21:
begin
result[0:31]<=reg_A[0:31]>>21;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[32:63]<=reg_A[32:63]>>21;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[64:95]<=reg_A[64:95]>>21;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[96:127]<=reg_A[96:127]>>21;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
end
22:
begin
result[0:31]<=reg_A[0:31]>>22;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[32:63]<=reg_A[32:63]>>22;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[64:95]<=reg_A[64:95]>>22;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[96:127]<=reg_A[96:127]>>22;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
end
23:
begin
result[0:31]<=reg_A[0:31]>>23;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[32:63]<=reg_A[32:63]>>23;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[64:95]<=reg_A[64:95]>>23;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[96:127]<=reg_A[96:127]>>23;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
end
24:
begin
result[0:31]<=reg_A[0:31]>>24;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[32:63]<=reg_A[32:63]>>24;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[64:95]<=reg_A[64:95]>>24;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[96:127]<=reg_A[96:127]>>24;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
end
25:
begin
result[0:31]<=reg_A[0:31]>>25;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[32:63]<=reg_A[32:63]>>25;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[64:95]<=reg_A[64:95]>>25;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[96:127]<=reg_A[96:127]>>25;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
end
26:
begin
result[0:31]<=reg_A[0:31]>>26;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[32:63]<=reg_A[32:63]>>26;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[64:95]<=reg_A[64:95]>>26;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[96:127]<=reg_A[96:127]>>26;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
end
27:
begin
$display("entered 32 - shift 27");
result[0:31]<=reg_A[0:31]>>27;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[32:63]<=reg_A[32:63]>>27;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[64:95]<=reg_A[64:95]>>27;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[96:127]<=reg_A[96:127]>>27;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
end
28:
begin
result[0:31]<=reg_A[0:31]>>28;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[32:63]<=reg_A[32:63]>>28;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[64:95]<=reg_A[64:95]>>28;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[96:127]<=reg_A[96:127]>>28;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
end
29:
begin
result[0:31]<=reg_A[0:31]>>29;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[28]<=result[0];
result[32:63]<=reg_A[32:63]>>29;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[60]<=result[32];
result[64:95]<=reg_A[64:95]>>29;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[92]<=result[64];
result[96:127]<=reg_A[96:127]>>29;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
result[124]<=result[96];
end
30:
begin
result[0:31]<=reg_A[0:31]>>30;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[28]<=result[0];
result[29]<=result[0];
result[32:63]<=reg_A[32:63]>>30;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[60]<=result[32];
result[61]<=result[32];
result[64:95]<=reg_A[64:95]>>30;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[92]<=result[64];
result[93]<=result[64];
result[96:127]<=reg_A[96:127]>>30;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
result[124]<=result[96];
result[125]<=result[96];
end
default: // sra AND `w32 && 31
begin
result[0:31]<=reg_A[0:31]>>31;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[28]<=result[0];
result[29]<=result[0];
result[30]<=result[0];
result[32:63]<=reg_A[32:63]>>31;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[60]<=result[32];
result[61]<=result[32];
result[62]<=result[32];
result[64:95]<=reg_A[64:95]>>31;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[92]<=result[64];
result[93]<=result[64];
result[94]<=result[64];
result[96:127]<=reg_A[96:127]>>31;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
result[124]<=result[96];
result[125]<=result[96];
result[126]<=result[96];
end
endcase
end
endcase
end
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ppp)
`aa: // aluwsrl AND `aa
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsrl AND `uu
begin
case(ctrl_ww)
`w8: // aluwsrl AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
end
`w16: // aluwsrl AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
end
`w32: // aluwsrl AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsrl AND `dd
begin
case(ctrl_ww)
`w8: // aluwsrl AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsrl AND `ee
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
end
`w16: // aluwsrl AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
end
`w32: // aluwsrl AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
end
default:
begin
// aluwsrl AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsrl AND `oo
begin
case(ctrl_ww)
`w8: // aluwsrl AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsrl AND `mm
begin
case(ctrl_ww)
`w8: // aluwsrl AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
end
`w16: // aluwsrl AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
end
`w32: // aluwsrl AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
end
default:
begin
// aluwsrl AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsrl AND `ll
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsrl AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
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//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
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//================================================================================
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//================================================================================
//================================================================================
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwand AND `aa
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwand AND `uu
begin
case(ctrl_ww)
`w8: // aluwand AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwand AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwand AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwand AND `dd
begin
case(ctrl_ww)
`w8: // aluwand AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwand AND `ee
begin
case(ctrl_ww)
`w8: // aluwand AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwand AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwand AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwand AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwand AND `oo
begin
case(ctrl_ww)
`w8: // aluwand AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwand AND `mm
begin
case(ctrl_ww)
`w8: // aluwand AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwand AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwand AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwand AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwand AND `ll
begin
case(ctrl_ww)
`w8: // aluwand AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwand AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwnot AND `aa
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwnot AND `uu
begin
case(ctrl_ww)
`w8: // aluwnot AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwnot AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwnot AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwnot AND `dd
begin
case(ctrl_ww)
`w8: // aluwnot AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwnot AND `ee
begin
case(ctrl_ww)
`w8: // aluwnot AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwnot AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwnot AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwnot AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwnot AND `oo
begin
case(ctrl_ww)
`w8: // aluwnot AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwnot AND `mm
begin
case(ctrl_ww)
`w8: // aluwnot AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwnot AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwnot AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwnot AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwnot AND `ll
begin
case(ctrl_ww)
`w8: // aluwnot AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwnot AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwor AND `aa
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwor AND `uu
begin
case(ctrl_ww)
`w8: // aluwor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwor AND `dd
begin
case(ctrl_ww)
`w8: // aluwor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwor AND `ee
begin
case(ctrl_ww)
`w8: // aluwor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwor AND `oo
begin
case(ctrl_ww)
`w8: // aluwor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwor AND `mm
begin
case(ctrl_ww)
`w8: // aluwor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwor AND `ll
begin
case(ctrl_ww)
`w8: // aluwor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwor AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ppp)
`aa: // aluwxor AND `aa
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwxor AND `uu
begin
case(ctrl_ww)
`w8: // aluwxor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
end
`w16: // aluwxor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
end
`w32: // aluwxor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwxor AND `dd
begin
case(ctrl_ww)
`w8: // aluwxor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwxor AND `ee
begin
case(ctrl_ww)
`w8: // aluwxor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
end
`w16: // aluwxor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
end
`w32: // aluwxor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
end
default:
begin
// aluwxor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwxor AND `oo
begin
case(ctrl_ww)
`w8: // aluwxor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwxor AND `mm
begin
case(ctrl_ww)
`w8: // aluwxor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
end
`w16: // aluwxor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
end
`w32: // aluwxor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
end
default:
begin
// aluwxor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwxor AND `ll
begin
case(ctrl_ww)
`w8: // aluwxor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwxor AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ppp)
`aa: // aluwsub AND `aa
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsub AND `uu
begin
case(ctrl_ww)
`w8: // aluwsub AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
end
`w16: // aluwsub AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
end
`w32: // aluwsub AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsub AND `dd
begin
case(ctrl_ww)
`w8: // aluwsub AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsub AND `ee
begin
case(ctrl_ww)
`w8: // aluwsub AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
end
`w16: // aluwsub AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
end
`w32: // aluwsub AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
end
default:
begin
// aluwsub AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsub AND `oo
begin
case(ctrl_ww)
`w8: // aluwsub AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsub AND `mm
begin
case(ctrl_ww)
`w8: // aluwsub AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
end
`w16: // aluwsub AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
end
`w32: // aluwsub AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
end
default:
begin
// aluwsub AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsub AND `ll
begin
case(ctrl_ww)
`w8: // aluwsub AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsub AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// PRM instruction
`aluwprm:
begin
case(ctrl_ppp)
`aa: // aluwprm PRM `aa
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`uu: // aluwprm PRM `uu
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//bytes8-15
result[64:127]<=64'd0;
end
`dd: // aluwprm PRM `dd
begin
//bytes0-7
result[0:63]<=64'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[0:7];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`ee: // aluwprm PRM `ee
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//byte1
result[8:15]<=8'd0;
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
//byte3
result[24:31]<=8'd0;
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
//byte5
result[40:47]<=8'd0;
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
//byte7
result[56:63]<=8'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
//byte9
result[72:79]<=8'd0;
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
//byte11
result[88:95]<=8'd0;
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
//byte13
result[104:111]<=8'd0;
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
//byte15
result[120:127]<=8'd0;
end
`oo: // aluwprm PRM `oo
begin
//byte0
result[0:7]<=8'd0;
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
//byte2
result[16:23]<=8'd0;
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
//byte4
result[32:39]<=8'd0;
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
//byte6
result[48:55]<=8'd0;
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//byte8
result[64:71]<=8'd0;
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
//byte10
result[80:87]<=8'd0;
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
//byte12
result[96:103]<=8'd0;
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
//byte14
result[112:119]<=8'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`mm: // aluwprm PRM `mm
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//bytes1-14
result[8:127]<=120'd0;
end
`ll: // aluwprm PRM `ll
begin
//bytes0-14
result[0:119]<=120'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
default: // aluwprm PRM Default
begin
result<=128'd0;
end
endcase
end
/*
* ========================================================
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*=======================================================
*/
// ================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ppp)
`aa: // aluwslli SLLI `aa
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`uu: // aluwslli SLLI `uu
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:127]<=64'd0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:127]<=64'd0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:127]<=64'd0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:127]<=64'd0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:127]<=64'd0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:127]<=64'd0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:127]<=64'd0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:127]<=64'd0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:127]<=64'd0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:127]<=64'd0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:127]<=64'd0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:127]<=64'd0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:127]<=64'd0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:127]<=64'd0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:127]<=64'd0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:127]<=64'd0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:127]<=64'd0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:127]<=64'd0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:127]<=64'd0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:127]<=64'd0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
endcase
end
`dd: // aluwslli SLLI `dd
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
3'd1:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
4'd1:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
5'd1:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`ee: // aluwslli SLLI `ee
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:15]<=8'b0;
result[16:23]<=reg_A[16:23];
result[24:31]<=8'b0;
result[32:39]<=reg_A[33:39];
result[40:47]<=8'b0;
result[48:55]<=reg_A[48:55];
result[56:63]<=8'b0;
result[64:71]<=reg_A[64:71];
result[72:79]<=8'b0;
result[80:87]<=reg_A[80:87];
result[88:95]<=8'b0;
result[96:103]<=reg_A[96:103];
result[104:111]<=8'b0;
result[112:119]<=reg_A[112:119];
result[120:127]<=8'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<=8'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<=8'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<=8'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<=8'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<=8'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<=8'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<=8'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<=16'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<=16'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<=16'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<=16'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<=16'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<=16'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<=16'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<=16'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<=16'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<=16'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<=16'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<=16'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<=16'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<=16'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<=16'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<=32'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<=32'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<=32'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<=32'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<=32'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<=32'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<=32'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<=32'b0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<=32'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<=32'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<=32'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<=32'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<=32'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<=32'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<=32'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<=32'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<=32'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<=32'b0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<=32'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<=32'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<=32'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<=32'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<=32'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<=32'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<=32'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<=32'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<=32'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<=32'b0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<=32'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<=32'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<=32'b0;
end
endcase
end
endcase
end
`oo: // aluwslli SLLI `oo
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`mm: // aluwslli SLLI `mm
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:127]<=119'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:127]<=119'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:127]<=119'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:127]<=119'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:127]<=119'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:127]<=119'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:127]<=119'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:127]<=119'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:15]<=reg_A[0:15];
result[16:127]<=112'b0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:127]<=112'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:127]<=112'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:127]<=112'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:127]<=112'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:127]<=112'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:127]<=112'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:127]<=112'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:127]<=112'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:127]<=112'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:127]<=112'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:127]<=112'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:127]<=112'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:127]<=112'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:127]<=112'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:127]<=112'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:31]<=reg_A[0:31];
result[32:127]<=96'b0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:127]<=96'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:127]<=96'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:127]<=96'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:127]<=96'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:127]<=96'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:127]<=96'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:127]<=96'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:127]<=96'b0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:127]<=96'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:127]<=96'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:127]<=96'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:127]<=96'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:127]<=96'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:127]<=96'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:127]<=96'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:127]<=96'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:127]<=96'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:127]<=96'b0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:127]<=96'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:127]<=96'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:127]<=96'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:127]<=96'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:127]<=96'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:127]<=96'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:127]<=96'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:127]<=96'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:127]<=96'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:127]<=96'b0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:127]<=96'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:127]<=96'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:127]<=96'b0;
end
endcase
end
endcase
end
`ll: // aluwslli SLLI `ll
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:119]<=120'b0;
result[120:127]<=reg_A[120:127];
end
3'd1:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:111]<=112'b0;
result[112:127]<=reg_A[112:127];
end
4'd1:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:95]<=96'b0;
result[96:127]<=reg_A[96:127];
end
5'd1:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule |
module tb_func_level;
`include "../task/task_disp_inst_issue.v"
`include "../task/task_disp_pcr.v"
`include "../task/task_disp_tag_info.v"
`include "../task/task_disp_branch.v"
`include "../task/task_disp_loadstore.v"
`include "../task/task_disp_logic_register.v"
localparam PL_CORE_CYCLE = 20; //It's necessary "Core Clock == Bus Clock". This restriction is removed near future.
localparam PL_BUS_CYCLE = 20; //
localparam PL_DPS_CYCLE = 18;
localparam PL_RESET_TIME = 20;
localparam PL_GCI_SIZE = 32'h0001_0000;
/****************************************
System
****************************************/
reg iCORE_CLOCK;
reg iBUS_CLOCK;
reg iDPS_CLOCK;
reg inRESET;
/****************************************
SCI
****************************************/
wire oSCI_TXD;
reg iSCI_RXD;
/****************************************
Memory BUS
****************************************/
//Req
wire oMEMORY_REQ;
wire iMEMORY_LOCK;
wire [1:0] oMEMORY_ORDER; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
wire [3:0] oMEMORY_MASK;
wire oMEMORY_RW; //1:Write | 0:Read
wire [31:0] oMEMORY_ADDR;
//This -> Data RAM
wire [31:0] oMEMORY_DATA;
//Data RAM -> This
wire iMEMORY_VALID;
wire oMEMORY_BUSY;
wire [63:0] iMEMORY_DATA;
/****************************************
GCI BUS
****************************************/
//Request
wire oGCI_REQ; //Input
reg iGCI_BUSY;
wire oGCI_RW; //0=Read : 1=Write
wire [31:0] oGCI_ADDR;
wire [31:0] oGCI_DATA;
//Return
reg iGCI_REQ; //Output
wire oGCI_BUSY;
reg [31:0] iGCI_DATA;
//Interrupt
reg iGCI_IRQ_REQ;
reg [5:0] iGCI_IRQ_NUM;
wire oGCI_IRQ_ACK;
//Interrupt Controll
wire oIO_IRQ_CONFIG_TABLE_REQ;
wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY;
wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK;
wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID;
wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL;
wire [31:0] oDEBUG_PC;
wire [31:0] oDEBUG0;
/****************************************
Debug
****************************************/
reg iDEBUG_UART_RXD;
wire oDEBUG_UART_TXD;
reg iDEBUG_PARA_REQ;
wire oDEBUG_PARA_BUSY;
reg [7:0] iDEBUG_PARA_CMD;
reg [31:0] iDEBUG_PARA_DATA;
wire oDEBUG_PARA_VALID;
reg iDEBUG_PARA_BUSY;
wire oDEBUG_PARA_ERROR;
wire [31:0] oDEBUG_PARA_DATA;
/******************************************************
Target
******************************************************/
mist1032sa TARGET(
/****************************************
System
****************************************/
.iCORE_CLOCK(iCORE_CLOCK),
.iBUS_CLOCK(iBUS_CLOCK),
.iDPS_CLOCK(iDPS_CLOCK),
.inRESET(inRESET),
/****************************************
SCI
****************************************/
.oSCI_TXD(oSCI_TXD),
.iSCI_RXD(iSCI_RXD),
/****************************************
Memory BUS
****************************************/
//Req
.oMEMORY_REQ(oMEMORY_REQ),
.iMEMORY_LOCK(iMEMORY_LOCK),
.oMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oMEMORY_MASK(oMEMORY_MASK),
.oMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.oMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.oMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.iMEMORY_VALID(iMEMORY_VALID),
.oMEMORY_BUSY(oMEMORY_BUSY),
.iMEMORY_DATA(iMEMORY_DATA),
/****************************************
GCI BUS
****************************************/
//Request
.oGCI_REQ(oGCI_REQ), //Input
.iGCI_BUSY(iGCI_BUSY),
.oGCI_RW(oGCI_RW), //0=Read : 1=Write
.oGCI_ADDR(oGCI_ADDR),
.oGCI_DATA(oGCI_DATA),
//Return
.iGCI_REQ(iGCI_REQ), //Output
.oGCI_BUSY(oGCI_BUSY),
.iGCI_DATA(iGCI_DATA),
//Interrupt
.iGCI_IRQ_REQ(iGCI_IRQ_REQ),
.iGCI_IRQ_NUM(iGCI_IRQ_NUM),
.oGCI_IRQ_ACK(oGCI_IRQ_ACK),
//Interrupt Controll
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
.oDEBUG_PC(oDEBUG_PC),
.oDEBUG0(oDEBUG0),
/****************************************
Debug
****************************************/
.iDEBUG_UART_RXD(iDEBUG_UART_RXD),
.oDEBUG_UART_TXD(oDEBUG_UART_TXD),
.iDEBUG_PARA_REQ(iDEBUG_PARA_REQ),
.oDEBUG_PARA_BUSY(oDEBUG_PARA_BUSY),
.iDEBUG_PARA_CMD(iDEBUG_PARA_CMD),
.iDEBUG_PARA_DATA(iDEBUG_PARA_DATA),
.oDEBUG_PARA_VALID(oDEBUG_PARA_VALID),
.iDEBUG_PARA_BUSY(iDEBUG_PARA_BUSY),
.oDEBUG_PARA_ERROR(oDEBUG_PARA_ERROR),
.oDEBUG_PARA_DATA(oDEBUG_PARA_DATA)
);
/******************************************************
Clock
******************************************************/
always#(PL_CORE_CYCLE/2)begin
iCORE_CLOCK = !iCORE_CLOCK;
end
always#(PL_BUS_CYCLE/2)begin
iBUS_CLOCK = !iBUS_CLOCK;
end
always#(PL_DPS_CYCLE/2)begin
iDPS_CLOCK = !iDPS_CLOCK;
end
/******************************************************
State
******************************************************/
initial begin
$display("Check Start");
//Initial
iCORE_CLOCK = 1'b0;
iBUS_CLOCK = 1'b0;
iDPS_CLOCK = 1'b0;
inRESET = 1'b0;
iSCI_RXD = 1'b1;
iGCI_BUSY = 1'b0;
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
iGCI_IRQ_REQ = 1'b0;
iGCI_IRQ_NUM = 6'h0;
iDEBUG_UART_RXD = 1'b1;
iDEBUG_PARA_REQ = 1'b0;
iDEBUG_PARA_CMD = 8'h0;
iDEBUG_PARA_DATA = 32'h0;
iDEBUG_PARA_BUSY = 1'b0;
//Reset After
#(PL_RESET_TIME);
inRESET = 1'b1;
//GCI Init
#(PL_BUS_CYCLE*32);
while(oGCI_BUSY) #(PL_BUS_CYCLE);
iGCI_REQ = 1'b1;
iGCI_DATA = PL_GCI_SIZE;
#(PL_BUS_CYCLE);
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
#15000000 begin
$finish;
end
end
/******************************************************
Memory Model
******************************************************/
sim_memory_model #(1, "tb_func_test.hex") MEMORY_MODEL(
.iCLOCK(iCORE_CLOCK),
.inRESET(inRESET),
//Req
.iMEMORY_REQ(oMEMORY_REQ),
.oMEMORY_LOCK(iMEMORY_LOCK),
.iMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.iMEMORY_MASK(oMEMORY_MASK),
.iMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.iMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.iMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.oMEMORY_VALID(iMEMORY_VALID),
.iMEMORY_LOCK(oMEMORY_BUSY),
.oMEMORY_DATA(iMEMORY_DATA)
);
/******************************************************
Display Dump
******************************************************/
always@(posedge iCORE_CLOCK)begin
if(inRESET)begin
//task_disp_inst_issue();
//task_disp_pcr();
//task_disp_tag_info();
task_disp_branch();
task_disp_loadstore();
//task_disp_logic_register_all();
//task_disp_logic_register_single(5'h2);
end
end
/******************************************************
Assertion
******************************************************/
reg assert_check_flag;
reg [31:0] assert_wrong_number;
reg [31:0] assert_wrong_type;
reg [31:0] assert_result;
reg [31:0] assert_expect;
always@(posedge iCORE_CLOCK)begin
if(inRESET && oMEMORY_REQ && !iMEMORY_LOCK && oMEMORY_ORDER == 2'h2 && oMEMORY_RW)begin
//Finish Check
if(oMEMORY_ADDR == 32'h0002_0004)begin
if(!assert_check_flag)begin
$display("[SIM-ERR]Wrong Data.");
$display("[SIM-ERR]Wrong Type : %d", assert_wrong_type);
$display("[SIM-ERR]Index:%d, Expect:%x, Result:%x", assert_wrong_number, assert_expect, assert_result);
$display("[SIM-ERR]Simulation Finished.");
$finish;
end
else begin
$display("[SIM-OK]Simulation Finished.");
$finish;
end
end
//Check Log
else if(oMEMORY_ADDR == 32'h0002_0008)begin
$display("[SIM-LOG]#d", {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]});
end
//Check Flag
else if(oMEMORY_ADDR == 32'h0002_0000)begin
assert_check_flag = oMEMORY_DATA[24];
end
//Error Number
else if(oMEMORY_ADDR == 32'h0002_0010)begin
assert_wrong_number = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Type
else if(oMEMORY_ADDR == 32'h0002_000c)begin
assert_wrong_type = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Result
else if(oMEMORY_ADDR == 32'h0002_0014)begin
assert_result = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Expect
else if(oMEMORY_ADDR == 32'h0002_0018)begin
assert_expect = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
end
end
endmodule |
module gtx_8x10enc(
input wire rst,
input wire clk,
input wire [1:0] inisk,
input wire [15:0] indata,
output wire [19:0] outdata
);
// addresses to reference an encoding table
wire [8:0] addr0;
wire [8:0] addr1;
assign addr0 = {inisk[0], indata[7:0]};
assign addr1 = {inisk[1], indata[15:8]};
// possible encoded data - both disparities, for both bytes
// due to registered memory output, this values will be valid after 2 clock cycles
// table[i] [9:0] in case of current disparity +, [19:10] in case of -
wire [31:0] table0_out;
wire [31:0] table1_out;
reg [19:0] table0_r;
reg [19:0] table1_r;
wire [19:0] table0;
wire [19:0] table1;
assign table0 = table0_out[19:0];
assign table1 = table1_out[19:0];
always @ (posedge clk)
begin
table0_r <= table0;
table1_r <= table1;
end
// encoded bytes
wire [9:0] enc0;
wire [9:0] enc1;
//reg [9:0] enc0_r;
//reg [9:0] enc1_r;
// running displarity, 0 = -, 1 = +
reg disparity;
// running disparity after encoding 1st byte
wire disparity_interm;
// invert disparity after a byte
// if current encoded word containg an equal amount of 1s and 0s (i.e. 5 x '1'), disp shall stay the same
// if amounts are unequal, there are either 4 or 6 '1's. in either case disp shall be inverted
wire inv_disp0;
wire inv_disp1;
assign inv_disp0 = ~^enc0;
assign inv_disp1 = ~^enc1;
assign disparity_interm = inv_disp0 ? ~disparity : disparity;
always @ (posedge clk)
disparity <= rst ? 1'b0 : inv_disp1 ^ inv_disp0 ? ~disparity : disparity;
// select encoded bytes depending on a previous disparity
assign enc0 = {10{~disparity}} & table0_r[19:10] | {10{disparity}} & table0_r[9:0];
assign enc1 = {10{~disparity_interm}} & table1_r[19:10] | {10{disparity_interm}} & table1_r[9:0];
// latch output data
reg [19:0] outdata_l;
assign outdata = outdata_l;
always @ (posedge clk)
outdata_l <= {enc1, enc0};
ramt_var_w_var_r #(
.REGISTERS_A (1),
.REGISTERS_B (1),
.LOG2WIDTH_A (5),
.LOG2WIDTH_B (5)
`include "gtx_8x10enc_init.v"
)
encoding_table(
.clk_a (clk),
.addr_a ({1'b0, addr0}),
.en_a (1'b1),
.regen_a (1'b1),
.we_a (1'b0),
.data_out_a (table0_out),
.data_in_a (32'h0),
.clk_b (clk),
.addr_b ({1'b0, addr1}),
.en_b (1'b1),
.regen_b (1'b1),
.we_b (1'b0),
.data_out_b (table1_out),
.data_in_b (32'h0)
);
`ifdef CHECKERS_ENABLED
reg [8:0] addr0_r;
reg [8:0] addr1_r;
reg [8:0] addr0_rr;
reg [8:0] addr1_rr;
always @ (posedge clk)
begin
addr0_r <= addr0;
addr1_r <= addr1;
addr0_rr <= addr0_r;
addr1_rr <= addr1_r;
end
always @ (posedge clk)
if (~rst)
if (|table0 | |table1) begin
// all good
end
else begin
// got xxxx or 0000, both cases tell us addresses were bad
$display("Error in %m: bad incoming data: 1) K = %h, Data = %h 2) K = %h, Data = %h", addr0_rr[8], addr0_rr[7:0], addr1_rr[8], addr1_rr[7:0]);
repeat (10) @(posedge clk);
$finish;
end
`endif // CHECKERS_ENABLED
endmodule |
module clk_wiz_0(clk_in1, clk_out1, reset, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */;
input clk_in1;
output clk_out1;
input reset;
output locked;
endmodule |
module sync_fifo #(
parameter DEPTH = 3,
parameter DATA_W = 32,
parameter ASSERT_OVERFLOW = 1,
parameter ASSERT_UNDERFLOW = 1,
parameter ENABLE_BYPASS = 0
)
(
input clk,
input rstn,
input [DATA_W-1:0] fifo_data_in,
input fifo_push,
output [DATA_W-1:0] fifo_data_out,
input fifo_pop,
output fifo_full,
output fifo_empty,
input fifo_flush
);
localparam DEPTH_LOG2 = `CLOG2(DEPTH);
reg [DATA_W-1:0] mem [0:DEPTH-1];
reg [DEPTH_LOG2-1:0] head, n_head;
reg [DEPTH_LOG2-1:0] tail, n_tail;
wire empty;
wire full;
reg push_last;
assign fifo_data_out = mem[tail];
assign fifo_full = full;
assign fifo_empty = empty;
always @ (*) begin
if (head < DEPTH-1) begin
n_head = head + 'h1;
end
else begin
n_head = 'h0;
end
end
always @ (*) begin
if (tail < DEPTH-1) begin
n_tail = tail + 'h1;
end
else begin
n_tail = 'h0;
end
end
generate
if (ENABLE_BYPASS) begin
assign full = (push_last && (head == tail) && !fifo_pop) ? 1'b1 : 1'b0;
assign empty = (!push_last && (head == tail) && !fifo_push) ? 1'b1 : 1'b0;
end
else begin
assign full = (push_last && (head == tail)) ? 1'b1 : 1'b0;
assign empty = (!push_last && (head == tail)) ? 1'b1 : 1'b0;
end
endgenerate
generate
if (ASSERT_OVERFLOW) begin
always @ (posedge clk) begin
if (clk && !fifo_flush && fifo_push && full) begin
$display("ERROR: FIFO OVERFLOW");
$finish;
end
end
end
if (ASSERT_UNDERFLOW) begin
always @ (posedge clk) begin
if (clk && !fifo_flush && fifo_pop && empty) begin
$display("ERROR: FIFO UNDERFLOW");
$finish;
end
end
end
endgenerate
always @ (posedge clk, negedge rstn) begin
if (~rstn) begin
head <= 'h0;
tail <= 'h0;
push_last <= 'h0;
end
else begin
if (fifo_flush) begin
tail <= 'h0;
head <= 'h0;
push_last <= 'h0;
end
else if (!((full && fifo_push) || (empty && fifo_pop))) begin
if (fifo_push) begin
mem[head] <= fifo_data_in;
head <= n_head;
end
if (fifo_pop) begin
tail <= n_tail;
end
if (fifo_push && !fifo_pop) begin
push_last = 'h1;
end
else if (!fifo_push && fifo_pop) begin
push_last = 'h0;
end
end
end
end
endmodule |
module altera_dpram_16x32 (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.clocken1 (1'b1),
.clocken0 (1'b1),
.q_a (),
.data_b ({32{1'b1}}),
.rden_b (1'b1),
.wren_b (1'b0),
.byteena_b (1'b1),
.addressstall_a (1'b0),
.byteena_a (1'b1),
.addressstall_b (1'b0),
.clock1 (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule |
module clocks(
input rst,
input clk50,
input divide_more,
input clk_dac_sel,
output clk_cpu,
output locked,
output clk_dac,
output reg rst_clk4,
output E,
output Q
);
wire clk_base; // 4*3.58MHz
reg [1:0] clk4_cnt;
reg Qr, Er;
reg clk_dac_sel2, clk_dac_aux;
always @(negedge clk_base)
clk_dac_sel2 <= clk_dac_sel;
reg dac_cnt;
always @(posedge clk_base or posedge rst)
if( rst )
dac_cnt <= 1'b0;
else begin
if( clk_dac_sel2 )
clk_dac_aux <= ~clk_dac_aux;
else
{ clk_dac_aux, dac_cnt } <= { clk_dac_aux, dac_cnt } + 1'b1;
end
// BUFG dacbuf( .I(clk_dac_aux), .O(clk_dac) );
// assign clk_dac = clk_base;
// assign clk_dac = clk4_cnt[0];
assign clk_dac = Er;
always @(posedge clk_base or posedge rst)
if (rst) begin
clk4_cnt <= 0;
{ Er, Qr } <= 2'b0;
end
else begin
clk4_cnt <= clk4_cnt+2'b01;
case( clk4_cnt )
2'b00: Qr <= 1; // RISING EDGE OF E
2'b01: Er <= 1; // RISING EDGE OF Q
2'b10: Qr <= 0; // FALLING EDGE OF E
2'b11: Er <= 0; // FALLING EDGE OF Q
endcase
end
BUFG ebuf( .I(Er), .O(E) );
BUFG qbuf( .I(Qr), .O(Q) );
reg rst_clk4_aux;
always @(negedge Q)
{ rst_clk4, rst_clk4_aux } <= { rst_clk4_aux, rst };
reg [1:0] clk_cpu_cnt;
always @( posedge clk_base or posedge rst)
if( rst )
clk_cpu_cnt <= 2'b0;
else
clk_cpu_cnt <= clk_cpu_cnt + 1'b1;
reg clk_sel;
always @( negedge clk_base )
clk_sel <= divide_more;
BUFG CLKDV_BUFG_INST(
.I( clk_sel ? clk_cpu_cnt[0] : clk_base ),
.O(clk_cpu)
);
// clk_base = clk50*2/7 = 14.28MHz
clk50div u_clk50div (
.CLKIN_IN(clk50),
.RST_IN(rst),
.CLKFX_OUT(clk_base),
//.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
//.CLK0_OUT(CLK0_OUT),
.LOCKED_OUT(locked)
);
endmodule |
module alu (
input wire [`WordDataBus] in_0, // üÍ 0
input wire [`WordDataBus] in_1, // üÍ 1
input wire [`AluOpBus] op, // Iy[V
output reg [`WordDataBus] out, // oÍ
output reg of // I[ot[
);
/********** t«üoÍM **********/
wire signed [`WordDataBus] s_in_0 = $signed(in_0); // t«üÍ 0
wire signed [`WordDataBus] s_in_1 = $signed(in_1); // t«üÍ 1
wire signed [`WordDataBus] s_out = $signed(out); // t«oÍ
/********** Zp_Z **********/
always @(*) begin
case (op)
`ALU_OP_AND : begin // _ÏiANDj
out = in_0 & in_1;
end
`ALU_OP_OR : begin // _aiORj
out = in_0 | in_1;
end
`ALU_OP_XOR : begin // r¼I_aiXORj
out = in_0 ^ in_1;
end
`ALU_OP_ADDS : begin // t«ÁZ
out = in_0 + in_1;
end
`ALU_OP_ADDU : begin // ȵÁZ
out = in_0 + in_1;
end
`ALU_OP_SUBS : begin // t«¸Z
out = in_0 - in_1;
end
`ALU_OP_SUBU : begin // ȵ¸Z
out = in_0 - in_1;
end
`ALU_OP_SHRL : begin // _EVtg
out = in_0 >> in_1[`ShAmountLoc];
end
`ALU_OP_SHLL : begin // _¶Vtg
out = in_0 << in_1[`ShAmountLoc];
end
default : begin // ftHgl (No Operation)
out = in_0;
end
endcase
end
/********** I[ot[`FbN **********/
always @(*) begin
case (op)
`ALU_OP_ADDS : begin // ÁZI[ot[Ì`FbN
if (((s_in_0 > 0) && (s_in_1 > 0) && (s_out < 0)) ||
((s_in_0 < 0) && (s_in_1 < 0) && (s_out > 0))) begin
of = `ENABLE;
end else begin
of = `DISABLE;
end
end
`ALU_OP_SUBS : begin // ¸ZI[ot[Ì`FbN
if (((s_in_0 < 0) && (s_in_1 > 0) && (s_out > 0)) ||
((s_in_0 > 0) && (s_in_1 < 0) && (s_out < 0))) begin
of = `ENABLE;
end else begin
of = `DISABLE;
end
end
default : begin // ftHgl
of = `DISABLE;
end
endcase
end
endmodule |
module tri_intersect_data_array_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk);
parameter DWIDTH = 576;
parameter AWIDTH = 5;
parameter MEM_SIZE = 20;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
q1 <= d1;
end
else
q1 <= ram[addr1];
end
end
endmodule |
module tri_intersect_data_array(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1);
parameter DataWidth = 32'd576;
parameter AddressRange = 32'd20;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
output[DataWidth - 1:0] q1;
tri_intersect_data_array_ram tri_intersect_data_array_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ),
.q1( q1 ));
endmodule |
module must to accept SRIO packet from DSP side,
save data (which was in packet) in DDR (on current time in FIFO),
and send response packet with data (if was get NREAD request);
In this part we accept packet by SRIO IP (srio_ip),
transfer data into srio_response, save their in FIFO and
transfer it back
*/
srio_response srio_rx(
.log_clk ( log_clk ),
.log_rst ( log_rst ),
.src_id ( deviceid ),
.id_override ( 1'b0 ),
// Regs with request data (from DSP to FPGA)
.axis_iorx_tvalid ( iorx_tvalid ),
.axis_iorx_tready ( iorx_tready ),
.axis_iorx_tlast ( iorx_tlast ),
.axis_iorx_tdata ( iorx_tdata ),
.axis_iorx_tkeep ( iorx_tkeep ),
.axis_iorx_tuser ( iorx_tuser ),
// Regs with response data (from FPGA to DSP)
.axis_iotx_tvalid ( iotx_tvalid ),
.axis_iotx_tlast ( iotx_tlast ),
.axis_iotx_tdata ( iotx_tdata ),
.axis_iotx_tkeep ( iotx_tkeep ),
.axis_iotx_tuser ( iotx_tuser ),
.axis_iotx_tready ( iotx_tready )
);
srio_gen2_0 srio_ip(
.sys_clkp ( sys_clkp ),
.sys_clkn ( sys_clkn ),
.sys_rst ( sys_rst ),
// all clocks as output in shared logic mode
.log_clk_out ( log_clk ),
.phy_clk_out ( phy_clk ),
.gt_clk_out ( gt_clk ),
.gt_pcs_clk_out ( gt_pcs_clk ),
.drpclk_out ( drpclk ),
.refclk_out ( refclk ),
.clk_lock_out ( clk_lock ),
// all resets as output in shared logic mode
.log_rst_out ( log_rst ),
.phy_rst_out ( phy_rst ),
.buf_rst_out ( buf_rst ),
.cfg_rst_out ( cfg_rst ),
.gt_pcs_rst_out ( gt_pcs_rst ),
.gt0_qpll_clk_out ( gt0_qpll_clk_out ),
.gt0_qpll_out_refclk_out ( gt0_qpll_out_refclk_out ),
// Serial IO Interface
.srio_rxn0 ( srio_rxn0 ),
.srio_rxp0 ( srio_rxp0 ),
.srio_rxn1 ( srio_rxn1 ),
.srio_rxp1 ( srio_rxp1 ),
/*.srio_rxn2 ( srio_rxn2 ),
.srio_rxp2 ( srio_rxp2 ),
.srio_rxn3 ( srio_rxn3 ),
.srio_rxp3 ( srio_rxp3 ),*/
.srio_txn0 ( srio_txn0 ),
.srio_txp0 ( srio_txp0 ),
.srio_txn1 ( srio_txn1 ),
.srio_txp1 ( srio_txp1 ),
/*.srio_txn2 ( srio_txn2 ),
.srio_txp2 ( srio_txp2 ),
.srio_txn3 ( srio_txn3 ),
.srio_txp3 ( srio_txp3 ),*/
// LOG User I/O Interface
.s_axis_iotx_tvalid ( iotx_tvalid ),
.s_axis_iotx_tready ( iotx_tready ), // output
.s_axis_iotx_tlast ( iotx_tlast ),
.s_axis_iotx_tdata ( iotx_tdata ),
.s_axis_iotx_tkeep ( iotx_tkeep ),
.s_axis_iotx_tuser ( iotx_tuser ),
.m_axis_iorx_tvalid ( iorx_tvalid ),
.m_axis_iorx_tready ( iorx_tready ), // input
.m_axis_iorx_tlast ( iorx_tlast ),
.m_axis_iorx_tdata ( iorx_tdata ),
.m_axis_iorx_tkeep ( iorx_tkeep ),
.m_axis_iorx_tuser ( iorx_tuser ),
// Maintenance Port Interface
.s_axi_maintr_rst ( maintr_rst ),
.s_axi_maintr_awvalid ( maintr_awvalid ),
.s_axi_maintr_awready ( maintr_awready ),
.s_axi_maintr_awaddr ( maintr_awaddr ),
.s_axi_maintr_wvalid ( maintr_wvalid ),
.s_axi_maintr_wready ( maintr_wready ),
.s_axi_maintr_wdata ( maintr_wdata ),
.s_axi_maintr_bvalid ( maintr_bvalid ),
.s_axi_maintr_bready ( maintr_bready ),
.s_axi_maintr_bresp ( maintr_bresp ),
.s_axi_maintr_arvalid ( maintr_arvalid ),
.s_axi_maintr_arready ( maintr_arready ),
.s_axi_maintr_araddr ( maintr_araddr ),
.s_axi_maintr_rvalid ( maintr_rvalid ),
.s_axi_maintr_rready ( maintr_rready ),
.s_axi_maintr_rdata ( maintr_rdata ),
.s_axi_maintr_rresp ( maintr_rresp ),
// PHY control signa
.sim_train_en ( sim_train_en ),
.phy_mce ( phy_mce ),
.phy_link_reset ( phy_link_reset ),
.force_reinit ( force_reinit ),
// Core debug signals
.phy_rcvd_mce ( phy_rcvd_mce ),
.phy_rcvd_link_reset ( phy_rcvd_link_reset ),
.phy_debug ( phy_debug ),
.gtrx_disperr_or ( gtrx_disperr_or ),
.gtrx_notintable_or ( gtrx_notintable_or ),
// Side band signals
.port_error ( port_error ),
.port_timeout ( port_timeout ),
.srio_host ( srio_host ),
// LOG Informational signals
.port_decode_error ( port_decode_error ),
.deviceid ( deviceid ),
.idle2_selected ( idle2_selected ),
.phy_lcl_master_enable_out (), // these are side band output only signals
.buf_lcl_response_only_out (),
.buf_lcl_tx_flow_control_out (),
.buf_lcl_phy_buf_stat_out (),
.phy_lcl_phy_next_fm_out (),
.phy_lcl_phy_last_ack_out (),
.phy_lcl_phy_rewind_out (),
.phy_lcl_phy_rcvd_buf_stat_out (),
.phy_lcl_maint_only_out (),
// PHY Informational signals
.port_initialized ( port_init ),
.link_initialized ( link_init ),
.idle_selected ( idle_selected ),
.mode_1x ( mode_1x )
);
endmodule |
module sky130_fd_sc_hs__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule |
module clk_gen(
input wire button,
input wire clk,
input wire res,
output wire clk_div
);
reg [3 : 0] ripple;
assign clk_div = &ripple;
always @(posedge clk) begin
if(res)
ripple <= 4'b0;
else begin
ripple[0] <= button;
ripple[1] <= ripple[0];
ripple[2] <= ripple[1];
ripple[3] <= ripple[2];
end
end
endmodule |
module sha256(input clk, input [7:0] in[0:79], input [31:0] job, input doWork, output reg[7:0] resultOut[0:31], output reg[31:0] resultJobOut, output reg[31:0] resultNonceOut, output reg resultAvailable);
//unroll parameter
parameter unroll = 4;
//sha initial digest constant
wire [31:0] H [0:7];
//initial digest (sha state)
assign H = '{32'h6a09e667, 32'hbb67ae85, 32'h3c6ef372, 32'ha54ff53a, 32'h510e527f, 32'h9b05688c, 32'h1f83d9ab, 32'h5be0cd19};
//actual work registers
reg[7:0] workBuffer[0:79];
reg[31:0] currentJob;
reg midstateReady;
reg[31:0] midstate[0:7];
//signals that there is task to be scheduled
reg scheduleTask;
//interconnection wires and regs for first pipeline follow
//task state wire and reg
reg[31:0] stateOut;
wire[31:0] stateIn;
//digest wires and registers
reg[31:0] digestOut[0:7];
reg[31:0] digestOutOriginal[0:7];
wire [31:0] digestIn [0:7];
wire [31:0] digestInOriginal [0:7];
//wires for first phase midstate computation
//second part with 12 header bytes + nonce and padding
wire[7:0] firstStageSecondPart[0:63];
wire[7:0] dataIn[0:63];
//used for words
reg[31:0] wordsOut[0:15];
wire[31:0] wordsIn[0:15];
//nonce vars
reg[31:0] nonceOut;
wire[31:0] nonceIn;
//job vars
reg[31:0] jobOut;
wire[31:0] jobIn;
//pipeline for first part of computation
sha_pipeline #(unroll) shap(clk, stateOut, digestOut, digestOutOriginal, wordsOut, jobOut, nonceOut, digestIn, digestInOriginal, wordsIn, stateIn, jobIn, nonceIn);
//wires and regs for internal connection with second pipeline
reg[31:0] stateOutb;
wire[31:0] stateInb;
reg[31:0] nonceOutb;
wire[31:0] nonceInb;
reg[31:0] digestOutb[0:7];
wire [31:0] digestInb [0:7];
reg[31:0] digestOutOriginalb[0:7];
wire [31:0] digestInOriginalb [0:7];
reg[31:0] wordsOutb[0:15];
wire[31:0] wordsInb[0:15];
reg[31:0] jobOutb;
wire[31:0] jobInb;
//pipeline for second part of computation
sha_pipeline #(unroll) shapb(clk, stateOutb, digestOutb, digestOutOriginalb, wordsOutb, jobOutb, nonceOutb, digestInb, digestInOriginalb, wordsInb, stateInb, jobInb, nonceInb);
//put second part of input data to queue, used only at several initial cycles after job submition (midstate is not known)
shaqueue #(.elementWidth(8), .elementCount(64), .depth(1 + unroll)) fsspq(clk, (firstPipelineReady & scheduleTask & ~midstateReady), midstateStageReady, firstStageSecondPart, dataIn);
//inputs for each stage
wire[7:0] stageTwoPadding[0:31];
//combinationals needed to assemble new data to hash (paddings, nonces...)
reg[31:0] newNonce;
wire [31:0] newDigest[0:7];
always @(*) begin
for(int i =0; i < 8; i++) begin
newDigest[i] = (digestIn[i] + digestInOriginal[i]);
end
//this is maybe not the best way to set this up, but i find it readable and easy to understand
firstStageSecondPart[0:11] = workBuffer[64:75];
//assembly nonce for new sha hashing
firstStageSecondPart[15] = newNonce;
firstStageSecondPart[14] = (newNonce >> 8);
firstStageSecondPart[13] = (newNonce >> 16);
firstStageSecondPart[12] = (newNonce >> 24);
//padding to 128 bytes of 80B input (first stage second sha part)
firstStageSecondPart[16] = 128;
for(int i =1; i < 46; i++) begin
firstStageSecondPart[16+i] = 0;
end
firstStageSecondPart[62] = 2;
firstStageSecondPart[63] = 128;
//padding for second stage input
stageTwoPadding[0] = 128;
for(int i =1; i < 30; i++) begin
stageTwoPadding[i] = 0;
end
stageTwoPadding[30] = 1;
stageTwoPadding[31] = 0;
end
//some states to be easilly readable
wire firstPipelineWorkIn = stateIn[31];
wire firstStageReady = (stateIn[7:0] == 128);
wire firstPipelineReady = ~firstPipelineWorkIn | firstStageReady;
wire firstPipelineResultReady = firstPipelineWorkIn & firstStageReady;
wire secondPipelineWorkIn = stateInb[31];
wire secondPipelineResultReady = secondPipelineWorkIn & (stateInb[7:0] == 64);
wire secondPipelineReady = (~secondPipelineWorkIn | secondPipelineResultReady);
wire midstateStageReady = (stateIn[7:0] == 64);
always@(posedge clk) begin
if(doWork) begin
//set new data
workBuffer <= in;
//set new job
currentJob <= job;
//reset nonce
//concatenation of input bytes in header
newNonce <= {in[76],in[77],in[78],in[79]};
//TODO reset queue... seems like it is not needed - jobstate guarantees drops (must test)
midstateReady <= 0;
scheduleTask <= 1;
end
if(firstPipelineReady) begin
if(scheduleTask) begin
//now we can schedule task, there is something to do! :) as always in life!
if(~midstateReady) begin
//begining of new work - there is no midstate known
//midstate is the same result of first 64 bytes part sha transform (because of nonce, which changes, lies at bytes 76-79 [zero index])
//--> concatenation
for(int i =0; i<16; i++) begin
wordsOut[i] <= (workBuffer[4*i] <<< 24) | (workBuffer[4*i + 1] <<< 16) | (workBuffer[4*i + 2] <<< 8) | (workBuffer[4*i + 3]);
end
//set state variables
stateOut[31] <= 1;
stateOut[7:0] <= 0;
//set up other job infos
jobOut <= currentJob;
nonceOut <= newNonce;
//increment nonce
newNonce <= newNonce + 1;
//we hit end of nonce interval - stop scheduling
if(newNonce == (32'hffffffff)) begin
scheduleTask <= 0;
end
//set initial digest
digestOut <= H;
digestOutOriginal <= H;
end else begin
//new work scheduling is in stage, where midstate is known (first sha done)
stateOut[31] <= 1;
//set digest from midstate
digestOut <= midstate;
digestOutOriginal <= midstate;
//set job info
jobOut <= currentJob;
nonceOut <= newNonce;
//use data out assembly, that generates new second part of first sha (few bytes from header with changing nonce + padding)
//this is in fact some kind of concatenation
for(int i =0; i<16; i++) begin
wordsOut[i] <= (firstStageSecondPart[4*i] <<< 24) | (firstStageSecondPart[4*i + 1] <<< 16) | (firstStageSecondPart[4*i + 2] <<< 8) | (firstStageSecondPart[4*i + 3]);
end
//increment nonce
newNonce <= newNonce + 1;
//if we hit end of nonce interval - stop scheduling
if(newNonce == (32'hffffffff)) begin
scheduleTask <= 0;
end
//we continue from state 64 (midstate known)
stateOut[7:0] <= 64;
end
end else begin
//otherwise fill pipeline with zeros
stateOut <= 0;
jobOut <= 0;
nonceOut <= 0;
for(int i = 0; i < 16; i++) begin
wordsOut[i] <= 0;
end
for(int i = 0; i < 8; i++) begin
digestOut[i] <= 0;
digestOutOriginal[i] <= 0;
end
end
end
if(firstPipelineWorkIn) begin
//this state is possible only at the beginning, when there is no midstate...
if(midstateStageReady) begin
//second part of data mix stored in queue
//concatenate/assemble words variable
for(int i =0; i<16; i++) begin
wordsOut[i] <= (dataIn[4*i] <<< 24) | (dataIn[4*i + 1] <<< 16) | (dataIn[4*i + 2] <<< 8) | (dataIn[4*i + 3]);
end
//complete digest - add original state/digest (H) to new one and set midstate.
digestOut <= newDigest;
midstate <= newDigest;
digestOutOriginal <= newDigest;
//continue with second part (from midstate), set job etc.
stateOut <= stateIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
//mark midstate ready for this job
midstateReady <= 1;
end else if(firstStageReady) begin
//first sha is complete, use its final digest and info as input for second sha pipeline
digestOutb <= H;
digestOutOriginalb <= H;
jobOutb <= jobIn;
nonceOutb <= nonceIn;
//set up initial words.
//concatenate some stages
for(int i =0; i < 8; i++) begin
wordsOutb[i] <= newDigest[i];
wordsOutb[8+i] <= (stageTwoPadding[4*i] <<< 24) | (stageTwoPadding[4*i + 1] <<< 16) | (stageTwoPadding[4*i + 2] <<< 8) | (stageTwoPadding[4*i + 3]);
end
//set state variables
stateOutb[7:0] <= 0;
stateOutb[31] <= 1;
end else begin
//some middle phase, continue mixing
wordsOut <= wordsIn;
digestOut <= digestIn;
digestOutOriginal <= digestInOriginal;
stateOut <= stateIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
end
end
//controls when to clean/discard data in second pipeline
//second pipe is ready and first one has nothing to schedule...
if(secondPipelineReady & ~firstPipelineResultReady) begin
stateOutb <= 0;
nonceOutb <= 0;
for(int i = 0; i < 16; i++) begin
wordsOutb[i] <= 0;
end
for(int i = 0; i < 8; i++) begin
digestOutb[i] <= 0;
digestOutOriginalb[i] <= 0;
end
jobOutb <= 0;
end
//if there is some result from second pipeline, process it
if(secondPipelineResultReady) begin
//end part of computation - we can signal completed work
//deconcatenate digest to bytes
for(int i =0; i < 8; i++) begin
resultOut[i*4 + 3] <= (digestInb[i] + digestInOriginalb[i]);
resultOut[i*4 + 2] <= (digestInb[i] + digestInOriginalb[i]) >>> 8;
resultOut[i*4 + 1] <= (digestInb[i] + digestInOriginalb[i]) >>> 16;
resultOut[i*4] <= (digestInb[i] + digestInOriginalb[i]) >>> 24;
end
resultJobOut <= jobInb;
resultNonceOut <= nonceInb;
resultAvailable <= 1;
end else if(secondPipelineWorkIn) begin
//otherwise continue in computation
wordsOutb <= wordsInb;
nonceOutb <= nonceInb;
jobOutb <= jobInb;
digestOutb <= digestInb;
digestOutOriginalb <= digestInOriginalb;
stateOutb <= stateInb;
resultAvailable <= 0;
end else begin
//realy, there is no result yet :)
resultAvailable <= 0;
end
end
endmodule |
module sha_pipeline(input clk, input [31:0] stateIn, input[31:0] digestIn[0:7], input[31:0] digestInOriginal[0:7], input [31:0] wordsIn[0:15], input [31:0] jobIn, input [31:0] nonceIn, output [31:0] digestOutNew[0:7], output [31:0] digestOutOriginal[0:7], output [31:0] wordsOut[0:15], output [31:0] stateOut, output [31:0] jobOut, output [31:0] nonceOut);
//valid values are 64,32,16,8,4,2,1
parameter N = 64;
//unroll assertion (taken from serial interface example)
generate
if(~(N==64 | N==32 | N==16 | N ==8 | N ==4 | N ==2 | N==1)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("SHA unroll parameter is not valid!");
endgenerate
//some interconnects
wire [31:0] stateMid;
wire [15:0] stateMidm;
//we need to shift some values in parallel with actual computation (usually needed in next steps)
parameterized_shift_packed #(.elementWidth(32), .depth(N)) db(clk, stateIn, stateMid);
parameterized_shift_packed #(.elementWidth(32), .depth(N)) db1(clk, jobIn, jobOut);
parameterized_shift_packed #(.elementWidth(32), .depth(N)) db2(clk, nonceIn, nonceOut);
parameterized_shift_unpacked #(.elementWidth(32), .elementCount(8),.depth(N)) db3(clk, digestInOriginal, digestOutOriginal);
//sha unrolled according to the N parameter
sha_mix #(N) mix(clk, stateIn[15:0], wordsIn, digestIn, digestOutNew, wordsOut, stateMidm);
//apply new index to state if needed (ie. there was valid task in pipeline)
assign stateOut = {stateMid[31:6], stateMid[31] ? stateMidm : 16'h0};
endmodule |
module sha_mix(input clk,input[15:0] indexIn, input [31:0] wordsIn[0:15], input [31:0] digestIn[0:7], output [31:0] digestOut[0:7],output [31:0] wordsOut[0:15], output[15:0] indexOut);
wire [31:0] K[0:63];
//unroll parameter
parameter N = 4;
//sha constant
assign K = '{
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
//generate block which governs how much sha mixer is unrolled
genvar i;
generate
if(N == 1) begin
//really small design, one passtrough core
sha_mix_part C(.clk(clk), .index(indexIn), .words(wordsIn), .digest(digestIn), .K(K[indexIn%64]), .wordsOut(wordsOut), .digestOut(digestOut), .indexOut(indexOut));
end else begin
for(i =0; i < N; i++) begin : cores
wire [31:0] local_words[0:15];
wire [31:0] local_digest[0:7];
wire [15:0] local_index;
//individual cores, cores[index] represents local wires generated for each core (in this case we connect everytime to previous one)
if(i == 0) begin
//first core connects mix input with actual one input and mix output with next core output
sha_mix_part core(.clk(clk), .index(indexIn), .words(wordsIn), .digest(digestIn), .K(K[indexIn%64]), .wordsOut(local_words), .digestOut(local_digest), .indexOut(local_index));
end else if(i < (N-1)) begin
//middle core(s) connect previous core output with actual one input and actual output with next core input
sha_mix_part core(.clk(clk), .index(cores[i-1].local_index), .words(cores[i-1].local_words), .digest(cores[i-1].local_digest), .K(K[cores[i-1].local_index%64]), .wordsOut(local_words), .digestOut(local_digest), .indexOut(local_index));
end else begin
//last core connects previous core output with actual one input and mix output with actual output
sha_mix_part core(clk, cores[i-1].local_index, cores[i-1].local_words, cores[i-1].local_digest, K[cores[i-1].local_index%64], wordsOut, digestOut, indexOut);
end
end
end
endgenerate
endmodule |
module sha_mix_part(input clk, input[15:0] index, input [31:0] words[0:15], input [31:0] digest[0:7], input [31:0] K, output reg[31:0] wordsOut[0:15], output reg[31:0] digestOut[0:7], output reg[15:0] indexOut);
//TODO resolve long combinational path for ch and newWork - too much chained adders
//digest/state computation for next round part
wire [31:0] s0;
wire [31:0] s00;
wire [31:0] s01;
wire [31:0] s02;
wire [31:0] s1;
wire [31:0] s10;
wire [31:0] s11;
wire [31:0] s12;
wire [31:0] maj;
wire [31:0] ch;
wire [31:0] t2;
wire [31:0] t1;
always @(*) begin
s00[31:30] = digest[0][1:0];
s00[29:0] = digest[0][31:2];
s01[31:19] = digest[0][12:0];
s01[18:0] = digest[0][31:13];
s02[31:10] = digest[0][21:0];
s02[9:0] = digest[0][31:22];
s10[31:26] = digest[4][5:0];
s10[25:0] = digest[4][31:6];
s11[31:21] = digest[4][10:0];
s11[20:0] = digest[4][31:11];
s12[31:7] = digest[4][24:0];
s12[6:0] = digest[4][31:25];
maj = (digest[0] & digest[1]) ^ (digest[0] & digest[2]) ^ (digest[1] & digest[2]);
ch = (digest[4] & digest[5]) ^ (~digest[4] & digest[6]);
s0 = s00 ^ s01 ^ s02;
s1 = s10 ^ s11 ^ s12;
t2 = s0+maj;
t1 = digest[7] + s1 + ch + K + words[0];
end
//shift digests (internal states)
always @(posedge clk) begin
digestOut[0] <= t1 + t2;
digestOut[1] <= digest[0];
digestOut[2] <= digest[1];
digestOut[3] <= digest[2];
digestOut[4] <= digest[3] + t1;
digestOut[5] <= digest[4];
digestOut[6] <= digest[5];
digestOut[7] <= digest[6];
end
//words computation for next round
wire [31:0] w00;
wire [31:0] w01;
wire [31:0] w02;
wire [31:0] w10;
wire [31:0] w11;
wire [31:0] w12;
wire [31:0] newWord;
always @(*) begin
w00[31:25] = words[1][6:0];
w00[24:0] = words[1][31:7];
w01[31:14] = words[1][17:0];
w01[13:0] = words[1][31:18];
w02 = words[1] >> 3;
w10[31:15] = words[14][16:0];
w10[14:0] = words[14][31:17];
w11[31:13] = words[14][18:0];
w11[12:0] = words[14][31:19];
w12 = words[14] >> 10;
newWord = words[0] + (w00^ w01^w02) + words[9] + (w10 ^ w11 ^ w12);
end
//words are shifted and last one is updated + index increment
always @(posedge clk) begin
wordsOut[15] <= newWord;
for(int i =0; i< 15; i++) begin
wordsOut[i] <= words[i+1];
end
//increment index
indexOut <= index +1'h1;
end
endmodule |
module shaqueue(clk, write, read, in, out, available, full);
parameter elementWidth = 8;
parameter elementCount = 128;
parameter depth = 256;
input clk;
input write;
input read;
input [(elementWidth-1):0] in[0:(elementCount-1)];
output [(elementWidth-1):0] out[0:(elementCount-1)];
output available;
output full;
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end endfunction
localparam addrWidth = log2(depth-1);
reg[(addrWidth-1):0] write_addr, read_addr;
reg[addrWidth:0] count;
ram #(.elementWidth(elementWidth), .elementCount(elementCount), .depth(depth)) ram(clk, in, write_addr, (read & available) ? (read_addr+1) : read_addr, write, out);
initial begin
read_addr = 0;
write_addr = 0;
count = 0;
end
//queue is full
assign full = (count == depth);
//some elements available
assign available = (count > 0);
always@(posedge clk) begin
//put, drop and available case
if(write & read & available) begin
write_addr <= write_addr + 1;
read_addr <= read_addr +1;
//write only case
end else if(write) begin
write_addr <= write_addr + 1;
//this causes rewrite of oldest value
if(~full) begin
count <= count +1;
end
//drop only case
end else if(read & available) begin
read_addr <= read_addr + 1;
count <= count - 1;
end
end
endmodule |
module crc_128_init (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk ,
input wire res_n ,
//----------------------------------
//----Input
//----------------------------------
input wire [127:0] inData ,
//----------------------------------
//----Output
//----------------------------------
output reg [31:0] crc
);
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if (!res_n) begin
crc <= 32'h0;
end
else begin
crc[31] <= inData[2]^inData[5]^inData[10]^inData[12]^inData[13]^inData[14]^inData[16]^inData[17]^inData[20]^inData[21]^inData[23]^inData[25]^inData[26]^inData[28]^inData[32]^inData[34]^inData[36]^inData[40]^inData[41]^inData[43]^inData[45]^inData[47]^inData[49]^inData[51]^inData[53]^inData[54]^inData[57]^inData[58]^inData[60]^inData[61]^inData[64]^inData[65]^inData[66]^inData[71]^inData[74]^inData[76]^inData[77]^inData[78]^inData[80]^inData[81]^inData[82]^inData[84]^inData[92]^inData[93]^inData[94]^inData[100]^inData[102]^inData[103]^inData[104]^inData[105]^inData[106]^inData[108]^inData[111]^inData[115]^inData[116]^inData[119]^inData[121]^inData[122]^inData[125]^inData[126];
crc[30] <= inData[3]^inData[6]^inData[11]^inData[13]^inData[14]^inData[15]^inData[17]^inData[18]^inData[21]^inData[22]^inData[24]^inData[26]^inData[27]^inData[29]^inData[33]^inData[35]^inData[37]^inData[41]^inData[42]^inData[44]^inData[46]^inData[48]^inData[50]^inData[52]^inData[54]^inData[55]^inData[58]^inData[59]^inData[61]^inData[62]^inData[65]^inData[66]^inData[67]^inData[72]^inData[75]^inData[77]^inData[78]^inData[79]^inData[81]^inData[82]^inData[83]^inData[85]^inData[93]^inData[94]^inData[95]^inData[101]^inData[103]^inData[104]^inData[105]^inData[106]^inData[107]^inData[109]^inData[112]^inData[116]^inData[117]^inData[120]^inData[122]^inData[123]^inData[126]^inData[127];
crc[29] <= inData[2]^inData[4]^inData[5]^inData[7]^inData[10]^inData[13]^inData[15]^inData[17]^inData[18]^inData[19]^inData[20]^inData[21]^inData[22]^inData[26]^inData[27]^inData[30]^inData[32]^inData[38]^inData[40]^inData[41]^inData[42]^inData[54]^inData[55]^inData[56]^inData[57]^inData[58]^inData[59]^inData[61]^inData[62]^inData[63]^inData[64]^inData[65]^inData[67]^inData[68]^inData[71]^inData[73]^inData[74]^inData[77]^inData[79]^inData[81]^inData[83]^inData[86]^inData[92]^inData[93]^inData[95]^inData[96]^inData[100]^inData[103]^inData[107]^inData[110]^inData[111]^inData[113]^inData[115]^inData[116]^inData[117]^inData[118]^inData[119]^inData[122]^inData[123]^inData[124]^inData[125]^inData[126]^inData[127];
crc[28] <= inData[0]^inData[2]^inData[3]^inData[6]^inData[8]^inData[10]^inData[11]^inData[12]^inData[13]^inData[17]^inData[18]^inData[19]^inData[22]^inData[25]^inData[26]^inData[27]^inData[31]^inData[32]^inData[33]^inData[34]^inData[36]^inData[39]^inData[40]^inData[42]^inData[45]^inData[47]^inData[49]^inData[51]^inData[53]^inData[54]^inData[55]^inData[56]^inData[59]^inData[61]^inData[62]^inData[63]^inData[68]^inData[69]^inData[71]^inData[72]^inData[75]^inData[76]^inData[77]^inData[81]^inData[87]^inData[92]^inData[96]^inData[97]^inData[100]^inData[101]^inData[102]^inData[103]^inData[105]^inData[106]^inData[112]^inData[114]^inData[115]^inData[117]^inData[118]^inData[120]^inData[121]^inData[122]^inData[123]^inData[124]^inData[127];
crc[27] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[4]^inData[5]^inData[7]^inData[9]^inData[10]^inData[11]^inData[16]^inData[17]^inData[18]^inData[19]^inData[21]^inData[25]^inData[27]^inData[33]^inData[35]^inData[36]^inData[37]^inData[45]^inData[46]^inData[47]^inData[48]^inData[49]^inData[50]^inData[51]^inData[52]^inData[53]^inData[55]^inData[56]^inData[58]^inData[61]^inData[62]^inData[63]^inData[65]^inData[66]^inData[69]^inData[70]^inData[71]^inData[72]^inData[73]^inData[74]^inData[80]^inData[81]^inData[84]^inData[88]^inData[92]^inData[94]^inData[97]^inData[98]^inData[100]^inData[101]^inData[105]^inData[107]^inData[108]^inData[111]^inData[113]^inData[118]^inData[123]^inData[124]^inData[126];
crc[26] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[4]^inData[5]^inData[6]^inData[8]^inData[10]^inData[11]^inData[12]^inData[17]^inData[18]^inData[19]^inData[20]^inData[22]^inData[26]^inData[28]^inData[34]^inData[36]^inData[37]^inData[38]^inData[46]^inData[47]^inData[48]^inData[49]^inData[50]^inData[51]^inData[52]^inData[53]^inData[54]^inData[56]^inData[57]^inData[59]^inData[62]^inData[63]^inData[64]^inData[66]^inData[67]^inData[70]^inData[71]^inData[72]^inData[73]^inData[74]^inData[75]^inData[81]^inData[82]^inData[85]^inData[89]^inData[93]^inData[95]^inData[98]^inData[99]^inData[101]^inData[102]^inData[106]^inData[108]^inData[109]^inData[112]^inData[114]^inData[119]^inData[124]^inData[125]^inData[127];
crc[25] <= inData[0]^inData[1]^inData[3]^inData[4]^inData[6]^inData[7]^inData[9]^inData[10]^inData[11]^inData[14]^inData[16]^inData[17]^inData[18]^inData[19]^inData[25]^inData[26]^inData[27]^inData[28]^inData[29]^inData[32]^inData[34]^inData[35]^inData[36]^inData[37]^inData[38]^inData[39]^inData[40]^inData[41]^inData[43]^inData[45]^inData[48]^inData[50]^inData[52]^inData[55]^inData[61]^inData[63]^inData[66]^inData[67]^inData[68]^inData[72]^inData[73]^inData[75]^inData[77]^inData[78]^inData[80]^inData[81]^inData[83]^inData[84]^inData[86]^inData[90]^inData[92]^inData[93]^inData[96]^inData[99]^inData[104]^inData[105]^inData[106]^inData[107]^inData[108]^inData[109]^inData[110]^inData[111]^inData[113]^inData[116]^inData[119]^inData[120]^inData[121]^inData[122];
crc[24] <= inData[1]^inData[2]^inData[4]^inData[5]^inData[7]^inData[8]^inData[10]^inData[11]^inData[12]^inData[15]^inData[17]^inData[18]^inData[19]^inData[20]^inData[26]^inData[27]^inData[28]^inData[29]^inData[30]^inData[33]^inData[35]^inData[36]^inData[37]^inData[38]^inData[39]^inData[40]^inData[41]^inData[42]^inData[44]^inData[46]^inData[49]^inData[51]^inData[53]^inData[56]^inData[62]^inData[64]^inData[67]^inData[68]^inData[69]^inData[73]^inData[74]^inData[76]^inData[78]^inData[79]^inData[81]^inData[82]^inData[84]^inData[85]^inData[87]^inData[91]^inData[93]^inData[94]^inData[97]^inData[100]^inData[105]^inData[106]^inData[107]^inData[108]^inData[109]^inData[110]^inData[111]^inData[112]^inData[114]^inData[117]^inData[120]^inData[121]^inData[122]^inData[123];
crc[23] <= inData[2]^inData[3]^inData[5]^inData[6]^inData[8]^inData[9]^inData[11]^inData[12]^inData[13]^inData[16]^inData[18]^inData[19]^inData[20]^inData[21]^inData[27]^inData[28]^inData[29]^inData[30]^inData[31]^inData[34]^inData[36]^inData[37]^inData[38]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[45]^inData[47]^inData[50]^inData[52]^inData[54]^inData[57]^inData[63]^inData[65]^inData[68]^inData[69]^inData[70]^inData[74]^inData[75]^inData[77]^inData[79]^inData[80]^inData[82]^inData[83]^inData[85]^inData[86]^inData[88]^inData[92]^inData[94]^inData[95]^inData[98]^inData[101]^inData[106]^inData[107]^inData[108]^inData[109]^inData[110]^inData[111]^inData[112]^inData[113]^inData[115]^inData[118]^inData[121]^inData[122]^inData[123]^inData[124];
crc[22] <= inData[3]^inData[4]^inData[6]^inData[7]^inData[9]^inData[10]^inData[12]^inData[13]^inData[14]^inData[17]^inData[19]^inData[20]^inData[21]^inData[22]^inData[28]^inData[29]^inData[30]^inData[31]^inData[32]^inData[35]^inData[37]^inData[38]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[46]^inData[48]^inData[51]^inData[53]^inData[55]^inData[58]^inData[64]^inData[66]^inData[69]^inData[70]^inData[71]^inData[75]^inData[76]^inData[78]^inData[80]^inData[81]^inData[83]^inData[84]^inData[86]^inData[87]^inData[89]^inData[93]^inData[95]^inData[96]^inData[99]^inData[102]^inData[107]^inData[108]^inData[109]^inData[110]^inData[111]^inData[112]^inData[113]^inData[114]^inData[116]^inData[119]^inData[122]^inData[123]^inData[124]^inData[125];
crc[21] <= inData[4]^inData[5]^inData[7]^inData[8]^inData[10]^inData[11]^inData[13]^inData[14]^inData[15]^inData[18]^inData[20]^inData[21]^inData[22]^inData[23]^inData[29]^inData[30]^inData[31]^inData[32]^inData[33]^inData[36]^inData[38]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[47]^inData[49]^inData[52]^inData[54]^inData[56]^inData[59]^inData[65]^inData[67]^inData[70]^inData[71]^inData[72]^inData[76]^inData[77]^inData[79]^inData[81]^inData[82]^inData[84]^inData[85]^inData[87]^inData[88]^inData[90]^inData[94]^inData[96]^inData[97]^inData[100]^inData[103]^inData[108]^inData[109]^inData[110]^inData[111]^inData[112]^inData[113]^inData[114]^inData[115]^inData[117]^inData[120]^inData[123]^inData[124]^inData[125]^inData[126];
crc[20] <= inData[0]^inData[5]^inData[6]^inData[8]^inData[9]^inData[11]^inData[12]^inData[14]^inData[15]^inData[16]^inData[19]^inData[21]^inData[22]^inData[23]^inData[24]^inData[30]^inData[31]^inData[32]^inData[33]^inData[34]^inData[37]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[46]^inData[48]^inData[50]^inData[53]^inData[55]^inData[57]^inData[60]^inData[66]^inData[68]^inData[71]^inData[72]^inData[73]^inData[77]^inData[78]^inData[80]^inData[82]^inData[83]^inData[85]^inData[86]^inData[88]^inData[89]^inData[91]^inData[95]^inData[97]^inData[98]^inData[101]^inData[104]^inData[109]^inData[110]^inData[111]^inData[112]^inData[113]^inData[114]^inData[115]^inData[116]^inData[118]^inData[121]^inData[124]^inData[125]^inData[126]^inData[127];
crc[19] <= inData[1]^inData[2]^inData[5]^inData[6]^inData[7]^inData[9]^inData[14]^inData[15]^inData[21]^inData[22]^inData[24]^inData[26]^inData[28]^inData[31]^inData[33]^inData[35]^inData[36]^inData[38]^inData[42]^inData[44]^inData[46]^inData[53]^inData[56]^inData[57]^inData[60]^inData[64]^inData[65]^inData[66]^inData[67]^inData[69]^inData[71]^inData[72]^inData[73]^inData[76]^inData[77]^inData[79]^inData[80]^inData[82]^inData[83]^inData[86]^inData[87]^inData[89]^inData[90]^inData[93]^inData[94]^inData[96]^inData[98]^inData[99]^inData[100]^inData[103]^inData[104]^inData[106]^inData[108]^inData[110]^inData[112]^inData[113]^inData[114]^inData[117]^inData[121]^inData[127];
crc[18] <= inData[3]^inData[5]^inData[6]^inData[7]^inData[8]^inData[12]^inData[13]^inData[14]^inData[15]^inData[17]^inData[20]^inData[21]^inData[22]^inData[26]^inData[27]^inData[28]^inData[29]^inData[37]^inData[39]^inData[40]^inData[41]^inData[49]^inData[51]^inData[53]^inData[60]^inData[64]^inData[67]^inData[68]^inData[70]^inData[71]^inData[72]^inData[73]^inData[76]^inData[82]^inData[83]^inData[87]^inData[88]^inData[90]^inData[91]^inData[92]^inData[93]^inData[95]^inData[97]^inData[99]^inData[101]^inData[102]^inData[103]^inData[106]^inData[107]^inData[108]^inData[109]^inData[113]^inData[114]^inData[116]^inData[118]^inData[119]^inData[121]^inData[125]^inData[126];
crc[17] <= inData[0]^inData[4]^inData[6]^inData[7]^inData[8]^inData[9]^inData[13]^inData[14]^inData[15]^inData[16]^inData[18]^inData[21]^inData[22]^inData[23]^inData[27]^inData[28]^inData[29]^inData[30]^inData[38]^inData[40]^inData[41]^inData[42]^inData[50]^inData[52]^inData[54]^inData[61]^inData[65]^inData[68]^inData[69]^inData[71]^inData[72]^inData[73]^inData[74]^inData[77]^inData[83]^inData[84]^inData[88]^inData[89]^inData[91]^inData[92]^inData[93]^inData[94]^inData[96]^inData[98]^inData[100]^inData[102]^inData[103]^inData[104]^inData[107]^inData[108]^inData[109]^inData[110]^inData[114]^inData[115]^inData[117]^inData[119]^inData[120]^inData[122]^inData[126]^inData[127];
crc[16] <= inData[0]^inData[1]^inData[2]^inData[7]^inData[8]^inData[9]^inData[12]^inData[13]^inData[15]^inData[19]^inData[20]^inData[21]^inData[22]^inData[24]^inData[25]^inData[26]^inData[29]^inData[30]^inData[31]^inData[32]^inData[34]^inData[36]^inData[39]^inData[40]^inData[42]^inData[45]^inData[47]^inData[49]^inData[54]^inData[55]^inData[57]^inData[58]^inData[60]^inData[61]^inData[62]^inData[64]^inData[65]^inData[69]^inData[70]^inData[71]^inData[72]^inData[73]^inData[75]^inData[76]^inData[77]^inData[80]^inData[81]^inData[82]^inData[85]^inData[89]^inData[90]^inData[95]^inData[97]^inData[99]^inData[100]^inData[101]^inData[102]^inData[106]^inData[109]^inData[110]^inData[118]^inData[119]^inData[120]^inData[122]^inData[123]^inData[125]^inData[126]^inData[127];
crc[15] <= inData[0]^inData[1]^inData[3]^inData[5]^inData[8]^inData[9]^inData[12]^inData[17]^inData[22]^inData[27]^inData[28]^inData[30]^inData[31]^inData[33]^inData[34]^inData[35]^inData[36]^inData[37]^inData[45]^inData[46]^inData[47]^inData[48]^inData[49]^inData[50]^inData[51]^inData[53]^inData[54]^inData[55]^inData[56]^inData[57]^inData[59]^inData[60]^inData[62]^inData[63]^inData[64]^inData[70]^inData[72]^inData[73]^inData[80]^inData[83]^inData[84]^inData[86]^inData[90]^inData[91]^inData[92]^inData[93]^inData[94]^inData[96]^inData[98]^inData[101]^inData[104]^inData[105]^inData[106]^inData[107]^inData[108]^inData[110]^inData[115]^inData[116]^inData[120]^inData[122]^inData[123]^inData[124]^inData[125]^inData[127];
crc[14] <= inData[0]^inData[1]^inData[4]^inData[5]^inData[6]^inData[9]^inData[12]^inData[14]^inData[16]^inData[17]^inData[18]^inData[20]^inData[21]^inData[25]^inData[26]^inData[29]^inData[31]^inData[35]^inData[37]^inData[38]^inData[40]^inData[41]^inData[43]^inData[45]^inData[46]^inData[48]^inData[50]^inData[52]^inData[53]^inData[55]^inData[56]^inData[63]^inData[66]^inData[73]^inData[76]^inData[77]^inData[78]^inData[80]^inData[82]^inData[85]^inData[87]^inData[91]^inData[95]^inData[97]^inData[99]^inData[100]^inData[103]^inData[104]^inData[107]^inData[109]^inData[115]^inData[117]^inData[119]^inData[122]^inData[123]^inData[124];
crc[13] <= inData[1]^inData[2]^inData[5]^inData[6]^inData[7]^inData[10]^inData[13]^inData[15]^inData[17]^inData[18]^inData[19]^inData[21]^inData[22]^inData[26]^inData[27]^inData[30]^inData[32]^inData[36]^inData[38]^inData[39]^inData[41]^inData[42]^inData[44]^inData[46]^inData[47]^inData[49]^inData[51]^inData[53]^inData[54]^inData[56]^inData[57]^inData[64]^inData[67]^inData[74]^inData[77]^inData[78]^inData[79]^inData[81]^inData[83]^inData[86]^inData[88]^inData[92]^inData[96]^inData[98]^inData[100]^inData[101]^inData[104]^inData[105]^inData[108]^inData[110]^inData[116]^inData[118]^inData[120]^inData[123]^inData[124]^inData[125];
crc[12] <= inData[0]^inData[2]^inData[3]^inData[6]^inData[7]^inData[8]^inData[11]^inData[14]^inData[16]^inData[18]^inData[19]^inData[20]^inData[22]^inData[23]^inData[27]^inData[28]^inData[31]^inData[33]^inData[37]^inData[39]^inData[40]^inData[42]^inData[43]^inData[45]^inData[47]^inData[48]^inData[50]^inData[52]^inData[54]^inData[55]^inData[57]^inData[58]^inData[65]^inData[68]^inData[75]^inData[78]^inData[79]^inData[80]^inData[82]^inData[84]^inData[87]^inData[89]^inData[93]^inData[97]^inData[99]^inData[101]^inData[102]^inData[105]^inData[106]^inData[109]^inData[111]^inData[117]^inData[119]^inData[121]^inData[124]^inData[125]^inData[126];
crc[11] <= inData[1]^inData[3]^inData[4]^inData[7]^inData[8]^inData[9]^inData[12]^inData[15]^inData[17]^inData[19]^inData[20]^inData[21]^inData[23]^inData[24]^inData[28]^inData[29]^inData[32]^inData[34]^inData[38]^inData[40]^inData[41]^inData[43]^inData[44]^inData[46]^inData[48]^inData[49]^inData[51]^inData[53]^inData[55]^inData[56]^inData[58]^inData[59]^inData[66]^inData[69]^inData[76]^inData[79]^inData[80]^inData[81]^inData[83]^inData[85]^inData[88]^inData[90]^inData[94]^inData[98]^inData[100]^inData[102]^inData[103]^inData[106]^inData[107]^inData[110]^inData[112]^inData[118]^inData[120]^inData[122]^inData[125]^inData[126]^inData[127];
crc[10] <= inData[4]^inData[8]^inData[9]^inData[12]^inData[14]^inData[17]^inData[18]^inData[22]^inData[23]^inData[24]^inData[26]^inData[28]^inData[29]^inData[30]^inData[32]^inData[33]^inData[34]^inData[35]^inData[36]^inData[39]^inData[40]^inData[42]^inData[43]^inData[44]^inData[50]^inData[51]^inData[52]^inData[53]^inData[56]^inData[58]^inData[59]^inData[61]^inData[64]^inData[65]^inData[66]^inData[67]^inData[70]^inData[71]^inData[74]^inData[76]^inData[78]^inData[86]^inData[89]^inData[91]^inData[92]^inData[93]^inData[94]^inData[95]^inData[99]^inData[100]^inData[101]^inData[102]^inData[105]^inData[106]^inData[107]^inData[113]^inData[115]^inData[116]^inData[122]^inData[123]^inData[125]^inData[127];
crc[ 9] <= inData[0]^inData[2]^inData[9]^inData[12]^inData[14]^inData[15]^inData[16]^inData[17]^inData[18]^inData[19]^inData[20]^inData[21]^inData[24]^inData[26]^inData[27]^inData[28]^inData[29]^inData[30]^inData[31]^inData[32]^inData[33]^inData[35]^inData[37]^inData[44]^inData[47]^inData[49]^inData[52]^inData[58]^inData[59]^inData[61]^inData[62]^inData[64]^inData[67]^inData[68]^inData[72]^inData[74]^inData[75]^inData[76]^inData[78]^inData[79]^inData[80]^inData[81]^inData[82]^inData[84]^inData[87]^inData[90]^inData[95]^inData[96]^inData[101]^inData[104]^inData[105]^inData[107]^inData[111]^inData[114]^inData[115]^inData[117]^inData[119]^inData[121]^inData[122]^inData[123]^inData[124]^inData[125];
crc[ 8] <= inData[1]^inData[3]^inData[10]^inData[13]^inData[15]^inData[16]^inData[17]^inData[18]^inData[19]^inData[20]^inData[21]^inData[22]^inData[25]^inData[27]^inData[28]^inData[29]^inData[30]^inData[31]^inData[32]^inData[33]^inData[34]^inData[36]^inData[38]^inData[45]^inData[48]^inData[50]^inData[53]^inData[59]^inData[60]^inData[62]^inData[63]^inData[65]^inData[68]^inData[69]^inData[73]^inData[75]^inData[76]^inData[77]^inData[79]^inData[80]^inData[81]^inData[82]^inData[83]^inData[85]^inData[88]^inData[91]^inData[96]^inData[97]^inData[102]^inData[105]^inData[106]^inData[108]^inData[112]^inData[115]^inData[116]^inData[118]^inData[120]^inData[122]^inData[123]^inData[124]^inData[125]^inData[126];
crc[ 7] <= inData[0]^inData[2]^inData[4]^inData[11]^inData[14]^inData[16]^inData[17]^inData[18]^inData[19]^inData[20]^inData[21]^inData[22]^inData[23]^inData[26]^inData[28]^inData[29]^inData[30]^inData[31]^inData[32]^inData[33]^inData[34]^inData[35]^inData[37]^inData[39]^inData[46]^inData[49]^inData[51]^inData[54]^inData[60]^inData[61]^inData[63]^inData[64]^inData[66]^inData[69]^inData[70]^inData[74]^inData[76]^inData[77]^inData[78]^inData[80]^inData[81]^inData[82]^inData[83]^inData[84]^inData[86]^inData[89]^inData[92]^inData[97]^inData[98]^inData[103]^inData[106]^inData[107]^inData[109]^inData[113]^inData[116]^inData[117]^inData[119]^inData[121]^inData[123]^inData[124]^inData[125]^inData[126]^inData[127];
crc[ 6] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[10]^inData[13]^inData[14]^inData[15]^inData[16]^inData[18]^inData[19]^inData[22]^inData[24]^inData[25]^inData[26]^inData[27]^inData[28]^inData[29]^inData[30]^inData[31]^inData[33]^inData[35]^inData[38]^inData[41]^inData[43]^inData[45]^inData[49]^inData[50]^inData[51]^inData[52]^inData[53]^inData[54]^inData[55]^inData[57]^inData[58]^inData[60]^inData[62]^inData[66]^inData[67]^inData[70]^inData[74]^inData[75]^inData[76]^inData[79]^inData[80]^inData[83]^inData[85]^inData[87]^inData[90]^inData[92]^inData[94]^inData[98]^inData[99]^inData[100]^inData[102]^inData[103]^inData[105]^inData[106]^inData[107]^inData[110]^inData[111]^inData[114]^inData[115]^inData[116]^inData[117]^inData[118]^inData[119]^inData[120]^inData[121]^inData[124]^inData[127];
crc[ 5] <= inData[1]^inData[3]^inData[4]^inData[5]^inData[10]^inData[11]^inData[12]^inData[13]^inData[15]^inData[19]^inData[21]^inData[27]^inData[29]^inData[30]^inData[31]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[46]^inData[47]^inData[49]^inData[50]^inData[52]^inData[55]^inData[56]^inData[57]^inData[59]^inData[60]^inData[63]^inData[64]^inData[65]^inData[66]^inData[67]^inData[68]^inData[74]^inData[75]^inData[78]^inData[82]^inData[86]^inData[88]^inData[91]^inData[92]^inData[94]^inData[95]^inData[99]^inData[101]^inData[102]^inData[105]^inData[107]^inData[112]^inData[117]^inData[118]^inData[120]^inData[126];
crc[ 4] <= inData[0]^inData[2]^inData[4]^inData[5]^inData[6]^inData[11]^inData[12]^inData[13]^inData[14]^inData[16]^inData[20]^inData[22]^inData[28]^inData[30]^inData[31]^inData[32]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[46]^inData[47]^inData[48]^inData[50]^inData[51]^inData[53]^inData[56]^inData[57]^inData[58]^inData[60]^inData[61]^inData[64]^inData[65]^inData[66]^inData[67]^inData[68]^inData[69]^inData[75]^inData[76]^inData[79]^inData[83]^inData[87]^inData[89]^inData[92]^inData[93]^inData[95]^inData[96]^inData[100]^inData[102]^inData[103]^inData[106]^inData[108]^inData[113]^inData[118]^inData[119]^inData[121]^inData[127];
crc[ 3] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[6]^inData[7]^inData[10]^inData[15]^inData[16]^inData[20]^inData[25]^inData[26]^inData[28]^inData[29]^inData[31]^inData[33]^inData[34]^inData[36]^inData[40]^inData[42]^inData[44]^inData[46]^inData[48]^inData[52]^inData[53]^inData[59]^inData[60]^inData[62]^inData[64]^inData[67]^inData[68]^inData[69]^inData[70]^inData[71]^inData[74]^inData[78]^inData[81]^inData[82]^inData[88]^inData[90]^inData[92]^inData[96]^inData[97]^inData[100]^inData[101]^inData[102]^inData[105]^inData[106]^inData[107]^inData[108]^inData[109]^inData[111]^inData[114]^inData[115]^inData[116]^inData[120]^inData[121]^inData[125]^inData[126];
crc[ 2] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[4]^inData[7]^inData[8]^inData[11]^inData[16]^inData[17]^inData[21]^inData[26]^inData[27]^inData[29]^inData[30]^inData[32]^inData[34]^inData[35]^inData[37]^inData[41]^inData[43]^inData[45]^inData[47]^inData[49]^inData[53]^inData[54]^inData[60]^inData[61]^inData[63]^inData[65]^inData[68]^inData[69]^inData[70]^inData[71]^inData[72]^inData[75]^inData[79]^inData[82]^inData[83]^inData[89]^inData[91]^inData[93]^inData[97]^inData[98]^inData[101]^inData[102]^inData[103]^inData[106]^inData[107]^inData[108]^inData[109]^inData[110]^inData[112]^inData[115]^inData[116]^inData[117]^inData[121]^inData[122]^inData[126]^inData[127];
crc[ 1] <= inData[0]^inData[1]^inData[3]^inData[4]^inData[8]^inData[9]^inData[10]^inData[13]^inData[14]^inData[16]^inData[18]^inData[20]^inData[21]^inData[22]^inData[23]^inData[25]^inData[26]^inData[27]^inData[30]^inData[31]^inData[32]^inData[33]^inData[34]^inData[35]^inData[38]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[46]^inData[47]^inData[48]^inData[49]^inData[50]^inData[51]^inData[53]^inData[55]^inData[57]^inData[58]^inData[60]^inData[62]^inData[65]^inData[69]^inData[70]^inData[72]^inData[73]^inData[74]^inData[77]^inData[78]^inData[81]^inData[82]^inData[83]^inData[90]^inData[93]^inData[98]^inData[99]^inData[100]^inData[105]^inData[106]^inData[107]^inData[109]^inData[110]^inData[113]^inData[115]^inData[117]^inData[118]^inData[119]^inData[121]^inData[123]^inData[125]^inData[126]^inData[127];
crc[ 0] <= inData[1]^inData[4]^inData[9]^inData[11]^inData[12]^inData[13]^inData[15]^inData[16]^inData[19]^inData[20]^inData[22]^inData[24]^inData[25]^inData[27]^inData[31]^inData[33]^inData[35]^inData[39]^inData[40]^inData[42]^inData[44]^inData[46]^inData[48]^inData[50]^inData[52]^inData[53]^inData[56]^inData[57]^inData[59]^inData[60]^inData[63]^inData[64]^inData[65]^inData[70]^inData[73]^inData[75]^inData[76]^inData[77]^inData[79]^inData[80]^inData[81]^inData[83]^inData[91]^inData[92]^inData[93]^inData[99]^inData[101]^inData[102]^inData[103]^inData[104]^inData[105]^inData[107]^inData[110]^inData[114]^inData[115]^inData[118]^inData[120]^inData[121]^inData[124]^inData[125]^inData[127];
end
end
endmodule |
module c2i_buf (/*AUTOARG*/
// Outputs
ucb_buf_acpt, iob_ucb_vld, iob_ucb_data,
// Inputs
rst_l, clk, c2i_packet_vld, ucb_sel, c2i_packet, ucb_iob_stall
);
// synopsys template
parameter REG_WIDTH = 64;
parameter IOB_UCB_WIDTH = 32;
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input rst_l;
input clk;
// slow control interface
input c2i_packet_vld;
input ucb_sel;
output ucb_buf_acpt;
// slow datapath interface
input [REG_WIDTH+63:0] c2i_packet;
// UCB interface
output iob_ucb_vld;
output [IOB_UCB_WIDTH-1:0] iob_ucb_data;
input ucb_iob_stall;
// Internal signals
wire dbl_buf_wr;
wire dbl_buf_rd;
wire dbl_buf_vld;
wire dbl_buf_full;
wire outdata_buf_wr;
wire [REG_WIDTH+63:0] outdata_buf_in;
wire [(REG_WIDTH+64)/IOB_UCB_WIDTH-1:0] outdata_vec_in;
wire outdata_buf_busy;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
assign dbl_buf_wr = c2i_packet_vld & ucb_sel & ~dbl_buf_full;
assign ucb_buf_acpt = dbl_buf_wr;
assign dbl_buf_rd = dbl_buf_vld & ~outdata_buf_busy;
assign outdata_buf_wr = dbl_buf_rd;
assign outdata_vec_in = {(REG_WIDTH+64)/IOB_UCB_WIDTH{1'b1}};
dbl_buf #(REG_WIDTH+64) dbl_buf (.rst_l(rst_l),
.clk(clk),
.wr(dbl_buf_wr),
.din(c2i_packet),
.rd(dbl_buf_rd),
.dout(outdata_buf_in),
.vld(dbl_buf_vld),
.full(dbl_buf_full));
ucb_bus_out #(IOB_UCB_WIDTH,REG_WIDTH) ucb_bus_out (.rst_l(rst_l),
.clk(clk),
.outdata_buf_wr(outdata_buf_wr),
.outdata_buf_in(outdata_buf_in),
.outdata_vec_in(outdata_vec_in),
.outdata_buf_busy(outdata_buf_busy),
.vld(iob_ucb_vld),
.data(iob_ucb_data),
.stall(ucb_iob_stall));
endmodule |
module dac (DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg DACout; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk)
begin
if(Reset)
begin
SigmaLatch <= #1 1'b1 << (`MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <= #1 SigmaAdder;
DACout <= #1 SigmaLatch[`MSBI+2];
end
end
endmodule |
module mixer (
input wire clkdac,
input wire reset,
input wire ear,
input wire mic,
input wire spk,
input wire [7:0] ay1,
input wire [7:0] ay2,
output wire audio
);
parameter
SRC_BEEPER = 2'd0,
SRC_AY1 = 2'd1,
SRC_AY2 = 2'd2;
wire [7:0] beeper = ({ear,spk,mic}==3'b000)? 8'd17 :
({ear,spk,mic}==3'b001)? 8'd36 :
({ear,spk,mic}==3'b010)? 8'd184 :
({ear,spk,mic}==3'b011)? 8'd192 :
({ear,spk,mic}==3'b100)? 8'd22 :
({ear,spk,mic}==3'b101)? 8'd48 :
({ear,spk,mic}==3'b110)? 8'd244 : 8'd255;
reg [7:0] mezcla;
reg [1:0] sndsource = 2'd0;
always @(posedge clkdac) begin
case (sndsource)
SRC_BEEPER: mezcla <= beeper;
SRC_AY1 : mezcla <= ay1;
SRC_AY2 : mezcla <= ay2;
endcase
sndsource <= (sndsource == 2'd2)? 2'd0 : sndsource + 2'd1; // en lugar de sumar, multiplexamos en el tiempo las fuentes de sonido
end
dac audio_dac (
.DACout(audio),
.DACin(mezcla),
.Clk(clkdac),
.Reset(reset)
);
endmodule |
module tb_m_rep_upload();
//input
reg clk;
reg rst;
reg [175:0] m_flits_rep;
reg v_m_flits_rep;
reg [3:0] flits_max;
reg en_flits_max;
reg rep_fifo_rdy;
//output
wire [15:0] m_flit_out;
wire v_m_flit_out;
wire [1:0] m_ctrl_out;
wire m_rep_upload_state;
m_rep_upload uut(//input
.clk(clk),
.rst(rst),
.m_flits_rep(m_flits_rep),
.v_m_flits_rep(v_m_flits_rep),
.flits_max(flits_max),
.en_flits_max(en_flits_max),
.rep_fifo_rdy(rep_fifo_rdy),
//output
.m_flit_out(m_flit_out),
.v_m_flit_out(v_m_flit_out),
.m_ctrl_out(m_ctrl_out),
.m_rep_upload_state(m_rep_upload_state)
);
//initial inputs
initial begin
clk=1'b0;
rst=1'b1;
m_flits_rep=144'h0000_0000_0000_0000_0000_0000_0000_0000_0000;
v_m_flits_rep=1'b0;
en_flits_max=1'b0;
flits_max=1'b1;
rep_fifo_rdy=1'b0;
end
`define clk_step # 14;
always #7 clk=~clk;
/////////////////////////////////////////////////////////////
////////////////////////////BEGIN TEST!//////////////////////
initial begin
`clk_step
rst=1'b0;
`clk_step
/////////////////////////////////////////////////////////////
//////////1st case: a msg which is only one flit long////////
en_flits_max=1'b1;
flits_max=4'b0000;
rep_fifo_rdy=1'b1;
`clk_step
en_flits_max=1'b0;
m_flits_rep=144'hc0de_c1de_c2de_c3de_c4de_c5de_c6de_c7de_c8de;
v_m_flits_rep=1'b1;
`clk_step
//since rey fifo is ready to receive flit ,so the only flit is poped to rep fifo
v_m_flits_rep=1'b0;
`clk_step
//this cycle m_rep_upload is idle
//in the meantime, preparing for next msg
en_flits_max=1'b1;
flits_max=4'b0010;
/////////////////////////////////////////////////////////////
/////////////2nd case: a msg with 3 flits is coming!/////////
`clk_step
v_m_flits_rep=1'b1;
m_flits_rep=144'habc1_abc2_abc3_abc4_abc5_abc6_abc7_abc8_abc9;
`clk_step
///the 1st flit is transfered to rep fifo
`clk_step
///this cycle rep fifo become full ,so 2nd flit still sit in the regs of m_upload
rep_fifo_rdy=1'b0;
`clk_step
//still full
`clk_step
//still full
`clk_step
//rep fifo become not full! And 2nd flit can be transfered to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
///3rd flit also last flit to rep fifo
`clk_step
/// m_rep_upload become idle
//////////////////////////////////////////////////////////////////
//////////// 3rd case: a msg with 9 flits is coming!//////////////
`clk_step
en_flits_max=1'b1;
flits_max=4'b1000;
`clk_step
m_flits_rep=144'h0123_1234_2345_3456_4567_5678_6789_7890_8901;
v_m_flits_rep=1'b1;
`clk_step
//since rep fifo is ready to receive flit, first flit will get out of m_rep_upload!
`clk_step
//2nd flit get out
`clk_step
//3rd flit get out
`clk_step
////rep fifo become full
rep_fifo_rdy=1'b0;
`clk_step
//still full
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
//rep fifo has empty slots now! And 4th flit get to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
//5th flit get out
`clk_step
//full again!
rep_fifo_rdy=1'b0;
`clk_step
//rep fifo has empty slots now! And 6th flit get to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
//7th get out
`clk_step
//8th get out
`clk_step
//9th get out
`clk_step
//////m_rep_upload become idle now !
`clk_step
$stop;
end
endmodule |
module testbench ();
// clock
logic clk;
bsg_nonsynth_clock_gen
#(.cycle_time_p(`dram_pkg::tck_ps))
clkgen
(.o(clk));
// reset
logic reset;
bsg_nonsynth_reset_gen
#(.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(20))
resetgen
(.clk_i(clk)
,.async_reset_o(reset));
// dramsim3
import `dram_pkg::*;
parameter int num_dramsim3_p = 2;
logic [num_channels_p-1:0] dramsim3_v_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_write_not_read_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] [channel_addr_width_p-1:0] dramsim3_ch_addr_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_yumi_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_data_v_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] [data_width_p-1:0] dramsim3_data_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_data_yumi_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_data_v_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] [data_width_p-1:0] dramsim3_data_lo [num_dramsim3_p-1:0];
`dram_pkg::dram_ch_addr_s dramsim3_ch_addr_li_cast [num_dramsim3_p-1:0];
for (genvar dramsim_i = 0; dramsim_i < num_dramsim3_p; dramsim_i++) begin
assign dramsim3_ch_addr_li_cast[dramsim_i] = dramsim3_ch_addr_li[dramsim_i][0];
bsg_nonsynth_dramsim3
#(.channel_addr_width_p(`dram_pkg::channel_addr_width_p)
,.data_width_p(`dram_pkg::data_width_p)
,.num_channels_p(`dram_pkg::num_channels_p)
,.num_columns_p(`dram_pkg::num_columns_p)
,.num_rows_p(`dram_pkg::num_rows_p)
,.num_ba_p(`dram_pkg::num_ba_p)
,.num_bg_p(`dram_pkg::num_bg_p)
,.num_ranks_p(`dram_pkg::num_ranks_p)
,.size_in_bits_p(`dram_pkg::size_in_bits_p)
,.address_mapping_p(`dram_pkg::address_mapping_p)
,.config_p(`dram_pkg::config_p)
,.masked_p(0)
,.trace_file_p(`BSG_STRINGIFY(`trace_file))
,.debug_p(1))
mem
(.clk_i(clk)
,.reset_i(reset)
,.v_i(dramsim3_v_li[dramsim_i])
,.write_not_read_i(dramsim3_write_not_read_li[dramsim_i])
,.ch_addr_i(dramsim3_ch_addr_li[dramsim_i])
,.yumi_o(dramsim3_yumi_lo[dramsim_i])
,.data_v_i(dramsim3_data_v_li[dramsim_i])
,.data_i(dramsim3_data_li[dramsim_i])
,.mask_i('0)
,.data_yumi_o(dramsim3_data_yumi_lo[dramsim_i])
,.data_v_o(dramsim3_data_v_lo[dramsim_i])
,.data_o(dramsim3_data_lo[dramsim_i])
,.read_done_ch_addr_o()
,.write_done_o()
,.write_done_ch_addr_o()
);
end
// trace replay
//
typedef struct packed {
logic write_not_read;
logic [channel_addr_width_p-1:0] ch_addr;
} dramsim3_trace_s;
localparam ring_width_p = $bits(dramsim3_trace_s);
localparam rom_addr_width_p=20;
dramsim3_trace_s [num_channels_p-1:0] tr_data_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] tr_v_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] tr_yumi_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0][4+ring_width_p-1:0] rom_data [num_dramsim3_p-1:0];
logic [num_channels_p-1:0][rom_addr_width_p-1:0] rom_addr [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] ch_done [num_dramsim3_p-1:0];
for (genvar dramsim_i = 0; dramsim_i < num_dramsim3_p; dramsim_i++) begin
for (genvar i = 0; i < num_channels_p; i++) begin
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
//,.en_i(i == '0)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo[dramsim_i][i])
,.data_o(tr_data_lo[dramsim_i][i])
,.yumi_i(tr_yumi_li[dramsim_i][i])
,.rom_addr_o(rom_addr[dramsim_i][i])
,.rom_data_i(rom_data[dramsim_i][i])
,.done_o(ch_done[dramsim_i][i])
,.error_o()
);
assign dramsim3_write_not_read_li[dramsim_i][i] = tr_data_lo[dramsim_i][i].write_not_read;
assign dramsim3_ch_addr_li[dramsim_i][i] = tr_data_lo[dramsim_i][i].ch_addr;
assign dramsim3_v_li[dramsim_i][i] = tr_v_lo[dramsim_i][i];
assign tr_yumi_li[dramsim_i][i] = dramsim3_yumi_lo[dramsim_i][i];
end // for (genvar i = 0; i < num_channels_p; i++)
end // for (genvar dramsim_i = 0; dramsim_i < num_dramsim3_p; dramsim_i++)
for (genvar i = 0; i < num_channels_p; i++) begin
bsg_nonsynth_test_rom #(.data_width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
,.filename_p(`BSG_STRINGIFY(`rom_file))
) rom0 (
.addr_i(rom_addr[0][i])
,.data_o(rom_data[0][i])
);
bsg_nonsynth_test_rom #(.data_width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
,.filename_p(`BSG_STRINGIFY(`rom_file_1))
) rom1 (
.addr_i(rom_addr[1][i])
,.data_o(rom_data[1][i])
);
end // for (genvar i = 0; i < num_channels_p; i++)
initial begin
# 10000000 $finish;
end
// always_ff @(posedge clk) begin
// if (~reset & dramsim3_v_li[0][0]) begin
// if (dramsim3_write_not_read_li[0][0])
// $display("write: 0x%08x {ro: %d, ba: %d, bg: %d, co: %d, byte: %d}",
// dramsim3_ch_addr_li[0][0],
// dramsim3_ch_addr_li_cast[0].ro,
// dramsim3_ch_addr_li_cast[0].ba,
// dramsim3_ch_addr_li_cast[0].bg,
// dramsim3_ch_addr_li_cast[0].co,
// dramsim3_ch_addr_li_cast[0].byte_offset);
// else
// $display("read: 0x%08x {ro: %d, ba: %d, bg: %d, co: %d, byte: %d}",
// dramsim3_ch_addr_li[0][0],
// dramsim3_ch_addr_li_cast[0].ro,
// dramsim3_ch_addr_li_cast[0].ba,
// dramsim3_ch_addr_li_cast[0].bg,
// dramsim3_ch_addr_li_cast[0].co,
// dramsim3_ch_addr_li_cast[0].byte_offset);
// end
// end
endmodule |
module wb_tx1_pcie #(
parameter DATA_INGRESS_FIFO_DEPTH = 10,
parameter DATA_EGRESS_FIFO_DEPTH = 6,
parameter CONTROL_FIFO_DEPTH = 7
) (
input clk,
input rst,
// output o_sys_rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
output o_pcie_reset,
output o_pcie_per_fifo_sel,
output o_pcie_mem_fifo_sel,
output o_pcie_dma_fifo_sel,
input i_pcie_write_fin,
input i_pcie_read_fin,
output [31:0] o_pcie_data_size,
output [31:0] o_pcie_data_address,
output o_pcie_data_fifo_flg,
output o_pcie_data_read_flg,
output o_pcie_data_write_flg,
input i_pcie_interrupt_stb,
input [31:0] i_pcie_interrupt_value,
input i_pcie_data_clk,
output o_pcie_ingress_fifo_rdy,
input i_pcie_ingress_fifo_act,
output [23:0] o_pcie_ingress_fifo_size,
input i_pcie_ingress_fifo_stb,
output [31:0] o_pcie_ingress_fifo_data,
output o_pcie_ingress_fifo_idle,
output [1:0] o_pcie_egress_fifo_rdy,
input [1:0] i_pcie_egress_fifo_act,
output [23:0] o_pcie_egress_fifo_size,
input i_pcie_egress_fifo_stb,
input [31:0] i_pcie_egress_fifo_data,
//DEBUG
output [3:0] o_sm_state,
// Tx
output o_pcie_exp_tx_p,
output o_pcie_exp_tx_n,
// Rx
input i_pcie_exp_rx_p,
input i_pcie_exp_rx_n,
input i_pcie_clk_p,
input i_pcie_clk_n,
//PCIE Control
input i_pcie_reset_n,
// output o_pcie_wake_n,
input i_pcie_wake_n,
output o_lax_clk,
output [31:0] o_debug,
output o_pcie_clkreq,
output reg o_wbs_int
);
//Local Parameters
localparam CONTROL = 32'h00;
localparam STATUS = 32'h01;
//Local Registers/Wires
wire w_sys_rst;
wire w_user_link_up;
wire w_user_reset_out;
/*
wire [15:0] w_cfg_status;
wire [15:0] w_cfg_command;
wire [15:0] w_cfg_dstatus;
wire [15:0] w_cfg_dcommand;
wire [15:0] w_cfg_lstatus;
wire [15:0] w_cfg_lcommand;
wire [15:0] w_cfg_dcommand2;
wire [2:0] w_cfg_pcie_link_state;
*/
wire [5:0] w_pl_ltssm_state;
wire w_clock_locked;
wire o_clk_in_stopped;
wire [2:0] pipe_rx0_status_gt;
wire pipe_rx0_phy_status_gt;
wire [3:0] w_tx_diff_ctr;
wire w_pl_sel_lnk_rate;
wire [1:0] w_pl_sel_lnk_width;
wire [2:0] w_pl_initial_link_width;
wire [15:0] w_rx_data;
wire [1:0] w_rx_data_k;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
wire w_master_ready;
wire w_in_ready;
wire [31:0] w_in_command;
wire [31:0] w_in_address;
wire [31:0] w_in_data;
wire [27:0] w_in_data_count;
wire w_out_ready;
wire w_ih_reset;
wire [31:0] w_id_value;
wire [31:0] w_command_value;
wire [31:0] w_count_value;
wire [31:0] w_address_value;
wire [63:0] m64_axis_rx_tdata;
wire [7:0] m64_axis_rx_tkeep;
wire m64_axis_rx_tlast;
wire m64_axis_rx_tvalid;
wire m64_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire [31:0] m32_axis_rx_tdata;
wire [3:0] m32_axis_rx_tkeep;
wire m32_axis_rx_tlast;
wire m32_axis_rx_tvalid;
wire m32_axis_rx_tready;
wire s64_axis_tx_tready;
wire [63:0] s64_axis_tx_tdata;
wire [7:0] s64_axis_tx_tkeep;
wire s64_axis_tx_tlast;
wire s64_axis_tx_tvalid;
wire s32_axis_tx_tready;
wire [31:0] s32_axis_tx_tdata;
wire [3:0] s32_axis_tx_tkeep;
wire s32_axis_tx_tlast;
wire s32_axis_tx_tvalid;
wire [3:0] ingress_state;
wire [3:0] controller_state;
//Submodules
tx1_pcie_adapter pcie_adapter (
.clk (clk ),
.rst (rst ),
.o_user_link_up (w_user_link_up ),
.o_sys_rst (w_sys_rst ),
/******************************************
* Debug Interface *
******************************************/
.o_lax_clk (w_lax_clk ),
.o_user_reset_out (w_user_reset_out ),
.o_pl_ltssm_state (w_pl_ltssm_state ),
.pipe_rx0_status_gt (pipe_rx0_status_gt ),
.pipe_rx0_phy_status_gt (pipe_rx0_phy_status_gt ),
.o_clock_locked (w_clock_locked ),
.o_clk_in_stopped (o_clk_in_stopped ),
.i_tx_diff_ctr (w_tx_diff_ctr ),
.o_pl_sel_lnk_rate (w_pl_sel_lnk_rate ),
.o_pl_sel_lnk_width (w_pl_sel_lnk_width ),
.o_pl_initial_link_width (w_pl_initial_link_width ),
/*
.o_cfg_status (w_cfg_status ),
.o_cfg_command (w_cfg_command ),
.o_cfg_dstatus (w_cfg_dstatus ),
.o_cfg_dcommand (w_cfg_dcommand ),
.o_cfg_lstatus (w_cfg_lstatus ),
.o_cfg_lcommand (w_cfg_lcommand ),
.o_cfg_dcommand2 (w_cfg_dcommand2 ),
.o_cfg_pcie_link_state (w_cfg_pcie_link_state ),
*/
.m64_axis_rx_tdata (m64_axis_rx_tdata ),
.m64_axis_rx_tkeep (m64_axis_rx_tkeep ),
.m64_axis_rx_tlast (m64_axis_rx_tlast ),
.m64_axis_rx_tvalid (m64_axis_rx_tvalid ),
.m64_axis_rx_tready (m64_axis_rx_tready ),
.m_axis_rx_tuser (maxis_rx_tuser ),
.m32_axis_rx_tdata (m32_axis_rx_tdata ),
.m32_axis_rx_tkeep (m32_axis_rx_tkeep ),
.m32_axis_rx_tlast (m32_axis_rx_tlast ),
.m32_axis_rx_tvalid (m32_axis_rx_tvalid ),
.m32_axis_rx_tready (m32_axis_rx_tready ),
.s64_axis_tx_tdata (s64_axis_tx_tdata ),
.s64_axis_tx_tkeep (s64_axis_tx_tkeep ),
.s64_axis_tx_tlast (s64_axis_tx_tlast ),
.s64_axis_tx_tvalid (s64_axis_tx_tvalid ),
.s64_axis_tx_tready (s64_axis_tx_tready ),
.s32_axis_tx_tdata (s32_axis_tx_tdata ),
.s32_axis_tx_tkeep (s32_axis_tx_tkeep ),
.s32_axis_tx_tlast (s32_axis_tx_tlast ),
.s32_axis_tx_tvalid (s32_axis_tx_tvalid ),
.s32_axis_tx_tready (s32_axis_tx_tready ),
.o_ingress_state (ingress_state ),
.o_controller_state (controller_state ),
/******************************************
* PCIE Phy Interface *
******************************************/
// Tx
.o_pcie_exp_tx_p (o_pcie_exp_tx_p ),
.o_pcie_exp_tx_n (o_pcie_exp_tx_n ),
// Rx
.i_pcie_exp_rx_p (i_pcie_exp_rx_p ),
.i_pcie_exp_rx_n (i_pcie_exp_rx_n ),
.i_pcie_clk_p (i_pcie_clk_p ),
.i_pcie_clk_n (i_pcie_clk_n ),
.o_rx_data (w_rx_data ),
.o_rx_data_k (w_rx_data_k ),
.o_rx_byte_is_comma (w_rx_byte_is_comma ),
.o_rx_byte_is_aligned (w_rx_byte_is_aligned ),
//PCIE Control control
.i_pcie_reset_n (i_pcie_reset_n ),
.o_pcie_clkreq (o_pcie_clkreq ),
/******************************************
* Host Interface *
******************************************/
.o_per_fifo_sel (o_pcie_per_fifo_sel ),
.o_mem_fifo_sel (o_pcie_mem_fifo_sel ),
.o_dma_fifo_sel (o_pcie_dma_fifo_sel ),
.i_write_fin (i_pcie_write_fin ),
.i_read_fin (i_pcie_read_fin ),
.o_data_size (o_pcie_data_size ),
.o_data_address (o_pcie_data_address ),
.o_data_fifo_flg (o_pcie_data_fifo_flg ),
.o_data_read_flg (o_pcie_data_read_flg ),
.o_data_write_flg (o_pcie_data_write_flg ),
.i_usr_interrupt_stb (i_pcie_interrupt ),
.i_usr_interrupt_value (i_pcie_interrupt_value ),
//Ingress FIFO
.i_data_clk (i_pcie_data_clk ),
.o_ingress_fifo_rdy (o_pcie_ingress_fifo_rdy ),
.i_ingress_fifo_act (i_pcie_ingress_fifo_act ),
.o_ingress_fifo_size (o_pcie_ingress_fifo_size ),
.i_ingress_fifo_stb (i_pcie_ingress_fifo_stb ),
.o_ingress_fifo_data (o_pcie_ingress_fifo_data ),
.o_ingress_fifo_idle (o_pcie_ingress_fifo_idle ),
//Egress FIFO
.o_egress_fifo_rdy (o_pcie_egress_fifo_rdy ),
.i_egress_fifo_act (i_pcie_egress_fifo_act ),
.o_egress_fifo_size (o_pcie_egress_fifo_size ),
.i_egress_fifo_stb (i_pcie_egress_fifo_stb ),
.i_egress_fifo_data (i_pcie_egress_fifo_data )
);
assign o_lax_clk = w_lax_clk;
//Asynchronous Logic
/*
//LINKUP Debug
assign o_debug[15:0] = w_rx_data;
assign o_debug[17:16] = w_rx_data_k;
assign o_debug[20:18] = pipe_rx0_status_gt;
assign o_debug[21] = pipe_rx0_phy_status_gt;
assign o_debug[23:22] = w_rx_byte_is_comma;
assign o_debug[29:24] = w_pl_ltssm_state;
//assign o_debug[31:30] = w_rx_byte_is_aligned;
assign o_debug[30] = w_rx_byte_is_aligned;
assign o_debug[31] = w_clock_locked;
*/
/*
//PCIE Comm Incomming Debug
//assign o_debug[15:0] = m64_axis_rx_tdata[15:0];
assign o_debug[15:0] = m32_axis_rx_tdata[15:0];
assign o_debug[19:16] = m32_axis_rx_tkeep[3:0];
assign o_debug[20] = m32_axis_rx_tvalid;
assign o_debug[21] = m32_axis_rx_tready;
assign o_debug[22] = m32_axis_rx_tlast;
assign o_debug[23] = 1'b0;
assign o_debug[27:24] = ingress_state;
assign o_debug[31:28] = controller_state;
*/
/*
assign o_debug[28] = m32_axis_rx_tvalid;
assign o_debug[29] = m32_axis_rx_tready;
assign o_debug[30] = m32_axis_rx_tlast;
assign o_debug[31] = 1'b0;
*/
assign o_debug[15:0] = s64_axis_tx_tdata[15:0];
//assign o_debug[15:0] = s32_axis_tx_tdata[15:0];
assign o_debug[19:16] = s64_axis_tx_tkeep[3:0];
assign o_debug[20] = s64_axis_tx_tvalid;
assign o_debug[21] = s64_axis_tx_tready;
assign o_debug[22] = s64_axis_tx_tlast;
assign o_debug[23] = 1'b0;
assign o_debug[27:24] = ingress_state;
assign o_debug[31:28] = controller_state;
//assign o_pcie_reset = w_user_reset_out;
assign o_pcie_reset = w_sys_rst;
assign w_tx_diff_ctr = 4'hC;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
CONTROL: begin
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
o_wbs_ack <= 1;
end
else begin
//read request
case (i_wbs_adr)
CONTROL: begin
o_wbs_dat <= 0;
end
STATUS: begin
o_wbs_dat <= 0;
end
default: begin
end
endcase
o_wbs_ack <= 1;
end
end
end
end
end
endmodule |
module sky130_fd_sc_lp__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module sky130_fd_sc_hd__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule |
module md_ram (
clk ,
wdata ,
waddr ,
we ,
rd ,
raddr ,
rdata
);
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk ;
input [31:0] wdata ;
input [3:0] waddr ;
input we ;
input rd ;
input [3:0] raddr ;
output [31:0] rdata ;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(.Addr_Width(4), .Word_Width(32))
rf_2p_32x16 (
.clka ( clk ),
.cena_i ( ~rd ),
.addra_i ( raddr ),
.dataa_o ( rdata ),
.clkb ( clk ),
.cenb_i ( ~we ),
.wenb_i ( ~we ),
.addrb_i ( waddr ),
.datab_i ( wdata )
);
endmodule |
module tld_sam (
input wire clk50mhz,
// Audio I/O
input wire ear,
output wire audio_out_left,
output wire audio_out_right,
// Video output
inout wire [2:0] r,
inout wire [2:0] g,
inout wire [2:0] b,
inout wire hsync,
inout wire vsync,
output wire [2:0] dr,
output wire [2:0] dg,
output wire [2:0] db,
output wire dhsync,
output wire dvsync,
output wire stdn,
output wire stdnb,
// SRAM interface
output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
// PS/2 keyoard interface
inout wire clkps2,
inout wire dataps2
);
// Interface with RAM
wire [18:0] sram_addr_from_sam;
wire sram_we_n_from_sam;
// Audio and video
wire [1:0] sam_r, sam_g, sam_b;
wire sam_bright;
// scandoubler
wire hsync_pal, vsync_pal;
wire [2:0] ri = {sam_r, sam_bright};
wire [2:0] gi = {sam_g, sam_bright};
wire [2:0] bi = {sam_b, sam_bright};
assign dr = r;
assign dg = g;
assign db = b;
assign dhsync = hsync;
assign dvsync = vsync;
assign stdn = 1'b0; // fijar norma PAL
assign stdnb = 1'b1; // y conectamos reloj PAL
wire clk24, clk12, clk6, clk8;
reg [7:0] poweron_reset = 8'h00;
reg [1:0] scandoubler_ctrl = 2'b00;
always @(posedge clk6) begin
poweron_reset <= {poweron_reset[6:0], 1'b1};
if (poweron_reset[6] == 1'b0)
scandoubler_ctrl <= sram_data[1:0];
end
assign sram_addr = (poweron_reset[7] == 1'b0)? 21'h008FD5 : {2'b00, sram_addr_from_sam};
assign sram_we_n = (poweron_reset[7] == 1'b0)? 1'b1 : sram_we_n_from_sam;
relojes los_relojes (
.CLK_IN1 (clk50mhz), // IN
// Clock out ports
.CLK_OUT1 (clk24), // modulo multiplexor de SRAM
.CLK_OUT2 (clk12), // ASIC
.CLK_OUT3 (clk6), // CPU y teclado PS/2
.CLK_OUT4 (clk8) // SAA1099 y DAC
);
samcoupe maquina (
.clk24(clk24),
.clk12(clk12),
.clk6(clk6),
.clk8(clk8),
.master_reset_n(poweron_reset[7]),
// Video output
.r(sam_r),
.g(sam_g),
.b(sam_b),
.bright(sam_bright),
.hsync_pal(hsync_pal),
.vsync_pal(vsync_pal),
// Audio output
.ear(~ear),
.audio_out_left(audio_out_left),
.audio_out_right(audio_out_right),
// PS/2 keyboard
.clkps2(clkps2),
.dataps2(dataps2),
// SRAM external interface
.sram_addr(sram_addr_from_sam),
.sram_data(sram_data),
.sram_we_n(sram_we_n_from_sam)
);
vga_scandoubler #(.CLKVIDEO(12000)) salida_vga (
.clkvideo(clk12),
.clkvga(clk24),
.enable_scandoubling(scandoubler_ctrl[0]),
.disable_scaneffect(~scandoubler_ctrl[1]),
.ri(ri),
.gi(gi),
.bi(bi),
.hsync_ext_n(hsync_pal),
.vsync_ext_n(vsync_pal),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync)
);
endmodule |
module sky130_fd_sc_ms__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module stratix3_pmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule |
module axis_delay #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
input wire [CNTR_WIDTH-1:0] axis_data_count,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
// Slave side
output wire s_axis_fifo_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_fifo_tdata,
input wire s_axis_fifo_tvalid,
// Master side
input wire m_axis_fifo_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_fifo_tdata,
output wire m_axis_fifo_tvalid
);
reg int_enbl_reg, int_enbl_next;
wire int_comp_wire;
assign int_comp_wire = axis_data_count > cfg_data;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_enbl_reg <= 1'b0;
end
else
begin
int_enbl_reg <= int_enbl_next;
end
end
always @*
begin
int_enbl_next = int_enbl_reg;
if( ~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
end
assign m_axis_fifo_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_fifo_tready;
assign m_axis_tvalid = int_enbl_reg ? s_axis_fifo_tvalid : s_axis_tvalid;
assign s_axis_fifo_tready = int_enbl_reg ? m_axis_tready : 1'b0;
assign m_axis_fifo_tdata=s_axis_tdata;
assign m_axis_tdata=s_axis_fifo_tdata;
endmodule |
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input LOWHVPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module
assign mrd_s = (mwaddr == mraddr) ? 1'b0 : win_ready;
assign maddrdiff_s = {1'b1, mwaddr} - mraddr;
assign mxfer_s = win_ready | ~win_valid;
always @(posedge clk) begin
maddrdiff <= maddrdiff_s[5:0];
if (maddrdiff >= 32) begin
adc_ready <= 1'b0;
end else if (maddrdiff <= 20) begin
adc_ready <= 1'b1;
end
end
// read and address update
always @(posedge clk) begin
if (mrd_s == 1'b1) begin
mraddr <= mraddr + 1'b1;
end
mrd <= mrd_s;
mrvalid <= mrd;
mrdata <= mrdata_s;
end
// hold data during sudden death (ready de-asserted!)
always @(posedge clk) begin
if (mrvalid == 1'b1) begin
mwcnt <= mwcnt + 1'b1;
end
if ((mwcnt == 2'd0) && (mrvalid == 1'b1)) begin
mvalid_0 <= 1'b1;
mdata_0 <= mrdata;
end else if ((mrcnt == 2'd0) && (mxfer_s == 1'b1)) begin
mvalid_0 <= 1'b0;
mdata_0 <= 17'd0;
end
if ((mwcnt == 2'd1) && (mrvalid == 1'b1)) begin
mvalid_1 <= 1'b1;
mdata_1 <= mrdata;
end else if ((mrcnt == 2'd1) && (mxfer_s == 1'b1)) begin
mvalid_1 <= 1'b0;
mdata_1 <= 17'd0;
end
if ((mwcnt == 2'd2) && (mrvalid == 1'b1)) begin
mvalid_2 <= 1'b1;
mdata_2 <= mrdata;
end else if ((mrcnt == 2'd2) && (mxfer_s == 1'b1)) begin
mvalid_2 <= 1'b0;
mdata_2 <= 17'd0;
end
if ((mwcnt == 2'd3) && (mrvalid == 1'b1)) begin
mvalid_3 <= 1'b1;
mdata_3 <= mrdata;
end else if ((mrcnt == 2'd3) && (mxfer_s == 1'b1)) begin
mvalid_3 <= 1'b0;
mdata_3 <= 17'd0;
end
if ((mrcnt != mwcnt) && (win_ready == 1'b1)) begin
mrcnt <= mrcnt + 1'b1;
end
if ((win_valid == 1'b0) || (win_ready == 1'b1)) begin
case (mrcnt)
2'd3: begin
win_valid <= mvalid_3;
win_data <= mdata_3[15:0];
win_last <= mdata_3[16] & mvalid_3;
end
2'd2: begin
win_valid <= mvalid_2;
win_data <= mdata_2[15:0];
win_last <= mdata_2[16] & mvalid_2;
end
2'd1: begin
win_valid <= mvalid_1;
win_data <= mdata_1[15:0];
win_last <= mdata_1[16] & mvalid_1;
end
default: begin
win_valid <= mvalid_0;
win_data <= mdata_0[15:0];
win_last <= mdata_0[16] & mvalid_0;
end
endcase
end
end
endmodule |
module sky130_fd_sc_lp__dlybuf4s50kapwr (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule |
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