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module sky130_fd_sc_lp__diode_0 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__diode_0 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__diode base (
.DIODE(DIODE)
);
endmodule |
module cpx_buf_pdr_even(/*AUTOARG*/
// Outputs
arbcp0_cpxdp_grant_ca, arbcp0_cpxdp_q0_hold_ca_l,
arbcp0_cpxdp_qsel0_ca, arbcp0_cpxdp_qsel1_ca_l,
arbcp0_cpxdp_shift_cx, arbcp2_cpxdp_grant_ca,
arbcp2_cpxdp_q0_hold_ca_l, arbcp2_cpxdp_qsel0_ca,
arbcp2_cpxdp_qsel1_ca_l, arbcp2_cpxdp_shift_cx,
arbcp4_cpxdp_grant_ca, arbcp4_cpxdp_q0_hold_ca_l,
arbcp4_cpxdp_qsel0_ca, arbcp4_cpxdp_qsel1_ca_l,
arbcp4_cpxdp_shift_cx, arbcp6_cpxdp_grant_ca,
arbcp6_cpxdp_q0_hold_ca_l, arbcp6_cpxdp_qsel0_ca,
arbcp6_cpxdp_qsel1_ca_l, arbcp6_cpxdp_shift_cx,
// Inputs
arbcp0_cpxdp_grant_bufp3_ca, arbcp0_cpxdp_q0_hold_bufp3_ca_l,
arbcp0_cpxdp_qsel0_bufp3_ca, arbcp0_cpxdp_qsel1_bufp3_ca_l,
arbcp0_cpxdp_shift_bufp3_cx, arbcp2_cpxdp_grant_bufp3_ca,
arbcp2_cpxdp_q0_hold_bufp3_ca_l, arbcp2_cpxdp_qsel0_bufp3_ca,
arbcp2_cpxdp_qsel1_bufp3_ca_l, arbcp2_cpxdp_shift_bufp3_cx,
arbcp4_cpxdp_grant_bufp3_ca, arbcp4_cpxdp_q0_hold_bufp3_ca_l,
arbcp4_cpxdp_qsel0_bufp3_ca, arbcp4_cpxdp_qsel1_bufp3_ca_l,
arbcp4_cpxdp_shift_bufp3_cx, arbcp6_cpxdp_grant_bufp3_ca,
arbcp6_cpxdp_q0_hold_bufp3_ca_l, arbcp6_cpxdp_qsel0_bufp3_ca,
arbcp6_cpxdp_qsel1_bufp3_ca_l, arbcp6_cpxdp_shift_bufp3_cx
);
output arbcp0_cpxdp_grant_ca ;
output arbcp0_cpxdp_q0_hold_ca_l ;
output arbcp0_cpxdp_qsel0_ca ;
output arbcp0_cpxdp_qsel1_ca_l ;
output arbcp0_cpxdp_shift_cx ;
output arbcp2_cpxdp_grant_ca ;
output arbcp2_cpxdp_q0_hold_ca_l ;
output arbcp2_cpxdp_qsel0_ca ;
output arbcp2_cpxdp_qsel1_ca_l ;
output arbcp2_cpxdp_shift_cx ;
output arbcp4_cpxdp_grant_ca ;
output arbcp4_cpxdp_q0_hold_ca_l ;
output arbcp4_cpxdp_qsel0_ca ;
output arbcp4_cpxdp_qsel1_ca_l ;
output arbcp4_cpxdp_shift_cx ;
output arbcp6_cpxdp_grant_ca ;
output arbcp6_cpxdp_q0_hold_ca_l ;
output arbcp6_cpxdp_qsel0_ca ;
output arbcp6_cpxdp_qsel1_ca_l ;
output arbcp6_cpxdp_shift_cx ;
input arbcp0_cpxdp_grant_bufp3_ca;
input arbcp0_cpxdp_q0_hold_bufp3_ca_l;
input arbcp0_cpxdp_qsel0_bufp3_ca;
input arbcp0_cpxdp_qsel1_bufp3_ca_l;
input arbcp0_cpxdp_shift_bufp3_cx;
input arbcp2_cpxdp_grant_bufp3_ca;
input arbcp2_cpxdp_q0_hold_bufp3_ca_l;
input arbcp2_cpxdp_qsel0_bufp3_ca;
input arbcp2_cpxdp_qsel1_bufp3_ca_l;
input arbcp2_cpxdp_shift_bufp3_cx;
input arbcp4_cpxdp_grant_bufp3_ca;
input arbcp4_cpxdp_q0_hold_bufp3_ca_l;
input arbcp4_cpxdp_qsel0_bufp3_ca;
input arbcp4_cpxdp_qsel1_bufp3_ca_l;
input arbcp4_cpxdp_shift_bufp3_cx;
input arbcp6_cpxdp_grant_bufp3_ca;
input arbcp6_cpxdp_q0_hold_bufp3_ca_l;
input arbcp6_cpxdp_qsel0_bufp3_ca;
input arbcp6_cpxdp_qsel1_bufp3_ca_l;
input arbcp6_cpxdp_shift_bufp3_cx;
assign arbcp0_cpxdp_grant_ca = arbcp0_cpxdp_grant_bufp3_ca;
assign arbcp0_cpxdp_q0_hold_ca_l = arbcp0_cpxdp_q0_hold_bufp3_ca_l;
assign arbcp0_cpxdp_qsel0_ca = arbcp0_cpxdp_qsel0_bufp3_ca;
assign arbcp0_cpxdp_qsel1_ca_l = arbcp0_cpxdp_qsel1_bufp3_ca_l;
assign arbcp0_cpxdp_shift_cx = arbcp0_cpxdp_shift_bufp3_cx;
assign arbcp2_cpxdp_grant_ca = arbcp2_cpxdp_grant_bufp3_ca;
assign arbcp2_cpxdp_q0_hold_ca_l = arbcp2_cpxdp_q0_hold_bufp3_ca_l;
assign arbcp2_cpxdp_qsel0_ca = arbcp2_cpxdp_qsel0_bufp3_ca;
assign arbcp2_cpxdp_qsel1_ca_l = arbcp2_cpxdp_qsel1_bufp3_ca_l;
assign arbcp2_cpxdp_shift_cx = arbcp2_cpxdp_shift_bufp3_cx;
assign arbcp4_cpxdp_grant_ca = arbcp4_cpxdp_grant_bufp3_ca;
assign arbcp4_cpxdp_q0_hold_ca_l = arbcp4_cpxdp_q0_hold_bufp3_ca_l;
assign arbcp4_cpxdp_qsel0_ca = arbcp4_cpxdp_qsel0_bufp3_ca;
assign arbcp4_cpxdp_qsel1_ca_l = arbcp4_cpxdp_qsel1_bufp3_ca_l;
assign arbcp4_cpxdp_shift_cx = arbcp4_cpxdp_shift_bufp3_cx;
assign arbcp6_cpxdp_grant_ca = arbcp6_cpxdp_grant_bufp3_ca;
assign arbcp6_cpxdp_q0_hold_ca_l = arbcp6_cpxdp_q0_hold_bufp3_ca_l;
assign arbcp6_cpxdp_qsel0_ca = arbcp6_cpxdp_qsel0_bufp3_ca;
assign arbcp6_cpxdp_qsel1_ca_l = arbcp6_cpxdp_qsel1_bufp3_ca_l;
assign arbcp6_cpxdp_shift_cx = arbcp6_cpxdp_shift_bufp3_cx;
endmodule |
module pipeline2(
clk_in, // clock_in
RST, // reset
pc_in, // entrada - contador de programa
instr, // instrucao
reg_addr, // endereco do registrador a ser gravado
reg_data, // dados a serem gravados no registrador reg_addr
reg_en, // habilita gravacao de reg_data em reg_addr no banco de registradores
A_addr, // endereco do registrador 1
B_addr, // endereco do registrador 2
A, // dados do registrador 1
B, // dados do registrador 2
imm, // immediato
pc_out, // saida - contador de programa
ctrl // saida - controller do processador,
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// declaracao de entrada / saida
input clk_in, RST;
input [PC_WIDTH-1:0] pc_in;
input [INSTR_WIDTH-1:0] instr;
input [REG_ADDR_WIDTH-1:0] reg_addr;
input [DATA_WIDTH-1:0] reg_data;
input reg_en;
output reg signed [DATA_WIDTH-1:0] imm;
output reg [PC_WIDTH-1:0] pc_out;
output reg [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
output signed [DATA_WIDTH-1:0] A, B;
output [CTRL_WIDTH-1:0] ctrl;
// variaveis auxiliares
reg [OPCODE_WIDTH-1:0] opcode;
wire clk_neg;
// instanciacao do controller e do banco de registradores
controller ctrl0(.opcode(opcode), .ctrl(ctrl));
regs regs0(.clk(clk_neg),
.en_write(reg_en), .addr_write(reg_addr), .data_write(reg_data),
.addr_read1(A_addr), .addr_read2(B_addr),
.data_read1(A), .data_read2(B));
assign clk_neg = ~clk_in;
// decodifique a instrucao e
// gera done indicando dados de saida estaveis
always @(posedge clk_in) begin
if (!RST) begin
// rotina de reset
opcode <= NOP;
A_addr <= 0;
B_addr <= 0;
imm <= 0;
// reset - PC vai pro valor inicial
pc_out <= PC_INITIAL + 1;
end else begin
opcode <= instr[OPCODE_WIDTH-1:0];
A_addr <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH];
B_addr <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH];
imm <= instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2];
// se opcode == RET, entao leia o registrador REG_FUNC_RET
if (instr[OPCODE_WIDTH-1:0] == RET) begin
A_addr <= REG_FUNC_RET;
end
// faca pc_out = pc_in (nao mexemos no pc no pipeline 2)
pc_out <= pc_in;
end
end
endmodule |
module system ( input CLK,
//DE0 ADC
output ADC_CS,
output ADC_SCLK,
output ADC_SDO,
input ADC_SDI,
//DE0 USER IO
input [1:0] BTNS,
input [3:0] DIP_SW,
output [7:0] LEDS );
//==================WIRE DECLARATIONS============================//
wire CLK_CPU, CLK_MEM, CLK_1M, RESET, RUN, I_SOURCE;
wire [31:0] INST_RD, CPU_RD, CPU_WD, STACK_MEM_WD, STACK_MEM_RD,
INST_D_RD, INST_D_WD;
wire [29:0] INST_ADDR, CPU_ADDR, STACK_MEM_A, INST_D_A;
wire [3:0] CPU_BE, STACK_MEM_BE;
wire CPU_WE, STACK_MEM_WE, INST_D_WE;
//JTAG signals
wire JTAG_WE;
wire [31:0] JTAG_WD, JTAG_RD, DEBUG_INST, CPU_INSTRUCTION;
//ADC signals
wire ADC_WE;
wire [31:0] ADC_RD, ADC_WD;
//USER IO
wire [31:0] USER_IO;
//Led signals
wire [31:0] LEDS_WD;
wire LEDS_WE;
//===================SYSTEM CLOCK================================//
pll main_pll(CLK, CLK_CPU, CLK_MEM, CLK_1M);
//======================THE CPU==================================//
mcpu the_cpu (.CLK ( CLK_CPU ),
.CLK_MEM ( CLK_MEM ),
.RESET ( RESET ),
.RUN ( RUN ),
//External inst memory iface
.INST_ADDR ( INST_ADDR ),
.INST_RD ( CPU_INSTRUCTION ),
//External data memory iface
.DATA_WE ( CPU_WE ),
.DATA_BE ( CPU_BE ),
.DATA_ADDR ( CPU_ADDR ),
.DATA_WD ( CPU_WD ),
.DATA_RD ( CPU_RD ));
//===================INSTRUCTION MEMORY==========================//
imem instr_mem( .CLK ( CLK_MEM ),
.DATA_A ( INST_D_A ),
.DATA_WE ( INST_D_WE ),
.DATA_WD ( INST_D_WD ),
.DATA_RD ( INST_D_RD ),
.MAIN_A ( INST_ADDR ),
.MAIN_RD ( INST_RD ));
//======================STACK SPACE==============================//
dmem stack_mem( .CLK ( CLK_MEM ),
.WE ( STACK_MEM_WE ),
.BE ( STACK_MEM_BE ),
.ADDR ( STACK_MEM_A ),
.WD ( STACK_MEM_WD ),
.RD ( STACK_MEM_RD ));
jtag jtag_m ( .CPU_CLK ( CLK_CPU ),
//CPU controls
.RESET ( RESET ), //cpu reset, 1 -- reset;
.RUN ( RUN ), //cpu run. 0 - pause, 1 - run. Pulsed in step-by-step
.I_SOURCE ( I_SOURCE ), //cpu instruction source; 0 for normal mem
//32bit DEBUG DATA PORT
.WE ( JTAG_WE ),
.WD ( JTAG_WD ),
.RD ( JTAG_RD ),
//32bit DEBUG INSTR PORT
.DEBUG_INST ( DEBUG_INST ), //cpu instruction from jtag
.MEM_INST ( INST_RD ), //current instruction from main mem
.INST_ADDR ( INST_ADDR )); //cpu inst memory address
mux2 isrc_mux (I_SOURCE, INST_RD,
DEBUG_INST, CPU_INSTRUCTION );
//=====================BUS CONTROLLER============================//
bus_controller bc( .CPU_ADDR ( CPU_ADDR ),
.CPU_WE ( CPU_WE ),
.CPU_BE ( CPU_BE ),
.CPU_WD ( CPU_WD ),
.CPU_RD ( CPU_RD ),
.STACK_MEM_A ( STACK_MEM_A ),
.STACK_MEM_BE ( STACK_MEM_BE ),
.STACK_MEM_WE ( STACK_MEM_WE ),
.STACK_MEM_WD ( STACK_MEM_WD ),
.STACK_MEM_RD ( STACK_MEM_RD ),
.CODE_MEM_A ( INST_D_A ),
.CODE_MEM_WE ( INST_D_WE ),
.CODE_MEM_WD ( INST_D_WD ),
.CODE_MEM_RD ( INST_D_RD ),
.JTAG_WE ( JTAG_WE ),
.JTAG_WD ( JTAG_WD ),
.JTAG_RD ( JTAG_RD ),
.ADC_WE ( ADC_WE ),
.ADC_WD ( ADC_WD ),
.ADC_RD ( ADC_RD ),
.USER_IO ( USER_IO ),
.LEDS_WE ( LEDS_WE ),
.LEDS_WD ( LEDS_WD ));
//========================LEDS===================================//
io8 led_reg( .CLK ( CLK_CPU ),
.WE ( LEDS_WE ),
.DATA_IN ( LEDS_WD ),
.IO_OUT ( LEDS ));
//======================USER INPUT===============================//
io6 user_io( .CLK_IO ( CLK_1M ),
.BTNS ( BTNS ),
.DIP_SW ( DIP_SW ),
.IO_OUT ( USER_IO ));
//=========================ADC===================================//
adc_interface the_adc( .CLK ( CLK_CPU ),
.CLK_1M ( CLK_1M ),
//processor interface
.DATA_IN ( ADC_WD ),
.DATA_OUT ( ADC_RD ),
.WR ( ADC_WE ),
//device interface
.CS ( ADC_CS ),
.SCLK ( ADC_SCLK ),
.SDO ( ADC_SDO ),
.SDI ( ADC_SDI ));
endmodule |
module ctu_clsp_clkgn_ssiclk(/*AUTOARG*/
// Outputs
ctu_jbi_ssiclk,
// Inputs
io_pwron_rst_l, jbus_clk, ssiclk_enable
);
input io_pwron_rst_l;
input jbus_clk;
input ssiclk_enable;
output ctu_jbi_ssiclk;
wire jbus_clk_stage1_nxt;
wire jbus_clk_stage1;
wire ctu_jbi_ssiclk;
assign jbus_clk_stage1_nxt = jbus_clk_stage1 | ctu_jbi_ssiclk?
~ctu_jbi_ssiclk : (~ctu_jbi_ssiclk & ssiclk_enable);
dffrl_async_ns u_ctu_jbi_ssiclk_d1 (
.din (jbus_clk_stage1_nxt),
.clk (jbus_clk),
.rst_l(io_pwron_rst_l),
.q(jbus_clk_stage1));
dffrl_async_ns u_ctu_jbi_ssiclk_d2 (
.din (jbus_clk_stage1),
.clk (jbus_clk),
.rst_l(io_pwron_rst_l),
.q(ctu_jbi_ssiclk));
endmodule |
module header
// Internal signals
//
// Generated Signal List
//
wire mix_logic0_0;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign mix_logic0_0 = 1'b0;
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
ent_a inst_a (
.low_bit_a(mix_logic0_0) // Ground bit port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
);
// End of Generated Instance Port Map for inst_b
endmodule |
module fifo_64in_out
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
valid,
rd_data_count);
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output valid;
output [11:0]rd_data_count;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire rst;
wire valid;
wire wr_clk;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [11:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [11:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "1" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "1" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4093" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "4092" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "12" *)
(* C_RD_DEPTH = "4096" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "12" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
fifo_64in_out_fifo_generator_v12_0__parameterized0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[11:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(valid),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[11:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule |
module fifo_64in_out_blk_mem_gen_generic_cstr
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_width \ramloop[0].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[3:0]),
.dout(dout[3:0]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[12:4]),
.dout(dout[12:4]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[21:13]),
.dout(dout[21:13]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[30:22]),
.dout(dout[30:22]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[39:31]),
.dout(dout[39:31]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[48:40]),
.dout(dout[48:40]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[57:49]),
.dout(dout[57:49]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[63:58]),
.dout(dout[63:58]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_width
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [3:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [3:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [3:0]din;
wire [3:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_width__parameterized0
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_width__parameterized1
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_width__parameterized2
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_width__parameterized3
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_width__parameterized4
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_width__parameterized5
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_width__parameterized6
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [5:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [5:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [5:0]din;
wire [5:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_wrapper
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [3:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [3:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [3:0]din;
wire [3:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({O2,1'b0,1'b0}),
.ADDRBWRADDR({O1,1'b0,1'b0}),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized0
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized1
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized2
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized3
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized4
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized5
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized6
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [5:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [5:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [5:0]din;
wire [5:0]dout;
wire \n_60_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \n_61_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\n_60_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,\n_61_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module fifo_64in_out_blk_mem_gen_top
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_generic_cstr \valid.cstr
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_v8_2__parameterized0
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_blk_mem_gen_v8_2_synth
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_clk_x_pntrs
(S,
WR_PNTR_RD,
O1,
O2,
RD_PNTR_WR,
Q,
I1,
wr_clk,
I2,
rd_clk,
I3);
output [3:0]S;
output [11:0]WR_PNTR_RD;
output [3:0]O1;
output [3:0]O2;
output [11:0]RD_PNTR_WR;
input [11:0]Q;
input [11:0]I1;
input wr_clk;
input [0:0]I2;
input rd_clk;
input [0:0]I3;
wire [11:0]I1;
wire [0:0]I2;
wire [0:0]I3;
wire [3:0]O1;
wire [3:0]O2;
wire [11:0]Q;
wire [11:0]Q_0;
wire [11:0]RD_PNTR_WR;
wire [3:0]S;
wire [11:0]WR_PNTR_RD;
wire \n_0_gsync_stage[1].wr_stg_inst ;
wire \n_0_gsync_stage[2].wr_stg_inst ;
wire \n_0_rd_pntr_gc[0]_i_1 ;
wire \n_0_rd_pntr_gc[10]_i_1 ;
wire \n_0_rd_pntr_gc[1]_i_1 ;
wire \n_0_rd_pntr_gc[2]_i_1 ;
wire \n_0_rd_pntr_gc[3]_i_1 ;
wire \n_0_rd_pntr_gc[4]_i_1 ;
wire \n_0_rd_pntr_gc[5]_i_1 ;
wire \n_0_rd_pntr_gc[6]_i_1 ;
wire \n_0_rd_pntr_gc[7]_i_1 ;
wire \n_0_rd_pntr_gc[8]_i_1 ;
wire \n_0_rd_pntr_gc[9]_i_1 ;
wire \n_10_gsync_stage[1].wr_stg_inst ;
wire \n_10_gsync_stage[2].wr_stg_inst ;
wire \n_11_gsync_stage[1].wr_stg_inst ;
wire \n_11_gsync_stage[2].wr_stg_inst ;
wire \n_1_gsync_stage[1].wr_stg_inst ;
wire \n_1_gsync_stage[2].wr_stg_inst ;
wire \n_2_gsync_stage[1].wr_stg_inst ;
wire \n_2_gsync_stage[2].wr_stg_inst ;
wire \n_3_gsync_stage[1].wr_stg_inst ;
wire \n_3_gsync_stage[2].wr_stg_inst ;
wire \n_4_gsync_stage[1].wr_stg_inst ;
wire \n_4_gsync_stage[2].wr_stg_inst ;
wire \n_5_gsync_stage[1].wr_stg_inst ;
wire \n_5_gsync_stage[2].wr_stg_inst ;
wire \n_6_gsync_stage[1].wr_stg_inst ;
wire \n_6_gsync_stage[2].wr_stg_inst ;
wire \n_7_gsync_stage[1].wr_stg_inst ;
wire \n_7_gsync_stage[2].wr_stg_inst ;
wire \n_8_gsync_stage[1].wr_stg_inst ;
wire \n_8_gsync_stage[2].wr_stg_inst ;
wire \n_9_gsync_stage[1].wr_stg_inst ;
wire \n_9_gsync_stage[2].wr_stg_inst ;
wire [11:0]p_0_in;
wire [10:0]p_0_in10_out;
wire rd_clk;
wire [11:0]rd_pntr_gc;
wire wr_clk;
wire [11:0]wr_pntr_gc;
fifo_64in_out_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.I1(wr_pntr_gc),
.I3(I3),
.Q(Q_0),
.rd_clk(rd_clk));
fifo_64in_out_synchronizer_ff_3 \gsync_stage[1].wr_stg_inst
(.I1(rd_pntr_gc),
.I2(I2),
.Q({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst ,\n_4_gsync_stage[1].wr_stg_inst ,\n_5_gsync_stage[1].wr_stg_inst ,\n_6_gsync_stage[1].wr_stg_inst ,\n_7_gsync_stage[1].wr_stg_inst ,\n_8_gsync_stage[1].wr_stg_inst ,\n_9_gsync_stage[1].wr_stg_inst ,\n_10_gsync_stage[1].wr_stg_inst ,\n_11_gsync_stage[1].wr_stg_inst }),
.wr_clk(wr_clk));
fifo_64in_out_synchronizer_ff_4 \gsync_stage[2].rd_stg_inst
(.D(Q_0),
.I3(I3),
.p_0_in(p_0_in),
.rd_clk(rd_clk));
fifo_64in_out_synchronizer_ff_5 \gsync_stage[2].wr_stg_inst
(.D({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst ,\n_4_gsync_stage[1].wr_stg_inst ,\n_5_gsync_stage[1].wr_stg_inst ,\n_6_gsync_stage[1].wr_stg_inst ,\n_7_gsync_stage[1].wr_stg_inst ,\n_8_gsync_stage[1].wr_stg_inst ,\n_9_gsync_stage[1].wr_stg_inst ,\n_10_gsync_stage[1].wr_stg_inst ,\n_11_gsync_stage[1].wr_stg_inst }),
.I2(I2),
.O1({\n_1_gsync_stage[2].wr_stg_inst ,\n_2_gsync_stage[2].wr_stg_inst ,\n_3_gsync_stage[2].wr_stg_inst ,\n_4_gsync_stage[2].wr_stg_inst ,\n_5_gsync_stage[2].wr_stg_inst ,\n_6_gsync_stage[2].wr_stg_inst ,\n_7_gsync_stage[2].wr_stg_inst ,\n_8_gsync_stage[2].wr_stg_inst ,\n_9_gsync_stage[2].wr_stg_inst ,\n_10_gsync_stage[2].wr_stg_inst ,\n_11_gsync_stage[2].wr_stg_inst }),
.Q(\n_0_gsync_stage[2].wr_stg_inst ),
.wr_clk(wr_clk));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[11]_i_2
(.I0(WR_PNTR_RD[11]),
.I1(Q[11]),
.O(O2[3]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[11]_i_3
(.I0(WR_PNTR_RD[10]),
.I1(Q[10]),
.O(O2[2]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[11]_i_4
(.I0(WR_PNTR_RD[9]),
.I1(Q[9]),
.O(O2[1]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[11]_i_5
(.I0(WR_PNTR_RD[8]),
.I1(Q[8]),
.O(O2[0]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_2
(.I0(WR_PNTR_RD[3]),
.I1(Q[3]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_3
(.I0(WR_PNTR_RD[2]),
.I1(Q[2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_4
(.I0(WR_PNTR_RD[1]),
.I1(Q[1]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_5
(.I0(WR_PNTR_RD[0]),
.I1(Q[0]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_2
(.I0(WR_PNTR_RD[7]),
.I1(Q[7]),
.O(O1[3]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_3
(.I0(WR_PNTR_RD[6]),
.I1(Q[6]),
.O(O1[2]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_4
(.I0(WR_PNTR_RD[5]),
.I1(Q[5]),
.O(O1[1]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_5
(.I0(WR_PNTR_RD[4]),
.I1(Q[4]),
.O(O1[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_11_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_1_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[10]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_0_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[11]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_10_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_9_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_8_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_7_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_6_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_5_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_4_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_3_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_2_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[9]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\n_0_rd_pntr_gc[0]_i_1 ));
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[10]_i_1
(.I0(Q[10]),
.I1(Q[11]),
.O(\n_0_rd_pntr_gc[10]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\n_0_rd_pntr_gc[1]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\n_0_rd_pntr_gc[2]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\n_0_rd_pntr_gc[3]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\n_0_rd_pntr_gc[4]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\n_0_rd_pntr_gc[5]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\n_0_rd_pntr_gc[6]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\n_0_rd_pntr_gc[7]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[8]_i_1
(.I0(Q[8]),
.I1(Q[9]),
.O(\n_0_rd_pntr_gc[8]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[9]_i_1
(.I0(Q[9]),
.I1(Q[10]),
.O(\n_0_rd_pntr_gc[9]_i_1 ));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[0]_i_1 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[10]_i_1 ),
.Q(rd_pntr_gc[10]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(Q[11]),
.Q(rd_pntr_gc[11]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[1]_i_1 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[2]_i_1 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[3]_i_1 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[4]_i_1 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[5]_i_1 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[6]_i_1 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[7]_i_1 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[8]_i_1 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[9]_i_1 ),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[10]),
.Q(WR_PNTR_RD[10]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[11]),
.Q(WR_PNTR_RD[11]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[1]),
.Q(WR_PNTR_RD[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[2]),
.Q(WR_PNTR_RD[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[3]),
.Q(WR_PNTR_RD[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[4]),
.Q(WR_PNTR_RD[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[5]),
.Q(WR_PNTR_RD[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[6]),
.Q(WR_PNTR_RD[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[7]),
.Q(WR_PNTR_RD[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[8]),
.Q(WR_PNTR_RD[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[9]),
.Q(WR_PNTR_RD[9]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(I1[0]),
.I1(I1[1]),
.O(p_0_in10_out[0]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[10]_i_1
(.I0(I1[10]),
.I1(I1[11]),
.O(p_0_in10_out[10]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(I1[1]),
.I1(I1[2]),
.O(p_0_in10_out[1]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(I1[2]),
.I1(I1[3]),
.O(p_0_in10_out[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(I1[3]),
.I1(I1[4]),
.O(p_0_in10_out[3]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[4]_i_1
(.I0(I1[4]),
.I1(I1[5]),
.O(p_0_in10_out[4]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[5]_i_1
(.I0(I1[5]),
.I1(I1[6]),
.O(p_0_in10_out[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[6]_i_1
(.I0(I1[6]),
.I1(I1[7]),
.O(p_0_in10_out[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[7]_i_1
(.I0(I1[7]),
.I1(I1[8]),
.O(p_0_in10_out[7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[8]_i_1
(.I0(I1[8]),
.I1(I1[9]),
.O(p_0_in10_out[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[9]_i_1
(.I0(I1[9]),
.I1(I1[10]),
.O(p_0_in10_out[9]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[10]),
.Q(wr_pntr_gc[10]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[11]),
.Q(wr_pntr_gc[11]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[9]),
.Q(wr_pntr_gc[9]));
endmodule |
module fifo_64in_out_compare
(comp1,
Q,
RD_PNTR_WR);
output comp1;
input [11:0]Q;
input [11:0]RD_PNTR_WR;
wire [11:0]Q;
wire [11:0]RD_PNTR_WR;
wire comp1;
wire \n_0_gmux.gm[3].gms.ms ;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(Q[0]),
.I1(RD_PNTR_WR[0]),
.I2(Q[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(Q[2]),
.I1(RD_PNTR_WR[2]),
.I2(Q[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(Q[4]),
.I1(RD_PNTR_WR[4]),
.I2(Q[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(Q[6]),
.I1(RD_PNTR_WR[6]),
.I2(Q[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(RD_PNTR_WR[8]),
.I2(Q[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(Q[10]),
.I1(RD_PNTR_WR[10]),
.I2(Q[11]),
.I3(RD_PNTR_WR[11]),
.O(v1_reg[5]));
endmodule |
module fifo_64in_out_compare_0
(comp2,
out,
RD_PNTR_WR);
output comp2;
input [11:0]out;
input [11:0]RD_PNTR_WR;
wire [11:0]RD_PNTR_WR;
wire comp2;
wire \n_0_gmux.gm[3].gms.ms ;
wire [11:0]out;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(out[0]),
.I1(RD_PNTR_WR[0]),
.I2(out[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(out[2]),
.I1(RD_PNTR_WR[2]),
.I2(out[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(out[4]),
.I1(RD_PNTR_WR[4]),
.I2(out[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(out[6]),
.I1(RD_PNTR_WR[6]),
.I2(out[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp2,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(out[8]),
.I1(RD_PNTR_WR[8]),
.I2(out[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(out[10]),
.I1(RD_PNTR_WR[10]),
.I2(out[11]),
.I3(RD_PNTR_WR[11]),
.O(v1_reg[5]));
endmodule |
module fifo_64in_out_compare_1
(comp0,
WR_PNTR_RD,
I1);
output comp0;
input [11:0]WR_PNTR_RD;
input [11:0]I1;
wire [11:0]I1;
wire [11:0]WR_PNTR_RD;
wire comp0;
wire \n_0_gmux.gm[3].gms.ms ;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(WR_PNTR_RD[0]),
.I1(I1[0]),
.I2(WR_PNTR_RD[1]),
.I3(I1[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(WR_PNTR_RD[2]),
.I1(I1[2]),
.I2(WR_PNTR_RD[3]),
.I3(I1[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(WR_PNTR_RD[4]),
.I1(I1[4]),
.I2(WR_PNTR_RD[5]),
.I3(I1[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(WR_PNTR_RD[6]),
.I1(I1[6]),
.I2(WR_PNTR_RD[7]),
.I3(I1[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(WR_PNTR_RD[8]),
.I1(I1[8]),
.I2(WR_PNTR_RD[9]),
.I3(I1[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(WR_PNTR_RD[10]),
.I1(I1[10]),
.I2(WR_PNTR_RD[11]),
.I3(I1[11]),
.O(v1_reg[5]));
endmodule |
module fifo_64in_out_compare_2
(comp1,
WR_PNTR_RD,
out);
output comp1;
input [11:0]WR_PNTR_RD;
input [11:0]out;
wire [11:0]WR_PNTR_RD;
wire comp1;
wire \n_0_gmux.gm[3].gms.ms ;
wire [11:0]out;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(WR_PNTR_RD[0]),
.I1(out[0]),
.I2(WR_PNTR_RD[1]),
.I3(out[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(WR_PNTR_RD[2]),
.I1(out[2]),
.I2(WR_PNTR_RD[3]),
.I3(out[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(WR_PNTR_RD[4]),
.I1(out[4]),
.I2(WR_PNTR_RD[5]),
.I3(out[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(WR_PNTR_RD[6]),
.I1(out[6]),
.I2(WR_PNTR_RD[7]),
.I3(out[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(WR_PNTR_RD[8]),
.I1(out[8]),
.I2(WR_PNTR_RD[9]),
.I3(out[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(WR_PNTR_RD[10]),
.I1(out[10]),
.I2(WR_PNTR_RD[11]),
.I3(out[11]),
.O(v1_reg[5]));
endmodule |
module fifo_64in_out_fifo_generator_ramfifo
(empty,
dout,
valid,
full,
rd_data_count,
rd_en,
wr_en,
wr_clk,
rd_clk,
din,
rst);
output empty;
output [63:0]dout;
output valid;
output full;
output [11:0]rd_data_count;
input rd_en;
input wr_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
wire RD_RST;
wire RST;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire \n_0_gntv_or_sync_fifo.gcx.clkx ;
wire \n_16_gntv_or_sync_fifo.gcx.clkx ;
wire \n_17_gntv_or_sync_fifo.gcx.clkx ;
wire \n_18_gntv_or_sync_fifo.gcx.clkx ;
wire \n_19_gntv_or_sync_fifo.gcx.clkx ;
wire \n_1_gntv_or_sync_fifo.gcx.clkx ;
wire \n_1_gntv_or_sync_fifo.gl0.wr ;
wire \n_20_gntv_or_sync_fifo.gcx.clkx ;
wire \n_21_gntv_or_sync_fifo.gcx.clkx ;
wire \n_22_gntv_or_sync_fifo.gcx.clkx ;
wire \n_23_gntv_or_sync_fifo.gcx.clkx ;
wire \n_2_gntv_or_sync_fifo.gcx.clkx ;
wire \n_3_gntv_or_sync_fifo.gcx.clkx ;
wire [11:0]p_0_out;
wire p_18_out;
wire [11:0]p_1_out;
wire [11:0]p_20_out;
wire [11:0]p_9_out;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire [1:0]rd_rst_i;
wire rst;
wire rst_d2;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire valid;
wire wr_clk;
wire wr_en;
wire [0:0]wr_rst_i;
fifo_64in_out_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.I1(p_9_out),
.I2(wr_rst_i),
.I3(rd_rst_i[1]),
.O1({\n_16_gntv_or_sync_fifo.gcx.clkx ,\n_17_gntv_or_sync_fifo.gcx.clkx ,\n_18_gntv_or_sync_fifo.gcx.clkx ,\n_19_gntv_or_sync_fifo.gcx.clkx }),
.O2({\n_20_gntv_or_sync_fifo.gcx.clkx ,\n_21_gntv_or_sync_fifo.gcx.clkx ,\n_22_gntv_or_sync_fifo.gcx.clkx ,\n_23_gntv_or_sync_fifo.gcx.clkx }),
.Q(p_20_out),
.RD_PNTR_WR(p_0_out),
.S({\n_0_gntv_or_sync_fifo.gcx.clkx ,\n_1_gntv_or_sync_fifo.gcx.clkx ,\n_2_gntv_or_sync_fifo.gcx.clkx ,\n_3_gntv_or_sync_fifo.gcx.clkx }),
.WR_PNTR_RD(p_1_out),
.rd_clk(rd_clk),
.wr_clk(wr_clk));
fifo_64in_out_rd_logic \gntv_or_sync_fifo.gl0.rd
(.I1({\n_16_gntv_or_sync_fifo.gcx.clkx ,\n_17_gntv_or_sync_fifo.gcx.clkx ,\n_18_gntv_or_sync_fifo.gcx.clkx ,\n_19_gntv_or_sync_fifo.gcx.clkx }),
.O1(p_20_out),
.O2({\n_20_gntv_or_sync_fifo.gcx.clkx ,\n_21_gntv_or_sync_fifo.gcx.clkx ,\n_22_gntv_or_sync_fifo.gcx.clkx ,\n_23_gntv_or_sync_fifo.gcx.clkx }),
.Q(RD_RST),
.S({\n_0_gntv_or_sync_fifo.gcx.clkx ,\n_1_gntv_or_sync_fifo.gcx.clkx ,\n_2_gntv_or_sync_fifo.gcx.clkx ,\n_3_gntv_or_sync_fifo.gcx.clkx }),
.WR_PNTR_RD(p_1_out),
.empty(empty),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.valid(valid));
fifo_64in_out_wr_logic \gntv_or_sync_fifo.gl0.wr
(.O1(\n_1_gntv_or_sync_fifo.gl0.wr ),
.O2(p_9_out),
.Q(RST),
.RD_PNTR_WR(p_0_out),
.full(full),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.wr_clk(wr_clk),
.wr_en(wr_en));
fifo_64in_out_memory \gntv_or_sync_fifo.mem
(.I1(\n_1_gntv_or_sync_fifo.gl0.wr ),
.O1(p_20_out),
.O2(p_9_out),
.Q(rd_rst_i[0]),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_reset_blk_ramfifo rstblk
(.O1({RST,wr_rst_i}),
.Q({RD_RST,rd_rst_i}),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_fifo_generator_top
(empty,
dout,
valid,
full,
rd_data_count,
rd_en,
wr_en,
wr_clk,
rd_clk,
din,
rst);
output empty;
output [63:0]dout;
output valid;
output full;
output [11:0]rd_data_count;
input rd_en;
input wr_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire rst;
wire valid;
wire wr_clk;
wire wr_en;
fifo_64in_out_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.valid(valid),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule |
module fifo_64in_out_fifo_generator_v12_0__parameterized0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [11:0]prog_empty_thresh;
input [11:0]prog_empty_thresh_assert;
input [11:0]prog_empty_thresh_negate;
input [11:0]prog_full_thresh;
input [11:0]prog_full_thresh_assert;
input [11:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [11:0]data_count;
output [11:0]rd_data_count;
output [11:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [11:0]prog_empty_thresh;
wire [11:0]prog_empty_thresh_assert;
wire [11:0]prog_empty_thresh_negate;
wire [11:0]prog_full_thresh;
wire [11:0]prog_full_thresh_assert;
wire [11:0]prog_full_thresh_negate;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire valid;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[11] = \<const0> ;
assign data_count[10] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[11] = \<const0> ;
assign wr_data_count[10] = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
fifo_64in_out_fifo_generator_v12_0_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.valid(valid),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule |
module fifo_64in_out_fifo_generator_v12_0_synth
(empty,
dout,
valid,
full,
rd_data_count,
rd_en,
wr_en,
wr_clk,
rd_clk,
din,
rst);
output empty;
output [63:0]dout;
output valid;
output full;
output [11:0]rd_data_count;
input rd_en;
input wr_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire rst;
wire valid;
wire wr_clk;
wire wr_en;
fifo_64in_out_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.valid(valid),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule |
module fifo_64in_out_memory
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_v8_2__parameterized0 \gbm.gbmg.gbmga.ngecc.bmg
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_rd_bin_cntr
(out,
O1,
E,
rd_clk,
Q);
output [11:0]out;
output [11:0]O1;
input [0:0]E;
input rd_clk;
input [0:0]Q;
wire [0:0]E;
wire [11:0]O1;
wire [0:0]Q;
wire \n_0_gc0.count[0]_i_2 ;
wire \n_0_gc0.count_reg[0]_i_1 ;
wire \n_0_gc0.count_reg[10]_i_1 ;
wire \n_0_gc0.count_reg[10]_i_2 ;
wire \n_0_gc0.count_reg[11]_i_1 ;
wire \n_0_gc0.count_reg[1]_i_1 ;
wire \n_0_gc0.count_reg[1]_i_2 ;
wire \n_0_gc0.count_reg[2]_i_1 ;
wire \n_0_gc0.count_reg[2]_i_2 ;
wire \n_0_gc0.count_reg[3]_i_1 ;
wire \n_0_gc0.count_reg[3]_i_2 ;
wire \n_0_gc0.count_reg[4]_i_1 ;
wire \n_0_gc0.count_reg[4]_i_2 ;
wire \n_0_gc0.count_reg[5]_i_1 ;
wire \n_0_gc0.count_reg[5]_i_2 ;
wire \n_0_gc0.count_reg[6]_i_1 ;
wire \n_0_gc0.count_reg[6]_i_2 ;
wire \n_0_gc0.count_reg[7]_i_1 ;
wire \n_0_gc0.count_reg[7]_i_2 ;
wire \n_0_gc0.count_reg[8]_i_1 ;
wire \n_0_gc0.count_reg[8]_i_2 ;
wire \n_0_gc0.count_reg[9]_i_1 ;
wire \n_0_gc0.count_reg[9]_i_2 ;
wire [11:0]out;
wire rd_clk;
wire [3:2]\NLW_gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_2
(.I0(out[0]),
.O(\n_0_gc0.count[0]_i_2 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[0]),
.Q(O1[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[10]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[10]),
.Q(O1[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[11]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[11]),
.Q(O1[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[1]),
.Q(O1[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[2]),
.Q(O1[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[3]),
.Q(O1[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[4]),
.Q(O1[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[5]),
.Q(O1[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[6]),
.Q(O1[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[7]),
.Q(O1[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[8]),
.Q(O1[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[9]),
.Q(O1[9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(\n_0_gc0.count_reg[0]_i_1 ),
.PRE(Q),
.Q(out[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[10]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[10]_i_1 ),
.Q(out[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[11]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[11]_i_1 ),
.Q(out[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[1]_i_1 ),
.Q(out[1]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gc0.count_reg[1]_i_2_CARRY4
(.CI(1'b0),
.CO({\n_0_gc0.count_reg[4]_i_2 ,\n_0_gc0.count_reg[3]_i_2 ,\n_0_gc0.count_reg[2]_i_2 ,\n_0_gc0.count_reg[1]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\n_0_gc0.count_reg[3]_i_1 ,\n_0_gc0.count_reg[2]_i_1 ,\n_0_gc0.count_reg[1]_i_1 ,\n_0_gc0.count_reg[0]_i_1 }),
.S({out[3:1],\n_0_gc0.count[0]_i_2 }));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[2]_i_1 ),
.Q(out[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[3]_i_1 ),
.Q(out[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[4]_i_1 ),
.Q(out[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[5]_i_1 ),
.Q(out[5]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gc0.count_reg[5]_i_2_CARRY4
(.CI(\n_0_gc0.count_reg[4]_i_2 ),
.CO({\n_0_gc0.count_reg[8]_i_2 ,\n_0_gc0.count_reg[7]_i_2 ,\n_0_gc0.count_reg[6]_i_2 ,\n_0_gc0.count_reg[5]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\n_0_gc0.count_reg[7]_i_1 ,\n_0_gc0.count_reg[6]_i_1 ,\n_0_gc0.count_reg[5]_i_1 ,\n_0_gc0.count_reg[4]_i_1 }),
.S(out[7:4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[6]_i_1 ),
.Q(out[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[7]_i_1 ),
.Q(out[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[8]_i_1 ),
.Q(out[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[9]_i_1 ),
.Q(out[9]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gc0.count_reg[9]_i_2_CARRY4
(.CI(\n_0_gc0.count_reg[8]_i_2 ),
.CO({\NLW_gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED [3:2],\n_0_gc0.count_reg[10]_i_2 ,\n_0_gc0.count_reg[9]_i_2 }),
.CYINIT(1'b0),
.DI({\NLW_gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}),
.O({\n_0_gc0.count_reg[11]_i_1 ,\n_0_gc0.count_reg[10]_i_1 ,\n_0_gc0.count_reg[9]_i_1 ,\n_0_gc0.count_reg[8]_i_1 }),
.S(out[11:8]));
endmodule |
module fifo_64in_out_rd_dc_as
(rd_data_count,
rd_clk,
Q,
WR_PNTR_RD,
S,
I1,
O2);
output [11:0]rd_data_count;
input rd_clk;
input [0:0]Q;
input [10:0]WR_PNTR_RD;
input [3:0]S;
input [3:0]I1;
input [3:0]O2;
wire [3:0]I1;
wire [3:0]O2;
wire [0:0]Q;
wire [3:0]S;
wire [10:0]WR_PNTR_RD;
wire [11:0]minusOp;
wire \n_0_rd_dc_i_reg[3]_i_1 ;
wire \n_0_rd_dc_i_reg[7]_i_1 ;
wire \n_1_rd_dc_i_reg[11]_i_1 ;
wire \n_1_rd_dc_i_reg[3]_i_1 ;
wire \n_1_rd_dc_i_reg[7]_i_1 ;
wire \n_2_rd_dc_i_reg[11]_i_1 ;
wire \n_2_rd_dc_i_reg[3]_i_1 ;
wire \n_2_rd_dc_i_reg[7]_i_1 ;
wire \n_3_rd_dc_i_reg[11]_i_1 ;
wire \n_3_rd_dc_i_reg[3]_i_1 ;
wire \n_3_rd_dc_i_reg[7]_i_1 ;
wire rd_clk;
wire [11:0]rd_data_count;
wire [3:3]\NLW_rd_dc_i_reg[11]_i_1_CO_UNCONNECTED ;
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[0]),
.Q(rd_data_count[0]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[10]),
.Q(rd_data_count[10]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[11]),
.Q(rd_data_count[11]));
CARRY4 \rd_dc_i_reg[11]_i_1
(.CI(\n_0_rd_dc_i_reg[7]_i_1 ),
.CO({\NLW_rd_dc_i_reg[11]_i_1_CO_UNCONNECTED [3],\n_1_rd_dc_i_reg[11]_i_1 ,\n_2_rd_dc_i_reg[11]_i_1 ,\n_3_rd_dc_i_reg[11]_i_1 }),
.CYINIT(1'b0),
.DI({1'b0,WR_PNTR_RD[10:8]}),
.O(minusOp[11:8]),
.S(O2));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[1]),
.Q(rd_data_count[1]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[2]),
.Q(rd_data_count[2]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[3]),
.Q(rd_data_count[3]));
CARRY4 \rd_dc_i_reg[3]_i_1
(.CI(1'b0),
.CO({\n_0_rd_dc_i_reg[3]_i_1 ,\n_1_rd_dc_i_reg[3]_i_1 ,\n_2_rd_dc_i_reg[3]_i_1 ,\n_3_rd_dc_i_reg[3]_i_1 }),
.CYINIT(1'b1),
.DI(WR_PNTR_RD[3:0]),
.O(minusOp[3:0]),
.S(S));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[4]),
.Q(rd_data_count[4]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[5]),
.Q(rd_data_count[5]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[6]),
.Q(rd_data_count[6]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[7]),
.Q(rd_data_count[7]));
CARRY4 \rd_dc_i_reg[7]_i_1
(.CI(\n_0_rd_dc_i_reg[3]_i_1 ),
.CO({\n_0_rd_dc_i_reg[7]_i_1 ,\n_1_rd_dc_i_reg[7]_i_1 ,\n_2_rd_dc_i_reg[7]_i_1 ,\n_3_rd_dc_i_reg[7]_i_1 }),
.CYINIT(1'b0),
.DI(WR_PNTR_RD[7:4]),
.O(minusOp[7:4]),
.S(I1));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[8]),
.Q(rd_data_count[8]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[9]),
.Q(rd_data_count[9]));
endmodule |
module fifo_64in_out_rd_handshaking_flags
(valid,
I1,
rd_clk,
Q);
output valid;
input I1;
input rd_clk;
input [0:0]Q;
wire I1;
wire [0:0]Q;
wire rd_clk;
wire valid;
FDCE #(
.INIT(1'b0))
\gv.ram_valid_d1_reg
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(I1),
.Q(valid));
endmodule |
module fifo_64in_out_rd_logic
(empty,
p_18_out,
valid,
O1,
rd_data_count,
rd_clk,
Q,
rd_en,
WR_PNTR_RD,
S,
I1,
O2);
output empty;
output p_18_out;
output valid;
output [11:0]O1;
output [11:0]rd_data_count;
input rd_clk;
input [0:0]Q;
input rd_en;
input [11:0]WR_PNTR_RD;
input [3:0]S;
input [3:0]I1;
input [3:0]O2;
wire [3:0]I1;
wire [11:0]O1;
wire [3:0]O2;
wire [0:0]Q;
wire [3:0]S;
wire [11:0]WR_PNTR_RD;
wire empty;
wire \n_2_gras.rsts ;
wire \n_3_gras.rsts ;
wire p_18_out;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire [11:0]rd_pntr_plus1;
wire valid;
fifo_64in_out_rd_dc_as \gras.grdc1.rdc
(.I1(I1),
.O2(O2),
.Q(Q),
.S(S),
.WR_PNTR_RD(WR_PNTR_RD[10:0]),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count));
fifo_64in_out_rd_status_flags_as \gras.rsts
(.E(\n_2_gras.rsts ),
.I1(O1),
.O1(\n_3_gras.rsts ),
.Q(Q),
.WR_PNTR_RD(WR_PNTR_RD),
.empty(empty),
.out(rd_pntr_plus1),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en));
fifo_64in_out_rd_handshaking_flags \grhf.rhf
(.I1(\n_3_gras.rsts ),
.Q(Q),
.rd_clk(rd_clk),
.valid(valid));
fifo_64in_out_rd_bin_cntr rpntr
(.E(\n_2_gras.rsts ),
.O1(O1),
.Q(Q),
.out(rd_pntr_plus1),
.rd_clk(rd_clk));
endmodule |
module fifo_64in_out_rd_status_flags_as
(empty,
p_18_out,
E,
O1,
rd_clk,
Q,
rd_en,
WR_PNTR_RD,
I1,
out);
output empty;
output p_18_out;
output [0:0]E;
output O1;
input rd_clk;
input [0:0]Q;
input rd_en;
input [11:0]WR_PNTR_RD;
input [11:0]I1;
input [11:0]out;
wire [0:0]E;
wire [11:0]I1;
wire O1;
wire [0:0]Q;
wire [11:0]WR_PNTR_RD;
wire comp0;
wire comp1;
wire empty;
wire n_0_ram_empty_i_i_1;
wire [11:0]out;
wire p_18_out;
wire rd_clk;
wire rd_en;
fifo_64in_out_compare_1 c0
(.I1(I1),
.WR_PNTR_RD(WR_PNTR_RD),
.comp0(comp0));
fifo_64in_out_compare_2 c1
(.WR_PNTR_RD(WR_PNTR_RD),
.comp1(comp1),
.out(out));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[11]_i_1
(.I0(rd_en),
.I1(p_18_out),
.O(E));
LUT2 #(
.INIT(4'h2))
\gv.ram_valid_d1_i_1
(.I0(rd_en),
.I1(empty),
.O(O1));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(n_0_ram_empty_i_i_1),
.PRE(Q),
.Q(p_18_out));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hAEAA))
ram_empty_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(p_18_out),
.I3(comp1),
.O(n_0_ram_empty_i_i_1));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(n_0_ram_empty_i_i_1),
.PRE(Q),
.Q(empty));
endmodule |
module fifo_64in_out_reset_blk_ramfifo
(rst_d2,
rst_full_gen_i,
tmp_ram_rd_en,
Q,
O1,
wr_clk,
rst,
rd_clk,
p_18_out,
rd_en);
output rst_d2;
output rst_full_gen_i;
output tmp_ram_rd_en;
output [2:0]Q;
output [1:0]O1;
input wr_clk;
input rst;
input rd_clk;
input p_18_out;
input rd_en;
wire [1:0]O1;
wire [2:0]Q;
wire \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ;
wire \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
wire rst;
wire rst_d1;
wire rst_d2;
wire rst_d3;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(Q[0]),
.I1(p_18_out),
.I2(rd_en),
.O(tmp_ram_rd_en));
FDCE #(
.INIT(1'b0))
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(rst),
.D(rst_d3),
.Q(rst_full_gen_i));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(rd_rst_asreg_d1),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg_d1),
.Q(rd_rst_asreg_d2),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(rd_rst_asreg_d1),
.D(1'b0),
.PRE(rst),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[1]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[2]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(wr_rst_asreg_d1),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg_d1),
.Q(wr_rst_asreg_d2),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(wr_rst_asreg_d1),
.D(1'b0),
.PRE(rst),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ),
.Q(O1[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ),
.Q(O1[1]));
endmodule |
module fifo_64in_out_synchronizer_ff
(Q,
I1,
rd_clk,
I3);
output [11:0]Q;
input [11:0]I1;
input rd_clk;
input [0:0]I3;
wire [11:0]I1;
wire [0:0]I3;
wire [11:0]Q;
wire rd_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[0]),
.Q(Q[0]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[10]),
.Q(Q[10]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[11]),
.Q(Q[11]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[1]),
.Q(Q[1]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[2]),
.Q(Q[2]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[3]),
.Q(Q[3]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[4]),
.Q(Q[4]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[5]),
.Q(Q[5]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[6]),
.Q(Q[6]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[7]),
.Q(Q[7]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[8]),
.Q(Q[8]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[9]),
.Q(Q[9]));
endmodule |
module fifo_64in_out_synchronizer_ff_3
(Q,
I1,
wr_clk,
I2);
output [11:0]Q;
input [11:0]I1;
input wr_clk;
input [0:0]I2;
wire [11:0]I1;
wire [0:0]I2;
wire [11:0]Q;
wire wr_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[0]),
.Q(Q[0]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[10]),
.Q(Q[10]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[11]),
.Q(Q[11]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[1]),
.Q(Q[1]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[2]),
.Q(Q[2]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[3]),
.Q(Q[3]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[4]),
.Q(Q[4]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[5]),
.Q(Q[5]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[6]),
.Q(Q[6]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[7]),
.Q(Q[7]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[8]),
.Q(Q[8]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[9]),
.Q(Q[9]));
endmodule |
module fifo_64in_out_synchronizer_ff_4
(p_0_in,
D,
rd_clk,
I3);
output [11:0]p_0_in;
input [11:0]D;
input rd_clk;
input [0:0]I3;
wire [11:0]D;
wire [0:0]I3;
wire \n_0_Q_reg_reg[0] ;
wire \n_0_Q_reg_reg[10] ;
wire \n_0_Q_reg_reg[1] ;
wire \n_0_Q_reg_reg[2] ;
wire \n_0_Q_reg_reg[3] ;
wire \n_0_Q_reg_reg[4] ;
wire \n_0_Q_reg_reg[5] ;
wire \n_0_Q_reg_reg[6] ;
wire \n_0_Q_reg_reg[7] ;
wire \n_0_Q_reg_reg[8] ;
wire \n_0_Q_reg_reg[9] ;
wire [11:0]p_0_in;
wire rd_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[0]),
.Q(\n_0_Q_reg_reg[0] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[10]),
.Q(\n_0_Q_reg_reg[10] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[11]),
.Q(p_0_in[11]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[1]),
.Q(\n_0_Q_reg_reg[1] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[2]),
.Q(\n_0_Q_reg_reg[2] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[3]),
.Q(\n_0_Q_reg_reg[3] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[4]),
.Q(\n_0_Q_reg_reg[4] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[5]),
.Q(\n_0_Q_reg_reg[5] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[6]),
.Q(\n_0_Q_reg_reg[6] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[7]),
.Q(\n_0_Q_reg_reg[7] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[8]),
.Q(\n_0_Q_reg_reg[8] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[9]),
.Q(\n_0_Q_reg_reg[9] ));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[0]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[0] ),
.I3(p_0_in[3]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[10]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(p_0_in[11]),
.O(p_0_in[10]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[1]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[3] ),
.I3(\n_0_Q_reg_reg[5] ),
.I4(p_0_in[6]),
.I5(\n_0_Q_reg_reg[4] ),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[2]_i_1
(.I0(\n_0_Q_reg_reg[3] ),
.I1(\n_0_Q_reg_reg[5] ),
.I2(p_0_in[6]),
.I3(\n_0_Q_reg_reg[4] ),
.I4(\n_0_Q_reg_reg[2] ),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[3]_i_1
(.I0(\n_0_Q_reg_reg[4] ),
.I1(p_0_in[6]),
.I2(\n_0_Q_reg_reg[5] ),
.I3(\n_0_Q_reg_reg[3] ),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[4]_i_1
(.I0(\n_0_Q_reg_reg[5] ),
.I1(p_0_in[6]),
.I2(\n_0_Q_reg_reg[4] ),
.O(p_0_in[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[5]_i_1
(.I0(p_0_in[6]),
.I1(\n_0_Q_reg_reg[5] ),
.O(p_0_in[5]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[6]_i_1
(.I0(\n_0_Q_reg_reg[7] ),
.I1(p_0_in[11]),
.I2(\n_0_Q_reg_reg[9] ),
.I3(\n_0_Q_reg_reg[10] ),
.I4(\n_0_Q_reg_reg[8] ),
.I5(\n_0_Q_reg_reg[6] ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[7]_i_1
(.I0(\n_0_Q_reg_reg[8] ),
.I1(\n_0_Q_reg_reg[10] ),
.I2(\n_0_Q_reg_reg[9] ),
.I3(p_0_in[11]),
.I4(\n_0_Q_reg_reg[7] ),
.O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[8]_i_1
(.I0(p_0_in[11]),
.I1(\n_0_Q_reg_reg[9] ),
.I2(\n_0_Q_reg_reg[10] ),
.I3(\n_0_Q_reg_reg[8] ),
.O(p_0_in[8]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[9]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(\n_0_Q_reg_reg[9] ),
.I2(p_0_in[11]),
.O(p_0_in[9]));
endmodule |
module fifo_64in_out_synchronizer_ff_5
(Q,
O1,
D,
wr_clk,
I2);
output [0:0]Q;
output [10:0]O1;
input [11:0]D;
input wr_clk;
input [0:0]I2;
wire [11:0]D;
wire [0:0]I2;
wire [10:0]O1;
wire [0:0]Q;
wire \n_0_Q_reg_reg[0] ;
wire \n_0_Q_reg_reg[10] ;
wire \n_0_Q_reg_reg[1] ;
wire \n_0_Q_reg_reg[2] ;
wire \n_0_Q_reg_reg[3] ;
wire \n_0_Q_reg_reg[4] ;
wire \n_0_Q_reg_reg[5] ;
wire \n_0_Q_reg_reg[6] ;
wire \n_0_Q_reg_reg[7] ;
wire \n_0_Q_reg_reg[8] ;
wire \n_0_Q_reg_reg[9] ;
wire wr_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[0]),
.Q(\n_0_Q_reg_reg[0] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[10]),
.Q(\n_0_Q_reg_reg[10] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[11]),
.Q(Q));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[1]),
.Q(\n_0_Q_reg_reg[1] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[2]),
.Q(\n_0_Q_reg_reg[2] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[3]),
.Q(\n_0_Q_reg_reg[3] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[4]),
.Q(\n_0_Q_reg_reg[4] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[5]),
.Q(\n_0_Q_reg_reg[5] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[6]),
.Q(\n_0_Q_reg_reg[6] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[7]),
.Q(\n_0_Q_reg_reg[7] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[8]),
.Q(\n_0_Q_reg_reg[8] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[9]),
.Q(\n_0_Q_reg_reg[9] ));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[0]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[0] ),
.I3(O1[3]),
.O(O1[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[10]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(Q),
.O(O1[10]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[1]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[3] ),
.I3(\n_0_Q_reg_reg[5] ),
.I4(O1[6]),
.I5(\n_0_Q_reg_reg[4] ),
.O(O1[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[2]_i_1
(.I0(\n_0_Q_reg_reg[3] ),
.I1(\n_0_Q_reg_reg[5] ),
.I2(O1[6]),
.I3(\n_0_Q_reg_reg[4] ),
.I4(\n_0_Q_reg_reg[2] ),
.O(O1[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[3]_i_1
(.I0(\n_0_Q_reg_reg[4] ),
.I1(O1[6]),
.I2(\n_0_Q_reg_reg[5] ),
.I3(\n_0_Q_reg_reg[3] ),
.O(O1[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[4]_i_1
(.I0(\n_0_Q_reg_reg[5] ),
.I1(O1[6]),
.I2(\n_0_Q_reg_reg[4] ),
.O(O1[4]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[5]_i_1
(.I0(O1[6]),
.I1(\n_0_Q_reg_reg[5] ),
.O(O1[5]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[6]_i_1
(.I0(\n_0_Q_reg_reg[7] ),
.I1(Q),
.I2(\n_0_Q_reg_reg[9] ),
.I3(\n_0_Q_reg_reg[10] ),
.I4(\n_0_Q_reg_reg[8] ),
.I5(\n_0_Q_reg_reg[6] ),
.O(O1[6]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[7]_i_1
(.I0(\n_0_Q_reg_reg[8] ),
.I1(\n_0_Q_reg_reg[10] ),
.I2(\n_0_Q_reg_reg[9] ),
.I3(Q),
.I4(\n_0_Q_reg_reg[7] ),
.O(O1[7]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[8]_i_1
(.I0(Q),
.I1(\n_0_Q_reg_reg[9] ),
.I2(\n_0_Q_reg_reg[10] ),
.I3(\n_0_Q_reg_reg[8] ),
.O(O1[8]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[9]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(\n_0_Q_reg_reg[9] ),
.I2(Q),
.O(O1[9]));
endmodule |
module fifo_64in_out_wr_bin_cntr
(out,
Q,
O2,
sel,
wr_clk,
I1);
output [11:0]out;
output [11:0]Q;
output [11:0]O2;
input sel;
input wr_clk;
input [0:0]I1;
wire [0:0]I1;
wire [11:0]O2;
wire [11:0]Q;
wire \n_0_gic0.gc0.count[0]_i_2 ;
wire \n_0_gic0.gc0.count_reg[0]_i_1 ;
wire \n_0_gic0.gc0.count_reg[10]_i_1 ;
wire \n_0_gic0.gc0.count_reg[10]_i_2 ;
wire \n_0_gic0.gc0.count_reg[11]_i_1 ;
wire \n_0_gic0.gc0.count_reg[1]_i_1 ;
wire \n_0_gic0.gc0.count_reg[1]_i_2 ;
wire \n_0_gic0.gc0.count_reg[2]_i_1 ;
wire \n_0_gic0.gc0.count_reg[2]_i_2 ;
wire \n_0_gic0.gc0.count_reg[3]_i_1 ;
wire \n_0_gic0.gc0.count_reg[3]_i_2 ;
wire \n_0_gic0.gc0.count_reg[4]_i_1 ;
wire \n_0_gic0.gc0.count_reg[4]_i_2 ;
wire \n_0_gic0.gc0.count_reg[5]_i_1 ;
wire \n_0_gic0.gc0.count_reg[5]_i_2 ;
wire \n_0_gic0.gc0.count_reg[6]_i_1 ;
wire \n_0_gic0.gc0.count_reg[6]_i_2 ;
wire \n_0_gic0.gc0.count_reg[7]_i_1 ;
wire \n_0_gic0.gc0.count_reg[7]_i_2 ;
wire \n_0_gic0.gc0.count_reg[8]_i_1 ;
wire \n_0_gic0.gc0.count_reg[8]_i_2 ;
wire \n_0_gic0.gc0.count_reg[9]_i_1 ;
wire \n_0_gic0.gc0.count_reg[9]_i_2 ;
wire [11:0]out;
wire sel;
wire wr_clk;
wire [3:2]\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_2
(.I0(out[0]),
.O(\n_0_gic0.gc0.count[0]_i_2 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(sel),
.D(out[0]),
.PRE(I1),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[10]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[11]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[9]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[0]),
.Q(O2[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[10]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[10]),
.Q(O2[10]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[11]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[11]),
.Q(O2[11]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[1]),
.Q(O2[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[2]),
.Q(O2[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[3]),
.Q(O2[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[4]),
.Q(O2[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[5]),
.Q(O2[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[6]),
.Q(O2[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[7]),
.Q(O2[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[8]),
.Q(O2[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[9]),
.Q(O2[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[0]_i_1 ),
.Q(out[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[10]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[10]_i_1 ),
.Q(out[10]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[11]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[11]_i_1 ),
.Q(out[11]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(sel),
.D(\n_0_gic0.gc0.count_reg[1]_i_1 ),
.PRE(I1),
.Q(out[1]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gic0.gc0.count_reg[1]_i_2_CARRY4
(.CI(1'b0),
.CO({\n_0_gic0.gc0.count_reg[4]_i_2 ,\n_0_gic0.gc0.count_reg[3]_i_2 ,\n_0_gic0.gc0.count_reg[2]_i_2 ,\n_0_gic0.gc0.count_reg[1]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\n_0_gic0.gc0.count_reg[3]_i_1 ,\n_0_gic0.gc0.count_reg[2]_i_1 ,\n_0_gic0.gc0.count_reg[1]_i_1 ,\n_0_gic0.gc0.count_reg[0]_i_1 }),
.S({out[3:1],\n_0_gic0.gc0.count[0]_i_2 }));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[2]_i_1 ),
.Q(out[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[3]_i_1 ),
.Q(out[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[4]_i_1 ),
.Q(out[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[5]_i_1 ),
.Q(out[5]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gic0.gc0.count_reg[5]_i_2_CARRY4
(.CI(\n_0_gic0.gc0.count_reg[4]_i_2 ),
.CO({\n_0_gic0.gc0.count_reg[8]_i_2 ,\n_0_gic0.gc0.count_reg[7]_i_2 ,\n_0_gic0.gc0.count_reg[6]_i_2 ,\n_0_gic0.gc0.count_reg[5]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\n_0_gic0.gc0.count_reg[7]_i_1 ,\n_0_gic0.gc0.count_reg[6]_i_1 ,\n_0_gic0.gc0.count_reg[5]_i_1 ,\n_0_gic0.gc0.count_reg[4]_i_1 }),
.S(out[7:4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[6]_i_1 ),
.Q(out[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[7]_i_1 ),
.Q(out[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[8]_i_1 ),
.Q(out[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[9]_i_1 ),
.Q(out[9]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gic0.gc0.count_reg[9]_i_2_CARRY4
(.CI(\n_0_gic0.gc0.count_reg[8]_i_2 ),
.CO({\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED [3:2],\n_0_gic0.gc0.count_reg[10]_i_2 ,\n_0_gic0.gc0.count_reg[9]_i_2 }),
.CYINIT(1'b0),
.DI({\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}),
.O({\n_0_gic0.gc0.count_reg[11]_i_1 ,\n_0_gic0.gc0.count_reg[10]_i_1 ,\n_0_gic0.gc0.count_reg[9]_i_1 ,\n_0_gic0.gc0.count_reg[8]_i_1 }),
.S(out[11:8]));
endmodule |
module fifo_64in_out_wr_logic
(full,
O1,
O2,
wr_clk,
rst_d2,
wr_en,
Q,
RD_PNTR_WR,
rst_full_gen_i);
output full;
output O1;
output [11:0]O2;
input wr_clk;
input rst_d2;
input wr_en;
input [0:0]Q;
input [11:0]RD_PNTR_WR;
input rst_full_gen_i;
wire O1;
wire [11:0]O2;
wire [0:0]Q;
wire [11:0]RD_PNTR_WR;
wire full;
wire [11:0]p_8_out;
wire rst_d2;
wire rst_full_gen_i;
wire wr_clk;
wire wr_en;
wire [11:0]wr_pntr_plus2;
fifo_64in_out_wr_status_flags_as \gwas.wsts
(.Q(p_8_out),
.RD_PNTR_WR(RD_PNTR_WR),
.full(full),
.out(wr_pntr_plus2),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.sel(O1),
.wr_clk(wr_clk),
.wr_en(wr_en));
fifo_64in_out_wr_bin_cntr wpntr
(.I1(Q),
.O2(O2),
.Q(p_8_out),
.out(wr_pntr_plus2),
.sel(O1),
.wr_clk(wr_clk));
endmodule |
module fifo_64in_out_wr_status_flags_as
(full,
sel,
wr_clk,
rst_d2,
wr_en,
Q,
RD_PNTR_WR,
out,
rst_full_gen_i);
output full;
output sel;
input wr_clk;
input rst_d2;
input wr_en;
input [11:0]Q;
input [11:0]RD_PNTR_WR;
input [11:0]out;
input rst_full_gen_i;
wire [11:0]Q;
wire [11:0]RD_PNTR_WR;
wire comp1;
wire comp2;
wire full;
wire [11:0]out;
wire p_0_out;
wire ram_full_i;
wire rst_d2;
wire rst_full_gen_i;
wire sel;
wire wr_clk;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(p_0_out),
.O(sel));
fifo_64in_out_compare c1
(.Q(Q),
.RD_PNTR_WR(RD_PNTR_WR),
.comp1(comp1));
fifo_64in_out_compare_0 c2
(.RD_PNTR_WR(RD_PNTR_WR),
.comp2(comp2),
.out(out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_d2),
.Q(p_0_out));
LUT5 #(
.INIT(32'h55550400))
ram_full_i_i_1
(.I0(rst_full_gen_i),
.I1(comp2),
.I2(p_0_out),
.I3(wr_en),
.I4(comp1),
.O(ram_full_i));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_d2),
.Q(full));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module rgb2hsv(
clk,
clk_en,
rst,
RGB,
//xxx,
HSV
);
input clk, rst;
input[31:0] RGB ;//xxx;
output[31:0] HSV;
input clk_en ;
// h ranges from (0, 360] degrees
// s and v ranges from [0,255] hya bet range mn 0-1 bas for calculation han5aleha from 0-255
// h [31:24] , s [23:16], v[15:8]
reg[31:0] HSV ;
reg[7:0] v_delay_final[2:0]; // Delays v so that h, s, v data lines up correctly
reg[19:0] div ;
wire[7:0] diff;
reg[31:0] H_old ;
reg signed [9:0] h_int;//ba7ot feha el value mtzabtah bel shifts bta3tha 3ala 7asb el hue_select value
reg[15:0] sat_dividend, sat_divisor;
reg[15:0] hue_dividend, hue_divisor;
//wire[15:0] sat_remainder, hue_remainder;
wire[15:0] sat_quotient, hue_quotient;
reg[2:0] hue_select; // Used to correctly modify the output of the hue divider
reg[2:0] hue_select_delay; // Accounts for divider delay
wire[7:0] max1 ;
wire[7:0] max;
wire[7:0] min1 ;
wire[7:0] min ;
assign diff = max - min;
assign max1 = (RGB[15:8] > RGB[23:16]) ? RGB[15:8] : RGB[23:16];
assign max = (max1 > RGB[31:24]) ? max1 : RGB[31:24];
assign min1 = (RGB[15:8] < RGB[23:16]) ? RGB[15:8] : RGB[23:16];
assign min = (min1 < RGB[31:24]) ? min1 : RGB[31:24];
always @ (posedge clk )
begin
if(rst == 1'b1)
begin
HSV<=0;
end
else if(clk_en == 1'b1)
begin
HSV[15:8] = max ;
case (HSV[15:8])
8'd0 : div=20'd0;
8'd1 : div=20'd1044480;
8'd2 : div=20'd522240;
8'd3 : div=20'd348160;
8'd4 : div=20'd261120;
8'd5 : div=20'd208896;
8'd6 : div=20'd174080;
8'd7 : div=20'd149211;
8'd8 : div=20'd130560;
8'd9 : div=20'd116053;
8'd10 : div=20'd104448;
8'd11 : div=20'd94953;
8'd12 : div=20'd87040;
8'd13 : div=20'd80345;
8'd14 : div=20'd74606;
8'd15 : div=20'd69632;
8'd16 : div=20'd65280;
8'd17 : div=20'd61440;
8'd18 : div=20'd58027;
8'd19 : div=20'd54973;
8'd20 : div=20'd52224;
8'd21 : div=20'd49737;
8'd22 : div=20'd47476;
8'd23 : div=20'd45412;
8'd24 : div=20'd43520;
8'd25 : div=20'd41779;
8'd26 : div=20'd40172;
8'd27 : div=20'd38684;
8'd28 : div=20'd37303;
8'd29 : div=20'd36017;
8'd30 : div=20'd34816;
8'd31 : div=20'd33693;
8'd32 : div=20'd32640;
8'd33 : div=20'd31651;
8'd34 : div=20'd30720;
8'd35 : div=20'd29842;
8'd36 : div=20'd29013;
8'd37 : div=20'd28229;
8'd38 : div=20'd27486;
8'd39 : div=20'd26782;
8'd40 : div=20'd26112;
8'd41 : div=20'd25475;
8'd42 : div=20'd24869;
8'd43 : div=20'd24290;
8'd44 : div=20'd23738;
8'd45 : div=20'd23211;
8'd46 : div=20'd22706;
8'd47 : div=20'd22223;
8'd48 : div=20'd21760;
8'd49 : div=20'd21316;
8'd50 : div=20'd20890;
8'd51 : div=20'd20480;
8'd52 : div=20'd20086;
8'd53 : div=20'd19707;
8'd54 : div=20'd19342;
8'd55 : div=20'd18991;
8'd56 : div=20'd18651;
8'd57 : div=20'd18324;
8'd58 : div=20'd18008;
8'd59 : div=20'd17703;
8'd60 : div=20'd17408;
8'd61 : div=20'd17123;
8'd62 : div=20'd16846;
8'd63 : div=20'd16579;
8'd64 : div=20'd16320;
8'd65 : div=20'd16069;
8'd66 : div=20'd15825;
8'd67 : div=20'd15589;
8'd68 : div=20'd15360;
8'd69 : div=20'd15137;
8'd70 : div=20'd14921;
8'd71 : div=20'd14711;
8'd72 : div=20'd14507;
8'd73 : div=20'd14308;
8'd74 : div=20'd14115;
8'd75 : div=20'd13926;
8'd76 : div=20'd13743;
8'd77 : div=20'd13565;
8'd78 : div=20'd13391;
8'd79 : div=20'd13221;
8'd80 : div=20'd13056;
8'd81 : div=20'd12895;
8'd82 : div=20'd12738;
8'd83 : div=20'd12584;
8'd84 : div=20'd12434;
8'd85 : div=20'd12288;
8'd86 : div=20'd12145;
8'd87 : div=20'd12006;
8'd88 : div=20'd11869;
8'd89 : div=20'd11736;
8'd90 : div=20'd11605;
8'd91 : div=20'd11478;
8'd92 : div=20'd11353;
8'd93 : div=20'd11231;
8'd94 : div=20'd11111;
8'd95 : div=20'd10995;
8'd96 : div=20'd10880;
8'd97 : div=20'd10768;
8'd98 : div=20'd10658;
8'd99 : div=20'd10550;
8'd100 : div=20'd10445;
8'd101 : div=20'd10341;
8'd102 : div=20'd10240;
8'd103 : div=20'd10141;
8'd104 : div=20'd10043;
8'd105 : div=20'd9947;
8'd106 : div=20'd9854;
8'd107 : div=20'd9761;
8'd108 : div=20'd9671;
8'd109 : div=20'd9582;
8'd110 : div=20'd9495;
8'd111 : div=20'd9410;
8'd112 : div=20'd9326;
8'd113 : div=20'd9243;
8'd114 : div=20'd9162;
8'd115 : div=20'd9082;
8'd116 : div=20'd9004;
8'd117 : div=20'd8927;
8'd118 : div=20'd8852;
8'd119 : div=20'd8777;
8'd120 : div=20'd8704;
8'd121 : div=20'd8632;
8'd122 : div=20'd8561;
8'd123 : div=20'd8492;
8'd124 : div=20'd8423;
8'd125 : div=20'd8356;
8'd126 : div=20'd8290;
8'd127 : div=20'd8224;
8'd128 : div=20'd8160;
8'd129 : div=20'd8097;
8'd130 : div=20'd8034;
8'd131 : div=20'd7973;
8'd132 : div=20'd7913;
8'd133 : div=20'd7853;
8'd134 : div=20'd7795;
8'd135 : div=20'd7737;
8'd136 : div=20'd7680;
8'd137 : div=20'd7624;
8'd138 : div=20'd7569;
8'd139 : div=20'd7514;
8'd140 : div=20'd7461;
8'd141 : div=20'd7408;
8'd142 : div=20'd7355;
8'd143 : div=20'd7304;
8'd144 : div=20'd7253;
8'd145 : div=20'd7203;
8'd146 : div=20'd7154;
8'd147 : div=20'd7105;
8'd148 : div=20'd7057;
8'd149 : div=20'd7010;
8'd150 : div=20'd6963;
8'd151 : div=20'd6917;
8'd152 : div=20'd6872;
8'd153 : div=20'd6827;
8'd154 : div=20'd6782;
8'd155 : div=20'd6739;
8'd156 : div=20'd6695;
8'd157 : div=20'd6653;
8'd158 : div=20'd6611;
8'd159 : div=20'd6569;
8'd160 : div=20'd6528;
8'd161 : div=20'd6487;
8'd162 : div=20'd6447;
8'd163 : div=20'd6408;
8'd164 : div=20'd6369;
8'd165 : div=20'd6330;
8'd166 : div=20'd6292;
8'd167 : div=20'd6254;
8'd168 : div=20'd6217;
8'd169 : div=20'd6180;
8'd170 : div=20'd6144;
8'd171 : div=20'd6108;
8'd172 : div=20'd6073;
8'd173 : div=20'd6037;
8'd174 : div=20'd6003;
8'd175 : div=20'd5968;
8'd176 : div=20'd5935;
8'd177 : div=20'd5901;
8'd178 : div=20'd5868;
8'd179 : div=20'd5835;
8'd180 : div=20'd5803;
8'd181 : div=20'd5771;
8'd182 : div=20'd5739;
8'd183 : div=20'd5708;
8'd184 : div=20'd5677;
8'd185 : div=20'd5646;
8'd186 : div=20'd5615;
8'd187 : div=20'd5585;
8'd188 : div=20'd5556;
8'd189 : div=20'd5526;
8'd190 : div=20'd5497;
8'd191 : div=20'd5468;
8'd192 : div=20'd5440;
8'd193 : div=20'd5412;
8'd194 : div=20'd5384;
8'd195 : div=20'd5356;
8'd196 : div=20'd5329;
8'd197 : div=20'd5302;
8'd198 : div=20'd5275;
8'd199 : div=20'd5249;
8'd200 : div=20'd5222;
8'd201 : div=20'd5196;
8'd202 : div=20'd5171;
8'd203 : div=20'd5145;
8'd204 : div=20'd5120;
8'd205 : div=20'd5095;
8'd206 : div=20'd5070;
8'd207 : div=20'd5046;
8'd208 : div=20'd5022;
8'd209 : div=20'd4998;
8'd210 : div=20'd4974;
8'd211 : div=20'd4950;
8'd212 : div=20'd4927;
8'd213 : div=20'd4904;
8'd214 : div=20'd4881;
8'd215 : div=20'd4858;
8'd216 : div=20'd4836;
8'd217 : div=20'd4813;
8'd218 : div=20'd4791;
8'd219 : div=20'd4769;
8'd220 : div=20'd4748;
8'd221 : div=20'd4726;
8'd222 : div=20'd4705;
8'd223 : div=20'd4684;
8'd224 : div=20'd4663;
8'd225 : div=20'd4642;
8'd226 : div=20'd4622;
8'd227 : div=20'd4601;
8'd228 : div=20'd4581;
8'd229 : div=20'd4561;
8'd230 : div=20'd4541;
8'd231 : div=20'd4522;
8'd232 : div=20'd4502;
8'd233 : div=20'd4483;
8'd234 : div=20'd4464;
8'd235 : div=20'd4445;
8'd236 : div=20'd4426;
8'd237 : div=20'd4407;
8'd238 : div=20'd4389;
8'd239 : div=20'd4370;
8'd240 : div=20'd4352;
8'd241 : div=20'd4334;
8'd242 : div=20'd4316;
8'd243 : div=20'd4298;
8'd244 : div=20'd4281;
8'd245 : div=20'd4263;
8'd246 : div=20'd4246;
8'd247 : div=20'd4229;
8'd248 : div=20'd4212;
8'd249 : div=20'd4195;
8'd250 : div=20'd4178;
8'd251 : div=20'd4161;
8'd252 : div=20'd4145;
8'd253 : div=20'd4128;
8'd254 : div=20'd4112;
8'd255 : div=20'd4096;
endcase
HSV[23:16] = ((diff * div)>>12) ;
case (diff)
8'd0 : H_old=32'd0;
8'd1 : H_old=32'd1044480;
8'd2 : H_old=32'd522240;
8'd3 : H_old=32'd348160;
8'd4 : H_old=32'd261120;
8'd5 : H_old=32'd208896;
8'd6 : H_old=32'd174080;
8'd7 : H_old=32'd149211;
8'd8 : H_old=32'd130560;
8'd9 : H_old=32'd116053;
8'd10 : H_old=32'd104448;
8'd11 : H_old=32'd94953;
8'd12 : H_old=32'd87040;
8'd13 : H_old=32'd80345;
8'd14 : H_old=32'd74606;
8'd15 : H_old=32'd69632;
8'd16 : H_old=32'd65280;
8'd17 : H_old=32'd61440;
8'd18 : H_old=32'd58027;
8'd19 : H_old=32'd54973;
8'd20 : H_old=32'd52224;
8'd21 : H_old=32'd49737;
8'd22 : H_old=32'd47476;
8'd23 : H_old=32'd45412;
8'd24 : H_old=32'd43520;
8'd25 : H_old=32'd41779;
8'd26 : H_old=32'd40172;
8'd27 : H_old=32'd38684;
8'd28 : H_old=32'd37303;
8'd29 : H_old=32'd36017;
8'd30 : H_old=32'd34816;
8'd31 : H_old=32'd33693;
8'd32 : H_old=32'd32640;
8'd33 : H_old=32'd31651;
8'd34 : H_old=32'd30720;
8'd35 : H_old=32'd29842;
8'd36 : H_old=32'd29013;
8'd37 : H_old=32'd28229;
8'd38 : H_old=32'd27486;
8'd39 : H_old=32'd26782;
8'd40 : H_old=32'd26112;
8'd41 : H_old=32'd25475;
8'd42 : H_old=32'd24869;
8'd43 : H_old=32'd24290;
8'd44 : H_old=32'd23738;
8'd45 : H_old=32'd23211;
8'd46 : H_old=32'd22706;
8'd47 : H_old=32'd22223;
8'd48 : H_old=32'd21760;
8'd49 : H_old=32'd21316;
8'd50 : H_old=32'd20890;
8'd51 : H_old=32'd20480;
8'd52 : H_old=32'd20086;
8'd53 : H_old=32'd19707;
8'd54 : H_old=32'd19342;
8'd55 : H_old=32'd18991;
8'd56 : H_old=32'd18651;
8'd57 : H_old=32'd18324;
8'd58 : H_old=32'd18008;
8'd59 : H_old=32'd17703;
8'd60 : H_old=32'd17408;
8'd61 : H_old=32'd17123;
8'd62 : H_old=32'd16846;
8'd63 : H_old=32'd16579;
8'd64 : H_old=32'd16320;
8'd65 : H_old=32'd16069;
8'd66 : H_old=32'd15825;
8'd67 : H_old=32'd15589;
8'd68 : H_old=32'd15360;
8'd69 : H_old=32'd15137;
8'd70 : H_old=32'd14921;
8'd71 : H_old=32'd14711;
8'd72 : H_old=32'd14507;
8'd73 : H_old=32'd14308;
8'd74 : H_old=32'd14115;
8'd75 : H_old=32'd13926;
8'd76 : H_old=32'd13743;
8'd77 : H_old=32'd13565;
8'd78 : H_old=32'd13391;
8'd79 : H_old=32'd13221;
8'd80 : H_old=32'd13056;
8'd81 : H_old=32'd12895;
8'd82 : H_old=32'd12738;
8'd83 : H_old=32'd12584;
8'd84 : H_old=32'd12434;
8'd85 : H_old=32'd12288;
8'd86 : H_old=32'd12145;
8'd87 : H_old=32'd12006;
8'd88 : H_old=32'd11869;
8'd89 : H_old=32'd11736;
8'd90 : H_old=32'd11605;
8'd91 : H_old=32'd11478;
8'd92 : H_old=32'd11353;
8'd93 : H_old=32'd11231;
8'd94 : H_old=32'd11111;
8'd95 : H_old=32'd10995;
8'd96 : H_old=32'd10880;
8'd97 : H_old=32'd10768;
8'd98 : H_old=32'd10658;
8'd99 : H_old=32'd10550;
8'd100 : H_old=32'd10445;
8'd101 : H_old=32'd10341;
8'd102 : H_old=32'd10240;
8'd103 : H_old=32'd10141;
8'd104 : H_old=32'd10043;
8'd105 : H_old=32'd9947;
8'd106 : H_old=32'd9854;
8'd107 : H_old=32'd9761;
8'd108 : H_old=32'd9671;
8'd109 : H_old=32'd9582;
8'd110 : H_old=32'd9495;
8'd111 : H_old=32'd9410;
8'd112 : H_old=32'd9326;
8'd113 : H_old=32'd9243;
8'd114 : H_old=32'd9162;
8'd115 : H_old=32'd9082;
8'd116 : H_old=32'd9004;
8'd117 : H_old=32'd8927;
8'd118 : H_old=32'd8852;
8'd119 : H_old=32'd8777;
8'd120 : H_old=32'd8704;
8'd121 : H_old=32'd8632;
8'd122 : H_old=32'd8561;
8'd123 : H_old=32'd8492;
8'd124 : H_old=32'd8423;
8'd125 : H_old=32'd8356;
8'd126 : H_old=32'd8290;
8'd127 : H_old=32'd8224;
8'd128 : H_old=32'd8160;
8'd129 : H_old=32'd8097;
8'd130 : H_old=32'd8034;
8'd131 : H_old=32'd7973;
8'd132 : H_old=32'd7913;
8'd133 : H_old=32'd7853;
8'd134 : H_old=32'd7795;
8'd135 : H_old=32'd7737;
8'd136 : H_old=32'd7680;
8'd137 : H_old=32'd7624;
8'd138 : H_old=32'd7569;
8'd139 : H_old=32'd7514;
8'd140 : H_old=32'd7461;
8'd141 : H_old=32'd7408;
8'd142 : H_old=32'd7355;
8'd143 : H_old=32'd7304;
8'd144 : H_old=32'd7253;
8'd145 : H_old=32'd7203;
8'd146 : H_old=32'd7154;
8'd147 : H_old=32'd7105;
8'd148 : H_old=32'd7057;
8'd149 : H_old=32'd7010;
8'd150 : H_old=32'd6963;
8'd151 : H_old=32'd6917;
8'd152 : H_old=32'd6872;
8'd153 : H_old=32'd6827;
8'd154 : H_old=32'd6782;
8'd155 : H_old=32'd6739;
8'd156 : H_old=32'd6695;
8'd157 : H_old=32'd6653;
8'd158 : H_old=32'd6611;
8'd159 : H_old=32'd6569;
8'd160 : H_old=32'd6528;
8'd161 : H_old=32'd6487;
8'd162 : H_old=32'd6447;
8'd163 : H_old=32'd6408;
8'd164 : H_old=32'd6369;
8'd165 : H_old=32'd6330;
8'd166 : H_old=32'd6292;
8'd167 : H_old=32'd6254;
8'd168 : H_old=32'd6217;
8'd169 : H_old=32'd6180;
8'd170 : H_old=32'd6144;
8'd171 : H_old=32'd6108;
8'd172 : H_old=32'd6073;
8'd173 : H_old=32'd6037;
8'd174 : H_old=32'd6003;
8'd175 : H_old=32'd5968;
8'd176 : H_old=32'd5935;
8'd177 : H_old=32'd5901;
8'd178 : H_old=32'd5868;
8'd179 : H_old=32'd5835;
8'd180 : H_old=32'd5803;
8'd181 : H_old=32'd5771;
8'd182 : H_old=32'd5739;
8'd183 : H_old=32'd5708;
8'd184 : H_old=32'd5677;
8'd185 : H_old=32'd5646;
8'd186 : H_old=32'd5615;
8'd187 : H_old=32'd5585;
8'd188 : H_old=32'd5556;
8'd189 : H_old=32'd5526;
8'd190 : H_old=32'd5497;
8'd191 : H_old=32'd5468;
8'd192 : H_old=32'd5440;
8'd193 : H_old=32'd5412;
8'd194 : H_old=32'd5384;
8'd195 : H_old=32'd5356;
8'd196 : H_old=32'd5329;
8'd197 : H_old=32'd5302;
8'd198 : H_old=32'd5275;
8'd199 : H_old=32'd5249;
8'd200 : H_old=32'd5222;
8'd201 : H_old=32'd5196;
8'd202 : H_old=32'd5171;
8'd203 : H_old=32'd5145;
8'd204 : H_old=32'd5120;
8'd205 : H_old=32'd5095;
8'd206 : H_old=32'd5070;
8'd207 : H_old=32'd5046;
8'd208 : H_old=32'd5022;
8'd209 : H_old=32'd4998;
8'd210 : H_old=32'd4974;
8'd211 : H_old=32'd4950;
8'd212 : H_old=32'd4927;
8'd213 : H_old=32'd4904;
8'd214 : H_old=32'd4881;
8'd215 : H_old=32'd4858;
8'd216 : H_old=32'd4836;
8'd217 : H_old=32'd4813;
8'd218 : H_old=32'd4791;
8'd219 : H_old=32'd4769;
8'd220 : H_old=32'd4748;
8'd221 : H_old=32'd4726;
8'd222 : H_old=32'd4705;
8'd223 : H_old=32'd4684;
8'd224 : H_old=32'd4663;
8'd225 : H_old=32'd4642;
8'd226 : H_old=32'd4622;
8'd227 : H_old=32'd4601;
8'd228 : H_old=32'd4581;
8'd229 : H_old=32'd4561;
8'd230 : H_old=32'd4541;
8'd231 : H_old=32'd4522;
8'd232 : H_old=32'd4502;
8'd233 : H_old=32'd4483;
8'd234 : H_old=32'd4464;
8'd235 : H_old=32'd4445;
8'd236 : H_old=32'd4426;
8'd237 : H_old=32'd4407;
8'd238 : H_old=32'd4389;
8'd239 : H_old=32'd4370;
8'd240 : H_old=32'd4352;
8'd241 : H_old=32'd4334;
8'd242 : H_old=32'd4316;
8'd243 : H_old=32'd4298;
8'd244 : H_old=32'd4281;
8'd245 : H_old=32'd4263;
8'd246 : H_old=32'd4246;
8'd247 : H_old=32'd4229;
8'd248 : H_old=32'd4212;
8'd249 : H_old=32'd4195;
8'd250 : H_old=32'd4178;
8'd251 : H_old=32'd4161;
8'd252 : H_old=32'd4145;
8'd253 : H_old=32'd4128;
8'd254 : H_old=32'd4112;
8'd255 : H_old=32'd4096;
endcase
if (RGB[15:8] == max)
begin
if (RGB[23:16] >= RGB[31:24])
begin
hue_dividend <= {2'b0,((16'd60*(RGB[23:16] - RGB[31:24])*H_old)>>20)};
end
else
begin
hue_dividend <= 0- ((16'd60*(RGB[31:24] - RGB[23:16])*H_old)>>20);
end
end
else if (RGB[23:16] == max)
begin
if (RGB[31:24] >= RGB[15:8])
begin
hue_dividend <= (16'd120+((16'd60*(RGB[31:24] - RGB[15:8])*H_old)>>20));
end
else
begin
hue_dividend <= (16'd120-((16'd60*(RGB[15:8] - RGB[31:24])*H_old)>>20));
end
end
else
begin
if (RGB[15:8] >= RGB[23:16])
begin
hue_dividend <= (16'd240+((16'd60*(RGB[15:8] - RGB[23:16])*H_old)>>20));
end
else
begin
hue_dividend <= (16'd240-((16'd60*(RGB[23:16] - RGB[15:8])*H_old)>>20));
end
end
h_int = hue_dividend ;
if (h_int < 0)
begin
HSV[31:24] <= ((h_int >>1)+180);
HSV[7:0]<=0;
end
else
begin
HSV[31:24]<= (h_int>>1);
HSV[7:0]<=0;
end
end
// if (hue_dividend < 0)
// H <= ((hue_dividend >>1)+180);
// else
// H <= (hue_dividend>>1);
end
endmodule |
module test_lfsr_prbs_check_prbs31_64;
// Parameters
parameter LFSR_WIDTH = 31;
parameter LFSR_POLY = 31'h10000001;
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}};
parameter LFSR_CONFIG = "FIBONACCI";
parameter REVERSE = 0;
parameter INVERT = 1;
parameter DATA_WIDTH = 64;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg data_in_valid = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
data_in,
data_in_valid
);
$to_myhdl(
data_out
);
// dump file
$dumpfile("test_lfsr_prbs_check_prbs31_64.lxt");
$dumpvars(0, test_lfsr_prbs_check_prbs31_64);
end
lfsr_prbs_check #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_INIT(LFSR_INIT),
.LFSR_CONFIG(LFSR_CONFIG),
.REVERSE(REVERSE),
.INVERT(INVERT),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_out(data_out)
);
endmodule |
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule |
module dma_pcie_bridge
(
clk,
reset,
// DMA interface (slave)
dma_address,
dma_read,
dma_readdata,
dma_readdatavalid,
dma_write,
dma_writedata,
dma_burstcount,
dma_byteenable,
dma_waitrequest,
// PCIe interface (master)
pcie_address,
pcie_read,
pcie_readdata,
pcie_readdatavalid,
pcie_write,
pcie_writedata,
pcie_burstcount,
pcie_byteenable,
pcie_waitrequest
);
// Parameters set from the GUI
parameter DMA_WIDTH = 256;
parameter PCIE_WIDTH = 64;
parameter DMA_BURSTCOUNT = 6;
parameter PCIE_BURSTCOUNT = 10;
parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required
parameter ADDR_OFFSET = 0;
// Derived parameters
localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8;
localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8;
localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH;
localparam ADDR_SHIFT = $clog2( WIDTH_RATIO );
localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES );
// Global ports
input clk;
input reset;
// DMA slave ports
input [DMA_ADDR_WIDTH-1:0] dma_address;
input dma_read;
output [DMA_WIDTH-1:0 ]dma_readdata;
output dma_readdatavalid;
input dma_write;
input [DMA_WIDTH-1:0] dma_writedata;
input [DMA_BURSTCOUNT-1:0] dma_burstcount;
input [DMA_WIDTH_BYTES-1:0] dma_byteenable;
output dma_waitrequest;
// PCIe master ports
output [31:0] pcie_address;
output pcie_read;
input [PCIE_WIDTH-1:0] pcie_readdata;
input pcie_readdatavalid;
output pcie_write;
output [PCIE_WIDTH-1:0] pcie_writedata;
output [PCIE_BURSTCOUNT-1:0] pcie_burstcount;
output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable;
input pcie_waitrequest;
// Address decoding into byte-address
wire [31:0] dma_byte_address;
assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES);
// Read logic - Buffer the pcie words into a full-sized dma word. The
// last word gets passed through, the first few words are stored
reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away
reg [$clog2(WIDTH_RATIO)-1:0] r_wc;
reg [DMA_WIDTH-1:0] r_demux;
wire [DMA_WIDTH-1:0] r_data;
wire r_full;
wire r_waitrequest;
// Full indicates that a full word is ready to be passed on to the DMA
// as soon as the next pcie-word arrives
assign r_full = &r_wc;
// True when a read request is being stalled (not a function of this unit)
assign r_waitrequest = pcie_waitrequest;
// Groups the previously stored words with the next read data on the pcie bus
assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]};
// Store the first returned words in a buffer, keep track of which word
// we are waiting for in the word counter (r_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_wc <= {$clog2(DMA_WIDTH){1'b0}};
r_buffer <= {(DMA_WIDTH){1'b0}};
end
else
begin
r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc;
if(pcie_readdatavalid)
r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata;
end
end
// Write logic - First word passes through, last words are registered
// and passed on to the fabric in order. Master is stalled until the
// full write has been completed (in PCIe word sized segments)
reg [$clog2(WIDTH_RATIO)-1:0] w_wc;
wire [PCIE_WIDTH_BYTES-1:0] w_byteenable;
wire [PCIE_WIDTH-1:0] w_writedata;
wire w_waitrequest;
wire w_sent;
// Indicates the successful transfer of a pcie-word to PCIe
assign w_sent = pcie_write && !pcie_waitrequest;
// Select the appropriate word to send downstream
assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH];
assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES];
// True when avalon is waiting, or the full word has not been written
assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest;
// Keep track of which word segment we are sending in the word counter (w_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
w_wc <= {$clog2(DMA_WIDTH){1'b0}};
else
w_wc <= w_sent ? (w_wc + 1) : w_wc;
end
// Shared read/write logic
assign pcie_address = ADDR_OFFSET + dma_byte_address;
assign pcie_read = dma_read;
assign pcie_write = dma_write;
assign pcie_writedata = w_writedata;
assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT);
assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable;
assign dma_readdata = r_data;
assign dma_readdatavalid = r_full && pcie_readdatavalid;
assign dma_waitrequest = r_waitrequest || w_waitrequest;
endmodule |
module qram32 (
address,
byteena,
clock,
data,
wren,
q);
input [13:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module sky130_fd_sc_hs__or3b (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module instructionmemory(output [31:0] data,input [6:0] addr,input clk);
reg [31:0] data;
reg [7:0] memdata [511:0];
initial
begin
memdata[0] = 8'b10001101; //load
memdata[1] = 8'b10100001;
memdata[2] = 8'b00000000;
memdata[3] = 8'b00000000;
memdata[4] = 8'b10001101; //load
memdata[5] = 8'b10100010;
memdata[6] = 8'b00000000;
memdata[7] = 8'b00000001;
memdata[8] = 8'b00000000; //add
memdata[9] = 8'b00100010;
memdata[10] = 8'b00011000;
memdata[11] = 8'b00100000;
memdata[12] = 8'b10001101; //load
memdata[13] = 8'b10100100;
memdata[14] = 8'b00000000;
memdata[15] = 8'b00000010;
memdata[16] = 8'b00000000; //sub
memdata[17] = 8'b01100100;
memdata[18] = 8'b00101000;
memdata[19] = 8'b00100010;
memdata[20] = 8'b10001101; //load
memdata[21] = 8'b10100110;
memdata[22] = 8'b00000000;
memdata[23] = 8'b00000011;
memdata[24] = 8'b00000000; //or
memdata[25] = 8'b10100110;
memdata[26] = 8'b00111000;
memdata[27] = 8'b00100101;
memdata[28] = 8'b10001101; //load
memdata[29] = 8'b10101000;
memdata[30] = 8'b00000000;
memdata[31] = 8'b00000100;
memdata[32] = 8'b00000000; //and
memdata[33] = 8'b11101000;
memdata[34] = 8'b01001000;
memdata[35] = 8'b00100100;
memdata[36] = 8'b10101101; //store
memdata[37] = 8'b10101001;
memdata[38] = 8'b00000000;
memdata[39] = 8'b00000111;
memdata[40] = 8'b00010001; //branch
memdata[41] = 8'b10101101;
memdata[42] = 8'b11111111;
memdata[43] = 8'b11111000;
end
always @(negedge clk)
begin
data = { memdata[addr] , memdata[addr+1] , memdata[addr+2] , memdata[addr+3] };
end
endmodule |
module sky130_fd_sc_hd__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_ms__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__tapvgnd2 base ();
endmodule |
module io_buf_iobuf_bidir_loo
(
datain,
dataio,
dataout,
oe) ;
input [0:0] datain;
inout [0:0] dataio;
output [0:0] dataout;
input [0:0] oe;
wire [0:0] wire_ibufa_o;
wire [0:0] wire_obufa_o;
cyclonev_io_ibuf ibufa_0
(
.i(dataio),
.o(wire_ibufa_o[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_0.bus_hold = "false",
ibufa_0.differential_mode = "false",
ibufa_0.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_obuf obufa_0
(
.i(datain),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(oe)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
dataio = wire_obufa_o,
dataout = wire_ibufa_o;
endmodule |
module io_buf (
datain,
oe,
dataio,
dataout);
input [0:0] datain;
input [0:0] oe;
inout [0:0] dataio;
output [0:0] dataout;
wire [0:0] sub_wire0;
wire [0:0] dataout = sub_wire0[0:0];
io_buf_iobuf_bidir_loo io_buf_iobuf_bidir_loo_component (
.dataio (dataio),
.datain (datain),
.oe (oe),
.dataout (sub_wire0));
endmodule |
module sky130_fd_sc_ms__clkbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module sky130_fd_sc_lp__maj3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module cabac_binari_epxgolomb_1kth(
symbol_i ,
mv_sign_i ,
num_bins_2_o ,
num_bins_1_o ,
num_bins_0_o ,
mv_bins_o
);
//-----------------------------------------------------------------------------------------------------------------------------
//
// inputs and outputs declaration
//
//-----------------------------------------------------------------------------------------------------------------------------
input [ 7:0 ] symbol_i ;
input mv_sign_i ;
output [ 2:0 ] num_bins_2_o ;
output [ 2:0 ] num_bins_1_o ;
output [ 2:0 ] num_bins_0_o ;
output [14:0 ] mv_bins_o ;
//-----------------------------------------------------------------------------------------------------------------------------
//
// reg signals declaration
//
//-----------------------------------------------------------------------------------------------------------------------------
reg [ 2:0 ] num_bins_2_r ;
reg [ 2:0 ] num_bins_1_r ;
reg [ 2:0 ] num_bins_0_r ;
//-----------------------------------------------------------------------------------------------------------------------------
//
// binarization process of 1kth epxgolomb
//
//-----------------------------------------------------------------------------------------------------------------------------
/*
always @* begin
case(symbol_i)
6'd0: begin num_group_r = 3'd1;bins_group_2_r=4'd0 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd0 ;num_bins_1_r =3'd0;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd1: begin num_group_r = 3'd1;bins_group_2_r=4'd1 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd0 ;num_bins_1_r =3'd0;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd2: begin num_group_r = 3'd1;bins_group_2_r=4'd8 ;num_bins_2_r= 3'd4;bins_group_1_r=4'd0 ;num_bins_1_r =3'd0;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd3: begin num_group_r = 3'd1;bins_group_2_r=4'd9 ;num_bins_2_r= 3'd4;bins_group_1_r=4'd0 ;num_bins_1_r =3'd0;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd4: begin num_group_r = 3'd1;bins_group_2_r=4'd10;num_bins_2_r= 3'd4;bins_group_1_r=4'd0 ;num_bins_1_r =3'd0;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd5: begin num_group_r = 3'd1;bins_group_2_r=4'd11;num_bins_2_r= 3'd4;bins_group_1_r=4'd0 ;num_bins_1_r =3'd0;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd6: begin num_group_r = 3'd2;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd0 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd7: begin num_group_r = 3'd2;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd1 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd8: begin num_group_r = 3'd2;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd2 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd9: begin num_group_r = 3'd2;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd3 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd10: begin num_group_r = 3'd2;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd4 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd11: begin num_group_r = 3'd2;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd5 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd12: begin num_group_r = 3'd2;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd6 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd13: begin num_group_r = 3'd2;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd7 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd14: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd0 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd15: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd1 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd16: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd2 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd17: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd3 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd18: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd4 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd19: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd5 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd20: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd6 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd21: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd7 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd22: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd8 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd23: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd9 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd24: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd10;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd25: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd11;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd26: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd27: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd28: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd14;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd29: begin num_group_r = 3'd2;bins_group_2_r=4'd14;num_bins_2_r= 3'd4;bins_group_1_r=4'd15;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd0;end
6'd30: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd5;end // include i_hor<0 and i_ver<0
6'd31: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd1 ;num_bins_0_r =3'd5;end
6'd32: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd2 ;num_bins_0_r =3'd5;end
6'd33: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd3 ;num_bins_0_r =3'd5;end
6'd34: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd4 ;num_bins_0_r =3'd5;end
6'd35: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd5 ;num_bins_0_r =3'd5;end
6'd36: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd6 ;num_bins_0_r =3'd5;end
6'd37: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd7 ;num_bins_0_r =3'd5;end
6'd38: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd8 ;num_bins_0_r =3'd5;end
6'd39: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd9 ;num_bins_0_r =3'd5;end
6'd40: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd10;num_bins_0_r =3'd5;end
6'd41: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd11;num_bins_0_r =3'd5;end
6'd42: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd12;num_bins_0_r =3'd5;end
6'd43: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd13;num_bins_0_r =3'd5;end
6'd44: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd14;num_bins_0_r =3'd5;end
6'd45: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd12;num_bins_1_r =3'd4;bins_group_0_r=4'd15;num_bins_0_r =3'd5;end
6'd46: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd5;end
6'd47: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd1 ;num_bins_0_r =3'd5;end
6'd48: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd2 ;num_bins_0_r =3'd5;end
6'd49: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd3 ;num_bins_0_r =3'd5;end
6'd50: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd4 ;num_bins_0_r =3'd5;end
6'd51: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd5 ;num_bins_0_r =3'd5;end
6'd52: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd6 ;num_bins_0_r =3'd5;end
6'd53: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd7 ;num_bins_0_r =3'd5;end
6'd54: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd8 ;num_bins_0_r =3'd5;end
6'd55: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd9 ;num_bins_0_r =3'd5;end
6'd56: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd10;num_bins_0_r =3'd5;end
6'd57: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd11;num_bins_0_r =3'd5;end
6'd58: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd12;num_bins_0_r =3'd5;end
6'd59: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd13;num_bins_0_r =3'd5;end
6'd60: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd14;num_bins_0_r =3'd5;end
6'd61: begin num_group_r = 3'd3;bins_group_2_r=4'd3 ;num_bins_2_r= 3'd2;bins_group_1_r=4'd13;num_bins_1_r =3'd4;bins_group_0_r=4'd15;num_bins_0_r =3'd5;end
6'd62: begin num_group_r = 3'd3;bins_group_2_r=4'd15;num_bins_2_r= 3'd2;bins_group_1_r=4'd8 ;num_bins_1_r =3'd4;bins_group_0_r=4'd0 ;num_bins_0_r =3'd5;end
6'd63: begin num_group_r = 3'd3;bins_group_2_r=4'd15;num_bins_2_r= 3'd4;bins_group_1_r=4'd8 ;num_bins_1_r =3'd4;bins_group_0_r=4'd1 ;num_bins_0_r =3'd5;end
default: begin num_group_r = 3'd3;bins_group_2_r=4'd15;num_bins_2_r= 3'd4;bins_group_1_r=4'd8 ;num_bins_1_r =3'd4;bins_group_0_r=4'd1 ;num_bins_0_r =3'd5;end
endcase
end
*/
wire [ 7:0 ] mv_x_abs_minus128_w ;
wire [ 7:0 ] mv_x_abs_minus64_w ;
wire [ 7:0 ] mv_x_abs_minus32_w ;
wire [ 7:0 ] mv_x_abs_minus16_w ;
wire [ 7:0 ] mv_x_abs_minus8_w ;
wire [ 7:0 ] mv_x_abs_minus4_w ;
wire [ 7:0 ] mv_x_abs_minus2_w ;
reg [14:0 ] mv_x_bins_r ;
assign mv_x_abs_minus128_w = symbol_i - 8'd128 ;
assign mv_x_abs_minus64_w = symbol_i - 8'd64 ;
assign mv_x_abs_minus32_w = symbol_i - 8'd32 ;
assign mv_x_abs_minus16_w = symbol_i - 8'd16 ;
assign mv_x_abs_minus8_w = symbol_i - 8'd8 ;
assign mv_x_abs_minus4_w = symbol_i - 8'd4 ;
assign mv_x_abs_minus2_w = symbol_i - 8'd2 ;
always @* begin
if(symbol_i[7]) begin //128--
mv_x_bins_r = { 7'b1111110,mv_x_abs_minus128_w[6:0],mv_sign_i} ;
num_bins_2_r = 3'd5 ;
num_bins_1_r = 3'd5 ;
num_bins_0_r = 3'd5 ;
end
else if(symbol_i[6]) begin //64--
mv_x_bins_r = {2'b0,6'b111110 ,mv_x_abs_minus64_w[5:0] ,mv_sign_i} ;
num_bins_2_r = 3'd3 ;
num_bins_1_r = 3'd5 ;
num_bins_0_r = 3'd5 ;
end
else if(symbol_i[5]) begin //32--
mv_x_bins_r = {4'b0,5'b11110 ,mv_x_abs_minus32_w[4:0] ,mv_sign_i} ;
num_bins_2_r = 3'd1 ;
num_bins_1_r = 3'd5 ;
num_bins_0_r = 3'd5 ;
end
else if(symbol_i[4]) begin //16--
mv_x_bins_r = {6'b0,4'b1110 ,mv_x_abs_minus16_w[3:0] ,mv_sign_i} ;
num_bins_2_r = 3'd0 ;
num_bins_1_r = 3'd4 ;
num_bins_0_r = 3'd5 ;
end
else if(symbol_i[3]) begin //8--
mv_x_bins_r = {8'b0,3'b110 ,mv_x_abs_minus8_w[2:0] ,mv_sign_i} ;
num_bins_2_r = 3'd0 ;
num_bins_1_r = 3'd2 ;
num_bins_0_r = 3'd5 ;
end
else if(symbol_i[2]) begin //4--
mv_x_bins_r = {10'b0,2'b10 ,mv_x_abs_minus4_w[1:0] ,mv_sign_i} ;
num_bins_2_r = 3'd0 ;
num_bins_1_r = 3'd0 ;
num_bins_0_r = 3'd5 ;
end
else if(symbol_i[1]) begin //2--
mv_x_bins_r = {12'b0,1'b0 ,mv_x_abs_minus2_w[0] ,mv_sign_i} ;
num_bins_2_r = 3'd0 ;
num_bins_1_r = 3'd0 ;
num_bins_0_r = 3'd3 ;
end
else if(symbol_i[0]) begin //1--
mv_x_bins_r = {14'b0, mv_sign_i} ;
num_bins_2_r = 3'd0 ;
num_bins_1_r = 3'd0 ;
num_bins_0_r = 3'd1 ;
end
else begin //0--
mv_x_bins_r = 15'b0 ;
num_bins_2_r = 3'd0 ;
num_bins_1_r = 3'd0 ;
num_bins_0_r = 3'd0 ;
end
end
//-----------------------------------------------------------------------------------------------------------------------------
//
// output
//
//-----------------------------------------------------------------------------------------------------------------------------
assign mv_bins_o = mv_x_bins_r ;
assign num_bins_2_o = num_bins_2_r ;
assign num_bins_1_o = num_bins_1_r ;
assign num_bins_0_o = num_bins_0_r ;
endmodule |
module diffeq_f_systemC(clk, reset, aport, dxport, xport, yport, uport);
input clk;
input reset;
input [31:0]aport;
input [31:0]dxport;
output [31:0]xport;
output [31:0]yport;
output [31:0]uport;
reg [31:0]xport;
reg [31:0]yport;
reg [31:0]uport;
wire [31:0]temp;
assign temp = uport * dxport;
always @(posedge clk )
begin
if (reset == 1'b1)
begin
xport <= 0;
yport <= 0;
uport <= 0;
end
else
if (xport < aport)
begin
xport <= xport + dxport;
yport <= yport + temp;//(uport * dxport);
uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport));
end
end
endmodule |
module body
//
// delay d
always @(posedge clk)
if (ena)
id <= #1 d;
// check z, take abs value
always @(posedge clk)
if (ena)
if (z[z_width-1])
iz <= #1 ~z +1'h1;
else
iz <= #1 z;
// generate spipe (sign bit pipe)
integer n;
always @(posedge clk)
if(ena)
begin
spipe[0] <= #1 z[z_width-1];
for(n=1; n <= d_width+1; n=n+1)
spipe[n] <= #1 spipe[n-1];
end
// hookup non-restoring divider
div_uu #(z_width, d_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(is),
.div0(idiv0),
.ovf(iovf)
);
// correct divider results if 'd' was negative
always @(posedge clk)
if(ena)
if(spipe[d_width+1])
begin
q <= #1 (~iq) + 1'h1;
s <= #1 (~is) + 1'h1;
end
else
begin
q <= #1 {1'b0, iq};
s <= #1 {1'b0, is};
end
// delay flags same as results
always @(posedge clk)
if(ena)
begin
div0 <= #1 idiv0;
ovf <= #1 iovf;
end
endmodule |
module gtwizard_ultrascale_v1_7_1_bit_synchronizer # (
parameter INITIALIZE = 5'b00000,
parameter FREQUENCY = 512
)(
input wire clk_in,
input wire i_in,
output wire o_out
);
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
// enable clustering. Their GSR default values are provided by the INITIALIZE parameter.
(* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0];
(* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1];
(* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2];
(* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3];
reg i_in_out = INITIALIZE[4];
always @(posedge clk_in) begin
i_in_meta <= i_in;
i_in_sync1 <= i_in_meta;
i_in_sync2 <= i_in_sync1;
i_in_sync3 <= i_in_sync2;
i_in_out <= i_in_sync3;
end
assign o_out = i_in_out;
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module sky130_fd_sc_hd__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule |
module outputs
wire [31 : 0] wciS0_SData, wmiM_MData, wmiM_MFlag, wsiM1_MData;
wire [13 : 0] wmiM_MAddr;
wire [11 : 0] wmiM_MBurstLength, wsiM1_MBurstLength;
wire [7 : 0] wsiM1_MReqInfo;
wire [3 : 0] wmiM_MDataByteEn, wsiM1_MByteEn;
wire [2 : 0] wmiM_MCmd, wsiM1_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wmiM_MAddrSpace,
wmiM_MDataLast,
wmiM_MDataValid,
wmiM_MReqInfo,
wmiM_MReqLast,
wmiM_MReset_n,
wsiM1_MBurstPrecise,
wsiM1_MReqLast,
wsiM1_MReset_n,
wsiS1_SReset_n,
wsiS1_SThreadBusy;
// inlined wires
wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget;
wire [60 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget;
wire [59 : 0] wci_wciReq$wget;
wire [37 : 0] wmi_dhF_x_wire$wget;
wire [33 : 0] wci_respF_x_wire$wget, wmi_wmiResponse$wget;
wire [31 : 0] wci_Es_mData_w$wget,
wmi_Em_sData_w$wget,
wmi_mFlagF_x_wire$wget,
wmi_reqF_x_wire$wget,
wsi_Es_mData_w$wget;
wire [19 : 0] wci_Es_mAddr_w$wget;
wire [11 : 0] wsi_Es_mBurstLength_w$wget;
wire [7 : 0] wsi_Es_mReqInfo_w$wget;
wire [3 : 0] fabRespCredit_acc_v1$wget,
fabRespCredit_acc_v2$wget,
wci_Es_mByteEn_w$wget,
wsi_Es_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget;
wire [1 : 0] wmi_Em_sResp_w$wget;
wire fabRespCredit_acc_v1$whas,
fabRespCredit_acc_v2$whas,
mesgPreRequest_1$wget,
mesgPreRequest_1$whas,
wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wmi_Em_sData_w$whas,
wmi_Em_sResp_w$whas,
wmi_dhF_dequeueing$whas,
wmi_dhF_enqueueing$whas,
wmi_dhF_x_wire$whas,
wmi_mFlagF_dequeueing$whas,
wmi_mFlagF_enqueueing$whas,
wmi_mFlagF_x_wire$whas,
wmi_operateD_1$wget,
wmi_operateD_1$whas,
wmi_peerIsReady_1$wget,
wmi_peerIsReady_1$whas,
wmi_reqF_dequeueing$whas,
wmi_reqF_enqueueing$whas,
wmi_reqF_x_wire$whas,
wmi_sDataThreadBusy_d_1$wget,
wmi_sDataThreadBusy_d_1$whas,
wmi_sThreadBusy_d_1$wget,
wmi_sThreadBusy_d_1$whas,
wmi_wmiResponse$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas;
// register abortCount
reg [31 : 0] abortCount;
wire [31 : 0] abortCount$D_IN;
wire abortCount$EN;
// register doAbort
reg doAbort;
wire doAbort$D_IN, doAbort$EN;
// register endOfMessage
reg endOfMessage;
wire endOfMessage$D_IN, endOfMessage$EN;
// register errCount
reg [31 : 0] errCount;
wire [31 : 0] errCount$D_IN;
wire errCount$EN;
// register fabRespCredit_value
reg [3 : 0] fabRespCredit_value;
wire [3 : 0] fabRespCredit_value$D_IN;
wire fabRespCredit_value$EN;
// register fabWordsCurReq
reg [13 : 0] fabWordsCurReq;
wire [13 : 0] fabWordsCurReq$D_IN;
wire fabWordsCurReq$EN;
// register fabWordsRemain
reg [13 : 0] fabWordsRemain;
wire [13 : 0] fabWordsRemain$D_IN;
wire fabWordsRemain$EN;
// register firstMsgReq
reg firstMsgReq;
wire firstMsgReq$D_IN, firstMsgReq$EN;
// register impreciseBurst
reg impreciseBurst;
reg impreciseBurst$D_IN;
wire impreciseBurst$EN;
// register lastMesg
reg [31 : 0] lastMesg;
wire [31 : 0] lastMesg$D_IN;
wire lastMesg$EN;
// register mesgCount
reg [31 : 0] mesgCount;
reg [31 : 0] mesgCount$D_IN;
wire mesgCount$EN;
// register mesgLength
reg [14 : 0] mesgLength;
reg [14 : 0] mesgLength$D_IN;
wire mesgLength$EN;
// register mesgLengthSoFar
reg [13 : 0] mesgLengthSoFar;
wire [13 : 0] mesgLengthSoFar$D_IN;
wire mesgLengthSoFar$EN;
// register mesgPreRequest
reg mesgPreRequest;
wire mesgPreRequest$D_IN, mesgPreRequest$EN;
// register mesgReqAddr
reg [13 : 0] mesgReqAddr;
wire [13 : 0] mesgReqAddr$D_IN;
wire mesgReqAddr$EN;
// register mesgReqOK
reg mesgReqOK;
wire mesgReqOK$D_IN, mesgReqOK$EN;
// register mesgReqValid
reg mesgReqValid;
wire mesgReqValid$D_IN, mesgReqValid$EN;
// register opcode
reg [8 : 0] opcode;
reg [8 : 0] opcode$D_IN;
wire opcode$EN;
// register preciseBurst
reg preciseBurst;
reg preciseBurst$D_IN;
wire preciseBurst$EN;
// register readyToPush
reg readyToPush;
reg readyToPush$D_IN;
wire readyToPush$EN;
// register readyToRequest
reg readyToRequest;
wire readyToRequest$D_IN, readyToRequest$EN;
// register smaCtrl
reg [31 : 0] smaCtrl;
wire [31 : 0] smaCtrl$D_IN;
wire smaCtrl$EN;
// register thisMesg
reg [31 : 0] thisMesg;
reg [31 : 0] thisMesg$D_IN;
wire thisMesg$EN;
// register unrollCnt
reg [15 : 0] unrollCnt;
wire [15 : 0] unrollCnt$D_IN;
wire unrollCnt$EN;
// register valExpect
reg [31 : 0] valExpect;
wire [31 : 0] valExpect$D_IN;
wire valExpect$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wmi_busyWithMessage
reg wmi_busyWithMessage;
wire wmi_busyWithMessage$D_IN, wmi_busyWithMessage$EN;
// register wmi_dhF_c_r
reg [1 : 0] wmi_dhF_c_r;
wire [1 : 0] wmi_dhF_c_r$D_IN;
wire wmi_dhF_c_r$EN;
// register wmi_dhF_q_0
reg [37 : 0] wmi_dhF_q_0;
reg [37 : 0] wmi_dhF_q_0$D_IN;
wire wmi_dhF_q_0$EN;
// register wmi_dhF_q_1
reg [37 : 0] wmi_dhF_q_1;
reg [37 : 0] wmi_dhF_q_1$D_IN;
wire wmi_dhF_q_1$EN;
// register wmi_mFlagF_c_r
reg [1 : 0] wmi_mFlagF_c_r;
wire [1 : 0] wmi_mFlagF_c_r$D_IN;
wire wmi_mFlagF_c_r$EN;
// register wmi_mFlagF_q_0
reg [31 : 0] wmi_mFlagF_q_0;
reg [31 : 0] wmi_mFlagF_q_0$D_IN;
wire wmi_mFlagF_q_0$EN;
// register wmi_mFlagF_q_1
reg [31 : 0] wmi_mFlagF_q_1;
reg [31 : 0] wmi_mFlagF_q_1$D_IN;
wire wmi_mFlagF_q_1$EN;
// register wmi_operateD
reg wmi_operateD;
wire wmi_operateD$D_IN, wmi_operateD$EN;
// register wmi_peerIsReady
reg wmi_peerIsReady;
wire wmi_peerIsReady$D_IN, wmi_peerIsReady$EN;
// register wmi_reqF_c_r
reg [1 : 0] wmi_reqF_c_r;
wire [1 : 0] wmi_reqF_c_r$D_IN;
wire wmi_reqF_c_r$EN;
// register wmi_reqF_q_0
reg [31 : 0] wmi_reqF_q_0;
reg [31 : 0] wmi_reqF_q_0$D_IN;
wire wmi_reqF_q_0$EN;
// register wmi_reqF_q_1
reg [31 : 0] wmi_reqF_q_1;
reg [31 : 0] wmi_reqF_q_1$D_IN;
wire wmi_reqF_q_1$EN;
// register wmi_sDataThreadBusy_d
reg wmi_sDataThreadBusy_d;
wire wmi_sDataThreadBusy_d$D_IN, wmi_sDataThreadBusy_d$EN;
// register wmi_sFlagReg
reg [31 : 0] wmi_sFlagReg;
wire [31 : 0] wmi_sFlagReg$D_IN;
wire wmi_sFlagReg$EN;
// register wmi_sThreadBusy_d
reg wmi_sThreadBusy_d;
wire wmi_sThreadBusy_d$D_IN, wmi_sThreadBusy_d$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [60 : 0] wsiM_reqFifo_q_0;
reg [60 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [60 : 0] wsiM_reqFifo_q_1;
reg [60 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// register wsiWordsRemain
reg [11 : 0] wsiWordsRemain;
wire [11 : 0] wsiWordsRemain$D_IN;
wire wsiWordsRemain$EN;
// register zeroLengthMesg
reg zeroLengthMesg;
wire zeroLengthMesg$D_IN, zeroLengthMesg$EN;
// ports of submodule wci_isReset
wire wci_isReset$VAL;
// ports of submodule wci_reqF
wire [59 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wmi_isReset
wire wmi_isReset$VAL;
// ports of submodule wmi_respF
wire [33 : 0] wmi_respF$D_IN, wmi_respF$D_OUT;
wire wmi_respF$CLR,
wmi_respF$DEQ,
wmi_respF$EMPTY_N,
wmi_respF$ENQ,
wmi_respF$FULL_N;
// ports of submodule wsiM_isReset
wire wsiM_isReset$VAL;
// ports of submodule wsiS_isReset
wire wsiS_isReset$VAL;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_fabRespCredit_accumulate,
CAN_FIRE_RL_mesgPreRequest__dreg_update,
CAN_FIRE_RL_operating_actions,
CAN_FIRE_RL_wci_Es_doAlways_Req,
CAN_FIRE_RL_wci_cfrd,
CAN_FIRE_RL_wci_cfwr,
CAN_FIRE_RL_wci_ctlAckReg__dreg_update,
CAN_FIRE_RL_wci_ctl_op_complete,
CAN_FIRE_RL_wci_ctl_op_start,
CAN_FIRE_RL_wci_ctrl_EiI,
CAN_FIRE_RL_wci_ctrl_IsO,
CAN_FIRE_RL_wci_ctrl_OrE,
CAN_FIRE_RL_wci_reqF__updateLevelCounter,
CAN_FIRE_RL_wci_reqF_enq,
CAN_FIRE_RL_wci_request_decode,
CAN_FIRE_RL_wci_respF_both,
CAN_FIRE_RL_wci_respF_decCtr,
CAN_FIRE_RL_wci_respF_deq,
CAN_FIRE_RL_wci_respF_incCtr,
CAN_FIRE_RL_wci_sFlagReg__dreg_update,
CAN_FIRE_RL_wci_sThreadBusy_reg,
CAN_FIRE_RL_wmi_Em_doAlways,
CAN_FIRE_RL_wmi_dhF_both,
CAN_FIRE_RL_wmi_dhF_decCtr,
CAN_FIRE_RL_wmi_dhF_deq,
CAN_FIRE_RL_wmi_dhF_incCtr,
CAN_FIRE_RL_wmi_mFlagF_both,
CAN_FIRE_RL_wmi_mFlagF_decCtr,
CAN_FIRE_RL_wmi_mFlagF_incCtr,
CAN_FIRE_RL_wmi_operateD__dreg_update,
CAN_FIRE_RL_wmi_peerIsReady__dreg_update,
CAN_FIRE_RL_wmi_reqF_both,
CAN_FIRE_RL_wmi_reqF_decCtr,
CAN_FIRE_RL_wmi_reqF_deq,
CAN_FIRE_RL_wmi_reqF_incCtr,
CAN_FIRE_RL_wmi_respAdvance,
CAN_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update,
CAN_FIRE_RL_wmi_sThreadBusy_d__dreg_update,
CAN_FIRE_RL_wmrd_mesgBegin,
CAN_FIRE_RL_wmrd_mesgBodyPreRequest,
CAN_FIRE_RL_wmrd_mesgBodyRequest,
CAN_FIRE_RL_wmrd_mesgBodyResponse,
CAN_FIRE_RL_wmwt_doAbort,
CAN_FIRE_RL_wmwt_mesgBegin,
CAN_FIRE_RL_wmwt_messageFinalize,
CAN_FIRE_RL_wmwt_messagePushImprecise,
CAN_FIRE_RL_wmwt_messagePushPrecise,
CAN_FIRE_RL_wmwt_requestPrecise,
CAN_FIRE_RL_wsiM_ext_status_assign,
CAN_FIRE_RL_wsiM_inc_tBusyCount,
CAN_FIRE_RL_wsiM_operateD__dreg_update,
CAN_FIRE_RL_wsiM_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiM_reqFifo_both,
CAN_FIRE_RL_wsiM_reqFifo_decCtr,
CAN_FIRE_RL_wsiM_reqFifo_deq,
CAN_FIRE_RL_wsiM_reqFifo_incCtr,
CAN_FIRE_RL_wsiM_sThreadBusy_reg,
CAN_FIRE_RL_wsiM_update_statusR,
CAN_FIRE_RL_wsiS_ext_status_assign,
CAN_FIRE_RL_wsiS_inc_tBusyCount,
CAN_FIRE_RL_wsiS_operateD__dreg_update,
CAN_FIRE_RL_wsiS_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
CAN_FIRE_RL_wsiS_reqFifo_enq,
CAN_FIRE_RL_wsiS_update_statusR,
CAN_FIRE_RL_wsi_Es_doAlways,
CAN_FIRE_RL_wsipass_doMessagePush,
CAN_FIRE_wciS0_mAddr,
CAN_FIRE_wciS0_mAddrSpace,
CAN_FIRE_wciS0_mByteEn,
CAN_FIRE_wciS0_mCmd,
CAN_FIRE_wciS0_mData,
CAN_FIRE_wciS0_mFlag,
CAN_FIRE_wmiM_sData,
CAN_FIRE_wmiM_sDataThreadBusy,
CAN_FIRE_wmiM_sFlag,
CAN_FIRE_wmiM_sReset_n,
CAN_FIRE_wmiM_sResp,
CAN_FIRE_wmiM_sRespLast,
CAN_FIRE_wmiM_sThreadBusy,
CAN_FIRE_wsiM1_sReset_n,
CAN_FIRE_wsiM1_sThreadBusy,
CAN_FIRE_wsiS1_mBurstLength,
CAN_FIRE_wsiS1_mBurstPrecise,
CAN_FIRE_wsiS1_mByteEn,
CAN_FIRE_wsiS1_mCmd,
CAN_FIRE_wsiS1_mData,
CAN_FIRE_wsiS1_mDataInfo,
CAN_FIRE_wsiS1_mReqInfo,
CAN_FIRE_wsiS1_mReqLast,
CAN_FIRE_wsiS1_mReset_n,
WILL_FIRE_RL_fabRespCredit_accumulate,
WILL_FIRE_RL_mesgPreRequest__dreg_update,
WILL_FIRE_RL_operating_actions,
WILL_FIRE_RL_wci_Es_doAlways_Req,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctlAckReg__dreg_update,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_reqF__updateLevelCounter,
WILL_FIRE_RL_wci_reqF_enq,
WILL_FIRE_RL_wci_request_decode,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_deq,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wci_sFlagReg__dreg_update,
WILL_FIRE_RL_wci_sThreadBusy_reg,
WILL_FIRE_RL_wmi_Em_doAlways,
WILL_FIRE_RL_wmi_dhF_both,
WILL_FIRE_RL_wmi_dhF_decCtr,
WILL_FIRE_RL_wmi_dhF_deq,
WILL_FIRE_RL_wmi_dhF_incCtr,
WILL_FIRE_RL_wmi_mFlagF_both,
WILL_FIRE_RL_wmi_mFlagF_decCtr,
WILL_FIRE_RL_wmi_mFlagF_incCtr,
WILL_FIRE_RL_wmi_operateD__dreg_update,
WILL_FIRE_RL_wmi_peerIsReady__dreg_update,
WILL_FIRE_RL_wmi_reqF_both,
WILL_FIRE_RL_wmi_reqF_decCtr,
WILL_FIRE_RL_wmi_reqF_deq,
WILL_FIRE_RL_wmi_reqF_incCtr,
WILL_FIRE_RL_wmi_respAdvance,
WILL_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update,
WILL_FIRE_RL_wmi_sThreadBusy_d__dreg_update,
WILL_FIRE_RL_wmrd_mesgBegin,
WILL_FIRE_RL_wmrd_mesgBodyPreRequest,
WILL_FIRE_RL_wmrd_mesgBodyRequest,
WILL_FIRE_RL_wmrd_mesgBodyResponse,
WILL_FIRE_RL_wmwt_doAbort,
WILL_FIRE_RL_wmwt_mesgBegin,
WILL_FIRE_RL_wmwt_messageFinalize,
WILL_FIRE_RL_wmwt_messagePushImprecise,
WILL_FIRE_RL_wmwt_messagePushPrecise,
WILL_FIRE_RL_wmwt_requestPrecise,
WILL_FIRE_RL_wsiM_ext_status_assign,
WILL_FIRE_RL_wsiM_inc_tBusyCount,
WILL_FIRE_RL_wsiM_operateD__dreg_update,
WILL_FIRE_RL_wsiM_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiM_sThreadBusy_reg,
WILL_FIRE_RL_wsiM_update_statusR,
WILL_FIRE_RL_wsiS_ext_status_assign,
WILL_FIRE_RL_wsiS_inc_tBusyCount,
WILL_FIRE_RL_wsiS_operateD__dreg_update,
WILL_FIRE_RL_wsiS_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_update_statusR,
WILL_FIRE_RL_wsi_Es_doAlways,
WILL_FIRE_RL_wsipass_doMessagePush,
WILL_FIRE_wciS0_mAddr,
WILL_FIRE_wciS0_mAddrSpace,
WILL_FIRE_wciS0_mByteEn,
WILL_FIRE_wciS0_mCmd,
WILL_FIRE_wciS0_mData,
WILL_FIRE_wciS0_mFlag,
WILL_FIRE_wmiM_sData,
WILL_FIRE_wmiM_sDataThreadBusy,
WILL_FIRE_wmiM_sFlag,
WILL_FIRE_wmiM_sReset_n,
WILL_FIRE_wmiM_sResp,
WILL_FIRE_wmiM_sRespLast,
WILL_FIRE_wmiM_sThreadBusy,
WILL_FIRE_wsiM1_sReset_n,
WILL_FIRE_wsiM1_sThreadBusy,
WILL_FIRE_wsiS1_mBurstLength,
WILL_FIRE_wsiS1_mBurstPrecise,
WILL_FIRE_wsiS1_mByteEn,
WILL_FIRE_wsiS1_mCmd,
WILL_FIRE_wsiS1_mData,
WILL_FIRE_wsiS1_mDataInfo,
WILL_FIRE_wsiS1_mReqInfo,
WILL_FIRE_wsiS1_mReqLast,
WILL_FIRE_wsiS1_mReset_n;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2;
reg [31 : 0] MUX_wmi_reqF_q_0$write_1__VAL_2;
wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
MUX_wsiM_reqFifo_q_1$write_1__VAL_1,
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1;
wire [37 : 0] MUX_wmi_dhF_q_0$write_1__VAL_1,
MUX_wmi_dhF_q_0$write_1__VAL_2,
MUX_wmi_dhF_q_1$write_1__VAL_1,
MUX_wmi_dhF_x_wire$wset_1__VAL_1,
MUX_wmi_dhF_x_wire$wset_1__VAL_2;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1,
MUX_wci_respF_q_1$write_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2;
wire [31 : 0] MUX_mesgCount$write_1__VAL_2,
MUX_thisMesg$write_1__VAL_1,
MUX_thisMesg$write_1__VAL_2,
MUX_wmi_mFlagF_q_0$write_1__VAL_1,
MUX_wmi_mFlagF_q_1$write_1__VAL_1,
MUX_wmi_mFlagF_x_wire$wset_1__VAL_1,
MUX_wmi_mFlagF_x_wire$wset_1__VAL_3,
MUX_wmi_reqF_q_0$write_1__VAL_1,
MUX_wmi_reqF_q_1$write_1__VAL_1,
MUX_wmi_reqF_x_wire$wset_1__VAL_1,
MUX_wmi_reqF_x_wire$wset_1__VAL_2,
MUX_wmi_reqF_x_wire$wset_1__VAL_3;
wire [15 : 0] MUX_unrollCnt$write_1__VAL_1, MUX_unrollCnt$write_1__VAL_2;
wire [14 : 0] MUX_mesgLength$write_1__VAL_2, MUX_mesgLength$write_1__VAL_4;
wire [13 : 0] MUX_fabWordsRemain$write_1__VAL_1,
MUX_fabWordsRemain$write_1__VAL_2,
MUX_mesgLengthSoFar$write_1__VAL_2,
MUX_mesgReqAddr$write_1__VAL_2;
wire [11 : 0] MUX_wsiWordsRemain$write_1__VAL_2;
wire [8 : 0] MUX_opcode$write_1__VAL_2;
wire [3 : 0] MUX_fabRespCredit_value$write_1__VAL_2;
wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wmi_dhF_c_r$write_1__VAL_1,
MUX_wmi_dhF_c_r$write_1__VAL_2,
MUX_wmi_mFlagF_c_r$write_1__VAL_1,
MUX_wmi_mFlagF_c_r$write_1__VAL_2,
MUX_wmi_reqF_c_r$write_1__VAL_1,
MUX_wmi_reqF_c_r$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_endOfMessage$write_1__PSEL_1,
MUX_endOfMessage$write_1__SEL_1,
MUX_endOfMessage$write_1__SEL_2,
MUX_impreciseBurst$write_1__PSEL_2,
MUX_impreciseBurst$write_1__SEL_1,
MUX_impreciseBurst$write_1__SEL_2,
MUX_lastMesg$write_1__SEL_2,
MUX_mesgCount$write_1__SEL_1,
MUX_mesgLength$write_1__SEL_2,
MUX_mesgReqValid$write_1__SEL_2,
MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__SEL_2,
MUX_wci_illegalEdge$write_1__VAL_2,
MUX_wci_respF_q_0$write_1__SEL_2,
MUX_wci_respF_q_1$write_1__SEL_2,
MUX_wmi_dhF_q_0$write_1__SEL_2,
MUX_wmi_dhF_q_1$write_1__SEL_2,
MUX_wmi_mFlagF_q_0$write_1__SEL_2,
MUX_wmi_mFlagF_q_1$write_1__SEL_2,
MUX_wmi_mFlagF_x_wire$wset_1__SEL_2,
MUX_wmi_reqF_q_0$write_1__SEL_2,
MUX_wmi_reqF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
MUX_wsiM_reqFifo_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1,
MUX_wsiWordsRemain$write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h15314,
v__h16237,
v__h16483,
v__h18178,
v__h18255,
v__h19472,
v__h2653,
v__h2800,
v__h3699;
reg [31 : 0] value__h6065, x_data__h15447;
wire [31 : 0] rdat__h15540;
wire [23 : 0] mesgMetaF_length__h16810, mesgMetaF_length__h17725;
wire [15 : 0] wsiBurstLength__h18456, x__h15543, x_length__h17088;
wire [13 : 0] IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753,
addr__h16647,
b__h19086,
mlp1B__h16631,
mlp1__h16630;
wire [11 : 0] bl__h17582, x_burstLength__h18561;
wire [7 : 0] mesgMetaF_opcode__h16809;
wire [3 : 0] b__h13937, x_byteEn__h18563;
wire NOT_wmi_reqF_c_r_46_EQ_2_47_48_AND_wmi_operate_ETC___d290,
NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355,
wsiS_reqFifo_i_notEmpty__52_AND_wmi_operateD_5_ETC___d165,
x__h16715,
x__h18886;
// action method wciS0_mCmd
assign CAN_FIRE_wciS0_mCmd = 1'd1 ;
assign WILL_FIRE_wciS0_mCmd = 1'd1 ;
// action method wciS0_mAddrSpace
assign CAN_FIRE_wciS0_mAddrSpace = 1'd1 ;
assign WILL_FIRE_wciS0_mAddrSpace = 1'd1 ;
// action method wciS0_mByteEn
assign CAN_FIRE_wciS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wciS0_mByteEn = 1'd1 ;
// action method wciS0_mAddr
assign CAN_FIRE_wciS0_mAddr = 1'd1 ;
assign WILL_FIRE_wciS0_mAddr = 1'd1 ;
// action method wciS0_mData
assign CAN_FIRE_wciS0_mData = 1'd1 ;
assign WILL_FIRE_wciS0_mData = 1'd1 ;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy = wci_reqF_countReg > 2'd1 || wci_isReset$VAL ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// action method wciS0_mFlag
assign CAN_FIRE_wciS0_mFlag = 1'd1 ;
assign WILL_FIRE_wciS0_mFlag = 1'd1 ;
// value method wmiM_mCmd
assign wmiM_MCmd = wmi_sThreadBusy_d ? 3'd0 : wmi_reqF_q_0[31:29] ;
// value method wmiM_mReqLast
assign wmiM_MReqLast = wmi_reqF_q_0[28] ;
// value method wmiM_mReqInfo
assign wmiM_MReqInfo = wmi_reqF_q_0[27] ;
// value method wmiM_mAddrSpace
assign wmiM_MAddrSpace = wmi_reqF_q_0[26] ;
// value method wmiM_mAddr
assign wmiM_MAddr = wmi_reqF_q_0[25:12] ;
// value method wmiM_mBurstLength
assign wmiM_MBurstLength = wmi_reqF_q_0[11:0] ;
// value method wmiM_mDataValid
assign wmiM_MDataValid = !wmi_sDataThreadBusy_d && wmi_dhF_q_0[37] ;
// value method wmiM_mDataLast
assign wmiM_MDataLast = wmi_dhF_q_0[36] ;
// value method wmiM_mData
assign wmiM_MData = wmi_dhF_q_0[35:4] ;
// value method wmiM_mDataByteEn
assign wmiM_MDataByteEn = wmi_dhF_q_0[3:0] ;
// action method wmiM_sResp
assign CAN_FIRE_wmiM_sResp = 1'd1 ;
assign WILL_FIRE_wmiM_sResp = 1'd1 ;
// action method wmiM_sData
assign CAN_FIRE_wmiM_sData = 1'd1 ;
assign WILL_FIRE_wmiM_sData = 1'd1 ;
// action method wmiM_sThreadBusy
assign CAN_FIRE_wmiM_sThreadBusy = 1'd1 ;
assign WILL_FIRE_wmiM_sThreadBusy = wmiM_SThreadBusy ;
// action method wmiM_sDataThreadBusy
assign CAN_FIRE_wmiM_sDataThreadBusy = 1'd1 ;
assign WILL_FIRE_wmiM_sDataThreadBusy = wmiM_SDataThreadBusy ;
// action method wmiM_sRespLast
assign CAN_FIRE_wmiM_sRespLast = 1'd1 ;
assign WILL_FIRE_wmiM_sRespLast = wmiM_SRespLast ;
// action method wmiM_sFlag
assign CAN_FIRE_wmiM_sFlag = 1'd1 ;
assign WILL_FIRE_wmiM_sFlag = 1'd1 ;
// value method wmiM_mFlag
assign wmiM_MFlag = wmi_sThreadBusy_d ? 32'd0 : wmi_mFlagF_q_0 ;
// value method wmiM_mReset_n
assign wmiM_MReset_n = !wmi_isReset$VAL && wmi_operateD ;
// action method wmiM_sReset_n
assign CAN_FIRE_wmiM_sReset_n = 1'd1 ;
assign WILL_FIRE_wmiM_sReset_n = wmiM_SReset_n ;
// value method wsiM1_mCmd
assign wsiM1_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ;
// value method wsiM1_mReqLast
assign wsiM1_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ;
// value method wsiM1_mBurstPrecise
assign wsiM1_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ;
// value method wsiM1_mBurstLength
assign wsiM1_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ;
// value method wsiM1_mData
assign wsiM1_MData = wsiM_reqFifo_q_0[43:12] ;
// value method wsiM1_mByteEn
assign wsiM1_MByteEn = wsiM_reqFifo_q_0[11:8] ;
// value method wsiM1_mReqInfo
assign wsiM1_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// action method wsiM1_sThreadBusy
assign CAN_FIRE_wsiM1_sThreadBusy = 1'd1 ;
assign WILL_FIRE_wsiM1_sThreadBusy = wsiM1_SThreadBusy ;
// value method wsiM1_mReset_n
assign wsiM1_MReset_n = !wsiM_isReset$VAL && wsiM_operateD ;
// action method wsiM1_sReset_n
assign CAN_FIRE_wsiM1_sReset_n = 1'd1 ;
assign WILL_FIRE_wsiM1_sReset_n = wsiM1_SReset_n ;
// action method wsiS1_mCmd
assign CAN_FIRE_wsiS1_mCmd = 1'd1 ;
assign WILL_FIRE_wsiS1_mCmd = 1'd1 ;
// action method wsiS1_mReqLast
assign CAN_FIRE_wsiS1_mReqLast = 1'd1 ;
assign WILL_FIRE_wsiS1_mReqLast = wsiS1_MReqLast ;
// action method wsiS1_mBurstPrecise
assign CAN_FIRE_wsiS1_mBurstPrecise = 1'd1 ;
assign WILL_FIRE_wsiS1_mBurstPrecise = wsiS1_MBurstPrecise ;
// action method wsiS1_mBurstLength
assign CAN_FIRE_wsiS1_mBurstLength = 1'd1 ;
assign WILL_FIRE_wsiS1_mBurstLength = 1'd1 ;
// action method wsiS1_mData
assign CAN_FIRE_wsiS1_mData = 1'd1 ;
assign WILL_FIRE_wsiS1_mData = 1'd1 ;
// action method wsiS1_mByteEn
assign CAN_FIRE_wsiS1_mByteEn = 1'd1 ;
assign WILL_FIRE_wsiS1_mByteEn = 1'd1 ;
// action method wsiS1_mReqInfo
assign CAN_FIRE_wsiS1_mReqInfo = 1'd1 ;
assign WILL_FIRE_wsiS1_mReqInfo = 1'd1 ;
// action method wsiS1_mDataInfo
assign CAN_FIRE_wsiS1_mDataInfo = 1'd1 ;
assign WILL_FIRE_wsiS1_mDataInfo = 1'd1 ;
// value method wsiS1_sThreadBusy
assign wsiS1_SThreadBusy =
NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 ||
wsiS_isReset$VAL ||
!wsiS_operateD ||
!wsiS_peerIsReady ;
// value method wsiS1_sReset_n
assign wsiS1_SReset_n = !wsiS_isReset$VAL && wsiS_operateD ;
// action method wsiS1_mReset_n
assign CAN_FIRE_wsiS1_mReset_n = 1'd1 ;
assign WILL_FIRE_wsiS1_mReset_n = wsiS1_MReset_n ;
// submodule wci_isReset
ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset$VAL));
// submodule wci_reqF
SizedFIFO #(.p1width(32'd60),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wmi_isReset
ResetToBool wmi_isReset(.RST(wciS0_MReset_n), .VAL(wmi_isReset$VAL));
// submodule wmi_respF
FIFO2 #(.width(32'd34), .guarded(32'd1)) wmi_respF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wmi_respF$D_IN),
.ENQ(wmi_respF$ENQ),
.DEQ(wmi_respF$DEQ),
.CLR(wmi_respF$CLR),
.D_OUT(wmi_respF$D_OUT),
.FULL_N(wmi_respF$FULL_N),
.EMPTY_N(wmi_respF$EMPTY_N));
// submodule wsiM_isReset
ResetToBool wsiM_isReset(.RST(wciS0_MReset_n), .VAL(wsiM_isReset$VAL));
// submodule wsiS_isReset
ResetToBool wsiS_isReset(.RST(wciS0_MReset_n), .VAL(wsiS_isReset$VAL));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// rule RL_wci_request_decode
assign CAN_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
assign WILL_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
// rule RL_wsiM_ext_status_assign
assign CAN_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
// rule RL_wsiS_ext_status_assign
assign CAN_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfrd_pw$whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wmrd_mesgBodyRequest
assign CAN_FIRE_RL_wmrd_mesgBodyRequest =
NOT_wmi_reqF_c_r_46_EQ_2_47_48_AND_wmi_operate_ETC___d290 &&
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
smaCtrl[3:0] == 4'h9) &&
mesgPreRequest ;
assign WILL_FIRE_RL_wmrd_mesgBodyRequest =
CAN_FIRE_RL_wmrd_mesgBodyRequest ;
// rule RL_wmrd_mesgBodyPreRequest
assign CAN_FIRE_RL_wmrd_mesgBodyPreRequest =
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
smaCtrl[3:0] == 4'h9) &&
fabWordsRemain != 14'd0 &&
(fabRespCredit_value ^ 4'h8) > 4'd8 &&
mesgReqOK ;
assign WILL_FIRE_RL_wmrd_mesgBodyPreRequest =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ;
// rule RL_wmrd_mesgBegin
assign CAN_FIRE_RL_wmrd_mesgBegin =
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
smaCtrl[3:0] == 4'h9) &&
!wmi_sThreadBusy_d &&
!wmi_sDataThreadBusy_d &&
unrollCnt == 16'd0 ;
assign WILL_FIRE_RL_wmrd_mesgBegin = CAN_FIRE_RL_wmrd_mesgBegin ;
// rule RL_wci_ctl_op_start
assign CAN_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas ;
assign WILL_FIRE_RL_wci_ctl_op_start =
CAN_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign CAN_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ;
// rule RL_wci_ctrl_OrE
assign CAN_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ;
// rule RL_wci_respF_deq
assign CAN_FIRE_RL_wci_respF_deq = 1'd1 ;
assign WILL_FIRE_RL_wci_respF_deq = 1'd1 ;
// rule RL_wci_sThreadBusy_reg
assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
// rule RL_wci_sFlagReg__dreg_update
assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
// rule RL_wsi_Es_doAlways
assign CAN_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
assign WILL_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
// rule RL_operating_actions
assign CAN_FIRE_RL_operating_actions = wci_cState == 3'd2 ;
assign WILL_FIRE_RL_operating_actions = CAN_FIRE_RL_operating_actions ;
// rule RL_wsiM_update_statusR
assign CAN_FIRE_RL_wsiM_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiM_update_statusR = 1'd1 ;
// rule RL_wsiM_inc_tBusyCount
assign CAN_FIRE_RL_wsiM_inc_tBusyCount =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_inc_tBusyCount = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// rule RL_wsiM_reqFifo_deq
assign CAN_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_reqFifo_deq = CAN_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_sThreadBusy_reg
assign CAN_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
// rule RL_wsiM_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsiM_operateD__dreg_update
assign CAN_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
// rule RL_wsiS_update_statusR
assign CAN_FIRE_RL_wsiS_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiS_update_statusR = 1'd1 ;
// rule RL_wsiS_inc_tBusyCount
assign CAN_FIRE_RL_wsiS_inc_tBusyCount =
wsiS_operateD && wsiS_peerIsReady &&
NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 ;
assign WILL_FIRE_RL_wsiS_inc_tBusyCount = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// rule RL_wsiS_reqFifo_enq
assign CAN_FIRE_RL_wsiS_reqFifo_enq =
wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[60:58] == 3'd1 ;
assign WILL_FIRE_RL_wsiS_reqFifo_enq = CAN_FIRE_RL_wsiS_reqFifo_enq ;
// rule RL_wsiS_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsiS_operateD__dreg_update
assign CAN_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
// rule RL_wmwt_messagePushImprecise
assign CAN_FIRE_RL_wmwt_messagePushImprecise =
wmi_reqF_c_r != 2'd2 && wmi_dhF_c_r != 2'd2 &&
wsiS_reqFifo_i_notEmpty__52_AND_wmi_operateD_5_ETC___d165 &&
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
readyToPush &&
impreciseBurst ;
assign WILL_FIRE_RL_wmwt_messagePushImprecise =
MUX_endOfMessage$write_1__PSEL_1 ;
// rule RL_wmwt_messagePushPrecise
assign CAN_FIRE_RL_wmwt_messagePushPrecise =
wmi_dhF_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && wmi_operateD &&
wmi_peerIsReady &&
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
wsiWordsRemain != 12'd0 &&
mesgReqValid &&
preciseBurst ;
assign WILL_FIRE_RL_wmwt_messagePushPrecise =
MUX_wsiWordsRemain$write_1__SEL_2 ;
// rule RL_wmwt_requestPrecise
assign CAN_FIRE_RL_wmwt_requestPrecise =
wmi_reqF_c_r != 2'd2 && wmi_mFlagF_c_r != 2'd2 && wmi_operateD &&
wmi_peerIsReady &&
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
readyToRequest &&
preciseBurst ;
assign WILL_FIRE_RL_wmwt_requestPrecise = MUX_mesgReqValid$write_1__SEL_2 ;
// rule RL_wmwt_messageFinalize
assign CAN_FIRE_RL_wmwt_messageFinalize = MUX_endOfMessage$write_1__SEL_2 ;
assign WILL_FIRE_RL_wmwt_messageFinalize = MUX_endOfMessage$write_1__SEL_2 ;
// rule RL_wmwt_mesgBegin
assign CAN_FIRE_RL_wmwt_mesgBegin =
wsiS_reqFifo$EMPTY_N && wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
!wmi_sThreadBusy_d &&
!wmi_sDataThreadBusy_d &&
!opcode[8] ;
assign WILL_FIRE_RL_wmwt_mesgBegin = MUX_impreciseBurst$write_1__PSEL_2 ;
// rule RL_wmwt_doAbort
assign CAN_FIRE_RL_wmwt_doAbort = MUX_impreciseBurst$write_1__SEL_1 ;
assign WILL_FIRE_RL_wmwt_doAbort = MUX_impreciseBurst$write_1__SEL_1 ;
// rule RL_wci_Es_doAlways_Req
assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
// rule RL_wci_reqF_enq
assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq$wget[59:57] != 3'd0 ;
assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ;
// rule RL_wmrd_mesgBodyResponse
assign CAN_FIRE_RL_wmrd_mesgBodyResponse =
wmi_respF$EMPTY_N && (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
smaCtrl[3:0] == 4'h9) &&
unrollCnt != 16'd0 ;
assign WILL_FIRE_RL_wmrd_mesgBodyResponse =
CAN_FIRE_RL_wmrd_mesgBodyResponse ;
// rule RL_wsipass_doMessagePush
assign CAN_FIRE_RL_wsipass_doMessagePush =
wsiS_reqFifo$EMPTY_N &&
(smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h0 || smaCtrl[3:0] == 4'h3) ;
assign WILL_FIRE_RL_wsipass_doMessagePush =
CAN_FIRE_RL_wsipass_doMessagePush &&
!WILL_FIRE_RL_wmwt_messagePushPrecise &&
!WILL_FIRE_RL_wmwt_messagePushImprecise ;
// rule RL_wci_cfwr
assign CAN_FIRE_RL_wci_cfwr =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfwr_pw$whas ;
assign WILL_FIRE_RL_wci_cfwr =
CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_reqF__updateLevelCounter
assign CAN_FIRE_RL_wci_reqF__updateLevelCounter =
(wci_wciReq$wget[59:57] != 3'd0) != wci_reqF_r_deq$whas ;
assign WILL_FIRE_RL_wci_reqF__updateLevelCounter =
CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// rule RL_wsiM_reqFifo_both
assign CAN_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_x_wire$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_x_wire$whas) &&
CAN_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_both = CAN_FIRE_RL_wsiM_reqFifo_both ;
// rule RL_wsiM_reqFifo_decCtr
assign CAN_FIRE_RL_wsiM_reqFifo_decCtr =
CAN_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = CAN_FIRE_RL_wsiM_reqFifo_decCtr ;
// rule RL_wsiM_reqFifo_incCtr
assign CAN_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_x_wire$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_x_wire$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = CAN_FIRE_RL_wsiM_reqFifo_incCtr ;
// rule RL_wsiS_reqFifo__updateLevelCounter
assign CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsiS_reqFifo_enq != wsiS_reqFifo_r_deq$whas ;
assign WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// rule RL_wmi_Em_doAlways
assign CAN_FIRE_RL_wmi_Em_doAlways = 1'd1 ;
assign WILL_FIRE_RL_wmi_Em_doAlways = 1'd1 ;
// rule RL_mesgPreRequest__dreg_update
assign CAN_FIRE_RL_mesgPreRequest__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_mesgPreRequest__dreg_update = 1'd1 ;
// rule RL_fabRespCredit_accumulate
assign CAN_FIRE_RL_fabRespCredit_accumulate = 1'd1 ;
assign WILL_FIRE_RL_fabRespCredit_accumulate = 1'd1 ;
// rule RL_wci_ctrl_IsO
assign CAN_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ;
// rule RL_wci_ctl_op_complete
assign CAN_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctlAckReg__dreg_update
assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
// rule RL_wci_respF_both
assign CAN_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd2 || wci_respF_x_wire$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ;
// rule RL_wci_respF_decCtr
assign CAN_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ;
// rule RL_wci_respF_incCtr
assign CAN_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd1 || wci_respF_x_wire$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ;
// rule RL_wmi_respAdvance
assign CAN_FIRE_RL_wmi_respAdvance =
wmi_respF$FULL_N && wmi_operateD && wmi_peerIsReady &&
wmi_wmiResponse$wget[33:32] != 2'd0 ;
assign WILL_FIRE_RL_wmi_respAdvance = CAN_FIRE_RL_wmi_respAdvance ;
// rule RL_wmi_dhF_deq
assign CAN_FIRE_RL_wmi_dhF_deq = !wmi_sDataThreadBusy_d ;
assign WILL_FIRE_RL_wmi_dhF_deq = CAN_FIRE_RL_wmi_dhF_deq ;
// rule RL_wmi_reqF_deq
assign CAN_FIRE_RL_wmi_reqF_deq = !wmi_sThreadBusy_d ;
assign WILL_FIRE_RL_wmi_reqF_deq = CAN_FIRE_RL_wmi_reqF_deq ;
// rule RL_wmi_peerIsReady__dreg_update
assign CAN_FIRE_RL_wmi_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wmi_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wmi_operateD__dreg_update
assign CAN_FIRE_RL_wmi_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wmi_operateD__dreg_update = 1'd1 ;
// rule RL_wmi_sDataThreadBusy_d__dreg_update
assign CAN_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update = 1'd1 ;
// rule RL_wmi_sThreadBusy_d__dreg_update
assign CAN_FIRE_RL_wmi_sThreadBusy_d__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wmi_sThreadBusy_d__dreg_update = 1'd1 ;
// rule RL_wmi_dhF_decCtr
assign CAN_FIRE_RL_wmi_dhF_decCtr =
wmi_dhF_dequeueing$whas && !wmi_dhF_enqueueing$whas ;
assign WILL_FIRE_RL_wmi_dhF_decCtr = CAN_FIRE_RL_wmi_dhF_decCtr ;
// rule RL_wmi_dhF_both
assign CAN_FIRE_RL_wmi_dhF_both =
((wmi_dhF_c_r == 2'd1) ?
wmi_dhF_enqueueing$whas :
wmi_dhF_c_r != 2'd2 || wmi_dhF_enqueueing$whas) &&
wmi_dhF_dequeueing$whas &&
wmi_dhF_enqueueing$whas ;
assign WILL_FIRE_RL_wmi_dhF_both = CAN_FIRE_RL_wmi_dhF_both ;
// rule RL_wmi_dhF_incCtr
assign CAN_FIRE_RL_wmi_dhF_incCtr =
((wmi_dhF_c_r == 2'd0) ?
wmi_dhF_enqueueing$whas :
wmi_dhF_c_r != 2'd1 || wmi_dhF_enqueueing$whas) &&
wmi_dhF_enqueueing$whas &&
!wmi_dhF_dequeueing$whas ;
assign WILL_FIRE_RL_wmi_dhF_incCtr = CAN_FIRE_RL_wmi_dhF_incCtr ;
// rule RL_wmi_mFlagF_both
assign CAN_FIRE_RL_wmi_mFlagF_both =
((wmi_mFlagF_c_r == 2'd1) ?
wmi_mFlagF_enqueueing$whas :
wmi_mFlagF_c_r != 2'd2 || wmi_mFlagF_enqueueing$whas) &&
wmi_mFlagF_dequeueing$whas &&
wmi_mFlagF_enqueueing$whas ;
assign WILL_FIRE_RL_wmi_mFlagF_both = CAN_FIRE_RL_wmi_mFlagF_both ;
// rule RL_wmi_mFlagF_decCtr
assign CAN_FIRE_RL_wmi_mFlagF_decCtr =
wmi_mFlagF_dequeueing$whas && !wmi_mFlagF_enqueueing$whas ;
assign WILL_FIRE_RL_wmi_mFlagF_decCtr = CAN_FIRE_RL_wmi_mFlagF_decCtr ;
// rule RL_wmi_mFlagF_incCtr
assign CAN_FIRE_RL_wmi_mFlagF_incCtr =
((wmi_mFlagF_c_r == 2'd0) ?
wmi_mFlagF_enqueueing$whas :
wmi_mFlagF_c_r != 2'd1 || wmi_mFlagF_enqueueing$whas) &&
wmi_mFlagF_enqueueing$whas &&
!wmi_mFlagF_dequeueing$whas ;
assign WILL_FIRE_RL_wmi_mFlagF_incCtr = CAN_FIRE_RL_wmi_mFlagF_incCtr ;
// rule RL_wmi_reqF_both
assign CAN_FIRE_RL_wmi_reqF_both =
((wmi_reqF_c_r == 2'd1) ?
wmi_reqF_x_wire$whas :
wmi_reqF_c_r != 2'd2 || wmi_reqF_x_wire$whas) &&
wmi_reqF_dequeueing$whas &&
wmi_reqF_enqueueing$whas ;
assign WILL_FIRE_RL_wmi_reqF_both = CAN_FIRE_RL_wmi_reqF_both ;
// rule RL_wmi_reqF_incCtr
assign CAN_FIRE_RL_wmi_reqF_incCtr =
((wmi_reqF_c_r == 2'd0) ?
wmi_reqF_x_wire$whas :
wmi_reqF_c_r != 2'd1 || wmi_reqF_x_wire$whas) &&
wmi_reqF_enqueueing$whas &&
!wmi_reqF_dequeueing$whas ;
assign WILL_FIRE_RL_wmi_reqF_incCtr = CAN_FIRE_RL_wmi_reqF_incCtr ;
// rule RL_wmi_reqF_decCtr
assign CAN_FIRE_RL_wmi_reqF_decCtr =
wmi_reqF_dequeueing$whas && !wmi_reqF_enqueueing$whas ;
assign WILL_FIRE_RL_wmi_reqF_decCtr = CAN_FIRE_RL_wmi_reqF_decCtr ;
// inputs to muxes for submodule ports
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
assign MUX_wci_illegalEdge$write_1__VAL_2 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_endOfMessage$write_1__SEL_2 =
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
mesgLength[14] &&
!doAbort &&
(preciseBurst && wsiWordsRemain == 12'd0 ||
impreciseBurst && endOfMessage) ;
assign MUX_impreciseBurst$write_1__SEL_1 =
wci_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
doAbort ;
assign MUX_mesgLength$write_1__VAL_2 =
(wsiS_reqFifo$D_OUT[11:8] == 4'd0) ?
15'd16384 :
{ 1'd1, wsiS_reqFifo$D_OUT[55:44], 2'd0 } ;
assign MUX_mesgLengthSoFar$write_1__VAL_2 = mesgLengthSoFar + 14'd1 ;
assign MUX_opcode$write_1__VAL_2 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ;
assign MUX_wsiWordsRemain$write_1__VAL_2 = wsiWordsRemain - 12'd1 ;
assign MUX_unrollCnt$write_1__VAL_1 =
(wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : wmi_sFlagReg[17:2] ;
assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ;
assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, x_data__h15447 } ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_0$write_1__VAL_1 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
wci_respF_q_1 ;
assign MUX_wci_respF_q_1$write_1__VAL_1 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_mesgLength$write_1__VAL_4 = { 1'd1, mlp1B__h16631 } ;
assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 =
{ 3'd1,
unrollCnt == 16'd1,
!smaCtrl[5],
x_burstLength__h18561,
wmi_respF$D_OUT[31:0],
x_byteEn__h18563,
thisMesg[23:16] } ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 ?
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 :
wsiS_reqFifo$D_OUT ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
61'h00000AAAAAAAAA00 ;
assign MUX_endOfMessage$write_1__PSEL_1 =
CAN_FIRE_RL_wmwt_messagePushImprecise &&
!WILL_FIRE_RL_wmwt_messageFinalize ;
assign MUX_endOfMessage$write_1__SEL_1 =
WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 ;
assign MUX_mesgReqValid$write_1__SEL_2 =
CAN_FIRE_RL_wmwt_requestPrecise &&
!WILL_FIRE_RL_wmwt_messagePushImprecise ;
assign MUX_wsiWordsRemain$write_1__SEL_2 =
CAN_FIRE_RL_wmwt_messagePushPrecise &&
!WILL_FIRE_RL_wmwt_messagePushImprecise &&
!WILL_FIRE_RL_wmwt_messageFinalize ;
assign MUX_impreciseBurst$write_1__PSEL_2 =
CAN_FIRE_RL_wmwt_mesgBegin &&
!WILL_FIRE_RL_wmwt_messagePushPrecise &&
!WILL_FIRE_RL_wmwt_messagePushImprecise &&
!WILL_FIRE_RL_wmwt_messageFinalize ;
assign MUX_impreciseBurst$write_1__SEL_2 =
WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56] ;
assign MUX_mesgLength$write_1__SEL_2 =
WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56] ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_lastMesg$write_1__SEL_2 =
WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wmwt_requestPrecise ;
assign MUX_mesgCount$write_1__SEL_1 =
WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ;
assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_2 =
WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18886 ;
assign MUX_fabRespCredit_value$write_1__VAL_2 =
fabRespCredit_value +
(CAN_FIRE_RL_wmrd_mesgBodyRequest ? b__h13937 : 4'd0) +
(CAN_FIRE_RL_wmrd_mesgBodyResponse ? 4'd1 : 4'd0) ;
assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ;
assign MUX_fabWordsRemain$write_1__VAL_1 =
(wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : wmi_sFlagReg[15:2] ;
assign MUX_mesgCount$write_1__VAL_2 = mesgCount + 32'd1 ;
assign MUX_mesgReqAddr$write_1__VAL_2 =
mesgReqAddr + { fabWordsCurReq[11:0], 2'd0 } ;
assign MUX_thisMesg$write_1__VAL_2 =
{ mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ;
assign MUX_thisMesg$write_1__VAL_1 =
{ mesgCount[7:0], mesgMetaF_opcode__h16809, x_length__h17088 } ;
assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r - 2'd1 ;
assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r + 2'd1 ;
assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r - 2'd1 ;
assign MUX_wmi_dhF_x_wire$wset_1__VAL_1 =
{ 1'd1,
wsiWordsRemain == 12'd1,
wsiS_reqFifo$D_OUT[43:12],
4'd0 } ;
assign MUX_wmi_dhF_x_wire$wset_1__VAL_2 =
{ 1'd1, x__h16715, wsiS_reqFifo$D_OUT[43:12], 4'd0 } ;
assign MUX_wmi_dhF_q_0$write_1__VAL_2 =
WILL_FIRE_RL_wmwt_messagePushPrecise ?
MUX_wmi_dhF_x_wire$wset_1__VAL_1 :
MUX_wmi_dhF_x_wire$wset_1__VAL_2 ;
assign MUX_wmi_dhF_q_0$write_1__VAL_1 =
(wmi_dhF_c_r == 2'd1) ?
MUX_wmi_dhF_q_0$write_1__VAL_2 :
wmi_dhF_q_1 ;
assign MUX_wmi_dhF_q_1$write_1__VAL_1 =
(wmi_dhF_c_r == 2'd2) ?
MUX_wmi_dhF_q_0$write_1__VAL_2 :
38'h0AAAAAAAAA ;
assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r + 2'd1 ;
assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_3 =
{ mesgMetaF_opcode__h16809, mesgMetaF_length__h17725 } ;
assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_1 =
{ mesgMetaF_opcode__h16809, mesgMetaF_length__h16810 } ;
assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 =
(wmi_mFlagF_c_r == 2'd1) ? value__h6065 : wmi_mFlagF_q_1 ;
assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 =
(wmi_mFlagF_c_r == 2'd2) ? value__h6065 : 32'd0 ;
assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r - 2'd1 ;
assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r + 2'd1 ;
assign MUX_wmi_reqF_x_wire$wset_1__VAL_1 = { 20'd229376, bl__h17582 } ;
assign MUX_wmi_reqF_x_wire$wset_1__VAL_2 =
{ 4'd5, x__h18886, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ;
assign MUX_wmi_reqF_x_wire$wset_1__VAL_3 =
{ 4'd3, x__h16715, 1'b0, addr__h16647, 12'd1 } ;
always@(WILL_FIRE_RL_wmwt_requestPrecise or
MUX_wmi_reqF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wmrd_mesgBodyRequest or
MUX_wmi_reqF_x_wire$wset_1__VAL_2 or
WILL_FIRE_RL_wmwt_messagePushImprecise or
MUX_wmi_reqF_x_wire$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmwt_requestPrecise:
MUX_wmi_reqF_q_0$write_1__VAL_2 = MUX_wmi_reqF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wmrd_mesgBodyRequest:
MUX_wmi_reqF_q_0$write_1__VAL_2 = MUX_wmi_reqF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wmwt_messagePushImprecise:
MUX_wmi_reqF_q_0$write_1__VAL_2 = MUX_wmi_reqF_x_wire$wset_1__VAL_3;
default: MUX_wmi_reqF_q_0$write_1__VAL_2 =
32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wmi_reqF_q_0$write_1__VAL_1 =
(wmi_reqF_c_r == 2'd1) ?
MUX_wmi_reqF_q_0$write_1__VAL_2 :
wmi_reqF_q_1 ;
assign MUX_wmi_reqF_q_1$write_1__VAL_1 =
(wmi_reqF_c_r == 2'd2) ?
MUX_wmi_reqF_q_0$write_1__VAL_2 :
32'd178956970 ;
assign MUX_wmi_reqF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ;
assign MUX_wmi_reqF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 ;
assign MUX_wmi_mFlagF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ;
assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ;
assign MUX_wmi_dhF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 ;
assign MUX_wmi_dhF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 ;
// inlined wires
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd1 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_respF_x_wire$whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wsiS_wsiReq$wget =
{ wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo } ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_reqFifo_r_enq$whas = CAN_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$whas = wsiS1_MReset_n ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_reqFifo_dequeueing$whas = CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_sThreadBusy_pw$whas = wsiM1_SThreadBusy ;
assign wsiM_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM1_SReset_n ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
assign wsi_Es_mCmd_w$wget = wsiS1_MCmd ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mReqLast_w$whas = wsiS1_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ;
assign wsi_Es_mBurstLength_w$wget = wsiS1_MBurstLength ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS1_MData ;
assign wsi_Es_mByteEn_w$wget = wsiS1_MByteEn ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$wget = wsiS1_MReqInfo ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ;
assign wsiS_reqFifo_r_deq$whas =
WILL_FIRE_RL_wsipass_doMessagePush ||
WILL_FIRE_RL_wmwt_messagePushPrecise ||
WILL_FIRE_RL_wmwt_messagePushImprecise ;
assign wsiM_reqFifo_enqueueing$whas =
(WILL_FIRE_RL_wsipass_doMessagePush ||
WILL_FIRE_RL_wmrd_mesgBodyResponse) &&
!smaCtrl[4] ;
assign wsiM_reqFifo_x_wire$whas =
WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ||
WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ;
assign wmi_reqF_enqueueing$whas =
WILL_FIRE_RL_wmrd_mesgBodyRequest ||
WILL_FIRE_RL_wmwt_requestPrecise ||
WILL_FIRE_RL_wmwt_messagePushImprecise ;
assign wmi_reqF_x_wire$wget = MUX_wmi_reqF_q_0$write_1__VAL_2 ;
assign wmi_reqF_x_wire$whas =
WILL_FIRE_RL_wmwt_requestPrecise ||
WILL_FIRE_RL_wmrd_mesgBodyRequest ||
WILL_FIRE_RL_wmwt_messagePushImprecise ;
assign wmi_reqF_dequeueing$whas =
WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ;
assign wmi_mFlagF_x_wire$wget = value__h6065 ;
assign wmi_mFlagF_enqueueing$whas =
WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 ||
WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18886 ||
WILL_FIRE_RL_wmwt_requestPrecise ;
assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ;
assign wmi_mFlagF_dequeueing$whas =
WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_q_0[27] &&
wmi_mFlagF_c_r != 2'd0 ;
assign wmi_dhF_enqueueing$whas =
WILL_FIRE_RL_wmwt_messagePushPrecise ||
WILL_FIRE_RL_wmwt_messagePushImprecise ;
assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ;
assign wmi_dhF_x_wire$whas = wmi_dhF_enqueueing$whas ;
assign wmi_dhF_dequeueing$whas =
WILL_FIRE_RL_wmi_dhF_deq && wmi_dhF_c_r != 2'd0 ;
assign wmi_wmiResponse$wget = { wmiM_SResp, wmiM_SData } ;
assign wmi_wmiResponse$whas = 1'd1 ;
assign wmi_sThreadBusy_d_1$wget = 1'd1 ;
assign wmi_sThreadBusy_d_1$whas = wmiM_SThreadBusy ;
assign wmi_sDataThreadBusy_d_1$wget = 1'd1 ;
assign wmi_operateD_1$wget = 1'd1 ;
assign wmi_sDataThreadBusy_d_1$whas = wmiM_SDataThreadBusy ;
assign wmi_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wmi_peerIsReady_1$wget = 1'd1 ;
assign wmi_peerIsReady_1$whas = wmiM_SReset_n ;
assign fabRespCredit_acc_v1$wget = b__h13937 ;
assign fabRespCredit_acc_v2$wget = 4'd1 ;
assign fabRespCredit_acc_v1$whas = CAN_FIRE_RL_wmrd_mesgBodyRequest ;
assign fabRespCredit_acc_v2$whas = CAN_FIRE_RL_wmrd_mesgBodyResponse ;
assign mesgPreRequest_1$whas = WILL_FIRE_RL_wmrd_mesgBodyPreRequest ;
assign mesgPreRequest_1$wget = 1'd1 ;
assign wmi_Em_sResp_w$wget = wmiM_SResp ;
assign wmi_Em_sData_w$wget = wmiM_SData ;
assign wmi_Em_sResp_w$whas = 1'd1 ;
assign wmi_Em_sData_w$whas = 1'd1 ;
// register abortCount
assign abortCount$D_IN = abortCount + 32'd1 ;
assign abortCount$EN = MUX_impreciseBurst$write_1__SEL_1 ;
// register doAbort
assign doAbort$D_IN = 1'd0 ;
assign doAbort$EN = MUX_impreciseBurst$write_1__SEL_1 ;
// register endOfMessage
assign endOfMessage$D_IN = MUX_endOfMessage$write_1__SEL_1 ;
assign endOfMessage$EN =
WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 ||
WILL_FIRE_RL_wmwt_messageFinalize ;
// register errCount
assign errCount$D_IN = errCount + 32'd1 ;
assign errCount$EN =
WILL_FIRE_RL_wmwt_messagePushImprecise &&
wsiS_reqFifo$D_OUT[43:12] != valExpect &&
(!x__h16715 || wsiS_reqFifo$D_OUT[11:8] != 4'd0) ;
// register fabRespCredit_value
assign fabRespCredit_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
4'd2 :
MUX_fabRespCredit_value$write_1__VAL_2 ;
assign fabRespCredit_value$EN = 1'b1 ;
// register fabWordsCurReq
assign fabWordsCurReq$D_IN =
(fabWordsRemain <= b__h19086) ? fabWordsRemain : b__h19086 ;
assign fabWordsCurReq$EN = WILL_FIRE_RL_wmrd_mesgBodyPreRequest ;
// register fabWordsRemain
assign fabWordsRemain$D_IN =
WILL_FIRE_RL_wmrd_mesgBegin ?
MUX_fabWordsRemain$write_1__VAL_1 :
MUX_fabWordsRemain$write_1__VAL_2 ;
assign fabWordsRemain$EN =
WILL_FIRE_RL_wmrd_mesgBegin ||
WILL_FIRE_RL_wmrd_mesgBodyRequest ;
// register firstMsgReq
assign firstMsgReq$EN = 1'b0 ;
assign firstMsgReq$D_IN = 1'b0 ;
// register impreciseBurst
always@(WILL_FIRE_RL_wmwt_doAbort or
MUX_impreciseBurst$write_1__SEL_2 or
WILL_FIRE_RL_wmwt_messageFinalize)
case (1'b1)
WILL_FIRE_RL_wmwt_doAbort: impreciseBurst$D_IN = 1'd0;
MUX_impreciseBurst$write_1__SEL_2: impreciseBurst$D_IN = 1'd1;
WILL_FIRE_RL_wmwt_messageFinalize: impreciseBurst$D_IN = 1'd0;
default: impreciseBurst$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign impreciseBurst$EN =
WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56] ||
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wmwt_doAbort ;
// register lastMesg
assign lastMesg$D_IN =
(MUX_endOfMessage$write_1__SEL_1 ||
MUX_lastMesg$write_1__SEL_2) ?
thisMesg :
32'hFEFEFFFE ;
assign lastMesg$EN =
WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 ||
WILL_FIRE_RL_wmrd_mesgBegin ||
WILL_FIRE_RL_wmwt_requestPrecise ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register mesgCount
assign mesgCount$EN =
WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ||
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wci_ctrl_IsO ;
always@(MUX_mesgCount$write_1__SEL_1 or
MUX_mesgCount$write_1__VAL_2 or
WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO)
begin
case (1'b1) // synopsys parallel_case
MUX_mesgCount$write_1__SEL_1:
mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2;
WILL_FIRE_RL_wmwt_messageFinalize:
mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2;
WILL_FIRE_RL_wci_ctrl_IsO: mesgCount$D_IN = 32'd0;
default: mesgCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
// register mesgLength
always@(WILL_FIRE_RL_wmwt_doAbort or
MUX_mesgLength$write_1__SEL_2 or
MUX_mesgLength$write_1__VAL_2 or
WILL_FIRE_RL_wmwt_messageFinalize or
MUX_endOfMessage$write_1__SEL_1 or MUX_mesgLength$write_1__VAL_4)
case (1'b1)
WILL_FIRE_RL_wmwt_doAbort: mesgLength$D_IN = 15'd10922;
MUX_mesgLength$write_1__SEL_2:
mesgLength$D_IN = MUX_mesgLength$write_1__VAL_2;
WILL_FIRE_RL_wmwt_messageFinalize: mesgLength$D_IN = 15'd10922;
MUX_endOfMessage$write_1__SEL_1:
mesgLength$D_IN = MUX_mesgLength$write_1__VAL_4;
default: mesgLength$D_IN = 15'b010101010101010 /* unspecified value */ ;
endcase
assign mesgLength$EN =
WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 ||
WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56] ||
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wmwt_doAbort ;
// register mesgLengthSoFar
assign mesgLengthSoFar$D_IN =
MUX_impreciseBurst$write_1__SEL_2 ?
14'd0 :
MUX_mesgLengthSoFar$write_1__VAL_2 ;
assign mesgLengthSoFar$EN =
WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56] ||
WILL_FIRE_RL_wmwt_messagePushImprecise ;
// register mesgPreRequest
assign mesgPreRequest$D_IN = WILL_FIRE_RL_wmrd_mesgBodyPreRequest ;
assign mesgPreRequest$EN = 1'd1 ;
// register mesgReqAddr
assign mesgReqAddr$D_IN =
WILL_FIRE_RL_wmrd_mesgBegin ?
14'd0 :
MUX_mesgReqAddr$write_1__VAL_2 ;
assign mesgReqAddr$EN =
WILL_FIRE_RL_wmrd_mesgBodyRequest ||
WILL_FIRE_RL_wmrd_mesgBegin ;
// register mesgReqOK
assign mesgReqOK$D_IN =
WILL_FIRE_RL_wmrd_mesgBodyResponse ||
WILL_FIRE_RL_wmrd_mesgBegin ;
assign mesgReqOK$EN =
WILL_FIRE_RL_wmrd_mesgBodyPreRequest ||
WILL_FIRE_RL_wmrd_mesgBegin ||
WILL_FIRE_RL_wmrd_mesgBodyResponse ;
// register mesgReqValid
assign mesgReqValid$D_IN = !WILL_FIRE_RL_wmwt_messageFinalize ;
assign mesgReqValid$EN =
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wmwt_requestPrecise ;
// register opcode
always@(WILL_FIRE_RL_wmwt_doAbort or
WILL_FIRE_RL_wmwt_mesgBegin or
MUX_opcode$write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize)
case (1'b1)
WILL_FIRE_RL_wmwt_doAbort: opcode$D_IN = 9'd170;
WILL_FIRE_RL_wmwt_mesgBegin: opcode$D_IN = MUX_opcode$write_1__VAL_2;
WILL_FIRE_RL_wmwt_messageFinalize: opcode$D_IN = 9'd170;
default: opcode$D_IN = 9'b010101010 /* unspecified value */ ;
endcase
assign opcode$EN =
WILL_FIRE_RL_wmwt_mesgBegin ||
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wmwt_doAbort ;
// register preciseBurst
always@(WILL_FIRE_RL_wmwt_doAbort or
MUX_mesgLength$write_1__SEL_2 or WILL_FIRE_RL_wmwt_messageFinalize)
case (1'b1)
WILL_FIRE_RL_wmwt_doAbort: preciseBurst$D_IN = 1'd0;
MUX_mesgLength$write_1__SEL_2: preciseBurst$D_IN = 1'd1;
WILL_FIRE_RL_wmwt_messageFinalize: preciseBurst$D_IN = 1'd0;
default: preciseBurst$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign preciseBurst$EN =
WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56] ||
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wmwt_doAbort ;
// register readyToPush
always@(WILL_FIRE_RL_wmwt_doAbort or
MUX_impreciseBurst$write_1__SEL_2 or
MUX_endOfMessage$write_1__SEL_1)
case (1'b1)
WILL_FIRE_RL_wmwt_doAbort: readyToPush$D_IN = 1'd0;
MUX_impreciseBurst$write_1__SEL_2: readyToPush$D_IN = 1'd1;
MUX_endOfMessage$write_1__SEL_1: readyToPush$D_IN = 1'd0;
default: readyToPush$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign readyToPush$EN =
WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 ||
WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56] ||
WILL_FIRE_RL_wmwt_doAbort ;
// register readyToRequest
assign readyToRequest$D_IN = MUX_mesgLength$write_1__SEL_2 ;
assign readyToRequest$EN =
WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56] ||
WILL_FIRE_RL_wmwt_requestPrecise ;
// register smaCtrl
assign smaCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign smaCtrl$EN = WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h0 ;
// register thisMesg
always@(MUX_endOfMessage$write_1__SEL_1 or
MUX_thisMesg$write_1__VAL_1 or
WILL_FIRE_RL_wmrd_mesgBegin or
MUX_thisMesg$write_1__VAL_2 or
WILL_FIRE_RL_wmwt_requestPrecise or WILL_FIRE_RL_wci_ctrl_IsO)
begin
case (1'b1) // synopsys parallel_case
MUX_endOfMessage$write_1__SEL_1:
thisMesg$D_IN = MUX_thisMesg$write_1__VAL_1;
WILL_FIRE_RL_wmrd_mesgBegin:
thisMesg$D_IN = MUX_thisMesg$write_1__VAL_2;
WILL_FIRE_RL_wmwt_requestPrecise:
thisMesg$D_IN = MUX_thisMesg$write_1__VAL_1;
WILL_FIRE_RL_wci_ctrl_IsO: thisMesg$D_IN = 32'hFEFEFFFE;
default: thisMesg$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign thisMesg$EN =
WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 ||
WILL_FIRE_RL_wmrd_mesgBegin ||
WILL_FIRE_RL_wmwt_requestPrecise ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register unrollCnt
assign unrollCnt$EN =
WILL_FIRE_RL_wmrd_mesgBegin ||
WILL_FIRE_RL_wmrd_mesgBodyResponse ;
assign unrollCnt$D_IN =
WILL_FIRE_RL_wmrd_mesgBegin ?
MUX_unrollCnt$write_1__VAL_1 :
MUX_unrollCnt$write_1__VAL_2 ;
// register valExpect
assign valExpect$D_IN = valExpect + 32'd1 ;
assign valExpect$EN =
WILL_FIRE_RL_wmwt_messagePushImprecise &&
(!x__h16715 || wsiS_reqFifo$D_OUT[11:8] != 4'd0) ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
!MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_2 ;
assign wci_illegalEdge$EN =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ||
MUX_wci_illegalEdge$write_1__SEL_2 ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[59:57] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_decCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ;
// register wci_respF_q_0
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_1 or
MUX_wci_respF_q_0$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
MUX_wci_respF_q_0$write_1__SEL_2:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
// register wci_respF_q_1
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_1 or
MUX_wci_respF_q_1$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1;
MUX_wci_respF_q_1$write_1__SEL_2:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wmi_busyWithMessage
assign wmi_busyWithMessage$D_IN = 1'b0 ;
assign wmi_busyWithMessage$EN = 1'b0 ;
// register wmi_dhF_c_r
assign wmi_dhF_c_r$D_IN =
WILL_FIRE_RL_wmi_dhF_decCtr ?
MUX_wmi_dhF_c_r$write_1__VAL_1 :
MUX_wmi_dhF_c_r$write_1__VAL_2 ;
assign wmi_dhF_c_r$EN =
WILL_FIRE_RL_wmi_dhF_decCtr || WILL_FIRE_RL_wmi_dhF_incCtr ;
// register wmi_dhF_q_0
always@(WILL_FIRE_RL_wmi_dhF_both or
MUX_wmi_dhF_q_0$write_1__VAL_1 or
MUX_wmi_dhF_q_0$write_1__SEL_2 or
MUX_wmi_dhF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_dhF_both:
wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1;
MUX_wmi_dhF_q_0$write_1__SEL_2:
wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_0$D_IN = wmi_dhF_q_1;
default: wmi_dhF_q_0$D_IN = 38'h2AAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_dhF_q_0$EN =
WILL_FIRE_RL_wmi_dhF_both ||
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 ||
WILL_FIRE_RL_wmi_dhF_decCtr ;
// register wmi_dhF_q_1
always@(WILL_FIRE_RL_wmi_dhF_both or
MUX_wmi_dhF_q_1$write_1__VAL_1 or
MUX_wmi_dhF_q_1$write_1__SEL_2 or
MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_dhF_both:
wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_1;
MUX_wmi_dhF_q_1$write_1__SEL_2:
wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1$D_IN = 38'h0AAAAAAAAA;
default: wmi_dhF_q_1$D_IN = 38'h2AAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_dhF_q_1$EN =
WILL_FIRE_RL_wmi_dhF_both ||
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 ||
WILL_FIRE_RL_wmi_dhF_decCtr ;
// register wmi_mFlagF_c_r
assign wmi_mFlagF_c_r$D_IN =
WILL_FIRE_RL_wmi_mFlagF_decCtr ?
MUX_wmi_mFlagF_c_r$write_1__VAL_1 :
MUX_wmi_mFlagF_c_r$write_1__VAL_2 ;
assign wmi_mFlagF_c_r$EN =
WILL_FIRE_RL_wmi_mFlagF_decCtr ||
WILL_FIRE_RL_wmi_mFlagF_incCtr ;
// register wmi_mFlagF_q_0
always@(WILL_FIRE_RL_wmi_mFlagF_both or
MUX_wmi_mFlagF_q_0$write_1__VAL_1 or
MUX_wmi_mFlagF_q_0$write_1__SEL_2 or
value__h6065 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_mFlagF_both:
wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1;
MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6065;
WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1;
default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_mFlagF_q_0$EN =
WILL_FIRE_RL_wmi_mFlagF_both ||
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ||
WILL_FIRE_RL_wmi_mFlagF_decCtr ;
// register wmi_mFlagF_q_1
always@(WILL_FIRE_RL_wmi_mFlagF_both or
MUX_wmi_mFlagF_q_1$write_1__VAL_1 or
MUX_wmi_mFlagF_q_1$write_1__SEL_2 or
value__h6065 or WILL_FIRE_RL_wmi_mFlagF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_mFlagF_both:
wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1;
MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6065;
WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0;
default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_mFlagF_q_1$EN =
WILL_FIRE_RL_wmi_mFlagF_both ||
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ||
WILL_FIRE_RL_wmi_mFlagF_decCtr ;
// register wmi_operateD
assign wmi_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wmi_operateD$EN = 1'd1 ;
// register wmi_peerIsReady
assign wmi_peerIsReady$D_IN = wmiM_SReset_n ;
assign wmi_peerIsReady$EN = 1'd1 ;
// register wmi_reqF_c_r
assign wmi_reqF_c_r$D_IN =
WILL_FIRE_RL_wmi_reqF_decCtr ?
MUX_wmi_reqF_c_r$write_1__VAL_1 :
MUX_wmi_reqF_c_r$write_1__VAL_2 ;
assign wmi_reqF_c_r$EN =
WILL_FIRE_RL_wmi_reqF_decCtr || WILL_FIRE_RL_wmi_reqF_incCtr ;
// register wmi_reqF_q_0
always@(WILL_FIRE_RL_wmi_reqF_both or
MUX_wmi_reqF_q_0$write_1__VAL_1 or
MUX_wmi_reqF_q_0$write_1__SEL_2 or
MUX_wmi_reqF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wmi_reqF_decCtr or wmi_reqF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqF_both:
wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_1;
MUX_wmi_reqF_q_0$write_1__SEL_2:
wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmi_reqF_decCtr: wmi_reqF_q_0$D_IN = wmi_reqF_q_1;
default: wmi_reqF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_reqF_q_0$EN =
WILL_FIRE_RL_wmi_reqF_both ||
WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ||
WILL_FIRE_RL_wmi_reqF_decCtr ;
// register wmi_reqF_q_1
always@(WILL_FIRE_RL_wmi_reqF_both or
MUX_wmi_reqF_q_1$write_1__VAL_1 or
MUX_wmi_reqF_q_1$write_1__SEL_2 or
MUX_wmi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqF_both:
wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_1$write_1__VAL_1;
MUX_wmi_reqF_q_1$write_1__SEL_2:
wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmi_reqF_decCtr: wmi_reqF_q_1$D_IN = 32'd178956970;
default: wmi_reqF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_reqF_q_1$EN =
WILL_FIRE_RL_wmi_reqF_both ||
WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 ||
WILL_FIRE_RL_wmi_reqF_decCtr ;
// register wmi_sDataThreadBusy_d
assign wmi_sDataThreadBusy_d$D_IN = wmiM_SDataThreadBusy ;
assign wmi_sDataThreadBusy_d$EN = 1'd1 ;
// register wmi_sFlagReg
assign wmi_sFlagReg$D_IN = wmiM_SFlag ;
assign wmi_sFlagReg$EN = 1'd1 ;
// register wmi_sThreadBusy_d
assign wmi_sThreadBusy_d$D_IN = wmiM_SThreadBusy ;
assign wmi_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
wsiM_burstKind == 2'd1 && wsiM_reqFifo_q_0[57] ||
wsiM_burstKind == 2'd2 && wsiM_reqFifo_q_0[55:44] == 12'd1) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[55:44] == 12'd1 ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM1_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
MUX_wsiM_reqFifo_q_0$write_1__SEL_2:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
MUX_wsiM_reqFifo_q_1$write_1__SEL_2:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset$VAL,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
wsiS_burstKind == 2'd1 && wsiS_wsiReq$wget[57] ||
wsiS_burstKind == 2'd2 && wsiS_wsiReq$wget[55:44] == 12'd1) ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'd1 ;
assign wsiS_errorSticky$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && !wsiS_reqFifo$FULL_N ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[55:44] == 12'd1 ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS1_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
CAN_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// register wsiS_statusR
assign wsiS_statusR$EN = 1'd1 ;
assign wsiS_statusR$D_IN =
{ wsiS_isReset$VAL,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 ||
wsiS_isReset$VAL ||
!wsiS_operateD ||
!wsiS_peerIsReady,
1'd0,
wsiS_trafficSticky } ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = CAN_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiWordsRemain
assign wsiWordsRemain$D_IN =
MUX_mesgLength$write_1__SEL_2 ?
wsiS_reqFifo$D_OUT[55:44] :
MUX_wsiWordsRemain$write_1__VAL_2 ;
assign wsiWordsRemain$EN =
WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56] ||
WILL_FIRE_RL_wmwt_messagePushPrecise ;
// register zeroLengthMesg
assign zeroLengthMesg$D_IN = wsiS_reqFifo$D_OUT[11:8] == 4'd0 ;
assign zeroLengthMesg$EN = MUX_mesgLength$write_1__SEL_2 ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$ENQ = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wmi_respF
assign wmi_respF$D_IN = wmi_wmiResponse$wget ;
assign wmi_respF$DEQ = CAN_FIRE_RL_wmrd_mesgBodyResponse ;
assign wmi_respF$ENQ = CAN_FIRE_RL_wmi_respAdvance ;
assign wmi_respF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$ENQ = CAN_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo$CLR = 1'b0 ;
assign wsiS_reqFifo$DEQ = wsiS_reqFifo_r_deq$whas ;
// remaining internal signals
assign IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 =
mesgLength[14] ? mesgLength[13:0] : 14'd0 ;
assign NOT_wmi_reqF_c_r_46_EQ_2_47_48_AND_wmi_operate_ETC___d290 =
wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady &&
(!x__h18886 || wmi_mFlagF_c_r != 2'd2) ;
assign NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 =
wsiS_reqFifo_countReg > 2'd1 ;
assign addr__h16647 = { mesgLengthSoFar[11:0], 2'd0 } ;
assign b__h13937 = -fabWordsCurReq[3:0] ;
assign b__h19086 = { {10{fabRespCredit_value[3]}}, fabRespCredit_value } ;
assign bl__h17582 =
zeroLengthMesg ?
12'd1 :
IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753[13:2] ;
assign mesgMetaF_length__h16810 = { 10'd0, mlp1B__h16631 } ;
assign mesgMetaF_length__h17725 =
{ 10'd0,
IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 } ;
assign mesgMetaF_opcode__h16809 = opcode[8] ? opcode[7:0] : 8'd0 ;
assign mlp1B__h16631 = { mlp1__h16630[11:0], 2'd0 } ;
assign mlp1__h16630 = MUX_mesgLengthSoFar$write_1__VAL_2 ;
assign rdat__h15540 = { 16'd0, x__h15543 } ;
assign wsiBurstLength__h18456 =
smaCtrl[5] ? 16'd2 : { 2'd0, thisMesg[15:2] } ;
assign wsiS_reqFifo_i_notEmpty__52_AND_wmi_operateD_5_ETC___d165 =
wsiS_reqFifo$EMPTY_N && wmi_operateD && wmi_peerIsReady &&
(!x__h16715 || wmi_mFlagF_c_r != 2'd2) ;
assign x__h15543 = { wsiS_statusR, wsiM_statusR } ;
assign x__h16715 = wsiS_reqFifo$D_OUT[55:44] == 12'd1 ;
assign x__h18886 = fabWordsRemain == fabWordsCurReq ;
assign x_burstLength__h18561 =
(thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ?
12'd1 :
(smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18456[11:0]) ;
assign x_byteEn__h18563 = (thisMesg[15:0] == 16'd0) ? 4'd0 : 4'd15 ;
assign x_length__h17088 =
{ 2'd0,
IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 } ;
always@(wci_reqF$D_OUT or
smaCtrl or
mesgCount or
abortCount or
thisMesg or
lastMesg or
rdat__h15540 or wsiS_extStatusW$wget or wsiM_extStatusW$wget)
begin
case (wci_reqF$D_OUT[39:32])
8'h0: x_data__h15447 = smaCtrl;
8'h04: x_data__h15447 = mesgCount;
8'h08: x_data__h15447 = abortCount;
8'h10: x_data__h15447 = thisMesg;
8'h14: x_data__h15447 = lastMesg;
8'h18: x_data__h15447 = rdat__h15540;
8'h20: x_data__h15447 = wsiS_extStatusW$wget[95:64];
8'h24: x_data__h15447 = wsiS_extStatusW$wget[63:32];
8'h28: x_data__h15447 = wsiS_extStatusW$wget[31:0];
8'h2C: x_data__h15447 = wsiM_extStatusW$wget[95:64];
8'h30: x_data__h15447 = wsiM_extStatusW$wget[63:32];
8'h34: x_data__h15447 = wsiM_extStatusW$wget[31:0];
default: x_data__h15447 = 32'd0;
endcase
end
always@(MUX_endOfMessage$write_1__SEL_1 or
MUX_wmi_mFlagF_x_wire$wset_1__VAL_1 or
MUX_wmi_mFlagF_x_wire$wset_1__SEL_2 or
WILL_FIRE_RL_wmwt_requestPrecise or
MUX_wmi_mFlagF_x_wire$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_endOfMessage$write_1__SEL_1:
value__h6065 = MUX_wmi_mFlagF_x_wire$wset_1__VAL_1;
MUX_wmi_mFlagF_x_wire$wset_1__SEL_2:
value__h6065 = 32'hAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_wmwt_requestPrecise:
value__h6065 = MUX_wmi_mFlagF_x_wire$wset_1__VAL_3;
default: value__h6065 = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (!wciS0_MReset_n)
begin
abortCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
doAbort <= `BSV_ASSIGNMENT_DELAY 1'd0;
endOfMessage <= `BSV_ASSIGNMENT_DELAY 1'd0;
errCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
fabRespCredit_value <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabWordsRemain <= `BSV_ASSIGNMENT_DELAY 14'd0;
firstMsgReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
impreciseBurst <= `BSV_ASSIGNMENT_DELAY 1'd0;
lastMesg <= `BSV_ASSIGNMENT_DELAY 32'hFEFEFFFE;
mesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
mesgLength <= `BSV_ASSIGNMENT_DELAY 15'd10922;
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY 14'd0;
mesgPreRequest <= `BSV_ASSIGNMENT_DELAY 1'd0;
mesgReqOK <= `BSV_ASSIGNMENT_DELAY 1'd0;
mesgReqValid <= `BSV_ASSIGNMENT_DELAY 1'd0;
opcode <= `BSV_ASSIGNMENT_DELAY 9'd170;
preciseBurst <= `BSV_ASSIGNMENT_DELAY 1'd0;
readyToPush <= `BSV_ASSIGNMENT_DELAY 1'd0;
readyToRequest <= `BSV_ASSIGNMENT_DELAY 1'd0;
smaCtrl <= `BSV_ASSIGNMENT_DELAY smaCtrlInit;
thisMesg <= `BSV_ASSIGNMENT_DELAY 32'hFEFEFFFE;
unrollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
valExpect <= `BSV_ASSIGNMENT_DELAY 32'd0;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'd7;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY 38'h0AAAAAAAAA;
wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY 38'h0AAAAAAAAA;
wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_mFlagF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd178956970;
wmi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd178956970;
wmi_sDataThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_sFlagReg <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiWordsRemain <= `BSV_ASSIGNMENT_DELAY 12'd0;
zeroLengthMesg <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (abortCount$EN)
abortCount <= `BSV_ASSIGNMENT_DELAY abortCount$D_IN;
if (doAbort$EN) doAbort <= `BSV_ASSIGNMENT_DELAY doAbort$D_IN;
if (endOfMessage$EN)
endOfMessage <= `BSV_ASSIGNMENT_DELAY endOfMessage$D_IN;
if (errCount$EN) errCount <= `BSV_ASSIGNMENT_DELAY errCount$D_IN;
if (fabRespCredit_value$EN)
fabRespCredit_value <= `BSV_ASSIGNMENT_DELAY
fabRespCredit_value$D_IN;
if (fabWordsRemain$EN)
fabWordsRemain <= `BSV_ASSIGNMENT_DELAY fabWordsRemain$D_IN;
if (firstMsgReq$EN)
firstMsgReq <= `BSV_ASSIGNMENT_DELAY firstMsgReq$D_IN;
if (impreciseBurst$EN)
impreciseBurst <= `BSV_ASSIGNMENT_DELAY impreciseBurst$D_IN;
if (lastMesg$EN) lastMesg <= `BSV_ASSIGNMENT_DELAY lastMesg$D_IN;
if (mesgCount$EN) mesgCount <= `BSV_ASSIGNMENT_DELAY mesgCount$D_IN;
if (mesgLength$EN)
mesgLength <= `BSV_ASSIGNMENT_DELAY mesgLength$D_IN;
if (mesgLengthSoFar$EN)
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY mesgLengthSoFar$D_IN;
if (mesgPreRequest$EN)
mesgPreRequest <= `BSV_ASSIGNMENT_DELAY mesgPreRequest$D_IN;
if (mesgReqOK$EN) mesgReqOK <= `BSV_ASSIGNMENT_DELAY mesgReqOK$D_IN;
if (mesgReqValid$EN)
mesgReqValid <= `BSV_ASSIGNMENT_DELAY mesgReqValid$D_IN;
if (opcode$EN) opcode <= `BSV_ASSIGNMENT_DELAY opcode$D_IN;
if (preciseBurst$EN)
preciseBurst <= `BSV_ASSIGNMENT_DELAY preciseBurst$D_IN;
if (readyToPush$EN)
readyToPush <= `BSV_ASSIGNMENT_DELAY readyToPush$D_IN;
if (readyToRequest$EN)
readyToRequest <= `BSV_ASSIGNMENT_DELAY readyToRequest$D_IN;
if (smaCtrl$EN) smaCtrl <= `BSV_ASSIGNMENT_DELAY smaCtrl$D_IN;
if (thisMesg$EN) thisMesg <= `BSV_ASSIGNMENT_DELAY thisMesg$D_IN;
if (unrollCnt$EN) unrollCnt <= `BSV_ASSIGNMENT_DELAY unrollCnt$D_IN;
if (valExpect$EN) valExpect <= `BSV_ASSIGNMENT_DELAY valExpect$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wmi_busyWithMessage$EN)
wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY
wmi_busyWithMessage$D_IN;
if (wmi_dhF_c_r$EN)
wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_c_r$D_IN;
if (wmi_dhF_q_0$EN)
wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_0$D_IN;
if (wmi_dhF_q_1$EN)
wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_1$D_IN;
if (wmi_mFlagF_c_r$EN)
wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_c_r$D_IN;
if (wmi_mFlagF_q_0$EN)
wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_q_0$D_IN;
if (wmi_mFlagF_q_1$EN)
wmi_mFlagF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_q_1$D_IN;
if (wmi_operateD$EN)
wmi_operateD <= `BSV_ASSIGNMENT_DELAY wmi_operateD$D_IN;
if (wmi_peerIsReady$EN)
wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmi_peerIsReady$D_IN;
if (wmi_reqF_c_r$EN)
wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_c_r$D_IN;
if (wmi_reqF_q_0$EN)
wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_reqF_q_0$D_IN;
if (wmi_reqF_q_1$EN)
wmi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_reqF_q_1$D_IN;
if (wmi_sDataThreadBusy_d$EN)
wmi_sDataThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wmi_sDataThreadBusy_d$D_IN;
if (wmi_sFlagReg$EN)
wmi_sFlagReg <= `BSV_ASSIGNMENT_DELAY wmi_sFlagReg$D_IN;
if (wmi_sThreadBusy_d$EN)
wmi_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wmi_sThreadBusy_d$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
if (wsiWordsRemain$EN)
wsiWordsRemain <= `BSV_ASSIGNMENT_DELAY wsiWordsRemain$D_IN;
if (zeroLengthMesg$EN)
zeroLengthMesg <= `BSV_ASSIGNMENT_DELAY zeroLengthMesg$D_IN;
end
if (fabWordsCurReq$EN)
fabWordsCurReq <= `BSV_ASSIGNMENT_DELAY fabWordsCurReq$D_IN;
if (mesgReqAddr$EN) mesgReqAddr <= `BSV_ASSIGNMENT_DELAY mesgReqAddr$D_IN;
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
abortCount = 32'hAAAAAAAA;
doAbort = 1'h0;
endOfMessage = 1'h0;
errCount = 32'hAAAAAAAA;
fabRespCredit_value = 4'hA;
fabWordsCurReq = 14'h2AAA;
fabWordsRemain = 14'h2AAA;
firstMsgReq = 1'h0;
impreciseBurst = 1'h0;
lastMesg = 32'hAAAAAAAA;
mesgCount = 32'hAAAAAAAA;
mesgLength = 15'h2AAA;
mesgLengthSoFar = 14'h2AAA;
mesgPreRequest = 1'h0;
mesgReqAddr = 14'h2AAA;
mesgReqOK = 1'h0;
mesgReqValid = 1'h0;
opcode = 9'h0AA;
preciseBurst = 1'h0;
readyToPush = 1'h0;
readyToRequest = 1'h0;
smaCtrl = 32'hAAAAAAAA;
thisMesg = 32'hAAAAAAAA;
unrollCnt = 16'hAAAA;
valExpect = 32'hAAAAAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wmi_busyWithMessage = 1'h0;
wmi_dhF_c_r = 2'h2;
wmi_dhF_q_0 = 38'h2AAAAAAAAA;
wmi_dhF_q_1 = 38'h2AAAAAAAAA;
wmi_mFlagF_c_r = 2'h2;
wmi_mFlagF_q_0 = 32'hAAAAAAAA;
wmi_mFlagF_q_1 = 32'hAAAAAAAA;
wmi_operateD = 1'h0;
wmi_peerIsReady = 1'h0;
wmi_reqF_c_r = 2'h2;
wmi_reqF_q_0 = 32'hAAAAAAAA;
wmi_reqF_q_1 = 32'hAAAAAAAA;
wmi_sDataThreadBusy_d = 1'h0;
wmi_sFlagReg = 32'hAAAAAAAA;
wmi_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiWordsRemain = 12'hAAA;
zeroLengthMesg = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmrd_mesgBegin)
begin
v__h19472 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmrd_mesgBegin)
$display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h",
v__h19472,
mesgCount,
wmi_sFlagReg[23:0],
wmi_sFlagReg[31:24]);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3699 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3699,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/SMAdapter.bsv\", line 298, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_EiI and RL_wci_cfrd fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/SMAdapter.bsv\", line 299, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/SMAdapter.bsv\", line 299, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_cfrd fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmwt_messageFinalize)
begin
v__h16237 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmwt_messageFinalize)
$display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x",
v__h16237,
mesgCount,
IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56])
begin
v__h18178 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56])
$display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x",
v__h18178,
mesgCount,
wsiS_reqFifo$D_OUT[55:44],
wsiS_reqFifo$D_OUT[7:0]);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56])
begin
v__h18255 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56])
$display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x",
v__h18255,
mesgCount);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmwt_doAbort)
begin
v__h16483 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wmwt_doAbort)
$display("[%0d]: %m: wmwt_doAbort", v__h16483);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/SMAdapter.bsv\", line 257, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/SMAdapter.bsv\", line 257, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/SMAdapter.bsv\", line 257, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_cfrd fired in the same clock\n cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h15314 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x",
v__h15314,
smaCtrl);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/SMAdapter.bsv\", line 289, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_ctrl_OrE fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/SMAdapter.bsv\", line 289, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/SMAdapter.bsv\", line 289, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_cfrd fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_cfwr)
$display("Error: \"bsv/SMAdapter.bsv\", line 289, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_cfwr fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h2800 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h2800,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h2653 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h2653,
wci_cEdge,
wci_cState,
wci_nState);
end
// synopsys translate_on
endmodule |
module mcu # (
// Size of Code TCM in 32-bit words.
parameter OPTION_CTCM_NUM_WORDS = 1024
)
(
input CLK,
input RESET_I,
input [31:0] DEBUG_I,
output reg [31:0] DEBUG_O
);
//==== CPU instantiation ===================================================
wire [31:0] code_addr;
wire [ 1:0] code_trans;
reg code_ready;
reg [ 1:0] code_resp;
reg [31:0] code_rdata;
wire [31:0] data_addr;
wire [ 1:0] data_trans;
wire [ 2:0] data_size;
reg data_ready;
reg [ 1:0] data_resp;
reg [31:0] data_rdata;
wire [31:0] data_wdata;
wire data_write;
reg data_wpending;
reg [ 1:0] data_wsize;
reg [31:0] data_waddr;
reg [31:0] mem_op_pc;
reg [31:0] mem_rdata;
reg [ 4:0] hw_irq;
reg [31:0] ctcm [0:OPTION_CTCM_NUM_WORDS-1];
reg [10:0] ctcm_addr;
reg [31:0] ctcm_data;
// The synth script and/or sim makefile should put this on the include path.
initial begin
`include "software.rom.inc"
end
cpu #(
)
cpu (
.CLK (CLK),
.RESET_I (RESET_I),
/* Code AHB interface. Only 32b RD supported so some signals omitted. */
.CADDR_O (code_addr),
.CTRANS_O (code_trans),
.CRDATA_I (code_rdata),
.CREADY_I (code_ready),
.CRESP_I (code_resp),
.DADDR_O (data_addr),
.DTRANS_O (data_trans),
.DSIZE_O (data_size),
.DRDATA_I (data_rdata),
.DWDATA_O (data_wdata),
.DWRITE_O (data_write),
.DREADY_I (data_ready),
.DRESP_I (data_resp),
.HWIRQ_I (hw_irq),
.STALL_I (1'b0)
);
// Let's hope we can trick the synth tool into not optimizing it all away.
always @(posedge CLK) begin
DEBUG_O <= {code_trans, data_trans, data_size, data_write, 24'h0} ^
data_addr ^
data_wdata;
end
// Dummy interconnect.
always @(*) begin
ctcm_addr = code_addr[12:2];
code_ready = 1'b1;
code_resp = 2'b00;
code_rdata = ctcm_data;
hw_irq = 0; // FIXME a good chunk of logic will go away!
// Remember: this DOES NOT WORK, we only want to fool the synth tool.
data_resp = 2'b00;
data_ready = 1'b1;
data_rdata = DEBUG_I;
end
// Synchronous CTCM ROM. We want to infer one or more BRAMs here and
// chances are they'll be part of the most interesting timing paths.
always @(posedge CLK) begin
ctcm_data <= ctcm[ctcm_addr];
end
endmodule |
module cpu
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
EPC_INTF_addr,
EPC_INTF_ads,
EPC_INTF_be,
EPC_INTF_burst,
EPC_INTF_clk,
EPC_INTF_cs_n,
EPC_INTF_data_i,
EPC_INTF_data_o,
EPC_INTF_data_t,
EPC_INTF_rd_n,
EPC_INTF_rdy,
EPC_INTF_rnw,
EPC_INTF_rst,
EPC_INTF_wr_n,
FCLK_CLK0,
FCLK_RESET0_N,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
GPIO_tri_i,
GPIO_tri_o,
GPIO_tri_t,
IIC_0_scl_i,
IIC_0_scl_o,
IIC_0_scl_t,
IIC_0_sda_i,
IIC_0_sda_o,
IIC_0_sda_t,
IIC_1_scl_i,
IIC_1_scl_o,
IIC_1_scl_t,
IIC_1_sda_i,
IIC_1_sda_o,
IIC_1_sda_t,
IIC_scl_i,
IIC_scl_o,
IIC_scl_t,
IIC_sda_i,
IIC_sda_o,
IIC_sda_t,
Int0,
Int1,
Int2,
Int3,
OCXO_CLK100,
OCXO_RESETN,
UART_0_rxd,
UART_0_txd,
Vp_Vn_v_n,
Vp_Vn_v_p);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
output [0:31]EPC_INTF_addr;
output EPC_INTF_ads;
output [0:3]EPC_INTF_be;
output EPC_INTF_burst;
input EPC_INTF_clk;
output [0:0]EPC_INTF_cs_n;
input [0:31]EPC_INTF_data_i;
output [0:31]EPC_INTF_data_o;
output [0:31]EPC_INTF_data_t;
output EPC_INTF_rd_n;
input [0:0]EPC_INTF_rdy;
output EPC_INTF_rnw;
input EPC_INTF_rst;
output EPC_INTF_wr_n;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [15:0]GPIO_tri_i;
output [15:0]GPIO_tri_o;
output [15:0]GPIO_tri_t;
input IIC_0_scl_i;
output IIC_0_scl_o;
output IIC_0_scl_t;
input IIC_0_sda_i;
output IIC_0_sda_o;
output IIC_0_sda_t;
input IIC_1_scl_i;
output IIC_1_scl_o;
output IIC_1_scl_t;
input IIC_1_sda_i;
output IIC_1_sda_o;
output IIC_1_sda_t;
input IIC_scl_i;
output IIC_scl_o;
output IIC_scl_t;
input IIC_sda_i;
output IIC_sda_o;
output IIC_sda_t;
input [0:0]Int0;
input [0:0]Int1;
input [0:0]Int2;
input [0:0]Int3;
input OCXO_CLK100;
output [0:0]OCXO_RESETN;
input UART_0_rxd;
output UART_0_txd;
input Vp_Vn_v_n;
input Vp_Vn_v_p;
wire GND_1;
wire [0:0]In4_1;
wire [0:0]In5_1;
wire [0:0]Int0_1;
wire [0:0]Int1_1;
wire M_AXI_GP0_ACLK_1;
wire M_AXI_GP1_ACLK_1;
wire VCC_1;
wire Vp_Vn_1_V_N;
wire Vp_Vn_1_V_P;
wire [0:31]axi_epc_0_EPC_INTF_ADDR;
wire axi_epc_0_EPC_INTF_ADS;
wire [0:3]axi_epc_0_EPC_INTF_BE;
wire axi_epc_0_EPC_INTF_BURST;
wire axi_epc_0_EPC_INTF_CLK;
wire [0:0]axi_epc_0_EPC_INTF_CS_N;
wire [0:31]axi_epc_0_EPC_INTF_DATA_I;
wire [0:31]axi_epc_0_EPC_INTF_DATA_O;
wire [0:31]axi_epc_0_EPC_INTF_DATA_T;
wire [0:0]axi_epc_0_EPC_INTF_RDY;
wire axi_epc_0_EPC_INTF_RD_N;
wire axi_epc_0_EPC_INTF_RNW;
wire axi_epc_0_EPC_INTF_RST;
wire axi_epc_0_EPC_INTF_WR_N;
wire [15:0]axi_gpio_0_GPIO_TRI_I;
wire [15:0]axi_gpio_0_GPIO_TRI_O;
wire [15:0]axi_gpio_0_GPIO_TRI_T;
wire axi_iic_0_IIC_SCL_I;
wire axi_iic_0_IIC_SCL_O;
wire axi_iic_0_IIC_SCL_T;
wire axi_iic_0_IIC_SDA_I;
wire axi_iic_0_IIC_SDA_O;
wire axi_iic_0_IIC_SDA_T;
wire axi_iic_0_iic2intc_irpt;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire processing_system7_0_IIC_0_SCL_I;
wire processing_system7_0_IIC_0_SCL_O;
wire processing_system7_0_IIC_0_SCL_T;
wire processing_system7_0_IIC_0_SDA_I;
wire processing_system7_0_IIC_0_SDA_O;
wire processing_system7_0_IIC_0_SDA_T;
wire processing_system7_0_IIC_1_SCL_I;
wire processing_system7_0_IIC_1_SCL_O;
wire processing_system7_0_IIC_1_SCL_T;
wire processing_system7_0_IIC_1_SDA_I;
wire processing_system7_0_IIC_1_SDA_O;
wire processing_system7_0_IIC_1_SDA_T;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_ARID;
wire [3:0]processing_system7_0_M_AXI_GP1_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_ARQOS;
wire processing_system7_0_M_AXI_GP1_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_ARSIZE;
wire processing_system7_0_M_AXI_GP1_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_AWID;
wire [3:0]processing_system7_0_M_AXI_GP1_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_AWQOS;
wire processing_system7_0_M_AXI_GP1_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_AWSIZE;
wire processing_system7_0_M_AXI_GP1_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP1_BID;
wire processing_system7_0_M_AXI_GP1_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_BRESP;
wire processing_system7_0_M_AXI_GP1_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_RID;
wire processing_system7_0_M_AXI_GP1_RLAST;
wire processing_system7_0_M_AXI_GP1_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_RRESP;
wire processing_system7_0_M_AXI_GP1_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_WID;
wire processing_system7_0_M_AXI_GP1_WLAST;
wire processing_system7_0_M_AXI_GP1_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP1_WSTRB;
wire processing_system7_0_M_AXI_GP1_WVALID;
wire processing_system7_0_UART_0_RxD;
wire processing_system7_0_UART_0_TxD;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_1_M00_AXI_ARREADY;
wire processing_system7_0_axi_periph_1_M00_AXI_ARVALID;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_1_M00_AXI_AWREADY;
wire processing_system7_0_axi_periph_1_M00_AXI_AWVALID;
wire processing_system7_0_axi_periph_1_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_1_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_1_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_RDATA;
wire processing_system7_0_axi_periph_1_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_1_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_1_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_1_M00_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_1_M00_AXI_WSTRB;
wire processing_system7_0_axi_periph_1_M00_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M00_AXI_WSTRB;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M01_AXI_ARADDR;
wire processing_system7_0_axi_periph_M01_AXI_ARREADY;
wire processing_system7_0_axi_periph_M01_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M01_AXI_AWADDR;
wire processing_system7_0_axi_periph_M01_AXI_AWREADY;
wire processing_system7_0_axi_periph_M01_AXI_AWVALID;
wire processing_system7_0_axi_periph_M01_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_BRESP;
wire processing_system7_0_axi_periph_M01_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_RDATA;
wire processing_system7_0_axi_periph_M01_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_RRESP;
wire processing_system7_0_axi_periph_M01_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_WDATA;
wire processing_system7_0_axi_periph_M01_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M01_AXI_WSTRB;
wire processing_system7_0_axi_periph_M01_AXI_WVALID;
wire [10:0]processing_system7_0_axi_periph_M02_AXI_ARADDR;
wire processing_system7_0_axi_periph_M02_AXI_ARREADY;
wire processing_system7_0_axi_periph_M02_AXI_ARVALID;
wire [10:0]processing_system7_0_axi_periph_M02_AXI_AWADDR;
wire processing_system7_0_axi_periph_M02_AXI_AWREADY;
wire processing_system7_0_axi_periph_M02_AXI_AWVALID;
wire processing_system7_0_axi_periph_M02_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_BRESP;
wire processing_system7_0_axi_periph_M02_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_RDATA;
wire processing_system7_0_axi_periph_M02_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_RRESP;
wire processing_system7_0_axi_periph_M02_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_WDATA;
wire processing_system7_0_axi_periph_M02_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M02_AXI_WSTRB;
wire processing_system7_0_axi_periph_M02_AXI_WVALID;
wire [0:0]rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn;
wire [0:0]rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
wire xadc_wiz_0_ip2intc_irpt;
wire [5:0]xlconcat_0_dout;
assign EPC_INTF_addr[0:31] = axi_epc_0_EPC_INTF_ADDR;
assign EPC_INTF_ads = axi_epc_0_EPC_INTF_ADS;
assign EPC_INTF_be[0:3] = axi_epc_0_EPC_INTF_BE;
assign EPC_INTF_burst = axi_epc_0_EPC_INTF_BURST;
assign EPC_INTF_cs_n[0] = axi_epc_0_EPC_INTF_CS_N;
assign EPC_INTF_data_o[0:31] = axi_epc_0_EPC_INTF_DATA_O;
assign EPC_INTF_data_t[0:31] = axi_epc_0_EPC_INTF_DATA_T;
assign EPC_INTF_rd_n = axi_epc_0_EPC_INTF_RD_N;
assign EPC_INTF_rnw = axi_epc_0_EPC_INTF_RNW;
assign EPC_INTF_wr_n = axi_epc_0_EPC_INTF_WR_N;
assign FCLK_CLK0 = M_AXI_GP0_ACLK_1;
assign FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N;
assign GPIO_tri_o[15:0] = axi_gpio_0_GPIO_TRI_O;
assign GPIO_tri_t[15:0] = axi_gpio_0_GPIO_TRI_T;
assign IIC_0_scl_o = processing_system7_0_IIC_0_SCL_O;
assign IIC_0_scl_t = processing_system7_0_IIC_0_SCL_T;
assign IIC_0_sda_o = processing_system7_0_IIC_0_SDA_O;
assign IIC_0_sda_t = processing_system7_0_IIC_0_SDA_T;
assign IIC_1_scl_o = processing_system7_0_IIC_1_SCL_O;
assign IIC_1_scl_t = processing_system7_0_IIC_1_SCL_T;
assign IIC_1_sda_o = processing_system7_0_IIC_1_SDA_O;
assign IIC_1_sda_t = processing_system7_0_IIC_1_SDA_T;
assign IIC_scl_o = axi_iic_0_IIC_SCL_O;
assign IIC_scl_t = axi_iic_0_IIC_SCL_T;
assign IIC_sda_o = axi_iic_0_IIC_SDA_O;
assign IIC_sda_t = axi_iic_0_IIC_SDA_T;
assign In4_1 = Int2[0];
assign In5_1 = Int3[0];
assign Int0_1 = Int0[0];
assign Int1_1 = Int1[0];
assign M_AXI_GP1_ACLK_1 = OCXO_CLK100;
assign OCXO_RESETN[0] = rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn;
assign UART_0_txd = processing_system7_0_UART_0_TxD;
assign Vp_Vn_1_V_N = Vp_Vn_v_n;
assign Vp_Vn_1_V_P = Vp_Vn_v_p;
assign axi_epc_0_EPC_INTF_CLK = EPC_INTF_clk;
assign axi_epc_0_EPC_INTF_DATA_I = EPC_INTF_data_i[0:31];
assign axi_epc_0_EPC_INTF_RDY = EPC_INTF_rdy[0];
assign axi_epc_0_EPC_INTF_RST = EPC_INTF_rst;
assign axi_gpio_0_GPIO_TRI_I = GPIO_tri_i[15:0];
assign axi_iic_0_IIC_SCL_I = IIC_scl_i;
assign axi_iic_0_IIC_SDA_I = IIC_sda_i;
assign processing_system7_0_IIC_0_SCL_I = IIC_0_scl_i;
assign processing_system7_0_IIC_0_SDA_I = IIC_0_sda_i;
assign processing_system7_0_IIC_1_SCL_I = IIC_1_scl_i;
assign processing_system7_0_IIC_1_SDA_I = IIC_1_sda_i;
assign processing_system7_0_UART_0_RxD = UART_0_rxd;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
cpu_axi_epc_0_0 axi_epc_0
(.prh_addr(axi_epc_0_EPC_INTF_ADDR),
.prh_ads(axi_epc_0_EPC_INTF_ADS),
.prh_be(axi_epc_0_EPC_INTF_BE),
.prh_burst(axi_epc_0_EPC_INTF_BURST),
.prh_clk(axi_epc_0_EPC_INTF_CLK),
.prh_cs_n(axi_epc_0_EPC_INTF_CS_N),
.prh_data_i(axi_epc_0_EPC_INTF_DATA_I),
.prh_data_o(axi_epc_0_EPC_INTF_DATA_O),
.prh_data_t(axi_epc_0_EPC_INTF_DATA_T),
.prh_rd_n(axi_epc_0_EPC_INTF_RD_N),
.prh_rdy(axi_epc_0_EPC_INTF_RDY),
.prh_rnw(axi_epc_0_EPC_INTF_RNW),
.prh_rst(axi_epc_0_EPC_INTF_RST),
.prh_wr_n(axi_epc_0_EPC_INTF_WR_N),
.s_axi_aclk(M_AXI_GP1_ACLK_1),
.s_axi_araddr(processing_system7_0_axi_periph_1_M00_AXI_ARADDR),
.s_axi_aresetn(rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_1_M00_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_1_M00_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_1_M00_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_1_M00_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_1_M00_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_1_M00_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_1_M00_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_1_M00_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_1_M00_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_1_M00_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_1_M00_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_1_M00_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_1_M00_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_1_M00_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_1_M00_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_1_M00_AXI_WVALID));
cpu_axi_gpio_0_0 axi_gpio_0
(.gpio_io_i(axi_gpio_0_GPIO_TRI_I),
.gpio_io_o(axi_gpio_0_GPIO_TRI_O),
.gpio_io_t(axi_gpio_0_GPIO_TRI_T),
.s_axi_aclk(M_AXI_GP0_ACLK_1),
.s_axi_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID));
cpu_axi_iic_0_0 axi_iic_0
(.iic2intc_irpt(axi_iic_0_iic2intc_irpt),
.s_axi_aclk(M_AXI_GP0_ACLK_1),
.s_axi_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.scl_i(axi_iic_0_IIC_SCL_I),
.scl_o(axi_iic_0_IIC_SCL_O),
.scl_t(axi_iic_0_IIC_SCL_T),
.sda_i(axi_iic_0_IIC_SDA_I),
.sda_o(axi_iic_0_IIC_SDA_O),
.sda_t(axi_iic_0_IIC_SDA_T));
cpu_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(M_AXI_GP0_ACLK_1),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.I2C0_SCL_I(processing_system7_0_IIC_0_SCL_I),
.I2C0_SCL_O(processing_system7_0_IIC_0_SCL_O),
.I2C0_SCL_T(processing_system7_0_IIC_0_SCL_T),
.I2C0_SDA_I(processing_system7_0_IIC_0_SDA_I),
.I2C0_SDA_O(processing_system7_0_IIC_0_SDA_O),
.I2C0_SDA_T(processing_system7_0_IIC_0_SDA_T),
.I2C1_SCL_I(processing_system7_0_IIC_1_SCL_I),
.I2C1_SCL_O(processing_system7_0_IIC_1_SCL_O),
.I2C1_SCL_T(processing_system7_0_IIC_1_SCL_T),
.I2C1_SDA_I(processing_system7_0_IIC_1_SDA_I),
.I2C1_SDA_O(processing_system7_0_IIC_1_SDA_O),
.I2C1_SDA_T(processing_system7_0_IIC_1_SDA_T),
.IRQ_F2P(xlconcat_0_dout),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK_1),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(M_AXI_GP1_ACLK_1),
.M_AXI_GP1_ARADDR(processing_system7_0_M_AXI_GP1_ARADDR),
.M_AXI_GP1_ARBURST(processing_system7_0_M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARCACHE(processing_system7_0_M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARID(processing_system7_0_M_AXI_GP1_ARID),
.M_AXI_GP1_ARLEN(processing_system7_0_M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARLOCK(processing_system7_0_M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARPROT(processing_system7_0_M_AXI_GP1_ARPROT),
.M_AXI_GP1_ARQOS(processing_system7_0_M_AXI_GP1_ARQOS),
.M_AXI_GP1_ARREADY(processing_system7_0_M_AXI_GP1_ARREADY),
.M_AXI_GP1_ARSIZE(processing_system7_0_M_AXI_GP1_ARSIZE),
.M_AXI_GP1_ARVALID(processing_system7_0_M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWADDR(processing_system7_0_M_AXI_GP1_AWADDR),
.M_AXI_GP1_AWBURST(processing_system7_0_M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWCACHE(processing_system7_0_M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWID(processing_system7_0_M_AXI_GP1_AWID),
.M_AXI_GP1_AWLEN(processing_system7_0_M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWLOCK(processing_system7_0_M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWPROT(processing_system7_0_M_AXI_GP1_AWPROT),
.M_AXI_GP1_AWQOS(processing_system7_0_M_AXI_GP1_AWQOS),
.M_AXI_GP1_AWREADY(processing_system7_0_M_AXI_GP1_AWREADY),
.M_AXI_GP1_AWSIZE(processing_system7_0_M_AXI_GP1_AWSIZE),
.M_AXI_GP1_AWVALID(processing_system7_0_M_AXI_GP1_AWVALID),
.M_AXI_GP1_BID(processing_system7_0_M_AXI_GP1_BID),
.M_AXI_GP1_BREADY(processing_system7_0_M_AXI_GP1_BREADY),
.M_AXI_GP1_BRESP(processing_system7_0_M_AXI_GP1_BRESP),
.M_AXI_GP1_BVALID(processing_system7_0_M_AXI_GP1_BVALID),
.M_AXI_GP1_RDATA(processing_system7_0_M_AXI_GP1_RDATA),
.M_AXI_GP1_RID(processing_system7_0_M_AXI_GP1_RID),
.M_AXI_GP1_RLAST(processing_system7_0_M_AXI_GP1_RLAST),
.M_AXI_GP1_RREADY(processing_system7_0_M_AXI_GP1_RREADY),
.M_AXI_GP1_RRESP(processing_system7_0_M_AXI_GP1_RRESP),
.M_AXI_GP1_RVALID(processing_system7_0_M_AXI_GP1_RVALID),
.M_AXI_GP1_WDATA(processing_system7_0_M_AXI_GP1_WDATA),
.M_AXI_GP1_WID(processing_system7_0_M_AXI_GP1_WID),
.M_AXI_GP1_WLAST(processing_system7_0_M_AXI_GP1_WLAST),
.M_AXI_GP1_WREADY(processing_system7_0_M_AXI_GP1_WREADY),
.M_AXI_GP1_WSTRB(processing_system7_0_M_AXI_GP1_WSTRB),
.M_AXI_GP1_WVALID(processing_system7_0_M_AXI_GP1_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.UART0_RX(processing_system7_0_UART_0_RxD),
.UART0_TX(processing_system7_0_UART_0_TxD),
.USB0_VBUS_PWRFAULT(GND_1));
cpu_processing_system7_0_axi_periph_0 processing_system7_0_axi_periph
(.ACLK(M_AXI_GP0_ACLK_1),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(M_AXI_GP0_ACLK_1),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.M01_ACLK(M_AXI_GP0_ACLK_1),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.M01_AXI_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.M01_AXI_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.M01_AXI_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.M01_AXI_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.M01_AXI_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.M01_AXI_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.M01_AXI_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.M01_AXI_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.M01_AXI_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.M01_AXI_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.M01_AXI_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.M01_AXI_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.M01_AXI_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.M01_AXI_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.M01_AXI_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.M01_AXI_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.M02_ACLK(M_AXI_GP0_ACLK_1),
.M02_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M02_AXI_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.M02_AXI_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.M02_AXI_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.M02_AXI_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.M02_AXI_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.M02_AXI_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.M02_AXI_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.M02_AXI_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.M02_AXI_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.M02_AXI_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.M02_AXI_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.M02_AXI_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.M02_AXI_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.M02_AXI_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.M02_AXI_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.M02_AXI_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.M02_AXI_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.S00_ACLK(M_AXI_GP0_ACLK_1),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
cpu_processing_system7_0_axi_periph_1_0 processing_system7_0_axi_periph_1
(.ACLK(M_AXI_GP1_ACLK_1),
.ARESETN(rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn),
.M00_ACLK(M_AXI_GP1_ACLK_1),
.M00_ARESETN(rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_1_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_1_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_1_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_1_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_1_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_1_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_1_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_1_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_1_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_1_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_1_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_1_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_1_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_1_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_1_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_0_axi_periph_1_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_0_axi_periph_1_M00_AXI_WVALID),
.S00_ACLK(M_AXI_GP1_ACLK_1),
.S00_ARESETN(rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP1_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP1_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP1_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP1_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP1_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP1_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP1_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP1_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP1_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP1_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP1_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP1_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP1_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP1_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP1_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP1_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP1_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP1_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP1_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP1_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP1_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP1_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP1_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP1_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP1_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP1_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP1_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP1_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP1_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP1_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP1_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP1_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP1_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP1_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP1_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP1_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP1_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP1_WVALID));
cpu_rst_M_AXI_GP1_ACLK_100M_0 rst_M_AXI_GP1_ACLK_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn),
.slowest_sync_clk(M_AXI_GP1_ACLK_1));
cpu_rst_processing_system7_0_100M_0 rst_processing_system7_0_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(M_AXI_GP0_ACLK_1));
cpu_xadc_wiz_0_0 xadc_wiz_0
(.ip2intc_irpt(xadc_wiz_0_ip2intc_irpt),
.s_axi_aclk(M_AXI_GP0_ACLK_1),
.s_axi_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.vn_in(Vp_Vn_1_V_N),
.vp_in(Vp_Vn_1_V_P));
cpu_xlconcat_0_0 xlconcat_0
(.In0(axi_iic_0_iic2intc_irpt),
.In1(xadc_wiz_0_ip2intc_irpt),
.In2(Int0_1),
.In3(Int1_1),
.In4(In4_1),
.In5(In5_1),
.dout(xlconcat_0_dout));
endmodule |
module cpu_processing_system7_0_axi_periph_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wstrb,
M02_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [8:0]M00_AXI_araddr;
input [0:0]M00_AXI_arready;
output [0:0]M00_AXI_arvalid;
output [8:0]M00_AXI_awaddr;
input [0:0]M00_AXI_awready;
output [0:0]M00_AXI_awvalid;
output [0:0]M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input [0:0]M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output [0:0]M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input [0:0]M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input [0:0]M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output [0:0]M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [8:0]M01_AXI_araddr;
input M01_AXI_arready;
output M01_AXI_arvalid;
output [8:0]M01_AXI_awaddr;
input M01_AXI_awready;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [10:0]M02_AXI_araddr;
input M02_AXI_arready;
output M02_AXI_arvalid;
output [10:0]M02_AXI_awaddr;
input M02_AXI_awready;
output M02_AXI_awvalid;
output M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input M02_AXI_wready;
output [3:0]M02_AXI_wstrb;
output M02_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire M01_ACLK_1;
wire [0:0]M01_ARESETN_1;
wire M02_ACLK_1;
wire [0:0]M02_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire [8:0]m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [8:0]m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m01_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m01_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [10:0]m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [10:0]m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m02_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m02_couplers_to_processing_system7_0_axi_periph_WVALID;
wire processing_system7_0_axi_periph_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [0:0]xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [0:0]xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire [0:0]xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire [0:0]xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire xbar_to_m02_couplers_ARREADY;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire xbar_to_m02_couplers_AWREADY;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire xbar_to_m02_couplers_WREADY;
wire [11:8]xbar_to_m02_couplers_WSTRB;
wire [2:2]xbar_to_m02_couplers_WVALID;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[8:0] = m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M00_AXI_arvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M00_AXI_awaddr[8:0] = m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M00_AXI_awvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M00_AXI_bready[0] = m00_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M00_AXI_rready[0] = m00_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M00_AXI_wstrb[3:0] = m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M00_AXI_wvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN[0];
assign M01_AXI_araddr[8:0] = m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M01_AXI_arvalid = m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M01_AXI_awaddr[8:0] = m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M01_AXI_awvalid = m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M01_AXI_bready = m01_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M01_AXI_rready = m01_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M02_ACLK_1 = M02_ACLK;
assign M02_ARESETN_1 = M02_ARESETN[0];
assign M02_AXI_araddr[10:0] = m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M02_AXI_arvalid = m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M02_AXI_awaddr[10:0] = m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M02_AXI_awvalid = m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M02_AXI_bready = m02_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M02_AXI_rready = m02_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M02_AXI_wstrb[3:0] = m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M02_AXI_wvalid = m02_couplers_to_processing_system7_0_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_to_s00_couplers_WREADY;
assign m00_couplers_to_processing_system7_0_axi_periph_ARREADY = M00_AXI_arready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_AWREADY = M00_AXI_awready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_BVALID = M00_AXI_bvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RVALID = M00_AXI_rvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_WREADY = M00_AXI_wready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_ARREADY = M01_AXI_arready;
assign m01_couplers_to_processing_system7_0_axi_periph_AWREADY = M01_AXI_awready;
assign m01_couplers_to_processing_system7_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_WREADY = M01_AXI_wready;
assign m02_couplers_to_processing_system7_0_axi_periph_ARREADY = M02_AXI_arready;
assign m02_couplers_to_processing_system7_0_axi_periph_AWREADY = M02_AXI_awready;
assign m02_couplers_to_processing_system7_0_axi_periph_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_BVALID = M02_AXI_bvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RVALID = M02_AXI_rvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_WREADY = M02_AXI_wready;
assign processing_system7_0_axi_periph_ACLK_net = ACLK;
assign processing_system7_0_axi_periph_ARESETN_net = ARESETN[0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
m00_couplers_imp_ZVW4AE m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m00_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m00_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m00_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m00_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m00_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m00_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m00_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m00_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m00_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m00_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m00_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m00_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m00_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m00_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m00_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m00_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[8:0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[8:0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_PQKNCJ m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m01_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m01_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m01_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m01_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m01_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m01_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m01_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m01_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m01_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m01_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m01_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m01_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m01_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m01_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m01_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m01_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR[40:32]),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[40:32]),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_1QFTZ3X m02_couplers
(.M_ACLK(M02_ACLK_1),
.M_ARESETN(M02_ARESETN_1),
.M_AXI_araddr(m02_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m02_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m02_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m02_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m02_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m02_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m02_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m02_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m02_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m02_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m02_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m02_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m02_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m02_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m02_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m02_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m02_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR[74:64]),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR[74:64]),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
s00_couplers_imp_B67PN0 s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_to_s00_couplers_WVALID));
cpu_xbar_0 xbar
(.aclk(processing_system7_0_axi_periph_ACLK_net),
.aresetn(processing_system7_0_axi_periph_ARESETN_net),
.m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule |
module cpu_processing_system7_0_axi_periph_1_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [31:0]M00_AXI_araddr;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire processing_system7_0_axi_periph_1_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_1_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_1_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_1_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_1_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_1_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_1_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_1_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_1_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_1_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR;
wire s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY;
wire s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR;
wire s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY;
wire s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID;
wire s00_couplers_to_processing_system7_0_axi_periph_1_BREADY;
wire [1:0]s00_couplers_to_processing_system7_0_axi_periph_1_BRESP;
wire s00_couplers_to_processing_system7_0_axi_periph_1_BVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_RDATA;
wire s00_couplers_to_processing_system7_0_axi_periph_1_RREADY;
wire [1:0]s00_couplers_to_processing_system7_0_axi_periph_1_RRESP;
wire s00_couplers_to_processing_system7_0_axi_periph_1_RVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_WDATA;
wire s00_couplers_to_processing_system7_0_axi_periph_1_WREADY;
wire [3:0]s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB;
wire s00_couplers_to_processing_system7_0_axi_periph_1_WVALID;
assign M00_AXI_araddr[31:0] = s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR;
assign M00_AXI_arvalid = s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID;
assign M00_AXI_awaddr[31:0] = s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR;
assign M00_AXI_awvalid = s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID;
assign M00_AXI_bready = s00_couplers_to_processing_system7_0_axi_periph_1_BREADY;
assign M00_AXI_rready = s00_couplers_to_processing_system7_0_axi_periph_1_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_processing_system7_0_axi_periph_1_WDATA;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_processing_system7_0_axi_periph_1_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_1_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_1_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_1_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_1_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_1_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_1_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_1_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_1_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_1_to_s00_couplers_WREADY;
assign processing_system7_0_axi_periph_1_ACLK_net = M00_ACLK;
assign processing_system7_0_axi_periph_1_ARESETN_net = M00_ARESETN[0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_1_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_1_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_1_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY = M00_AXI_arready;
assign s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY = M00_AXI_awready;
assign s00_couplers_to_processing_system7_0_axi_periph_1_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_processing_system7_0_axi_periph_1_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_processing_system7_0_axi_periph_1_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_processing_system7_0_axi_periph_1_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_processing_system7_0_axi_periph_1_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_processing_system7_0_axi_periph_1_WREADY = M00_AXI_wready;
s00_couplers_imp_1AHKP6S s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_1_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_1_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR),
.M_AXI_arready(s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY),
.M_AXI_arvalid(s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID),
.M_AXI_awaddr(s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR),
.M_AXI_awready(s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY),
.M_AXI_awvalid(s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID),
.M_AXI_bready(s00_couplers_to_processing_system7_0_axi_periph_1_BREADY),
.M_AXI_bresp(s00_couplers_to_processing_system7_0_axi_periph_1_BRESP),
.M_AXI_bvalid(s00_couplers_to_processing_system7_0_axi_periph_1_BVALID),
.M_AXI_rdata(s00_couplers_to_processing_system7_0_axi_periph_1_RDATA),
.M_AXI_rready(s00_couplers_to_processing_system7_0_axi_periph_1_RREADY),
.M_AXI_rresp(s00_couplers_to_processing_system7_0_axi_periph_1_RRESP),
.M_AXI_rvalid(s00_couplers_to_processing_system7_0_axi_periph_1_RVALID),
.M_AXI_wdata(s00_couplers_to_processing_system7_0_axi_periph_1_WDATA),
.M_AXI_wready(s00_couplers_to_processing_system7_0_axi_periph_1_WREADY),
.M_AXI_wstrb(s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB),
.M_AXI_wvalid(s00_couplers_to_processing_system7_0_axi_periph_1_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_1_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_1_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_1_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_1_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_1_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_1_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_1_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_1_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_1_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_1_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_1_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_1_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_1_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_1_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_1_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_1_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_1_to_s00_couplers_WVALID));
endmodule |
module m00_couplers_imp_ZVW4AE
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [8:0]m00_couplers_to_m00_couplers_ARADDR;
wire [0:0]m00_couplers_to_m00_couplers_ARREADY;
wire [0:0]m00_couplers_to_m00_couplers_ARVALID;
wire [8:0]m00_couplers_to_m00_couplers_AWADDR;
wire [0:0]m00_couplers_to_m00_couplers_AWREADY;
wire [0:0]m00_couplers_to_m00_couplers_AWVALID;
wire [0:0]m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire [0:0]m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire [0:0]m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire [0:0]m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire [0:0]m00_couplers_to_m00_couplers_WREADY;
wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
wire [0:0]m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[8:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[8:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0];
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0];
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0];
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0];
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0];
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0];
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0];
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0];
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0];
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0];
endmodule |
module m01_couplers_imp_PQKNCJ
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [8:0]m01_couplers_to_m01_couplers_ARADDR;
wire m01_couplers_to_m01_couplers_ARREADY;
wire m01_couplers_to_m01_couplers_ARVALID;
wire [8:0]m01_couplers_to_m01_couplers_AWADDR;
wire m01_couplers_to_m01_couplers_AWREADY;
wire m01_couplers_to_m01_couplers_AWVALID;
wire m01_couplers_to_m01_couplers_BREADY;
wire [1:0]m01_couplers_to_m01_couplers_BRESP;
wire m01_couplers_to_m01_couplers_BVALID;
wire [31:0]m01_couplers_to_m01_couplers_RDATA;
wire m01_couplers_to_m01_couplers_RREADY;
wire [1:0]m01_couplers_to_m01_couplers_RRESP;
wire m01_couplers_to_m01_couplers_RVALID;
wire [31:0]m01_couplers_to_m01_couplers_WDATA;
wire m01_couplers_to_m01_couplers_WREADY;
wire [3:0]m01_couplers_to_m01_couplers_WSTRB;
wire m01_couplers_to_m01_couplers_WVALID;
assign M_AXI_araddr[8:0] = m01_couplers_to_m01_couplers_ARADDR;
assign M_AXI_arvalid = m01_couplers_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m01_couplers_to_m01_couplers_AWADDR;
assign M_AXI_awvalid = m01_couplers_to_m01_couplers_AWVALID;
assign M_AXI_bready = m01_couplers_to_m01_couplers_BREADY;
assign M_AXI_rready = m01_couplers_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = m01_couplers_to_m01_couplers_WVALID;
assign S_AXI_arready = m01_couplers_to_m01_couplers_ARREADY;
assign S_AXI_awready = m01_couplers_to_m01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
assign S_AXI_bvalid = m01_couplers_to_m01_couplers_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
assign S_AXI_rvalid = m01_couplers_to_m01_couplers_RVALID;
assign S_AXI_wready = m01_couplers_to_m01_couplers_WREADY;
assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[8:0];
assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready;
assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready;
assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready;
assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid;
assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready;
assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid;
assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule |
module m02_couplers_imp_1QFTZ3X
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [10:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [10:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [10:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [10:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [10:0]m02_couplers_to_m02_couplers_ARADDR;
wire m02_couplers_to_m02_couplers_ARREADY;
wire m02_couplers_to_m02_couplers_ARVALID;
wire [10:0]m02_couplers_to_m02_couplers_AWADDR;
wire m02_couplers_to_m02_couplers_AWREADY;
wire m02_couplers_to_m02_couplers_AWVALID;
wire m02_couplers_to_m02_couplers_BREADY;
wire [1:0]m02_couplers_to_m02_couplers_BRESP;
wire m02_couplers_to_m02_couplers_BVALID;
wire [31:0]m02_couplers_to_m02_couplers_RDATA;
wire m02_couplers_to_m02_couplers_RREADY;
wire [1:0]m02_couplers_to_m02_couplers_RRESP;
wire m02_couplers_to_m02_couplers_RVALID;
wire [31:0]m02_couplers_to_m02_couplers_WDATA;
wire m02_couplers_to_m02_couplers_WREADY;
wire [3:0]m02_couplers_to_m02_couplers_WSTRB;
wire m02_couplers_to_m02_couplers_WVALID;
assign M_AXI_araddr[10:0] = m02_couplers_to_m02_couplers_ARADDR;
assign M_AXI_arvalid = m02_couplers_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[10:0] = m02_couplers_to_m02_couplers_AWADDR;
assign M_AXI_awvalid = m02_couplers_to_m02_couplers_AWVALID;
assign M_AXI_bready = m02_couplers_to_m02_couplers_BREADY;
assign M_AXI_rready = m02_couplers_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m02_couplers_to_m02_couplers_WSTRB;
assign M_AXI_wvalid = m02_couplers_to_m02_couplers_WVALID;
assign S_AXI_arready = m02_couplers_to_m02_couplers_ARREADY;
assign S_AXI_awready = m02_couplers_to_m02_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP;
assign S_AXI_bvalid = m02_couplers_to_m02_couplers_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA;
assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP;
assign S_AXI_rvalid = m02_couplers_to_m02_couplers_RVALID;
assign S_AXI_wready = m02_couplers_to_m02_couplers_WREADY;
assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[10:0];
assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready;
assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid;
assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[10:0];
assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready;
assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid;
assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready;
assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid;
assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready;
assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid;
assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready;
assign m02_couplers_to_m02_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid;
endmodule |
module s00_couplers_imp_1AHKP6S
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
cpu_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule |
module s00_couplers_imp_B67PN0
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
cpu_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule |
module sky130_fd_sc_lp__buf_lp (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__buf_lp (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A)
);
endmodule |
module sky130_fd_sc_hdll__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule |
module in the ce_num_array. An integer is returned reflecting the
// starting index of the assigned Chip Enables within the CE, RdCE, and
// WrCE Buses.
//---------------------------------------------------------------------------
function automatic integer calc_start_ce_index;
input [0:8*C_NUM_ADDRESS_RANGES-1] ce_num_array;
input index;
integer index, ce_num_sum;
begin
ce_num_sum = 0;
if (index == 0)
begin
ce_num_sum = 0;
end
else
begin
begin : CALC_START_INDEX_FOR_CE_GEN
integer i;
for(i = 0; i <= index-1; i = i + 1)
begin
ce_num_sum = ce_num_sum + ce_num_array[(i*8)+:8];
end
end
end
calc_start_ce_index = ce_num_sum;
end
endfunction
wire[0:C_NUM_ADDRESS_RANGES-1] pselect_hit_i;
reg [0:C_NUM_ADDRESS_RANGES-1] cs_out_i ;
wire[0:C_TOTAL_NUM_CE-1] ce_expnd_i;
reg [0:C_TOTAL_NUM_CE-1] rdce_out_i ;
reg [0:C_TOTAL_NUM_CE-1] wrce_out_i ;
wire cs_ce_clr;
wire[0:C_TOTAL_NUM_CE-1] rdce_expnd_i;
wire[0:C_TOTAL_NUM_CE-1] wrce_expnd_i;
// Register clears
assign cs_ce_clr = ~Bus_rst | Clear_CS_CE_Reg ;
//-------------------------------------------------------------------------------
//-- Universal Address Decode Block
//-------------------------------------------------------------------------------
generate //start of MEM_DECODE_GEN generate
genvar bar_index;
for (bar_index = 0; bar_index <= C_NUM_ADDRESS_RANGES-1; bar_index = bar_index+1) begin : MEM_DECODE_GEN
localparam [0:31] TEMP = C_ARD_ADDR_RANGE_ARRAY[(bar_index*2)*32:(bar_index*2+1)*32-1];
localparam [0:31] TEMP_1 = C_ARD_ADDR_RANGE_ARRAY[(bar_index*2+1)*32:(bar_index*2+2)*32-1];
localparam [0:C_BUS_AWIDTH-1] ARD_ADDR_RANGE_ARRAY = TEMP[(32-C_BUS_AWIDTH):31];
localparam [0:C_BUS_AWIDTH-1] ARD_ADDR_RANGE_ARRAY_1= TEMP_1[(32-C_BUS_AWIDTH):31];
localparam CE_INDEX_START = calc_start_ce_index(C_ARD_NUM_CE_ARRAY[0:(8*C_NUM_ADDRESS_RANGES-1)],bar_index);
localparam DECODE_BITS = Addr_Bits(ARD_ADDR_RANGE_ARRAY, ARD_ADDR_RANGE_ARRAY_1);
localparam [0:7] CE_ADDR_SIZE_SLICE = C_ARD_NUM_CE_ARRAY[bar_index*8:(bar_index+1)*8-1];
localparam CE_ADDR_SIZE = `log2(CE_ADDR_SIZE_SLICE);
localparam TEMP_CE = C_ARD_NUM_CE_ARRAY[bar_index*8:(bar_index+1)*8-1];
// Generate GEN_FOR_MULTI_CS for for multiple address ranges
if (C_NUM_ADDRESS_RANGES > 1)begin : GEN_FOR_MULTI_CS
pselect_f #(.C_AB(DECODE_BITS),
.C_AW(C_BUS_AWIDTH),
.C_BAR(ARD_ADDR_RANGE_ARRAY),
.C_FAMILY(C_FAMILY)
)
MEM_SELECT_I(
.A(Address_In_Erly),
.AValid(Address_Valid_Erly),
.CS(pselect_hit_i[bar_index]));
end //end GEN_FOR_MULTI_CS
// Generate GEN_FOR_ONE_CS for a single address range
if (C_NUM_ADDRESS_RANGES == 1 )begin : GEN_FOR_ONE_CS
assign pselect_hit_i[bar_index] = Address_Valid_Erly ;
end //end GEN_FOR_ONE_CS
//-------------------------------------------------------------------------------
// Instantate backend registers for the Chip Selects
//-------------------------------------------------------------------------------
always @(posedge Bus_clk)
begin : BKEND_CS_REG
if (Bus_rst == 1'b0 | Clear_CS_CE_Reg == 1'b1)
begin
cs_out_i[bar_index] <= 1'b0;
end
else if (CS_CE_ld_enable == 1'b1)
begin
cs_out_i[bar_index] <= pselect_hit_i[bar_index];
end
end
//-----------------------------------------------------------------------
// Now expand the individual CEs for each base address.
//-----------------------------------------------------------------------
// Generate PER_CE_GEN to generate CEs for each address range
genvar j;
for (j = 0; j < TEMP_CE; j = j+1) begin : PER_CE_GEN
//--------------------------------------------------------------------
// CE decoders for multiple CE's
//--------------------------------------------------------------------
//Generate MULTIPLE_CES_THIS_CS_GEN start
localparam [CE_ADDR_SIZE-1:0] BAR = j;
if (CE_ADDR_SIZE > 0) begin : MULTIPLE_CES_THIS_CS_GEN
pselect_f #(.C_AB(CE_ADDR_SIZE),
.C_AW(CE_ADDR_SIZE),
.C_BAR(BAR),
.C_FAMILY(C_FAMILY)
)
CE_I(
.A(Address_In_Erly[C_BUS_AWIDTH-CE_ADDR_SIZE-2:C_BUS_AWIDTH-2-1]),
.AValid(pselect_hit_i[bar_index]),
.CS(ce_expnd_i[CE_INDEX_START + j]));
end //end MULTIPLE_CES_THIS_CS_GEN;
//--------------------------------------------------------------------
// CE decoders for single CE
//--------------------------------------------------------------------
// Generate SINGLE_CE_THIS_CS_GEN
if (CE_ADDR_SIZE == 0 )begin : SINGLE_CE_THIS_CS_GEN
assign ce_expnd_i[CE_INDEX_START + j] = pselect_hit_i[bar_index] ;
end // end SINGLE_CE_THIS_CS_GEN ;
end //end PER_CE_GEN;
end
endgenerate
//-------------------------------------------------------------------------
// GEN_BKEND_CE_REGISTERS
// This ForGen implements the backend registering for
// the CE, RdCE, and WrCE output buses.
//-------------------------------------------------------------------------
generate // Start of generate GEN_BKEND_CE_REGISTERS
genvar ce_index;
for (ce_index = 0; ce_index <= C_TOTAL_NUM_CE-1; ce_index = ce_index+1) begin : GEN_BKEND_CE_REGISTERS
assign rdce_expnd_i[ce_index] = ce_expnd_i[ce_index] & Bus_RNW_Erly ;
// Instantate Backend RdCE register
always @(posedge Bus_clk)
begin : BKEND_RDCE_REG
if (cs_ce_clr == 1'b1)
begin
rdce_out_i[ce_index] <= 1'b0 ;
end
else if (RW_CE_ld_enable == 1'b1)
begin
rdce_out_i[ce_index] <= rdce_expnd_i[ce_index];
end
end
assign wrce_expnd_i[ce_index] = ce_expnd_i[ce_index] & ~Bus_RNW_Erly ;
// Instantate Backend WrCE register
always @(posedge Bus_clk)
begin : BKEND_WRCE_REG
if (cs_ce_clr == 1'b1)
begin
wrce_out_i[ce_index] <= 1'b0 ;
end
else if (RW_CE_ld_enable == 1'b1)
begin
wrce_out_i[ce_index] <= wrce_expnd_i[ce_index] ;
end
end
end
endgenerate// end of generate GEN_BKEND_CE_REGISTERS
// Assign registered output signals
assign CS_Out = cs_out_i;
assign RdCE_Out = rdce_out_i;
assign WrCE_Out = wrce_out_i;
endmodule |
module wb_ram_xilinx (/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, rst, we, din, waddr, raddr
) ;
input clk;
input rst;
input [3:0] we;
input [31:0] din;
input [14:0] waddr;
input [14:0] raddr;
output wire [31:0] dout;
initial begin
$display("WB XILINX RAM");
end
wire bank_select = waddr[13] | raddr[13];
wire [31:0] dout_bank0;
wire [31:0] dout_bank1;
assign dout = bank_select ? dout_bank1 : dout_bank0;
wb_ram_xilinx_bank bank0(
// Outputs
.dout (dout_bank0[31:0]),
// Inputs
.clk (clk),
.rst (rst),
.bank_select (~bank_select),
.we (we[3:0]),
.din (din[31:0]),
.waddr (waddr[12:0]),
.raddr (raddr[12:0]));
wb_ram_xilinx_bank bank1(
// Outputs
.dout (dout_bank1[31:0]),
// Inputs
.clk (clk),
.rst (rst),
.bank_select (bank_select),
.we (we[3:0]),
.din (din[31:0]),
.waddr (waddr[12:0]),
.raddr (raddr[12:0]));
endmodule |
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module example (
input wire FCLK_IN,
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
//debug
output wire [15:0] DEBUG_D,
output wire LED1,
output wire LED2,
output wire LED3,
output wire LED4,
output wire LED5,
inout wire FPGA_BUTTON,
inout wire SDA,
inout wire SCL
);
wire [15:0] BUS_ADD;
wire BUS_CLK, BUS_RD, BUS_WR, BUS_RST;
assign BUS_CLK = FCLK_IN;
fx2_to_bus i_fx2_to_bus (
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.BUS_CLK(BUS_CLK),
.BUS_ADD(BUS_ADD),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CS_FPGA()
);
reset_gen i_reset_gen (
.CLK(BUS_CLK),
.RST(BUS_RST)
);
//MODULE ADREESSES
localparam GPIO_BASEADDR = 16'h0000;
localparam GPIO_HIGHADDR = 16'h000f;
// USER MODULES //
wire [1:0] GPIO_NOT_USED;
gpio #(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.IO_WIDTH(8),
.IO_DIRECTION(8'h1f) // 3 MSBs are input the rest output
) i_gpio (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO({FPGA_BUTTON, GPIO_NOT_USED, LED5, LED4, LED3, LED2, LED1})
);
assign GPIO_NOT_USED = {LED2, LED1};
//For simulation
initial begin
$dumpfile("mio_example.vcd");
$dumpvars(0);
end
assign SDA = 1'bz;
assign SCL = 1'bz;
assign DEBUG_D = 16'ha5a5;
`ifdef COCOTB_SIM
assign FPGA_BUTTON = 0;
`endif
endmodule |
module sim_fsusb_foot
(inout dp,
inout dm);
localparam HALFBIT = 41667;
localparam BIT = 83333;
reg vp_noise_inject;
reg vm_noise_inject;
reg vm_noise, vp_noise;
integer delay_amount;
initial begin
vp_noise = 1'b0;
vp_noise_inject = 1'b0;
#1_200_000_000;
forever begin
vp_noise = ~vp_noise;
vp_noise_inject = 1'b0;
#232238251;
vp_noise_inject = 1'b1;
#1895231;
end
end
initial begin
vm_noise = 1'b0;
vm_noise_inject = 1'b0;
#1_300_000_000;
forever begin
vm_noise = ~vm_noise;
vm_noise_inject = 1'b0;
#158983124;
vm_noise_inject = 1'b1;
#832389;
vm_noise_inject = 1'b0;
end
end
reg oe = 1'b0;
reg vp = 1'b1;
reg vm = 1'b0;
assign dp = vp_noise_inject ? vp_noise : (oe ? vp : 1'bz);
assign dm = vm_noise_inject ? vm_noise : (oe ? vm : 1'bz);
integer i;
wire [7:0] sync = 8'b1101_0101;
reg decoded, prev_state, save_bit;
integer byte_count, bit_count, num_rx_ones;
reg [7:0] rx_byte;
reg [7:0] rx_pkt[63:0];
`include "usb_pids.v"
`include "usb_defs.v"
integer tx_num_ones = 0;
/*
task tx_sync;
integer bit_cnt;
begin
vp = 1'b1;
vm = 1'b0;
oe = 1'b1;
#BIT;
for (bit_cnt = 0; bit_cnt < 8; bit_cnt = bit_cnt + 1) begin
vp = sync[bit_cnt];
vm = ~sync[bit_cnt];
#BIT;
end
tx_nrzi = 1'b1;
tx_prev_bit = 1'b1;
tx_num_ones = 1'b1;
end
endtask
*/
task tx_byte;
input [7:0] byte;
integer bit_cnt;
reg bit;
begin
for (bit_cnt = 0; bit_cnt < 8; bit_cnt = bit_cnt + 1) begin
bit = byte[bit_cnt]; // save some typing
if (bit) begin
tx_num_ones = tx_num_ones + 1'b1;
if (tx_num_ones >= 7) begin
// bit stuffing... throw a bit-flip in there
//nrzi = ~nrzi;
vp = ~vp;
vm = ~vm;
#BIT;
tx_num_ones = 0;
end
#BIT; // to send a "1" we just leave the lines the same
end else begin
// to send a "0" we toggle the lines
vp = ~vp;
vm = ~vm;
#BIT;
tx_num_ones = 0;
end
end
end
endtask
task tx_32bits_be;
input [31:0] bits;
begin
tx_byte(bits[31:24]);
tx_byte(bits[23:16]);
tx_byte(bits[15:8]);
tx_byte(bits[7:0]);
end
endtask
task tx_eop;
begin
vp = 1'b0;
vm = 1'b0;
#BIT;
#BIT;
vp = 1'b1;
#BIT;
oe = 1'b0;
end
endtask
task tx_warmup;
begin
oe = 1'b1;
vp = 1'b1;
vm = 1'b0;
#BIT;
end
endtask
task rx_data0;
integer len;
begin
len = byte_count - 3;
$display("%t rx data0 len %d ", $time, len);
#(2*BIT);
tx_warmup();
tx_byte(USB_SYNC);
tx_byte(PID_ACK);
tx_eop();
end
endtask
integer rx_in_cnt = 0;
task rx_in;
begin
$display("%t rx IN", $time);
#(2*BIT);
tx_warmup();
tx_byte(USB_SYNC);
if (rx_in_cnt == 0) begin
$display("%t sending NAK", $time);
tx_byte(PID_NAK);
end else if (rx_in_cnt == 5) begin
$display("not transmitting anything in response to this IN request...");
end else begin
if (rx_pkt[1] == 8'h91) begin
$display("%t received IN pkt on EP1", $time);
tx_byte(PID_DATA1); // TODO: toggle data0 / data1
tx_foot_pkt();
/*
for (i = 0; i < 64; i = i + 1) begin
//$display("%t tx 0x%02h", $time, 64-i);
tx_byte(64-i);
end
*/
end else if (rx_pkt[1] == 8'h00 | rx_pkt[1] == 8'h01 | rx_pkt[1] == USB_DEV_ADDR) begin
$display("%t responding to IN pkt on EP0", $time);
tx_byte(PID_DATA1);
// for now, always just a zero-length packet
tx_byte(0);
tx_byte(0);
end else begin
$display("%t unhandled IN request!", $time);
for (i = 0; i < 64; i = i + 1) begin
$display("rx %d = 0x%02h", $time, rx_pkt[i]);
//$display("%t tx 0x%02h", $time, 64-i);
//tx_byte(64-i);
end
end
end
tx_eop();
rx_in_cnt = rx_in_cnt + 1;
end
endtask
task tx_foot_pkt;
begin
tx_32bits_be(32'h0000abcd);
tx_32bits_be(32'h12345678);
tx_32bits_be(32'h01000200); // 0
tx_32bits_be(32'h03000400); // 2
tx_32bits_be(32'h05000600); // 4
tx_32bits_be(32'h07000800); // 6
tx_32bits_be(32'h09000a00); // 8
tx_32bits_be(32'h0b000c00); // 10
tx_32bits_be(32'h0d000e00); // 12
tx_32bits_be(32'h0f001000); // 14
tx_32bits_be(32'h00000000);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
tx_32bits_be(32'h0);
end
endtask
initial begin
oe = 1'b0;
vp = 1'b0;
vm = 1'b0;
//$printtimescale;
// wait for USB reset
wait(~dp && ~dm);
$display("%t usb reset start", $time);
wait(dp && ~dm);
$display("%t usb reset end", $time); // todo: time reset pulse length
wait(~dp && ~dm);
$display("%t usb reset2 start", $time);
wait(dp && ~dm);
$display("%t usb reset2 end", $time); // todo: time reset pulse length
forever begin
num_rx_ones = 0;
bit_count = 0;
byte_count = 0;
rx_byte = 8'h0;
prev_state = 1;
decoded = 0;
save_bit = 1; // this is set to 0 when we get a stuffed bit
wait(~dp);
//$display("%t fsusb pkt start", $time);
#41667; // shift to the middle of a bit period
for (i = 0; i < 8; i = i + 1) begin
//$display("%t sync bit", $time);
if (dp != ~dm) begin
$display("illegal usb state at %t", $time);
//#1000 $finish();
end
if (sync[i] != dm) begin
$display("sync fail at %t", $time);
//#1000 $finish();
end
#83333; // skip over a full bit
end
//$display("%t sync OK", $time);
// decode the NRZI data
while (~(dp == 0 & dm == 0)) begin
if (dp != ~dm) begin
$display("%t illegal usb state", $time);
//#1000 $finish();
end
if (prev_state != dm) begin
decoded = 0;
prev_state = dm;
if (num_rx_ones == 6) begin
$display("%t stuffed bit detected", $time);
save_bit = 0; // it's a stuffed bit; ignore it
end
else
save_bit = 1;
num_rx_ones = 0;
//$display("%t rx flip @ %d", $time, bit_count);
end else begin
decoded = 1;
num_rx_ones = num_rx_ones + 1;
save_bit = 1; // ones are never stuffed
if (num_rx_ones > 6) begin
$display("%t received more than 6 ones in a row.", $time);
//#100000 $finish();
end
//$display("%t rx same @ %d", $time, bit_count);
end
if (save_bit) begin
rx_byte = { decoded, rx_byte[7:1] };
bit_count = bit_count + 1;
end
if (bit_count == 8) begin
rx_pkt[byte_count] = rx_byte;
if (byte_count == 0) begin
case (rx_byte)
PID_SOF: $display("%t SOF", $time);
PID_SETUP: $display("%t SETUP", $time);
PID_DATA0: $display("%t DATA0", $time);
PID_IN : $display("%t IN", $time);
PID_ACK : $display("%t ACK", $time);
default: begin
$display("%t ERROR: rx unknown PID (0x%02h)", $time, rx_byte);
//$finish();
end
endcase
end
else
$display("%t rx 0x%02h", $time, rx_byte);
byte_count = byte_count + 1;
bit_count = 0;
end
#83333; // skip over a full bit
end
if (num_rx_ones == 6) begin
$display("%t expected to see bit-stuffing right before SE0", $time);
//#100000 $finish();
end
if (bit_count != 0) begin
$display("%t SE0 seen at non-byte boundary", $time);
//#5000 $finish();
end
//$display("%t found SE0", $time);
#83333;
if (dp != 0 | dm != 0) begin
$display("%t SE0 state wasn't two bits long", $time);
//#1000 $finish();
end
#83333;
if (dp != 1 | dm != 0) begin
$display("%t didn't finish EOP with J state", $time);
//#1000 $finish();
end
#83.333;
$display("%t packet RX complete", $time);
case (rx_pkt[0])
PID_SOF: ;
PID_SETUP: ;
PID_DATA0: rx_data0();
PID_IN: rx_in();
PID_ACK: ;
default: begin
$display("%t unknown rx PID (0x%02h)", $time, rx_pkt[0]);
//$finish();
end
endcase
//if (rx_pkt[0] == PID_DATA0)
// rx_data0();
end
end
endmodule |
module testbench();
localparam width_p = 32;
localparam ring_width_p = width_p*2 + 3;
localparam rom_addr_width_p = 32;
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(10)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic v_r;
logic [width_p-1:0] a_r;
logic [width_p-1:0] b_r;
logic eq_lo;
logic lt_lo;
logic le_lo;
logic [width_p-1:0] min_lo;
logic [width_p-1:0] max_lo;
bsg_fpu_cmp #(
.e_p(8)
,.m_p(23)
) dut (
.a_i(a_r)
,.b_i(b_r)
,.eq_o(eq_lo)
,.lt_o(lt_lo)
,.le_o(le_lo)
,.lt_le_invalid_o()
,.eq_invalid_o()
,.min_o(min_lo)
,.max_o(max_lo)
,.min_max_invalid_o()
);
logic [ring_width_p-1:0] tr_data_li;
logic tr_ready_lo;
logic tr_v_lo;
logic [ring_width_p-1:0] tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [ring_width_p+4-1:0] rom_data;
logic done_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_r)
,.data_i(tr_data_li)
,.ready_o(tr_ready_lo)
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_lo)
,.error_o()
);
bsg_fpu_trace_rom #(
.width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
assign tr_data_li = {
eq_lo
, lt_lo
, le_lo
, min_lo
, max_lo
};
logic [width_p-1:0] a_n, b_n;
logic v_n;
always_comb begin
if (v_r == 1'b0) begin
tr_yumi_li = tr_v_lo;
v_n = tr_v_lo;
{a_n, b_n} = tr_v_lo
? tr_data_lo[0+:width_p*2]
: {a_r, b_r};
end
else begin
tr_yumi_li = 1'b0;
v_n = tr_ready_lo
? 1'b0
: v_r;
{a_n, b_n} = {a_r, b_r};
end
end
always_ff @ (posedge clk) begin
if (reset) begin
v_r <= 1'b0;
a_r <= '0;
b_r <= '0;
end
else begin
v_r <= v_n;
a_r <= a_n;
b_r <= b_n;
end
end
initial begin
wait(done_lo);
$finish;
end
endmodule |
module SCB_P4_v1_20_0 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("8c8734ef-3644-4eed-bc55-360072b94fff/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("41666666.6666667"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
wire [0:0] tmpOE__ss_s_net;
wire [0:0] tmpIO_0__ss_s_net;
wire [0:0] tmpINTERRUPT_0__ss_s_net;
electrical [0:0] tmpSIOVREF__ss_s_net;
cy_psoc3_pins_v1_10
#(.id("8c8734ef-3644-4eed-bc55-360072b94fff/3446580a-3b9d-491c-8730-f7ea34ca86e3"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
ss_s
(.oe(tmpOE__ss_s_net),
.y({1'b0}),
.fb({Net_458}),
.io({tmpIO_0__ss_s_net[0:0]}),
.siovref(tmpSIOVREF__ss_s_net),
.interrupt({tmpINTERRUPT_0__ss_s_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__ss_s_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_458;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_452;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_387;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_252;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__miso_s_net;
wire [0:0] tmpFB_0__miso_s_net;
wire [0:0] tmpIO_0__miso_s_net;
wire [0:0] tmpINTERRUPT_0__miso_s_net;
electrical [0:0] tmpSIOVREF__miso_s_net;
cy_psoc3_pins_v1_10
#(.id("8c8734ef-3644-4eed-bc55-360072b94fff/52f31aa9-2f0a-497d-9a1f-1424095e13e6"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
miso_s
(.oe(tmpOE__miso_s_net),
.y({Net_703}),
.fb({tmpFB_0__miso_s_net[0:0]}),
.io({tmpIO_0__miso_s_net[0:0]}),
.siovref(tmpSIOVREF__miso_s_net),
.interrupt({tmpINTERRUPT_0__miso_s_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__miso_s_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
wire [0:0] tmpOE__sclk_s_net;
wire [0:0] tmpIO_0__sclk_s_net;
wire [0:0] tmpINTERRUPT_0__sclk_s_net;
electrical [0:0] tmpSIOVREF__sclk_s_net;
cy_psoc3_pins_v1_10
#(.id("8c8734ef-3644-4eed-bc55-360072b94fff/4c15b41e-e284-4978-99e7-5aaee19bd0ce"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
sclk_s
(.oe(tmpOE__sclk_s_net),
.y({1'b0}),
.fb({Net_387}),
.io({tmpIO_0__sclk_s_net[0:0]}),
.siovref(tmpSIOVREF__sclk_s_net),
.interrupt({tmpINTERRUPT_0__sclk_s_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__sclk_s_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__mosi_s_net;
wire [0:0] tmpIO_0__mosi_s_net;
wire [0:0] tmpINTERRUPT_0__mosi_s_net;
electrical [0:0] tmpSIOVREF__mosi_s_net;
cy_psoc3_pins_v1_10
#(.id("8c8734ef-3644-4eed-bc55-360072b94fff/5e2b647c-52cb-4f09-80bd-87ed9563ab24"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
mosi_s
(.oe(tmpOE__mosi_s_net),
.y({1'b0}),
.fb({Net_252}),
.io({tmpIO_0__mosi_s_net[0:0]}),
.siovref(tmpSIOVREF__mosi_s_net),
.interrupt({tmpINTERRUPT_0__mosi_s_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__mosi_s_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 1;
endmodule |
module SCB_P4_v1_20_1 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("723379629.62963"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_379;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
tx
(.oe(tmpOE__tx_net),
.y({Net_656}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_379}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 2;
endmodule |
module top ;
wire Net_12;
wire Net_10;
wire Net_20;
wire Net_19;
wire Net_11;
wire Net_14;
SCB_P4_v1_20_0 SPI (
.sclk(Net_19),
.interrupt(Net_14),
.clock(1'b0));
SCB_P4_v1_20_1 UART (
.sclk(Net_10),
.interrupt(Net_11),
.clock(1'b0));
cy_isr_v1_0
#(.int_type(2'b10))
isr_SPI
(.int_signal(Net_14));
cy_isr_v1_0
#(.int_type(2'b10))
isr_UART
(.int_signal(Net_11));
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
lab3_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
lab3_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim0_inst_CLK (hps_io_spim0_inst_CLK), // .hps_io_spim0_inst_CLK
.hps_io_spim0_inst_MOSI (hps_io_spim0_inst_MOSI), // .hps_io_spim0_inst_MOSI
.hps_io_spim0_inst_MISO (hps_io_spim0_inst_MISO), // .hps_io_spim0_inst_MISO
.hps_io_spim0_inst_SS0 (hps_io_spim0_inst_SS0), // .hps_io_spim0_inst_SS0
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL) // .hps_io_i2c1_inst_SCL
);
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
(D,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_o,
gpio_io_t,
Q,
bus2ip_rnw_i_reg,
\Not_Dual.gpio_Data_In_reg[4]_0 ,
s_axi_aclk,
\Not_Dual.gpio_Data_In_reg[3]_0 ,
\Not_Dual.gpio_Data_In_reg[2]_0 ,
\Not_Dual.gpio_Data_In_reg[1]_0 ,
GPIO_DBus_i,
SS,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
E,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
rst_reg);
output [4:0]D;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [4:0]gpio_io_o;
output [4:0]gpio_io_t;
output [4:0]Q;
input bus2ip_rnw_i_reg;
input \Not_Dual.gpio_Data_In_reg[4]_0 ;
input s_axi_aclk;
input \Not_Dual.gpio_Data_In_reg[3]_0 ;
input \Not_Dual.gpio_Data_In_reg[2]_0 ;
input \Not_Dual.gpio_Data_In_reg[1]_0 ;
input [0:0]GPIO_DBus_i;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [4:0]gpio_io_i;
input [0:0]E;
input [4:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
input [0:0]rst_reg;
wire [4:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [4:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \Not_Dual.gpio_Data_In_reg[1]_0 ;
wire \Not_Dual.gpio_Data_In_reg[2]_0 ;
wire \Not_Dual.gpio_Data_In_reg[3]_0 ;
wire \Not_Dual.gpio_Data_In_reg[4]_0 ;
wire [4:0]Q;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire bus2ip_rnw_i_reg;
wire [4:0]gpio_io_i;
wire [0:4]gpio_io_i_d2;
wire [4:0]gpio_io_o;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire [0:0]rst_reg;
wire s_axi_aclk;
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus_i),
.Q(D[4]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_Data_In_reg[1]_0 ),
.Q(D[3]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_Data_In_reg[2]_0 ),
.Q(D[2]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_Data_In_reg[3]_0 ),
.Q(D[1]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_Data_In_reg[4]_0 ),
.Q(D[0]),
.R(bus2ip_rnw_i_reg));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \Not_Dual.INPUT_DOUBLE_REGS3
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4]}));
FDRE \Not_Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(Q[4]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(Q[3]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(Q[1]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[4]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
iGPIO_xferAck_i_1
(.I0(bus2ip_cs),
.I1(gpio_xferAck_Reg),
.I2(GPIO_xferAck_i),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_arready,
s_axi_wready,
GPIO_DBus_i,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ,
D,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ,
s_axi_aclk,
rst_reg,
bus2ip_rnw_i_reg,
Q,
ip2bus_rdack_i_D1,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
ip2bus_wrack_i_D1,
is_write_reg,
\Not_Dual.gpio_Data_In_reg[0] ,
gpio_io_t,
s_axi_wdata,
start2_reg,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_arready;
output s_axi_wready;
output [0:0]GPIO_DBus_i;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
output [4:0]D;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ;
input s_axi_aclk;
input rst_reg;
input bus2ip_rnw_i_reg;
input [2:0]Q;
input ip2bus_rdack_i_D1;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input ip2bus_wrack_i_D1;
input is_write_reg;
input [4:0]\Not_Dual.gpio_Data_In_reg[0] ;
input [4:0]gpio_io_t;
input [9:0]s_axi_wdata;
input start2_reg;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
wire [4:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
wire [4:0]\Not_Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [2:0]Q;
wire bus2ip_rnw_i_reg;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [9:0]s_axi_wdata;
wire s_axi_wready;
wire start2_reg;
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(start2_reg),
.I2(s_axi_aresetn),
.I3(s_axi_arready),
.I4(s_axi_wready),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
LUT6 #(
.INIT(64'h000000E000000020))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i[27]_i_1
(.I0(\Not_Dual.gpio_Data_In_reg[0] [4]),
.I1(Q[0]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(Q[2]),
.I4(Q[1]),
.I5(gpio_io_t[4]),
.O(GPIO_DBus_i));
LUT6 #(
.INIT(64'h000000E000000020))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i[28]_i_1
(.I0(\Not_Dual.gpio_Data_In_reg[0] [3]),
.I1(Q[0]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(Q[2]),
.I4(Q[1]),
.I5(gpio_io_t[3]),
.O(\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ));
LUT6 #(
.INIT(64'h000000E000000020))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i[29]_i_1
(.I0(\Not_Dual.gpio_Data_In_reg[0] [2]),
.I1(Q[0]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(Q[2]),
.I4(Q[1]),
.I5(gpio_io_t[2]),
.O(\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ));
LUT6 #(
.INIT(64'h000000E000000020))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i[30]_i_1
(.I0(\Not_Dual.gpio_Data_In_reg[0] [1]),
.I1(Q[0]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(Q[2]),
.I4(Q[1]),
.I5(gpio_io_t[1]),
.O(\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ));
LUT4 #(
.INIT(16'hFFF7))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(gpio_xferAck_Reg),
.I3(GPIO_xferAck_i),
.O(\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ));
LUT6 #(
.INIT(64'h000000E000000020))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_2
(.I0(\Not_Dual.gpio_Data_In_reg[0] [0]),
.I1(Q[0]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(Q[2]),
.I4(Q[1]),
.I5(gpio_io_t[0]),
.O(\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAABAA))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(rst_reg),
.I1(bus2ip_rnw_i_reg),
.I2(Q[0]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(Q[2]),
.I5(Q[1]),
.O(E));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[4]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[9]),
.O(D[4]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[3]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[8]),
.O(D[3]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[2]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[7]),
.O(D[2]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[1]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[6]),
.O(D[1]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[0]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[5]),
.O(D[0]));
LUT6 #(
.INIT(64'hAAAAAAAAAABAAAAA))
\Not_Dual.gpio_OE[0]_i_1
(.I0(rst_reg),
.I1(bus2ip_rnw_i_reg),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(Q[2]),
.I4(Q[0]),
.I5(Q[1]),
.O(\Not_Dual.gpio_OE_reg[0] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(is_read),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(is_write_reg),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_wready));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [4:0]gpio_io_i;
output [4:0]gpio_io_o;
output [4:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_10;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_19;
wire AXI_LITE_IPIF_I_n_6;
wire AXI_LITE_IPIF_I_n_7;
wire [0:4]DBus_Reg;
wire [27:27]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:4]gpio_Data_In;
wire gpio_core_1_n_8;
wire [4:0]gpio_io_i;
wire [4:0]gpio_io_o;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [27:31]ip2bus_data;
wire [27:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [4:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4:0] = \^s_axi_rdata [4:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] (AXI_LITE_IPIF_I_n_19),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_10),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_11),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_12),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_13),
.\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4]}),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[27] ({ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[31:27],s_axi_wdata[4:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
(.D({ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4]}),
.\Not_Dual.gpio_Data_In_reg[1]_0 (AXI_LITE_IPIF_I_n_10),
.\Not_Dual.gpio_Data_In_reg[2]_0 (AXI_LITE_IPIF_I_n_11),
.\Not_Dual.gpio_Data_In_reg[3]_0 (AXI_LITE_IPIF_I_n_12),
.\Not_Dual.gpio_Data_In_reg[4]_0 (AXI_LITE_IPIF_I_n_13),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4]}),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_19),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_8),
.rst_reg(AXI_LITE_IPIF_I_n_7),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_8),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
bus2ip_cs,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
GPIO_DBus_i,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ,
D,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
Q,
gpio_io_t,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[27] );
output bus2ip_reset;
output bus2ip_rnw;
output bus2ip_cs;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [0:0]GPIO_DBus_i;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
output [4:0]D;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ;
output [4:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [4:0]Q;
input [4:0]gpio_io_t;
input [9:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [4:0]\ip2bus_data_i_D1_reg[27] ;
wire [4:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [4:0]Q;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [4:0]\ip2bus_data_i_D1_reg[27] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [4:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [9:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ),
.\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q(Q),
.SR(bus2ip_reset),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[27] (\ip2bus_data_i_D1_reg[27] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
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