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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [4:0]scndry_vect_out;
input [4:0]gpio_io_i;
input s_axi_aclk;
wire [4:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire [4:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(SR,
\Not_Dual.gpio_Data_Out_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
GPIO_DBus_i,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ,
D,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
Q,
gpio_io_t,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[27] );
output SR;
output \Not_Dual.gpio_Data_Out_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [0:0]GPIO_DBus_i;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
output [4:0]D;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ;
output [4:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [4:0]Q;
input [4:0]gpio_io_t;
input [9:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [4:0]\ip2bus_data_i_D1_reg[27] ;
wire [4:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
wire \Not_Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [4:0]Q;
wire SR;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire bus2ip_rnw_i06_out;
wire clear;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [4:0]\ip2bus_data_i_D1_reg[27] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [1:0]p_0_out;
wire p_1_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [4:0]s_axi_rdata;
wire \s_axi_rdata_i[4]_i_1_n_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [9:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ),
.\Not_Dual.gpio_Data_In_reg[0] (Q),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Not_Dual.gpio_Data_Out_reg[0] ),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.rst_reg(SR),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2_reg(start2));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[0]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h10))
bus2ip_rnw_i_i_1
(.I0(state[0]),
.I1(state[1]),
.I2(s_axi_arvalid),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(\Not_Dual.gpio_Data_Out_reg[0] ),
.R(SR));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(SR));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_1_in));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(SR));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[4]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\s_axi_rdata_i[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[4]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[27] [0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[4]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[27] [1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[4]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[27] [2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[4]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[27] [3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[4]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[27] [4]),
.Q(s_axi_rdata[4]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(state[0]),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(s_axi_wready),
.O(p_0_out[0]));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(\state[1]_i_3_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arready),
.O(p_0_out[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[0]),
.Q(state[0]),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[1]),
.Q(state[1]),
.R(SR));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [4:0]gpio_io_i;
wire [4:0]gpio_io_i;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [4:0]NLW_U0_gpio_io_o_UNCONNECTED;
wire [4:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "1" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "5" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[4:0]),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[4:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module top();
// Inputs are registered
reg D;
reg SET_ASYNC;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SET_ASYNC = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SET_ASYNC = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 SET_ASYNC = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 SET_ASYNC = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 SET_ASYNC = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 SET_ASYNC = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$PSa_pp$PKG$s dut (.D(D), .SET_ASYNC(SET_ASYNC), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule |
module MyReconfigLogic (
input Reset_n_i,
input Clk_i,
input AdcConvComplete_i,
output AdcDoConvert_o,
input[9:0] AdcValue_i,
input I2C_Busy_i,
output[7:0] I2C_DataIn_o,
input[7:0] I2C_DataOut_i,
output[15:0] I2C_Divider800_o,
output I2C_ErrAckParam_o,
input I2C_Error_i,
output I2C_F100_400_n_o,
input I2C_FIFOEmpty_i,
input I2C_FIFOFull_i,
output I2C_FIFOReadNext_o,
output I2C_FIFOWrite_o,
output[3:0] I2C_ReadCount_o,
output I2C_ReceiveSend_n_o,
output I2C_StartProcess_o,
input[7:0] Inputs_i,
output[7:0] Outputs_o,
output[4:0] ReconfModuleIRQs_o,
output SPI_CPHA_o,
output SPI_CPOL_o,
output[7:0] SPI_DataIn_o,
input[7:0] SPI_DataOut_i,
input SPI_FIFOEmpty_i,
input SPI_FIFOFull_i,
output SPI_LSBFE_o,
output SPI_ReadNext_o,
output[7:0] SPI_SPPR_SPR_o,
input SPI_Transmission_i,
output SPI_Write_o,
input[7:0] ReconfModuleIn_i,
output[7:0] ReconfModuleOut_o,
input[7:0] I2C_Errors_i,
input[13:0] PerAddr_i,
input[15:0] PerDIn_i,
input[1:0] PerWr_i,
input PerEn_i,
output[15:0] CfgIntfDOut_o,
output[15:0] ParamIntfDOut_o
);
wire [7:0] I2C_ReadCount_s;
wire [15:0] PeriodCounterPreset_s;
wire [15:0] SensorValue_s;
wire [15:0] Threshold_s;
wire [15:0] WaitCounterPreset_s;
wire [0:0] CfgClk_s;
wire CfgMode_s;
wire [0:0] CfgShift_s;
wire CfgDataOut_s;
wire [0:0] CfgDataIn_s;
wire [2:0] ParamWrAddr_s;
wire [15:0] ParamWrData_s;
wire ParamWr_s;
wire [0:0] ParamRdAddr_s;
wire [15:0] ParamRdData_s;
TODO: implement
wire Params_s;
wire [0:0] I2C_ErrAckParam_s;
wire ParamI2C_Divider800Enable_s;
wire ParamI2C_ErrAckParamEnable_s;
wire ParamPeriodCounterPresetEnable_s;
wire ParamThresholdEnable_s;
wire ParamWaitCounterPresetEnable_s;
// Configuration Interface
CfgIntf #(
.BaseAddr('h0180),
.NumCfgs(1)
) CfgIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(CfgIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.CfgClk_o(CfgClk_s),
.CfgMode_o(CfgMode_s),
.CfgShift_o(CfgShift_s),
.CfgDataOut_o(CfgDataOut_s),
.CfgDataIn_i(CfgDataIn_s)
);
// Parameterization Interface: 5 write addresses, 2 read addresses
ParamIntf #(
.BaseAddr('h0188),
.WrAddrWidth(3),
.RdAddrWidth(1)
) ParamIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(ParamIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.ParamWrAddr_o(ParamWrAddr_s),
.ParamWrData_o(ParamWrData_s),
.ParamWr_o(ParamWr_s),
.ParamRdAddr_o(ParamRdAddr_s),
.ParamRdData_i(ParamRdData_s)
);
ADT7410 ADT7410_0 (
.I2C_Busy_i(I2C_Busy_i),
.I2C_Data_o(I2C_DataIn_o),
.I2C_Data_i(I2C_DataOut_i),
.I2C_Error_i(I2C_Error_i),
.I2C_FIFOReadNext_o(I2C_FIFOReadNext_o),
.I2C_FIFOWrite_o(I2C_FIFOWrite_o),
.I2C_ReadCount_o(I2C_ReadCount_s),
.I2C_ReceiveSend_n_o(I2C_ReceiveSend_n_o),
.I2C_StartProcess_o(I2C_StartProcess_o),
.CpuIntr_o(ReconfModuleIRQs_o[0]),
.Enable_i(ReconfModuleIn_i[0]),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i),
.PeriodCounterPreset_i(PeriodCounterPreset_s),
.SensorValue_o(SensorValue_s),
.Threshold_i(Threshold_s),
.WaitCounterPreset_i(WaitCounterPreset_s)
);
assign AdcDoConvert_o = 1'b0;
assign I2C_F100_400_n_o = 1'b1;
assign I2C_ReadCount_o = I2C_ReadCount_s[3:0];
assign Outputs_o[0] = 1'b0;
assign Outputs_o[1] = 1'b0;
assign Outputs_o[2] = 1'b0;
assign Outputs_o[3] = 1'b0;
assign Outputs_o[4] = 1'b0;
assign Outputs_o[5] = 1'b0;
assign Outputs_o[6] = 1'b0;
assign Outputs_o[7] = 1'b0;
assign ReconfModuleIRQs_o[1] = 1'b0;
assign ReconfModuleIRQs_o[2] = 1'b0;
assign ReconfModuleIRQs_o[3] = 1'b0;
assign ReconfModuleIRQs_o[4] = 1'b0;
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_DataIn_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign SPI_ReadNext_o = 1'b0;
assign SPI_SPPR_SPR_o = 8'b00000000;
assign SPI_Write_o = 1'b0;
assign ReconfModuleOut_o[0] = 1'b0;
assign ReconfModuleOut_o[1] = 1'b0;
assign ReconfModuleOut_o[2] = 1'b0;
assign ReconfModuleOut_o[3] = 1'b0;
assign ReconfModuleOut_o[4] = 1'b0;
assign ReconfModuleOut_o[5] = 1'b0;
assign ReconfModuleOut_o[6] = 1'b0;
assign ReconfModuleOut_o[7] = 1'b0;
/* just a fixed value for the config interface */
assign CfgDataIn_s = 1'b0;
/* Param read address decoder
Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
hope that the synthesis optimizes the MUX
Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
0 to n.", even during param write cycles, because ParamRdAddr has the
source as ParamWrAddr. Use the parameter "-noindexcheck" during
compilation ("vcom"). Simulation works fine then, but ModelSim generates
numerous "INTERNAL ERROR"s to stdout, which seem harmless. */
assign ParamRdData_s = Params_s[to_integer(unsigned(ParamRdAddr_s))];
ParamOutReg #(
.Width(16)
) ParamOutReg_I2C_Divider800 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_Divider800_o),
.Enable_i(ParamI2C_Divider800Enable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(1)
) ParamOutReg_I2C_ErrAckParam (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_ErrAckParam_s),
.Enable_i(ParamI2C_ErrAckParamEnable_s),
.ParamWrData_i(ParamWrData_s[0:0])
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPreset (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPreset_s),
.Enable_i(ParamPeriodCounterPresetEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_Threshold (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(Threshold_s),
.Enable_i(ParamThresholdEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_WaitCounterPreset (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(WaitCounterPreset_s),
.Enable_i(ParamWaitCounterPresetEnable_s),
.ParamWrData_i(ParamWrData_s)
);
assign I2C_ErrAckParam_o = I2C_ErrAckParam_s[0];
/* Address $00 */
assign Params_s[0] = { 8'b00000000, I2C_Errors_i };
/* Address $01 */
assign Params_s[1] = SensorValue_s;
/* Address $00 */
assign ParamI2C_Divider800Enable_s = TODO: implement;
/* Address $01 */
assign ParamI2C_ErrAckParamEnable_s = TODO: implement;
/* Address $02 */
assign ParamPeriodCounterPresetEnable_s = TODO: implement;
/* Address $03 */
assign ParamThresholdEnable_s = TODO: implement;
/* Address $04 */
assign ParamWaitCounterPresetEnable_s = TODO: implement;
endmodule |
module FB_InjectorController
(
input wire clk,
//input events
input wire InjectorArmFinishedMovement_eI,
input wire EmergencyStopChanged_eI,
input wire CanisterPressureChanged_eI,
input wire FillContentsAvailableChanged_eI,
input wire ConveyorStoppedForInject_eI,
input wire VacuumTimerElapsed_eI,
//output events
output wire InjectDone_eO,
output wire InjectorPositionChanged_eO,
output wire InjectorControlsChanged_eO,
output wire RejectCanister_eO,
output wire FillContentsChanged_eO,
output wire StartVacuumTimer_eO,
output wire InjectRunning_eO,
//input variables
input wire EmergencyStop_I,
input wire [7:0] CanisterPressure_I,
input wire [7:0] FillContentsAvailable_I,
//output variables
output wire [7:0] InjectorPosition_O ,
output wire InjectorContentsValveOpen_O ,
output wire InjectorVacuumRun_O ,
output wire InjectorPressurePumpRun_O ,
output wire FillContents_O ,
input reset
);
//Wires needed for event connections
wire InjectorArmFinishedMovement_conn;
wire EmergencyStopChanged_conn;
wire CanisterPressureChanged_conn;
wire FillContentsAvailableChanged_conn;
wire ConveyorStoppedForInject_conn;
wire VacuumTimerElapsed_conn;
wire Arm_InjectDone_conn;
wire Arm_InjectorPositionChanged_conn;
wire Pumps_InjectorControlsChanged_conn;
wire Pumps_RejectCanister_conn;
wire Pumps_FillContentsChanged_conn;
wire Pumps_StartVacuumTimer_conn;
wire Arm_InjectRunning_conn;
wire Arm_StartPump_conn;
wire Pumps_PumpFinished_conn;
//Wires needed for data connections
wire EmergencyStop_conn;
wire [7:0] CanisterPressure_conn;
wire [7:0] FillContentsAvailable_conn;
wire [7:0] Arm_InjectorPosition_conn;
wire Pumps_InjectorContentsValveOpen_conn;
wire Pumps_InjectorVacuumRun_conn;
wire Pumps_InjectorPressurePumpRun_conn;
wire Pumps_FillContents_conn;
//top level I/O to signals
//input events
assign InjectorArmFinishedMovement_conn = InjectorArmFinishedMovement_eI;
assign EmergencyStopChanged_conn = EmergencyStopChanged_eI;
assign EmergencyStopChanged_conn = EmergencyStopChanged_eI;
assign CanisterPressureChanged_conn = CanisterPressureChanged_eI;
assign FillContentsAvailableChanged_conn = FillContentsAvailableChanged_eI;
assign ConveyorStoppedForInject_conn = ConveyorStoppedForInject_eI;
assign VacuumTimerElapsed_conn = VacuumTimerElapsed_eI;
//output events
assign InjectDone_eO = Arm_InjectDone_conn;
assign InjectorPositionChanged_eO = Arm_InjectorPositionChanged_conn;
assign InjectorControlsChanged_eO = Pumps_InjectorControlsChanged_conn;
assign RejectCanister_eO = Pumps_RejectCanister_conn;
assign FillContentsChanged_eO = Pumps_FillContentsChanged_conn;
assign StartVacuumTimer_eO = Pumps_StartVacuumTimer_conn;
assign InjectRunning_eO = Arm_InjectRunning_conn;
//input variables
assign EmergencyStop_conn = EmergencyStop_I;
assign EmergencyStop_conn = EmergencyStop_I;
assign CanisterPressure_conn = CanisterPressure_I;
assign FillContentsAvailable_conn = FillContentsAvailable_I;
//output events
assign InjectorPosition_O = Arm_InjectorPosition_conn;
assign InjectorContentsValveOpen_O = Pumps_InjectorContentsValveOpen_conn;
assign InjectorVacuumRun_O = Pumps_InjectorVacuumRun_conn;
assign InjectorPressurePumpRun_O = Pumps_InjectorPressurePumpRun_conn;
assign FillContents_O = Pumps_FillContents_conn;
// child I/O to signals
FB_InjectorMotorController Arm (
.clk(clk),
//event outputs
.InjectDone_eO(Arm_InjectDone_conn),
.InjectorPositionChanged_eO(Arm_InjectorPositionChanged_conn),
.InjectRunning_eO(Arm_InjectRunning_conn),
.StartPump_eO(Arm_StartPump_conn),
//event inputs
.InjectorArmFinishedMovement_eI(InjectorArmFinishedMovement_conn),
.EmergencyStopChanged_eI(EmergencyStopChanged_conn),
.ConveyorStoppedForInject_eI(ConveyorStoppedForInject_conn),
.PumpFinished_eI(Pumps_PumpFinished_conn),
//data outputs
.InjectorPosition_O(Arm_InjectorPosition_conn),
//data inputs
.EmergencyStop_I(EmergencyStop_conn),
.reset(reset)
);
FB_InjectorPumpsController Pumps (
.clk(clk),
//event outputs
.InjectorControlsChanged_eO(Pumps_InjectorControlsChanged_conn),
.RejectCanister_eO(Pumps_RejectCanister_conn),
.FillContentsChanged_eO(Pumps_FillContentsChanged_conn),
.StartVacuumTimer_eO(Pumps_StartVacuumTimer_conn),
.PumpFinished_eO(Pumps_PumpFinished_conn),
//event inputs
.EmergencyStopChanged_eI(EmergencyStopChanged_conn),
.CanisterPressureChanged_eI(CanisterPressureChanged_conn),
.FillContentsAvailableChanged_eI(FillContentsAvailableChanged_conn),
.VacuumTimerElapsed_eI(VacuumTimerElapsed_conn),
.StartPump_eI(Arm_StartPump_conn),
//data outputs
.InjectorContentsValveOpen_O(Pumps_InjectorContentsValveOpen_conn),
.InjectorVacuumRun_O(Pumps_InjectorVacuumRun_conn),
.InjectorPressurePumpRun_O(Pumps_InjectorPressurePumpRun_conn),
.FillContents_O(Pumps_FillContents_conn),
//data inputs
.EmergencyStop_I(EmergencyStop_conn),
.CanisterPressure_I(CanisterPressure_conn),
.FillContentsAvailable_I(FillContentsAvailable_conn),
.reset(reset)
);
endmodule |
module sky130_fd_sc_ms__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_lp__dlrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module design_1_axi_gpio_0_0_GPIO_Core
(GPIO2_DBus_i,
GPIO_DBus_i,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_o,
gpio_io_t,
gpio2_io_o,
gpio2_io_t,
Q,
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ,
Read_Reg_Rst,
Read_Reg2_In,
s_axi_aclk,
Read_Reg_In,
SS,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
gpio2_io_i,
E,
s_axi_wdata,
bus2ip_rnw_i_reg,
bus2ip_rnw_i_reg_0,
bus2ip_rnw_i_reg_1);
output [3:0]GPIO2_DBus_i;
output [3:0]GPIO_DBus_i;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
output [3:0]gpio2_io_o;
output [3:0]gpio2_io_t;
output [3:0]Q;
output [3:0]\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
input Read_Reg_Rst;
input [0:3]Read_Reg2_In;
input s_axi_aclk;
input [0:3]Read_Reg_In;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [3:0]gpio_io_i;
input [3:0]gpio2_io_i;
input [0:0]E;
input [3:0]s_axi_wdata;
input [0:0]bus2ip_rnw_i_reg;
input [0:0]bus2ip_rnw_i_reg_0;
input [0:0]bus2ip_rnw_i_reg_1;
wire [3:0]\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire [0:0]bus2ip_rnw_i_reg_1;
wire [3:0]gpio2_io_i;
wire [0:3]gpio2_io_i_d2;
wire [3:0]gpio2_io_o;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_i;
wire [0:3]gpio_io_i_d2;
wire [3:0]gpio_io_o;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire s_axi_aclk;
wire [3:0]s_axi_wdata;
design_1_axi_gpio_0_0_cdc_sync \Dual.INPUT_DOUBLE_REGS4
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
design_1_axi_gpio_0_0_cdc_sync_0 \Dual.INPUT_DOUBLE_REGS5
(.gpio2_io_i(gpio2_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3]}));
FDRE \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[0]),
.Q(GPIO2_DBus_i[3]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[1]),
.Q(GPIO2_DBus_i[2]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[2]),
.Q(GPIO2_DBus_i[1]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[3]),
.Q(GPIO2_DBus_i[0]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[0]),
.Q(GPIO_DBus_i[3]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[1]),
.Q(GPIO_DBus_i[2]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[2]),
.Q(GPIO_DBus_i[1]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[3]),
.Q(GPIO_DBus_i[0]),
.R(Read_Reg_Rst));
FDRE \Dual.gpio2_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[0]),
.Q(Q[3]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[1]),
.Q(Q[2]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[2]),
.Q(Q[1]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[3]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[3]),
.Q(gpio2_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[2]),
.Q(gpio2_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[1]),
.Q(gpio2_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[0]),
.Q(gpio2_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[3]),
.Q(gpio2_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[2]),
.Q(gpio2_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[1]),
.Q(gpio2_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[0]),
.Q(gpio2_io_t[0]),
.S(SS));
FDRE \Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [3]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [2]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [1]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[0]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h04))
iGPIO_xferAck_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_cs),
.I2(gpio_xferAck_Reg),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule |
module design_1_axi_gpio_0_0_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
s_axi_arready,
s_axi_wready,
Read_Reg2_In,
E,
\Dual.gpio2_Data_Out_reg[0] ,
D,
Read_Reg_In,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_aclk,
Q,
is_read,
ip2bus_rdack_i_D1,
is_write_reg,
ip2bus_wrack_i_D1,
gpio2_io_t,
\Dual.gpio2_Data_In_reg[0] ,
\bus2ip_addr_i_reg[8] ,
bus2ip_rnw_i_reg,
rst_reg,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
gpio_xferAck_Reg,
GPIO_xferAck_i,
start2,
s_axi_aresetn);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output s_axi_arready;
output s_axi_wready;
output [0:3]Read_Reg2_In;
output [0:0]E;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [3:0]D;
output [0:3]Read_Reg_In;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output Read_Reg_Rst;
input s_axi_aclk;
input [3:0]Q;
input is_read;
input ip2bus_rdack_i_D1;
input is_write_reg;
input ip2bus_wrack_i_D1;
input [3:0]gpio2_io_t;
input [3:0]\Dual.gpio2_Data_In_reg[0] ;
input [2:0]\bus2ip_addr_i_reg[8] ;
input bus2ip_rnw_i_reg;
input rst_reg;
input [3:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input start2;
input s_axi_aresetn;
wire [3:0]D;
wire [3:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [2:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_wready;
wire start2;
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[28]_i_1
(.I0(gpio2_io_t[3]),
.I1(\Dual.gpio2_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[0]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[29]_i_1
(.I0(gpio2_io_t[2]),
.I1(\Dual.gpio2_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[1]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[30]_i_1
(.I0(gpio2_io_t[1]),
.I1(\Dual.gpio2_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[2]));
LUT4 #(
.INIT(16'hFFDF))
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(gpio_xferAck_Reg),
.I2(bus2ip_rnw_i_reg),
.I3(GPIO_xferAck_i),
.O(Read_Reg_Rst));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_2
(.I0(gpio2_io_t[0]),
.I1(\Dual.gpio2_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[3]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1
(.I0(gpio_io_t[3]),
.I1(\Dual.gpio_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[0]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1
(.I0(gpio_io_t[2]),
.I1(\Dual.gpio_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[1]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1
(.I0(gpio_io_t[1]),
.I1(\Dual.gpio_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[2]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1
(.I0(gpio_io_t[0]),
.I1(\Dual.gpio_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[3]));
LUT6 #(
.INIT(64'hFFFFFFFF00001000))
\Dual.gpio2_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(\Dual.gpio2_Data_Out_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFFF10000000))
\Dual.gpio2_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(E));
LUT6 #(
.INIT(64'hFFFFFFFF00000100))
\Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(\Dual.gpio_Data_Out_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFFF00040000))
\Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(rst_reg),
.O(\Dual.gpio_OE_reg[0] ));
LUT5 #(
.INIT(32'h000E0000))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(start2),
.I2(s_axi_wready),
.I3(s_axi_arready),
.I4(s_axi_aresetn),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[28]_i_1
(.I0(GPIO2_DBus_i[3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[3]),
.O(D[3]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[29]_i_1
(.I0(GPIO2_DBus_i[2]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[2]),
.O(D[2]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[30]_i_1
(.I0(GPIO2_DBus_i[1]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[1]),
.O(D[1]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[31]_i_1
(.I0(GPIO2_DBus_i[0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[0]),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_arready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_read),
.I5(ip2bus_rdack_i_D1),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_wready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_write_reg),
.I5(ip2bus_wrack_i_D1),
.O(s_axi_wready));
endmodule |
module design_1_axi_gpio_0_0_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
input [3:0]gpio2_io_i;
output [3:0]gpio2_io_o;
output [3:0]gpio2_io_t;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_21;
wire AXI_LITE_IPIF_I_n_22;
wire [28:31]GPIO2_DBus_i;
wire [3:0]GPIO_DBus;
wire [28:31]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:3]gpio2_Data_In;
wire [3:0]gpio2_io_i;
wire [3:0]gpio2_io_o;
wire [3:0]gpio2_io_t;
wire [0:3]gpio_Data_In;
wire gpio_core_1_n_11;
wire [3:0]gpio_io_i;
wire [3:0]gpio_io_o;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [3:0]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [3:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3:0] = \^s_axi_rdata [3:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
design_1_axi_gpio_0_0_axi_lite_ipif AXI_LITE_IPIF_I
(.D(GPIO_DBus),
.\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_12),
.\Dual.gpio_Data_In_reg[0] ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
.\Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_22),
.\Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_21),
.E(AXI_LITE_IPIF_I_n_11),
.GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
.GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[28] (ip2bus_data_i_D1),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
design_1_axi_gpio_0_0_GPIO_Core gpio_core_1
(.\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
.E(AXI_LITE_IPIF_I_n_22),
.GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
.GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_21),
.bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_12),
.bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_11),
.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(gpio2_io_o),
.gpio2_io_t(gpio2_io_t),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_11),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[3:0]));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[3]),
.Q(ip2bus_data_i_D1[3]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[2]),
.Q(ip2bus_data_i_D1[2]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[1]),
.Q(ip2bus_data_i_D1[1]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[0]),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_11),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule |
module design_1_axi_gpio_0_0_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
bus2ip_cs,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
Read_Reg2_In,
E,
\Dual.gpio2_Data_Out_reg[0] ,
D,
Read_Reg_In,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
gpio2_io_t,
Q,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[28] );
output bus2ip_reset;
output bus2ip_rnw;
output bus2ip_cs;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [0:3]Read_Reg2_In;
output [0:0]E;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [3:0]D;
output [0:3]Read_Reg_In;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output Read_Reg_Rst;
output [3:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [2:0]s_axi_awaddr;
input [2:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [3:0]gpio2_io_t;
input [3:0]Q;
input [3:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [3:0]\ip2bus_data_i_D1_reg[28] ;
wire [3:0]D;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [3:0]\ip2bus_data_i_D1_reg[28] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [3:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
design_1_axi_gpio_0_0_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio2_OE_reg[0] (bus2ip_rnw),
.\Dual.gpio_Data_In_reg[0] (\Dual.gpio_Data_In_reg[0] ),
.\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO2_DBus_i(GPIO2_DBus_i),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.Q(Q),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_rnw_i_reg_0(bus2ip_reset),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[28] (\ip2bus_data_i_D1_reg[28] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module design_1_axi_gpio_0_0_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [3:0]scndry_vect_out;
input [3:0]gpio_io_i;
input s_axi_aclk;
wire [3:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire [3:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
endmodule |
module design_1_axi_gpio_0_0_cdc_sync_0
(scndry_vect_out,
gpio2_io_i,
s_axi_aclk);
output [3:0]scndry_vect_out;
input [3:0]gpio2_io_i;
input s_axi_aclk;
wire [3:0]gpio2_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire [3:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
endmodule |
module design_1_axi_gpio_0_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i,
gpio2_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [3:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) input [3:0]gpio2_io_i;
wire [3:0]gpio2_io_i;
wire [3:0]gpio_io_i;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [3:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [3:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [3:0]NLW_U0_gpio_io_o_UNCONNECTED;
wire [3:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "1" *)
(* C_ALL_INPUTS_2 = "1" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "4" *)
(* C_GPIO_WIDTH = "4" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
design_1_axi_gpio_0_0_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[3:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[3:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[3:0]),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[3:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module design_1_axi_gpio_0_0_slave_attachment
(bus2ip_rnw_i_reg_0,
\Dual.gpio2_OE_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
Read_Reg2_In,
E,
\Dual.gpio2_Data_Out_reg[0] ,
D,
Read_Reg_In,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
gpio2_io_t,
Q,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[28] );
output bus2ip_rnw_i_reg_0;
output \Dual.gpio2_OE_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [0:3]Read_Reg2_In;
output [0:0]E;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [3:0]D;
output [0:3]Read_Reg_In;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output Read_Reg_Rst;
output [3:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [2:0]s_axi_awaddr;
input [2:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [3:0]gpio2_io_t;
input [3:0]Q;
input [3:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [3:0]\ip2bus_data_i_D1_reg[28] ;
wire [3:0]D;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire \Dual.gpio2_OE_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire bus2ip_rnw_i06_out;
wire bus2ip_rnw_i_reg_0;
wire clear;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [3:0]\ip2bus_data_i_D1_reg[28] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [1:0]p_0_out;
wire p_1_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [3:0]s_axi_rdata;
wire s_axi_rdata_i;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
design_1_axi_gpio_0_0_address_decoder I_DECODER
(.D(D),
.\Dual.gpio2_Data_In_reg[0] (Q),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio_Data_In_reg[0] (\Dual.gpio_Data_In_reg[0] ),
.\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO2_DBus_i(GPIO2_DBus_i),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Dual.gpio2_OE_reg[0] ),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.rst_reg(bus2ip_rnw_i_reg_0),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wready(s_axi_wready),
.start2(start2));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_awaddr[0]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[0]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_awaddr[1]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[1]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_awaddr[2]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[2]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(bus2ip_rnw_i_reg_0));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(bus2ip_rnw_i_reg_0));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[8]_i_1_n_0 ),
.Q(bus2ip_addr[0]),
.R(bus2ip_rnw_i_reg_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(bus2ip_rnw_i06_out),
.Q(\Dual.gpio2_OE_reg[0] ),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\state[1]_i_2_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(bus2ip_rnw_i_reg_0));
LUT6 #(
.INIT(64'h1000FFFF10000000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(s_axi_wvalid),
.I3(s_axi_awvalid),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(state[1]),
.I5(state[0]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(bus2ip_rnw_i_reg_0));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_1_in));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(bus2ip_rnw_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(bus2ip_rnw_i_reg_0));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [0]),
.Q(s_axi_rdata[0]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [1]),
.Q(s_axi_rdata[1]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [2]),
.Q(s_axi_rdata[2]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [3]),
.Q(s_axi_rdata[3]),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h0FFFAACC))
\state[0]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arvalid),
.I2(\state[1]_i_2_n_0 ),
.I3(state[1]),
.I4(state[0]),
.O(p_0_out[0]));
LUT6 #(
.INIT(64'h2E2E2E2ECCCCFFCC))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(\state[1]_i_3_n_0 ),
.I4(s_axi_arvalid),
.I5(state[0]),
.O(p_0_out[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_3
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[0]),
.Q(state[0]),
.R(bus2ip_rnw_i_reg_0));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[1]),
.Q(state[1]),
.R(bus2ip_rnw_i_reg_0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_ls__or3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_ms__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_ms__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule |
module sky130_fd_sc_lp__o2bb2ai_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__o2bb2ai_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule |
module sky130_fd_sc_hd__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module jaxa (
output wire autostart_external_connection_export, // autostart_external_connection.export
input wire clk_clk, // clk.clk
output wire [1:0] controlflagsin_external_connection_export, // controlflagsin_external_connection.export
input wire [1:0] controlflagsout_external_connection_export, // controlflagsout_external_connection.export
input wire [5:0] creditcount_external_connection_export, // creditcount_external_connection.export
input wire [7:0] errorstatus_external_connection_export, // errorstatus_external_connection.export
output wire linkdisable_external_connection_export, // linkdisable_external_connection.export
output wire linkstart_external_connection_export, // linkstart_external_connection.export
input wire [15:0] linkstatus_external_connection_export, // linkstatus_external_connection.export
output wire [12:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [7:0] memory_mem_dq, // .mem_dq
inout wire memory_mem_dqs, // .mem_dqs
inout wire memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire [5:0] outstandingcount_external_connection_export, // outstandingcount_external_connection.export
output wire pll_0_outclk0_clk, // pll_0_outclk0.clk
input wire receiveactivity_external_connection_export, // receiveactivity_external_connection.export
output wire receiveclock_external_connection_export, // receiveclock_external_connection.export
input wire receivefifodatacount_external_connection_export, // receivefifodatacount_external_connection.export
input wire [8:0] receivefifodataout_external_connection_export, // receivefifodataout_external_connection.export
input wire receivefifoempty_external_connection_export, // receivefifoempty_external_connection.export
input wire receivefifofull_external_connection_export, // receivefifofull_external_connection.export
output wire receivefiforeadenable_external_connection_export, // receivefiforeadenable_external_connection.export
output wire spacewiredatain_external_connection_export, // spacewiredatain_external_connection.export
input wire spacewiredataout_external_connection_export, // spacewiredataout_external_connection.export
output wire spacewirestrobein_external_connection_export, // spacewirestrobein_external_connection.export
input wire spacewirestrobeout_external_connection_export, // spacewirestrobeout_external_connection.export
input wire [31:0] statisticalinformation_0_external_connection_export, // statisticalinformation_0_external_connection.export
output wire [7:0] statisticalinformation_1_external_connection_export, // statisticalinformation_1_external_connection.export
output wire statisticalinformationclear_external_connection_export, // statisticalinformationclear_external_connection.export
output wire tickin_external_connection_export, // tickin_external_connection.export
input wire tickout_external_connection_export, // tickout_external_connection.export
output wire [5:0] timein_external_connection_export, // timein_external_connection.export
input wire [5:0] timeout_external_connection_export, // timeout_external_connection.export
input wire transmitactivity_external_connection_export, // transmitactivity_external_connection.export
output wire transmitclock_external_connection_export, // transmitclock_external_connection.export
output wire [5:0] transmitclockdividevalue_external_connection_export, // transmitclockdividevalue_external_connection.export
input wire [5:0] transmitfifodatacount_external_connection_export, // transmitfifodatacount_external_connection.export
output wire [8:0] transmitfifodatain_external_connection_export, // transmitfifodatain_external_connection.export
input wire transmitfifofull_external_connection_export, // transmitfifofull_external_connection.export
output wire transmitfifowriteenable_external_connection_export // transmitfifowriteenable_external_connection.export
);
wire hps_0_h2f_reset_reset; // hps_0:h2f_rst_n -> [pll_0:rst, rst_controller:reset_in0, rst_controller_001:reset_in0]
wire [1:0] hps_0_h2f_axi_master_awburst; // hps_0:h2f_AWBURST -> mm_interconnect_0:hps_0_h2f_axi_master_awburst
wire [3:0] hps_0_h2f_axi_master_arlen; // hps_0:h2f_ARLEN -> mm_interconnect_0:hps_0_h2f_axi_master_arlen
wire [3:0] hps_0_h2f_axi_master_wstrb; // hps_0:h2f_WSTRB -> mm_interconnect_0:hps_0_h2f_axi_master_wstrb
wire hps_0_h2f_axi_master_wready; // mm_interconnect_0:hps_0_h2f_axi_master_wready -> hps_0:h2f_WREADY
wire [11:0] hps_0_h2f_axi_master_rid; // mm_interconnect_0:hps_0_h2f_axi_master_rid -> hps_0:h2f_RID
wire hps_0_h2f_axi_master_rready; // hps_0:h2f_RREADY -> mm_interconnect_0:hps_0_h2f_axi_master_rready
wire [3:0] hps_0_h2f_axi_master_awlen; // hps_0:h2f_AWLEN -> mm_interconnect_0:hps_0_h2f_axi_master_awlen
wire [11:0] hps_0_h2f_axi_master_wid; // hps_0:h2f_WID -> mm_interconnect_0:hps_0_h2f_axi_master_wid
wire [3:0] hps_0_h2f_axi_master_arcache; // hps_0:h2f_ARCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_arcache
wire hps_0_h2f_axi_master_wvalid; // hps_0:h2f_WVALID -> mm_interconnect_0:hps_0_h2f_axi_master_wvalid
wire [29:0] hps_0_h2f_axi_master_araddr; // hps_0:h2f_ARADDR -> mm_interconnect_0:hps_0_h2f_axi_master_araddr
wire [2:0] hps_0_h2f_axi_master_arprot; // hps_0:h2f_ARPROT -> mm_interconnect_0:hps_0_h2f_axi_master_arprot
wire [2:0] hps_0_h2f_axi_master_awprot; // hps_0:h2f_AWPROT -> mm_interconnect_0:hps_0_h2f_axi_master_awprot
wire [31:0] hps_0_h2f_axi_master_wdata; // hps_0:h2f_WDATA -> mm_interconnect_0:hps_0_h2f_axi_master_wdata
wire hps_0_h2f_axi_master_arvalid; // hps_0:h2f_ARVALID -> mm_interconnect_0:hps_0_h2f_axi_master_arvalid
wire [3:0] hps_0_h2f_axi_master_awcache; // hps_0:h2f_AWCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_awcache
wire [11:0] hps_0_h2f_axi_master_arid; // hps_0:h2f_ARID -> mm_interconnect_0:hps_0_h2f_axi_master_arid
wire [1:0] hps_0_h2f_axi_master_arlock; // hps_0:h2f_ARLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_arlock
wire [1:0] hps_0_h2f_axi_master_awlock; // hps_0:h2f_AWLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_awlock
wire [29:0] hps_0_h2f_axi_master_awaddr; // hps_0:h2f_AWADDR -> mm_interconnect_0:hps_0_h2f_axi_master_awaddr
wire [1:0] hps_0_h2f_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_axi_master_bresp -> hps_0:h2f_BRESP
wire hps_0_h2f_axi_master_arready; // mm_interconnect_0:hps_0_h2f_axi_master_arready -> hps_0:h2f_ARREADY
wire [31:0] hps_0_h2f_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_axi_master_rdata -> hps_0:h2f_RDATA
wire hps_0_h2f_axi_master_awready; // mm_interconnect_0:hps_0_h2f_axi_master_awready -> hps_0:h2f_AWREADY
wire [1:0] hps_0_h2f_axi_master_arburst; // hps_0:h2f_ARBURST -> mm_interconnect_0:hps_0_h2f_axi_master_arburst
wire [2:0] hps_0_h2f_axi_master_arsize; // hps_0:h2f_ARSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_arsize
wire hps_0_h2f_axi_master_bready; // hps_0:h2f_BREADY -> mm_interconnect_0:hps_0_h2f_axi_master_bready
wire hps_0_h2f_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_axi_master_rlast -> hps_0:h2f_RLAST
wire hps_0_h2f_axi_master_wlast; // hps_0:h2f_WLAST -> mm_interconnect_0:hps_0_h2f_axi_master_wlast
wire [1:0] hps_0_h2f_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_axi_master_rresp -> hps_0:h2f_RRESP
wire [11:0] hps_0_h2f_axi_master_awid; // hps_0:h2f_AWID -> mm_interconnect_0:hps_0_h2f_axi_master_awid
wire [11:0] hps_0_h2f_axi_master_bid; // mm_interconnect_0:hps_0_h2f_axi_master_bid -> hps_0:h2f_BID
wire hps_0_h2f_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_axi_master_bvalid -> hps_0:h2f_BVALID
wire [2:0] hps_0_h2f_axi_master_awsize; // hps_0:h2f_AWSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_awsize
wire hps_0_h2f_axi_master_awvalid; // hps_0:h2f_AWVALID -> mm_interconnect_0:hps_0_h2f_axi_master_awvalid
wire hps_0_h2f_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_axi_master_rvalid -> hps_0:h2f_RVALID
wire mm_interconnect_0_autostart_s1_chipselect; // mm_interconnect_0:autoStart_s1_chipselect -> autoStart:chipselect
wire [31:0] mm_interconnect_0_autostart_s1_readdata; // autoStart:readdata -> mm_interconnect_0:autoStart_s1_readdata
wire [1:0] mm_interconnect_0_autostart_s1_address; // mm_interconnect_0:autoStart_s1_address -> autoStart:address
wire mm_interconnect_0_autostart_s1_write; // mm_interconnect_0:autoStart_s1_write -> autoStart:write_n
wire [31:0] mm_interconnect_0_autostart_s1_writedata; // mm_interconnect_0:autoStart_s1_writedata -> autoStart:writedata
wire mm_interconnect_0_linkdisable_s1_chipselect; // mm_interconnect_0:linkDisable_s1_chipselect -> linkDisable:chipselect
wire [31:0] mm_interconnect_0_linkdisable_s1_readdata; // linkDisable:readdata -> mm_interconnect_0:linkDisable_s1_readdata
wire [1:0] mm_interconnect_0_linkdisable_s1_address; // mm_interconnect_0:linkDisable_s1_address -> linkDisable:address
wire mm_interconnect_0_linkdisable_s1_write; // mm_interconnect_0:linkDisable_s1_write -> linkDisable:write_n
wire [31:0] mm_interconnect_0_linkdisable_s1_writedata; // mm_interconnect_0:linkDisable_s1_writedata -> linkDisable:writedata
wire mm_interconnect_0_linkstart_s1_chipselect; // mm_interconnect_0:linkStart_s1_chipselect -> linkStart:chipselect
wire [31:0] mm_interconnect_0_linkstart_s1_readdata; // linkStart:readdata -> mm_interconnect_0:linkStart_s1_readdata
wire [1:0] mm_interconnect_0_linkstart_s1_address; // mm_interconnect_0:linkStart_s1_address -> linkStart:address
wire mm_interconnect_0_linkstart_s1_write; // mm_interconnect_0:linkStart_s1_write -> linkStart:write_n
wire [31:0] mm_interconnect_0_linkstart_s1_writedata; // mm_interconnect_0:linkStart_s1_writedata -> linkStart:writedata
wire [31:0] mm_interconnect_0_receivefifodatacount_s1_readdata; // receiveFIFODataCount:readdata -> mm_interconnect_0:receiveFIFODataCount_s1_readdata
wire [1:0] mm_interconnect_0_receivefifodatacount_s1_address; // mm_interconnect_0:receiveFIFODataCount_s1_address -> receiveFIFODataCount:address
wire [31:0] mm_interconnect_0_receivefifodataout_s1_readdata; // receiveFIFODataOut:readdata -> mm_interconnect_0:receiveFIFODataOut_s1_readdata
wire [1:0] mm_interconnect_0_receivefifodataout_s1_address; // mm_interconnect_0:receiveFIFODataOut_s1_address -> receiveFIFODataOut:address
wire [31:0] mm_interconnect_0_receivefifoempty_s1_readdata; // receiveFIFOEmpty:readdata -> mm_interconnect_0:receiveFIFOEmpty_s1_readdata
wire [1:0] mm_interconnect_0_receivefifoempty_s1_address; // mm_interconnect_0:receiveFIFOEmpty_s1_address -> receiveFIFOEmpty:address
wire [31:0] mm_interconnect_0_receivefifofull_s1_readdata; // receiveFIFOFull:readdata -> mm_interconnect_0:receiveFIFOFull_s1_readdata
wire [1:0] mm_interconnect_0_receivefifofull_s1_address; // mm_interconnect_0:receiveFIFOFull_s1_address -> receiveFIFOFull:address
wire mm_interconnect_0_receivefiforeadenable_s1_chipselect; // mm_interconnect_0:receiveFIFOReadEnable_s1_chipselect -> receiveFIFOReadEnable:chipselect
wire [31:0] mm_interconnect_0_receivefiforeadenable_s1_readdata; // receiveFIFOReadEnable:readdata -> mm_interconnect_0:receiveFIFOReadEnable_s1_readdata
wire [1:0] mm_interconnect_0_receivefiforeadenable_s1_address; // mm_interconnect_0:receiveFIFOReadEnable_s1_address -> receiveFIFOReadEnable:address
wire mm_interconnect_0_receivefiforeadenable_s1_write; // mm_interconnect_0:receiveFIFOReadEnable_s1_write -> receiveFIFOReadEnable:write_n
wire [31:0] mm_interconnect_0_receivefiforeadenable_s1_writedata; // mm_interconnect_0:receiveFIFOReadEnable_s1_writedata -> receiveFIFOReadEnable:writedata
wire [31:0] mm_interconnect_0_transmitfifofull_s1_readdata; // transmitFIFOFull:readdata -> mm_interconnect_0:transmitFIFOFull_s1_readdata
wire [1:0] mm_interconnect_0_transmitfifofull_s1_address; // mm_interconnect_0:transmitFIFOFull_s1_address -> transmitFIFOFull:address
wire mm_interconnect_0_transmitfifowriteenable_s1_chipselect; // mm_interconnect_0:transmitFIFOWriteEnable_s1_chipselect -> transmitFIFOWriteEnable:chipselect
wire [31:0] mm_interconnect_0_transmitfifowriteenable_s1_readdata; // transmitFIFOWriteEnable:readdata -> mm_interconnect_0:transmitFIFOWriteEnable_s1_readdata
wire [1:0] mm_interconnect_0_transmitfifowriteenable_s1_address; // mm_interconnect_0:transmitFIFOWriteEnable_s1_address -> transmitFIFOWriteEnable:address
wire mm_interconnect_0_transmitfifowriteenable_s1_write; // mm_interconnect_0:transmitFIFOWriteEnable_s1_write -> transmitFIFOWriteEnable:write_n
wire [31:0] mm_interconnect_0_transmitfifowriteenable_s1_writedata; // mm_interconnect_0:transmitFIFOWriteEnable_s1_writedata -> transmitFIFOWriteEnable:writedata
wire mm_interconnect_0_transmitfifodatain_s1_chipselect; // mm_interconnect_0:transmitFIFODataIn_s1_chipselect -> transmitFIFODataIn:chipselect
wire [31:0] mm_interconnect_0_transmitfifodatain_s1_readdata; // transmitFIFODataIn:readdata -> mm_interconnect_0:transmitFIFODataIn_s1_readdata
wire [1:0] mm_interconnect_0_transmitfifodatain_s1_address; // mm_interconnect_0:transmitFIFODataIn_s1_address -> transmitFIFODataIn:address
wire mm_interconnect_0_transmitfifodatain_s1_write; // mm_interconnect_0:transmitFIFODataIn_s1_write -> transmitFIFODataIn:write_n
wire [31:0] mm_interconnect_0_transmitfifodatain_s1_writedata; // mm_interconnect_0:transmitFIFODataIn_s1_writedata -> transmitFIFODataIn:writedata
wire [31:0] mm_interconnect_0_transmitfifodatacount_s1_readdata; // transmitFIFODataCount:readdata -> mm_interconnect_0:transmitFIFODataCount_s1_readdata
wire [1:0] mm_interconnect_0_transmitfifodatacount_s1_address; // mm_interconnect_0:transmitFIFODataCount_s1_address -> transmitFIFODataCount:address
wire mm_interconnect_0_tickin_s1_chipselect; // mm_interconnect_0:tickIn_s1_chipselect -> tickIn:chipselect
wire [31:0] mm_interconnect_0_tickin_s1_readdata; // tickIn:readdata -> mm_interconnect_0:tickIn_s1_readdata
wire [1:0] mm_interconnect_0_tickin_s1_address; // mm_interconnect_0:tickIn_s1_address -> tickIn:address
wire mm_interconnect_0_tickin_s1_write; // mm_interconnect_0:tickIn_s1_write -> tickIn:write_n
wire [31:0] mm_interconnect_0_tickin_s1_writedata; // mm_interconnect_0:tickIn_s1_writedata -> tickIn:writedata
wire mm_interconnect_0_timein_s1_chipselect; // mm_interconnect_0:timeIn_s1_chipselect -> timeIn:chipselect
wire [31:0] mm_interconnect_0_timein_s1_readdata; // timeIn:readdata -> mm_interconnect_0:timeIn_s1_readdata
wire [1:0] mm_interconnect_0_timein_s1_address; // mm_interconnect_0:timeIn_s1_address -> timeIn:address
wire mm_interconnect_0_timein_s1_write; // mm_interconnect_0:timeIn_s1_write -> timeIn:write_n
wire [31:0] mm_interconnect_0_timein_s1_writedata; // mm_interconnect_0:timeIn_s1_writedata -> timeIn:writedata
wire [31:0] mm_interconnect_0_tickout_s1_readdata; // tickOut:readdata -> mm_interconnect_0:tickOut_s1_readdata
wire [1:0] mm_interconnect_0_tickout_s1_address; // mm_interconnect_0:tickOut_s1_address -> tickOut:address
wire [31:0] mm_interconnect_0_timeout_s1_readdata; // timeOut:readdata -> mm_interconnect_0:timeOut_s1_readdata
wire [1:0] mm_interconnect_0_timeout_s1_address; // mm_interconnect_0:timeOut_s1_address -> timeOut:address
wire [31:0] mm_interconnect_0_statisticalinformation_0_s1_readdata; // statisticalInformation_0:readdata -> mm_interconnect_0:statisticalInformation_0_s1_readdata
wire [1:0] mm_interconnect_0_statisticalinformation_0_s1_address; // mm_interconnect_0:statisticalInformation_0_s1_address -> statisticalInformation_0:address
wire mm_interconnect_0_statisticalinformation_1_s1_chipselect; // mm_interconnect_0:statisticalInformation_1_s1_chipselect -> statisticalInformation_1:chipselect
wire [31:0] mm_interconnect_0_statisticalinformation_1_s1_readdata; // statisticalInformation_1:readdata -> mm_interconnect_0:statisticalInformation_1_s1_readdata
wire [1:0] mm_interconnect_0_statisticalinformation_1_s1_address; // mm_interconnect_0:statisticalInformation_1_s1_address -> statisticalInformation_1:address
wire mm_interconnect_0_statisticalinformation_1_s1_write; // mm_interconnect_0:statisticalInformation_1_s1_write -> statisticalInformation_1:write_n
wire [31:0] mm_interconnect_0_statisticalinformation_1_s1_writedata; // mm_interconnect_0:statisticalInformation_1_s1_writedata -> statisticalInformation_1:writedata
wire mm_interconnect_0_statisticalinformationclear_s1_chipselect; // mm_interconnect_0:statisticalInformationClear_s1_chipselect -> statisticalInformationClear:chipselect
wire [31:0] mm_interconnect_0_statisticalinformationclear_s1_readdata; // statisticalInformationClear:readdata -> mm_interconnect_0:statisticalInformationClear_s1_readdata
wire [1:0] mm_interconnect_0_statisticalinformationclear_s1_address; // mm_interconnect_0:statisticalInformationClear_s1_address -> statisticalInformationClear:address
wire mm_interconnect_0_statisticalinformationclear_s1_write; // mm_interconnect_0:statisticalInformationClear_s1_write -> statisticalInformationClear:write_n
wire [31:0] mm_interconnect_0_statisticalinformationclear_s1_writedata; // mm_interconnect_0:statisticalInformationClear_s1_writedata -> statisticalInformationClear:writedata
wire [31:0] mm_interconnect_0_linkstatus_s1_readdata; // linkStatus:readdata -> mm_interconnect_0:linkStatus_s1_readdata
wire [1:0] mm_interconnect_0_linkstatus_s1_address; // mm_interconnect_0:linkStatus_s1_address -> linkStatus:address
wire [31:0] mm_interconnect_0_errorstatus_s1_readdata; // errorStatus:readdata -> mm_interconnect_0:errorStatus_s1_readdata
wire [1:0] mm_interconnect_0_errorstatus_s1_address; // mm_interconnect_0:errorStatus_s1_address -> errorStatus:address
wire mm_interconnect_0_transmitclockdividevalue_s1_chipselect; // mm_interconnect_0:transmitClockDivideValue_s1_chipselect -> transmitClockDivideValue:chipselect
wire [31:0] mm_interconnect_0_transmitclockdividevalue_s1_readdata; // transmitClockDivideValue:readdata -> mm_interconnect_0:transmitClockDivideValue_s1_readdata
wire [1:0] mm_interconnect_0_transmitclockdividevalue_s1_address; // mm_interconnect_0:transmitClockDivideValue_s1_address -> transmitClockDivideValue:address
wire mm_interconnect_0_transmitclockdividevalue_s1_write; // mm_interconnect_0:transmitClockDivideValue_s1_write -> transmitClockDivideValue:write_n
wire [31:0] mm_interconnect_0_transmitclockdividevalue_s1_writedata; // mm_interconnect_0:transmitClockDivideValue_s1_writedata -> transmitClockDivideValue:writedata
wire mm_interconnect_0_transmitclock_s1_chipselect; // mm_interconnect_0:transmitClock_s1_chipselect -> transmitClock:chipselect
wire [31:0] mm_interconnect_0_transmitclock_s1_readdata; // transmitClock:readdata -> mm_interconnect_0:transmitClock_s1_readdata
wire [1:0] mm_interconnect_0_transmitclock_s1_address; // mm_interconnect_0:transmitClock_s1_address -> transmitClock:address
wire mm_interconnect_0_transmitclock_s1_write; // mm_interconnect_0:transmitClock_s1_write -> transmitClock:write_n
wire [31:0] mm_interconnect_0_transmitclock_s1_writedata; // mm_interconnect_0:transmitClock_s1_writedata -> transmitClock:writedata
wire [31:0] mm_interconnect_0_transmitactivity_s1_readdata; // transmitActivity:readdata -> mm_interconnect_0:transmitActivity_s1_readdata
wire [1:0] mm_interconnect_0_transmitactivity_s1_address; // mm_interconnect_0:transmitActivity_s1_address -> transmitActivity:address
wire mm_interconnect_0_spacewirestrobein_s1_chipselect; // mm_interconnect_0:spaceWireStrobeIn_s1_chipselect -> spaceWireStrobeIn:chipselect
wire [31:0] mm_interconnect_0_spacewirestrobein_s1_readdata; // spaceWireStrobeIn:readdata -> mm_interconnect_0:spaceWireStrobeIn_s1_readdata
wire [1:0] mm_interconnect_0_spacewirestrobein_s1_address; // mm_interconnect_0:spaceWireStrobeIn_s1_address -> spaceWireStrobeIn:address
wire mm_interconnect_0_spacewirestrobein_s1_write; // mm_interconnect_0:spaceWireStrobeIn_s1_write -> spaceWireStrobeIn:write_n
wire [31:0] mm_interconnect_0_spacewirestrobein_s1_writedata; // mm_interconnect_0:spaceWireStrobeIn_s1_writedata -> spaceWireStrobeIn:writedata
wire [31:0] mm_interconnect_0_spacewirestrobeout_s1_readdata; // spaceWireStrobeOut:readdata -> mm_interconnect_0:spaceWireStrobeOut_s1_readdata
wire [1:0] mm_interconnect_0_spacewirestrobeout_s1_address; // mm_interconnect_0:spaceWireStrobeOut_s1_address -> spaceWireStrobeOut:address
wire [31:0] mm_interconnect_0_spacewiredataout_s1_readdata; // spaceWireDataOut:readdata -> mm_interconnect_0:spaceWireDataOut_s1_readdata
wire [1:0] mm_interconnect_0_spacewiredataout_s1_address; // mm_interconnect_0:spaceWireDataOut_s1_address -> spaceWireDataOut:address
wire mm_interconnect_0_spacewiredatain_s1_chipselect; // mm_interconnect_0:spaceWireDataIn_s1_chipselect -> spaceWireDataIn:chipselect
wire [31:0] mm_interconnect_0_spacewiredatain_s1_readdata; // spaceWireDataIn:readdata -> mm_interconnect_0:spaceWireDataIn_s1_readdata
wire [1:0] mm_interconnect_0_spacewiredatain_s1_address; // mm_interconnect_0:spaceWireDataIn_s1_address -> spaceWireDataIn:address
wire mm_interconnect_0_spacewiredatain_s1_write; // mm_interconnect_0:spaceWireDataIn_s1_write -> spaceWireDataIn:write_n
wire [31:0] mm_interconnect_0_spacewiredatain_s1_writedata; // mm_interconnect_0:spaceWireDataIn_s1_writedata -> spaceWireDataIn:writedata
wire mm_interconnect_0_controlflagsin_s1_chipselect; // mm_interconnect_0:controlFlagsIn_s1_chipselect -> controlFlagsIn:chipselect
wire [31:0] mm_interconnect_0_controlflagsin_s1_readdata; // controlFlagsIn:readdata -> mm_interconnect_0:controlFlagsIn_s1_readdata
wire [1:0] mm_interconnect_0_controlflagsin_s1_address; // mm_interconnect_0:controlFlagsIn_s1_address -> controlFlagsIn:address
wire mm_interconnect_0_controlflagsin_s1_write; // mm_interconnect_0:controlFlagsIn_s1_write -> controlFlagsIn:write_n
wire [31:0] mm_interconnect_0_controlflagsin_s1_writedata; // mm_interconnect_0:controlFlagsIn_s1_writedata -> controlFlagsIn:writedata
wire [31:0] mm_interconnect_0_controlflagsout_s1_readdata; // controlFlagsOut:readdata -> mm_interconnect_0:controlFlagsOut_s1_readdata
wire [1:0] mm_interconnect_0_controlflagsout_s1_address; // mm_interconnect_0:controlFlagsOut_s1_address -> controlFlagsOut:address
wire [31:0] mm_interconnect_0_creditcount_s1_readdata; // creditCount:readdata -> mm_interconnect_0:creditCount_s1_readdata
wire [1:0] mm_interconnect_0_creditcount_s1_address; // mm_interconnect_0:creditCount_s1_address -> creditCount:address
wire [31:0] mm_interconnect_0_outstandingcount_s1_readdata; // outstandingCount:readdata -> mm_interconnect_0:outstandingCount_s1_readdata
wire [1:0] mm_interconnect_0_outstandingcount_s1_address; // mm_interconnect_0:outstandingCount_s1_address -> outstandingCount:address
wire [31:0] mm_interconnect_0_receiveactivity_s1_readdata; // receiveActivity:readdata -> mm_interconnect_0:receiveActivity_s1_readdata
wire [1:0] mm_interconnect_0_receiveactivity_s1_address; // mm_interconnect_0:receiveActivity_s1_address -> receiveActivity:address
wire mm_interconnect_0_receiveclock_s1_chipselect; // mm_interconnect_0:receiveClock_s1_chipselect -> receiveClock:chipselect
wire [31:0] mm_interconnect_0_receiveclock_s1_readdata; // receiveClock:readdata -> mm_interconnect_0:receiveClock_s1_readdata
wire [1:0] mm_interconnect_0_receiveclock_s1_address; // mm_interconnect_0:receiveClock_s1_address -> receiveClock:address
wire mm_interconnect_0_receiveclock_s1_write; // mm_interconnect_0:receiveClock_s1_write -> receiveClock:write_n
wire [31:0] mm_interconnect_0_receiveclock_s1_writedata; // mm_interconnect_0:receiveClock_s1_writedata -> receiveClock:writedata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [autoStart:reset_n, controlFlagsIn:reset_n, controlFlagsOut:reset_n, creditCount:reset_n, errorStatus:reset_n, linkDisable:reset_n, linkStart:reset_n, linkStatus:reset_n, mm_interconnect_0:autoStart_reset_reset_bridge_in_reset_reset, outstandingCount:reset_n, receiveActivity:reset_n, receiveClock:reset_n, receiveFIFODataCount:reset_n, receiveFIFODataOut:reset_n, receiveFIFOEmpty:reset_n, receiveFIFOFull:reset_n, receiveFIFOReadEnable:reset_n, spaceWireDataIn:reset_n, spaceWireDataOut:reset_n, spaceWireStrobeIn:reset_n, spaceWireStrobeOut:reset_n, statisticalInformationClear:reset_n, statisticalInformation_0:reset_n, statisticalInformation_1:reset_n, tickIn:reset_n, tickOut:reset_n, timeIn:reset_n, timeOut:reset_n, transmitActivity:reset_n, transmitClock:reset_n, transmitClockDivideValue:reset_n, transmitFIFODataCount:reset_n, transmitFIFODataIn:reset_n, transmitFIFOFull:reset_n, transmitFIFOWriteEnable:reset_n]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
jaxa_autoStart autostart (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_autostart_s1_address), // s1.address
.write_n (~mm_interconnect_0_autostart_s1_write), // .write_n
.writedata (mm_interconnect_0_autostart_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_autostart_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_autostart_s1_readdata), // .readdata
.out_port (autostart_external_connection_export) // external_connection.export
);
jaxa_controlFlagsIn controlflagsin (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_controlflagsin_s1_address), // s1.address
.write_n (~mm_interconnect_0_controlflagsin_s1_write), // .write_n
.writedata (mm_interconnect_0_controlflagsin_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_controlflagsin_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_controlflagsin_s1_readdata), // .readdata
.out_port (controlflagsin_external_connection_export) // external_connection.export
);
jaxa_controlFlagsOut controlflagsout (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_controlflagsout_s1_address), // s1.address
.readdata (mm_interconnect_0_controlflagsout_s1_readdata), // .readdata
.in_port (controlflagsout_external_connection_export) // external_connection.export
);
jaxa_creditCount creditcount (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_creditcount_s1_address), // s1.address
.readdata (mm_interconnect_0_creditcount_s1_readdata), // .readdata
.in_port (creditcount_external_connection_export) // external_connection.export
);
jaxa_errorStatus errorstatus (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_errorstatus_s1_address), // s1.address
.readdata (mm_interconnect_0_errorstatus_s1_readdata), // .readdata
.in_port (errorstatus_external_connection_export) // external_connection.export
);
jaxa_hps_0 #(
.F2S_Width (0),
.S2F_Width (1)
) hps_0 (
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.h2f_rst_n (hps_0_h2f_reset_reset), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (hps_0_h2f_axi_master_awid), // h2f_axi_master.awid
.h2f_AWADDR (hps_0_h2f_axi_master_awaddr), // .awaddr
.h2f_AWLEN (hps_0_h2f_axi_master_awlen), // .awlen
.h2f_AWSIZE (hps_0_h2f_axi_master_awsize), // .awsize
.h2f_AWBURST (hps_0_h2f_axi_master_awburst), // .awburst
.h2f_AWLOCK (hps_0_h2f_axi_master_awlock), // .awlock
.h2f_AWCACHE (hps_0_h2f_axi_master_awcache), // .awcache
.h2f_AWPROT (hps_0_h2f_axi_master_awprot), // .awprot
.h2f_AWVALID (hps_0_h2f_axi_master_awvalid), // .awvalid
.h2f_AWREADY (hps_0_h2f_axi_master_awready), // .awready
.h2f_WID (hps_0_h2f_axi_master_wid), // .wid
.h2f_WDATA (hps_0_h2f_axi_master_wdata), // .wdata
.h2f_WSTRB (hps_0_h2f_axi_master_wstrb), // .wstrb
.h2f_WLAST (hps_0_h2f_axi_master_wlast), // .wlast
.h2f_WVALID (hps_0_h2f_axi_master_wvalid), // .wvalid
.h2f_WREADY (hps_0_h2f_axi_master_wready), // .wready
.h2f_BID (hps_0_h2f_axi_master_bid), // .bid
.h2f_BRESP (hps_0_h2f_axi_master_bresp), // .bresp
.h2f_BVALID (hps_0_h2f_axi_master_bvalid), // .bvalid
.h2f_BREADY (hps_0_h2f_axi_master_bready), // .bready
.h2f_ARID (hps_0_h2f_axi_master_arid), // .arid
.h2f_ARADDR (hps_0_h2f_axi_master_araddr), // .araddr
.h2f_ARLEN (hps_0_h2f_axi_master_arlen), // .arlen
.h2f_ARSIZE (hps_0_h2f_axi_master_arsize), // .arsize
.h2f_ARBURST (hps_0_h2f_axi_master_arburst), // .arburst
.h2f_ARLOCK (hps_0_h2f_axi_master_arlock), // .arlock
.h2f_ARCACHE (hps_0_h2f_axi_master_arcache), // .arcache
.h2f_ARPROT (hps_0_h2f_axi_master_arprot), // .arprot
.h2f_ARVALID (hps_0_h2f_axi_master_arvalid), // .arvalid
.h2f_ARREADY (hps_0_h2f_axi_master_arready), // .arready
.h2f_RID (hps_0_h2f_axi_master_rid), // .rid
.h2f_RDATA (hps_0_h2f_axi_master_rdata), // .rdata
.h2f_RRESP (hps_0_h2f_axi_master_rresp), // .rresp
.h2f_RLAST (hps_0_h2f_axi_master_rlast), // .rlast
.h2f_RVALID (hps_0_h2f_axi_master_rvalid), // .rvalid
.h2f_RREADY (hps_0_h2f_axi_master_rready) // .rready
);
jaxa_autoStart linkdisable (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_linkdisable_s1_address), // s1.address
.write_n (~mm_interconnect_0_linkdisable_s1_write), // .write_n
.writedata (mm_interconnect_0_linkdisable_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_linkdisable_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_linkdisable_s1_readdata), // .readdata
.out_port (linkdisable_external_connection_export) // external_connection.export
);
jaxa_autoStart linkstart (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_linkstart_s1_address), // s1.address
.write_n (~mm_interconnect_0_linkstart_s1_write), // .write_n
.writedata (mm_interconnect_0_linkstart_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_linkstart_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_linkstart_s1_readdata), // .readdata
.out_port (linkstart_external_connection_export) // external_connection.export
);
jaxa_linkStatus linkstatus (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_linkstatus_s1_address), // s1.address
.readdata (mm_interconnect_0_linkstatus_s1_readdata), // .readdata
.in_port (linkstatus_external_connection_export) // external_connection.export
);
jaxa_creditCount outstandingcount (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_outstandingcount_s1_address), // s1.address
.readdata (mm_interconnect_0_outstandingcount_s1_readdata), // .readdata
.in_port (outstandingcount_external_connection_export) // external_connection.export
);
jaxa_pll_0 pll_0 (
.refclk (clk_clk), // refclk.clk
.rst (~hps_0_h2f_reset_reset), // reset.reset
.outclk_0 (pll_0_outclk0_clk), // outclk0.clk
.locked () // locked.export
);
jaxa_receiveActivity receiveactivity (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_receiveactivity_s1_address), // s1.address
.readdata (mm_interconnect_0_receiveactivity_s1_readdata), // .readdata
.in_port (receiveactivity_external_connection_export) // external_connection.export
);
jaxa_autoStart receiveclock (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_receiveclock_s1_address), // s1.address
.write_n (~mm_interconnect_0_receiveclock_s1_write), // .write_n
.writedata (mm_interconnect_0_receiveclock_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_receiveclock_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_receiveclock_s1_readdata), // .readdata
.out_port (receiveclock_external_connection_export) // external_connection.export
);
jaxa_receiveActivity receivefifodatacount (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_receivefifodatacount_s1_address), // s1.address
.readdata (mm_interconnect_0_receivefifodatacount_s1_readdata), // .readdata
.in_port (receivefifodatacount_external_connection_export) // external_connection.export
);
jaxa_receiveFIFODataOut receivefifodataout (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_receivefifodataout_s1_address), // s1.address
.readdata (mm_interconnect_0_receivefifodataout_s1_readdata), // .readdata
.in_port (receivefifodataout_external_connection_export) // external_connection.export
);
jaxa_receiveActivity receivefifoempty (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_receivefifoempty_s1_address), // s1.address
.readdata (mm_interconnect_0_receivefifoempty_s1_readdata), // .readdata
.in_port (receivefifoempty_external_connection_export) // external_connection.export
);
jaxa_receiveActivity receivefifofull (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_receivefifofull_s1_address), // s1.address
.readdata (mm_interconnect_0_receivefifofull_s1_readdata), // .readdata
.in_port (receivefifofull_external_connection_export) // external_connection.export
);
jaxa_autoStart receivefiforeadenable (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_receivefiforeadenable_s1_address), // s1.address
.write_n (~mm_interconnect_0_receivefiforeadenable_s1_write), // .write_n
.writedata (mm_interconnect_0_receivefiforeadenable_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_receivefiforeadenable_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_receivefiforeadenable_s1_readdata), // .readdata
.out_port (receivefiforeadenable_external_connection_export) // external_connection.export
);
jaxa_autoStart spacewiredatain (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_spacewiredatain_s1_address), // s1.address
.write_n (~mm_interconnect_0_spacewiredatain_s1_write), // .write_n
.writedata (mm_interconnect_0_spacewiredatain_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_spacewiredatain_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_spacewiredatain_s1_readdata), // .readdata
.out_port (spacewiredatain_external_connection_export) // external_connection.export
);
jaxa_receiveActivity spacewiredataout (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_spacewiredataout_s1_address), // s1.address
.readdata (mm_interconnect_0_spacewiredataout_s1_readdata), // .readdata
.in_port (spacewiredataout_external_connection_export) // external_connection.export
);
jaxa_autoStart spacewirestrobein (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_spacewirestrobein_s1_address), // s1.address
.write_n (~mm_interconnect_0_spacewirestrobein_s1_write), // .write_n
.writedata (mm_interconnect_0_spacewirestrobein_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_spacewirestrobein_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_spacewirestrobein_s1_readdata), // .readdata
.out_port (spacewirestrobein_external_connection_export) // external_connection.export
);
jaxa_receiveActivity spacewirestrobeout (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_spacewirestrobeout_s1_address), // s1.address
.readdata (mm_interconnect_0_spacewirestrobeout_s1_readdata), // .readdata
.in_port (spacewirestrobeout_external_connection_export) // external_connection.export
);
jaxa_autoStart statisticalinformationclear (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_statisticalinformationclear_s1_address), // s1.address
.write_n (~mm_interconnect_0_statisticalinformationclear_s1_write), // .write_n
.writedata (mm_interconnect_0_statisticalinformationclear_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_statisticalinformationclear_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_statisticalinformationclear_s1_readdata), // .readdata
.out_port (statisticalinformationclear_external_connection_export) // external_connection.export
);
jaxa_statisticalInformation_0 statisticalinformation_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_statisticalinformation_0_s1_address), // s1.address
.readdata (mm_interconnect_0_statisticalinformation_0_s1_readdata), // .readdata
.in_port (statisticalinformation_0_external_connection_export) // external_connection.export
);
jaxa_statisticalInformation_1 statisticalinformation_1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_statisticalinformation_1_s1_address), // s1.address
.write_n (~mm_interconnect_0_statisticalinformation_1_s1_write), // .write_n
.writedata (mm_interconnect_0_statisticalinformation_1_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_statisticalinformation_1_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_statisticalinformation_1_s1_readdata), // .readdata
.out_port (statisticalinformation_1_external_connection_export) // external_connection.export
);
jaxa_autoStart tickin (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_tickin_s1_address), // s1.address
.write_n (~mm_interconnect_0_tickin_s1_write), // .write_n
.writedata (mm_interconnect_0_tickin_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_tickin_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_tickin_s1_readdata), // .readdata
.out_port (tickin_external_connection_export) // external_connection.export
);
jaxa_receiveActivity tickout (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_tickout_s1_address), // s1.address
.readdata (mm_interconnect_0_tickout_s1_readdata), // .readdata
.in_port (tickout_external_connection_export) // external_connection.export
);
jaxa_timeIn timein (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_timein_s1_address), // s1.address
.write_n (~mm_interconnect_0_timein_s1_write), // .write_n
.writedata (mm_interconnect_0_timein_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_timein_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_timein_s1_readdata), // .readdata
.out_port (timein_external_connection_export) // external_connection.export
);
jaxa_creditCount timeout (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_timeout_s1_address), // s1.address
.readdata (mm_interconnect_0_timeout_s1_readdata), // .readdata
.in_port (timeout_external_connection_export) // external_connection.export
);
jaxa_receiveActivity transmitactivity (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_transmitactivity_s1_address), // s1.address
.readdata (mm_interconnect_0_transmitactivity_s1_readdata), // .readdata
.in_port (transmitactivity_external_connection_export) // external_connection.export
);
jaxa_autoStart transmitclock (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_transmitclock_s1_address), // s1.address
.write_n (~mm_interconnect_0_transmitclock_s1_write), // .write_n
.writedata (mm_interconnect_0_transmitclock_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_transmitclock_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_transmitclock_s1_readdata), // .readdata
.out_port (transmitclock_external_connection_export) // external_connection.export
);
jaxa_timeIn transmitclockdividevalue (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_transmitclockdividevalue_s1_address), // s1.address
.write_n (~mm_interconnect_0_transmitclockdividevalue_s1_write), // .write_n
.writedata (mm_interconnect_0_transmitclockdividevalue_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_transmitclockdividevalue_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_transmitclockdividevalue_s1_readdata), // .readdata
.out_port (transmitclockdividevalue_external_connection_export) // external_connection.export
);
jaxa_creditCount transmitfifodatacount (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_transmitfifodatacount_s1_address), // s1.address
.readdata (mm_interconnect_0_transmitfifodatacount_s1_readdata), // .readdata
.in_port (transmitfifodatacount_external_connection_export) // external_connection.export
);
jaxa_transmitFIFODataIn transmitfifodatain (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_transmitfifodatain_s1_address), // s1.address
.write_n (~mm_interconnect_0_transmitfifodatain_s1_write), // .write_n
.writedata (mm_interconnect_0_transmitfifodatain_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_transmitfifodatain_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_transmitfifodatain_s1_readdata), // .readdata
.out_port (transmitfifodatain_external_connection_export) // external_connection.export
);
jaxa_receiveActivity transmitfifofull (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_transmitfifofull_s1_address), // s1.address
.readdata (mm_interconnect_0_transmitfifofull_s1_readdata), // .readdata
.in_port (transmitfifofull_external_connection_export) // external_connection.export
);
jaxa_autoStart transmitfifowriteenable (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_transmitfifowriteenable_s1_address), // s1.address
.write_n (~mm_interconnect_0_transmitfifowriteenable_s1_write), // .write_n
.writedata (mm_interconnect_0_transmitfifowriteenable_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_transmitfifowriteenable_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_transmitfifowriteenable_s1_readdata), // .readdata
.out_port (transmitfifowriteenable_external_connection_export) // external_connection.export
);
jaxa_mm_interconnect_0 mm_interconnect_0 (
.hps_0_h2f_axi_master_awid (hps_0_h2f_axi_master_awid), // hps_0_h2f_axi_master.awid
.hps_0_h2f_axi_master_awaddr (hps_0_h2f_axi_master_awaddr), // .awaddr
.hps_0_h2f_axi_master_awlen (hps_0_h2f_axi_master_awlen), // .awlen
.hps_0_h2f_axi_master_awsize (hps_0_h2f_axi_master_awsize), // .awsize
.hps_0_h2f_axi_master_awburst (hps_0_h2f_axi_master_awburst), // .awburst
.hps_0_h2f_axi_master_awlock (hps_0_h2f_axi_master_awlock), // .awlock
.hps_0_h2f_axi_master_awcache (hps_0_h2f_axi_master_awcache), // .awcache
.hps_0_h2f_axi_master_awprot (hps_0_h2f_axi_master_awprot), // .awprot
.hps_0_h2f_axi_master_awvalid (hps_0_h2f_axi_master_awvalid), // .awvalid
.hps_0_h2f_axi_master_awready (hps_0_h2f_axi_master_awready), // .awready
.hps_0_h2f_axi_master_wid (hps_0_h2f_axi_master_wid), // .wid
.hps_0_h2f_axi_master_wdata (hps_0_h2f_axi_master_wdata), // .wdata
.hps_0_h2f_axi_master_wstrb (hps_0_h2f_axi_master_wstrb), // .wstrb
.hps_0_h2f_axi_master_wlast (hps_0_h2f_axi_master_wlast), // .wlast
.hps_0_h2f_axi_master_wvalid (hps_0_h2f_axi_master_wvalid), // .wvalid
.hps_0_h2f_axi_master_wready (hps_0_h2f_axi_master_wready), // .wready
.hps_0_h2f_axi_master_bid (hps_0_h2f_axi_master_bid), // .bid
.hps_0_h2f_axi_master_bresp (hps_0_h2f_axi_master_bresp), // .bresp
.hps_0_h2f_axi_master_bvalid (hps_0_h2f_axi_master_bvalid), // .bvalid
.hps_0_h2f_axi_master_bready (hps_0_h2f_axi_master_bready), // .bready
.hps_0_h2f_axi_master_arid (hps_0_h2f_axi_master_arid), // .arid
.hps_0_h2f_axi_master_araddr (hps_0_h2f_axi_master_araddr), // .araddr
.hps_0_h2f_axi_master_arlen (hps_0_h2f_axi_master_arlen), // .arlen
.hps_0_h2f_axi_master_arsize (hps_0_h2f_axi_master_arsize), // .arsize
.hps_0_h2f_axi_master_arburst (hps_0_h2f_axi_master_arburst), // .arburst
.hps_0_h2f_axi_master_arlock (hps_0_h2f_axi_master_arlock), // .arlock
.hps_0_h2f_axi_master_arcache (hps_0_h2f_axi_master_arcache), // .arcache
.hps_0_h2f_axi_master_arprot (hps_0_h2f_axi_master_arprot), // .arprot
.hps_0_h2f_axi_master_arvalid (hps_0_h2f_axi_master_arvalid), // .arvalid
.hps_0_h2f_axi_master_arready (hps_0_h2f_axi_master_arready), // .arready
.hps_0_h2f_axi_master_rid (hps_0_h2f_axi_master_rid), // .rid
.hps_0_h2f_axi_master_rdata (hps_0_h2f_axi_master_rdata), // .rdata
.hps_0_h2f_axi_master_rresp (hps_0_h2f_axi_master_rresp), // .rresp
.hps_0_h2f_axi_master_rlast (hps_0_h2f_axi_master_rlast), // .rlast
.hps_0_h2f_axi_master_rvalid (hps_0_h2f_axi_master_rvalid), // .rvalid
.hps_0_h2f_axi_master_rready (hps_0_h2f_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.autoStart_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // autoStart_reset_reset_bridge_in_reset.reset
.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.autoStart_s1_address (mm_interconnect_0_autostart_s1_address), // autoStart_s1.address
.autoStart_s1_write (mm_interconnect_0_autostart_s1_write), // .write
.autoStart_s1_readdata (mm_interconnect_0_autostart_s1_readdata), // .readdata
.autoStart_s1_writedata (mm_interconnect_0_autostart_s1_writedata), // .writedata
.autoStart_s1_chipselect (mm_interconnect_0_autostart_s1_chipselect), // .chipselect
.controlFlagsIn_s1_address (mm_interconnect_0_controlflagsin_s1_address), // controlFlagsIn_s1.address
.controlFlagsIn_s1_write (mm_interconnect_0_controlflagsin_s1_write), // .write
.controlFlagsIn_s1_readdata (mm_interconnect_0_controlflagsin_s1_readdata), // .readdata
.controlFlagsIn_s1_writedata (mm_interconnect_0_controlflagsin_s1_writedata), // .writedata
.controlFlagsIn_s1_chipselect (mm_interconnect_0_controlflagsin_s1_chipselect), // .chipselect
.controlFlagsOut_s1_address (mm_interconnect_0_controlflagsout_s1_address), // controlFlagsOut_s1.address
.controlFlagsOut_s1_readdata (mm_interconnect_0_controlflagsout_s1_readdata), // .readdata
.creditCount_s1_address (mm_interconnect_0_creditcount_s1_address), // creditCount_s1.address
.creditCount_s1_readdata (mm_interconnect_0_creditcount_s1_readdata), // .readdata
.errorStatus_s1_address (mm_interconnect_0_errorstatus_s1_address), // errorStatus_s1.address
.errorStatus_s1_readdata (mm_interconnect_0_errorstatus_s1_readdata), // .readdata
.linkDisable_s1_address (mm_interconnect_0_linkdisable_s1_address), // linkDisable_s1.address
.linkDisable_s1_write (mm_interconnect_0_linkdisable_s1_write), // .write
.linkDisable_s1_readdata (mm_interconnect_0_linkdisable_s1_readdata), // .readdata
.linkDisable_s1_writedata (mm_interconnect_0_linkdisable_s1_writedata), // .writedata
.linkDisable_s1_chipselect (mm_interconnect_0_linkdisable_s1_chipselect), // .chipselect
.linkStart_s1_address (mm_interconnect_0_linkstart_s1_address), // linkStart_s1.address
.linkStart_s1_write (mm_interconnect_0_linkstart_s1_write), // .write
.linkStart_s1_readdata (mm_interconnect_0_linkstart_s1_readdata), // .readdata
.linkStart_s1_writedata (mm_interconnect_0_linkstart_s1_writedata), // .writedata
.linkStart_s1_chipselect (mm_interconnect_0_linkstart_s1_chipselect), // .chipselect
.linkStatus_s1_address (mm_interconnect_0_linkstatus_s1_address), // linkStatus_s1.address
.linkStatus_s1_readdata (mm_interconnect_0_linkstatus_s1_readdata), // .readdata
.outstandingCount_s1_address (mm_interconnect_0_outstandingcount_s1_address), // outstandingCount_s1.address
.outstandingCount_s1_readdata (mm_interconnect_0_outstandingcount_s1_readdata), // .readdata
.receiveActivity_s1_address (mm_interconnect_0_receiveactivity_s1_address), // receiveActivity_s1.address
.receiveActivity_s1_readdata (mm_interconnect_0_receiveactivity_s1_readdata), // .readdata
.receiveClock_s1_address (mm_interconnect_0_receiveclock_s1_address), // receiveClock_s1.address
.receiveClock_s1_write (mm_interconnect_0_receiveclock_s1_write), // .write
.receiveClock_s1_readdata (mm_interconnect_0_receiveclock_s1_readdata), // .readdata
.receiveClock_s1_writedata (mm_interconnect_0_receiveclock_s1_writedata), // .writedata
.receiveClock_s1_chipselect (mm_interconnect_0_receiveclock_s1_chipselect), // .chipselect
.receiveFIFODataCount_s1_address (mm_interconnect_0_receivefifodatacount_s1_address), // receiveFIFODataCount_s1.address
.receiveFIFODataCount_s1_readdata (mm_interconnect_0_receivefifodatacount_s1_readdata), // .readdata
.receiveFIFODataOut_s1_address (mm_interconnect_0_receivefifodataout_s1_address), // receiveFIFODataOut_s1.address
.receiveFIFODataOut_s1_readdata (mm_interconnect_0_receivefifodataout_s1_readdata), // .readdata
.receiveFIFOEmpty_s1_address (mm_interconnect_0_receivefifoempty_s1_address), // receiveFIFOEmpty_s1.address
.receiveFIFOEmpty_s1_readdata (mm_interconnect_0_receivefifoempty_s1_readdata), // .readdata
.receiveFIFOFull_s1_address (mm_interconnect_0_receivefifofull_s1_address), // receiveFIFOFull_s1.address
.receiveFIFOFull_s1_readdata (mm_interconnect_0_receivefifofull_s1_readdata), // .readdata
.receiveFIFOReadEnable_s1_address (mm_interconnect_0_receivefiforeadenable_s1_address), // receiveFIFOReadEnable_s1.address
.receiveFIFOReadEnable_s1_write (mm_interconnect_0_receivefiforeadenable_s1_write), // .write
.receiveFIFOReadEnable_s1_readdata (mm_interconnect_0_receivefiforeadenable_s1_readdata), // .readdata
.receiveFIFOReadEnable_s1_writedata (mm_interconnect_0_receivefiforeadenable_s1_writedata), // .writedata
.receiveFIFOReadEnable_s1_chipselect (mm_interconnect_0_receivefiforeadenable_s1_chipselect), // .chipselect
.spaceWireDataIn_s1_address (mm_interconnect_0_spacewiredatain_s1_address), // spaceWireDataIn_s1.address
.spaceWireDataIn_s1_write (mm_interconnect_0_spacewiredatain_s1_write), // .write
.spaceWireDataIn_s1_readdata (mm_interconnect_0_spacewiredatain_s1_readdata), // .readdata
.spaceWireDataIn_s1_writedata (mm_interconnect_0_spacewiredatain_s1_writedata), // .writedata
.spaceWireDataIn_s1_chipselect (mm_interconnect_0_spacewiredatain_s1_chipselect), // .chipselect
.spaceWireDataOut_s1_address (mm_interconnect_0_spacewiredataout_s1_address), // spaceWireDataOut_s1.address
.spaceWireDataOut_s1_readdata (mm_interconnect_0_spacewiredataout_s1_readdata), // .readdata
.spaceWireStrobeIn_s1_address (mm_interconnect_0_spacewirestrobein_s1_address), // spaceWireStrobeIn_s1.address
.spaceWireStrobeIn_s1_write (mm_interconnect_0_spacewirestrobein_s1_write), // .write
.spaceWireStrobeIn_s1_readdata (mm_interconnect_0_spacewirestrobein_s1_readdata), // .readdata
.spaceWireStrobeIn_s1_writedata (mm_interconnect_0_spacewirestrobein_s1_writedata), // .writedata
.spaceWireStrobeIn_s1_chipselect (mm_interconnect_0_spacewirestrobein_s1_chipselect), // .chipselect
.spaceWireStrobeOut_s1_address (mm_interconnect_0_spacewirestrobeout_s1_address), // spaceWireStrobeOut_s1.address
.spaceWireStrobeOut_s1_readdata (mm_interconnect_0_spacewirestrobeout_s1_readdata), // .readdata
.statisticalInformation_0_s1_address (mm_interconnect_0_statisticalinformation_0_s1_address), // statisticalInformation_0_s1.address
.statisticalInformation_0_s1_readdata (mm_interconnect_0_statisticalinformation_0_s1_readdata), // .readdata
.statisticalInformation_1_s1_address (mm_interconnect_0_statisticalinformation_1_s1_address), // statisticalInformation_1_s1.address
.statisticalInformation_1_s1_write (mm_interconnect_0_statisticalinformation_1_s1_write), // .write
.statisticalInformation_1_s1_readdata (mm_interconnect_0_statisticalinformation_1_s1_readdata), // .readdata
.statisticalInformation_1_s1_writedata (mm_interconnect_0_statisticalinformation_1_s1_writedata), // .writedata
.statisticalInformation_1_s1_chipselect (mm_interconnect_0_statisticalinformation_1_s1_chipselect), // .chipselect
.statisticalInformationClear_s1_address (mm_interconnect_0_statisticalinformationclear_s1_address), // statisticalInformationClear_s1.address
.statisticalInformationClear_s1_write (mm_interconnect_0_statisticalinformationclear_s1_write), // .write
.statisticalInformationClear_s1_readdata (mm_interconnect_0_statisticalinformationclear_s1_readdata), // .readdata
.statisticalInformationClear_s1_writedata (mm_interconnect_0_statisticalinformationclear_s1_writedata), // .writedata
.statisticalInformationClear_s1_chipselect (mm_interconnect_0_statisticalinformationclear_s1_chipselect), // .chipselect
.tickIn_s1_address (mm_interconnect_0_tickin_s1_address), // tickIn_s1.address
.tickIn_s1_write (mm_interconnect_0_tickin_s1_write), // .write
.tickIn_s1_readdata (mm_interconnect_0_tickin_s1_readdata), // .readdata
.tickIn_s1_writedata (mm_interconnect_0_tickin_s1_writedata), // .writedata
.tickIn_s1_chipselect (mm_interconnect_0_tickin_s1_chipselect), // .chipselect
.tickOut_s1_address (mm_interconnect_0_tickout_s1_address), // tickOut_s1.address
.tickOut_s1_readdata (mm_interconnect_0_tickout_s1_readdata), // .readdata
.timeIn_s1_address (mm_interconnect_0_timein_s1_address), // timeIn_s1.address
.timeIn_s1_write (mm_interconnect_0_timein_s1_write), // .write
.timeIn_s1_readdata (mm_interconnect_0_timein_s1_readdata), // .readdata
.timeIn_s1_writedata (mm_interconnect_0_timein_s1_writedata), // .writedata
.timeIn_s1_chipselect (mm_interconnect_0_timein_s1_chipselect), // .chipselect
.timeOut_s1_address (mm_interconnect_0_timeout_s1_address), // timeOut_s1.address
.timeOut_s1_readdata (mm_interconnect_0_timeout_s1_readdata), // .readdata
.transmitActivity_s1_address (mm_interconnect_0_transmitactivity_s1_address), // transmitActivity_s1.address
.transmitActivity_s1_readdata (mm_interconnect_0_transmitactivity_s1_readdata), // .readdata
.transmitClock_s1_address (mm_interconnect_0_transmitclock_s1_address), // transmitClock_s1.address
.transmitClock_s1_write (mm_interconnect_0_transmitclock_s1_write), // .write
.transmitClock_s1_readdata (mm_interconnect_0_transmitclock_s1_readdata), // .readdata
.transmitClock_s1_writedata (mm_interconnect_0_transmitclock_s1_writedata), // .writedata
.transmitClock_s1_chipselect (mm_interconnect_0_transmitclock_s1_chipselect), // .chipselect
.transmitClockDivideValue_s1_address (mm_interconnect_0_transmitclockdividevalue_s1_address), // transmitClockDivideValue_s1.address
.transmitClockDivideValue_s1_write (mm_interconnect_0_transmitclockdividevalue_s1_write), // .write
.transmitClockDivideValue_s1_readdata (mm_interconnect_0_transmitclockdividevalue_s1_readdata), // .readdata
.transmitClockDivideValue_s1_writedata (mm_interconnect_0_transmitclockdividevalue_s1_writedata), // .writedata
.transmitClockDivideValue_s1_chipselect (mm_interconnect_0_transmitclockdividevalue_s1_chipselect), // .chipselect
.transmitFIFODataCount_s1_address (mm_interconnect_0_transmitfifodatacount_s1_address), // transmitFIFODataCount_s1.address
.transmitFIFODataCount_s1_readdata (mm_interconnect_0_transmitfifodatacount_s1_readdata), // .readdata
.transmitFIFODataIn_s1_address (mm_interconnect_0_transmitfifodatain_s1_address), // transmitFIFODataIn_s1.address
.transmitFIFODataIn_s1_write (mm_interconnect_0_transmitfifodatain_s1_write), // .write
.transmitFIFODataIn_s1_readdata (mm_interconnect_0_transmitfifodatain_s1_readdata), // .readdata
.transmitFIFODataIn_s1_writedata (mm_interconnect_0_transmitfifodatain_s1_writedata), // .writedata
.transmitFIFODataIn_s1_chipselect (mm_interconnect_0_transmitfifodatain_s1_chipselect), // .chipselect
.transmitFIFOFull_s1_address (mm_interconnect_0_transmitfifofull_s1_address), // transmitFIFOFull_s1.address
.transmitFIFOFull_s1_readdata (mm_interconnect_0_transmitfifofull_s1_readdata), // .readdata
.transmitFIFOWriteEnable_s1_address (mm_interconnect_0_transmitfifowriteenable_s1_address), // transmitFIFOWriteEnable_s1.address
.transmitFIFOWriteEnable_s1_write (mm_interconnect_0_transmitfifowriteenable_s1_write), // .write
.transmitFIFOWriteEnable_s1_readdata (mm_interconnect_0_transmitfifowriteenable_s1_readdata), // .readdata
.transmitFIFOWriteEnable_s1_writedata (mm_interconnect_0_transmitfifowriteenable_s1_writedata), // .writedata
.transmitFIFOWriteEnable_s1_chipselect (mm_interconnect_0_transmitfifowriteenable_s1_chipselect) // .chipselect
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~hps_0_h2f_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~hps_0_h2f_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module der_smdisp
(
input de_clk,
input de_rstn,
input en_3d,
input cmdrdy,
input sup_done,
input abort_cmd,
input dex_busy,
input [3:0] opc_1,
input [3:0] opc_15,
input [3:0] opc_2,
input pc_last, // Last push from the pixel cache.
input cmd_done_3d,
input pal_busy,
output reg go_sup,
output reg load_15, // Transfer parameters from L1 to L1.5
output reg load_actvn, // Transfer parameters from L1.5 to L2 or L1 to L2.
output reg load_actv_3d, // Transfer parameters from L1.5 to L2, in 3D engine.
output reg goline,
output reg goblt,
output reg pal_load,
output reg tc_inv_cmd,
output reg cmdack,
output reg cmdcpyclr,
output reg busy_3d
);
//////////////////////////////////////////////////////////////////
// DISPATCHER STATE MACHINE
// DEFINE PARAMETERS
//
reg abort_cmd_flag;
reg abort_cmd_ack;
reg sup_done_flag;
reg sup_done_ack;
reg goline_ii;
reg goblt_ii;
reg goline_i;
reg goblt_i;
reg dex_3d_busy;
reg sup_busy;
`ifdef RTL_ENUM
enum {
IDLE =3'b000,
DECODE =3'b001,
DECODE2 =3'b010,
WAIT_SUP =3'b011,
DECODE3 =3'b100,
WAIT_3D =3'b101,
BUSY =3'b110,
NOOP_ST =3'b111
} d_cs;
`else
parameter
IDLE =3'b000,
DECODE =3'b001,
DECODE2 =3'b010,
WAIT_SUP =3'b011,
DECODE3 =3'b100,
WAIT_3D =3'b101,
BUSY =3'b110,
NOOP_ST =3'b111;
reg [2:0] d_cs;
`endif
parameter
NOOP = 4'h0,
BLT = 4'h1,
LINE = 4'h2,
ELINE = 4'h3,
P_LINE = 4'h5,
RXFER = 4'h6,
WXFER = 4'h7,
LINE_3D = 4'h8,
TRIAN_3D = 4'h9,
LD_TEX = 4'hA,
LD_TPAL = 4'hB,
busy_0 = 3'b001,
busy_15 = 3'b010,
busy_2 = 3'b100;
// Delay goblt and goline for data delay.
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
goblt_ii <= 1'b0;
goline_ii <= 1'b0;
goblt <= 1'b0;
goline <= 1'b0;
end
else begin
goblt <= goblt_ii;
goblt_ii <= goblt_i;
goline <= goline_ii;
goline_ii <= goline_i;
end
end
// Capture abort and sup_done.
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
abort_cmd_flag <= 1'b0;
sup_done_flag <= 1'b0;
dex_3d_busy <= 1'b0;
busy_3d <= 1'b0;
end
else begin
if(abort_cmd) abort_cmd_flag <= 1'b1;
else if(abort_cmd_ack) abort_cmd_flag <= 1'b0;
if(sup_done) sup_done_flag <= 1'b1;
else if(sup_done_ack) sup_done_flag <= 1'b0;
if(load_actv_3d) dex_3d_busy <= 1'b1;
// else if(cmd_done_3d) dex_3d_busy <= 1'b0;
else if(pc_last) dex_3d_busy <= 1'b0;
if(d_cs == IDLE) busy_3d <= 1'b0;
else if(load_actv_3d) busy_3d <= 1'b1;
end
end
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
go_sup <= 1'b0;
sup_busy <= 1'b0;
load_15 <= 1'b0;
cmdack <= 1'b0;
load_actvn <= 1'b1;
load_actv_3d <= 1'b0;
cmdcpyclr <= 1'b0;
goline_i <= 1'b0;
goblt_i <= 1'b0;
pal_load <= 1'b0;
tc_inv_cmd <= 1'b0;
abort_cmd_ack <= 1'b0;
sup_done_ack <= 1'b0;
d_cs <= IDLE;
end
else begin
go_sup <= 1'b0;
load_15 <= 1'b0;
cmdack <= 1'b0;
load_actvn <= 1'b1;
load_actv_3d <= 1'b0;
cmdcpyclr <= 1'b0;
goline_i <= 1'b0;
goblt_i <= 1'b0;
pal_load <= 1'b0;
tc_inv_cmd <= 1'b0;
abort_cmd_ack <= 1'b0;
sup_done_ack <= 1'b0;
case(d_cs)
// No commands in pipe.
// Wait for command ready.
IDLE: if(!cmdrdy)d_cs <= IDLE;
// NOOP, or obsolete RXFER, WXFER.
else if((opc_1==NOOP) || (opc_1==RXFER) || (opc_1==WXFER)) begin
cmdack <= 1'b1; // Free Level 1.
d_cs <= NOOP_ST; // Kill one cycle.
end
// 3D Command, load L15, and start setup engine.
else if(((opc_1==TRIAN_3D) || (opc_1==LINE_3D)) & en_3d & !sup_busy) begin
go_sup <= 1'b1; // Start setup.
load_15 <= 1'b1; // Load Level 15.
cmdack <= 1'b1; // Free Level 1.
sup_busy <= 1'b1;
d_cs <= WAIT_SUP; // Go wait for setup.
end
// 2D Command.
else begin
if(opc_1 == BLT) begin goblt_i <= 1'b1; cmdack <= 1'b1; end
if(opc_1 == LINE) begin goline_i <= 1'b1; cmdack <= 1'b1; end
if(opc_1 == ELINE) begin goline_i <= 1'b1; cmdack <= 1'b1; end
if(opc_1 == P_LINE) begin goline_i <= 1'b1; cmdack <= 1'b1; end
if((opc_1 == LD_TEX) & en_3d) cmdack <= 1'b1;
if((opc_1 == LD_TPAL) & en_3d) cmdack <= 1'b1;
if(en_3d) begin // if 3D Core, L15 is included.
load_15 <= 1'b1;
d_cs <= DECODE;
end else begin // else just L2 is included.
load_actvn <= 1'b1;
d_cs <= DECODE2;
end
end
DECODE: begin // Not a 3D command transfer 1.5 to 2.0
d_cs <= DECODE2;
load_actvn <= 1'b0;
end
DECODE2: d_cs <= BUSY;
WAIT_SUP: begin // Wait for setup, no 3D in progress.
if(abort_cmd_flag && !dex_3d_busy) begin
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
abort_cmd_ack <= 1'b1;
sup_busy <= 1'b0;
end
// SUP done no 3D in progress.
else if(sup_done_flag && !dex_3d_busy) begin
d_cs <= DECODE3;
cmdcpyclr <= 1'b1;
load_actvn <= 1'b0;
load_actv_3d <= 1'b1;
sup_done_ack <= 1'b1;
sup_busy <= 1'b0;
end
else d_cs <= WAIT_SUP;
end
DECODE3: d_cs <= WAIT_3D;
WAIT_3D: begin // 3D in progress, another setup can be started.
if(!dex_3d_busy) begin
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
end
else if(!cmdrdy || sup_busy)d_cs <= WAIT_3D;
// if another 3D command start setup.
else if((opc_1==TRIAN_3D) || (opc_1==LINE_3D) ) begin
go_sup <= 1'b1; // Start setup.
load_15 <= 1'b1; // Load Level 15.
cmdack <= 1'b1; // Free Level 1.
sup_busy <= 1'b1;
d_cs <= WAIT_SUP; // Go wait for setup.
end
else d_cs <= WAIT_3D;
end
BUSY: begin
if(opc_2 == LD_TEX && !dex_3d_busy) begin // texture load command done
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
tc_inv_cmd <= 1'b1;
end
else if(opc_2==LD_TPAL && !dex_3d_busy) begin // palette load command done.
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
pal_load <= 1'b1;
end
else if(opc_2==LD_TEX && dex_3d_busy)d_cs <= BUSY;
else if(opc_2==LD_TPAL && dex_3d_busy)d_cs <= BUSY;
else if((opc_2== NOOP) || !dex_busy) begin
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
end
else d_cs <= BUSY;
end
NOOP_ST: d_cs <= IDLE;
endcase
end
end
endmodule |
module Data_Memory
(
clk_i,
rst_i,
addr_i,
data_i,
enable_i,
write_i,
ack_o,
data_o
);
// Interface
input clk_i;
input rst_i;
input [31:0] addr_i;
input [255:0] data_i;
input enable_i;
input write_i;
output ack_o;
output [255:0] data_o;
// Memory
reg [255:0] memory [0:511]; //16KB
reg [3:0] count;
reg ack;
reg ok;
reg [255:0] data;
wire [26:0] addr;
parameter STATE_IDLE = 3'h0,
STATE_WAIT = 3'h1,
STATE_ACK = 3'h2,
STATE_FINISH = 3'h3;
reg [1:0] state;
assign ack_o = ack;
assign addr = addr_i>>5;
assign data_o = data;
//Controller
always@(posedge clk_i or negedge rst_i) begin
if(~rst_i) begin
count <= 4'b0;
ok <= 1'b0;
ack <= 1'b0;
state <= STATE_IDLE;
end
else begin
case(state)
STATE_IDLE: begin
if(enable_i) begin
count <= count + 1;
state <= STATE_WAIT;
end
else begin
state <= STATE_IDLE;
end
end
STATE_WAIT: begin
if(count == 4'd6) begin
ok <= 1'b1;
state <= STATE_ACK;
end
else begin
count <= count + 1;
state <= STATE_WAIT;
end
end
STATE_ACK: begin
count <= 4'b0;
ok <= 1'b0;
ack <= 1'b1;
state <= STATE_FINISH;
end
STATE_FINISH: begin
ack <= 1'b0;
state <= STATE_IDLE;
end
endcase
end
end
// Read Data
always@(posedge clk_i) begin
if(ok && !write_i) begin
data = memory[addr];
end
end
// Write Data
always@(posedge clk_i) begin
if(ok && write_i) begin
memory[addr] <= data_i;
end
end
endmodule |
module tuner_2 #(
parameter dsz = 10,
fsz = 26,
psz = 12
)
(
input clk, reset,
input signed [dsz-1:0] in,
input [fsz-1:0] frq,
input ns_ena,
output signed [dsz-1:0] i_out, q_out
);
// phase accumulator
reg [fsz-1:0] acc;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
acc <= {fsz{1'b0}};
end
else
begin
acc <= acc + frq;
end
end
// noise shaping
reg [fsz-1:0] ns_acc;
wire [psz-1:0] phs = ns_acc[fsz-1:fsz-psz];
wire [fsz-1:0] res = ns_acc[fsz-psz-1:0];
always @(posedge clk)
begin
if(reset == 1'b1)
begin
ns_acc <= {fsz{1'b0}};
end
else
begin
ns_acc <= acc + (ns_ena ? {{psz{res[fsz-psz-1]}},res} : 0);
end
end
//------------------------------
// I slice instance
//------------------------------
tuner_slice_1k #(
.dsz(dsz),
.psz(psz)
)
u_slice_i(
.clk(clk),
.reset(reset),
.shf_90(1'b1),
.in(in),
.phs(phs),
.out(i_out)
);
//------------------------------
// Q slice instance
//------------------------------
tuner_slice_1k #(
.dsz(dsz),
.psz(psz)
)
u_slice_q(
.clk(clk),
.reset(reset),
.shf_90(1'b0),
.in(in),
.phs(phs),
.out(q_out)
);
endmodule |
module sky130_fd_sc_ms__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule |
module sky130_fd_sc_hs__dfsbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_df_p_s_no_pg u_df_p_s_no_pg0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule |
module mux2_1_tb;
// Inputs
reg [7:0] input1;
reg [7:0] input2;
reg select;
// Outputs
wire [7:0] selected_out;
// Instantiate the Unit Under Test (UUT)
mux2_1 uut (
.input1(input1),
.input2(input2),
.select(select),
.selected_out(selected_out)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
select = 0;
// Wait 100 ns for global reset to finish
#100;
// First case: select input2 from mux
input1 = 8'b10000001;
input2 = 8'b10101010;
select = 1'b1;
#100;
// Second Case: select input1 from mux
select = 1'b0;
end
endmodule |
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule |
module altera_pli_streaming (
clk,
reset_n,
// source out
source_valid,
source_data,
source_ready,
// sink in
sink_valid,
sink_data,
sink_ready,
// resetrequest
resetrequest
);
parameter PLI_PORT = 50000;
parameter PURPOSE = 0;
input clk;
input reset_n;
output reg source_valid;
output reg [7 : 0] source_data;
input source_ready;
input sink_valid;
input [7 : 0] sink_data;
output reg sink_ready;
output reg resetrequest;
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(.PURPOSE(PURPOSE)) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)
);
always @* begin
source_valid = jtag_source_valid;
source_data = jtag_source_data;
sink_ready = jtag_sink_ready;
resetrequest = jtag_resetrequest;
//synthesis translate_off
source_valid = pli_out_valid;
source_data = pli_out_data;
sink_ready = pli_in_ready;
resetrequest = 0;
//synthesis translate_on
end
endmodule |
module sky130_fd_sc_ls__tapvgndnovpb (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule |
module sky130_fd_sc_ls__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sirv_uart(
input clock,
input reset,
output io_interrupts_0_0,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [4:0] io_in_0_a_bits_source,
input [28:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [4:0] io_in_0_b_bits_source,
output [28:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [4:0] io_in_0_c_bits_source,
input [28:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [4:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
output io_port_txd,
input io_port_rxd
);
wire txm_clock;
wire txm_reset;
wire txm_io_en;
wire txm_io_in_ready;
wire txm_io_in_valid;
wire [7:0] txm_io_in_bits;
wire txm_io_out;
wire [15:0] txm_io_div;
wire txm_io_nstop;
wire txq_clock;
wire txq_reset;
wire txq_io_enq_ready;
wire txq_io_enq_valid;
wire [7:0] txq_io_enq_bits;
wire txq_io_deq_ready;
wire txq_io_deq_valid;
wire [7:0] txq_io_deq_bits;
wire [3:0] txq_io_count;
wire rxm_clock;
wire rxm_reset;
wire rxm_io_en;
wire rxm_io_in;
wire rxm_io_out_valid;
wire [7:0] rxm_io_out_bits;
wire [15:0] rxm_io_div;
wire rxq_clock;
wire rxq_reset;
wire rxq_io_enq_ready;
wire rxq_io_enq_valid;
wire [7:0] rxq_io_enq_bits;
wire rxq_io_deq_ready;
wire rxq_io_deq_valid;
wire [7:0] rxq_io_deq_bits;
wire [3:0] rxq_io_count;
reg [15:0] div;
reg [31:0] GEN_76;
reg txen;
reg [31:0] GEN_77;
reg rxen;
reg [31:0] GEN_78;
reg [3:0] txwm;
reg [31:0] GEN_79;
reg [3:0] rxwm;
reg [31:0] GEN_80;
reg nstop;
reg [31:0] GEN_81;
wire T_902_rxwm;
wire T_902_txwm;
wire [1:0] T_906;
wire T_907;
wire T_908;
reg ie_rxwm;
reg [31:0] GEN_82;
reg ie_txwm;
reg [31:0] GEN_83;
wire ip_rxwm;
wire ip_txwm;
wire T_916;
wire T_917;
wire T_918;
wire T_919;
wire T_920;
wire T_924;
wire T_927;
wire T_951_ready;
wire T_951_valid;
wire T_951_bits_read;
wire [9:0] T_951_bits_index;
wire [31:0] T_951_bits_data;
wire [3:0] T_951_bits_mask;
wire [9:0] T_951_bits_extra;
wire T_968;
wire [26:0] T_969;
wire [1:0] T_970;
wire [6:0] T_971;
wire [9:0] T_972;
wire T_990_ready;
wire T_990_valid;
wire T_990_bits_read;
wire [31:0] T_990_bits_data;
wire [9:0] T_990_bits_extra;
wire T_1026_ready;
wire T_1026_valid;
wire T_1026_bits_read;
wire [9:0] T_1026_bits_index;
wire [31:0] T_1026_bits_data;
wire [3:0] T_1026_bits_mask;
wire [9:0] T_1026_bits_extra;
wire [9:0] T_1063;
wire T_1065;
wire [9:0] T_1071;
wire [9:0] T_1072;
wire T_1074;
wire [9:0] T_1080;
wire [9:0] T_1081;
wire T_1083;
wire [9:0] T_1089;
wire [9:0] T_1090;
wire T_1092;
wire [9:0] T_1098;
wire [9:0] T_1099;
wire T_1101;
wire [9:0] T_1107;
wire [9:0] T_1108;
wire T_1110;
wire [9:0] T_1116;
wire [9:0] T_1117;
wire T_1119;
wire T_1127_0;
wire T_1127_1;
wire T_1127_2;
wire T_1127_3;
wire T_1127_4;
wire T_1127_5;
wire T_1127_6;
wire T_1127_7;
wire T_1127_8;
wire T_1127_9;
wire T_1127_10;
wire T_1127_11;
wire T_1127_12;
wire T_1127_13;
wire T_1127_14;
wire T_1127_15;
wire T_1132_0;
wire T_1132_1;
wire T_1132_2;
wire T_1132_3;
wire T_1132_4;
wire T_1132_5;
wire T_1132_6;
wire T_1132_7;
wire T_1132_8;
wire T_1132_9;
wire T_1132_10;
wire T_1132_11;
wire T_1132_12;
wire T_1132_13;
wire T_1132_14;
wire T_1132_15;
wire T_1137_0;
wire T_1137_1;
wire T_1137_2;
wire T_1137_3;
wire T_1137_4;
wire T_1137_5;
wire T_1137_6;
wire T_1137_7;
wire T_1137_8;
wire T_1137_9;
wire T_1137_10;
wire T_1137_11;
wire T_1137_12;
wire T_1137_13;
wire T_1137_14;
wire T_1137_15;
wire T_1142_0;
wire T_1142_1;
wire T_1142_2;
wire T_1142_3;
wire T_1142_4;
wire T_1142_5;
wire T_1142_6;
wire T_1142_7;
wire T_1142_8;
wire T_1142_9;
wire T_1142_10;
wire T_1142_11;
wire T_1142_12;
wire T_1142_13;
wire T_1142_14;
wire T_1142_15;
wire T_1147_0;
wire T_1147_1;
wire T_1147_2;
wire T_1147_3;
wire T_1147_4;
wire T_1147_5;
wire T_1147_6;
wire T_1147_7;
wire T_1147_8;
wire T_1147_9;
wire T_1147_10;
wire T_1147_11;
wire T_1147_12;
wire T_1147_13;
wire T_1147_14;
wire T_1147_15;
wire T_1152_0;
wire T_1152_1;
wire T_1152_2;
wire T_1152_3;
wire T_1152_4;
wire T_1152_5;
wire T_1152_6;
wire T_1152_7;
wire T_1152_8;
wire T_1152_9;
wire T_1152_10;
wire T_1152_11;
wire T_1152_12;
wire T_1152_13;
wire T_1152_14;
wire T_1152_15;
wire T_1157_0;
wire T_1157_1;
wire T_1157_2;
wire T_1157_3;
wire T_1157_4;
wire T_1157_5;
wire T_1157_6;
wire T_1157_7;
wire T_1157_8;
wire T_1157_9;
wire T_1157_10;
wire T_1157_11;
wire T_1157_12;
wire T_1157_13;
wire T_1157_14;
wire T_1157_15;
wire T_1162_0;
wire T_1162_1;
wire T_1162_2;
wire T_1162_3;
wire T_1162_4;
wire T_1162_5;
wire T_1162_6;
wire T_1162_7;
wire T_1162_8;
wire T_1162_9;
wire T_1162_10;
wire T_1162_11;
wire T_1162_12;
wire T_1162_13;
wire T_1162_14;
wire T_1162_15;
wire T_1204;
wire T_1205;
wire T_1206;
wire T_1207;
wire [7:0] T_1211;
wire [7:0] T_1215;
wire [7:0] T_1219;
wire [7:0] T_1223;
wire [15:0] T_1224;
wire [15:0] T_1225;
wire [31:0] T_1226;
wire [7:0] T_1250;
wire T_1252;
wire [7:0] T_1254;
wire T_1256;
wire T_1269;
wire [7:0] T_1270;
wire [31:0] GEN_56;
wire [31:0] T_1365;
wire T_1370;
wire T_1374;
wire T_1376;
wire T_1390;
wire T_1410;
wire T_1414;
wire T_1416;
wire T_1430;
wire [1:0] GEN_57;
wire [1:0] T_1445;
wire [1:0] GEN_58;
wire [1:0] T_1449;
wire T_1465;
wire [7:0] T_1485;
wire [30:0] T_1529;
wire [31:0] GEN_59;
wire [31:0] T_1565;
wire [31:0] GEN_60;
wire [31:0] T_1569;
wire [15:0] T_1570;
wire [15:0] T_1574;
wire T_1576;
wire T_1589;
wire [15:0] T_1590;
wire [15:0] GEN_6;
wire T_1629;
wire GEN_7;
wire T_1669;
wire GEN_8;
wire [1:0] GEN_61;
wire [1:0] T_1685;
wire [1:0] GEN_62;
wire [1:0] T_1689;
wire [3:0] T_1690;
wire [3:0] T_1694;
wire T_1696;
wire T_1709;
wire [3:0] T_1710;
wire [3:0] GEN_9;
wire [19:0] GEN_63;
wire [19:0] T_1725;
wire [19:0] GEN_64;
wire [19:0] T_1729;
wire T_1749;
wire GEN_10;
wire T_1789;
wire [3:0] GEN_11;
wire [19:0] GEN_65;
wire [19:0] T_1805;
wire [19:0] GEN_66;
wire [19:0] T_1809;
wire T_1829;
wire GEN_12;
wire T_1869;
wire GEN_13;
wire [1:0] GEN_67;
wire [1:0] T_1885;
wire [1:0] GEN_68;
wire [1:0] T_1889;
wire T_1891;
wire T_1892;
wire T_1893;
wire T_1895;
wire T_1897;
wire T_1898;
wire T_1899;
wire T_1901;
wire T_1903;
wire T_1904;
wire T_1905;
wire T_1907;
wire T_1909;
wire T_1910;
wire T_1912;
wire T_1914;
wire T_1915;
wire T_1917;
wire T_1919;
wire T_1920;
wire T_1922;
wire T_1924;
wire T_1926;
wire T_1941_0;
wire T_1941_1;
wire T_1941_2;
wire T_1941_3;
wire T_1941_4;
wire T_1941_5;
wire T_1941_6;
wire T_1941_7;
wire T_1954;
wire T_1955;
wire T_1957;
wire T_1960;
wire T_1961;
wire T_1963;
wire T_1966;
wire T_1967;
wire T_1969;
wire T_1972;
wire T_1974;
wire T_1977;
wire T_1979;
wire T_1982;
wire T_1984;
wire T_1988;
wire T_2003_0;
wire T_2003_1;
wire T_2003_2;
wire T_2003_3;
wire T_2003_4;
wire T_2003_5;
wire T_2003_6;
wire T_2003_7;
wire T_2016;
wire T_2017;
wire T_2019;
wire T_2022;
wire T_2023;
wire T_2025;
wire T_2028;
wire T_2029;
wire T_2031;
wire T_2034;
wire T_2036;
wire T_2039;
wire T_2041;
wire T_2044;
wire T_2046;
wire T_2050;
wire T_2065_0;
wire T_2065_1;
wire T_2065_2;
wire T_2065_3;
wire T_2065_4;
wire T_2065_5;
wire T_2065_6;
wire T_2065_7;
wire T_2078;
wire T_2079;
wire T_2081;
wire T_2084;
wire T_2085;
wire T_2087;
wire T_2090;
wire T_2091;
wire T_2093;
wire T_2096;
wire T_2098;
wire T_2101;
wire T_2103;
wire T_2106;
wire T_2108;
wire T_2112;
wire T_2127_0;
wire T_2127_1;
wire T_2127_2;
wire T_2127_3;
wire T_2127_4;
wire T_2127_5;
wire T_2127_6;
wire T_2127_7;
wire T_2138;
wire T_2139;
wire T_2140;
wire [1:0] T_2148;
wire [2:0] T_2149;
wire GEN_0;
wire GEN_14;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_1;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire GEN_26;
wire GEN_27;
wire T_2164;
wire GEN_2;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_3;
wire GEN_35;
wire GEN_36;
wire GEN_37;
wire GEN_38;
wire GEN_39;
wire GEN_40;
wire GEN_41;
wire T_2167;
wire T_2168;
wire T_2169;
wire T_2170;
wire T_2171;
wire [7:0] T_2173;
wire [1:0] T_2174;
wire [1:0] T_2175;
wire [3:0] T_2176;
wire [1:0] T_2177;
wire [1:0] T_2178;
wire [3:0] T_2179;
wire [7:0] T_2180;
wire [7:0] T_2181;
wire T_2192;
wire T_2193;
wire T_2194;
wire T_2195;
wire T_2198;
wire T_2199;
wire T_2201;
wire T_2202;
wire T_2203;
wire T_2205;
wire T_2209;
wire T_2211;
wire T_2214;
wire T_2215;
wire T_2221;
wire T_2225;
wire T_2231;
wire T_2234;
wire T_2235;
wire T_2241;
wire T_2245;
wire T_2251;
wire T_2254;
wire T_2255;
wire T_2261;
wire T_2265;
wire T_2271;
wire T_2274;
wire T_2275;
wire T_2281;
wire T_2285;
wire T_2291;
wire T_2294;
wire T_2295;
wire T_2301;
wire T_2305;
wire T_2311;
wire T_2314;
wire T_2315;
wire T_2321;
wire T_2325;
wire T_2331;
wire T_2352;
wire T_2353;
wire T_2355;
wire T_2356;
wire T_2358;
wire T_2359;
wire T_2361;
wire T_2362;
wire T_2365;
wire T_2368;
wire T_2371;
wire T_2374;
wire T_2376;
wire T_2377;
wire T_2379;
wire T_2380;
wire T_2382;
wire T_2383;
wire T_2385;
wire T_2386;
wire T_2388;
wire T_2390;
wire T_2392;
wire T_2394;
wire T_2396;
wire T_2398;
wire T_2400;
wire T_2402;
wire T_2404;
wire T_2405;
wire T_2407;
wire T_2408;
wire T_2410;
wire T_2411;
wire T_2413;
wire T_2414;
wire T_2417;
wire T_2420;
wire T_2423;
wire T_2426;
wire T_2428;
wire T_2429;
wire T_2431;
wire T_2432;
wire T_2434;
wire T_2435;
wire T_2437;
wire T_2438;
wire T_2444;
wire T_2445;
wire T_2447;
wire T_2448;
wire T_2450;
wire T_2451;
wire T_2453;
wire T_2454;
wire T_2457;
wire T_2460;
wire T_2463;
wire T_2466;
wire T_2468;
wire T_2469;
wire T_2471;
wire T_2472;
wire T_2474;
wire T_2475;
wire T_2477;
wire T_2478;
wire T_2480;
wire T_2482;
wire T_2484;
wire T_2486;
wire T_2488;
wire T_2490;
wire T_2492;
wire T_2494;
wire T_2496;
wire T_2498;
wire T_2500;
wire T_2502;
wire T_2504;
wire T_2506;
wire T_2508;
wire T_2510;
wire T_2523_0;
wire T_2523_1;
wire T_2523_2;
wire T_2523_3;
wire T_2523_4;
wire T_2523_5;
wire T_2523_6;
wire T_2523_7;
wire [31:0] T_2546_0;
wire [31:0] T_2546_1;
wire [31:0] T_2546_2;
wire [31:0] T_2546_3;
wire [31:0] T_2546_4;
wire [31:0] T_2546_5;
wire [31:0] T_2546_6;
wire [31:0] T_2546_7;
wire GEN_4;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire [31:0] GEN_5;
wire [31:0] GEN_49;
wire [31:0] GEN_50;
wire [31:0] GEN_51;
wire [31:0] GEN_52;
wire [31:0] GEN_53;
wire [31:0] GEN_54;
wire [31:0] GEN_55;
wire [31:0] T_2559;
wire [1:0] T_2560;
wire [4:0] T_2562;
wire [2:0] T_2563;
wire [2:0] T_2574_opcode;
wire [1:0] T_2574_param;
wire [2:0] T_2574_size;
wire [4:0] T_2574_source;
wire T_2574_sink;
wire [1:0] T_2574_addr_lo;
wire [31:0] T_2574_data;
wire T_2574_error;
wire [2:0] GEN_69 = 3'b0;
wire [1:0] GEN_70 = 2'b0;
wire [2:0] GEN_71 = 3'b0;
wire [4:0] GEN_72 = 5'b0;
wire [28:0] GEN_73 = 29'b0;
wire [3:0] GEN_74 = 4'b0;
wire [31:0] GEN_75 = 32'b0;
sirv_uarttx u_txm (
.clock(txm_clock),
.reset(txm_reset),
.io_en(txm_io_en),
.io_in_ready(txm_io_in_ready),
.io_in_valid(txm_io_in_valid),
.io_in_bits(txm_io_in_bits),
.io_out(txm_io_out),
.io_div(txm_io_div),
.io_nstop(txm_io_nstop)
);
sirv_queue_1 u_txq (
.clock(txq_clock),
.reset(txq_reset),
.io_enq_ready(txq_io_enq_ready),
.io_enq_valid(txq_io_enq_valid),
.io_enq_bits(txq_io_enq_bits),
.io_deq_ready(txq_io_deq_ready),
.io_deq_valid(txq_io_deq_valid),
.io_deq_bits(txq_io_deq_bits),
.io_count(txq_io_count)
);
sirv_uartrx u_rxm (
.clock(rxm_clock),
.reset(rxm_reset),
.io_en(rxm_io_en),
.io_in(rxm_io_in),
.io_out_valid(rxm_io_out_valid),
.io_out_bits(rxm_io_out_bits),
.io_div(rxm_io_div)
);
sirv_queue_1 u_rxq (
.clock(rxq_clock),
.reset(rxq_reset),
.io_enq_ready(rxq_io_enq_ready),
.io_enq_valid(rxq_io_enq_valid),
.io_enq_bits(rxq_io_enq_bits),
.io_deq_ready(rxq_io_deq_ready),
.io_deq_valid(rxq_io_deq_valid),
.io_deq_bits(rxq_io_deq_bits),
.io_count(rxq_io_count)
);
assign io_interrupts_0_0 = T_920;
assign io_in_0_a_ready = T_951_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_69;
assign io_in_0_b_bits_param = GEN_70;
assign io_in_0_b_bits_size = GEN_71;
assign io_in_0_b_bits_source = GEN_72;
assign io_in_0_b_bits_address = GEN_73;
assign io_in_0_b_bits_mask = GEN_74;
assign io_in_0_b_bits_data = GEN_75;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = T_990_valid;
assign io_in_0_d_bits_opcode = {{2'd0}, T_990_bits_read};
assign io_in_0_d_bits_param = T_2574_param;
assign io_in_0_d_bits_size = T_2574_size;
assign io_in_0_d_bits_source = T_2574_source;
assign io_in_0_d_bits_sink = T_2574_sink;
assign io_in_0_d_bits_addr_lo = T_2574_addr_lo;
assign io_in_0_d_bits_data = T_990_bits_data;
assign io_in_0_d_bits_error = T_2574_error;
assign io_in_0_e_ready = 1'h1;
assign io_port_txd = txm_io_out;
assign txm_clock = clock;
assign txm_reset = reset;
assign txm_io_en = txen;
assign txm_io_in_valid = txq_io_deq_valid;
assign txm_io_in_bits = txq_io_deq_bits;
assign txm_io_div = div;
assign txm_io_nstop = nstop;
assign txq_clock = clock;
assign txq_reset = reset;
assign txq_io_enq_valid = T_1269;
assign txq_io_enq_bits = T_1270;
assign txq_io_deq_ready = txm_io_in_ready;
assign rxm_clock = clock;
assign rxm_reset = reset;
assign rxm_io_en = rxen;
assign rxm_io_in = io_port_rxd;
assign rxm_io_div = div;
assign rxq_clock = clock;
assign rxq_reset = reset;
assign rxq_io_enq_valid = rxm_io_out_valid;
assign rxq_io_enq_bits = rxm_io_out_bits;
assign rxq_io_deq_ready = T_1465;
assign T_902_rxwm = T_908;
assign T_902_txwm = T_907;
assign T_906 = 2'h0;
assign T_907 = T_906[0];
assign T_908 = T_906[1];
assign ip_rxwm = T_917;
assign ip_txwm = T_916;
assign T_916 = txq_io_count < txwm;
assign T_917 = rxq_io_count > rxwm;
assign T_918 = ip_txwm & ie_txwm;
assign T_919 = ip_rxwm & ie_rxwm;
assign T_920 = T_918 | T_919;
assign T_924 = txq_io_enq_ready == 1'h0;
assign T_927 = rxq_io_deq_valid == 1'h0;
assign T_951_ready = T_2168;
assign T_951_valid = io_in_0_a_valid;
assign T_951_bits_read = T_968;
assign T_951_bits_index = T_969[9:0];
assign T_951_bits_data = io_in_0_a_bits_data;
assign T_951_bits_mask = io_in_0_a_bits_mask;
assign T_951_bits_extra = T_972;
assign T_968 = io_in_0_a_bits_opcode == 3'h4;
assign T_969 = io_in_0_a_bits_address[28:2];
assign T_970 = io_in_0_a_bits_address[1:0];
assign T_971 = {T_970,io_in_0_a_bits_source};
assign T_972 = {T_971,io_in_0_a_bits_size};
assign T_990_ready = io_in_0_d_ready;
assign T_990_valid = T_2171;
assign T_990_bits_read = T_1026_bits_read;
assign T_990_bits_data = T_2559;
assign T_990_bits_extra = T_1026_bits_extra;
assign T_1026_ready = T_2170;
assign T_1026_valid = T_2169;
assign T_1026_bits_read = T_951_bits_read;
assign T_1026_bits_index = T_951_bits_index;
assign T_1026_bits_data = T_951_bits_data;
assign T_1026_bits_mask = T_951_bits_mask;
assign T_1026_bits_extra = T_951_bits_extra;
assign T_1063 = T_1026_bits_index & 10'h3f8;
assign T_1065 = T_1063 == 10'h0;
assign T_1071 = T_1026_bits_index ^ 10'h5;
assign T_1072 = T_1071 & 10'h3f8;
assign T_1074 = T_1072 == 10'h0;
assign T_1080 = T_1026_bits_index ^ 10'h1;
assign T_1081 = T_1080 & 10'h3f8;
assign T_1083 = T_1081 == 10'h0;
assign T_1089 = T_1026_bits_index ^ 10'h6;
assign T_1090 = T_1089 & 10'h3f8;
assign T_1092 = T_1090 == 10'h0;
assign T_1098 = T_1026_bits_index ^ 10'h2;
assign T_1099 = T_1098 & 10'h3f8;
assign T_1101 = T_1099 == 10'h0;
assign T_1107 = T_1026_bits_index ^ 10'h3;
assign T_1108 = T_1107 & 10'h3f8;
assign T_1110 = T_1108 == 10'h0;
assign T_1116 = T_1026_bits_index ^ 10'h4;
assign T_1117 = T_1116 & 10'h3f8;
assign T_1119 = T_1117 == 10'h0;
assign T_1127_0 = T_2353;
assign T_1127_1 = T_2365;
assign T_1127_2 = T_2377;
assign T_1127_3 = T_2388;
assign T_1127_4 = T_2396;
assign T_1127_5 = T_2405;
assign T_1127_6 = T_2417;
assign T_1127_7 = T_2429;
assign T_1127_8 = T_2315;
assign T_1127_9 = T_2445;
assign T_1127_10 = T_2457;
assign T_1127_11 = T_2469;
assign T_1127_12 = T_2480;
assign T_1127_13 = T_2488;
assign T_1127_14 = T_2496;
assign T_1127_15 = T_2504;
assign T_1132_0 = T_2356;
assign T_1132_1 = T_2368;
assign T_1132_2 = T_2380;
assign T_1132_3 = T_2390;
assign T_1132_4 = T_2398;
assign T_1132_5 = T_2408;
assign T_1132_6 = T_2420;
assign T_1132_7 = T_2432;
assign T_1132_8 = T_2321;
assign T_1132_9 = T_2448;
assign T_1132_10 = T_2460;
assign T_1132_11 = T_2472;
assign T_1132_12 = T_2482;
assign T_1132_13 = T_2490;
assign T_1132_14 = T_2498;
assign T_1132_15 = T_2506;
assign T_1137_0 = 1'h1;
assign T_1137_1 = 1'h1;
assign T_1137_2 = 1'h1;
assign T_1137_3 = 1'h1;
assign T_1137_4 = 1'h1;
assign T_1137_5 = 1'h1;
assign T_1137_6 = 1'h1;
assign T_1137_7 = 1'h1;
assign T_1137_8 = 1'h1;
assign T_1137_9 = 1'h1;
assign T_1137_10 = 1'h1;
assign T_1137_11 = 1'h1;
assign T_1137_12 = 1'h1;
assign T_1137_13 = 1'h1;
assign T_1137_14 = 1'h1;
assign T_1137_15 = 1'h1;
assign T_1142_0 = 1'h1;
assign T_1142_1 = 1'h1;
assign T_1142_2 = 1'h1;
assign T_1142_3 = 1'h1;
assign T_1142_4 = 1'h1;
assign T_1142_5 = 1'h1;
assign T_1142_6 = 1'h1;
assign T_1142_7 = 1'h1;
assign T_1142_8 = 1'h1;
assign T_1142_9 = 1'h1;
assign T_1142_10 = 1'h1;
assign T_1142_11 = 1'h1;
assign T_1142_12 = 1'h1;
assign T_1142_13 = 1'h1;
assign T_1142_14 = 1'h1;
assign T_1142_15 = 1'h1;
assign T_1147_0 = 1'h1;
assign T_1147_1 = 1'h1;
assign T_1147_2 = 1'h1;
assign T_1147_3 = 1'h1;
assign T_1147_4 = 1'h1;
assign T_1147_5 = 1'h1;
assign T_1147_6 = 1'h1;
assign T_1147_7 = 1'h1;
assign T_1147_8 = 1'h1;
assign T_1147_9 = 1'h1;
assign T_1147_10 = 1'h1;
assign T_1147_11 = 1'h1;
assign T_1147_12 = 1'h1;
assign T_1147_13 = 1'h1;
assign T_1147_14 = 1'h1;
assign T_1147_15 = 1'h1;
assign T_1152_0 = 1'h1;
assign T_1152_1 = 1'h1;
assign T_1152_2 = 1'h1;
assign T_1152_3 = 1'h1;
assign T_1152_4 = 1'h1;
assign T_1152_5 = 1'h1;
assign T_1152_6 = 1'h1;
assign T_1152_7 = 1'h1;
assign T_1152_8 = 1'h1;
assign T_1152_9 = 1'h1;
assign T_1152_10 = 1'h1;
assign T_1152_11 = 1'h1;
assign T_1152_12 = 1'h1;
assign T_1152_13 = 1'h1;
assign T_1152_14 = 1'h1;
assign T_1152_15 = 1'h1;
assign T_1157_0 = T_2359;
assign T_1157_1 = T_2371;
assign T_1157_2 = T_2383;
assign T_1157_3 = T_2392;
assign T_1157_4 = T_2400;
assign T_1157_5 = T_2411;
assign T_1157_6 = T_2423;
assign T_1157_7 = T_2435;
assign T_1157_8 = T_2325;
assign T_1157_9 = T_2451;
assign T_1157_10 = T_2463;
assign T_1157_11 = T_2475;
assign T_1157_12 = T_2484;
assign T_1157_13 = T_2492;
assign T_1157_14 = T_2500;
assign T_1157_15 = T_2508;
assign T_1162_0 = T_2362;
assign T_1162_1 = T_2374;
assign T_1162_2 = T_2386;
assign T_1162_3 = T_2394;
assign T_1162_4 = T_2402;
assign T_1162_5 = T_2414;
assign T_1162_6 = T_2426;
assign T_1162_7 = T_2438;
assign T_1162_8 = T_2331;
assign T_1162_9 = T_2454;
assign T_1162_10 = T_2466;
assign T_1162_11 = T_2478;
assign T_1162_12 = T_2486;
assign T_1162_13 = T_2494;
assign T_1162_14 = T_2502;
assign T_1162_15 = T_2510;
assign T_1204 = T_1026_bits_mask[0];
assign T_1205 = T_1026_bits_mask[1];
assign T_1206 = T_1026_bits_mask[2];
assign T_1207 = T_1026_bits_mask[3];
assign T_1211 = T_1204 ? 8'hff : 8'h0;
assign T_1215 = T_1205 ? 8'hff : 8'h0;
assign T_1219 = T_1206 ? 8'hff : 8'h0;
assign T_1223 = T_1207 ? 8'hff : 8'h0;
assign T_1224 = {T_1215,T_1211};
assign T_1225 = {T_1223,T_1219};
assign T_1226 = {T_1225,T_1224};
assign T_1250 = T_1226[7:0];
assign T_1252 = T_1250 != 8'h0;
assign T_1254 = ~ T_1250;
assign T_1256 = T_1254 == 8'h0;
assign T_1269 = T_1162_0 & T_1256;
assign T_1270 = T_1026_bits_data[7:0];
assign GEN_56 = {{31'd0}, T_924};
assign T_1365 = GEN_56 << 31;
assign T_1370 = T_1226[0];
assign T_1374 = ~ T_1370;
assign T_1376 = T_1374 == 1'h0;
assign T_1390 = T_1026_bits_data[0];
assign T_1410 = T_1226[1];
assign T_1414 = ~ T_1410;
assign T_1416 = T_1414 == 1'h0;
assign T_1430 = T_1026_bits_data[1];
assign GEN_57 = {{1'd0}, ip_rxwm};
assign T_1445 = GEN_57 << 1;
assign GEN_58 = {{1'd0}, ip_txwm};
assign T_1449 = GEN_58 | T_1445;
assign T_1465 = T_1157_5 & T_1252;
assign T_1485 = rxq_io_deq_bits;
assign T_1529 = {{23'd0}, T_1485};
assign GEN_59 = {{31'd0}, T_927};
assign T_1565 = GEN_59 << 31;
assign GEN_60 = {{1'd0}, T_1529};
assign T_1569 = GEN_60 | T_1565;
assign T_1570 = T_1226[15:0];
assign T_1574 = ~ T_1570;
assign T_1576 = T_1574 == 16'h0;
assign T_1589 = T_1162_8 & T_1576;
assign T_1590 = T_1026_bits_data[15:0];
assign GEN_6 = T_1589 ? T_1590 : div;
assign T_1629 = T_1162_9 & T_1376;
assign GEN_7 = T_1629 ? T_1390 : txen;
assign T_1669 = T_1162_10 & T_1416;
assign GEN_8 = T_1669 ? T_1430 : nstop;
assign GEN_61 = {{1'd0}, nstop};
assign T_1685 = GEN_61 << 1;
assign GEN_62 = {{1'd0}, txen};
assign T_1689 = GEN_62 | T_1685;
assign T_1690 = T_1226[19:16];
assign T_1694 = ~ T_1690;
assign T_1696 = T_1694 == 4'h0;
assign T_1709 = T_1162_11 & T_1696;
assign T_1710 = T_1026_bits_data[19:16];
assign GEN_9 = T_1709 ? T_1710 : txwm;
assign GEN_63 = {{16'd0}, txwm};
assign T_1725 = GEN_63 << 16;
assign GEN_64 = {{18'd0}, T_1689};
assign T_1729 = GEN_64 | T_1725;
assign T_1749 = T_1162_12 & T_1376;
assign GEN_10 = T_1749 ? T_1390 : rxen;
assign T_1789 = T_1162_13 & T_1696;
assign GEN_11 = T_1789 ? T_1710 : rxwm;
assign GEN_65 = {{16'd0}, rxwm};
assign T_1805 = GEN_65 << 16;
assign GEN_66 = {{19'd0}, rxen};
assign T_1809 = GEN_66 | T_1805;
assign T_1829 = T_1162_14 & T_1376;
assign GEN_12 = T_1829 ? T_1390 : ie_txwm;
assign T_1869 = T_1162_15 & T_1416;
assign GEN_13 = T_1869 ? T_1430 : ie_rxwm;
assign GEN_67 = {{1'd0}, ie_rxwm};
assign T_1885 = GEN_67 << 1;
assign GEN_68 = {{1'd0}, ie_txwm};
assign T_1889 = GEN_68 | T_1885;
assign T_1891 = T_1065 == 1'h0;
assign T_1892 = T_1137_2 & T_1137_1;
assign T_1893 = T_1892 & T_1137_0;
assign T_1895 = T_1891 | T_1893;
assign T_1897 = T_1083 == 1'h0;
assign T_1898 = T_1137_7 & T_1137_6;
assign T_1899 = T_1898 & T_1137_5;
assign T_1901 = T_1897 | T_1899;
assign T_1903 = T_1101 == 1'h0;
assign T_1904 = T_1137_11 & T_1137_10;
assign T_1905 = T_1904 & T_1137_9;
assign T_1907 = T_1903 | T_1905;
assign T_1909 = T_1110 == 1'h0;
assign T_1910 = T_1137_13 & T_1137_12;
assign T_1912 = T_1909 | T_1910;
assign T_1914 = T_1119 == 1'h0;
assign T_1915 = T_1137_15 & T_1137_14;
assign T_1917 = T_1914 | T_1915;
assign T_1919 = T_1074 == 1'h0;
assign T_1920 = T_1137_4 & T_1137_3;
assign T_1922 = T_1919 | T_1920;
assign T_1924 = T_1092 == 1'h0;
assign T_1926 = T_1924 | T_1137_8;
assign T_1941_0 = T_1895;
assign T_1941_1 = T_1901;
assign T_1941_2 = T_1907;
assign T_1941_3 = T_1912;
assign T_1941_4 = T_1917;
assign T_1941_5 = T_1922;
assign T_1941_6 = T_1926;
assign T_1941_7 = 1'h1;
assign T_1954 = T_1142_2 & T_1142_1;
assign T_1955 = T_1954 & T_1142_0;
assign T_1957 = T_1891 | T_1955;
assign T_1960 = T_1142_7 & T_1142_6;
assign T_1961 = T_1960 & T_1142_5;
assign T_1963 = T_1897 | T_1961;
assign T_1966 = T_1142_11 & T_1142_10;
assign T_1967 = T_1966 & T_1142_9;
assign T_1969 = T_1903 | T_1967;
assign T_1972 = T_1142_13 & T_1142_12;
assign T_1974 = T_1909 | T_1972;
assign T_1977 = T_1142_15 & T_1142_14;
assign T_1979 = T_1914 | T_1977;
assign T_1982 = T_1142_4 & T_1142_3;
assign T_1984 = T_1919 | T_1982;
assign T_1988 = T_1924 | T_1142_8;
assign T_2003_0 = T_1957;
assign T_2003_1 = T_1963;
assign T_2003_2 = T_1969;
assign T_2003_3 = T_1974;
assign T_2003_4 = T_1979;
assign T_2003_5 = T_1984;
assign T_2003_6 = T_1988;
assign T_2003_7 = 1'h1;
assign T_2016 = T_1147_2 & T_1147_1;
assign T_2017 = T_2016 & T_1147_0;
assign T_2019 = T_1891 | T_2017;
assign T_2022 = T_1147_7 & T_1147_6;
assign T_2023 = T_2022 & T_1147_5;
assign T_2025 = T_1897 | T_2023;
assign T_2028 = T_1147_11 & T_1147_10;
assign T_2029 = T_2028 & T_1147_9;
assign T_2031 = T_1903 | T_2029;
assign T_2034 = T_1147_13 & T_1147_12;
assign T_2036 = T_1909 | T_2034;
assign T_2039 = T_1147_15 & T_1147_14;
assign T_2041 = T_1914 | T_2039;
assign T_2044 = T_1147_4 & T_1147_3;
assign T_2046 = T_1919 | T_2044;
assign T_2050 = T_1924 | T_1147_8;
assign T_2065_0 = T_2019;
assign T_2065_1 = T_2025;
assign T_2065_2 = T_2031;
assign T_2065_3 = T_2036;
assign T_2065_4 = T_2041;
assign T_2065_5 = T_2046;
assign T_2065_6 = T_2050;
assign T_2065_7 = 1'h1;
assign T_2078 = T_1152_2 & T_1152_1;
assign T_2079 = T_2078 & T_1152_0;
assign T_2081 = T_1891 | T_2079;
assign T_2084 = T_1152_7 & T_1152_6;
assign T_2085 = T_2084 & T_1152_5;
assign T_2087 = T_1897 | T_2085;
assign T_2090 = T_1152_11 & T_1152_10;
assign T_2091 = T_2090 & T_1152_9;
assign T_2093 = T_1903 | T_2091;
assign T_2096 = T_1152_13 & T_1152_12;
assign T_2098 = T_1909 | T_2096;
assign T_2101 = T_1152_15 & T_1152_14;
assign T_2103 = T_1914 | T_2101;
assign T_2106 = T_1152_4 & T_1152_3;
assign T_2108 = T_1919 | T_2106;
assign T_2112 = T_1924 | T_1152_8;
assign T_2127_0 = T_2081;
assign T_2127_1 = T_2087;
assign T_2127_2 = T_2093;
assign T_2127_3 = T_2098;
assign T_2127_4 = T_2103;
assign T_2127_5 = T_2108;
assign T_2127_6 = T_2112;
assign T_2127_7 = 1'h1;
assign T_2138 = T_1026_bits_index[0];
assign T_2139 = T_1026_bits_index[1];
assign T_2140 = T_1026_bits_index[2];
assign T_2148 = {T_2140,T_2139};
assign T_2149 = {T_2148,T_2138};
assign GEN_0 = GEN_20;
assign GEN_14 = 3'h1 == T_2149 ? T_1941_1 : T_1941_0;
assign GEN_15 = 3'h2 == T_2149 ? T_1941_2 : GEN_14;
assign GEN_16 = 3'h3 == T_2149 ? T_1941_3 : GEN_15;
assign GEN_17 = 3'h4 == T_2149 ? T_1941_4 : GEN_16;
assign GEN_18 = 3'h5 == T_2149 ? T_1941_5 : GEN_17;
assign GEN_19 = 3'h6 == T_2149 ? T_1941_6 : GEN_18;
assign GEN_20 = 3'h7 == T_2149 ? T_1941_7 : GEN_19;
assign GEN_1 = GEN_27;
assign GEN_21 = 3'h1 == T_2149 ? T_2003_1 : T_2003_0;
assign GEN_22 = 3'h2 == T_2149 ? T_2003_2 : GEN_21;
assign GEN_23 = 3'h3 == T_2149 ? T_2003_3 : GEN_22;
assign GEN_24 = 3'h4 == T_2149 ? T_2003_4 : GEN_23;
assign GEN_25 = 3'h5 == T_2149 ? T_2003_5 : GEN_24;
assign GEN_26 = 3'h6 == T_2149 ? T_2003_6 : GEN_25;
assign GEN_27 = 3'h7 == T_2149 ? T_2003_7 : GEN_26;
assign T_2164 = T_1026_bits_read ? GEN_0 : GEN_1;
assign GEN_2 = GEN_34;
assign GEN_28 = 3'h1 == T_2149 ? T_2065_1 : T_2065_0;
assign GEN_29 = 3'h2 == T_2149 ? T_2065_2 : GEN_28;
assign GEN_30 = 3'h3 == T_2149 ? T_2065_3 : GEN_29;
assign GEN_31 = 3'h4 == T_2149 ? T_2065_4 : GEN_30;
assign GEN_32 = 3'h5 == T_2149 ? T_2065_5 : GEN_31;
assign GEN_33 = 3'h6 == T_2149 ? T_2065_6 : GEN_32;
assign GEN_34 = 3'h7 == T_2149 ? T_2065_7 : GEN_33;
assign GEN_3 = GEN_41;
assign GEN_35 = 3'h1 == T_2149 ? T_2127_1 : T_2127_0;
assign GEN_36 = 3'h2 == T_2149 ? T_2127_2 : GEN_35;
assign GEN_37 = 3'h3 == T_2149 ? T_2127_3 : GEN_36;
assign GEN_38 = 3'h4 == T_2149 ? T_2127_4 : GEN_37;
assign GEN_39 = 3'h5 == T_2149 ? T_2127_5 : GEN_38;
assign GEN_40 = 3'h6 == T_2149 ? T_2127_6 : GEN_39;
assign GEN_41 = 3'h7 == T_2149 ? T_2127_7 : GEN_40;
assign T_2167 = T_1026_bits_read ? GEN_2 : GEN_3;
assign T_2168 = T_1026_ready & T_2164;
assign T_2169 = T_951_valid & T_2164;
assign T_2170 = T_990_ready & T_2167;
assign T_2171 = T_1026_valid & T_2167;
assign T_2173 = 8'h1 << T_2149;
assign T_2174 = {T_1083,T_1065};
assign T_2175 = {T_1110,T_1101};
assign T_2176 = {T_2175,T_2174};
assign T_2177 = {T_1074,T_1119};
assign T_2178 = {1'h1,T_1092};
assign T_2179 = {T_2178,T_2177};
assign T_2180 = {T_2179,T_2176};
assign T_2181 = T_2173 & T_2180;
assign T_2192 = T_951_valid & T_1026_ready;
assign T_2193 = T_2192 & T_1026_bits_read;
assign T_2194 = T_2181[0];
assign T_2195 = T_2193 & T_2194;
assign T_2198 = T_1026_bits_read == 1'h0;
assign T_2199 = T_2192 & T_2198;
assign T_2201 = T_2199 & T_2194;
assign T_2202 = T_1026_valid & T_990_ready;
assign T_2203 = T_2202 & T_1026_bits_read;
assign T_2205 = T_2203 & T_2194;
assign T_2209 = T_2202 & T_2198;
assign T_2211 = T_2209 & T_2194;
assign T_2214 = T_2181[1];
assign T_2215 = T_2193 & T_2214;
assign T_2221 = T_2199 & T_2214;
assign T_2225 = T_2203 & T_2214;
assign T_2231 = T_2209 & T_2214;
assign T_2234 = T_2181[2];
assign T_2235 = T_2193 & T_2234;
assign T_2241 = T_2199 & T_2234;
assign T_2245 = T_2203 & T_2234;
assign T_2251 = T_2209 & T_2234;
assign T_2254 = T_2181[3];
assign T_2255 = T_2193 & T_2254;
assign T_2261 = T_2199 & T_2254;
assign T_2265 = T_2203 & T_2254;
assign T_2271 = T_2209 & T_2254;
assign T_2274 = T_2181[4];
assign T_2275 = T_2193 & T_2274;
assign T_2281 = T_2199 & T_2274;
assign T_2285 = T_2203 & T_2274;
assign T_2291 = T_2209 & T_2274;
assign T_2294 = T_2181[5];
assign T_2295 = T_2193 & T_2294;
assign T_2301 = T_2199 & T_2294;
assign T_2305 = T_2203 & T_2294;
assign T_2311 = T_2209 & T_2294;
assign T_2314 = T_2181[6];
assign T_2315 = T_2193 & T_2314;
assign T_2321 = T_2199 & T_2314;
assign T_2325 = T_2203 & T_2314;
assign T_2331 = T_2209 & T_2314;
assign T_2352 = T_2195 & T_1137_2;
assign T_2353 = T_2352 & T_1137_1;
assign T_2355 = T_2201 & T_1142_2;
assign T_2356 = T_2355 & T_1142_1;
assign T_2358 = T_2205 & T_1147_2;
assign T_2359 = T_2358 & T_1147_1;
assign T_2361 = T_2211 & T_1152_2;
assign T_2362 = T_2361 & T_1152_1;
assign T_2365 = T_2352 & T_1137_0;
assign T_2368 = T_2355 & T_1142_0;
assign T_2371 = T_2358 & T_1147_0;
assign T_2374 = T_2361 & T_1152_0;
assign T_2376 = T_2195 & T_1137_1;
assign T_2377 = T_2376 & T_1137_0;
assign T_2379 = T_2201 & T_1142_1;
assign T_2380 = T_2379 & T_1142_0;
assign T_2382 = T_2205 & T_1147_1;
assign T_2383 = T_2382 & T_1147_0;
assign T_2385 = T_2211 & T_1152_1;
assign T_2386 = T_2385 & T_1152_0;
assign T_2388 = T_2295 & T_1137_4;
assign T_2390 = T_2301 & T_1142_4;
assign T_2392 = T_2305 & T_1147_4;
assign T_2394 = T_2311 & T_1152_4;
assign T_2396 = T_2295 & T_1137_3;
assign T_2398 = T_2301 & T_1142_3;
assign T_2400 = T_2305 & T_1147_3;
assign T_2402 = T_2311 & T_1152_3;
assign T_2404 = T_2215 & T_1137_7;
assign T_2405 = T_2404 & T_1137_6;
assign T_2407 = T_2221 & T_1142_7;
assign T_2408 = T_2407 & T_1142_6;
assign T_2410 = T_2225 & T_1147_7;
assign T_2411 = T_2410 & T_1147_6;
assign T_2413 = T_2231 & T_1152_7;
assign T_2414 = T_2413 & T_1152_6;
assign T_2417 = T_2404 & T_1137_5;
assign T_2420 = T_2407 & T_1142_5;
assign T_2423 = T_2410 & T_1147_5;
assign T_2426 = T_2413 & T_1152_5;
assign T_2428 = T_2215 & T_1137_6;
assign T_2429 = T_2428 & T_1137_5;
assign T_2431 = T_2221 & T_1142_6;
assign T_2432 = T_2431 & T_1142_5;
assign T_2434 = T_2225 & T_1147_6;
assign T_2435 = T_2434 & T_1147_5;
assign T_2437 = T_2231 & T_1152_6;
assign T_2438 = T_2437 & T_1152_5;
assign T_2444 = T_2235 & T_1137_11;
assign T_2445 = T_2444 & T_1137_10;
assign T_2447 = T_2241 & T_1142_11;
assign T_2448 = T_2447 & T_1142_10;
assign T_2450 = T_2245 & T_1147_11;
assign T_2451 = T_2450 & T_1147_10;
assign T_2453 = T_2251 & T_1152_11;
assign T_2454 = T_2453 & T_1152_10;
assign T_2457 = T_2444 & T_1137_9;
assign T_2460 = T_2447 & T_1142_9;
assign T_2463 = T_2450 & T_1147_9;
assign T_2466 = T_2453 & T_1152_9;
assign T_2468 = T_2235 & T_1137_10;
assign T_2469 = T_2468 & T_1137_9;
assign T_2471 = T_2241 & T_1142_10;
assign T_2472 = T_2471 & T_1142_9;
assign T_2474 = T_2245 & T_1147_10;
assign T_2475 = T_2474 & T_1147_9;
assign T_2477 = T_2251 & T_1152_10;
assign T_2478 = T_2477 & T_1152_9;
assign T_2480 = T_2255 & T_1137_13;
assign T_2482 = T_2261 & T_1142_13;
assign T_2484 = T_2265 & T_1147_13;
assign T_2486 = T_2271 & T_1152_13;
assign T_2488 = T_2255 & T_1137_12;
assign T_2490 = T_2261 & T_1142_12;
assign T_2492 = T_2265 & T_1147_12;
assign T_2494 = T_2271 & T_1152_12;
assign T_2496 = T_2275 & T_1137_15;
assign T_2498 = T_2281 & T_1142_15;
assign T_2500 = T_2285 & T_1147_15;
assign T_2502 = T_2291 & T_1152_15;
assign T_2504 = T_2275 & T_1137_14;
assign T_2506 = T_2281 & T_1142_14;
assign T_2508 = T_2285 & T_1147_14;
assign T_2510 = T_2291 & T_1152_14;
assign T_2523_0 = T_1065;
assign T_2523_1 = T_1083;
assign T_2523_2 = T_1101;
assign T_2523_3 = T_1110;
assign T_2523_4 = T_1119;
assign T_2523_5 = T_1074;
assign T_2523_6 = T_1092;
assign T_2523_7 = 1'h1;
assign T_2546_0 = T_1365;
assign T_2546_1 = T_1569;
assign T_2546_2 = {{12'd0}, T_1729};
assign T_2546_3 = {{12'd0}, T_1809};
assign T_2546_4 = {{30'd0}, T_1889};
assign T_2546_5 = {{30'd0}, T_1449};
assign T_2546_6 = {{16'd0}, div};
assign T_2546_7 = 32'h0;
assign GEN_4 = GEN_48;
assign GEN_42 = 3'h1 == T_2149 ? T_2523_1 : T_2523_0;
assign GEN_43 = 3'h2 == T_2149 ? T_2523_2 : GEN_42;
assign GEN_44 = 3'h3 == T_2149 ? T_2523_3 : GEN_43;
assign GEN_45 = 3'h4 == T_2149 ? T_2523_4 : GEN_44;
assign GEN_46 = 3'h5 == T_2149 ? T_2523_5 : GEN_45;
assign GEN_47 = 3'h6 == T_2149 ? T_2523_6 : GEN_46;
assign GEN_48 = 3'h7 == T_2149 ? T_2523_7 : GEN_47;
assign GEN_5 = GEN_55;
assign GEN_49 = 3'h1 == T_2149 ? T_2546_1 : T_2546_0;
assign GEN_50 = 3'h2 == T_2149 ? T_2546_2 : GEN_49;
assign GEN_51 = 3'h3 == T_2149 ? T_2546_3 : GEN_50;
assign GEN_52 = 3'h4 == T_2149 ? T_2546_4 : GEN_51;
assign GEN_53 = 3'h5 == T_2149 ? T_2546_5 : GEN_52;
assign GEN_54 = 3'h6 == T_2149 ? T_2546_6 : GEN_53;
assign GEN_55 = 3'h7 == T_2149 ? T_2546_7 : GEN_54;
assign T_2559 = GEN_4 ? GEN_5 : 32'h0;
assign T_2560 = T_990_bits_extra[9:8];
assign T_2562 = T_990_bits_extra[7:3];
assign T_2563 = T_990_bits_extra[2:0];
assign T_2574_opcode = 3'h0;
assign T_2574_param = 2'h0;
assign T_2574_size = T_2563;
assign T_2574_source = T_2562;
assign T_2574_sink = 1'h0;
assign T_2574_addr_lo = T_2560;
assign T_2574_data = 32'h0;
assign T_2574_error = 1'h0;
always @(posedge clock or posedge reset)
if (reset) begin
div <= 16'h21e;
end else begin
if (T_1589) begin
div <= T_1590;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txen <= 1'h0;
end else begin
if (T_1629) begin
txen <= T_1390;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
rxen <= 1'h0;
end else begin
if (T_1749) begin
rxen <= T_1390;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txwm <= 4'h0;
end else begin
if (T_1709) begin
txwm <= T_1710;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
rxwm <= 4'h0;
end else begin
if (T_1789) begin
rxwm <= T_1710;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
nstop <= 1'h0;
end else begin
if (T_1669) begin
nstop <= T_1430;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ie_rxwm <= T_902_rxwm;
end else begin
if (T_1869) begin
ie_rxwm <= T_1430;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
ie_txwm <= T_902_txwm;
end else begin
if (T_1829) begin
ie_txwm <= T_1390;
end
end
endmodule |
module sky130_fd_sc_hd__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module SyncReset0 (
IN_RST_N,
OUT_RST_N
);
input IN_RST_N ;
output OUT_RST_N ;
assign OUT_RST_N = IN_RST_N ;
endmodule |
module sky130_fd_sc_hdll__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule |
module instructioncache_tb();
reg [31:0] requestedAddresses [0:5000];
reg [31:0] addressCounter;
wire [31:0] selectedAddress;
wire [15:0] memDat;
reg clk;
wire rst;
wire wt;
wire [63:0] outWire;
wire [31:0] outAddr;
wire cachewt;
assign selectedAddress=requestedAddresses[addressCounter];
assign memDat=outAddr[15:0];
assign rst=0;
assign wt=0;
instructioncache icache(memDat, selectedAddress, clk, rst, wt, outWire, outAddr, cachewt);
reg [31:0] numMisses;
reg [31:0] numHits;
reg [31:0] numCycles;
reg [31:0] numwtCycles;
initial begin
addressCounter=0;
$readmemb("memaccess.txt", requestedAddresses);
clk=0;
numMisses=0;
numCycles=0;
numwtCycles=0;
numHits=0;
end
always begin
#1 clk=~clk;
end
always@(posedge cachewt) begin
numMisses<=numMisses+1;
end
always@(posedge clk) begin
numCycles<=numCycles+1;
if(~cachewt) begin
addressCounter<=addressCounter+1;
numHits=numHits+1;
end
else begin
numwtCycles<=numwtCycles+1;
end
end
initial begin
$display("Number of misses: %d", numMisses);
$display("Number of cycles: %d", numCycles);
$display("Number of cycles stalled: %d", numwtCycles);
$dumpfile("instructioncache_tb.vcd");
$dumpvars;
end
initial
#4000 $finish;
endmodule |
module jtransmissiongatetb;
wire y;
reg a,control;
jtransmissiongate jtgate(y,control,a);
initial
begin
$display ("RESULT\ta\ty");
a = 0; control = 0; # 50; // Initial value is set
if ( y === 1'bz ) // Test for inversion
$display ("PASS \t%d\t%d",a,y);
else
$display ("FAIL \t%d\t%d",a,y);
control = 1; # 50; // Simply change the control signal
control = 0; # 50; // Simply change the control signal
control = 1; # 50; // Simply change the control signal
control = 0; # 50; // Simply change the control signal
a = 0; control = 1; # 50; // Initial value is set
if ( y === 0 ) // Test for inversion
$display ("PASS \t%d\t%d",a,y);
else
$display ("FAIL \t%d\t%d",a,y);
a = 1; control = 0; # 50; // Another value
if ( y === 1'bz ) // Test for inversion
$display ("PASS \t%d\t%d",a,y);
else
$display ("FAIL \t%d\t%d",a,y);
control = 1; # 50; // Simply change the control signal
control = 0; # 50; // Simply change the control signal
control = 1; # 50; // Simply change the control signal
control = 0; # 50; // Simply change the control signal
a = 1; control = 1; # 50; // Another value
if ( y === 1 ) // Test for inversion
$display ("PASS \t%d\t%d",a,y);
else
$display ("FAIL \t%d\t%d",a,y);
end
endmodule |
module test_mem;
// Inputs
reg clock_in;
reg [31:0] address;
reg [31:0] writeData;
reg memWrite;
reg memRead;
// Outputs
wire [31:0] readData;
// Instantiate the Unit Under Test (UUT)
dataMemory uut (
.clock_in(clock_in),
.address(address),
.writeData(writeData),
.readData(readData),
.memWrite(memWrite),
.memRead(memRead)
);
always #100 clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
address = 0;
writeData = 0;
memWrite = 0;
memRead = 0;
#185;
address = 32'b00000000000000000000000000001111;
writeData= 32'b00000000000000001111111111111111;
#250;
memWrite = 1;
#200;
memRead = 1;
memWrite= 0;
end
endmodule |
module ballmover(clk, reset, advance, ball_x, ball_y, collide, collidereset, deflect, set_side, outA, outB, wall);
parameter SCREENWIDTH = 640;
parameter SCREENHEIGHT = 480;
parameter BALLSIZE = 8;
input clk;
input reset;
input advance;
output reg [9:0] ball_x;
output reg [9:0] ball_y;
input collide;
output reg collidereset;
input [9:0] deflect;
input set_side;
output reg outA, outB, wall;
reg sgnX;
reg sgnY;
parameter speedX = 4'd8;
reg [3:0] speedY = 8;
reg [3:0] lsb_x;
reg [3:0] lsb_y;
wire[3:0] woot;
assign woot[1:0] = {(ball_x < BALLSIZE/2), (ball_x > SCREENWIDTH - BALLSIZE/2)};
assign woot[3:2] = {(ball_y < BALLSIZE/2), (ball_y > SCREENHEIGHT - BALLSIZE/2)};
always @(posedge advance or posedge reset) begin
if (reset) begin
//if (outA) {ball_x,lsb_x} = {SCREENWIDTH/3, 4'b0};
//else if (outB) {ball_x, lsb_x} = {(SCREENWIDTH-SCREENWIDTH/3), 4'b0};
//else {ball_x, lsb_x} = {SCREENWIDTH/2, 4'b0};
{ball_x, lsb_x} = {(set_side ? (SCREENWIDTH/3) : (SCREENWIDTH-SCREENWIDTH/3)), 4'b0};
{ball_y, lsb_y} = SCREENHEIGHT/2 * 16;
speedY = 1;
outA = 0;
outB = 0;
end
else begin
if (collide) begin
sgnX = !sgnX;
sgnY = ~deflect[9];
speedY = deflect[5:2];
collidereset = 1;
end
else collidereset = 0;
if (woot[1]) begin ball_x = BALLSIZE/2; sgnX = 1; outA = 1; end
if (woot[0]) begin ball_x = 640-BALLSIZE/2; sgnX = 0; outB = 1; end
if (woot[3]) begin ball_y = BALLSIZE/2; sgnY = 1; end
if (woot[2]) begin ball_y = 480-BALLSIZE/2; sgnY = 0; end
{ball_x,lsb_x} = {ball_x,lsb_x} + (sgnX ? speedX : -speedX);
{ball_y,lsb_y} = {ball_y,lsb_y} + (sgnY ? speedY : -speedY);
wall <= woot[2] | woot[3];
//outA <= woot[1];
//outB <= woot[0];
end
end
endmodule |
module system_lmb_bram_0 (
clka,
rsta,
ena,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
web,
addrb,
dinb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)
input wire rsta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [3 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [31 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [31 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *)
input wire rstb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *)
input wire [3 : 0] web;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [31 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *)
input wire [31 : 0] dinb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [31 : 0] doutb;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(1),
.C_ENABLE_32BIT_ADDRESS(1),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(2),
.C_BYTE_SIZE(8),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("system_lmb_bram_0.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(1),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(4),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_READ_WIDTH_A(32),
.C_WRITE_DEPTH_A(8192),
.C_READ_DEPTH_A(8192),
.C_ADDRA_WIDTH(32),
.C_HAS_RSTB(1),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(4),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(8192),
.C_READ_DEPTH_B(8192),
.C_ADDRB_WIDTH(32),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("8"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 19.3686 mW")
) inst (
.clka(clka),
.rsta(rsta),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(clkb),
.rstb(rstb),
.enb(enb),
.regceb(1'D0),
.web(web),
.addrb(addrb),
.dinb(dinb),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(32'B0),
.s_axi_wstrb(4'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule |
module nukv_Top_Module_v2_Comp #(
parameter META_WIDTH = 96,
parameter VALUE_WIDTH = 512,
parameter MEMORY_WIDTH = 512,
parameter KEY_WIDTH = 128,
parameter HEADER_WIDTH = 42,
parameter HASHTABLE_MEM_SIZE = 24,
parameter VALUESTORE_MEM_SIZE = 25,
parameter SUPPORT_SCANS = 1,
parameter DECOMPRESS_ENGINES = 16,
parameter CONDITION_EVALS = 4,
parameter REGEX_ENABLED = 1,
parameter IS_SIM = 0
)(
// Clock
input wire clk,
input wire rst,
// Memcached Request Input
input wire [127:0] s_axis_tdata,
input wire s_axis_tvalid,
input wire s_axis_tlast,
output wire s_axis_tready,
// Memcached Response Output
output wire [127:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast,
input wire m_axis_tready,
// HashTable DRAM Connection
// ht_rd: Pull Input, 1536b
input wire [511:0] ht_rd_data,
input wire ht_rd_empty,
input wire ht_rd_almost_empty,
output wire ht_rd_read,
// ht_rd_cmd: Push Output, 10b
output wire [63:0] ht_rd_cmd_data,
output wire ht_rd_cmd_valid,
input wire ht_rd_cmd_stall,
// ht_wr: Push Output, 1536b
output wire [511:0] ht_wr_data,
output wire ht_wr_valid,
input wire ht_wr_stall,
// ht_wr_cmd: Push Output, 10b
output wire [63:0] ht_wr_cmd_data,
output wire ht_wr_cmd_valid,
input wire ht_wr_cmd_stall,
// Update DRAM Connection
// upd_rd: Pull Input, 1536b
input wire [MEMORY_WIDTH-1:0] upd_rd_data,
input wire upd_rd_empty,
input wire upd_rd_almost_empty,
output wire upd_rd_read,
// upd_rd_cmd: Push Output, 10b
output wire [63:0] upd_rd_cmd_data,
output wire upd_rd_cmd_valid,
input wire upd_rd_cmd_stall,
// upd_wr: Push Output, 1536b
output wire [511:0] upd_wr_data,
output wire upd_wr_valid,
input wire upd_wr_stall,
// upd_wr_cmd: Push Output, 10b
output wire [63:0] upd_wr_cmd_data,
output wire upd_wr_cmd_valid,
input wire upd_wr_cmd_stall,
output wire [63:0] p_rdcmd_data,
output wire p_rdcmd_valid,
input wire p_rdcmd_ready,
input wire [512-1:0] p_rd_data,
input wire p_rd_valid,
output wire p_rd_ready,
output wire [512-1:0] p_wr_data,
output wire p_wr_valid,
input wire p_wr_ready,
output wire [63:0] p_wrcmd_data,
output wire p_wrcmd_valid,
input wire p_wrcmd_ready,
output wire [63:0] b_rdcmd_data,
output wire b_rdcmd_valid,
input wire b_rdcmd_ready,
input wire [512-1:0] b_rd_data,
input wire b_rd_valid,
output wire b_rd_ready,
output wire [512-1:0] b_wr_data,
output wire b_wr_valid,
input wire b_wr_ready,
output wire [63:0] b_wrcmd_data,
output wire b_wrcmd_valid,
input wire b_wrcmd_ready,
output wire [7:0] debug
);
wire [31:0] rdcmd_data;
wire rdcmd_valid;
wire rdcmd_stall;
wire rdcmd_ready;
wire [31:0] wrcmd_data;
wire wrcmd_valid;
wire wrcmd_stall;
wire wrcmd_ready;
wire [39:0] upd_rdcmd_data;
wire upd_rdcmd_ready;
wire [39:0] upd_wrcmd_data;
wire upd_wrcmd_ready;
wire [15:0] mreq_data;
wire mreq_valid;
wire mreq_ready;
wire [15:0] mreq_data_b;
wire mreq_valid_b;
wire mreq_ready_b;
wire [31:0] malloc_data;
wire malloc_valid;
wire malloc_failed;
wire malloc_ready;
wire [31:0] free_data;
wire [15:0] free_size;
wire free_valid;
wire free_ready;
wire free_wipe;
wire [31:0] malloc_data_b;
wire [31+1:0] malloc_data_full_b;
wire malloc_valid_b;
wire malloc_failed_b;
wire malloc_ready_b;
wire [31+16+1:0] free_data_full_b;
wire [31:0] free_data_b;
wire [15:0] free_size_b;
wire free_valid_b;
wire free_ready_b;
wire free_wipe_b;
wire [63:0] key_data;
wire key_last;
wire key_valid;
wire key_ready;
wire [META_WIDTH-1:0] meta_data;
wire meta_valid;
wire meta_ready;
wire [1+63:0] tohash_data;
wire tohash_valid;
wire tohash_ready;
wire [31:0] fromhash_data;
wire fromhash_valid;
wire fromhash_ready;
wire [63:0] hash_one_data;
wire hash_one_valid;
wire hash_one_ready;
wire[31:0] secondhash_data;
wire secondhash_valid;
wire secondhash_ready;
wire[63:0] hash_two_data;
wire hash_two_valid;
wire hash_two_ready;
reg [KEY_WIDTH-1:0] widekey_assembly;
reg [KEY_WIDTH-1:0] widekey_data;
reg widekey_valid;
wire widekey_ready;
wire [KEY_WIDTH-1:0] widekey_b_data;
wire widekey_b_valid;
wire widekey_b_ready;
wire [META_WIDTH-1:0] meta_b_data;
wire meta_b_valid;
wire meta_b_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] keywhash_data;
wire keywhash_valid;
wire keywhash_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] towrite_b_data;
wire towrite_b_valid;
wire towrite_b_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] writeout_data;
wire writeout_valid;
wire writeout_ready;
wire [KEY_WIDTH+META_WIDTH+HEADER_WIDTH-1:0] writeout_b_data;
wire writeout_b_valid;
wire writeout_b_ready;
wire [KEY_WIDTH+META_WIDTH+HEADER_WIDTH-1:0] fromset_data;
wire fromset_valid;
wire fromset_ready;
wire [KEY_WIDTH+META_WIDTH+HEADER_WIDTH-1:0] fromset_b_data;
wire fromset_b_valid;
wire fromset_b_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] towrite_data;
wire towrite_valid;
wire towrite_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] writefb_data;
wire writefb_valid;
wire writefb_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] writefb_b_data;
wire writefb_b_valid;
wire writefb_b_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] feedbwhash_data;
wire feedbwhash_valid;
wire feedbwhash_ready;
wire [VALUE_WIDTH-1:0] value_data;
wire [15:0] value_length;
wire value_last;
wire value_valid;
wire value_ready;
wire value_almost_full;
wire [VALUE_WIDTH+16+1-1:0] value_b_data;
wire [15:0] value_b_length;
wire value_b_last;
wire value_b_valid;
wire value_b_ready;
wire[VALUE_WIDTH-1:0] value_read_data;
wire value_read_valid;
wire value_read_last;
wire value_read_ready;
wire [63:0] setter_rdcmd_data;
wire setter_rdcmd_valid;
wire setter_rdcmd_ready;
wire [63:0] scan_rdcmd_data;
wire scan_rdcmd_valid;
wire scan_rdcmd_ready;
wire scan_kickoff;
wire scan_reading;
reg scan_mode_on;
reg rst_regex_after_scan;
wire [31:0] scan_readsissued;
reg [31:0] scan_readsprocessed;
wire scan_valid;
wire[31:0] scan_addr;
wire[7:0] scan_cnt;
wire scan_ready;
wire pe_cmd_ready;
wire pe_cmd_valid;
wire[15:0] pe_cmd_data;
wire[95:0] pe_cmd_meta;
wire [511:0] value_frompred_data;
wire value_frompred_ready;
wire value_frompred_valid;
wire value_frompred_drop;
wire value_frompred_last;
wire [511:0] value_frompipe_data;
wire value_frompipe_ready;
wire value_frompipe_valid;
wire value_frompipe_drop;
wire value_frompipe_last;
wire [511:0] value_frompred_b_data;
wire value_frompred_b_ready;
wire value_frompred_b_valid;
wire value_read_almostfull_int;
reg scan_pause;
wire sh_in_buf_ready;
wire sh_in_ready;
wire sh_in_valid;
wire sh_in_choice;
wire[63:0] sh_in_data;
wire hash_two_in_ready;
wire write_feedback_channel_ready;
reg[31:0] input_counter;
wire[127:0] input_buf_data;
wire input_buf_last;
wire input_buf_valid;
wire input_buf_ready;
wire[127:0] final_out_data;
wire final_out_valid;
wire final_out_ready;
wire final_out_last;
wire decision_is_valid;
wire decision_is_drop;
wire read_decision;
wire clk_faster; // 2*156MHz Clock for regex
wire clkout0;
wire fbclk;
wire fclk_locked;
reg frst = 1;
reg rst_faster = 1;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(6.400), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE(5),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
PLLE2_BASE_inst (
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(clk_faster), // 1-bit output: CLKOUT0
.CLKOUT1(), // 1-bit output: CLKOUT1
.CLKOUT2(), // 1-bit output: CLKOUT2
.CLKOUT3(), // 1-bit output: CLKOUT3
.CLKOUT4(), // 1-bit output: CLKOUT4
.CLKOUT5(), // 1-bit output: CLKOUT5
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(fbclk), // 1-bit output: Feedback clock
.LOCKED(fclk_locked), // 1-bit output: LOCK
.CLKIN1(clk), // 1-bit input: Input clock
// Control Ports: 1-bit (each) input: PLL control ports
.PWRDWN(1'b0), // 1-bit input: Power-down
.RST(1'b0), // 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(fbclk) // 1-bit input: Feedback clock
);
reg rst_regd;
always @(posedge clk) begin
rst_regd <= rst;
end
reg rst_faster0;
reg lockedx;
always @(posedge clk_faster) begin
frst <= rst_regd;
rst_faster0 <= frst;
lockedx <= ~fclk_locked;
rst_faster <= rst_faster0 | lockedx;
end
nukv_fifogen #(
.DATA_SIZE(129),
.ADDR_BITS(8)
) fifo_inputbuf (
.clk(clk),
.rst(rst),
.s_axis_tdata({s_axis_tdata,s_axis_tlast}),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.m_axis_tdata({input_buf_data,input_buf_last}),
.m_axis_tvalid(input_buf_valid),
.m_axis_tready(input_buf_ready)
);
nukv_RequestSplit #(
.SPECIAL_ARE_UPDATES(0)
)
splitter
(
.clk(clk),
.rst(rst),
.s_axis_tdata(input_buf_data),
.s_axis_tvalid(input_buf_valid),
.s_axis_tready(input_buf_ready),
.s_axis_tlast(input_buf_last),
.key_data(key_data),
.key_valid(key_valid),
.key_last(key_last),
.key_ready(key_ready),
.meta_data(meta_data),
.meta_valid(meta_valid),
.meta_ready(meta_ready),
.value_data(value_data),
.value_valid(value_valid),
.value_length(value_length),
.value_last(value_last),
.value_ready(value_ready),
.value_almost_full(value_almost_full),
.malloc_data(),
.malloc_valid(),
.malloc_ready(1'b1),
._debug()
);
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH+16+1),
.ADDR_BITS(10)
) fifo_value (
.clk(clk),
.rst(rst),
.s_axis_tdata({value_last, value_length, value_data}),
.s_axis_tvalid(value_valid),
.s_axis_tready(value_ready),
.s_axis_talmostfull(value_almost_full),
.m_axis_tdata(value_b_data),
.m_axis_tvalid(value_b_valid),
.m_axis_tready(value_b_ready)
);
assign value_b_length = value_b_data[VALUE_WIDTH +: 16];
assign value_b_last = value_b_data[VALUE_WIDTH+16];
nukv_fifogen #(
.DATA_SIZE(META_WIDTH),
.ADDR_BITS(8)
) fifo_meta_delayer (
.clk(clk),
.rst(rst),
.s_axis_tdata(meta_data),
.s_axis_tvalid(meta_valid),
.s_axis_tready(meta_ready),
.m_axis_tdata(meta_b_data),
.m_axis_tvalid(meta_b_valid),
.m_axis_tready(meta_b_ready)
);
wire hash_one_in_ready;
assign key_ready = hash_one_in_ready & widekey_ready;
kvs_ht_Hash_v2 #(
.MEMORY_WIDTH(HASHTABLE_MEM_SIZE)
) hash_number_one (
.clk(clk),
.rst(rst),
.in_valid(key_valid & widekey_ready),
.in_ready(hash_one_in_ready),
.in_data(key_data),
.in_last(key_last),
.out_valid(hash_one_valid),
.out_ready(hash_one_ready | ~hash_one_valid),
.out_data1(hash_one_data[31:0]),
.out_data2(hash_one_data[63:32])
);
always @(posedge clk) begin
if (rst) begin
widekey_data <= 0;
widekey_assembly <= 0;
widekey_valid <= 0;
end
else begin
if (widekey_valid==1 && widekey_ready==1) begin
widekey_valid <= 0;
end
if (widekey_valid==0 && widekey_ready==1 && key_valid==1 && hash_one_in_ready==1) begin
if (widekey_assembly==0) begin
widekey_assembly[63:0] <= key_data;
end else begin
widekey_assembly <= {widekey_assembly[KEY_WIDTH-64-1:0],key_data};
end
if (key_last==1) begin
widekey_data <= {widekey_assembly[KEY_WIDTH-64-1:0],key_data};
widekey_valid <= 1;
widekey_assembly <= 0;
end
end
end
end
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH),
.ADDR_BITS(6)
) fifo_widekey_delayer (
.clk(clk),
.rst(rst),
.s_axis_tdata(widekey_data),
.s_axis_tvalid(widekey_valid),
.s_axis_tready(widekey_ready),
.m_axis_tdata(widekey_b_data),
.m_axis_tvalid(widekey_b_valid),
.m_axis_tready(widekey_b_ready)
);
assign keywhash_valid = widekey_b_valid & hash_one_valid & meta_b_valid;
assign widekey_b_ready = keywhash_ready & keywhash_valid ;
assign hash_one_ready = keywhash_ready & keywhash_valid;
assign meta_b_ready = keywhash_ready & keywhash_valid;
assign keywhash_data = {hash_one_data,meta_b_data,widekey_b_data};
kvs_ht_Hash_v2 #(
.MEMORY_WIDTH(HASHTABLE_MEM_SIZE)
) hash_number_two (
.clk(clk),
.rst(rst),
.in_valid(writefb_valid & write_feedback_channel_ready),
.in_ready(hash_two_in_ready),
.in_data(writefb_data[63:0]),
.in_last(1'b1),
.out_valid(hash_two_valid),
.out_ready(hash_two_ready | ~hash_two_valid),
.out_data1(hash_two_data[31:0]),
.out_data2(hash_two_data[63:32])
);
assign feedbwhash_data = {hash_two_data, writefb_b_data[KEY_WIDTH+META_WIDTH-1:0]};
assign feedbwhash_valid = writefb_b_valid & hash_two_valid;
assign hash_two_ready = feedbwhash_ready & feedbwhash_valid;
assign writefb_b_ready = feedbwhash_ready & feedbwhash_valid;
nukv_HT_Read_v2 #(
.MEMADDR_WIDTH(HASHTABLE_MEM_SIZE)
)
readmodule
(
.clk(clk),
.rst(rst),
.input_data(keywhash_data),
.input_valid(keywhash_valid),
.input_ready(keywhash_ready),
.feedback_data(feedbwhash_data),
.feedback_valid(feedbwhash_valid),
.feedback_ready(feedbwhash_ready),
.output_data(towrite_data),
.output_valid(towrite_valid),
.output_ready(towrite_ready),
.rdcmd_data(rdcmd_data),
.rdcmd_valid(rdcmd_valid),
.rdcmd_ready(rdcmd_ready)
);
wire[VALUE_WIDTH-1:0] ht_buf_rd_data;
wire ht_buf_rd_ready;
wire ht_buf_rd_valid;
wire ht_rd_ready;
wire ht_rd_almostfull;
wire ht_rd_isvalid;
assign ht_rd_read = ~ht_rd_almostfull & ht_rd_ready & ~ht_rd_empty;
assign ht_rd_isvalid = ~ht_rd_empty & ht_rd_read;
wire[VALUE_WIDTH-1:0] ht_read_data_int;
wire ht_read_valid_int;
wire ht_read_ready_int;
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH),
.ADDR_BITS(7)
) fifo_ht_rd (
.clk(clk),
.rst(rst),
.s_axis_tdata(ht_rd_data),
.s_axis_tvalid(ht_rd_isvalid),
.s_axis_tready(ht_rd_ready),
.s_axis_talmostfull(ht_rd_almostfull),
.m_axis_tdata(ht_buf_rd_data),
.m_axis_tvalid(ht_buf_rd_valid),
.m_axis_tready(ht_buf_rd_ready)
//.m_axis_tdata(ht_read_data_int),
//.m_axis_tvalid(ht_read_valid_int),
//.m_axis_tready(ht_read_ready_int)
);
/*
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH),
.ADDR_BITS(6)
) fifo_ht_rd2 (
.clk(clk),
.rst(rst),
.s_axis_tdata(ht_read_data_int),
.s_axis_tvalid(ht_read_valid_int),
.s_axis_tready(ht_read_ready_int),
.m_axis_tdata(ht_buf_rd_data),
.m_axis_tvalid(ht_buf_rd_valid),
.m_axis_tready(ht_buf_rd_ready)
);
*/
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH+META_WIDTH+64),
.ADDR_BITS(6)
) fifo_towrite_delayer (
.clk(clk),
.rst(rst),
.s_axis_tdata(towrite_data),
.s_axis_tvalid(towrite_valid),
.s_axis_tready(towrite_ready),
.m_axis_tdata(towrite_b_data),
.m_axis_tvalid(towrite_b_valid),
.m_axis_tready(towrite_b_ready)
);
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH+META_WIDTH+64),
.ADDR_BITS(6)
) fifo_feedback_delayer (
.clk(clk),
.rst(rst),
.s_axis_tdata(writefb_data),
.s_axis_tvalid(writefb_valid & write_feedback_channel_ready),
.s_axis_tready(writefb_ready),
.m_axis_tdata(writefb_b_data),
.m_axis_tvalid(writefb_b_valid),
.m_axis_tready(writefb_b_ready)
);
assign write_feedback_channel_ready = writefb_ready & hash_two_in_ready;
nukv_HT_Write_v2 #(
.IS_SIM(IS_SIM),
.MEMADDR_WIDTH(HASHTABLE_MEM_SIZE)
)
writemodule
(
.clk(clk),
.rst(rst),
.input_data(towrite_b_data),
.input_valid(towrite_b_valid),
.input_ready(towrite_b_ready),
.feedback_data(writefb_data),
.feedback_valid(writefb_valid),
.feedback_ready(write_feedback_channel_ready),
.output_data(writeout_data),
.output_valid(writeout_valid),
.output_ready(writeout_ready),
.malloc_req_valid(mreq_valid),
.malloc_req_size (mreq_data),
.malloc_req_ready(mreq_ready),
.malloc_pointer(malloc_data_b),
.malloc_valid(malloc_valid_b),
.malloc_failed(malloc_failed_b),
.malloc_ready(malloc_ready_b),
.free_pointer(free_data),
.free_size(free_size),
.free_valid(free_valid),
.free_ready(free_ready),
.free_wipe(free_wipe),
.rd_data(ht_buf_rd_data),
.rd_valid(ht_buf_rd_valid),
.rd_ready(ht_buf_rd_ready),
.wr_data(ht_wr_data),
.wr_valid(ht_wr_valid),
.wr_ready(~ht_wr_stall),
.wrcmd_data(wrcmd_data),
.wrcmd_valid(wrcmd_valid),
.wrcmd_ready(wrcmd_ready)
);
nukv_fifogen #(
.DATA_SIZE(49),
.ADDR_BITS(6)
) fifo_freepointers (
.clk(clk),
.rst(rst),
.s_axis_tdata({free_wipe,free_data,free_size}),
.s_axis_tvalid(free_valid),
.s_axis_tready(free_ready),
.m_axis_tdata(free_data_full_b),
.m_axis_tvalid(free_valid_b),
.m_axis_tready(free_ready_b)
);
assign free_wipe_b = free_data_full_b[32+16];
assign free_data_b = free_data_full_b[32+16-1:16];
assign free_size_b = free_data_full_b[15:0];
nukv_fifogen #(
.DATA_SIZE(65),
.ADDR_BITS(6)
) fifo_mallocpointers (
.clk(clk),
.rst(rst),
.s_axis_tdata({malloc_failed,malloc_data}),
.s_axis_tvalid(malloc_valid),
.s_axis_tready(malloc_ready),
.m_axis_tdata(malloc_data_full_b),
.m_axis_tvalid(malloc_valid_b),
.m_axis_tready(malloc_ready_b)
);
assign malloc_failed_b = malloc_data_full_b[32];
assign malloc_data_b = malloc_data_full_b[31:0];
wire [31:0] p_rdcmd_data_short;
wire [31:0] p_wrcmd_data_short;
wire [31:0] b_rdcmd_data_short;
wire [7:0] b_rdcmd_cnt;
wire [31:0] b_wrcmd_data_short;
nukv_fifogen #(
.DATA_SIZE(16),
.ADDR_BITS(6)
) fifo_malloc_request (
.clk(clk),
.rst(rst),
.s_axis_tdata(mreq_data),
.s_axis_tvalid(mreq_valid),
.s_axis_tready(mreq_ready),
.m_axis_tdata(mreq_data_b),
.m_axis_tvalid(mreq_valid_b),
.m_axis_tready(mreq_ready_b)
);
/*
wire[511:0] p_rd_data_b;
wire p_rd_ready_b;
wire p_rd_valid_b;
nukv_fifogen #(
.DATA_SIZE(512),
.ADDR_BITS(6)
) fifo_pread_data (
.clk(clk),
.rst(rst),
.s_axis_tdata(p_rd_data),
.s_axis_tvalid(p_rd_valid),
.s_axis_tready(p_rd_ready),
.m_axis_tdata(p_rd_data_b),
.m_axis_tvalid(p_rd_valid_b),
.m_axis_tready(p_rd_ready_b)
);*/
/*
wire[511:0] b_rd_data_b;
wire b_rd_ready_b;
wire b_rd_valid_b;
nukv_fifogen #(
.DATA_SIZE(512),
.ADDR_BITS(6)
) fifo_bread_data (
.clk(clk),
.rst(rst),
.s_axis_tdata(b_rd_data),
.s_axis_tvalid(b_rd_valid),
.s_axis_tready(b_rd_ready),
.m_axis_tdata(b_rd_data_b),
.m_axis_tvalid(b_rd_valid_b),
.m_axis_tready(b_rd_ready_b)
);*/
wire malloc_error_valid;
wire[7:0] malloc_error_state;
nukv_Malloc #(
.IS_SIM(IS_SIM),
.SUPPORT_SCANS(SUPPORT_SCANS),
.MAX_MEMORY_SIZE(VALUESTORE_MEM_SIZE)
)
mallocmodule
(
.clk(clk),
.rst(rst),
.req_data(mreq_data_b),
.req_valid(mreq_valid_b),
.req_ready(mreq_ready_b),
.malloc_pointer(malloc_data),
.malloc_valid(malloc_valid),
.malloc_failed(malloc_failed),
.malloc_ready(malloc_ready),
.free_pointer(free_data_b),
.free_size(free_size_b),
.free_valid(free_valid_b),
.free_ready(free_ready_b),
.free_wipe(free_wipe_b),
.p_rdcmd_data(p_rdcmd_data_short),
.p_rdcmd_valid(p_rdcmd_valid),
.p_rdcmd_ready(p_rdcmd_ready),
.p_rd_data(p_rd_data),
.p_rd_valid(p_rd_valid),
.p_rd_ready(p_rd_ready),
.p_wr_data(p_wr_data),
.p_wr_valid(p_wr_valid),
.p_wr_ready(p_wr_ready),
.p_wrcmd_data(p_wrcmd_data_short),
.p_wrcmd_valid(p_wrcmd_valid),
.p_wrcmd_ready(p_wrcmd_ready),
.b_rdcmd_data(b_rdcmd_data_short),
.b_rdcmd_cnt(b_rdcmd_cnt),
.b_rdcmd_valid(b_rdcmd_valid),
.b_rdcmd_ready(b_rdcmd_ready),
.b_rd_data(b_rd_data),
.b_rd_valid(b_rd_valid),
.b_rd_ready(b_rd_ready),
.b_wr_data(b_wr_data),
.b_wr_valid(b_wr_valid),
.b_wr_ready(b_wr_ready),
.b_wrcmd_data(b_wrcmd_data_short),
.b_wrcmd_valid(b_wrcmd_valid),
.b_wrcmd_ready(b_wrcmd_ready),
.scan_start(scan_kickoff),
.is_scanning(scan_reading),
.scan_numlines(scan_readsissued),
.scan_valid(scan_valid),
.scan_addr(scan_addr),
.scan_cnt(scan_cnt),
.scan_ready(scan_ready),
.scan_pause(SUPPORT_SCANS==1 ? scan_pause : 0),
.error_memory(malloc_error_valid),
.error_state(malloc_error_state)
);
always @(posedge clk) begin
if (SUPPORT_SCANS==1) begin
if (rst) begin
scan_mode_on <= 0;
scan_readsprocessed <= 0;
rst_regex_after_scan <= 0;
end
else begin
rst_regex_after_scan <= 0;
if (scan_mode_on==0 && scan_reading==1) begin
scan_mode_on <= 1;
scan_readsprocessed <= 0;
end
// this only works if all values are <64B!!!
if (scan_mode_on==1 && decision_is_valid==1 && read_decision==1) begin
scan_readsprocessed <= scan_readsprocessed +1;
end
if (scan_mode_on==1 && scan_reading==0 && scan_readsprocessed==scan_readsissued) begin
scan_mode_on <= 0;
rst_regex_after_scan <= 1;
end
end
end else begin
scan_mode_on <= 0;
rst_regex_after_scan <= 0;
end
end
assign scan_ready = scan_rdcmd_ready;
assign scan_rdcmd_valid = scan_valid;
assign scan_rdcmd_data = {scan_cnt, scan_addr};
assign b_rdcmd_data ={24'b000000000000000100000001, b_rdcmd_cnt[7:0], 4'b0000, b_rdcmd_data_short[27:0]};
assign b_wrcmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, b_wrcmd_data_short[27:0]};
assign p_rdcmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, p_rdcmd_data_short[27:0]};
assign p_wrcmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, p_wrcmd_data_short[27:0]};
assign ht_rd_cmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, 4'b0000, rdcmd_data[23:0]};
assign ht_rd_cmd_valid = rdcmd_valid;
assign rdcmd_ready = ~ht_rd_cmd_stall;
assign ht_wr_cmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, 4'b0000, wrcmd_data[23:0]};
assign ht_wr_cmd_valid = wrcmd_valid;
assign wrcmd_ready = ~ht_wr_cmd_stall;
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH+META_WIDTH+42),
.ADDR_BITS(5)
) fifo_write_to_set (
.clk(clk),
.rst(rst),
.s_axis_tdata({writeout_data[KEY_WIDTH +: META_WIDTH], writeout_data[KEY_WIDTH+META_WIDTH +: 42], writeout_data[KEY_WIDTH-1:0]}),
.s_axis_tvalid(writeout_valid),
.s_axis_tready(writeout_ready),
.m_axis_tdata(writeout_b_data),
.m_axis_tvalid(writeout_b_valid),
.m_axis_tready(writeout_b_ready)
);
wire predconf_valid;
wire predconf_scan;
wire predconf_ready;
wire[96+511:0] predconf_data;
wire predconf_b_valid;
wire predconf_b_scan;
wire predconf_b_ready;
wire[96+511:0] predconf_b_data;
wire[1+511+96:0] predconf_b_fulldata;
assign setter_rdcmd_ready = (scan_mode_on == 1 && SUPPORT_SCANS==1) ? 0 : upd_rdcmd_ready;
assign scan_rdcmd_ready = (scan_mode_on == 1 && SUPPORT_SCANS==1) ? upd_rdcmd_ready : 0;
assign upd_rdcmd_data = (scan_mode_on == 1 && SUPPORT_SCANS==1) ? scan_rdcmd_data : setter_rdcmd_data;
assign upd_rd_cmd_valid = (scan_mode_on == 1 && SUPPORT_SCANS==1) ? scan_rdcmd_valid : setter_rdcmd_valid;
nukv_Value_Set #(.SUPPORT_SCANS(SUPPORT_SCANS))
valuesetter
(
.clk(clk),
.rst(rst),
.input_data(writeout_b_data),
.input_valid(writeout_b_valid),
.input_ready(writeout_b_ready),
.value_data(value_b_data[VALUE_WIDTH-1:0]),
.value_valid(value_b_valid),
.value_ready(value_b_ready),
.output_data(fromset_data),
.output_valid(fromset_valid),
.output_ready(fromset_ready),
.wrcmd_data(upd_wrcmd_data),
.wrcmd_valid(upd_wr_cmd_valid),
.wrcmd_ready(upd_wrcmd_ready),
.wr_data(upd_wr_data),
.wr_valid(upd_wr_valid),
.wr_ready(~upd_wr_stall),
.rdcmd_data(setter_rdcmd_data) ,
.rdcmd_valid(setter_rdcmd_valid),
.rdcmd_ready(setter_rdcmd_ready),
.pe_valid(predconf_valid),
.pe_scan(predconf_scan),
.pe_ready(predconf_ready),
.pe_data(predconf_data),
.scan_start(scan_kickoff),
.scan_mode(scan_mode_on)
);
wire[VALUE_WIDTH-1:0] value_read_data_int;
wire value_read_valid_int;
wire value_read_ready_int;
wire value_read_almostfull_int2;
always @(posedge clk) begin
if (rst) begin
scan_pause <= 0;
end
else begin
if (scan_readsissued>0 && scan_readsissued-scan_readsprocessed> (IS_SIM==1 ? 64 : 200)) begin
scan_pause <= 1;
end else begin
scan_pause <= 0;
end
end
end
wire[511:0] value_read_data_buf;
wire value_read_ready_buf;
wire value_read_valid_buf;
wire upd_ready;
assign upd_rd_read = upd_ready & ~upd_rd_empty;
wire toget_ready;
assign fromset_ready = (scan_mode_on==0 || SUPPORT_SCANS==0) ? toget_ready : 0;
assign pe_cmd_ready = (scan_mode_on==0 || SUPPORT_SCANS==0) ? 0 : toget_ready;
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH+META_WIDTH+HEADER_WIDTH),
.ADDR_BITS(7)
) fifo_output_from_set (
.clk(clk),
.rst(rst),
.s_axis_tdata((scan_mode_on==0 || SUPPORT_SCANS==0) ? fromset_data : {8'b00001111, pe_cmd_meta[0 +: 88], 1'b0, pe_cmd_data[9:0], 159'd0}),
.s_axis_tvalid((scan_mode_on==0 || SUPPORT_SCANS==0) ? fromset_valid : pe_cmd_valid),
.s_axis_tready(toget_ready),
.m_axis_tdata(fromset_b_data),
.m_axis_tvalid(fromset_b_valid),
.m_axis_tready(fromset_b_ready)
);
wire predconf_regex_ready;
wire predconf_pred0_ready;
wire predconf_predother_ready;
assign predconf_b_ready = predconf_regex_ready & predconf_predother_ready;
nukv_fifogen #(
.DATA_SIZE(512+96+1),
.ADDR_BITS(7)
) fifo_output_conf_pe (
.clk(clk),
.rst(rst),
.s_axis_tdata({predconf_data, predconf_scan}),
.s_axis_tvalid(predconf_valid),
.s_axis_tready(predconf_ready),
.m_axis_tdata(predconf_b_fulldata),
.m_axis_tvalid(predconf_b_valid),
.m_axis_tready(predconf_b_ready)
);
assign predconf_b_scan = predconf_b_fulldata[0];
assign predconf_b_data = predconf_b_fulldata[1 +: 512+96];
wire pred_eval_error;
// begin DECOMP
wire[511:0] decompress_in_data;
wire[DECOMPRESS_ENGINES-1:0] decompress_in_valid;
wire[DECOMPRESS_ENGINES-1:0] decompress_in_ready;
wire[511:0] decompress_interm_data [0:DECOMPRESS_ENGINES-1];
wire[DECOMPRESS_ENGINES-1:0] decompress_interm_valid;
wire[DECOMPRESS_ENGINES-1:0] decompress_interm_ready;
wire[511:0] decompress_out_data[0:DECOMPRESS_ENGINES-1];
wire[DECOMPRESS_ENGINES-1:0] decompress_out_valid;
wire[DECOMPRESS_ENGINES-1:0] decompress_out_ready;
wire[DECOMPRESS_ENGINES-1:0] decompress_out_last;
wire[511:0] decompress_comb_data[0:DECOMPRESS_ENGINES-1];
wire[DECOMPRESS_ENGINES-1:0] decompress_comb_valid;
wire[DECOMPRESS_ENGINES-1:0] decompress_comb_last;
reg[5:0] decompress_in_rrid;
reg[5:0] decompress_out_rrid;
generate
if (DECOMPRESS_ENGINES>0) begin
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH),
.ADDR_BITS(9)
) fifo_valuedatafrommemory (
.clk(clk),
.rst(rst),
.s_axis_tdata(upd_rd_data),
.s_axis_tvalid(~upd_rd_empty),
.s_axis_tready(upd_ready),
.s_axis_talmostfull(value_read_almostfull_int2),
.m_axis_tdata(value_read_data_buf),
.m_axis_tvalid(value_read_valid_buf),
.m_axis_tready(value_read_ready_buf)
);
assign value_read_ready_buf = decompress_in_ready[decompress_in_rrid];
assign decompress_in_data = value_read_data_buf;
always @(posedge clk) begin
if (rst) begin
decompress_in_rrid <=0;
end
else begin
if (value_read_valid_buf==1 && value_read_ready_buf==1) begin
decompress_in_rrid <= decompress_in_rrid+1;
if (decompress_in_rrid==DECOMPRESS_ENGINES-1) begin
decompress_in_rrid <= 0;
end
end
end
end
genvar xx;
for (xx=0; xx<DECOMPRESS_ENGINES; xx=xx+1)
begin : decompression
assign decompress_in_valid[xx +: 1] = xx==decompress_in_rrid ? value_read_valid_buf : 0;
fifo_generator_512_shallow_async fifo_values (
.s_aclk(clk),
.m_aclk(clk_faster),
.s_aresetn(~rst),
.s_axis_tdata(decompress_in_data),
.s_axis_tvalid(decompress_in_valid[xx +: 1]),
.s_axis_tready(decompress_in_ready[xx +: 1]),
.m_axis_tdata(decompress_interm_data[xx]),
.m_axis_tvalid(decompress_interm_valid[xx +: 1]),
.m_axis_tready(decompress_interm_ready[xx +: 1])
);
nukv_Decompress decompress_unit (
.clk(clk_faster),
.rst(rst_faster),
.input_valid(decompress_interm_valid[xx +: 1]),
.input_ready(decompress_interm_ready[xx +: 1]),
.input_data(decompress_interm_data[xx]),
.input_last(1),
.output_valid(decompress_out_valid[xx +: 1]),
.output_ready(decompress_out_ready[xx +: 1]),
.output_data(decompress_out_data[xx]),
.output_last(decompress_out_last[xx +: 1])
);
fifo_generator_512_shallow_async fifo_decompressed_values (
.s_aclk(clk_faster),
.m_aclk(clk),
.s_aresetn(~rst_faster),
.s_axis_tdata(decompress_out_data[xx]),
.s_axis_tvalid(decompress_out_valid[xx +: 1]),
.s_axis_tready(decompress_out_ready[xx +: 1]),
.s_axis_tuser(decompress_out_last[xx +: 1]),
.m_axis_tdata(decompress_comb_data[xx]),
.m_axis_tvalid(decompress_comb_valid[xx +: 1]),
.m_axis_tready(xx==decompress_out_rrid ? value_read_ready : 0),
.m_axis_tuser(decompress_comb_last[xx +: 1 ])
);
end
always @(posedge clk) begin
if (rst) begin
decompress_out_rrid <=0;
end
else begin
if (value_read_ready==1 && value_read_valid==1 && value_read_last==1) begin
decompress_out_rrid <= decompress_out_rrid+1;
if (decompress_out_rrid==DECOMPRESS_ENGINES-1) begin
decompress_out_rrid <= 0;
end
end
end
end
assign value_read_data = decompress_comb_data[decompress_out_rrid];
assign value_read_valid = decompress_comb_valid[decompress_out_rrid +: 1];
assign value_read_last = decompress_comb_last[decompress_out_rrid +: 1];
end else begin
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH),
.ADDR_BITS(9)
) fifo_valuedatafrommemory (
.clk(clk),
.rst(rst),
.s_axis_tdata(upd_rd_data),
.s_axis_tvalid(~upd_rd_empty),
.s_axis_tready(upd_ready),
.s_axis_talmostfull(value_read_almostfull_int2),
.m_axis_tdata(value_read_data_buf),
.m_axis_tvalid(value_read_valid_buf),
.m_axis_tready(value_read_ready_buf)
);
assign value_read_ready_buf = value_read_ready;
assign value_read_valid = value_read_valid_buf;
assign value_read_data = value_read_data_buf;
assign value_read_last = 0;
end
endgenerate
//end DECOMP
wire [513:0] regexin_data;
wire regexin_valid;
wire regexin_ready;
wire regexin_prebuf_ready;
wire[511:0] regexconf_data;
wire regexconf_valid;
wire regexconf_ready;
wire regexout_data;
wire regexout_valid;
wire regexout_ready;
wire buffer_violation;
wire before_get_ready;
wire before_get_almfull;
wire condin_ready;
wire cond_valid;
wire cond_ready;
wire cond_drop;
assign buffer_violation = ~cond_ready & before_get_ready;
nukv_Predicate_Eval_Pipeline_v2
#(.SUPPORT_SCANS(SUPPORT_SCANS),
.PIPE_DEPTH(CONDITION_EVALS)
) pred_eval_pipe (
.clk(clk),
.rst(rst),
.pred_data({predconf_b_data[META_WIDTH+MEMORY_WIDTH-1 : META_WIDTH], predconf_b_data[META_WIDTH-1:0]}),
.pred_valid(predconf_b_valid & predconf_b_ready),
.pred_ready(predconf_predother_ready),
.pred_scan((SUPPORT_SCANS==1) ? predconf_b_scan : 0),
.value_data(value_read_data),
.value_last(value_read_last),
.value_drop(0),
.value_valid(value_read_valid),
.value_ready(value_read_ready),
.output_valid(value_frompred_valid),
.output_ready(value_frompred_ready),
.output_data(value_frompred_data),
.output_last(value_frompred_last),
.output_drop(value_frompred_drop),
.scan_on_outside(scan_mode_on),
.cmd_valid(pe_cmd_valid),
.cmd_length(pe_cmd_data),
.cmd_meta(pe_cmd_meta),
.cmd_ready(pe_cmd_ready),
.error_input(pred_eval_error)
);
// REGEX ---------------------------------------------------
wire toregex_ready;
assign value_frompred_ready = toregex_ready & condin_ready & before_get_ready;
fifo_generator_512_shallow_sync
//#(
// .DATA_SIZE(512+1),
// .ADDR_BITS(7)
//)
fifo_toward_regex (
.s_aclk(clk),
.s_aresetn(~rst),
.s_axis_tdata(value_frompred_data),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready),
.s_axis_tready(toregex_ready),
.s_axis_tuser(value_frompred_drop),
.s_axis_tlast(value_frompred_last),
.m_axis_tdata(regexin_data[511:0]),
.m_axis_tvalid(regexin_valid),
.m_axis_tready(regexin_ready),
.m_axis_tuser(regexin_data[513]),
.m_axis_tlast(regexin_data[512])
);
assign regexconf_data[512-48*CONDITION_EVALS-1:0] = predconf_b_data[META_WIDTH+48*CONDITION_EVALS +: (512-48*CONDITION_EVALS)];
assign regexconf_data[511] = scan_mode_on;
assign regexconf_valid = predconf_b_valid & predconf_b_ready;
assign predconf_regex_ready = regexconf_ready;
wire [511:0] regexconf_buf_data;
wire regexconf_buf_valid;
wire regexconf_buf_ready;
//nukv_fifogen_async_clock #(
// .DATA_SIZE(512),
// .ADDR_BITS(7)
//)
fifo_generator_512_shallow_sync
fifo_config_regex (
.s_aclk(clk),
.s_aresetn(~rst),
.s_axis_tdata(regexconf_data),
.s_axis_tvalid(regexconf_valid),
.s_axis_tready(regexconf_ready),
.s_axis_tlast(1'b1),
.m_axis_tdata(regexconf_buf_data),
.m_axis_tvalid(regexconf_buf_valid),
.m_axis_tready(regexconf_buf_ready),
.m_axis_tlast()
);
wire regexout_int_data;
wire regexout_int_valid;
wire regexout_int_ready;
kvs_vs_RegexTop_FastClockInside regex_module (
.clk(clk),
.rst(rst | rst_regex_after_scan),
.fast_clk(clk_faster),
.fast_rst(rst_faster),
.input_data(regexin_data[511:0]),
.input_valid(regexin_valid),
.input_last(regexin_data[512]),
.input_ready(regexin_ready),
.config_data(regexconf_buf_data),
.config_valid(regexconf_buf_valid),
.config_ready(regexconf_buf_ready),
.found_loc(regexout_int_data),
.found_valid(regexout_int_valid),
.found_ready(regexout_int_ready)
);
//nukv_fifogen_async_clock #(
//.DATA_SIZE(1),
// .ADDR_BITS(8)
//)
fifo_generator_1byte_sync
fifo_decision_from_regex (
.s_aclk(clk),
.s_aresetn(~rst),
.s_axis_tdata(regexout_int_data),
.s_axis_tvalid(regexout_int_valid),
.s_axis_tready(regexout_int_ready),
.m_axis_tdata(regexout_data),
.m_axis_tvalid(regexout_valid),
.m_axis_tready(regexout_ready)
);
nukv_fifogen #(
.DATA_SIZE(MEMORY_WIDTH),
.ADDR_BITS(8)
) fifo_value_from_pe (
.clk(clk),
.rst(rst),
.s_axis_tdata(value_frompred_data),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready),
.s_axis_tready(before_get_ready),
.m_axis_tdata(value_frompred_b_data),
.m_axis_tvalid(value_frompred_b_valid),
.m_axis_tready(value_frompred_b_ready)
);
nukv_fifogen #(
.DATA_SIZE(1),
.ADDR_BITS(8)
) fifo_decision_from_pe (
.clk(clk),
.rst(rst),
.s_axis_tdata(value_frompred_drop),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready & value_frompred_last ),
.s_axis_tready(condin_ready),
.m_axis_tdata(cond_drop),
.m_axis_tvalid(cond_valid),
.m_axis_tready(cond_ready)
);
assign decision_is_valid = cond_valid & regexout_valid;
assign decision_is_drop = cond_drop | ~regexout_data;
assign cond_ready = read_decision & decision_is_valid;
assign regexout_ready = read_decision & decision_is_valid;
nukv_Value_Get #(.SUPPORT_SCANS(SUPPORT_SCANS))
valuegetter
(
.clk(clk),
.rst(rst),
.input_data(fromset_b_data),
.input_valid(fromset_b_valid),
.input_ready(fromset_b_ready),
.value_data(value_frompred_b_data),
.value_valid(value_frompred_b_valid),
.value_ready(value_frompred_b_ready),
.cond_valid(decision_is_valid),
.cond_drop(decision_is_drop),
.cond_ready(read_decision),
.output_data(final_out_data[127:0]),
.output_valid(final_out_valid),
.output_ready(final_out_ready),
.output_last(final_out_last),
.scan_mode(scan_mode_on)
);
assign m_axis_tvalid = (final_out_data[64+:16]==16'h7fff) ? 0 : final_out_valid;
assign m_axis_tlast = final_out_last;
assign m_axis_tdata = final_out_data;
assign final_out_ready = m_axis_tready;
assign upd_rd_cmd_data ={24'b000000000000000100000001, upd_rdcmd_data[39:32], 4'b0000, 3'b001, upd_rdcmd_data[24:0]};
assign upd_rdcmd_ready = ~upd_rd_cmd_stall;
assign upd_wr_cmd_data ={24'b000000000000000100000001, upd_wrcmd_data[39:32], 4'b0000, 3'b001, upd_wrcmd_data[24:0]};
assign upd_wrcmd_ready = ~upd_wr_cmd_stall;
reg[31:0] rdaddr_aux;
reg[191:0] data_aux;
// -------------------------------------------------
/* */
wire [35:0] control0, control1;
reg [255:0] data;
reg [255:0] debug_r;
reg [255:0] debug_r2;
reg [255:0] debug_r3;
wire [63:0] vio_cmd;
reg [63:0] vio_cmd_r;
reg old_scan_mode;
reg [31:0] condcnt;
reg [31:0] regxcnt;
reg [31:0] diffrescnt;
always @(posedge clk) begin
if (rst==1) begin
input_counter<=0;
old_scan_mode <= 0;
condcnt <= 0;
regxcnt <= 0;
end else begin
//if(debug_r[2:0]==3'b111) begin
input_counter<= input_counter+1;
//end
if (value_frompred_valid==1 && value_frompred_ready==1 && value_frompred_last==1 && condin_ready==1) begin
condcnt <= condcnt +1;
end
if (regexout_int_valid==1 && regexout_int_ready==1) begin
regxcnt <= regxcnt+1;
end
end
old_scan_mode <= scan_mode_on;
if (regxcnt > condcnt) begin
diffrescnt <= regxcnt - condcnt;
end
else begin
diffrescnt <= condcnt - regxcnt;
end
//data_aux <= {regexin_data[63:0],diffrescnt};
data_aux <= {value_read_data[0 +: 64], s_axis_tdata[63:0]};
debug_r[0] <= s_axis_tvalid ;
debug_r[1] <= s_axis_tready;
debug_r[2] <= s_axis_tlast;
debug_r[3] <= key_valid ;
debug_r[4] <= key_ready;
debug_r[5] <= meta_valid;
debug_r[6] <= meta_ready;
debug_r[7] <= value_valid;
debug_r[8] <= value_ready;
debug_r[9] <= mreq_valid;
debug_r[10] <= mreq_ready;
debug_r[11] <= keywhash_valid;
debug_r[12] <= keywhash_ready;
debug_r[13] <= feedbwhash_valid;
debug_r[14] <= feedbwhash_ready;
debug_r[15] <= towrite_valid;
debug_r[16] <= towrite_ready;
debug_r[17] <= rdcmd_valid;
debug_r[18] <= rdcmd_ready;
debug_r[19] <= writeout_valid;
debug_r[20] <= writeout_ready;
debug_r[21] <= p_rd_valid;
debug_r[22] <= p_rd_ready;
//debug_r[23] <= (b_rd_data==0 ? 0 : 1);
debug_r[24] <= free_valid;
debug_r[25] <= free_ready;
debug_r[26] <= ht_buf_rd_valid;
debug_r[27] <= ht_buf_rd_ready;
debug_r[28] <= ht_wr_valid;
debug_r[29] <= ht_wr_stall;
debug_r[30] <= wrcmd_valid;
debug_r[31] <= wrcmd_ready;
debug_r[32] <= writeout_b_valid;
debug_r[33] <= writeout_b_ready;
debug_r[34] <= value_b_valid;
debug_r[35] <= value_b_ready;
debug_r[36] <= upd_wr_cmd_valid;
debug_r[37] <= ~upd_wr_cmd_stall;
debug_r[38] <= b_rdcmd_valid;
debug_r[39] <= b_rdcmd_ready;
debug_r[40] <= b_rd_valid;
debug_r[41] <= b_rd_ready;
debug_r[42] <= upd_rd_cmd_valid;
debug_r[43] <= ~upd_rd_cmd_stall;
debug_r[44] <= fromset_b_valid;
debug_r[45] <= fromset_b_ready;
debug_r[46] <= value_read_valid;
debug_r[47] <= value_read_ready;
debug_r[48] <= m_axis_tvalid;
debug_r[49] <= m_axis_tlast;
debug_r[50] <= m_axis_tready;
debug_r[51] <= (old_scan_mode != scan_mode_on) ? 1'b1: 1'b0;
debug_r[52] <= scan_reading;
debug_r[53] <= scan_pause;
debug_r[54] <= value_read_almostfull_int;
debug_r[56] <= pred_eval_error;
//debug_r[57] <= malloc_error_valid;
//debug_r[58] <= malloc_valid;
//debug_r[64 +: 32] <= {malloc_error_state};
// 71 70 69 68 67 66 65 64
debug_r[64 +: 8] <= {value_frompred_b_ready,value_frompred_b_valid,regexout_ready, regexout_valid, cond_ready, cond_valid, regexin_ready, regexin_valid};
//debug_r[96 +: 16] <= diffrescnt[15:0];
debug_r[128 +: 128] <= data_aux;
debug_r2 <= debug_r;
debug_r3 <= debug_r2;
data <= debug_r3;
end
icon icon_inst(
.CONTROL0(control0),
.CONTROL1(control1)
);
vio vio_inst(
.CONTROL(control1),
.CLK(clk),
.SYNC_OUT(vio_cmd)
// .SYNC_OUT()
);
ila_256 ila_256_inst(
.CONTROL(control0),
.CLK(clk),
.TRIG0(data)
);
/**/
endmodule |
module sky130_fd_sc_lp__sdfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__sdfxbp_1 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule |
module de4_230
(
input GCLKIN,
output GCLKOUT_FPGA,
input OSC_50_BANK2,
input OSC_50_BANK3,
input OSC_50_BANK4,
input OSC_50_BANK5,
input OSC_50_BANK6,
input OSC_50_BANK7,
input PLL_CLKIN_p,
output [7:0] LED,
input [3:0] BUTTON,
input CPU_RESET_n, // CPU Reset Push Button
inout EXT_IO,
input [7:0] SW, // DIP Switches
input [3:0] SLIDE_SW, // Slide switches
output [6:0] SEG0_D,
output SEG0_DP,
output [6:0] SEG1_D,
output SEG1_DP
);
// wires & inputs
wire clk;
wire clkIn = OSC_50_BANK2;
wire rst_n = CPU_RESET_n;
wire clkEnable = SW [7] | ~BUTTON[0];
wire [ 3:0 ] clkDevide = SW [3:0];
wire [ 4:0 ] regAddr = { ~BUTTON[1], SLIDE_SW };
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
//outputs
assign LED[0] = clk;
assign LED[7:1] = regData[6:0];
wire [ 31:0 ] h7segment = regData;
assign SEG0_DP = 1'b1;
assign SEG1_DP = 1'b1;
sm_hex_display digit_1 ( h7segment [ 7: 4] , SEG1_D );
sm_hex_display digit_0 ( h7segment [ 3: 0] , SEG0_D );
endmodule |
module sky130_fd_sc_hd__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule |
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__ebufn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule |
module x;
always @(/*AUTOSENSE*/arb_select_f or octet_idx) begin
octet_flag[0] = |arb_select_f[ 7: 0];
octet_flag[1] = |arb_select_f[15: 8];
octet_flag[2] = |arb_select_f[23:16];
octet_flag[3] = |arb_select_f[31:24];
octet_flag[4] = |arb_select_f[39:32];
octet_flag[5] = |arb_select_f[47:40];
octet_flag[6] = |arb_select_f[55:48];
octet_flag[7] = |arb_select_f[63:56];
octet_available = |octet_flag;
shifted8_64 = barrel_shifter(octet_flag, octet_idx[5:3]);
end // always @ (arb_select_f)
endmodule |
module sky130_fd_sc_ls__a31oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__a31oi_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule |
module impl_axi_test();
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
localparam tries = 10;
localparam sword = 32;
localparam masters = 2;
localparam slaves = 7;
localparam impl = 0;
localparam syncing = 0;
localparam max_wait = 1000000;
localparam SIZE_FIRMWARE = 4194304;
localparam GPIO_PINS = 32; // How many pins exists?
localparam GPIO_PWM = 32; // How many of the above support PWM?
localparam GPIO_IRQ = 8; // How many of the above support IRQ?
localparam GPIO_TWO_PRESCALER = 1; // Independent Prescaler PWM enabled?
localparam PWM_PRESCALER_BITS = 16; // How many bits is the prescaler? (Main frequency divisor)
localparam PWM_BITS = 16; // How many bits are the pwms?
localparam UART_RX_BUFFER_BITS = 10; // How many buffer?
// Autogen localparams
reg CLK = 1'b0;
reg SCLK = 1'b0;
reg RST;
reg DATA;
wire DOUT;
reg CEB;
wire [11:0] DAC_interface_AXI_DATA;
// DDR2 interface
wire ROM_CS;
wire ROM_SDI;
wire ROM_SDO;
wire ROM_WP;
wire ROM_HLD;
wire ROM_SCK;
// DDR2 interface
wire [12:0] ddr2_addr;
wire [2:0] ddr2_ba;
wire ddr2_ras_n;
wire ddr2_cas_n;
wire ddr2_we_n;
wire [0:0] ddr2_ck_p;
wire [0:0] ddr2_ck_n;
wire [0:0] ddr2_cke;
wire [0:0] ddr2_cs_n;
wire [1:0] ddr2_dm;
wire [0:0] ddr2_odt;
wire [15:0] ddr2_dq;
wire [1:0] ddr2_dqs_p;
wire [1:0] ddr2_dqs_n;
// GPIO
wire [GPIO_PINS-1:0] GPIO_pin;
reg [GPIO_PINS-1:0] GPIO_pin_act;
reg [GPIO_PINS-1:0] GPIO_pins;
// 7-seg
wire [7:0] SEGMENT_AN;
wire [7:0] SEGMENT_SEG;
// SPI slave
wire spi_axi_slave_CEB;
wire spi_axi_slave_SCLK;
wire spi_axi_slave_DATA;
localparam numbit_instr = 2; // Nop (00), Read(01), Write(10)
localparam numbit_address = sword;
localparam numbit_handshake = numbit_instr+numbit_address+sword;
reg [numbit_handshake-1:0] handshake;
reg [sword-1:0] result;
// Data per capturing
reg [sword-1:0] cap;
reg stat;
reg stats;
reg is_o, is_ok;
reg waiting_ok;
integer waiting;
integer fd1, tmp1, ifstop;
integer PERIOD = 5000 ;
integer SPERIOD = 20000 ;
integer i, j, error, l;
// Device under test
impl_axi inst_impl_axi(
// General
.CLK(CLK),
.RST(RST),
.spi_axi_master_CEB(CEB),
.spi_axi_master_SCLK(SCLK),
.spi_axi_master_DATA(DATA),
.spi_axi_master_DOUT(DOUT),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_addr (ddr2_addr[12:0]),
.ddr2_ba (ddr2_ba[2:0]),
.ddr2_ck_n (ddr2_ck_n[0:0]),
.ddr2_ck_p (ddr2_ck_p[0:0]),
.ddr2_cke (ddr2_cke[0:0]),
.ddr2_cs_n (ddr2_cs_n[0:0]),
.ddr2_dm (ddr2_dm[1:0]),
.ddr2_odt (ddr2_odt[0:0]),
.ddr2_dq (ddr2_dq[15:0]),
.ddr2_dqs_n (ddr2_dqs_n[1:0]),
.ddr2_dqs_p (ddr2_dqs_p[1:0]),
.DAC_data (DAC_interface_AXI_DATA),
.VP(0),
.VN(1),
.GPIO_pin(GPIO_pin),
.SEGMENT_AN(SEGMENT_AN),
.SEGMENT_SEG(SEGMENT_SEG),
.spi_axi_slave_CEB(spi_axi_slave_CEB),
.spi_axi_slave_SCLK(spi_axi_slave_SCLK),
.spi_axi_slave_DATA(spi_axi_slave_DATA)
);
ddr2 inst_ddr2
(
.ck(ddr2_ck_p),
.ck_n(ddr2_ck_n),
.cke(ddr2_cke),
.cs_n(ddr2_cs_n),
.ras_n(ddr2_ras_n),
.cas_n(ddr2_cas_n),
.we_n(ddr2_we_n),
.dm_rdqs(ddr2_dm),
.ba(ddr2_ba),
.addr(ddr2_addr),
.dq(ddr2_dq),
.dqs(ddr2_dqs_p),
.dqs_n(ddr2_dqs_n),
//.rdqs_n(open),
.odt(ddr2_odt)
);
always
begin #(SPERIOD/2) SCLK = ~SCLK; end
always
begin #(PERIOD/2) CLK = ~CLK; end
task spi_write;
input [sword-1:0] waddr, wdata;
begin
CEB = 1'b0;
handshake = {2'b10,waddr,wdata};
for(j = 0; j < numbit_handshake; j = j+1) begin
DATA = handshake[numbit_handshake-j-1];
#SPERIOD;
end
CEB = 1'b1;
#(SPERIOD*4);
stat = 1'b1;
// Wait the axi handshake, SPI-POV
while(stat) begin
CEB = 1'b0;
DATA = 1'b0;
#SPERIOD;
DATA = 1'b0;
#SPERIOD; // SENT "SEND STATUS"
for(j = 0; j < sword; j = j+1) begin
result[sword-j-1] = DOUT;
#SPERIOD;
end
CEB = 1'b1;
#(SPERIOD*2);
if(result[1] == 1'b0 && result[0] == 1'b0) begin // CHECKING WBUSY AND BUSY
stat = 1'b0;
end
end
$display ("SPI: Written data %x = %x", waddr, wdata);
#(SPERIOD*8);
end
endtask
task spi_read;
input [sword-1:0] raddr;
begin
CEB = 1'b0;
handshake = {2'b01,raddr,32'h00000000};
for(j = 0; j < numbit_handshake; j = j+1) begin
DATA = handshake[numbit_handshake-j-1];
#SPERIOD;
end
CEB = 1'b1;
#(SPERIOD*3);
stat = 1'b1;
// Wait the axi handshake, SPI-POV
while(stat) begin
CEB = 1'b0;
DATA = 1'b0;
#SPERIOD;
DATA = 1'b0;
#SPERIOD; // SENT "SEND STATUS"
for(j = 0; j < sword; j = j+1) begin
result[sword-j-1] = DOUT;
#SPERIOD;
end
CEB = 1'b1;
#(SPERIOD*3);
if(result[2] == 1'b0 && result[0] == 1'b0) begin // CHECKING RBUSY AND BUSY
stat = 1'b0;
end else begin
$display ("SPI: Waiting reading to be done (%b) %x", result[2:0], raddr);
end
end
CEB = 1'b0;
DATA = 1'b1;
#SPERIOD;
DATA = 1'b1;
#SPERIOD; // SEND "SEND RDATA"
for(j = 0; j < sword; j = j+1) begin
result[sword-j-1] = DOUT;
#SPERIOD;
end
CEB = 1'b1;
$display ("SPI: Read data %x = %x", raddr, result);
#(SPERIOD*8);
end
endtask
task spi_picorv32_reset;
input rst;
begin
// SENDING PICORV RESET
CEB = 1'b0;
DATA = 1'b0;
#SPERIOD;
DATA = 1'b0;
#SPERIOD; // SENT "SEND STATUS", but we ignore totally the result
#(SPERIOD*(2*sword-1));
DATA = rst; // Send to the reset
#SPERIOD;
CEB = 1'b1;
#(SPERIOD*4);
end
endtask
// Task for expect something (helper)
task aexpect;
input [sword-1:0] av, e;
begin
if (av == e)
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e);
else
begin
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e);
error = error + 1;
end
end
endtask
// Our pseudo-random generator
reg [63:0] xorshift64_state = 64'd88172645463325252;
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
// Memory to write
reg [31:0] memory [0:SIZE_FIRMWARE];
initial $readmemh("firmware/firmware.hex", memory);
genvar z;
generate
for(z = 0; z < GPIO_PINS; z=z+1) begin : GPIO_PIN_ASSIGN
assign GPIO_pin[z] = GPIO_pin_act[z]?GPIO_pins[z]:1'bz;
end
endgenerate
initial begin
waiting = 0;
waiting_ok = 1'b0;
cap = {sword{1'b0}};
is_o = 1'b0;
is_ok = 1'b0;
CEB = 1'b1;
CLK = 1'b0;
SCLK = 1'b0;
RST = 1'b0;
DATA = 1'b0;
stat = 1'b0;
stats = 1'b0;
GPIO_pin_act = 32'd0;
GPIO_pins = 32'd0;
error = 0;
result = {sword{1'b0}};
handshake = {numbit_handshake{1'b0}};
#(SPERIOD*20);
RST = 1'b1;
#(SPERIOD*6);
/*// SENDING PICORV RESET TO ZERO
spi_picorv32_reset(1'b0);
// WRITTING PROGRAM
for(i = 0; i < SIZE_FIRMWARE; i = i+1) begin
spi_write(i, memory[i]);
end
// SENDING PICORV RESET TO ONE
spi_picorv32_reset(1'b1);
$display ("TIME=%t.", $time, "SPI: Programmed all instructions, picorv32 activated!");
$timeformat(-9,0,"ns",7);
// Waiting picorv to finish (Remember to put OK)
while(~waiting_ok) #SPERIOD;
// DAC_interface_AXI
$display("TIME=%t.", $time, "Doing the DAC_interface_AXI test");
for(l = 0; l < tries; l = l + 1) begin
CEB = 1'b0;
// Making handshake, writting, DAC dir, at random data
spi_write(32'h00005000,xorshift64_state[31:0]);
aexpect(DAC_interface_AXI_DATA, xorshift64_state[11:0]);
#(SPERIOD*8);
xorshift64_next;
end
// ADC_interface_AXI
$display("TIME=%t." , $time, "Doing the ADC_interface_AXI test");
for(i = 0; i < tries; i = i+1) begin
spi_read((32'h00000000 << 2) | 32'h0004000);
spi_read((32'h00000001 << 2) | 32'h0004000);
spi_read((32'h00000002 << 2) | 32'h0004000);
spi_read((32'h00000006 << 2) | 32'h0004000);
spi_read((32'h00000010 << 2) | 32'h0004000);
spi_read((32'h00000011 << 2) | 32'h0004000);
spi_read((32'h00000012 << 2) | 32'h0004000);
spi_read((32'h00000013 << 2) | 32'h0004000);
end
// GPIO_interface_AXI
$display("TIME=%t." , $time, "Doing the GPIO_interface_AXI test");
spi_write(((2*GPIO_PWM+ 1) << 2) | 32'h00004200, 32'h00000000); // Deactivate UART
spi_write(((2*GPIO_PWM+ 3) << 2) | 32'h00004200, 32'h00000000); // Deactivate PWMs
// General GPIO tests
for(i = 0; i < tries; i = i+1) begin
// General GPIO Pullup test
// What I write is what i get
xorshift64_next;
spi_write(((2*GPIO_PWM+10) << 2) | 32'h00004200, xorshift64_state[31:0]);
//aexpect(GPIO_Pullup, xorshift64_state[GPIO_PINS-1:0]);
// General GPIO Pulldown test
// What I write is what i get
xorshift64_next;
spi_write(((2*GPIO_PWM+ 9) << 2) | 32'h00004200, xorshift64_state[31:0]);
//aexpect(GPIO_Pulldown, xorshift64_state[GPIO_PINS-1:0]);
// General GPIO Strength test
// What I write is what i get
xorshift64_next;
spi_write(((2*GPIO_PWM+ 8) << 2) | 32'h00004200, xorshift64_state[31:0]);
//aexpect(GPIO_Strength, xorshift64_state[GPIO_PINS-1:0]);
// General GPIO Tx test
// What I write is what i get
xorshift64_next;
spi_write(((2*GPIO_PWM+ 7) << 2) | 32'h00004200, xorshift64_state[31:0]);
//aexpect(GPIO_Tx, xorshift64_state[GPIO_PINS-1:0]);
// General GPIO Rx test
// What I write is what i get
xorshift64_next;
spi_write(((2*GPIO_PWM+ 6) << 2) | 32'h00004200, xorshift64_state[31:0]);
//aexpect(GPIO_Rx, xorshift64_state[GPIO_PINS-1:0]);
// General GPIO Out test
// What I write is what i get
xorshift64_next;
spi_write(((2*GPIO_PWM+ 7) << 2) | 32'h00004200, 32'hFFFFFFFF); // Tx
spi_write(((2*GPIO_PWM+ 6) << 2) | 32'h00004200, 32'h00000000); // Rx
GPIO_pin_act = 32'h00000000;
spi_write(((2*GPIO_PWM+ 5) << 2) | 32'h00004200, xorshift64_state[31:0]);
aexpect(GPIO_pin, xorshift64_state[GPIO_PINS-1:0]);
// General GPIO In test
// What I get is what i put
xorshift64_next;
spi_write(((2*GPIO_PWM+ 7) << 2) | 32'h00004200, 32'h00000000); // Tx
spi_write(((2*GPIO_PWM+ 6) << 2) | 32'h00004200, 32'hFFFFFFFF); // Rx
GPIO_pin_act = 32'hFFFFFFFF;
GPIO_pins = xorshift64_state[GPIO_PINS-1:0];
spi_read(((2*GPIO_PWM+ 2) << 2) | 32'h00004200);
aexpect(result[GPIO_PINS-1:0], xorshift64_state[GPIO_PINS-1:0]);
end
// General UART test
GPIO_pins[1] = 1'b1; // Uart Rx on 1
spi_write(((2*GPIO_PWM+ 1) << 2) | 32'h00004200, 32'h00000001); // Activate UART, 9600 BPS
spi_write(((2*GPIO_PWM+ 6) << 2) | 32'h00004200, 32'h00000002); // Rx Pin 1 must be 1
spi_write(((2*GPIO_PWM+ 7) << 2) | 32'h00004200, 32'h00000001); // Tx Pin 0 must be 1
GPIO_pin_act = 32'h00000001;
for(i = 0; i < tries; i = i+1) begin
// General GPIO Out test
xorshift64_next;
spi_write(((2*GPIO_PWM+11) << 2) | 32'h00004200, {24'd0, xorshift64_state[7:0]});
// 104166667=1000000000000/9600
for(j=0; j < (104166667/PERIOD*(12)); j = j+1) begin
GPIO_pins[1] = GPIO_pin[0];
#PERIOD;
end
spi_read(((2*GPIO_PWM+11) << 2) | 32'h00004200);
aexpect(result[7:0], xorshift64_state[7:0]);
end
// PWMs (Graphical)
spi_write(((2*GPIO_PWM+ 3) << 2) | 32'h00004200, 32'hFFFFFFFF); // Activate PWMs
spi_write(((2*GPIO_PWM+ 1) << 2) | 32'h00004200, 32'h00000000); // Deactivate UART
spi_write(((2*GPIO_PWM+ 6) << 2) | 32'h00004200, 32'h00000000); // Rx must be 0
spi_write(((2*GPIO_PWM+ 7) << 2) | 32'h00004200, 32'hFFFFFFFF); // Tx must be 1
spi_write(((2*GPIO_PWM+ 0) << 2) | 32'h00004200, 32'h00000000); // Main prescaler is 0
for(i = 0; i < GPIO_PWM; i = i+1) begin
xorshift64_next;
spi_write((i << 2) | 32'h00004200, {16'd0, xorshift64_state[15:0]}); // Partial prescaler is 0
spi_write(((GPIO_PWM+ i) << 2) | 32'h00004200, 32'h00000000); // Partial prescaler is 0
end
// Time for PWMs
#(PERIOD*300000);
// SEGMENT_interface_AXI
$display("TIME=%t." , $time, "Doing the SEGMENT_interface_AXI test");
spi_write((32'h00000000 << 2) | 32'h00004600, {24'd0, "a"});
spi_write((32'h00000000 << 2) | 32'h00004600, {24'd0, "b"});
spi_write((32'h00000000 << 2) | 32'h00004600, {24'd0, "r"});
spi_write((32'h00000000 << 2) | 32'h00004600, {24'd0, "a"});
spi_write((32'h00000000 << 2) | 32'h00004600, {24'd0, "s"});
spi_write((32'h00000000 << 2) | 32'h00004600, {24'd0, "e"});
spi_write((32'h00000000 << 2) | 32'h00004600, {24'd0, "."});
spi_write((32'h00000000 << 2) | 32'h00004600, {24'd0, " "});
#(PERIOD*300000);
*/
if (error == 0)
$display("All match");
else
$display("Mismatches = %d", error);
$finish;
//$stop;
end
// SPI AXI SLAVE interface simulation
always @(posedge spi_axi_slave_SCLK) begin
if(spi_axi_slave_CEB == 1'b0) begin
stats <= 1'b1;
cap <= {cap[sword-2:0], spi_axi_slave_DATA};
end else if(stats == 1'b1) begin
stats <= 1'b0;
if(cap == 79 || (cap == 75 && is_o == 1'b1))
is_o <= 1'b1;
else
is_o <= 1'b0;
if(cap == 75 && is_o == 1'b1)
is_ok <= 1'b1;
`ifdef VERBOSE
if (32 <= cap && cap < 128)
$display("OUT: '%c'", cap);
else
$display("OUT: %3d", cap);
`else
$write("%c", cap);
$fflush();
`endif
end
end
// Waiting to end program
always @(posedge SCLK) begin
if(waiting_ok == 1'b0) begin
if(is_ok == 1'b1) begin
$display ("Program Suceed! Reseted the picorv");
waiting_ok = 1'b1;
#(SPERIOD*4);
end else begin
waiting = waiting + 1;
if(waiting >= max_wait) begin
waiting_ok = 1'b1;
$display("TIMEOUT!, PLEASE DO NOT FORGET TO PUT 'OK' ON THE FIRMWARE");
$finish;
end
xorshift64_next;
end
end
end
endmodule |
module sky130_fd_sc_lp__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule |
module Scheduler(input clk, input reset,
input [3:0] io_slots_7,
input [3:0] io_slots_6,
input [3:0] io_slots_5,
input [3:0] io_slots_4,
input [3:0] io_slots_3,
input [3:0] io_slots_2,
input [3:0] io_slots_1,
input [3:0] io_slots_0,
input [1:0] io_thread_modes_3,
input [1:0] io_thread_modes_2,
input [1:0] io_thread_modes_1,
input [1:0] io_thread_modes_0,
output[1:0] io_thread,
output io_valid
);
wire T0;
wire T1;
wire T2;
wire T3;
wire T4;
wire[1:0] T5;
wire[1:0] T6;
wire T7;
wire[1:0] T8;
wire[1:0] T9;
wire[3:0] T10;
wire[3:0] T11;
wire T12;
wire T13;
wire T14;
wire T15;
wire T16;
wire T17;
wire T18;
wire T19;
wire T20;
wire T21;
wire T22;
wire T23;
wire T24;
wire T25;
wire T26;
wire T27;
wire T28;
wire T29;
wire T30;
wire T31;
wire T32;
wire T33;
reg R34;
wire T214;
wire T35;
wire T36;
wire T37;
wire T38;
wire T39;
wire T40;
wire T41;
wire T42;
wire T43;
wire T44;
wire T45;
wire T46;
wire T47;
reg R48;
wire T215;
wire T49;
wire T50;
wire T51;
wire T52;
wire T53;
wire T54;
wire T55;
wire T56;
wire T57;
wire T58;
wire T59;
reg R60;
wire T216;
wire T61;
wire T62;
wire T63;
wire T64;
reg R65;
wire T217;
wire T66;
wire T67;
wire T68;
wire T69;
wire T70;
reg R71;
wire T218;
wire T72;
wire T73;
wire T74;
wire T75;
wire T76;
wire T77;
wire T78;
wire T79;
wire T80;
wire T81;
wire T82;
wire T83;
wire T84;
wire T85;
reg R86;
wire T219;
wire T87;
wire T88;
wire T89;
wire T90;
wire T91;
wire T92;
wire T93;
wire T94;
wire T95;
wire T96;
wire T97;
wire T98;
wire T99;
wire T100;
wire T101;
wire T102;
wire T103;
wire T104;
wire T105;
wire T106;
wire T107;
wire T108;
wire T109;
wire T110;
reg R111;
wire T220;
wire T112;
wire T113;
wire T114;
wire T115;
wire T116;
wire T117;
wire T118;
wire T119;
wire T120;
wire T121;
wire T122;
wire T123;
wire T124;
wire T125;
wire T126;
wire T127;
wire T128;
wire T129;
wire T130;
wire T131;
wire T132;
wire T133;
wire T134;
wire T135;
wire T136;
wire T137;
wire[3:0] T138;
wire[3:0] T139;
wire[3:0] T140;
wire[3:0] T141;
wire[3:0] T142;
wire[3:0] T143;
wire[3:0] T144;
wire[3:0] T145;
wire[3:0] T146;
wire[3:0] T147;
wire[3:0] T148;
wire[3:0] T149;
wire[3:0] T150;
wire[1:0] T151;
wire T152;
wire T153;
wire T154;
wire T155;
wire T156;
wire T157;
wire T158;
wire T159;
wire T160;
wire T161;
wire T162;
wire T163;
wire T164;
wire T165;
wire T166;
wire T167;
wire T168;
wire T169;
wire T170;
wire T171;
wire T172;
wire T173;
wire T174;
wire T175;
wire T176;
wire T177;
wire T178;
wire T179;
reg R180;
wire T221;
wire T181;
wire T182;
wire T183;
wire T184;
reg R185;
wire T222;
wire T186;
wire T187;
wire T188;
wire T189;
wire T190;
reg R191;
wire T223;
wire T192;
wire T193;
wire T194;
wire T195;
wire T196;
wire T197;
wire T198;
wire T199;
wire T200;
wire T201;
wire T202;
wire T203;
wire T204;
wire[1:0] T224;
wire[2:0] T205;
wire[2:0] T206;
wire[2:0] T225;
wire[1:0] T207;
wire[2:0] T208;
wire[2:0] T226;
wire[1:0] T227;
wire T228;
wire[1:0] T229;
wire[1:0] T230;
wire[3:0] T210;
wire[3:0] T211;
wire[1:0] T212;
wire[1:0] T213;
wire[1:0] T231;
wire T232;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R34 = {1{$random}};
R48 = {1{$random}};
R60 = {1{$random}};
R65 = {1{$random}};
R71 = {1{$random}};
R86 = {1{$random}};
R111 = {1{$random}};
R180 = {1{$random}};
R185 = {1{$random}};
R191 = {1{$random}};
end
// synthesis translate_on
`endif
assign io_valid = T0;
assign T0 = T163 ? 1'h1 : T1;
assign T1 = T156 & T2;
assign T2 = T155 & T3;
assign T3 = T154 | T4;
assign T4 = T5 == 2'h2;
assign T5 = T153 ? T151 : T6;
assign T6 = T7 ? io_thread_modes_1 : io_thread_modes_0;
assign T7 = T8[1'h0:1'h0];
assign T8 = T9;
assign T9 = T10[1'h1:1'h0];
assign T10 = T138 | T11;
assign T11 = T12 ? io_slots_7 : 4'h0;
assign T12 = T132 ? T29 : T13;
assign T13 = T28 & T14;
assign T14 = T15 ^ 1'h1;
assign T15 = T17 | T16;
assign T16 = io_slots_6 != 4'hf;
assign T17 = T19 | T18;
assign T18 = io_slots_5 != 4'hf;
assign T19 = T21 | T20;
assign T20 = io_slots_4 != 4'hf;
assign T21 = T23 | T22;
assign T22 = io_slots_3 != 4'hf;
assign T23 = T25 | T24;
assign T24 = io_slots_2 != 4'hf;
assign T25 = T27 | T26;
assign T26 = io_slots_1 != 4'hf;
assign T27 = io_slots_0 != 4'hf;
assign T28 = io_slots_7 != 4'hf;
assign T29 = T109 & T30;
assign T30 = T31 ^ 1'h1;
assign T31 = T105 | T32;
assign T32 = T16 & T33;
assign T33 = T101 | R34;
assign T214 = reset ? 1'h0 : T35;
assign T35 = T156 ? T36 : R34;
assign T36 = T132 ? T43 : T37;
assign T37 = T18 & T38;
assign T38 = T39 ^ 1'h1;
assign T39 = T40 | T20;
assign T40 = T41 | T22;
assign T41 = T42 | T24;
assign T42 = T27 | T26;
assign T43 = T84 & T44;
assign T44 = T45 ^ 1'h1;
assign T45 = T82 | T46;
assign T46 = T20 & T47;
assign T47 = T80 | R48;
assign T215 = reset ? 1'h0 : T49;
assign T49 = T156 ? T50 : R48;
assign T50 = T132 ? T55 : T51;
assign T51 = T22 & T52;
assign T52 = T53 ^ 1'h1;
assign T53 = T54 | T24;
assign T54 = T27 | T26;
assign T55 = T69 & T56;
assign T56 = T57 ^ 1'h1;
assign T57 = T68 | T58;
assign T58 = T24 & T59;
assign T59 = R65 | R60;
assign T216 = reset ? 1'h0 : T61;
assign T61 = T156 ? T62 : R60;
assign T62 = T132 ? T68 : T63;
assign T63 = T26 & T64;
assign T64 = T27 ^ 1'h1;
assign T217 = reset ? 1'h0 : T66;
assign T66 = T156 ? T67 : R65;
assign T67 = T132 ? 1'h0 : T27;
assign T68 = T26 & R65;
assign T69 = T22 & T70;
assign T70 = T79 | R71;
assign T218 = reset ? 1'h0 : T72;
assign T72 = T156 ? T73 : R71;
assign T73 = T132 ? T77 : T74;
assign T74 = T24 & T75;
assign T75 = T76 ^ 1'h1;
assign T76 = T27 | T26;
assign T77 = T58 & T78;
assign T78 = T68 ^ 1'h1;
assign T79 = R65 | R60;
assign T80 = T81 | R71;
assign T81 = R65 | R60;
assign T82 = T83 | T69;
assign T83 = T68 | T58;
assign T84 = T18 & T85;
assign T85 = T98 | R86;
assign T219 = reset ? 1'h0 : T87;
assign T87 = T156 ? T88 : R86;
assign T88 = T132 ? T94 : T89;
assign T89 = T20 & T90;
assign T90 = T91 ^ 1'h1;
assign T91 = T92 | T22;
assign T92 = T93 | T24;
assign T93 = T27 | T26;
assign T94 = T46 & T95;
assign T95 = T96 ^ 1'h1;
assign T96 = T97 | T69;
assign T97 = T68 | T58;
assign T98 = T99 | R48;
assign T99 = T100 | R71;
assign T100 = R65 | R60;
assign T101 = T102 | R86;
assign T102 = T103 | R48;
assign T103 = T104 | R71;
assign T104 = R65 | R60;
assign T105 = T106 | T84;
assign T106 = T107 | T46;
assign T107 = T108 | T69;
assign T108 = T68 | T58;
assign T109 = T28 & T110;
assign T110 = T127 | R111;
assign T220 = reset ? 1'h0 : T112;
assign T112 = T156 ? T113 : R111;
assign T113 = T132 ? T121 : T114;
assign T114 = T16 & T115;
assign T115 = T116 ^ 1'h1;
assign T116 = T117 | T18;
assign T117 = T118 | T20;
assign T118 = T119 | T22;
assign T119 = T120 | T24;
assign T120 = T27 | T26;
assign T121 = T32 & T122;
assign T122 = T123 ^ 1'h1;
assign T123 = T124 | T84;
assign T124 = T125 | T46;
assign T125 = T126 | T69;
assign T126 = T68 | T58;
assign T127 = T128 | R34;
assign T128 = T129 | R86;
assign T129 = T130 | R48;
assign T130 = T131 | R71;
assign T131 = R65 | R60;
assign T132 = T133 | T109;
assign T133 = T134 | T32;
assign T134 = T135 | T84;
assign T135 = T136 | T46;
assign T136 = T137 | T69;
assign T137 = T68 | T58;
assign T138 = T140 | T139;
assign T139 = T113 ? io_slots_6 : 4'h0;
assign T140 = T142 | T141;
assign T141 = T36 ? io_slots_5 : 4'h0;
assign T142 = T144 | T143;
assign T143 = T88 ? io_slots_4 : 4'h0;
assign T144 = T146 | T145;
assign T145 = T50 ? io_slots_3 : 4'h0;
assign T146 = T148 | T147;
assign T147 = T73 ? io_slots_2 : 4'h0;
assign T148 = T150 | T149;
assign T149 = T62 ? io_slots_1 : 4'h0;
assign T150 = T67 ? io_slots_0 : 4'h0;
assign T151 = T152 ? io_thread_modes_3 : io_thread_modes_2;
assign T152 = T8[1'h0:1'h0];
assign T153 = T8[1'h1:1'h1];
assign T154 = T5 == 2'h0;
assign T155 = T10 != 4'he;
assign T156 = T157 | T12;
assign T157 = T158 | T113;
assign T158 = T159 | T36;
assign T159 = T160 | T88;
assign T160 = T161 | T50;
assign T161 = T162 | T73;
assign T162 = T67 | T62;
assign T163 = T156 & T164;
assign T164 = T204 & T165;
assign T165 = T202 | T166;
assign T166 = T200 ? T175 : T167;
assign T167 = T174 & T168;
assign T168 = T169 ^ 1'h1;
assign T169 = T171 | T170;
assign T170 = io_thread_modes_2 == 2'h2;
assign T171 = T173 | T172;
assign T172 = io_thread_modes_1 == 2'h2;
assign T173 = io_thread_modes_0 == 2'h2;
assign T174 = io_thread_modes_3 == 2'h2;
assign T175 = T189 & T176;
assign T176 = T177 ^ 1'h1;
assign T177 = T188 | T178;
assign T178 = T170 & T179;
assign T179 = R185 | R180;
assign T221 = reset ? 1'h0 : T181;
assign T181 = T163 ? T182 : R180;
assign T182 = T200 ? T188 : T183;
assign T183 = T172 & T184;
assign T184 = T173 ^ 1'h1;
assign T222 = reset ? 1'h0 : T186;
assign T186 = T163 ? T187 : R185;
assign T187 = T200 ? 1'h0 : T173;
assign T188 = T172 & R185;
assign T189 = T174 & T190;
assign T190 = T199 | R191;
assign T223 = reset ? 1'h0 : T192;
assign T192 = T163 ? T193 : R191;
assign T193 = T200 ? T197 : T194;
assign T194 = T170 & T195;
assign T195 = T196 ^ 1'h1;
assign T196 = T173 | T172;
assign T197 = T178 & T198;
assign T198 = T188 ^ 1'h1;
assign T199 = R185 | R180;
assign T200 = T201 | T189;
assign T201 = T188 | T178;
assign T202 = T203 | T193;
assign T203 = T187 | T182;
assign T204 = T2 ^ 1'h1;
assign io_thread = T224;
assign T224 = T205[1'h1:1'h0];
assign T205 = T163 ? T226 : T206;
assign T206 = T1 ? T208 : T225;
assign T225 = {1'h0, T207};
assign T207 = T10[1'h1:1'h0];
assign T208 = T10[2'h2:1'h0];
assign T226 = {1'h0, T227};
assign T227 = {T232, T228};
assign T228 = T229[1'h1:1'h1];
assign T229 = T231 | T230;
assign T230 = T210[1'h1:1'h0];
assign T210 = T211;
assign T211 = {T213, T212};
assign T212 = {T182, T187};
assign T213 = {T166, T193};
assign T231 = T210[2'h3:2'h2];
assign T232 = T231 != 2'h0;
always @(posedge clk) begin
if(reset) begin
R34 <= 1'h0;
end else if(T156) begin
R34 <= T36;
end
if(reset) begin
R48 <= 1'h0;
end else if(T156) begin
R48 <= T50;
end
if(reset) begin
R60 <= 1'h0;
end else if(T156) begin
R60 <= T62;
end
if(reset) begin
R65 <= 1'h0;
end else if(T156) begin
R65 <= T67;
end
if(reset) begin
R71 <= 1'h0;
end else if(T156) begin
R71 <= T73;
end
if(reset) begin
R86 <= 1'h0;
end else if(T156) begin
R86 <= T88;
end
if(reset) begin
R111 <= 1'h0;
end else if(T156) begin
R111 <= T113;
end
if(reset) begin
R180 <= 1'h0;
end else if(T163) begin
R180 <= T182;
end
if(reset) begin
R185 <= 1'h0;
end else if(T163) begin
R185 <= T187;
end
if(reset) begin
R191 <= 1'h0;
end else if(T163) begin
R191 <= T193;
end
end
endmodule |
module Control(input clk, input reset,
output[2:0] io_dec_imm_sel,
output[1:0] io_dec_op1_sel,
output[1:0] io_dec_op2_sel,
output[3:0] io_exe_alu_type,
output[2:0] io_exe_br_type,
output[1:0] io_exe_csr_type,
output[1:0] io_exe_mul_type,
output[1:0] io_exe_rd_data_sel,
output[3:0] io_exe_mem_type,
output[1:0] io_mem_rd_data_sel,
output[1:0] io_next_pc_sel_3,
output[1:0] io_next_pc_sel_2,
output[1:0] io_next_pc_sel_1,
output[1:0] io_next_pc_sel_0,
output[1:0] io_next_tid,
output io_next_valid,
output[1:0] io_dec_rs1_sel,
output[1:0] io_dec_rs2_sel,
output io_exe_valid,
output io_exe_load,
output io_exe_store,
output io_exe_csr_write,
output io_exe_exception,
output[4:0] io_exe_cause,
output io_exe_kill,
output io_exe_sleep,
output io_exe_ie,
output io_exe_ee,
output io_exe_sret,
output io_exe_cycle,
output io_exe_instret,
output io_mem_rd_write,
input [1:0] io_if_tid,
input [1:0] io_dec_tid,
input [31:0] io_dec_inst,
input io_exe_br_cond,
input [1:0] io_exe_tid,
input [4:0] io_exe_rd_addr,
input io_exe_expire,
input [3:0] io_csr_slots_7,
input [3:0] io_csr_slots_6,
input [3:0] io_csr_slots_5,
input [3:0] io_csr_slots_4,
input [3:0] io_csr_slots_3,
input [3:0] io_csr_slots_2,
input [3:0] io_csr_slots_1,
input [3:0] io_csr_slots_0,
input [1:0] io_csr_tmodes_3,
input [1:0] io_csr_tmodes_2,
input [1:0] io_csr_tmodes_1,
input [1:0] io_csr_tmodes_0,
input [1:0] io_mem_tid,
input [4:0] io_mem_rd_addr,
input [1:0] io_wb_tid,
input [4:0] io_wb_rd_addr,
input io_if_exc_misaligned,
input io_if_exc_fault,
input io_exe_exc_priv_inst,
input io_exe_exc_load_misaligned,
input io_exe_exc_load_fault,
input io_exe_exc_store_misaligned,
input io_exe_exc_store_fault,
input io_exe_exc_expire,
input io_exe_int_expire,
input io_exe_int_ext
);
wire exe_valid;
wire T0;
wire exe_exception;
wire T1;
wire T2;
wire exe_any_exc;
wire T3;
wire T4;
wire exe_inst_exc;
wire T5;
reg exe_reg_exc;
wire T6;
wire dec_exc;
wire T7;
wire dec_scall;
wire[31:0] T8;
wire T9;
wire T10;
wire dec_legal;
wire T11;
wire[31:0] T12;
wire T13;
wire T14;
wire[31:0] T15;
wire T16;
wire T17;
wire[31:0] T18;
wire T19;
wire T20;
wire[31:0] T21;
wire T22;
wire T23;
wire[31:0] T24;
wire T25;
wire dec_ie;
wire[31:0] T26;
wire T27;
wire dec_du;
wire[31:0] T28;
wire T29;
wire T30;
wire[31:0] T31;
wire T32;
wire T33;
wire[31:0] T34;
wire T35;
wire T36;
wire[31:0] T37;
wire T38;
wire T39;
wire[31:0] T40;
wire T41;
wire T42;
wire T43;
wire[31:0] T44;
wire T45;
wire T46;
wire[31:0] T47;
wire T48;
wire T49;
wire[31:0] T50;
wire T51;
wire T52;
wire[31:0] T53;
wire T54;
wire T55;
wire[31:0] T56;
wire T57;
wire T58;
wire[31:0] T59;
wire T60;
wire T61;
wire[31:0] T62;
wire T63;
wire T64;
wire[31:0] T65;
wire T66;
wire[31:0] T67;
reg dec_reg_exc;
reg exe_reg_valid;
wire T354;
wire dec_valid;
wire T68;
wire T69;
wire T70;
wire exe_flush;
wire T71;
wire T72;
wire exe_brjmp;
wire T73;
wire T74;
reg exe_reg_branch;
wire T75;
wire dec_branch;
wire T76;
wire[31:0] T77;
reg exe_reg_jump;
wire T78;
wire dec_jump;
wire T79;
wire[31:0] T80;
wire exe_sleep;
wire exe_du;
wire T81;
wire T82;
wire T83;
reg R84;
wire T85;
reg dec_reg_valid;
wire T355;
wire if_valid;
wire T86;
wire T87;
wire T88;
wire if_pre_valid;
wire T89;
wire[1:0] T90;
wire[1:0] T91;
reg [1:0] stall_count_0;
wire[1:0] T356;
wire[1:0] T92;
wire[1:0] T93;
wire[1:0] T94;
wire[1:0] T95;
wire[1:0] T96;
wire T97;
wire T98;
wire T99;
wire[3:0] T100;
wire[1:0] T101;
wire T102;
wire T103;
wire T104;
wire dec_fence_i;
wire[31:0] T105;
wire T106;
reg [1:0] stall_count_1;
wire[1:0] T357;
wire[1:0] T107;
wire[1:0] T108;
wire[1:0] T109;
wire[1:0] T110;
wire[1:0] T111;
wire T112;
wire T113;
wire T114;
wire T115;
wire T116;
wire T117;
wire[1:0] T118;
wire[1:0] T119;
reg [1:0] stall_count_2;
wire[1:0] T358;
wire[1:0] T120;
wire[1:0] T121;
wire[1:0] T122;
wire[1:0] T123;
wire[1:0] T124;
wire T125;
wire T126;
wire T127;
wire T128;
wire T129;
reg [1:0] stall_count_3;
wire[1:0] T359;
wire[1:0] T130;
wire[1:0] T131;
wire[1:0] T132;
wire[1:0] T133;
wire[1:0] T134;
wire T135;
wire T136;
wire T137;
wire T138;
wire T139;
wire T140;
wire T141;
wire T142;
wire T143;
wire T144;
wire T145;
wire dec_stall;
wire T146;
wire T147;
wire T148;
wire T149;
wire dec_load;
wire T150;
wire[31:0] T151;
wire T152;
wire T153;
wire[1:0] dec_mem_rd_data_sel;
wire T154;
wire[31:0] T155;
wire T156;
wire[31:0] T157;
reg if_reg_valid;
wire T360;
wire next_valid;
reg R158;
wire T361;
wire mem_rd_write;
reg mem_reg_valid;
wire T362;
reg mem_reg_rd_write;
wire T159;
reg exe_reg_rd_write;
wire T160;
wire dec_rd_write;
wire T161;
wire dec_rd_en;
wire T162;
wire T163;
wire T164;
wire T165;
wire T166;
wire T167;
wire T168;
wire[31:0] T169;
wire T170;
wire T171;
wire T172;
wire T173;
wire T174;
wire T175;
wire T176;
wire T177;
wire[31:0] T178;
wire T179;
wire[4:0] T180;
wire exe_instret;
wire exe_cycle;
wire exe_sret;
reg exe_reg_sret;
wire T181;
wire exe_ee;
wire T182;
reg R183;
wire T184;
wire T185;
wire T186;
wire T187;
wire T188;
wire exe_ie;
wire T189;
reg R190;
wire T191;
wire T192;
wire T193;
wire T194;
wire exe_kill;
wire[4:0] exe_exception_cause;
wire[4:0] T195;
wire[4:0] T196;
wire[4:0] exe_any_cause;
wire[4:0] T197;
wire[4:0] T198;
wire[4:0] T363;
wire[3:0] exe_inst_cause;
wire[3:0] T199;
wire[3:0] T200;
wire[4:0] T364;
reg [2:0] exe_reg_cause;
wire[2:0] T201;
wire[2:0] dec_cause;
wire[2:0] T202;
wire[2:0] T365;
reg dec_reg_cause;
wire exe_csr_write;
reg exe_reg_csr_write;
wire T203;
wire dec_csr;
wire exe_store;
reg exe_reg_store;
wire T204;
wire dec_store;
wire T205;
wire[31:0] T206;
wire T207;
wire[31:0] T208;
wire exe_load;
reg exe_reg_load;
wire T209;
wire[1:0] dec_rs2_sel;
wire[1:0] T210;
wire[1:0] T211;
wire[1:0] T212;
wire T213;
wire T214;
wire[4:0] T215;
wire T216;
reg wb_reg_rd_write;
wire T217;
wire T218;
wire T219;
wire T220;
wire T221;
wire T222;
wire T223;
wire T224;
wire T225;
wire[1:0] dec_rs1_sel;
wire[1:0] T226;
wire[1:0] T227;
wire[1:0] T228;
wire T229;
wire T230;
wire[4:0] T231;
wire T232;
wire T233;
wire T234;
wire T235;
wire[1:0] next_tid;
reg [1:0] R236;
wire[1:0] next_pc_sel_0;
wire[1:0] T237;
wire[1:0] T238;
wire[1:0] T239;
wire T240;
wire T241;
wire[3:0] T242;
wire[1:0] T243;
wire T244;
wire T245;
wire[3:0] T246;
wire[1:0] T247;
wire T248;
wire T249;
wire T250;
wire[3:0] T251;
wire[1:0] T252;
reg mem_reg_exception;
wire[1:0] next_pc_sel_1;
wire[1:0] T253;
wire[1:0] T254;
wire[1:0] T255;
wire T256;
wire T257;
wire T258;
wire T259;
wire T260;
wire T261;
wire[1:0] next_pc_sel_2;
wire[1:0] T262;
wire[1:0] T263;
wire[1:0] T264;
wire T265;
wire T266;
wire T267;
wire T268;
wire T269;
wire T270;
wire[1:0] next_pc_sel_3;
wire[1:0] T271;
wire[1:0] T272;
wire[1:0] T273;
wire T274;
wire T275;
wire T276;
wire T277;
wire T278;
wire T279;
reg [1:0] mem_reg_rd_data_sel;
reg [1:0] R280;
reg [3:0] exe_reg_mem_type;
wire[3:0] dec_mem_type;
wire[2:0] T281;
wire[1:0] T282;
wire T283;
wire[31:0] T284;
wire T285;
wire[31:0] T286;
wire T287;
wire[31:0] T288;
wire T289;
wire[31:0] T290;
reg [1:0] exe_reg_rd_data_sel;
wire[1:0] dec_exe_rd_data_sel;
wire T291;
wire[31:0] T292;
wire T293;
wire[31:0] T294;
reg [1:0] exe_reg_mul_type;
wire[1:0] dec_mul_type;
reg [1:0] exe_reg_csr_type;
wire[1:0] dec_csr_type;
reg [2:0] exe_reg_br_type;
wire[2:0] dec_br_type;
wire[1:0] T295;
wire T296;
wire[31:0] T297;
reg [3:0] exe_reg_alu_type;
wire[3:0] dec_alu_type;
wire[2:0] T298;
wire[1:0] T299;
wire T300;
wire[31:0] T301;
wire T302;
wire[31:0] T303;
wire T304;
wire[31:0] T305;
wire T306;
wire T307;
wire[31:0] T308;
wire T309;
wire T310;
wire[31:0] T311;
wire T312;
wire[31:0] T313;
wire[1:0] dec_op2_sel;
wire T314;
wire T315;
wire[31:0] T316;
wire T317;
wire T318;
wire[31:0] T319;
wire T320;
wire[31:0] T321;
wire T322;
wire T323;
wire[31:0] T324;
wire T325;
wire T326;
wire[31:0] T327;
wire[1:0] dec_op1_sel;
wire T328;
wire T329;
wire[31:0] T330;
wire T331;
wire T332;
wire[31:0] T333;
wire T334;
wire[31:0] T335;
wire T336;
wire T337;
wire[31:0] T338;
wire T339;
wire[31:0] T340;
wire[2:0] dec_imm_sel;
wire[1:0] T341;
wire T342;
wire T343;
wire[31:0] T344;
wire T345;
wire T346;
wire[31:0] T347;
wire T348;
wire T349;
wire[31:0] T350;
wire T351;
wire T352;
wire[31:0] T353;
wire[1:0] scheduler_io_thread;
wire scheduler_io_valid;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
exe_reg_exc = {1{$random}};
dec_reg_exc = {1{$random}};
exe_reg_valid = {1{$random}};
exe_reg_branch = {1{$random}};
exe_reg_jump = {1{$random}};
R84 = {1{$random}};
dec_reg_valid = {1{$random}};
stall_count_0 = {1{$random}};
stall_count_1 = {1{$random}};
stall_count_2 = {1{$random}};
stall_count_3 = {1{$random}};
if_reg_valid = {1{$random}};
R158 = {1{$random}};
mem_reg_valid = {1{$random}};
mem_reg_rd_write = {1{$random}};
exe_reg_rd_write = {1{$random}};
exe_reg_sret = {1{$random}};
R183 = {1{$random}};
R190 = {1{$random}};
exe_reg_cause = {1{$random}};
dec_reg_cause = {1{$random}};
exe_reg_csr_write = {1{$random}};
exe_reg_store = {1{$random}};
exe_reg_load = {1{$random}};
wb_reg_rd_write = {1{$random}};
R236 = {1{$random}};
mem_reg_exception = {1{$random}};
mem_reg_rd_data_sel = {1{$random}};
R280 = {1{$random}};
exe_reg_mem_type = {1{$random}};
exe_reg_rd_data_sel = {1{$random}};
exe_reg_mul_type = {1{$random}};
exe_reg_csr_type = {1{$random}};
exe_reg_br_type = {1{$random}};
exe_reg_alu_type = {1{$random}};
end
// synthesis translate_on
`endif
assign exe_valid = exe_reg_valid & T0;
assign T0 = exe_exception ^ 1'h1;
assign exe_exception = T1;
assign T1 = exe_reg_valid & T2;
assign T2 = T4 | exe_any_exc;
assign exe_any_exc = T3 | io_exe_int_ext;
assign T3 = io_exe_exc_expire | io_exe_int_expire;
assign T4 = exe_reg_exc | exe_inst_exc;
assign exe_inst_exc = T5 | io_exe_exc_store_misaligned;
assign T5 = io_exe_exc_priv_inst | io_exe_exc_load_misaligned;
assign T6 = dec_reg_exc | dec_exc;
assign dec_exc = T9 | T7;
assign T7 = dec_scall;
assign dec_scall = T8 == 32'h73;
assign T8 = io_dec_inst & 32'h8010707f;
assign T9 = T10 ^ 1'h1;
assign T10 = dec_legal;
assign dec_legal = T13 | T11;
assign T11 = T12 == 32'h3;
assign T12 = io_dec_inst & 32'h306f;
assign T13 = T16 | T14;
assign T14 = T15 == 32'h1013;
assign T15 = io_dec_inst & 32'hfc00705f;
assign T16 = T19 | T17;
assign T17 = T18 == 32'h4063;
assign T18 = io_dec_inst & 32'h407f;
assign T19 = T22 | T20;
assign T20 = T21 == 32'h1063;
assign T21 = io_dec_inst & 32'h306f;
assign T22 = T25 | T23;
assign T23 = T24 == 32'h23;
assign T24 = io_dec_inst & 32'h603f;
assign T25 = T27 | dec_ie;
assign dec_ie = T26 == 32'h705b;
assign T26 = io_dec_inst & 32'h707f;
assign T27 = T29 | dec_du;
assign dec_du = T28 == 32'h700b;
assign T28 = io_dec_inst & 32'h705f;
assign T29 = T32 | T30;
assign T30 = T31 == 32'h5033;
assign T31 = io_dec_inst & 32'hbe00707f;
assign T32 = T35 | T33;
assign T33 = T34 == 32'h5013;
assign T34 = io_dec_inst & 32'hbc00707f;
assign T35 = T38 | T36;
assign T36 = T37 == 32'h2073;
assign T37 = io_dec_inst & 32'h207f;
assign T38 = T41 | T39;
assign T39 = T40 == 32'h2013;
assign T40 = io_dec_inst & 32'h207f;
assign T41 = T42 | dec_scall;
assign T42 = T45 | T43;
assign T43 = T44 == 32'h6f;
assign T44 = io_dec_inst & 32'h7f;
assign T45 = T48 | T46;
assign T46 = T47 == 32'h63;
assign T47 = io_dec_inst & 32'h707b;
assign T48 = T51 | T49;
assign T49 = T50 == 32'h33;
assign T50 = io_dec_inst & 32'hbe00707f;
assign T51 = T54 | T52;
assign T52 = T53 == 32'h33;
assign T53 = io_dec_inst & 32'hfc00407f;
assign T54 = T57 | T55;
assign T55 = T56 == 32'h33;
assign T56 = io_dec_inst & 32'hfe00007f;
assign T57 = T60 | T58;
assign T58 = T59 == 32'h17;
assign T59 = io_dec_inst & 32'h5f;
assign T60 = T63 | T61;
assign T61 = T62 == 32'hf;
assign T62 = io_dec_inst & 32'h607f;
assign T63 = T66 | T64;
assign T64 = T65 == 32'h3;
assign T65 = io_dec_inst & 32'h207f;
assign T66 = T67 == 32'h3;
assign T67 = io_dec_inst & 32'h505f;
assign T354 = reset ? 1'h0 : dec_valid;
assign dec_valid = dec_reg_valid & T68;
assign T68 = T69 ^ 1'h1;
assign T69 = exe_flush & T70;
assign T70 = io_dec_tid == io_exe_tid;
assign exe_flush = T71;
assign T71 = exe_sleep ? 1'h1 : T72;
assign T72 = exe_brjmp ? 1'h1 : exe_exception;
assign exe_brjmp = exe_reg_valid & T73;
assign T73 = exe_reg_jump | T74;
assign T74 = exe_reg_branch & io_exe_br_cond;
assign T75 = dec_branch;
assign dec_branch = T76 | T17;
assign T76 = T77 == 32'h63;
assign T77 = io_dec_inst & 32'h207f;
assign T78 = dec_jump;
assign dec_jump = T79 | T43;
assign T79 = T80 == 32'h67;
assign T80 = io_dec_inst & 32'h707f;
assign exe_sleep = exe_du & exe_valid;
assign exe_du = T81;
assign T81 = T83 & T82;
assign T82 = io_exe_expire ^ 1'h1;
assign T83 = exe_reg_valid & R84;
assign T85 = dec_du;
assign T355 = reset ? 1'h0 : if_valid;
assign if_valid = if_pre_valid & T86;
assign T86 = T87 ^ 1'h1;
assign T87 = exe_flush & T88;
assign T88 = io_if_tid == io_exe_tid;
assign if_pre_valid = T142 & T89;
assign T89 = T90 == 2'h0;
assign T90 = T141 ? T119 : T91;
assign T91 = T117 ? stall_count_1 : stall_count_0;
assign T356 = reset ? 2'h0 : T92;
assign T92 = T106 ? 2'h1 : T93;
assign T93 = T102 ? 2'h1 : T94;
assign T94 = T98 ? 2'h2 : T95;
assign T95 = T97 ? T96 : 2'h0;
assign T96 = stall_count_0 - 2'h1;
assign T97 = stall_count_0 != 2'h0;
assign T98 = exe_sleep & T99;
assign T99 = T100[1'h0:1'h0];
assign T100 = 1'h1 << T101;
assign T101 = io_exe_tid;
assign T102 = T103 & T99;
assign T103 = dec_reg_valid & T104;
assign T104 = dec_fence_i;
assign dec_fence_i = T105 == 32'h100f;
assign T105 = io_dec_inst & 32'h707f;
assign T106 = T1 & T99;
assign T357 = reset ? 2'h0 : T107;
assign T107 = T116 ? 2'h1 : T108;
assign T108 = T115 ? 2'h1 : T109;
assign T109 = T113 ? 2'h2 : T110;
assign T110 = T112 ? T111 : 2'h0;
assign T111 = stall_count_1 - 2'h1;
assign T112 = stall_count_1 != 2'h0;
assign T113 = exe_sleep & T114;
assign T114 = T100[1'h1:1'h1];
assign T115 = T103 & T114;
assign T116 = T1 & T114;
assign T117 = T118[1'h0:1'h0];
assign T118 = io_if_tid;
assign T119 = T140 ? stall_count_3 : stall_count_2;
assign T358 = reset ? 2'h0 : T120;
assign T120 = T129 ? 2'h1 : T121;
assign T121 = T128 ? 2'h1 : T122;
assign T122 = T126 ? 2'h2 : T123;
assign T123 = T125 ? T124 : 2'h0;
assign T124 = stall_count_2 - 2'h1;
assign T125 = stall_count_2 != 2'h0;
assign T126 = exe_sleep & T127;
assign T127 = T100[2'h2:2'h2];
assign T128 = T103 & T127;
assign T129 = T1 & T127;
assign T359 = reset ? 2'h0 : T130;
assign T130 = T139 ? 2'h1 : T131;
assign T131 = T138 ? 2'h1 : T132;
assign T132 = T136 ? 2'h2 : T133;
assign T133 = T135 ? T134 : 2'h0;
assign T134 = stall_count_3 - 2'h1;
assign T135 = stall_count_3 != 2'h0;
assign T136 = exe_sleep & T137;
assign T137 = T100[2'h3:2'h3];
assign T138 = T103 & T137;
assign T139 = T1 & T137;
assign T140 = T118[1'h0:1'h0];
assign T141 = T118[1'h1:1'h1];
assign T142 = if_reg_valid & T143;
assign T143 = T144 ^ 1'h1;
assign T144 = dec_stall & T145;
assign T145 = io_if_tid == io_dec_tid;
assign dec_stall = T146;
assign T146 = T103 ? 1'h1 : T147;
assign T147 = T152 ? 1'h1 : T148;
assign T148 = dec_reg_valid & T149;
assign T149 = dec_load;
assign dec_load = T150 | T64;
assign T150 = T151 == 32'h3;
assign T151 = io_dec_inst & 32'h507f;
assign T152 = dec_reg_valid & T153;
assign T153 = dec_mem_rd_data_sel == 2'h2;
assign dec_mem_rd_data_sel = {T156, T154};
assign T154 = T155 == 32'h0;
assign T155 = io_dec_inst & 32'h50;
assign T156 = T157 == 32'h2000020;
assign T157 = io_dec_inst & 32'h2000064;
assign T360 = reset ? 1'h0 : next_valid;
assign next_valid = R158;
assign T361 = reset ? 1'h0 : scheduler_io_valid;
assign io_mem_rd_write = mem_rd_write;
assign mem_rd_write = mem_reg_rd_write & mem_reg_valid;
assign T362 = reset ? 1'h0 : exe_valid;
assign T159 = exe_reg_rd_write & exe_reg_valid;
assign T160 = dec_rd_write & dec_reg_valid;
assign dec_rd_write = T179 & T161;
assign T161 = dec_rd_en;
assign dec_rd_en = T162 | T11;
assign T162 = T163 | T14;
assign T163 = T164 | T30;
assign T164 = T165 | T33;
assign T165 = T166 | T36;
assign T166 = T167 | T39;
assign T167 = T170 | T168;
assign T168 = T169 == 32'h1073;
assign T169 = io_dec_inst & 32'h107f;
assign T170 = T171 | T43;
assign T171 = T172 | T79;
assign T172 = T173 | T49;
assign T173 = T174 | T52;
assign T174 = T175 | T55;
assign T175 = T176 | T58;
assign T176 = T177 | T64;
assign T177 = T178 == 32'h3;
assign T178 = io_dec_inst & 32'h506f;
assign T179 = T180 != 5'h0;
assign T180 = io_dec_inst[4'hb:3'h7];
assign io_exe_instret = exe_instret;
assign exe_instret = 1'h0;
assign io_exe_cycle = exe_cycle;
assign exe_cycle = 1'h0;
assign io_exe_sret = exe_sret;
assign exe_sret = exe_reg_sret & exe_reg_valid;
assign T181 = 1'h0;
assign io_exe_ee = exe_ee;
assign exe_ee = T182;
assign T182 = exe_valid & R183;
assign T184 = T188 & T185;
assign T185 = T186 ^ 1'h1;
assign T186 = T187;
assign T187 = io_dec_inst[5'h19:5'h19];
assign T188 = dec_ie;
assign io_exe_ie = exe_ie;
assign exe_ie = T189;
assign T189 = exe_valid & R190;
assign T191 = T194 & T192;
assign T192 = T193;
assign T193 = io_dec_inst[5'h19:5'h19];
assign T194 = dec_ie;
assign io_exe_sleep = exe_sleep;
assign io_exe_kill = exe_kill;
assign exe_kill = exe_reg_exc | exe_any_exc;
assign io_exe_cause = exe_exception_cause;
assign exe_exception_cause = T195;
assign T195 = exe_reg_exc ? T364 : T196;
assign T196 = exe_inst_exc ? T363 : exe_any_cause;
assign exe_any_cause = io_exe_exc_expire ? 5'hd : T197;
assign T197 = io_exe_int_expire ? 5'h1d : T198;
assign T198 = io_exe_int_ext ? 5'h1e : 5'h0;
assign T363 = {1'h0, exe_inst_cause};
assign exe_inst_cause = io_exe_exc_priv_inst ? 4'h3 : T199;
assign T199 = io_exe_exc_load_misaligned ? 4'h8 : T200;
assign T200 = io_exe_exc_store_misaligned ? 4'h9 : 4'h0;
assign T364 = {2'h0, exe_reg_cause};
assign T201 = dec_reg_exc ? T365 : dec_cause;
assign dec_cause = T9 ? 3'h2 : T202;
assign T202 = T7 ? 3'h6 : 3'h0;
assign T365 = {2'h0, dec_reg_cause};
assign io_exe_exception = exe_exception;
assign io_exe_csr_write = exe_csr_write;
assign exe_csr_write = exe_reg_csr_write & exe_reg_valid;
assign T203 = dec_csr;
assign dec_csr = T168 | T36;
assign io_exe_store = exe_store;
assign exe_store = exe_reg_store & exe_reg_valid;
assign T204 = dec_store;
assign dec_store = T207 | T205;
assign T205 = T206 == 32'h23;
assign T206 = io_dec_inst & 32'h507f;
assign T207 = T208 == 32'h23;
assign T208 = io_dec_inst & 32'h607f;
assign io_exe_load = exe_load;
assign exe_load = exe_reg_load & exe_reg_valid;
assign T209 = dec_load;
assign io_exe_valid = exe_reg_valid;
assign io_dec_rs2_sel = dec_rs2_sel;
assign dec_rs2_sel = T210;
assign T210 = T222 ? 2'h1 : T211;
assign T211 = T218 ? 2'h2 : T212;
assign T212 = T213 ? 2'h3 : 2'h0;
assign T213 = T216 & T214;
assign T214 = T215 == io_wb_rd_addr;
assign T215 = io_dec_inst[5'h18:5'h14];
assign T216 = T217 & wb_reg_rd_write;
assign T217 = io_dec_tid == io_wb_tid;
assign T218 = T220 & T219;
assign T219 = T215 == io_mem_rd_addr;
assign T220 = T221 & mem_reg_rd_write;
assign T221 = io_dec_tid == io_mem_tid;
assign T222 = T224 & T223;
assign T223 = T215 == io_exe_rd_addr;
assign T224 = T225 & exe_reg_rd_write;
assign T225 = io_dec_tid == io_exe_tid;
assign io_dec_rs1_sel = dec_rs1_sel;
assign dec_rs1_sel = T226;
assign T226 = T234 ? 2'h1 : T227;
assign T227 = T232 ? 2'h2 : T228;
assign T228 = T229 ? 2'h3 : 2'h0;
assign T229 = T216 & T230;
assign T230 = T231 == io_wb_rd_addr;
assign T231 = io_dec_inst[5'h13:4'hf];
assign T232 = T220 & T233;
assign T233 = T231 == io_mem_rd_addr;
assign T234 = T224 & T235;
assign T235 = T231 == io_exe_rd_addr;
assign io_next_valid = next_valid;
assign io_next_tid = next_tid;
assign next_tid = R236;
assign io_next_pc_sel_0 = next_pc_sel_0;
assign next_pc_sel_0 = T237;
assign T237 = T249 ? 2'h3 : T238;
assign T238 = T244 ? 2'h2 : T239;
assign T239 = T240 ? 2'h1 : 2'h0;
assign T240 = if_pre_valid & T241;
assign T241 = T242[1'h0:1'h0];
assign T242 = 1'h1 << T243;
assign T243 = io_if_tid;
assign T244 = T248 & T245;
assign T245 = T246[1'h0:1'h0];
assign T246 = 1'h1 << T247;
assign T247 = io_exe_tid;
assign T248 = exe_brjmp | exe_du;
assign T249 = mem_reg_exception & T250;
assign T250 = T251[1'h0:1'h0];
assign T251 = 1'h1 << T252;
assign T252 = io_mem_tid;
assign io_next_pc_sel_1 = next_pc_sel_1;
assign next_pc_sel_1 = T253;
assign T253 = T260 ? 2'h3 : T254;
assign T254 = T258 ? 2'h2 : T255;
assign T255 = T256 ? 2'h1 : 2'h0;
assign T256 = if_pre_valid & T257;
assign T257 = T242[1'h1:1'h1];
assign T258 = T248 & T259;
assign T259 = T246[1'h1:1'h1];
assign T260 = mem_reg_exception & T261;
assign T261 = T251[1'h1:1'h1];
assign io_next_pc_sel_2 = next_pc_sel_2;
assign next_pc_sel_2 = T262;
assign T262 = T269 ? 2'h3 : T263;
assign T263 = T267 ? 2'h2 : T264;
assign T264 = T265 ? 2'h1 : 2'h0;
assign T265 = if_pre_valid & T266;
assign T266 = T242[2'h2:2'h2];
assign T267 = T248 & T268;
assign T268 = T246[2'h2:2'h2];
assign T269 = mem_reg_exception & T270;
assign T270 = T251[2'h2:2'h2];
assign io_next_pc_sel_3 = next_pc_sel_3;
assign next_pc_sel_3 = T271;
assign T271 = T278 ? 2'h3 : T272;
assign T272 = T276 ? 2'h2 : T273;
assign T273 = T274 ? 2'h1 : 2'h0;
assign T274 = if_pre_valid & T275;
assign T275 = T242[2'h3:2'h3];
assign T276 = T248 & T277;
assign T277 = T246[2'h3:2'h3];
assign T278 = mem_reg_exception & T279;
assign T279 = T251[2'h3:2'h3];
assign io_mem_rd_data_sel = mem_reg_rd_data_sel;
assign io_exe_mem_type = exe_reg_mem_type;
assign dec_mem_type = {T289, T281};
assign T281 = {T287, T282};
assign T282 = {T285, T283};
assign T283 = T284 == 32'h1000;
assign T284 = io_dec_inst & 32'h1000;
assign T285 = T286 == 32'h2000;
assign T286 = io_dec_inst & 32'h2000;
assign T287 = T288 == 32'h4000;
assign T288 = io_dec_inst & 32'h4000;
assign T289 = T290 == 32'h20;
assign T290 = io_dec_inst & 32'h20;
assign io_exe_rd_data_sel = exe_reg_rd_data_sel;
assign dec_exe_rd_data_sel = {T293, T291};
assign T291 = T292 == 32'h40;
assign T292 = io_dec_inst & 32'h44;
assign T293 = T294 == 32'h0;
assign T294 = io_dec_inst & 32'h10;
assign io_exe_mul_type = exe_reg_mul_type;
assign dec_mul_type = {T285, T283};
assign io_exe_csr_type = exe_reg_csr_type;
assign dec_csr_type = {T285, T283};
assign io_exe_br_type = exe_reg_br_type;
assign dec_br_type = {T285, T295};
assign T295 = {T296, T283};
assign T296 = T297 == 32'h4000;
assign T297 = io_dec_inst & 32'h6000;
assign io_exe_alu_type = exe_reg_alu_type;
assign dec_alu_type = {T306, T298};
assign T298 = {T304, T299};
assign T299 = {T302, T300};
assign T300 = T301 == 32'h1010;
assign T301 = io_dec_inst & 32'h1054;
assign T302 = T303 == 32'h2010;
assign T303 = io_dec_inst & 32'h2054;
assign T304 = T305 == 32'h4010;
assign T305 = io_dec_inst & 32'h4054;
assign T306 = T309 | T307;
assign T307 = T308 == 32'h40001010;
assign T308 = io_dec_inst & 32'h40003054;
assign T309 = T312 | T310;
assign T310 = T311 == 32'h40000030;
assign T311 = io_dec_inst & 32'h40003034;
assign T312 = T313 == 32'h2010;
assign T313 = io_dec_inst & 32'h6054;
assign io_dec_op2_sel = dec_op2_sel;
assign dec_op2_sel = {T322, T314};
assign T314 = T317 | T315;
assign T315 = T316 == 32'h4020;
assign T316 = io_dec_inst & 32'h4064;
assign T317 = T320 | T318;
assign T318 = T319 == 32'h40;
assign T319 = io_dec_inst & 32'h60;
assign T320 = T321 == 32'h30;
assign T321 = io_dec_inst & 32'h74;
assign T322 = T325 | T323;
assign T323 = T324 == 32'h6000;
assign T324 = io_dec_inst & 32'h6050;
assign T325 = T318 | T326;
assign T326 = T327 == 32'h50;
assign T327 = io_dec_inst & 32'h4050;
assign io_dec_op1_sel = dec_op1_sel;
assign dec_op1_sel = {T336, T328};
assign T328 = T331 | T329;
assign T329 = T330 == 32'h10;
assign T330 = io_dec_inst & 32'h4014;
assign T331 = T334 | T332;
assign T332 = T333 == 32'h4;
assign T333 = io_dec_inst & 32'h1c;
assign T334 = T335 == 32'h0;
assign T335 = io_dec_inst & 32'h4c;
assign T336 = T339 | T337;
assign T337 = T338 == 32'h4050;
assign T338 = io_dec_inst & 32'h4058;
assign T339 = T340 == 32'h24;
assign T340 = io_dec_inst & 32'h64;
assign io_dec_imm_sel = dec_imm_sel;
assign dec_imm_sel = {T348, T341};
assign T341 = {T345, T342};
assign T342 = T343 | T291;
assign T343 = T344 == 32'h8;
assign T344 = io_dec_inst & 32'h8;
assign T345 = T346 | T343;
assign T346 = T347 == 32'h4;
assign T347 = io_dec_inst & 32'h44;
assign T348 = T351 | T349;
assign T349 = T350 == 32'h10;
assign T350 = io_dec_inst & 32'h14;
assign T351 = T352 | T332;
assign T352 = T353 == 32'h0;
assign T353 = io_dec_inst & 32'h24;
Scheduler scheduler(.clk(clk), .reset(reset),
.io_slots_7( io_csr_slots_7 ),
.io_slots_6( io_csr_slots_6 ),
.io_slots_5( io_csr_slots_5 ),
.io_slots_4( io_csr_slots_4 ),
.io_slots_3( io_csr_slots_3 ),
.io_slots_2( io_csr_slots_2 ),
.io_slots_1( io_csr_slots_1 ),
.io_slots_0( io_csr_slots_0 ),
.io_thread_modes_3( io_csr_tmodes_3 ),
.io_thread_modes_2( io_csr_tmodes_2 ),
.io_thread_modes_1( io_csr_tmodes_1 ),
.io_thread_modes_0( io_csr_tmodes_0 ),
.io_thread( scheduler_io_thread ),
.io_valid( scheduler_io_valid )
);
always @(posedge clk) begin
exe_reg_exc <= T6;
dec_reg_exc <= io_if_exc_misaligned;
if(reset) begin
exe_reg_valid <= 1'h0;
end else begin
exe_reg_valid <= dec_valid;
end
exe_reg_branch <= T75;
exe_reg_jump <= T78;
R84 <= T85;
if(reset) begin
dec_reg_valid <= 1'h0;
end else begin
dec_reg_valid <= if_valid;
end
if(reset) begin
stall_count_0 <= 2'h0;
end else if(T106) begin
stall_count_0 <= 2'h1;
end else if(T102) begin
stall_count_0 <= 2'h1;
end else if(T98) begin
stall_count_0 <= 2'h2;
end else if(T97) begin
stall_count_0 <= T96;
end else begin
stall_count_0 <= 2'h0;
end
if(reset) begin
stall_count_1 <= 2'h0;
end else if(T116) begin
stall_count_1 <= 2'h1;
end else if(T115) begin
stall_count_1 <= 2'h1;
end else if(T113) begin
stall_count_1 <= 2'h2;
end else if(T112) begin
stall_count_1 <= T111;
end else begin
stall_count_1 <= 2'h0;
end
if(reset) begin
stall_count_2 <= 2'h0;
end else if(T129) begin
stall_count_2 <= 2'h1;
end else if(T128) begin
stall_count_2 <= 2'h1;
end else if(T126) begin
stall_count_2 <= 2'h2;
end else if(T125) begin
stall_count_2 <= T124;
end else begin
stall_count_2 <= 2'h0;
end
if(reset) begin
stall_count_3 <= 2'h0;
end else if(T139) begin
stall_count_3 <= 2'h1;
end else if(T138) begin
stall_count_3 <= 2'h1;
end else if(T136) begin
stall_count_3 <= 2'h2;
end else if(T135) begin
stall_count_3 <= T134;
end else begin
stall_count_3 <= 2'h0;
end
if(reset) begin
if_reg_valid <= 1'h0;
end else begin
if_reg_valid <= next_valid;
end
if(reset) begin
R158 <= 1'h0;
end else begin
R158 <= scheduler_io_valid;
end
if(reset) begin
mem_reg_valid <= 1'h0;
end else begin
mem_reg_valid <= exe_valid;
end
mem_reg_rd_write <= T159;
exe_reg_rd_write <= T160;
exe_reg_sret <= T181;
R183 <= T184;
R190 <= T191;
if(dec_reg_exc) begin
exe_reg_cause <= T365;
end else if(T9) begin
exe_reg_cause <= 3'h2;
end else if(T7) begin
exe_reg_cause <= 3'h6;
end else begin
exe_reg_cause <= 3'h0;
end
dec_reg_cause <= 1'h0;
exe_reg_csr_write <= T203;
exe_reg_store <= T204;
exe_reg_load <= T209;
wb_reg_rd_write <= mem_rd_write;
R236 <= scheduler_io_thread;
mem_reg_exception <= exe_exception;
mem_reg_rd_data_sel <= R280;
R280 <= dec_mem_rd_data_sel;
exe_reg_mem_type <= dec_mem_type;
exe_reg_rd_data_sel <= dec_exe_rd_data_sel;
exe_reg_mul_type <= dec_mul_type;
exe_reg_csr_type <= dec_csr_type;
exe_reg_br_type <= dec_br_type;
exe_reg_alu_type <= dec_alu_type;
end
endmodule |
module RegisterFile(input clk,
input [1:0] io_rs1_thread,
input [4:0] io_rs1_addr,
output[31:0] io_rs1_data,
input [1:0] io_rs2_thread,
input [4:0] io_rs2_addr,
output[31:0] io_rs2_data,
input [1:0] io_rd_thread,
input [4:0] io_rd_addr,
input [31:0] io_rd_data,
input io_rd_enable
);
reg [31:0] dout2;
wire[31:0] T0;
wire[31:0] T1;
reg [31:0] regfile [127:0];
wire[31:0] T2;
wire[6:0] T3;
wire[6:0] T4;
wire T5;
reg [31:0] dout1;
wire[31:0] T6;
wire[31:0] T7;
wire[6:0] T8;
wire T9;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
dout2 = {1{$random}};
for (initvar = 0; initvar < 128; initvar = initvar+1)
regfile[initvar] = {1{$random}};
dout1 = {1{$random}};
end
// synthesis translate_on
`endif
assign io_rs2_data = dout2;
assign T0 = T5 ? 32'h0 : T1;
assign T1 = regfile[T4];
assign T3 = {io_rd_addr, io_rd_thread};
assign T4 = {io_rs2_addr, io_rs2_thread};
assign T5 = io_rs2_addr == 5'h0;
assign io_rs1_data = dout1;
assign T6 = T9 ? 32'h0 : T7;
assign T7 = regfile[T8];
assign T8 = {io_rs1_addr, io_rs1_thread};
assign T9 = io_rs1_addr == 5'h0;
always @(posedge clk) begin
if(T5) begin
dout2 <= 32'h0;
end else begin
dout2 <= T1;
end
if (io_rd_enable)
regfile[T3] <= io_rd_data;
if(T9) begin
dout1 <= 32'h0;
end else begin
dout1 <= T7;
end
end
endmodule |
module Multiplier(input clk,
input [31:0] io_op1,
input [31:0] io_op2,
input [3:0] io_func,
output[31:0] io_result
);
reg [31:0] R0;
wire[31:0] result;
wire[31:0] T1;
wire[65:0] mul_result;
wire[32:0] op2;
wire[32:0] T2;
wire[32:0] T3;
wire T4;
wire[32:0] T5;
wire[32:0] T6;
wire T7;
wire T8;
wire T9;
wire[32:0] op1;
wire[32:0] T10;
wire[32:0] T11;
wire T12;
wire[32:0] T13;
wire[32:0] T14;
wire T15;
wire[31:0] T16;
wire T17;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R0 = {1{$random}};
end
// synthesis translate_on
`endif
assign io_result = R0;
assign result = T17 ? T16 : T1;
assign T1 = mul_result[6'h3f:6'h20];
assign mul_result = $signed(op1) * $signed(op2);
assign op2 = T7 ? T5 : T2;
assign T2 = T3;
assign T3 = {T4, io_op2};
assign T4 = io_op2[5'h1f:5'h1f];
assign T5 = T6;
assign T6 = {1'h0, io_op2};
assign T7 = T9 | T8;
assign T8 = io_func == 4'h3;
assign T9 = io_func == 4'h2;
assign op1 = T15 ? T13 : T10;
assign T10 = T11;
assign T11 = {T12, io_op1};
assign T12 = io_op1[5'h1f:5'h1f];
assign T13 = T14;
assign T14 = {1'h0, io_op1};
assign T15 = io_func == 4'h3;
assign T16 = mul_result[5'h1f:1'h0];
assign T17 = io_func == 4'h0;
always @(posedge clk) begin
if(T17) begin
R0 <= T16;
end else begin
R0 <= T1;
end
end
endmodule |
module LoadStore(input clk,
output[12:0] io_dmem_addr,
output io_dmem_enable,
input [31:0] io_dmem_data_out,
output io_dmem_byte_write_3,
output io_dmem_byte_write_2,
output io_dmem_byte_write_1,
output io_dmem_byte_write_0,
output[31:0] io_dmem_data_in,
//output[12:0] io_imem_r_addr
//output io_imem_r_enable
//input [31:0] io_imem_r_data_out
output[12:0] io_imem_rw_addr,
output io_imem_rw_enable,
input [31:0] io_imem_rw_data_out,
output io_imem_rw_write,
output[31:0] io_imem_rw_data_in,
output[9:0] io_bus_addr,
output io_bus_enable,
input [31:0] io_bus_data_out,
output io_bus_write,
output[31:0] io_bus_data_in,
input [31:0] io_addr,
input [1:0] io_thread,
input io_load,
input io_store,
input [3:0] io_mem_type,
input [31:0] io_data_in,
output[31:0] io_data_out,
input [3:0] io_imem_protection_7,
input [3:0] io_imem_protection_6,
input [3:0] io_imem_protection_5,
input [3:0] io_imem_protection_4,
input [3:0] io_imem_protection_3,
input [3:0] io_imem_protection_2,
input [3:0] io_imem_protection_1,
input [3:0] io_imem_protection_0,
input [3:0] io_dmem_protection_7,
input [3:0] io_dmem_protection_6,
input [3:0] io_dmem_protection_5,
input [3:0] io_dmem_protection_4,
input [3:0] io_dmem_protection_3,
input [3:0] io_dmem_protection_2,
input [3:0] io_dmem_protection_1,
input [3:0] io_dmem_protection_0,
input io_kill,
output io_load_misaligned,
output io_load_fault,
output io_store_misaligned,
output io_store_fault
);
wire store_fault;
wire store_misaligned;
wire T0;
wire T1;
wire T2;
wire T3;
wire[1:0] T4;
wire T5;
wire T6;
wire T7;
wire T8;
wire T9;
wire load_fault;
wire load_misaligned;
wire T10;
wire T11;
wire T12;
wire T13;
wire[1:0] T14;
wire T15;
wire T16;
wire T17;
wire T18;
wire T19;
wire T20;
wire T21;
wire[31:0] T22;
wire[31:0] T23;
reg imem_op_reg;
wire imem_op;
wire[2:0] T24;
wire[31:0] T25;
wire[31:0] T26;
wire[31:0] T27;
wire[31:0] T28;
wire[31:0] T29;
wire[4:0] T30;
reg [1:0] addr_byte_reg;
wire[1:0] T31;
wire[31:0] T32;
wire[15:0] T33;
wire T34;
reg [3:0] mem_type_reg;
wire[31:0] T35;
wire[15:0] T36;
wire[15:0] T37;
wire[15:0] T140;
wire T38;
wire T39;
wire[31:0] T40;
wire[7:0] T41;
wire T42;
wire[31:0] T43;
wire[7:0] T44;
wire[23:0] T45;
wire[23:0] T141;
wire T46;
wire T47;
reg dmem_op_reg;
wire dmem_op;
wire[2:0] T48;
wire T49;
wire write;
wire T50;
wire T51;
wire T52;
wire T53;
wire T54;
wire T55;
wire permission;
wire T56;
wire T57;
wire T58;
wire T59;
wire T60;
wire[3:0] T61;
wire[3:0] T62;
wire[3:0] T63;
wire T64;
wire[2:0] T65;
wire[2:0] T66;
wire[3:0] T67;
wire T68;
wire T69;
wire[3:0] T70;
wire[3:0] T71;
wire T72;
wire[3:0] T73;
wire T74;
wire T75;
wire T76;
wire T77;
wire T78;
wire[1:0] T79;
wire T80;
wire T81;
wire T82;
wire T83;
wire[3:0] T84;
wire[3:0] T85;
wire[3:0] T86;
wire T87;
wire[2:0] T88;
wire[2:0] T89;
wire[3:0] T90;
wire T91;
wire T92;
wire[3:0] T93;
wire[3:0] T94;
wire T95;
wire[3:0] T96;
wire T97;
wire T98;
wire T99;
wire T100;
wire T101;
wire[1:0] T102;
wire T103;
wire bus_op;
wire[1:0] T104;
wire T105;
wire T106;
wire[9:0] T107;
wire[7:0] T108;
wire T109;
wire T110;
wire T111;
wire[12:0] T142;
wire[10:0] T112;
wire[31:0] T113;
wire[31:0] T114;
wire[31:0] T115;
wire[15:0] T116;
wire T117;
wire[31:0] T118;
wire[15:0] T119;
wire[7:0] T120;
wire T121;
wire T122;
wire[4:0] T123;
wire[4:0] T143;
wire[3:0] T124;
wire[4:0] T125;
wire[4:0] T126;
wire[4:0] T144;
wire[3:0] T127;
wire T128;
wire[4:0] T129;
wire[1:0] T130;
wire T131;
wire[4:0] T145;
wire[3:0] T132;
wire T133;
wire T134;
wire T135;
wire T136;
wire T137;
wire T138;
wire[12:0] T139;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
imem_op_reg = {1{$random}};
addr_byte_reg = {1{$random}};
mem_type_reg = {1{$random}};
dmem_op_reg = {1{$random}};
end
// synthesis translate_on
`endif
`ifndef SYNTHESIS
// synthesis translate_off
// assign io_imem_r_enable = {1{$random}};
// assign io_imem_r_addr = {1{$random}};
// synthesis translate_on
`endif
assign io_store_fault = store_fault;
assign store_fault = 1'h0;
assign io_store_misaligned = store_misaligned;
assign store_misaligned = T0;
assign T0 = io_store & T1;
assign T1 = T6 | T2;
assign T2 = T5 & T3;
assign T3 = T4 != 2'h0;
assign T4 = io_addr[1'h1:1'h0];
assign T5 = io_mem_type == 4'ha;
assign T6 = T9 & T7;
assign T7 = T8 != 1'h0;
assign T8 = io_addr[1'h0:1'h0];
assign T9 = io_mem_type == 4'h9;
assign io_load_fault = load_fault;
assign load_fault = 1'h0;
assign io_load_misaligned = load_misaligned;
assign load_misaligned = T10;
assign T10 = io_load & T11;
assign T11 = T16 | T12;
assign T12 = T15 & T13;
assign T13 = T14 != 2'h0;
assign T14 = io_addr[1'h1:1'h0];
assign T15 = io_mem_type == 4'h2;
assign T16 = T19 & T17;
assign T17 = T18 != 1'h0;
assign T18 = io_addr[1'h0:1'h0];
assign T19 = T21 | T20;
assign T20 = io_mem_type == 4'h5;
assign T21 = io_mem_type == 4'h1;
assign io_data_out = T22;
assign T22 = dmem_op_reg ? T25 : T23;
assign T23 = imem_op_reg ? io_imem_rw_data_out : io_bus_data_out;
assign imem_op = T24 == 3'h0;
assign T24 = io_addr[5'h1f:5'h1d];
assign T25 = T47 ? T43 : T26;
assign T26 = T42 ? T40 : T27;
assign T27 = T39 ? T35 : T28;
assign T28 = T34 ? T32 : T29;
assign T29 = io_dmem_data_out >> T30;
assign T30 = {addr_byte_reg, 3'h0};
assign T31 = io_addr[1'h1:1'h0];
assign T32 = {16'h0, T33};
assign T33 = T29[4'hf:1'h0];
assign T34 = mem_type_reg == 4'h5;
assign T35 = {T37, T36};
assign T36 = T29[4'hf:1'h0];
assign T37 = 16'h0 - T140;
assign T140 = {15'h0, T38};
assign T38 = T29[4'hf:4'hf];
assign T39 = mem_type_reg == 4'h1;
assign T40 = {24'h0, T41};
assign T41 = T29[3'h7:1'h0];
assign T42 = mem_type_reg == 4'h4;
assign T43 = {T45, T44};
assign T44 = T29[3'h7:1'h0];
assign T45 = 24'h0 - T141;
assign T141 = {23'h0, T46};
assign T46 = T29[3'h7:3'h7];
assign T47 = mem_type_reg == 4'h0;
assign dmem_op = T48 == 3'h1;
assign T48 = io_addr[5'h1f:5'h1d];
assign io_bus_data_in = io_data_in;
assign io_bus_write = T49;
assign T49 = bus_op & write;
assign write = T51 & T50;
assign T50 = io_kill ^ 1'h1;
assign T51 = T53 & T52;
assign T52 = store_fault ^ 1'h1;
assign T53 = T55 & T54;
assign T54 = store_misaligned ^ 1'h1;
assign T55 = io_store & permission;
assign permission = T56;
assign T56 = T57 | bus_op;
assign T57 = T81 | T58;
assign T58 = imem_op & T59;
assign T59 = T77 & T60;
assign T60 = T61 != 4'hc;
assign T61 = T76 ? T70 : T62;
assign T62 = T69 ? T67 : T63;
assign T63 = T64 ? io_imem_protection_1 : io_imem_protection_0;
assign T64 = T65[1'h0:1'h0];
assign T65 = T66;
assign T66 = io_addr[4'he:4'hc];
assign T67 = T68 ? io_imem_protection_3 : io_imem_protection_2;
assign T68 = T65[1'h0:1'h0];
assign T69 = T65[1'h1:1'h1];
assign T70 = T75 ? T73 : T71;
assign T71 = T72 ? io_imem_protection_5 : io_imem_protection_4;
assign T72 = T65[1'h0:1'h0];
assign T73 = T74 ? io_imem_protection_7 : io_imem_protection_6;
assign T74 = T65[1'h0:1'h0];
assign T75 = T65[1'h1:1'h1];
assign T76 = T65[2'h2:2'h2];
assign T77 = T80 | T78;
assign T78 = T79 == io_thread;
assign T79 = T61[1'h1:1'h0];
assign T80 = T61 == 4'h8;
assign T81 = dmem_op & T82;
assign T82 = T100 & T83;
assign T83 = T84 != 4'hc;
assign T84 = T99 ? T93 : T85;
assign T85 = T92 ? T90 : T86;
assign T86 = T87 ? io_dmem_protection_1 : io_dmem_protection_0;
assign T87 = T88[1'h0:1'h0];
assign T88 = T89;
assign T89 = io_addr[4'he:4'hc];
assign T90 = T91 ? io_dmem_protection_3 : io_dmem_protection_2;
assign T91 = T88[1'h0:1'h0];
assign T92 = T88[1'h1:1'h1];
assign T93 = T98 ? T96 : T94;
assign T94 = T95 ? io_dmem_protection_5 : io_dmem_protection_4;
assign T95 = T88[1'h0:1'h0];
assign T96 = T97 ? io_dmem_protection_7 : io_dmem_protection_6;
assign T97 = T88[1'h0:1'h0];
assign T98 = T88[1'h1:1'h1];
assign T99 = T88[2'h2:2'h2];
assign T100 = T103 | T101;
assign T101 = T102 == io_thread;
assign T102 = T84[1'h1:1'h0];
assign T103 = T84 == 4'h8;
assign bus_op = T104 == 2'h1;
assign T104 = io_addr[5'h1f:5'h1e];
assign io_bus_enable = T105;
assign T105 = bus_op & T106;
assign T106 = io_load | io_store;
assign io_bus_addr = T107;
assign T107 = {io_thread, T108};
assign T108 = io_addr[3'h7:1'h0];
assign io_imem_rw_data_in = io_data_in;
assign io_imem_rw_write = T109;
assign T109 = imem_op & write;
assign io_imem_rw_enable = T110;
assign T110 = imem_op & T111;
assign T111 = io_load | io_store;
assign io_imem_rw_addr = T142;
assign T142 = {2'h0, T112};
assign T112 = io_addr[4'hc:2'h2];
assign io_dmem_data_in = T113;
assign T113 = T121 ? T118 : T114;
assign T114 = T117 ? T115 : io_data_in;
assign T115 = {T116, T116};
assign T116 = io_data_in[4'hf:1'h0];
assign T117 = io_mem_type == 4'h9;
assign T118 = {T119, T119};
assign T119 = {T120, T120};
assign T120 = io_data_in[3'h7:1'h0];
assign T121 = io_mem_type == 4'h8;
assign io_dmem_byte_write_0 = T122;
assign T122 = T123[1'h0:1'h0];
assign T123 = T125 & T143;
assign T143 = {1'h0, T124};
assign T124 = write ? 4'hf : 4'h0;
assign T125 = T133 ? T145 : T126;
assign T126 = T131 ? T129 : T144;
assign T144 = {1'h0, T127};
assign T127 = T128 ? 4'hf : 4'h0;
assign T128 = io_mem_type == 4'ha;
assign T129 = 2'h3 << T130;
assign T130 = io_addr[1'h1:1'h0];
assign T131 = io_mem_type == 4'h9;
assign T145 = {1'h0, T132};
assign T132 = 1'h1 << T130;
assign T133 = io_mem_type == 4'h8;
assign io_dmem_byte_write_1 = T134;
assign T134 = T123[1'h1:1'h1];
assign io_dmem_byte_write_2 = T135;
assign T135 = T123[2'h2:2'h2];
assign io_dmem_byte_write_3 = T136;
assign T136 = T123[2'h3:2'h3];
assign io_dmem_enable = T137;
assign T137 = dmem_op & T138;
assign T138 = io_load | io_store;
assign io_dmem_addr = T139;
assign T139 = io_addr[4'he:2'h2];
always @(posedge clk) begin
imem_op_reg <= imem_op;
addr_byte_reg <= T31;
mem_type_reg <= io_mem_type;
dmem_op_reg <= dmem_op;
end
endmodule |
module CSR(input clk, input reset,
input [11:0] io_rw_addr,
input [1:0] io_rw_thread,
input [1:0] io_rw_csr_type,
input io_rw_write,
input [31:0] io_rw_data_in,
output[31:0] io_rw_data_out,
input io_rw_valid,
output[3:0] io_slots_7,
output[3:0] io_slots_6,
output[3:0] io_slots_5,
output[3:0] io_slots_4,
output[3:0] io_slots_3,
output[3:0] io_slots_2,
output[3:0] io_slots_1,
output[3:0] io_slots_0,
output[1:0] io_tmodes_3,
output[1:0] io_tmodes_2,
output[1:0] io_tmodes_1,
output[1:0] io_tmodes_0,
input io_kill,
input io_exception,
input [31:0] io_epc,
input [4:0] io_cause,
output[31:0] io_evecs_3,
output[31:0] io_evecs_2,
output[31:0] io_evecs_1,
output[31:0] io_evecs_0,
input io_sleep,
input io_ie,
input io_ee,
output io_expire,
input [1:0] io_dec_tid,
input io_sret,
output[31:0] io_host_to_host,
input io_gpio_in_3,
input io_gpio_in_2,
input io_gpio_in_1,
input io_gpio_in_0,
output[1:0] io_gpio_out_3,
output[1:0] io_gpio_out_2,
output[1:0] io_gpio_out_1,
output[1:0] io_gpio_out_0,
input io_int_exts_3,
input io_int_exts_2,
input io_int_exts_1,
input io_int_exts_0,
output[3:0] io_imem_protection_7,
output[3:0] io_imem_protection_6,
output[3:0] io_imem_protection_5,
output[3:0] io_imem_protection_4,
output[3:0] io_imem_protection_3,
output[3:0] io_imem_protection_2,
output[3:0] io_imem_protection_1,
output[3:0] io_imem_protection_0,
output[3:0] io_dmem_protection_7,
output[3:0] io_dmem_protection_6,
output[3:0] io_dmem_protection_5,
output[3:0] io_dmem_protection_4,
output[3:0] io_dmem_protection_3,
output[3:0] io_dmem_protection_2,
output[3:0] io_dmem_protection_1,
output[3:0] io_dmem_protection_0,
input io_cycle,
input io_instret,
output io_int_expire,
output io_exc_expire,
output io_int_ext,
output io_priv_fault
);
wire priv_fault;
wire int_ext;
wire T0;
wire T1;
wire T2;
reg reg_msip_0;
wire T612;
wire T3;
wire T4;
wire T5;
wire T6;
wire T7;
wire T8;
wire T9;
wire[35:0] data_in;
wire[35:0] T10;
wire[35:0] T613;
wire[31:0] T11;
wire T12;
wire[35:0] T13;
wire[35:0] T614;
wire[31:0] T14;
wire[35:0] data_out;
wire[35:0] T15;
wire[35:0] T16;
wire[35:0] T17;
wire[35:0] T18;
wire[35:0] T19;
wire[35:0] T20;
wire[35:0] T21;
wire[35:0] T22;
wire[35:0] T23;
wire[35:0] T24;
wire[35:0] T25;
wire[35:0] T26;
wire[35:0] T27;
wire[35:0] T28;
wire[35:0] T29;
wire[35:0] T30;
wire[35:0] T31;
wire[35:0] T32;
wire[35:0] T615;
wire[31:0] T33;
wire[31:0] T34;
wire[31:0] T35;
wire[31:0] T36;
wire[31:0] T37;
wire[15:0] T38;
wire[7:0] T39;
reg [3:0] reg_slots_0;
wire[3:0] T616;
wire[3:0] T40;
wire[3:0] T41;
wire T42;
wire T43;
wire write;
wire T44;
wire T45;
wire T46;
reg [3:0] reg_slots_1;
wire[3:0] T617;
wire[3:0] T47;
wire[3:0] T48;
wire[7:0] T49;
reg [3:0] reg_slots_2;
wire[3:0] T618;
wire[3:0] T50;
wire[3:0] T51;
reg [3:0] reg_slots_3;
wire[3:0] T619;
wire[3:0] T52;
wire[3:0] T53;
wire[15:0] T54;
wire[7:0] T55;
reg [3:0] reg_slots_4;
wire[3:0] T620;
wire[3:0] T56;
wire[3:0] T57;
reg [3:0] reg_slots_5;
wire[3:0] T621;
wire[3:0] T58;
wire[3:0] T59;
wire[7:0] T60;
reg [3:0] reg_slots_6;
wire[3:0] T622;
wire[3:0] T61;
wire[3:0] T62;
reg [3:0] reg_slots_7;
wire[3:0] T623;
wire[3:0] T63;
wire[3:0] T64;
wire T65;
wire[31:0] T66;
wire T67;
wire[31:0] T68;
wire[7:0] T69;
wire[7:0] T70;
wire[3:0] T71;
reg [1:0] reg_tmodes_0;
wire[1:0] T624;
wire[1:0] T72;
wire[1:0] T73;
wire[1:0] T74;
wire[1:0] T75;
wire T76;
wire T77;
wire[1:0] T78;
wire[1:0] T79;
wire[1:0] T80;
wire T81;
wire[1:0] T82;
wire[1:0] T83;
reg [1:0] reg_tmodes_2;
wire[1:0] T625;
wire[1:0] T84;
wire[1:0] T85;
wire[1:0] T86;
wire[1:0] T87;
wire T88;
wire T89;
wire[3:0] T90;
wire sleep;
wire[1:0] T91;
wire wake_2;
wire T92;
wire T93;
wire expired_2;
wire T94;
wire T95;
wire[31:0] T96;
reg [31:0] reg_compare_2;
wire[31:0] T97;
wire[31:0] T98;
wire T99;
wire T100;
wire[3:0] T101;
wire[1:0] T102;
wire T103;
wire T104;
wire[31:0] T105;
reg [63:0] reg_time;
wire[63:0] T626;
wire[63:0] T106;
wire T107;
reg [1:0] reg_timer_2;
wire[1:0] T627;
wire[1:0] T108;
wire[1:0] T109;
wire[1:0] T110;
wire[1:0] T111;
wire[1:0] T112;
wire[1:0] T113;
wire[1:0] T114;
wire T115;
wire T116;
wire[3:0] T117;
wire[1:0] T118;
wire T119;
wire T120;
wire T121;
wire T122;
wire T123;
wire T124;
wire expired_0;
wire T125;
wire T126;
wire[31:0] T127;
reg [31:0] reg_compare_0;
wire[31:0] T128;
wire T129;
wire T130;
wire[31:0] T131;
wire expired_1;
wire T132;
wire T133;
wire[31:0] T134;
reg [31:0] reg_compare_1;
wire[31:0] T135;
wire T136;
wire T137;
wire[31:0] T138;
wire T139;
wire[1:0] T140;
wire T141;
wire expired_3;
wire T142;
wire T143;
wire[31:0] T144;
reg [31:0] reg_compare_3;
wire[31:0] T145;
wire T146;
wire T147;
wire[31:0] T148;
wire T149;
wire T150;
wire T151;
wire T152;
wire[1:0] T153;
wire[1:0] T154;
reg [1:0] reg_timer_0;
wire[1:0] T628;
wire[1:0] T155;
wire[1:0] T156;
wire[1:0] T157;
wire[1:0] T158;
wire[1:0] T159;
wire[1:0] T160;
wire[1:0] T161;
wire T162;
wire T163;
wire T164;
wire T165;
wire T166;
wire T167;
wire T168;
wire T169;
wire T170;
wire T171;
wire T172;
wire T173;
reg [1:0] reg_timer_1;
wire[1:0] T629;
wire[1:0] T174;
wire[1:0] T175;
wire[1:0] T176;
wire[1:0] T177;
wire[1:0] T178;
wire[1:0] T179;
wire[1:0] T180;
wire T181;
wire T182;
wire T183;
wire T184;
wire T185;
wire T186;
wire T187;
wire T188;
wire T189;
wire T190;
wire[1:0] T191;
reg [1:0] reg_timer_3;
wire[1:0] T630;
wire[1:0] T192;
wire[1:0] T193;
wire[1:0] T194;
wire[1:0] T195;
wire[1:0] T196;
wire[1:0] T197;
wire[1:0] T198;
wire T199;
wire T200;
wire T201;
wire T202;
wire T203;
wire T204;
wire T205;
wire T206;
wire T207;
wire T208;
wire T209;
wire T210;
wire T211;
reg [1:0] reg_tmodes_3;
wire[1:0] T631;
wire[1:0] T212;
wire[1:0] T213;
wire[1:0] T214;
wire[1:0] T215;
wire T216;
wire T217;
wire[1:0] T218;
wire wake_3;
wire T219;
wire T220;
wire T221;
wire T222;
wire T223;
wire[1:0] T224;
wire wake_0;
wire T225;
reg [1:0] reg_tmodes_1;
wire[1:0] T632;
wire[1:0] T226;
wire[1:0] T227;
wire[1:0] T228;
wire[1:0] T229;
wire T230;
wire T231;
wire[1:0] T232;
wire wake_1;
wire T233;
wire[3:0] T234;
wire T235;
wire[35:0] T236;
wire[35:0] T237;
reg [35:0] reg_evecs_0;
wire[35:0] T238;
wire T239;
wire T240;
wire[3:0] T241;
wire[1:0] T242;
wire T243;
wire T244;
reg [35:0] reg_evecs_1;
wire[35:0] T245;
wire T246;
wire T247;
wire T248;
wire[35:0] T249;
reg [35:0] reg_evecs_2;
wire[35:0] T250;
wire T251;
wire T252;
reg [35:0] reg_evecs_3;
wire[35:0] T253;
wire T254;
wire T255;
wire T256;
wire T257;
wire T258;
wire[35:0] T633;
wire[31:0] T259;
wire[31:0] T260;
reg [31:0] reg_epcs_0;
wire[31:0] T261;
wire T262;
wire T263;
wire[3:0] T264;
wire[1:0] T265;
reg [31:0] reg_epcs_1;
wire[31:0] T266;
wire T267;
wire T268;
wire T269;
wire[31:0] T270;
reg [31:0] reg_epcs_2;
wire[31:0] T271;
wire T272;
wire T273;
reg [31:0] reg_epcs_3;
wire[31:0] T274;
wire T275;
wire T276;
wire T277;
wire T278;
wire T279;
wire[35:0] T634;
wire[31:0] T280;
wire[30:0] T281;
wire[3:0] T282;
wire[4:0] T283;
wire[4:0] T284;
reg [4:0] reg_causes_0;
wire[4:0] T285;
wire T286;
wire T287;
wire[3:0] T288;
wire[1:0] T289;
reg [4:0] reg_causes_1;
wire[4:0] T290;
wire T291;
wire T292;
wire T293;
wire[4:0] T294;
reg [4:0] reg_causes_2;
wire[4:0] T295;
wire T296;
wire T297;
reg [4:0] reg_causes_3;
wire[4:0] T298;
wire T299;
wire T300;
wire T301;
wire T302;
wire T303;
wire T304;
wire[35:0] T305;
wire[35:0] T306;
reg [35:0] reg_sup0_0;
wire[35:0] T307;
wire T308;
wire T309;
wire[3:0] T310;
wire[1:0] T311;
wire T312;
wire T313;
reg [35:0] reg_sup0_1;
wire[35:0] T314;
wire T315;
wire T316;
wire T317;
wire[35:0] T318;
reg [35:0] reg_sup0_2;
wire[35:0] T319;
wire T320;
wire T321;
reg [35:0] reg_sup0_3;
wire[35:0] T322;
wire T323;
wire T324;
wire T325;
wire T326;
wire T327;
wire[35:0] T635;
wire[31:0] T328;
wire T329;
wire[35:0] T636;
reg [31:0] reg_to_host;
wire[31:0] T637;
wire[35:0] T638;
wire[35:0] T330;
wire[35:0] T639;
wire T331;
wire T332;
wire T333;
wire[35:0] T640;
wire[31:0] T334;
reg reg_gpis_0;
wire T335;
wire[35:0] T641;
wire[31:0] T336;
reg reg_gpis_1;
wire T337;
wire[35:0] T642;
wire[31:0] T338;
reg reg_gpis_2;
wire T339;
wire[35:0] T643;
wire[31:0] T340;
reg reg_gpis_3;
wire T341;
wire[35:0] T644;
wire[31:0] T342;
reg [1:0] reg_gpos_0;
wire[1:0] T645;
wire[1:0] T343;
wire[1:0] T344;
wire T345;
wire T346;
wire T347;
reg [3:0] reg_gpo_protection_0;
wire[3:0] T646;
wire[3:0] T348;
wire[3:0] T349;
wire T350;
wire T351;
wire T352;
wire T353;
wire[1:0] T354;
wire T355;
wire T356;
wire T357;
wire T358;
wire[35:0] T647;
wire[31:0] T359;
reg [1:0] reg_gpos_1;
wire[1:0] T648;
wire[1:0] T360;
wire[1:0] T361;
wire T362;
wire T363;
wire T364;
reg [3:0] reg_gpo_protection_1;
wire[3:0] T649;
wire[3:0] T365;
wire[3:0] T366;
wire T367;
wire T368;
wire[1:0] T369;
wire T370;
wire T371;
wire T372;
wire T373;
wire[35:0] T650;
wire[31:0] T374;
reg [1:0] reg_gpos_2;
wire[1:0] T651;
wire[1:0] T375;
wire[1:0] T376;
wire T377;
wire T378;
wire T379;
reg [3:0] reg_gpo_protection_2;
wire[3:0] T652;
wire[3:0] T380;
wire[3:0] T381;
wire T382;
wire T383;
wire[1:0] T384;
wire T385;
wire T386;
wire T387;
wire T388;
wire[35:0] T653;
wire[31:0] T389;
reg [1:0] reg_gpos_3;
wire[1:0] T654;
wire[1:0] T390;
wire[1:0] T391;
wire T392;
wire T393;
wire T394;
reg [3:0] reg_gpo_protection_3;
wire[3:0] T655;
wire[3:0] T395;
wire[3:0] T396;
wire T397;
wire T398;
wire[1:0] T399;
wire T400;
wire T401;
wire T402;
wire T403;
wire[35:0] T656;
wire[15:0] T404;
wire[15:0] T405;
wire[7:0] T406;
wire[7:0] T407;
wire T408;
wire[35:0] T657;
wire[31:0] T409;
wire[31:0] T410;
wire[15:0] T411;
wire[7:0] T412;
reg [3:0] reg_imem_protection_0;
wire[3:0] T658;
wire[3:0] T413;
wire[3:0] T414;
wire T415;
wire T416;
reg [3:0] reg_imem_protection_1;
wire[3:0] T659;
wire[3:0] T417;
wire[3:0] T418;
wire[7:0] T419;
reg [3:0] reg_imem_protection_2;
wire[3:0] T660;
wire[3:0] T420;
wire[3:0] T421;
reg [3:0] reg_imem_protection_3;
wire[3:0] T661;
wire[3:0] T422;
wire[3:0] T423;
wire[15:0] T424;
wire[7:0] T425;
reg [3:0] reg_imem_protection_4;
wire[3:0] T662;
wire[3:0] T426;
wire[3:0] T427;
reg [3:0] reg_imem_protection_5;
wire[3:0] T663;
wire[3:0] T428;
wire[3:0] T429;
wire[7:0] T430;
reg [3:0] reg_imem_protection_6;
wire[3:0] T664;
wire[3:0] T431;
wire[3:0] T432;
reg [3:0] reg_imem_protection_7;
wire[3:0] T665;
wire[3:0] T433;
wire[3:0] T434;
wire T435;
wire[35:0] T666;
wire[31:0] T436;
wire[31:0] T437;
wire[15:0] T438;
wire[7:0] T439;
reg [3:0] reg_dmem_protection_0;
wire[3:0] T667;
wire[3:0] T440;
wire[3:0] T441;
wire T442;
wire T443;
reg [3:0] reg_dmem_protection_1;
wire[3:0] T668;
wire[3:0] T444;
wire[3:0] T445;
wire[7:0] T446;
reg [3:0] reg_dmem_protection_2;
wire[3:0] T669;
wire[3:0] T447;
wire[3:0] T448;
reg [3:0] reg_dmem_protection_3;
wire[3:0] T670;
wire[3:0] T449;
wire[3:0] T450;
wire[15:0] T451;
wire[7:0] T452;
reg [3:0] reg_dmem_protection_4;
wire[3:0] T671;
wire[3:0] T453;
wire[3:0] T454;
reg [3:0] reg_dmem_protection_5;
wire[3:0] T672;
wire[3:0] T455;
wire[3:0] T456;
wire[7:0] T457;
reg [3:0] reg_dmem_protection_6;
wire[3:0] T673;
wire[3:0] T458;
wire[3:0] T459;
reg [3:0] reg_dmem_protection_7;
wire[3:0] T674;
wire[3:0] T460;
wire[3:0] T461;
wire T462;
wire[35:0] T463;
wire[35:0] T464;
wire[35:0] status_0;
wire[35:0] T465;
wire[7:0] T466;
wire[4:0] T467;
wire[3:0] T468;
reg reg_ie_0;
wire T675;
wire T469;
wire T470;
wire T471;
wire T472;
wire T473;
wire T474;
wire[3:0] T475;
wire[1:0] T476;
wire T477;
wire T478;
wire[2:0] T479;
reg [1:0] reg_prv_0;
wire[1:0] T676;
reg reg_ie1_0;
wire T677;
wire[27:0] T480;
wire[22:0] T481;
wire[21:0] T482;
reg [1:0] reg_prv1_0;
wire[1:0] T678;
reg reg_mtie_0;
wire T679;
wire T483;
wire T484;
wire T485;
wire T486;
wire T487;
wire T488;
wire[3:0] T489;
wire[1:0] T490;
wire T491;
wire[35:0] status_1;
wire[35:0] T492;
wire[7:0] T493;
wire[4:0] T494;
wire[3:0] T495;
reg reg_ie_1;
wire T680;
wire T496;
wire T497;
wire T498;
wire T499;
wire[2:0] T500;
reg [1:0] reg_prv_1;
wire[1:0] T681;
reg reg_ie1_1;
wire T682;
wire[27:0] T501;
wire[22:0] T502;
wire[21:0] T503;
reg [1:0] reg_prv1_1;
wire[1:0] T683;
reg reg_mtie_1;
wire T684;
wire T504;
wire T505;
wire T506;
wire T507;
wire T508;
wire T509;
wire[1:0] T510;
wire[35:0] T511;
wire[35:0] status_2;
wire[35:0] T512;
wire[7:0] T513;
wire[4:0] T514;
wire[3:0] T515;
reg reg_msip_2;
wire T685;
wire T516;
wire T517;
wire T518;
wire T519;
wire T520;
wire T521;
wire T522;
wire[3:0] T523;
wire[1:0] T524;
wire T525;
wire T526;
wire T527;
wire T528;
reg reg_ie_2;
wire T686;
wire T529;
wire T530;
wire T531;
wire T532;
wire[2:0] T533;
reg [1:0] reg_prv_2;
wire[1:0] T687;
reg reg_ie1_2;
wire T688;
wire[27:0] T534;
wire[22:0] T535;
wire[21:0] T536;
reg [1:0] reg_prv1_2;
wire[1:0] T689;
reg reg_mtie_2;
wire T690;
wire T537;
wire T538;
wire T539;
wire T540;
wire T541;
wire[35:0] status_3;
wire[35:0] T542;
wire[7:0] T543;
wire[4:0] T544;
wire[3:0] T545;
reg reg_msip_3;
wire T691;
wire T546;
wire T547;
wire T548;
wire T549;
wire T550;
wire T551;
wire T552;
wire T553;
wire T554;
wire T555;
wire T556;
reg reg_ie_3;
wire T692;
wire T557;
wire T558;
wire T559;
wire T560;
wire[2:0] T561;
reg [1:0] reg_prv_3;
wire[1:0] T693;
reg reg_ie1_3;
wire T694;
wire[27:0] T562;
wire[22:0] T563;
wire[21:0] T564;
reg [1:0] reg_prv1_3;
wire[1:0] T695;
reg reg_mtie_3;
wire T696;
wire T565;
wire T566;
wire T567;
wire T568;
wire T569;
wire T570;
wire T571;
wire T572;
wire T573;
wire[35:0] T574;
wire[35:0] T697;
wire T575;
wire T576;
wire T577;
wire T578;
wire T579;
wire T580;
wire T581;
reg reg_msip_1;
wire T698;
wire T582;
wire T583;
wire T584;
wire T585;
wire T586;
wire T587;
wire T588;
wire T589;
wire T590;
wire T591;
wire T592;
wire T593;
wire T594;
wire T595;
wire T596;
wire T597;
wire T598;
wire T599;
wire T600;
wire T601;
wire T602;
wire exc_expire;
wire int_expire;
wire T603;
wire T604;
wire T605;
wire T606;
wire T607;
wire T608;
wire T609;
wire T610;
wire T611;
wire[31:0] T699;
wire[31:0] T700;
wire[31:0] T701;
wire[31:0] T702;
wire[31:0] T703;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
reg_msip_0 = {1{$random}};
reg_slots_0 = {1{$random}};
reg_slots_1 = {1{$random}};
reg_slots_2 = {1{$random}};
reg_slots_3 = {1{$random}};
reg_slots_4 = {1{$random}};
reg_slots_5 = {1{$random}};
reg_slots_6 = {1{$random}};
reg_slots_7 = {1{$random}};
reg_tmodes_0 = {1{$random}};
reg_tmodes_2 = {1{$random}};
reg_compare_2 = {1{$random}};
reg_time = {2{$random}};
reg_timer_2 = {1{$random}};
reg_compare_0 = {1{$random}};
reg_compare_1 = {1{$random}};
reg_compare_3 = {1{$random}};
reg_timer_0 = {1{$random}};
reg_timer_1 = {1{$random}};
reg_timer_3 = {1{$random}};
reg_tmodes_3 = {1{$random}};
reg_tmodes_1 = {1{$random}};
reg_evecs_0 = {2{$random}};
reg_evecs_1 = {2{$random}};
reg_evecs_2 = {2{$random}};
reg_evecs_3 = {2{$random}};
reg_epcs_0 = {1{$random}};
reg_epcs_1 = {1{$random}};
reg_epcs_2 = {1{$random}};
reg_epcs_3 = {1{$random}};
reg_causes_0 = {1{$random}};
reg_causes_1 = {1{$random}};
reg_causes_2 = {1{$random}};
reg_causes_3 = {1{$random}};
reg_sup0_0 = {2{$random}};
reg_sup0_1 = {2{$random}};
reg_sup0_2 = {2{$random}};
reg_sup0_3 = {2{$random}};
reg_to_host = {1{$random}};
reg_gpis_0 = {1{$random}};
reg_gpis_1 = {1{$random}};
reg_gpis_2 = {1{$random}};
reg_gpis_3 = {1{$random}};
reg_gpos_0 = {1{$random}};
reg_gpo_protection_0 = {1{$random}};
reg_gpos_1 = {1{$random}};
reg_gpo_protection_1 = {1{$random}};
reg_gpos_2 = {1{$random}};
reg_gpo_protection_2 = {1{$random}};
reg_gpos_3 = {1{$random}};
reg_gpo_protection_3 = {1{$random}};
reg_imem_protection_0 = {1{$random}};
reg_imem_protection_1 = {1{$random}};
reg_imem_protection_2 = {1{$random}};
reg_imem_protection_3 = {1{$random}};
reg_imem_protection_4 = {1{$random}};
reg_imem_protection_5 = {1{$random}};
reg_imem_protection_6 = {1{$random}};
reg_imem_protection_7 = {1{$random}};
reg_dmem_protection_0 = {1{$random}};
reg_dmem_protection_1 = {1{$random}};
reg_dmem_protection_2 = {1{$random}};
reg_dmem_protection_3 = {1{$random}};
reg_dmem_protection_4 = {1{$random}};
reg_dmem_protection_5 = {1{$random}};
reg_dmem_protection_6 = {1{$random}};
reg_dmem_protection_7 = {1{$random}};
reg_ie_0 = {1{$random}};
reg_prv_0 = {1{$random}};
reg_ie1_0 = {1{$random}};
reg_prv1_0 = {1{$random}};
reg_mtie_0 = {1{$random}};
reg_ie_1 = {1{$random}};
reg_prv_1 = {1{$random}};
reg_ie1_1 = {1{$random}};
reg_prv1_1 = {1{$random}};
reg_mtie_1 = {1{$random}};
reg_msip_2 = {1{$random}};
reg_ie_2 = {1{$random}};
reg_prv_2 = {1{$random}};
reg_ie1_2 = {1{$random}};
reg_prv1_2 = {1{$random}};
reg_mtie_2 = {1{$random}};
reg_msip_3 = {1{$random}};
reg_ie_3 = {1{$random}};
reg_prv_3 = {1{$random}};
reg_ie1_3 = {1{$random}};
reg_prv1_3 = {1{$random}};
reg_mtie_3 = {1{$random}};
reg_msip_1 = {1{$random}};
end
// synthesis translate_on
`endif
assign io_priv_fault = priv_fault;
assign priv_fault = 1'h0;
assign io_int_ext = int_ext;
assign int_ext = T0;
assign T0 = T597 & T1;
assign T1 = T596 ? T594 : T2;
assign T2 = T593 ? reg_msip_1 : reg_msip_0;
assign T612 = reset ? 1'h0 : T3;
assign T3 = T581 ? 1'h1 : T4;
assign T4 = T580 ? 1'h1 : T5;
assign T5 = T579 ? 1'h1 : T6;
assign T6 = T578 ? 1'h1 : T7;
assign T7 = T576 ? T8 : reg_msip_0;
assign T8 = T9;
assign T9 = data_in[2'h3:2'h3];
assign data_in = T575 ? T574 : T10;
assign T10 = T573 ? T13 : T613;
assign T613 = {4'h0, T11};
assign T11 = T12 ? io_rw_data_in : io_rw_data_in;
assign T12 = io_rw_csr_type == 2'h1;
assign T13 = data_out & T614;
assign T614 = {4'h0, T14};
assign T14 = ~ io_rw_data_in;
assign data_out = T15;
assign T15 = T572 ? T463 : T16;
assign T16 = T462 ? T666 : T17;
assign T17 = T435 ? T657 : T18;
assign T18 = T408 ? T656 : T19;
assign T19 = T403 ? T653 : T20;
assign T20 = T388 ? T650 : T21;
assign T21 = T373 ? T647 : T22;
assign T22 = T358 ? T644 : T23;
assign T23 = T341 ? T643 : T24;
assign T24 = T339 ? T642 : T25;
assign T25 = T337 ? T641 : T26;
assign T26 = T335 ? T640 : T27;
assign T27 = T333 ? T636 : T28;
assign T28 = T329 ? T635 : T29;
assign T29 = T327 ? T305 : T30;
assign T30 = T304 ? T634 : T31;
assign T31 = T279 ? T633 : T32;
assign T32 = T258 ? T236 : T615;
assign T615 = {4'h0, T33};
assign T33 = T235 ? T68 : T34;
assign T34 = T67 ? T66 : T35;
assign T35 = T65 ? T36 : 32'h0;
assign T36 = T37;
assign T37 = {T54, T38};
assign T38 = {T49, T39};
assign T39 = {reg_slots_1, reg_slots_0};
assign T616 = reset ? 4'hf : T40;
assign T40 = T42 ? T41 : reg_slots_0;
assign T41 = data_in[2'h3:1'h0];
assign T42 = write & T43;
assign T43 = io_rw_addr == 12'h503;
assign write = T45 & T44;
assign T44 = io_kill ^ 1'h1;
assign T45 = io_rw_write & T46;
assign T46 = priv_fault ^ 1'h1;
assign T617 = reset ? 4'hf : T47;
assign T47 = T42 ? T48 : reg_slots_1;
assign T48 = data_in[3'h7:3'h4];
assign T49 = {reg_slots_3, reg_slots_2};
assign T618 = reset ? 4'hf : T50;
assign T50 = T42 ? T51 : reg_slots_2;
assign T51 = data_in[4'hb:4'h8];
assign T619 = reset ? 4'hf : T52;
assign T52 = T42 ? T53 : reg_slots_3;
assign T53 = data_in[4'hf:4'hc];
assign T54 = {T60, T55};
assign T55 = {reg_slots_5, reg_slots_4};
assign T620 = reset ? 4'hf : T56;
assign T56 = T42 ? T57 : reg_slots_4;
assign T57 = data_in[5'h13:5'h10];
assign T621 = reset ? 4'hf : T58;
assign T58 = T42 ? T59 : reg_slots_5;
assign T59 = data_in[5'h17:5'h14];
assign T60 = {reg_slots_7, reg_slots_6};
assign T622 = reset ? 4'hf : T61;
assign T61 = T42 ? T62 : reg_slots_6;
assign T62 = data_in[5'h1b:5'h18];
assign T623 = reset ? 4'h0 : T63;
assign T63 = T42 ? T64 : reg_slots_7;
assign T64 = data_in[5'h1f:5'h1c];
assign T65 = io_rw_addr == 12'h503;
assign T66 = {30'h0, io_rw_thread};
assign T67 = io_rw_addr == 12'h50b;
assign T68 = {24'h0, T69};
assign T69 = T70;
assign T70 = {T234, T71};
assign T71 = {reg_tmodes_1, reg_tmodes_0};
assign T624 = reset ? 2'h0 : T72;
assign T72 = wake_0 ? T224 : T73;
assign T73 = T222 ? T78 : T74;
assign T74 = T76 ? T75 : reg_tmodes_0;
assign T75 = data_in[1'h1:1'h0];
assign T76 = write & T77;
assign T77 = io_rw_addr == 12'h504;
assign T78 = T79 | 2'h1;
assign T79 = T221 ? T83 : T80;
assign T80 = T81 ? reg_tmodes_1 : reg_tmodes_0;
assign T81 = T82[1'h0:1'h0];
assign T82 = io_rw_thread;
assign T83 = T220 ? reg_tmodes_3 : reg_tmodes_2;
assign T625 = reset ? 2'h1 : T84;
assign T84 = wake_2 ? T91 : T85;
assign T85 = T88 ? T78 : T86;
assign T86 = T76 ? T87 : reg_tmodes_2;
assign T87 = data_in[3'h5:3'h4];
assign T88 = sleep & T89;
assign T89 = T90[2'h2:2'h2];
assign T90 = 1'h1 << T82;
assign sleep = io_sleep;
assign T91 = reg_tmodes_2 & 2'h2;
assign wake_2 = T92;
assign T92 = io_int_exts_2 ? 1'h1 : T93;
assign T93 = T107 & expired_2;
assign expired_2 = T94;
assign T94 = T95 == 1'h0;
assign T95 = T96[5'h1f:5'h1f];
assign T96 = T105 - reg_compare_2;
assign T97 = T99 ? T98 : reg_compare_2;
assign T98 = data_in[5'h1f:1'h0];
assign T99 = T103 & T100;
assign T100 = T101[2'h2:2'h2];
assign T101 = 1'h1 << T102;
assign T102 = io_rw_thread;
assign T103 = write & T104;
assign T104 = io_rw_addr == 12'h507;
assign T105 = reg_time[5'h1f:1'h0];
assign T626 = reset ? 64'h0 : T106;
assign T106 = reg_time + 64'ha;
assign T107 = reg_timer_2 == 2'h1;
assign T627 = reset ? 2'h0 : T108;
assign T108 = T211 ? 2'h0 : T109;
assign T109 = T210 ? 2'h2 : T110;
assign T110 = T121 ? 2'h0 : T111;
assign T111 = T120 ? 2'h3 : T112;
assign T112 = T93 ? 2'h0 : T113;
assign T113 = T119 ? 2'h1 : T114;
assign T114 = T115 ? 2'h0 : reg_timer_2;
assign T115 = T103 & T116;
assign T116 = T117[2'h2:2'h2];
assign T117 = 1'h1 << T118;
assign T118 = io_rw_thread;
assign T119 = io_sleep & T116;
assign T120 = io_ee & T116;
assign T121 = T122 & T116;
assign T122 = T151 & T123;
assign T123 = T150 ? T141 : T124;
assign T124 = T139 ? expired_1 : expired_0;
assign expired_0 = T125;
assign T125 = T126 == 1'h0;
assign T126 = T127[5'h1f:5'h1f];
assign T127 = T131 - reg_compare_0;
assign T128 = T129 ? T98 : reg_compare_0;
assign T129 = T103 & T130;
assign T130 = T101[1'h0:1'h0];
assign T131 = reg_time[5'h1f:1'h0];
assign expired_1 = T132;
assign T132 = T133 == 1'h0;
assign T133 = T134[5'h1f:5'h1f];
assign T134 = T138 - reg_compare_1;
assign T135 = T136 ? T98 : reg_compare_1;
assign T136 = T103 & T137;
assign T137 = T101[1'h1:1'h1];
assign T138 = reg_time[5'h1f:1'h0];
assign T139 = T140[1'h0:1'h0];
assign T140 = io_rw_thread;
assign T141 = T149 ? expired_3 : expired_2;
assign expired_3 = T142;
assign T142 = T143 == 1'h0;
assign T143 = T144[5'h1f:5'h1f];
assign T144 = T148 - reg_compare_3;
assign T145 = T146 ? T98 : reg_compare_3;
assign T146 = T103 & T147;
assign T147 = T101[2'h3:2'h3];
assign T148 = reg_time[5'h1f:1'h0];
assign T149 = T140[1'h0:1'h0];
assign T150 = T140[1'h1:1'h1];
assign T151 = io_rw_valid & T152;
assign T152 = T153 == 2'h3;
assign T153 = T209 ? T191 : T154;
assign T154 = T190 ? reg_timer_1 : reg_timer_0;
assign T628 = reset ? 2'h0 : T155;
assign T155 = T170 ? 2'h0 : T156;
assign T156 = T169 ? 2'h2 : T157;
assign T157 = T168 ? 2'h0 : T158;
assign T158 = T167 ? 2'h3 : T159;
assign T159 = T165 ? 2'h0 : T160;
assign T160 = T164 ? 2'h1 : T161;
assign T161 = T162 ? 2'h0 : reg_timer_0;
assign T162 = T103 & T163;
assign T163 = T117[1'h0:1'h0];
assign T164 = io_sleep & T163;
assign T165 = T166 & expired_0;
assign T166 = reg_timer_0 == 2'h1;
assign T167 = io_ee & T163;
assign T168 = T122 & T163;
assign T169 = io_ie & T163;
assign T170 = T171 & T163;
assign T171 = T172 & T123;
assign T172 = io_rw_valid & T173;
assign T173 = T153 == 2'h2;
assign T629 = reset ? 2'h0 : T174;
assign T174 = T189 ? 2'h0 : T175;
assign T175 = T188 ? 2'h2 : T176;
assign T176 = T187 ? 2'h0 : T177;
assign T177 = T186 ? 2'h3 : T178;
assign T178 = T184 ? 2'h0 : T179;
assign T179 = T183 ? 2'h1 : T180;
assign T180 = T181 ? 2'h0 : reg_timer_1;
assign T181 = T103 & T182;
assign T182 = T117[1'h1:1'h1];
assign T183 = io_sleep & T182;
assign T184 = T185 & expired_1;
assign T185 = reg_timer_1 == 2'h1;
assign T186 = io_ee & T182;
assign T187 = T122 & T182;
assign T188 = io_ie & T182;
assign T189 = T171 & T182;
assign T190 = T118[1'h0:1'h0];
assign T191 = T208 ? reg_timer_3 : reg_timer_2;
assign T630 = reset ? 2'h0 : T192;
assign T192 = T207 ? 2'h0 : T193;
assign T193 = T206 ? 2'h2 : T194;
assign T194 = T205 ? 2'h0 : T195;
assign T195 = T204 ? 2'h3 : T196;
assign T196 = T202 ? 2'h0 : T197;
assign T197 = T201 ? 2'h1 : T198;
assign T198 = T199 ? 2'h0 : reg_timer_3;
assign T199 = T103 & T200;
assign T200 = T117[2'h3:2'h3];
assign T201 = io_sleep & T200;
assign T202 = T203 & expired_3;
assign T203 = reg_timer_3 == 2'h1;
assign T204 = io_ee & T200;
assign T205 = T122 & T200;
assign T206 = io_ie & T200;
assign T207 = T171 & T200;
assign T208 = T118[1'h0:1'h0];
assign T209 = T118[1'h1:1'h1];
assign T210 = io_ie & T116;
assign T211 = T171 & T116;
assign T631 = reset ? 2'h1 : T212;
assign T212 = wake_3 ? T218 : T213;
assign T213 = T216 ? T78 : T214;
assign T214 = T76 ? T215 : reg_tmodes_3;
assign T215 = data_in[3'h7:3'h6];
assign T216 = sleep & T217;
assign T217 = T90[2'h3:2'h3];
assign T218 = reg_tmodes_3 & 2'h2;
assign wake_3 = T219;
assign T219 = io_int_exts_3 ? 1'h1 : T202;
assign T220 = T82[1'h0:1'h0];
assign T221 = T82[1'h1:1'h1];
assign T222 = sleep & T223;
assign T223 = T90[1'h0:1'h0];
assign T224 = reg_tmodes_0 & 2'h2;
assign wake_0 = T225;
assign T225 = io_int_exts_0 ? 1'h1 : T165;
assign T632 = reset ? 2'h1 : T226;
assign T226 = wake_1 ? T232 : T227;
assign T227 = T230 ? T78 : T228;
assign T228 = T76 ? T229 : reg_tmodes_1;
assign T229 = data_in[2'h3:2'h2];
assign T230 = sleep & T231;
assign T231 = T90[1'h1:1'h1];
assign T232 = reg_tmodes_1 & 2'h2;
assign wake_1 = T233;
assign T233 = io_int_exts_1 ? 1'h1 : T184;
assign T234 = {reg_tmodes_3, reg_tmodes_2};
assign T235 = io_rw_addr == 12'h504;
assign T236 = T257 ? T249 : T237;
assign T237 = T248 ? reg_evecs_1 : reg_evecs_0;
assign T238 = T239 ? data_in : reg_evecs_0;
assign T239 = T243 & T240;
assign T240 = T241[1'h0:1'h0];
assign T241 = 1'h1 << T242;
assign T242 = io_rw_thread;
assign T243 = write & T244;
assign T244 = io_rw_addr == 12'h508;
assign T245 = T246 ? data_in : reg_evecs_1;
assign T246 = T243 & T247;
assign T247 = T241[1'h1:1'h1];
assign T248 = T242[1'h0:1'h0];
assign T249 = T256 ? reg_evecs_3 : reg_evecs_2;
assign T250 = T251 ? data_in : reg_evecs_2;
assign T251 = T243 & T252;
assign T252 = T241[2'h2:2'h2];
assign T253 = T254 ? data_in : reg_evecs_3;
assign T254 = T243 & T255;
assign T255 = T241[2'h3:2'h3];
assign T256 = T242[1'h0:1'h0];
assign T257 = T242[1'h1:1'h1];
assign T258 = io_rw_addr == 12'h508;
assign T633 = {4'h0, T259};
assign T259 = T278 ? T270 : T260;
assign T260 = T269 ? reg_epcs_1 : reg_epcs_0;
assign T261 = T262 ? io_epc : reg_epcs_0;
assign T262 = io_exception & T263;
assign T263 = T264[1'h0:1'h0];
assign T264 = 1'h1 << T265;
assign T265 = io_rw_thread;
assign T266 = T267 ? io_epc : reg_epcs_1;
assign T267 = io_exception & T268;
assign T268 = T264[1'h1:1'h1];
assign T269 = T265[1'h0:1'h0];
assign T270 = T277 ? reg_epcs_3 : reg_epcs_2;
assign T271 = T272 ? io_epc : reg_epcs_2;
assign T272 = io_exception & T273;
assign T273 = T264[2'h2:2'h2];
assign T274 = T275 ? io_epc : reg_epcs_3;
assign T275 = io_exception & T276;
assign T276 = T264[2'h3:2'h3];
assign T277 = T265[1'h0:1'h0];
assign T278 = T265[1'h1:1'h1];
assign T279 = io_rw_addr == 12'h502;
assign T634 = {4'h0, T280};
assign T280 = {T303, T281};
assign T281 = {27'h0, T282};
assign T282 = T283[2'h3:1'h0];
assign T283 = T302 ? T294 : T284;
assign T284 = T293 ? reg_causes_1 : reg_causes_0;
assign T285 = T286 ? io_cause : reg_causes_0;
assign T286 = io_exception & T287;
assign T287 = T288[1'h0:1'h0];
assign T288 = 1'h1 << T289;
assign T289 = io_rw_thread;
assign T290 = T291 ? io_cause : reg_causes_1;
assign T291 = io_exception & T292;
assign T292 = T288[1'h1:1'h1];
assign T293 = T289[1'h0:1'h0];
assign T294 = T301 ? reg_causes_3 : reg_causes_2;
assign T295 = T296 ? io_cause : reg_causes_2;
assign T296 = io_exception & T297;
assign T297 = T288[2'h2:2'h2];
assign T298 = T299 ? io_cause : reg_causes_3;
assign T299 = io_exception & T300;
assign T300 = T288[2'h3:2'h3];
assign T301 = T289[1'h0:1'h0];
assign T302 = T289[1'h1:1'h1];
assign T303 = T283[3'h4:3'h4];
assign T304 = io_rw_addr == 12'h509;
assign T305 = T326 ? T318 : T306;
assign T306 = T317 ? reg_sup0_1 : reg_sup0_0;
assign T307 = T308 ? data_in : reg_sup0_0;
assign T308 = T312 & T309;
assign T309 = T310[1'h0:1'h0];
assign T310 = 1'h1 << T311;
assign T311 = io_rw_thread;
assign T312 = write & T313;
assign T313 = io_rw_addr == 12'h500;
assign T314 = T315 ? data_in : reg_sup0_1;
assign T315 = T312 & T316;
assign T316 = T310[1'h1:1'h1];
assign T317 = T311[1'h0:1'h0];
assign T318 = T325 ? reg_sup0_3 : reg_sup0_2;
assign T319 = T320 ? data_in : reg_sup0_2;
assign T320 = T312 & T321;
assign T321 = T310[2'h2:2'h2];
assign T322 = T323 ? data_in : reg_sup0_3;
assign T323 = T312 & T324;
assign T324 = T310[2'h3:2'h3];
assign T325 = T311[1'h0:1'h0];
assign T326 = T311[1'h1:1'h1];
assign T327 = io_rw_addr == 12'h500;
assign T635 = {4'h0, T328};
assign T328 = reg_time[5'h1f:1'h0];
assign T329 = io_rw_addr == 12'h1;
assign T636 = {4'h0, reg_to_host};
assign T637 = T638[5'h1f:1'h0];
assign T638 = reset ? 36'h0 : T330;
assign T330 = T331 ? data_in : T639;
assign T639 = {4'h0, reg_to_host};
assign T331 = write & T332;
assign T332 = io_rw_addr == 12'h51e;
assign T333 = io_rw_addr == 12'h51e;
assign T640 = {4'h0, T334};
assign T334 = {31'h0, reg_gpis_0};
assign T335 = io_rw_addr == 12'hcc0;
assign T641 = {4'h0, T336};
assign T336 = {31'h0, reg_gpis_1};
assign T337 = io_rw_addr == 12'hcc1;
assign T642 = {4'h0, T338};
assign T338 = {31'h0, reg_gpis_2};
assign T339 = io_rw_addr == 12'hcc2;
assign T643 = {4'h0, T340};
assign T340 = {31'h0, reg_gpis_3};
assign T341 = io_rw_addr == 12'hcc3;
assign T644 = {4'h0, T342};
assign T342 = {30'h0, reg_gpos_0};
assign T645 = reset ? 2'h0 : T343;
assign T343 = T345 ? T344 : reg_gpos_0;
assign T344 = data_in[1'h1:1'h0];
assign T345 = T356 & T346;
assign T346 = T352 & T347;
assign T347 = reg_gpo_protection_0 != 4'hc;
assign T646 = reset ? 4'h0 : T348;
assign T348 = T350 ? T349 : reg_gpo_protection_0;
assign T349 = data_in[2'h3:1'h0];
assign T350 = write & T351;
assign T351 = io_rw_addr == 12'h50d;
assign T352 = T355 | T353;
assign T353 = T354 == io_rw_thread;
assign T354 = reg_gpo_protection_0[1'h1:1'h0];
assign T355 = reg_gpo_protection_0 == 4'h8;
assign T356 = write & T357;
assign T357 = io_rw_addr == 12'hcc4;
assign T358 = io_rw_addr == 12'hcc4;
assign T647 = {4'h0, T359};
assign T359 = {30'h0, reg_gpos_1};
assign T648 = reset ? 2'h0 : T360;
assign T360 = T362 ? T361 : reg_gpos_1;
assign T361 = data_in[1'h1:1'h0];
assign T362 = T371 & T363;
assign T363 = T367 & T364;
assign T364 = reg_gpo_protection_1 != 4'hc;
assign T649 = reset ? 4'h8 : T365;
assign T365 = T350 ? T366 : reg_gpo_protection_1;
assign T366 = data_in[3'h7:3'h4];
assign T367 = T370 | T368;
assign T368 = T369 == io_rw_thread;
assign T369 = reg_gpo_protection_1[1'h1:1'h0];
assign T370 = reg_gpo_protection_1 == 4'h8;
assign T371 = write & T372;
assign T372 = io_rw_addr == 12'hcc5;
assign T373 = io_rw_addr == 12'hcc5;
assign T650 = {4'h0, T374};
assign T374 = {30'h0, reg_gpos_2};
assign T651 = reset ? 2'h0 : T375;
assign T375 = T377 ? T376 : reg_gpos_2;
assign T376 = data_in[1'h1:1'h0];
assign T377 = T386 & T378;
assign T378 = T382 & T379;
assign T379 = reg_gpo_protection_2 != 4'hc;
assign T652 = reset ? 4'h8 : T380;
assign T380 = T350 ? T381 : reg_gpo_protection_2;
assign T381 = data_in[4'hb:4'h8];
assign T382 = T385 | T383;
assign T383 = T384 == io_rw_thread;
assign T384 = reg_gpo_protection_2[1'h1:1'h0];
assign T385 = reg_gpo_protection_2 == 4'h8;
assign T386 = write & T387;
assign T387 = io_rw_addr == 12'hcc6;
assign T388 = io_rw_addr == 12'hcc6;
assign T653 = {4'h0, T389};
assign T389 = {30'h0, reg_gpos_3};
assign T654 = reset ? 2'h0 : T390;
assign T390 = T392 ? T391 : reg_gpos_3;
assign T391 = data_in[1'h1:1'h0];
assign T392 = T401 & T393;
assign T393 = T397 & T394;
assign T394 = reg_gpo_protection_3 != 4'hc;
assign T655 = reset ? 4'h8 : T395;
assign T395 = T350 ? T396 : reg_gpo_protection_3;
assign T396 = data_in[4'hf:4'hc];
assign T397 = T400 | T398;
assign T398 = T399 == io_rw_thread;
assign T399 = reg_gpo_protection_3[1'h1:1'h0];
assign T400 = reg_gpo_protection_3 == 4'h8;
assign T401 = write & T402;
assign T402 = io_rw_addr == 12'hcc7;
assign T403 = io_rw_addr == 12'hcc7;
assign T656 = {20'h0, T404};
assign T404 = T405;
assign T405 = {T407, T406};
assign T406 = {reg_gpo_protection_1, reg_gpo_protection_0};
assign T407 = {reg_gpo_protection_3, reg_gpo_protection_2};
assign T408 = io_rw_addr == 12'h50d;
assign T657 = {4'h0, T409};
assign T409 = T410;
assign T410 = {T424, T411};
assign T411 = {T419, T412};
assign T412 = {reg_imem_protection_1, reg_imem_protection_0};
assign T658 = reset ? 4'h8 : T413;
assign T413 = T415 ? T414 : reg_imem_protection_0;
assign T414 = data_in[2'h3:1'h0];
assign T415 = write & T416;
assign T416 = io_rw_addr == 12'h505;
assign T659 = reset ? 4'hc : T417;
assign T417 = T415 ? T418 : reg_imem_protection_1;
assign T418 = data_in[3'h7:3'h4];
assign T419 = {reg_imem_protection_3, reg_imem_protection_2};
assign T660 = reset ? 4'hc : T420;
assign T420 = T415 ? T421 : reg_imem_protection_2;
assign T421 = data_in[4'hb:4'h8];
assign T661 = reset ? 4'hc : T422;
assign T422 = T415 ? T423 : reg_imem_protection_3;
assign T423 = data_in[4'hf:4'hc];
assign T424 = {T430, T425};
assign T425 = {reg_imem_protection_5, reg_imem_protection_4};
assign T662 = reset ? 4'hc : T426;
assign T426 = T415 ? T427 : reg_imem_protection_4;
assign T427 = data_in[5'h13:5'h10];
assign T663 = reset ? 4'hc : T428;
assign T428 = T415 ? T429 : reg_imem_protection_5;
assign T429 = data_in[5'h17:5'h14];
assign T430 = {reg_imem_protection_7, reg_imem_protection_6};
assign T664 = reset ? 4'hc : T431;
assign T431 = T415 ? T432 : reg_imem_protection_6;
assign T432 = data_in[5'h1b:5'h18];
assign T665 = reset ? 4'hc : T433;
assign T433 = T415 ? T434 : reg_imem_protection_7;
assign T434 = data_in[5'h1f:5'h1c];
assign T435 = io_rw_addr == 12'h505;
assign T666 = {4'h0, T436};
assign T436 = T437;
assign T437 = {T451, T438};
assign T438 = {T446, T439};
assign T439 = {reg_dmem_protection_1, reg_dmem_protection_0};
assign T667 = reset ? 4'h8 : T440;
assign T440 = T442 ? T441 : reg_dmem_protection_0;
assign T441 = data_in[2'h3:1'h0];
assign T442 = write & T443;
assign T443 = io_rw_addr == 12'h50c;
assign T668 = reset ? 4'h8 : T444;
assign T444 = T442 ? T445 : reg_dmem_protection_1;
assign T445 = data_in[3'h7:3'h4];
assign T446 = {reg_dmem_protection_3, reg_dmem_protection_2};
assign T669 = reset ? 4'h8 : T447;
assign T447 = T442 ? T448 : reg_dmem_protection_2;
assign T448 = data_in[4'hb:4'h8];
assign T670 = reset ? 4'h8 : T449;
assign T449 = T442 ? T450 : reg_dmem_protection_3;
assign T450 = data_in[4'hf:4'hc];
assign T451 = {T457, T452};
assign T452 = {reg_dmem_protection_5, reg_dmem_protection_4};
assign T671 = reset ? 4'h8 : T453;
assign T453 = T442 ? T454 : reg_dmem_protection_4;
assign T454 = data_in[5'h13:5'h10];
assign T672 = reset ? 4'h8 : T455;
assign T455 = T442 ? T456 : reg_dmem_protection_5;
assign T456 = data_in[5'h17:5'h14];
assign T457 = {reg_dmem_protection_7, reg_dmem_protection_6};
assign T673 = reset ? 4'h8 : T458;
assign T458 = T442 ? T459 : reg_dmem_protection_6;
assign T459 = data_in[5'h1b:5'h18];
assign T674 = reset ? 4'h8 : T460;
assign T460 = T442 ? T461 : reg_dmem_protection_7;
assign T461 = data_in[5'h1f:5'h1c];
assign T462 = io_rw_addr == 12'h50c;
assign T463 = T571 ? T511 : T464;
assign T464 = T509 ? status_1 : status_0;
assign status_0 = T465;
assign T465 = {T480, T466};
assign T466 = {T479, T467};
assign T467 = {reg_ie_0, T468};
assign T468 = {reg_msip_0, 3'h0};
assign T675 = reset ? 1'h0 : T469;
assign T469 = io_exception ? 1'h0 : T470;
assign T470 = T473 ? T471 : reg_ie_0;
assign T471 = T472;
assign T472 = data_in[3'h4:3'h4];
assign T473 = T477 & T474;
assign T474 = T475[1'h0:1'h0];
assign T475 = 1'h1 << T476;
assign T476 = io_rw_thread;
assign T477 = write & T478;
assign T478 = io_rw_addr == 12'h50a;
assign T479 = {reg_ie1_0, reg_prv_0};
assign T676 = reset ? 2'h3 : reg_prv_0;
assign T677 = reset ? 1'h0 : reg_ie1_0;
assign T480 = {5'h10, T481};
assign T481 = {reg_mtie_0, T482};
assign T482 = {20'h0, reg_prv1_0};
assign T678 = reset ? 2'h0 : reg_prv1_0;
assign T679 = reset ? 1'h0 : T483;
assign T483 = T491 ? 1'h1 : T484;
assign T484 = T487 ? T485 : reg_mtie_0;
assign T485 = T486;
assign T486 = data_in[5'h1a:5'h1a];
assign T487 = T477 & T488;
assign T488 = T489[1'h0:1'h0];
assign T489 = 1'h1 << T490;
assign T490 = io_rw_thread;
assign T491 = T171 & T488;
assign status_1 = T492;
assign T492 = {T501, T493};
assign T493 = {T500, T494};
assign T494 = {reg_ie_1, T495};
assign T495 = {reg_msip_1, 3'h0};
assign T680 = reset ? 1'h0 : T496;
assign T496 = io_exception ? 1'h0 : T497;
assign T497 = T498 ? T471 : reg_ie_1;
assign T498 = T477 & T499;
assign T499 = T475[1'h1:1'h1];
assign T500 = {reg_ie1_1, reg_prv_1};
assign T681 = reset ? 2'h3 : reg_prv_1;
assign T682 = reset ? 1'h0 : reg_ie1_1;
assign T501 = {5'h10, T502};
assign T502 = {reg_mtie_1, T503};
assign T503 = {20'h0, reg_prv1_1};
assign T683 = reset ? 2'h0 : reg_prv1_1;
assign T684 = reset ? 1'h0 : T504;
assign T504 = T508 ? 1'h1 : T505;
assign T505 = T506 ? T485 : reg_mtie_1;
assign T506 = T477 & T507;
assign T507 = T489[1'h1:1'h1];
assign T508 = T171 & T507;
assign T509 = T510[1'h0:1'h0];
assign T510 = io_rw_thread;
assign T511 = T570 ? status_3 : status_2;
assign status_2 = T512;
assign T512 = {T534, T513};
assign T513 = {T533, T514};
assign T514 = {reg_ie_2, T515};
assign T515 = {reg_msip_2, 3'h0};
assign T685 = reset ? 1'h0 : T516;
assign T516 = T528 ? 1'h1 : T517;
assign T517 = T527 ? 1'h1 : T518;
assign T518 = T526 ? 1'h1 : T519;
assign T519 = T525 ? 1'h1 : T520;
assign T520 = T521 ? T8 : reg_msip_2;
assign T521 = T477 & T522;
assign T522 = T523[2'h2:2'h2];
assign T523 = 1'h1 << T524;
assign T524 = io_rw_thread;
assign T525 = io_int_exts_0 & T522;
assign T526 = io_int_exts_1 & T522;
assign T527 = io_int_exts_2 & T522;
assign T528 = io_int_exts_3 & T522;
assign T686 = reset ? 1'h0 : T529;
assign T529 = io_exception ? 1'h0 : T530;
assign T530 = T531 ? T471 : reg_ie_2;
assign T531 = T477 & T532;
assign T532 = T475[2'h2:2'h2];
assign T533 = {reg_ie1_2, reg_prv_2};
assign T687 = reset ? 2'h3 : reg_prv_2;
assign T688 = reset ? 1'h0 : reg_ie1_2;
assign T534 = {5'h10, T535};
assign T535 = {reg_mtie_2, T536};
assign T536 = {20'h0, reg_prv1_2};
assign T689 = reset ? 2'h0 : reg_prv1_2;
assign T690 = reset ? 1'h0 : T537;
assign T537 = T541 ? 1'h1 : T538;
assign T538 = T539 ? T485 : reg_mtie_2;
assign T539 = T477 & T540;
assign T540 = T489[2'h2:2'h2];
assign T541 = T171 & T540;
assign status_3 = T542;
assign T542 = {T562, T543};
assign T543 = {T561, T544};
assign T544 = {reg_ie_3, T545};
assign T545 = {reg_msip_3, 3'h0};
assign T691 = reset ? 1'h0 : T546;
assign T546 = T556 ? 1'h1 : T547;
assign T547 = T555 ? 1'h1 : T548;
assign T548 = T554 ? 1'h1 : T549;
assign T549 = T553 ? 1'h1 : T550;
assign T550 = T551 ? T8 : reg_msip_3;
assign T551 = T477 & T552;
assign T552 = T523[2'h3:2'h3];
assign T553 = io_int_exts_0 & T552;
assign T554 = io_int_exts_1 & T552;
assign T555 = io_int_exts_2 & T552;
assign T556 = io_int_exts_3 & T552;
assign T692 = reset ? 1'h0 : T557;
assign T557 = io_exception ? 1'h0 : T558;
assign T558 = T559 ? T471 : reg_ie_3;
assign T559 = T477 & T560;
assign T560 = T475[2'h3:2'h3];
assign T561 = {reg_ie1_3, reg_prv_3};
assign T693 = reset ? 2'h3 : reg_prv_3;
assign T694 = reset ? 1'h0 : reg_ie1_3;
assign T562 = {5'h10, T563};
assign T563 = {reg_mtie_3, T564};
assign T564 = {20'h0, reg_prv1_3};
assign T695 = reset ? 2'h0 : reg_prv1_3;
assign T696 = reset ? 1'h0 : T565;
assign T565 = T569 ? 1'h1 : T566;
assign T566 = T567 ? T485 : reg_mtie_3;
assign T567 = T477 & T568;
assign T568 = T489[2'h3:2'h3];
assign T569 = T171 & T568;
assign T570 = T510[1'h0:1'h0];
assign T571 = T510[1'h1:1'h1];
assign T572 = io_rw_addr == 12'h50a;
assign T573 = io_rw_csr_type == 2'h3;
assign T574 = data_out | T697;
assign T697 = {4'h0, io_rw_data_in};
assign T575 = io_rw_csr_type == 2'h2;
assign T576 = T477 & T577;
assign T577 = T523[1'h0:1'h0];
assign T578 = io_int_exts_0 & T577;
assign T579 = io_int_exts_1 & T577;
assign T580 = io_int_exts_2 & T577;
assign T581 = io_int_exts_3 & T577;
assign T698 = reset ? 1'h0 : T582;
assign T582 = T592 ? 1'h1 : T583;
assign T583 = T591 ? 1'h1 : T584;
assign T584 = T590 ? 1'h1 : T585;
assign T585 = T589 ? 1'h1 : T586;
assign T586 = T587 ? T8 : reg_msip_1;
assign T587 = T477 & T588;
assign T588 = T523[1'h1:1'h1];
assign T589 = io_int_exts_0 & T588;
assign T590 = io_int_exts_1 & T588;
assign T591 = io_int_exts_2 & T588;
assign T592 = io_int_exts_3 & T588;
assign T593 = T524[1'h0:1'h0];
assign T594 = T595 ? reg_msip_3 : reg_msip_2;
assign T595 = T524[1'h0:1'h0];
assign T596 = T524[1'h1:1'h1];
assign T597 = T602 ? T600 : T598;
assign T598 = T599 ? reg_ie_1 : reg_ie_0;
assign T599 = T476[1'h0:1'h0];
assign T600 = T601 ? reg_ie_3 : reg_ie_2;
assign T601 = T476[1'h0:1'h0];
assign T602 = T476[1'h1:1'h1];
assign io_exc_expire = exc_expire;
assign exc_expire = T122;
assign io_int_expire = int_expire;
assign int_expire = T603;
assign T603 = T597 & T604;
assign T604 = T606 | T605;
assign T605 = T171;
assign T606 = T611 ? T609 : T607;
assign T607 = T608 ? reg_mtie_1 : reg_mtie_0;
assign T608 = T490[1'h0:1'h0];
assign T609 = T610 ? reg_mtie_3 : reg_mtie_2;
assign T610 = T490[1'h0:1'h0];
assign T611 = T490[1'h1:1'h1];
assign io_dmem_protection_0 = reg_dmem_protection_0;
assign io_dmem_protection_1 = reg_dmem_protection_1;
assign io_dmem_protection_2 = reg_dmem_protection_2;
assign io_dmem_protection_3 = reg_dmem_protection_3;
assign io_dmem_protection_4 = reg_dmem_protection_4;
assign io_dmem_protection_5 = reg_dmem_protection_5;
assign io_dmem_protection_6 = reg_dmem_protection_6;
assign io_dmem_protection_7 = reg_dmem_protection_7;
assign io_imem_protection_0 = reg_imem_protection_0;
assign io_imem_protection_1 = reg_imem_protection_1;
assign io_imem_protection_2 = reg_imem_protection_2;
assign io_imem_protection_3 = reg_imem_protection_3;
assign io_imem_protection_4 = reg_imem_protection_4;
assign io_imem_protection_5 = reg_imem_protection_5;
assign io_imem_protection_6 = reg_imem_protection_6;
assign io_imem_protection_7 = reg_imem_protection_7;
assign io_gpio_out_0 = reg_gpos_0;
assign io_gpio_out_1 = reg_gpos_1;
assign io_gpio_out_2 = reg_gpos_2;
assign io_gpio_out_3 = reg_gpos_3;
assign io_host_to_host = reg_to_host;
assign io_expire = T123;
assign io_evecs_0 = T699;
assign T699 = reg_evecs_0[5'h1f:1'h0];
assign io_evecs_1 = T700;
assign T700 = reg_evecs_1[5'h1f:1'h0];
assign io_evecs_2 = T701;
assign T701 = reg_evecs_2[5'h1f:1'h0];
assign io_evecs_3 = T702;
assign T702 = reg_evecs_3[5'h1f:1'h0];
assign io_tmodes_0 = reg_tmodes_0;
assign io_tmodes_1 = reg_tmodes_1;
assign io_tmodes_2 = reg_tmodes_2;
assign io_tmodes_3 = reg_tmodes_3;
assign io_slots_0 = reg_slots_0;
assign io_slots_1 = reg_slots_1;
assign io_slots_2 = reg_slots_2;
assign io_slots_3 = reg_slots_3;
assign io_slots_4 = reg_slots_4;
assign io_slots_5 = reg_slots_5;
assign io_slots_6 = reg_slots_6;
assign io_slots_7 = reg_slots_7;
assign io_rw_data_out = T703;
assign T703 = data_out[5'h1f:1'h0];
always @(posedge clk) begin
if(reset) begin
reg_msip_0 <= 1'h0;
end else if(T581) begin
reg_msip_0 <= 1'h1;
end else if(T580) begin
reg_msip_0 <= 1'h1;
end else if(T579) begin
reg_msip_0 <= 1'h1;
end else if(T578) begin
reg_msip_0 <= 1'h1;
end else if(T576) begin
reg_msip_0 <= T8;
end
if(reset) begin
reg_slots_0 <= 4'hf;
end else if(T42) begin
reg_slots_0 <= T41;
end
if(reset) begin
reg_slots_1 <= 4'hf;
end else if(T42) begin
reg_slots_1 <= T48;
end
if(reset) begin
reg_slots_2 <= 4'hf;
end else if(T42) begin
reg_slots_2 <= T51;
end
if(reset) begin
reg_slots_3 <= 4'hf;
end else if(T42) begin
reg_slots_3 <= T53;
end
if(reset) begin
reg_slots_4 <= 4'hf;
end else if(T42) begin
reg_slots_4 <= T57;
end
if(reset) begin
reg_slots_5 <= 4'hf;
end else if(T42) begin
reg_slots_5 <= T59;
end
if(reset) begin
reg_slots_6 <= 4'hf;
end else if(T42) begin
reg_slots_6 <= T62;
end
if(reset) begin
reg_slots_7 <= 4'h0;
end else if(T42) begin
reg_slots_7 <= T64;
end
if(reset) begin
reg_tmodes_0 <= 2'h0;
end else if(wake_0) begin
reg_tmodes_0 <= T224;
end else if(T222) begin
reg_tmodes_0 <= T78;
end else if(T76) begin
reg_tmodes_0 <= T75;
end
if(reset) begin
reg_tmodes_2 <= 2'h1;
end else if(wake_2) begin
reg_tmodes_2 <= T91;
end else if(T88) begin
reg_tmodes_2 <= T78;
end else if(T76) begin
reg_tmodes_2 <= T87;
end
if(T99) begin
reg_compare_2 <= T98;
end
if(reset) begin
reg_time <= 64'h0;
end else begin
reg_time <= T106;
end
if(reset) begin
reg_timer_2 <= 2'h0;
end else if(T211) begin
reg_timer_2 <= 2'h0;
end else if(T210) begin
reg_timer_2 <= 2'h2;
end else if(T121) begin
reg_timer_2 <= 2'h0;
end else if(T120) begin
reg_timer_2 <= 2'h3;
end else if(T93) begin
reg_timer_2 <= 2'h0;
end else if(T119) begin
reg_timer_2 <= 2'h1;
end else if(T115) begin
reg_timer_2 <= 2'h0;
end
if(T129) begin
reg_compare_0 <= T98;
end
if(T136) begin
reg_compare_1 <= T98;
end
if(T146) begin
reg_compare_3 <= T98;
end
if(reset) begin
reg_timer_0 <= 2'h0;
end else if(T170) begin
reg_timer_0 <= 2'h0;
end else if(T169) begin
reg_timer_0 <= 2'h2;
end else if(T168) begin
reg_timer_0 <= 2'h0;
end else if(T167) begin
reg_timer_0 <= 2'h3;
end else if(T165) begin
reg_timer_0 <= 2'h0;
end else if(T164) begin
reg_timer_0 <= 2'h1;
end else if(T162) begin
reg_timer_0 <= 2'h0;
end
if(reset) begin
reg_timer_1 <= 2'h0;
end else if(T189) begin
reg_timer_1 <= 2'h0;
end else if(T188) begin
reg_timer_1 <= 2'h2;
end else if(T187) begin
reg_timer_1 <= 2'h0;
end else if(T186) begin
reg_timer_1 <= 2'h3;
end else if(T184) begin
reg_timer_1 <= 2'h0;
end else if(T183) begin
reg_timer_1 <= 2'h1;
end else if(T181) begin
reg_timer_1 <= 2'h0;
end
if(reset) begin
reg_timer_3 <= 2'h0;
end else if(T207) begin
reg_timer_3 <= 2'h0;
end else if(T206) begin
reg_timer_3 <= 2'h2;
end else if(T205) begin
reg_timer_3 <= 2'h0;
end else if(T204) begin
reg_timer_3 <= 2'h3;
end else if(T202) begin
reg_timer_3 <= 2'h0;
end else if(T201) begin
reg_timer_3 <= 2'h1;
end else if(T199) begin
reg_timer_3 <= 2'h0;
end
if(reset) begin
reg_tmodes_3 <= 2'h1;
end else if(wake_3) begin
reg_tmodes_3 <= T218;
end else if(T216) begin
reg_tmodes_3 <= T78;
end else if(T76) begin
reg_tmodes_3 <= T215;
end
if(reset) begin
reg_tmodes_1 <= 2'h1;
end else if(wake_1) begin
reg_tmodes_1 <= T232;
end else if(T230) begin
reg_tmodes_1 <= T78;
end else if(T76) begin
reg_tmodes_1 <= T229;
end
if(T239) begin
reg_evecs_0 <= data_in;
end
if(T246) begin
reg_evecs_1 <= data_in;
end
if(T251) begin
reg_evecs_2 <= data_in;
end
if(T254) begin
reg_evecs_3 <= data_in;
end
if(T262) begin
reg_epcs_0 <= io_epc;
end
if(T267) begin
reg_epcs_1 <= io_epc;
end
if(T272) begin
reg_epcs_2 <= io_epc;
end
if(T275) begin
reg_epcs_3 <= io_epc;
end
if(T286) begin
reg_causes_0 <= io_cause;
end
if(T291) begin
reg_causes_1 <= io_cause;
end
if(T296) begin
reg_causes_2 <= io_cause;
end
if(T299) begin
reg_causes_3 <= io_cause;
end
if(T308) begin
reg_sup0_0 <= data_in;
end
if(T315) begin
reg_sup0_1 <= data_in;
end
if(T320) begin
reg_sup0_2 <= data_in;
end
if(T323) begin
reg_sup0_3 <= data_in;
end
reg_to_host <= T637;
reg_gpis_0 <= io_gpio_in_0;
reg_gpis_1 <= io_gpio_in_1;
reg_gpis_2 <= io_gpio_in_2;
reg_gpis_3 <= io_gpio_in_3;
if(reset) begin
reg_gpos_0 <= 2'h0;
end else if(T345) begin
reg_gpos_0 <= T344;
end
if(reset) begin
reg_gpo_protection_0 <= 4'h0;
end else if(T350) begin
reg_gpo_protection_0 <= T349;
end
if(reset) begin
reg_gpos_1 <= 2'h0;
end else if(T362) begin
reg_gpos_1 <= T361;
end
if(reset) begin
reg_gpo_protection_1 <= 4'h8;
end else if(T350) begin
reg_gpo_protection_1 <= T366;
end
if(reset) begin
reg_gpos_2 <= 2'h0;
end else if(T377) begin
reg_gpos_2 <= T376;
end
if(reset) begin
reg_gpo_protection_2 <= 4'h8;
end else if(T350) begin
reg_gpo_protection_2 <= T381;
end
if(reset) begin
reg_gpos_3 <= 2'h0;
end else if(T392) begin
reg_gpos_3 <= T391;
end
if(reset) begin
reg_gpo_protection_3 <= 4'h8;
end else if(T350) begin
reg_gpo_protection_3 <= T396;
end
if(reset) begin
reg_imem_protection_0 <= 4'h8;
end else if(T415) begin
reg_imem_protection_0 <= T414;
end
if(reset) begin
reg_imem_protection_1 <= 4'hc;
end else if(T415) begin
reg_imem_protection_1 <= T418;
end
if(reset) begin
reg_imem_protection_2 <= 4'hc;
end else if(T415) begin
reg_imem_protection_2 <= T421;
end
if(reset) begin
reg_imem_protection_3 <= 4'hc;
end else if(T415) begin
reg_imem_protection_3 <= T423;
end
if(reset) begin
reg_imem_protection_4 <= 4'hc;
end else if(T415) begin
reg_imem_protection_4 <= T427;
end
if(reset) begin
reg_imem_protection_5 <= 4'hc;
end else if(T415) begin
reg_imem_protection_5 <= T429;
end
if(reset) begin
reg_imem_protection_6 <= 4'hc;
end else if(T415) begin
reg_imem_protection_6 <= T432;
end
if(reset) begin
reg_imem_protection_7 <= 4'hc;
end else if(T415) begin
reg_imem_protection_7 <= T434;
end
if(reset) begin
reg_dmem_protection_0 <= 4'h8;
end else if(T442) begin
reg_dmem_protection_0 <= T441;
end
if(reset) begin
reg_dmem_protection_1 <= 4'h8;
end else if(T442) begin
reg_dmem_protection_1 <= T445;
end
if(reset) begin
reg_dmem_protection_2 <= 4'h8;
end else if(T442) begin
reg_dmem_protection_2 <= T448;
end
if(reset) begin
reg_dmem_protection_3 <= 4'h8;
end else if(T442) begin
reg_dmem_protection_3 <= T450;
end
if(reset) begin
reg_dmem_protection_4 <= 4'h8;
end else if(T442) begin
reg_dmem_protection_4 <= T454;
end
if(reset) begin
reg_dmem_protection_5 <= 4'h8;
end else if(T442) begin
reg_dmem_protection_5 <= T456;
end
if(reset) begin
reg_dmem_protection_6 <= 4'h8;
end else if(T442) begin
reg_dmem_protection_6 <= T459;
end
if(reset) begin
reg_dmem_protection_7 <= 4'h8;
end else if(T442) begin
reg_dmem_protection_7 <= T461;
end
if(reset) begin
reg_ie_0 <= 1'h0;
end else if(io_exception) begin
reg_ie_0 <= 1'h0;
end else if(T473) begin
reg_ie_0 <= T471;
end
if(reset) begin
reg_prv_0 <= 2'h3;
end
if(reset) begin
reg_ie1_0 <= 1'h0;
end
if(reset) begin
reg_prv1_0 <= 2'h0;
end
if(reset) begin
reg_mtie_0 <= 1'h0;
end else if(T491) begin
reg_mtie_0 <= 1'h1;
end else if(T487) begin
reg_mtie_0 <= T485;
end
if(reset) begin
reg_ie_1 <= 1'h0;
end else if(io_exception) begin
reg_ie_1 <= 1'h0;
end else if(T498) begin
reg_ie_1 <= T471;
end
if(reset) begin
reg_prv_1 <= 2'h3;
end
if(reset) begin
reg_ie1_1 <= 1'h0;
end
if(reset) begin
reg_prv1_1 <= 2'h0;
end
if(reset) begin
reg_mtie_1 <= 1'h0;
end else if(T508) begin
reg_mtie_1 <= 1'h1;
end else if(T506) begin
reg_mtie_1 <= T485;
end
if(reset) begin
reg_msip_2 <= 1'h0;
end else if(T528) begin
reg_msip_2 <= 1'h1;
end else if(T527) begin
reg_msip_2 <= 1'h1;
end else if(T526) begin
reg_msip_2 <= 1'h1;
end else if(T525) begin
reg_msip_2 <= 1'h1;
end else if(T521) begin
reg_msip_2 <= T8;
end
if(reset) begin
reg_ie_2 <= 1'h0;
end else if(io_exception) begin
reg_ie_2 <= 1'h0;
end else if(T531) begin
reg_ie_2 <= T471;
end
if(reset) begin
reg_prv_2 <= 2'h3;
end
if(reset) begin
reg_ie1_2 <= 1'h0;
end
if(reset) begin
reg_prv1_2 <= 2'h0;
end
if(reset) begin
reg_mtie_2 <= 1'h0;
end else if(T541) begin
reg_mtie_2 <= 1'h1;
end else if(T539) begin
reg_mtie_2 <= T485;
end
if(reset) begin
reg_msip_3 <= 1'h0;
end else if(T556) begin
reg_msip_3 <= 1'h1;
end else if(T555) begin
reg_msip_3 <= 1'h1;
end else if(T554) begin
reg_msip_3 <= 1'h1;
end else if(T553) begin
reg_msip_3 <= 1'h1;
end else if(T551) begin
reg_msip_3 <= T8;
end
if(reset) begin
reg_ie_3 <= 1'h0;
end else if(io_exception) begin
reg_ie_3 <= 1'h0;
end else if(T559) begin
reg_ie_3 <= T471;
end
if(reset) begin
reg_prv_3 <= 2'h3;
end
if(reset) begin
reg_ie1_3 <= 1'h0;
end
if(reset) begin
reg_prv1_3 <= 2'h0;
end
if(reset) begin
reg_mtie_3 <= 1'h0;
end else if(T569) begin
reg_mtie_3 <= 1'h1;
end else if(T567) begin
reg_mtie_3 <= T485;
end
if(reset) begin
reg_msip_1 <= 1'h0;
end else if(T592) begin
reg_msip_1 <= 1'h1;
end else if(T591) begin
reg_msip_1 <= 1'h1;
end else if(T590) begin
reg_msip_1 <= 1'h1;
end else if(T589) begin
reg_msip_1 <= 1'h1;
end else if(T587) begin
reg_msip_1 <= T8;
end
end
endmodule |
module Datapath(input clk, input reset,
input [2:0] io_control_dec_imm_sel,
input [1:0] io_control_dec_op1_sel,
input [1:0] io_control_dec_op2_sel,
input [3:0] io_control_exe_alu_type,
input [2:0] io_control_exe_br_type,
input [1:0] io_control_exe_csr_type,
input [1:0] io_control_exe_mul_type,
input [1:0] io_control_exe_rd_data_sel,
input [3:0] io_control_exe_mem_type,
input [1:0] io_control_mem_rd_data_sel,
input [1:0] io_control_next_pc_sel_3,
input [1:0] io_control_next_pc_sel_2,
input [1:0] io_control_next_pc_sel_1,
input [1:0] io_control_next_pc_sel_0,
input [1:0] io_control_next_tid,
input io_control_next_valid,
input [1:0] io_control_dec_rs1_sel,
input [1:0] io_control_dec_rs2_sel,
input io_control_exe_valid,
input io_control_exe_load,
input io_control_exe_store,
input io_control_exe_csr_write,
input io_control_exe_exception,
input [4:0] io_control_exe_cause,
input io_control_exe_kill,
input io_control_exe_sleep,
input io_control_exe_ie,
input io_control_exe_ee,
input io_control_exe_sret,
input io_control_exe_cycle,
input io_control_exe_instret,
input io_control_mem_rd_write,
output[1:0] io_control_if_tid,
output[1:0] io_control_dec_tid,
output[31:0] io_control_dec_inst,
output io_control_exe_br_cond,
output[1:0] io_control_exe_tid,
output[4:0] io_control_exe_rd_addr,
output io_control_exe_expire,
output[3:0] io_control_csr_slots_7,
output[3:0] io_control_csr_slots_6,
output[3:0] io_control_csr_slots_5,
output[3:0] io_control_csr_slots_4,
output[3:0] io_control_csr_slots_3,
output[3:0] io_control_csr_slots_2,
output[3:0] io_control_csr_slots_1,
output[3:0] io_control_csr_slots_0,
output[1:0] io_control_csr_tmodes_3,
output[1:0] io_control_csr_tmodes_2,
output[1:0] io_control_csr_tmodes_1,
output[1:0] io_control_csr_tmodes_0,
output[1:0] io_control_mem_tid,
output[4:0] io_control_mem_rd_addr,
output[1:0] io_control_wb_tid,
output[4:0] io_control_wb_rd_addr,
output io_control_if_exc_misaligned,
output io_control_if_exc_fault,
output io_control_exe_exc_priv_inst,
output io_control_exe_exc_load_misaligned,
output io_control_exe_exc_load_fault,
output io_control_exe_exc_store_misaligned,
output io_control_exe_exc_store_fault,
output io_control_exe_exc_expire,
output io_control_exe_int_expire,
output io_control_exe_int_ext,
output[12:0] io_imem_r_addr,
output io_imem_r_enable,
input [31:0] io_imem_r_data_out,
output[12:0] io_imem_rw_addr,
output io_imem_rw_enable,
input [31:0] io_imem_rw_data_out,
output io_imem_rw_write,
output[31:0] io_imem_rw_data_in,
output[12:0] io_dmem_addr,
output io_dmem_enable,
input [31:0] io_dmem_data_out,
output io_dmem_byte_write_3,
output io_dmem_byte_write_2,
output io_dmem_byte_write_1,
output io_dmem_byte_write_0,
output[31:0] io_dmem_data_in,
output[9:0] io_bus_addr,
output io_bus_enable,
input [31:0] io_bus_data_out,
output io_bus_write,
output[31:0] io_bus_data_in,
output[31:0] io_host_to_host,
input io_gpio_in_3,
input io_gpio_in_2,
input io_gpio_in_1,
input io_gpio_in_0,
output[1:0] io_gpio_out_3,
output[1:0] io_gpio_out_2,
output[1:0] io_gpio_out_1,
output[1:0] io_gpio_out_0,
input io_int_exts_3,
input io_int_exts_2,
input io_int_exts_1,
input io_int_exts_0
);
reg [1:0] dec_reg_tid;
reg [1:0] if_reg_tid;
reg [31:0] exe_reg_pc;
reg [31:0] dec_reg_pc;
reg [31:0] if_reg_pc;
wire[31:0] next_pc;
wire[31:0] T0;
wire[31:0] next_pcs_0;
wire[31:0] T1;
wire[31:0] T2;
wire[31:0] T3;
reg [31:0] if_reg_pcs_0;
wire[31:0] T4;
wire[31:0] T206;
wire[31:0] if_pc_plus4;
wire[31:0] T5;
wire T6;
wire T7;
wire[3:0] T8;
wire[1:0] T9;
wire T10;
wire[1:0] T11;
wire[1:0] T12;
wire T13;
wire[1:0] T14;
wire[1:0] T15;
wire T16;
wire T17;
wire[31:0] exe_address;
wire[31:0] exe_alu_result;
wire[31:0] T18;
wire[31:0] T19;
wire[31:0] T20;
wire[31:0] T21;
wire[31:0] T22;
wire[31:0] T23;
wire[31:0] T24;
wire[31:0] T25;
wire[31:0] T26;
wire[31:0] T27;
wire[31:0] def_exe_alu_result;
reg [31:0] exe_reg_op2;
wire[31:0] dec_op2;
wire[31:0] T28;
wire[31:0] dec_imm;
wire[31:0] T29;
wire[31:0] T30;
wire[31:0] T31;
wire[31:0] T32;
wire[31:0] T33;
wire[31:0] dec_imm_z;
wire[4:0] T34;
reg [31:0] dec_reg_inst;
wire T35;
wire[31:0] dec_imm_i;
wire[10:0] T36;
wire[20:0] T37;
wire[20:0] T207;
wire T38;
wire T39;
wire[31:0] dec_imm_j;
wire[11:0] T40;
wire[10:0] T41;
wire[9:0] T42;
wire T43;
wire[19:0] T44;
wire[7:0] T45;
wire[11:0] T46;
wire[11:0] T208;
wire T47;
wire T48;
wire[31:0] dec_imm_u;
wire[19:0] T49;
wire T50;
wire[31:0] dec_imm_b;
wire[10:0] T51;
wire[4:0] T52;
wire[3:0] T53;
wire[5:0] T54;
wire[20:0] T55;
wire T56;
wire[19:0] T57;
wire[19:0] T209;
wire T58;
wire T59;
wire[31:0] dec_imm_s;
wire[10:0] T60;
wire[4:0] T61;
wire[5:0] T62;
wire[20:0] T63;
wire[20:0] T210;
wire T64;
wire T65;
wire T66;
wire[31:0] dec_rs2_data;
wire[31:0] T67;
wire[31:0] T68;
wire[31:0] T69;
wire[31:0] wb_rd_data;
reg [31:0] wb_reg_rd_data;
wire T70;
wire[31:0] mem_rd_data;
wire[31:0] T71;
wire[31:0] T72;
reg [31:0] mem_reg_rd_data;
wire[31:0] mem_mul_result;
wire T73;
wire T74;
wire T75;
wire[31:0] exe_rd_data;
wire[31:0] T76;
wire[31:0] T77;
reg [31:0] exe_reg_pc4;
reg [31:0] dec_reg_pc4;
wire T78;
wire T79;
wire T80;
wire T81;
reg [31:0] exe_reg_op1;
wire[31:0] dec_op1;
wire[31:0] T82;
wire T83;
wire[31:0] dec_rs1_data;
wire[31:0] T84;
wire[31:0] T85;
wire[31:0] T86;
wire T87;
wire T88;
wire T89;
wire T90;
wire[31:0] T91;
wire[4:0] exe_alu_shift;
wire[31:0] T92;
wire T93;
wire[31:0] T211;
wire T94;
wire T95;
wire[31:0] T212;
wire T96;
wire[31:0] T97;
wire[31:0] T98;
wire T99;
wire[31:0] T100;
wire T101;
wire[31:0] T102;
wire T103;
wire[31:0] T104;
wire T105;
wire[31:0] T106;
wire T107;
wire[31:0] T108;
wire T109;
wire[31:0] T110;
wire[62:0] T111;
wire T112;
wire[31:0] T113;
wire T114;
wire T115;
wire T116;
wire[3:0] T117;
wire[1:0] T118;
reg [1:0] exe_reg_tid;
wire T119;
wire[1:0] T120;
wire[1:0] T121;
wire T122;
wire[1:0] T123;
wire[1:0] T124;
wire T125;
wire T126;
wire[31:0] mem_evec;
wire[31:0] T127;
wire[31:0] T128;
wire T129;
wire[1:0] T130;
reg [1:0] mem_reg_tid;
wire[31:0] T131;
wire T132;
wire T133;
wire T134;
wire T135;
wire[3:0] T136;
wire[1:0] T137;
wire T138;
wire[1:0] T139;
wire[1:0] T140;
wire T141;
wire[1:0] T142;
wire[1:0] T143;
wire T144;
wire T145;
wire[31:0] next_pcs_1;
wire[31:0] T146;
wire[31:0] T147;
wire[31:0] T148;
reg [31:0] if_reg_pcs_1;
wire[31:0] T149;
wire[31:0] T213;
wire T150;
wire T151;
wire T152;
wire T153;
wire T154;
wire T155;
wire T156;
wire[1:0] T157;
wire[31:0] T158;
wire[31:0] next_pcs_2;
wire[31:0] T159;
wire[31:0] T160;
wire[31:0] T161;
reg [31:0] if_reg_pcs_2;
wire[31:0] T162;
wire[31:0] T214;
wire T163;
wire T164;
wire T165;
wire T166;
wire T167;
wire T168;
wire[31:0] next_pcs_3;
wire[31:0] T169;
wire[31:0] T170;
wire[31:0] T171;
reg [31:0] if_reg_pcs_3;
wire[31:0] T172;
wire[31:0] T215;
wire T173;
wire T174;
wire T175;
wire T176;
wire T177;
wire T178;
wire T179;
wire T180;
reg [31:0] exe_csr_data;
wire[31:0] dec_csr_data;
wire T181;
reg [11:0] exe_reg_csr_addr;
wire[11:0] T182;
reg [31:0] exe_reg_rs2_data;
wire[3:0] T216;
reg [4:0] mem_reg_rd_addr;
reg [4:0] exe_reg_rd_addr;
wire[4:0] T183;
wire[4:0] T184;
wire[4:0] T185;
wire[12:0] T217;
wire[29:0] T186;
wire T187;
wire[1:0] T188;
reg [4:0] wb_reg_rd_addr;
reg [1:0] wb_reg_tid;
wire exe_br_cond;
wire T189;
wire T190;
wire T191;
wire T192;
wire T193;
wire T194;
wire T195;
wire T196;
wire T197;
wire T198;
wire T199;
wire T200;
wire exe_ltu;
reg [31:0] exe_reg_rs1_data;
wire T201;
wire exe_lt;
wire[31:0] T202;
wire[31:0] T203;
wire T204;
wire exe_eq;
wire T205;
wire[31:0] regfile_io_rs1_data;
wire[31:0] regfile_io_rs2_data;
wire[31:0] Multiplier_io_result;
wire[12:0] loadstore_io_dmem_addr;
wire loadstore_io_dmem_enable;
wire loadstore_io_dmem_byte_write_3;
wire loadstore_io_dmem_byte_write_2;
wire loadstore_io_dmem_byte_write_1;
wire loadstore_io_dmem_byte_write_0;
wire[31:0] loadstore_io_dmem_data_in;
wire[12:0] loadstore_io_imem_rw_addr;
wire loadstore_io_imem_rw_enable;
wire loadstore_io_imem_rw_write;
wire[31:0] loadstore_io_imem_rw_data_in;
wire[9:0] loadstore_io_bus_addr;
wire loadstore_io_bus_enable;
wire loadstore_io_bus_write;
wire[31:0] loadstore_io_bus_data_in;
wire[31:0] loadstore_io_data_out;
wire loadstore_io_load_misaligned;
wire loadstore_io_load_fault;
wire loadstore_io_store_misaligned;
wire loadstore_io_store_fault;
wire[31:0] csr_io_rw_data_out;
wire[3:0] csr_io_slots_7;
wire[3:0] csr_io_slots_6;
wire[3:0] csr_io_slots_5;
wire[3:0] csr_io_slots_4;
wire[3:0] csr_io_slots_3;
wire[3:0] csr_io_slots_2;
wire[3:0] csr_io_slots_1;
wire[3:0] csr_io_slots_0;
wire[1:0] csr_io_tmodes_3;
wire[1:0] csr_io_tmodes_2;
wire[1:0] csr_io_tmodes_1;
wire[1:0] csr_io_tmodes_0;
wire[31:0] csr_io_evecs_3;
wire[31:0] csr_io_evecs_2;
wire[31:0] csr_io_evecs_1;
wire[31:0] csr_io_evecs_0;
wire csr_io_expire;
wire[31:0] csr_io_host_to_host;
wire[1:0] csr_io_gpio_out_3;
wire[1:0] csr_io_gpio_out_2;
wire[1:0] csr_io_gpio_out_1;
wire[1:0] csr_io_gpio_out_0;
wire[3:0] csr_io_imem_protection_7;
wire[3:0] csr_io_imem_protection_6;
wire[3:0] csr_io_imem_protection_5;
wire[3:0] csr_io_imem_protection_4;
wire[3:0] csr_io_imem_protection_3;
wire[3:0] csr_io_imem_protection_2;
wire[3:0] csr_io_imem_protection_1;
wire[3:0] csr_io_imem_protection_0;
wire[3:0] csr_io_dmem_protection_7;
wire[3:0] csr_io_dmem_protection_6;
wire[3:0] csr_io_dmem_protection_5;
wire[3:0] csr_io_dmem_protection_4;
wire[3:0] csr_io_dmem_protection_3;
wire[3:0] csr_io_dmem_protection_2;
wire[3:0] csr_io_dmem_protection_1;
wire[3:0] csr_io_dmem_protection_0;
wire csr_io_int_expire;
wire csr_io_exc_expire;
wire csr_io_int_ext;
wire csr_io_priv_fault;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
dec_reg_tid = {1{$random}};
if_reg_tid = {1{$random}};
exe_reg_pc = {1{$random}};
dec_reg_pc = {1{$random}};
if_reg_pc = {1{$random}};
if_reg_pcs_0 = {1{$random}};
exe_reg_op2 = {1{$random}};
dec_reg_inst = {1{$random}};
wb_reg_rd_data = {1{$random}};
mem_reg_rd_data = {1{$random}};
exe_reg_pc4 = {1{$random}};
dec_reg_pc4 = {1{$random}};
exe_reg_op1 = {1{$random}};
exe_reg_tid = {1{$random}};
mem_reg_tid = {1{$random}};
if_reg_pcs_1 = {1{$random}};
if_reg_pcs_2 = {1{$random}};
if_reg_pcs_3 = {1{$random}};
exe_csr_data = {1{$random}};
exe_reg_csr_addr = {1{$random}};
exe_reg_rs2_data = {1{$random}};
mem_reg_rd_addr = {1{$random}};
exe_reg_rd_addr = {1{$random}};
wb_reg_rd_addr = {1{$random}};
wb_reg_tid = {1{$random}};
exe_reg_rs1_data = {1{$random}};
end
// synthesis translate_on
`endif
assign next_pc = T180 ? T158 : T0;
assign T0 = T156 ? next_pcs_1 : next_pcs_0;
assign next_pcs_0 = T1;
assign T1 = T134 ? mem_evec : T2;
assign T2 = T115 ? exe_address : T3;
assign T3 = T6 ? if_pc_plus4 : if_reg_pcs_0;
assign T4 = 32'h0;
assign T206 = reset ? T4 : next_pcs_0;
assign if_pc_plus4 = T5;
assign T5 = if_reg_pc + 32'h4;
assign T6 = T10 & T7;
assign T7 = T8[1'h0:1'h0];
assign T8 = 1'h1 << T9;
assign T9 = if_reg_tid;
assign T10 = T11 == 2'h1;
assign T11 = T17 ? T15 : T12;
assign T12 = T13 ? io_control_next_pc_sel_1 : io_control_next_pc_sel_0;
assign T13 = T14[1'h0:1'h0];
assign T14 = if_reg_tid;
assign T15 = T16 ? io_control_next_pc_sel_3 : io_control_next_pc_sel_2;
assign T16 = T14[1'h0:1'h0];
assign T17 = T14[1'h1:1'h1];
assign exe_address = exe_alu_result;
assign exe_alu_result = T18;
assign T18 = T114 ? T113 : T19;
assign T19 = T112 ? T110 : T20;
assign T20 = T109 ? T108 : T21;
assign T21 = T107 ? T106 : T22;
assign T22 = T105 ? T104 : T23;
assign T23 = T103 ? T102 : T24;
assign T24 = T101 ? T100 : T25;
assign T25 = T99 ? T212 : T26;
assign T26 = T95 ? T211 : T27;
assign T27 = T93 ? T91 : def_exe_alu_result;
assign def_exe_alu_result = exe_reg_op1 + exe_reg_op2;
assign dec_op2 = T81 ? dec_rs2_data : T28;
assign T28 = T66 ? dec_imm : 32'h0;
assign dec_imm = T65 ? dec_imm_s : T29;
assign T29 = T59 ? dec_imm_b : T30;
assign T30 = T50 ? dec_imm_u : T31;
assign T31 = T48 ? dec_imm_j : T32;
assign T32 = T39 ? dec_imm_i : T33;
assign T33 = T35 ? dec_imm_z : dec_imm_i;
assign dec_imm_z = {27'h0, T34};
assign T34 = dec_reg_inst[5'h13:4'hf];
assign T35 = io_control_dec_imm_sel == 3'h5;
assign dec_imm_i = {T37, T36};
assign T36 = dec_reg_inst[5'h1e:5'h14];
assign T37 = 21'h0 - T207;
assign T207 = {20'h0, T38};
assign T38 = dec_reg_inst[5'h1f:5'h1f];
assign T39 = io_control_dec_imm_sel == 3'h4;
assign dec_imm_j = {T44, T40};
assign T40 = {T43, T41};
assign T41 = {T42, 1'h0};
assign T42 = dec_reg_inst[5'h1e:5'h15];
assign T43 = dec_reg_inst[5'h14:5'h14];
assign T44 = {T46, T45};
assign T45 = dec_reg_inst[5'h13:4'hc];
assign T46 = 12'h0 - T208;
assign T208 = {11'h0, T47};
assign T47 = dec_reg_inst[5'h1f:5'h1f];
assign T48 = io_control_dec_imm_sel == 3'h3;
assign dec_imm_u = {T49, 12'h0};
assign T49 = dec_reg_inst[5'h1f:4'hc];
assign T50 = io_control_dec_imm_sel == 3'h2;
assign dec_imm_b = {T55, T51};
assign T51 = {T54, T52};
assign T52 = {T53, 1'h0};
assign T53 = dec_reg_inst[4'hb:4'h8];
assign T54 = dec_reg_inst[5'h1e:5'h19];
assign T55 = {T57, T56};
assign T56 = dec_reg_inst[3'h7:3'h7];
assign T57 = 20'h0 - T209;
assign T209 = {19'h0, T58};
assign T58 = dec_reg_inst[5'h1f:5'h1f];
assign T59 = io_control_dec_imm_sel == 3'h1;
assign dec_imm_s = {T63, T60};
assign T60 = {T62, T61};
assign T61 = dec_reg_inst[4'hb:3'h7];
assign T62 = dec_reg_inst[5'h1e:5'h19];
assign T63 = 21'h0 - T210;
assign T210 = {20'h0, T64};
assign T64 = dec_reg_inst[5'h1f:5'h1f];
assign T65 = io_control_dec_imm_sel == 3'h0;
assign T66 = io_control_dec_op2_sel == 2'h0;
assign dec_rs2_data = T67;
assign T67 = T80 ? exe_rd_data : T68;
assign T68 = T75 ? mem_rd_data : T69;
assign T69 = T70 ? wb_rd_data : regfile_io_rs2_data;
assign wb_rd_data = wb_reg_rd_data;
assign T70 = io_control_dec_rs2_sel == 2'h3;
assign mem_rd_data = T71;
assign T71 = T74 ? loadstore_io_data_out : T72;
assign T72 = T73 ? mem_mul_result : mem_reg_rd_data;
assign mem_mul_result = Multiplier_io_result;
assign T73 = io_control_mem_rd_data_sel == 2'h2;
assign T74 = io_control_mem_rd_data_sel == 2'h1;
assign T75 = io_control_dec_rs2_sel == 2'h2;
assign exe_rd_data = T76;
assign T76 = T79 ? csr_io_rw_data_out : T77;
assign T77 = T78 ? exe_reg_pc4 : exe_alu_result;
assign T78 = io_control_exe_rd_data_sel == 2'h2;
assign T79 = io_control_exe_rd_data_sel == 2'h1;
assign T80 = io_control_dec_rs2_sel == 2'h1;
assign T81 = io_control_dec_op2_sel == 2'h1;
assign dec_op1 = T90 ? dec_rs1_data : T82;
assign T82 = T83 ? dec_reg_pc : 32'h0;
assign T83 = io_control_dec_op1_sel == 2'h0;
assign dec_rs1_data = T84;
assign T84 = T89 ? exe_rd_data : T85;
assign T85 = T88 ? mem_rd_data : T86;
assign T86 = T87 ? wb_rd_data : regfile_io_rs1_data;
assign T87 = io_control_dec_rs1_sel == 2'h3;
assign T88 = io_control_dec_rs1_sel == 2'h2;
assign T89 = io_control_dec_rs1_sel == 2'h1;
assign T90 = io_control_dec_op1_sel == 2'h1;
assign T91 = $signed(T92) >>> exe_alu_shift;
assign exe_alu_shift = exe_reg_op2[3'h4:1'h0];
assign T92 = exe_reg_op1;
assign T93 = io_control_exe_alu_type == 4'hd;
assign T211 = {31'h0, T94};
assign T94 = exe_reg_op1 < exe_reg_op2;
assign T95 = io_control_exe_alu_type == 4'hb;
assign T212 = {31'h0, T96};
assign T96 = $signed(T98) < $signed(T97);
assign T97 = exe_reg_op2;
assign T98 = exe_reg_op1;
assign T99 = io_control_exe_alu_type == 4'ha;
assign T100 = exe_reg_op1 - exe_reg_op2;
assign T101 = io_control_exe_alu_type == 4'h8;
assign T102 = exe_reg_op1 & exe_reg_op2;
assign T103 = io_control_exe_alu_type == 4'h7;
assign T104 = exe_reg_op1 | exe_reg_op2;
assign T105 = io_control_exe_alu_type == 4'h6;
assign T106 = exe_reg_op1 >> exe_alu_shift;
assign T107 = io_control_exe_alu_type == 4'h5;
assign T108 = exe_reg_op1 ^ exe_reg_op2;
assign T109 = io_control_exe_alu_type == 4'h4;
assign T110 = T111[5'h1f:1'h0];
assign T111 = exe_reg_op1 << exe_alu_shift;
assign T112 = io_control_exe_alu_type == 4'h1;
assign T113 = exe_reg_op1 + exe_reg_op2;
assign T114 = io_control_exe_alu_type == 4'h0;
assign T115 = T119 & T116;
assign T116 = T117[1'h0:1'h0];
assign T117 = 1'h1 << T118;
assign T118 = exe_reg_tid;
assign T119 = T120 == 2'h2;
assign T120 = T126 ? T124 : T121;
assign T121 = T122 ? io_control_next_pc_sel_1 : io_control_next_pc_sel_0;
assign T122 = T123[1'h0:1'h0];
assign T123 = exe_reg_tid;
assign T124 = T125 ? io_control_next_pc_sel_3 : io_control_next_pc_sel_2;
assign T125 = T123[1'h0:1'h0];
assign T126 = T123[1'h1:1'h1];
assign mem_evec = T127;
assign T127 = T133 ? T131 : T128;
assign T128 = T129 ? csr_io_evecs_1 : csr_io_evecs_0;
assign T129 = T130[1'h0:1'h0];
assign T130 = mem_reg_tid;
assign T131 = T132 ? csr_io_evecs_3 : csr_io_evecs_2;
assign T132 = T130[1'h0:1'h0];
assign T133 = T130[1'h1:1'h1];
assign T134 = T138 & T135;
assign T135 = T136[1'h0:1'h0];
assign T136 = 1'h1 << T137;
assign T137 = mem_reg_tid;
assign T138 = T139 == 2'h3;
assign T139 = T145 ? T143 : T140;
assign T140 = T141 ? io_control_next_pc_sel_1 : io_control_next_pc_sel_0;
assign T141 = T142[1'h0:1'h0];
assign T142 = mem_reg_tid;
assign T143 = T144 ? io_control_next_pc_sel_3 : io_control_next_pc_sel_2;
assign T144 = T142[1'h0:1'h0];
assign T145 = T142[1'h1:1'h1];
assign next_pcs_1 = T146;
assign T146 = T154 ? mem_evec : T147;
assign T147 = T152 ? exe_address : T148;
assign T148 = T150 ? if_pc_plus4 : if_reg_pcs_1;
assign T149 = 32'h0;
assign T213 = reset ? T149 : next_pcs_1;
assign T150 = T10 & T151;
assign T151 = T8[1'h1:1'h1];
assign T152 = T119 & T153;
assign T153 = T117[1'h1:1'h1];
assign T154 = T138 & T155;
assign T155 = T136[1'h1:1'h1];
assign T156 = T157[1'h0:1'h0];
assign T157 = io_control_next_tid;
assign T158 = T179 ? next_pcs_3 : next_pcs_2;
assign next_pcs_2 = T159;
assign T159 = T167 ? mem_evec : T160;
assign T160 = T165 ? exe_address : T161;
assign T161 = T163 ? if_pc_plus4 : if_reg_pcs_2;
assign T162 = 32'h0;
assign T214 = reset ? T162 : next_pcs_2;
assign T163 = T10 & T164;
assign T164 = T8[2'h2:2'h2];
assign T165 = T119 & T166;
assign T166 = T117[2'h2:2'h2];
assign T167 = T138 & T168;
assign T168 = T136[2'h2:2'h2];
assign next_pcs_3 = T169;
assign T169 = T177 ? mem_evec : T170;
assign T170 = T175 ? exe_address : T171;
assign T171 = T173 ? if_pc_plus4 : if_reg_pcs_3;
assign T172 = 32'h0;
assign T215 = reset ? T172 : next_pcs_3;
assign T173 = T10 & T174;
assign T174 = T8[2'h3:2'h3];
assign T175 = T119 & T176;
assign T176 = T117[2'h3:2'h3];
assign T177 = T138 & T178;
assign T178 = T136[2'h3:2'h3];
assign T179 = T157[1'h0:1'h0];
assign T180 = T157[1'h1:1'h1];
assign dec_csr_data = T181 ? dec_imm : dec_rs1_data;
assign T181 = io_control_dec_op2_sel == 2'h0;
assign T182 = dec_reg_inst[5'h1f:5'h14];
assign T216 = {2'h0, io_control_exe_mul_type};
assign T183 = dec_reg_inst[4'hb:3'h7];
assign T184 = io_imem_r_data_out[5'h18:5'h14];
assign T185 = io_imem_r_data_out[5'h13:4'hf];
assign io_gpio_out_0 = csr_io_gpio_out_0;
assign io_gpio_out_1 = csr_io_gpio_out_1;
assign io_gpio_out_2 = csr_io_gpio_out_2;
assign io_gpio_out_3 = csr_io_gpio_out_3;
assign io_host_to_host = csr_io_host_to_host;
assign io_bus_data_in = loadstore_io_bus_data_in;
assign io_bus_write = loadstore_io_bus_write;
assign io_bus_enable = loadstore_io_bus_enable;
assign io_bus_addr = loadstore_io_bus_addr;
assign io_dmem_data_in = loadstore_io_dmem_data_in;
assign io_dmem_byte_write_0 = loadstore_io_dmem_byte_write_0;
assign io_dmem_byte_write_1 = loadstore_io_dmem_byte_write_1;
assign io_dmem_byte_write_2 = loadstore_io_dmem_byte_write_2;
assign io_dmem_byte_write_3 = loadstore_io_dmem_byte_write_3;
assign io_dmem_enable = loadstore_io_dmem_enable;
assign io_dmem_addr = loadstore_io_dmem_addr;
assign io_imem_rw_data_in = loadstore_io_imem_rw_data_in;
assign io_imem_rw_write = loadstore_io_imem_rw_write;
assign io_imem_rw_enable = loadstore_io_imem_rw_enable;
assign io_imem_rw_addr = loadstore_io_imem_rw_addr;
assign io_imem_r_enable = io_control_next_valid;
assign io_imem_r_addr = T217;
assign T217 = T186[4'hc:1'h0];
assign T186 = next_pc[5'h1f:2'h2];
assign io_control_exe_int_ext = csr_io_int_ext;
assign io_control_exe_int_expire = csr_io_int_expire;
assign io_control_exe_exc_expire = csr_io_exc_expire;
assign io_control_exe_exc_store_fault = loadstore_io_store_fault;
assign io_control_exe_exc_store_misaligned = loadstore_io_store_misaligned;
assign io_control_exe_exc_load_fault = loadstore_io_load_fault;
assign io_control_exe_exc_load_misaligned = loadstore_io_load_misaligned;
assign io_control_exe_exc_priv_inst = csr_io_priv_fault;
assign io_control_if_exc_fault = 1'h0;
assign io_control_if_exc_misaligned = T187;
assign T187 = T188 != 2'h0;
assign T188 = if_reg_pc[1'h1:1'h0];
assign io_control_wb_rd_addr = wb_reg_rd_addr;
assign io_control_wb_tid = wb_reg_tid;
assign io_control_mem_rd_addr = mem_reg_rd_addr;
assign io_control_mem_tid = mem_reg_tid;
assign io_control_csr_tmodes_0 = csr_io_tmodes_0;
assign io_control_csr_tmodes_1 = csr_io_tmodes_1;
assign io_control_csr_tmodes_2 = csr_io_tmodes_2;
assign io_control_csr_tmodes_3 = csr_io_tmodes_3;
assign io_control_csr_slots_0 = csr_io_slots_0;
assign io_control_csr_slots_1 = csr_io_slots_1;
assign io_control_csr_slots_2 = csr_io_slots_2;
assign io_control_csr_slots_3 = csr_io_slots_3;
assign io_control_csr_slots_4 = csr_io_slots_4;
assign io_control_csr_slots_5 = csr_io_slots_5;
assign io_control_csr_slots_6 = csr_io_slots_6;
assign io_control_csr_slots_7 = csr_io_slots_7;
assign io_control_exe_expire = csr_io_expire;
assign io_control_exe_rd_addr = exe_reg_rd_addr;
assign io_control_exe_tid = exe_reg_tid;
assign io_control_exe_br_cond = exe_br_cond;
assign exe_br_cond = T189;
assign T189 = T205 ? exe_eq : T190;
assign T190 = T204 ? exe_lt : T191;
assign T191 = T201 ? exe_ltu : T192;
assign T192 = T200 ? T199 : T193;
assign T193 = T198 ? T197 : T194;
assign T194 = T196 ? T195 : 1'h0;
assign T195 = exe_ltu ^ 1'h1;
assign T196 = io_control_exe_br_type == 3'h5;
assign T197 = exe_lt ^ 1'h1;
assign T198 = io_control_exe_br_type == 3'h3;
assign T199 = exe_eq ^ 1'h1;
assign T200 = io_control_exe_br_type == 3'h1;
assign exe_ltu = exe_reg_rs1_data < exe_reg_rs2_data;
assign T201 = io_control_exe_br_type == 3'h4;
assign exe_lt = $signed(T203) < $signed(T202);
assign T202 = exe_reg_rs2_data;
assign T203 = exe_reg_rs1_data;
assign T204 = io_control_exe_br_type == 3'h2;
assign exe_eq = exe_reg_rs1_data == exe_reg_rs2_data;
assign T205 = io_control_exe_br_type == 3'h0;
assign io_control_dec_inst = dec_reg_inst;
assign io_control_dec_tid = dec_reg_tid;
assign io_control_if_tid = if_reg_tid;
RegisterFile regfile(.clk(clk),
.io_rs1_thread( if_reg_tid ),
.io_rs1_addr( T185 ),
.io_rs1_data( regfile_io_rs1_data ),
.io_rs2_thread( if_reg_tid ),
.io_rs2_addr( T184 ),
.io_rs2_data( regfile_io_rs2_data ),
.io_rd_thread( mem_reg_tid ),
.io_rd_addr( mem_reg_rd_addr ),
.io_rd_data( mem_rd_data ),
.io_rd_enable( io_control_mem_rd_write )
);
Multiplier Multiplier(.clk(clk),
.io_op1( exe_reg_op1 ),
.io_op2( exe_reg_op2 ),
.io_func( T216 ),
.io_result( Multiplier_io_result )
);
LoadStore loadstore(.clk(clk),
.io_dmem_addr( loadstore_io_dmem_addr ),
.io_dmem_enable( loadstore_io_dmem_enable ),
.io_dmem_data_out( io_dmem_data_out ),
.io_dmem_byte_write_3( loadstore_io_dmem_byte_write_3 ),
.io_dmem_byte_write_2( loadstore_io_dmem_byte_write_2 ),
.io_dmem_byte_write_1( loadstore_io_dmem_byte_write_1 ),
.io_dmem_byte_write_0( loadstore_io_dmem_byte_write_0 ),
.io_dmem_data_in( loadstore_io_dmem_data_in ),
//.io_imem_r_addr( )
//.io_imem_r_enable( )
//.io_imem_r_data_out( )
.io_imem_rw_addr( loadstore_io_imem_rw_addr ),
.io_imem_rw_enable( loadstore_io_imem_rw_enable ),
.io_imem_rw_data_out( io_imem_rw_data_out ),
.io_imem_rw_write( loadstore_io_imem_rw_write ),
.io_imem_rw_data_in( loadstore_io_imem_rw_data_in ),
.io_bus_addr( loadstore_io_bus_addr ),
.io_bus_enable( loadstore_io_bus_enable ),
.io_bus_data_out( io_bus_data_out ),
.io_bus_write( loadstore_io_bus_write ),
.io_bus_data_in( loadstore_io_bus_data_in ),
.io_addr( exe_address ),
.io_thread( exe_reg_tid ),
.io_load( io_control_exe_load ),
.io_store( io_control_exe_store ),
.io_mem_type( io_control_exe_mem_type ),
.io_data_in( exe_reg_rs2_data ),
.io_data_out( loadstore_io_data_out ),
.io_imem_protection_7( csr_io_imem_protection_7 ),
.io_imem_protection_6( csr_io_imem_protection_6 ),
.io_imem_protection_5( csr_io_imem_protection_5 ),
.io_imem_protection_4( csr_io_imem_protection_4 ),
.io_imem_protection_3( csr_io_imem_protection_3 ),
.io_imem_protection_2( csr_io_imem_protection_2 ),
.io_imem_protection_1( csr_io_imem_protection_1 ),
.io_imem_protection_0( csr_io_imem_protection_0 ),
.io_dmem_protection_7( csr_io_dmem_protection_7 ),
.io_dmem_protection_6( csr_io_dmem_protection_6 ),
.io_dmem_protection_5( csr_io_dmem_protection_5 ),
.io_dmem_protection_4( csr_io_dmem_protection_4 ),
.io_dmem_protection_3( csr_io_dmem_protection_3 ),
.io_dmem_protection_2( csr_io_dmem_protection_2 ),
.io_dmem_protection_1( csr_io_dmem_protection_1 ),
.io_dmem_protection_0( csr_io_dmem_protection_0 ),
.io_kill( io_control_exe_kill ),
.io_load_misaligned( loadstore_io_load_misaligned ),
.io_load_fault( loadstore_io_load_fault ),
.io_store_misaligned( loadstore_io_store_misaligned ),
.io_store_fault( loadstore_io_store_fault )
);
CSR csr(.clk(clk), .reset(reset),
.io_rw_addr( exe_reg_csr_addr ),
.io_rw_thread( exe_reg_tid ),
.io_rw_csr_type( io_control_exe_csr_type ),
.io_rw_write( io_control_exe_csr_write ),
.io_rw_data_in( exe_csr_data ),
.io_rw_data_out( csr_io_rw_data_out ),
.io_rw_valid( io_control_exe_valid ),
.io_slots_7( csr_io_slots_7 ),
.io_slots_6( csr_io_slots_6 ),
.io_slots_5( csr_io_slots_5 ),
.io_slots_4( csr_io_slots_4 ),
.io_slots_3( csr_io_slots_3 ),
.io_slots_2( csr_io_slots_2 ),
.io_slots_1( csr_io_slots_1 ),
.io_slots_0( csr_io_slots_0 ),
.io_tmodes_3( csr_io_tmodes_3 ),
.io_tmodes_2( csr_io_tmodes_2 ),
.io_tmodes_1( csr_io_tmodes_1 ),
.io_tmodes_0( csr_io_tmodes_0 ),
.io_kill( io_control_exe_kill ),
.io_exception( io_control_exe_exception ),
.io_epc( exe_reg_pc ),
.io_cause( io_control_exe_cause ),
.io_evecs_3( csr_io_evecs_3 ),
.io_evecs_2( csr_io_evecs_2 ),
.io_evecs_1( csr_io_evecs_1 ),
.io_evecs_0( csr_io_evecs_0 ),
.io_sleep( io_control_exe_sleep ),
.io_ie( io_control_exe_ie ),
.io_ee( io_control_exe_ee ),
.io_expire( csr_io_expire ),
.io_dec_tid( dec_reg_tid ),
.io_sret( io_control_exe_sret ),
.io_host_to_host( csr_io_host_to_host ),
.io_gpio_in_3( io_gpio_in_3 ),
.io_gpio_in_2( io_gpio_in_2 ),
.io_gpio_in_1( io_gpio_in_1 ),
.io_gpio_in_0( io_gpio_in_0 ),
.io_gpio_out_3( csr_io_gpio_out_3 ),
.io_gpio_out_2( csr_io_gpio_out_2 ),
.io_gpio_out_1( csr_io_gpio_out_1 ),
.io_gpio_out_0( csr_io_gpio_out_0 ),
.io_int_exts_3( io_int_exts_3 ),
.io_int_exts_2( io_int_exts_2 ),
.io_int_exts_1( io_int_exts_1 ),
.io_int_exts_0( io_int_exts_0 ),
.io_imem_protection_7( csr_io_imem_protection_7 ),
.io_imem_protection_6( csr_io_imem_protection_6 ),
.io_imem_protection_5( csr_io_imem_protection_5 ),
.io_imem_protection_4( csr_io_imem_protection_4 ),
.io_imem_protection_3( csr_io_imem_protection_3 ),
.io_imem_protection_2( csr_io_imem_protection_2 ),
.io_imem_protection_1( csr_io_imem_protection_1 ),
.io_imem_protection_0( csr_io_imem_protection_0 ),
.io_dmem_protection_7( csr_io_dmem_protection_7 ),
.io_dmem_protection_6( csr_io_dmem_protection_6 ),
.io_dmem_protection_5( csr_io_dmem_protection_5 ),
.io_dmem_protection_4( csr_io_dmem_protection_4 ),
.io_dmem_protection_3( csr_io_dmem_protection_3 ),
.io_dmem_protection_2( csr_io_dmem_protection_2 ),
.io_dmem_protection_1( csr_io_dmem_protection_1 ),
.io_dmem_protection_0( csr_io_dmem_protection_0 ),
.io_cycle( io_control_exe_cycle ),
.io_instret( io_control_exe_instret ),
.io_int_expire( csr_io_int_expire ),
.io_exc_expire( csr_io_exc_expire ),
.io_int_ext( csr_io_int_ext ),
.io_priv_fault( csr_io_priv_fault )
);
always @(posedge clk) begin
dec_reg_tid <= if_reg_tid;
if_reg_tid <= io_control_next_tid;
exe_reg_pc <= dec_reg_pc;
dec_reg_pc <= if_reg_pc;
if(T180) begin
if_reg_pc <= T158;
end else if(T156) begin
if_reg_pc <= next_pcs_1;
end else begin
if_reg_pc <= next_pcs_0;
end
if(reset) begin
if_reg_pcs_0 <= T4;
end else begin
if_reg_pcs_0 <= next_pcs_0;
end
if(T81) begin
exe_reg_op2 <= dec_rs2_data;
end else if(T66) begin
exe_reg_op2 <= dec_imm;
end else begin
exe_reg_op2 <= 32'h0;
end
dec_reg_inst <= io_imem_r_data_out;
wb_reg_rd_data <= mem_rd_data;
mem_reg_rd_data <= exe_rd_data;
exe_reg_pc4 <= dec_reg_pc4;
dec_reg_pc4 <= if_pc_plus4;
if(T90) begin
exe_reg_op1 <= dec_rs1_data;
end else if(T83) begin
exe_reg_op1 <= dec_reg_pc;
end else begin
exe_reg_op1 <= 32'h0;
end
exe_reg_tid <= dec_reg_tid;
mem_reg_tid <= exe_reg_tid;
if(reset) begin
if_reg_pcs_1 <= T149;
end else begin
if_reg_pcs_1 <= next_pcs_1;
end
if(reset) begin
if_reg_pcs_2 <= T162;
end else begin
if_reg_pcs_2 <= next_pcs_2;
end
if(reset) begin
if_reg_pcs_3 <= T172;
end else begin
if_reg_pcs_3 <= next_pcs_3;
end
if(T181) begin
exe_csr_data <= dec_imm;
end else begin
exe_csr_data <= dec_rs1_data;
end
exe_reg_csr_addr <= T182;
exe_reg_rs2_data <= dec_rs2_data;
mem_reg_rd_addr <= exe_reg_rd_addr;
exe_reg_rd_addr <= T183;
wb_reg_rd_addr <= mem_reg_rd_addr;
wb_reg_tid <= mem_reg_tid;
exe_reg_rs1_data <= dec_rs1_data;
end
endmodule |
module Core(input clk, input reset,
input [12:0] io_imem_addr,
input io_imem_enable,
output[31:0] io_imem_data_out,
input io_imem_write,
input [31:0] io_imem_data_in,
output io_imem_ready,
input [12:0] io_dmem_addr,
input io_dmem_enable,
output[31:0] io_dmem_data_out,
input io_dmem_byte_write_3,
input io_dmem_byte_write_2,
input io_dmem_byte_write_1,
input io_dmem_byte_write_0,
input [31:0] io_dmem_data_in,
output[9:0] io_bus_addr,
output io_bus_enable,
input [31:0] io_bus_data_out,
output io_bus_write,
output[31:0] io_bus_data_in,
output[31:0] io_host_to_host,
input io_gpio_in_3,
input io_gpio_in_2,
input io_gpio_in_1,
input io_gpio_in_0,
output[1:0] io_gpio_out_3,
output[1:0] io_gpio_out_2,
output[1:0] io_gpio_out_1,
output[1:0] io_gpio_out_0,
input io_int_exts_7,
input io_int_exts_6,
input io_int_exts_5,
input io_int_exts_4,
input io_int_exts_3,
input io_int_exts_2,
input io_int_exts_1,
input io_int_exts_0
);
wire[31:0] imem_io_core_r_data_out;
wire[31:0] imem_io_core_rw_data_out;
wire[31:0] imem_io_bus_data_out;
wire imem_io_bus_ready;
wire[31:0] dmem_io_core_data_out;
wire[31:0] dmem_io_bus_data_out;
wire[2:0] control_io_dec_imm_sel;
wire[1:0] control_io_dec_op1_sel;
wire[1:0] control_io_dec_op2_sel;
wire[3:0] control_io_exe_alu_type;
wire[2:0] control_io_exe_br_type;
wire[1:0] control_io_exe_csr_type;
wire[1:0] control_io_exe_mul_type;
wire[1:0] control_io_exe_rd_data_sel;
wire[3:0] control_io_exe_mem_type;
wire[1:0] control_io_mem_rd_data_sel;
wire[1:0] control_io_next_pc_sel_3;
wire[1:0] control_io_next_pc_sel_2;
wire[1:0] control_io_next_pc_sel_1;
wire[1:0] control_io_next_pc_sel_0;
wire[1:0] control_io_next_tid;
wire control_io_next_valid;
wire[1:0] control_io_dec_rs1_sel;
wire[1:0] control_io_dec_rs2_sel;
wire control_io_exe_valid;
wire control_io_exe_load;
wire control_io_exe_store;
wire control_io_exe_csr_write;
wire control_io_exe_exception;
wire[4:0] control_io_exe_cause;
wire control_io_exe_kill;
wire control_io_exe_sleep;
wire control_io_exe_ie;
wire control_io_exe_ee;
wire control_io_exe_sret;
wire control_io_exe_cycle;
wire control_io_exe_instret;
wire control_io_mem_rd_write;
wire[1:0] datapath_io_control_if_tid;
wire[1:0] datapath_io_control_dec_tid;
wire[31:0] datapath_io_control_dec_inst;
wire datapath_io_control_exe_br_cond;
wire[1:0] datapath_io_control_exe_tid;
wire[4:0] datapath_io_control_exe_rd_addr;
wire datapath_io_control_exe_expire;
wire[3:0] datapath_io_control_csr_slots_7;
wire[3:0] datapath_io_control_csr_slots_6;
wire[3:0] datapath_io_control_csr_slots_5;
wire[3:0] datapath_io_control_csr_slots_4;
wire[3:0] datapath_io_control_csr_slots_3;
wire[3:0] datapath_io_control_csr_slots_2;
wire[3:0] datapath_io_control_csr_slots_1;
wire[3:0] datapath_io_control_csr_slots_0;
wire[1:0] datapath_io_control_csr_tmodes_3;
wire[1:0] datapath_io_control_csr_tmodes_2;
wire[1:0] datapath_io_control_csr_tmodes_1;
wire[1:0] datapath_io_control_csr_tmodes_0;
wire[1:0] datapath_io_control_mem_tid;
wire[4:0] datapath_io_control_mem_rd_addr;
wire[1:0] datapath_io_control_wb_tid;
wire[4:0] datapath_io_control_wb_rd_addr;
wire datapath_io_control_if_exc_misaligned;
wire datapath_io_control_if_exc_fault;
wire datapath_io_control_exe_exc_priv_inst;
wire datapath_io_control_exe_exc_load_misaligned;
wire datapath_io_control_exe_exc_load_fault;
wire datapath_io_control_exe_exc_store_misaligned;
wire datapath_io_control_exe_exc_store_fault;
wire datapath_io_control_exe_exc_expire;
wire datapath_io_control_exe_int_expire;
wire datapath_io_control_exe_int_ext;
wire[12:0] datapath_io_imem_r_addr;
wire datapath_io_imem_r_enable;
wire[12:0] datapath_io_imem_rw_addr;
wire datapath_io_imem_rw_enable;
wire datapath_io_imem_rw_write;
wire[31:0] datapath_io_imem_rw_data_in;
wire[12:0] datapath_io_dmem_addr;
wire datapath_io_dmem_enable;
wire datapath_io_dmem_byte_write_3;
wire datapath_io_dmem_byte_write_2;
wire datapath_io_dmem_byte_write_1;
wire datapath_io_dmem_byte_write_0;
wire[31:0] datapath_io_dmem_data_in;
wire[9:0] datapath_io_bus_addr;
wire datapath_io_bus_enable;
wire datapath_io_bus_write;
wire[31:0] datapath_io_bus_data_in;
wire[31:0] datapath_io_host_to_host;
wire[1:0] datapath_io_gpio_out_3;
wire[1:0] datapath_io_gpio_out_2;
wire[1:0] datapath_io_gpio_out_1;
wire[1:0] datapath_io_gpio_out_0;
assign io_gpio_out_0 = datapath_io_gpio_out_0;
assign io_gpio_out_1 = datapath_io_gpio_out_1;
assign io_gpio_out_2 = datapath_io_gpio_out_2;
assign io_gpio_out_3 = datapath_io_gpio_out_3;
assign io_host_to_host = datapath_io_host_to_host;
assign io_bus_data_in = datapath_io_bus_data_in;
assign io_bus_write = datapath_io_bus_write;
assign io_bus_enable = datapath_io_bus_enable;
assign io_bus_addr = datapath_io_bus_addr;
assign io_dmem_data_out = dmem_io_bus_data_out;
assign io_imem_ready = imem_io_bus_ready;
assign io_imem_data_out = imem_io_bus_data_out;
Control control(.clk(clk), .reset(reset),
.io_dec_imm_sel( control_io_dec_imm_sel ),
.io_dec_op1_sel( control_io_dec_op1_sel ),
.io_dec_op2_sel( control_io_dec_op2_sel ),
.io_exe_alu_type( control_io_exe_alu_type ),
.io_exe_br_type( control_io_exe_br_type ),
.io_exe_csr_type( control_io_exe_csr_type ),
.io_exe_mul_type( control_io_exe_mul_type ),
.io_exe_rd_data_sel( control_io_exe_rd_data_sel ),
.io_exe_mem_type( control_io_exe_mem_type ),
.io_mem_rd_data_sel( control_io_mem_rd_data_sel ),
.io_next_pc_sel_3( control_io_next_pc_sel_3 ),
.io_next_pc_sel_2( control_io_next_pc_sel_2 ),
.io_next_pc_sel_1( control_io_next_pc_sel_1 ),
.io_next_pc_sel_0( control_io_next_pc_sel_0 ),
.io_next_tid( control_io_next_tid ),
.io_next_valid( control_io_next_valid ),
.io_dec_rs1_sel( control_io_dec_rs1_sel ),
.io_dec_rs2_sel( control_io_dec_rs2_sel ),
.io_exe_valid( control_io_exe_valid ),
.io_exe_load( control_io_exe_load ),
.io_exe_store( control_io_exe_store ),
.io_exe_csr_write( control_io_exe_csr_write ),
.io_exe_exception( control_io_exe_exception ),
.io_exe_cause( control_io_exe_cause ),
.io_exe_kill( control_io_exe_kill ),
.io_exe_sleep( control_io_exe_sleep ),
.io_exe_ie( control_io_exe_ie ),
.io_exe_ee( control_io_exe_ee ),
.io_exe_sret( control_io_exe_sret ),
.io_exe_cycle( control_io_exe_cycle ),
.io_exe_instret( control_io_exe_instret ),
.io_mem_rd_write( control_io_mem_rd_write ),
.io_if_tid( datapath_io_control_if_tid ),
.io_dec_tid( datapath_io_control_dec_tid ),
.io_dec_inst( datapath_io_control_dec_inst ),
.io_exe_br_cond( datapath_io_control_exe_br_cond ),
.io_exe_tid( datapath_io_control_exe_tid ),
.io_exe_rd_addr( datapath_io_control_exe_rd_addr ),
.io_exe_expire( datapath_io_control_exe_expire ),
.io_csr_slots_7( datapath_io_control_csr_slots_7 ),
.io_csr_slots_6( datapath_io_control_csr_slots_6 ),
.io_csr_slots_5( datapath_io_control_csr_slots_5 ),
.io_csr_slots_4( datapath_io_control_csr_slots_4 ),
.io_csr_slots_3( datapath_io_control_csr_slots_3 ),
.io_csr_slots_2( datapath_io_control_csr_slots_2 ),
.io_csr_slots_1( datapath_io_control_csr_slots_1 ),
.io_csr_slots_0( datapath_io_control_csr_slots_0 ),
.io_csr_tmodes_3( datapath_io_control_csr_tmodes_3 ),
.io_csr_tmodes_2( datapath_io_control_csr_tmodes_2 ),
.io_csr_tmodes_1( datapath_io_control_csr_tmodes_1 ),
.io_csr_tmodes_0( datapath_io_control_csr_tmodes_0 ),
.io_mem_tid( datapath_io_control_mem_tid ),
.io_mem_rd_addr( datapath_io_control_mem_rd_addr ),
.io_wb_tid( datapath_io_control_wb_tid ),
.io_wb_rd_addr( datapath_io_control_wb_rd_addr ),
.io_if_exc_misaligned( datapath_io_control_if_exc_misaligned ),
.io_if_exc_fault( datapath_io_control_if_exc_fault ),
.io_exe_exc_priv_inst( datapath_io_control_exe_exc_priv_inst ),
.io_exe_exc_load_misaligned( datapath_io_control_exe_exc_load_misaligned ),
.io_exe_exc_load_fault( datapath_io_control_exe_exc_load_fault ),
.io_exe_exc_store_misaligned( datapath_io_control_exe_exc_store_misaligned ),
.io_exe_exc_store_fault( datapath_io_control_exe_exc_store_fault ),
.io_exe_exc_expire( datapath_io_control_exe_exc_expire ),
.io_exe_int_expire( datapath_io_control_exe_int_expire ),
.io_exe_int_ext( datapath_io_control_exe_int_ext )
);
Datapath datapath(.clk(clk), .reset(reset),
.io_control_dec_imm_sel( control_io_dec_imm_sel ),
.io_control_dec_op1_sel( control_io_dec_op1_sel ),
.io_control_dec_op2_sel( control_io_dec_op2_sel ),
.io_control_exe_alu_type( control_io_exe_alu_type ),
.io_control_exe_br_type( control_io_exe_br_type ),
.io_control_exe_csr_type( control_io_exe_csr_type ),
.io_control_exe_mul_type( control_io_exe_mul_type ),
.io_control_exe_rd_data_sel( control_io_exe_rd_data_sel ),
.io_control_exe_mem_type( control_io_exe_mem_type ),
.io_control_mem_rd_data_sel( control_io_mem_rd_data_sel ),
.io_control_next_pc_sel_3( control_io_next_pc_sel_3 ),
.io_control_next_pc_sel_2( control_io_next_pc_sel_2 ),
.io_control_next_pc_sel_1( control_io_next_pc_sel_1 ),
.io_control_next_pc_sel_0( control_io_next_pc_sel_0 ),
.io_control_next_tid( control_io_next_tid ),
.io_control_next_valid( control_io_next_valid ),
.io_control_dec_rs1_sel( control_io_dec_rs1_sel ),
.io_control_dec_rs2_sel( control_io_dec_rs2_sel ),
.io_control_exe_valid( control_io_exe_valid ),
.io_control_exe_load( control_io_exe_load ),
.io_control_exe_store( control_io_exe_store ),
.io_control_exe_csr_write( control_io_exe_csr_write ),
.io_control_exe_exception( control_io_exe_exception ),
.io_control_exe_cause( control_io_exe_cause ),
.io_control_exe_kill( control_io_exe_kill ),
.io_control_exe_sleep( control_io_exe_sleep ),
.io_control_exe_ie( control_io_exe_ie ),
.io_control_exe_ee( control_io_exe_ee ),
.io_control_exe_sret( control_io_exe_sret ),
.io_control_exe_cycle( control_io_exe_cycle ),
.io_control_exe_instret( control_io_exe_instret ),
.io_control_mem_rd_write( control_io_mem_rd_write ),
.io_control_if_tid( datapath_io_control_if_tid ),
.io_control_dec_tid( datapath_io_control_dec_tid ),
.io_control_dec_inst( datapath_io_control_dec_inst ),
.io_control_exe_br_cond( datapath_io_control_exe_br_cond ),
.io_control_exe_tid( datapath_io_control_exe_tid ),
.io_control_exe_rd_addr( datapath_io_control_exe_rd_addr ),
.io_control_exe_expire( datapath_io_control_exe_expire ),
.io_control_csr_slots_7( datapath_io_control_csr_slots_7 ),
.io_control_csr_slots_6( datapath_io_control_csr_slots_6 ),
.io_control_csr_slots_5( datapath_io_control_csr_slots_5 ),
.io_control_csr_slots_4( datapath_io_control_csr_slots_4 ),
.io_control_csr_slots_3( datapath_io_control_csr_slots_3 ),
.io_control_csr_slots_2( datapath_io_control_csr_slots_2 ),
.io_control_csr_slots_1( datapath_io_control_csr_slots_1 ),
.io_control_csr_slots_0( datapath_io_control_csr_slots_0 ),
.io_control_csr_tmodes_3( datapath_io_control_csr_tmodes_3 ),
.io_control_csr_tmodes_2( datapath_io_control_csr_tmodes_2 ),
.io_control_csr_tmodes_1( datapath_io_control_csr_tmodes_1 ),
.io_control_csr_tmodes_0( datapath_io_control_csr_tmodes_0 ),
.io_control_mem_tid( datapath_io_control_mem_tid ),
.io_control_mem_rd_addr( datapath_io_control_mem_rd_addr ),
.io_control_wb_tid( datapath_io_control_wb_tid ),
.io_control_wb_rd_addr( datapath_io_control_wb_rd_addr ),
.io_control_if_exc_misaligned( datapath_io_control_if_exc_misaligned ),
.io_control_if_exc_fault( datapath_io_control_if_exc_fault ),
.io_control_exe_exc_priv_inst( datapath_io_control_exe_exc_priv_inst ),
.io_control_exe_exc_load_misaligned( datapath_io_control_exe_exc_load_misaligned ),
.io_control_exe_exc_load_fault( datapath_io_control_exe_exc_load_fault ),
.io_control_exe_exc_store_misaligned( datapath_io_control_exe_exc_store_misaligned ),
.io_control_exe_exc_store_fault( datapath_io_control_exe_exc_store_fault ),
.io_control_exe_exc_expire( datapath_io_control_exe_exc_expire ),
.io_control_exe_int_expire( datapath_io_control_exe_int_expire ),
.io_control_exe_int_ext( datapath_io_control_exe_int_ext ),
.io_imem_r_addr( datapath_io_imem_r_addr ),
.io_imem_r_enable( datapath_io_imem_r_enable ),
.io_imem_r_data_out( imem_io_core_r_data_out ),
.io_imem_rw_addr( datapath_io_imem_rw_addr ),
.io_imem_rw_enable( datapath_io_imem_rw_enable ),
.io_imem_rw_data_out( imem_io_core_rw_data_out ),
.io_imem_rw_write( datapath_io_imem_rw_write ),
.io_imem_rw_data_in( datapath_io_imem_rw_data_in ),
.io_dmem_addr( datapath_io_dmem_addr ),
.io_dmem_enable( datapath_io_dmem_enable ),
.io_dmem_data_out( dmem_io_core_data_out ),
.io_dmem_byte_write_3( datapath_io_dmem_byte_write_3 ),
.io_dmem_byte_write_2( datapath_io_dmem_byte_write_2 ),
.io_dmem_byte_write_1( datapath_io_dmem_byte_write_1 ),
.io_dmem_byte_write_0( datapath_io_dmem_byte_write_0 ),
.io_dmem_data_in( datapath_io_dmem_data_in ),
.io_bus_addr( datapath_io_bus_addr ),
.io_bus_enable( datapath_io_bus_enable ),
.io_bus_data_out( io_bus_data_out ),
.io_bus_write( datapath_io_bus_write ),
.io_bus_data_in( datapath_io_bus_data_in ),
.io_host_to_host( datapath_io_host_to_host ),
.io_gpio_in_3( io_gpio_in_3 ),
.io_gpio_in_2( io_gpio_in_2 ),
.io_gpio_in_1( io_gpio_in_1 ),
.io_gpio_in_0( io_gpio_in_0 ),
.io_gpio_out_3( datapath_io_gpio_out_3 ),
.io_gpio_out_2( datapath_io_gpio_out_2 ),
.io_gpio_out_1( datapath_io_gpio_out_1 ),
.io_gpio_out_0( datapath_io_gpio_out_0 ),
.io_int_exts_3( io_int_exts_3 ),
.io_int_exts_2( io_int_exts_2 ),
.io_int_exts_1( io_int_exts_1 ),
.io_int_exts_0( io_int_exts_0 )
);
ISpm imem(.clk(clk),
.io_core_r_addr( datapath_io_imem_r_addr ),
.io_core_r_enable( datapath_io_imem_r_enable ),
.io_core_r_data_out( imem_io_core_r_data_out ),
.io_core_rw_addr( datapath_io_imem_rw_addr ),
.io_core_rw_enable( datapath_io_imem_rw_enable ),
.io_core_rw_data_out( imem_io_core_rw_data_out ),
.io_core_rw_write( datapath_io_imem_rw_write ),
.io_core_rw_data_in( datapath_io_imem_rw_data_in ),
.io_bus_addr( io_imem_addr ),
.io_bus_enable( io_imem_enable ),
.io_bus_data_out( imem_io_bus_data_out ),
.io_bus_write( io_imem_write ),
.io_bus_data_in( io_imem_data_in ),
.io_bus_ready( imem_io_bus_ready )
);
DSpm dmem(.clk(clk),
.io_core_addr( datapath_io_dmem_addr ),
.io_core_enable( datapath_io_dmem_enable ),
.io_core_data_out( dmem_io_core_data_out ),
.io_core_byte_write_3( datapath_io_dmem_byte_write_3 ),
.io_core_byte_write_2( datapath_io_dmem_byte_write_2 ),
.io_core_byte_write_1( datapath_io_dmem_byte_write_1 ),
.io_core_byte_write_0( datapath_io_dmem_byte_write_0 ),
.io_core_data_in( datapath_io_dmem_data_in ),
.io_bus_addr( io_dmem_addr ),
.io_bus_enable( io_dmem_enable ),
.io_bus_data_out( dmem_io_bus_data_out ),
.io_bus_byte_write_3( io_dmem_byte_write_3 ),
.io_bus_byte_write_2( io_dmem_byte_write_2 ),
.io_bus_byte_write_1( io_dmem_byte_write_1 ),
.io_bus_byte_write_0( io_dmem_byte_write_0 ),
.io_bus_data_in( io_dmem_data_in )
);
endmodule |
module
nextState = s0;
else
nextState = s5;
end
endcase
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd
(m_valid_i,
SR,
aa_grant_rnw,
D,
\m_atarget_hot_reg[2] ,
Q,
\m_atarget_hot_reg[2]_0 ,
\m_atarget_hot_reg[3] ,
s_ready_i_reg,
m_valid_i_reg,
\m_ready_d_reg[2] ,
s_axi_bvalid,
m_axi_bready,
\m_ready_d_reg[2]_0 ,
s_axi_wready,
m_ready_d0,
m_axi_wvalid,
m_axi_awvalid,
\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
E,
m_axi_arvalid,
\gen_axilite.s_axi_rvalid_i_reg ,
s_axi_awready,
s_axi_arready,
s_axi_rvalid,
\gen_axilite.s_axi_awready_i_reg ,
aclk,
\aresetn_d_reg[1] ,
aresetn_d,
m_ready_d,
\m_atarget_enc_reg[0] ,
\gen_axilite.s_axi_bvalid_i_reg ,
\m_atarget_hot_reg[3]_0 ,
s_axi_bready,
\gen_axilite.s_axi_awready_i_reg_0 ,
s_axi_wvalid,
m_valid_i_reg_0,
\gen_axilite.s_axi_arready_i_reg ,
m_ready_d_0,
aa_rready,
\gen_axilite.s_axi_rvalid_i_reg_0 ,
s_axi_rready,
sr_rvalid,
s_axi_arprot,
s_axi_arvalid,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr,
\m_ready_d_reg[2]_1 ,
s_axi_awvalid,
mi_bvalid,
mi_wready);
output m_valid_i;
output [0:0]SR;
output aa_grant_rnw;
output [3:0]D;
output \m_atarget_hot_reg[2] ;
output [34:0]Q;
output \m_atarget_hot_reg[2]_0 ;
output \m_atarget_hot_reg[3] ;
output s_ready_i_reg;
output m_valid_i_reg;
output \m_ready_d_reg[2] ;
output [0:0]s_axi_bvalid;
output [2:0]m_axi_bready;
output \m_ready_d_reg[2]_0 ;
output [0:0]s_axi_wready;
output [0:0]m_ready_d0;
output [2:0]m_axi_wvalid;
output [2:0]m_axi_awvalid;
output \gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
output [0:0]E;
output [2:0]m_axi_arvalid;
output \gen_axilite.s_axi_rvalid_i_reg ;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
output \gen_axilite.s_axi_awready_i_reg ;
input aclk;
input [1:0]\aresetn_d_reg[1] ;
input aresetn_d;
input [2:0]m_ready_d;
input \m_atarget_enc_reg[0] ;
input \gen_axilite.s_axi_bvalid_i_reg ;
input [3:0]\m_atarget_hot_reg[3]_0 ;
input [0:0]s_axi_bready;
input \gen_axilite.s_axi_awready_i_reg_0 ;
input [0:0]s_axi_wvalid;
input m_valid_i_reg_0;
input \gen_axilite.s_axi_arready_i_reg ;
input [1:0]m_ready_d_0;
input aa_rready;
input \gen_axilite.s_axi_rvalid_i_reg_0 ;
input [0:0]s_axi_rready;
input sr_rvalid;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
input \m_ready_d_reg[2]_1 ;
input [0:0]s_axi_awvalid;
input [0:0]mi_bvalid;
input [0:0]mi_wready;
wire [3:0]D;
wire [0:0]E;
wire [34:0]Q;
wire [0:0]SR;
wire aa_grant_any;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire aresetn_d;
wire [1:0]\aresetn_d_reg[1] ;
wire \gen_axilite.s_axi_arready_i_reg ;
wire \gen_axilite.s_axi_awready_i_i_2_n_0 ;
wire \gen_axilite.s_axi_awready_i_reg ;
wire \gen_axilite.s_axi_awready_i_reg_0 ;
wire \gen_axilite.s_axi_bvalid_i_reg ;
wire \gen_axilite.s_axi_rvalid_i_reg ;
wire \gen_axilite.s_axi_rvalid_i_reg_0 ;
wire \gen_no_arbiter.grant_rnw_i_1_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_2_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
wire \m_atarget_enc_reg[0] ;
wire \m_atarget_hot[3]_i_5_n_0 ;
wire \m_atarget_hot_reg[2] ;
wire \m_atarget_hot_reg[2]_0 ;
wire \m_atarget_hot_reg[3] ;
wire [3:0]\m_atarget_hot_reg[3]_0 ;
wire [2:0]m_axi_arvalid;
wire [2:0]m_axi_awvalid;
wire [2:0]m_axi_bready;
wire [2:0]m_axi_wvalid;
wire [2:0]m_ready_d;
wire [0:0]m_ready_d0;
wire [1:0]m_ready_d_0;
wire \m_ready_d_reg[2] ;
wire \m_ready_d_reg[2]_0 ;
wire \m_ready_d_reg[2]_1 ;
wire m_valid_i;
wire m_valid_i_i_2_n_0;
wire m_valid_i_i_3_n_0;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire [0:0]mi_bvalid;
wire [0:0]mi_wready;
wire p_0_in1_in;
wire [48:1]s_amesg;
wire \s_arvalid_reg[0]_i_1_n_0 ;
wire \s_arvalid_reg_reg_n_0_[0] ;
wire s_awvalid_reg;
wire \s_awvalid_reg[0]_i_1_n_0 ;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i;
wire s_ready_i_reg;
wire sr_rvalid;
LUT6 #(
.INIT(64'hFFFFFFFB00000004))
\gen_axilite.s_axi_awready_i_i_1
(.I0(\gen_axilite.s_axi_awready_i_i_2_n_0 ),
.I1(\m_atarget_hot_reg[3]_0 [3]),
.I2(m_ready_d[2]),
.I3(\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
.I4(mi_bvalid),
.I5(mi_wready),
.O(\gen_axilite.s_axi_awready_i_reg ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFBFF))
\gen_axilite.s_axi_awready_i_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d[1]),
.I3(s_axi_wvalid),
.O(\gen_axilite.s_axi_awready_i_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h40))
\gen_axilite.s_axi_rvalid_i_i_2
(.I0(m_ready_d_0[1]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.O(\gen_axilite.s_axi_rvalid_i_reg ));
LUT6 #(
.INIT(64'hFFFFFF5300000050))
\gen_no_arbiter.grant_rnw_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.I3(aa_grant_any),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(\gen_no_arbiter.grant_rnw_i_1_n_0 ));
FDRE \gen_no_arbiter.grant_rnw_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.grant_rnw_i_1_n_0 ),
.Q(aa_grant_rnw),
.R(SR));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[10]_i_1
(.I0(s_axi_araddr[9]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[9]),
.O(s_amesg[10]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[11]_i_1
(.I0(s_axi_araddr[10]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[10]),
.O(s_amesg[11]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[12]_i_1
(.I0(s_axi_araddr[11]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[11]),
.O(s_amesg[12]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[13]_i_1
(.I0(s_axi_araddr[12]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[12]),
.O(s_amesg[13]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[14]_i_1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[13]),
.O(s_amesg[14]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[15]_i_1
(.I0(s_axi_araddr[14]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[14]),
.O(s_amesg[15]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[16]_i_1
(.I0(s_axi_araddr[15]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[15]),
.O(s_amesg[16]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[17]_i_1
(.I0(s_axi_araddr[16]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[16]),
.O(s_amesg[17]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[18]_i_1
(.I0(s_axi_araddr[17]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[17]),
.O(s_amesg[18]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[19]_i_1
(.I0(s_axi_araddr[18]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[18]),
.O(s_amesg[19]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[1]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[0]),
.O(s_amesg[1]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[20]_i_1
(.I0(s_axi_araddr[19]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[19]),
.O(s_amesg[20]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[21]_i_1
(.I0(s_axi_araddr[20]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[20]),
.O(s_amesg[21]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[22]_i_1
(.I0(s_axi_araddr[21]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[21]),
.O(s_amesg[22]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[23]_i_1
(.I0(s_axi_araddr[22]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[22]),
.O(s_amesg[23]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[24]_i_1
(.I0(s_axi_araddr[23]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[23]),
.O(s_amesg[24]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[25]_i_1
(.I0(s_axi_araddr[24]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[24]),
.O(s_amesg[25]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[26]_i_1
(.I0(s_axi_araddr[25]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[25]),
.O(s_amesg[26]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[27]_i_1
(.I0(s_axi_araddr[26]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[26]),
.O(s_amesg[27]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[28]_i_1
(.I0(s_axi_araddr[27]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[27]),
.O(s_amesg[28]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[29]_i_1
(.I0(s_axi_araddr[28]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[28]),
.O(s_amesg[29]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[2]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[1]),
.O(s_amesg[2]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[30]_i_1
(.I0(s_axi_araddr[29]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[29]),
.O(s_amesg[30]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[31]_i_1
(.I0(s_axi_araddr[30]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[30]),
.O(s_amesg[31]));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[32]_i_1
(.I0(aresetn_d),
.O(SR));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[32]_i_2
(.I0(aa_grant_any),
.O(p_0_in1_in));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[32]_i_3
(.I0(s_axi_araddr[31]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[31]),
.O(s_amesg[32]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[3]_i_1
(.I0(s_axi_araddr[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[2]),
.O(s_amesg[3]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[46]_i_1
(.I0(s_axi_arprot[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[0]),
.O(s_amesg[46]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[47]_i_1
(.I0(s_axi_arprot[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[1]),
.O(s_amesg[47]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[48]_i_1
(.I0(s_axi_arprot[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[2]),
.O(s_amesg[48]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[4]_i_1
(.I0(s_axi_araddr[3]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[3]),
.O(s_amesg[4]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[5]_i_1
(.I0(s_axi_araddr[4]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[4]),
.O(s_amesg[5]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[6]_i_1
(.I0(s_axi_araddr[5]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[5]),
.O(s_amesg[6]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[7]_i_1
(.I0(s_axi_araddr[6]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[6]),
.O(s_amesg[7]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[8]_i_1
(.I0(s_axi_araddr[7]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[7]),
.O(s_amesg[8]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[9]_i_1
(.I0(s_axi_araddr[8]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[8]),
.O(s_amesg[9]));
FDRE \gen_no_arbiter.m_amesg_i_reg[10]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[10]),
.Q(Q[9]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[11]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[11]),
.Q(Q[10]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[12]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[12]),
.Q(Q[11]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[13]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[13]),
.Q(Q[12]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[14]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[14]),
.Q(Q[13]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[15]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[15]),
.Q(Q[14]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[16]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[16]),
.Q(Q[15]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[17]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[17]),
.Q(Q[16]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[18]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[18]),
.Q(Q[17]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[19]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[19]),
.Q(Q[18]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[1]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[1]),
.Q(Q[0]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[20]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[20]),
.Q(Q[19]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[21]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[21]),
.Q(Q[20]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[22]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[22]),
.Q(Q[21]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[23]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[23]),
.Q(Q[22]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[24]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[24]),
.Q(Q[23]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[25]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[25]),
.Q(Q[24]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[26]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[26]),
.Q(Q[25]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[27]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[27]),
.Q(Q[26]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[28]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[28]),
.Q(Q[27]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[29]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[29]),
.Q(Q[28]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[2]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[2]),
.Q(Q[1]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[30]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[30]),
.Q(Q[29]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[31]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[31]),
.Q(Q[30]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[32]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[32]),
.Q(Q[31]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[3]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[3]),
.Q(Q[2]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[46]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[46]),
.Q(Q[32]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[47]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[47]),
.Q(Q[33]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[48]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[48]),
.Q(Q[34]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[4]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[4]),
.Q(Q[3]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[5]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[5]),
.Q(Q[4]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[6]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[6]),
.Q(Q[5]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[7]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[7]),
.Q(Q[6]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[8]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[8]),
.Q(Q[7]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[9]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[9]),
.Q(Q[8]),
.R(SR));
LUT6 #(
.INIT(64'h0000000088888088))
\gen_no_arbiter.m_grant_hot_i[0]_i_1
(.I0(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
.I1(aresetn_d),
.I2(\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
.I3(m_ready_d0),
.I4(\m_ready_d_reg[2]_1 ),
.I5(\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hF0FE))
\gen_no_arbiter.m_grant_hot_i[0]_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_arvalid),
.I2(aa_grant_any),
.I3(m_valid_i),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'hB))
\gen_no_arbiter.m_grant_hot_i[0]_i_3
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h51000000))
\gen_no_arbiter.m_grant_hot_i[0]_i_5
(.I0(m_valid_i_reg_0),
.I1(\gen_axilite.s_axi_arready_i_reg ),
.I2(m_ready_d_0[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0 ));
FDRE \gen_no_arbiter.m_grant_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
.Q(aa_grant_any),
.R(1'b0));
LUT6 #(
.INIT(64'h3AFA3A0A3AFA3AFA))
\gen_no_arbiter.m_valid_i_i_1
(.I0(aa_grant_any),
.I1(\gen_no_arbiter.m_valid_i_i_2_n_0 ),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(\m_ready_d_reg[2]_1 ),
.I5(m_ready_d0),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h0000F0F8))
\gen_no_arbiter.m_valid_i_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d_0[1]),
.I3(\gen_axilite.s_axi_arready_i_reg ),
.I4(m_valid_i_reg_0),
.O(\gen_no_arbiter.m_valid_i_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(m_valid_i),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h40))
\gen_no_arbiter.s_ready_i[0]_i_1
(.I0(m_valid_i),
.I1(aa_grant_any),
.I2(aresetn_d),
.O(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
.Q(s_ready_i),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0010))
\m_atarget_hot[0]_i_1
(.I0(\m_atarget_hot_reg[2]_0 ),
.I1(Q[16]),
.I2(aa_grant_any),
.I3(\m_atarget_hot_reg[3] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0400))
\m_atarget_hot[1]_i_1
(.I0(\m_atarget_hot_reg[3] ),
.I1(Q[16]),
.I2(\m_atarget_hot_reg[2]_0 ),
.I3(aa_grant_any),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h0100))
\m_atarget_hot[2]_i_1
(.I0(\m_atarget_hot_reg[2] ),
.I1(Q[16]),
.I2(\m_atarget_hot_reg[2]_0 ),
.I3(aa_grant_any),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFEAA0000))
\m_atarget_hot[3]_i_1
(.I0(\m_atarget_hot_reg[2]_0 ),
.I1(Q[16]),
.I2(\m_atarget_hot_reg[2] ),
.I3(\m_atarget_hot_reg[3] ),
.I4(aa_grant_any),
.O(D[3]));
LUT4 #(
.INIT(16'hFFFE))
\m_atarget_hot[3]_i_2
(.I0(Q[26]),
.I1(Q[27]),
.I2(Q[29]),
.I3(\m_atarget_hot[3]_i_5_n_0 ),
.O(\m_atarget_hot_reg[2]_0 ));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFF))
\m_atarget_hot[3]_i_3
(.I0(Q[20]),
.I1(Q[24]),
.I2(Q[21]),
.I3(Q[22]),
.I4(Q[23]),
.I5(Q[25]),
.O(\m_atarget_hot_reg[2] ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF7))
\m_atarget_hot[3]_i_4
(.I0(Q[21]),
.I1(Q[24]),
.I2(Q[20]),
.I3(Q[23]),
.I4(Q[22]),
.I5(Q[25]),
.O(\m_atarget_hot_reg[3] ));
LUT6 #(
.INIT(64'hFFFFFFFEFFFFFFFF))
\m_atarget_hot[3]_i_5
(.I0(Q[31]),
.I1(Q[28]),
.I2(Q[18]),
.I3(Q[19]),
.I4(Q[17]),
.I5(Q[30]),
.O(\m_atarget_hot[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[2]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [2]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[2]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [2]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[0]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [0]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[0]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[1]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [1]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[1]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[2]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [2]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[2]));
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [0]),
.I1(s_axi_wvalid),
.I2(m_ready_d[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_axi_wvalid[0]));
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [1]),
.I1(s_axi_wvalid),
.I2(m_ready_d[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_axi_wvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[2]_INST_0
(.I0(\m_atarget_hot_reg[3]_0 [2]),
.I1(s_axi_wvalid),
.I2(m_ready_d[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_axi_wvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h0080FFFF))
\m_payload_i[34]_i_1
(.I0(s_axi_rready),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[0]),
.I4(sr_rvalid),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hF0F4F0F0))
\m_ready_d[2]_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d[1]),
.I3(\gen_axilite.s_axi_awready_i_reg_0 ),
.I4(s_axi_wvalid),
.O(m_ready_d0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0020))
\m_ready_d[2]_i_3
(.I0(s_axi_bready),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[0]),
.O(\m_ready_d_reg[2]_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h4555))
\m_ready_d[2]_i_4
(.I0(m_ready_d[2]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(\m_atarget_enc_reg[0] ),
.O(\m_ready_d_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hA2))
m_valid_i_i_1
(.I0(\aresetn_d_reg[1] [1]),
.I1(m_valid_i_i_2_n_0),
.I2(m_valid_i_i_3_n_0),
.O(m_valid_i_reg));
LUT5 #(
.INIT(32'h8AAAAAAA))
m_valid_i_i_2
(.I0(aa_rready),
.I1(m_ready_d_0[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(\gen_axilite.s_axi_rvalid_i_reg_0 ),
.O(m_valid_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h8AAAAAAA))
m_valid_i_i_3
(.I0(sr_rvalid),
.I1(m_ready_d_0[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_rready),
.O(m_valid_i_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0040))
\s_arvalid_reg[0]_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_arvalid),
.I2(aresetn_d),
.I3(s_ready_i),
.O(\s_arvalid_reg[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_arvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_arvalid_reg[0]_i_1_n_0 ),
.Q(\s_arvalid_reg_reg_n_0_[0] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000D00000))
\s_awvalid_reg[0]_i_1
(.I0(s_axi_arvalid),
.I1(s_awvalid_reg),
.I2(s_axi_awvalid),
.I3(\s_arvalid_reg_reg_n_0_[0] ),
.I4(aresetn_d),
.I5(s_ready_i),
.O(\s_awvalid_reg[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_awvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_awvalid_reg[0]_i_1_n_0 ),
.Q(s_awvalid_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
\s_axi_arready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_arready));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\s_axi_awready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_awready));
LUT5 #(
.INIT(32'h00000400))
\s_axi_bvalid[0]_INST_0
(.I0(m_ready_d[0]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(aa_grant_any),
.I4(\gen_axilite.s_axi_bvalid_i_reg ),
.O(s_axi_bvalid));
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[0]_INST_0
(.I0(aa_grant_any),
.I1(sr_rvalid),
.O(s_axi_rvalid));
LUT5 #(
.INIT(32'h00000200))
\s_axi_wready[0]_INST_0
(.I0(aa_grant_any),
.I1(\gen_axilite.s_axi_awready_i_reg_0 ),
.I2(m_ready_d[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(s_axi_wready));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hA2))
s_ready_i_i_1
(.I0(\aresetn_d_reg[1] [0]),
.I1(m_valid_i_i_3_n_0),
.I2(m_valid_i_i_2_n_0),
.O(s_ready_i_reg));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [0:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wuser;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [2:0]m_axi_awid;
output [95:0]m_axi_awaddr;
output [23:0]m_axi_awlen;
output [8:0]m_axi_awsize;
output [5:0]m_axi_awburst;
output [2:0]m_axi_awlock;
output [11:0]m_axi_awcache;
output [8:0]m_axi_awprot;
output [11:0]m_axi_awregion;
output [11:0]m_axi_awqos;
output [2:0]m_axi_awuser;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [2:0]m_axi_wid;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wlast;
output [2:0]m_axi_wuser;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [2:0]m_axi_bid;
input [5:0]m_axi_bresp;
input [2:0]m_axi_buser;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [2:0]m_axi_arid;
output [95:0]m_axi_araddr;
output [23:0]m_axi_arlen;
output [8:0]m_axi_arsize;
output [5:0]m_axi_arburst;
output [2:0]m_axi_arlock;
output [11:0]m_axi_arcache;
output [8:0]m_axi_arprot;
output [11:0]m_axi_arregion;
output [11:0]m_axi_arqos;
output [2:0]m_axi_aruser;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [2:0]m_axi_rid;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rlast;
input [2:0]m_axi_ruser;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [15:0]\^m_axi_araddr ;
wire [2:0]\^m_axi_arprot ;
wire [2:0]m_axi_arready;
wire [2:0]m_axi_arvalid;
wire [95:80]\^m_axi_awaddr ;
wire [2:0]m_axi_awready;
wire [2:0]m_axi_awvalid;
wire [2:0]m_axi_bready;
wire [5:0]m_axi_bresp;
wire [2:0]m_axi_bvalid;
wire [95:0]m_axi_rdata;
wire [2:0]m_axi_rready;
wire [5:0]m_axi_rresp;
wire [2:0]m_axi_rvalid;
wire [2:0]m_axi_wready;
wire [2:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
assign m_axi_araddr[95:80] = \^m_axi_awaddr [95:80];
assign m_axi_araddr[79:64] = \^m_axi_araddr [15:0];
assign m_axi_araddr[63:48] = \^m_axi_awaddr [95:80];
assign m_axi_araddr[47:32] = \^m_axi_araddr [15:0];
assign m_axi_araddr[31:16] = \^m_axi_awaddr [95:80];
assign m_axi_araddr[15:0] = \^m_axi_araddr [15:0];
assign m_axi_arburst[5] = \<const0> ;
assign m_axi_arburst[4] = \<const0> ;
assign m_axi_arburst[3] = \<const0> ;
assign m_axi_arburst[2] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[11] = \<const0> ;
assign m_axi_arcache[10] = \<const0> ;
assign m_axi_arcache[9] = \<const0> ;
assign m_axi_arcache[8] = \<const0> ;
assign m_axi_arcache[7] = \<const0> ;
assign m_axi_arcache[6] = \<const0> ;
assign m_axi_arcache[5] = \<const0> ;
assign m_axi_arcache[4] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[23] = \<const0> ;
assign m_axi_arlen[22] = \<const0> ;
assign m_axi_arlen[21] = \<const0> ;
assign m_axi_arlen[20] = \<const0> ;
assign m_axi_arlen[19] = \<const0> ;
assign m_axi_arlen[18] = \<const0> ;
assign m_axi_arlen[17] = \<const0> ;
assign m_axi_arlen[16] = \<const0> ;
assign m_axi_arlen[15] = \<const0> ;
assign m_axi_arlen[14] = \<const0> ;
assign m_axi_arlen[13] = \<const0> ;
assign m_axi_arlen[12] = \<const0> ;
assign m_axi_arlen[11] = \<const0> ;
assign m_axi_arlen[10] = \<const0> ;
assign m_axi_arlen[9] = \<const0> ;
assign m_axi_arlen[8] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[2] = \<const0> ;
assign m_axi_arlock[1] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_arprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_arprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_arqos[11] = \<const0> ;
assign m_axi_arqos[10] = \<const0> ;
assign m_axi_arqos[9] = \<const0> ;
assign m_axi_arqos[8] = \<const0> ;
assign m_axi_arqos[7] = \<const0> ;
assign m_axi_arqos[6] = \<const0> ;
assign m_axi_arqos[5] = \<const0> ;
assign m_axi_arqos[4] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[11] = \<const0> ;
assign m_axi_arregion[10] = \<const0> ;
assign m_axi_arregion[9] = \<const0> ;
assign m_axi_arregion[8] = \<const0> ;
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[8] = \<const0> ;
assign m_axi_arsize[7] = \<const0> ;
assign m_axi_arsize[6] = \<const0> ;
assign m_axi_arsize[5] = \<const0> ;
assign m_axi_arsize[4] = \<const0> ;
assign m_axi_arsize[3] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[2] = \<const0> ;
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awaddr[95:80] = \^m_axi_awaddr [95:80];
assign m_axi_awaddr[79:64] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[63:48] = \^m_axi_awaddr [95:80];
assign m_axi_awaddr[47:32] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[31:16] = \^m_axi_awaddr [95:80];
assign m_axi_awaddr[15:0] = \^m_axi_araddr [15:0];
assign m_axi_awburst[5] = \<const0> ;
assign m_axi_awburst[4] = \<const0> ;
assign m_axi_awburst[3] = \<const0> ;
assign m_axi_awburst[2] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[11] = \<const0> ;
assign m_axi_awcache[10] = \<const0> ;
assign m_axi_awcache[9] = \<const0> ;
assign m_axi_awcache[8] = \<const0> ;
assign m_axi_awcache[7] = \<const0> ;
assign m_axi_awcache[6] = \<const0> ;
assign m_axi_awcache[5] = \<const0> ;
assign m_axi_awcache[4] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[23] = \<const0> ;
assign m_axi_awlen[22] = \<const0> ;
assign m_axi_awlen[21] = \<const0> ;
assign m_axi_awlen[20] = \<const0> ;
assign m_axi_awlen[19] = \<const0> ;
assign m_axi_awlen[18] = \<const0> ;
assign m_axi_awlen[17] = \<const0> ;
assign m_axi_awlen[16] = \<const0> ;
assign m_axi_awlen[15] = \<const0> ;
assign m_axi_awlen[14] = \<const0> ;
assign m_axi_awlen[13] = \<const0> ;
assign m_axi_awlen[12] = \<const0> ;
assign m_axi_awlen[11] = \<const0> ;
assign m_axi_awlen[10] = \<const0> ;
assign m_axi_awlen[9] = \<const0> ;
assign m_axi_awlen[8] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[2] = \<const0> ;
assign m_axi_awlock[1] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_awprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_awprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_awqos[11] = \<const0> ;
assign m_axi_awqos[10] = \<const0> ;
assign m_axi_awqos[9] = \<const0> ;
assign m_axi_awqos[8] = \<const0> ;
assign m_axi_awqos[7] = \<const0> ;
assign m_axi_awqos[6] = \<const0> ;
assign m_axi_awqos[5] = \<const0> ;
assign m_axi_awqos[4] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[11] = \<const0> ;
assign m_axi_awregion[10] = \<const0> ;
assign m_axi_awregion[9] = \<const0> ;
assign m_axi_awregion[8] = \<const0> ;
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[8] = \<const0> ;
assign m_axi_awsize[7] = \<const0> ;
assign m_axi_awsize[6] = \<const0> ;
assign m_axi_awsize[5] = \<const0> ;
assign m_axi_awsize[4] = \<const0> ;
assign m_axi_awsize[3] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[2] = \<const0> ;
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[95:64] = s_axi_wdata;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[2] = \<const0> ;
assign m_axi_wlast[1] = \<const0> ;
assign m_axi_wlast[0] = \<const0> ;
assign m_axi_wstrb[11:8] = s_axi_wstrb;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[2] = \<const0> ;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd \gen_sasd.crossbar_sasd_0
(.Q({\^m_axi_arprot ,\^m_axi_awaddr ,\^m_axi_araddr }),
.aclk(aclk),
.aresetn(aresetn),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd
(Q,
\s_axi_rdata[31] ,
s_axi_bvalid,
m_axi_bready,
s_axi_wready,
m_axi_wvalid,
m_axi_awvalid,
m_axi_arvalid,
s_axi_bresp,
s_axi_awready,
s_axi_arready,
s_axi_rvalid,
m_axi_rready,
aresetn,
aclk,
s_axi_bready,
s_axi_wvalid,
s_axi_rready,
m_axi_rresp,
m_axi_rvalid,
m_axi_wready,
m_axi_awready,
m_axi_bvalid,
m_axi_arready,
m_axi_rdata,
m_axi_bresp,
s_axi_arprot,
s_axi_arvalid,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr,
s_axi_awvalid);
output [34:0]Q;
output [33:0]\s_axi_rdata[31] ;
output [0:0]s_axi_bvalid;
output [2:0]m_axi_bready;
output [0:0]s_axi_wready;
output [2:0]m_axi_wvalid;
output [2:0]m_axi_awvalid;
output [2:0]m_axi_arvalid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
output [2:0]m_axi_rready;
input aresetn;
input aclk;
input [0:0]s_axi_bready;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_rready;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
input [2:0]m_axi_wready;
input [2:0]m_axi_awready;
input [2:0]m_axi_bvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_bresp;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
input [0:0]s_axi_awvalid;
wire [34:0]Q;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire addr_arbiter_inst_n_3;
wire addr_arbiter_inst_n_4;
wire addr_arbiter_inst_n_43;
wire addr_arbiter_inst_n_44;
wire addr_arbiter_inst_n_45;
wire addr_arbiter_inst_n_46;
wire addr_arbiter_inst_n_47;
wire addr_arbiter_inst_n_5;
wire addr_arbiter_inst_n_52;
wire addr_arbiter_inst_n_61;
wire addr_arbiter_inst_n_66;
wire addr_arbiter_inst_n_7;
wire addr_arbiter_inst_n_70;
wire aresetn;
wire aresetn_d;
wire \gen_decerr.decerr_slave_inst_n_2 ;
wire \gen_decerr.decerr_slave_inst_n_3 ;
wire \gen_decerr.decerr_slave_inst_n_4 ;
wire \gen_decerr.decerr_slave_inst_n_5 ;
wire \gen_decerr.decerr_slave_inst_n_6 ;
wire \gen_decerr.decerr_slave_inst_n_7 ;
wire [1:0]m_atarget_enc;
wire \m_atarget_enc[0]_i_1_n_0 ;
wire \m_atarget_enc[1]_i_1_n_0 ;
wire [3:0]m_atarget_hot;
wire [0:0]m_atarget_hot0;
wire [2:0]m_axi_arready;
wire [2:0]m_axi_arvalid;
wire [2:0]m_axi_awready;
wire [2:0]m_axi_awvalid;
wire [2:0]m_axi_bready;
wire [5:0]m_axi_bresp;
wire [2:0]m_axi_bvalid;
wire [95:0]m_axi_rdata;
wire [2:0]m_axi_rready;
wire [5:0]m_axi_rresp;
wire [2:0]m_axi_rvalid;
wire [2:0]m_axi_wready;
wire [2:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [1:1]m_ready_d0;
wire [2:0]m_ready_d_0;
wire m_valid_i;
wire [3:3]mi_bvalid;
wire [3:3]mi_wready;
wire p_1_in;
wire reg_slice_r_n_2;
wire reg_slice_r_n_6;
wire reg_slice_r_n_7;
wire reset;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [33:0]\s_axi_rdata[31] ;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire splitter_aw_n_0;
wire sr_rvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd addr_arbiter_inst
(.D({addr_arbiter_inst_n_3,addr_arbiter_inst_n_4,addr_arbiter_inst_n_5,m_atarget_hot0}),
.E(p_1_in),
.Q(Q),
.SR(reset),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\aresetn_d_reg[1] ({reg_slice_r_n_6,reg_slice_r_n_7}),
.\gen_axilite.s_axi_arready_i_reg (\gen_decerr.decerr_slave_inst_n_7 ),
.\gen_axilite.s_axi_awready_i_reg (addr_arbiter_inst_n_70),
.\gen_axilite.s_axi_awready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_6 ),
.\gen_axilite.s_axi_bvalid_i_reg (\gen_decerr.decerr_slave_inst_n_4 ),
.\gen_axilite.s_axi_rvalid_i_reg (addr_arbiter_inst_n_66),
.\gen_axilite.s_axi_rvalid_i_reg_0 (\gen_decerr.decerr_slave_inst_n_5 ),
.\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (addr_arbiter_inst_n_61),
.\m_atarget_enc_reg[0] (\gen_decerr.decerr_slave_inst_n_3 ),
.\m_atarget_hot_reg[2] (addr_arbiter_inst_n_7),
.\m_atarget_hot_reg[2]_0 (addr_arbiter_inst_n_43),
.\m_atarget_hot_reg[3] (addr_arbiter_inst_n_44),
.\m_atarget_hot_reg[3]_0 (m_atarget_hot),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d_0),
.m_ready_d0(m_ready_d0),
.m_ready_d_0(m_ready_d),
.\m_ready_d_reg[2] (addr_arbiter_inst_n_47),
.\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_52),
.\m_ready_d_reg[2]_1 (\gen_decerr.decerr_slave_inst_n_2 ),
.m_valid_i(m_valid_i),
.m_valid_i_reg(addr_arbiter_inst_n_46),
.m_valid_i_reg_0(reg_slice_r_n_2),
.mi_bvalid(mi_bvalid),
.mi_wready(mi_wready),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(addr_arbiter_inst_n_45),
.sr_rvalid(sr_rvalid));
FDRE #(
.INIT(1'b0))
aresetn_d_reg
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave \gen_decerr.decerr_slave_inst
(.Q(m_atarget_enc),
.SR(reset),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_61),
.\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_52),
.\gen_no_arbiter.m_grant_hot_i_reg[0] (\gen_decerr.decerr_slave_inst_n_2 ),
.\gen_no_arbiter.m_grant_hot_i_reg[0]_0 (\gen_decerr.decerr_slave_inst_n_3 ),
.\gen_no_arbiter.m_grant_hot_i_reg[0]_1 (\gen_decerr.decerr_slave_inst_n_6 ),
.\m_atarget_hot_reg[3] (addr_arbiter_inst_n_70),
.\m_atarget_hot_reg[3]_0 (m_atarget_hot[3]),
.m_axi_arready(m_axi_arready),
.m_axi_awready(m_axi_awready),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_ready_d({m_ready_d_0[2],m_ready_d_0[0]}),
.\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_7 ),
.\m_ready_d_reg[1]_0 (splitter_aw_n_0),
.\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_66),
.\m_ready_d_reg[2] (\gen_decerr.decerr_slave_inst_n_4 ),
.m_valid_i_reg(\gen_decerr.decerr_slave_inst_n_5 ),
.mi_bvalid(mi_bvalid),
.mi_wready(mi_wready),
.s_axi_bready(s_axi_bready));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT4 #(
.INIT(16'hFEEE))
\m_atarget_enc[0]_i_1
(.I0(addr_arbiter_inst_n_43),
.I1(Q[16]),
.I2(addr_arbiter_inst_n_7),
.I3(addr_arbiter_inst_n_44),
.O(\m_atarget_enc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT4 #(
.INIT(16'hFFAB))
\m_atarget_enc[1]_i_1
(.I0(addr_arbiter_inst_n_43),
.I1(Q[16]),
.I2(addr_arbiter_inst_n_7),
.I3(addr_arbiter_inst_n_44),
.O(\m_atarget_enc[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_atarget_enc[0]_i_1_n_0 ),
.Q(m_atarget_enc[0]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_atarget_enc[1]_i_1_n_0 ),
.Q(m_atarget_enc[1]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0),
.Q(m_atarget_hot[0]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_5),
.Q(m_atarget_hot[1]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_4),
.Q(m_atarget_hot[2]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[3]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_3),
.Q(m_atarget_hot[3]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice reg_slice_r
(.E(p_1_in),
.Q(m_atarget_enc),
.SR(reset),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.\aresetn_d_reg[0]_0 (addr_arbiter_inst_n_45),
.\aresetn_d_reg[1]_0 (addr_arbiter_inst_n_46),
.\m_atarget_hot_reg[2] (m_atarget_hot[2:0]),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_ready_d(m_ready_d[0]),
.\m_ready_d_reg[1] (reg_slice_r_n_2),
.m_valid_i(m_valid_i),
.m_valid_i_reg_0({reg_slice_r_n_6,reg_slice_r_n_7}),
.\s_axi_rdata[31] (\s_axi_rdata[31] ),
.s_axi_rready(s_axi_rready),
.sr_rvalid(sr_rvalid));
LUT5 #(
.INIT(32'hFCAFFCA0))
\s_axi_bresp[0]_INST_0
(.I0(m_axi_bresp[4]),
.I1(m_axi_bresp[2]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.I4(m_axi_bresp[0]),
.O(s_axi_bresp[0]));
LUT5 #(
.INIT(32'hFCAFFCA0))
\s_axi_bresp[1]_INST_0
(.I0(m_axi_bresp[5]),
.I1(m_axi_bresp[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.I4(m_axi_bresp[1]),
.O(s_axi_bresp[1]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0 splitter_ar
(.aa_grant_rnw(aa_grant_rnw),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axilite.s_axi_arready_i_reg (\gen_decerr.decerr_slave_inst_n_7 ),
.m_ready_d(m_ready_d),
.m_valid_i(m_valid_i),
.m_valid_i_reg(reg_slice_r_n_2));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter splitter_aw
(.Q(m_atarget_hot[3]),
.aa_grant_rnw(aa_grant_rnw),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axilite.s_axi_bvalid_i_reg (splitter_aw_n_0),
.\gen_axilite.s_axi_bvalid_i_reg_0 (\gen_decerr.decerr_slave_inst_n_4 ),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_52),
.m_ready_d(m_ready_d_0),
.m_ready_d0(m_ready_d0),
.\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_47),
.m_valid_i(m_valid_i),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave
(mi_bvalid,
mi_wready,
\gen_no_arbiter.m_grant_hot_i_reg[0] ,
\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ,
\m_ready_d_reg[2] ,
m_valid_i_reg,
\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ,
\m_ready_d_reg[1] ,
SR,
aclk,
\m_atarget_hot_reg[3] ,
m_ready_d,
\gen_no_arbiter.grant_rnw_reg ,
s_axi_bready,
m_axi_rvalid,
Q,
m_axi_wready,
m_axi_awready,
m_axi_bvalid,
m_axi_arready,
\m_atarget_hot_reg[3]_0 ,
\gen_no_arbiter.grant_rnw_reg_0 ,
\m_ready_d_reg[1]_0 ,
\m_ready_d_reg[1]_1 ,
aa_rready,
aresetn_d);
output [0:0]mi_bvalid;
output [0:0]mi_wready;
output \gen_no_arbiter.m_grant_hot_i_reg[0] ;
output \gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
output \m_ready_d_reg[2] ;
output m_valid_i_reg;
output \gen_no_arbiter.m_grant_hot_i_reg[0]_1 ;
output \m_ready_d_reg[1] ;
input [0:0]SR;
input aclk;
input \m_atarget_hot_reg[3] ;
input [1:0]m_ready_d;
input \gen_no_arbiter.grant_rnw_reg ;
input [0:0]s_axi_bready;
input [2:0]m_axi_rvalid;
input [1:0]Q;
input [2:0]m_axi_wready;
input [2:0]m_axi_awready;
input [2:0]m_axi_bvalid;
input [2:0]m_axi_arready;
input [0:0]\m_atarget_hot_reg[3]_0 ;
input \gen_no_arbiter.grant_rnw_reg_0 ;
input \m_ready_d_reg[1]_0 ;
input \m_ready_d_reg[1]_1 ;
input aa_rready;
input aresetn_d;
wire [1:0]Q;
wire [0:0]SR;
wire aa_rready;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_arready_i_i_1_n_0 ;
wire \gen_axilite.s_axi_bvalid_i_i_1_n_0 ;
wire \gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire \gen_no_arbiter.grant_rnw_reg_0 ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0] ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0]_0 ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0]_1 ;
wire \m_atarget_hot_reg[3] ;
wire [0:0]\m_atarget_hot_reg[3]_0 ;
wire [2:0]m_axi_arready;
wire [2:0]m_axi_awready;
wire [2:0]m_axi_bvalid;
wire [2:0]m_axi_rvalid;
wire [2:0]m_axi_wready;
wire [1:0]m_ready_d;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[2] ;
wire m_valid_i_reg;
wire [3:3]mi_arready;
wire [0:0]mi_bvalid;
wire [3:3]mi_rvalid;
wire [0:0]mi_wready;
wire [0:0]s_axi_bready;
LUT5 #(
.INIT(32'hAA2A00AA))
\gen_axilite.s_axi_arready_i_i_1
(.I0(aresetn_d),
.I1(\m_ready_d_reg[1]_1 ),
.I2(\m_atarget_hot_reg[3]_0 ),
.I3(mi_rvalid),
.I4(mi_arready),
.O(\gen_axilite.s_axi_arready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\m_atarget_hot_reg[3] ),
.Q(mi_wready),
.R(SR));
LUT5 #(
.INIT(32'h77770F00))
\gen_axilite.s_axi_bvalid_i_i_1
(.I0(\m_atarget_hot_reg[3]_0 ),
.I1(\gen_no_arbiter.grant_rnw_reg_0 ),
.I2(\m_ready_d_reg[1]_0 ),
.I3(mi_wready),
.I4(mi_bvalid),
.O(\gen_axilite.s_axi_bvalid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_bvalid_i_i_1_n_0 ),
.Q(mi_bvalid),
.R(SR));
LUT5 #(
.INIT(32'h0FFF8800))
\gen_axilite.s_axi_rvalid_i_i_1
(.I0(mi_arready),
.I1(\m_ready_d_reg[1]_1 ),
.I2(aa_rready),
.I3(\m_atarget_hot_reg[3]_0 ),
.I4(mi_rvalid),
.O(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_rvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
.Q(mi_rvalid),
.R(SR));
LUT6 #(
.INIT(64'h3F1F3F1F3F113F1F))
\gen_no_arbiter.m_grant_hot_i[0]_i_4
(.I0(\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ),
.I1(m_ready_d[1]),
.I2(m_ready_d[0]),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.I4(s_axi_bready),
.I5(\m_ready_d_reg[2] ),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0] ));
LUT6 #(
.INIT(64'h0F3300550F33FF55))
\m_ready_d[1]_i_2
(.I0(m_axi_arready[0]),
.I1(m_axi_arready[2]),
.I2(mi_arready),
.I3(Q[0]),
.I4(Q[1]),
.I5(m_axi_arready[1]),
.O(\m_ready_d_reg[1] ));
LUT6 #(
.INIT(64'hFFAAF0CC00AAF0CC))
\m_ready_d[2]_i_5
(.I0(m_axi_awready[2]),
.I1(m_axi_awready[0]),
.I2(m_axi_awready[1]),
.I3(Q[0]),
.I4(Q[1]),
.I5(mi_wready),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0]_0 ));
LUT6 #(
.INIT(64'hAAFFCCF0AA00CCF0))
m_valid_i_i_4
(.I0(mi_rvalid),
.I1(m_axi_rvalid[1]),
.I2(m_axi_rvalid[0]),
.I3(Q[0]),
.I4(Q[1]),
.I5(m_axi_rvalid[2]),
.O(m_valid_i_reg));
LUT6 #(
.INIT(64'h55000F3355FF0F33))
\s_axi_bvalid[0]_INST_0_i_1
(.I0(mi_bvalid),
.I1(m_axi_bvalid[0]),
.I2(m_axi_bvalid[2]),
.I3(Q[1]),
.I4(Q[0]),
.I5(m_axi_bvalid[1]),
.O(\m_ready_d_reg[2] ));
LUT6 #(
.INIT(64'h33000F5533FF0F55))
\s_axi_wready[0]_INST_0_i_1
(.I0(m_axi_wready[0]),
.I1(mi_wready),
.I2(m_axi_wready[2]),
.I3(Q[1]),
.I4(Q[0]),
.I5(m_axi_wready[1]),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0]_1 ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter
(\gen_axilite.s_axi_bvalid_i_reg ,
m_ready_d,
s_axi_wvalid,
Q,
m_valid_i,
aa_grant_rnw,
aresetn_d,
m_ready_d0,
\gen_axilite.s_axi_bvalid_i_reg_0 ,
\gen_no_arbiter.grant_rnw_reg ,
\m_ready_d_reg[2]_0 ,
aclk);
output \gen_axilite.s_axi_bvalid_i_reg ;
output [2:0]m_ready_d;
input [0:0]s_axi_wvalid;
input [0:0]Q;
input m_valid_i;
input aa_grant_rnw;
input aresetn_d;
input [0:0]m_ready_d0;
input \gen_axilite.s_axi_bvalid_i_reg_0 ;
input \gen_no_arbiter.grant_rnw_reg ;
input \m_ready_d_reg[2]_0 ;
input aclk;
wire [0:0]Q;
wire aa_grant_rnw;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_bvalid_i_reg ;
wire \gen_axilite.s_axi_bvalid_i_reg_0 ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire [2:0]m_ready_d;
wire [0:0]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d[2]_i_1_n_0 ;
wire \m_ready_d_reg[2]_0 ;
wire m_valid_i;
wire [0:0]s_axi_wvalid;
LUT6 #(
.INIT(64'hFFFFFFFFFFDFFFFF))
\gen_axilite.s_axi_bvalid_i_i_2
(.I0(s_axi_wvalid),
.I1(m_ready_d[1]),
.I2(Q),
.I3(m_ready_d[2]),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(\gen_axilite.s_axi_bvalid_i_reg ));
LUT6 #(
.INIT(64'hA0AAA0A020222020))
\m_ready_d[0]_i_1
(.I0(aresetn_d),
.I1(m_ready_d0),
.I2(m_ready_d[0]),
.I3(\gen_axilite.s_axi_bvalid_i_reg_0 ),
.I4(\gen_no_arbiter.grant_rnw_reg ),
.I5(\m_ready_d_reg[2]_0 ),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8888888808000808))
\m_ready_d[1]_i_1
(.I0(aresetn_d),
.I1(m_ready_d0),
.I2(m_ready_d[0]),
.I3(\gen_axilite.s_axi_bvalid_i_reg_0 ),
.I4(\gen_no_arbiter.grant_rnw_reg ),
.I5(\m_ready_d_reg[2]_0 ),
.O(\m_ready_d[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000002A222A2A))
\m_ready_d[2]_i_1
(.I0(aresetn_d),
.I1(m_ready_d0),
.I2(m_ready_d[0]),
.I3(\gen_axilite.s_axi_bvalid_i_reg_0 ),
.I4(\gen_no_arbiter.grant_rnw_reg ),
.I5(\m_ready_d_reg[2]_0 ),
.O(\m_ready_d[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[2]_i_1_n_0 ),
.Q(m_ready_d[2]),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0
(m_ready_d,
aresetn_d,
aa_grant_rnw,
m_valid_i,
\gen_axilite.s_axi_arready_i_reg ,
m_valid_i_reg,
aclk);
output [1:0]m_ready_d;
input aresetn_d;
input aa_grant_rnw;
input m_valid_i;
input \gen_axilite.s_axi_arready_i_reg ;
input m_valid_i_reg;
input aclk;
wire aa_grant_rnw;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_arready_i_reg ;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire m_valid_i;
wire m_valid_i_reg;
LUT6 #(
.INIT(64'h0000000000AA002A))
\m_ready_d[0]_i_1
(.I0(aresetn_d),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[1]),
.I4(\gen_axilite.s_axi_arready_i_reg ),
.I5(m_valid_i_reg),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAA00AA8000000000))
\m_ready_d[1]_i_1
(.I0(aresetn_d),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[1]),
.I4(\gen_axilite.s_axi_arready_i_reg ),
.I5(m_valid_i_reg),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
(sr_rvalid,
aa_rready,
\m_ready_d_reg[1] ,
m_axi_rready,
m_valid_i_reg_0,
\s_axi_rdata[31] ,
\aresetn_d_reg[1]_0 ,
aclk,
\aresetn_d_reg[0]_0 ,
s_axi_rready,
aa_grant_rnw,
m_valid_i,
m_ready_d,
m_axi_rresp,
Q,
m_axi_rdata,
\m_atarget_hot_reg[2] ,
SR,
E);
output sr_rvalid;
output aa_rready;
output \m_ready_d_reg[1] ;
output [2:0]m_axi_rready;
output [1:0]m_valid_i_reg_0;
output [33:0]\s_axi_rdata[31] ;
input \aresetn_d_reg[1]_0 ;
input aclk;
input \aresetn_d_reg[0]_0 ;
input [0:0]s_axi_rready;
input aa_grant_rnw;
input m_valid_i;
input [0:0]m_ready_d;
input [5:0]m_axi_rresp;
input [1:0]Q;
input [95:0]m_axi_rdata;
input [2:0]\m_atarget_hot_reg[2] ;
input [0:0]SR;
input [0:0]E;
wire [0:0]E;
wire [1:0]Q;
wire [0:0]SR;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire \aresetn_d_reg[0]_0 ;
wire \aresetn_d_reg[1]_0 ;
wire [2:0]\m_atarget_hot_reg[2] ;
wire [95:0]m_axi_rdata;
wire [2:0]m_axi_rready;
wire [5:0]m_axi_rresp;
wire \m_payload_i[1]_i_2_n_0 ;
wire \m_payload_i[2]_i_2_n_0 ;
wire \m_payload_i_reg_n_0_[0] ;
wire [0:0]m_ready_d;
wire \m_ready_d_reg[1] ;
wire m_valid_i;
wire [1:0]m_valid_i_reg_0;
wire [33:0]\s_axi_rdata[31] ;
wire [0:0]s_axi_rready;
wire [34:0]skid_buffer;
wire \skid_buffer[10]_i_1_n_0 ;
wire \skid_buffer[11]_i_1_n_0 ;
wire \skid_buffer[12]_i_1_n_0 ;
wire \skid_buffer[13]_i_1_n_0 ;
wire \skid_buffer[14]_i_1_n_0 ;
wire \skid_buffer[15]_i_1_n_0 ;
wire \skid_buffer[16]_i_1_n_0 ;
wire \skid_buffer[17]_i_1_n_0 ;
wire \skid_buffer[18]_i_1_n_0 ;
wire \skid_buffer[19]_i_1_n_0 ;
wire \skid_buffer[20]_i_1_n_0 ;
wire \skid_buffer[21]_i_1_n_0 ;
wire \skid_buffer[22]_i_1_n_0 ;
wire \skid_buffer[23]_i_1_n_0 ;
wire \skid_buffer[24]_i_1_n_0 ;
wire \skid_buffer[25]_i_1_n_0 ;
wire \skid_buffer[26]_i_1_n_0 ;
wire \skid_buffer[27]_i_1_n_0 ;
wire \skid_buffer[28]_i_1_n_0 ;
wire \skid_buffer[29]_i_1_n_0 ;
wire \skid_buffer[30]_i_1_n_0 ;
wire \skid_buffer[31]_i_1_n_0 ;
wire \skid_buffer[32]_i_1_n_0 ;
wire \skid_buffer[33]_i_1_n_0 ;
wire \skid_buffer[34]_i_1_n_0 ;
wire \skid_buffer[3]_i_1_n_0 ;
wire \skid_buffer[4]_i_1_n_0 ;
wire \skid_buffer[5]_i_1_n_0 ;
wire \skid_buffer[6]_i_1_n_0 ;
wire \skid_buffer[7]_i_1_n_0 ;
wire \skid_buffer[8]_i_1_n_0 ;
wire \skid_buffer[9]_i_1_n_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire sr_rvalid;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(1'b1),
.Q(m_valid_i_reg_0[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_reg_0[0]),
.Q(m_valid_i_reg_0[1]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[0]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[2] [0]),
.O(m_axi_rready[0]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[1]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[2] [1]),
.O(m_axi_rready[1]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[2]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[2] [2]),
.O(m_axi_rready[2]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(\skid_buffer[10]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(\skid_buffer[11]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(\skid_buffer[12]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1
(.I0(\skid_buffer[13]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(\skid_buffer[14]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(\skid_buffer[15]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(\skid_buffer[16]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(\skid_buffer[17]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(\skid_buffer[18]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(\skid_buffer[19]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h0E))
\m_payload_i[1]_i_1
(.I0(\skid_buffer_reg_n_0_[1] ),
.I1(aa_rready),
.I2(\m_payload_i[1]_i_2_n_0 ),
.O(skid_buffer[1]));
LUT6 #(
.INIT(64'h00550F3300000000))
\m_payload_i[1]_i_2
(.I0(m_axi_rresp[4]),
.I1(m_axi_rresp[0]),
.I2(m_axi_rresp[2]),
.I3(Q[0]),
.I4(Q[1]),
.I5(aa_rready),
.O(\m_payload_i[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(\skid_buffer[20]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(\skid_buffer[21]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(\skid_buffer[22]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(\skid_buffer[23]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(\skid_buffer[24]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(\skid_buffer[25]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(\skid_buffer[26]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(\skid_buffer[27]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(\skid_buffer[28]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(\skid_buffer[29]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h0E))
\m_payload_i[2]_i_1
(.I0(\skid_buffer_reg_n_0_[2] ),
.I1(aa_rready),
.I2(\m_payload_i[2]_i_2_n_0 ),
.O(skid_buffer[2]));
LUT6 #(
.INIT(64'h00220A0000220AAA))
\m_payload_i[2]_i_2
(.I0(aa_rready),
.I1(m_axi_rresp[5]),
.I2(m_axi_rresp[3]),
.I3(Q[0]),
.I4(Q[1]),
.I5(m_axi_rresp[1]),
.O(\m_payload_i[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(\skid_buffer[30]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1
(.I0(\skid_buffer[31]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(\skid_buffer[32]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(\skid_buffer[33]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_2
(.I0(\skid_buffer[34]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(\skid_buffer[3]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(\skid_buffer[4]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(\skid_buffer[5]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(\skid_buffer[6]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(\skid_buffer[7]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(\skid_buffer[8]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(\skid_buffer[9]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(\m_payload_i_reg_n_0_[0] ),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(\s_axi_rdata[31] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(\s_axi_rdata[31] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(\s_axi_rdata[31] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(\s_axi_rdata[31] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(\s_axi_rdata[31] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(\s_axi_rdata[31] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(\s_axi_rdata[31] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(\s_axi_rdata[31] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(\s_axi_rdata[31] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(\s_axi_rdata[31] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(\s_axi_rdata[31] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(\s_axi_rdata[31] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(\s_axi_rdata[31] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(\s_axi_rdata[31] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(\s_axi_rdata[31] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(\s_axi_rdata[31] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(\s_axi_rdata[31] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(\s_axi_rdata[31] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(\s_axi_rdata[31] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(\s_axi_rdata[31] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(\s_axi_rdata[31] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(\s_axi_rdata[31] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(\s_axi_rdata[31] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(\s_axi_rdata[31] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(\s_axi_rdata[31] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(\s_axi_rdata[31] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\s_axi_rdata[31] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(\s_axi_rdata[31] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(\s_axi_rdata[31] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(\s_axi_rdata[31] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(\s_axi_rdata[31] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(\s_axi_rdata[31] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(\s_axi_rdata[31] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(\s_axi_rdata[31] [8]),
.R(1'b0));
LUT6 #(
.INIT(64'h000000007FFFFFFF))
\m_ready_d[1]_i_3
(.I0(sr_rvalid),
.I1(\m_payload_i_reg_n_0_[0] ),
.I2(s_axi_rready),
.I3(aa_grant_rnw),
.I4(m_valid_i),
.I5(m_ready_d),
.O(\m_ready_d_reg[1] ));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[1]_0 ),
.Q(sr_rvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(aa_rready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'hE))
\skid_buffer[0]_i_1
(.I0(aa_rready),
.I1(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[10]_i_1
(.I0(m_axi_rdata[7]),
.I1(m_axi_rdata[39]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[71]),
.O(\skid_buffer[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[11]_i_1
(.I0(m_axi_rdata[8]),
.I1(m_axi_rdata[40]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[72]),
.O(\skid_buffer[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[12]_i_1
(.I0(m_axi_rdata[9]),
.I1(m_axi_rdata[41]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[73]),
.O(\skid_buffer[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[13]_i_1
(.I0(m_axi_rdata[10]),
.I1(m_axi_rdata[42]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[74]),
.O(\skid_buffer[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[14]_i_1
(.I0(m_axi_rdata[11]),
.I1(m_axi_rdata[43]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[75]),
.O(\skid_buffer[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[15]_i_1
(.I0(m_axi_rdata[12]),
.I1(m_axi_rdata[44]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[76]),
.O(\skid_buffer[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0ACF0AC0))
\skid_buffer[16]_i_1
(.I0(m_axi_rdata[45]),
.I1(m_axi_rdata[77]),
.I2(Q[1]),
.I3(Q[0]),
.I4(m_axi_rdata[13]),
.O(\skid_buffer[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[17]_i_1
(.I0(m_axi_rdata[14]),
.I1(m_axi_rdata[46]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[78]),
.O(\skid_buffer[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[18]_i_1
(.I0(m_axi_rdata[15]),
.I1(m_axi_rdata[47]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[79]),
.O(\skid_buffer[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[19]_i_1
(.I0(m_axi_rdata[16]),
.I1(m_axi_rdata[48]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[80]),
.O(\skid_buffer[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[20]_i_1
(.I0(m_axi_rdata[17]),
.I1(m_axi_rdata[49]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[81]),
.O(\skid_buffer[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[21]_i_1
(.I0(m_axi_rdata[18]),
.I1(m_axi_rdata[50]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[82]),
.O(\skid_buffer[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[22]_i_1
(.I0(m_axi_rdata[19]),
.I1(m_axi_rdata[51]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[83]),
.O(\skid_buffer[22]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[23]_i_1
(.I0(m_axi_rdata[20]),
.I1(m_axi_rdata[52]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[84]),
.O(\skid_buffer[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[24]_i_1
(.I0(m_axi_rdata[21]),
.I1(m_axi_rdata[53]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[85]),
.O(\skid_buffer[24]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[25]_i_1
(.I0(m_axi_rdata[22]),
.I1(m_axi_rdata[54]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[86]),
.O(\skid_buffer[25]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[26]_i_1
(.I0(m_axi_rdata[23]),
.I1(m_axi_rdata[55]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[87]),
.O(\skid_buffer[26]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0CAF0CA0))
\skid_buffer[27]_i_1
(.I0(m_axi_rdata[88]),
.I1(m_axi_rdata[56]),
.I2(Q[1]),
.I3(Q[0]),
.I4(m_axi_rdata[24]),
.O(\skid_buffer[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[28]_i_1
(.I0(m_axi_rdata[25]),
.I1(m_axi_rdata[57]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[89]),
.O(\skid_buffer[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[29]_i_1
(.I0(m_axi_rdata[26]),
.I1(m_axi_rdata[58]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[90]),
.O(\skid_buffer[29]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[30]_i_1
(.I0(m_axi_rdata[27]),
.I1(m_axi_rdata[59]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[91]),
.O(\skid_buffer[30]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[31]_i_1
(.I0(m_axi_rdata[28]),
.I1(m_axi_rdata[60]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[92]),
.O(\skid_buffer[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[32]_i_1
(.I0(m_axi_rdata[29]),
.I1(m_axi_rdata[61]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[93]),
.O(\skid_buffer[32]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[33]_i_1
(.I0(m_axi_rdata[30]),
.I1(m_axi_rdata[62]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[94]),
.O(\skid_buffer[33]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[34]_i_1
(.I0(m_axi_rdata[31]),
.I1(m_axi_rdata[63]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[95]),
.O(\skid_buffer[34]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[3]_i_1
(.I0(m_axi_rdata[0]),
.I1(m_axi_rdata[32]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[64]),
.O(\skid_buffer[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[4]_i_1
(.I0(m_axi_rdata[1]),
.I1(m_axi_rdata[33]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[65]),
.O(\skid_buffer[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[5]_i_1
(.I0(m_axi_rdata[2]),
.I1(m_axi_rdata[66]),
.I2(Q[1]),
.I3(Q[0]),
.I4(m_axi_rdata[34]),
.O(\skid_buffer[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[6]_i_1
(.I0(m_axi_rdata[3]),
.I1(m_axi_rdata[35]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[67]),
.O(\skid_buffer[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[7]_i_1
(.I0(m_axi_rdata[4]),
.I1(m_axi_rdata[36]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[68]),
.O(\skid_buffer[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[8]_i_1
(.I0(m_axi_rdata[5]),
.I1(m_axi_rdata[37]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[69]),
.O(\skid_buffer[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0FCA00CA))
\skid_buffer[9]_i_1
(.I0(m_axi_rdata[6]),
.I1(m_axi_rdata[38]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_rdata[70]),
.O(\skid_buffer[9]_i_1_n_0 ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[10]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[11]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[12]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[13]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[14]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[15]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[16]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[17]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[18]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[19]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[20]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[21]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[22]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[23]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[24]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[25]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[26]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[27]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[28]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[29]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[30]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[31]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[32]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[33]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[34]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[3]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[4]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[5]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[6]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[7]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[8]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[9]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *) output [95:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *) output [8:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *) output [2:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *) input [2:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *) output [95:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *) output [11:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *) output [2:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *) input [2:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *) input [5:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *) input [2:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *) output [2:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *) output [95:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *) output [8:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *) output [2:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *) input [2:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *) input [95:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *) input [5:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *) input [2:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *) output [2:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [95:0]m_axi_araddr;
wire [8:0]m_axi_arprot;
wire [2:0]m_axi_arready;
wire [2:0]m_axi_arvalid;
wire [95:0]m_axi_awaddr;
wire [8:0]m_axi_awprot;
wire [2:0]m_axi_awready;
wire [2:0]m_axi_awvalid;
wire [2:0]m_axi_bready;
wire [5:0]m_axi_bresp;
wire [2:0]m_axi_bvalid;
wire [95:0]m_axi_rdata;
wire [2:0]m_axi_rready;
wire [5:0]m_axi_rresp;
wire [2:0]m_axi_rvalid;
wire [95:0]m_axi_wdata;
wire [2:0]m_axi_wready;
wire [11:0]m_axi_wstrb;
wire [2:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "0" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *)
(* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "192'b000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "3" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *)
(* C_S_AXI_THREAD_ID_WIDTH = "0" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "3'b111" *)
(* P_M_AXI_SUPPORTS_WRITE = "3'b111" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0}),
.m_axi_rlast({1'b1,1'b1,1'b1}),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s_axi_arready),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b1),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hs__o21ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__o21ai_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule |
module sky130_fd_sc_hd__lpflow_inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module data_cache
(
input clk,
input boot_done,
// Interface for using the cache
input wr_en,
input [`ADDR_BITS-1:0] wr_addr,
input [`WORD_BITS-1:0] wr_data,
output wr_done,
input rd_en,
input [`ADDR_BITS-1:0] rd_addr,
output reg [`WORD_BITS-1:0] rd_data,
output rd_done,
// Signals for communicating with main memory
output reg mem_cmd_en,
output reg [2:0] mem_cmd_instr,
output reg [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output reg mem_wr_en,
output reg [3:0] mem_wr_mask,
output reg [31:0] mem_wr_data,
input mem_wr_full,
input mem_wr_empty,
input [6:0] mem_wr_count,
input mem_wr_underrun,
input mem_wr_error,
output reg mem_rd_en,
input [31:0] mem_rd_data,
input mem_rd_full,
input mem_rd_empty,
input [6:0] mem_rd_count,
input mem_rd_overflow,
input mem_rd_error
);
initial begin
rd_data = 0;
mem_cmd_en = 0;
mem_wr_en = 0;
mem_rd_en = 0;
end
// State machine for accessing the RAM
localparam [2:0] STATE_PRE_BOOT = 0;
localparam [2:0] STATE_IDLE = 1;
localparam [2:0] STATE_WR_CMD = 2;
localparam [2:0] STATE_WR_WAIT = 3;
localparam [2:0] STATE_RD_WAIT = 4;
localparam [2:0] STATE_RD_EN = 5;
reg [2:0] state = 0;
wire mostly_done =
(STATE_IDLE == state) && !wr_en && !rd_en && !mem_cmd_full;
assign wr_done = mostly_done && !mem_wr_full;
assign rd_done = mostly_done && !mem_rd_full;
always @ (posedge clk) begin
mem_cmd_en <= 0;
mem_wr_en <= 0;
mem_rd_en <= 0;
case (state)
STATE_PRE_BOOT: begin
if (boot_done) begin
state <= STATE_IDLE;
end
end
STATE_IDLE: begin
if (wr_en) begin
// Set up command signals and write the data to the write FIFO
mem_cmd_instr <= 3'b000;
mem_cmd_bl <= 6'b000000;
mem_cmd_byte_addr <= { `MAIN_MEM_PREFIX, wr_addr };
mem_wr_en <= 1;
// We write only the upper or lower 16 bits
mem_wr_mask <= wr_addr[1] ? 4'b1100 : 4'b0011;
mem_wr_data <= {2{wr_data}};
state <= STATE_WR_CMD;
end else if (rd_en) begin
// Send the read command
mem_cmd_en <= 1;
mem_cmd_instr <= 3'b001;
mem_cmd_bl <= 6'b000000;
mem_cmd_byte_addr <= { `MAIN_MEM_PREFIX, rd_addr };
state <= STATE_RD_WAIT;
end
end
STATE_WR_CMD: begin
mem_cmd_en <= 1;
state <= STATE_IDLE;
end
STATE_RD_WAIT: begin
if (!mem_rd_empty) begin
mem_rd_en <= 1;
state <= STATE_RD_EN;
end
end
STATE_RD_EN: begin
// Only grab the upper or lower half, depending on the second
// to last address bit
rd_data <= mem_cmd_byte_addr[1] ?
mem_rd_data[15:0] :
mem_rd_data[31:16];
state <= STATE_IDLE;
end
endcase
end
endmodule |
module sky130_fd_sc_ls__buf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hd__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module roi(input clk,
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
parameter DIN_N = `DIN_N;
parameter DOUT_N = `DOUT_N;
wire [DIN_N-1:0] internal;
genvar i;
generate
//CLK
(* KEEP, DONT_TOUCH *)
reg clk_reg;
always @(posedge clk) begin
clk_reg <= clk_reg;
end
//DIN
for (i = 0; i < DIN_N; i = i+1) begin:ins
//Very expensive inverter
(* KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'b10)
) lut (
.I0(din[i]),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0),
.I5(1'b0),
.O(internal[i]));
end
//DOUT
for (i = 0; i < DOUT_N; i = i+1) begin:outs
//Very expensive buffer
(* KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'b010)
) lut (
.I0(internal[i]),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0),
.I5(1'b0),
.O(dout[i]));
end
endgenerate
endmodule |
module ANN_dexp_64ns_64ns_64_18_full_dsp
#(parameter
ID = 8,
NUM_STAGE = 18,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_dexp_16_full_dsp_64 ANN_ap_dexp_16_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din1_buf1 <= din1;
end
end
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset), // resetrequest.reset
.source_ready (1'b1), // (terminated)
.mgmt_valid (), // (terminated)
.mgmt_channel (), // (terminated)
.mgmt_data (), // (terminated)
.jtag_tck (1'b0), // (terminated)
.jtag_tms (1'b0), // (terminated)
.jtag_tdi (1'b0), // (terminated)
.jtag_tdo (), // (terminated)
.jtag_ena (1'b0), // (terminated)
.jtag_usr1 (1'b0), // (terminated)
.jtag_clr (1'b0), // (terminated)
.jtag_clrn (1'b0), // (terminated)
.jtag_state_tlr (1'b0), // (terminated)
.jtag_state_rti (1'b0), // (terminated)
.jtag_state_sdrs (1'b0), // (terminated)
.jtag_state_cdr (1'b0), // (terminated)
.jtag_state_sdr (1'b0), // (terminated)
.jtag_state_e1dr (1'b0), // (terminated)
.jtag_state_pdr (1'b0), // (terminated)
.jtag_state_e2dr (1'b0), // (terminated)
.jtag_state_udr (1'b0), // (terminated)
.jtag_state_sirs (1'b0), // (terminated)
.jtag_state_cir (1'b0), // (terminated)
.jtag_state_sir (1'b0), // (terminated)
.jtag_state_e1ir (1'b0), // (terminated)
.jtag_state_pir (1'b0), // (terminated)
.jtag_state_e2ir (1'b0), // (terminated)
.jtag_state_uir (1'b0), // (terminated)
.jtag_ir_in (3'b000), // (terminated)
.jtag_irq (), // (terminated)
.jtag_ir_out () // (terminated)
);
soc_system_fpga_only_master_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.out_data (timing_adt_out_data), // out.data
.out_valid (timing_adt_out_valid), // .valid
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
soc_system_fpga_only_master_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (b2p_out_packets_stream_data), // in.data
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_ready (b2p_out_packets_stream_ready), // .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_channel (b2p_out_packets_stream_channel), // .channel
.out_data (b2p_adapter_out_data), // out.data
.out_valid (b2p_adapter_out_valid), // .valid
.out_ready (b2p_adapter_out_ready), // .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
soc_system_fpga_only_master_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (transacto_out_stream_data), // in.data
.in_valid (transacto_out_stream_valid), // .valid
.in_ready (transacto_out_stream_ready), // .ready
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_data (p2b_adapter_out_data), // out.data
.out_valid (p2b_adapter_out_valid), // .valid
.out_ready (p2b_adapter_out_ready), // .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module car_detector(
input wire clk, res,
input wire sensorA,
input wire sensorB,
output wire [3:0] car_count
);
localparam abUnblocked=2'b00, aBlocked=2'b01, abBlocked=2'b10, bBlocked=2'b11;
reg [1:0] current_state;
reg increase, decrease;
reg [3:0] count = 0;
//initialize all necessary values
initial begin
increase = 0;
decrease = 0;
current_state = 0;
end
// State register logic
always@(posedge clk, posedge res) begin
if (res)
current_state <= abUnblocked;
else
begin
increase <= 0;
decrease <= 0;
case(current_state)
abUnblocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
else if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked; //stay
end
aBlocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked; //stay
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
decrease <= 1; //finished exiting
end
abBlocked: if ({sensorA,sensorB} == 2'b10) begin
current_state <= aBlocked;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked; //stay
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked;
end
bBlocked: if ({sensorA,sensorB} == 2'b00) begin
current_state <= abUnblocked;
increase <= 1;
end
else if ({sensorA,sensorB} == 2'b11) begin
current_state <= abBlocked;
end
else if ({sensorA,sensorB} == 2'b01) begin
current_state <= bBlocked; //stay
end
default: current_state <= abUnblocked;
endcase
if(increase)
count <= count + 1'b1; //increment the total counter
else if(decrease)
count <= count - 1'b1; //decrement the total counter
end //end else
end //end always
assign car_count = count;
endmodule |
module ded_funshf
#(parameter BYTES = 4)
(
input mclock,
`ifdef BYTE16 input [6:0] rad, // fifo read address.
`elsif BYTE8 input [5:0] rad, // fifo read address.
`else input [4:0] rad, `endif // fifo read address.
input [(BYTES<<3)-1:0] bsd0, // data in from fifo_0
input [(BYTES<<3)-1:0] bsd1, // data in from fifo_1
input apat8_4, // Area 8x8 mode.
input apat32_4, // Area 32x32 mode.
output reg [(BYTES<<3)-1:0] bsout, // funnel shifter output.
output [BYTES-1:0] cx_sel // color expand data
);
`ifdef BYTE16 reg [6:0] rad_1, rad_d; // fifo read address.
`elsif BYTE8 reg [5:0] rad_1, rad_d; // fifo read address.
`else reg [4:0] rad_1, rad_d; `endif// fifo read address.
reg [(BYTES<<4)-1:0] bsin; // data in from fifo.
reg [31:0] bpck_dat;
reg [4:0] cx_rad;
wire [1:0] n_a32_rad;
wire [1:0] a32_rad;
wire [3:0] bso_sel;
wire [127:0] bs1;
wire [135:0] bs2;
wire [151:0] bs4;
wire [183:0] bs8;
wire [BYTES-1:0] cx1;
wire [BYTES:0] cx2;
wire [BYTES+2:0] cx4;
wire [BYTES+6:0] cx8;
wire [BYTES+14:0] cx16;
/************************************************************************/
// The RAD value needs to be delayed one clock. This is due to the new Rams
// which has everything delayed one cycle
always @(posedge mclock) begin
rad_1 <= rad;
rad_d <= rad_1;
bsin <= {bsd1,bsd0};
end
/************************************************************************/
/* BYTE ADDRESSING */
/************************************************************************/
assign n_a32_rad = {2{~apat32_4}} & rad_d[4:3];
`ifdef BYTE16
assign bso_sel = {rad_d[6:5],n_a32_rad};
always @*
bsout = bs1;
assign bs1 = bso_sel[0] ? bs2[135:8] : bs2[127:0];
assign bs2 = bso_sel[1] ? bs4[151:16] : bs4[135:0];
assign bs4 = bso_sel[2] ? bs8[183:32] : bs8[151:0];
assign bs8 = bso_sel[3] ? bsin[247:64] : bsin[183:0];
`endif
`ifdef BYTE8
always @*
case ({rad_d[5],n_a32_rad})
3'h0: bsout = bsin[63:0];
3'h1: bsout = bsin[71:8];
3'h2: bsout = bsin[79:16];
3'h3: bsout = bsin[87:24];
3'h4: bsout = bsin[95:32];
3'h5: bsout = bsin[103:40];
3'h6: bsout = bsin[111:48];
3'h7: bsout = bsin[119:56];
endcase
`endif
`ifdef BYTE4
always @*
case (n_a32_rad)
2'h0: bsout = bsin[31:0];
2'h1: bsout = bsin[39:8];
2'h2: bsout = bsin[47:16];
2'h3: bsout = bsin[55:24];
endcase
`endif
/************************************************************************/
/* Packed one bit per pixel mux */
/************************************************************************/
assign a32_rad = {2{apat32_4}} & rad_d[4:3];
// FB: added to increase MC clock speed
always @(posedge mclock) begin
bpck_dat <= (apat8_4) ? {4{bsout[7:0]}} : bsout[31:0];
cx_rad <= {a32_rad, rad_d[2:0]};
end
`ifdef BYTE16
assign cx_sel = cx1;
assign cx1 = cx_rad[0] ? cx2[16:1] : cx2[15:0];
assign cx2 = cx_rad[1] ? cx4[18:2] : cx4[16:0];
assign cx4 = cx_rad[2] ? cx8[22:4] : cx8[18:0];
assign cx8 = cx_rad[3] ? cx16[30:8] : cx16[22:0];
assign cx16 = cx_rad[4] ? {bpck_dat[14:0],bpck_dat[31:16]} : bpck_dat[30:0];
`endif
`ifdef BYTE8
assign cx_sel = cx1;
assign cx1 = cx_rad[0] ? cx2[8:1] : cx2[7:0];
assign cx2 = cx_rad[1] ? cx4[10:2] : cx4[8:0];
assign cx4 = cx_rad[2] ? cx8[14:4] : cx8[10:0];
assign cx8 = cx_rad[3] ? cx16[22:8] : cx16[14:0];
assign cx16 = cx_rad[4] ? {bpck_dat[6:0],bpck_dat[31:16]} : bpck_dat[22:0];
`endif
`ifdef BYTE4
assign cx_sel = cx1;
assign cx1 = cx_rad[0] ? cx2[4:1] : cx2[3:0];
assign cx2 = cx_rad[1] ? cx4[6:2] : cx4[4:0];
assign cx4 = cx_rad[2] ? cx8[10:4] : cx8[6:0];
assign cx8 = cx_rad[3] ? cx16[18:8] : cx16[10:0];
assign cx16 = cx_rad[4] ? {bpck_dat[3:0],bpck_dat[31:16]} : bpck_dat[18:0];
`endif
endmodule |
module sky130_fd_sc_ls__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module clock_divider(
input wire clk,
input wire reset,
input wire enabled,
output reg refresh_clk,
output reg sys_clk
);
reg [8:0] counter1;
reg [8:0] counter2;
reg [8:0] clk_divid;
always@(posedge clk or negedge reset)
begin
if( ~reset )
begin
refresh_clk <= 1;
sys_clk <= 0;
counter1 <= 0;
counter2 <= 63;
clk_divid <= 100;
end
else if( enabled )
begin
clk_divid <= clk_divid;
if( counter1 < clk_divid )
begin
counter1 <= counter1 + 1;
refresh_clk <= refresh_clk;
end
else
begin
refresh_clk <= !refresh_clk;
counter1 <= 0;
end
if( counter2 < clk_divid )
begin
counter2 <= counter2 + 1;
sys_clk <= sys_clk;
end
else
begin
sys_clk <= !sys_clk;
counter2 <= 0;
end
end
end
endmodule |
module nios_dut_pio_0 (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire data_in;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(data_in & irq_mask);
endmodule |
module mge6m
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [24:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [24:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [24:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 25,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule |
module Debounce_B
(
CLK_IN,
reset,
enb,
In,
Out
);
input CLK_IN;
input reset;
input enb;
input In;
output Out;
wire [7:0] Debouce_Count_out1; // uint8
wire Count_Up_Down_out1;
// <S4>/Debouce_Count
assign Debouce_Count_out1 = 8'd25;
// <S4>/Count_Up_Down
Count_Up_Down u_Count_Up_Down (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.u(In),
.count_debounce(Debouce_Count_out1), // uint8
.y(Count_Up_Down_out1)
);
assign Out = Count_Up_Down_out1;
endmodule |
module rcpu ( // RCPU
input wire rst, // Reset
input wire clk, // Clock
input wire irq, // Interrupt request
output wire turnOffIRQ, // Interrupt acknowledgement signal
input wire memReady, // Is memory ready
input wire[N-1:0] intAddr, // Interrupt address
input wire[M-1:0] intData, // Interrupt data
input wire[M-1:0] page, // High 16 bits for addressed mode
output reg[N-1:0] memAddr, // Memory address
input wire[M-1:0] memReadIn, // Readed from memory
output reg[M-1:0] memWrite, // For writing to memory
output wire memRE, // Enable reading from memory
output wire memWE, // Enable writing to memory
output wire[1:0] inMask,
output wire[1:0] outMask,
// For debugging only
output wire[M-1:0] A,
output wire[M-1:0] B,
output wire[M-1:0] C,
output wire[N-1:0] PC,
output wire[M-1:0] FP,
output wire[M-1:0] SP,
output wire[5:0] state,
output wire[3:0] F
);
`include "constants"
parameter M = 16; // Data bus width
parameter N = 32; // Address bus width
wire[M-1:0] memRead;
wire stall = !memReady && memRE;
// Registers
//wire[M-1:0] A;
//wire[M-1:0] B;
//wire[M-1:0] C;
//wire[N-1:0] PC; // Program counter
//wire[M-1:0] SP; // Stack pointer
//wire[M-1:0] FP; // Frame pointer
// Enable write signals
wire enA;
wire enB;
wire enC;
wire enPC;
wire enSP;
wire enFP;
wire[1:0] sourcePC;
wire sourceFP;
wire[M-1:0] inR = aluY; // Input to ABC registers
reg[N-1:0] inPC; // Input to program counter
always @ ( * ) begin
inPC = {aluYHigh, aluY};
if (sourcePC == 2'b01)
inPC = {PC[31:16], memRead};
else if (sourcePC == 2'b10)
inPC = {memRead, PC[15:0]};
else if (sourcePC == 2'b11)
inPC = {PC[31:17], aluB, 1'b0};
end
wire[M-1:0] opcode; // Instruction register
wire enIR;
wire[M-1:0] value1; // Internal registers
wire enV1;
wire[M-1:0] value2;
wire enV2;
wire[M-1:0] res;
wire enR;
// Flag register
//wire[3:0] F;
wire enF;
wire[3:0] inFFromAlu;
reg[3:0] inF;
// Flags
wire c = F[3]; // Carry
wire n = F[2]; // Negative
wire z = F[1]; // Zero
wire v = F[0]; // Overflow
wire[M-1:0] aluY; // ALU output
wire[M-1:0] aluYHigh; // ALU output high bits
wire[1:0] sourceF;
wire[3:0] altF;
wire isMul;
wire initSPFP;
wire writeToSP = (memAddr == 32'hFFFF100F) && memWE;
wire[M-1:0] inSP = initSPFP? 16'hFFFE:
writeToSP? memWrite:
aluY;
// Registers logic
register #(M) rIR (clk, memRead, opcode, enIR && !stall, rst, 2'b11, 2'b11);
register #(M) rV1 (clk, memRead, value1, enV1 && !stall, rst, 2'b11, 2'b11);
register #(M) rV2 (clk, memRead, value2, enV2 && !stall, rst, 2'b11, 2'b11);
register #(M) rR (clk, aluY, res, enR && !stall, rst, 2'b11, 2'b11);
register #(M) rA (clk, isMul? yhigh : inR, A, enA && !stall, rst, inMask, outMask);
register #(M) rB (clk, inR, B, enB && !stall, rst, inMask, outMask);
register #(M) rC (clk, inR, C, enC && !stall, rst, inMask, outMask);
register #(N) rPC (clk, inPC, PC, enPC && !stall, rst, 2'b11, 2'b11);
register #(M) rSP (clk, inSP, SP, (enSP || writeToSP) && !stall, rst, 2'b11, 2'b11);
register #(M) rFP (clk, initSPFP? 16'hFFFE: sourceFP? memRead: aluY, FP, enFP && !stall, rst, 2'b11, 2'b11);
register #(4) rF (clk, inF, F, enF && !stall, rst, 2'b11, 2'b11);
assign memRead = memAddr == 32'hFFFF100F ? SP : memReadIn;
// ALU inputs
reg[M-1:0] aluA;
reg[M-1:0] aluAHigh;
reg[M-1:0] aluB;
wire[3:0] aluFunc; // ALU function control bus
wire[M-1:0] aluOutA; // ALU output to A register
wire[3:0] aluASource; // Source of ALU input A
wire[3:0] aluBSource; // Source of ALU input B
reg use32bit; // ALU size control bit
alu alu1 ( // ALU logic
.a (aluA),
.ahigh (aluAHigh),
.b (aluB),
.y (aluY),
.yhigh (aluYHigh),
.func (aluFunc),
.use32bit (use32bit),
.co (inFFromAlu[3]), // Carry flag out
.negative (inFFromAlu[2]),
.zero (inFFromAlu[1]),
.overflow (inFFromAlu[0]),
.ci (c) // Carry flag in
);
wire[2:0] memAddrSource;
wire[3:0] writeDataSource;
wire readStack;
cpuController cpuCTRL ( // CPU control unit (FSM)
// Inputs
.clk (clk),
.stall(stall),
.rst (rst),
.opcode (enIR? memRead : opcode), // Current instruction
.flags (F),
.irq (irq),
// Outputs
.enPC (enPC),
.aluFunc (aluFunc),
.aluA (aluASource),
.aluB (aluBSource),
.enA (enA),
.enB (enB),
.enC (enC),
.saveOpcode (enIR),
.saveMem1 (enV1),
.saveMem2 (enV2),
.memAddr (memAddrSource), // Source of memory read/write address
.we (memWE), // Enable write to memory
.re (memRE), // Enable read from memory
.writeDataSource (writeDataSource), // Source of memory write data
.saveResult (enR), //Enable write to ALU result register
.enF (enF),
.sourceF (sourceF),
.sourceFP (sourceFP),
.enFP (enFP),
.sourcePC (sourcePC),
.inF (altF), // Input to flag register
.enSP (enSP),
.state (state),
.turnOffIRQ (turnOffIRQ),
.readStack (readStack),
.isMul (isMul),
.initSPFP (initSPFP),
.inMask (inMask),
.outMask (outMask)
);
always @ ( * ) begin // ALU input A logic
aluA = 0; // If none, equals 0
use32bit = 0;
aluAHigh = 0;
case (aluASource)
ALU1_FROM_0: aluA = 0;
ALU1_FROM_A: aluA = A;
ALU1_FROM_B: aluA = B;
ALU1_FROM_C: aluA = C;
ALU1_FROM_PC: begin {aluAHigh, aluA} = PC; use32bit = 1; end
ALU1_FROM_MEM: aluA = value1;
ALU1_FROM_HIMEM: begin {aluAHigh, aluA} = {value2, value1};
use32bit = 1;
end
ALU1_FROM_SP: aluA = SP;
ALU1_FROM_XX: aluA = opcode[6:0];
ALU1_FROM_INTADDR: begin {aluAHigh, aluA} = intAddr; use32bit = 1; end
ALU1_FROM_DIRECTREAD: aluA = memRead;
default: aluA = 0;
endcase
end
always @ ( * ) begin // ALU input B logic
aluB = 0; // If none, equals 0
case (aluBSource)
ALU2_FROM_0: aluB = 0;
ALU2_FROM_A: aluB = A;
ALU2_FROM_B: aluB = B;
ALU2_FROM_C: aluB = C;
// From instruction itself
ALU2_FROM_OP: aluB = {{9{opcode[7]}}, opcode[6:0]};
// Adress from J Type instruction
ALU2_FROM_ADDR: aluB = {{3{opcode[12]}}, opcode[11:0], 1'b0}; // From instruction itself
ALU2_FROM_FADDR: aluB = {{8{opcode[7]}}, opcode[6:0], 1'b0};
ALU2_FROM_2: aluB = 2;
ALU2_FROM_FP: aluB = FP;
ALU2_FROM_MEM: aluB = value1;
default: aluB = 0;
endcase
end
always @ ( * ) begin // Flag register logic
case (sourceF)
FLAG_FROM_ALU: inF = inFFromAlu;
FLAG_FROM_ALU_OUT: inF = aluY[3:0];
FLAG_FROM_8BIT: inF = {1'b0, aluY[7], aluY[7:0] == 8'h00, 1'b0};
default: inF = inFFromAlu;
endcase
end
always @ ( * ) begin // Memory address logic
case (memAddrSource)
READ_FROM_PC: memAddr = PC;
READ_FROM_A: memAddr = {page, A};
READ_FROM_ALU: memAddr = readStack? {16'hD000, aluY} : {aluYHigh, aluY};
READ_FROM_SP: memAddr = {16'hD000, SP};
READ_FROM_FASTMEM: memAddr = {25'h1FFFE20, opcode[6:0]};
default: memAddr = PC;
endcase
end
always @ ( * ) begin // Memory write data logic
memWrite = aluY;
case (writeDataSource)
WRITE_FROM_ALU: memWrite = aluY;
WRITE_FROM_RES: memWrite = res;
WRITE_FROM_PC1: memWrite = PC[15:0];
WRITE_FROM_PC2: memWrite = PC[31:16];
WRITE_FROM_FP: memWrite = FP;
WRITE_FROM_A: memWrite = A;
WRITE_FROM_B: memWrite = B;
WRITE_FROM_C: memWrite = C;
WRITE_FROM_INTDATA: memWrite = intData;
WRITE_FROM_F: memWrite = F;
endcase
end
endmodule |
module bigfile(
sysclk,
g_zaq_in,
g_aux,
scanb,
g_wrb,
g_rdb,
g_noop_clr,
swe_ed,
swe_lv,
din,
g_dout_w0x0f,
n9_bit_write,
reset,
alu_u,
debct_ping,
g_sys_in,
g_zaq_in_rst_hold,
g_zaq_hhh_enb,
g_zaq_out,
g_dout,
g_zaq_ctl,
g_zaq_qaz_hb,
g_zaq_qaz_lb,
gwerth,
g_noop,
g_vector,
swe_qaz1
);
// from external pins
input sysclk;
input [31:0] g_zaq_in;
input [31:0] g_aux;
input scanb;
input g_wrb;
input g_rdb;
input [31:0] g_noop_clr;
input swe_ed;
input swe_lv;
input [63:0] din;
input [4:0] g_dout_w0x0f;
input n9_bit_write;
// from reset_gen block
input reset;
input [31:0] alu_u;
input debct_ping;
output [31:0] g_sys_in;
output [31:0] g_zaq_in_rst_hold;
output [31:0] g_zaq_hhh_enb;
output [31:0] g_zaq_out;
output [31:0] g_dout;
output [31:0] g_zaq_ctl;
output [31:0] g_zaq_qaz_hb;
output [31:0] g_zaq_qaz_lb;
output [31:0] gwerth;
output [31:0] g_noop;
output [8 * 32 - 1:0] g_vector;
output [31:0] swe_qaz1;
wire sysclk;
wire [31:0] g_zaq_in;
wire [31:0] g_aux;
wire scanb;
wire g_wrb;
wire g_rdb;
wire [31:0] g_noop_clr;
wire swe_ed;
wire swe_lv;
wire [63:0] din;
wire [4:0] g_dout_w0x0f;
wire n9_bit_write;
wire reset;
wire [31:0] alu_u;
wire debct_ping;
wire [31:0] g_sys_in;
wire [31:0] g_zaq_in_rst_hold;
wire [31:0] g_zaq_hhh_enb;
wire [31:0] g_zaq_out;
wire [31:0] g_dout;
wire [31:0] g_zaq_ctl;
wire [31:0] g_zaq_qaz_hb;
wire [31:0] g_zaq_qaz_lb;
reg [31:0] gwerth;
wire [31:0] g_noop;
reg [8 * 32 - 1:0] g_vector;
reg [31:0] swe_qaz1;
// IMPLEMENTATION
// constants
parameter g_t_klim_w0x0f = 5'b 00000;
parameter g_t_u_w0x0f = 5'b 00001;
parameter g_t_l_w0x0f = 5'b 00010;
parameter g_t_hhh_l_w0x0f = 5'b 00011;
parameter g_t_jkl_sink_l_w0x0f = 5'b 00100;
parameter g_secondary_t_l_w0x0f = 5'b 00101;
parameter g_style_c_l_w0x0f = 5'b 00110;
parameter g_e_z_w0x0f = 5'b 00111;
parameter g_n_both_qbars_l_w0x0f = 5'b 01000;
parameter g_style_vfr_w0x0f = 5'b 01001;
parameter g_style_klim_w0x0f = 5'b 01010;
parameter g_unklimed_style_vfr_w0x0f = 5'b 01011;
parameter g_style_t_y_w0x0f = 5'b 01100;
parameter g_n_l_w0x0f = 5'b 01101;
parameter g_n_vfr_w0x0f = 5'b 01110;
parameter g_e_n_r_w0x0f = 5'b 01111;
parameter g_n_r_bne_w0x0f = 5'b 10000;
parameter g_n_div_rebeq_w0x0f = 5'b 10001;
parameter g_alu_l_w0x0f = 5'b 10010;
parameter g_t_qaz_mult_low_w0x0f = 5'b 10011;
parameter g_t_qaz_mult_high_w0x0f = 5'b 10100;
parameter gwerthernal_style_u_w0x0f = 5'b 10101;
parameter gwerthernal_style_l_w0x0f = 5'b 10110;
parameter g_style_main_reset_hold_w0x0f = 5'b 10111; // comment
reg [31:0] g_t_klim_dout;
reg [31:0] g_t_u_dout;
reg [31:0] g_t_l_dout;
reg [31:0] g_t_hhh_l_dout;
reg [31:0] g_t_jkl_sink_l_dout;
reg [31:0] g_secondary_t_l_dout;
reg [3:0] g_style_c_l_dout; // not used
reg [31:0] g_e_z_dout;
reg [31:0] g_n_both_qbars_l_dout;
wire [31:0] g_style_vfr_dout;
reg [31:0] g_style_klim_dout;
wire [31:0] g_unklimed_style_vfr_dout;
reg [31:0] g_style_t_y_dout;
reg [31:0] g_n_l_dout;
reg [31:0] g_n_vfr_dout;
reg [31:0] g_e_n_r_dout;
reg g_n_r_bne_dout;
reg [31:0] g_n_div_rebeq_dout;
reg [31:0] g_alu_l_dout;
reg [31:0] g_t_qaz_mult_low_dout;
reg [31:0] g_t_qaz_mult_high_dout;
reg [31:0] gwerthernal_style_u_dout;
reg [31:0] gwerthernal_style_l_dout;
reg [31:0] g_style_main_reset_hold_dout; // other
reg [31:0] q_g_zaq_in;
reg [31:0] q2_g_zaq_in;
reg [31:0] q3_g_zaq_in;
reg [3:0] q_g_zaq_in_cd;
reg [31:0] q_g_style_vfr_dout;
reg [3:0] q_g_unzq; // i
wire [31:0] g_n_active; // inter
wire [31:0] g_zaq_in_y;
wire [31:0] g_zaq_in_y_no_dout;
wire [31:0] g_zaq_out_i;
wire [31:0] g_zaq_ctl_i;
wire [31:0] g_sys_in_i;
wire [31:0] g_sys_in_ii;
wire [31:0] g_dout_i;
// qaz out
assign g_zaq_out_i = ((g_secondary_t_l_dout & ((g_aux ^ g_style_t_y_dout)))) | ((g_alu_l_dout & alu_u & ~g_secondary_t_l_dout)) | (( ~g_alu_l_dout & ~g_secondary_t_l_dout & g_t_u_dout));
// Changed
assign g_zaq_out = g_zaq_out_i & ~g_t_jkl_sink_l_dout;
// qaz
// JLB
assign g_zaq_ctl_i = ~((((g_t_l_dout & ~g_t_jkl_sink_l_dout)) | ((g_t_l_dout & g_t_jkl_sink_l_dout & ~g_zaq_out_i))));
// mux
//vnavigatoroff
assign g_zaq_ctl = scanb == 1'b 1 ? g_zaq_ctl_i : 32'b 00000000000000000000000000000000;
//vnavigatoron
assign g_zaq_hhh_enb = ~((g_t_hhh_l_dout));
assign g_zaq_qaz_hb = g_t_qaz_mult_high_dout;
assign g_zaq_qaz_lb = g_t_qaz_mult_low_dout;
// Dout
assign g_dout_i = g_dout_w0x0f == g_t_klim_w0x0f ? g_t_klim_dout & g_style_klim_dout : g_dout_w0x0f == g_t_u_w0x0f ? g_t_u_dout & g_style_klim_dout : g_dout_w0x0f == g_t_l_w0x0f ? g_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_hhh_l_w0x0f ? g_t_hhh_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_jkl_sink_l_w0x0f ? g_t_jkl_sink_l_dout & g_style_klim_dout : g_dout_w0x0f == g_secondary_t_l_w0x0f ? g_secondary_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_style_c_l_w0x0f ? ({28'b 0000000000000000000000000000,g_style_c_l_dout}) & g_style_klim_dout : g_dout_w0x0f == g_e_z_w0x0f ? g_e_z_dout : g_dout_w0x0f == g_n_both_qbars_l_w0x0f ? g_n_both_qbars_l_dout : g_dout_w0x0f == g_style_vfr_w0x0f ? g_style_vfr_dout & g_style_klim_dout : g_dout_w0x0f == g_style_klim_w0x0f ? g_style_klim_dout : g_dout_w0x0f == g_unklimed_style_vfr_w0x0f ? g_unklimed_style_vfr_dout : g_dout_w0x0f == g_style_t_y_w0x0f ? g_style_t_y_dout & g_style_klim_dout : g_dout_w0x0f == g_n_l_w0x0f ? g_n_l_dout : g_dout_w0x0f == g_n_vfr_w0x0f ? g_n_vfr_dout : g_dout_w0x0f == g_e_n_r_w0x0f ? g_e_n_r_dout : g_dout_w0x0f == g_n_r_bne_w0x0f ? {31'b 0000000000000000000000000000000,g_n_r_bne_dout} : g_dout_w0x0f == g_n_div_rebeq_w0x0f ? g_n_div_rebeq_dout : g_dout_w0x0f == g_alu_l_w0x0f ? g_alu_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_low_w0x0f ? g_t_qaz_mult_low_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_high_w0x0f ? g_t_qaz_mult_high_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_u_w0x0f ? gwerthernal_style_u_dout & g_style_klim_dout : g_dout_w0x0f == g_style_main_reset_hold_w0x0f ? g_style_main_reset_hold_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_l_w0x0f ? gwerthernal_style_l_dout & g_style_klim_dout : 32'b 00000000000000000000000000000000;
assign g_dout = g_rdb == 1'b 0 ? g_dout_i : {32{1'b1}};
// this can be used to use zzz1
always @(posedge sysclk) begin
if((scanb == 1'b 1)) begin
if((reset == 1'b 1)) begin
g_style_main_reset_hold_dout <= g_zaq_in;
end
//vnavigatoroff
end
else begin
g_style_main_reset_hold_dout <= q2_g_zaq_in;
end
//vnavigatoron
end
// qaz
assign g_zaq_in_rst_hold = g_style_main_reset_hold_dout;
// Din
always @(posedge reset or posedge sysclk) begin : P2
reg [4:0] g_dout_w0x0f_v;
if((reset != 1'b 0)) begin
g_t_klim_dout <= {32{1'b0}};
g_t_u_dout <= {32{1'b0}};
g_t_l_dout <= {32{1'b0}};
g_t_hhh_l_dout <= {32{1'b0}};
g_t_jkl_sink_l_dout <= {32{1'b0}};
g_secondary_t_l_dout <= {32{1'b0}};
g_style_c_l_dout <= {4{1'b0}};
g_e_z_dout <= {32{1'b0}};
g_n_both_qbars_l_dout <= {32{1'b0}};
g_style_klim_dout <= {32{1'b0}};
g_style_t_y_dout <= {32{1'b0}};
g_n_l_dout <= {32{1'b0}};
g_e_n_r_dout <= {32{1'b0}};
g_n_r_bne_dout <= 1'b 0;
g_n_div_rebeq_dout <= {32{1'b1}};
g_alu_l_dout <= {32{1'b0}};
g_t_qaz_mult_low_dout <= {32{1'b1}};
// NOTE Low
g_t_qaz_mult_high_dout <= {32{1'b0}};
gwerthernal_style_u_dout <= {32{1'b0}};
gwerthernal_style_l_dout <= {32{1'b0}};
end else begin
// clear
g_n_div_rebeq_dout <= g_n_div_rebeq_dout & ~g_noop_clr;
if((g_wrb == 1'b 0)) begin
// because we now...
for (i=0; i <= 1; i = i + 1) begin
if((i == 0)) begin
g_dout_w0x0f_v = g_dout_w0x0f;
end
else if((i == 1)) begin
if((n9_bit_write == 1'b 1)) begin
// set
g_dout_w0x0f_v = {g_dout_w0x0f[4:1],1'b 1};
end
else begin
disable; //VHD2VL: add block name here
end
//vnavigatoroff
end
else begin
// not possible but added for code coverage's sake
end
//vnavigatoron
case(g_dout_w0x0f_v)
g_t_klim_w0x0f : begin
g_t_klim_dout <= din[i * 32 + 31:i * 32];
end
g_t_u_w0x0f : begin
// output klim
for (j=0; j <= 31; j = j + 1) begin
if(((g_t_klim_dout[j] == 1'b 0 && n9_bit_write == 1'b 0) || (din[j] == 1'b 0 && n9_bit_write == 1'b 1))) begin
g_t_u_dout[j] <= din[32 * i + j];
end
end
end
g_t_l_w0x0f : begin
g_t_l_dout <= din[i * 32 + 31:i * 32];
end
g_t_hhh_l_w0x0f : begin
g_t_hhh_l_dout <= din[i * 32 + 31:i * 32];
end
g_t_jkl_sink_l_w0x0f : begin
g_t_jkl_sink_l_dout <= din[i * 32 + 31:i * 32];
end
g_secondary_t_l_w0x0f : begin
g_secondary_t_l_dout <= din[i * 32 + 31:i * 32];
end
g_style_c_l_w0x0f : begin
g_style_c_l_dout[3:0] <= din[3 + i * 32:i * 32];
end
g_e_z_w0x0f : begin
g_e_z_dout <= din[i * 32 + 31:i * 32];
end
g_n_both_qbars_l_w0x0f : begin
g_n_both_qbars_l_dout <= din[i * 32 + 31:i * 32];
end
g_style_vfr_w0x0f : begin
// read-only register
end
g_style_klim_w0x0f : begin
g_style_klim_dout <= din[i * 32 + 31:i * 32];
end
g_unklimed_style_vfr_w0x0f : begin
// read-only register
end
g_style_t_y_w0x0f : begin
g_style_t_y_dout <= din[i * 32 + 31:i * 32];
end
g_n_l_w0x0f : begin
g_n_l_dout <= din[i * 32 + 31:i * 32];
end
g_n_vfr_w0x0f : begin
// writes
end
g_e_n_r_w0x0f : begin
g_e_n_r_dout <= din[i * 32 + 31:i * 32];
end
g_n_r_bne_w0x0f : begin
g_n_r_bne_dout <= din[i * 32];
end
g_n_div_rebeq_w0x0f : begin
g_n_div_rebeq_dout <= din[i * 32 + 31:i * 32] | g_n_div_rebeq_dout;
// a '1' writes
end
g_alu_l_w0x0f : begin
g_alu_l_dout <= din[i * 32 + 31:i * 32];
end
g_t_qaz_mult_low_w0x0f : begin
g_t_qaz_mult_low_dout <= din[i * 32 + 31:i * 32];
end
g_t_qaz_mult_high_w0x0f : begin
g_t_qaz_mult_high_dout <= din[i * 32 + 31:i * 32];
end
gwerthernal_style_u_w0x0f : begin
gwerthernal_style_u_dout <= din[i * 32 + 31:i * 32];
end
gwerthernal_style_l_w0x0f : begin
gwerthernal_style_l_dout <= din[i * 32 + 31:i * 32];
//vnavigatoroff
end
default : begin
//vnavigatoron
end
endcase
end
end
end
end
// sample
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
q_g_zaq_in <= {32{1'b0}};
q2_g_zaq_in <= {32{1'b0}};
q3_g_zaq_in <= {32{1'b0}};
end else begin
q_g_zaq_in <= g_zaq_in;
q2_g_zaq_in <= q_g_zaq_in;
q3_g_zaq_in <= g_zaq_in_y;
end
end
// vfr register
assign g_unklimed_style_vfr_dout = q2_g_zaq_in;
// switch
assign g_zaq_in_y = g_style_t_y_dout ^ q2_g_zaq_in;
// qaz
assign g_style_vfr_dout = {g_zaq_in_y[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y[3:0])))};
// in scan mode
assign g_zaq_in_y_no_dout = scanb == 1'b 1 ? (g_style_t_y_dout ^ g_zaq_in) : g_style_t_y_dout;
//vnavigatoron
assign g_sys_in_i = ({g_zaq_in_y_no_dout[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y_no_dout[3:0])))});
assign g_sys_in_ii = ((g_sys_in_i & ~gwerthernal_style_l_dout)) | ((gwerthernal_style_u_dout & gwerthernal_style_l_dout));
assign g_sys_in = g_sys_in_ii;
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
q_g_zaq_in_cd <= {4{1'b0}};
q_g_unzq <= {4{1'b1}};
end else begin
// sample
if((debct_ping == 1'b 1)) begin
// taken
for (i=0; i <= 3; i = i + 1) begin
if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin
q_g_unzq[i] <= 1'b 1;
end
else begin
if((q_g_unzq[i] == 1'b 0)) begin
q_g_zaq_in_cd[i] <= g_zaq_in_y[i];
end
else begin
q_g_unzq[i] <= 1'b 0;
end
end
end
end
else begin
for (i=0; i <= 3; i = i + 1) begin
if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin
q_g_unzq[i] <= 1'b 1;
end
end
end
end
end
// generate lqqs
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
q_g_style_vfr_dout <= {32{1'b0}};
end else begin
if((scanb == 1'b 1)) begin
q_g_style_vfr_dout <= g_style_vfr_dout;
//vnavigatoroff
end
else begin
// in scan
q_g_style_vfr_dout <= g_style_vfr_dout | ({g_zaq_out_i[31:17],1'b 0,g_zaq_out_i[15:1],1'b 0}) | g_zaq_ctl_i | g_sys_in_ii;
end
//vnavigatoron
end
end
// generate
assign g_n_active = (((((q_g_style_vfr_dout & ~g_style_vfr_dout)) | (( ~q_g_style_vfr_dout & g_style_vfr_dout & g_n_both_qbars_l_dout))))) & g_n_l_dout;
// check for lqq active and set lqq vfr register
// also clear
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
g_n_vfr_dout <= {32{1'b0}};
gwerth <= {32{1'b0}};
end else begin
for (i=0; i <= 31; i = i + 1) begin
// lqq
// vfr matches
if((g_n_active[i] == 1'b 1)) begin
gwerth[i] <= 1'b 1;
if((g_e_z_dout[i] == 1'b 1)) begin
// lqq
g_n_vfr_dout[i] <= 1'b 1;
end
else begin
g_n_vfr_dout[i] <= q_g_style_vfr_dout[i];
end
end
else begin
// clear
if((g_e_z_dout[i] == 1'b 0)) begin
g_n_vfr_dout[i] <= q_g_style_vfr_dout[i];
// default always assign
// in both
if((g_n_both_qbars_l_dout[i] == 1'b 1 || g_style_vfr_dout[i] == 1'b 1)) begin
gwerth[i] <= 1'b 0;
end
end
else begin
// write
if((g_wrb == 1'b 0 && g_dout_w0x0f == g_n_vfr_w0x0f && din[i] == 1'b 1)) begin
gwerth[i] <= 1'b 0;
g_n_vfr_dout[i] <= 1'b 0;
end
end
end
end
end
end
//--
// Create the Lqq
always @(g_n_r_bne_dout or g_e_n_r_dout) begin : P1
reg [31:0] imod8, idiv8;
for (i=0; i <= 31; i = i + 1) begin
imod8 = i % 8;
idiv8 = i / 8;
if((g_n_r_bne_dout == 1'b 0)) begin
// non-unique
g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
end
else begin
// unique
if((imod8 == 0)) begin
g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
end
else begin
g_vector[8 * i + 7:8 * i] <= (((g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8])) + ((imod8)));
end
end
end
end
//--
// Qaz
assign g_noop = g_n_div_rebeq_dout;
always @(swe_ed or swe_lv or g_e_z_dout) begin
for (i=0; i <= 31; i = i + 1) begin
if((g_e_z_dout[i] == 1'b 1)) begin
swe_qaz1[i] <= swe_ed;
end
else begin
swe_qaz1[i] <= swe_lv;
end
end
end
endmodule |
module
gfx_top top(
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_inta_o (wb_inta_o),
// Wishbone master signals (interfaces with video memory)
.wbm_write_cyc_o (wbm_write_cyc_o),
.wbm_write_stb_o (wbm_write_stb_o),
.wbm_write_cti_o (wbm_write_cti_o),
.wbm_write_bte_o (wbm_write_bte_o),
.wbm_write_we_o (wbm_write_we_o),
.wbm_write_adr_o (wbm_write_adr_o),
.wbm_write_sel_o (wbm_write_sel_o),
.wbm_write_ack_i (wbm_write_ack_i),
.wbm_write_err_i (wbm_write_err_i),
.wbm_write_dat_o (wbm_write_dat_o),
// Wishbone master signals (interfaces with video memory)
.wbm_read_cyc_o (wbm_read_cyc_o),
.wbm_read_stb_o (wbm_read_stb_o),
.wbm_read_cti_o (wbm_read_cti_o),
.wbm_read_bte_o (wbm_read_bte_o),
.wbm_read_we_o (wbm_read_we_o),
.wbm_read_adr_o (wbm_read_adr_o),
.wbm_read_sel_o (wbm_read_sel_o),
.wbm_read_ack_i (wbm_read_ack_i),
.wbm_read_err_i (wbm_read_err_i),
.wbm_read_dat_i (wbm_read_dat_i),
// Wishbone slave signals (interfaces with main bus/CPU)
.wbs_cyc_i (wbs_cyc_i),
.wbs_stb_i (wbs_stb_i),
.wbs_cti_i (wbs_cti_i),
.wbs_bte_i (wbs_bte_i),
.wbs_we_i (wbs_we_i),
.wbs_adr_i (wbs_adr_i),
.wbs_sel_i (wbs_sel_i),
.wbs_ack_o (wbs_ack_o),
.wbs_err_o (wbs_err_o),
.wbs_dat_i (wbs_dat_i),
.wbs_dat_o (wbs_dat_o)
);
defparam top.point_width = point_width;
defparam top.subpixel_width = subpixel_width;
defparam top.fifo_depth = fifo_depth;
endmodule |
module pdp1_memory(i_clk, i_rst,
mm_we, mm_adr, mm_din, mm_dout);
input i_clk;
input i_rst;
input mm_we;
input [0:11] mm_adr;
output [0:17] mm_din;
input [0:17] mm_dout;
reg [0:18] m_memory [0:4095];
integer i;
assign mm_din = (~mm_we) ? m_memory[mm_adr] : 18'h00000;
always @(posedge i_clk) begin
if(i_rst) begin
for(i = 0; i < 4095; i = i + 1)
m_memory[i] = 0;
$readmemh("test.hex", m_memory); ///XXX
end
else begin
if(mm_we) begin
m_memory[mm_adr] <= mm_dout;
//$display("%m @%o <= %o", mm_adr, mm_dout);
end
end
end
endmodule |
module minimig_mist_top (
// clock inputs
input wire [ 2-1:0] CLOCK_32, // 32 MHz
input wire [ 2-1:0] CLOCK_27, // 27 MHz
input wire [ 2-1:0] CLOCK_50, // 50 MHz
// LED outputs
output wire LED, // LED Yellow
// UART
output wire UART_TX, // UART Transmitter
input wire UART_RX, // UART Receiver
// VGA
output wire VGA_HS, // VGA H_SYNC
output wire VGA_VS, // VGA V_SYNC
output wire [ 6-1:0] VGA_R, // VGA Red[5:0]
output wire [ 6-1:0] VGA_G, // VGA Green[5:0]
output wire [ 6-1:0] VGA_B, // VGA Blue[5:0]
// SDRAM
inout wire [ 16-1:0] SDRAM_DQ, // SDRAM Data bus 16 Bits
output wire [ 13-1:0] SDRAM_A, // SDRAM Address bus 13 Bits
output wire SDRAM_DQML, // SDRAM Low-byte Data Mask
output wire SDRAM_DQMH, // SDRAM High-byte Data Mask
output wire SDRAM_nWE, // SDRAM Write Enable
output wire SDRAM_nCAS, // SDRAM Column Address Strobe
output wire SDRAM_nRAS, // SDRAM Row Address Strobe
output wire SDRAM_nCS, // SDRAM Chip Select
output wire [ 2-1:0] SDRAM_BA, // SDRAM Bank Address
output wire SDRAM_CLK, // SDRAM Clock
output wire SDRAM_CKE, // SDRAM Clock Enable
// MINIMIG specific
output wire AUDIO_L, // sigma-delta DAC output left
output wire AUDIO_R, // sigma-delta DAC output right
// SPI
inout wire SPI_DO, // inout
input wire SPI_DI,
input wire SPI_SCK,
input wire SPI_SS2, // fpga
input wire SPI_SS3, // OSD
input wire SPI_SS4, // "sniff" mode
input wire CONF_DATA0 // SPI_SS for user_io
);
////////////////////////////////////////
// internal signals //
////////////////////////////////////////
// clock
wire pll_in_clk;
wire clk_114;
wire clk_28;
wire clk_sdram;
wire pll_locked;
wire clk_7;
wire clk7_en;
wire clk7n_en;
wire c1;
wire c3;
wire cck;
wire [ 10-1:0] eclk;
// reset
wire pll_rst;
wire sdctl_rst;
wire rst_50;
wire rst_minimig;
// ctrl
wire rom_status;
wire ram_status;
wire reg_status;
// tg68
wire tg68_rst;
wire [ 16-1:0] tg68_dat_in;
wire [ 16-1:0] tg68_dat_out;
wire [ 32-1:0] tg68_adr;
wire [ 3-1:0] tg68_IPL;
wire tg68_dtack;
wire tg68_as;
wire tg68_uds;
wire tg68_lds;
wire tg68_rw;
wire tg68_ena7RD;
wire tg68_ena7WR;
wire tg68_enaWR;
wire [ 16-1:0] tg68_cout;
wire tg68_cpuena;
wire [ 4-1:0] cpu_config;
wire [ 6-1:0] memcfg;
wire turbochipram;
wire turbokick;
wire cache_inhibit;
wire [ 32-1:0] tg68_cad;
wire [ 6-1:0] tg68_cpustate;
wire tg68_nrst_out;
wire tg68_cdma;
wire tg68_clds;
wire tg68_cuds;
wire [ 4-1:0] tg68_CACR_out;
wire [ 32-1:0] tg68_VBR_out;
wire tg68_ovr;
// minimig
wire led;
wire [ 16-1:0] ram_data; // sram data bus
wire [ 16-1:0] ramdata_in; // sram data bus in
wire [ 48-1:0] chip48; // big chip read
wire [ 22-1:1] ram_address; // sram address bus
wire _ram_bhe; // sram upper byte select
wire _ram_ble; // sram lower byte select
wire _ram_we; // sram write enable
wire _ram_oe; // sram output enable
wire _15khz; // scandoubler disable
wire joy_emu_en; // joystick emulation enable
wire sdo; // SPI data output
wire [ 15-1:0] ldata; // left DAC data
wire [ 15-1:0] rdata; // right DAC data
wire audio_left;
wire audio_right;
wire vs;
wire hs;
wire [ 8-1:0] red;
wire [ 8-1:0] green;
wire [ 8-1:0] blue;
reg vs_reg;
reg hs_reg;
reg [ 6-1:0] red_reg;
reg [ 6-1:0] green_reg;
reg [ 6-1:0] blue_reg;
// sdram
wire reset_out;
wire [ 4-1:0] sdram_cs;
wire [ 2-1:0] sdram_dqm;
wire [ 2-1:0] sdram_ba;
// mist
wire user_io_sdo;
wire minimig_sdo;
wire [ 8-1:0] JOYA;
wire [ 8-1:0] JOYB;
reg [ 8-1:0] JOYA_0;
reg [ 8-1:0] JOYB_0;
reg [ 8-1:0] JOYA_1;
reg [ 8-1:0] JOYB_1;
wire [ 8-1:0] joya;
wire [ 8-1:0] joyb;
wire [ 8-1:0] kbd_mouse_data;
wire kbd_mouse_strobe;
wire kms_level;
wire [ 2-1:0] kbd_mouse_type;
wire [ 3-1:0] MOUSE_BUTTONS;
reg [ 3-1:0] MOUSE_BUTTONS_0;
reg [ 3-1:0] MOUSE_BUTTONS_1;
wire [ 3-1:0] mouse_buttons;
wire [ 4-1:0] CORE_CONFIG;
reg [ 4-1:0] CORE_CONFIG_0;
reg [ 4-1:0] CORE_CONFIG_1;
wire [ 4-1:0] core_config;
////////////////////////////////////////
// toplevel assignments //
////////////////////////////////////////
// SDRAM
assign SDRAM_CKE = 1'b1;
assign SDRAM_CLK = clk_sdram;
assign SDRAM_nCS = sdram_cs[0];
assign SDRAM_DQML = sdram_dqm[0];
assign SDRAM_DQMH = sdram_dqm[1];
assign SDRAM_BA = sdram_ba;
// clock
assign pll_in_clk = CLOCK_27[0];
// reset
assign pll_rst = 1'b0;
assign sdctl_rst = pll_locked;
// mist
always @ (posedge clk_28) begin
CORE_CONFIG_0 <= #1 CORE_CONFIG;
CORE_CONFIG_1 <= #1 CORE_CONFIG_0;
JOYA_0 <= #1 JOYA;
JOYB_0 <= #1 JOYB;
JOYA_1 <= #1 JOYA_0;
JOYB_1 <= #1 JOYB_0;
MOUSE_BUTTONS_0 <= #1 MOUSE_BUTTONS;
MOUSE_BUTTONS_1 <= #1 MOUSE_BUTTONS_0;
end
assign core_config = CORE_CONFIG_1;
assign joya = JOYA_1;
assign joyb = JOYB_1;
assign mouse_buttons = MOUSE_BUTTONS_1;
// minimig
assign _15khz = ~core_config[0];
assign joy_emu_en = 1'b1;
assign LED = ~led;
// VGA data
always @ (posedge clk_28) begin
vs_reg <= #1 vs;
hs_reg <= #1 hs;
red_reg <= #1 red[7:2];
green_reg <= #1 green[7:2];
blue_reg <= #1 blue[7:2];
end
assign VGA_VS = vs_reg;
assign VGA_HS = hs_reg;
assign VGA_R[5:0] = red_reg[5:0];
assign VGA_G[5:0] = green_reg[5:0];
assign VGA_B[5:0] = blue_reg[5:0];
//// amiga clocks ////
amiga_clk amiga_clk (
.rst (pll_rst ), // async reset input
.clk_in (pll_in_clk ), // input clock ( 27.000000MHz)
.clk_114 (clk_114 ), // output clock c0 (114.750000MHz)
.clk_sdram (clk_sdram ), // output clock c2 (114.750000MHz, -146.25 deg)
.clk_28 (clk_28 ), // output clock c1 ( 28.687500MHz)
.clk_7 (clk_7 ), // output clock 7 ( 7.171875MHz)
.clk7_en (clk7_en ), // output clock 7 enable (on 28MHz clock domain)
.clk7n_en (clk7n_en ), // 7MHz negedge output clock enable (on 28MHz clock domain)
.c1 (c1 ), // clk28m clock domain signal synchronous with clk signal
.c3 (c3 ), // clk28m clock domain signal synchronous with clk signal delayed by 90 degrees
.cck (cck ), // colour clock output (3.54 MHz)
.eclk (eclk ), // 0.709379 MHz clock enable output (clk domain pulse)
.locked (pll_locked ) // pll locked output
);
//// TG68K main CPU ////
`ifdef MINIMIG_MIST_NEWCPU
TG68K_SplitClock tg68k (
.clk (clk_114 ),
.clk28 (clk_28 ),
.reset (tg68_rst ),
.IPL (tg68_IPL ),
.dtack (tg68_dtack ),
// .vpa (1'b1 ),
// .ein (1'b1 ),
.addr (tg68_adr ),
.data_read (tg68_dat_in ),
.data_write (tg68_dat_out ),
.as (tg68_as ),
.uds (tg68_uds ),
.lds (tg68_lds ),
.rw (tg68_rw ),
.e ( ),
.vma ( ),
.wrd ( ),
.ena7RDreg (tg68_ena7RD ),
.ena7WRreg (tg68_ena7WR ),
.enaWRreg (tg68_enaWR ),
.fromram (tg68_cout ),
.toram (tg68_cin ),
.ramready (tg68_cpuena ),
.cache_valid(cache_valid),
.cacheable(tg68_cacheable),
.cpu (cpu_config[1:0] ),
.turbochipram (memcfg[5]&memcfg[4]&turbochipram/*1'b0*//*turbochipram*/ ),
.fastramcfg ({memcfg[5]&memcfg[4],memcfg[5:4]}),
.ramaddr (tg68_cad ),
.cpustate (tg68_cpustate ),
.nResetOut (tg68_nrst_out ),
.skipFetch ( ),
.ramlds (tg68_clds ),
.ramuds (tg68_cuds ),
.VBR_out (tg68_VBR_out )
);
`else
TG68K tg68k (
.clk (clk_114 ),
.reset (tg68_rst ),
.clkena_in (1'b1 ),
.IPL (tg68_IPL ),
.dtack (tg68_dtack ),
.vpa (1'b1 ),
.ein (1'b1 ),
.addr (tg68_adr ),
.data_read (tg68_dat_in ),
.data_write (tg68_dat_out ),
.as (tg68_as ),
.uds (tg68_uds ),
.lds (tg68_lds ),
.rw (tg68_rw ),
.e ( ),
.vma ( ),
.wrd ( ),
.ena7RDreg (tg68_ena7RD ),
.ena7WRreg (tg68_ena7WR ),
.enaWRreg (tg68_enaWR ),
.fromram (tg68_cout ),
.ramready (tg68_cpuena ),
.cpu (cpu_config[1:0] ),
.turbochipram (turbochipram ),
.turbokick (turbokick ),
.cache_inhibit(cache_inhibit ),
.fastramcfg ({&memcfg[5:4],memcfg[5:4]}),
.eth_en (1'b1), // TODO
.sel_eth (),
.frometh (16'd0),
.ethready (1'b0),
.ovr (tg68_ovr ),
.ramaddr (tg68_cad ),
.cpustate (tg68_cpustate ),
.nResetOut (tg68_nrst_out ),
.skipFetch ( ),
.cpuDMA (tg68_cdma ),
.ramlds (tg68_clds ),
.ramuds (tg68_cuds ),
.CACR_out (tg68_CACR_out ),
.VBR_out (tg68_VBR_out )
);
`endif
/*
//// TG68 main CPU ////
TG68 tg68 (
.clk (clk_114 ),
.reset (tg68_rst ),
.clkena_in (1'b1 ),
.data_in (tg68_dat_in ),
.data_out (tg68_dat_out ),
.IPL (tg68_IPL ),
.dtack (tg68_dtack ),
.addr (tg68_adr ),
.as (tg68_as ),
.uds (tg68_uds ),
.lds (tg68_lds ),
.rw (tg68_rw ),
.drive_data ( ),
.enaRDreg (tg68_ena7RD ),
.enaWRreg (tg68_ena7WR )
);
*/
//// sdram ////
/*
sdram_ctrl sdram (
// sys
.sysclk (clk_114 ),
.c_7m (clk_7 ),
.reset_in (sdctl_rst ),
.cache_rst (tg68_rst ),
.reset_out (reset_out ),
.cache_ena (cpu_config[2] ),
// sdram
.sdaddr (SDRAM_A[12:0] ),
.sd_cs (sdram_cs ),
.ba (sdram_ba ),
.sd_we (SDRAM_nWE ),
.sd_ras (SDRAM_nRAS ),
.sd_cas (SDRAM_nCAS ),
.dqm (sdram_dqm ),
.sdata (SDRAM_DQ ),
// host
.host_cs (1'b0 ),
.host_adr (22'hxxxxxx ),
.host_we (1'b0 ),
.host_bs (2'bxx ),
.host_wdat (16'hxxxx ),
.host_rdat ( ),
.host_ack ( ),
// chip
.chipAddr ({2'b00, ram_address[21:1]}),
.chipL (_ram_ble ),
.chipU (_ram_bhe ),
.chipRW (_ram_we ),
.chip_dma (_ram_oe ),
.chipWR (ram_data ),
.chipRD (ramdata_in ),
.chip48 (chip48 ),
// cpu
.cpuAddr (tg68_cad[24:1] ),
.cpustate (tg68_cpustate ),
.cpuL (tg68_clds ),
.cpuU (tg68_cuds ),
.cpu_dma (tg68_cdma ),
.cpuWR (tg68_dat_out ),
.cpuRD (tg68_cout ),
.enaWRreg (tg68_enaWR ),
.ena7RDreg (tg68_ena7RD ),
.ena7WRreg (tg68_ena7WR ),
.cpuena (tg68_cpuena )
);
*/
//sdram sdram (
sdram_ctrl sdram (
.cache_rst (tg68_rst ),
.cache_inhibit(cache_inhibit ),
.cpu_cache_ctrl (tg68_CACR_out ),
.sdata (SDRAM_DQ ),
.sdaddr (SDRAM_A[12:0] ),
.dqm (sdram_dqm ),
.sd_cs (sdram_cs ),
.ba (sdram_ba ),
.sd_we (SDRAM_nWE ),
.sd_ras (SDRAM_nRAS ),
.sd_cas (SDRAM_nCAS ),
.sysclk (clk_114 ),
.reset_in (sdctl_rst ),
.hostWR (16'h0 ),
.hostAddr (24'h0 ),
.hostState ({1'b0, 2'b01} ),
.hostL (1'b1 ),
.hostU (1'b1 ),
.cpuWR (tg68_dat_out ),
.cpuAddr (tg68_cad[24:1] ),
.cpuU (tg68_cuds ),
.cpuL (tg68_clds ),
.cpustate (tg68_cpustate ),
.cpu_dma (tg68_cdma ),
.chipWR (ram_data ),
.chipAddr ({2'b00, ram_address[21:1]}),
.chipU (_ram_bhe ),
.chipL (_ram_ble ),
.chipRW (_ram_we ),
.chip_dma (_ram_oe ),
.c_7m (clk_7 ),
.hostRD ( ),
.hostena ( ),
.cpuRD (tg68_cout ),
.cpuena (tg68_cpuena ),
.chipRD (ramdata_in ),
.chip48 (chip48 ),
.reset_out (reset_out ),
.enaRDreg ( ),
.enaWRreg (tg68_enaWR ),
.ena7RDreg (tg68_ena7RD ),
.ena7WRreg (tg68_ena7WR )
);
// multiplex spi_do, drive it from user_io if that's selected, drive
// it from minimig if it's selected and leave it open else (also
// to be able to monitor sd card data directly)
assign SPI_DO = (CONF_DATA0 == 1'b0)?user_io_sdo:
(((SPI_SS2 == 1'b0)|| (SPI_SS3 == 1'b0))?minimig_sdo:1'bZ);
//// user io has an extra spi channel outside minimig core ////
user_io user_io(
.SPI_CLK(SPI_SCK),
.SPI_SS_IO(CONF_DATA0),
.SPI_MISO(user_io_sdo),
.SPI_MOSI(SPI_DI),
.JOY0(JOYA),
.JOY1(JOYB),
.MOUSE_BUTTONS(MOUSE_BUTTONS),
.KBD_MOUSE_DATA(kbd_mouse_data),
.KBD_MOUSE_TYPE(kbd_mouse_type),
.KBD_MOUSE_STROBE(kbd_mouse_strobe),
.KMS_LEVEL(kms_level),
.CORE_TYPE(8'ha5), // minimig core id (a1 - old minimig id, a5 - new aga minimig id)
.CONF(CORE_CONFIG)
);
//// minimig top ////
minimig minimig (
//m68k pins
.cpu_address (tg68_adr[23:1] ), // M68K address bus
.cpu_data (tg68_dat_in ), // M68K data bus
.cpudata_in (tg68_dat_out ), // M68K data in
._cpu_ipl (tg68_IPL ), // M68K interrupt request
._cpu_as (tg68_as ), // M68K address strobe
._cpu_uds (tg68_uds ), // M68K upper data strobe
._cpu_lds (tg68_lds ), // M68K lower data strobe
.cpu_r_w (tg68_rw ), // M68K read / write
._cpu_dtack (tg68_dtack ), // M68K data acknowledge
._cpu_reset (tg68_rst ), // M68K reset
._cpu_reset_in(tg68_nrst_out ), // M68K reset out
.cpu_vbr (tg68_VBR_out ), // M68K VBR
.ovr (tg68_ovr ), // NMI override address decoding
//sram pins
.ram_data (ram_data ), // SRAM data bus
.ramdata_in (ramdata_in ), // SRAM data bus in
.ram_address (ram_address[21:1]), // SRAM address bus
._ram_bhe (_ram_bhe ), // SRAM upper byte select
._ram_ble (_ram_ble ), // SRAM lower byte select
._ram_we (_ram_we ), // SRAM write enable
._ram_oe (_ram_oe ), // SRAM output enable
.chip48 (chip48 ), // big chipram read
//system pins
.rst_ext (rst_minimig ), // reset from ctrl block
.rst_out ( ), // minimig reset status
.clk (clk_28 ), // output clock c1 ( 28.687500MHz)
.clk7_en (clk7_en ), // 7MHz clock enable
.clk7n_en (clk7n_en ), // 7MHz negedge clock enable
.c1 (c1 ), // clk28m clock domain signal synchronous with clk signal
.c3 (c3 ), // clk28m clock domain signal synchronous with clk signal delayed by 90 degrees
.cck (cck ), // colour clock output (3.54 MHz)
.eclk (eclk ), // 0.709379 MHz clock enable output (clk domain pulse)
//rs232 pins
.rxd (UART_RX ), // RS232 receive
.txd (UART_TX ), // RS232 send
.cts (1'b0 ), // RS232 clear to send
.rts ( ), // RS232 request to send
//I/O
._joy1 (~joya ), // joystick 1 [fire4,fire3,fire2,fire,up,down,left,right] (default mouse port)
._joy2 (~joyb ), // joystick 2 [fire4,fire3,fire2,fire,up,down,left,right] (default joystick port)
.mouse_btn1 (1'b1 ), // mouse button 1
.mouse_btn2 (1'b1 ), // mouse button 2
.mouse_btn (mouse_buttons ), // mouse buttons
.kbd_mouse_data (kbd_mouse_data ), // mouse direction data, keycodes
.kbd_mouse_type (kbd_mouse_type ), // type of data
.kbd_mouse_strobe (kbd_mouse_strobe), // kbd/mouse data strobe
.kms_level (kms_level ),
._15khz (_15khz ), // scandoubler disable
.pwrled (led ), // power led
.msdat ( ), // PS2 mouse data
.msclk ( ), // PS2 mouse clk
.kbddat ( ), // PS2 keyboard data
.kbdclk ( ), // PS2 keyboard clk
//host controller interface (SPI)
._scs ( {SPI_SS4,SPI_SS3,SPI_SS2} ), // SPI chip select
.direct_sdi (SPI_DO ), // SD Card direct in SPI_SDO
.sdi (SPI_DI ), // SPI data input
.sdo (minimig_sdo ), // SPI data output
.sck (SPI_SCK ), // SPI clock
//video
._hsync (hs ), // horizontal sync
._vsync (vs ), // vertical sync
.red (red ), // red
.green (green ), // green
.blue (blue ), // blue
//audio
.left (AUDIO_L ), // audio bitstream left
.right (AUDIO_R ), // audio bitstream right
.ldata ( ), // left DAC data
.rdata ( ), // right DAC data
//user i/o
.cpu_config (cpu_config ), // CPU config
.memcfg (memcfg ), // memory config
.turbochipram (turbochipram ), // turbo chipRAM
.turbokick (turbokick ), // turbo kickstart
.init_b ( ), // vertical sync for MCU (sync OSD update)
.fifo_full ( ),
// fifo / track display
.trackdisp ( ), // floppy track number
.secdisp ( ), // sector
.floppy_fwr ( ), // floppy fifo writing
.floppy_frd ( ), // floppy fifo reading
.hd_fwr ( ), // hd fifo writing
.hd_frd ( ) // hd fifo ading
);
endmodule |
module sky130_fd_sc_hs__sdfsbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_s_no_pg u_df_p_s_no_pg0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule |
module outputs
wire [31 : 0] wciS0_SData, wsiM0_MData;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [3 : 0] wsiM0_MByteEn;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget;
wire [71 : 0] wci_wslv_wciReq$wget;
wire [60 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget;
wire [33 : 0] wci_wslv_respF_x_wire$wget;
wire [31 : 0] ddc_sRegPwdata_w$wget,
wci_wci_Es_mAddr_w$wget,
wci_wci_Es_mData_w$wget,
wsi_Es_mData_w$wget;
wire [15 : 0] ddc_sDataR_w$wget;
wire [11 : 0] ddc_sRegPaddr_w$wget, wsi_Es_mBurstLength_w$wget;
wire [7 : 0] wsi_Es_mReqInfo_w$wget;
wire [3 : 0] wci_wci_Es_mByteEn_w$wget, wsi_Es_mByteEn_w$wget;
wire [2 : 0] wci_wci_Es_mCmd_w$wget,
wci_wslv_wEdge$wget,
wsi_Es_mCmd_w$wget;
wire ddc_dataResetn_w$wget,
ddc_dataResetn_w$whas,
ddc_mDataReady_w$wget,
ddc_mDataReady_w$whas,
ddc_sDataR_w$whas,
ddc_sDataValid_w$wget,
ddc_sDataValid_w$whas,
ddc_sRegPaddr_w$whas,
ddc_sRegPenable_w$wget,
ddc_sRegPenable_w$whas,
ddc_sRegPsel_w$wget,
ddc_sRegPsel_w$whas,
ddc_sRegPwdata_w$whas,
ddc_sRegPwrite_w$wget,
ddc_sRegPwrite_w$whas,
wci_wci_Es_mAddrSpace_w$wget,
wci_wci_Es_mAddrSpace_w$whas,
wci_wci_Es_mAddr_w$whas,
wci_wci_Es_mByteEn_w$whas,
wci_wci_Es_mCmd_w$whas,
wci_wci_Es_mData_w$whas,
wci_wslv_ctlAckReg_1$wget,
wci_wslv_ctlAckReg_1$whas,
wci_wslv_reqF_r_clr$whas,
wci_wslv_reqF_r_deq$whas,
wci_wslv_reqF_r_enq$whas,
wci_wslv_respF_dequeueing$whas,
wci_wslv_respF_enqueueing$whas,
wci_wslv_respF_x_wire$whas,
wci_wslv_sFlagReg_1$wget,
wci_wslv_sFlagReg_1$whas,
wci_wslv_sThreadBusy_pw$whas,
wci_wslv_wEdge$whas,
wci_wslv_wciReq$whas,
wci_wslv_wci_cfrd_pw$whas,
wci_wslv_wci_cfwr_pw$whas,
wci_wslv_wci_ctrl_pw$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_doResetClr$whas,
wsiS_reqFifo_doResetDeq$whas,
wsiS_reqFifo_doResetEnq$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_sThreadBusy_dw$wget,
wsiS_sThreadBusy_dw$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas;
// register ambaErrCnt
reg [31 : 0] ambaErrCnt;
wire [31 : 0] ambaErrCnt$D_IN;
wire ambaErrCnt$EN;
// register ambaRdReqCnt
reg [31 : 0] ambaRdReqCnt;
wire [31 : 0] ambaRdReqCnt$D_IN;
wire ambaRdReqCnt$EN;
// register ambaRespCnt
reg [31 : 0] ambaRespCnt;
wire [31 : 0] ambaRespCnt$D_IN;
wire ambaRespCnt$EN;
// register ambaWrReqCnt
reg [31 : 0] ambaWrReqCnt;
wire [31 : 0] ambaWrReqCnt$D_IN;
wire ambaWrReqCnt$EN;
// register ddcCtrl
reg [31 : 0] ddcCtrl;
wire [31 : 0] ddcCtrl$D_IN;
wire ddcCtrl$EN;
// register ddc_reqSetup
reg ddc_reqSetup;
wire ddc_reqSetup$D_IN, ddc_reqSetup$EN;
// register ddc_started
reg ddc_started;
wire ddc_started$D_IN, ddc_started$EN;
// register outMesgCnt
reg [31 : 0] outMesgCnt;
wire [31 : 0] outMesgCnt$D_IN;
wire outMesgCnt$EN;
// register splitReadInFlight
reg splitReadInFlight;
wire splitReadInFlight$D_IN, splitReadInFlight$EN;
// register splitWriteInFlight
reg splitWriteInFlight;
wire splitWriteInFlight$D_IN, splitWriteInFlight$EN;
// register takeEven
reg takeEven;
wire takeEven$D_IN, takeEven$EN;
// register unloadCnt
reg [15 : 0] unloadCnt;
wire [15 : 0] unloadCnt$D_IN;
wire unloadCnt$EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge$D_IN;
wire wci_wslv_cEdge$EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState$D_IN;
wire wci_wslv_cState$EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg$D_IN, wci_wslv_ctlAckReg$EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive$D_IN, wci_wslv_ctlOpActive$EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge$D_IN, wci_wslv_illegalEdge$EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset$D_IN, wci_wslv_isReset_isInReset$EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState$D_IN;
wire wci_wslv_nState$EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg$D_IN;
wire wci_wslv_reqF_countReg$EN;
// register wci_wslv_respF_c_r
reg [1 : 0] wci_wslv_respF_c_r;
wire [1 : 0] wci_wslv_respF_c_r$D_IN;
wire wci_wslv_respF_c_r$EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0$D_IN;
wire wci_wslv_respF_q_0$EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1$D_IN;
wire wci_wslv_respF_q_1$EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg$D_IN, wci_wslv_sFlagReg$EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d$D_IN, wci_wslv_sThreadBusy_d$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [60 : 0] wsiM_reqFifo_q_0;
reg [60 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [60 : 0] wsiM_reqFifo_q_1;
reg [60 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength$D_IN;
wire wsiS_mesgWordLength$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount$D_IN;
wire wsiS_wordCount$EN;
// ports of submodule ddc_apbReqF
wire [45 : 0] ddc_apbReqF$D_IN, ddc_apbReqF$D_OUT;
wire ddc_apbReqF$CLR,
ddc_apbReqF$DEQ,
ddc_apbReqF$EMPTY_N,
ddc_apbReqF$ENQ,
ddc_apbReqF$FULL_N;
// ports of submodule ddc_apbRespF
wire [32 : 0] ddc_apbRespF$D_IN, ddc_apbRespF$D_OUT;
wire ddc_apbRespF$CLR,
ddc_apbRespF$DEQ,
ddc_apbRespF$EMPTY_N,
ddc_apbRespF$ENQ,
ddc_apbRespF$FULL_N;
// ports of submodule ddc_ddc
wire [31 : 0] ddc_ddc$sreg_prdata, ddc_ddc$sreg_pwdata;
wire [15 : 0] ddc_ddc$mdata_i, ddc_ddc$mdata_q, ddc_ddc$sdata_r;
wire [11 : 0] ddc_ddc$sreg_paddr;
wire ddc_ddc$data_resetn,
ddc_ddc$int_ducddc,
ddc_ddc$int_errpacket,
ddc_ddc$int_lostoutput,
ddc_ddc$int_missinput,
ddc_ddc$mdata_ready,
ddc_ddc$mdata_valid,
ddc_ddc$sdata_ready,
ddc_ddc$sdata_valid,
ddc_ddc$sreg_penable,
ddc_ddc$sreg_pready,
ddc_ddc$sreg_psel,
ddc_ddc$sreg_pslverr,
ddc_ddc$sreg_pwrite;
// ports of submodule ddc_xkF
wire [31 : 0] ddc_xkF$D_IN, ddc_xkF$D_OUT;
wire ddc_xkF$CLR, ddc_xkF$DEQ, ddc_xkF$EMPTY_N, ddc_xkF$ENQ, ddc_xkF$FULL_N;
// ports of submodule ddc_xnF
wire [15 : 0] ddc_xnF$D_IN, ddc_xnF$D_OUT;
wire ddc_xnF$CLR, ddc_xnF$DEQ, ddc_xnF$EMPTY_N, ddc_xnF$ENQ, ddc_xnF$FULL_N;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF$D_IN, wci_wslv_reqF$D_OUT;
wire wci_wslv_reqF$CLR,
wci_wslv_reqF$DEQ,
wci_wslv_reqF$EMPTY_N,
wci_wslv_reqF$ENQ;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// ports of submodule xnF
wire [31 : 0] xnF$D_IN, xnF$D_OUT;
wire xnF$CLR, xnF$DEQ, xnF$EMPTY_N, xnF$ENQ, xnF$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_advance_wci_response,
WILL_FIRE_RL_ddcEnable_doEgress,
WILL_FIRE_RL_ddcEnable_doIngress,
WILL_FIRE_RL_ddcEnable_output_feedDDC,
WILL_FIRE_RL_ddcPass_bypass,
WILL_FIRE_RL_ddc_sreg_request,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1;
wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
MUX_wsiM_reqFifo_q_1$write_1__VAL_2,
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1;
wire [45 : 0] MUX_ddc_apbReqF$enq_1__VAL_1, MUX_ddc_apbReqF$enq_1__VAL_2;
wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2,
MUX_wci_wslv_respF_q_1$write_1__VAL_2,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_3;
wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_ddc_apbReqF$enq_1__SEL_1,
MUX_ddc_apbReqF$enq_1__SEL_2,
MUX_splitReadInFlight$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_2,
MUX_wci_wslv_illegalEdge$write_1__VAL_2,
MUX_wci_wslv_respF_q_0$write_1__SEL_1,
MUX_wci_wslv_respF_q_1$write_1__SEL_1,
MUX_wci_wslv_respF_x_wire$wset_1__SEL_1,
MUX_wsiM_reqFifo_q_0$write_1__SEL_1,
MUX_wsiM_reqFifo_q_1$write_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h14747, v__h3699, v__h3874, v__h4018;
reg [31 : 0] IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509;
wire [31 : 0] ddcStatus__h13569,
g_data__h14465,
rdat___1__h14502,
rdat___1__h14581,
rdat___1__h14595,
rdat___1__h14603,
rdat___1__h14609,
rdat___1__h14623,
rdat___1__h14631,
rdat___1__h14637,
rdat___1__h14643,
rdat___1__h14649,
rdat___1__h14655,
rdat___1__h14661,
x_data__h13440;
wire [15 : 0] x__h14506;
wire [7 : 0] x__h14479;
wire wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d447;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[43:12] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[11:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// submodule ddc_apbReqF
FIFO2 #(.width(32'd46), .guarded(32'd1)) ddc_apbReqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(ddc_apbReqF$D_IN),
.ENQ(ddc_apbReqF$ENQ),
.DEQ(ddc_apbReqF$DEQ),
.CLR(ddc_apbReqF$CLR),
.D_OUT(ddc_apbReqF$D_OUT),
.FULL_N(ddc_apbReqF$FULL_N),
.EMPTY_N(ddc_apbReqF$EMPTY_N));
// submodule ddc_apbRespF
FIFO2 #(.width(32'd33), .guarded(32'd1)) ddc_apbRespF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(ddc_apbRespF$D_IN),
.ENQ(ddc_apbRespF$ENQ),
.DEQ(ddc_apbRespF$DEQ),
.CLR(ddc_apbRespF$CLR),
.D_OUT(ddc_apbRespF$D_OUT),
.FULL_N(ddc_apbRespF$FULL_N),
.EMPTY_N(ddc_apbRespF$EMPTY_N));
// submodule ddc_ddc
duc_ddc_compiler_v1_0 ddc_ddc(.clk(wciS0_Clk),
.sreg_presetn(wciS0_MReset_n),
.data_resetn(ddc_ddc$data_resetn),
.mdata_ready(ddc_ddc$mdata_ready),
.sdata_r(ddc_ddc$sdata_r),
.sdata_valid(ddc_ddc$sdata_valid),
.sreg_paddr(ddc_ddc$sreg_paddr),
.sreg_penable(ddc_ddc$sreg_penable),
.sreg_psel(ddc_ddc$sreg_psel),
.sreg_pwdata(ddc_ddc$sreg_pwdata),
.sreg_pwrite(ddc_ddc$sreg_pwrite),
.mdata_valid(ddc_ddc$mdata_valid),
.mdata_last(),
.sdata_ready(ddc_ddc$sdata_ready),
.mdata_clean(),
.mdata_i(ddc_ddc$mdata_i),
.mdata_q(ddc_ddc$mdata_q),
.sreg_pready(ddc_ddc$sreg_pready),
.sreg_prdata(ddc_ddc$sreg_prdata),
.sreg_pslverr(ddc_ddc$sreg_pslverr),
.int_missinput(ddc_ddc$int_missinput),
.int_errpacket(ddc_ddc$int_errpacket),
.int_lostoutput(ddc_ddc$int_lostoutput),
.int_ducddc(ddc_ddc$int_ducddc));
// submodule ddc_xkF
FIFO2 #(.width(32'd32), .guarded(32'd1)) ddc_xkF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(ddc_xkF$D_IN),
.ENQ(ddc_xkF$ENQ),
.DEQ(ddc_xkF$DEQ),
.CLR(ddc_xkF$CLR),
.D_OUT(ddc_xkF$D_OUT),
.FULL_N(ddc_xkF$FULL_N),
.EMPTY_N(ddc_xkF$EMPTY_N));
// submodule ddc_xnF
FIFO2 #(.width(32'd16), .guarded(32'd1)) ddc_xnF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(ddc_xnF$D_IN),
.ENQ(ddc_xnF$ENQ),
.DEQ(ddc_xnF$DEQ),
.CLR(ddc_xnF$CLR),
.D_OUT(ddc_xnF$D_OUT),
.FULL_N(ddc_xnF$FULL_N),
.EMPTY_N(ddc_xnF$EMPTY_N));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF$D_IN),
.ENQ(wci_wslv_reqF$ENQ),
.DEQ(wci_wslv_reqF$DEQ),
.CLR(wci_wslv_reqF$CLR),
.D_OUT(wci_wslv_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF$EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// submodule xnF
FIFO2 #(.width(32'd32), .guarded(32'd1)) xnF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(xnF$D_IN),
.ENQ(xnF$ENQ),
.DEQ(xnF$DEQ),
.CLR(xnF$CLR),
.D_OUT(xnF$D_OUT),
.FULL_N(xnF$FULL_N),
.EMPTY_N(xnF$EMPTY_N));
// rule RL_ddcEnable_doIngress
assign WILL_FIRE_RL_ddcEnable_doIngress =
ddc_xnF$FULL_N && xnF$EMPTY_N && wci_wslv_cState == 3'd2 &&
ddcCtrl[1:0] == 2'd1 &&
!wsiM_statusR[6] ;
// rule RL_advance_wci_response
assign WILL_FIRE_RL_advance_wci_response =
wci_wslv_respF_c_r != 2'd2 && ddc_apbRespF$EMPTY_N &&
!wci_wslv_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_cfrd &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_ddcPass_bypass
assign WILL_FIRE_RL_ddcPass_bypass =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_wslv_cState == 3'd2 &&
ddcCtrl[1:0] == 2'd0 ;
// rule RL_ddcEnable_output_feedDDC
assign WILL_FIRE_RL_ddcEnable_output_feedDDC =
wsiS_reqFifo$EMPTY_N && xnF$FULL_N && wci_wslv_cState == 3'd2 &&
ddcCtrl[1:0] == 2'd1 ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d447 &&
wci_wslv_wci_cfrd_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_ddcEnable_doEgress
assign WILL_FIRE_RL_ddcEnable_doEgress =
wsiM_reqFifo_c_r != 2'd2 && ddc_xkF$EMPTY_N &&
wci_wslv_cState == 3'd2 &&
ddcCtrl[1:0] == 2'd1 ;
// rule RL_wci_cfwr
assign CAN_FIRE_RL_wci_cfwr =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N &&
(!wci_wslv_reqF$D_OUT[44] || ddc_apbReqF$FULL_N) &&
wci_wslv_wci_cfwr_pw$whas ;
assign WILL_FIRE_RL_wci_cfwr =
CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
((wci_wslv_respF_c_r == 2'd0) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_enqueueing$whas &&
!(wci_wslv_respF_c_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
((wci_wslv_respF_c_r == 2'd1) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_c_r != 2'd0 &&
wci_wslv_respF_enqueueing$whas ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
// rule RL_ddc_sreg_request
assign WILL_FIRE_RL_ddc_sreg_request =
ddc_apbReqF$EMPTY_N &&
(!ddc_reqSetup || !ddc_ddc$sreg_pready ||
ddc_apbReqF$D_OUT[45] ||
ddc_apbRespF$FULL_N) ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[60:58] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq || wsiS_reqFifo_r_deq$whas ;
// inputs to muxes for submodule ports
assign MUX_ddc_apbReqF$enq_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[44] ;
assign MUX_ddc_apbReqF$enq_1__SEL_2 =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[44] ;
assign MUX_splitReadInFlight$write_1__SEL_1 =
WILL_FIRE_RL_advance_wci_response && splitReadInFlight ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ;
assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[44] ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_ddc_apbReqF$enq_1__VAL_1 = { 2'd2, wci_wslv_reqF$D_OUT[43:0] } ;
assign MUX_ddc_apbReqF$enq_1__VAL_2 = { 2'd0, wci_wslv_reqF$D_OUT[43:0] } ;
assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ;
always@(MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 or
WILL_FIRE_RL_advance_wci_response or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_x_wire$wset_1__SEL_1:
MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_advance_wci_response:
MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_3;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0$write_1__VAL_1 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
(wci_wslv_respF_c_r == 2'd1) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_1 :
wci_wslv_respF_q_1 ;
assign MUX_wci_wslv_respF_q_1$write_1__VAL_2 =
(wci_wslv_respF_c_r == 2'd2) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_1 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h14465 } ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 =
ddc_apbRespF$D_OUT[32] ?
34'h3C0DE4202 :
{ 2'd1,
splitWriteInFlight ?
32'hC0DE4201 :
ddc_apbRespF$D_OUT[31:0] } ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
WILL_FIRE_RL_ddcEnable_doEgress ?
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 :
wsiS_reqFifo$D_OUT ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
(wsiM_reqFifo_c_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 =
(wsiM_reqFifo_c_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
61'h00000AAAAAAAAA00 ;
assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 =
{ 3'd1,
unloadCnt == 16'd2047,
13'd6144,
x_data__h13440,
12'd3840 } ;
// inlined wires
assign wci_wslv_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq$whas = 1'd1 ;
assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_1 ;
assign wci_wslv_respF_x_wire$whas =
WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[44] ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_advance_wci_response ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge$wget = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_wEdge$whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1$wget = 1'b0 ;
assign wci_wslv_sFlagReg_1$whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1$wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wci_wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_wci_Es_mData_w$wget = wciS0_MData ;
assign wci_wci_Es_mData_w$whas = 1'd1 ;
assign wsiS_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw$whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ;
assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
assign ddc_sDataValid_w$wget = 1'd1 ;
assign ddc_sDataValid_w$whas = ddc_xnF$EMPTY_N && ddc_ddc$sdata_ready ;
assign ddc_sDataR_w$wget = ddc_xnF$D_OUT ;
assign ddc_sDataR_w$whas = ddc_sDataValid_w$whas ;
assign ddc_mDataReady_w$wget = 1'd1 ;
assign ddc_mDataReady_w$whas = ddc_xkF$FULL_N && ddc_ddc$mdata_valid ;
assign ddc_dataResetn_w$wget = 1'd1 ;
assign ddc_dataResetn_w$whas = ddc_started ;
assign ddc_sRegPaddr_w$wget = ddc_apbReqF$D_OUT[43:32] ;
assign ddc_sRegPaddr_w$whas = WILL_FIRE_RL_ddc_sreg_request ;
assign ddc_sRegPsel_w$wget = 1'd1 ;
assign ddc_sRegPsel_w$whas = WILL_FIRE_RL_ddc_sreg_request ;
assign ddc_sRegPenable_w$wget = ddc_reqSetup ;
assign ddc_sRegPenable_w$whas = WILL_FIRE_RL_ddc_sreg_request ;
assign ddc_sRegPwrite_w$wget = ddc_apbReqF$D_OUT[45] ;
assign ddc_sRegPwrite_w$whas = WILL_FIRE_RL_ddc_sreg_request ;
assign ddc_sRegPwdata_w$wget = ddc_apbReqF$D_OUT[31:0] ;
assign ddc_sRegPwdata_w$whas = WILL_FIRE_RL_ddc_sreg_request ;
assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS0_MData ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wci_wslv_reqF_r_enq$whas = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr$whas = 1'b0 ;
assign wci_wslv_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[44] ||
WILL_FIRE_RL_advance_wci_response ||
WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw$whas =
wci_wslv_reqF$EMPTY_N && !wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq$whas =
WILL_FIRE_RL_ddcEnable_output_feedDDC ||
WILL_FIRE_RL_ddcPass_bypass ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing$whas =
WILL_FIRE_RL_ddcEnable_doEgress || WILL_FIRE_RL_ddcPass_bypass ;
assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register ambaErrCnt
assign ambaErrCnt$D_IN = ambaErrCnt + 32'd1 ;
assign ambaErrCnt$EN =
WILL_FIRE_RL_advance_wci_response && ddc_apbRespF$D_OUT[32] ;
// register ambaRdReqCnt
assign ambaRdReqCnt$D_IN = ambaRdReqCnt + 32'd1 ;
assign ambaRdReqCnt$EN = MUX_ddc_apbReqF$enq_1__SEL_2 ;
// register ambaRespCnt
assign ambaRespCnt$D_IN = ambaRespCnt + 32'd1 ;
assign ambaRespCnt$EN =
WILL_FIRE_RL_advance_wci_response && !ddc_apbRespF$D_OUT[32] ;
// register ambaWrReqCnt
assign ambaWrReqCnt$D_IN = ambaWrReqCnt + 32'd1 ;
assign ambaWrReqCnt$EN = MUX_ddc_apbReqF$enq_1__SEL_1 ;
// register ddcCtrl
assign ddcCtrl$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign ddcCtrl$EN =
WILL_FIRE_RL_wci_cfwr &&
wci_wslv_reqF$D_OUT[63:32] == 32'h00000004 ;
// register ddc_reqSetup
assign ddc_reqSetup$D_IN = !ddc_reqSetup ;
assign ddc_reqSetup$EN =
WILL_FIRE_RL_ddc_sreg_request &&
(ddc_ddc$sreg_pready || !ddc_reqSetup) ;
// register ddc_started
assign ddc_started$D_IN = 1'd1 ;
assign ddc_started$EN = !ddc_started ;
// register outMesgCnt
assign outMesgCnt$D_IN = outMesgCnt + 32'd1 ;
assign outMesgCnt$EN =
WILL_FIRE_RL_ddcEnable_doEgress && unloadCnt == 16'd2047 ;
// register splitReadInFlight
assign splitReadInFlight$D_IN = !MUX_splitReadInFlight$write_1__SEL_1 ;
assign splitReadInFlight$EN =
WILL_FIRE_RL_advance_wci_response && splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[44] ;
// register splitWriteInFlight
assign splitWriteInFlight$D_IN = 1'd0 ;
assign splitWriteInFlight$EN =
WILL_FIRE_RL_advance_wci_response && splitWriteInFlight ;
// register takeEven
assign takeEven$D_IN = !takeEven ;
assign takeEven$EN = WILL_FIRE_RL_ddcEnable_doIngress ;
// register unloadCnt
assign unloadCnt$D_IN =
(unloadCnt == 16'd2047) ? 16'd0 : unloadCnt + 16'd1 ;
assign unloadCnt$EN = WILL_FIRE_RL_ddcEnable_doEgress ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge$D_IN = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_cEdge$EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState$D_IN = wci_wslv_nState ;
assign wci_wslv_cState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg$D_IN = wci_wslv_ctlAckReg_1$whas ;
assign wci_wslv_ctlAckReg$EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
!MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge$write_1__VAL_2 ;
assign wci_wslv_illegalEdge$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ||
MUX_wci_wslv_illegalEdge$write_1__SEL_2 ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset$EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF$D_OUT)
begin
case (wci_wslv_reqF$D_OUT[36:34])
3'd0: wci_wslv_nState$D_IN = 3'd1;
3'd1: wci_wslv_nState$D_IN = 3'd2;
3'd2: wci_wslv_nState$D_IN = 3'd3;
default: wci_wslv_nState$D_IN = 3'd0;
endcase
end
assign wci_wslv_nState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg$D_IN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg$EN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq$whas ;
// register wci_wslv_respF_c_r
assign wci_wslv_respF_c_r$D_IN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ?
MUX_wci_wslv_respF_c_r$write_1__VAL_1 :
MUX_wci_wslv_respF_c_r$write_1__VAL_2 ;
assign wci_wslv_respF_c_r$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or
MUX_wci_wslv_respF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0$write_1__SEL_1:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0$D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or
MUX_wci_wslv_respF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_1$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1$write_1__SEL_1:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg$D_IN = 1'b0 ;
assign wci_wslv_sFlagReg$EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[57]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset$D_IN = 1'd0 ;
assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0$write_1__SEL_1:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1$write_1__SEL_1:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq$wget[57]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'b0 ;
assign wsiS_errorSticky$EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset$D_IN = 1'd0 ;
assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[57] ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq != wsiS_reqFifo_r_deq$whas ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid$EN =
WILL_FIRE_RL_ddcEnable_output_feedDDC ||
WILL_FIRE_RL_ddcPass_bypass ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR$D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR$EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount$D_IN =
wsiS_wsiReq$wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule ddc_apbReqF
assign ddc_apbReqF$D_IN =
MUX_ddc_apbReqF$enq_1__SEL_1 ?
MUX_ddc_apbReqF$enq_1__VAL_1 :
MUX_ddc_apbReqF$enq_1__VAL_2 ;
assign ddc_apbReqF$ENQ =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[44] ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[44] ;
assign ddc_apbReqF$DEQ =
WILL_FIRE_RL_ddc_sreg_request && ddc_reqSetup &&
ddc_ddc$sreg_pready ;
assign ddc_apbReqF$CLR = 1'b0 ;
// submodule ddc_apbRespF
assign ddc_apbRespF$D_IN = { ddc_ddc$sreg_pslverr, ddc_ddc$sreg_prdata } ;
assign ddc_apbRespF$ENQ =
WILL_FIRE_RL_ddc_sreg_request && ddc_reqSetup &&
ddc_ddc$sreg_pready &&
!ddc_apbReqF$D_OUT[45] ;
assign ddc_apbRespF$DEQ = WILL_FIRE_RL_advance_wci_response ;
assign ddc_apbRespF$CLR = 1'b0 ;
// submodule ddc_ddc
assign ddc_ddc$data_resetn = ddc_started ;
assign ddc_ddc$mdata_ready = ddc_mDataReady_w$whas ;
assign ddc_ddc$sdata_r = ddc_sDataValid_w$whas ? ddc_xnF$D_OUT : 16'd0 ;
assign ddc_ddc$sdata_valid = ddc_sDataValid_w$whas ;
assign ddc_ddc$sreg_paddr =
WILL_FIRE_RL_ddc_sreg_request ?
ddc_apbReqF$D_OUT[43:32] :
12'd0 ;
assign ddc_ddc$sreg_penable =
WILL_FIRE_RL_ddc_sreg_request && ddc_reqSetup ;
assign ddc_ddc$sreg_psel = WILL_FIRE_RL_ddc_sreg_request ;
assign ddc_ddc$sreg_pwdata =
WILL_FIRE_RL_ddc_sreg_request ? ddc_apbReqF$D_OUT[31:0] : 32'd0 ;
assign ddc_ddc$sreg_pwrite =
WILL_FIRE_RL_ddc_sreg_request && ddc_apbReqF$D_OUT[45] ;
// submodule ddc_xkF
assign ddc_xkF$D_IN = { ddc_ddc$mdata_i, ddc_ddc$mdata_q } ;
assign ddc_xkF$ENQ = ddc_mDataReady_w$whas ;
assign ddc_xkF$DEQ = WILL_FIRE_RL_ddcEnable_doEgress ;
assign ddc_xkF$CLR = 1'b0 ;
// submodule ddc_xnF
assign ddc_xnF$D_IN = takeEven ? xnF$D_OUT[15:0] : xnF$D_OUT[31:16] ;
assign ddc_xnF$ENQ = WILL_FIRE_RL_ddcEnable_doIngress ;
assign ddc_xnF$DEQ = ddc_sDataValid_w$whas ;
assign ddc_xnF$CLR = 1'b0 ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ;
assign wci_wslv_reqF$ENQ = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF$DEQ = wci_wslv_reqF_r_deq$whas ;
assign wci_wslv_reqF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo$DEQ = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo$CLR = 1'b0 ;
// submodule xnF
assign xnF$D_IN = wsiS_reqFifo$D_OUT[43:12] ;
assign xnF$ENQ = WILL_FIRE_RL_ddcEnable_output_feedDDC ;
assign xnF$DEQ = WILL_FIRE_RL_ddcEnable_doIngress && !takeEven ;
assign xnF$CLR = 1'b0 ;
// remaining internal signals
assign ddcStatus__h13569 = { 24'd0, x__h14479 } ;
assign g_data__h14465 =
wci_wslv_reqF$D_OUT[44] ?
32'd0 :
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 ;
assign rdat___1__h14502 = hasDebugLogic ? { 16'd0, x__h14506 } : 32'd0 ;
assign rdat___1__h14581 =
hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ;
assign rdat___1__h14595 =
hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ;
assign rdat___1__h14603 =
hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ;
assign rdat___1__h14609 =
hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ;
assign rdat___1__h14623 =
hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ;
assign rdat___1__h14631 =
hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ;
assign rdat___1__h14637 = hasDebugLogic ? ambaWrReqCnt : 32'd0 ;
assign rdat___1__h14643 = hasDebugLogic ? ambaRdReqCnt : 32'd0 ;
assign rdat___1__h14649 = hasDebugLogic ? ambaRespCnt : 32'd0 ;
assign rdat___1__h14655 = hasDebugLogic ? ambaErrCnt : 32'd0 ;
assign rdat___1__h14661 = hasDebugLogic ? outMesgCnt : 32'd0 ;
assign wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d447 =
wci_wslv_reqF$EMPTY_N &&
(wci_wslv_reqF$D_OUT[44] ?
ddc_apbReqF$FULL_N :
wci_wslv_respF_c_r != 2'd2) ;
assign x__h14479 =
{ ddc_ddc$int_missinput,
ddc_ddc$int_errpacket,
ddc_ddc$int_lostoutput,
ddc_ddc$int_ducddc,
3'b0,
hasDebugLogic } ;
assign x__h14506 = { wsiS_statusR, wsiM_statusR } ;
assign x_data__h13440 = { ddc_xkF$D_OUT[15:0], ddc_xkF$D_OUT[31:16] } ;
always@(wci_wslv_reqF$D_OUT or
ddcStatus__h13569 or
ddcCtrl or
rdat___1__h14502 or
rdat___1__h14581 or
rdat___1__h14595 or
rdat___1__h14603 or
rdat___1__h14609 or
rdat___1__h14623 or
rdat___1__h14631 or
rdat___1__h14637 or
rdat___1__h14643 or
rdat___1__h14649 or rdat___1__h14655 or rdat___1__h14661)
begin
case (wci_wslv_reqF$D_OUT[63:32])
32'h0:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
ddcStatus__h13569;
32'h00000004:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 = ddcCtrl;
32'h00000010:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14502;
32'h00000014:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14581;
32'h00000018:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14595;
32'h0000001C:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14603;
32'h00000020:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14609;
32'h00000024:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14623;
32'h00000028:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14631;
32'h0000002C:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14637;
32'h00000030:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14643;
32'h00000034:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14649;
32'h00000038:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14655;
32'h0000003C:
IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
rdat___1__h14661;
default: IF_wci_wslv_reqF_first__5_BITS_63_TO_32_42_EQ__ETC___d509 =
32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
ambaErrCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ambaRdReqCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ambaRespCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ambaWrReqCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ddcCtrl <= `BSV_ASSIGNMENT_DELAY ddcCtrlInit;
ddc_reqSetup <= `BSV_ASSIGNMENT_DELAY 1'd0;
ddc_started <= `BSV_ASSIGNMENT_DELAY 1'd0;
outMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
splitWriteInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
takeEven <= `BSV_ASSIGNMENT_DELAY 1'd1;
unloadCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (ambaErrCnt$EN)
ambaErrCnt <= `BSV_ASSIGNMENT_DELAY ambaErrCnt$D_IN;
if (ambaRdReqCnt$EN)
ambaRdReqCnt <= `BSV_ASSIGNMENT_DELAY ambaRdReqCnt$D_IN;
if (ambaRespCnt$EN)
ambaRespCnt <= `BSV_ASSIGNMENT_DELAY ambaRespCnt$D_IN;
if (ambaWrReqCnt$EN)
ambaWrReqCnt <= `BSV_ASSIGNMENT_DELAY ambaWrReqCnt$D_IN;
if (ddcCtrl$EN) ddcCtrl <= `BSV_ASSIGNMENT_DELAY ddcCtrl$D_IN;
if (ddc_reqSetup$EN)
ddc_reqSetup <= `BSV_ASSIGNMENT_DELAY ddc_reqSetup$D_IN;
if (ddc_started$EN)
ddc_started <= `BSV_ASSIGNMENT_DELAY ddc_started$D_IN;
if (outMesgCnt$EN)
outMesgCnt <= `BSV_ASSIGNMENT_DELAY outMesgCnt$D_IN;
if (splitReadInFlight$EN)
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight$D_IN;
if (splitWriteInFlight$EN)
splitWriteInFlight <= `BSV_ASSIGNMENT_DELAY splitWriteInFlight$D_IN;
if (takeEven$EN) takeEven <= `BSV_ASSIGNMENT_DELAY takeEven$D_IN;
if (unloadCnt$EN) unloadCnt <= `BSV_ASSIGNMENT_DELAY unloadCnt$D_IN;
if (wci_wslv_cEdge$EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge$D_IN;
if (wci_wslv_cState$EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState$D_IN;
if (wci_wslv_ctlAckReg$EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg$D_IN;
if (wci_wslv_ctlOpActive$EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive$D_IN;
if (wci_wslv_illegalEdge$EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge$D_IN;
if (wci_wslv_nState$EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState$D_IN;
if (wci_wslv_reqF_countReg$EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg$D_IN;
if (wci_wslv_respF_c_r$EN)
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN;
if (wci_wslv_respF_q_0$EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN;
if (wci_wslv_respF_q_1$EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1$D_IN;
if (wci_wslv_sFlagReg$EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg$D_IN;
if (wci_wslv_sThreadBusy_d$EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_reqFifo_levelsValid$EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
if (wsiS_wordCount$EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN;
end
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
if (wsiS_mesgWordLength$EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset$EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset$D_IN;
if (wsiM_isReset_isInReset$EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset$D_IN;
if (wsiS_isReset_isInReset$EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
ambaErrCnt = 32'hAAAAAAAA;
ambaRdReqCnt = 32'hAAAAAAAA;
ambaRespCnt = 32'hAAAAAAAA;
ambaWrReqCnt = 32'hAAAAAAAA;
ddcCtrl = 32'hAAAAAAAA;
ddc_reqSetup = 1'h0;
ddc_started = 1'h0;
outMesgCnt = 32'hAAAAAAAA;
splitReadInFlight = 1'h0;
splitWriteInFlight = 1'h0;
takeEven = 1'h0;
unloadCnt = 16'hAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_c_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3699 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3699,
wci_wslv_reqF$D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h14747 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting DDC ddcCtrl:%0x", v__h14747, ddcCtrl);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/DDCWorker.bsv\", line 97, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h4018 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4018,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3874 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3874,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
end
// synopsys translate_on
endmodule |
module System(
clk_i,
rst_i,
irq_i,
nmi_i,
rdy_i,
mem_u_stl_o,
mem_u_if_dat_o,
mem_u_ea_dat_o,
mem_u_rd_dat_o,
mem_u_inst_o,
core_u_we_o,
core_u_if_cnt_o,
core_u_w_cnt_o,
core_u_w_dat_o,
core_u_w_adr_o,
core_u_inst_adr_o,
core_u_if_adr_o,
core_u_ea_adr_o,
core_u_rd_adr_o
`ifdef DEBUG
,core_u_a_o,
core_u_x_o,
core_u_y_o,
mem_u_dbg_o,
core_u_pf_u_dbg_o,
core_u_dec_u_dbg_o,
core_u_ea_u_dbg_o,
core_u_rd_u_dbg_o,
core_u_exe_u_dbg_o,
core_u_wb_u_dbg_o
`endif
);
//Input signals :
input wire clk_i;
input wire rst_i;
input wire irq_i;
input wire nmi_i;
input wire rdy_i;
//Output signals :
output wire mem_u_stl_o;
output wire [23:0] mem_u_if_dat_o;
output wire [15:0] mem_u_ea_dat_o;
output wire [7:0] mem_u_rd_dat_o;
output wire [7:0] mem_u_inst_o;
output wire core_u_we_o;
output wire [1:0] core_u_if_cnt_o;
output wire [1:0] core_u_w_cnt_o;
output wire [23:0] core_u_w_dat_o;
output wire [15:0] core_u_w_adr_o;
output wire [15:0] core_u_inst_adr_o;
output wire [15:0] core_u_if_adr_o;
output wire [15:0] core_u_ea_adr_o;
output wire [15:0] core_u_rd_adr_o;
`ifdef DEBUG
output wire [7:0] core_u_a_o;
output wire [7:0] core_u_x_o;
output wire [7:0] core_u_y_o;
output wire [`MEM_DBG_WIDTH - 1:0] mem_u_dbg_o;
output wire [`PRF_DBG_WIDTH - 1:0] core_u_pf_u_dbg_o;
output wire [`DEC_DBG_WIDTH - 1:0] core_u_dec_u_dbg_o;
output wire [`EAD_DBG_WIDTH - 1:0] core_u_ea_u_dbg_o;
output wire [`RDA_DBG_WIDTH - 1:0] core_u_rd_u_dbg_o;
output wire [`EXE_DBG_WIDTH - 1:0] core_u_exe_u_dbg_o;
output wire [`WRB_DBG_WIDTH - 1:0] core_u_wb_u_dbg_o;
`endif
//Instantiations :
Memory mem_u
(
.clk_i (clk_i),
.we_i (core_u_we_o),
.if_cnt_i (core_u_if_cnt_o),
.w_cnt_i (core_u_w_cnt_o),
.w_dat_i (core_u_w_dat_o),
.w_adr_i (core_u_w_adr_o),
.inst_adr_i (core_u_inst_adr_o),
.if_adr_i (core_u_if_adr_o),
.ea_adr_i (core_u_ea_adr_o),
.rd_adr_i (core_u_rd_adr_o),
.stl_o (mem_u_stl_o),
.if_dat_o (mem_u_if_dat_o),
.ea_dat_o (mem_u_ea_dat_o),
.rd_dat_o (mem_u_rd_dat_o),
.inst_o (mem_u_inst_o)
`ifdef DEBUG
,.debug_o (mem_u_dbg_o)
`endif
);
Core core_u
(
.clk_i (clk_i),
.rst_i (rst_i),
.irq_i (irq_i),
.nmi_i (nmi_i),
.rdy_i (rdy_i),
.stl_i (mem_u_stl_o),
.if_dat_i (mem_u_if_dat_o),
.ea_dat_i (mem_u_ea_dat_o),
.rd_dat_i (mem_u_rd_dat_o),
.inst_i (mem_u_inst_o),
.we_o (core_u_we_o),
.if_cnt_o (core_u_if_cnt_o),
.w_cnt_o (core_u_w_cnt_o),
.w_dat_o (core_u_w_dat_o),
.w_adr_o (core_u_w_adr_o),
.inst_adr_o (core_u_inst_adr_o),
.if_adr_o (core_u_if_adr_o),
.ea_adr_o (core_u_ea_adr_o),
.rd_adr_o (core_u_rd_adr_o)
`ifdef DEBUG
,.a_o (core_u_a_o),
.x_o (core_u_x_o),
.y_o (core_u_y_o),
.pf_u_dbg_o (core_u_pf_u_dbg_o),
.dec_u_dbg_o (core_u_dec_u_dbg_o),
.ea_u_dbg_o (core_u_ea_u_dbg_o),
.rd_u_dbg_o (core_u_rd_u_dbg_o),
.exe_u_dbg_o (core_u_exe_u_dbg_o),
.wb_u_dbg_o (core_u_wb_u_dbg_o)
`endif
);
endmodule |
module sineTable_tb ();
///////////////////////////////////////////////////////////////////////////
// PARAMETER AND SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
wire signed [17:0] sine;
reg signed [17:0] expectedSine;
reg [11:0] angle;
reg [11:0] angleD1;
reg clk;
integer i;
///////////////////////////////////////////////////////////////////////////
// MAIN CODE
///////////////////////////////////////////////////////////////////////////
always #1 clk = ~clk;
initial begin
clk = 1'b0;
angle = 0;
angleD1 = 0;
// Let sine table start outputting valid data
@(posedge clk);
@(posedge clk);
// Run sine table over several frequencies
for (i=1; i<2**11; i=i<<1) begin // double frequency each time
@(posedge clk) angle = angle + i;
while (angle != 0) begin
@(posedge clk) angle = angle + i;
if ((sine - expectedSine > 1) || (sine - expectedSine < -1)) begin
$display("FAILED @ angle=%d", angleD1);
$finish(2);
end
end
end
$display("PASSED");
$finish(2);
end
always @(posedge clk) begin
angleD1 <= angle;
expectedSine <= $rtoi($floor($sin(($itor(angleD1)+0.5)*2*3.14159/2**12)*(2**17-1)+0.5));
end
sineTable #(
.ANGLE_WIDTH(12),
.OUT_WIDTH(18)
) uut (
.clk(clk), ///< System Clock
.angle(angle), ///< [ANGLE_WIDTH-1:0] Angle to take sine of
.sine(sine) ///< [OUT_WIDTH-1:0] Sine of angle
);
endmodule |
module sky130_fd_sc_hs__tapvpwrvgnd (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule |
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